diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml index 7888529ee40534..0b3755c7d9e37e 100644 --- a/.github/workflows/codecov.yaml +++ b/.github/workflows/codecov.yaml @@ -20,7 +20,7 @@ jobs: strategy: fail-fast: false matrix: - platform: ["mps2_an385", "native_sim", "qemu_x86", "unit_testing"] + platform: ["mps2/an385", "native_sim", "qemu_x86", "unit_testing"] steps: - name: Apply container owner mismatch workaround run: | diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml index 219fbfae60764f..5e6e2cff9a6fba 100644 --- a/.github/workflows/compliance.yml +++ b/.github/workflows/compliance.yml @@ -57,6 +57,8 @@ jobs: # debug ls -la git log --pretty=oneline | head -n 10 + # Increase rename limit to allow for large PRs + git config diff.renameLimit 10000 ./scripts/ci/check_compliance.py --annotate -e KconfigBasic \ -c origin/${BASE_REF}.. diff --git a/.gitignore b/.gitignore index 13c99731c52966..15636eaaeac0ea 100644 --- a/.gitignore +++ b/.gitignore @@ -68,14 +68,17 @@ tags # from check_compliance.py BinaryFiles.txt +BoardYml.txt Checkpatch.txt DevicetreeBindings.txt +GitDiffCheck.txt Gitlint.txt Identity.txt ImageSize.txt Kconfig.txt KconfigBasic.txt KconfigBasicNoModules.txt +KconfigHWMv2.txt KeepSorted.txt MaintainersFormat.txt ModulesMaintainers.txt diff --git a/CMakeLists.txt b/CMakeLists.txt index f1fb89660f9c7c..091bae3798094b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -118,7 +118,7 @@ zephyr_include_directories( include(${ZEPHYR_BASE}/cmake/linker_script/${ARCH}/linker.cmake OPTIONAL) -zephyr_include_directories(${SOC_DIR}/${ARCH}/${SOC_PATH}) +zephyr_include_directories(${SOC_FULL_DIR}) # Don't inherit compiler flags from the environment foreach(var AFLAGS CFLAGS CXXFLAGS CPPFLAGS LDFLAGS) diff --git a/CODEOWNERS b/CODEOWNERS index df8b4cb4d42218..bd6bbf17e86773 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -19,13 +19,7 @@ # entries that are not covered by the MAINTAINERS file. /soc/arm/aspeed/ @aspeeddylan -/soc/arm/atmel_sam/common/*_sam4l_*.c @nandojve -/soc/arm/atmel_sam/sam3x/ @ioannisg -/soc/arm/atmel_sam/sam4e/ @nandojve -/soc/arm/atmel_sam/sam4l/ @nandojve -/soc/arm/atmel_sam/sam4s/ @fallrisk -/soc/arm/atmel_sam/same70/ @nandojve -/soc/arm/atmel_sam/samv71/ @nandojve +/soc/atmel/ @nandojve /soc/arm/bcm*/ @sbranden /soc/arm/infineon_cat1/ @ifyall @npal-cy /soc/arm/infineon_xmc/ @parthitce @@ -101,11 +95,7 @@ /boards/arm/rpi_pico/ @yonsch /boards/arm/ronoth_lodev/ @NorthernDean /boards/arm/xmc45_relax_kit/ @parthitce -/boards/arm/sam4e_xpro/ @nandojve -/boards/arm/sam4l_ek/ @nandojve -/boards/arm/sam4s_xplained/ @fallrisk -/boards/arm/sam_e70_xplained/ @nandojve -/boards/arm/sam_v71_xult/ @nandojve +/boards/atmel/ @nandojve /boards/arm/scobc_module1/ @yashi /boards/arm/v2m_beetle/ @fvincenzo /boards/arm/olimexino_stm32/ @ydamigos @@ -411,13 +401,7 @@ /dts/arc/ @abrodkin @ruuddw @iriszzw @evgeniy-paltsev /dts/arm/acsip/ @NorthernDean /dts/arm/aspeed/ @aspeeddylan -/dts/arm/atmel/sam4e* @nandojve -/dts/arm/atmel/sam4l* @nandojve -/dts/arm/atmel/samr21.dtsi @benpicco -/dts/arm/atmel/sam*5*.dtsi @benpicco -/dts/arm/atmel/same70* @nandojve -/dts/arm/atmel/samv71* @nandojve -/dts/arm/atmel/ @galak +/dts/arm/atmel/ @galak @nandojve /dts/arm/broadcom/ @sbranden /dts/arm/cypress/ @ifyall @npal-cy /dts/arm/gd/ @nandojve @@ -428,7 +412,7 @@ /dts/arm64/nxp/ @JiafeiPan /dts/arm64/renesas/ @lorc @xakep-amatop /dts/arm/quicklogic/ @fkokosinski @kgugala -/dts/arm/seeed/ @str4t0m +/dts/arm/seeed_studio/ @str4t0m /dts/arm/st/ @erwango /dts/arm/st/h7/*stm32h735* @benediktibk /dts/arm/st/l4/*stm32l451* @benediktibk @@ -475,6 +459,7 @@ /dts/bindings/counter/snps,dw-timers.yaml @pbalsundar /dts/bindings/wifi/*esp-at.yaml @mniestroj /dts/bindings/*/*gd32* @nandojve +/dts/bindings/*/*sam* @nandojve /dts/bindings/*/*npcx* @MulinChao @ChiHuaL /dts/bindings/*/*psoc6* @ifyall @npal-cy /dts/bindings/*/*infineon*cat1* @ifyall @npal-cy diff --git a/Kconfig.zephyr b/Kconfig.zephyr index 5ad2fb2bf85c0b..eb4399c297f4e9 100644 --- a/Kconfig.zephyr +++ b/Kconfig.zephyr @@ -21,12 +21,11 @@ osource "$(KCONFIG_BINARY_DIR)/Kconfig.shield.defconfig" # This loads Zephyr base shield defconfigs source "boards/shields/*/Kconfig.defconfig" -source "$(BOARD_DIR)/Kconfig.defconfig" +osource "$(BOARD_DIR)/Kconfig.defconfig" + +# This loads Zephyr specific SoC root defconfigs +source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.defconfig" -# This loads custom SoC root defconfigs -osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc.defconfig" -# This loads Zephyr base SoC root defconfigs -osource "soc/$(ARCH)/*/Kconfig.defconfig" # This loads the toolchain defconfigs osource "$(TOOLCHAIN_KCONFIG_DIR)/Kconfig.defconfig" # This loads the testsuite defconfig @@ -644,7 +643,7 @@ config BUILD_OUTPUT_UF2_FAMILY_ID default "0x1c5f21b0" if SOC_SERIES_ESP32 default "0x621e937a" if SOC_NRF52833_QIAA default "0xada52840" if SOC_NRF52840_QIAA - default "0x4fb2d5bd" if SOC_SERIES_IMX_RT + default "0x4fb2d5bd" if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX default "0x2abc77ec" if SOC_SERIES_LPC55XXX default "0xe48bff56" if SOC_SERIES_RP2XXX default "0x68ed2b88" if SOC_SERIES_SAMD21 @@ -906,7 +905,7 @@ config BOOTLOADER_SRAM_SIZE_DEPRECATED config BOOTLOADER_ESP_IDF bool "ESP-IDF bootloader support" - depends on SOC_FAMILY_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT + depends on SOC_FAMILY_ESPRESSIF_ESP32 && !BOOTLOADER_MCUBOOT && !MCUBOOT default y help This option will trigger the compilation of the ESP-IDF bootloader diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml index d8f9047277d216..2d59af4630484c 100644 --- a/MAINTAINERS.yml +++ b/MAINTAINERS.yml @@ -166,9 +166,7 @@ ARM arch: - include/zephyr/arch/arm/ - tests/arch/arm/ - doc/hardware/arch/arm_cortex_m.rst - - boards/arm/qemu_cortex_m3/ - - boards/arm/qemu_cortex_m0/ - - soc/arm/* + - boards/qemu/cortex_m0/ labels: - "area: ARM" tests: @@ -186,9 +184,9 @@ ARM64 arch: - arch/arm64/ - include/zephyr/arch/arm64/ - tests/arch/arm64/ - - soc/arm64/ - - boards/arm64/ - dts/arm64/ + - boards/qemu/kvm_arm64/ + - boards/qemu/cortex_a53/ labels: - "area: ARM64" tests: @@ -198,8 +196,11 @@ ARM Platforms: status: odd fixes files: - boards/arm/mps*/ - - soc/arm/arm/ - boards/arm/v2m_*/ + - soc/arm/mps*/ + - soc/arm/musca/ + - soc/arm/beetle/ + - soc/arm/fvp_aemv8r/aarch32/ - dts/arm/armv*.dtsi labels: - "platform: ARM" @@ -207,7 +208,7 @@ ARM Platforms: ASPEED Platforms: status: odd fixes files: - - soc/arm/aspeed/ + - soc/aspeed/ - dts/arm/aspeed/ - drivers/*/*_ast10x0.c - drivers/*/Kconfig.aspeed @@ -230,10 +231,9 @@ ARM SiP SVC: MIPS arch: status: odd fixes files: - - soc/mips/ - arch/mips/ - include/zephyr/arch/mips/ - - boards/mips/ + - boards/qemu/malta/ labels: - "area: MIPS" tests: @@ -249,8 +249,8 @@ Ambiq Platforms: - aaronyegx - RichardSWheatley files: - - soc/arm/ambiq/ - - boards/arm/apollo*/ + - soc/ambiq/ + - boards/ambiq/apollo*/ - dts/arm/ambiq/ - dts/bindings/*/ambiq,* - drivers/*/*ambiq* @@ -268,8 +268,7 @@ BeagleBoard Platforms: - con-pax - vaishnavachath files: - - boards/arm/beagle*/ - - boards/riscv/beagle*/ + - boards/beagle/ labels: - "platform: BeagleBoard" @@ -524,7 +523,7 @@ Board/SoC configuration: - nordicjm - "57300" files: - - soc/Kconfig + - soc/Kconfig* - boards/Kconfig labels: - "area: Board/SoC configuration" @@ -2011,8 +2010,8 @@ Xen Platform: - include/zephyr/xen/ - drivers/xen/ - arch/arm64/core/xen/ - - soc/arm64/xenvm/ - - boards/arm64/xenvm/ + - soc/xen/ + - boards/xen/ labels: - "area: Xen Platform" @@ -2070,7 +2069,7 @@ Google Platforms: - fabiobaltieri - keith-zephyr files: - - boards/*/google_*/ + - boards/google/ - samples/boards/google_*/ Hash Utilities: @@ -2303,12 +2302,7 @@ Laird Connectivity platforms: collaborators: - greg-leach files: - - boards/arm/bl5340_dvk/ - - boards/arm/bl65*/ - - boards/arm/bt510/ - - boards/arm/bt610/ - - boards/arm/pinnacle_100_dvk/ - - boards/arm/mg100/ + - boards/lairdconnect/ labels: - "platform: Laird Connectivity" @@ -2513,10 +2507,10 @@ Native POSIX/Sim and POSIX arch: - aescolar files: - arch/posix/ - - boards/posix/common/ - - boards/posix/native_*/ - - boards/posix/doc/ - - boards/posix/*.rst + - boards/native/common/ + - boards/native/native_*/ + - boards/native/doc/ + - boards/native/*.rst - drivers/*/*posix* - drivers/*/*native* - drivers/*/*/*posix* @@ -2525,7 +2519,7 @@ Native POSIX/Sim and POSIX arch: - include/zephyr/arch/posix/ - scripts/native_simulator/ - scripts/valgrind.supp - - soc/posix/ + - soc/native/ - tests/boards/native_sim/ labels: - "area: native port" @@ -2769,11 +2763,11 @@ NIOS-2 arch: - arch/nios2/ - dts/nios2/intel/ - boards/common/nios2.board.cmake - - boards/nios2/ - - soc/nios2/ + - soc/altr/*nios2*/ - include/zephyr/arch/nios2/ - tests/boards/altera_max10/ - - boards/nios2/qemu_nios2/ + - boards/qemu/nios2/ + - boards/altr/max10/ - scripts/support/quartus-flash.py labels: - "area: NIOS2" @@ -2785,7 +2779,7 @@ nRF BSIM: maintainers: - aescolar files: - - boards/posix/nrf_bsim/ + - boards/native/nrf_bsim/ - tests/boards/nrf52_bsim/ - tests/bsim/ files-exclude: @@ -2846,7 +2840,7 @@ Power management: "Quicklogic Platform": status: odd fixes files: - - soc/arm/quicklogic_eos_s3/ + - soc/quicklogic/ - dts/arm/quicklogic/ labels: - "platform: Quicklogic" @@ -2865,10 +2859,14 @@ RISCV arch: - npitre files: - arch/riscv/ - - boards/riscv/ + - boards/qemu/riscv*/ + - boards/sifive/ + - boards/sparkfun/red_v_things_plus/ - dts/bindings/riscv/ - dts/riscv/ - include/zephyr/arch/riscv/ + - soc/common/riscv-privileged/ + - soc/sifive/ - soc/riscv/ - tests/arch/riscv/ - doc/hardware/arch/risc-v.rst @@ -3009,9 +3007,19 @@ SPARC arch: files: - arch/sparc/ - include/zephyr/arch/sparc/ - - soc/sparc/ - - boards/sparc/ - dts/sparc/ + - boards/qemu/leon3/ + labels: + - "area: SPARC" + +Gaisler Platforms: + status: odd fixes + collaborators: + - julius-barendt + files: + - dts/sparc/gaisler/ + - soc/gaisler/ + - boards/gaisler/ labels: - "area: SPARC" @@ -3039,7 +3047,7 @@ ADI Platforms: - galak - microbuilder files: - - boards/arm/adi_*/ + - boards/adi/ - drivers/*/max* - drivers/*/*max*/ - drivers/dac/dac_ltc* @@ -3058,8 +3066,8 @@ Broadcom Platforms: status: odd fixes files: - dts/arm/broadcom/ - - soc/arm/bcm_vk/ - - boards/arm/bcm95840*/ + - soc/brcm/ + - boards/brcm/ GD32 Platforms: status: maintained @@ -3070,14 +3078,12 @@ GD32 Platforms: - gmarull - soburi files: - - boards/arm/gd32*/ - - boards/riscv/gd32*/ - - boards/riscv/longan_nano/ + - boards/gd/ - drivers/*/*gd32* - dts/*/gd/ - dts/bindings/*/*gd32* - - soc/*/gd_gd32/ - scripts/west_commands/*/*gd32* + - soc/gd/gd32/ labels: - "platform: GD32" description: >- @@ -3093,8 +3099,8 @@ Synopsys Platforms: - evgeniy-paltsev - IRISZZW files: - - soc/arc/ - - boards/arc/ + - soc/synopsys/ + - boards/synopsys/ - samples/boards/arc_secure_services/ labels: - "platform: Synopsys" @@ -3112,8 +3118,8 @@ Nuvoton NPCX Platforms: - jackrosenthal - fabiobaltieri files: - - soc/arm/nuvoton_npcx/ - - boards/arm/npcx*/ + - soc/nuvoton/npcx/ + - boards/nuvoton/npcx*/ - dts/arm/nuvoton/ - dts/bindings/*/*npcx* - drivers/*/*_npcx*.c @@ -3127,10 +3133,9 @@ Nuvoton Numicro Numaker Platforms: collaborators: - ssekar15 files: - - soc/arm/nuvoton_numicro/ - - soc/arm/nuvoton_numaker/ - - boards/arm/nuvoton_pfm*/ - - boards/arm/numaker_*/ + - soc/nuvoton/numaker/ + - soc/nuvoton/numicro/ + - boards/nuvoton/numaker*/ - dts/arm/nuvoton/ - dts/bindings/*/*numicro* - dts/bindings/*/*numaker* @@ -3146,15 +3151,15 @@ Raspberry Pi Pico Platforms: collaborators: - soburi files: - - boards/arm/rpi_pico/ - - boards/arm/adafruit_kb2040/ - - boards/arm/sparkfun_pro_micro_rp2040/ + - boards/raspberrypi/ + - boards/adafruit/kb2040/ + - boards/sparkfun/pro_micro_rp2040/ - dts/arm/rpi_pico/ - dts/bindings/*/raspberrypi,pico* - drivers/*/*rpi_pico - drivers/*/*rpi_pico*/ - drivers/*/*rpi_pico*.c - - soc/arm/rpi_pico/ + - soc/raspberrypi/ labels: - "platform: Raspberry Pi Pico" @@ -3165,8 +3170,8 @@ SiLabs Platforms: collaborators: - tgorochowik files: - - soc/arm/silabs_*/ - - boards/arm/ef*/ + - soc/silabs/ + - boards/silabs/ - dts/arm/silabs/ - dts/bindings/*/silabs* - drivers/*/*_gecko* @@ -3181,9 +3186,13 @@ Intel Platforms (X86): - tbursztyka - laurenmurphyx64 files: - - boards/x86/ + - boards/intel/adl/ + - boards/intel/ehl/ + - boards/intel/rpl/ - dts/x86/intel/ - - soc/x86/ + - soc/intel/atom/ + - soc/intel/lakemont/ + - soc/intel/*_lake/ - samples/boards/up_squared/ labels: - "platform: X86" @@ -3205,8 +3214,8 @@ Intel Platforms (Xtensa): - jxstelter - marcinszkudlinski files: - - boards/xtensa/intel_*/ - - soc/xtensa/intel_*/ + - boards/intel/adsp/ + - soc/intel/intel_adsp/ - dts/xtensa/intel/ - tests/boards/intel_adsp/ - samples/boards/intel_adsp/ @@ -3223,8 +3232,8 @@ Intel Platforms (ISH): - teburd - likongintel files: - - boards/x86/intel_ish/ - - soc/x86/intel_ish/ + - boards/intel/ish/ + - soc/intel/intel_ish/ - dts/x86/intel/intel_ish* - dts/bindings/*/intel,sedi* - drivers/*/*sedi* @@ -3239,8 +3248,8 @@ Intel Platforms (Agilex): - nbalabak - teikheng files: - - boards/arm64/intel_*/ - - soc/arm64/intel_*/ + - boards/intel/socfpga/ + - soc/intel/intel_socfpga/ - dts/arm64/intel/ - dts/bindings/*/intel,agilex* - dts/arm/intel_socfpga_std/ @@ -3272,17 +3281,13 @@ NXP Drivers: - include/zephyr/drivers/*/*mcux* - arch/arm/core/mpu/nxp_mpu.c - dts/bindings/*/nxp* - files-exclude: - - drivers/*/*s32* - - drivers/misc/*/*s32* - - include/zephyr/dt-bindings/*/*s32* - - include/zephyr/drivers/*/*s32* - - dts/bindings/*/*s32* + files-regex-exclude: + - .*s32.* labels: - "platform: NXP Drivers" description: NXP Drivers -NXP Platforms (MCUX): +NXP Platforms (MCU): status: maintained maintainers: - dleach02 @@ -3294,23 +3299,21 @@ NXP Platforms (MCUX): - EmilioCBen - decsny files: - - boards/arm/mimx*/ - - boards/arm/frdm*/ - - boards/arm/lpcxpress*/ - - boards/arm/twr_*/ - - boards/arm/vmu*/ - - soc/arm/nxp_imx/ - - soc/arm/nxp_kinetis/ - - soc/arm/nxp_lpc/ + - boards/nxp/mimxrt*/ + - boards/nxp/frdm*/ + - boards/nxp/lpcxpress*/ + - boards/nxp/twr_*/ + - boards/nxp/vmu*/ + - soc/nxp/imxrt/ + - soc/nxp/kinetis/ + - soc/nxp/lpc/ - dts/arm/nxp/ - samples/boards/nxp*/ - files-exclude: - - boards/arm/*s32*/ - - dts/arm/nxp/*s32* - - samples/boards/nxp_s32/ + files-regex-exclude: + - .*s32.* labels: - "platform: NXP" - description: NXP Platforms supported by MCUXpresso suite + description: NXP MCU Platforms supported by MCUXpresso suite NXP Platforms (S32): status: maintained @@ -3321,11 +3324,11 @@ NXP Platforms (S32): - bperseghetti - Dat-NguyenDuy files: - - boards/arm/s32*/ - - boards/arm/mr_canhubk3/ - - boards/arm/ucans32k1sic/ + - boards/nxp/s32*/ + - boards/nxp/mr_canhubk3/ + - boards/nxp/ucans32k1sic/ - boards/common/*nxp_s32* - - soc/arm/nxp_s32/ + - soc/nxp/s32/ - drivers/*/*nxp_s32* - drivers/misc/*nxp_s32*/ - dts/bindings/*/nxp,s32* @@ -3338,6 +3341,26 @@ NXP Platforms (S32): - "platform: NXP S32" description: NXP S32 platforms and S32-specific drivers +NXP Platforms (MPU): + status: maintained + maintainers: + - dleach + collaborators: + - JiafeiPan + - dbaluta + - iuliana-prodan + - danieldegrasse + - decsny + - yvanderv + files: + - soc/nxp/imx/ + - soc/nxp/layerscape/ + files-regex: + - boards/nxp/m?imx[^(rt)].*/ + labels: + - "platform: NXP MPU" + description: NXP MPU platforms + NXP Platforms (Xtensa): status: maintained maintainers: @@ -3345,10 +3368,10 @@ NXP Platforms (Xtensa): collaborators: - iuliana-prodan files: - - soc/xtensa/nxp_adsp/ - - boards/xtensa/nxp_adsp_*/ + - soc/nxp/imx/*/adsp/ + - soc/nxp/imxrt/imxrt5xx/f1/ labels: - - "platform: NXP ADSP" + - "platform: NXP Xtensa" description: NXP Xtensa platforms Microchip MEC Platforms: @@ -3359,9 +3382,9 @@ Microchip MEC Platforms: - VenkatKotakonda - albertofloyd files: - - boards/arm/mec*/ + - boards/microchip/mec*/ - dts/arm/microchip/ - - soc/arm/microchip_mec/ + - soc/microchip/mec/ - drivers/*/*mchp*.c - tests/boards/mec15xxevb_assy6853/ - tests/boards/mec172xevb_assy6906/ @@ -3379,10 +3402,9 @@ Microchip SAM Platforms: - mnkp - stephanosio files: - - boards/arm/atsam*/ - - boards/arm/sam*/ + - boards/atmel/ - dts/arm/atmel/ - - soc/arm/atmel_sam*/ + - soc/atmel/ - drivers/*/*sam*.c - dts/bindings/*/atmel,* labels: @@ -3393,9 +3415,9 @@ nRF Platforms: maintainers: - anangl files: - - boards/arm/*nrf*/ + - boards/nordic/ - drivers/*/*nrfx*.c - - soc/arm/nordic_nrf/ + - soc/nordic/ - samples/boards/nrf/ - dts/arm/nordic/ - dts/bindings/*/nordic,* @@ -3409,11 +3431,11 @@ Renesas SmartBond Platforms: - andrzej-kaczmarek - blauret files: - - boards/arm/da14*/ + - boards/renesas/da14*/ - drivers/*/*smartbond* - dts/arm/renesas/smartbond/ - dts/bindings/*/renesas,smartbond* - - soc/arm/renesas_smartbond/ + - soc/renesas/smartbond/ labels: - "platform: Renesas SmartBond" description: >- @@ -3425,11 +3447,11 @@ Renesas RA Platforms: maintainers: - soburi files: - - boards/arm/arduino_uno_r4/ + - boards/arduino/uno_r4_minima/ - drivers/*/*renesas_ra* - dts/arm/renesas/ra/ - dts/bindings/*/*renesas,ra* - - soc/arm/renesas_ra/ + - soc/renesas/ra/ labels: - "platforms: Renesas RA" description: >- @@ -3441,11 +3463,11 @@ Renesas RZ Platforms: maintainers: - tgorochowik files: - - boards/arm/rzt2m_*/ + - boards/renesas/rzt2m_*/ - drivers/*/*rzt2m* - dts/arm/renesas/rz/ - dts/bindings/*/*rzt2m* - - soc/arm/renesas_rzt2m/ + - soc/renesas/rzt2m/ labels: - "platforms: Renesas RZ" description: >- @@ -3461,15 +3483,13 @@ Renesas R-Car Platforms: - xakep-amatop files: - dts/arm/renesas/rcar/ - - boards/arm/rcar_*/ - - boards/arm64/rcar_*/ + - boards/renesas/rcar_*/ - drivers/*/*rcar* - drivers/clock_control/*cpg_mssr* - dts/arm/renesas/rcar/ - dts/arm64/renesas/ - dts/bindings/*/*rcar* - - soc/arm/renesas_rcar/ - - soc/arm64/renesas_rcar/ + - soc/renesas/rcar/ labels: - "platform: Renesas R-Car" description: >- @@ -3488,11 +3508,7 @@ STM32 Platforms: - Desvauxm-st - GeorgeCGV files: - - boards/arm/b_*/ - - boards/arm/nucleo_*/ - - boards/arm/stm32*_disco/ - - boards/arm/stm32*_dk*/ - - boards/arm/stm32*_eval/ + - boards/st/ - drivers/*/*stm32*/ - drivers/*/*stm32*.c - drivers/*/*stm32*.h @@ -3500,7 +3516,7 @@ STM32 Platforms: - drivers/*/*stm32* - dts/arm/st/ - dts/bindings/*/*stm32* - - soc/arm/st_stm32/ + - soc/st/stm32/ - samples/boards/stm32/ labels: - "platform: STM32" @@ -3518,16 +3534,14 @@ Espressif Platforms: - uLipe files: - drivers/*/*esp32*.c - - boards/xtensa/esp32*/ - - soc/xtensa/espressif_esp32*/ - - boards/riscv/esp32*/ - - soc/riscv/espressif_esp32*/ + - boards/espressif/ + - soc/espressif/ - dts/xtensa/espressif/ - dts/riscv/espressif/ - dts/bindings/*/*esp32* - samples/boards/esp32*/ - tests/boards/espressif_esp32/ - - drivers/wifi/esp32/ + - drivers/*/*esp32*/ labels: - "platform: ESP32" @@ -3543,13 +3557,13 @@ ITE Platforms: - brockus-zephyr - sjg20 files: - - boards/riscv/it8*_evb/ + - boards/ite/ - drivers/*/*/*it8xxx2*.c - drivers/*/*it8xxx2*.c - drivers/*/*_ite_* - dts/bindings/*/*ite* - dts/riscv/ite/ - - soc/riscv/ite_ec/ + - soc/ite/ labels: - "platform: ITE" @@ -3560,17 +3574,15 @@ TI SimpleLink Platforms: collaborators: - vanti files: - - boards/arm/cc13*/ - - boards/arm/cc26*/ - - boards/arm/cc32*/ - - boards/*/msp*/ + - boards/ti/cc*/ + - boards/ti/msp*/ - drivers/*/*cc13* - drivers/*/*cc25* - drivers/*/*cc26* - drivers/*/*cc32* - dts/arm/ti/ - dts/bindings/*/ti,* - - soc/arm/ti_simplelink/ + - soc/ti/simplelink/ - dts/bindings/*/ti,* - modules/Kconfig.simplelink labels: @@ -3583,18 +3595,18 @@ TI K3 Platforms: collaborators: - gramsay0 files: - - boards/*/*phycore_am6*/ - - boards/*/am6*/ + - boards/phytec/*am62*/ + - boards/ti/*am62*/ - drivers/*/*ti_k3* - dts/bindings/*/ti,k3* - - soc/*/ti_k3/ + - soc/ti/k3/ labels: - "platform: TI K3" TI Platforms: status: odd fixes files: - - soc/arm/ti_lm3s6965/ + - soc/ti/lm3s6965/ - dts/arm/ti/lm3s6965.dtsi labels: - "platform: TI" @@ -3609,7 +3621,7 @@ Xilinx Platforms: - dts/*/xilinx/ - dts/bindings/*/*xlnx* - include/zephyr/*/*/*xlnx* - - soc/arm/xilinx*/ + - soc/xlnx/ labels: - "platform: Xilinx" @@ -3621,18 +3633,17 @@ Infineon Platforms: - npal-cy - talih0 files: - - boards/arm/cy8ckit_*/ - - boards/arm/cy8cproto_*/ - - boards/arm/xmc*_relax*/ + - boards/cypress/ + - boards/infineon/ - drivers/*/*ifx_cat1* - drivers/*/*xmc*/ - drivers/*/*xmc*.c - drivers/*/*/*xmc* - dts/arm/infineon/ - dts/arm/cypress/ - - soc/arm/cypress/ + - soc/cypress/ - dts/bindings/*/*infineon* - - soc/arm/infineon_*/ + - soc/infineon/ labels: - "platform: Infineon" description: >- @@ -3644,7 +3655,7 @@ Panasonic Platforms: maintainers: - pideu-sj files: - - boards/arm/pan17*/ + - boards/panasonic/ labels: - "platform: Panasonic" @@ -4588,11 +4599,11 @@ Xtensa arch: - arch/xtensa/ - include/zephyr/arch/xtensa/ - dts/xtensa/ - - boards/xtensa/qemu_xtensa/ - - boards/xtensa/xt-sim/ - - soc/xtensa/dc233c/ - - soc/xtensa/sample_controller/ - - soc/xtensa/CMakeLists.txt + - boards/qemu/xtensa/ + - boards/cdns/xt-sim/ + - soc/cdns/dc233c/ + - soc/cdns/dc233c/ + - soc/cdns/xtensa_sample_controller/ labels: - "area: Xtensa" @@ -4698,8 +4709,8 @@ Testing with Renode: - fkokosinski files: - cmake/emu/renode.cmake - - boards/*/*/support/*.repl - - boards/*/*/support/*.resc + - boards/**/*/support/*.repl + - boards/**/*/support/*.resc labels: - "area: Renode" diff --git a/arch/Kconfig b/arch/Kconfig index 1e28103509f256..4a90eb395d3b4e 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -8,8 +8,10 @@ # Include these first so that any properties (e.g. defaults) below can be # overridden (by defining symbols in multiple locations) -# Note: $ARCH might be a glob pattern -source "$(ARCH_DIR)/$(ARCH)/Kconfig" +source "$(ARCH_DIR)/Kconfig.$(HWM_SCHEME)" + +# ToDo: Generate a Kconfig.arch for loading of additional arch in HWMv2. +osource "$(KCONFIG_BINARY_DIR)/Kconfig.arch" # Architecture symbols # @@ -1019,27 +1021,6 @@ config ARCH help System architecture string. -config SOC - string - help - SoC name which can be found under soc//. - This option holds the directory name used by the build system to locate - the correct linker and header files for the SoC. - -config SOC_SERIES - string - help - SoC series name which can be found under soc///. - This option holds the directory name used by the build system to locate - the correct linker and header files. - -config SOC_FAMILY - string - help - SoC family name which can be found under soc//. - This option holds the directory name used by the build system to locate - the correct linker and header files. - config TOOLCHAIN_HAS_BUILTIN_FFS bool default y if !(64BIT && RISCV) diff --git a/arch/Kconfig.v1 b/arch/Kconfig.v1 new file mode 100644 index 00000000000000..d76acba59a3e19 --- /dev/null +++ b/arch/Kconfig.v1 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Note: $ARCH might be a glob pattern +source "$(ARCH_DIR)/$(ARCH)/Kconfig" diff --git a/arch/Kconfig.v2 b/arch/Kconfig.v2 new file mode 100644 index 00000000000000..19db8d46246576 --- /dev/null +++ b/arch/Kconfig.v2 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +source "$(KCONFIG_BINARY_DIR)/arch/Kconfig" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index 5dee9d76b841e0..8a3bd5b1b3c2a7 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -9,7 +9,6 @@ menu "ARC Options" config ARCH default "arc" - config CPU_ARCEM bool select ATOMIC_OPERATIONS_C @@ -380,8 +379,6 @@ config ARC_EARLY_SOC_INIT (before C runtime initialization). Setup code is called in form of soc_early_asm_init_percpu assembler macro. -endmenu - config MAIN_STACK_SIZE default 4096 if 64BIT @@ -408,3 +405,5 @@ config CMSIS_V2_THREAD_MAX_STACK_SIZE config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE default 2048 if 64BIT + +endmenu diff --git a/arch/archs.yml b/arch/archs.yml new file mode 100644 index 00000000000000..e07d10ffe80b36 --- /dev/null +++ b/arch/archs.yml @@ -0,0 +1,21 @@ +archs: + - name: arc + path: arc + - name: arm + path: arm + - name: arm64 + path: arm64 + - name: mips + path: mips + - name: nios2 + path: nios2 + - name: posix + path: posix + - name: riscv + path: riscv + - name: sparc + path: sparc + - name: xtensa + path: xtensa + - name: x86 + path: x86 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8b0d53ec3cf203..3f5f3075777fc8 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -82,4 +82,47 @@ config ARM_ON_EXIT_CPU_IDLE rsource "core/Kconfig" rsource "core/Kconfig.vfp" +# General options signifying CPU capabilities of ARM SoCs +config CPU_HAS_ARM_MPU + bool + select CPU_HAS_MPU + help + This option is enabled when the CPU has a Memory Protection Unit (MPU) + in ARM flavor. + +config CPU_HAS_NXP_MPU + bool + select CPU_HAS_MPU + help + This option is enabled when the CPU has a Memory Protection Unit (MPU) + in NXP flavor. + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + bool "Custom fixed SoC MPU region definition" + help + If enabled, this option signifies that the SoC will + define and configure its own fixed MPU regions in the + SoC definition. These fixed MPU regions are currently + used to set Flash and SRAM default access policies and + they are programmed at boot time. + +config CPU_HAS_ARM_SAU + bool + select CPU_HAS_TEE + help + MCU implements the ARM Security Attribution Unit (SAU). + +config CPU_HAS_NRF_IDAU + bool + select CPU_HAS_TEE + help + MCU implements the nRF (vendor-specific) Security Attribution Unit. + (IDAU: "Implementation-Defined Attribution Unit", in accordance with + ARM terminology). + +config HAS_SWO + bool + help + When enabled, indicates that SoC has an SWO output + endmenu diff --git a/arch/arm/core/cortex_m/timing.c b/arch/arm/core/cortex_m/timing.c index 861f1a9995aaa2..3b847af02ac58f 100644 --- a/arch/arm/core/cortex_m/timing.c +++ b/arch/arm/core/cortex_m/timing.c @@ -28,8 +28,8 @@ */ static inline uint64_t z_arm_dwt_freq_get(void) { -#if defined(CONFIG_SOC_FAMILY_NRF) || \ - defined(CONFIG_SOC_SERIES_IMX_RT6XX) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) || \ + defined(CONFIG_SOC_SERIES_IMXRT6XX) /* * DWT frequency is taken directly from the * System Core clock (CPU) frequency, if the @@ -77,7 +77,7 @@ static inline uint64_t z_arm_dwt_freq_get(void) } return dwt_frequency; -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ } void arch_timing_init(void) diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt index 409c378f620bef..78fc6396ed63ac 100644 --- a/arch/common/CMakeLists.txt +++ b/arch/common/CMakeLists.txt @@ -71,7 +71,7 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY # Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET. if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64 - OR DEFINED CONFIG_SOC_OPENISA_RV32M1_RISCV32) + OR DEFINED CONFIG_SOC_OPENISA_RV32M1) # Exclamation mark is printable character with lowest number in ASCII table. # We are sure that this file will be included as a first. zephyr_linker_sources(ROM_START SORT_KEY ! rom_start_address.ld) diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c index 36457a23de7f99..d0f789a328d6a5 100644 --- a/arch/riscv/core/fatal.c +++ b/arch/riscv/core/fatal.c @@ -163,7 +163,7 @@ void _Fault(z_arch_esf_t *esf) __asm__ volatile("csrr %0, mcause" : "=r" (mcause)); -#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32 +#ifndef CONFIG_SOC_OPENISA_RV32M1 unsigned long mtval; __asm__ volatile("csrr %0, mtval" : "=r" (mtval)); #endif @@ -171,7 +171,7 @@ void _Fault(z_arch_esf_t *esf) mcause &= CONFIG_RISCV_MCAUSE_EXCEPTION_MASK; LOG_ERR(""); LOG_ERR(" mcause: %ld, %s", mcause, cause_str(mcause)); -#ifndef CONFIG_SOC_OPENISA_RV32M1_RISCV32 +#ifndef CONFIG_SOC_OPENISA_RV32M1 LOG_ERR(" mtval: %lx", mtval); #endif diff --git a/arch/x86/core/early_serial.c b/arch/x86/core/early_serial.c index 3a0bc7465e1ff1..a2abafbf05e508 100644 --- a/arch/x86/core/early_serial.c +++ b/arch/x86/core/early_serial.c @@ -8,7 +8,6 @@ #include #include #include -#include #if DT_PROP_OR(DT_CHOSEN(zephyr_console), io_mapped, 0) != 0 diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt index db0909bb4f8d26..e9271d4982f64e 100644 --- a/arch/xtensa/core/CMakeLists.txt +++ b/arch/xtensa/core/CMakeLists.txt @@ -53,7 +53,7 @@ file(WRITE ${CORE_ISA_IN} "#include \n") add_custom_command(OUTPUT ${CORE_ISA_DM} COMMAND ${CMAKE_C_COMPILER} -E -dM -U__XCC__ -I${ZEPHYR_XTENSA_MODULE_DIR}/zephyr/soc/${CONFIG_SOC} - -I${SOC_DIR}/${ARCH}/${SOC_PATH} + -I${SOC_FULL_DIR} ${CORE_ISA_IN} -o ${CORE_ISA_DM}) # Generates a list of device-specific scratch register choices diff --git a/boards/arm/96b_aerocore2/96b_aerocore2.dts b/boards/96boards/aerocore2/96b_aerocore2.dts similarity index 100% rename from boards/arm/96b_aerocore2/96b_aerocore2.dts rename to boards/96boards/aerocore2/96b_aerocore2.dts diff --git a/boards/arm/96b_aerocore2/96b_aerocore2.yaml b/boards/96boards/aerocore2/96b_aerocore2.yaml similarity index 94% rename from boards/arm/96b_aerocore2/96b_aerocore2.yaml rename to boards/96boards/aerocore2/96b_aerocore2.yaml index b066c364322ef1..6e704190fddae4 100644 --- a/boards/arm/96b_aerocore2/96b_aerocore2.yaml +++ b/boards/96boards/aerocore2/96b_aerocore2.yaml @@ -19,4 +19,4 @@ supported: - adc ram: 256 flash: 2048 -vendor: gumstix +vendor: 96boards diff --git a/boards/arm/96b_aerocore2/96b_aerocore2_defconfig b/boards/96boards/aerocore2/96b_aerocore2_defconfig similarity index 86% rename from boards/arm/96b_aerocore2/96b_aerocore2_defconfig rename to boards/96boards/aerocore2/96b_aerocore2_defconfig index 8cd955fe1cbe88..490ce68a742b4b 100644 --- a/boards/arm/96b_aerocore2/96b_aerocore2_defconfig +++ b/boards/96boards/aerocore2/96b_aerocore2_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2020 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F427XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/aerocore2/Kconfig.96b_aerocore2 b/boards/96boards/aerocore2/Kconfig.96b_aerocore2 new file mode 100644 index 00000000000000..dae093b174bc21 --- /dev/null +++ b/boards/96boards/aerocore2/Kconfig.96b_aerocore2 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_AEROCORE2 + select SOC_STM32F427XX diff --git a/boards/arm/96b_aerocore2/board.cmake b/boards/96boards/aerocore2/board.cmake similarity index 100% rename from boards/arm/96b_aerocore2/board.cmake rename to boards/96boards/aerocore2/board.cmake diff --git a/boards/96boards/aerocore2/board.yml b/boards/96boards/aerocore2/board.yml new file mode 100644 index 00000000000000..42c4b7cae96847 --- /dev/null +++ b/boards/96boards/aerocore2/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_aerocore2 + vendor: 96boards + socs: + - name: stm32f427xx diff --git a/boards/arm/96b_aerocore2/doc/img/96b_aerocore2.jpg b/boards/96boards/aerocore2/doc/img/96b_aerocore2.jpg similarity index 100% rename from boards/arm/96b_aerocore2/doc/img/96b_aerocore2.jpg rename to boards/96boards/aerocore2/doc/img/96b_aerocore2.jpg diff --git a/boards/96boards/aerocore2/doc/index.rst b/boards/96boards/aerocore2/doc/index.rst new file mode 100644 index 00000000000000..ca12b694950eba --- /dev/null +++ b/boards/96boards/aerocore2/doc/index.rst @@ -0,0 +1,349 @@ +.. _96b_aerocore2_board: + +96Boards Aerocore2 +################## + +Overview +******** + +The 96Boards Aerocore2 Mezzanine is based on the STMicroelectronics +STM32F427VIT6 Cortex-M4 CPU primarily designed for use in drones. +This board acts as a mezzanine platform for all 96Boards CE compliant +boards. It can also be used as a standalone board. + + +.. figure:: img/96b_aerocore2.jpg + :align: center + :alt: 96Boards Aerocore2 + + 96Boards Aerocore2 + +Hardware +******** + +96Boards Aerocore2 provides the following hardware components: + +- STM32F427VIT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 2048 KB Flash +- 256 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels +- RTC +- Advanced-control Timers (2) +- General Purpose Timers (10) +- Watchdog Timers (2) +- USART/UART (4) +- I2C (3) +- SPI (3) +- SDIO +- USB 2.0 OTG FS +- DMA Controller + +More information about STM32F427VIT6 can be found here: + - `STM32F427 on www.st.com`_ + +Supported Features +================== + +The Zephyr 96b_aerocore2 board configuration supports the following hardware +features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| PWM | on-chip | timers / pwm | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ + +More details about the board can be found at `96Boards website`_. + +The default configuration can be found in +:zephyr_file:`boards/96boards/aerocore2/96b_aerocore2_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PE10 +- LED2 / User2 LED = PE9 + +External Connectors +------------------- + +Octal PWM Header (J1) + ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | Pin # | Signal Name | ++=======+=============+=========================+=======+=============+=======+=============+ +| 1 | PWM4_CH1 | PD12 | 2 | 5.0v | 3 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 4 | PWM4_CH2 | PD13 | 5 | 5.0v | 6 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 7 | PWM4_CH3 | PD14 | 8 | 5.0v | 9 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 10 | PWM4_CH4 | PD15 | 11 | 5.0v | 12 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 13 | PWM5_CH1 | PA0 | 14 | 5.0v | 15 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 16 | PWM5_CH2 | PA1 | 17 | 5.0v | 18 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 19 | PWM5_CH3 | PA2 | 20 | 5.0v | 21 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ +| 22 | PWM5_CH4 | PA3 | 23 | 5.0v | 24 | GND | ++-------+-------------+-------------------------+-------+-------------+-------+-------------+ + + +IO Header J11 + ++-------+-------------+-------+-------------+ +| PIN # | Signal Name | PIN # | Signal Name | ++=======+=============+=======+=============+ +| 1 | PB9 | 2 | PB8* | ++-------+-------------+-------+-------------+ +| 3 | PC9 | 4 | PB0 | ++-------+-------------+-------+-------------+ +| 5 | PE5 | 6 | NA | ++-------+-------------+-------+-------------+ +| 7 | PE6 | 8 | NA | ++-------+-------------+-------+-------------+ +| 9 | PC6 | 10 | NA | ++-------+-------------+-------+-------------+ +| 11 | PC7 | 12 | NA | ++-------+-------------+-------+-------------+ +| 13 | PC8 | 14 | NA | ++-------+-------------+-------+-------------+ +| 15 | PA8 | 16 | GND | ++-------+-------------+-------+-------------+ +| 17 | PA9 | 18 | 3v3 | ++-------+-------------+-------+-------------+ +| 19 | PA10 | 20 | GND | ++-------+-------------+-------+-------------+ + +* PB8 is connected to a watchdog buzzer, It needs to be pulsed every 10 seconds to keep the buzzer silent. + +IO Header J5 + ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | STM32F427 Functions Pin | ++=======+=============+=========================+=======+=============+=========================+ +| 1 | AGND | AGND | 2 | ADC1_13 | PC3 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 3 | ADC1_12 | PC2 | 4 | ADC1_11 | PC1 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 5 | I2C_SDA | PB11 | 6 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 7 | I2C_SCL | PB10 | 8 | VCC 3v3 | VCC 3v3 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 9 | NC | NC | 10 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 11 | NC | NC | 12 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 13 | UART_TX 7 | PE8 | 14 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 15 | UART_RX 7 | PE7 | 16 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 17 | UART_TX 2 | PD5 | 18 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 19 | UART_TX 2 | PD6 | 20 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 21 | NC | NC | 10 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 23 | NC | NC | 10 | NC | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 25 | SPI1_NIRQ | PC5 | 26 | GND | GND | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 27 | SPI1_CLK | PA5 | 28 | SPI1_MISO | PA6 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 29 | SPI1_CS0 | PA4 | 30 | SPI1_MOSI | PA7 | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 31 | CAN_TX | PD1 | 32 | CANH | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ +| 33 | CAN_RX | PD0 | 34 | CANL | NC | ++-------+-------------+-------------------------+-------+-------------+-------------------------+ + + +GPS connector J15 + ++-------+-------------+-------------------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | ++=======+=============+=========================+ +| 1 | V_OUT 5v | NC | ++-------+-------------+-------------------------+ +| 2 | UART1_TX | PB6 | ++-------+-------------+-------------------------+ +| 3 | UART1_RX | PB7 | ++-------+-------------+-------------------------+ +| 4 | VCC 3v3 | NC | ++-------+-------------+-------------------------+ +| 5 | GND | GND | ++-------+-------------+-------------------------+ + + +Spektrum connector J3 + ++-------+-------------+-------------------------+ +| PIN # | Signal Name | STM32F427 Functions Pin | ++=======+=============+=========================+ +| 1 | VCC 3v3 | NC | ++-------+-------------+-------------------------+ +| 2 | GND | GND | ++-------+-------------+-------------------------+ +| 3 | UART8_RX | PE0 | ++-------+-------------+-------------------------+ + + +External Clock Sources +---------------------- + +STM32F4 has one external oscillator. The frequency of the clock is +32.768 kHz. The internal 16MHz clock is used as the main clock. + +Serial Port +----------- + +96Boards Aerocore2 board has up to 4 U(S)ARTs. The Zephyr console output is +assigned to USART7. Default settings are 115200 8N1. + +I2C +--- + +96Boards Aerocore2 board has 1 I2C port. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB10 +- I2C1_SDA : PB11 + +SPI +--- + +96Boards Aerocore2 board has 1 SPI port. The default SPI mapping for Zephyr is: + +- SPI1_CS0 : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 + +USB +=== + +96Boards Aerocore2 board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its mini "OTG" USB connector. +Only USB device functions are supported in Zephyr at the moment. + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader +supports flashing via USB (DFU), UART, I2C and SPI. You can read more about +how to enable and use the ROM bootloader by checking the application +note `AN2606`_, page 109. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +Flashing an Application to 96Boards Aerocore2 +--------------------------------------------- + +Connect the micro-USB cable to the USB OTG/STM_CONSOLE Aerocore2 port and to your computer. +The board should power ON. Force the board into DFU mode by keeping the BOOT0 +switch pressed while pressing and releasing the RST switch. + +The BOOT button is located at the back-side of the PCB. + +Confirm that the board is in DFU mode: + +.. code-block:: console + + $ sudo dfu-util -l + dfu-util 0.8 + Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. + Copyright 2010-2014 Tormod Volden and Stefan Schmidt + This program is Free Software and has ABSOLUTELY NO WARRANTY + Please report bugs to dfu-util@lists.gnumonks.org + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" + Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" + +You should see following confirmation on your Linux host: + +.. code-block:: console + + $ dmesg + usb 1-2.1: new full-speed USB device number 14 using xhci_hcd + usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 + usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + usb 1-2.1: Product: STM32 BOOTLOADER + usb 1-2.1: Manufacturer: STMicroelectronics + usb 1-2.1: SerialNumber: 3574364C3034 + +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_aerocore2 + :goals: build flash + +Connect a USB-TTL dongle to the UART_7 header port and to your computer. +Run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board 96Boards Aerocore2 +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. +The ``-b`` option sets baud rate ignoring the value from config. + +Press the Reset button and you should see the following message in your +terminal: + +.. code-block:: console + + Hello World! arm + +.. _96Boards website: + https://www.96boards.org/product/aerocore2/ + +.. _STM32F427 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _AN2606: + https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf diff --git a/boards/arm/96b_argonkey/96b_argonkey.dts b/boards/96boards/argonkey/96b_argonkey.dts similarity index 100% rename from boards/arm/96b_argonkey/96b_argonkey.dts rename to boards/96boards/argonkey/96b_argonkey.dts diff --git a/boards/arm/96b_argonkey/96b_argonkey.yaml b/boards/96boards/argonkey/96b_argonkey.yaml similarity index 100% rename from boards/arm/96b_argonkey/96b_argonkey.yaml rename to boards/96boards/argonkey/96b_argonkey.yaml diff --git a/boards/arm/96b_argonkey/96b_argonkey_defconfig b/boards/96boards/argonkey/96b_argonkey_defconfig similarity index 85% rename from boards/arm/96b_argonkey/96b_argonkey_defconfig rename to boards/96boards/argonkey/96b_argonkey_defconfig index 76869d633452fc..82ee7285d52d8a 100644 --- a/boards/arm/96b_argonkey/96b_argonkey_defconfig +++ b/boards/96boards/argonkey/96b_argonkey_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412CX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/argonkey/Kconfig.96b_argonkey b/boards/96boards/argonkey/Kconfig.96b_argonkey new file mode 100644 index 00000000000000..6795385fa40200 --- /dev/null +++ b/boards/96boards/argonkey/Kconfig.96b_argonkey @@ -0,0 +1,5 @@ +# Copyright (c) 2018 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_ARGONKEY + select SOC_STM32F412CX diff --git a/boards/96boards/argonkey/Kconfig.defconfig b/boards/96boards/argonkey/Kconfig.defconfig new file mode 100644 index 00000000000000..fd35e508696945 --- /dev/null +++ b/boards/96boards/argonkey/Kconfig.defconfig @@ -0,0 +1,23 @@ +# 96Boards Argonkey Board Configuration + +# Copyright (c) 2018 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_ARGONKEY + +if LSM6DSL + +choice LSM6DSL_TRIGGER_MODE + default LSM6DSL_TRIGGER_GLOBAL_THREAD +endchoice + +config LSM6DSL_SENSORHUB + default y + +choice LSM6DSL_EXTERNAL_SENSOR_0 + default LSM6DSL_EXT0_LIS2MDL +endchoice + +endif # LSM6DSL + +endif # BOARD_96B_ARGONKEY diff --git a/boards/96boards/argonkey/board.yml b/boards/96boards/argonkey/board.yml new file mode 100644 index 00000000000000..9e78ee2394a456 --- /dev/null +++ b/boards/96boards/argonkey/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_argonkey + vendor: 96boards + socs: + - name: stm32f412cx diff --git a/boards/arm/96b_argonkey/doc/img/96b_argonkey.jpg b/boards/96boards/argonkey/doc/img/96b_argonkey.jpg similarity index 100% rename from boards/arm/96b_argonkey/doc/img/96b_argonkey.jpg rename to boards/96boards/argonkey/doc/img/96b_argonkey.jpg diff --git a/boards/96boards/argonkey/doc/index.rst b/boards/96boards/argonkey/doc/index.rst new file mode 100644 index 00000000000000..810ab2e578133e --- /dev/null +++ b/boards/96boards/argonkey/doc/index.rst @@ -0,0 +1,239 @@ +.. _96b_argonkey: + +96Boards Argonkey +################# + +Overview +******** + +96Boards Argonkey board is based on the ST Microelectronics STM32F412CG +Cortex M4 CPU. + +This board acts as a sensor hub platform for all 96Boards compliant +family products. It can also be used as a standalone board. + +.. figure:: img/96b_argonkey.jpg + :align: center + :alt: 96Boards Argonkey + + 96Boards Argonkey + +Hardware +******** + +96Boards Argonkey provides the following hardware components: + +- STM32F412CG in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 100 MHz max CPU frequency +- 1.8V work voltage +- 1024 KB Flash +- 256 KB SRAM +- On board sensors: + + - Humidity: STMicro HTS221 + - Temperature/Pressure: STMicro LPS22HB + - ALS: Intersil ISL29034 + - Proximity: STMicro VL53L0X + - Accelerometer/Gyroscope: STMicro LSM6DSL + - Geomagnetic: STMicro LIS2MDL + - AMR Hall sensor: MRMS501A + - Microphone: STMicro MP34DT05 + +- 2 User LEDs +- 16 General purpose LEDs +- GPIO with external interrupt capability +- UART +- I2C (3) +- SPI (1) +- I2S (1) + +Supported Features +================== + +The Zephyr 96b_argonkey board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +More information about the board can be found at the +`ARGONKEY website`_. + +The default board configuration can be found in +:zephyr_file:`boards/96boards/argonkey/96b_argonkey_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PB2 +- LED2 / User2 LED = PC13 + +Push buttons +------------ + +- BUTTON = RST (BT1) +- BUTTON = USR (BT2) + +System Clock +============ + +96Boards Argonkey can be driven by an internal oscillator as well as the main +PLL clock. In default board configuration, the 16MHz external oscillator is +used to drive the main PLL clock to generate a System Clock (SYSCLK) at 84MHz. +On the bus side, AHB clock runs at 84MHz, while APB1/APB2 clock runs at 42MHz. + +Serial Port +=========== + +On 96Boards Argonkey, Zephyr console output is assigned to USART1. +Default settings are 115200 8N1. + +I2C +--- + +96Boards Argonkey board has up to 3 I2Cs. The default I2C mapping is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB9 +- I2C3_SCL : PA8 +- I2C3_SCL : PB4 + +I2C3 goes to the P2 connector and can be used to attach external sensors. +It goes to 100Kbit maximum. + +SPI +--- +96Boards Argonkey board has 2 SPIs. SPI1 is used in slave mode as the communication +bus with the AP. SPI2 is used in master mode to control the LSM6DSL sensor. +The default SPI mapping is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 + +Programming and Debugging +************************* + +Building +======== + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_argonkey + :goals: build + +Flashing +======== + +96Boards Argonkey can be flashed by two methods, one using the ROM +bootloader and another using the SWD debug port (which requires additional +hardware). + +Flashing using the ROM bootloader requires a special activation pattern, +which can be triggered by using the BOOT0 pin. The ROM bootloader supports +flashing via USB (DFU), UART, I2C and SPI, but this document describes the +UART case only. You can read more about how to enable and use the ROM +bootloader by checking the application note `AN2606`_ . + +Using ROM bootloader: +--------------------- + +Hereafter the documents describes basic steps to perform ArgonKey firmware +flashing on a Linux PC using UART as communication channel. + +1. Connect ArgonKey UART to your Linux PC using, for example, a USB-TTL serial + cable. The flashing procedure has been tested using a `TTL-232RG`_ cable with + FTDI chip. The UART pins on ArgonKey can be found on the P3 low speed + expansion connector on the back of the board. + + - GND (black) to ArgonKey GND (P3.1) + - TXD (orange) to ArgonKey UART0_TXD (P3.5) + - RXD (yellow) to ArgonKey UART0_RXD (P3.7) + + When the USB cable is inserted to the Linux PC the following device will be + created: /dev/ttyUSBx (x is usually '0'). + +2. Force STM32F412CG to enter in Bootloader mode + + - Connect BOOT0 to 1V8 (link P2.1 to P3.30) + - Press and release the RST button + +3. Use stm32flash utility to flash the ArgonKey: + +.. code-block:: console + + $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyUSB0 + +See References section for more info on `stm32flash`_. + +Using SWD debugger: +------------------- + +Select a commercial JTAG/SWD h/w tool and connect it to ArgonKey P4 connector. + +The ArgonKey has been tested using the `ST-LINK/V2`_ tool. Once that the tool +is connected to the PC through USB, it presents itself as a USB composite +device with mass storage capability. The device can be then mounted in linux +and the f/w can be actually copied there and will be automatically flashed by +the ST-LINK onto the ArgonKey. + +Example: + +.. code-block:: console + + $ mount /dev/sdb /mnt + $ cp zephyr.bin /mnt + $ umount /mnt + +Debugging +========= + +References +********** + +.. target-notes:: + +.. _ARGONKEY website: + https://www.st.com/en/evaluation-tools/steval-mki187v1.html + +.. _AN2606: + https://www.st.com/resource/en/application_note/cd00167594.pdf + +.. _stm32flash: + https://sourceforge.net/p/stm32flash/wiki/Home/ + +.. _ST-LINK/V2: + https://www.st.com/en/development-tools/st-link-v2.html + +.. _TTL-232RG: + http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232RG_CABLES.pdf diff --git a/boards/arm/96b_avenger96/96b_avenger96.dts b/boards/96boards/avenger96/96b_avenger96.dts similarity index 100% rename from boards/arm/96b_avenger96/96b_avenger96.dts rename to boards/96boards/avenger96/96b_avenger96.dts diff --git a/boards/arm/96b_avenger96/96b_avenger96.yaml b/boards/96boards/avenger96/96b_avenger96.yaml similarity index 94% rename from boards/arm/96b_avenger96/96b_avenger96.yaml rename to boards/96boards/avenger96/96b_avenger96.yaml index e1e21e4d4c79ec..5d50bcd6943426 100644 --- a/boards/arm/96b_avenger96/96b_avenger96.yaml +++ b/boards/96boards/avenger96/96b_avenger96.yaml @@ -22,4 +22,4 @@ testing: - nfc ram: 256 flash: 64 -vendor: arrow +vendor: 96boards diff --git a/boards/arm/96b_avenger96/96b_avenger96_defconfig b/boards/96boards/avenger96/96b_avenger96_defconfig similarity index 89% rename from boards/arm/96b_avenger96/96b_avenger96_defconfig rename to boards/96boards/avenger96/96b_avenger96_defconfig index 05be01fbb36ec2..11db7ac995f04b 100644 --- a/boards/arm/96b_avenger96/96b_avenger96_defconfig +++ b/boards/96boards/avenger96/96b_avenger96_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32MP1X=y -CONFIG_SOC_STM32MP15_M4=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/avenger96/Kconfig.96b_avenger96 b/boards/96boards/avenger96/Kconfig.96b_avenger96 new file mode 100644 index 00000000000000..9c891b2cf4fede --- /dev/null +++ b/boards/96boards/avenger96/Kconfig.96b_avenger96 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_AVENGER96 + select SOC_STM32MP15_M4 diff --git a/boards/arm/96b_avenger96/board.cmake b/boards/96boards/avenger96/board.cmake similarity index 100% rename from boards/arm/96b_avenger96/board.cmake rename to boards/96boards/avenger96/board.cmake diff --git a/boards/96boards/avenger96/board.yml b/boards/96boards/avenger96/board.yml new file mode 100644 index 00000000000000..042bb6a472fbd9 --- /dev/null +++ b/boards/96boards/avenger96/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_avenger96 + vendor: 96boards + socs: + - name: stm32mp157cxx diff --git a/boards/arm/96b_avenger96/doc/img/96b_avenger96.jpg b/boards/96boards/avenger96/doc/img/96b_avenger96.jpg similarity index 100% rename from boards/arm/96b_avenger96/doc/img/96b_avenger96.jpg rename to boards/96boards/avenger96/doc/img/96b_avenger96.jpg diff --git a/boards/96boards/avenger96/doc/index.rst b/boards/96boards/avenger96/doc/index.rst new file mode 100644 index 00000000000000..b451a51ea02dbc --- /dev/null +++ b/boards/96boards/avenger96/doc/index.rst @@ -0,0 +1,279 @@ +.. _96b_avenger96: + +96Boards Avenger96 +################## + +Overview +******** + +96Boards Avenger96 board is based on ST Microelectronics STM32MP157A +multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4 +core. Zephyr OS is ported to run on the Cortex®-M4 core. + +- Board features: + + - PMIC: STPMIC1A + - RAM: 1024 Mbyte @ 533MHz + - Storage: + + - eMMC: v4.51: 8 Gbyte + - QSPI: 2Mbyte + - EEPROM: 128 byte + - microSD Socket: UHS-1 v3.01 + - Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant + - Wireless: + + - WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac + - Bluetooth: v4.2 (BR/EDR/BLE) + - USB: + + - Host - 2x type A, 2.0 high-speed + - OTG: - 1x type micro-AB, 2.0 high-speed + - HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4 + - Connectors: + + - 40-Pin Low Speed Header + - 60-Pin High Speed Header + - LEDs: + + - 4x Green user LEDs + - 1x Blue Bluetooth LED + - 1x Yellow WiFi LED + - 1x Red power supply LED + +.. image:: img/96b_avenger96.jpg + :align: center + :alt: 96Boards Avenger96 + +More information about the board can be found at the +`96Boards website`_. + +Hardware +******** + +The STM32MP157A SoC provides the following hardware capabilities: + +- Core: + + - 32-bit dual-core Arm® Cortex®-A7 + + - L1 32-Kbyte I / 32-Kbyte D for each core + - 256-Kbyte unified level 2 cache + - Arm® NEON™ + + - 32-bit Arm® Cortex®-M4 with FPU/MPU + + - Up to 209 MHz (Up to 703 CoreMark®) + +- Memories: + + - External DDR memory up to 1 Gbyte. + - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + + 64 KB of AHB SRAM in backup domain. + - Dual mode Quad-SPI memory interface + - Flexible external memory controller with up to 16-bit data bus + +- Clock management: + + - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz + LSI oscillator + - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator + - 6 × PLLs with fractional mode + +- General-purpose input/outputs: + + - Up to 176 I/O ports with interrupt capability + +- Interconnect matrix + +- 3 DMA controllers + +- Communication peripherals: + + - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) + - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) + - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy) + - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) + - SPDIF Rx with 4 inputs + - HDMI-CEC interface + - MDIO Slave interface + - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO) + - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability + - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously + - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI) + - 8- to 14-bit camera interface up to 140 Mbyte/s + - 6 analog peripherals + - 2 × ADCs with 16-bit max. resolution. + - 1 × temperature sensor + - 2 × 12-bit D/A converters (1 MHz) + - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 + filters + - Internal or external ADC/DAC reference VREF+ + +- Graphics: + + - 3D GPU: Vivante® - OpenGL® ES 2.0 + - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps + - MIPI® DSI 2 data lanes up to 1 GHz each + +- Timers: + + - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature + (incremental) encoder input + - 2 × 16-bit advanced motor control timers + - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) + - 5 × 16-bit low-power timers + - RTC with sub-second accuracy and hardware calendar + - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) + - 1 × SysTick Cortex®-M4 timer + +- Hardware acceleration: + + - HASH (MD5, SHA-1, SHA224, SHA256), HMAC + - 2 × true random number generator (3 oscillators each) + - 2 × CRC calculation unit + +- Debug mode: + + - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces + - 8-Kbyte embedded trace buffer + - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user + +More information about STM32P157A can be found here: + +- `STM32MP157A on www.st.com`_ +- `STM32MP157A reference manual`_ + +Supported Features +================== + +The Zephyr 96b_avenger96 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/96boards/avenger96/96b_avenger96_defconfig` + + +Connections and IOs +=================== + +96Boards Avenger96 Board schematic is available here: +`Avenger96 board schematics`_. + + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console) +- UART_4 TX/RX : PD1/PB2 + +System Clock +------------ + +The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value +must match the configured mlhclk_ck frequency. + +Serial Port +----------- + +96Boards Avenger96 board has 3 U(S)ARTs. The Zephyr console output is assigned +by default to the RAM console to be dumped by the Linux Remoteproc Framework +on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to +UART7 which is disabled by default. UART console can be enabled through +board's devicetree and 96b_avenger96_defconfig board file (or prj.conf +project files), and will disable existing RAM console output. Default UART +console settings are 115200 8N1. + +Programming and Debugging +************************* + +The STM32MP157A doesn't have QSPI flash for the Cortex®-M4 and it needs to be +started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the +Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset. +The Cortex®-A7 can perform these steps at bootloader level or after the Linux +system has booted. + +The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at +address 0x00000000 (RETRAM), the vector table should be loaded at this address +These are the memory mappings for Cortex®-A7 and Cortex®-M4: + ++------------+-----------------------+------------------------+----------------+ +| Region | Cortex®-A7 | Cortex®-M4 | Size | ++============+=======================+========================+================+ +| RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB | ++------------+-----------------------+------------------------+----------------+ +| MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB | ++------------+-----------------------+------------------------+----------------+ +| DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB | ++------------+-----------------------+------------------------+----------------+ + + +Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction +to load and start the Cortex-M4 firmware. + +Debugging +========= + +You can debug an application using OpenOCD and GDB. The Solution proposed below +is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux +environment. The firmware must first be loaded by the Cortex®-A7. Developer +then attaches the debugger to the running Zephyr using OpenOCD. + +Prerequisite +------------ +install `stm32mp1 developer package`_. + +1) start OpenOCD in a dedicated terminal + + - Start up the sdk environment:: + + source /environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi + + - Start OpenOCD:: + + ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_ev1_jlink_jtag.cfg + +2) run gdb in Zephyr environment + + .. code-block:: console + + # On Linux + cd $ZEPHYR_BASE/samples/hello_world + mkdir -p build && cd build + + # Use cmake to configure a Ninja-based build system: + cmake -GNinja -DBOARD=96b_avenger96 .. + + # Now run ninja on the generated build system: + ninja debug + +.. _96Boards website: + https://www.96boards.org/product/avenger96/ + +.. _STM32MP157A on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157a.html + +.. _STM32MP157A reference manual: + https://www.st.com/resource/en/reference_manual/DM00327659.pdf + +.. _Avenger96 board schematics: + https://www.96boards.org/documentation/consumer/avenger96/hardware-docs/files/avenger96-schematics.pdf + +.. _stm32mp1 developer package: + https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK + +.. _stm32mp157 boot Cortex-M4 firmware: + https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51-pinctrl.dtsi b/boards/96boards/carbon/96b_carbon_nrf51822-pinctrl.dtsi similarity index 100% rename from boards/arm/96b_carbon_nrf51/96b_carbon_nrf51-pinctrl.dtsi rename to boards/96boards/carbon/96b_carbon_nrf51822-pinctrl.dtsi diff --git a/boards/96boards/carbon/96b_carbon_nrf51822.dts b/boards/96boards/carbon/96b_carbon_nrf51822.dts new file mode 100644 index 00000000000000..98ccd264fdfe2e --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_nrf51822.dts @@ -0,0 +1,63 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "96b_carbon_nrf51822-pinctrl.dtsi" + +/ { + model = "Seeed Studio Carbon nRF51 96board"; + compatible = "seeed,carbon_nrf51"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + aliases { + watchdog0 = &wdt0; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi1 { + compatible = "nordic,nrf-spis"; + status = "okay"; + def-char = <0x00>; + + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + bt-hci@0 { + compatible = "zephyr,bt-hci-spi-slave"; + reg = <0>; + irq-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + }; +}; diff --git a/boards/96boards/carbon/96b_carbon_nrf51822.yaml b/boards/96boards/carbon/96b_carbon_nrf51822.yaml new file mode 100644 index 00000000000000..135d5aa461bd88 --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_nrf51822.yaml @@ -0,0 +1,13 @@ +identifier: 96b_carbon/nrf51822 +name: 96Boards Carbon (nRF51) +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - ble +vendor: seeed diff --git a/boards/96boards/carbon/96b_carbon_nrf51822_defconfig b/boards/96boards/carbon/96b_carbon_nrf51822_defconfig new file mode 100644 index 00000000000000..0a45ef65e1153a --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_nrf51822_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/96b_carbon/96b_carbon.dts b/boards/96boards/carbon/96b_carbon_stm32f401xe.dts similarity index 100% rename from boards/arm/96b_carbon/96b_carbon.dts rename to boards/96boards/carbon/96b_carbon_stm32f401xe.dts diff --git a/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml b/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml new file mode 100644 index 00000000000000..4b0c56dc5a4891 --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml @@ -0,0 +1,18 @@ +identifier: 96b_carbon/stm32f401xe +name: 96Boards Carbon +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - ble + - i2c + - counter + - spi + - usb_device +ram: 96 +flash: 512 +vendor: 96boards diff --git a/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig b/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig new file mode 100644 index 00000000000000..c729b83e3d0506 --- /dev/null +++ b/boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/96b_carbon/96b_lscon.dtsi b/boards/96boards/carbon/96b_lscon.dtsi similarity index 100% rename from boards/arm/96b_carbon/96b_lscon.dtsi rename to boards/96boards/carbon/96b_lscon.dtsi diff --git a/boards/96boards/carbon/Kconfig.96b_carbon b/boards/96boards/carbon/Kconfig.96b_carbon new file mode 100644 index 00000000000000..6db6af8cf3d9aa --- /dev/null +++ b/boards/96boards/carbon/Kconfig.96b_carbon @@ -0,0 +1,6 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_CARBON + select SOC_STM32F401XE if BOARD_96B_CARBON_STM32F401XE + select SOC_NRF51822_QFAC if BOARD_96B_CARBON_NRF51822 diff --git a/boards/96boards/carbon/Kconfig.defconfig b/boards/96boards/carbon/Kconfig.defconfig new file mode 100644 index 00000000000000..fe90a4fdd4cd7c --- /dev/null +++ b/boards/96boards/carbon/Kconfig.defconfig @@ -0,0 +1,61 @@ +# 96boards Carbon board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_CARBON_STM32F401XE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +endif # BT + +if NETWORKING + +# Re-create the NET_L2_BT dependencies here +config BT + default y + +config BT_PERIPHERAL + default BT + +config BT_CENTRAL + default BT + +config BT_SMP + default BT + +config BT_L2CAP_DYNAMIC_CHANNEL + default BT + +# BT is the only onboard network iface, so use it for IP networking +# if it's enabled + +config NET_L2_BT + depends on NET_IPV6 + default BT + +config NET_L2_BT_ZEP1656 + depends on NET_IPV6 + default BT + +endif # NETWORKING + +endif # BOARD_96B_CARBON_STM32F401XE + +if BOARD_96B_CARBON_NRF51822 + +config BT_CTLR + default BT + +endif # BOARD_96B_CARBON_NRF51822 diff --git a/boards/96boards/carbon/board.cmake b/boards/96boards/carbon/board.cmake new file mode 100644 index 00000000000000..19e4554022e98b --- /dev/null +++ b/boards/96boards/carbon/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_96B_CARBON_STM32F401XE) + board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") + + include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +endif() diff --git a/boards/96boards/carbon/board.yml b/boards/96boards/carbon/board.yml new file mode 100644 index 00000000000000..79101f957be323 --- /dev/null +++ b/boards/96boards/carbon/board.yml @@ -0,0 +1,6 @@ +board: + name: 96b_carbon + vendor: 96boards + socs: + - name: stm32f401xe + - name: nrf51822 diff --git a/boards/arm/96b_carbon/doc/img/96b_carbon.jpg b/boards/96boards/carbon/doc/img/96b_carbon.jpg similarity index 100% rename from boards/arm/96b_carbon/doc/img/96b_carbon.jpg rename to boards/96boards/carbon/doc/img/96b_carbon.jpg diff --git a/boards/arm/96b_carbon_nrf51/doc/img/96b_carbon_nrf51.jpg b/boards/96boards/carbon/doc/img/96b_carbon_nrf51.jpg similarity index 100% rename from boards/arm/96b_carbon_nrf51/doc/img/96b_carbon_nrf51.jpg rename to boards/96boards/carbon/doc/img/96b_carbon_nrf51.jpg diff --git a/boards/96boards/carbon/doc/nrf51822.rst b/boards/96boards/carbon/doc/nrf51822.rst new file mode 100644 index 00000000000000..072c0e2157f8b5 --- /dev/null +++ b/boards/96boards/carbon/doc/nrf51822.rst @@ -0,0 +1,170 @@ +.. _96b_carbon_nrf51_board: + +96Boards Carbon nRF51 +##################### + +Overview +******** + +This is the secondary nRF51822 chip on the 96Boards Carbon and provides +Bluetooth functionality to the main STM32F401RET chip via SPI. + +.. note:: + + If you're looking to reprogram the main STMicro part, see + :ref:`96b_carbon_board`. Users should not use this configuration + unless they want to reprogram the secondary chip which provides + Bluetooth connectivity. + + +Hardware +******** + +The 96Boards Carbon nRF51 has two external oscillators. The frequency +of the slow clock is 32.768 kHz. The frequency of the main clock is 16 +MHz. + +See :ref:`96b_carbon_board` for other general information about the +board; that configuration is for the same physical board, just a +different chip. + +Supported Features +================== + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPIS | on-chip | SPI slave | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/96boards/carbon/96b_carbon_nrf51822_defconfig` + +Connections and IOs +=================== + +SPI +--- + +96Boards Carbon nRF51 has one SPI, which for providing Bluetooth +communication. The default SPI mapping for Zephyr is: + +- SPI1_NSS : P0.25 +- SPI1_SCK : P0.07 +- SPI1_MISO : P0.30 +- SPI1_MOSI : P0.00 + +The SWD debug pins are broken out to an external header; all other +connected pins are to the main STM32F401RET chip. + +.. _96b_carbon_nrf51_programming: + +Programming and Debugging +************************* + +Flashing +======== + +The 96Boards Carbon nRF51 can be flashed using an external SWD +debugger, via the debug header labeled "BLE" on the board's +silkscreen. The header is not populated; 0.1" male header must be +soldered on first. + +.. figure:: img/96b_carbon_nrf51.jpg + :align: center + :alt: 96Boards Carbon nRF51 Debug + + 96Boards Carbon nRF51 Debug + +The following example assumes a Zephyr binary ``zephyr.elf`` will be +flashed to the board. + +It uses the `Black Magic Debug Probe`_ as an SWD programmer, which can +be connected to the BLE debug header using flying leads and its 20 Pin +JTAG Adapter Board Kit. When plugged into your host PC, the Black +Magic Debug Probe enumerates as a USB serial device as documented on +its `Getting started page`_. + +It also uses the GDB binary provided with the Zephyr SDK, +``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC +ARM Embedded, can be used as well. + +.. code-block:: console + + $ arm-zephyr-eabi-gdb -q zephyr.elf + (gdb) target extended-remote /dev/ttyACM0 + Remote debugging using /dev/ttyACM0 + (gdb) monitor swdp_scan + Target voltage: 3.3V + Available Targets: + No. Att Driver + 1 nRF51 + (gdb) attach 1 + Attaching to Remote target + 0xabcdef12 in ?? () + (gdb) load + +Debugging +========= + +After you've flashed the chip, you can keep debugging using the same +GDB instance. To reattach, just follow the same steps above, but don't +run "load". You can then debug as usual with GDB. In particular, type +"run" at the GDB prompt to restart the program you've flashed. + +As an aid to debugging, this board configuration directs a console +output to a currently unused pin connected to the STM32F401RET. Users +who are experienced in electronics rework can remove a resistor (R22) +on the board and attach a wire to the nRF51822's UART output. + +.. _96b_carbon_nrf51_bluetooth: + +Providing Bluetooth to 96b_carbon +********************************* + +This ``96b_carbon/nrf51822`` Zephyr board configuration can be used to provide +Bluetooth functionality from the secondary nRF51822 chip to the +primary STM32F401RE chip on the :ref:`96b_carbon_board`. + +To do this, build the ``samples/bluetooth/hci_spi/`` application +provided with Zephyr with ``BOARD=96b_carbon/nrf51822``, then flash it to +the nRF51822 chip using the instructions :ref:`above +<96b_carbon_nrf51_programming>`. (For instructions on how to build a +Zephyr application, see :ref:`build_an_application`.) + +.. warning:: + + Be sure to flash the hci_spi application to the nRF51822 chip and + not to the main STM32F401RET chip. While both chips are supported + by Zephyr, the hci_spi application providing Bluetooth support will + only run on the nRF51822 chip. + +References +********** + +- `Board documentation from 96Boards`_ +- `nRF51822 information from Nordic Semiconductor`_ + +.. _Black Magic Debug Probe: + https://github.com/blacksphere/blackmagic/wiki + +.. _Getting started page: + https://github.com/blacksphere/blackmagic/wiki/Getting-Started + +.. _Board documentation from 96Boards: + http://www.96boards.org/product/carbon/ + +.. _nRF51822 information from Nordic Semiconductor: + https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF51822 diff --git a/boards/96boards/carbon/doc/stm32f401xe.rst b/boards/96boards/carbon/doc/stm32f401xe.rst new file mode 100644 index 00000000000000..e025a12ff32129 --- /dev/null +++ b/boards/96boards/carbon/doc/stm32f401xe.rst @@ -0,0 +1,383 @@ +.. _96b_carbon_board: + +96Boards Carbon +############### + +Overview +******** + +The 96Boards is based on the STMicroelectronics STM32F401RET Cortex-M4 CPU and +also contains a nRF51822 chip connected over SPI for BLE connectivity. + +The 96Boards Carbon board is built with two chips: an STMicroelectronics +STM32F401RET Cortex-M4 CPU and an nRF51822 chip connected to +the Cortex-M4 CPU over SPI for Bluetooth LE connectivity. Even though +both chips exist on the same physical board, they must be programmed +separately: + +- The ``96b_carbon/stm32f401xe`` configuration is used when developing programs for + the main chip on the board, the STM32F401RET. Users will likely want to + write applications targeting this chip, using the ``96b_carbon`` + configuration, since it is connected to all of the breakout + I/O headers. + +- The ``96b_carbon/nrf51822`` configuration should be used for programming + the secondary nRF51822 chip. Most users will likely not develop + applications for this chip, since Zephyr already provides a + sample application that can be flashed onto the nRF51822 + to provide Bluetooth functionality to applications on the main + STM32F401RET chip. + +For instructions on how to set up the nRF51822 to develop Bluetooth +applications, see :ref:`96b_carbon_nrf51_bluetooth`. + +After you have flashed your nRF51, you can perform basic validation +of this Bluetooth setup using the instructions +:ref:`below <96b_carbon_verify_bluetooth>`. + +.. figure:: img/96b_carbon.jpg + :align: center + :alt: 96Boards Carbon + + 96Boards Carbon + +Hardware +******** + +96Boards Carbon provides the following hardware components: + +- STM32F401RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 96 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (7) +- Watchdog Timers (2) +- USART/UART (4) +- I2C (3) +- SPI (3) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- Bluetooth LE over SPI, provided by nRF51822 + +More information about STM32F401RE can be found here: + - `STM32F401RE on www.st.com`_ + - `STM32F401 reference manual`_ + +Supported Features +================== + +The Zephyr ``96b_carbon/stm32f401xe`` board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +More details about the board can be found at `96Boards website`_. + +The default configuration can be found in +:zephyr_file:`boards/96boards/carbon/96b_carbon_stm32f401xe_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PD2 +- LED2 / User2 LED = PA15 +- LED3 / BT LED = PB5 +- LED4 / Power LED = VCC + +Push buttons +------------ + +- BUTTON = BOOT0 (SW1) +- BUTTON = RST + +External Connectors +------------------- + +Low Speed Header + ++--------+-------------+----------------------+ +| PIN # | Signal Name | STM32F401 Functions | ++========+=============+======================+ +| 1 | UART2_CTS | PA0 | ++--------+-------------+----------------------+ +| 3 | UART2_TX | PA2 | ++--------+-------------+----------------------+ +| 5 | UART2_RX | PA3 | ++--------+-------------+----------------------+ +| 7 | UART2_RTS | PA1 | ++--------+-------------+----------------------+ +| 9 | GND | GND | ++--------+-------------+----------------------+ +| 11 | USB5V | USB5V | ++--------+-------------+----------------------+ +| 13 | AIN12 | PC2 | ++--------+-------------+----------------------+ +| 15 | AIN14 | PC4 | ++--------+-------------+----------------------+ +| 17 | UART6_TX | PC6 | ++--------+-------------+----------------------+ +| 19 | GPIO | PC8 | ++--------+-------------+----------------------+ +| 21 | I2C1_SCL | PB6 | ++--------+-------------+----------------------+ +| 23 | I2C1_SCA | PB7 | ++--------+-------------+----------------------+ +| 25 | I2C2_SCA | PB3 | ++--------+-------------+----------------------+ +| 27 | I2C2_SCL | PB10 | ++--------+-------------+----------------------+ +| 29 | RST_BTN | RST_BTN | ++--------+-------------+----------------------+ + ++--------+-------------+----------------------+ +| PIN # | Signal Name | STM32F401 Functions | ++========+=============+======================+ +| 2 | SPI2_SS | PB12 | ++--------+-------------+----------------------+ +| 4 | SPI2_MOSI | PB15 | ++--------+-------------+----------------------+ +| 6 | SPI2_MISO | PB14 | ++--------+-------------+----------------------+ +| 8 | SPI2_SCK | PB13 | ++--------+-------------+----------------------+ +| 10 | GND | GND | ++--------+-------------+----------------------+ +| 12 | VCC2 | VCC2 | ++--------+-------------+----------------------+ +| 14 | AIN13 | PC3 | ++--------+-------------+----------------------+ +| 16 | AIN15 | PC5 | ++--------+-------------+----------------------+ +| 18 | UART6_RX | PC7 | ++--------+-------------+----------------------+ +| 20 | GPIO | PC9 | ++--------+-------------+----------------------+ +| 22 | I2C1_SCL | PB8 | ++--------+-------------+----------------------+ +| 24 | I2C1_SDA | PB9 | ++--------+-------------+----------------------+ +| 26 | AIN10 | PC0 | ++--------+-------------+----------------------+ +| 28 | AIN11 | PC1 | ++--------+-------------+----------------------+ +| 30 | NC | NC | ++--------+-------------+----------------------+ + +More detailed information about the connectors can be found in +`96Boards IE Specification`_. + +External Clock Sources +---------------------- + +STM32F4 has two external oscillators. The frequency of the slow clock is +32.768 kHz. The frequency of the main clock is 16 MHz. + +Serial Port +----------- + +96Boards Carbon board has up to 4 U(S)ARTs. The Zephyr console output is +assigned to USART1. Default settings are 115200 8N1. + +I2C +--- + +96Boards Carbon board has up to 2 I2Cs. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB3 + +SPI +--- + +96Boards Carbon board has up to 2 SPIs. SPI1 is used for Bluetooth communication +over HCI. The default SPI mapping for Zephyr is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 + +USB +=== + +96Boards Carbon board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its mini "OTG" USB connector. +Only USB device functions are supported in Zephyr at the moment. + +- USB_DM : PA11 +- USB_DP : PA12 + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader +supports flashing via USB (DFU), UART, I2C and SPI. You can read more about +how to enable and use the ROM bootloader by checking the application +note `AN2606`_, page 109. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +Flashing an Application to 96Boards Carbon +------------------------------------------ + +Connect the micro-USB cable to the USB OTG Carbon port and to your computer. +The board should power ON. Force the board into DFU mode by keeping the BOOT0 +switch pressed while pressing and releasing the RST switch. + +Confirm that the board is in DFU mode: + +.. code-block:: console + + $ sudo dfu-util -l + dfu-util 0.8 + Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. + Copyright 2010-2014 Tormod Volden and Stefan Schmidt + This program is Free Software and has ABSOLUTELY NO WARRANTY + Please report bugs to dfu-util@lists.gnumonks.org + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" + Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" + Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" + +You should see following confirmation on your Linux host: + +.. code-block:: console + + $ dmesg + usb 1-2.1: new full-speed USB device number 14 using xhci_hcd + usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 + usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + usb 1-2.1: Product: STM32 BOOTLOADER + usb 1-2.1: Manufacturer: STMicroelectronics + usb 1-2.1: SerialNumber: 3574364C3034 + +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_carbon/stm32f401xe + :goals: build flash + +Connect the micro-USB cable to the USB UART (FTDI) port and to your computer. +Run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board 96Boards Carbon +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. +The ``-b`` option sets baud rate ignoring the value from config. + +Press the Reset button and you should see the following message in your +terminal: + +.. code-block:: console + + Hello World! arm + +.. _96b_carbon_verify_bluetooth: + +Verifying Bluetooth Functionality +--------------------------------- + +This section contains instructions for verifying basic Bluetooth +functionality on the board. For help on Zephyr applications +in general, see :ref:`build_an_application`. + +1. Flash the nRF51 with the hci_spi sample application as described in + :ref:`96b_carbon_nrf51_bluetooth`. + +#. Install the dfu-util flashing app, as described above. + +#. Build and flash the ``samples/bluetooth/ipsp`` application for + 96b_carbon. See the instructions above for how to put your board + into DFU mode if you haven't done this before: + + .. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/ipsp + :board: 96b_carbon/stm32f401xe + :goals: build flash + +#. Refer to the instructions in :ref:`bluetooth-ipsp-sample` for how + to verify functionality. + +Congratulations! Your 96Boards Carbon now has Bluetooth +connectivity. Refer to :ref:`bluetooth` for additional information on +further Bluetooth application development. + +Debugging +========= + +The ``96b_carbon/stm32f401xe`` board can be debugged by installing a 100 mil (0.1 inch) header +into the header at the bottom right hand side of the board, and +attaching an SWD debugger to the 3V3 (3.3V), GND, CLK, DIO, and RST +pins on that header. Then apply power to the 96Boards Carbon via one +of its USB connectors. You can now attach your debugger to the +STM32F401RET using an SWD scan. + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _AN2606: + https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf + +.. _96Boards website: + http://www.96boards.org/documentation + +.. _STM32F401RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f401re.html + +.. _STM32F401 reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf + +.. _96Boards IE Specification: + https://linaro.co/ie-specification diff --git a/boards/96boards/carbon/pre_dt_board.cmake b/boards/96boards/carbon/pre_dt_board.cmake new file mode 100644 index 00000000000000..2b6fc0edc8762a --- /dev/null +++ b/boards/96boards/carbon/pre_dt_board.cmake @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if("${BOARD_IDENTIFIER}" STREQUAL "/nrf51822") + # Suppress "unique_unit_address_if_enabled" to handle the following overlaps: + # - power@40000000 & clock@40000000 & nrf-mpu@40000000 + list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") +endif() diff --git a/boards/96boards/index.rst b/boards/96boards/index.rst new file mode 100644 index 00000000000000..9778649e7d92b0 --- /dev/null +++ b/boards/96boards/index.rst @@ -0,0 +1,10 @@ +.. _boards-96boards: + +96Boards +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/96b_meerkat96/96b_meerkat96-pinctrl.dtsi b/boards/96boards/meerkat96/96b_meerkat96-pinctrl.dtsi similarity index 100% rename from boards/arm/96b_meerkat96/96b_meerkat96-pinctrl.dtsi rename to boards/96boards/meerkat96/96b_meerkat96-pinctrl.dtsi diff --git a/boards/arm/96b_meerkat96/96b_meerkat96.dts b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts similarity index 100% rename from boards/arm/96b_meerkat96/96b_meerkat96.dts rename to boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts diff --git a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml new file mode 100644 index 00000000000000..39f57323369cb9 --- /dev/null +++ b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019, Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: 96b_meerkat96/mcimx7d/m4 +name: 96Boards Meerkat96 +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - shell +testing: + ignore_tags: + - net + - bluetooth +vendor: novtech diff --git a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig new file mode 100644 index 00000000000000..90dfb85138a020 --- /dev/null +++ b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2019, Linaro Ltd. +# +# SPDX-License-Identifier: Apache-2.0 +# + +# enable uart driver +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# pinctrl +CONFIG_PINCTRL=y + +CONFIG_XIP=y diff --git a/boards/96boards/meerkat96/Kconfig.96b_meerkat96 b/boards/96boards/meerkat96/Kconfig.96b_meerkat96 new file mode 100644 index 00000000000000..9c5ce6864968d6 --- /dev/null +++ b/boards/96boards/meerkat96/Kconfig.96b_meerkat96 @@ -0,0 +1,7 @@ +# Copyright (c) 2019, Linaro Ltd. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_MEERKAT96 + select SOC_PART_NUMBER_MCIMX7D5EVM10SC + select SOC_MCIMX7D_M4 if BOARD_96B_MEERKAT96_MCIMX7D_M4 diff --git a/boards/96boards/meerkat96/Kconfig.defconfig b/boards/96boards/meerkat96/Kconfig.defconfig new file mode 100644 index 00000000000000..a401b7ecb89bc8 --- /dev/null +++ b/boards/96boards/meerkat96/Kconfig.defconfig @@ -0,0 +1,15 @@ +# 96Boards Meerkat96 board + +# Copyright (c) 2019, Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_MEERKAT96 + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_96B_MEERKAT96 diff --git a/boards/96boards/meerkat96/board.yml b/boards/96boards/meerkat96/board.yml new file mode 100644 index 00000000000000..48d60ae68884d5 --- /dev/null +++ b/boards/96boards/meerkat96/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_meerkat96 + vendor: 96boards + socs: + - name: mcimx7d diff --git a/boards/arm/96b_meerkat96/doc/img/96b_meerkat96.jpg b/boards/96boards/meerkat96/doc/img/96b_meerkat96.jpg similarity index 100% rename from boards/arm/96b_meerkat96/doc/img/96b_meerkat96.jpg rename to boards/96boards/meerkat96/doc/img/96b_meerkat96.jpg diff --git a/boards/96boards/meerkat96/doc/index.rst b/boards/96boards/meerkat96/doc/index.rst new file mode 100644 index 00000000000000..c76229de75b4ad --- /dev/null +++ b/boards/96boards/meerkat96/doc/index.rst @@ -0,0 +1,325 @@ +.. _96b_meerkat96: + +96Boards Meerkat96 +################## + +Overview +******** + +96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor, +composed of a dual Cortex®-A7 and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-M4 core. + +- Board features: + + - RAM: 512 Mbyte + - Storage: + + - microSD Socket + - Wireless: + + - WiFi: 2.4GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 (BR/EDR) + - USB: + + - Host - 2x type A + - OTG: - 1x type micro-B + - HDMI + - Connectors: + + - 40-Pin Low Speed Header + - 60-Pin High Speed Header + - LEDs: + + - 4x Green user LEDs + - 1x Blue Bluetooth LED + - 1x Yellow WiFi LED + +.. image:: img/96b_meerkat96.jpg + :align: center + :alt: 96Boards Meerkat96 + +More information about the board can be found at the +`96Boards website`_. + +Hardware +******** + +The i.MX7 SoC provides the following hardware capabilities: + +- Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core + +- Memory + + - External DDR memory up to 1 Gbyte + - Internal RAM -> A7: 256KB SRAM + - Internal RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + +- Display + + - RGB 1920x1080x24bpp + - 4-wire Resistive touch + +- Multimedia + + - 1x Camera Parallel Interface + - 1x Analog Audio Line in (Stereo) + - 1x Analog Audio Mic in (Mono) + - 1x Analog Audio Headphone out (Stereo) + +- Connectivity + + - USB 2.0 OTG (High Speed) + - USB 2.0 host (High Speed) + - 10/100 Mbit/s Ethernet PHY + - 4x I2C + - 4x SPI + - 7x UART + - 1x IrDA + - 20x PWM + - Up to 125 GPIO + - 4x Analog Input (12 Bit) + - 2x SDIO/SD/MMC (8 Bit) + - 2x CAN + +More information about the i.MX7 SoC can be found here: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Dual Datasheet`_ +- `i.MX 7 Dual Reference Manual`_ + +Supported Features +================== + +The Zephyr 96b_meerkat96 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +96Boards Meerkat96 board was tested with the following pinmux controller +configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART_1 RXD | UART1_TXD | UART Console | ++---------------+-----------------+---------------------------+ +| UART_1 TXD | UART1_RXD | UART Console | ++---------------+-----------------+---------------------------+ +| LED_R1 | GPIO1_IO04 | LED0 | ++---------------+-----------------+---------------------------+ +| LED_R2 | GPIO1_IO05 | LED1 | ++---------------+-----------------+---------------------------+ +| LED_R3 | GPIO1_IO06 | LED2 | ++---------------+-----------------+---------------------------+ +| LED_R4 | GPIO1_IO07 | LED3 | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7D SoC has seven UARTs. UART_1 is configured for the console and +the remaining are not used/tested. + +Programming and Debugging +************************* + +The 96Boards Meerkat96 board doesn't have QSPI flash for the M4 and it needs +to be started by the A7 core. The A7 core is responsible to load the M4 binary +application into the RAM, put the M4 in reset, set the M4 Program Counter and +Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at +bootloader level or after the Linux system has booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 7 Dual Reference Manual`_ (section 2.1.2 and 2.1.3), and the +`Toradex Wiki`_. + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from +A7 using u-boot. + +Copy the compiled zephyr.bin to the first FAT partition of the SD card and +plug into the board. Power it up and stop the u-boot execution. +Set the u-boot environment variables and run the zephyr.bin from the +appropriated memory configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + +Debugging +========= + +96Boards Meerkat96 board can be debugged by connecting an external JLink +JTAG debugger to the J4 debug connector. Then download and install +`J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. + +To run Zephyr Binary using J-Link create the following script in order to +get the Program Counter and Stack Pointer from zephyr.bin. + +get-pc-sp.sh: +.. code-block:: console + + #!/bin/sh + + firmware=$1 + + pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') + sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') + + echo pc=$pc + echo sp=$sp + + +Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` +.. code-block:: console + + pc=00900f01 + sp=00905020 + +Plug in the J-Link into the board and PC and run the J-Link command line tool: + +.. code-block:: console + + /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript + +The following steps are necessary to run the zephyr.bin: + +1. Put the M4 core in reset +2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) +3. Set PC (Program Counter) +4. Set SP (Stack Pointer) +5. Get the M4 core out of reset + +Issue the following commands inside J-Link commander: + +.. code-block:: console + + w4 0x3039000C 0xAC + loadfile zephyr.bin,0x00900000 + w4 0x00180000 00900f01 + w4 0x00180004 00905020 + w4 0x3039000C 0xAA + +With these mechanisms, applications for the ``96b_meerkat96`` board +configuration can be built and debugged in the usual way (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _96Boards website: + https://www.96boards.org/product/imx7-96/ + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Dual Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf + +.. _i.MX 7 Dual Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7DRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/96b_neonkey/96b_neonkey.dts b/boards/96boards/neonkey/96b_neonkey.dts similarity index 100% rename from boards/arm/96b_neonkey/96b_neonkey.dts rename to boards/96boards/neonkey/96b_neonkey.dts diff --git a/boards/arm/96b_neonkey/96b_neonkey.yaml b/boards/96boards/neonkey/96b_neonkey.yaml similarity index 100% rename from boards/arm/96b_neonkey/96b_neonkey.yaml rename to boards/96boards/neonkey/96b_neonkey.yaml diff --git a/boards/arm/96b_neonkey/96b_neonkey_defconfig b/boards/96boards/neonkey/96b_neonkey_defconfig similarity index 85% rename from boards/arm/96b_neonkey/96b_neonkey_defconfig rename to boards/96boards/neonkey/96b_neonkey_defconfig index 1b51c0cc14ad3c..82ee7285d52d8a 100644 --- a/boards/arm/96b_neonkey/96b_neonkey_defconfig +++ b/boards/96boards/neonkey/96b_neonkey_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/neonkey/Kconfig.96b_neonkey b/boards/96boards/neonkey/Kconfig.96b_neonkey new file mode 100644 index 00000000000000..63d01784688c71 --- /dev/null +++ b/boards/96boards/neonkey/Kconfig.96b_neonkey @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_NEONKEY + select SOC_STM32F411XE diff --git a/boards/96boards/neonkey/Kconfig.defconfig b/boards/96boards/neonkey/Kconfig.defconfig new file mode 100644 index 00000000000000..ac39b66107ec74 --- /dev/null +++ b/boards/96boards/neonkey/Kconfig.defconfig @@ -0,0 +1,12 @@ +# 96Boards Neonkey Board Configuration + +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_NEONKEY + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_96B_NEONKEY diff --git a/boards/96boards/neonkey/board.yml b/boards/96boards/neonkey/board.yml new file mode 100644 index 00000000000000..214cdc883bb09e --- /dev/null +++ b/boards/96boards/neonkey/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_neonkey + vendor: 96boards + socs: + - name: stm32f411xe diff --git a/boards/arm/96b_neonkey/doc/img/96b_neonkey.jpg b/boards/96boards/neonkey/doc/img/96b_neonkey.jpg similarity index 100% rename from boards/arm/96b_neonkey/doc/img/96b_neonkey.jpg rename to boards/96boards/neonkey/doc/img/96b_neonkey.jpg diff --git a/boards/96boards/neonkey/doc/index.rst b/boards/96boards/neonkey/doc/index.rst new file mode 100644 index 00000000000000..96308784941cc5 --- /dev/null +++ b/boards/96boards/neonkey/doc/index.rst @@ -0,0 +1,232 @@ +.. _96b_neonkey: + +96Boards Neonkey +################ + +Overview +******** + +96Boards Neonkey board is based on the STMicroelectronics STM32F411CE +Cortex M4 CPU. + +.. figure:: img/96b_neonkey.jpg + :align: center + :alt: 96Boards Neonkey + + 96Boards Neonkey + +This board acts as a sensor hub platform for all 96Boards compliant +family products. It can also be used as a standalone board. + +Hardware +******** + +96Boards Neonkey provides the following hardware components: + +- STM32F411CE in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 84 MHz max CPU frequency +- 1.8V work voltage +- 512 KB Flash +- 128 KB SRAM +- On board sensors: + + - Temperature/Humidity: SI7034-A10 + - Pressure: BMP280 + - ALS/Proximity: RPR-0521RS + - Geomagnetic: BMM150 + - Accelerometer/Gyroscope: BMI160 + - AMR Hall sensor: MRMS501A + - Microphone: SPK0415HM4H-B + +- 4 User LEDs +- 15 General purpose LEDs +- GPIO with external interrupt capability +- I2C (3) +- SPI (1) +- I2S (1) + +Supported Features +================== + +The Zephyr 96b_neonkey board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +More details about the board can be found at `96Boards website`_. + +The default board configuration can be found in +:zephyr_file:`boards/96boards/neonkey/96b_neonkey_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PB12 +- LED2 / User2 LED = PB13 +- LED3 / User3 LED = PB14 +- LED4 / User4 LED = PB15 + +Push buttons +------------ + +- BUTTON = RST (SW1) +- BUTTON = USR (SW2) + +System Clock +============ + +96Boards Neonkey can be driven by an internal oscillator as well as the main +PLL clock. By default System clock is sourced by PLL clock at 84MHz, driven +by internal oscillator. + +Serial Port +=========== + +On 96Boards Neonkey Zephyr console output is assigned to USART1. +Default settings are 115200 8N1. + +I2C +--- + +96Boards Neonkey board has up to 3 I2Cs. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB3 +- I2C3_SCL : PA8 +- I2C3_SCL : PB4 + +SPI +--- + +96Boards Neonkey board has one SPI. The default SPI mapping for Zephyr is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 + +Programming and Debugging +************************* + +Building +======== + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_neonkey + :goals: build + +Flashing +======== + +96Boards Neonkey can be flashed by two methods, one using the ROM +bootloader and another using the SWD debug port (which requires additional +hardware). + +Using ROM bootloader: +--------------------- + +ROM bootloader can be triggered by the following pattern: + +1. Connect BOOT0 to VDD (link JTAG pins 1 and 5 on P4 header) +2. Press and hold the USR button +3. Press and release the RST button + +More detailed information on activating the ROM bootloader can be found in +Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing +via UART, I2C and SPI protocols. + +For flashing, `stm32flash`_ command line utility can be used. The following +command will flash the ``zephyr.bin`` binary to the Neonkey board using UART +and starts its execution: + +.. code-block:: console + + $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyS0 + +.. note:: + The above command assumes that Neonkey board is connected to + serial port ``/dev/ttyS0``. + +Using SWD debugger: +------------------- + +For flashing via SWD debug port, 0.1" male header must be soldered at P4 +header available at the bottom of the board, near RST button. + +Use the `Black Magic Debug Probe`_ as an SWD programmer, which can +be connected to the P4 header using its flying leads and its 20 Pin +JTAG Adapter Board Kit. When plugged into your host PC, the Black +Magic Debug Probe enumerates as a USB serial device as documented on +its `Getting started page`_. + +It also uses the GDB binary provided with the Zephyr SDK, +``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC +ARM Embedded, can be used as well. + +.. code-block:: console + + $ arm-zephyr-eabi-gdb -q zephyr.elf + (gdb) target extended-remote /dev/ttyACM0 + Remote debugging using /dev/ttyACM0 + (gdb) monitor swdp_scan + Target voltage: 1.8V + Available Targets: + No. Att Driver + 1 STM32F4xx + (gdb) attach 1 + Attaching to Remote target + 0x080005d0 in ?? () + (gdb) load + +Debugging +========= + +After flashing 96Boards Neonkey, it can be debugged using the same +GDB instance. To reattach, just follow the same steps above, till +"attach 1". You can then debug as usual with GDB. In particular, type +"run" at the GDB prompt to restart the program you've flashed. + +References +********** + +.. _96Boards website: + https://www.96boards.org/product/neonkey/ + +.. _AN2606: + https://www.st.com/resource/en/application_note/cd00167594.pdf + +.. _stm32flash: + https://sourceforge.net/p/stm32flash/wiki/Home/ + +.. _Black Magic Debug Probe: + https://github.com/blacksphere/blackmagic/wiki + +.. _Getting started page: + https://github.com/blacksphere/blackmagic/wiki/Getting-Started diff --git a/boards/arm/96b_nitrogen/96b_lscon.dtsi b/boards/96boards/nitrogen/96b_lscon.dtsi similarity index 100% rename from boards/arm/96b_nitrogen/96b_lscon.dtsi rename to boards/96boards/nitrogen/96b_lscon.dtsi diff --git a/boards/arm/96b_nitrogen/96b_nitrogen-pinctrl.dtsi b/boards/96boards/nitrogen/96b_nitrogen-pinctrl.dtsi similarity index 100% rename from boards/arm/96b_nitrogen/96b_nitrogen-pinctrl.dtsi rename to boards/96boards/nitrogen/96b_nitrogen-pinctrl.dtsi diff --git a/boards/arm/96b_nitrogen/96b_nitrogen.dts b/boards/96boards/nitrogen/96b_nitrogen.dts similarity index 100% rename from boards/arm/96b_nitrogen/96b_nitrogen.dts rename to boards/96boards/nitrogen/96b_nitrogen.dts diff --git a/boards/arm/96b_nitrogen/96b_nitrogen.yaml b/boards/96boards/nitrogen/96b_nitrogen.yaml similarity index 100% rename from boards/arm/96b_nitrogen/96b_nitrogen.yaml rename to boards/96boards/nitrogen/96b_nitrogen.yaml diff --git a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig b/boards/96boards/nitrogen/96b_nitrogen_defconfig similarity index 77% rename from boards/arm/96b_nitrogen/96b_nitrogen_defconfig rename to boards/96boards/nitrogen/96b_nitrogen_defconfig index b8565973eb1a99..7167aca850a04d 100644 --- a/boards/arm/96b_nitrogen/96b_nitrogen_defconfig +++ b/boards/96boards/nitrogen/96b_nitrogen_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/nitrogen/Kconfig.96b_nitrogen b/boards/96boards/nitrogen/Kconfig.96b_nitrogen new file mode 100644 index 00000000000000..7ae2b0710fbc12 --- /dev/null +++ b/boards/96boards/nitrogen/Kconfig.96b_nitrogen @@ -0,0 +1,7 @@ +# 96Boards NITROGEN board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_NITROGEN + select SOC_NRF52832_QFAA diff --git a/boards/96boards/nitrogen/Kconfig.defconfig b/boards/96boards/nitrogen/Kconfig.defconfig new file mode 100644 index 00000000000000..c1686a82539c81 --- /dev/null +++ b/boards/96boards/nitrogen/Kconfig.defconfig @@ -0,0 +1,11 @@ +# 96Boards NITROGEN board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_NITROGEN + +config BT_CTLR + default BT + +endif # BOARD_96B_NITROGEN diff --git a/boards/arm/96b_nitrogen/board.cmake b/boards/96boards/nitrogen/board.cmake similarity index 100% rename from boards/arm/96b_nitrogen/board.cmake rename to boards/96boards/nitrogen/board.cmake diff --git a/boards/96boards/nitrogen/board.yml b/boards/96boards/nitrogen/board.yml new file mode 100644 index 00000000000000..279d2c63a66c98 --- /dev/null +++ b/boards/96boards/nitrogen/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_nitrogen + vendor: 96boards + socs: + - name: nrf52832 diff --git a/boards/arm/96b_nitrogen/doc/img/96b_nitrogen.jpg b/boards/96boards/nitrogen/doc/img/96b_nitrogen.jpg similarity index 100% rename from boards/arm/96b_nitrogen/doc/img/96b_nitrogen.jpg rename to boards/96boards/nitrogen/doc/img/96b_nitrogen.jpg diff --git a/boards/96boards/nitrogen/doc/index.rst b/boards/96boards/nitrogen/doc/index.rst new file mode 100644 index 00000000000000..952f11237bfeb5 --- /dev/null +++ b/boards/96boards/nitrogen/doc/index.rst @@ -0,0 +1,329 @@ +.. _96b_nitrogen_board: + +96Boards Nitrogen +################# + +Overview +******** + +The 96Boards Nitrogen hardware provides support for the Nordic Semiconductor +nRF52832 ARM Cortex-M4F CPU. + +.. figure:: img/96b_nitrogen.jpg + :align: center + :alt: 96Boards Nitrogen + + 96Boards Nitrogen + +More information about the board can be found at the `seeed BLE Nitrogen`_ +website. The `Nordic Semiconductor Infocenter`_ contains the processor's +information and the datasheet. + +Hardware +******** + +96Boards Nitrogen provides the following hardware components: + +- nRF52832 microcontroller with 512kB Flash, 64kB RAM +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Bluetooth LE +- NFC +- LPC11U35 on board SWD debugger + + - SWD debugger firmware + - USB to UART + - Drag and Drop firmware upgrade + +- 7 LEDs + + - USR1, BT, PWR, CDC, DAP, MSD, Battery charge + +- SWD debug connectors + + - nRF52832 SWD connector + - nRF52832 Uart connector + +- On board chip antenna +- 1.8V work voltage +- 2x20pin 2.0mm pitch Low speed connector + +Supported Features +================== + +The Zephyr 96b_nitrogen board configuration supports the following hardware +features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vectored interrupt controller | ++-----------+------------+--------------------------------------+ +| RTC | on-chip | system clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+--------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+--------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+--------------------------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+--------------------------------------+ +| RTT | on-chip | console | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ for a complete list of nRF52-based +board hardware features. + +The default configuration can be found in +:zephyr_file:`boards/96boards/nitrogen/96b_nitrogen_defconfig` + +Pin Mapping +=========== + +LED +--- + +- LED1 / User LED (green) = P0.29 +- LED2 / BT LED (blue) = P0.28 + +Push buttons +------------ + +- BUTTON = SW1 = P0.27 + +External Connectors +------------------- + +Low Speed Header + ++--------+-------------+----------------------+ +| PIN # | Signal Name | nRF52832 Functions | ++========+=============+======================+ +| 1 | GND | GND | ++--------+-------------+----------------------+ +| 3 | UART CTS | P.014 / TRACEDATA[3] | ++--------+-------------+----------------------+ +| 5 | UART TX | P0.13 | ++--------+-------------+----------------------+ +| 7 | UART RX | P0.15 / TRACEDATA[2] | ++--------+-------------+----------------------+ +| 9 | UART RTS | P0.12 | ++--------+-------------+----------------------+ +| 11 | UART TX | P0.13 | ++--------+-------------+----------------------+ +| 13 | UART RX | P0.15 / TRACEDATA[2] | ++--------+-------------+----------------------+ +| 15 | P0.22 | P0.22 | ++--------+-------------+----------------------+ +| 17 | P0.20 | P0.20 | ++--------+-------------+----------------------+ +| 19 | N/A | N/A | ++--------+-------------+----------------------+ +| 21 | N/A | N/A | ++--------+-------------+----------------------+ +| 23 | P0.02 | P0.02 | ++--------+-------------+----------------------+ +| 25 | P0.04 | P0.04 | ++--------+-------------+----------------------+ +| 27 | P0.06 | P0.06 | ++--------+-------------+----------------------+ +| 29 | P0.08 | P0.08 | ++--------+-------------+----------------------+ +| 31 | P0.16 | P0.16 | ++--------+-------------+----------------------+ +| 33 | P0.18 | P0.18 | ++--------+-------------+----------------------+ +| 35 | VCC | | ++--------+-------------+----------------------+ +| 37 | USB5V | | ++--------+-------------+----------------------+ +| 39 | GND | GND | ++--------+-------------+----------------------+ + ++--------+-------------+----------------------+ +| PIN # | Signal Name | nRF52832 Functions | ++========+=============+======================+ +| 2 | GND | GND | ++--------+-------------+----------------------+ +| 4 | PWR BTN | | ++--------+-------------+----------------------+ +| 6 | RST BTN | P0.21 / RESET | ++--------+-------------+----------------------+ +| 8 | P0.26 | P0.26 | ++--------+-------------+----------------------+ +| 10 | P0.25 | P0.25 | ++--------+-------------+----------------------+ +| 12 | P0.24 | P0.24 | ++--------+-------------+----------------------+ +| 14 | P0.23 | P0.23 | ++--------+-------------+----------------------+ +| 16 | N/A | N/A | ++--------+-------------+----------------------+ +| 18 | N/A | PC7 | ++--------+-------------+----------------------+ +| 20 | N/A | PC9 | ++--------+-------------+----------------------+ +| 22 | N/A | PB8 | ++--------+-------------+----------------------+ +| 24 | P0.03 | P0.03 | ++--------+-------------+----------------------+ +| 26 | P0.05 | P0.05 | ++--------+-------------+----------------------+ +| 28 | P0.07 | P0.07 | ++--------+-------------+----------------------+ +| 30 | P0.11 | P0.11 | ++--------+-------------+----------------------+ +| 32 | P0.17 | P0.17 | ++--------+-------------+----------------------+ +| 34 | P0.19 | P0.19 | ++--------+-------------+----------------------+ +| 36 | NC | | ++--------+-------------+----------------------+ +| 38 | NC | | ++--------+-------------+----------------------+ +| 40 | GND | GND | ++--------+-------------+----------------------+ + +More detailed information about the connectors can be found in +`96Boards IE Specification`_. + +System Clock +============ + +nRF52 has two external oscillators. The frequency of the slow clock is +32.768 kHz. The frequency of the main clock is 32 MHz. + +Serial Port +----------- + +96Boards Nitrogen has one UART, which is used as Zephyr console. +Default settings is 115200 8N1. + +I2C +--- + +96Boards Nitrogen has one I2C. The default I2C mapping for Zephyr is: + +- I2C0_SCL : P0.22 +- I2C0_SDA : P0.20 + +SPI +--- + +96Boards Nitrogen has one SPI. The default SPI mapping for Zephyr is: + +- SPI0_NSS : P0.24 +- SPI0_SCK : P0.26 +- SPI0_MISO : P0.25 +- SPI0_MOSI : P0.23 + +Flashing Zephyr onto 96Boards Nitrogen +************************************** + +The 96Boards Nitrogen board can be flashed via the `CMSIS DAP`_ interface, +which is provided by the micro USB interface to the LPC11U35 chip. + +Using the CMSIS-DAP interface, the board can be flashed via the USB storage +interface (drag-and-drop) and also via `pyOCD`_. + +To use ``pyOCD``, install the :ref:`pyocd-debug-host-tools` and make sure they +are in your search path. + +Common Errors +============= + +No connected boards +------------------- + +If you don't use sudo when invoking pyocd-flashtool, you might get any of the +following errors: + +.. code-block:: console + + No available boards are connected + +.. code-block:: console + + No connected boards + +.. code-block:: console + + Error: There is no board connected. + +To fix the permission issue, simply add the following udev rule for the +NXP LPC1768 interface: + +.. code-block:: console + + $ echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules + +Finally, unplug and plug the board again. + +ValueError: The device has no langid +------------------------------------ + +As described by `pyOCD issue 259`_, you might get the +:code:`ValueError: The device has no langid` error when not running +pyOCD as root (e.g. sudo). + +To fix the above error, add the udev rule shown in the previous section +and install a more recent version of pyOCD. + +Flashing an Application to 96Boards Nitrogen +============================================ + +Here is an example for the :ref:`hello_world` application. This +requires installing the :ref:`pyocd-debug-host-tools`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_nitrogen + :goals: build flash + +Run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board 96Boards Nitrogen +can be found. For example, under Linux, :code:`/dev/ttyACM0`. +The ``-b`` option sets baud rate ignoring the value from config. + +Press the Reset button and you should see the following message in your +terminal: + +.. code-block:: console + + Hello World! arm + +Debugging with GDB +================== + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. This also requires pyOCD. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_nitrogen + :maybe-skip-config: + :goals: debug + +.. _pyOCD: + https://github.com/mbedmicro/pyOCD + +.. _CMSIS DAP: + https://developer.mbed.org/handbook/CMSIS-DAP + +.. _Nordic Semiconductor Infocenter: + http://infocenter.nordicsemi.com/ + +.. _seeed BLE Nitrogen: + http://wiki.seeed.cc/BLE_Nitrogen/ + +.. _pyOCD issue 259: + https://github.com/mbedmicro/pyOCD/issues/259 + +.. _96Boards IE Specification: + https://linaro.co/ie-specification diff --git a/boards/arm/96b_nitrogen/pre_dt_board.cmake b/boards/96boards/nitrogen/pre_dt_board.cmake similarity index 100% rename from boards/arm/96b_nitrogen/pre_dt_board.cmake rename to boards/96boards/nitrogen/pre_dt_board.cmake diff --git a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.dts b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.dts rename to boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.dts diff --git a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.yaml b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez.yaml rename to boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml diff --git a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig similarity index 84% rename from boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig rename to boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig index a9e0141c1258c9..c729b83e3d0506 100644 --- a/boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig +++ b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F446XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez b/boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez new file mode 100644 index 00000000000000..aa4bd5b97bb341 --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/Kconfig.96b_stm32_sensor_mez @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_STM32_SENSOR_MEZ + select SOC_STM32F446XX diff --git a/boards/96boards/stm32_sensor_mez/Kconfig.defconfig b/boards/96boards/stm32_sensor_mez/Kconfig.defconfig new file mode 100644 index 00000000000000..f6678ae9110721 --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/Kconfig.defconfig @@ -0,0 +1,12 @@ +# 96Boards STM32 Sensor Mezzanine board configuration + +# Copyright (c) 2018 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_STM32_SENSOR_MEZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_96B_STM32_SENSOR_MEZ diff --git a/boards/arm/96b_stm32_sensor_mez/board.cmake b/boards/96boards/stm32_sensor_mez/board.cmake similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/board.cmake rename to boards/96boards/stm32_sensor_mez/board.cmake diff --git a/boards/96boards/stm32_sensor_mez/board.yml b/boards/96boards/stm32_sensor_mez/board.yml new file mode 100644 index 00000000000000..e410dcc9e65e8f --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_stm32_sensor_mez + vendor: st + socs: + - name: stm32f446xx diff --git a/boards/arm/96b_stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg b/boards/96boards/stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg rename to boards/96boards/stm32_sensor_mez/doc/img/96b_stm32_sensor_mez.jpg diff --git a/boards/96boards/stm32_sensor_mez/doc/index.rst b/boards/96boards/stm32_sensor_mez/doc/index.rst new file mode 100644 index 00000000000000..350d4720a8018a --- /dev/null +++ b/boards/96boards/stm32_sensor_mez/doc/index.rst @@ -0,0 +1,247 @@ +.. _96b_stm32_sensor_mez: + +96Boards STM32 Sensor Mezzanine +############################### + +Overview +******** + +96Boards STM32 Sensor Mezzanine is based on the ST Microelectronics +STM32F446VE Cortex M4 CPU. + +This board acts as a mezzanine platform for all 96Boards CE compliant +boards. It can also be used as a standalone board. + +.. figure:: img/96b_stm32_sensor_mez.jpg + :align: center + :alt: 96Boards STM32 Sensor Mezzanine + + 96Boards STM32 Sensor Mezzanine + +Hardware +******** + +96Boards STM32 Sensor Mezzanine provides the following hardware components: + +- STM32F446VE in LQFP100 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 180 MHz max CPU frequency +- 1.8V work voltage +- 512 KB Flash +- 128 KB SRAM +- On board sensors: + + - Temperature/Pressure: STMicro LPS22HB + - Accelerometer/Gyroscope: STMicro LSM6DS3H + - Magnetometer: STMicro LIS3MDL + - Microphone: STMicro MP34DT01 + +- 3User LEDs +- GPIO with external interrupt capability +- UART +- I2C (2) +- SPI (3) +- I2S (1) + +Supported Features +================== + +The Zephyr 96b_stm32_sensor_mez board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ + +The default board configuration can be found in +:zephyr_file:`boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez_defconfig` + +Connections and IOs +=================== + +LED +--- + +- LED1 / User1 LED = PD10 +- LED2 / User2 LED = PD11 +- LED3 / User3 LED = PD12 + +Push buttons +------------ + +- BUTTON = RST (BT1) +- BUTTON = USR (BT2) + +System Clock +============ + +96Boards STM32 Sensor Mezzanine can be driven by an internal oscillator as +well as the main PLL clock. In default board configuration, the 16MHz external +oscillator is used to drive the main PLL clock to generate a System Clock +(SYSCLK) at 84MHz. On the bus side, AHB/APB2 clocks runs at 84MHz, while APB1 +clock runs at 42MHz. + +Serial Port +=========== + +On 96Boards STM32 Sensor Mezzanine, Zephyr console output is assigned to UART4 +exposed via on-board Micro USB connector. Default settings are 115200 8N1. + +The default USART mappings for the remaining ones are: + +- USART1: Connected to AP via UART0 on the 96Boards Low-Speed Header. + - TX: PA9 + - RX: PA10 + +- USART2: Connected to D0(RX) and D1(TX) on the Arduino Header. + - TX: PD5 + - RX: PD6 + +- USART3: Broken out to Grove connector J10. + - TX: PD8 + - RX: PD9 + +I2C +--- + +96Boards STM32 Sensor Mezzanine board has up to 3 I2Cs. The default I2C +mapping is: + +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PC12 + +I2C2 goes to the Groove connectors and can be used to attach external sensors. + +SPI +--- +96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode +as the communication bus with the AP. SPI2 is used in master mode to control +the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5. +The default SPI mapping is: + +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB9 +- SPI2_SCK : PD3 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- SPI4_NSS : PE11 +- SPI4_SCK : PE12 +- SPI4_MISO : PE13 +- SPI4_MOSI : PE14 + +PWM +--- +96Boards STM32 Sensor Mezzanine board exposes 6 PWM channels on the Arduino +connector. The default PWM mapping is: + +- PWM3_CH1 : PB4 : D9 +- PWM3_CH3 : PC8 : D3 +- PWM4_CH3 : PD14 : D6 +- PWM4_CH4 : PD15 : D5 +- PWM9_CH1 : PE5 : D12 +- PWM9_CH2 : PE6 : D11 + +I2S +--- + +96Boards STM32 Sensor Mezzanine board exposes 1 I2S port which is connected +to the on-board ST MP34DT01 DMIC. The default I2S mapping is: + +- I2S2_SD : PC1 +- I2S2_CK : PC7 + +Programming and Debugging +************************* + +Building +======== + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_stm32_sensor_mez + :goals: build + +Flashing +======== + +96Boards STM32 Sensor Mezzanine board includes an ST-LINK/V2-1 embedded +debug tool interface. This interface is supported by the openocd version +included in the Zephyr SDK. + +Flashing an application to 96Boards STM32 Sensor Mezzanine +---------------------------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine +board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_stm32_sensor_mez + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! 96b_stm32_sensor_mez + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: 96b_stm32_sensor_mez + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _96Boards STM32 Sensor Mezzanine website: + https://www.96boards.org/documentation/mezzanine/stm32/ + +.. _STM32F446VE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f446ve.html + +.. _STM32F446 reference manual: + https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/96b_stm32_sensor_mez/support/openocd.cfg b/boards/96boards/stm32_sensor_mez/support/openocd.cfg similarity index 100% rename from boards/arm/96b_stm32_sensor_mez/support/openocd.cfg rename to boards/96boards/stm32_sensor_mez/support/openocd.cfg diff --git a/boards/arm/96b_wistrio/96b_lscon.dtsi b/boards/96boards/wistrio/96b_lscon.dtsi similarity index 100% rename from boards/arm/96b_wistrio/96b_lscon.dtsi rename to boards/96boards/wistrio/96b_lscon.dtsi diff --git a/boards/arm/96b_wistrio/96b_wistrio.dts b/boards/96boards/wistrio/96b_wistrio.dts similarity index 100% rename from boards/arm/96b_wistrio/96b_wistrio.dts rename to boards/96boards/wistrio/96b_wistrio.dts diff --git a/boards/arm/96b_wistrio/96b_wistrio.yaml b/boards/96boards/wistrio/96b_wistrio.yaml similarity index 100% rename from boards/arm/96b_wistrio/96b_wistrio.yaml rename to boards/96boards/wistrio/96b_wistrio.yaml diff --git a/boards/arm/96b_wistrio/96b_wistrio_defconfig b/boards/96boards/wistrio/96b_wistrio_defconfig similarity index 83% rename from boards/arm/96b_wistrio/96b_wistrio_defconfig rename to boards/96boards/wistrio/96b_wistrio_defconfig index 9520805e917d81..23d51e28afa2de 100644 --- a/boards/arm/96b_wistrio/96b_wistrio_defconfig +++ b/boards/96boards/wistrio/96b_wistrio_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32L1X=y -CONFIG_SOC_STM32L151XBA=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/96b_wistrio/CMakeLists.txt b/boards/96boards/wistrio/CMakeLists.txt similarity index 100% rename from boards/arm/96b_wistrio/CMakeLists.txt rename to boards/96boards/wistrio/CMakeLists.txt diff --git a/boards/96boards/wistrio/Kconfig.96b_wistrio b/boards/96boards/wistrio/Kconfig.96b_wistrio new file mode 100644 index 00000000000000..f66f9ba9b5fd94 --- /dev/null +++ b/boards/96boards/wistrio/Kconfig.96b_wistrio @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_96B_WISTRIO + select SOC_STM32L151XBA diff --git a/boards/96boards/wistrio/Kconfig.defconfig b/boards/96boards/wistrio/Kconfig.defconfig new file mode 100644 index 00000000000000..751ed00ab7e8c9 --- /dev/null +++ b/boards/96boards/wistrio/Kconfig.defconfig @@ -0,0 +1,11 @@ +# 96boards WisTrio board configuration + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_96B_WISTRIO + +config REGULATOR + default y if LORA + +endif # BOARD_96B_WISTRIO diff --git a/boards/arm/96b_wistrio/board.cmake b/boards/96boards/wistrio/board.cmake similarity index 100% rename from boards/arm/96b_wistrio/board.cmake rename to boards/96boards/wistrio/board.cmake diff --git a/boards/96boards/wistrio/board.yml b/boards/96boards/wistrio/board.yml new file mode 100644 index 00000000000000..508c590a6b5ab0 --- /dev/null +++ b/boards/96boards/wistrio/board.yml @@ -0,0 +1,5 @@ +board: + name: 96b_wistrio + vendor: 96boards + socs: + - name: stm32l151xba diff --git a/boards/arm/96b_wistrio/doc/96b_wistrio.rst b/boards/96boards/wistrio/doc/96b_wistrio.rst similarity index 97% rename from boards/arm/96b_wistrio/doc/96b_wistrio.rst rename to boards/96boards/wistrio/doc/96b_wistrio.rst index 58bb3ee18b8812..14f93e6bae116b 100644 --- a/boards/arm/96b_wistrio/doc/96b_wistrio.rst +++ b/boards/96boards/wistrio/doc/96b_wistrio.rst @@ -70,9 +70,8 @@ features: | EEPROM | on-chip | eeprom | +-----------+------------+-------------------------------------+ -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_wistrio/96b_wistrio_defconfig`` +The default board configuration can be found in +:zephyr_file:`boards/96boards/wistrio/96b_wistrio_defconfig` Connections and IOs =================== diff --git a/boards/arm/96b_wistrio/doc/img/96b-wistrio.jpg b/boards/96boards/wistrio/doc/img/96b-wistrio.jpg similarity index 100% rename from boards/arm/96b_wistrio/doc/img/96b-wistrio.jpg rename to boards/96boards/wistrio/doc/img/96b-wistrio.jpg diff --git a/boards/arm/96b_wistrio/dts/bindings/qorvo,rfsw8001.yaml b/boards/96boards/wistrio/dts/bindings/qorvo,rfsw8001.yaml similarity index 100% rename from boards/arm/96b_wistrio/dts/bindings/qorvo,rfsw8001.yaml rename to boards/96boards/wistrio/dts/bindings/qorvo,rfsw8001.yaml diff --git a/boards/arm/96b_wistrio/rf.c b/boards/96boards/wistrio/rf.c similarity index 100% rename from boards/arm/96b_wistrio/rf.c rename to boards/96boards/wistrio/rf.c diff --git a/boards/Kconfig b/boards/Kconfig index f56c2cab04ef9a..9268b7c0c9dde6 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -2,6 +2,8 @@ config BOARD string + # When using hw model v2, then the board is inherited from CMake. + default "$(BOARD)" if "$(HWM_SCHEME)" = "v2" help This option holds the name of the board and is used to locate the files related to the board in the source tree (under boards/). @@ -38,14 +40,7 @@ config NET_DRIVERS When building for a qemu target then NET_DRIVERS will be default enabled to allow for easy use of SLIP or PPP -# Note: $BOARD_DIR might be a glob pattern - -choice - prompt "Board Selection" - -source "$(BOARD_DIR)/Kconfig.board" - -endchoice +rsource "Kconfig.$(HWM_SCHEME)" # Parse shields references # Don't do it as a menuconfig, as shield selection is a CMake feature. diff --git a/boards/Kconfig.v1 b/boards/Kconfig.v1 new file mode 100644 index 00000000000000..670e2f2376eb89 --- /dev/null +++ b/boards/Kconfig.v1 @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "Board Selection" + +source "$(BOARD_DIR)/Kconfig.board" + +endchoice diff --git a/boards/Kconfig.v2 b/boards/Kconfig.v2 new file mode 100644 index 00000000000000..a2221dd04b9143 --- /dev/null +++ b/boards/Kconfig.v2 @@ -0,0 +1,18 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +BOARD_STRING := $(sanitize_upper,$(BOARD)) +BOARD_FULL_STRING := $(sanitize_upper,$(BOARD)$(BOARD_IDENTIFIER)) + +config BOARD_$(BOARD_STRING) + def_bool y + help + Kconfig symbol identifying the board. + +config BOARD_$(BOARD_FULL_STRING) + def_bool y + help + Kconfig symbol identifying the board including full board identifier. + +osource "$(BOARD_DIR)/Kconfig.$(BOARD)" diff --git a/boards/aconno/acn52832/Kconfig.acn52832 b/boards/aconno/acn52832/Kconfig.acn52832 new file mode 100644 index 00000000000000..ef035c30f9d0ad --- /dev/null +++ b/boards/aconno/acn52832/Kconfig.acn52832 @@ -0,0 +1,7 @@ +# aconno acn52832 board configuration + +# Copyright (c) 2023 Sven Herrmann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACN52832 + select SOC_NRF52832_QFAA diff --git a/boards/aconno/acn52832/Kconfig.defconfig b/boards/aconno/acn52832/Kconfig.defconfig new file mode 100644 index 00000000000000..10c5ce95ed8a83 --- /dev/null +++ b/boards/aconno/acn52832/Kconfig.defconfig @@ -0,0 +1,11 @@ +# aconno acn52832 board configuration + +# Copyright (c) 2023 Sven Herrmann +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACN52832 + +config BT_CTLR + default BT + +endif # BOARD_ACN52832 diff --git a/boards/arm/acn52832/acn52832-pinctrl.dtsi b/boards/aconno/acn52832/acn52832-pinctrl.dtsi similarity index 100% rename from boards/arm/acn52832/acn52832-pinctrl.dtsi rename to boards/aconno/acn52832/acn52832-pinctrl.dtsi diff --git a/boards/arm/acn52832/acn52832.dts b/boards/aconno/acn52832/acn52832.dts similarity index 100% rename from boards/arm/acn52832/acn52832.dts rename to boards/aconno/acn52832/acn52832.dts diff --git a/boards/arm/acn52832/acn52832.yaml b/boards/aconno/acn52832/acn52832.yaml similarity index 100% rename from boards/arm/acn52832/acn52832.yaml rename to boards/aconno/acn52832/acn52832.yaml diff --git a/boards/aconno/acn52832/acn52832_defconfig b/boards/aconno/acn52832/acn52832_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/aconno/acn52832/acn52832_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/acn52832/board.cmake b/boards/aconno/acn52832/board.cmake similarity index 100% rename from boards/arm/acn52832/board.cmake rename to boards/aconno/acn52832/board.cmake diff --git a/boards/aconno/acn52832/board.yml b/boards/aconno/acn52832/board.yml new file mode 100644 index 00000000000000..179637e1ded3c4 --- /dev/null +++ b/boards/aconno/acn52832/board.yml @@ -0,0 +1,5 @@ +board: + name: acn52832 + vendor: aconno + socs: + - name: nrf52832 diff --git a/boards/arm/acn52832/doc/index.rst b/boards/aconno/acn52832/doc/index.rst similarity index 100% rename from boards/arm/acn52832/doc/index.rst rename to boards/aconno/acn52832/doc/index.rst diff --git a/boards/arm/acn52832/pre_dt_board.cmake b/boards/aconno/acn52832/pre_dt_board.cmake similarity index 100% rename from boards/arm/acn52832/pre_dt_board.cmake rename to boards/aconno/acn52832/pre_dt_board.cmake diff --git a/boards/aconno/index.rst b/boards/aconno/index.rst new file mode 100644 index 00000000000000..4e79f407b98291 --- /dev/null +++ b/boards/aconno/index.rst @@ -0,0 +1,10 @@ +.. _boards-aconno: + +Aconno +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/x86/acrn/CMakeLists.txt b/boards/acrn/acrn/CMakeLists.txt similarity index 100% rename from boards/x86/acrn/CMakeLists.txt rename to boards/acrn/acrn/CMakeLists.txt diff --git a/boards/acrn/acrn/Kconfig b/boards/acrn/acrn/Kconfig new file mode 100644 index 00000000000000..7d7b97605a46c6 --- /dev/null +++ b/boards/acrn/acrn/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2019-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACRN + bool + select CPU_HAS_FPU + select X86_64 + help + "ACRN User OS" + +config BOARD_ACRN_EHL_CRB + bool + select CPU_HAS_FPU + select X86_64 + help + "ACRN User OS on ElkhartLake CRB" diff --git a/boards/acrn/acrn/Kconfig.acrn b/boards/acrn/acrn/Kconfig.acrn new file mode 100644 index 00000000000000..8d1e1db92b4bfc --- /dev/null +++ b/boards/acrn/acrn/Kconfig.acrn @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACRN + select SOC_ATOM diff --git a/boards/acrn/acrn/Kconfig.acrn_ehl_crb b/boards/acrn/acrn/Kconfig.acrn_ehl_crb new file mode 100644 index 00000000000000..e28c959907d2a7 --- /dev/null +++ b/boards/acrn/acrn/Kconfig.acrn_ehl_crb @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACRN_EHL_CRB + select SOC_ATOM diff --git a/boards/acrn/acrn/Kconfig.defconfig b/boards/acrn/acrn/Kconfig.defconfig new file mode 100644 index 00000000000000..678c8a5e378f46 --- /dev/null +++ b/boards/acrn/acrn/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config MP_MAX_NUM_CPUS + default 2 + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 32768 + depends on ACPI diff --git a/boards/x86/acrn/acrn.dts b/boards/acrn/acrn/acrn.dts similarity index 95% rename from boards/x86/acrn/acrn.dts rename to boards/acrn/acrn/acrn.dts index ebf08b3f69b6ed..dbd30373e34be0 100644 --- a/boards/x86/acrn/acrn.dts +++ b/boards/acrn/acrn/acrn.dts @@ -11,7 +11,7 @@ #define DT_DRAM_SIZE DT_SIZE_K(8192) #define DT_DRAM_BASE 0 -#include +#include / { model = "ACRN"; diff --git a/boards/x86/acrn/acrn.yaml b/boards/acrn/acrn/acrn.yaml similarity index 100% rename from boards/x86/acrn/acrn.yaml rename to boards/acrn/acrn/acrn.yaml diff --git a/boards/x86/acrn/acrn_defconfig b/boards/acrn/acrn/acrn_defconfig similarity index 88% rename from boards/x86/acrn/acrn_defconfig rename to boards/acrn/acrn/acrn_defconfig index 2f72c30dce8e5b..0ec5c2b256459f 100644 --- a/boards/x86/acrn/acrn_defconfig +++ b/boards/acrn/acrn/acrn_defconfig @@ -1,7 +1,7 @@ +# Copyright (c) 2019-2024 Intel Corporation +# # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_IA32=y -CONFIG_BOARD_ACRN=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_APIC_TSC_DEADLINE_TIMER=y diff --git a/boards/x86/acrn/acrn_ehl_crb.dts b/boards/acrn/acrn/acrn_ehl_crb.dts similarity index 100% rename from boards/x86/acrn/acrn_ehl_crb.dts rename to boards/acrn/acrn/acrn_ehl_crb.dts diff --git a/boards/x86/acrn/acrn_ehl_crb.yaml b/boards/acrn/acrn/acrn_ehl_crb.yaml similarity index 100% rename from boards/x86/acrn/acrn_ehl_crb.yaml rename to boards/acrn/acrn/acrn_ehl_crb.yaml diff --git a/boards/x86/acrn/acrn_ehl_crb_defconfig b/boards/acrn/acrn/acrn_ehl_crb_defconfig similarity index 90% rename from boards/x86/acrn/acrn_ehl_crb_defconfig rename to boards/acrn/acrn/acrn_ehl_crb_defconfig index 5e3af1f8be36f9..f7b256d2c8482a 100644 --- a/boards/x86/acrn/acrn_ehl_crb_defconfig +++ b/boards/acrn/acrn/acrn_ehl_crb_defconfig @@ -1,7 +1,7 @@ +# Copyright (c) 2019-2024 Intel Corporation +# # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_IA32=y -CONFIG_BOARD_ACRN=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_X2APIC=y diff --git a/boards/x86/acrn/board.cmake b/boards/acrn/acrn/board.cmake similarity index 100% rename from boards/x86/acrn/board.cmake rename to boards/acrn/acrn/board.cmake diff --git a/boards/acrn/acrn/board.yml b/boards/acrn/acrn/board.yml new file mode 100644 index 00000000000000..4130a85b8f69be --- /dev/null +++ b/boards/acrn/acrn/board.yml @@ -0,0 +1,9 @@ +boards: + + - name: acrn + socs: + - name: atom + + - name: acrn_ehl_crb + socs: + - name: elkhart_lake diff --git a/boards/x86/acrn/board_acrn.c b/boards/acrn/acrn/board_acrn.c similarity index 100% rename from boards/x86/acrn/board_acrn.c rename to boards/acrn/acrn/board_acrn.c diff --git a/boards/x86/acrn/doc/ACRN-Hybrid.jpg b/boards/acrn/acrn/doc/ACRN-Hybrid.jpg similarity index 100% rename from boards/x86/acrn/doc/ACRN-Hybrid.jpg rename to boards/acrn/acrn/doc/ACRN-Hybrid.jpg diff --git a/boards/acrn/acrn/doc/index.rst b/boards/acrn/acrn/doc/index.rst new file mode 100644 index 00000000000000..9251284106d7a6 --- /dev/null +++ b/boards/acrn/acrn/doc/index.rst @@ -0,0 +1,302 @@ +ACRN hypervisor +############### + +Zephyr's is capable of running as a guest under the x86 ACRN +hypervisor (see https://projectacrn.org/). The process for getting +this to work is somewhat involved, however. + +ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so- +called "pre-launched" mode. This means Zephyr will access the ACRN +hypervisor directly without involving the SOS VM. This is the most +practical user scenario in the real world because Zephyr's real-time +and safety capability can be assured without influence from other +VMs. The following figure from ACRN's official documentation shows +how a hybrid scenario works: + +.. figure:: ACRN-Hybrid.jpg + :align: center + :alt: ACRN Hybrid User Scenario + :figclass: align-center + + ACRN Hybrid User Scenario + +In this tutorial, we will show you how to build a minimal running instance of Zephyr +and ACRN hypervisor to demonstrate that it works successfully. To learn more about +other features of ACRN, such as building and using the SOS VM or other guest VMs, +please refer to the Getting Started Guide for ACRN: +https://projectacrn.github.io/latest/tutorials/using_hybrid_mode_on_nuc.html + +Build your Zephyr App +********************* + +First, build the Zephyr application you want to run in ACRN as you +normally would, selecting an appropriate board: + + .. code-block:: console + + west build -b acrn_ehl_crb samples/hello_world + +In this tutorial, we will use the Intel Elkhart Lake Reference Board +(`EHL`_ CRB) since it is one of the suggested platforms for this +type of scenario. Use ``acrn_ehl_crb`` as the target board parameter. + +Note the kconfig output in ``build/zephyr/.config``, you will need to +reference that to configure ACRN later. + +The Zephyr build artifact you will need is ``build/zephyr/zephyr.bin``, +which is a raw memory image. Unlike other x86 targets, you do not +want to use ``zephyr.elf``! + +Configure and build ACRN +************************ + +First you need the source code, clone from: + + .. code-block:: console + + git clone https://github.com/projectacrn/acrn-hypervisor + +We suggest that you use versions v2.5.1 or later of the ACRN hypervisor +as they have better support for SMP in Zephyr. + +Like Zephyr, ACRN favors build-time configuration management instead +of runtime probing or control. Unlike Zephyr, ACRN has single large +configuration files instead of small easily-merged configuration +elements like kconfig defconfig files or devicetree includes. You +have to edit a big XML file to match your Zephyr configuration. +Choose an ACRN host config that matches your hardware ("ehl-crb-b" in +this case). Then find the relevant file in +``misc/config_tools/data//hybrid.xml``. + +First, find the list of ```` declarations. Each has an ``id=`` +attribute. For testing Zephyr, you will want to make sure that the +Zephyr image is ID zero. This allows you to launch ACRN with just one +VM image and avoids the need to needlessly copy large Linux blobs into +the boot filesystem. Under currently tested configurations, Zephyr +will always have a "vm_type" tag of "SAFETY_VM". + +Configure Zephyr Memory Layout +============================== + +Next, locate the load address of the Zephyr image and its entry point +address. These have to be configured manually in ACRN. Traditionally +Zephyr distributes itself as an ELF image where these addresses can be +automatically extracted, but ACRN does not know how to do that, it +only knows how to load a single contiguous region of data into memory +and jump to a specific address. + +Find the "..." tag that will look something like this: + + .. code-block:: xml + + + Zephyr + KERNEL_ZEPHYR + Zephyr_RawImage + + + 0x1000 + 0x1000 + + +The ``kern_load_addr`` tag must match the Zephyr LOCORE_BASE symbol +found in include/arch/x86/memory.ld. This is currently 0x1000 and +matches the default ACRN config. + +The ``kern_entry_addr`` tag must match the entry point in the built +``zephyr.elf`` file. You can find this with binutils, for example: + + .. code-block:: console + + $ objdump -f build/zephyr/zephyr.elf + + build/zephyr/zephyr.elf: file format elf64-x86-64 + architecture: i386:x86-64, flags 0x00000012: + EXEC_P, HAS_SYMS + start address 0x0000000000001000 + +By default this entry address is the same, at 0x1000. This has not +always been true of all configurations, however, and will likely +change in the future. + +Configure Zephyr CPUs +===================== + +Now you need to configure the CPU environment ACRN presents to the +guest. By default Zephyr builds in SMP mode, but ACRN's default +configuration gives it only one CPU. Find the value of +``CONFIG_MP_MAX_NUM_CPUS`` in the Zephyr .config file give the guest that +many CPUs in the ```` tag. For example: + + .. code-block:: xml + + + SAFETY_VM + ACRN PRE-LAUNCHED VM0 + + 0 + + + 0 + 1 + + ... + + 0 + 0 + + ... + + +To use SMP, we have to change the pcpu_id of VM0 to 0 and 1. +This configures ACRN to run Zephyr on CPU0 and CPU1. The ACRN hypervisor +and Zephyr application will not boot successfully without this change. +If you plan to run Zephyr with one CPU only, you can skip it. + +Since Zephyr is using CPU0 and CPU1, we also have to change +VM1's configuration so it runs on CPU2 and CPU3. If your ACRN setup has +additional VMs, you should change their configurations as well. + + .. code-block:: xml + + + SOS_VM + ACRN SOS VM + + 0 + + + 2 + 3 + + + 0 + 0 + + ... + + +Note that these indexes are physical CPUs on the host. When +configuring multiple guests, you probably don't want to overlap these +assignments with other guests. But for testing Zephyr simply using +CPUs 0 and 1 works fine. (Note that ehl-crb-b has four physical CPUs, +so configuring all of 0-3 will work fine too, but leave no space for +other guests to have dedicated CPUs). + +Build ACRN +========== + +Once configuration is complete, ACRN builds fairly cleanly: + + .. code-block:: console + + $ make -j BOARD=ehl-crb-b SCENARIO=hybrid + +The only build artifact you need is the ACRN multiboot image in +``build/hypervisor/acrn.bin`` + +Assemble EFI Boot Media +*********************** + +ACRN will boot on the hardware via the GNU GRUB bootloader, which is +itself launched from the EFI firmware. These need to be configured +correctly. + +Locate GRUB +=========== + +First, you will need a GRUB EFI binary that corresponds to your +hardware. In many cases, a simple upstream build from source or a +copy from a friendly Linux distribution will work. In some cases it +will not, however, and GRUB will need to be specially patched for +specific hardware. Contact your hardware support team (pause for +laughter) for clear instructions for how to build a working GRUB. In +practice you may just need to ask around and copy a binary from the +last test that worked for someone. + +Create EFI Boot Filesystem +========================== + +Now attach your boot media (e.g. a USB stick on /dev/sdb, your +hardware may differ!) to a Linux system and create an EFI boot +partition (type code 0xEF) large enough to store your boot artifacts. +This command feeds the relevant commands to fdisk directly, but you +can type them yourself if you like: + + .. code-block:: console + + # for i in n p 1 "" "" t ef w; do echo $i; done | fdisk /dev/sdb + ... + + +Now create a FAT filesystem in the new partition and mount it: + + .. code-block:: console + + # mkfs.vfat -n ACRN_ZEPHYR /dev/sdb1 + # mkdir -p /mnt/acrn + # mount /dev/sdb1 /mnt/acrn + +Copy Images and Configure GRUB +============================== + +ACRN does not have access to a runtime filesystem of its own. It +receives its guest VMs (i.e. zephyr.bin) as GRUB "multiboot" modules. +This means that we must rely on GRUB's filesystem driver. The three +files (GRUB, ACRN and Zephyr) all need to be copied into the +"/efi/boot" directory of the boot media. Note that GRUB must be named +"bootx64.efi" for the firmware to recognize it as the bootloader: + + .. code-block:: console + + # mkdir -p /mnt/acrn/efi/boot + # cp $PATH_TO_GRUB_BINARY /mnt/acrn/efi/boot/bootx64.efi + # cp $ZEPHYR_BASE/build/zephyr/zephyr.bin /mnt/acrn/efi/boot/ + # cp $PATH_TO_ACRN/build/hypervisor/acrn.bin /mnt/acrn/efi/boot/ + +At boot, GRUB will load a "efi/boot/grub.cfg" file for its runtime +configuration instructions (a feature, ironically, that both ACRN and +Zephyr lack!). This needs to load acrn.bin as the boot target and +pass it the zephyr.bin file as its first module (because Zephyr was +configured as ```` above). This minimal configuration will +work fine for all but the weirdest hardware (i.e. "hd0" is virtually +always the boot filesystem from which grub loaded), no need to fiddle +with GRUB plugins or menus or timeouts: + + .. code-block:: console + + # cat > /mnt/acrn/efi/boot/grub.cfg<vm_console 0 + + ----- Entering VM 0 Shell ----- + *** Booting Zephyr OS build v2.6.0-rc1-324-g1a03783861ad *** + Hello World! acrn + + +.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/acrn/index.rst b/boards/acrn/index.rst new file mode 100644 index 00000000000000..608717081c8e53 --- /dev/null +++ b/boards/acrn/index.rst @@ -0,0 +1,10 @@ +.. _boards-acrn: + +Project ACRN +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/actinius/icarus/CMakeLists.txt b/boards/actinius/icarus/CMakeLists.txt new file mode 100644 index 00000000000000..9a434a4d73dd28 --- /dev/null +++ b/boards/actinius/icarus/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2019-2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus/Kconfig.actinius_icarus b/boards/actinius/icarus/Kconfig.actinius_icarus new file mode 100644 index 00000000000000..4c7d234bb632bc --- /dev/null +++ b/boards/actinius/icarus/Kconfig.actinius_icarus @@ -0,0 +1,7 @@ +# Actinius Icarus board configuration + +# Copyright (c) 2019 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus/Kconfig.defconfig b/boards/actinius/icarus/Kconfig.defconfig new file mode 100644 index 00000000000000..80f8e6cab5df8b --- /dev/null +++ b/boards/actinius/icarus/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus board configuration + +# Copyright (c) 2019 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS diff --git a/boards/arm/actinius_icarus/actinius_icarus_common-pinctrl.dtsi b/boards/actinius/icarus/actinius_icarus_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common-pinctrl.dtsi rename to boards/actinius/icarus/actinius_icarus_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus/actinius_icarus_common.dtsi b/boards/actinius/icarus/actinius_icarus_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common.dtsi rename to boards/actinius/icarus/actinius_icarus_common.dtsi diff --git a/boards/arm/actinius_icarus/actinius_icarus_common_1_4_0.dtsi b/boards/actinius/icarus/actinius_icarus_common_1_4_0.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common_1_4_0.dtsi rename to boards/actinius/icarus/actinius_icarus_common_1_4_0.dtsi diff --git a/boards/arm/actinius_icarus/actinius_icarus_common_2_0_0.dtsi b/boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_common_2_0_0.dtsi rename to boards/actinius/icarus/actinius_icarus_common_2_0_0.dtsi diff --git a/boards/actinius/icarus/actinius_icarus_defconfig b/boards/actinius/icarus/actinius_icarus_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/actinius_icarus.dts b/boards/actinius/icarus/actinius_icarus_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus.dts rename to boards/actinius/icarus/actinius_icarus_nrf9160.dts diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.overlay new file mode 100644 index 00000000000000..69d500b69fa191 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml new file mode 100644 index 00000000000000..1f3d3d9e0c0d35 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@1.4.0/nrf9160 +name: Actinius Icarus +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.overlay new file mode 100644 index 00000000000000..68c064cb1b5745 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml new file mode 100644 index 00000000000000..d8bce88855696d --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@2.0.0/nrf9160 +name: Actinius Icarus +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns.dts b/boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_ns.dts rename to boards/actinius/icarus/actinius_icarus_nrf9160_ns.dts diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.overlay new file mode 100644 index 00000000000000..69d500b69fa191 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml new file mode 100644 index 00000000000000..46005a7da105c3 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@1.4.0/nrf9160/ns +name: Actinius Icarus Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.overlay b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.overlay new file mode 100644 index 00000000000000..68c064cb1b5745 --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Actinius + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml new file mode 100644 index 00000000000000..e8d9256f3f0c9f --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml @@ -0,0 +1,23 @@ +identifier: actinius_icarus@2.0.0/nrf9160/ns +name: Actinius Icarus Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - feather_serial + - feather_i2c + - feather_spi + - arduino_i2c + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..4baa62c55eff2b --- /dev/null +++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus/actinius_icarus_partition_conf.dtsi b/boards/actinius/icarus/actinius_icarus_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus/actinius_icarus_partition_conf.dtsi rename to boards/actinius/icarus/actinius_icarus_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus/board.cmake b/boards/actinius/icarus/board.cmake similarity index 100% rename from boards/arm/actinius_icarus/board.cmake rename to boards/actinius/icarus/board.cmake diff --git a/boards/actinius/icarus/board.yml b/boards/actinius/icarus/board.yml new file mode 100644 index 00000000000000..69d6aa457076d1 --- /dev/null +++ b/boards/actinius/icarus/board.yml @@ -0,0 +1,13 @@ +board: + name: actinius_icarus + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' + revision: + format: major.minor.patch + default: "2.0.0" + revisions: + - name: "1.4.0" + - name: "2.0.0" diff --git a/boards/arm/actinius_icarus/doc/img/Icarus_front.jpg b/boards/actinius/icarus/doc/img/Icarus_front.jpg similarity index 100% rename from boards/arm/actinius_icarus/doc/img/Icarus_front.jpg rename to boards/actinius/icarus/doc/img/Icarus_front.jpg diff --git a/boards/arm/actinius_icarus/doc/img/Icarus_pinouts.jpg b/boards/actinius/icarus/doc/img/Icarus_pinouts.jpg similarity index 100% rename from boards/arm/actinius_icarus/doc/img/Icarus_pinouts.jpg rename to boards/actinius/icarus/doc/img/Icarus_pinouts.jpg diff --git a/boards/actinius/icarus/doc/index.rst b/boards/actinius/icarus/doc/index.rst new file mode 100644 index 00000000000000..8092c53c8c90e9 --- /dev/null +++ b/boards/actinius/icarus/doc/index.rst @@ -0,0 +1,238 @@ +.. _actinius_icarus: + +Actinius Icarus +############### + +Overview +******** + +.. figure:: img/Icarus_front.jpg + :align: center + :alt: Icarus IoT Dev Board + + Icarus IoT Dev Board (nRF9160 Feather) + +The Icarus is a cost-effective cellular IoT board in Adafruit's Feather/FeatherWing +form factor. It is built around Nordic Semi's nRF9160 modem and combines +LTE-M, NB-IoT, GPS, accelerometer, USB, LiPo charger as well as +an eSIM and a nano SIM connector. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus Product Website`_. + +.. figure:: img/Icarus_pinouts.jpg + :align: center + :alt: Icarus IoT Dev Board w/ Pinouts + + Icarus IoT Dev Board w/ Pinouts + +Pin description +=============== + +External Pins available to user: + ++------------+----------------------------+----------------------------------------------+------------------+ +| Icarus pin | Function | Description | Device-tree node | ++============+============================+==============================================+==================+ +| RST | Reset | Active low reset with internal pullup | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| 3.3V | Power output | Main 3.3 V supply | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| NC | - | Not connected | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| GND | Power output | Ground | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| 14 / A1 | GPIO / Analog in | nRF9160 P0.14 / AIN1 | gpio0 / adc_1 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 15 / A2 | GPIO / Analog in | nRF9160 P0.15 / AIN2 | gpio0 / adc_2 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 16 / A3 | GPIO / Analog in | nRF9160 P0.16 / AIN3 | gpio0 / adc_3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 17 / A4 | GPIO / Analog in | nRF9160 P0.17 / AIN4 | gpio0 / adc_4 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 18 / A5 | GPIO / Analog in | nRF9160 P0.18 / AIN5 | gpio0 / adc_5 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 19 / A6 | GPIO / Analog in | nRF9160 P0.19 / AIN6 | gpio0 / adc_6 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 20 / SCK | GPIO / SPI pin | nRF9160 P0.20 / SPI SCK pin | gpio0 / spi3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 21 / MOSI | GPIO / SPI pin | nRF9160 P0.21 / SPI MOSI pin | gpio0 / spi3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 22 / MISO | GPIO / SPI pin | nRF9160 P0.22 / SPI MISO pin | gpio0 / spi3 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 23 / RX | GPIO / UART pin | nRF9160 P0.23 / UART RX pin | gpio0 / uart1 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 24 / TX | GPIO / UART pin | nRF9160 P0.24 / UART TX pin | gpio0 / uart1 | ++------------+----------------------------+----------------------------------------------+------------------+ +| VIN | Power input | Voltage input (maximum 10.2 V) | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| VBAT | Power input | Battery voltage input | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| EN | Power enable | Power enable pin (pull low to disable power) | - | ++------------+----------------------------+----------------------------------------------+------------------+ +| USB | Power input | USB voltage input | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 4 | GPIO | nRF9160 P0.04 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 3 | GPIO | nRF9160 P0.03 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 2 | GPIO | nRF9160 P0.02 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 1 | GPIO | nRF9160 P0.01 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 0 | GPIO | nRF9160 P0.00 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 30 | GPIO | nRF9160 P0.30 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| 31 | GPIO | nRF9160 P0.31 | gpio0 | ++------------+----------------------------+----------------------------------------------+------------------+ +| SCL | GPIO / I2C pin | nRF9160 P0.26 / I2C SCL pin | gpio0 / i2c2 | ++------------+----------------------------+----------------------------------------------+------------------+ +| SDA | GPIO / I2C pin | nRF9160 P0.27 / I2C SDA pin | gpio0 / i2c2 | ++------------+----------------------------+----------------------------------------------+------------------+ + +nRF9160 pins connected internally: + ++--------------+---------------------------------------+----------------------+ +| nRF9160 pin | Function | Device-tree node | ++==============+=======================================+======================+ +| P0.05 | User button | button0 | ++--------------+---------------------------------------+----------------------+ +| P0.10 | Red LED | led0 / pwm-led0 | ++--------------+---------------------------------------+----------------------+ +| P0.11 | Green LED | led1 / pwm-led1 | ++--------------+---------------------------------------+----------------------+ +| P0.12 | Blue LED | led2 / pwm-led2 | ++--------------+---------------------------------------+----------------------+ +| P0.28 | Accelerometer Interrupt 1 | lis2dh12-accel | ++--------------+---------------------------------------+----------------------+ +| P0.29 | Accelerometer Interrupt 2 | lis2dh12-accel | ++--------------+---------------------------------------+----------------------+ +| P0.08 | SIM select pin | gpio0 | ++--------------+---------------------------------------+----------------------+ +| P0.13 / AIN0 | Battery voltage measurement | adc_0 | ++--------------+---------------------------------------+----------------------+ +| P0.06 | USB - FTDI serial RX | uart0 | ++--------------+---------------------------------------+----------------------+ +| P0.09 | USB - FTDI serial TX | uart0 | ++--------------+---------------------------------------+----------------------+ +| P0.07 | USB - FTDI serial RTS | uart0 | +| | Charger enable pin (Icarus v2.0) | gpio0 (Icarus v2.0) | ++--------------+---------------------------------------+----------------------+ +| P0.25 | USB - FTDI serial CTS | uart0 | +| | FLASH memory SPI CS pin (Icarus v2.0) | gpio0 (Icarus v2.0) | ++--------------+---------------------------------------+----------------------+ + +Supported Features +================== + +The actinius_icarus board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM Selection +============= + +The SIM choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Charger Enable/Disable +====================== + +Since hardware version 2.0 the charger can be disabled by adjusting the ``charger`` +property of the ``charger_enable`` device tree node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus "Get Started" Guide`_ or the +`Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus Product Website: + https://www.actinius.com/icarus + +.. _Icarus "Get Started" Guide: + https://www.actinius.com/get-started + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus/dts/bindings/actinius-charger-enable.yaml b/boards/actinius/icarus/dts/bindings/actinius-charger-enable.yaml similarity index 100% rename from boards/arm/actinius_icarus/dts/bindings/actinius-charger-enable.yaml rename to boards/actinius/icarus/dts/bindings/actinius-charger-enable.yaml diff --git a/boards/arm/actinius_icarus/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus/feather_connector.dtsi b/boards/actinius/icarus/feather_connector.dtsi similarity index 100% rename from boards/arm/actinius_icarus/feather_connector.dtsi rename to boards/actinius/icarus/feather_connector.dtsi diff --git a/boards/arm/actinius_icarus/pre_dt_board.cmake b/boards/actinius/icarus/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus/pre_dt_board.cmake rename to boards/actinius/icarus/pre_dt_board.cmake diff --git a/boards/actinius/icarus_bee/CMakeLists.txt b/boards/actinius/icarus_bee/CMakeLists.txt new file mode 100644 index 00000000000000..7ddd62dbb2d899 --- /dev/null +++ b/boards/actinius/icarus_bee/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2021-2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus_bee/Kconfig.actinius_icarus_bee b/boards/actinius/icarus_bee/Kconfig.actinius_icarus_bee new file mode 100644 index 00000000000000..6eb4e431f1245e --- /dev/null +++ b/boards/actinius/icarus_bee/Kconfig.actinius_icarus_bee @@ -0,0 +1,7 @@ +# Actinius Icarus Bee board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS_BEE + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus_bee/Kconfig.defconfig b/boards/actinius/icarus_bee/Kconfig.defconfig new file mode 100644 index 00000000000000..3eaf7f5f1c652e --- /dev/null +++ b/boards/actinius/icarus_bee/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus Bee board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS_BEE + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_BEE_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_BEE_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_BEE_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS_BEE diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi rename to boards/actinius/icarus_bee/actinius_icarus_bee_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_common.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_common.dtsi rename to boards/actinius/icarus_bee/actinius_icarus_bee_common.dtsi diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_defconfig b/boards/actinius/icarus_bee/actinius_icarus_bee_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee.dts b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee.dts rename to boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.dts diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml new file mode 100644 index 00000000000000..8fd851899ba336 --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml @@ -0,0 +1,18 @@ +identifier: actinius_icarus_bee/nrf9160 +name: Actinius Icarus Bee +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: actinius diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.dts b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.dts rename to boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.dts diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml new file mode 100644 index 00000000000000..89b21ece170029 --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml @@ -0,0 +1,18 @@ +identifier: actinius_icarus_bee/nrf9160/ns +name: Actinius Icarus Bee Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: actinius diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..4baa62c55eff2b --- /dev/null +++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_partition_conf.dtsi b/boards/actinius/icarus_bee/actinius_icarus_bee_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus_bee/actinius_icarus_bee_partition_conf.dtsi rename to boards/actinius/icarus_bee/actinius_icarus_bee_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus_bee/board.cmake b/boards/actinius/icarus_bee/board.cmake similarity index 100% rename from boards/arm/actinius_icarus_bee/board.cmake rename to boards/actinius/icarus_bee/board.cmake diff --git a/boards/actinius/icarus_bee/board.yml b/boards/actinius/icarus_bee/board.yml new file mode 100644 index 00000000000000..653294a9cf58df --- /dev/null +++ b/boards/actinius/icarus_bee/board.yml @@ -0,0 +1,7 @@ +board: + name: actinius_icarus_bee + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/actinius_icarus_bee/doc/img/icarus-bee-external-pins.jpg b/boards/actinius/icarus_bee/doc/img/icarus-bee-external-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_bee/doc/img/icarus-bee-external-pins.jpg rename to boards/actinius/icarus_bee/doc/img/icarus-bee-external-pins.jpg diff --git a/boards/arm/actinius_icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg b/boards/actinius/icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg rename to boards/actinius/icarus_bee/doc/img/icarus-bee-peripherals-pins.jpg diff --git a/boards/arm/actinius_icarus_bee/doc/img/icarus-bee.jpg b/boards/actinius/icarus_bee/doc/img/icarus-bee.jpg similarity index 100% rename from boards/arm/actinius_icarus_bee/doc/img/icarus-bee.jpg rename to boards/actinius/icarus_bee/doc/img/icarus-bee.jpg diff --git a/boards/actinius/icarus_bee/doc/index.rst b/boards/actinius/icarus_bee/doc/index.rst new file mode 100644 index 00000000000000..630d0aa07c7836 --- /dev/null +++ b/boards/actinius/icarus_bee/doc/index.rst @@ -0,0 +1,137 @@ +.. _actinius_icarus_bee: + +Actinius Icarus Bee +################### + +Overview +******** + +.. figure:: img/icarus-bee.jpg + :align: center + :alt: Icarus Bee + + Icarus Bee (nRF9160 Bee) + +The Icarus Bee is a cellular IoT board in Bee/xBee form factor. +It is built around Nordic Semi's nRF9160 modem and combines +LTE-M, NB-IoT, GPS, accelerometer, SPI Flash, RGB LED, Button, +as well as an eSIM and a nano SIM connector. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/icarus-bee-external-pins.jpg + :align: center + :alt: Icarus Bee w/ Pinouts + + Icarus Bee w/ Pinouts + +.. figure:: img/icarus-bee-peripherals-pins.jpg + :align: center + :alt: Icarus Bee + + Internal Pinouts + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus Bee Product Website`_. + +Supported Features +================== + +The actinius_icarus_bee board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM selection +************* + +The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_bee``. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_bee/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus Bee Product Website`_ or the +`Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus Bee Product Website: + https://www.actinius.com/icarus-bee + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_bee/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus_bee/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus_bee/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus_bee/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus_bee/pre_dt_board.cmake b/boards/actinius/icarus_bee/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus_bee/pre_dt_board.cmake rename to boards/actinius/icarus_bee/pre_dt_board.cmake diff --git a/boards/actinius/icarus_som/CMakeLists.txt b/boards/actinius/icarus_som/CMakeLists.txt new file mode 100644 index 00000000000000..7ddd62dbb2d899 --- /dev/null +++ b/boards/actinius/icarus_som/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2021-2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus_som/Kconfig.actinius_icarus_som b/boards/actinius/icarus_som/Kconfig.actinius_icarus_som new file mode 100644 index 00000000000000..a82ff7216b3299 --- /dev/null +++ b/boards/actinius/icarus_som/Kconfig.actinius_icarus_som @@ -0,0 +1,7 @@ +# Actinius Icarus SoM board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS_SOM + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus_som/Kconfig.defconfig b/boards/actinius/icarus_som/Kconfig.defconfig new file mode 100644 index 00000000000000..43730eb6945b98 --- /dev/null +++ b/boards/actinius/icarus_som/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus SoM board configuration + +# Copyright (c) 2021 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS_SOM + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_SOM_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_SOM_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_SOM_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS_SOM diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_common-pinctrl.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_common-pinctrl.dtsi rename to boards/actinius/icarus_som/actinius_icarus_som_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_common.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_common.dtsi rename to boards/actinius/icarus_som/actinius_icarus_som_common.dtsi diff --git a/boards/actinius/icarus_som/actinius_icarus_som_defconfig b/boards/actinius/icarus_som/actinius_icarus_som_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som.dts b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som.dts rename to boards/actinius/icarus_som/actinius_icarus_som_nrf9160.dts diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml new file mode 100644 index 00000000000000..1eab502534061e --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml @@ -0,0 +1,17 @@ +identifier: actinius_icarus_som/nrf9160 +name: Actinius Icarus SoM +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - watchdog + - counter +vendor: actinius diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.dts b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_ns.dts rename to boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.dts diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml new file mode 100644 index 00000000000000..0a6968beec278d --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml @@ -0,0 +1,17 @@ +identifier: actinius_icarus_som/nrf9160/ns +name: Actinius Icarus SoM Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - watchdog + - counter +vendor: actinius diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..4baa62c55eff2b --- /dev/null +++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_partition_conf.dtsi b/boards/actinius/icarus_som/actinius_icarus_som_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som/actinius_icarus_som_partition_conf.dtsi rename to boards/actinius/icarus_som/actinius_icarus_som_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus_som/board.cmake b/boards/actinius/icarus_som/board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som/board.cmake rename to boards/actinius/icarus_som/board.cmake diff --git a/boards/actinius/icarus_som/board.yml b/boards/actinius/icarus_som/board.yml new file mode 100644 index 00000000000000..9acf3b4fa5ed40 --- /dev/null +++ b/boards/actinius/icarus_som/board.yml @@ -0,0 +1,7 @@ +board: + name: actinius_icarus_som + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/actinius_icarus_som/doc/img/icarus-som-external-pins.jpg b/boards/actinius/icarus_som/doc/img/icarus-som-external-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_som/doc/img/icarus-som-external-pins.jpg rename to boards/actinius/icarus_som/doc/img/icarus-som-external-pins.jpg diff --git a/boards/arm/actinius_icarus_som/doc/img/icarus-som-peripherals-pins.jpg b/boards/actinius/icarus_som/doc/img/icarus-som-peripherals-pins.jpg similarity index 100% rename from boards/arm/actinius_icarus_som/doc/img/icarus-som-peripherals-pins.jpg rename to boards/actinius/icarus_som/doc/img/icarus-som-peripherals-pins.jpg diff --git a/boards/arm/actinius_icarus_som/doc/img/icarus-som.jpg b/boards/actinius/icarus_som/doc/img/icarus-som.jpg similarity index 100% rename from boards/arm/actinius_icarus_som/doc/img/icarus-som.jpg rename to boards/actinius/icarus_som/doc/img/icarus-som.jpg diff --git a/boards/actinius/icarus_som/doc/index.rst b/boards/actinius/icarus_som/doc/index.rst new file mode 100644 index 00000000000000..f3206e63fe3f7f --- /dev/null +++ b/boards/actinius/icarus_som/doc/index.rst @@ -0,0 +1,137 @@ +.. _actinius_icarus_som: + +Actinius Icarus SoM +################### + +Overview +******** + +.. figure:: img/icarus-som.jpg + :align: center + :alt: Icarus SoM + + Icarus SoM (nRF9160) + +The Icarus SoM is a coin-sized, easy-to-solder cellular IoT Module +built around Nordic Semi's nRF9160 modem and combines +LTE-M, NB-IoT, GPS, accelerometer as well as an eSIM and option for +an external nano SIM connector. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/icarus-som-external-pins.jpg + :align: center + :alt: Icarus SoM Pins + + Icarus SoM Pins + +.. figure:: img/icarus-som-peripherals-pins.jpg + :align: center + :alt: Icarus SoM + + Internal Pinouts + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_. + +Supported Features +================== + +The actinius_icarus_som board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM selection +************* + +The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som``. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus SoM Product Website`_ or the +`Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus SoM Product Website: + https://www.actinius.com/icarus-som + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus_som/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus_som/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus_som/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus_som/pre_dt_board.cmake b/boards/actinius/icarus_som/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som/pre_dt_board.cmake rename to boards/actinius/icarus_som/pre_dt_board.cmake diff --git a/boards/actinius/icarus_som_dk/CMakeLists.txt b/boards/actinius/icarus_som_dk/CMakeLists.txt new file mode 100644 index 00000000000000..4e57b25bdf1c6a --- /dev/null +++ b/boards/actinius/icarus_som_dk/CMakeLists.txt @@ -0,0 +1,6 @@ +# +# Copyright (c) 2022 Actinius +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/actinius/icarus_som_dk/Kconfig.actinius_icarus_som_dk b/boards/actinius/icarus_som_dk/Kconfig.actinius_icarus_som_dk new file mode 100644 index 00000000000000..4c4966e9839bfd --- /dev/null +++ b/boards/actinius/icarus_som_dk/Kconfig.actinius_icarus_som_dk @@ -0,0 +1,7 @@ +# Actinius Icarus SoM DK board configuration + +# Copyright (c) 2022 Actinius +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ACTINIUS_ICARUS_SOM_DK + select SOC_NRF9160_SICA diff --git a/boards/actinius/icarus_som_dk/Kconfig.defconfig b/boards/actinius/icarus_som_dk/Kconfig.defconfig new file mode 100644 index 00000000000000..62e848d3468138 --- /dev/null +++ b/boards/actinius/icarus_som_dk/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Actinius Icarus SoM DK board configuration + +# Copyright (c) 2022 Actinius +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ACTINIUS_ICARUS_SOM_DK + +source "boards/common/actinius/Kconfig" + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_ACTINIUS_ICARUS_SOM_DK_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_ACTINIUS_ICARUS_SOM_DK_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_ACTINIUS_ICARUS_SOM_DK_NRF9160_NS + +endif # BOARD_ACTINIUS_ICARUS_SOM_DK diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common-pinctrl.dtsi diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_common.dtsi rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_common.dtsi diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_defconfig b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.dts b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.dts similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.dts rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.dts diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml new file mode 100644 index 00000000000000..3b7d7377caa836 --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml @@ -0,0 +1,22 @@ +identifier: actinius_icarus_som_dk/nrf9160 +name: Actinius Icarus SoM DK +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 256 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi +vendor: actinius diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.dts b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.dts rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.dts diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml new file mode 100644 index 00000000000000..b41972384ba050 --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml @@ -0,0 +1,22 @@ +identifier: actinius_icarus_som_dk/nrf9160/ns +name: Actinius Icarus SoM DK Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - gpio + - i2c + - pwm + - spi + - watchdog + - counter + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi +vendor: actinius diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..4baa62c55eff2b --- /dev/null +++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi rename to boards/actinius/icarus_som_dk/actinius_icarus_som_dk_partition_conf.dtsi diff --git a/boards/arm/actinius_icarus_som_dk/arduino_connector.dtsi b/boards/actinius/icarus_som_dk/arduino_connector.dtsi similarity index 100% rename from boards/arm/actinius_icarus_som_dk/arduino_connector.dtsi rename to boards/actinius/icarus_som_dk/arduino_connector.dtsi diff --git a/boards/arm/actinius_icarus_som_dk/board.cmake b/boards/actinius/icarus_som_dk/board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som_dk/board.cmake rename to boards/actinius/icarus_som_dk/board.cmake diff --git a/boards/actinius/icarus_som_dk/board.yml b/boards/actinius/icarus_som_dk/board.yml new file mode 100644 index 00000000000000..137f39705d1a1f --- /dev/null +++ b/boards/actinius/icarus_som_dk/board.yml @@ -0,0 +1,7 @@ +board: + name: actinius_icarus_som_dk + vendor: actinius + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg b/boards/actinius/icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg similarity index 100% rename from boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg rename to boards/actinius/icarus_som_dk/doc/img/icarus-som-dk-block-diagram.jpg diff --git a/boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk.jpg b/boards/actinius/icarus_som_dk/doc/img/icarus-som-dk.jpg similarity index 100% rename from boards/arm/actinius_icarus_som_dk/doc/img/icarus-som-dk.jpg rename to boards/actinius/icarus_som_dk/doc/img/icarus-som-dk.jpg diff --git a/boards/actinius/icarus_som_dk/doc/index.rst b/boards/actinius/icarus_som_dk/doc/index.rst new file mode 100644 index 00000000000000..c0d0a940339589 --- /dev/null +++ b/boards/actinius/icarus_som_dk/doc/index.rst @@ -0,0 +1,245 @@ +.. _actinius_icarus_som_dk: + +Actinius Icarus SoM DK +###################### + +Overview +******** + +.. figure:: img/icarus-som-dk.jpg + :width: 450px + :align: center + :alt: Icarus SoM DK + + Icarus SoM Development Kit (nRF9160) + +The Icarus SoM DK is a single board development kit for +evaluation and development on the Icarus SoM (`Icarus SoM Docs`_). +The Icarus SoM features the nRF9160 SiP from Nordic Semiconductor, +a low-power 3-axis accelerometer and an on-board eSIM. +The development kit provides interfacing to the SoM through USB-C, +a set of user LEDs, a reset and a user button, a battery charging port, +and a external nano SIM connector. +The board is also Arduino Uno Rev3 compatible which makes +using external shields possible. + +The main uController is the Nordic Semiconductor nRF9160, with +ARM Cortex-M33F CPU, ARMv8-M Security Extension and the +following devices (provided directly by Nordic): + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/icarus-som-dk-block-diagram.jpg + :width: 450px + :align: center + :alt: Icarus SoM DK Block Diagram + + Icarus SoM DK Block Diagram + +Hardware +******** + +The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_ +and the `Icarus SoM DK Product Website`_. + +Pin description +=============== + +External Pins available to user: + ++----+-------+------------------------------------+------------------+ +| # | Label | Description | Device-tree node | ++====+=======+====================================+==================+ +| 1 | NC | Not Connected | - | ++----+-------+------------------------------------+------------------+ +| 2 | IOREF | I/O reference, connected to 3.3V | - | ++----+-------+------------------------------------+------------------+ +| 3 | RST | Reset of the nRF9160 | - | ++----+-------+------------------------------------+------------------+ +| 4 | 3.3V | 3.3V Power output | - | ++----+-------+------------------------------------+------------------+ +| 5 | 4.4V | Power output between Vbat and 4.4V | - | ++----+-------+------------------------------------+------------------+ +| 6 | GND | Ground pin | - | ++----+-------+------------------------------------+------------------+ +| 7 | GND | Ground pin | - | ++----+-------+------------------------------------+------------------+ +| 8 | VIN | Power input pin (4.35V to 10.5V) | - | ++----+-------+------------------------------------+------------------+ +| 9 | A2 | AIN2 / nRF9160 P0.15 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 10 | A3 | AIN3 / nRF9160 P0.16 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 11 | A4 | AIN4 / nRF9160 P0.17 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 12 | A5 | AIN5 / nRF9160 P0.18 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 13 | A6 | AIN6 / nRF9160 P0.19 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 14 | A7 | AIN7 / nRF9160 P0.20 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 15 | P4 | nRF9160 P0.04 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 16 | P5 | nRF9160 P0.05 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 17 | P2 | nRF9160 P0.02 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 18 | P1 | nRF9160 P0.01 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 19 | P23 | nRF9160 P0.23 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 20 | P0 | nRF9160 P0.00 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 21 | P26 | nRF9160 P0.26 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 22 | P27 | nRF9160 P0.27 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 23 | P30 | nRF9160 P0.30 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 24 | P31 | nRF9160 P0.31 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 25 | P7 | nRF9160 P0.07 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 26 | P13 | nRF9160 P0.13 or NC (Jumper-dependent) | gpio0 | ++----+-------+------------------------------------+------------------+ +| 27 | P14 | nRF9160 P0.14 or NC (Jumper-dependent) | gpio0 | ++----+-------+------------------------------------+------------------+ +| 28 | P3 | nRF9160 P0.03 | gpio0 | ++----+-------+------------------------------------+------------------+ +| 29 | GND | Ground pin | - | ++----+-------+------------------------------------+------------------+ +| 30 | AREF | NC or AIN1 (Jumper-dependent) | gpio0 | ++----+-------+------------------------------------+------------------+ +| 31 | SDA | I2C SDA pin | i2c2 | ++----+-------+------------------------------------+------------------+ +| 32 | SCL | I2C SCL pin | i2c2 | ++----+-------+------------------------------------+------------------+ +| - | TS | Pin for optional battery thermistor| - | ++----+-------+------------------------------------+------------------+ +| - | CHG | Pin for battery charging indication| - | ++----+-------+------------------------------------+------------------+ +| - | CE | Pin for enabling/disabling charging| - | ++----+-------+------------------------------------+------------------+ + + +nRF9160 pins connected internally: + ++--------------+------------------------------+---------------------+ +| nRF9160 pin | Function | Device-tree node | ++==============+==============================+=====================+ +| P0.03 | Blue LED | led0 / pwm-led0 | ++--------------+------------------------------+---------------------+ +| P0.08 | NeoPixel RGB LED | spi1 | ++--------------+------------------------------+---------------------+ +| P0.12 | SIM select pin | gpio0 | ++--------------+------------------------------+---------------------+ +| P0.23 | Connected to the user button | gpio0 / button0 | ++--------------+------------------------------+---------------------+ +| P0.24 | SPI NOR Flash chip select | gpio0 / spi3 | ++--------------+------------------------------+---------------------+ +| P0.28 | Accelerometer Interrupt 2 | lis2dh12-accel | ++--------------+------------------------------+---------------------+ +| P0.29 | Accelerometer Interrupt 1 | lis2dh12-accel | ++--------------+------------------------------+---------------------+ + +Supported Features +================== + +The actinius_icarus_som_dk board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| ACCEL | st | lis2dh | ++-----------+------------+----------------------+ + +SIM selection +************* + +The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting +the ``sim`` property in the ``sim_select`` node. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk``. +2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk/ns``. +3. Merge the two binaries together. + +If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and +burned automatically, unless you have disabled the feature. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +More information can be found in the `Icarus SoM Product Website`_, +the `Icarus SoM DK Product Website`_ or the `Actinius Documentation Portal`_. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau + +.. _Icarus SoM Product Website: + https://www.actinius.com/icarus-som + +.. _Icarus SoM DK Product Website: + https://www.actinius.com/icarus-som-dk + +.. _Icarus SoM Docs: + https://docs.actinius.com/icarus-som/introduction + +.. _Actinius Documentation Portal: + https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som_dk/dts/bindings/actinius-sim-select.yaml b/boards/actinius/icarus_som_dk/dts/bindings/actinius-sim-select.yaml similarity index 100% rename from boards/arm/actinius_icarus_som_dk/dts/bindings/actinius-sim-select.yaml rename to boards/actinius/icarus_som_dk/dts/bindings/actinius-sim-select.yaml diff --git a/boards/arm/actinius_icarus_som_dk/pre_dt_board.cmake b/boards/actinius/icarus_som_dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/actinius_icarus_som_dk/pre_dt_board.cmake rename to boards/actinius/icarus_som_dk/pre_dt_board.cmake diff --git a/boards/actinius/index.rst b/boards/actinius/index.rst new file mode 100644 index 00000000000000..045387a0c50269 --- /dev/null +++ b/boards/actinius/index.rst @@ -0,0 +1,10 @@ +.. _boards-actinius: + +Actinius +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/adafruit/feather/Kconfig b/boards/adafruit/feather/Kconfig new file mode 100644 index 00000000000000..e266540aa871f6 --- /dev/null +++ b/boards/adafruit/feather/Kconfig @@ -0,0 +1,10 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_ADAFRUIT_FEATHER diff --git a/boards/adafruit/feather/Kconfig.adafruit_feather b/boards/adafruit/feather/Kconfig.adafruit_feather new file mode 100644 index 00000000000000..ed952670ce1a3f --- /dev/null +++ b/boards/adafruit/feather/Kconfig.adafruit_feather @@ -0,0 +1,7 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER + select SOC_NRF52840_QIAA diff --git a/boards/adafruit/feather/Kconfig.defconfig b/boards/adafruit/feather/Kconfig.defconfig new file mode 100644 index 00000000000000..3ae6f23be55c81 --- /dev/null +++ b/boards/adafruit/feather/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Adafruit Feather nRF52840 Express board configuration + +# Copyright (c) 2020 Tobias Svehagen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_FEATHER + +config BT_CTLR + default BT + +endif # BOARD_ADAFRUIT_FEATHER diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840-pinctrl.dtsi b/boards/adafruit/feather/adafruit_feather_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840-pinctrl.dtsi rename to boards/adafruit/feather/adafruit_feather_nrf52840-pinctrl.dtsi diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts b/boards/adafruit/feather/adafruit_feather_nrf52840.dts similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.dts rename to boards/adafruit/feather/adafruit_feather_nrf52840.dts diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.yaml b/boards/adafruit/feather/adafruit_feather_nrf52840.yaml similarity index 86% rename from boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.yaml rename to boards/adafruit/feather/adafruit_feather_nrf52840.yaml index f626fd46a4a729..487c78377a13ba 100644 --- a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840.yaml +++ b/boards/adafruit/feather/adafruit_feather_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: adafruit_feather_nrf52840 +identifier: adafruit_feather/nrf52840 name: Adafruit Feather nRF52840 Express type: mcu arch: arm diff --git a/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig b/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/adafruit/feather/adafruit_feather_nrf52840_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_feather_nrf52840/board.cmake b/boards/adafruit/feather/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/board.cmake rename to boards/adafruit/feather/board.cmake diff --git a/boards/adafruit/feather/board.yml b/boards/adafruit/feather/board.yml new file mode 100644 index 00000000000000..f4ae7ce2d19185 --- /dev/null +++ b/boards/adafruit/feather/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather + vendor: adafruit + socs: + - name: nrf52840 diff --git a/boards/arm/adafruit_feather_nrf52840/doc/img/adafruit_feather_nrf52840.jpg b/boards/adafruit/feather/doc/img/adafruit_feather_nrf52840.jpg similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/doc/img/adafruit_feather_nrf52840.jpg rename to boards/adafruit/feather/doc/img/adafruit_feather_nrf52840.jpg diff --git a/boards/adafruit/feather/doc/index.rst b/boards/adafruit/feather/doc/index.rst new file mode 100644 index 00000000000000..241f11e7305adb --- /dev/null +++ b/boards/adafruit/feather/doc/index.rst @@ -0,0 +1,146 @@ +.. _adafruit_feather_nrf52840: + +Adafruit Feather nRF52840 Express +################################# + +Overview +******** + +The Adafruit Feather nRF52840 provides support for the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/adafruit_feather_nrf52840.jpg + :align: center + :alt: Adafruit Feather nRF52840 Express + +Hardware +******** + +- nRF52840 ARM Cortex-M4F processor at 64 MHz +- 1 MB flash memory and 256 KB of SRAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- 2 User LEDs +- 1 NeoPixel LED +- Reset button +- SWD connector + +Supported Features +================== + +The Adafruit Feather nRF52840 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `Adafruit Feather nRF52840 Express Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +LED +--- + +* LED0 (red) = P1.15 +* LED1 (blue) = P1.10 + +Push buttons +------------ + +* SWITCH = P1.02 +* RESET = P0.18 + +Programming and Debugging +************************* + +Applications for the ``adafruit_feather/nrf52840`` board configuration +can be built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing +======== + +Flashing Zephyr onto the ``adafruit_feather_nrf52480`` board requires +an external programmer. The programmer is attached to the SWD header. + +Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather/nrf52840 + :goals: build + :compact: + +Flash the image. + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_feather/nrf52840 + :goals: flash + :compact: + +You should see the red LED blink. + +References +********** + +.. target-notes:: + +.. _Adafruit Feather nRF52840 Express Learn site: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/ + +.. _pinouts: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/pinouts + +.. _schematic: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/downloads diff --git a/boards/arm/adafruit_feather_nrf52840/feather_connector.dtsi b/boards/adafruit/feather/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/feather_connector.dtsi rename to boards/adafruit/feather/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_nrf52840/pre_dt_board.cmake b/boards/adafruit/feather/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_feather_nrf52840/pre_dt_board.cmake rename to boards/adafruit/feather/pre_dt_board.cmake diff --git a/boards/adafruit/feather_m0_basic_proto/Kconfig.adafruit_feather_m0_basic_proto b/boards/adafruit/feather_m0_basic_proto/Kconfig.adafruit_feather_m0_basic_proto new file mode 100644 index 00000000000000..cd561180a014a2 --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/Kconfig.adafruit_feather_m0_basic_proto @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Henrik Brix Andersen +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO + select SOC_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi rename to boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto-pinctrl.dtsi diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts rename to boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.dts diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml rename to boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml diff --git a/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig new file mode 100644 index 00000000000000..55aee7ced2d69f --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_feather_m0_basic_proto/board.cmake b/boards/adafruit/feather_m0_basic_proto/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/board.cmake rename to boards/adafruit/feather_m0_basic_proto/board.cmake diff --git a/boards/adafruit/feather_m0_basic_proto/board.yml b/boards/adafruit/feather_m0_basic_proto/board.yml new file mode 100644 index 00000000000000..cf9353bf78c6ff --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather_m0_basic_proto + vendor: adafruit + socs: + - name: samd21g18a diff --git a/boards/arm/adafruit_feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg b/boards/adafruit/feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg rename to boards/adafruit/feather_m0_basic_proto/doc/img/adafruit_feather_m0_basic_proto.jpg diff --git a/boards/adafruit/feather_m0_basic_proto/doc/index.rst b/boards/adafruit/feather_m0_basic_proto/doc/index.rst new file mode 100644 index 00000000000000..a9dc7f0c2297da --- /dev/null +++ b/boards/adafruit/feather_m0_basic_proto/doc/index.rst @@ -0,0 +1,167 @@ +.. _adafruit_feather_m0_basic_proto: + +Adafruit Feather M0 Basic Proto +############################### + +Overview +******** + +The Adafruit Feather M0 Basic Proto is a thin, light ARM development +board with an onboard battery connector and charger for 3.7 V lithium +polymer batteries, charging status indicator and user LEDs, native USB +connector, 20 I/O pins, and a small prototyping area. + +.. image:: img/adafruit_feather_m0_basic_proto.jpg + :align: center + :alt: Adafruit Feather M0 Basic Proto + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- User LED +- Reset button +- Native USB port + +Supported Features +================== + +The adafruit_feather_m0_basic_proto board configuration supports the +following hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | Systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial port | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface port | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Feather M0 Basic Proto Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +Basic Proto, SERCOM0 is the Zephyr console and is available on pins 0 +(RX) and 1 (TX). + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +Basic Proto, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 +Basic Proto, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and +pin 24 (SCK). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Adafruit Feather M0 Basic Proto ships with a BOSSA compatible +SAM-BA bootloader. The bootloader can be entered by quickly tapping +the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_basic_proto + :goals: build + :compact: + +#. Connect the Adafruit Feather M0 Basic Proto to your host computer + using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_basic_proto + :goals: flash + :compact: + + You should see "Hello World! adafruit_feather_m0_basic_proto" in your terminal. + +References +********** + +.. target-notes:: + +.. _Adafruit Feather M0 Basic Proto Learn site: + https://learn.adafruit.com/adafruit-feather-m0-basic-proto/ + +.. _pinouts: + https://learn.adafruit.com/adafruit-feather-m0-basic-proto/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-feather-m0-basic-proto/downloads diff --git a/boards/arm/adafruit_feather_m0_basic_proto/feather_connector.dtsi b/boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/feather_connector.dtsi rename to boards/adafruit/feather_m0_basic_proto/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_m0_basic_proto/pre_dt_board.cmake b/boards/adafruit/feather_m0_basic_proto/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_basic_proto/pre_dt_board.cmake rename to boards/adafruit/feather_m0_basic_proto/pre_dt_board.cmake diff --git a/boards/adafruit/feather_m0_lora/Kconfig.adafruit_feather_m0_lora b/boards/adafruit/feather_m0_lora/Kconfig.adafruit_feather_m0_lora new file mode 100644 index 00000000000000..17a1d5e49f355a --- /dev/null +++ b/boards/adafruit/feather_m0_lora/Kconfig.adafruit_feather_m0_lora @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Miguel Dardenne +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_M0_LORA + select SOC_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi rename to boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora-pinctrl.dtsi diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.dts b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.dts similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.dts rename to boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.dts diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.yaml b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora.yaml rename to boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml diff --git a/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig new file mode 100644 index 00000000000000..55aee7ced2d69f --- /dev/null +++ b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_feather_m0_lora/board.cmake b/boards/adafruit/feather_m0_lora/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/board.cmake rename to boards/adafruit/feather_m0_lora/board.cmake diff --git a/boards/adafruit/feather_m0_lora/board.yml b/boards/adafruit/feather_m0_lora/board.yml new file mode 100644 index 00000000000000..b720fc95ffeb7b --- /dev/null +++ b/boards/adafruit/feather_m0_lora/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather_m0_lora + vendor: adafruit + socs: + - name: samd21g18a diff --git a/boards/arm/adafruit_feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg b/boards/adafruit/feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg rename to boards/adafruit/feather_m0_lora/doc/img/adafruit_feather_m0_lora.jpg diff --git a/boards/adafruit/feather_m0_lora/doc/index.rst b/boards/adafruit/feather_m0_lora/doc/index.rst new file mode 100644 index 00000000000000..3303c6e480c77f --- /dev/null +++ b/boards/adafruit/feather_m0_lora/doc/index.rst @@ -0,0 +1,176 @@ +.. _adafruit_feather_m0_lora: + +Adafruit Feather M0 LoRa +######################## + +Overview +******** + +The Adafruit Feather M0 Lora is a thin, light ARM development +boards with an onboard battery connector and charger for 3.7 V lithium +polymer batteries, charging status indicator and user LEDs, native USB +connector, 20 I/O pins, and a LoRa radio module from Semtech. + +.. image:: img/adafruit_feather_m0_lora.jpg + :align: center + :alt: Adafruit Feather M0 LoRa + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- User LED +- Reset button +- Native USB port +- SX127x LoRa radio + +Supported Features +================== + +The adafruit_feather_m0_lora board configuration supports the +following hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | Systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial port | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface port | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| RADIO | SPI | LoRa radio | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Feather M0 with LoRa radio module Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +with LoRa, SERCOM0 is the Zephyr console and is available on pins 0 +(RX) and 1 (TX). + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 +with LoRa, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 +with LoRa, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and +pin 24 (SCK). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +LoRa Radio +========== +The Semtech SX127x radio chip on the Adafruit Feather M0 with LoRa +is attached to the SPI port (SERCOM4). Depending on the hardware +version, 433MHz or 900MHz is supported. + +Programming and Debugging +************************* + +The Adafruit Feather M0 with LoRa ships with a BOSSA compatible +SAM-BA bootloader. The bootloader can be entered by quickly tapping +the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_lora + :goals: build + :compact: + +#. Connect the Adafruit Feather M0 with LoRa to your host computer + using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_feather_m0_lora + :goals: flash + :compact: + + You should see "Hello World! adafruit_feather_m0_lora" in your terminal. + +References +********** + +.. target-notes:: + +.. _Adafruit Feather M0 with LoRa radio module Learn site: + https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module + +.. _pinouts: + https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/downloads diff --git a/boards/arm/adafruit_feather_m0_lora/feather_connector.dtsi b/boards/adafruit/feather_m0_lora/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/feather_connector.dtsi rename to boards/adafruit/feather_m0_lora/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_m0_lora/pre_dt_board.cmake b/boards/adafruit/feather_m0_lora/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_feather_m0_lora/pre_dt_board.cmake rename to boards/adafruit/feather_m0_lora/pre_dt_board.cmake diff --git a/boards/adafruit/feather_stm32f405/Kconfig.adafruit_feather_stm32f405 b/boards/adafruit/feather_stm32f405/Kconfig.adafruit_feather_stm32f405 new file mode 100644 index 00000000000000..e26a99c90ce52b --- /dev/null +++ b/boards/adafruit/feather_stm32f405/Kconfig.adafruit_feather_stm32f405 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Lucian Copeland for Adafruit Industries +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_FEATHER_STM32F405 + select SOC_STM32F405XX diff --git a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.dts b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.dts rename to boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.dts diff --git a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.yaml b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405.yaml rename to boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml diff --git a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405_defconfig b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig similarity index 84% rename from boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405_defconfig rename to boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig index ca015a21976c5a..c729b83e3d0506 100644 --- a/boards/arm/adafruit_feather_stm32f405/adafruit_feather_stm32f405_defconfig +++ b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F405XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/adafruit_feather_stm32f405/board.cmake b/boards/adafruit/feather_stm32f405/board.cmake similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/board.cmake rename to boards/adafruit/feather_stm32f405/board.cmake diff --git a/boards/adafruit/feather_stm32f405/board.yml b/boards/adafruit/feather_stm32f405/board.yml new file mode 100644 index 00000000000000..e30f5c0cbcff63 --- /dev/null +++ b/boards/adafruit/feather_stm32f405/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_feather_stm32f405 + vendor: adafruit + socs: + - name: stm32f405xx diff --git a/boards/arm/adafruit_feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg b/boards/adafruit/feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg rename to boards/adafruit/feather_stm32f405/doc/img/adafruit_feather_stm32f405.jpg diff --git a/boards/arm/adafruit_feather_stm32f405/doc/index.rst b/boards/adafruit/feather_stm32f405/doc/index.rst similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/doc/index.rst rename to boards/adafruit/feather_stm32f405/doc/index.rst diff --git a/boards/arm/adafruit_feather_stm32f405/feather_connector.dtsi b/boards/adafruit/feather_stm32f405/feather_connector.dtsi similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/feather_connector.dtsi rename to boards/adafruit/feather_stm32f405/feather_connector.dtsi diff --git a/boards/arm/adafruit_feather_stm32f405/support/openocd.cfg b/boards/adafruit/feather_stm32f405/support/openocd.cfg similarity index 100% rename from boards/arm/adafruit_feather_stm32f405/support/openocd.cfg rename to boards/adafruit/feather_stm32f405/support/openocd.cfg diff --git a/boards/adafruit/grand_central_m4_express/Kconfig.adafruit_grand_central_m4_express b/boards/adafruit/grand_central_m4_express/Kconfig.adafruit_grand_central_m4_express new file mode 100644 index 00000000000000..d761870a9afbe2 --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/Kconfig.adafruit_grand_central_m4_express @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Lukas Jung +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS + select SOC_SAMD51P20A diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi rename to boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express-pinctrl.dtsi diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.dts b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.dts rename to boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.dts diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.yaml b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.yaml similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express.yaml rename to boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express.yaml diff --git a/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig new file mode 100644 index 00000000000000..82a151d53e841d --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_grand_central_m4_express/board.cmake b/boards/adafruit/grand_central_m4_express/board.cmake similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/board.cmake rename to boards/adafruit/grand_central_m4_express/board.cmake diff --git a/boards/adafruit/grand_central_m4_express/board.yml b/boards/adafruit/grand_central_m4_express/board.yml new file mode 100644 index 00000000000000..92a48d1b2b325e --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_grand_central_m4_express + vendor: adafruit + socs: + - name: samd51p20a diff --git a/boards/arm/adafruit_grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp b/boards/adafruit/grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp rename to boards/adafruit/grand_central_m4_express/doc/img/adafruit_grand_central_m4_express.webp diff --git a/boards/adafruit/grand_central_m4_express/doc/index.rst b/boards/adafruit/grand_central_m4_express/doc/index.rst new file mode 100644 index 00000000000000..ec8ab08afdfff5 --- /dev/null +++ b/boards/adafruit/grand_central_m4_express/doc/index.rst @@ -0,0 +1,195 @@ +.. _adafruit_grand_central_m4_express: + +Adafruit Grand Central M4 Express +################################# + +Overview +******** + +The Adafruit Grand Central M4 Express is an ARM development board with the +form factor of an Arduino Mega. +It features 70 GPIO pins, a microSDHC slot and 8MiB of QSPI Flash. + +.. figure:: img/adafruit_grand_central_m4_express.webp + :width: 800px + :align: center + :alt: Adafruit Grand Central M4 Express + + Adafruit Grand Central M4 Express (Credit: Kattni Rembor / Adafruit) + +Hardware +******** + +- ATSAMD51P20A ARM Cortex-M4F processor at 120 MHz +- 1024 KiB of flash memory and 256 KiB of RAM +- 8 MiB of QSPI flash +- A red user LED +- A RGB "NeoPixel" / WS2812B LED +- A microSDHC slot (connected via SPI) +- Native USB port + +Supported Features +================== + +The adafruit_grand_central_m4_express board configuration supports the following +hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | SysTick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports, User LED | ++-----------+------------+------------------------------------------+ +| UART | on-chip | Serial ports, Console | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | SPI ports, microSDHC slot | ++-----------+------------+------------------------------------------+ +| TRNG | on-chip | True Random Number Generator | ++-----------+------------+------------------------------------------+ +| RTC | on-chip | Real-Time Counter | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog Timer | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Learning System`_ has detailed information about +the board including `pinouts`_ and the `schematics`_. + +System Clock +============ + +The SAMD51 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 120 MHz system clock. + +Serial Port +=========== + +The SAMD51 MCU has 8 SERCOM based UARTs. On the Grand Central, SERCOM0 is +the Zephyr console and is available on RX(PB25) and TX(PB24). + +SPI Port +======== + +The SAMD51 MCU has 8 SERCOM based SPIs. On the Grand Central, SERCOM7 has been +set into SPI mode to connect to devices over the SCK(PD09), MOSI(PD08), and MISO(PD11) pins. +Additionally SERCOM2 has been configured as SPI to access the microSDHC card. + +I2C Port +======== + +The SAMD51 MCU has 8 SERCOM based I2Cs. On the Grand Central, SERCOM3 has been +configured as I2C to connect to devices over the SCL(PB21) and SDA(PB20) pins. + +USB Device Port +=============== + +The SAMD51 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Grand Central ships with a BOSSA compatible UF2 bootloader. +The bootloader can be entered by quickly tapping the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: build + :compact: + +#. Connect the Grand Central to your host computer using USB. + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: flash + :compact: + + You should see "Hello World! adafruit_grand_central_m4_express" in your terminal. + +Debugging +========= + +In addition to the built-in bootloader, the Grand Central can be flashed and +debugged using a SWD probe such as the Segger J-Link. + +#. Connect the probe to the board using the 10-pin SWD interface. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: flash + :flash-args: -r openocd + :compact: + +#. Start debugging: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_grand_central_m4_express + :goals: debug + :compact: + +References +********** + +.. target-notes:: + +.. _Adafruit Learning System: + https://learn.adafruit.com/adafruit-grand-central + +.. _pinouts: + https://learn.adafruit.com/adafruit-grand-central/pinouts + +.. _schematics: + https://learn.adafruit.com/adafruit-grand-central/downloads + +.. _J-Link: + https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_grand_central_m4_express/support/openocd.cfg b/boards/adafruit/grand_central_m4_express/support/openocd.cfg similarity index 100% rename from boards/arm/adafruit_grand_central_m4_express/support/openocd.cfg rename to boards/adafruit/grand_central_m4_express/support/openocd.cfg diff --git a/boards/adafruit/index.rst b/boards/adafruit/index.rst new file mode 100644 index 00000000000000..63e0385c8e5b70 --- /dev/null +++ b/boards/adafruit/index.rst @@ -0,0 +1,10 @@ +.. _boards-adafruit: + +Adafruit Industries LLC +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/adafruit/itsybitsy/Kconfig b/boards/adafruit/itsybitsy/Kconfig new file mode 100644 index 00000000000000..e2c47273197b2b --- /dev/null +++ b/boards/adafruit/itsybitsy/Kconfig @@ -0,0 +1,15 @@ +# Adafruit ItsyBitsy nRF52840 Express board configuration + +# Copyright (c) 2022 Embla Flatlandsmo +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_ADAFRUIT_ITSYBITSY + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "USB CDC" + default y + depends on BOARD_ADAFRUIT_ITSYBITSY diff --git a/boards/adafruit/itsybitsy/Kconfig.adafruit_itsybitsy b/boards/adafruit/itsybitsy/Kconfig.adafruit_itsybitsy new file mode 100644 index 00000000000000..6e64301cb46ac3 --- /dev/null +++ b/boards/adafruit/itsybitsy/Kconfig.adafruit_itsybitsy @@ -0,0 +1,7 @@ +# Adafruit ItsyBitsy nRF52840 Express board configuration + +# Copyright (c) 2022 Embla Flatlandsmo +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_ITSYBITSY + select SOC_NRF52840_QIAA diff --git a/boards/adafruit/itsybitsy/Kconfig.defconfig b/boards/adafruit/itsybitsy/Kconfig.defconfig new file mode 100644 index 00000000000000..b637497e148694 --- /dev/null +++ b/boards/adafruit/itsybitsy/Kconfig.defconfig @@ -0,0 +1,53 @@ +# Adafruit ItsyBitsy nRF52840 Express board configuration + +# Copyright (c) 2022 Embla Flatlandsmo +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_ITSYBITSY + +config BT_CTLR + default BT + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default SERIAL + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if CONSOLE + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +# Logger cannot use itself to log +config USB_CDC_ACM_LOG_LEVEL + default 0 + +# Set USB log level to error only +config USB_DEVICE_LOG_LEVEL + default 1 + +# Wait 1500ms at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 1500 + +endif # LOG + +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +endif # BOARD_ADAFRUIT_ITSYBITSY diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840-pinctrl.dtsi b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840-pinctrl.dtsi rename to boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840-pinctrl.dtsi diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.dts b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.dts rename to boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.yaml b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml similarity index 86% rename from boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.yaml rename to boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml index a95f91e9b129ed..3e571954bf1aba 100644 --- a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.yaml +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: adafruit_itsybitsy_nrf52840 +identifier: adafruit_itsybitsy/nrf52840 name: Adafruit ItsyBitsy nRF52840 Express type: mcu arch: arm diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840_defconfig b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840_defconfig new file mode 100644 index 00000000000000..f136674fc14d20 --- /dev/null +++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Flashing +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/board.cmake b/boards/adafruit/itsybitsy/board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/board.cmake rename to boards/adafruit/itsybitsy/board.cmake diff --git a/boards/adafruit/itsybitsy/board.yml b/boards/adafruit/itsybitsy/board.yml new file mode 100644 index 00000000000000..484a68e348b8b8 --- /dev/null +++ b/boards/adafruit/itsybitsy/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_itsybitsy + vendor: adafruit + socs: + - name: nrf52840 diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/doc/img/adafruit_itsybitsy_nrf52840.jpeg b/boards/adafruit/itsybitsy/doc/img/adafruit_itsybitsy_nrf52840.jpeg similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/doc/img/adafruit_itsybitsy_nrf52840.jpeg rename to boards/adafruit/itsybitsy/doc/img/adafruit_itsybitsy_nrf52840.jpeg diff --git a/boards/adafruit/itsybitsy/doc/index.rst b/boards/adafruit/itsybitsy/doc/index.rst new file mode 100644 index 00000000000000..f4d6259ff418ce --- /dev/null +++ b/boards/adafruit/itsybitsy/doc/index.rst @@ -0,0 +1,192 @@ +.. _adafruit_itsybitsy_nrf52840: + +Adafruit ItsyBitsy nRF52840 +########################### + +Overview +******** + +The Adafruit ItsyBitsy nRF52840 Express is a small (36 mm x 18 mm) ARM +development board with an onboard RGB LED, USB port, 2 MB of QSPI flash, +and range of I/O broken out onto 21 GPIO pins. + +This development kit has the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`I2S (Inter-Integrated Sound)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. image:: img/adafruit_itsybitsy_nrf52840.jpeg + :align: center + :alt: Adafruit ItsyBitsy nRF52840 Express + +Hardware +******** +- nRF52840 ARM Cortex-M4F CPU at 64MHz +- 1 MB of flash memory and 256 KB of SRAM +- 2 MB of QSPI flash +- A user LED +- A user switch +- An RGB DotStar LED +- Native USB port +- One reset button + +Supported Features +================== + +The Adafruit ItsyBitsy nRF52840 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `Adafruit ItsyBitsy nRF52840 Express Learn site`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +LED +--- + +* LED0 (red) = P0.06 + +* LED1 (Adafruit DotStar) + + * DATA = P0.08 + + * CLK = P1.09 + +Push buttons +------------ + +* SWITCH = P0.29 + +* RESET = P0.18 + +Logging +------- + +Logging is done using the USB-CDC port. See the :zephyr:code-sample:`logging` sample +or the :zephyr:code-sample:`usb-cdc-acm-console` sample applications to see how this works. + +Testing LEDs and buttons on the Adafruit ItsyBitsy nRF52840 Express +******************************************************************* +The :zephyr:code-sample:`button` sample lets you test the buttons (switches) and the red LED. +The :zephyr:code-sample:`blinky` sample lets you test the red LED. + +The DotStar LED has been implemented as a SPI device and can be tested +with the :zephyr:code-sample:`led-apa102` sample application. + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.dts`. + +Programming and Debugging +************************* +The ItsyBitsy ships with the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +First time setup +================ +Some versions of this board were shipped with a buggy bootloader. +Ensure that the bootloader is up to date by following the +`Adafruit UF2 Bootloader update`_ tutorial. Note that this tutorial +was made for the Adafruit Feather nRF52840, but the steps to update +the bootloader are the same for the ItsyBitsy. The files for the +ItsyBitsy bootloader can be found in the `Adafruit nRF52 Bootloader repo`_. + +The building and flashing of Zephyr applications have been tested with +release 0.7.0 of the UF2 bootloader. + +Flashing +======== +Flashing is done by dragging and dropping the built Zephyr UF2-file +into the :code:`ITSY840BOOT` drive. + +#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` + sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: adafruit_itsybitsy/nrf52840 + :goals: build + :compact: + +#. Connect the ItsyBitsy to your host computer using USB + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + Drag and drop the file :code:`samples/basic/blinky/build/zephyr/zephyr.uf2` + into :code:`ITSY840BOOT` + +The device will disconnect and you should see the red LED blink. + +References +********** + +.. target-notes:: + +.. _Adafruit ItsyBitsy nRF52840 Express Learn site: + https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express + +.. _pinouts: + https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/pinouts + +.. _schematic: + https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/downloads + +.. _Adafruit UF2 Bootloader update: + https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/update-bootloader + +.. _Adafruit nRF52 Bootloader repo: + https://github.com/adafruit/Adafruit_nRF52_Bootloader/releases diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/pre_dt_board.cmake b/boards/adafruit/itsybitsy/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_nrf52840/pre_dt_board.cmake rename to boards/adafruit/itsybitsy/pre_dt_board.cmake diff --git a/boards/adafruit/itsybitsy_m4_express/Kconfig.adafruit_itsybitsy_m4_express b/boards/adafruit/itsybitsy_m4_express/Kconfig.adafruit_itsybitsy_m4_express new file mode 100644 index 00000000000000..79fa829dbee64b --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/Kconfig.adafruit_itsybitsy_m4_express @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS + select SOC_SAMD51G19A diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi rename to boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express-pinctrl.dtsi diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts rename to boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.dts diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml rename to boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml diff --git a/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig new file mode 100644 index 00000000000000..32994801245327 --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD5X_OSCULP32K_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_ARM_MPU=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_itsybitsy_m4_express/board.cmake b/boards/adafruit/itsybitsy_m4_express/board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/board.cmake rename to boards/adafruit/itsybitsy_m4_express/board.cmake diff --git a/boards/adafruit/itsybitsy_m4_express/board.yml b/boards/adafruit/itsybitsy_m4_express/board.yml new file mode 100644 index 00000000000000..7d295017fc9ef3 --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_itsybitsy_m4_express + vendor: adafruit + socs: + - name: samd51g19a diff --git a/boards/arm/adafruit_itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg b/boards/adafruit/itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg rename to boards/adafruit/itsybitsy_m4_express/doc/img/adafruit_itsybitsy_m4_express.jpg diff --git a/boards/adafruit/itsybitsy_m4_express/doc/index.rst b/boards/adafruit/itsybitsy_m4_express/doc/index.rst new file mode 100644 index 00000000000000..a25df0bf2fa6b2 --- /dev/null +++ b/boards/adafruit/itsybitsy_m4_express/doc/index.rst @@ -0,0 +1,209 @@ +.. _adafruit_itsybitsy_m4_express: + +Adafruit ItsyBitsy M4 Express +############################# + +Overview +******** + +The Adafruit ItsyBitsy M4 express is a small (36 mm x 18 mm) ARM development +board with an onboard RGB LED, USB port, 2 MiB of SPI flash, and range of I/O +broken out onto 23 GPIO pins. + +.. image:: img/adafruit_itsybitsy_m4_express.jpg + :align: center + :alt: Adafruit ItsyBitsy M4 Express + +Hardware +******** + +- ATSAMD51G19A ARM Cortex-M4 processor at 120 MHz +- 512 KiB of flash memory and 192 KiB of RAM +- 2 MiB of SPI flash +- Internal trimmed 8 MHz oscillator +- A user LED +- An RGB DotStar LED +- Native USB port +- One reset button + +Supported Features +================== + +The adafruit_itsybitsy_m4_express board configuration supports the following +hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | Nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| TRNG | on-chip | True Random Number Generator | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Unique 128 bit serial number | ++-----------+------------+------------------------------------------+ +| RTC | on-chip | Real-Time Counter | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog Timer | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig`. + +Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. +To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set +:code:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided by 7, +i.e. no more than 4500. + +Connections and IOs +=================== + +The `Adafruit Learning System`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD51 MCU is configured to use the 32 kHz internal oscillator +with the on-chip PLL generating the 120 MHz system clock. + +Serial Port +=========== + +The SAMD51 MCU has 6 SERCOM based USARTs. On the ItsyBitsy, SERCOM3 is +the Zephyr console and is available on pins 0 (RX) and 1 (TX). + +SPI Port +======== + +The SAMD51 MCU has 6 SERCOM based SPIs. On the ItsyBitsy, SERCOM1 can be put +into SPI mode and used to connect to devices over the SCK (SCLK), MO (MOSI), and +MI (MISO) pins. + +PWM +=== + +The SAMD51 has three PWM generators with up to six channels each. :code:`TCC_0` +has a resolution of 24 bits and all other generators are 16 bit. :code:`TCC_1` +pin 2 is mapped to PA18 (D7) and pin 3 is mapped to PA19 (D9). + +USB Device Port +=============== + +The SAMD51 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The ItsyBitsy ships with a the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: build + :compact: + +#. Connect the ItsyBitsy to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: flash + :compact: + + You should see "Hello World! adafruit_itsybitsy_m4_express" in your terminal. + +Debugging +========= + +In addition to the built-in bootloader, the ItsyBitsy can be flashed and +debugged using a SWD probe such as the Segger J-Link. + +#. Connect the board to the probe by connecting the :code:`SWCLK`, + :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the + ItsyBitsy to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, :code:`GND`, + and :code:`VTref` pins on the `J-Link`_. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: flash + :flash-args: -r openocd + :compact: + +#. Start debugging: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_itsybitsy_m4_express + :goals: debug + :compact: + +References +********** + +.. target-notes:: + +.. _Adafruit Learning System: + https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4 + +.. _pinouts: + https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/pinouts + +.. _schematic: + https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/downloads + +.. _J-Link: + https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_itsybitsy_m4_express/pre_dt_board.cmake b/boards/adafruit/itsybitsy_m4_express/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/pre_dt_board.cmake rename to boards/adafruit/itsybitsy_m4_express/pre_dt_board.cmake diff --git a/boards/arm/adafruit_itsybitsy_m4_express/support/openocd.cfg b/boards/adafruit/itsybitsy_m4_express/support/openocd.cfg similarity index 100% rename from boards/arm/adafruit_itsybitsy_m4_express/support/openocd.cfg rename to boards/adafruit/itsybitsy_m4_express/support/openocd.cfg diff --git a/boards/adafruit/kb2040/Kconfig.adafruit_kb2040 b/boards/adafruit/kb2040/Kconfig.adafruit_kb2040 new file mode 100644 index 00000000000000..669fddf899cafa --- /dev/null +++ b/boards/adafruit/kb2040/Kconfig.adafruit_kb2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_KB2040 + select SOC_RP2040 diff --git a/boards/adafruit/kb2040/Kconfig.defconfig b/boards/adafruit/kb2040/Kconfig.defconfig new file mode 100644 index 00000000000000..e17682abac05ac --- /dev/null +++ b/boards/adafruit/kb2040/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_KB2040 + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_KB2040 diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040-pinctrl.dtsi b/boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_kb2040/adafruit_kb2040-pinctrl.dtsi rename to boards/adafruit/kb2040/adafruit_kb2040-pinctrl.dtsi diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040.dts b/boards/adafruit/kb2040/adafruit_kb2040.dts similarity index 100% rename from boards/arm/adafruit_kb2040/adafruit_kb2040.dts rename to boards/adafruit/kb2040/adafruit_kb2040.dts diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040.yaml b/boards/adafruit/kb2040/adafruit_kb2040.yaml similarity index 100% rename from boards/arm/adafruit_kb2040/adafruit_kb2040.yaml rename to boards/adafruit/kb2040/adafruit_kb2040.yaml diff --git a/boards/arm/adafruit_kb2040/adafruit_kb2040_defconfig b/boards/adafruit/kb2040/adafruit_kb2040_defconfig similarity index 79% rename from boards/arm/adafruit_kb2040/adafruit_kb2040_defconfig rename to boards/adafruit/kb2040/adafruit_kb2040_defconfig index 6ce0691032d226..f2202a534b6ad7 100644 --- a/boards/arm/adafruit_kb2040/adafruit_kb2040_defconfig +++ b/boards/adafruit/kb2040/adafruit_kb2040_defconfig @@ -1,16 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_ADAFRUIT_KB2040=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_kb2040/board.cmake b/boards/adafruit/kb2040/board.cmake similarity index 100% rename from boards/arm/adafruit_kb2040/board.cmake rename to boards/adafruit/kb2040/board.cmake diff --git a/boards/adafruit/kb2040/board.yml b/boards/adafruit/kb2040/board.yml new file mode 100644 index 00000000000000..5fbe751090e705 --- /dev/null +++ b/boards/adafruit/kb2040/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_kb2040 + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/arm/adafruit_kb2040/doc/img/kb2040.jpg b/boards/adafruit/kb2040/doc/img/kb2040.jpg similarity index 100% rename from boards/arm/adafruit_kb2040/doc/img/kb2040.jpg rename to boards/adafruit/kb2040/doc/img/kb2040.jpg diff --git a/boards/arm/adafruit_kb2040/doc/index.rst b/boards/adafruit/kb2040/doc/index.rst similarity index 100% rename from boards/arm/adafruit_kb2040/doc/index.rst rename to boards/adafruit/kb2040/doc/index.rst diff --git a/boards/arm/adafruit_kb2040/sparkfun_pro_micro_connector.dtsi b/boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi similarity index 100% rename from boards/arm/adafruit_kb2040/sparkfun_pro_micro_connector.dtsi rename to boards/adafruit/kb2040/sparkfun_pro_micro_connector.dtsi diff --git a/boards/arm/nrf52_adafruit_feather/Kconfig b/boards/adafruit/nrf52_adafruit_feather/Kconfig similarity index 100% rename from boards/arm/nrf52_adafruit_feather/Kconfig rename to boards/adafruit/nrf52_adafruit_feather/Kconfig diff --git a/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig b/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig new file mode 100644 index 00000000000000..48cb9d7332dac1 --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 ADAFRUIT FEATHER board configuration + +# Copyright (c) 2018 LEDCity AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_ADAFRUIT_FEATHER + +config BT_CTLR + default BT + +endif # BOARD_NRF52_ADAFRUIT_FEATHER diff --git a/boards/adafruit/nrf52_adafruit_feather/Kconfig.nrf52_adafruit_feather b/boards/adafruit/nrf52_adafruit_feather/Kconfig.nrf52_adafruit_feather new file mode 100644 index 00000000000000..d2d1b26de92324 --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/Kconfig.nrf52_adafruit_feather @@ -0,0 +1,7 @@ +# nRF52 ADAFRUIT FEATHER board configuration + +# Copyright (c) 2018 LEDCity AG. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_ADAFRUIT_FEATHER + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_adafruit_feather/board.cmake b/boards/adafruit/nrf52_adafruit_feather/board.cmake similarity index 100% rename from boards/arm/nrf52_adafruit_feather/board.cmake rename to boards/adafruit/nrf52_adafruit_feather/board.cmake diff --git a/boards/arm/nrf52_adafruit_feather/board.h b/boards/adafruit/nrf52_adafruit_feather/board.h similarity index 100% rename from boards/arm/nrf52_adafruit_feather/board.h rename to boards/adafruit/nrf52_adafruit_feather/board.h diff --git a/boards/adafruit/nrf52_adafruit_feather/board.yml b/boards/adafruit/nrf52_adafruit_feather/board.yml new file mode 100644 index 00000000000000..a3d6b4274ce690 --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_adafruit_feather + vendor: adafruit + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg b/boards/adafruit/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg similarity index 100% rename from boards/arm/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg rename to boards/adafruit/nrf52_adafruit_feather/doc/img/nrf52_adafruit_feather.jpg diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst new file mode 100644 index 00000000000000..0e7680e70b86f3 --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst @@ -0,0 +1,192 @@ +.. _nrf52_adafruit_feather: + +nRF52 Adafruit Feather +###################### + +Overview +******** + +The nRF52 Adafruit Bluefruit Feather hardware provides +support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`RTC (nRF RTC System Clock)` +* UART +* GPIO +* FLASH +* RADIO (Bluetooth Low Energy) +* Segger RTT (RTT Console) + +.. figure:: img/nrf52_adafruit_feather.jpg + :align: center + :alt: nRF52 Adafruit Feather Board + + nRF52 Adafruit Feather Board (Credit: Adafruit) + +More information about the board and its features can be found at the +`Adafruit Feather nRF52 Bluefruit Learning Guide`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +- nRF52832 ARM Cortex-M4F processor at 64 MHz +- 32.768 kHz crystal oscillator +- 512 KiB flash memory and 64 KiB of SRAM +- Battery connector and charger for 3.7 V lithium polymer batteries +- Charging indicator LED +- 2 User LEDs +- Reset button +- SWD connector +- USB serial converter + +Supported Features +================== + +The nRF52 Adafruit Feather board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTT | on-chip | console | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `Adafruit Feather nRF52 Bluefruit Learning Guide`_ has detailed +information about the board including `pinouts`_ and the `schematic`_. + +LED +--- + +* LED0 (red) = P0.17 +* LED1 (blue) = P0.19 + +Push buttons +------------ + +* DFU = SW0 = P0.20 +* RESET = SW1 = P0.21/reset + +Programming and Debugging +************************* + +The ``nrf52_adafruit_feather`` board is available in two different versions: + +- `Adafruit Feather nRF52 Pro with myNewt Bootloader`_ + This board version is the recommended one to use. It has the SWD header + already populated and comes with the Mynewt serial bootloader installed by + default. + +- `Adafruit Feather nRF52 Bluefruit LE`_ + This board is identical to the board above, but the SWD header is not + populated and ships with an Arduino friendly bootloader. To be able to work + with this version a 2*5pin 0.5" SWD header (e.g. `Adafruit SWD connector`_) + needs to be soldered. + +Applications for the ``nrf52_adafruit_feather`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` +and :ref:`application_run` for more details on building and running. + +Flashing +======== + +Flashing Zephyr onto the ``nrf52_adafruit_feather`` board requires an external +J-Link programmer. The programmer is attached to the X1 SWD header. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52_adafruit_feather + :goals: build + :compact: + +#. Connect the Adafruit nRF52 Feather to your host computer using USB + +#. Run your favorite terminal program to listen for output. + + .. code-block:: console + + $ minicom -D -b 115200 + + Replace :code:`` with the port where the nRF52 Adafruit Feather + board can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52_adafruit_feather + :goals: flash + :compact: + + You should see "Hello World! nrf52_adafruit_feather" in your terminal. + + +Debugging +========= + +The ``nrf52_adafruit_feather`` board does not have an on-board J-Link debug IC +as some nRF5x development boards, however, instructions from the +:ref:`nordic_segger` page also apply to this board, with the additional step +of connecting an external debugger. + + +Testing the LEDs and buttons on the nRF52 Adafruit Feather +********************************************************** + +There are several samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +- :zephyr:code-sample:`blinky` +- :zephyr:code-sample:`button` +- :zephyr:code-sample:`fade-led` +- :zephyr:code-sample:`pwm-blinky` +- :zephyr:code-sample:`multi-thread-blinky` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/adafruit/nrf52_adafruit_feather/board.h`. + + +References +********** + +.. target-notes:: + +.. _Adafruit Feather nRF52 Bluefruit Learning Guide: https://learn.adafruit.com/bluefruit-nrf52-feather-learning-guide/introduction +.. _schematic: https://learn.adafruit.com/assets/39913 +.. _pinouts: https://cdn-learn.adafruit.com/assets/assets/000/046/210/original/Feather_NRF52_Pinout_v1.2.pdf?1504807075 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _Adafruit Feather nRF52 Bluefruit LE: https://www.adafruit.com/product/3406 +.. _Adafruit Feather nRF52 Pro with myNewt Bootloader: https://www.adafruit.com/product/3574 +.. _Adafruit SWD connector: https://www.adafruit.com/product/752 diff --git a/boards/arm/nrf52_adafruit_feather/feather_connector.dtsi b/boards/adafruit/nrf52_adafruit_feather/feather_connector.dtsi similarity index 100% rename from boards/arm/nrf52_adafruit_feather/feather_connector.dtsi rename to boards/adafruit/nrf52_adafruit_feather/feather_connector.dtsi diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi rename to boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather-pinctrl.dtsi diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.dts b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts similarity index 100% rename from boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.dts rename to boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.dts diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml similarity index 100% rename from boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml rename to boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml diff --git a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arduino_nano_33_ble/pre_dt_board.cmake b/boards/adafruit/nrf52_adafruit_feather/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_ble/pre_dt_board.cmake rename to boards/adafruit/nrf52_adafruit_feather/pre_dt_board.cmake diff --git a/boards/adafruit/qt_py_rp2040/Kconfig.adafruit_qt_py_rp2040 b/boards/adafruit/qt_py_rp2040/Kconfig.adafruit_qt_py_rp2040 new file mode 100644 index 00000000000000..7cde06cb166554 --- /dev/null +++ b/boards/adafruit/qt_py_rp2040/Kconfig.adafruit_qt_py_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Kelly Lord +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_QT_PY_RP2040 + select SOC_RP2040 diff --git a/boards/adafruit/qt_py_rp2040/Kconfig.defconfig b/boards/adafruit/qt_py_rp2040/Kconfig.defconfig new file mode 100644 index 00000000000000..22d40318634b6f --- /dev/null +++ b/boards/adafruit/qt_py_rp2040/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2022 Peter Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADAFRUIT_QT_PY_RP2040 + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif #I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_ADAFRUIT_QT_PY_RP2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040-pinctrl.dtsi diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.dts rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.yaml b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040.yaml rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml diff --git a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040_defconfig b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig similarity index 78% rename from boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040_defconfig rename to boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig index d0987d6025f518..f2202a534b6ad7 100644 --- a/boards/arm/adafruit_qt_py_rp2040/adafruit_qt_py_rp2040_defconfig +++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040_defconfig @@ -1,16 +1,12 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_ADAFRUIT_QT_PY_RP2040=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_qt_py_rp2040/board.cmake b/boards/adafruit/qt_py_rp2040/board.cmake similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/board.cmake rename to boards/adafruit/qt_py_rp2040/board.cmake diff --git a/boards/adafruit/qt_py_rp2040/board.yml b/boards/adafruit/qt_py_rp2040/board.yml new file mode 100644 index 00000000000000..e07cab669c6dba --- /dev/null +++ b/boards/adafruit/qt_py_rp2040/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_qt_py_rp2040 + vendor: adafruit + socs: + - name: rp2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/doc/img/qtpy_rp2040.jpg b/boards/adafruit/qt_py_rp2040/doc/img/qtpy_rp2040.jpg similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/doc/img/qtpy_rp2040.jpg rename to boards/adafruit/qt_py_rp2040/doc/img/qtpy_rp2040.jpg diff --git a/boards/arm/adafruit_qt_py_rp2040/doc/index.rst b/boards/adafruit/qt_py_rp2040/doc/index.rst similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/doc/index.rst rename to boards/adafruit/qt_py_rp2040/doc/index.rst diff --git a/boards/arm/adafruit_qt_py_rp2040/seeed_xiao_connector.dtsi b/boards/adafruit/qt_py_rp2040/seeed_xiao_connector.dtsi similarity index 100% rename from boards/arm/adafruit_qt_py_rp2040/seeed_xiao_connector.dtsi rename to boards/adafruit/qt_py_rp2040/seeed_xiao_connector.dtsi diff --git a/boards/adafruit/trinket_m0/Kconfig.adafruit_trinket_m0 b/boards/adafruit/trinket_m0/Kconfig.adafruit_trinket_m0 new file mode 100644 index 00000000000000..3bb901530593b3 --- /dev/null +++ b/boards/adafruit/trinket_m0/Kconfig.adafruit_trinket_m0 @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADAFRUIT_TRINKET_M0 + select SOC_SAMD21E18A diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0-pinctrl.dtsi b/boards/adafruit/trinket_m0/adafruit_trinket_m0-pinctrl.dtsi similarity index 100% rename from boards/arm/adafruit_trinket_m0/adafruit_trinket_m0-pinctrl.dtsi rename to boards/adafruit/trinket_m0/adafruit_trinket_m0-pinctrl.dtsi diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts b/boards/adafruit/trinket_m0/adafruit_trinket_m0.dts similarity index 100% rename from boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.dts rename to boards/adafruit/trinket_m0/adafruit_trinket_m0.dts diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.yaml b/boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml similarity index 100% rename from boards/arm/adafruit_trinket_m0/adafruit_trinket_m0.yaml rename to boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml diff --git a/boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig b/boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig new file mode 100644 index 00000000000000..dcbfbd007df50f --- /dev/null +++ b/boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/adafruit_trinket_m0/board.cmake b/boards/adafruit/trinket_m0/board.cmake similarity index 100% rename from boards/arm/adafruit_trinket_m0/board.cmake rename to boards/adafruit/trinket_m0/board.cmake diff --git a/boards/adafruit/trinket_m0/board.yml b/boards/adafruit/trinket_m0/board.yml new file mode 100644 index 00000000000000..6d7a783ae3e3f4 --- /dev/null +++ b/boards/adafruit/trinket_m0/board.yml @@ -0,0 +1,5 @@ +board: + name: adafruit_trinket_m0 + vendor: adafruit + socs: + - name: samd21e18a diff --git a/boards/arm/adafruit_trinket_m0/doc/img/adafruit_trinket_m0.jpg b/boards/adafruit/trinket_m0/doc/img/adafruit_trinket_m0.jpg similarity index 100% rename from boards/arm/adafruit_trinket_m0/doc/img/adafruit_trinket_m0.jpg rename to boards/adafruit/trinket_m0/doc/img/adafruit_trinket_m0.jpg diff --git a/boards/adafruit/trinket_m0/doc/index.rst b/boards/adafruit/trinket_m0/doc/index.rst new file mode 100644 index 00000000000000..4e23822b242c43 --- /dev/null +++ b/boards/adafruit/trinket_m0/doc/index.rst @@ -0,0 +1,170 @@ +.. _adafruit_trinket_m0: + +Adafruit Trinket M0 +################### + +Overview +******** + +The Adafruit Trinket M0 is a tiny (27 mm x 15 mm) ARM development +board with an onboard RGB LED, USB port, and range of I/O broken out +onto 5 pins. + +.. image:: img/adafruit_trinket_m0.jpg + :align: center + :alt: Adafruit Trinket M0 + +Hardware +******** + +- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- Internal trimmed 8 MHz oscillator +- A user LED +- An RGB DotStar LED +- Native USB port +- One reset button + +Supported Features +================== + +The adafruit_trinket_m0 board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig`. + +Connections and IOs +=================== + +The `Adafruit Trinket M0 Learn site`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 8 MHz internal oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the Trinket, SERCOM0 is +the Zephyr console and is available on pins 3 (RX) and 4 (TX). +SERCOM2 is available on pins 2 (RX) and 0 (TX). + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Trinket, SERCOM1 is +used to drive the DotStar RGB LED. SERCOM0 can be put into SPI mode +and used to connect to devices over pin 2 (MISO), pin 4 (MOSI), and +pin 3 (SCK). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Trinket M0 ships the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_trinket_m0 + :goals: build + :compact: + +#. Connect the Trinket M0 to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adafruit_trinket_m0 + :goals: flash + :compact: + + You should see "Hello World! adafruit_trinket_m0" in your terminal. + +References +********** + +.. target-notes:: + +.. _Adafruit Trinket M0 Learn site: + https://learn.adafruit.com/adafruit-trinket-m0-circuitpython-arduino + +.. _pinouts: + https://learn.adafruit.com/assets/49778 + +.. _schematic: + https://learn.adafruit.com/assets/45723 diff --git a/boards/arm/adafruit_trinket_m0/pre_dt_board.cmake b/boards/adafruit/trinket_m0/pre_dt_board.cmake similarity index 100% rename from boards/arm/adafruit_trinket_m0/pre_dt_board.cmake rename to boards/adafruit/trinket_m0/pre_dt_board.cmake diff --git a/boards/adi/eval_adin1110ebz/Kconfig.adi_eval_adin1110ebz b/boards/adi/eval_adin1110ebz/Kconfig.adi_eval_adin1110ebz new file mode 100644 index 00000000000000..366fff3086b66f --- /dev/null +++ b/boards/adi/eval_adin1110ebz/Kconfig.adi_eval_adin1110ebz @@ -0,0 +1,5 @@ +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADI_EVAL_ADIN1110EBZ + select SOC_STM32L4S5XX diff --git a/boards/adi/eval_adin1110ebz/Kconfig.defconfig b/boards/adi/eval_adin1110ebz/Kconfig.defconfig new file mode 100644 index 00000000000000..9c33c1d288d63b --- /dev/null +++ b/boards/adi/eval_adin1110ebz/Kconfig.defconfig @@ -0,0 +1,30 @@ +# ADI EVAL-ADIN1110EBZ board configuration + +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADI_EVAL_ADIN1110EBZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config MDIO_INIT_PRIORITY + default 81 + depends on MDIO + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +config MEMC + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_ADI_EVAL_ADIN1110EBZ diff --git a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.dts b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.dts rename to boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.dts diff --git a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.yaml b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz.yaml rename to boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig new file mode 100644 index 00000000000000..c19a47618d1bb7 --- /dev/null +++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin1110ebz/arduino_r3_connector.dtsi b/boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/arduino_r3_connector.dtsi rename to boards/adi/eval_adin1110ebz/arduino_r3_connector.dtsi diff --git a/boards/arm/adi_eval_adin1110ebz/board.cmake b/boards/adi/eval_adin1110ebz/board.cmake similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/board.cmake rename to boards/adi/eval_adin1110ebz/board.cmake diff --git a/boards/adi/eval_adin1110ebz/board.yml b/boards/adi/eval_adin1110ebz/board.yml new file mode 100644 index 00000000000000..e5af49e3f351f4 --- /dev/null +++ b/boards/adi/eval_adin1110ebz/board.yml @@ -0,0 +1,5 @@ +board: + name: adi_eval_adin1110ebz + vendor: adi + socs: + - name: stm32l4s5xx diff --git a/boards/arm/adi_eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp b/boards/adi/eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp rename to boards/adi/eval_adin1110ebz/doc/img/adi_eval_adin1110ebz.webp diff --git a/boards/adi/eval_adin1110ebz/doc/index.rst b/boards/adi/eval_adin1110ebz/doc/index.rst new file mode 100644 index 00000000000000..92b70f0c1c06a1 --- /dev/null +++ b/boards/adi/eval_adin1110ebz/doc/index.rst @@ -0,0 +1,183 @@ +.. _adi_eval_adin1110ebz: + +ADI EVAL-ADIN1110EVB Evaluation board +##################################### + +Overview +******** + +The EVAL-ADIN1110EBZ is a flexible platform enabling quick evaluation of the ADIN1110, robust, +low power 10BASE-T1L MAC-PHY. It provides 10Mbit per second Single Pair Ethernet (SPE) connections +with devices across 1.7km of cable. + +The evaluation board offers two modes of operation for maximum flexibility. Connected to a PC +via USB port, the full set of ADIN1110 register settings and features such as link quality +monitoring and diagnostics can be accessed over the USB using serial command interface. +The board also provides an Arduino interface. + +Alternatively, the board can operate in stand-alone mode where it is configured by setting hardware +configuration links and switches. On-board LEDs provide status indication. + +The SPI interface provides configuration and data access to the ADIN1110. + +A small prototyping area and test points are provided for experimentation with alternative cable +connection topologies including isolation transformers and/or power coupling inductors. + +.. figure:: img/adi_eval_adin1110ebz.webp + :align: center + :alt: ADI EVAL-ADIN1110EBZ + + ADI EVAL-ADIN1110EBZ (Credit: Analog Devices, Inc.) + +.. important:: + + S201 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr + default board configuration is set to work as "Generic SPI, CRC enabled", + so the S201 DIP switches must be set as ``SPI_CFG0 OFF`` and ``SPI_CFG1 ON``. + An inconsistent S201 DIP switches configuration will halt the boot. + +Hardware +******** + +The ADI EVAL-ADIN1110EBZ hardware features list is available here: + +https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide + + +Supported Features +================== + +The ADI adi_eval_adin1110ebz board configuration supports the +following hardware features: + ++--------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++==============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++--------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++--------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++--------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++--------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++--------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++--------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++--------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++--------------+------------+-------------------------------------+ +| ADIN1110 | spi | adin1110 10BASE-T1L mac/phy | ++--------------+------------+-------------------------------------+ +| FT232 | uart | usb-uart | ++--------------+------------+-------------------------------------+ +| ADT7422 | i2c | temperature sensor | ++--------------+------------+-------------------------------------+ +| ISS66WVE4M16 | fmc | 8MB PSRAM | ++--------------+------------+-------------------------------------+ + + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig` + + +Connections and IOs +=================== + +ADI ADIN1110EBZ evaluation board has 7 GPIO controllers (from A to G). These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For mode details please refer to `EVAL-ADIN1110EBZ User Guide `_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (UART to FT232) +- UART_4 TX/RX : PA0/PA1 (Arduino Serial) +- I2C1 SCL/SDA : PG14/PG13 (Arduino I2C) +- I2C3 SCL/SDA : PG7/PG8 (Sensor I2C bus) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Simple SPI to nor Flash) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (ADIN1110) +- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (Arduino SPI) +- LD1 : PC13 (Green LED) +- LD2 : PE2 (Red LED) +- LD3 : PE6 (Yellow LED) +- LD4 : PG15 (Blue LED) +- PSRAM : PE0/PE1/PF0-PF15/PG0-PG5/PD11-PD13/PE3/PE4 + PD14/PD15/PD9/PD1/PE7-PE15/PD8-PD10 + + +System Clock +------------ + +EVAL-ADIN1110EBZ System Clock could be driven by an internal or external oscillator, as well as +the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the +16MHz high speed internal oscillator. + +Serial Port +----------- + +EVAL-ADIN1110EBZ has 2 U(S)ARTs. The Zephyr console output is assigned to UART1 that is connected +to a FT232, so available through Micro USB connector. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +EVAL-ADIN1110EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is +supported by the openocd version included in Zephyr SDK. + +Flashing an application to Discovery kit +----------------------------------------- + +Connect the EVAL-ADIN1110EBZ to your host computer using the USB port, then run a serial host +program to connect with your ADI board. For example: + +.. code-block:: console + + $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN1110EBZ_AVAS_XXXXXX-if00-port0 + +where XXXXXX is the serial number of the connected device. +Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin1110ebz + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! adi_eval_adin1110ebz + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin1110ebz + :maybe-skip-config: + :goals: debug + +.. _EVAL-ADIN1110EBZ evaluation board website: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin1110.html + +.. _EVAL-ADIN1110EBZ board User Guide: + https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide + +.. _ADIN1110 Datasheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adin1110.pdf + +.. _STM32L4S5QII3P reference manual: + https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_eval_adin1110ebz/pre_dt_board.cmake b/boards/adi/eval_adin1110ebz/pre_dt_board.cmake similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/pre_dt_board.cmake rename to boards/adi/eval_adin1110ebz/pre_dt_board.cmake diff --git a/boards/arm/adi_eval_adin1110ebz/support/openocd.cfg b/boards/adi/eval_adin1110ebz/support/openocd.cfg similarity index 100% rename from boards/arm/adi_eval_adin1110ebz/support/openocd.cfg rename to boards/adi/eval_adin1110ebz/support/openocd.cfg diff --git a/boards/adi/eval_adin2111ebz/Kconfig.adi_eval_adin2111ebz b/boards/adi/eval_adin2111ebz/Kconfig.adi_eval_adin2111ebz new file mode 100644 index 00000000000000..9b051ece984485 --- /dev/null +++ b/boards/adi/eval_adin2111ebz/Kconfig.adi_eval_adin2111ebz @@ -0,0 +1,5 @@ +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADI_EVAL_ADIN2111EBZ + select SOC_STM32L4S5XX diff --git a/boards/adi/eval_adin2111ebz/Kconfig.defconfig b/boards/adi/eval_adin2111ebz/Kconfig.defconfig new file mode 100644 index 00000000000000..ae255907083f35 --- /dev/null +++ b/boards/adi/eval_adin2111ebz/Kconfig.defconfig @@ -0,0 +1,34 @@ +# ADI EVAL-ADIN2111EBZ board configuration + +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADI_EVAL_ADIN2111EBZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config MDIO_INIT_PRIORITY + default 81 + depends on MDIO + +config PHY_INIT_PRIORITY + default 82 + depends on NET_L2_ETHERNET && ETH_DRIVER + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_ADIN2111 + +config NET_IF_MAX_IPV4_COUNT + default 2 + +endif # ETH_ADIN2111 + +endif # NETWORKING + +endif # BOARD_ADI_EVAL_ADIN2111EBZ diff --git a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.dts b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.dts rename to boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.dts diff --git a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.yaml b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz.yaml rename to boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig new file mode 100644 index 00000000000000..c19a47618d1bb7 --- /dev/null +++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin2111ebz/board.cmake b/boards/adi/eval_adin2111ebz/board.cmake similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/board.cmake rename to boards/adi/eval_adin2111ebz/board.cmake diff --git a/boards/adi/eval_adin2111ebz/board.yml b/boards/adi/eval_adin2111ebz/board.yml new file mode 100644 index 00000000000000..0151d544acab44 --- /dev/null +++ b/boards/adi/eval_adin2111ebz/board.yml @@ -0,0 +1,5 @@ +board: + name: adi_eval_adin2111ebz + vendor: adi + socs: + - name: stm32l4s5xx diff --git a/boards/arm/adi_eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp b/boards/adi/eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp rename to boards/adi/eval_adin2111ebz/doc/img/adi_eval_adin2111ebz.webp diff --git a/boards/adi/eval_adin2111ebz/doc/index.rst b/boards/adi/eval_adin2111ebz/doc/index.rst new file mode 100644 index 00000000000000..c88e6d520edc6e --- /dev/null +++ b/boards/adi/eval_adin2111ebz/doc/index.rst @@ -0,0 +1,184 @@ +.. _adi_eval_adin2111ebz: + +ADI EVAL-ADIN2111EVB Evaluation board +##################################### + +Overview +******** + +The EVAL-ADIN2111EBZ is a flexible platform enabling quick evaluation of the ADIN2111, robust, +low power 10BASE-T1L 2-Port Ethernet switch. The evaluation board provides 2 10BASE-T1L channels +with 10Mbit per second Single Pair Ethernet (SPE) connections reaching up to 1.7km of link distance. + +The ADIN2111 internal switch can be configured in store and forward mode between the two 10BASE-T1L +channels and the SPI host. Cut through mode is also available between Port 1 and Port 2 and can +be used without the need of the SPI host (unmanaged configuration). + +The evaluation board offers two modes of operation for maximum flexibility: Connected to a PC +via USB port, the full set of ADIN2111 register settings and features such as link quality +monitoring and diagnostics can be accessed over the USB using the serial command interface +implemented in the evaluation firmware. + +Alternatively, the board can operate in cut-through mode between Port 1 and Port 2 (unmanaged +configuration without firmware) where the EVAL-ADIN2111EBZ acts as a network switch forwarding +packets between the 2x 10BASE-T1L ports. The 2x links are configured by setting the ADIN2111 +hardware configuration pins jumper and switches. The 2x On-board Activity LEDs provide Link +activity status indication for each port. + +Custom firmware can also be developed and the ADIN2111 driver support package includes simple +project examples to start a custom implementation. + +The SPI interface provides access to the management registers required for the switch configuration, +the 2 PHYs configuration and data exchange between SPI host and ports. + +.. important:: + + S1 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr + default board configuration is set to work as "Generic SPI, CRC enabled", + so the S1 DIP switches must be set as ``SPI_CFG0 OFF and SPI_CFG1 OFF``. + An inconsistent S1 DIP switches configuration will halt the boot. + +.. figure:: img/adi_eval_adin2111ebz.webp + :align: center + :alt: ADI EVAL-ADIN2111EBZ + + ADI EVAL-ADIN2111EBZ (Credit: Analog Devices, Inc.) + +Hardware +******** + +The ADI EVAL-ADIN2111EBZ hardware features list is available here: + +https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide + + +Supported Features +================== + +The ADI adi_eval_adin2111ebz board configuration supports the +following hardware features: + ++--------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++==============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++--------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++--------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++--------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++--------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++--------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++--------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++--------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++--------------+------------+-------------------------------------+ +| ADIN2111 | spi | adin2111 10BASE-T1L mac/phy | ++--------------+------------+-------------------------------------+ +| FT232 | uart | usb-uart | ++--------------+------------+-------------------------------------+ + + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig` + + +Connections and IOs +=================== + +ADI ADIN2111EBZ evaluation board has 7 GPIO controllers (from A to G). +These controllers are responsible for pin muxing, input/output, pull-up, etc. + +For mode details please refer to `EVAL-ADIN2111EBZ User Guide `_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (UART to FT232, console) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (SPI to external nor flash IS25LP128) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (SPI to external ADIN2111) +- LED1 : POWER (Green LED) +- UC_LED1 : PB6 (Blue LED) +- MOD LED1 : PE2 (SR LED) +- MOD LED2 : PE6 (BG LED) +- NET LED1 : PB10 (SR LED) +- NET LED2 : PB11 (BG LED) + + +System Clock +------------ + +EVAL-ADIN2111EBZ System Clock could be driven by an internal or external oscillator, as well as the +main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the +16MHz high speed internal oscillator. + +Serial Port +----------- + +EVAL-ADIN2111EBZ has 1 U(S)ART. The Zephyr console output is assigned to UART1 that is connected +to a FT232, available through Micro USB connector. Default settings are 115200 8N1. +Same UART1 TX and RX cmos signals are available before the FT232, at P9 connector. + + +Programming and Debugging +************************* + +Flashing +======== + +EVAL-ADIN2111EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is +supported by the openocd version included in Zephyr SDK. + +Flashing an application to Discovery kit +----------------------------------------- + +Connect the EVAL-ADIN2111EBZ to your host computer using the USB port, then run a serial host +program to connect with your ADI board. For example: + +.. code-block:: console + + $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN2111EBZ_XXXXXX-12-if00-port0 + +where XXXXXX is the serial number of the connected device. +Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin2111ebz + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! adi_eval_adin2111ebz + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_eval_adin2111ebz + :maybe-skip-config: + :goals: debug + +.. _EVAL-ADIN2111EBZ evaluation board website: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin2111.html + +.. _EVAL-ADIN2111EBZ board User Guide: + https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide + +.. _ADIN2111 Datasheet: + https://www.analog.com/media/en/technical-documentation/data-sheets/adin2111.pdf + +.. _STM32L4S5QII3P reference manual: + https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_eval_adin2111ebz/pre_dt_board.cmake b/boards/adi/eval_adin2111ebz/pre_dt_board.cmake similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/pre_dt_board.cmake rename to boards/adi/eval_adin2111ebz/pre_dt_board.cmake diff --git a/boards/arm/adi_eval_adin2111ebz/support/openocd.cfg b/boards/adi/eval_adin2111ebz/support/openocd.cfg similarity index 100% rename from boards/arm/adi_eval_adin2111ebz/support/openocd.cfg rename to boards/adi/eval_adin2111ebz/support/openocd.cfg diff --git a/boards/adi/index.rst b/boards/adi/index.rst new file mode 100644 index 00000000000000..1627e65cb70100 --- /dev/null +++ b/boards/adi/index.rst @@ -0,0 +1,10 @@ +.. _boards-adi: + +Analog Devices, Inc. +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/adi/sdp_k1/Kconfig.adi_sdp_k1 b/boards/adi/sdp_k1/Kconfig.adi_sdp_k1 new file mode 100644 index 00000000000000..b48600e49fbdd4 --- /dev/null +++ b/boards/adi/sdp_k1/Kconfig.adi_sdp_k1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADI_SDP_K1 + select SOC_STM32F469XX diff --git a/boards/adi/sdp_k1/Kconfig.defconfig b/boards/adi/sdp_k1/Kconfig.defconfig new file mode 100644 index 00000000000000..22cac53aa50e1b --- /dev/null +++ b/boards/adi/sdp_k1/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ADI SDP-K1 board configuration + +# Copyright (c) 2024 BayLibre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ADI_SDP_K1 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_ADI_SDP_K1 diff --git a/boards/arm/adi_sdp_k1/adi_sdp_k1.dts b/boards/adi/sdp_k1/adi_sdp_k1.dts similarity index 100% rename from boards/arm/adi_sdp_k1/adi_sdp_k1.dts rename to boards/adi/sdp_k1/adi_sdp_k1.dts diff --git a/boards/arm/adi_sdp_k1/adi_sdp_k1.yaml b/boards/adi/sdp_k1/adi_sdp_k1.yaml similarity index 100% rename from boards/arm/adi_sdp_k1/adi_sdp_k1.yaml rename to boards/adi/sdp_k1/adi_sdp_k1.yaml diff --git a/boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig b/boards/adi/sdp_k1/adi_sdp_k1_defconfig similarity index 84% rename from boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig rename to boards/adi/sdp_k1/adi_sdp_k1_defconfig index 94a8f52809e7ec..c729b83e3d0506 100644 --- a/boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig +++ b/boards/adi/sdp_k1/adi_sdp_k1_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F469XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/adi_sdp_k1/arduino_r3_connector.dtsi b/boards/adi/sdp_k1/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/adi_sdp_k1/arduino_r3_connector.dtsi rename to boards/adi/sdp_k1/arduino_r3_connector.dtsi diff --git a/boards/arm/adi_sdp_k1/board.cmake b/boards/adi/sdp_k1/board.cmake similarity index 100% rename from boards/arm/adi_sdp_k1/board.cmake rename to boards/adi/sdp_k1/board.cmake diff --git a/boards/adi/sdp_k1/board.yml b/boards/adi/sdp_k1/board.yml new file mode 100644 index 00000000000000..c659c3b14c8e9d --- /dev/null +++ b/boards/adi/sdp_k1/board.yml @@ -0,0 +1,5 @@ +board: + name: adi_sdp_k1 + vendor: adi + socs: + - name: stm32f469xx diff --git a/boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1.webp b/boards/adi/sdp_k1/doc/img/adi_sdp_k1.webp similarity index 100% rename from boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1.webp rename to boards/adi/sdp_k1/doc/img/adi_sdp_k1.webp diff --git a/boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_120pin.webp b/boards/adi/sdp_k1/doc/img/adi_sdp_k1_120pin.webp similarity index 100% rename from boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_120pin.webp rename to boards/adi/sdp_k1/doc/img/adi_sdp_k1_120pin.webp diff --git a/boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_arduino.webp b/boards/adi/sdp_k1/doc/img/adi_sdp_k1_arduino.webp similarity index 100% rename from boards/arm/adi_sdp_k1/doc/img/adi_sdp_k1_arduino.webp rename to boards/adi/sdp_k1/doc/img/adi_sdp_k1_arduino.webp diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst new file mode 100644 index 00000000000000..1f6f918e0a6cff --- /dev/null +++ b/boards/adi/sdp_k1/doc/index.rst @@ -0,0 +1,183 @@ +.. _adi_sdp_k1: + +ADI SDP-K1 +########## + +Overview +******** + +The EVAL-SDP-CK1Z (SDP-K1) controller board is a system demonstration platform +(SDP) from Analog Devices designed to connect to evaluation shields containing +ADI components. + +- STM32 microcontroller in BGA216 package +- USB 2.0 device with USB-C connector +- USB debug interface supporting CMSIS-DAP through a NXP Freescale + microcontroller +- Flexible board power supply + - USB VBUS 5 V max. 500 mA + - 5.5mm DC power jack 7 - 12 V min. 300 mA + - VIN from Arduino* compatible connectors + - VIN from 120-pin connector 5 V min. 300 mA +- 3 color LEDs (green, orange, red) and 1 status LED +- One push-buttons: RESET +- 16MB SDRAM +- Arduino UNO and 120-pin SDP connectors + +.. figure:: img/adi_sdp_k1.webp + :align: center + :alt: ADI SDP-K1 + + ADI SDP-K1 (Credit: Analog Devices, Inc.) + +More information about the board can be found on the `ADI SDP-K1 website`_. + +Hardware +******** + +ADI SDP-K1 provides the following hardware components: + +- STM32F469NIH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD of 1.8 V or 3.3 V +- 2 MB Flash +- 384 KB SRAM +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- LCD TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (6) +- 1xSAI (serial audio interface) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F469NI can be found here: + - `STM32F469NI product page`_ + - `STM32F469 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f469i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/adi/sdp_k1/adi_sdp_k1_defconfig` + +Pin Mapping +=========== + +For more details please refer to `EVAL-SDP-CK1Z User Guide`_. + +Arduino UNO headers +------------------- + +.. figure:: img/adi_sdp_k1_arduino.webp + :align: center + :alt: ADI SDP-K1 Arduino UNO headers pinout + + ADI SDP-K1 (Credit: Analog Devices, Inc.) + +120-pin SDP connector +--------------------- + +.. figure:: img/adi_sdp_k1_120pin.webp + :align: center + :alt: ADI SDP-K1 120-pin SDP connector pinout + + ADI SDP-K1 (Credit: Analog Devices, Inc.) + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_5 TX/RX : P2 (DAPLink USB-C) +- UART_5 TX/RX : P8 (DAPLink two position through hole) +- LED1 : DS6 (Red) +- LED2 : DS5 (Orange) +- LED3 : DS4 (Green) +- LED4 : DS4 (Status) + +Programming and Debugging +************************* + +The ADI SDP-K1 be programmed over USB using the DAPLink firmware running on an +embedded NXP Freescale microcontroller or a 10-pin ``DEBUG`` header connected +to a STLINK debugger. + +DAPLink exposes a storage device, as well as USB HID and CDC Endpoints, to the +host. For more details please refer to the `Official DAPLink website`_. + +Flashing +======== + +Flashing an application with a STLINK debugger +---------------------------------------------- + +First, connect the STLINK debugger to your host computer using the Micro-USB port. +Then attach the debugger to the 10-pin ``DEBUG`` header on the SDP-K1. Finally +connect the SDP-K1 to your host computer using the USB-C port. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/serial/by-id/usb-ARM_DAPLink_CMSIS-DAP_<...> + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adi_sdp_k1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! adi_sdp_k1 + +Debugging +========= + +.. _ADI SDP-K1 website: + https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/sdp-k1.html + +.. _EVAL-SDP-CK1Z User Guide: + https://www.analog.com/media/en/technical-documentation/user-guides/EVAL-SDP-CK1Z-UG-1539.pdf + +.. _STM32F469NI product page: + https://www.st.com/en/microcontrollers/stm32f469ni.html + +.. _STM32F469 reference manual: + https://www.st.com/resource/en/reference_manual/dm00127514.pdf + +.. _Official DAPLink website: + https://daplink.io/ diff --git a/boards/arm/adi_sdp_k1/revision.cmake b/boards/adi/sdp_k1/revision.cmake similarity index 100% rename from boards/arm/adi_sdp_k1/revision.cmake rename to boards/adi/sdp_k1/revision.cmake diff --git a/boards/arm/adi_sdp_k1/support/openocd.cfg b/boards/adi/sdp_k1/support/openocd.cfg similarity index 100% rename from boards/arm/adi_sdp_k1/support/openocd.cfg rename to boards/adi/sdp_k1/support/openocd.cfg diff --git a/boards/alientek/index.rst b/boards/alientek/index.rst new file mode 100644 index 00000000000000..f124ce93459efe --- /dev/null +++ b/boards/alientek/index.rst @@ -0,0 +1,10 @@ +.. _boards-alientek: + +Alientek +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/alientek/pandora_stm32l475/Kconfig.pandora_stm32l475 b/boards/alientek/pandora_stm32l475/Kconfig.pandora_stm32l475 new file mode 100644 index 00000000000000..1d42c17a83d4c5 --- /dev/null +++ b/boards/alientek/pandora_stm32l475/Kconfig.pandora_stm32l475 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Tisilicon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PANDORA_STM32L475 + select SOC_STM32L475XX diff --git a/boards/arm/pandora_stm32l475/board.cmake b/boards/alientek/pandora_stm32l475/board.cmake similarity index 100% rename from boards/arm/pandora_stm32l475/board.cmake rename to boards/alientek/pandora_stm32l475/board.cmake diff --git a/boards/alientek/pandora_stm32l475/board.yml b/boards/alientek/pandora_stm32l475/board.yml new file mode 100644 index 00000000000000..725d13c5f305a5 --- /dev/null +++ b/boards/alientek/pandora_stm32l475/board.yml @@ -0,0 +1,5 @@ +board: + name: pandora_stm32l475 + vendor: alientek + socs: + - name: stm32l475xx diff --git a/boards/arm/pandora_stm32l475/doc/img/pandora_stm32l475.jpg b/boards/alientek/pandora_stm32l475/doc/img/pandora_stm32l475.jpg similarity index 100% rename from boards/arm/pandora_stm32l475/doc/img/pandora_stm32l475.jpg rename to boards/alientek/pandora_stm32l475/doc/img/pandora_stm32l475.jpg diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst new file mode 100644 index 00000000000000..cee292e1e56acb --- /dev/null +++ b/boards/alientek/pandora_stm32l475/doc/index.rst @@ -0,0 +1,214 @@ +.. _pandora_stm32l475_board: + +Alientek STM32L475 Pandora +########################## + +Overview +******** + +The STM32L475 Pandora board features an ARM Cortex-M4 based STM32L475VE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32L475 Pandora board: + + +- STM32L475Vx microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Three different interfaces supported on USB: + + - Virtual com port + - Mass storage + - Debug port + +- Pushbutton (reset) +- Four directions Joystick with selection +- USB OTG FS with micro-AB connector +- SAI Audio DAC, Stereo with output jack +- Digital microphone, accelerometer, magnetometer and gyroscope MEMS +- 128-Mbit Quad-SPI Flash memory +- MCU current ammeter with 4 ranges and auto-calibration +- Connector for external board or RF-EEPROM +- Four power supply options: + - ST-LINK/V2-1 + - USB FS connector + - External 5 V + - CR2032 battery (not provided) + +.. image:: img/pandora_stm32l475.jpg + :align: center + :alt: STM32L475 Pandora + +More information about the board can be found at the `STM32L475 Pandora website`_. + +Hardware +******** + +The STM32L475VE SoC provides the following hardware features: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- 16x timers: + - 2x 16-bit advanced motor-control + - 2x 32-bit and 7x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 82 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +Supported Features +================== + +The Zephyr stm32l475ve_pandora board configuration supports the following hardware features: + ++-----------+------------+----------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==============================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+----------------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+----------------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+----------------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------------------------------+ +| I2C | on-chip | I2C-AHT10(Temperature and humidity sensor) | +| | | I2C-ICM2068(light environment sensor) | ++-----------+------------+----------------------------------------------+ +| I2S | on-chip | I2S-ES8388(Audio Decoder) | ++-----------+------------+----------------------------------------------+ +| USB | on-chip | I2S-OTG | ++-----------+------------+----------------------------------------------+ +| SDIO | on-chip | SDIO-AP6181(WIFI) | ++-----------+------------+----------------------------------------------+ +| SPI | on-chip | LCD-TFT | ++-----------+------------+----------------------------------------------+ +| QSPI NOR | on-chip | flash | ++-----------+------------+----------------------------------------------+ +| IR-RX/TX | on-board | Infrared Receiver(38Khz)/Transmitter | ++-----------+------------+----------------------------------------------+ +| STLINK-V2 | on-board | STLINK-V2 Debugger | ++-----------+------------+----------------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig` + + +Connections and IOs +=================== + +STM32L475 Pandora Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L475 Pandora board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- LED_R : PE7 +- LED_G : PE8 +- LED_B : PE9 + +System Clock +------------ + +STM32L475 Pandora System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +STM32L475 Pandora board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +STM32L475 Pandora board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32L475 Pandora +-------------------------------------------- + +Connect the STM32L475 Pandora to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l475ve_pandora + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l475ve_pandora + :maybe-skip-config: + :goals: debug + +.. _STM32L475 Pandora website: + http://www.openedv.com/docs/boards/iot/zdyz_panduola.html + +.. _STM32L475 Pandora board User Manual: + http://www.openedv.com/thread-284556-1-1.html diff --git a/boards/arm/pandora_stm32l475/pandora_stm32l475.dts b/boards/alientek/pandora_stm32l475/pandora_stm32l475.dts similarity index 100% rename from boards/arm/pandora_stm32l475/pandora_stm32l475.dts rename to boards/alientek/pandora_stm32l475/pandora_stm32l475.dts diff --git a/boards/arm/pandora_stm32l475/pandora_stm32l475.yaml b/boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml similarity index 100% rename from boards/arm/pandora_stm32l475/pandora_stm32l475.yaml rename to boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml diff --git a/boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig b/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig similarity index 85% rename from boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig rename to boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig index 6b76862a311973..82ee7285d52d8a 100644 --- a/boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig +++ b/boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L475XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/pandora_stm32l475/support/openocd.cfg b/boards/alientek/pandora_stm32l475/support/openocd.cfg similarity index 100% rename from boards/arm/pandora_stm32l475/support/openocd.cfg rename to boards/alientek/pandora_stm32l475/support/openocd.cfg diff --git a/boards/altr/index.rst b/boards/altr/index.rst new file mode 100644 index 00000000000000..83220f8c905bc1 --- /dev/null +++ b/boards/altr/index.rst @@ -0,0 +1,10 @@ +.. _boards-altera: + +Altera Corporation +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/altr/max10/Kconfig.altera_max10 b/boards/altr/max10/Kconfig.altera_max10 new file mode 100644 index 00000000000000..b0b39da844877c --- /dev/null +++ b/boards/altr/max10/Kconfig.altera_max10 @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +config BOARD_ALTERA_MAX10 + select SOC_ZEPHYR_NIOS2F diff --git a/boards/altr/max10/Kconfig.defconfig b/boards/altr/max10/Kconfig.defconfig new file mode 100644 index 00000000000000..d0617d44c33cda --- /dev/null +++ b/boards/altr/max10/Kconfig.defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +if BOARD_ALTERA_MAX10 + +if FLASH + +config SOC_FLASH_NIOS2_QSPI + default y + +endif # FLASH + +endif # BOARD_ALTERA_MAX10 diff --git a/boards/nios2/altera_max10/altera_max10.dts b/boards/altr/max10/altera_max10.dts similarity index 95% rename from boards/nios2/altera_max10/altera_max10.dts rename to boards/altr/max10/altera_max10.dts index 9b258bda273bcd..30c7e44250571c 100644 --- a/boards/nios2/altera_max10/altera_max10.dts +++ b/boards/altr/max10/altera_max10.dts @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2018 Intel */ /dts-v1/; diff --git a/boards/nios2/altera_max10/altera_max10.yaml b/boards/altr/max10/altera_max10.yaml similarity index 100% rename from boards/nios2/altera_max10/altera_max10.yaml rename to boards/altr/max10/altera_max10.yaml diff --git a/boards/altr/max10/altera_max10_defconfig b/boards/altr/max10/altera_max10_defconfig new file mode 100644 index 00000000000000..ac9a2e96e4d3c7 --- /dev/null +++ b/boards/altr/max10/altera_max10_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel + +CONFIG_HAS_ALTERA_HAL=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nios2/altera_max10/board.cmake b/boards/altr/max10/board.cmake similarity index 100% rename from boards/nios2/altera_max10/board.cmake rename to boards/altr/max10/board.cmake diff --git a/boards/altr/max10/board.yml b/boards/altr/max10/board.yml new file mode 100644 index 00000000000000..976a0f83a80b48 --- /dev/null +++ b/boards/altr/max10/board.yml @@ -0,0 +1,5 @@ +board: + name: altera_max10 + vendor: altr + socs: + - name: zephyr_nios2f diff --git a/boards/nios2/altera_max10/doc/img/Altera_MAX10_switches.jpg b/boards/altr/max10/doc/img/Altera_MAX10_switches.jpg similarity index 100% rename from boards/nios2/altera_max10/doc/img/Altera_MAX10_switches.jpg rename to boards/altr/max10/doc/img/Altera_MAX10_switches.jpg diff --git a/boards/nios2/altera_max10/doc/img/altera_max10.jpg b/boards/altr/max10/doc/img/altera_max10.jpg similarity index 100% rename from boards/nios2/altera_max10/doc/img/altera_max10.jpg rename to boards/altr/max10/doc/img/altera_max10.jpg diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst new file mode 100644 index 00000000000000..64d7f14257f850 --- /dev/null +++ b/boards/altr/max10/doc/index.rst @@ -0,0 +1,332 @@ +.. _altera_max10: + +Altera MAX10 +############ + +Overview +******** + + +The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using +the Nios II Gen 2 soft CPU. + +.. figure:: img/altera_max10.jpg + :align: center + :alt: Altera's MAX* 10 + + Altera's MAX* 10 (Credit: Altera) + +Hardware +******** + +DIP Switch settings +=================== + +There are two sets of switches on the back of the board. Of particular +importance is SW2: + +* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first + boot image is CFM0 +* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing + scripts won't work +* Switch 4 (HSMC_BYPASSN) should be OFF (up) + +.. image:: img/Altera_MAX10_switches.jpg + :align: center + :alt: Altera's MAX* 10 Switches + +Other switches are user switches, their position is application-specific. + +Necessary Software +================== + +You will need the Altera Quartus SDK in order to work with this device. The +`Altera Lite Distribution`_ of Quartus may be obtained without +charge. + +For your convenience using the SDK tools (such as ``nios2-configure-sof``), +you should put the binaries provided by the SDK +in your path. Below is an example, adjust ALTERA_BASE to where you installed the +SDK: + +.. code-block:: console + + export ALTERA_BASE=/opt/altera_lite/16.0 + export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin + +You may need to adjust your udev rules so that you can talk to the USB Blaster +II peripheral, which is the built-in JTAG interface for this device. + +The following works for Fedora 23: + +.. code-block:: console + + # For Altera USB-Blaster permissions. + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6010",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6810",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + +You can test connectivity with the SDK jtagconfig tool, you should see something +like: + +.. code-block:: console + + $ jtagconfig + 1) USB-BlasterII [1-1.2] + 031050DD 10M50DA(.|ES)/10M50DC + 020D10DD VTAP10 + + +Reference CPU +============= + +A reference CPU design of a Nios II/f core is included in the Zephyr tree +in the :zephyr_file:`soc/altera/zephyr_nios2f/cpu` directory. + +Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA +configuration file +:zephyr_file:`soc/altera/zephyr_nios2f/cpu/ghrd_10m50da.sof`: + +.. code-block:: console + + $ nios2-configure-sof ghrd_10m50da.sof + +This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. +For any Nios II SOC definition, you can find out more details about the CPU +configuration by inspecting system.h in the SOC's include directory. + +Console Output +============== + +16550 UART +---------- + +By default, the kernel is configured to send console output to the 16550 UART. +You can monitor this on your workstation by connecting to the top right mini USB +port on the board (it will show up in /dev as a ttyUSB node), and then running +minicom with flow control disabled, 115200-8N1 settings. + +JTAG UART +--------- + +You can also have it send its console output to the JTAG UART. +Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: + +.. code-block:: devicetree + + &jtag_uart { + status = "okay"; + current-speed = <115200>; + }; + +To view these messages on your local workstation, run the terminal application +in the SDK: + +.. code-block:: console + + $ nios2-terminal + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Kernel into UFM +------------------------ + +The usual ``flash`` target will work with the ``altera_max10`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: altera_max10 + :goals: flash + +Refer to :ref:`build_an_application` and :ref:`application_run` for +more details. + +This provisions the Zephyr kernel and the CPU configuration onto the board, +using the scripts/support/quartus-flash.py script. After it completes the kernel +will immediately boot. + + +Flashing Kernel directly into RAM over JTAG +------------------------------------------- + +The SDK included the nios2-download tool which will let you flash a kernel +directly into RAM and then boot it from the __start symbol. + +In order for this to work, your entire kernel must be located in RAM. Make sure +the following config options are disabled: + +.. code-block:: console + + CONFIG_XIP=n + CONFIG_INCLUDE_RESET_VECTOR=n + +Then, after building your kernel, push it into device's RAM by running +this from the build directory: + +.. code-block:: console + + $ nios2-download --go zephyr/zephyr.elf + +If you have a console session running (either minicom or nios2-terminal) you +should see the application's output. There are additional arguments you can pass +to nios2-download so that it spawns a GDB server that you can connect to, +although it's typically simpler to just use nios2-gdb-server as described below. + +Debugging +========= + +The Altera SDK includes a GDB server which can be used to debug a MAX10 board. +You can either debug a running image that was flashed onto the device in User +Flash Memory (UFM), or load an image over the JTAG using GDB. + +Debugging With UFM Flashed Image +-------------------------------- + +You can debug an application in the usual way. Here is an example. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: altera_max10 + :goals: debug + +You will see output similar to the following: + +.. code-block:: console + + Nios II GDB server running on port 3335 + Ignoring --stop option because --tcpport also specified + GNU gdb (GDB) 7.11.0.20160511-git + Copyright (C) 2016 Free Software Foundation, Inc. + License GPLv3+: GNU GPL version 3 or later + This is free software: you are free to change and redistribute it. + There is NO WARRANTY, to the extent permitted by law. Type "show copying" + and "show warranty" for details. + This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". + Type "show configuration" for configuration details. + For bug reporting instructions, please see: + . + Find the GDB manual and other documentation resources online at: + . + For help, type "help". + Type "apropos word" to search for commands related to "word"... + Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. + Remote debugging using :3335 + Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 + Resetting and pausing target processor: OK + Listening on port 3335 for connection from GDB: accepted + isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 + 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); + (gdb) b z_prep_c + Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. + (gdb) b z_cstart + Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. + (gdb) c + Continuing. + + Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 + 348 { + (gdb) + +To start debugging manually: + + +.. code-block:: console + + nios2-gdb-server --tcpport 1234 --stop --reset-target + +And then connect with GDB from the build directory: + + +.. code-block:: console + + nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" + +Debugging With JTAG Flashed Image +--------------------------------- + +In order for this to work, execute-in-place must be disabled, since the GDB +'load' command can only put text and data in RAM. Ensure this is in your +configuration: + +.. code-block:: console + + CONFIG_XIP=n + +It is OK for this procedure to leave the reset vector enabled, unlike +nios2-download (which errors out if it finds sections outside of SRAM) it will +be ignored. + +In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if +any) is on the device, but you should have at least flashed a CPU using +nios2-configure-sof. You can leave this process running. + +.. code-block:: console + + $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target + +Build your Zephyr kernel, and load it into a GDB built for Nios II (included in +the Zephyr SDK) from the build directory: + +.. code-block:: console + + $ nios2-poky-elf-gdb zephyr/zephyr.elf + +Then connect to the GDB server: + +.. code-block:: console + + (gdb) target remote :1234 + +And then load the kernel image over the wire. The CPU will not start from the +reset vector, instead it will boot from the __start symbol: + + +.. code-block:: console + + (gdb) load + Loading section reset, size 0xc lma 0x0 + Loading section exceptions, size 0x1b0 lma 0x400020 + Loading section text, size 0x8df0 lma 0x4001d0 + Loading section devconfig, size 0x30 lma 0x408fc0 + Loading section rodata, size 0x3f4 lma 0x408ff0 + Loading section datas, size 0x888 lma 0x4093e4 + Loading section initlevel, size 0x30 lma 0x409c6c + Loading section _k_task_list, size 0x58 lma 0x409c9c + Loading section _k_task_ptr, size 0x8 lma 0x409cf4 + Loading section _k_event_list, size 0x10 lma 0x409cfc + Start address 0x408f54, load size 40184 + Transfer rate: 417 KB/sec, 368 bytes/write. + After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. + + + +References +********** + +* `CPU Documentation `_ +* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ +* `Embedded Peripherals IP User Guide `_ +* `MAX 10 FPGA Configuration User Guide `_ +* `MAX 10 FPGA Development Kit User Guide `_ +* `Nios II Command-Line Tools `_ +* `Quartus II Scripting Reference Manual `_ + + +.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.apollo4p_blue_kxr_evb b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.apollo4p_blue_kxr_evb new file mode 100644 index 00000000000000..09de003fc1478d --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.apollo4p_blue_kxr_evb @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Ambiq Micro Inc. + +config BOARD_APOLLO4P_BLUE_KXR_EVB + select SOC_APOLLO4P_BLUE diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..87e1c5a8764f9d --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Ambiq Micro Inc. + +if BOARD_APOLLO4P_BLUE_KXR_EVB + +if BT + +config MAIN_STACK_SIZE + default 2048 + +choice BT_HCI_BUS_TYPE + default BT_AMBIQ_HCI +endchoice + +config BT_BUF_ACL_TX_COUNT + default 14 + +config BT_BUF_CMD_TX_SIZE + default 255 + +config BT_BUF_EVT_RX_SIZE + default 255 + +config BT_BUF_ACL_TX_SIZE + default 251 + +config BT_BUF_ACL_RX_SIZE + default 251 + +# L2CAP SDU/PDU TX MTU +# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE +config BT_L2CAP_TX_MTU + default 247 + +endif # BT + +endif # BOARD_APOLLO4P_BLUE_KXR_EVB diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.yaml diff --git a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig similarity index 76% rename from boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig rename to boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig index 4c940d417fddbd..5f556803e527ab 100644 --- a/boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig +++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig @@ -2,8 +2,6 @@ # # Copyright (c) 2023 Ambiq Micro Inc. -CONFIG_SOC_SERIES_APOLLO4X=y -CONFIG_SOC_APOLLO4P_BLUE=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/apollo4p_blue_kxr_evb/board.cmake b/boards/ambiq/apollo4p_blue_kxr_evb/board.cmake similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/board.cmake rename to boards/ambiq/apollo4p_blue_kxr_evb/board.cmake diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/board.yml b/boards/ambiq/apollo4p_blue_kxr_evb/board.yml new file mode 100644 index 00000000000000..16a9a6cc979926 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: apollo4p_blue_kxr_evb + vendor: ambiq + socs: + - name: apollo4p_blue diff --git a/boards/arm/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg b/boards/ambiq/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg similarity index 100% rename from boards/arm/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg rename to boards/ambiq/apollo4p_blue_kxr_evb/doc/apollo4-blue-plus-kxr-soc-eval-board.jpg diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst new file mode 100644 index 00000000000000..214b5d4c2ef3a8 --- /dev/null +++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst @@ -0,0 +1,110 @@ +.. _apollo4p_blue_kxr_evb: + +Ambiq Apollo4 Blue Plus KXR EVB +############################### + +Apollo4 Blue Plus KXR EVB is a board by Ambiq featuring their ultra-low power Apollo4 Blue Plus SoC. + +.. image:: ./apollo4-blue-plus-kxr-soc-eval-board.jpg + :align: center + :alt: Apollo4 Blue Plus KXR EVB + +Hardware +******** + +- Apollo4 Blue Plus SoC with upto 192 MHz operating frequency +- ARM® Cortex® M4F core +- 64 kB 2-way Associative/Direct-Mapped Cache per core +- Up to 2 MB of non-volatile memory (NVM) for code/data +- Up to 2.75 MB of low leakage / low power RAM for code/data +- 384 kB Tightly Coupled RAM +- 384 kB Extended RAM +- Bluetooth 5.1 Low Energy + +For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR EVB board: + +- `Apollo4 Blue Plus Website`_ +- `Apollo4 Blue Plus Datasheet`_ +- `Apollo4 Blue Plus KXR EVB Website`_ + +Supported Features +================== + +The Apollo4 Blue Plus KXR EVB board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| STIMER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig` + +Programming and Debugging +========================= + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: apollo4p_blue_kxr_evb + :goals: flash + +.. note:: + `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! apollo4p_blue_kxr_evb + +.. _Apollo4 Blue Plus Website: + https://ambiq.com/apollo4-blue-plus/ + +.. _Apollo4 Blue Plus Datasheet: + https://contentportal.ambiq.com/documents/20123/388410/Apollo4-Blue-Plus-SoC-Datasheet.pdf + +.. _Apollo4 Blue Plus KXR EVB Website: + https://www.ambiq.top/en/apollo4-blue-plus-kxr-soc-eval-board + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/ambiq/apollo4p_evb/Kconfig.apollo4p_evb b/boards/ambiq/apollo4p_evb/Kconfig.apollo4p_evb new file mode 100644 index 00000000000000..0d77eae0c0b993 --- /dev/null +++ b/boards/ambiq/apollo4p_evb/Kconfig.apollo4p_evb @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +config BOARD_APOLLO4P_EVB + select SOC_APOLLO4P diff --git a/boards/arm/apollo4p_evb/apollo4p_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb-pinctrl.dtsi rename to boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi diff --git a/boards/arm/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb.dts rename to boards/ambiq/apollo4p_evb/apollo4p_evb.dts diff --git a/boards/arm/apollo4p_evb/apollo4p_evb.yaml b/boards/ambiq/apollo4p_evb/apollo4p_evb.yaml similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb.yaml rename to boards/ambiq/apollo4p_evb/apollo4p_evb.yaml diff --git a/boards/arm/apollo4p_evb/apollo4p_evb_connector.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi similarity index 100% rename from boards/arm/apollo4p_evb/apollo4p_evb_connector.dtsi rename to boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi diff --git a/boards/arm/apollo4p_evb/apollo4p_evb_defconfig b/boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig similarity index 85% rename from boards/arm/apollo4p_evb/apollo4p_evb_defconfig rename to boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig index e3c18add0df7ff..1b05969a07d3d5 100644 --- a/boards/arm/apollo4p_evb/apollo4p_evb_defconfig +++ b/boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig @@ -2,7 +2,6 @@ # # Copyright (c) 2023 Antmicro -CONFIG_SOC_SERIES_APOLLO4X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/apollo4p_evb/board.cmake b/boards/ambiq/apollo4p_evb/board.cmake similarity index 100% rename from boards/arm/apollo4p_evb/board.cmake rename to boards/ambiq/apollo4p_evb/board.cmake diff --git a/boards/ambiq/apollo4p_evb/board.yml b/boards/ambiq/apollo4p_evb/board.yml new file mode 100644 index 00000000000000..023487c3ecdcc3 --- /dev/null +++ b/boards/ambiq/apollo4p_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: apollo4p_evb + vendor: ambiq + socs: + - name: apollo4p diff --git a/boards/arm/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg b/boards/ambiq/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg similarity index 100% rename from boards/arm/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg rename to boards/ambiq/apollo4p_evb/doc/apollo4-plus-soc-eval-board.jpg diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst new file mode 100644 index 00000000000000..7c5cd174cf6f5e --- /dev/null +++ b/boards/ambiq/apollo4p_evb/doc/index.rst @@ -0,0 +1,105 @@ +.. _apollo4p_evb: + +Ambiq Apollo4P EVB +################## + +Apollo4P EVB is a board by Ambiq featuring their ultra-low power Apollo4 Plus SoC. + +.. image:: ./apollo4-plus-soc-eval-board.jpg + :align: center + :alt: Apollo4P EVB + +Hardware +******** + +- Apollo4 Plus SoC with upto 192 MHz operating frequency +- ARM® Cortex® M4F core +- 64 kB 2-way Associative/Direct-Mapped Cache per core +- Up to 2 MB of non-volatile memory (NVM) for code/data +- Up to 2.75 MB of low leakage / low power RAM for code/data +- 384 kB Tightly Coupled RAM +- 384 kB Extended RAM + +For more information about the Apollo4 Plus SoC and Apollo4P EVB board: + +- `Apollo4 Plus Website`_ +- `Apollo4 Plus Datasheet`_ +- `Apollo4P EVB Website`_ + +Supported Features +================== + +The Apollo4P EVB board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| STIMER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig` + +Programming and Debugging +========================= + +Flashing an application +----------------------- + +Connect your device to your host computer using the JLINK USB port. +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application, then flash it to the device: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: apollo4p_evb + :goals: flash + +.. note:: + `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module + to be installed on you host computer. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! apollo4p_evb + +.. _Apollo4 Plus Website: + https://ambiq.com/apollo4-plus/ + +.. _Apollo4 Plus Datasheet: + https://contentportal.ambiq.com/documents/20123/388415/Apollo4-Plus-SoC-Datasheet.pdf + +.. _Apollo4P EVB Website: + https://www.ambiq.top/en/apollo4-plus-soc-eval-board + +.. _SEGGER J-Link software: + https://www.segger.com/downloads/jlink + +.. _pylink: + https://github.com/Square/pylink diff --git a/boards/ambiq/index.rst b/boards/ambiq/index.rst new file mode 100644 index 00000000000000..9c202652c622de --- /dev/null +++ b/boards/ambiq/index.rst @@ -0,0 +1,10 @@ +.. _boards-ambiq: + +Ambiq +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/amd/index.rst b/boards/amd/index.rst new file mode 100644 index 00000000000000..fc172e9e0f6103 --- /dev/null +++ b/boards/amd/index.rst @@ -0,0 +1,10 @@ +.. _boards-amd: + +Advanced Micro Devices (AMD), Inc. +################################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/amd/kv260_r5/Kconfig.defconfig b/boards/amd/kv260_r5/Kconfig.defconfig new file mode 100644 index 00000000000000..aa92cd2bb2056d --- /dev/null +++ b/boards/amd/kv260_r5/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2022 Linaro. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_KV260_R5 + +config BUILD_OUTPUT_BIN + default y + +if USERSPACE + +config COMPILER_ISA_THUMB2 + default n + +endif + +endif # BOARD_KV260_R5 diff --git a/boards/amd/kv260_r5/Kconfig.kv260_r5 b/boards/amd/kv260_r5/Kconfig.kv260_r5 new file mode 100644 index 00000000000000..01327adf72a510 --- /dev/null +++ b/boards/amd/kv260_r5/Kconfig.kv260_r5 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Linaro. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KV260_R5 + select SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/kv260_r5/board.cmake b/boards/amd/kv260_r5/board.cmake similarity index 100% rename from boards/arm/kv260_r5/board.cmake rename to boards/amd/kv260_r5/board.cmake diff --git a/boards/amd/kv260_r5/board.yml b/boards/amd/kv260_r5/board.yml new file mode 100644 index 00000000000000..9e43962bfc35cb --- /dev/null +++ b/boards/amd/kv260_r5/board.yml @@ -0,0 +1,5 @@ +board: + name: kv260_r5 + vendor: amd + socs: + - name: zynqmp_rpu diff --git a/boards/arm/kv260_r5/doc/index.rst b/boards/amd/kv260_r5/doc/index.rst similarity index 100% rename from boards/arm/kv260_r5/doc/index.rst rename to boards/amd/kv260_r5/doc/index.rst diff --git a/boards/arm/kv260_r5/doc/kv260-starter-kit.jpg b/boards/amd/kv260_r5/doc/kv260-starter-kit.jpg similarity index 100% rename from boards/arm/kv260_r5/doc/kv260-starter-kit.jpg rename to boards/amd/kv260_r5/doc/kv260-starter-kit.jpg diff --git a/boards/arm/kv260_r5/kv260_r5.dts b/boards/amd/kv260_r5/kv260_r5.dts similarity index 100% rename from boards/arm/kv260_r5/kv260_r5.dts rename to boards/amd/kv260_r5/kv260_r5.dts diff --git a/boards/arm/kv260_r5/kv260_r5.yaml b/boards/amd/kv260_r5/kv260_r5.yaml similarity index 100% rename from boards/arm/kv260_r5/kv260_r5.yaml rename to boards/amd/kv260_r5/kv260_r5.yaml diff --git a/boards/amd/kv260_r5/kv260_r5_defconfig b/boards/amd/kv260_r5/kv260_r5_defconfig new file mode 100644 index 00000000000000..4b86de20d6b92d --- /dev/null +++ b/boards/amd/kv260_r5/kv260_r5_defconfig @@ -0,0 +1,17 @@ +CONFIG_XIP=n + +CONFIG_ISR_STACK_SIZE=512 +CONFIG_THREAD_STACK_INFO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_XLNX_PS=y + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_ARM_MPU=y diff --git a/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k new file mode 100644 index 00000000000000..a1a3daffac8c65 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/Kconfig.adp_xc7k @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ADP_XC7K + select SOC_ANDES_AE350 if BOARD_ADP_XC7K_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.dts b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts similarity index 100% rename from boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.dts rename to boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.dts diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml similarity index 90% rename from boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml rename to boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml index c837eda1ef162b..69087b9ad9ebb1 100644 --- a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350.yaml +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350.yaml @@ -1,4 +1,4 @@ -identifier: adp_xc7k_ae350 +identifier: adp_xc7k/ae350 name: Andes ADP-XC7K AE350 type: mcu arch: riscv diff --git a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig similarity index 90% rename from boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig rename to boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig index edbe7118c64301..78a5b22ff6f5bd 100644 --- a/boards/riscv/adp_xc7k_ae350/adp_xc7k_ae350_defconfig +++ b/boards/andestech/adp_xc7k_ae350/adp_xc7k_ae350_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_ANDES_AE350=y -CONFIG_SOC_ANDES_AE350=y -CONFIG_BOARD_ADP_XC7K_AE350=y CONFIG_XIP=n CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/andestech/adp_xc7k_ae350/board.yml b/boards/andestech/adp_xc7k_ae350/board.yml new file mode 100644 index 00000000000000..09ade0170f32b9 --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/board.yml @@ -0,0 +1,5 @@ +board: + name: adp_xc7k + vendor: andestech + socs: + - name: ae350 diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg b/boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg similarity index 100% rename from boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg rename to boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k160.jpg diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg b/boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg similarity index 100% rename from boards/riscv/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg rename to boards/andestech/adp_xc7k_ae350/doc/img/adp_xc7k410.jpg diff --git a/boards/riscv/adp_xc7k_ae350/doc/img/connect_aice.jpg b/boards/andestech/adp_xc7k_ae350/doc/img/connect_aice.jpg similarity index 100% rename from boards/riscv/adp_xc7k_ae350/doc/img/connect_aice.jpg rename to boards/andestech/adp_xc7k_ae350/doc/img/connect_aice.jpg diff --git a/boards/andestech/adp_xc7k_ae350/doc/index.rst b/boards/andestech/adp_xc7k_ae350/doc/index.rst new file mode 100644 index 00000000000000..ee7dc40d35599b --- /dev/null +++ b/boards/andestech/adp_xc7k_ae350/doc/index.rst @@ -0,0 +1,334 @@ +.. _adp_xc7k_ae350: + +Andes ADP-XC7K AE350 +#################### + +Overview +******** + +ADP-XC7K AE350 board is for AndeShape AE350 platform on ADP-XC7K series +FPGA-based development boards. + +ADP-XC7K series are FPGA-based development and prototyping boards for evaluation of +variety of AndesCore processors and AndeShape SoC platform IPs. +AE350 is a RISC-V platform which can integrate AndesCore CPUs with a collection +of fundamental peripheral IPs. + +1st figure shows the green PCB is ADP-XC7K160 and 2nd figure shows the red PCB is ADP-XC7K410. + +.. image:: img/adp_xc7k160.jpg + :align: center + :alt: ADP-XC7K160 + +.. image:: img/adp_xc7k410.jpg + :align: center + :alt: ADP-XC7K410 + +More information can be found on `ADP-XC7K160/410`_ and `AndeShape AE350`_ websites. + +Hardware +******** + +The ADP-XC7K AE350 platform integrates 1 ~ 4 cores 32/64-bit 60MHz RISC-V CPUs, DSP, +1GB RAM, Cache, SPI flash memory, ethernet controller and other peripherals. + +The ADP-XC7K AE350 platform provides following hardware components: + +- 1 ~ 4 cores 32/64-bit 60MHz AndeStar v5 RISC-V CPUs +- 1GB on-board SDRAM +- 2MB SPI flash memory (1MB can be used for XIP) +- UART +- I2C +- SPI +- GPIO +- PWM +- DMA +- 10/100 Ethernet RJ45 port +- LCD module connector +- 16KB I2C EEPROM +- SD memory card slot +- MIC-in, Line-in, and Line-out with AC97 audio codec + +Supported Features +================== + +The ``adp_xc7k/ae350`` board configuration supports the following hardware features: + ++----------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++================+============+======================+ +| PLIC | on-chip | interrupt_controller | ++----------------+------------+----------------------+ +| RISC-V Machine | on-chip | timer | +| Timer | | | ++----------------+------------+----------------------+ +| GPIO | on-chip | gpio | ++----------------+------------+----------------------+ +| UART | on-chip | serial | ++----------------+------------+----------------------+ +| COUNTER | on-chip | counter | ++----------------+------------+----------------------+ +| SPI | on-chip | spi | ++----------------+------------+----------------------+ +| I2C | on-chip | i2c | ++----------------+------------+----------------------+ +| EEPROM | on-chip | eeprom | ++----------------+------------+----------------------+ +| FLASH | on-chip | flash | ++----------------+------------+----------------------+ +| HWINFO | on-chip | syscon | ++----------------+------------+----------------------+ +| MAILBOX | on-chip | mbox | ++----------------+------------+----------------------+ +| DMA | on-chip | dma | ++----------------+------------+----------------------+ +| WATCHDOG | on-chip | wdt | ++----------------+------------+----------------------+ + +Other hardware features are not supported yet. + +Connections and IOs +=================== + +The ADP-XC7K AE350 platform has 1 GPIO controller. It providing 32 bits of IO. +It is responsible for pin input/output, pull-up, etc. + +Mapping from GPIO controller to the ADP-XC7K board pins: + ++--------------------+--------------------+ +| GPIO controller | Usage / Board pins | ++====================+====================+ +| **Push Buttons** | | ++--------------------+--------------------+ +| GPIO.0 | SW1 | ++--------------------+--------------------+ +| GPIO.1 | SW2 | ++--------------------+--------------------+ +| GPIO.2 | SW3 | ++--------------------+--------------------+ +| GPIO.3 | SW4 | ++--------------------+--------------------+ +| GPIO.4 | SW5 | ++--------------------+--------------------+ +| GPIO.5 | SW6 | ++--------------------+--------------------+ +| GPIO.6 | SW7 | ++--------------------+--------------------+ +| **7-Segment LED1** | | ++--------------------+--------------------+ +| GPIO.16 | 7SEG1.A | ++--------------------+--------------------+ +| GPIO.17 | 7SEG1.B | ++--------------------+--------------------+ +| GPIO.18 | 7SEG1.C | ++--------------------+--------------------+ +| GPIO.19 | 7SEG1.D | ++--------------------+--------------------+ +| GPIO.20 | 7SEG1.E | ++--------------------+--------------------+ +| GPIO.21 | 7SEG1.F | ++--------------------+--------------------+ +| GPIO.22 | 7SEG1.G | ++--------------------+--------------------+ +| GPIO.23 | 7SEG1.DP | ++--------------------+--------------------+ +| **7-Segment LED2** | | ++--------------------+--------------------+ +| GPIO.24 | 7SEG2.A | ++--------------------+--------------------+ +| GPIO.25 | 7SEG2.B | ++--------------------+--------------------+ +| GPIO.26 | 7SEG2.C | ++--------------------+--------------------+ +| GPIO.27 | 7SEG2.D | ++--------------------+--------------------+ +| GPIO.28 | 7SEG2.E | ++--------------------+--------------------+ +| GPIO.29 | 7SEG2.F | ++--------------------+--------------------+ +| GPIO.30 | 7SEG2.G | ++--------------------+--------------------+ +| GPIO.31 | 7SEG2.DP | ++--------------------+--------------------+ +| **GPIO pins** | | ++--------------------+--------------------+ +| GPIO.7 | IDE_CON1.4 | ++--------------------+--------------------+ +| GPIO.8 | IDE_CON1.6 | ++--------------------+--------------------+ +| GPIO.9 | IDE_CON1.8 | ++--------------------+--------------------+ +| GPIO.10 | IDE_CON1.10 | ++--------------------+--------------------+ +| GPIO.11 | IDE_CON1.11 | ++--------------------+--------------------+ +| GPIO.12 | IDE_CON1.12 | ++--------------------+--------------------+ +| GPIO.13 | IDE_CON1.13 | ++--------------------+--------------------+ +| GPIO.14 | IDE_CON1.14 | ++--------------------+--------------------+ +| GPIO.15 | IDE_CON1.15 | ++--------------------+--------------------+ + +Other peripheral mapping are listed below: + ++-------------+---------------------------------+ +| Peripherals | Usage / Board pins | ++=============+=================================+ +| SPI_1 | internal connected to SPI Flash | ++-------------+---------------------------------+ +| SPI_2_CS | IDE_CON1.37 | ++-------------+---------------------------------+ +| SPI_2_MOSI | IDE_CON1.36 | ++-------------+---------------------------------+ +| SPI_2_MISO | IDE_CON1.38 | ++-------------+---------------------------------+ +| SPI_2_SCLK | IDE_CON1.35 | ++-------------+---------------------------------+ +| I2C_SDA | J27.1 | ++-------------+---------------------------------+ +| I2C_SCL | J27.2 | ++-------------+---------------------------------+ + +System Clock +------------ + +The ADP-XC7K AE350 platform has 60MHz core clock. + +Serial Port +----------- + +The ADP-XC7K AE350 platform has 2 UARTs. +The Zephyr console output is by default assigned to UART2 and the default +settings are 115200 8N1. + +Programming and debugging +************************* + +For debugging zephyr applications or burning them into a flash, you will need to +connect Andes ICE from host computer to ADP-XC7K board and execute the +Andes ICE management software, ICEman, on this host computer. + +Connecting Andes ICE (AICE) +=========================== + +AICE is used for flashing and debugging the board. Please connect AICE to both +ADP-XC7K board and the host computer as shown in the figure. + +.. image:: img/connect_aice.jpg + :align: center + :alt: Connect AICE + +More information can be found on `AICE-MINI+`_, `AICE-MICRO`_ website + +Building +======== + +You can build applications in the usual way. Here is an example for +the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: adp_xc7k/ae350 + :goals: build + +Flashing +======== + +Before flashing, you have to download ICEman (``ice.zip``) from the +`Andes Development Kit`_. +If you want to use XIP mode (``CONFIG_XIP=y``), you also need to download +the flash burner (``flash.zip``). + +At first, you should run ICEman when flashing and debugging program. + +.. code-block:: console + + # Enable execute file permission of ICEman + chmod a+x ./ICEman + + # Running the ICEman server + sudo ./ICEman -Z v5 + +.. note:: + + To run ICEman commands as a normal user, you will need to install the + :file:`70-ndsusb-v1.rules` udev rules file (usually by placing it in + :file:`/etc/udev/rules.d`, then unplugging and plugging the + AICE adapter in again via USB.). + +If ``CONFIG_XIP=n``, you can load the program (``zephyr.elf``) into RAM directly +and execute it. + +.. code-block:: console + + # Check the ICEman server is running + # Load the program into RAM and execute it + riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf + (gdb) target remote :1111 + (gdb) monitor reset halt + (gdb) load + (gdb) quit + +If ``CONFIG_XIP=y``, you need to burn the program (``zephyr.bin``) into flash memory +and execute it. + +.. code-block:: console + + # Check the ICEman server is running + # Burn the program into flash and execute it + /bin/target_burn_frontend \ + -P 4444 --unlock --verify --image=build/zephyr/zephyr.bin \ + --algorithm-bin=/target_bin/target_SPI_v5_[32|64].bin + + # Note: + # 1. Assume the flash burner is downloaded to directory + # 2. For algorithm-bin file, use target_SPI_v5_32.bin in RV32 platform and + # use target_SPI_v5_64.bin in RV64 platform + +Open a serial terminal with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.4.0 ***** + Hello World! adp_xc7k + +Debugging +========= + +.. code-block:: console + + # Check the ICEman server is running + # Load and debug program + ./riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf + (gdb) target remote :1111 + (gdb) monitor reset halt + (gdb) load + +If ``CONFIG_XIP=y``, please follow the flashing section to burn the program into +flash memory first. +Then, you can use GDB to debug program by above commands but do NOT execute ``load`` +command since the program has been placed in the flash memory. + +References +********** + +.. target-notes:: + +.. _ADP-XC7K160/410: http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/ + +.. _AndeShape AE350: http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ + +.. _AICE-MINI+: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-mini-plus/ + +.. _AICE-MICRO: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-micro/ + +.. _Andes Development Kit: https://github.com/andestech/Andes-Development-Kit/releases diff --git a/boards/andestech/index.rst b/boards/andestech/index.rst new file mode 100644 index 00000000000000..17618d8186ed50 --- /dev/null +++ b/boards/andestech/index.rst @@ -0,0 +1,10 @@ +.. _boards-andes: + +Andes Technology +################ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arc/em_starterkit/CMakeLists.txt b/boards/arc/em_starterkit/CMakeLists.txt deleted file mode 100644 index 5b1b4b9b11bf27..00000000000000 --- a/boards/arc/em_starterkit/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(pmodmux.c) -zephyr_sources_ifdef(CONFIG_ARC_MPU_ENABLE arc_mpu_regions.c) diff --git a/boards/arc/em_starterkit/Kconfig b/boards/arc/em_starterkit/Kconfig deleted file mode 100644 index 45cf1bd2431264..00000000000000 --- a/boards/arc/em_starterkit/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# DesignWare ARC EM Starter Kit board configuration options - -# Copyright (c) 2017 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Board Firmware Version" - default BOARD_EM_STARTERKIT_R23 - depends on BOARD_EM_STARTERKIT - - config BOARD_EM_STARTERKIT_R22 - bool "2.2" - - config BOARD_EM_STARTERKIT_R23 - bool "2.3" - -endchoice diff --git a/boards/arc/em_starterkit/Kconfig.board b/boards/arc/em_starterkit/Kconfig.board deleted file mode 100644 index dd7da9f0512b20..00000000000000 --- a/boards/arc/em_starterkit/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# DesignWare ARC EM Starter Kit board configuration - -# Copyright (c) 2016 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EM_STARTERKIT - bool "ARC EM Starter Kit" - depends on SOC_EMSK - help - The DesignWare ARC EM Starter Kit board is a board - that can host up to 3 different SOC FPGA bit files. - Both version 2.2 and 2.3 firmware have EM7D, EM9D and EM11D configurations. - EM9D using CCM memories and is a Harvard Architecture. - EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache. - EM7D of EMSK 2.3 supports secure mode. diff --git a/boards/arc/em_starterkit/Kconfig.defconfig b/boards/arc/em_starterkit/Kconfig.defconfig deleted file mode 100644 index 7e9c5bc45d53e8..00000000000000 --- a/boards/arc/em_starterkit/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EM_STARTERKIT - -config BOARD - default "em_starterkit" - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 100 - -endif # I2C_DW - -endif # BOARD_EM_STARTERKIT diff --git a/boards/arc/em_starterkit/board.dtsi b/boards/arc/em_starterkit/board.dtsi deleted file mode 100644 index e80ee0eea30b9d..00000000000000 --- a/boards/arc/em_starterkit/board.dtsi +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include - -/ { - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - led4 = &led4; - led5 = &led5; - led6 = &led6; - led7 = &led7; - led8 = &led8; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio1 0 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpio1 1 0>; - label = "LED 1"; - }; - led2: led_2 { - gpios = <&gpio1 2 0>; - label = "LED 2"; - }; - led3: led_3 { - gpios = <&gpio1 3 0>; - label = "LED 3"; - }; - led4: led_4 { - gpios = <&gpio1 4 0>; - label = "LED 4"; - }; - led5: led_5 { - gpios = <&gpio1 5 0>; - label = "LED 5"; - }; - led6: led_6 { - gpios = <&gpio1 6 0>; - label = "LED 6"; - }; - led7: led_7 { - gpios = <&gpio1 7 0>; - label = "LED 7"; - }; - led8: led_8 { - gpios = <&gpio1 8 0>; - label = "LED 8"; - }; - - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - label = "Push button switch 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; - label = "Push button switch 1"; - zephyr,code = ; - }; - button2: button_2 { - /* gpio flags need validation */ - gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; - label = "Push button switch 2"; - zephyr,code = ; - }; - switch0: switch_0 { - /* gpio flags need validation */ - gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 1"; - zephyr,code = ; - }; - switch1: switch_1 { - /* gpio flags need validation */ - gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 2"; - zephyr,code = ; - }; - switch2: switch_2 { - /* gpio flags need validation */ - gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 3"; - zephyr,code = ; - }; - switch3: switch_3 { - /* gpio flags need validation */ - gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; - label = "DIP SW1 - Switch 4"; - zephyr,code = ; - }; - }; - -}; diff --git a/boards/arc/em_starterkit/doc/index.rst b/boards/arc/em_starterkit/doc/index.rst deleted file mode 100644 index 6e11af1b12d68b..00000000000000 --- a/boards/arc/em_starterkit/doc/index.rst +++ /dev/null @@ -1,331 +0,0 @@ -.. _em_starterkit: - -DesignWare(R) ARC(R) EM Starter Kit -################################### - -Overview -******** - -The DesignWare(R) ARC(R) EM Starter Kit is a low-cost, versatile solution -enabling rapid software development and software debugging, and profiling -for the ARC EM Family of processors. The EM Family includes the EM4, EM6, -EM5D, EM7D, EM9D, and EM11D cores. The Zephyr RTOS can be used with the -EM Starter Kit. - -.. image:: em_starterkit.jpg - :align: center - :alt: DesignWare(R) ARC(R) EM Starter Kit (synopsys.com) - -The ARC EM Starter Kit consists of a hardware platform, including pre-installed -FPGA images of different ARC EM processor configurations with peripherals. -Documentation for this board can be found at `embARC website`_. - -See also this URL for details about the board: -`Designware ARC EM Starter Kit website`_ . - -The latest version of EM Starter Kit is 2.3, developer can upgrade from -2.0/2.1/2.2 to 2.3 using latest firmware. -The default configuration for EM Starter Kit boards can be found in -:zephyr_file:`boards/arc/em_starterkit/em_starterkit_defconfig`. - -The default SoC for this board supported in Zephyr is the EM9D. -This configuration is a Harvard Architecture, with a separate -instruction bus and data bus. Instruction memory is called ICCM -and data memory is called DCCM. The configuration file for EM9D -is found in :zephyr_file:`soc/arc/snps_emsk/Kconfig.defconfig.em9d`. - -If you have a larger program, you can select the EM7D or EM11D, which gives -access to 128KB DRAM with i-cache and d-cache. The configuration file for EM7D -is found in :zephyr_file:`soc/arc/snps_emsk/Kconfig.defconfig.em7d` and EM11D is -found in :zephyr_file:`soc/arc/snps_emsk/Kconfig.defconfig.em11d`. - - -Hardware -******** -Board Layout -============ - -The ARC EM Starter Kit main board has 6 Pmod connectors. These can be configured -to support attachment of GPIO, I2C, UART or SPI devices. - -The board also has a 16MB SPI-FLASH and an SDCard for storage. There are 9 LEDs, -3 buttons, and 4 dip switches that can be used with GPIO. - -The Xilinx Spartan(R)-6 LX150 FPGA can auto-load one of 3 FPGA SoC bit files -which have the EM7D, EM9D, or EM11D SoC. - -Documentation and general information for the board can be found at the -`embARC website`_, which also includes some free sample software. - - -Supported Firmware Versions -=========================== - -The EM Starter Kit has different versions, such as 1.0, 1.1, 2.0, 2.1, -2.2 and 2.3. -In Zephyr, only firmware versions 2.2 and 2.3 are supported. - -* For EM Starter Kit 2.2, EM7D, EM9D and EM11D core configurations are supported. - - * Use :kconfig:option:`CONFIG_BOARD_EM_STARTERKIT_R22` to select 2.2 version. - * Use :kconfig:option:`CONFIG_SOC_EMSK_EM7D`, :kconfig:option:`CONFIG_SOC_EMSK_EM9D` or - :kconfig:option:`CONFIG_SOC_EMSK_EM11D` to select EM7D or EM9D or EM11D. - -* For EM Starter Kit 2.3, EM7D, EM9D and EM11D core configurations are - supported. - - * Use :kconfig:option:`CONFIG_BOARD_EM_STARTERKIT_R23` to select 2.3 version. - * Use :kconfig:option:`CONFIG_SOC_EMSK_EM7D`, :kconfig:option:`CONFIG_SOC_EMSK_EM9D` or - :kconfig:option:`CONFIG_SOC_EMSK_EM11D` to select EM7D or EM9D or EM11D. - -Supported Features -================== - -The Zephyr kernel supports multiple hardware features on the EM Starter Kit -through the use of device drivers. - -The EM Starter Kit supports 6 Digilent Pmod(TM) Interfaces, which enables the -use of a large variety of pluggable modules for storage, communications, -sensors, displays, etc. With the Pmod interface, you can prototype your -applications using the Zephyr RTOS. - -The table below shows which drivers are supported and which functionality can -be found on which architectures: - -+-----------+------------+-----+-------+-----------------------+ -| Interface | Controller |EM9D | EM11D | Driver/Component | -+===========+============+=====+=======+=======================+ -| INT | on-chip | Y | Y | interrupt_controller | -+-----------+------------+-----+-------+-----------------------+ -| UART | usb + | Y | Y | serial port-polling; | -| | 2 Pmods | | | serial port-interrupt | -+-----------+------------+-----+-------+-----------------------+ -| SPI | 2 Pmods | Y | Y | spi | -+-----------+------------+-----+-------+-----------------------+ -| ADC | n/a | N | N | adc (can add via Pmod)| -+-----------+------------+-----+-------+-----------------------+ -| I2C | 2 Pmods | Y | Y | i2c | -+-----------+------------+-----+-------+-----------------------+ -| GPIO | 6 Pmods | Y | Y | gpio | -+-----------+------------+-----+-------+-----------------------+ -| PWM | n/a | N | N | pwm | -+-----------+------------+-----+-------+-----------------------+ - -The board has 3 (debounced and interrupting) buttons for use with GPIO, 4 dip -switches, 9 LEDs, SDCard on SPI, and a 16MB SPI-Flash memory. - -The SPI-FLASH driver is supported with sample, which can be found in -``samples/drivers/spi_flash``. - -The SPI-Flash also holds 3 (or 4) separate FPGA CPU bit files, selectable via -dip switch. - -The SPI-Flash is also programmed with a bootloader. The bootloader can copy a -program image from SPI-Flash into executable memory. Zephyr initialization will -copy the initialized data section to the data memory if CONFIG_XIP is used. - - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To use Zephyr RTOS applications on the EM Starter Kit board, a few additional -pieces of hardware are required. - -* USB Cable (delivered as part of the ARC EM Starter Kit) - -* The USB cable provides power to the board; however, if the board is to run - standalone, the universal switching power adaptor (110-240V AC to 5V DC), - provided in the package, can be used to power the board. - -* :ref:`The Zephyr SDK ` - -* Terminal emulator software for use with the USB-UART. Suggestion: - `Putty Website`_. - -* (optional) A collection of Pmods. - See `Digilent Pmod Modules`_ or develop your custom interfaces to attach - to the Pmod connector. - -Set up the ARC EM Starter Kit -============================= - -To run Zephyr application on correct arc core of EM Starter Kit, you need to -setup the board correctly. - -* Connect the digilent usb cable from your host to the board. - -* Connect the 5V DC power supply to your board. - -* Select the core configuration of the board by choosing correct dip switch - SW1 settings, then press then FPGA configure button located above the letter - 'C' of the ARC logo on the board. - -* Then the board will be reconfigured with selected core configuration, you - can download and debug Zephyr application now. - -* If you want to know more about how to use this board, you can take a look - at the `ARC EM Starter Kit User Guide`_. - -Set up Zephyr Software -====================== - -Since there are different firmware versions of EM Starter Kit, you need to -choose the proper firmware version supported in Zephyr. - -Three different configurations exist for this board: - -* EM7D: em_starterkit_em7d_defconfig -* EM9D: em_starterkit_defconfig -* EM11D: em_starterkit_em11d_defconfig - - -Building Sample Applications -============================== - -You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. -It is found in :zephyr_file:`samples/hello_world`. - -Configuring ------------ - -You may need to write a prj_arc.conf file if the sample doesn't have one. -Next, you can use the menuconfig rule to configure the target. By -specifying ``em_starterkit`` as the board configuration, you can select the ARC -EM Starter Kit board support for Zephyr. - -.. zephyr-app-commands:: - :board: em_starterkit - :zephyr-app: samples/hello_world - :goals: menuconfig - -On this board you will also need to consider the "ARC SoC Selection" and set -it either to EM9D or EM11D. To boot up the EM9D on the board, all dip -switches should be UP except for switch 1. Other configuration choices -are made in the normal way. To boot up the EM11D on the board, -all dip switches should be UP except for switch 2. Next press the button -above the letter C in the "ARC" logo on the silkscreen. - -Building --------- - -You can build application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: em_starterkit - :zephyr-app: samples/hello_world - :maybe-skip-config: - :goals: build - -Connecting Serial Output -========================= - -In the default configuration, Zephyr's EM Starter Kit images support -serial output via the UART1 on the board. To enable serial output: - -On your development environment, you will need to: - -* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) -* Specify the tty driver name, for example, on Linux this may be :file:`/dev/ttyUSB1` -* Set the communication settings to: - - -========= ===== -Parameter Value -========= ===== -Baud: 115200 -Data: 8 bits -Parity: None -Stopbits: 1 -========= ===== - -Debugging -========== - -Using the latest version of Zephyr SDK(>=0.9), you can debug and flash -EM Starterkit directly. - -One option is to build and debug the application using the usual -Zephyr build system commands. - -.. zephyr-app-commands:: - :board: em_starterkit - :app: - :goals: debug - -At this point you can do your normal debug session. Set breakpoints and then -'c' to continue into the program. - -The other option is to launch a debug server, as follows. - -.. zephyr-app-commands:: - :board: em_starterkit - :app: - :goals: debugserver - -Then connect to the debug server at the EM Starter Kit from a second -console, from the build directory containing the output :file:`zephyr.elf`. - -.. code-block:: console - - $ cd - $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/bin/arc-zephyr-elf-gdb zephyr.elf - (gdb) target remote localhost:3333 - (gdb) load - (gdb) b main - (gdb) c - -Flashing -======== - -If you just want to download the application to the EM Starter Kit's CCM -or DDR and run, you can do so in the usual way. - -.. zephyr-app-commands:: - :board: em_starterkit - :goals: flash - -This command still uses openocd and gdb to load application elf file -to EM Starter Kit, but it will load application and then run immediately. -If power is lost, the application will also lost due to power loss. - -Most of the time you will not be flashing your program but will instead -debug it using openocd and gdb. The program can be download via the USB -cable into the code and data memories. - -When you are ready to deploy the program so that it boots up automatically -on reset or power-up, you can follow the steps to place the program on -SPI-FLASH. - -For instructions on how to write your program to SPI-FLASH, -refer to the documentation on the ARC EM Starter Kit at the -`embARC website`_, which includes instructions for how to place an -executable image onto the SPI-FLASH in such a way that it is understood -by the bootloader. - -Release Notes -************* - -The following is a list of TODO items: - -* ``GH-2647``: Zephyr needs i-cache API (all targets) -* ``GH-2230``: Zephyr ARC port doesn't yet support nested regular interrupts. -* pinmux driver: Possibly it can be written to configure PMods too. - -References -********** - -.. _embARC website: https://www.embarc.org - -.. _Designware ARC EM Starter Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit - -.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules - -.. _Putty website: http://www.putty.org - -.. _ARC EM Starter Kit User Guide: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit diff --git a/boards/arc/em_starterkit/em_starterkit.dts b/boards/arc/em_starterkit/em_starterkit.dts deleted file mode 100644 index 7acf111e6c7304..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include "em_starterkit_r23.dtsi" -#include "board.dtsi" - -/ { - model = "em_starterkit-em9d"; - compatible = "snps,em_starterkit-em9d", "snps,em_starterkit"; - - aliases { - uart-0 = &uart0; - uart-1 = &uart1; - uart-2 = &uart2; - spi-flash0 = &w25q128bv; - }; - - chosen { - zephyr,sram = &dccm0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - }; - - iccm0: iccm@0 { - compatible = "arc,iccm"; - reg = <0x0 DT_SIZE_K(256)>; - }; - - dccm0: dccm@80000000 { - compatible = "arc,dccm"; - reg = <0x80000000 DT_SIZE_K(128)>; - }; - - xccm@c0000000 { - compatible = "arc,xccm"; - reg = <0xc0000000 DT_SIZE_K(8)>; - }; - - yccm@e0000000 { - compatible = "arc,yccm"; - reg = <0xe0000000 DT_SIZE_K(8)>; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; diff --git a/boards/arc/em_starterkit/em_starterkit.yaml b/boards/arc/em_starterkit/em_starterkit.yaml deleted file mode 100644 index f489b0a28ac723..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit -name: EM Starterkit -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_defconfig b/boards/arc/em_starterkit/em_starterkit_defconfig deleted file mode 100644 index 3bc77c1b6f8579..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM9D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arc/em_starterkit/em_starterkit_em11d.dts b/boards/arc/em_starterkit/em_starterkit_em11d.dts deleted file mode 100644 index 618731c3d9a99b..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_em11d.dts +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2018, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include "em_starterkit_r23.dtsi" -#include "board.dtsi" - -/ { - model = "em_starterkit-em11d"; - compatible = "snps,em_starterkit-em11d", "snps,em_starterkit"; - - aliases { - uart-0 = &uart0; - uart-1 = &uart1; - uart-2 = &uart2; - spi-flash0 = &w25q128bv; - }; - - chosen { - zephyr,sram = &ddr0; - zephyr,console = &uart1; - zephyr,shell-uart = &uart1; - }; - - iccm0: iccm@0 { - compatible = "arc,iccm"; - reg = <0x0 DT_SIZE_K(64)>; - }; - - dccm0: dccm@80000000 { - compatible = "arc,dccm"; - reg = <0x80000000 DT_SIZE_K(64)>; - }; - - xccm@c0000000 { - compatible = "arc,xccm"; - reg = <0xc0000000 DT_SIZE_K(8)>; - }; - - yccm@e0000000 { - compatible = "arc,yccm"; - reg = <0xe0000000 DT_SIZE_K(8)>; - }; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; diff --git a/boards/arc/em_starterkit/em_starterkit_em11d.yaml b/boards/arc/em_starterkit/em_starterkit_em11d.yaml deleted file mode 100644 index f06dccbc8e7af4..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_em11d.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit_em11d -name: EM Starterkit EM11D -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em11d_defconfig b/boards/arc/em_starterkit/em_starterkit_em11d_defconfig deleted file mode 100644 index 7146e82d57bf78..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_em11d_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM11D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y -CONFIG_XIP=n -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arc/em_starterkit/em_starterkit_em7d.yaml b/boards/arc/em_starterkit/em_starterkit_em7d.yaml deleted file mode 100644 index d4ab57393b44ea..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit_em7d -name: EM Starterkit EM7D -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_defconfig b/boards/arc/em_starterkit/em_starterkit_em7d_defconfig deleted file mode 100644 index 345776e14f1823..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM7D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y -CONFIG_XIP=n -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_ARC_HAS_SECURE=y -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_INIT_ARCH_HW_AT_BOOT=y diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_v22.yaml b/boards/arc/em_starterkit/em_starterkit_em7d_v22.yaml deleted file mode 100644 index b7eb883286ff21..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d_v22.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: em_starterkit_em7d_v22 -name: EM Starterkit V22 EM7D -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -supported: - - i2c - - spi - - gpio -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_v22_defconfig b/boards/arc/em_starterkit/em_starterkit_em7d_v22_defconfig deleted file mode 100644 index 70af0aafedcef8..00000000000000 --- a/boards/arc/em_starterkit/em_starterkit_em7d_v22_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_EMSK=y -CONFIG_SOC_EMSK_EM7D=y -CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R22=y -CONFIG_XIP=n -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/emsdp/Kconfig.board b/boards/arc/emsdp/Kconfig.board deleted file mode 100644 index c27a4d2c07bb2d..00000000000000 --- a/boards/arc/emsdp/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# DesignWare ARC EM Software Development Platform board configuration - -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EMSDP - bool "EM Software Development Platform" - depends on SOC_ARC_EMSDP - help - The ARC EM Software Development Platform (emsdp) is an FPGA based - development platform intended to support ARC licenses in developing - their software for the ARC EM processor family and ARC EM Subsystems. - It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D - processors. ARC EM Enhanced Security Package (ESP) and ARC EM - Subsystems (DFSS, SCSS, DSS) are also supported. diff --git a/boards/arc/emsdp/Kconfig.defconfig b/boards/arc/emsdp/Kconfig.defconfig deleted file mode 100644 index 98101cb3a2805d..00000000000000 --- a/boards/arc/emsdp/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# DesignWare ARC EM Software Development Platform board configuration - -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EMSDP - -config BOARD - default "emsdp" - -if SPI - -config SPI_DW - default y - -endif # SPI - -endif # BOARD_EMSDP diff --git a/boards/arc/emsdp/doc/index.rst b/boards/arc/emsdp/doc/index.rst deleted file mode 100644 index b02c2539ef5d99..00000000000000 --- a/boards/arc/emsdp/doc/index.rst +++ /dev/null @@ -1,286 +0,0 @@ -.. _emsdp: - -DesignWare(R) ARC(R) EM Software Development Platform -##################################################### - -Overview -******** - -The DesignWare® ARC® EM Software Development Platform (SDP) is a flexible platform -for rapid software development on ARC EM processor-based subsystems. It is intended -to accelerate software development and debug of ARC EM processors and subsystems for -a wide range of ultra-low power embedded applications such as IoT, sensor fusion, -and voice applications. - -.. image:: emsdp.jpg - :align: center - :alt: DesignWare(R) ARC(R) EM Software Development Platform (synopsys.com) - -For details about the board, see: `DesignWare ARC EM Software Development Platform -(EM SDP) `__ - - -Hardware -******** - -The EM Software Development Platform supports different core configurations, such as EM4, -EM5D, EM6, EM7D, EM9D, EM9D+ESP, EM11D, the default core configuration is EM11D. Use -:kconfig:option:`CONFIG_SOC_EMSDP_EM4`, :kconfig:option:`CONFIG_SOC_EMSDP_EM5D`, -:kconfig:option:`CONFIG_SOC_EMSDP_EM6`, :kconfig:option:`CONFIG_SOC_EMSDP_EM7D`, -:kconfig:option:`CONFIG_SOC_EMSDP_EM7D_ESP`, :kconfig:option:`CONFIG_SOC_EMSDP_EM9D` or -:kconfig:option:`CONFIG_SOC_EMSDP_EM11D` to select different core configuration. - -The following table shows the hardware features supported for different core configuration: - -+-----------+-----+-----+------+------+----------+------+-------+ -| Features | EM4 | EM6 | EM5D | EM7D | EM7D_ESP | EM9D | EM11D | -+===========+=====+=====+======+======+==========+======+=======+ -| Caches | N | Y | N | Y | Y | N | Y | -+-----------+-----+-----+------+------+----------+------+-------+ -| DSP | N | N | Y | Y | Y | Y | Y | -+-----------+-----+-----+------+------+----------+------+-------+ -| XY Memory | N | N | N | N | N | Y | Y | -+-----------+-----+-----+------+------+----------+------+-------+ -| Secure | N | N | N | N | Y | N | N | -+-----------+-----+-----+------+------+----------+------+-------+ - -The table below shows which drivers are currently available in Zephyr. - -+-----------+------------+-------+-----------------------+ -| Interface | Controller | EMSDP | Driver/Component | -+===========+============+=======+=======================+ -| SDIO | on-chip | N | SD-card controller | -+-----------+------------+-------+-----------------------+ -| UART | Arduino + | Y | serial port-polling; | -| | 3 Pmods | | serial port-interrupt | -+-----------+------------+-------+-----------------------+ -| SPI | Arduino + | Y | spi | -| | Pmod + adc | | | -+-----------+------------+-------+-----------------------+ -| ADC | 1 Pmod | N | adc (via spi) | -+-----------+------------+-------+-----------------------+ -| I2C | Arduino + | N | i2c | -| | Pmod | | | -+-----------+------------+-------+-----------------------+ -| GPIO | Arduino + | Y | gpio | -| | Pmod + Pin | | | -+-----------+------------+-------+-----------------------+ -| PWM | Arduino + | N | pwm | -| | Pmod | | | -+-----------+------------+-------+-----------------------+ -| I2S | on-chip | N | Audio interface | -+-----------+------------+-------+-----------------------+ - -Support two 32 MByte Quad-SPI Flash memory, one only contains FPGA image, the other -one is user SPI-FLASH, which is connected via SPI bus and its sample can be found in -``samples/drivers/spi_flash``. - -To configure the FPGA, The ARC EM SDP offers a single USB 2.0 host port, which is -both used to access the FPGAs configuration memory and as a DEBUG/ UART port. - -When connected using the USB cable to a PC, the ARC EM SDP presents itself as a mass -storage device. This allows an FPGA configuration bitstream to be dragged and dropped into -the configuration memory. The FPGA bitstream is automatically loaded into the FPGA device -upon power-on reset, or when the configuration button is pressed. - -For hardware feature details, refer to : `ARC EM Software Development Platform -`__ - -Peripheral driver test and sample -================================= - -``tests/drivers/spi/spi_loopback``: verify DesignWare SPI driver. No need to connect -MISO with MOSI, DW SPI register is configured to internally connect them. This test -use two different speed to verify data transfer with asynchronous functionality. -Note: DW SPI only available on SPI0 and SPI1. - -``samples/drivers/spi_flash``: Verfiy DW SPI and SPI-FLASH on SPI1. First erase the -whole flash then write 4 byte data to the flash. Read from the flash and compare the -result with buffer to check functionality. - -Pinmux interface -================ - -The following pinmux peripheral module standards are supported: - -* Digilent Pmod (3x) - -The ARC EM SDP features three 12-pin Pmod connectors: Pmod_A, Pmod_B, and Pmod_C. -The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, -I2C, and PWM (Note: support two type UART Pmod interface: UARTA is newer version). -Multiplexing is controlled by software using the PMOD_MUX_CTRL register. - -* Arduino (1x) - -The ARC EM SDP provides an Arduino shield interface. Multiplexing is controlled by software -using the ARDUINO_MUX_CTRL register. Note: some IO must be programmed in group and can't be -set individually, for details see Table 9 in `EM Software Development Platform user guide`_. - -* MikroBUS (1x) - -Note that since the controllers that are mapped to the MikroBUS are shared with the Arduino -controllers, and therefore the MikroBUS functions are only available when the Arduino -multiplexer ARDUINO_MUX_CTRL is in the default mode (GPIO). - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To use Zephyr RTOS applications on the EM Software Development Platform board, -a few additional pieces of hardware are required. - -* A micro USB cable to connect the computer. - -* A universal switching power adaptor (110-240V AC to 12 DC), - provided in the package, which used to power the board. - -* :ref:`The Zephyr SDK ` - -* Terminal emulator software for use with the USB-UART. Suggestion: - `Putty Website`_. - -* (optional) A collection of Pmods, Arduino modules, or Mikro modules. - See `Digilent Pmod Modules`_ or develop your custom interfaces to attach - to the Pmod connector. - -Set up the EM Software Development Platform -=========================================== - -To run Zephyr application on EM Software Development Platform, you need to -setup the board correctly. - -* Connect the 12V DC power supply to your board. - -* Connect the digilent usb cable from your host to the board. - -Set up Zephyr Software -====================== - -Building Sample Applications -============================== - -You can try many of the sample applications or tests, but let us discuss -the one called :ref:`hello_world`. -It is found in :zephyr_file:`samples/hello_world`. - -Configuring ------------ - -You may need to write a prj_arc.conf file if the sample doesn't have one. -Next, you can use the menuconfig rule to configure the target. By specifying -``emsdp`` as the board configuration, you can select the ARC EM Software -Development Platform board support for Zephyr. - -.. zephyr-app-commands:: - :board: emsdp - :zephyr-app: samples/hello_world - :goals: menuconfig - - -Building --------- - -You can build an application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: emsdp - :zephyr-app: samples/hello_world - :maybe-skip-config: - :goals: build - -Connecting Serial Output -========================= - -In the default configuration, Zephyr's EM Software Development Platform images -support serial output via the USB-UART on the board. To enable serial output: - -* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) - -* Specify the tty driver name, for example, on Linux this may be - :file:`/dev/ttyUSB0` - -* Set the communication settings to: - - -========= ===== -Parameter Value -========= ===== -Baud: 115200 -Data: 8 bits -Parity: None -Stopbits: 1 -========= ===== - -Debugging -========== - -Using the latest version of Zephyr SDK(>=0.9), you can debug and flash IoT -Development Kit directly. - -One option is to build and debug the application using the usual -Zephyr build system commands. - -.. zephyr-app-commands:: - :board: emsdp - :app: - :goals: debug - -At this point you can do your normal debug session. Set breakpoints and then -'c' to continue into the program. - -The other option is to launch a debug server, as follows. - -.. zephyr-app-commands:: - :board: emsdp - :app: - :goals: debugserver - -Then connect to the debug server at the EM Software Development Platform from a -second console, from the build directory containing the output :file:`zephyr.elf`. - -.. code-block:: console - - $ cd - $ $ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/ \ - arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf - (gdb) target remote localhost:3333 - (gdb) load - (gdb) b main - (gdb) c - -Flashing -======== - -If you just want to download the application to the EM Software Development -Platform's CCM and run, you can do so in the usual way. - -.. zephyr-app-commands:: - :board: emsdp - :app: - :goals: flash - -This command still uses openocd and gdb to load the application elf file to EM -Software Development Platform, but it will load the application and immediately run. -If power is removed, the application will be lost since it wasn't written to flash. - -Most of the time you will not be flashing your program but will instead debug -it using openocd and gdb. The program can be download via the USB cable into -the code and data memories. - -References -********** - -.. target-notes:: - -.. _EM Software Development Platform user guide: - https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform - -.. _Digilent Pmod Modules: - http://store.digilentinc.com/pmod-modules - -.. _Putty website: - http://www.putty.org diff --git a/boards/arc/emsdp/emsdp.yaml b/boards/arc/emsdp/emsdp.yaml deleted file mode 100644 index c5a9afc8da410c..00000000000000 --- a/boards/arc/emsdp/emsdp.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp -name: EM Software Development Platform (EM11D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em4.yaml b/boards/arc/emsdp/emsdp_em4.yaml deleted file mode 100644 index 9be5bbca31b830..00000000000000 --- a/boards/arc/emsdp/emsdp_em4.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: emsdp_em4 -name: EM Software Development Platform (EM4) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em4_defconfig b/boards/arc/emsdp/emsdp_em4_defconfig deleted file mode 100644 index 40c816b1db491a..00000000000000 --- a/boards/arc/emsdp/emsdp_em4_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM4=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y diff --git a/boards/arc/emsdp/emsdp_em5d.yaml b/boards/arc/emsdp/emsdp_em5d.yaml deleted file mode 100644 index 80cbc08e066152..00000000000000 --- a/boards/arc/emsdp/emsdp_em5d.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: emsdp_em5d -name: EM Software Development Platform (EM5D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em5d_defconfig b/boards/arc/emsdp/emsdp_em5d_defconfig deleted file mode 100644 index 2d117c7f42de9d..00000000000000 --- a/boards/arc/emsdp/emsdp_em5d_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM5D=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em6.yaml b/boards/arc/emsdp/emsdp_em6.yaml deleted file mode 100644 index ce15754d7be645..00000000000000 --- a/boards/arc/emsdp/emsdp_em6.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp_em6 -name: EM Software Development Platform (EM6) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em6_defconfig b/boards/arc/emsdp/emsdp_em6_defconfig deleted file mode 100644 index 7bcaa11ecb0dc4..00000000000000 --- a/boards/arc/emsdp/emsdp_em6_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM6=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em7d.yaml b/boards/arc/emsdp/emsdp_em7d.yaml deleted file mode 100644 index e3591d300f5440..00000000000000 --- a/boards/arc/emsdp/emsdp_em7d.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: emsdp_em7d -name: EM Software Development Platform (EM7D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em7d_defconfig b/boards/arc/emsdp/emsdp_em7d_defconfig deleted file mode 100644 index 5c10716fe75b5e..00000000000000 --- a/boards/arc/emsdp/emsdp_em7d_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM7D=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y diff --git a/boards/arc/emsdp/emsdp_em7d_esp.yaml b/boards/arc/emsdp/emsdp_em7d_esp.yaml deleted file mode 100644 index 2b8cc296bb893a..00000000000000 --- a/boards/arc/emsdp/emsdp_em7d_esp.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp_em7d_esp -name: EM Software Development Platform (EM7D_ESP) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em7d_esp_defconfig b/boards/arc/emsdp/emsdp_em7d_esp_defconfig deleted file mode 100644 index b67dca68179a76..00000000000000 --- a/boards/arc/emsdp/emsdp_em7d_esp_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM7D_ESP=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_ARC_HAS_SECURE=y -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em9d.yaml b/boards/arc/emsdp/emsdp_em9d.yaml deleted file mode 100644 index f20f29d18d0112..00000000000000 --- a/boards/arc/emsdp/emsdp_em9d.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: emsdp_em9d -name: EM Software Development Platform (EM9D) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools -ram: 128 -supported: - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/emsdp/emsdp_em9d_defconfig b/boards/arc/emsdp/emsdp_em9d_defconfig deleted file mode 100644 index 5a7342f67b2695..00000000000000 --- a/boards/arc/emsdp/emsdp_em9d_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM9D=y -CONFIG_BOARD_EMSDP=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_GPIO=y -CONFIG_SPI=y diff --git a/boards/arc/hsdk/Kconfig.board b/boards/arc/hsdk/Kconfig.board deleted file mode 100644 index 975d2f5ab245a3..00000000000000 --- a/boards/arc/hsdk/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# DesignWare ARC HS Development Kit board configuration - -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HSDK - bool "ARC HS Development Kit" - depends on SOC_ARC_HSDK - help - The DesignWare ARC HS Development Kit is a ready-to-use platform for - rapid software development on the ARC HS3x family of processors. It - supports single- and multi-core ARC HS34, HS36 and HS38 processors - and offers a wide range of interfaces diff --git a/boards/arc/hsdk/Kconfig.defconfig b/boards/arc/hsdk/Kconfig.defconfig deleted file mode 100644 index c6ba3652de56ad..00000000000000 --- a/boards/arc/hsdk/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HSDK - -config BOARD - default "hsdk" - -if SPI_DW - -config SPI_DW_ACCESS_WORD_ONLY - default y - -endif # SPI_DW - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 200 - -endif #I2C_DW - -endif # BOARD_HSDK diff --git a/boards/arc/hsdk/board.cmake b/boards/arc/hsdk/board.cmake deleted file mode 100644 index 40d4c22d3b5439..00000000000000 --- a/boards/arc/hsdk/board.cmake +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf") - -if(${CONFIG_MP_MAX_NUM_CPUS} EQUAL 2) -board_runner_args(openocd "--config=${CMAKE_CURRENT_LIST_DIR}/support/openocd-2-cores.cfg") -endif() - -board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/arc/hsdk/hsdk_2cores.yaml b/boards/arc/hsdk/hsdk_2cores.yaml deleted file mode 100644 index d21fa765887ef8..00000000000000 --- a/boards/arc/hsdk/hsdk_2cores.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: hsdk_2cores -name: HS Development Kit(2 cores) -type: mcu -arch: arc -toolchain: - - zephyr - - cross-compile - - xtools - - arcmwdt -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/hsdk/hsdk_2cores_defconfig b/boards/arc/hsdk/hsdk_2cores_defconfig deleted file mode 100644 index ccc920e7103619..00000000000000 --- a/boards/arc/hsdk/hsdk_2cores_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_ARC_HSDK=y -CONFIG_BOARD_HSDK=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_NO_GAP_FILL=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 diff --git a/boards/arc/hsdk4xd/Kconfig.board b/boards/arc/hsdk4xd/Kconfig.board deleted file mode 100644 index 76819350da3af9..00000000000000 --- a/boards/arc/hsdk4xd/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# DesignWare ARC HSDK4XD Development Kit board configuration - -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HSDK4XD - bool "ARC HSDK4XD Development Kit" - depends on SOC_ARC_HSDK4XD - help - The ARC HS4x/4xD Development Kit is a ready-to-use software development - platform for the ARC HS4x/4xD family of processor IP. It includes - a multicore ARC HS4x/HS4xD-based chip and integrates a wide range - of interfaces. diff --git a/boards/arc/hsdk4xd/Kconfig.defconfig b/boards/arc/hsdk4xd/Kconfig.defconfig deleted file mode 100644 index cabe258f68ff18..00000000000000 --- a/boards/arc/hsdk4xd/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HSDK4XD - -config BOARD - default "hsdk4xd" - -endif #BOARD_HSDK4XD diff --git a/boards/arc/hsdk4xd/board.cmake b/boards/arc/hsdk4xd/board.cmake deleted file mode 100644 index 04fb70c5dad60b..00000000000000 --- a/boards/arc/hsdk4xd/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf") - -board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/arc/hsdk4xd/doc/index.rst b/boards/arc/hsdk4xd/doc/index.rst deleted file mode 100644 index ee59fe32d2cadc..00000000000000 --- a/boards/arc/hsdk4xd/doc/index.rst +++ /dev/null @@ -1,557 +0,0 @@ -.. _hsdk4xd: - -DesignWare(R) ARC(R) HS4x/HS4xD Development Kit -############################################### - -Overview -******** - -The ARC HS4x/HS4xD Development Kit is the next revision of :ref:`Synopsys HSDK board `. -It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces -including Ethernet, HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and GPIO, -as well as a Think Silicon GPU. - -.. image:: hsdk4xd.jpg - :align: center - :alt: DesignWare(R) ARC(R) HS4x/HS4xD Development Kit (synopsys.com) - -For details about the board, see: `ARC HS4x/HS4xD Development Kit -(HSDK4xD) `__ - -Hardware -******** - -The ARC HSDK4xD has 24 general GPIOs, which divided into 8 groups named from ``GPIO_SEL_0`` to ``GPIO_SEL_7``. -Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can program -``CREG_GPIO_MUX`` register to do configuration for each sel. Tables below show the bit definition for -``CREG_GPIO_MUX`` register and the details configuration for each pin. - -+--------+-------------+---------+--------------+---------------------------------+ -| Bit | Name | Access | Reset value | Description | -+--------+-------------+---------+--------------+---------------------------------+ -| 2:0 | GPIO_SEL_0 | RW | 0x0 | GPIO mux select for gpio[3:0] | -+--------+-------------+---------+--------------+---------------------------------+ -| 5:3 | GPIO_SEL_1 | RW | 0x0 | GPIO mux select for gpio[7:4] | -+--------+-------------+---------+--------------+---------------------------------+ -| 8:6 | GPIO_SEL_2 | RW | 0x0 | GPIO mux select for gpio[11:8] | -+--------+-------------+---------+--------------+---------------------------------+ -| 11:9 | GPIO_SEL_3 | RW | 0x0 | GPIO mux select for gpio[15:12] | -+--------+-------------+---------+--------------+---------------------------------+ -| 14:12 | GPIO_SEL_4 | RW | 0x0 | GPIO mux select for gpio[17:16] | -+--------+-------------+---------+--------------+---------------------------------+ -| 17:15 | GPIO_SEL_5 | RW | 0x0 | GPIO mux select for gpio[19:18] | -+--------+-------------+---------+--------------+---------------------------------+ -| 20:18 | GPIO_SEL_6 | RW | 0x0 | GPIO mux select for gpio[21:20] | -+--------+-------------+---------+--------------+---------------------------------+ -| 23:21 | GPIO_SEL_7 | RW | 0x0 | GPIO mux select for gpio[23:22] | -+--------+-------------+---------+--------------+---------------------------------+ - -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SELS | GPIO PINS | FUN0 | FUN1 | FUN2 | FUN3 | FUN4 | FUN5 | FUN6 | FUN7 | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_ch[6] | pwm_ch[1] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 1 | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_ch[0] | pwm_ch[0] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 2 | gpio[2] | uart0_rxd | spi1 _miso | i2c1_scl | gpio[2] | gpio[2] | gpio[2] | gpio[2] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 3 | gpio[3] | uart0_rts | spi1_clk | i2c1_sda | gpio[3] | gpio[3] | gpio[3] | gpio[3] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL1 | 4 | gpio[4] | uart1_cts | spi2_cs[0] | gpio[4] | gpio[4] | pwm_ch[4] | pwm_ch[4] | pwm_ch[3] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 5 | gpio[5] | uart1_txd | spi2_mosi | gpio[5] | pwm_ch[2] | gpio[5] | pwm_ch[2] | pwm_ch[2] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 6 | gpio[6] | uart1_rxd | spi2_miso | i2c2_scl | gpio[6] | gpio[6] | gpio[6] | gpio[6] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 7 | gpio[7] | uart1_rts | spi2_clk | i2c2_sda | gpio[7] | gpio[7] | gpio[7] | gpio[7] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL2 | 8 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | pwm_ch[2] | pwm_ch[5] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 9 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | pwm_ch[4] | pwm_ch[4] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 10 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | gpio[10] | gpio[10] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 11 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | gpio[11] | gpio[11] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL3 | 12 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | pwm_ch[0] | pwm_ch[7] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 13 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | pwm_ch[6] | pwm_ch[6] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 14 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | gpio[14] | gpio[14] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 15 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | gpio[15] | gpio[15] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL4 | 16 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | pwm_fault_0 | gpio[16] | pwm_fault_0 | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 17 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | pwm_ch[0] | pwm_ch[5] | pwm_ch[5] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL5 | 18 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | gpio[18] | gpio[18] | gpio[18] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 19 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | gpio[19] | gpio[19] | gpio[19] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL6 | 20 | gpio[20] | uart0_txd | spi2_cs[2] | i2c1_scl | gpio[20] | pwm_fault_1 | gpio[20] | pwm_fault_1 | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 21 | gpio[21] | uart0_rxd | spi2_mosi | i2c1_sda | pwm_ch[6] | pwm_ch[6] | pwm_ch[3] | pwm_ch[3] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| SEL7 | 22 | gpio[22] | uart2_txd | spi2_miso | i2c2_scl | gpio[22] | gpio[22] | gpio[22] | gpio[22] | -| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ -| | 23 | gpio[23] | uart2_rxd | spi2_clk | i2c2_sda | gpio[23] | gpio[23] | gpio[23] | gpio[23] | -+------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ - -Digilent Pmod -============= - -The ARC HSDK4xD features two 12-pin Pmod connectors ``Pmod_A`` and ``Pmod_B`` and one 6-pin Pmod connector ``Pmod_C``. -The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, I2C and PWM. -The location of the pins on the Pmod connectors is shown in Figure below. Detailed pin descriptions -depending on the pin multiplexer settings are provided in the subsequent sections. - -.. image:: pinout_diagram_of_the_pmod.jpg - :align: center - :alt: Pinout Diagram of the Pmod - -Pmod_A Connector ----------------- - -Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_A`` -connector. The GPIO column is the default assignment after Reset. - -+------+-----------+------------+-------------+-----------+------------+-----------+ -| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A1 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A2 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A3 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A4 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A5 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A7 | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A8 | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A11 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| A12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ - -Pmod_B Connector ----------------- - -Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_B`` -connector. The GPIO column is the default assignment after Reset. - -+------+-----------+------------+-------------+-----------+------------+-----------+ -| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B1 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B2 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B3 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B4 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B5 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B7 | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B8 | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B11 | GND | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+------------+-----------+ -| B12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+------------+-----------+ - -Pmod_C Connector ----------------- - -Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_C`` -connector. The GPIO column is the default assignment after Reset. - -+------+-----------+------------+-------------+-----------+-----------+ -| Pin | GPIO | UART | SPI | I2C | PWM | -+------+-----------+------------+-------------+-----------+-----------+ -| C1 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | -+------+-----------+------------+-------------+-----------+-----------+ -| C2 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | -+------+-----------+------------+-------------+-----------+-----------+ -| C3 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | -+------+-----------+------------+-------------+-----------+-----------+ -| C4 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | -+------+-----------+------------+-------------+-----------+-----------+ -| C5 | GND | GND | GND | GND | GND | -+------+-----------+------------+-------------+-----------+-----------+ -| C6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | -+------+-----------+------------+-------------+-----------+-----------+ - -Mikrobus -======== - -The ARC HSDK4xD features a set of MikroBUS headers. Figure below shows the relevant function assignments, -fully compatible with the MikroBUS standard. Table below shows the pin assignment on the I/O Multiplexer. - -.. image:: mikrobus_header.jpg - :align: center - :alt: mikrobus header - -+-------+-----------------+------+-----------+ -| Pin | I/O | Pin | I/O | -+-------+-----------------+------+-----------+ -| AN | ADC VIN6* | PWM | pwm_ch[0] | -+-------+-----------------+------+-----------+ -| RST | GPX_Port0_bit1 | INT | gpio[16] | -+-------+-----------------+------+-----------+ -| CS | spi2_cs[1] | RX | uart2_rxd | -+-------+-----------------+------+-----------+ -| SCK | spi2_clk | TX | uart2_txd | -+-------+-----------------+------+-----------+ -| MISO | spi2_miso | SCL | i2c2_scl | -+-------+-----------------+------+-----------+ -| MOSI | spi2_mosi | SDA | i2c2_sda | -+-------+-----------------+------+-----------+ - -.. note:: - ADC VIN6 is available through the on-board ADC and is - read though SPI0 using SPI chip select 1. - -Arduino -======= - -The ARC HSDK4xD provides an Arduino shield interface. Figure below shows the relevant -function assignments. The Arduino shield interface is compatible with the Arduino UNO -R3 with the following exceptions: 5 Volt shields are not supported, the IOREF voltage on -the ARC HSDK4xD board is fixed to 3V3. Note that the ICSP header is also not available. Most -shields do not require this ICSP header as the SPI master interface on this ICSP header -is also available on the ``IO10`` to ``IO13`` pins. - -.. image:: arduino_shield_interface.jpg - :align: center - :alt: arduino shield interface - -Table below shows the pin assignment on the I/O Multiplexer. Multiplexing is controlled by software -using the ``CREG_GPIO_MUX`` register (see Pinmux ). After a reset, all ports are configured as GPIO inputs. - -+-------+------------+-----------------+------------+ -| Pin | I/O-1 | I/O-2 | I/O-3 | -+-------+------------+-----------------+------------+ -| AD0 | ADC VIN0* | GPX_port0_bit2 | - | -+-------+------------+-----------------+------------+ -| AD1 | ADC VIN1* | GPX_port0_bit3 | - | -+-------+------------+-----------------+------------+ -| AD2 | ADC VIN2* | GPX_port0_bit4 | - | -+-------+------------+-----------------+------------+ -| AD3 | ADC VIN3* | GPX_port0_bit5 | - | -+-------+------------+-----------------+------------+ -| AD4 | ADC VIN4* | gpio[18] | i2c2_sda | -+-------+------------+-----------------+------------+ -| AD5 | ADC VIN5* | gpio[19] | i2c2_scl | -+-------+------------+-----------------+------------+ -| IO0 | gpio[23] | uart2_rxd | - | -+-------+------------+-----------------+------------+ -| IO1 | gpio[22] | uart2_txd | - | -+-------+------------+-----------------+------------+ -| IO2 | gpio[16] | - | - | -+-------+------------+-----------------+------------+ -| IO3 | gpio[17] | pwm_ch[5] | - | -+-------+------------+-----------------+------------+ -| IO4 | gpio[11] | - | | -+-------+------------+-----------------+------------+ -| IO5 | gpio[9] | pwm_ch[4] | - | -+-------+------------+-----------------+------------+ -| IO6 | gpio[21] | pwm_ch[3] | - | -+-------+------------+-----------------+------------+ -| IO7 | gpio[20] | - | - | -+-------+------------+-----------------+------------+ -| IO8 | gpio[10] | - | - | -+-------+------------+-----------------+------------+ -| IO9 | gpio[8] | pwm_ch[2] | - | -+-------+------------+-----------------+------------+ -| IO10 | gpio[12] | pwm_ch[0] | spi2_cs[1] | -+-------+------------+-----------------+------------+ -| IO11 | gpio[13] | pwm_ch[6] | spi2_mosi | -+-------+------------+-----------------+------------+ -| IO12 | gpio[14] | - | spi2_miso | -+-------+------------+-----------------+------------+ -| IO13 | gpio[15] | - | spi2_clk | -+-------+------------+-----------------+------------+ - -I/O expander -============ - -The ARC HSDK4xD board includes a CY8C9520A I/O expander from `Cypress CY8C9520A -`__. The I/O -expander offers additional GPIO signals and board control signals and can be accessed -through the on-board I2C bus, we have implemented a basic driver for it. -Tables below shows an overview of relevant I/O signals. - -+------------+---------------------------------------------+ -| Pins | Usage | -+------------+---------------------------------------------+ -| port0_bit0 | RS9113 Bluetooth I2S RX enable (active low) | -+------------+---------------------------------------------+ -| port0_bit1 | mikroBUS Reset (active low) | -+------------+---------------------------------------------+ -| port0_bit2 | GPIO for Arduino AD0 | -+------------+---------------------------------------------+ -| port0_bit3 | GPIO for Arduino AD1 | -+------------+---------------------------------------------+ -| port0_bit4 | GPIO for Arduino AD2 | -+------------+---------------------------------------------+ -| port0_bit5 | GPIO for Arduino AD3 | -+------------+---------------------------------------------+ -| port1_bit4 | On-board user LED0 | -+------------+---------------------------------------------+ -| port1_bit5 | On-board user LED1 | -+------------+---------------------------------------------+ -| port1_bit6 | On-board user LED2 | -+------------+---------------------------------------------+ -| port1_bit7 | On-board user LED3 | -+------------+---------------------------------------------+ - -On-board user LEDS -================== - -The ARC HSDK4xD includes 4 user LEDs(active high), which can be controlled through the I/O expander pins. - -+-------+-----------------+ -| LEDs | PINs | -+-------+-----------------+ -| LED0 | GPX_port1_bit4 | -+-------+-----------------+ -| LED1 | GPX_port1_bit5 | -+-------+-----------------+ -| LED2 | GPX_port1_bit6 | -+-------+-----------------+ -| LED3 | GPX_port1_bit7 | -+-------+-----------------+ - -For hardware feature details, refer to : `Designware HS4x/HS4xD Development Kit website -`__. - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To use Zephyr RTOS applications on the HS4x/HS4xD Development Kit board, a few -additional pieces of hardware are required. - -* A micro USB cable provides USB-JTAG debug and USB-UART communication - to the board - -* A universal switching power adaptor (110-240V - AC to 12V DC), provided in the package, provides power to the board. - -* :ref:`The Zephyr SDK ` - -* Terminal emulator software for use with the USB-UART. Suggestion: - `Putty Website`_. - -* (optional) A collection of Pmods, Arduino modules, or Mikro modules. - See `Digilent Pmod Modules`_ or develop your custom interfaces to attach - to the Pmod connector. - -Set up the ARC HS4x/HS4xD Development Kit -========================================= - -To run Zephyr application on ARC HS4x/HS4xD Development Kit, you need to -set up the board correctly. - -* Connect the digilent USB cable from your host to the board. - -* Connect the 12V DC power supply to your board - -Set up Zephyr Software -====================== - -Building Sample Applications -============================== - -You can try many of the :ref:`sample applications and demos -`. We'll use :ref:`hello_world`, found in -:zephyr_file:`samples/hello_world` as an example. - -Configuring ------------ - -You may need to write a ``prj_arc.conf`` file if the sample doesn't have one. -Next, you can use the menuconfig rule to configure the target. By specifying -``hsdk4xd`` as the board configuration, you can select the ARC HS4x/HS4xD Development -Kit board support for Zephyr. - -.. zephyr-app-commands:: - :board: hsdk4xd - :zephyr-app: samples/hello_world - :goals: menuconfig - - -Building --------- - -You can build an application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: hsdk4xd - :zephyr-app: samples/hello_world - :maybe-skip-config: - :goals: build - - -Connecting Serial Output -========================= - -In the default configuration, Zephyr's HS4x/HS4xD Development Kit images support -serial output via the USB-UART on the board. To enable serial output: - -* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) - -* Specify the tty driver name, for example, on Linux this may be - :file:`/dev/ttyUSB0` - -* Set the communication settings to: - - -========= ===== -Parameter Value -========= ===== -Baud: 115200 -Data: 8 bits -Parity: None -Stopbits: 1 -========= ===== - -Debugging -========== - -Using the latest version of Zephyr SDK(>=0.15.2), you can debug and -flash (run) HS4x/HS4xD Development Kit directly. - -One option is to build and debug the application using the usual -Zephyr build system commands. - -.. zephyr-app-commands:: - :board: hsdk4xd - :app: - :goals: debug - -At this point you can do your normal debug session. Set breakpoints and then -:kbd:`c` to continue into the program. - -The other option is to launch a debug server, as follows. - -.. zephyr-app-commands:: - :board: hsdk4xd - :app: - :goals: debugserver - -Then connect to the debug server at the HS4x/HS4xD Development Kit from a second -console, from the build directory containing the output :file:`zephyr.elf`. - -.. code-block:: console - - $ cd - $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf - (gdb) target remote localhost:3333 - (gdb) load - (gdb) b main - (gdb) c - -Flashing -======== - -If you just want to download the application to the HS4x/HS4xD Development Kit's DDR -and run, you can do so in the usual way. - -.. zephyr-app-commands:: - :board: hsdk4xd - :app: - :goals: flash - -This command still uses openocd and gdb to load the application elf file to -HS4x/HS4xD Development Kit, but it will load the application and immediately run. If -power is removed, the application will be lost since it wasn't written to flash. - -Most of the time you will not be flashing your program but will instead debug -it using openocd and gdb. The program can be download via the USB cable into -the code and data memories. - -The HS4x/HS4xD Development Kit also supports flashing the Zephyr application -with the U-Boot bootloader, a powerful and flexible tool for loading -an executable from different sources and running it on the target platform. - -The U-Boot implementation for the HS4x/HS4xD Development Kit was further extended with -additional functionality that allows users to better manage the broad -configurability of the HS4x/HS4xD Development Kit - -When you are ready to deploy the program so that it boots up automatically on -reset or power-up, you can follow the steps to place the program on SD card. - -For details, see: `Uboot-HS4x/HS4xD-Command-Reference -`__ - -Supported peripheral -==================== - -The following list indicates the state of HS4x/HS4xD Development Kit peripherals’ support - -+------------+---------+ -| Peripheral | Support | -+------------+---------+ -| ADC | No | -+------------+---------+ -| Bluetooth | No | -+------------+---------+ -| Ethernet | No | -+------------+---------+ -| GPIO | No | -+------------+---------+ -| GPU | No | -+------------+---------+ -| HDMI | No | -+------------+---------+ -| I2C | No | -+------------+---------+ -| I2S | No | -+------------+---------+ -| PWM | No | -+------------+---------+ -| SDIO | No | -+------------+---------+ -| SPI | No | -+------------+---------+ -| UART | Yes | -+------------+---------+ -| USB | No | -+------------+---------+ -| WiFi | No | -+------------+---------+ - -References -********** - -.. _embARC website: https://www.embarc.org - -.. _Designware HS Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit - -.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules - -.. _Putty website: http://www.putty.org diff --git a/boards/arc/hsdk4xd/hsdk4xd.dts b/boards/arc/hsdk4xd/hsdk4xd.dts deleted file mode 100644 index e58b349c3621c0..00000000000000 --- a/boards/arc/hsdk4xd/hsdk4xd.dts +++ /dev/null @@ -1,14 +0,0 @@ -/* - * Copyright (c) 2023, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "hsdk4xd.dtsi" - -/ { - model = "hsdk4xd"; - compatible = "snps,hsdk4xd"; -}; diff --git a/boards/arc/hsdk4xd/hsdk4xd.dtsi b/boards/arc/hsdk4xd/hsdk4xd.dtsi deleted file mode 100644 index 1e0fa062b9820c..00000000000000 --- a/boards/arc/hsdk4xd/hsdk4xd.dtsi +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2023, Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - - aliases { - uart-dbg = &uart_dbg; - }; - - chosen { - zephyr,sram = &ddr0; - zephyr,console = &uart_dbg; - zephyr,shell-uart = &uart_dbg; - }; - -}; - -arduino_spi: &spi2 {}; - -&uart_dbg { - status = "okay"; - current-speed = <115200>; -}; - -&creg_gpio { - status = "okay"; -}; diff --git a/boards/arc/index.rst b/boards/arc/index.rst deleted file mode 100644 index 816048df0acc54..00000000000000 --- a/boards/arc/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-arc: - -ARC Boards -########## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/arc/iotdk/Kconfig.board b/boards/arc/iotdk/Kconfig.board deleted file mode 100644 index a92c55ec740d36..00000000000000 --- a/boards/arc/iotdk/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# DesignWare ARC IoT Development Kit board configuration - -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IOTDK - bool "ARC IoT Development Kit" - depends on SOC_ARC_IOT - help - The DesignWare ARC IoT Development Kit board is a versatile platform that includes the necessary hardware and software to accelerate software development and debugging of sensor fusion, voice recognition and face detection designs. It includes a silicon implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's 55-nm ultra-low power process, and a rich set of peripherals commonly used in IoT designs such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. diff --git a/boards/arc/iotdk/Kconfig.defconfig b/boards/arc/iotdk/Kconfig.defconfig deleted file mode 100644 index 93f707a0afba57..00000000000000 --- a/boards/arc/iotdk/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "iotdk" - depends on BOARD_IOTDK diff --git a/boards/arc/iotdk/board.cmake b/boards/arc/iotdk/board.cmake deleted file mode 100644 index 292253eb64e8e4..00000000000000 --- a/boards/arc/iotdk/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd "--use-elf") -board_runner_args(mdb-hw "--jtag=digilent") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/arc/iotdk/board.dtsi b/boards/arc/iotdk/board.dtsi deleted file mode 100644 index 0f1a02d0213eee..00000000000000 --- a/boards/arc/iotdk/board.dtsi +++ /dev/null @@ -1,2 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - diff --git a/boards/arc/nsim/Kconfig.board b/boards/arc/nsim/Kconfig.board deleted file mode 100644 index 6bec8088323d46..00000000000000 --- a/boards/arc/nsim/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# DesignWare ARC nSIM simulated platform configuration - -# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NSIM - bool "ARC nSIM simulator" - depends on SOC_NSIM - select HAS_COVERAGE_SUPPORT - help - The DesignWare ARC nSIM board is a virtual board based on - the ARC nSIM simulator. It demonstrates the ARC core features - and a console based on the ns16550 UART model. diff --git a/boards/arc/nsim/Kconfig.defconfig b/boards/arc/nsim/Kconfig.defconfig deleted file mode 100644 index 1f1e19ee38abc7..00000000000000 --- a/boards/arc/nsim/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NSIM - -config BOARD - default "nsim" - -endif # BOARD_NSIM diff --git a/boards/arc/nsim/doc/index.rst b/boards/arc/nsim/doc/index.rst deleted file mode 100644 index 4e7054fc43b0a4..00000000000000 --- a/boards/arc/nsim/doc/index.rst +++ /dev/null @@ -1,339 +0,0 @@ -.. _nsim: - -DesignWare ARC nSIM and HAPS FPGA boards -######################################## - -Overview -******** - -This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in -simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The -platform includes the following features: - -* ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to - :ref:`here ` for a complete list of ARC processor families which - currently supported -* Virtual serial console (a standard ``ns16550`` UART model) - -ARC processors are known for being highly customizable and some but not all of the configurations -are currently supported in the Zephyr RTOS for ARC, again please refer to -:ref:`here ` for a complete list of supported features. - -There are multiple supported sub-configurations for that platform. Some but not all of currently -available configurations are listed below: - -* ``nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and - XY-memory -* ``nsim_em_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's -* ``nsim_em_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options and - XY-memory -* ``nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4 -* ``nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 -* ``nsim_hs_smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 -* ``nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template -* ``nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options -* ``nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options -* ``nsim_hs5x_smp_12cores`` - SMP 12 cores 32-bit ARCv3 HS platform -* ``nsim_hs6x_smp_12cores`` - SMP 12 cores 64-bit ARCv3 HS platform - -.. _board_arc_nsim_prop_args_files: - -It is recommended to look at precise description of a particular sub-configuration in either -``.props`` or ``.args`` files in :zephyr_file:`boards/arc/nsim/support/` directory to understand -which options are configured and so will be used on invocation of the simulator. - -In case of single-core configurations it would be ``.props`` file which contains configuration -for nSIM simulator and ``.args`` file which contains configuration for MetaWare debugger (MDB). -Note that these files contain identical HW configuration and meant to be used with the corresponding -tool: ``.props`` file for nSIM simulator and ``.args`` file for MDB (which internally uses nSIM for -simulation anyway). - -.. hint:: - If different behavior is observed during execution or debugging of a particular application - (especially after creation of a new board or modification of the existing one) make sure features - defined in ``.props`` and ``.args`` are semantically identical (unfortunately options of - nSIM & MDB don't exactly match, so care should be taken). - -I.e. for the single-core ``nsim_hs5x`` platform there are -:zephyr_file:`boards/arc/nsim/support/nsim_hs5x.props` and -:zephyr_file:`boards/arc/nsim/support/mdb_hs5x.args`. - -For the multi-core configurations there is only ``.args`` file as the multi-core configuration -can only be instantiated with help of MDB. - -I.e. for the multi-core ``nsim_hs5x_smp`` platform there is only -:zephyr_file:`boards/arc/nsim/support/mdb_hs5x_smp.args`. - -.. warning:: - All nSIM/MDB configurations are used for demo and testing purposes. They are not meant to - represent any real system and so might be renamed, removed or modified at any point. - -Programming and Debugging -************************* - -Required Hardware and Software -============================== - -To run single-core Zephyr RTOS applications in simulation on this board, -either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required. - -To run multi-core Zephyr RTOS applications in simulation on this board, -`DesignWare ARC nSIM`_ and MetaWare Debugger from `ARC MWDT`_ are required. - -To run Zephyr RTOS applications on FPGA-based `HAPS`_ platform, -MetaWare Debugger from `ARC MWDT`_ is required as well as the HAPS platform itself. - -Building & Running Sample Applications -====================================== - -Most board sub-configurations support building with both GNU and ARC MWDT toolchains, however -there might be exceptions from that, especially for newly added targets. You can check supported -toolchains for the sub-configurations in the corresponding ``.yaml`` file. - -I.e. for the ``nsim_hs5x`` board we can check :zephyr_file:`boards/arc/nsim/nsim_hs5x.yaml` - -The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find: - -* **zephyr** - implies ARC GNU toolchain from Zephyr SDK. You can find more information about - Zephyr SDK :ref:`here `. -* **cross-compile** - implies ARC GNU cross toolchain, which is not a part of Zephyr SDK. Note that - some (especially new) sub-configurations may declare ``cross-compile`` toolchain support without - ``zephyr`` toolchain support because corresponding target CPU support hasn't been added to Zephyr - SDK yet. You can find more information about its usage here: :ref:`here `. -* **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its - usage here: :ref:`here `. - -.. note:: - Note that even if both GNU and MWDT toolchain support is declared for the target some tests or - samples can be only built with either GNU or MWDT toolchain due to some features limited to a - particular toolchain. - -Use this configuration to run basic Zephyr applications and kernel tests in -nSIM, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nsim_em - :goals: flash - -This will build an image with the synchronization sample app, boot it using -nSIM, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 *** - thread_a: Hello World from cpu 0 on nsim! - thread_b: Hello World from cpu 0 on nsim! - thread_a: Hello World from cpu 0 on nsim! - thread_b: Hello World from cpu 0 on nsim! - thread_a: Hello World from cpu 0 on nsim! - - -.. note:: - To exit the simulator, use :kbd:`Ctrl+]`, then :kbd:`Ctrl+c` - -.. _board_arc_nsim_verbose_build: - -.. tip:: - You can get more details about the building process by running build in verbose mode. It can be - done by passing ``-v`` flag to the west: ``west -v build -b nsim_hs samples/synchronization`` - -You can run applications built for ``nsim`` board not only on nSIM simulation itself, but also on -FPGA based HW platform `HAPS`_. To run previously built application on HAPS do: - -.. code-block:: console - - west flash --runner mdb-hw - -.. note:: - To run on HAPS, in addition to proper build and flash Zephyr image, you need setup HAPS itself - as well as flash proper built FPGA image (aka .bit-file). This instruction doesn't cover those - steps, so you need to follow HAPS manual. - -Debugging -========= - -.. _board_arc_nsim_debugging_mwdt: - -Debugging with MDB ------------------- - -.. note:: - We strongly recommend to debug with MetaWare debugger (MDB) because it: - - * Supports wider range of ARC hardware features - * Allows to debug both single-core and multi-core ``nsim`` targets. - * Allows to debug on `HAPS`_ platform. - -You can use the following command to start GUI debugging when running application on nSIM simulator -(regardless if single- or multi-core configuration is used): - -.. code-block:: console - - west debug --runner mdb-nsim - -You can use the following command to start GUI debugging when running application on `HAPS`_ -platform: - -.. code-block:: console - - west debug --runner mdb-hw - -.. tip:: - The ``west debug`` (as well as ``west flash``) is just a wrapper script and so it's possible to - extract the exact commands which are called in it by running it in verbose mode. For that you - need to pass ``-v`` flag to the wrapper. For example, if you run the following command: - - .. code-block:: console - - west -v debug --runner mdb-nsim - - it will produce the following output (the ``nsim_hs5x_smp`` configuration was used for that - example): - - .. code-block:: console - - < *snip* > - -- west debug: using runner mdb-nsim - runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - runners.mdb-nsim: mdb -multifiles=core1,core0 -OKN - - From that output it's possible to extract MDB commands used for setting-up the GUI debugging - session: - - .. code-block:: console - - mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/arc/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf - mdb -multifiles=core1,core0 -OKN - - Then it's possible to use them directly or in some machinery if required. - - .. warning:: - It is strongly recommended to not rely on the mdb command line options listed above but - extract it yourself for your configuration. - - .. note:: - In case of execution or debugging with MDB on multi-core configuration on nSIM - simulator without ``west flash`` and ``west debug`` wrappers it's necessary to - set :envvar:`NSIM_MULTICORE` environment variable to ``1``. If you are using ``west flash`` or - ``west debug`` it's done automatically by wrappers. - - Without :envvar:`NSIM_MULTICORE` environment variable set to 1, MDB will simulate 2 separate - ARC cores which don't share any memory regions with each other and so SMP-enabled code won't - work as expected. - -Debugging with GDB ------------------- - -.. note:: - Debugging on nSIM via GDB is only supported on single-core configurations (which use standalone - nSIM). However if it's possible to launch application on multi-core nsim target that means you - can simply :ref:`debug with MDB debugger `. - It's the nSIM with ARC GDB restriction, real HW multi-core ARC targets can be debugged with ARC - GDB. - -.. note:: - Currently debugging with GDB is not supported on `HAPS`_ platform. - -.. note:: - The normal ``west debug`` command won't work for debugging applications using nsim boards - because both the nSIM simulator and the debugger (either GDB or MDB) use the same console for - input / output. - In case of GDB debugger it's possible to use a separate terminal windows for GDB and nSIM to - avoid intermixing their output. For the MDB debugger simply use GUI mode. - -After building your application, open two terminal windows. In terminal one, use nSIM to start a GDB -server and wait for a remote connection with following command: - -.. code-block:: console - - west debugserver --runner arc-nsim - -In terminal two, connect to the GDB server using ARC GDB. You can find it in Zephyr SDK: - -* for the ARCv2 targets you should use :file:`arc-zephyr-elf-gdb` -* for the ARCv3 targets you should use :file:`arc64-zephyr-elf-gdb` - -This command loads the symbol table from the elf binary file, for example the -:file:`build/zephyr/zephyr.elf` file: - -.. code-block:: console - - arc-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf - -Now the debug environment has been set up, and it's possible to debug the application with gdb -commands. - -Modifying the configuration -*************************** - -If modification of existing nsim configuration is required or even there's a need in creation of a -new one it's required to maintain alignment between - -* Zephyr OS configuration -* nSIM & MDB configuration -* GNU & MWDT toolchain compiler options - -.. note:: - The ``.tcf`` configuration files are not supported by Zephyr directly. There are multiple - reasons for that. ``.tcf`` perfectly suits building of bare-metal single-thread application - - in that case all the compiler options from ``.tcf`` are passed to the compiler, so all the HW - features are used by the application and optimal code is being generated. - The situation is completely different when multi-thread feature-rich operation system is - considered. Of course it is still possible to build all the code with all the - options from ``.tcf`` - but that may be far from optimal solution. For example, such approach - require so save & restore full register context for all tasks (and sometimes even for - interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra - registers save and restore even if the most of the user and kernel tasks don't actually use - DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros) - require us to maintain them separately from ``.tcf`` configuration. - - -Zephyr OS configuration -======================= - -Zephyr OS configuration is defined via Kconfig and Device tree. These are non ARC-specific -mechanisms which are described in :ref:`board porting guide `. - -It is advised to look for ``_defconfig``, ``.dts`` and -``.yaml`` as an entry point for board configuration. - -nSIM configuration -================== - -nSIM configuration is defined in :ref:`props and args files `. -Generally they are identical to the values from corresponding ``.tcf`` configuration with few -exceptions: - -* The UART model is added (to both ``.props`` and ``.args`` files). -* Options to fine-tuned MDB behavior are added (to ``.args`` files only) to disable MDB profiling - and fine-tune MDB behavior on multi-core systems. - -GNU & MWDT toolchain compiler options -===================================== - -The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim`` board -it is :zephyr_file:`soc/arc/snps_nsim/CMakeLists.txt`. - -For the GNU toolchain the basic configuration is set via ``-mcpu`` which is defined in generic code -and based on the selected CPU model via Kconfig. It still can be forcefully set to required value -on SoC level. - -For the MWDT toolchain all hardware-specific compiler options are set directly in SoC -``CMakeLists.txt``. - -.. note:: - The non hardware-specific compiler options like optimizations, library selections, C / C++ - language options are still set in Zephyr generic code. It could be observed by - :ref:`running build in verbose mode `. - -References -********** - -.. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim -.. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi -.. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html -.. _ARC MWDT: https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware diff --git a/boards/arc/nsim/nsim_em.yaml b/boards/arc/nsim/nsim_em.yaml deleted file mode 100644 index 9eb0c88ad50f14..00000000000000 --- a/boards/arc/nsim/nsim_em.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_em -name: EM Nsim simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_em11d.yaml b/boards/arc/nsim/nsim_em11d.yaml deleted file mode 100644 index a37c9c3888d8cc..00000000000000 --- a/boards/arc/nsim/nsim_em11d.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_em11d -name: EM11D Nsim simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_em11d_defconfig b/boards/arc/nsim/nsim_em11d_defconfig deleted file mode 100644 index 494ff760838e63..00000000000000 --- a/boards/arc/nsim/nsim_em11d_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_EM11D=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_em7d_v22.yaml b/boards/arc/nsim/nsim_em7d_v22.yaml deleted file mode 100644 index bd2069c8359019..00000000000000 --- a/boards/arc/nsim/nsim_em7d_v22.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nsim_em7d_v22 -name: EM nSIM simulator (EM7D_v22) -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_em7d_v22_defconfig b/boards/arc/nsim/nsim_em7d_v22_defconfig deleted file mode 100644 index 0a6d7ad5e4cca3..00000000000000 --- a/boards/arc/nsim/nsim_em7d_v22_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_EM7D_V22=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_em_defconfig b/boards/arc/nsim/nsim_em_defconfig deleted file mode 100644 index 263c5b27af5356..00000000000000 --- a/boards/arc/nsim/nsim_em_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_EM=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_hs.yaml b/boards/arc/nsim/nsim_hs.yaml deleted file mode 100644 index 18f2a71039ae9b..00000000000000 --- a/boards/arc/nsim/nsim_hs.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs -name: HS nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs3x_hostlink.yaml b/boards/arc/nsim/nsim_hs3x_hostlink.yaml deleted file mode 100644 index f23cdc18501a31..00000000000000 --- a/boards/arc/nsim/nsim_hs3x_hostlink.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs3x_hostlink -name: HS3x nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs3x_hostlink_defconfig b/boards/arc/nsim/nsim_hs3x_hostlink_defconfig deleted file mode 100644 index eddd5076c65d23..00000000000000 --- a/boards/arc/nsim/nsim_hs3x_hostlink_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs5x.yaml b/boards/arc/nsim/nsim_hs5x.yaml deleted file mode 100644 index 14d6cf03f8ebb2..00000000000000 --- a/boards/arc/nsim/nsim_hs5x.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs5x -name: HS5x nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - arcmwdt - - cross-compile -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x_defconfig b/boards/arc/nsim/nsim_hs5x_defconfig deleted file mode 100644 index 03c5f678869097..00000000000000 --- a/boards/arc/nsim/nsim_hs5x_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS5X=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs5x_smp.yaml b/boards/arc/nsim/nsim_hs5x_smp.yaml deleted file mode 100644 index 21015ecee69895..00000000000000 --- a/boards/arc/nsim/nsim_hs5x_smp.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: nsim_hs5x_smp -name: Multi-core HS5x nSIM simulator -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - zephyr - - arcmwdt - - cross-compile -supported: - - smp -testing: - timeout_multiplier: 1.5 - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x_smp_12cores.yaml b/boards/arc/nsim/nsim_hs5x_smp_12cores.yaml deleted file mode 100644 index f7f9fa1ec7201e..00000000000000 --- a/boards/arc/nsim/nsim_hs5x_smp_12cores.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: nsim_hs5x_smp_12cores -name: Multi-core HS5x nSIM simulator (12 cores) -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - zephyr - - arcmwdt - - cross-compile -supported: - - smp -testing: - timeout_multiplier: 4 - ignore_tags: - - net - - bluetooth diff --git a/boards/arc/nsim/nsim_hs5x_smp_12cores_defconfig b/boards/arc/nsim/nsim_hs5x_smp_12cores_defconfig deleted file mode 100644 index c27e5d81edeac7..00000000000000 --- a/boards/arc/nsim/nsim_hs5x_smp_12cores_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS5X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=12 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs5x_smp_defconfig b/boards/arc/nsim/nsim_hs5x_smp_defconfig deleted file mode 100644 index ac6baba1858c70..00000000000000 --- a/boards/arc/nsim/nsim_hs5x_smp_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS5X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs6x.yaml b/boards/arc/nsim/nsim_hs6x.yaml deleted file mode 100644 index 08b881eb743e0d..00000000000000 --- a/boards/arc/nsim/nsim_hs6x.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs6x -name: HS6x nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - arcmwdt - - cross-compile - - zephyr -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs6x_defconfig b/boards/arc/nsim/nsim_hs6x_defconfig deleted file mode 100644 index dfb41bf2215625..00000000000000 --- a/boards/arc/nsim/nsim_hs6x_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS6X=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs6x_smp.yaml b/boards/arc/nsim/nsim_hs6x_smp.yaml deleted file mode 100644 index d05faa51b29383..00000000000000 --- a/boards/arc/nsim/nsim_hs6x_smp.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: nsim_hs6x_smp -name: Multi-core HS6x nSIM simulator -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - cross-compile - - zephyr - - arcmwdt -supported: - - smp -testing: - timeout_multiplier: 1.5 - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs6x_smp_12cores.yaml b/boards/arc/nsim/nsim_hs6x_smp_12cores.yaml deleted file mode 100644 index 9abea29aabc83e..00000000000000 --- a/boards/arc/nsim/nsim_hs6x_smp_12cores.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: nsim_hs6x_smp_12cores -name: Multi-core HS6x nSIM simulator (12 cores) -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - cross-compile - - zephyr - - arcmwdt -supported: - - smp -testing: - timeout_multiplier: 4 - ignore_tags: - - net - - bluetooth diff --git a/boards/arc/nsim/nsim_hs6x_smp_12cores_defconfig b/boards/arc/nsim/nsim_hs6x_smp_12cores_defconfig deleted file mode 100644 index 2e14a87ed40d0f..00000000000000 --- a/boards/arc/nsim/nsim_hs6x_smp_12cores_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS6X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=12 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs6x_smp_defconfig b/boards/arc/nsim/nsim_hs6x_smp_defconfig deleted file mode 100644 index c34a380d1d0345..00000000000000 --- a/boards/arc/nsim/nsim_hs6x_smp_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ISA_ARCV3=y -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS6X_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs_defconfig b/boards/arc/nsim/nsim_hs_defconfig deleted file mode 100644 index eddd5076c65d23..00000000000000 --- a/boards/arc/nsim/nsim_hs_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs_flash_xip.yaml b/boards/arc/nsim/nsim_hs_flash_xip.yaml deleted file mode 100644 index eabe0c9cd846aa..00000000000000 --- a/boards/arc/nsim/nsim_hs_flash_xip.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs_flash_xip -name: HS nSIM simulator (FLASH XIP) -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_flash_xip_defconfig b/boards/arc/nsim/nsim_hs_flash_xip_defconfig deleted file mode 100644 index e4124a3ed69e22..00000000000000 --- a/boards/arc/nsim/nsim_hs_flash_xip_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_HARVARD=n -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs_mpuv6.yaml b/boards/arc/nsim/nsim_hs_mpuv6.yaml deleted file mode 100644 index cf1fdba06a7463..00000000000000 --- a/boards/arc/nsim/nsim_hs_mpuv6.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: nsim_hs_mpuv6 -name: HS (with MPU v6) nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_mpuv6_defconfig b/boards/arc/nsim/nsim_hs_mpuv6_defconfig deleted file mode 100644 index 4f57122f208a1a..00000000000000 --- a/boards/arc/nsim/nsim_hs_mpuv6_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS_MPUV6=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs_smp.yaml b/boards/arc/nsim/nsim_hs_smp.yaml deleted file mode 100644 index ccc1fab694dac0..00000000000000 --- a/boards/arc/nsim/nsim_hs_smp.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: nsim_hs_smp -name: Multi-core HS nSIM simulator -type: sim -simulation: mdb-nsim -simulation_exec: mdb -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -supported: - - smp -testing: - timeout_multiplier: 1.5 - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_smp_defconfig b/boards/arc/nsim/nsim_hs_smp_defconfig deleted file mode 100644 index 1b0d663da8db0b..00000000000000 --- a/boards/arc/nsim/nsim_hs_smp_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS_SMP=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs_sram.yaml b/boards/arc/nsim/nsim_hs_sram.yaml deleted file mode 100644 index cfbf02d6023884..00000000000000 --- a/boards/arc/nsim/nsim_hs_sram.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_hs_sram -name: HS nSIM simulator (SRAM) -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_hs_sram_defconfig b/boards/arc/nsim/nsim_hs_sram_defconfig deleted file mode 100644 index 8c4032b2054739..00000000000000 --- a/boards/arc/nsim/nsim_hs_sram_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_HS=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_HARVARD=n -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_sem.yaml b/boards/arc/nsim/nsim_sem.yaml deleted file mode 100644 index 13afb56ca698e7..00000000000000 --- a/boards/arc/nsim/nsim_sem.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: nsim_sem -name: SEM Nsim simulator -type: sim -arch: arc -simulation: nsim -simulation_exec: nsimdrv -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_sem_defconfig b/boards/arc/nsim/nsim_sem_defconfig deleted file mode 100644 index c6be9e45d58dc8..00000000000000 --- a/boards/arc/nsim/nsim_sem_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_SEM=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arc/nsim/nsim_sem_mpu_stack_guard.yaml b/boards/arc/nsim/nsim_sem_mpu_stack_guard.yaml deleted file mode 100644 index 13a48179fd5efb..00000000000000 --- a/boards/arc/nsim/nsim_sem_mpu_stack_guard.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: nsim_sem_mpu_stack_guard -name: SEM nSIM simulator (stack guard) -type: sim -arch: arc -simulation: nsim -simulation_exec: nsimdrv -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_sem_mpu_stack_guard_defconfig b/boards/arc/nsim/nsim_sem_mpu_stack_guard_defconfig deleted file mode 100644 index 4f846b18d61a7a..00000000000000 --- a/boards/arc/nsim/nsim_sem_mpu_stack_guard_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_SEM=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_ARC_MPU_ENABLE=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arc/nsim/nsim_vpx5.yaml b/boards/arc/nsim/nsim_vpx5.yaml deleted file mode 100644 index 4d5a3c8e96e48c..00000000000000 --- a/boards/arc/nsim/nsim_vpx5.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: nsim_vpx5 -name: VPX5 nSIM simulator -type: sim -simulation: nsim -simulation_exec: nsimdrv -arch: arc -toolchain: - - arcmwdt -testing: - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/nsim/nsim_vpx5_defconfig b/boards/arc/nsim/nsim_vpx5_defconfig deleted file mode 100644 index 83fdaa12a7df72..00000000000000 --- a/boards/arc/nsim/nsim_vpx5_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NSIM=y -CONFIG_SOC_NSIM_VPX5=y -CONFIG_BOARD_NSIM=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arc/qemu_arc/Kconfig.board b/boards/arc/qemu_arc/Kconfig.board deleted file mode 100644 index 1ea1a6bd77efd6..00000000000000 --- a/boards/arc/qemu_arc/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_ARC - bool "ARC QEMU for EM & HS cores" - depends on SOC_QEMU_ARC - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT diff --git a/boards/arc/qemu_arc/Kconfig.defconfig b/boards/arc/qemu_arc/Kconfig.defconfig deleted file mode 100644 index 54319f18bf377d..00000000000000 --- a/boards/arc/qemu_arc/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2020,2021 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_ARC - -config BOARD - default "qemu_arc" - -if NETWORKING - - config NET_L2_ETHERNET - default y - - # Required to satisfy dependency of networking stack on RNG - config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif diff --git a/boards/arc/qemu_arc/board.cmake b/boards/arc/qemu_arc/board.cmake deleted file mode 100644 index be83feb16371f0..00000000000000 --- a/boards/arc/qemu_arc/board.cmake +++ /dev/null @@ -1,44 +0,0 @@ -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} arc) - -if(${CONFIG_SOC_QEMU_ARC_EM}) -set(QEMU_CPU_TYPE_${ARCH} arcem) -set(QEMU_FLAGS_${ARCH} -cpu arcem) -elseif(${CONFIG_SOC_QEMU_ARC_HS}) -set(QEMU_CPU_TYPE_${ARCH} archs) -set(QEMU_FLAGS_${ARCH} -cpu archs) -elseif(${CONFIG_SOC_QEMU_ARC_HS5X}) -set(QEMU_ARCH arc) -set(QEMU_CPU_TYPE_${ARCH} hs5x) -set(QEMU_FLAGS_${ARCH} -cpu hs5x) -elseif(${CONFIG_SOC_QEMU_ARC_HS6X}) -set(QEMU_ARCH arc64) -set(QEMU_CPU_TYPE_${ARCH} hs6x) -set(QEMU_FLAGS_${ARCH} -cpu hs6x) -endif() - -# For old QEMU we had 'simhs' qemu board, however we are going to rename it -# to 'virt' board. It will be renamed in ARC QEMU in the nearest Zephyr SDK -# (where ARCv3 HS6x support will be added to QEMU) -# Let's rely on the QEMU defaults instead of specifying exact board name, -# until the updated Zephyr SDK will be set as default. By that we keep both SDKs -# (old and new) working for ARCv2. -# After that we can specify board explicitly with '-M virt' option. -list(APPEND QEMU_FLAGS_${ARCH} - -m 8M - -nographic - -no-reboot - -monitor none - -global cpu.firq=false - -global cpu.num-irqlevels=15 - -global cpu.num-irq=25 - -global cpu.ext-irq=20 - -global cpu.freq_hz=10000000 - -global cpu.timer0=true - -global cpu.timer1=true - -global cpu.has-mpu=true - -global cpu.mpu-numreg=16 - ) - -set(BOARD_DEBUG_RUNNER qemu) diff --git a/boards/arc/qemu_arc/doc/index.rst b/boards/arc/qemu_arc/doc/index.rst deleted file mode 100644 index 5a0857edc41b7e..00000000000000 --- a/boards/arc/qemu_arc/doc/index.rst +++ /dev/null @@ -1,102 +0,0 @@ -.. _qemu_arc: - -ARCv2 & ARCv3 Emulation (QEMU) -############################### - -Overview -******** - -This board configuration will use QEMU to emulate set of generic -ARCv2 and ARCv3 hardware platforms. - -The following features of ARC ISA cores are currently supported: - -* CPU: - * ARCv2 EM - * ARCv2 HS3x - * ARCv3 HS5x - * ARCv3 HS6x -* Only little-endian configurations -* Full 32 register set -* ARC core free-running timers/counters Timer0 & Timer1 -* ARC core interrupt controller with multiple priority levels -* DW UART -* 5 slots for MMIO Virtio devices - -Hardware -******** -Supported Features -================== - -The following hardware features are supported: - -+--------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+==============+============+======================+ -| ARCv2 INTC | on-chip | interrupt controller | -+--------------+------------+----------------------+ -| DW UART | on-chip | serial port | -+--------------+------------+----------------------+ -| ARC TIMER0 | on-chip | system clock | -+--------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 1 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -DesignWare UART. - -Known Problems or Limitations -============================== - -The following platform features are unsupported: - -* Memory-protection unit (MPU) -* MMIO Virtio Ethernet - -Programming and Debugging -************************* - -Use this configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample -(note you may use ``qemu_arc_em``, ``qemu_arc_hs``, ``qemu_arc_hs5x`` or -``qemu_arc_hs6x`` depending on target CPU): - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_arc_em - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57 *** - threadA: Hello World from qemu_arc! - threadB: Hello World from qemu_arc! - threadA: Hello World from qemu_arc! - threadB: Hello World from qemu_arc! - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. - -References -********** - -1.`Programmer’s Reference Manual for ARC HS - `_ diff --git a/boards/arc/qemu_arc/qemu_arc_em.yaml b/boards/arc/qemu_arc/qemu_arc_em.yaml deleted file mode 100644 index 2c1db9ed3746b0..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_em.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_em -name: QEMU Emulation for ARC EM -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_em_defconfig b/boards/arc/qemu_arc/qemu_arc_em_defconfig deleted file mode 100644 index 0d6f4052e64c34..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_em_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_EM=y -CONFIG_XIP=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs.yaml b/boards/arc/qemu_arc/qemu_arc_hs.yaml deleted file mode 100644 index 468b3a05215ccc..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: qemu_arc_hs -name: QEMU Emulation for ARC HS -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile - - arcmwdt -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs5x.yaml b/boards/arc/qemu_arc/qemu_arc_hs5x.yaml deleted file mode 100644 index 0abe51e04727f9..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs5x.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_hs5x -name: QEMU Emulation for ARC HS5x -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs5x_defconfig b/boards/arc/qemu_arc/qemu_arc_hs5x_defconfig deleted file mode 100644 index f8e50bcf3f8a53..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs5x_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_ISA_ARCV3=y -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS5X=y -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x.yaml b/boards/arc/qemu_arc/qemu_arc_hs6x.yaml deleted file mode 100644 index ed5425cc5654f9..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs6x.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_hs6x -name: QEMU Emulation for ARC HS6x -type: qemu -simulation: qemu -arch: arc -toolchain: - - cross-compile - - zephyr -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig b/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig deleted file mode 100644 index 8ab0d4ae0f0a6b..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs6x_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_ISA_ARCV3=y -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS6X=y -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/arc/qemu_arc/qemu_arc_hs_defconfig b/boards/arc/qemu_arc/qemu_arc_hs_defconfig deleted file mode 100644 index 911702aab21c1c..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS=y -CONFIG_XIP=n -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs_xip.yaml b/boards/arc/qemu_arc/qemu_arc_hs_xip.yaml deleted file mode 100644 index 4f7b9cee45d3c7..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs_xip.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_arc_hs_xip -name: QEMU Emulation for ARC HS (XIP) -type: qemu -simulation: qemu -arch: arc -toolchain: - - zephyr - - cross-compile -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs_xip_defconfig b/boards/arc/qemu_arc/qemu_arc_hs_xip_defconfig deleted file mode 100644 index bec83e7c5ae56a..00000000000000 --- a/boards/arc/qemu_arc/qemu_arc_hs_xip_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -CONFIG_SOC_QEMU_ARC=y -CONFIG_SOC_QEMU_ARC_HS=y -CONFIG_XIP=y -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_ARCV2_INTERRUPT_UNIT=y -CONFIG_ARCV2_TIMER=y -CONFIG_ARC_HAS_STACK_CHECKING=n -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arduino/due/Kconfig.arduino_due b/boards/arduino/due/Kconfig.arduino_due new file mode 100644 index 00000000000000..0e9cc38393cf96 --- /dev/null +++ b/boards/arduino/due/Kconfig.arduino_due @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Justin Watson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_DUE + select SOC_SAM3X8E diff --git a/boards/arm/arduino_due/arduino_due-pinctrl.dtsi b/boards/arduino/due/arduino_due-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_due/arduino_due-pinctrl.dtsi rename to boards/arduino/due/arduino_due-pinctrl.dtsi diff --git a/boards/arm/arduino_due/arduino_due.dts b/boards/arduino/due/arduino_due.dts similarity index 100% rename from boards/arm/arduino_due/arduino_due.dts rename to boards/arduino/due/arduino_due.dts diff --git a/boards/arm/arduino_due/arduino_due.yaml b/boards/arduino/due/arduino_due.yaml similarity index 100% rename from boards/arm/arduino_due/arduino_due.yaml rename to boards/arduino/due/arduino_due.yaml index 779271c0e12af1..21a71527ffea08 100644 --- a/boards/arm/arduino_due/arduino_due.yaml +++ b/boards/arduino/due/arduino_due.yaml @@ -2,14 +2,14 @@ identifier: arduino_due name: Arduino Due type: mcu arch: arm -ram: 96 -flash: 512 toolchain: - zephyr - gnuarmemb - xtools +flash: 512 +ram: 96 supported: - - watchdog - - gpio - arduino_i2c + - gpio + - watchdog vendor: arduino diff --git a/boards/arduino/due/arduino_due_defconfig b/boards/arduino/due/arduino_due_defconfig new file mode 100644 index 00000000000000..fb11f348f48d93 --- /dev/null +++ b/boards/arduino/due/arduino_due_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/arduino_due/board.cmake b/boards/arduino/due/board.cmake similarity index 100% rename from boards/arm/arduino_due/board.cmake rename to boards/arduino/due/board.cmake diff --git a/boards/arduino/due/board.yml b/boards/arduino/due/board.yml new file mode 100644 index 00000000000000..351bc719a15374 --- /dev/null +++ b/boards/arduino/due/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_due + vendor: arduino + socs: + - name: sam3x8e diff --git a/boards/arm/arduino_due/doc/img/arduino_due.jpg b/boards/arduino/due/doc/img/arduino_due.jpg similarity index 100% rename from boards/arm/arduino_due/doc/img/arduino_due.jpg rename to boards/arduino/due/doc/img/arduino_due.jpg diff --git a/boards/arduino/due/doc/index.rst b/boards/arduino/due/doc/index.rst new file mode 100644 index 00000000000000..5d984027534575 --- /dev/null +++ b/boards/arduino/due/doc/index.rst @@ -0,0 +1,214 @@ +.. _arduino_due: + +Arduino Due +########### + +Overview +******** + +The arduino_due board configuration is used by Zephyr applications +that run on the Arduino Due board. It provides support for the Atmel +SAM3X8E ARM Cortex-M3 CPU and the following devices: + +* Nested Vectored Interrupt Controller (NVIC) + +* System Tick System Clock (SYSTICK) + +* Serial Port over USB (ATMEL_SAM3) + +More information about the board can be found at the `Arduino Due website`_. +The `Atmel SAM3X8E Datasheet`_ has the information and the datasheet about +the processor. + +.. note:: + This configuration is not supported by Arduino. + +.. image:: img/arduino_due.jpg + :align: center + :alt: Arduino Due + +Hardware +******** +Supported Features +================== + +The arduino_due board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| Watchdog | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not currently supported by the Zephyr kernel. +See `Arduino Due website`_ and `Atmel SAM3X8E Datasheet`_ for a complete +list of Arduino Due board hardware features. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/due/arduino_due_defconfig`. + +.. note:: + For I2C, pull-up resistors are required for using SCL1 and SDA1 (near IO13). + +Interrupt Controller +==================== + +There are 15 fixed exceptions including exceptions 12 (debug monitor) and 15 +(SYSTICK) that behave more as interrupts than exceptions. In addition, there can +be a variable number of IRQs. Exceptions 7-10 and 13 are reserved. They don't +need handlers. + +A Cortex-M3/4-based board uses vectored exceptions. This means each exception +calls a handler directly from the vector table. + +Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here +identifies the handlers used for each exception. + ++------+------------+----------------+-----------------------+ +| Exc# | Name | Remarks | Used by Zephyr Kernel | ++======+============+================+=======================+ +| 1 | Reset | | system initialization | ++------+------------+----------------+-----------------------+ +| 2 | NMI | | system fatal error | ++------+------------+----------------+-----------------------+ +| 3 | Hard fault | | system fatal error | ++------+------------+----------------+-----------------------+ +| 4 | MemManage | MPU fault | system fatal error | ++------+------------+----------------+-----------------------+ +| 5 | Bus | | system fatal error | ++------+------------+----------------+-----------------------+ +| 6 | Usage | undefined | system fatal error | +| | fault | instruction, | | +| | | or switch | | +| | | attempt to ARM | | +| | | mode | | ++------+------------+----------------+-----------------------+ +| 11 | SVC | | system calls, kernel | +| | | | run-time exceptions, | +| | | | and IRQ offloading | ++------+------------+----------------+-----------------------+ +| 12 | Debug | | system fatal error | +| | monitor | | | ++------+------------+----------------+-----------------------+ +| 14 | PendSV | | context switch | ++------+------------+----------------+-----------------------+ +| 15 | SYSTICK | | system clock | ++------+------------+----------------+-----------------------+ + +.. note:: + After a reset, all exceptions have a priority of 0. Interrupts cannot run + at priority 0 for the interrupt locking mechanism and exception handling + to function properly. + +System Clock +============ + +Arduino Due has two external oscillators/resonators. The slow clock is +32.768 kHz, and the main clock is 12 MHz. The processor can set up PLL to drive +the master clock, which can be set as high as 84 MHz. + +Serial Port +=========== + +The Atmel SAM3X8E processor has a single UART that is used by the SAM-BA +bootloader. This UART has only two wires for RX/TX and does not have flow +control (CTS/RTS) or FIFO. The RX/TX pins are connected to the ATmega16U2, +which provides USB-to-TTL serial function. The Zephyr console output, by +default, is utilizing this controller. + + +Programming and Debugging +************************* + +Flashing +======== + +BOSSA Tool +---------- + +Flashing the Zephyr kernel onto Arduino Due requires the `bossa tool`_. + +There are GUI and command line versions of the bossa tool. The following +section provides the steps to build the command line version. Please +refer to the bossa tool's README file on how to build the GUI version. + +To build the bossa tool, follow these steps: + +#. Checkout the bossa tool's code from the repository. + + .. code-block:: console + + $ git clone https://github.com/shumatech/BOSSA.git + $ cd BOSSA + +#. Checkout the arduino branch. The code on the master branch does not + work with Arduino Due. + + .. code-block:: console + + $ git checkout arduino + +#. Build the command line version of the bossa tool. + + .. code-block:: console + + $ make bin/bossac + +#. The resulting binary is available at :file:`bin/bossac`. + + +Flashing an Application to Arduino Due +-------------------------------------- + +Applications for the ``arduino_due`` board configuration can be built +and flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. After +building the application, press the Reset button before running the +flash command, so the board will boot into the SAM-BA bootloader and +be prepared to receive the new program. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_due + :goals: build flash + +After flashing the application, run your favorite terminal program to +listen for output. For example, under Linux, the terminal should be +:code:`/dev/ttyACM0`. For example: + +.. code-block:: console + + $ sudo minicom -D /dev/ttyACM0 -o + +The -o option tells minicom not to send the modem initialization +string. + +Now press the Reset button and you should see "Hello World! arduino_due" in your terminal. + +.. note:: + Make sure your terminal program is closed before flashing the binary image, + or it will interfere with the flashing process. + +References +********** + +.. _Arduino Due website: https://www.arduino.cc/en/Main/ArduinoBoardDue + +.. _Atmel SAM3X8E Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf + +.. _bossa tool: https://github.com/shumatech/BOSSA + +.. _bossa arduino branch: https://github.com/shumatech/BOSSA/tree/arduino diff --git a/boards/arduino/giga_r1/Kconfig.arduino_giga_r1 b/boards/arduino/giga_r1/Kconfig.arduino_giga_r1 new file mode 100644 index 00000000000000..6eb5d937b84e39 --- /dev/null +++ b/boards/arduino/giga_r1/Kconfig.arduino_giga_r1 @@ -0,0 +1,6 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_GIGA_R1 + select SOC_STM32H747XX_M7 if BOARD_ARDUINO_GIGA_R1_STM32H747XX_M7 + select SOC_STM32H747XX_M4 if BOARD_ARDUINO_GIGA_R1_STM32H747XX_M4 diff --git a/boards/arduino/giga_r1/Kconfig.defconfig b/boards/arduino/giga_r1/Kconfig.defconfig new file mode 100644 index 00000000000000..0d20cf3c341d73 --- /dev/null +++ b/boards/arduino/giga_r1/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_GIGA_R1 + +if BT + +choice AIROC_PART + default CYW4343W +endchoice + +choice CYW4343W_MODULE + default CYW4343W_MURATA_1DX +endchoice + +endif # BT + +endif # BOARD_ARDUINO_GIGA_R1 diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1.dtsi b/boards/arduino/giga_r1/arduino_giga_r1.dtsi similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_giga_r1.dtsi rename to boards/arduino/giga_r1/arduino_giga_r1.dtsi diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_giga_r1_m4.dts rename to boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.dts diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml new file mode 100644 index 00000000000000..3917682bd21c07 --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml @@ -0,0 +1,19 @@ +identifier: arduino_giga_r1/stm32h747xx/m4 +name: Arduino GIGA R1 WiFi (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - arduino_gpio + - gpio +testing: + ignore_tags: + - mpu + - nfc + - net +vendor: arduino diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000000..c7a9e88969b6b9 --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4_defconfig @@ -0,0 +1,24 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_giga_r1_m7.dts rename to boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml new file mode 100644 index 00000000000000..cdcaeba7c77b2c --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml @@ -0,0 +1,19 @@ +identifier: arduino_giga_r1/stm32h747xx/m7 +name: Arduino GIGA R1 WiFi (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - arduino_gpio + - gpio + - arduino_spi + - spi + - memc + - usb_cdc + - usb_device +vendor: arduino diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000000..0bd7546e26a850 --- /dev/null +++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7_defconfig @@ -0,0 +1,30 @@ +# Copyright 2023 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +# Disable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=n + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_giga_r1/arduino_r3_connector.dtsi b/boards/arduino/giga_r1/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/arduino_giga_r1/arduino_r3_connector.dtsi rename to boards/arduino/giga_r1/arduino_r3_connector.dtsi diff --git a/boards/arduino/giga_r1/board.cmake b/boards/arduino/giga_r1/board.cmake new file mode 100644 index 00000000000000..f02ceaf2c3dbe3 --- /dev/null +++ b/boards/arduino/giga_r1/board.cmake @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_ARDUINO_GIGA_R1_STM32H747XX_M7) +board_runner_args(jlink "--device=STM32H747XI_M7" "--speed=4000") +board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m7.cfg") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_ARDUINO_GIGA_R1_STM32H747XX_M4) +board_runner_args(jlink "--device=STM32H747XI_M4" "--speed=4000") +board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m4.cfg") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() +board_runner_args(dfu-util "--pid=2341:0366" "--alt=0" "--dfuse") +board_runner_args(blackmagicprobe "--connect-rst") + +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arduino/giga_r1/board.yml b/boards/arduino/giga_r1/board.yml new file mode 100644 index 00000000000000..3079c2f0d5c85e --- /dev/null +++ b/boards/arduino/giga_r1/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_giga_r1 + vendor: arduino + socs: + - name: stm32h747xx diff --git a/boards/arm/arduino_giga_r1/doc/img/arduino_giga_r1.jpg b/boards/arduino/giga_r1/doc/img/arduino_giga_r1.jpg similarity index 100% rename from boards/arm/arduino_giga_r1/doc/img/arduino_giga_r1.jpg rename to boards/arduino/giga_r1/doc/img/arduino_giga_r1.jpg diff --git a/boards/arduino/giga_r1/doc/index.rst b/boards/arduino/giga_r1/doc/index.rst new file mode 100644 index 00000000000000..0e95653edfaee1 --- /dev/null +++ b/boards/arduino/giga_r1/doc/index.rst @@ -0,0 +1,186 @@ +.. _arduino_giga_r1_board: + +Arduino GIGA R1 WiFi +#################### + +Overview +******** + +Arduino GIGA R1 WiFi is a development board by Arduino based on the +STM32H747XI, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash +memory and 1MB SRAM. + +The board features: + +- RGB LED +- Reset and Boot buttons +- USB-C device +- USB Host +- 16MB external QSPI flash +- 8MB external SDRAM +- Murata Type 1DX Bluetooth + WiFi module (CYW4343W based) +- Audio jack +- ATECC608A secure element + +.. image:: img/arduino_giga_r1.jpg + :align: center + :alt: Arduino GIGA R1 WiFi + +More information about the board, including the datasheet, pinout and +schematics, can be found at the `Arduino GIGA website`_. + +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr ``arduino_giga_r1_m7`` board configuration supports the +following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| QSPI | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| RADIO | Murata 1DX | WiFi and Bluetooth module | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr port. + +Fetch Binary Blobs +****************** + +The board Bluetooth/WiFi module requires fetching some binary blob files, to do +that run the command: + +.. code-block:: console + + west blobs fetch hal_infineon + +.. note:: Only Bluetooth functionality is currently supported. + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``arduino_giga_r1`` board should be built per core target, +using either ``arduino_giga_r1/stm32h747xx/m7`` or ``arduino_giga_r1/stm32h747xx/m4`` as the target. + +See :ref:`build_an_application` for more information about application builds. + +Flashing +======== + +This board can be flashed either using dfu-util, or with an external debugging +probe, such as a J-Link or Black Magic Probe, connected to the on board MIPI-10 +SWD port marked as "JTAG". + +.. note:: + + The board ships with a custom Arduino bootloader programmed in the first + flash page that can be triggered by double clicking the ``RST`` button. This + bootloader is USB-DFU compatible and supports programming both the internal + and external flash and is the one used by ``west flash`` by default. The + internal STM32 ROM bootloader can also be used by pressing ``RST`` while + holding the ``BOOT0`` button, this also supports USB-DFU but can only + program the internal flash and can overwrite the Arduino bootloader. More + details can be found in the "Boot0" section of the `Arduino GIGA Cheat + Sheet`_. + +First, connect the Arduino GIGA R1 board to your host computer using the USB +port to prepare it for flashing. Double click the ``RST`` button to put the +board into the Arduino Bootloader mode. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_giga_r1/stm32h747xx/m7 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arduino_giga_r1 + +Similarly, you can build and flash samples on the M4 target. + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_giga_r1/stm32h747xx/m4 + :goals: build flash + +Debugging +========= + +Debugging is supported by using ``west debug`` with an external probe such as a +J-Link or Black Magic Probe, connected to the on board MIPI-10 SWD port marked +as "JTAG". For example:: + + west debug -r jlink + +.. _Arduino GIGA website: + https://docs.arduino.cc/hardware/giga-r1-wifi + +.. _Arduino GIGA Cheat Sheet: + https://docs.arduino.cc/tutorials/giga-r1-wifi/cheat-sheet + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html diff --git a/boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m4.cfg b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg similarity index 100% rename from boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m4.cfg rename to boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m4.cfg diff --git a/boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m7.cfg b/boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg similarity index 100% rename from boards/arm/arduino_giga_r1/support/openocd_arduino_giga_r1_m7.cfg rename to boards/arduino/giga_r1/support/openocd_arduino_giga_r1_m7.cfg diff --git a/boards/arduino/index.rst b/boards/arduino/index.rst new file mode 100644 index 00000000000000..a8877f1a3a2a1f --- /dev/null +++ b/boards/arduino/index.rst @@ -0,0 +1,10 @@ +.. _boards-arduino: + +Arduino +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arduino/mkrzero/Kconfig.arduino_mkrzero b/boards/arduino/mkrzero/Kconfig.arduino_mkrzero new file mode 100644 index 00000000000000..9958bc8555d5ea --- /dev/null +++ b/boards/arduino/mkrzero/Kconfig.arduino_mkrzero @@ -0,0 +1,6 @@ +# Copyright (c) 2022 TOKITA Hiroshi +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_MKRZERO + select SOC_SAMD21G18A diff --git a/boards/arduino/mkrzero/Kconfig.defconfig b/boards/arduino/mkrzero/Kconfig.defconfig new file mode 100644 index 00000000000000..6d5f9448b9e03f --- /dev/null +++ b/boards/arduino/mkrzero/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Arduino MKR Zero board configuration + +# Copyright (c) 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if DISK_DRIVERS + +config DISK_DRIVER_SDMMC + default y + +config SPI + default y + +config GPIO + default y + +endif # DISK_DRIVERS diff --git a/boards/arm/arduino_mkrzero/arduino_mkr_connector.dtsi b/boards/arduino/mkrzero/arduino_mkr_connector.dtsi similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkr_connector.dtsi rename to boards/arduino/mkrzero/arduino_mkr_connector.dtsi diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero-pinctrl.dtsi b/boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkrzero-pinctrl.dtsi rename to boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero.dts b/boards/arduino/mkrzero/arduino_mkrzero.dts similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkrzero.dts rename to boards/arduino/mkrzero/arduino_mkrzero.dts diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero.yaml b/boards/arduino/mkrzero/arduino_mkrzero.yaml similarity index 100% rename from boards/arm/arduino_mkrzero/arduino_mkrzero.yaml rename to boards/arduino/mkrzero/arduino_mkrzero.yaml diff --git a/boards/arduino/mkrzero/arduino_mkrzero_defconfig b/boards/arduino/mkrzero/arduino_mkrzero_defconfig new file mode 100644 index 00000000000000..ab658e1e5d698d --- /dev/null +++ b/boards/arduino/mkrzero/arduino_mkrzero_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ARDUINO=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/arduino_mkrzero/board.cmake b/boards/arduino/mkrzero/board.cmake similarity index 100% rename from boards/arm/arduino_mkrzero/board.cmake rename to boards/arduino/mkrzero/board.cmake diff --git a/boards/arduino/mkrzero/board.yml b/boards/arduino/mkrzero/board.yml new file mode 100644 index 00000000000000..a53c04cbd182db --- /dev/null +++ b/boards/arduino/mkrzero/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_mkrzero + vendor: arduino + socs: + - name: samd21g18a diff --git a/boards/arm/arduino_mkrzero/doc/img/arduino_mkrzero.jpg b/boards/arduino/mkrzero/doc/img/arduino_mkrzero.jpg similarity index 100% rename from boards/arm/arduino_mkrzero/doc/img/arduino_mkrzero.jpg rename to boards/arduino/mkrzero/doc/img/arduino_mkrzero.jpg diff --git a/boards/arduino/mkrzero/doc/index.rst b/boards/arduino/mkrzero/doc/index.rst new file mode 100644 index 00000000000000..b6fe37ddd16410 --- /dev/null +++ b/boards/arduino/mkrzero/doc/index.rst @@ -0,0 +1,183 @@ +.. _arduino_mkrzero: + +Arduino MKR Zero +#################### + +Overview +******** + +The Arduino MKR Zero built with smaller MKR form factor and powered by Atmel's SAMD21 MCU. +This board come with microSD card holder that allows you to play with music files with no extra hardware. + +.. image:: img/arduino_mkrzero.jpg + :align: center + :alt: Arduino MKR Zero + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One user LEDs +- One reset button +- microSD card slot +- ATECC508A secure element + +Supported Features +================== + +The arduino_mkrzero board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| ADC | on-chip | Analog to digital converter | ++-----------+------------+------------------------------------------+ +| COUNTER | on-chip | Pulse counter | ++-----------+------------+------------------------------------------+ +| DMA | on-chip | Direct memory access unit | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Hardware info and serial number | ++-----------+------------+------------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit ports | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ + + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/mkrzero/arduino_mkrzero_defconfig`. + +Connections and IOs +=================== + +The `Arduino store`_ has detailed information about board +connections. Download the `Arduino MKR Zero Schematic`_ for more detail. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 13(PA23) and 14(PA22). + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino MKR Zero, SERCOM1 +is available on pin 8, 9, and 10. +SERCOM2 connect to microSD card slot as SPI interface. + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based I2Cs. SERCOM0 is available on pin 11(PA08) and 12(PA09). +This I2C bus also available as ESLOV(JST SH 5pin) socket. +ATECC508A secure element is connect to this I2C bus. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +DAC +=== + +The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the +Arduino MKR Zero, the DAC is available on pin A0. + +Programming and Debugging +************************* + +The Arduino MKR Zero ships the BOSSA compatible bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_mkrzero + :goals: build + :compact: + +#. Connect the MKR Zero to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_mkrzero + :goals: flash + :compact: + + You should see "Hello World! arduino_mkrzero" in your terminal. + +References +********** + +.. target-notes:: + +.. _Arduino Store: + https://store.arduino.cc/collections/boards/products/arduino-mkr-zero-i2s-bus-sd-for-sound-music-digital-audio-data + +.. _Arduino MKR Zero Schematic: + https://www.arduino.cc/en/uploads/Main/ArduinoMKRZero-schematic.pdf diff --git a/boards/arm/arduino_mkrzero/pre_dt_board.cmake b/boards/arduino/mkrzero/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_mkrzero/pre_dt_board.cmake rename to boards/arduino/mkrzero/pre_dt_board.cmake diff --git a/boards/arm/arduino_nano_33_ble/CMakeLists.txt b/boards/arduino/nano_33_ble/CMakeLists.txt similarity index 100% rename from boards/arm/arduino_nano_33_ble/CMakeLists.txt rename to boards/arduino/nano_33_ble/CMakeLists.txt diff --git a/boards/arduino/nano_33_ble/Kconfig.arduino_nano_33_ble b/boards/arduino/nano_33_ble/Kconfig.arduino_nano_33_ble new file mode 100644 index 00000000000000..7fafc189aa4b8e --- /dev/null +++ b/boards/arduino/nano_33_ble/Kconfig.arduino_nano_33_ble @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Jefferson Lee. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NANO_33_BLE + select SOC_NRF52840_QIAA diff --git a/boards/arduino/nano_33_ble/Kconfig.defconfig b/boards/arduino/nano_33_ble/Kconfig.defconfig new file mode 100644 index 00000000000000..73bd7e9c32deb7 --- /dev/null +++ b/boards/arduino/nano_33_ble/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 Jefferson Lee. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_NANO_33_BLE + +config BT_CTLR + default BT + +config REGULATOR + default y if SENSOR + +endif # BOARD_ARDUINO_NANO_33_BLE diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-common.dtsi b/boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-common.dtsi rename to boards/arduino/nano_33_ble/arduino_nano_33_ble-common.dtsi diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi b/boards/arduino/nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi rename to boards/arduino/nano_33_ble/arduino_nano_33_ble-pinctrl.dtsi diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble.dts similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.dts rename to boards/arduino/nano_33_ble/arduino_nano_33_ble.dts diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble.yaml rename to boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig b/boards/arduino/nano_33_ble/arduino_nano_33_ble_defconfig similarity index 77% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig rename to boards/arduino/nano_33_ble/arduino_nano_33_ble_defconfig index 49b2009f744ab6..9e62deccc4d0b1 100644 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_defconfig +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ARDUINO_NANO_33_BLE=y - # Enable MPU CONFIG_ARM_MPU=y CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.dts b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.dts rename to boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.dts diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml new file mode 100644 index 00000000000000..b8741e66b3575d --- /dev/null +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml @@ -0,0 +1,20 @@ +identifier: arduino_nano_33_ble//sense +name: Arduino Nano 33 BLE Sense +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - ble + - i2c + - pwm + - serial + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: arduino diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense_defconfig b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense_defconfig new file mode 100644 index 00000000000000..9e62deccc4d0b1 --- /dev/null +++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# enable peripherals +CONFIG_GPIO=y +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable sam-ba bootloader on legacy mode +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_LEGACY=y diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_ble/arduino_nano_r3_connector.dtsi rename to boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/arduino_nano_33_ble/board.c b/boards/arduino/nano_33_ble/board.c similarity index 100% rename from boards/arm/arduino_nano_33_ble/board.c rename to boards/arduino/nano_33_ble/board.c diff --git a/boards/arm/arduino_nano_33_ble/board.cmake b/boards/arduino/nano_33_ble/board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_ble/board.cmake rename to boards/arduino/nano_33_ble/board.cmake diff --git a/boards/arduino/nano_33_ble/board.yml b/boards/arduino/nano_33_ble/board.yml new file mode 100644 index 00000000000000..919864839ed04f --- /dev/null +++ b/boards/arduino/nano_33_ble/board.yml @@ -0,0 +1,7 @@ +board: + name: arduino_nano_33_ble + vendor: arduino + socs: + - name: nrf52840 + variants: + - name: 'sense' diff --git a/boards/arm/arduino_nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg b/boards/arduino/nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg similarity index 100% rename from boards/arm/arduino_nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg rename to boards/arduino/nano_33_ble/doc/img/arduino_nano_33_ble_sense.jpg diff --git a/boards/arm/arduino_nano_33_ble/doc/img/nano_33_ble_swd.jpg b/boards/arduino/nano_33_ble/doc/img/nano_33_ble_swd.jpg similarity index 100% rename from boards/arm/arduino_nano_33_ble/doc/img/nano_33_ble_swd.jpg rename to boards/arduino/nano_33_ble/doc/img/nano_33_ble_swd.jpg diff --git a/boards/arm/arduino_nano_33_ble/doc/index.rst b/boards/arduino/nano_33_ble/doc/index.rst similarity index 100% rename from boards/arm/arduino_nano_33_ble/doc/index.rst rename to boards/arduino/nano_33_ble/doc/index.rst diff --git a/boards/arm/arduino_nicla_sense_me/pre_dt_board.cmake b/boards/arduino/nano_33_ble/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_nicla_sense_me/pre_dt_board.cmake rename to boards/arduino/nano_33_ble/pre_dt_board.cmake diff --git a/boards/arm/arduino_nano_33_ble/support/debug.cmm b/boards/arduino/nano_33_ble/support/debug.cmm similarity index 100% rename from boards/arm/arduino_nano_33_ble/support/debug.cmm rename to boards/arduino/nano_33_ble/support/debug.cmm diff --git a/boards/arm/arduino_nano_33_ble/support/startup.cmm b/boards/arduino/nano_33_ble/support/startup.cmm similarity index 100% rename from boards/arm/arduino_nano_33_ble/support/startup.cmm rename to boards/arduino/nano_33_ble/support/startup.cmm diff --git a/boards/arduino/nano_33_iot/Kconfig.arduino_nano_33_iot b/boards/arduino/nano_33_iot/Kconfig.arduino_nano_33_iot new file mode 100644 index 00000000000000..55021a63b2fcd9 --- /dev/null +++ b/boards/arduino/nano_33_iot/Kconfig.arduino_nano_33_iot @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NANO_33_IOT + select SOC_SAMD21G18A diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi b/boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi rename to boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.dts rename to boards/arduino/nano_33_iot/arduino_nano_33_iot.dts diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.yaml b/boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_33_iot.yaml rename to boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig b/boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig new file mode 100644 index 00000000000000..051825bb7510f7 --- /dev/null +++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ARDUINO=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/arduino_nano_33_iot/arduino_nano_r3_connector.dtsi rename to boards/arduino/nano_33_iot/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/arduino_nano_33_iot/board.cmake b/boards/arduino/nano_33_iot/board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_iot/board.cmake rename to boards/arduino/nano_33_iot/board.cmake diff --git a/boards/arduino/nano_33_iot/board.yml b/boards/arduino/nano_33_iot/board.yml new file mode 100644 index 00000000000000..63b7dab7992ec4 --- /dev/null +++ b/boards/arduino/nano_33_iot/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_nano_33_iot + vendor: arduino + socs: + - name: samd21g18a diff --git a/boards/arm/arduino_nano_33_iot/doc/img/nano_33_iot.jpg b/boards/arduino/nano_33_iot/doc/img/nano_33_iot.jpg similarity index 100% rename from boards/arm/arduino_nano_33_iot/doc/img/nano_33_iot.jpg rename to boards/arduino/nano_33_iot/doc/img/nano_33_iot.jpg diff --git a/boards/arduino/nano_33_iot/doc/index.rst b/boards/arduino/nano_33_iot/doc/index.rst new file mode 100644 index 00000000000000..5b87fb52c182ab --- /dev/null +++ b/boards/arduino/nano_33_iot/doc/index.rst @@ -0,0 +1,171 @@ +.. _arduino_nano_33_iot: + +Arduino Nano 33 IOT +################### + +Overview +******** + +The Arduino Nano 33 IOT is a small form factor development board with USB, +Wifi, Bluetooth, a 6 axis IMU, and secure element. + +.. image:: img/nano_33_iot.jpg + :align: center + :alt: Arduino Nano 33 IOT + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- One user LED +- One reset button +- Native USB port +- Wifi and Bluetooth via a u-blox NINA-W102 +- ATECC608A secure element +- LSM6DS3 six axis accelerometer and gyro + +Supported Features +================== + +The arduino_nano_33_iot board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| ADC | on-chip | Analog to digital converter | ++-----------+------------+------------------------------------------+ +| COUNTER | on-chip | Pulse counter | ++-----------+------------+------------------------------------------+ +| DMA | on-chip | Direct memory access unit | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Hardware info and serial number | ++-----------+------------+------------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig`. + +Connections and IOs +=================== + +The `Arduino store`_ has detailed information about board +connections. Download the `schematic`_ for more detail. + +System Clock +============ + +The SAMD21 MCU is configured to use the 8 MHz internal oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 1 and 2. + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC2 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. SERCOM1 is available on pins 1, 14, +and 15. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +Programming and Debugging +************************* + +The Nano 33 IOT ships the BOSSA compatible UF2 bootloader. The +bootloader can be entered by quickly tapping the reset button twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_nano_33_iot + :goals: build + :compact: + +#. Connect the Nano 33 IOT to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_nano_33_iot + :goals: flash + :compact: + + You should see "Hello World! arduino_nano_33_iot" in your terminal. + +References +********** + +.. target-notes:: + +.. _Arduino Store: + https://store.arduino.cc/arduino-nano-33-iot + +.. _schematic: + https://content.arduino.cc/assets/NANO33IoTV2.0_sch.pdf diff --git a/boards/arm/arduino_nano_33_iot/pre_dt_board.cmake b/boards/arduino/nano_33_iot/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_nano_33_iot/pre_dt_board.cmake rename to boards/arduino/nano_33_iot/pre_dt_board.cmake diff --git a/boards/arduino/nicla_sense_me/Kconfig.arduino_nicla_sense_me b/boards/arduino/nicla_sense_me/Kconfig.arduino_nicla_sense_me new file mode 100644 index 00000000000000..e79b67a84b304f --- /dev/null +++ b/boards/arduino/nicla_sense_me/Kconfig.arduino_nicla_sense_me @@ -0,0 +1,7 @@ +# Arduino Nicla Sense ME board configuration + +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_NICLA_SENSE_ME + select SOC_NRF52832_QFAA diff --git a/boards/arduino/nicla_sense_me/Kconfig.defconfig b/boards/arduino/nicla_sense_me/Kconfig.defconfig new file mode 100644 index 00000000000000..b1e6a59d7d3d5c --- /dev/null +++ b/boards/arduino/nicla_sense_me/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Arduino Nicla Sense ME board configuration + +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARDUINO_NICLA_SENSE_ME + +config BT_CTLR + default BT + +endif # BOARD_ARDUINO_NICLA_SENSE_ME diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi rename to boards/arduino/nicla_sense_me/arduino_nicla_sense_me-pinctrl.dtsi diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.dts b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts similarity index 100% rename from boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.dts rename to boards/arduino/nicla_sense_me/arduino_nicla_sense_me.dts diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.yaml b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml similarity index 100% rename from boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me.yaml rename to boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml diff --git a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig new file mode 100644 index 00000000000000..f8691d1c1cefe8 --- /dev/null +++ b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_nicla_sense_me/board.cmake b/boards/arduino/nicla_sense_me/board.cmake similarity index 100% rename from boards/arm/arduino_nicla_sense_me/board.cmake rename to boards/arduino/nicla_sense_me/board.cmake diff --git a/boards/arduino/nicla_sense_me/board.yml b/boards/arduino/nicla_sense_me/board.yml new file mode 100644 index 00000000000000..0a470e79ce578f --- /dev/null +++ b/boards/arduino/nicla_sense_me/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_nicla_sense_me + vendor: arduino + socs: + - name: nrf52832 diff --git a/boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me.jpg b/boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me.jpg similarity index 100% rename from boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me.jpg rename to boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me.jpg diff --git a/boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg b/boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg similarity index 100% rename from boards/arm/arduino_nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg rename to boards/arduino/nicla_sense_me/doc/arduino_nicla_sense_me_pinout.jpg diff --git a/boards/arm/arduino_nicla_sense_me/doc/index.rst b/boards/arduino/nicla_sense_me/doc/index.rst similarity index 100% rename from boards/arm/arduino_nicla_sense_me/doc/index.rst rename to boards/arduino/nicla_sense_me/doc/index.rst diff --git a/boards/arm/bbc_microbit_v2/pre_dt_board.cmake b/boards/arduino/nicla_sense_me/pre_dt_board.cmake similarity index 100% rename from boards/arm/bbc_microbit_v2/pre_dt_board.cmake rename to boards/arduino/nicla_sense_me/pre_dt_board.cmake diff --git a/boards/arduino/opta/Kconfig.arduino_opta b/boards/arduino/opta/Kconfig.arduino_opta new file mode 100644 index 00000000000000..d591283a6ff05d --- /dev/null +++ b/boards/arduino/opta/Kconfig.arduino_opta @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_OPTA + select SOC_STM32H747XX_M4 diff --git a/boards/arm/arduino_opta_m4/arduino_opta_m4.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/arduino_opta_m4/arduino_opta_m4.dts rename to boards/arduino/opta/arduino_opta_stm32h747xx_m4.dts diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml new file mode 100644 index 00000000000000..e7495a72ea1447 --- /dev/null +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml @@ -0,0 +1,21 @@ +identifier: arduino_opta/stm32h747xx/m4 +name: ARDUINO OPTA (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 512 +supported: + - gpio +testing: + ignore_tags: + - mpu + - nfc + - net + - flash + - input + - mcumgr +vendor: arduino diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig b/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000000..f9f3e39d9c7c62 --- /dev/null +++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2023 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable pin controller +CONFIG_PINCTRL=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_opta_m4/board.cmake b/boards/arduino/opta/board.cmake similarity index 100% rename from boards/arm/arduino_opta_m4/board.cmake rename to boards/arduino/opta/board.cmake diff --git a/boards/arduino/opta/board.yml b/boards/arduino/opta/board.yml new file mode 100644 index 00000000000000..c572627b3488ef --- /dev/null +++ b/boards/arduino/opta/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_opta + vendor: arduino + socs: + - name: stm32h747xx diff --git a/boards/arm/arduino_opta_m4/doc/img/arduino_opta.jpeg b/boards/arduino/opta/doc/img/arduino_opta.jpeg similarity index 100% rename from boards/arm/arduino_opta_m4/doc/img/arduino_opta.jpeg rename to boards/arduino/opta/doc/img/arduino_opta.jpeg diff --git a/boards/arduino/opta/doc/index.rst b/boards/arduino/opta/doc/index.rst new file mode 100644 index 00000000000000..c50c7e27ec90d3 --- /dev/null +++ b/boards/arduino/opta/doc/index.rst @@ -0,0 +1,177 @@ +.. _arduino_opta_m4_board: + +Arduino OPTA M4-Core +#################### + +Overview +******** + +The Arduino™ Opta® is a secure micro Programmable Logic Controller (PLC) +with Industrial Internet of Things (IoT) capabilities. + +Developed in partnership with Finder®, this device supports both the Arduino +programming language and standard IEC-61131-3 PLC programming languages, +such as Ladder Diagram (LD), Sequential Function Chart (SFC), +Function Block Diagram (FBD), Structured Text (ST), and Instruction List (IL), +making it an ideal device for automation engineers. + +For Zephyr RTOS, only the M4 is supported for now, making the M7 run the PLC +tasks while the M4 core under Zephyr acts as a coprocessor. + +Additionally, the device features: + +- Ethernet compliant with IEEE802.3-2002 +- 16MB QSPI Flash +- 4 x green color status LEDs +- 1 x user push-button +- 1 x reset push-button accessible via pinhole +- 8 x analog inputs +- 4 x isolated relay outputs + +.. image:: img/arduino_opta.jpeg + :align: center + :alt: ARDUINO-OPTA + +More information about the board can be found at the `ARDUINO-OPTA website`_. +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr arduino_opta_m4 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration per core can be found in the defconfig file: +:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig` + +Pin Mapping +=========== + +ARDUINO OPTA M4 has access to the 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `ARDUINO-OPTA website`_. + +Default Zephyr Peripheral Mapping +--------------------------------- + +- Status LED1 : PI0 +- Status LED2 : PI1 +- Status LED3 : PI3 +- Status LED4 : PH15 +- User button : PE4 + +System Clock +============ + +The STM32H747I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock +is driven at 240MHz. PLL clock is fed by a 25MHz high speed external clock. + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``arduino_opta`` use the regular Zephyr build commands. +See :ref:`build_an_application` for more information about application builds. + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. The OPTA has a DFU capable bootloader which +can be accessed by connecting the device to the USB, and then pressing +the RESET button shortly twice, the RESET-LED on the board will fade +indicating the board is in bootloader mode. + +By default: + + - CPU2 (Cortex-M4) boot address is set to 0x08180000 (OB: BOOT_CM4_ADD0) + +Zephyr flash configuration has been set to meet these default settings. + +Flashing an application to ARDUINO OPTA M4 +------------------------------------------ + +First, connect the device to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_opta/stm32h747xx/m4 + :goals: build flash + +Starting the application on the ARDUINO OPTA M4 +----------------------------------------------- + +Make sure the option bytes are set to prevent the M4 from auto-starting, and +that the M7 side starts the M4 at the correct Flash address. + +This can be done by selecting in the Arduino IDE's "Tools" / "Flash Split" +menu the "1.5MB M7 + 0.5MB M4" option, and loading a sketch that contains +at least the following code: + + .. code-block:: cpp + + #include + + void setup() { + RPC.begin(); + } + + void loop() { } + +Debugging +========= + +Debugging is not yet supported by this board, since the debug port does +not have an easy access. + +.. _ARDUINO-OPTA website: + https://docs.arduino.cc/hardware/opta + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf diff --git a/boards/arduino/portenta_h7/CMakeLists.txt b/boards/arduino/portenta_h7/CMakeLists.txt new file mode 100644 index 00000000000000..526629d7110fcb --- /dev/null +++ b/boards/arduino/portenta_h7/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M7) + +zephyr_library() +zephyr_library_sources(board.c) + +endif() diff --git a/boards/arduino/portenta_h7/Kconfig.arduino_portenta_h7 b/boards/arduino/portenta_h7/Kconfig.arduino_portenta_h7 new file mode 100644 index 00000000000000..fa3b247b922e1a --- /dev/null +++ b/boards/arduino/portenta_h7/Kconfig.arduino_portenta_h7 @@ -0,0 +1,8 @@ +# Arduino Portenta H7 board configuration + +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_PORTENTA_H7 + select SOC_STM32H747XX_M7 if BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M7 + select SOC_STM32H747XX_M4 if BOARD_ARDUINO_PORTENTA_H7_STM32H747XX_M4 diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi similarity index 100% rename from boards/arm/arduino_portenta_h7/arduino_portenta_h7-common.dtsi rename to boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.dts rename to boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.dts diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml new file mode 100644 index 00000000000000..afbca313573ebe --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml @@ -0,0 +1,17 @@ +identifier: arduino_portenta_h7/stm32h747xx/m4 +name: Arduino Portenta H7 (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - gpio +testing: + ignore_tags: + - mpu + - nfc +vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000000..4929eecabb7006 --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4_defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable pin controller +CONFIG_PINCTRL=y + +# Enable uart driver +# CONFIG_SERIAL=y + +# By default CONSOLE is assigned to m7 +# CONFIG_CONSOLE=y +# CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts similarity index 100% rename from boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.dts rename to boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml new file mode 100644 index 00000000000000..ee73966dbfedae --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml @@ -0,0 +1,13 @@ +identifier: arduino_portenta_h7/stm32h747xx/m7 +name: Arduino Portenta H7 (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - gpio +vendor: arduino diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000000..18f533bf91d916 --- /dev/null +++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2022 Benjamin Björnsson . +# SPDX-License-Identifier: Apache-2.0 + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable pin controller +CONFIG_PINCTRL=y + +# Use zephyr,code-partition as flash offset +CONFIG_USE_DT_CODE_PARTITION=y + +# Disable following to assign serial ports to m4 core + +# Enable uart driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable regulator +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED=y diff --git a/boards/arm/arduino_portenta_h7/board.c b/boards/arduino/portenta_h7/board.c similarity index 100% rename from boards/arm/arduino_portenta_h7/board.c rename to boards/arduino/portenta_h7/board.c diff --git a/boards/arm/arduino_portenta_h7/board.cmake b/boards/arduino/portenta_h7/board.cmake similarity index 100% rename from boards/arm/arduino_portenta_h7/board.cmake rename to boards/arduino/portenta_h7/board.cmake diff --git a/boards/arduino/portenta_h7/board.yml b/boards/arduino/portenta_h7/board.yml new file mode 100644 index 00000000000000..be2ba58da962f1 --- /dev/null +++ b/boards/arduino/portenta_h7/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_portenta_h7 + vendor: arduino + socs: + - name: stm32h747xx diff --git a/boards/arm/arduino_portenta_h7/doc/img/arduino_portenta_h7.jpeg b/boards/arduino/portenta_h7/doc/img/arduino_portenta_h7.jpeg similarity index 100% rename from boards/arm/arduino_portenta_h7/doc/img/arduino_portenta_h7.jpeg rename to boards/arduino/portenta_h7/doc/img/arduino_portenta_h7.jpeg diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst new file mode 100644 index 00000000000000..87b7aefdfe5d70 --- /dev/null +++ b/boards/arduino/portenta_h7/doc/index.rst @@ -0,0 +1,144 @@ +.. _arduino_portenta_h7_board: + +Arduino Portenta H7 +################### + +Overview +******** + +The Portenta H7 enables a wide diversity of applications taking benefit +from Computer Vision, PLCs, Robotics controller, High-end industrial machinery +and high-speed booting computation (ms). + +The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, +with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, +large set of peripherals, SMPS, and MIPI-DSI. + +Additionally, the board features: +- USB OTG FS +- 3 color user LEDs + +.. image:: img/arduino_portenta_h7.jpeg + :width: 500px + :align: center + :height: 325px + :alt: ARDUINO_PORTENTA_H7 + +More information about the board can be found at the `ARDUINO_PORTENTA_H7 website`_. +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr arduino_portenta_h7 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Building and Flashing +************************* + +Applications for the ``arduino_portenta_h7`` board should be built per core target, +using either ``arduino_portenta_h7_m7`` or ``arduino_portenta_h7_m4`` as the target. +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Installing dfu-util +------------------- + +This board requires dfu-utils for flashing. It is recommended to use at least +v0.8 of `dfu-util`_. The package available in debian/ubuntu can be quite old, so you might +have to build dfu-util from source. + +Flashing an application to STM32H747I M7 Core +--------------------------------------------- + +First, connect the Arduino Portenta H7 board to your host computer using +the USB port to prepare it for flashing. Double tap the button to put the board +into the Arduino Bootloader mode. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_portenta_h7/stm32h747xx/m7 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arduino_portenta_h7 + +Similarly, you can build and flash samples on the M4 target. For this, please +take care of the resource sharing (UART port used for console for instance). + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: arduino_portenta_h7/stm32h747xx/m4 + :goals: build flash + +.. _ARDUINO_PORTENTA_H7 website: + https://docs.arduino.cc/hardware/portenta-h7 + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html diff --git a/boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima b/boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima new file mode 100644 index 00000000000000..2fae481238c0b3 --- /dev/null +++ b/boards/arduino/uno_r4_minima/Kconfig.arduino_uno_r4_minima @@ -0,0 +1,5 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_UNO_R4_MINIMA + select SOC_R7FA4M1AB3CFM diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4_minima/arduino_uno_r4_common.dtsi similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_common.dtsi rename to boards/arduino/uno_r4_minima/arduino_uno_r4_common.dtsi diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima-pinctrl.dtsi b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima-pinctrl.dtsi rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima-pinctrl.dtsi diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima.dts b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima.dts similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima.dts rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima.dts diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima.yaml b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima.yaml similarity index 100% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima.yaml rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima.yaml diff --git a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima_defconfig b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig similarity index 76% rename from boards/arm/arduino_uno_r4/arduino_uno_r4_minima_defconfig rename to boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig index 57abb934998940..bcd05338d44458 100644 --- a/boards/arm/arduino_uno_r4/arduino_uno_r4_minima_defconfig +++ b/boards/arduino/uno_r4_minima/arduino_uno_r4_minima_defconfig @@ -1,22 +1,19 @@ # Copyright (c) 2023 TOKITA Hiroshi # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RA4M1=y -CONFIG_SOC_R7FA4M1AB3CFM=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_BUILD_OUTPUT_HEX=y -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_uno_r4/board.cmake b/boards/arduino/uno_r4_minima/board.cmake similarity index 100% rename from boards/arm/arduino_uno_r4/board.cmake rename to boards/arduino/uno_r4_minima/board.cmake diff --git a/boards/arduino/uno_r4_minima/board.yml b/boards/arduino/uno_r4_minima/board.yml new file mode 100644 index 00000000000000..f4dc7b8467b639 --- /dev/null +++ b/boards/arduino/uno_r4_minima/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_uno_r4_minima + vendor: arduino + socs: + - name: r7fa4m1ab3cfm diff --git a/boards/arm/arduino_uno_r4/doc/index.rst b/boards/arduino/uno_r4_minima/doc/index.rst similarity index 100% rename from boards/arm/arduino_uno_r4/doc/index.rst rename to boards/arduino/uno_r4_minima/doc/index.rst diff --git a/boards/arduino/zero/Kconfig.arduino_zero b/boards/arduino/zero/Kconfig.arduino_zero new file mode 100644 index 00000000000000..ade23a1229fafd --- /dev/null +++ b/boards/arduino/zero/Kconfig.arduino_zero @@ -0,0 +1,6 @@ +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARDUINO_ZERO + select SOC_SAMD21G18A diff --git a/boards/arm/arduino_zero/arduino_zero-pinctrl.dtsi b/boards/arduino/zero/arduino_zero-pinctrl.dtsi similarity index 100% rename from boards/arm/arduino_zero/arduino_zero-pinctrl.dtsi rename to boards/arduino/zero/arduino_zero-pinctrl.dtsi diff --git a/boards/arm/arduino_zero/arduino_zero.dts b/boards/arduino/zero/arduino_zero.dts similarity index 100% rename from boards/arm/arduino_zero/arduino_zero.dts rename to boards/arduino/zero/arduino_zero.dts diff --git a/boards/arm/arduino_zero/arduino_zero.yaml b/boards/arduino/zero/arduino_zero.yaml similarity index 100% rename from boards/arm/arduino_zero/arduino_zero.yaml rename to boards/arduino/zero/arduino_zero.yaml diff --git a/boards/arduino/zero/arduino_zero_defconfig b/boards/arduino/zero/arduino_zero_defconfig new file mode 100644 index 00000000000000..c7f66b36c3647d --- /dev/null +++ b/boards/arduino/zero/arduino_zero_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/arduino_zero/board.cmake b/boards/arduino/zero/board.cmake similarity index 100% rename from boards/arm/arduino_zero/board.cmake rename to boards/arduino/zero/board.cmake diff --git a/boards/arduino/zero/board.yml b/boards/arduino/zero/board.yml new file mode 100644 index 00000000000000..86d4a97c1129ba --- /dev/null +++ b/boards/arduino/zero/board.yml @@ -0,0 +1,5 @@ +board: + name: arduino_zero + vendor: arduino + socs: + - name: samd21g18a diff --git a/boards/arm/arduino_zero/doc/img/arduino_zero.jpg b/boards/arduino/zero/doc/img/arduino_zero.jpg similarity index 100% rename from boards/arm/arduino_zero/doc/img/arduino_zero.jpg rename to boards/arduino/zero/doc/img/arduino_zero.jpg diff --git a/boards/arduino/zero/doc/index.rst b/boards/arduino/zero/doc/index.rst new file mode 100644 index 00000000000000..46eb837040c507 --- /dev/null +++ b/boards/arduino/zero/doc/index.rst @@ -0,0 +1,166 @@ +.. _arduino_zero: + +Arduino/Genuino Zero +#################### + +Overview +******** + +The Arduino Zero is a maker-friendly development board with +Atmel’s Embedded Debugger (EDBG), which provides a full +debug interface without the need for additional hardware. + +.. image:: img/arduino_zero.jpg + :align: center + :alt: Arduino Zero + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- 3 user LEDs +- One reset button +- On-board USB based EDBG unit with serial console +- Native USB port + +Supported Features +================== + +The arduino_zero board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| DAC | on-chip | Digital to analogue converter | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/arduino/zero/arduino_zero_defconfig`. + +Connections and IOs +=================== + +The `Arduino store`_ has detailed information about board +connections. Download the `Arduino Zero Schematic`_ for more detail. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. One of the USARTs +(SERCOM5) is connected to the onboard Atmel Embedded Debugger (EDBG). +SERCOM0 is available on the D0/D1 pins. + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC2 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino Zero, SERCOM4 +is available on the 6 pin connector at the edge of the board. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +DAC +=== + +The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the +Arduino Zero, the DAC is available on pin A0. + +Programming and Debugging +************************* + +The Arduino Zero comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMD21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_zero + :goals: build + :compact: + +#. Connect the Arduino Zero to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arduino_zero + :goals: flash + :compact: + + You should see "Hello World! arduino_zero" in your terminal. + +References +********** + +.. target-notes:: + +.. _Arduino Store: + https://store.arduino.cc/genuino-zero + +.. _Arduino Zero Schematic: + https://www.arduino.cc/en/uploads/Main/Zero_V1.0.pdf diff --git a/boards/arm/arduino_zero/pre_dt_board.cmake b/boards/arduino/zero/pre_dt_board.cmake similarity index 100% rename from boards/arm/arduino_zero/pre_dt_board.cmake rename to boards/arduino/zero/pre_dt_board.cmake diff --git a/boards/arm/arduino_zero/support/openocd.cfg b/boards/arduino/zero/support/openocd.cfg similarity index 100% rename from boards/arm/arduino_zero/support/openocd.cfg rename to boards/arduino/zero/support/openocd.cfg diff --git a/boards/arm/96b_aerocore2/Kconfig.board b/boards/arm/96b_aerocore2/Kconfig.board deleted file mode 100644 index 55d8a706d1b87f..00000000000000 --- a/boards/arm/96b_aerocore2/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_AEROCORE2 - bool "96Boards AEROCORE2 (STM32F427)" - depends on SOC_STM32F427XX diff --git a/boards/arm/96b_aerocore2/Kconfig.defconfig b/boards/arm/96b_aerocore2/Kconfig.defconfig deleted file mode 100644 index 02d82f6f25a01a..00000000000000 --- a/boards/arm/96b_aerocore2/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_AEROCORE2 - -config BOARD - default "96b_aerocore2" - -endif # BOARD_96B_AEROCORE2 diff --git a/boards/arm/96b_aerocore2/doc/index.rst b/boards/arm/96b_aerocore2/doc/index.rst deleted file mode 100644 index 6d56911c2f1acf..00000000000000 --- a/boards/arm/96b_aerocore2/doc/index.rst +++ /dev/null @@ -1,350 +0,0 @@ -.. _96b_aerocore2_board: - -96Boards Aerocore2 -################## - -Overview -******** - -The 96Boards Aerocore2 Mezzanine is based on the STMicroelectronics -STM32F427VIT6 Cortex-M4 CPU primarily designed for use in drones. -This board acts as a mezzanine platform for all 96Boards CE compliant -boards. It can also be used as a standalone board. - - -.. figure:: img/96b_aerocore2.jpg - :align: center - :alt: 96Boards Aerocore2 - - 96Boards Aerocore2 - -Hardware -******** - -96Boards Aerocore2 provides the following hardware components: - -- STM32F427VIT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 2048 KB Flash -- 256 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels -- RTC -- Advanced-control Timers (2) -- General Purpose Timers (10) -- Watchdog Timers (2) -- USART/UART (4) -- I2C (3) -- SPI (3) -- SDIO -- USB 2.0 OTG FS -- DMA Controller - -More information about STM32F427VIT6 can be found here: - - `STM32F427 on www.st.com`_ - -Supported Features -================== - -The Zephyr 96b_aerocore2 board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| PWM | on-chip | timers / pwm | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ - -More details about the board can be found at `96Boards website`_. - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_aerocore2/96b_aerocore2_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PE10 -- LED2 / User2 LED = PE9 - -External Connectors -------------------- - -Octal PWM Header (J1) - -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | Pin # | Signal Name | -+=======+=============+=========================+=======+=============+=======+=============+ -| 1 | PWM4_CH1 | PD12 | 2 | 5.0v | 3 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 4 | PWM4_CH2 | PD13 | 5 | 5.0v | 6 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 7 | PWM4_CH3 | PD14 | 8 | 5.0v | 9 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 10 | PWM4_CH4 | PD15 | 11 | 5.0v | 12 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 13 | PWM5_CH1 | PA0 | 14 | 5.0v | 15 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 16 | PWM5_CH2 | PA1 | 17 | 5.0v | 18 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 19 | PWM5_CH3 | PA2 | 20 | 5.0v | 21 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ -| 22 | PWM5_CH4 | PA3 | 23 | 5.0v | 24 | GND | -+-------+-------------+-------------------------+-------+-------------+-------+-------------+ - - -IO Header J11 - -+-------+-------------+-------+-------------+ -| PIN # | Signal Name | PIN # | Signal Name | -+=======+=============+=======+=============+ -| 1 | PB9 | 2 | PB8* | -+-------+-------------+-------+-------------+ -| 3 | PC9 | 4 | PB0 | -+-------+-------------+-------+-------------+ -| 5 | PE5 | 6 | NA | -+-------+-------------+-------+-------------+ -| 7 | PE6 | 8 | NA | -+-------+-------------+-------+-------------+ -| 9 | PC6 | 10 | NA | -+-------+-------------+-------+-------------+ -| 11 | PC7 | 12 | NA | -+-------+-------------+-------+-------------+ -| 13 | PC8 | 14 | NA | -+-------+-------------+-------+-------------+ -| 15 | PA8 | 16 | GND | -+-------+-------------+-------+-------------+ -| 17 | PA9 | 18 | 3v3 | -+-------+-------------+-------+-------------+ -| 19 | PA10 | 20 | GND | -+-------+-------------+-------+-------------+ - -* PB8 is connected to a watchdog buzzer, It needs to be pulsed every 10 seconds to keep the buzzer silent. - -IO Header J5 - -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | PIN # | Signal Name | STM32F427 Functions Pin | -+=======+=============+=========================+=======+=============+=========================+ -| 1 | AGND | AGND | 2 | ADC1_13 | PC3 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 3 | ADC1_12 | PC2 | 4 | ADC1_11 | PC1 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 5 | I2C_SDA | PB11 | 6 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 7 | I2C_SCL | PB10 | 8 | VCC 3v3 | VCC 3v3 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 9 | NC | NC | 10 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 11 | NC | NC | 12 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 13 | UART_TX 7 | PE8 | 14 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 15 | UART_RX 7 | PE7 | 16 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 17 | UART_TX 2 | PD5 | 18 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 19 | UART_TX 2 | PD6 | 20 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 21 | NC | NC | 10 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 23 | NC | NC | 10 | NC | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 25 | SPI1_NIRQ | PC5 | 26 | GND | GND | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 27 | SPI1_CLK | PA5 | 28 | SPI1_MISO | PA6 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 29 | SPI1_CS0 | PA4 | 30 | SPI1_MOSI | PA7 | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 31 | CAN_TX | PD1 | 32 | CANH | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ -| 33 | CAN_RX | PD0 | 34 | CANL | NC | -+-------+-------------+-------------------------+-------+-------------+-------------------------+ - - -GPS connector J15 - -+-------+-------------+-------------------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | -+=======+=============+=========================+ -| 1 | V_OUT 5v | NC | -+-------+-------------+-------------------------+ -| 2 | UART1_TX | PB6 | -+-------+-------------+-------------------------+ -| 3 | UART1_RX | PB7 | -+-------+-------------+-------------------------+ -| 4 | VCC 3v3 | NC | -+-------+-------------+-------------------------+ -| 5 | GND | GND | -+-------+-------------+-------------------------+ - - -Spektrum connector J3 - -+-------+-------------+-------------------------+ -| PIN # | Signal Name | STM32F427 Functions Pin | -+=======+=============+=========================+ -| 1 | VCC 3v3 | NC | -+-------+-------------+-------------------------+ -| 2 | GND | GND | -+-------+-------------+-------------------------+ -| 3 | UART8_RX | PE0 | -+-------+-------------+-------------------------+ - - -External Clock Sources ----------------------- - -STM32F4 has one external oscillator. The frequency of the clock is -32.768 kHz. The internal 16MHz clock is used as the main clock. - -Serial Port ------------ - -96Boards Aerocore2 board has up to 4 U(S)ARTs. The Zephyr console output is -assigned to USART7. Default settings are 115200 8N1. - -I2C ---- - -96Boards Aerocore2 board has 1 I2C port. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB10 -- I2C1_SDA : PB11 - -SPI ---- - -96Boards Aerocore2 board has 1 SPI port. The default SPI mapping for Zephyr is: - -- SPI1_CS0 : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 - -USB -=== - -96Boards Aerocore2 board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its mini "OTG" USB connector. -Only USB device functions are supported in Zephyr at the moment. - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader -supports flashing via USB (DFU), UART, I2C and SPI. You can read more about -how to enable and use the ROM bootloader by checking the application -note `AN2606`_, page 109. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -Flashing an Application to 96Boards Aerocore2 ---------------------------------------------- - -Connect the micro-USB cable to the USB OTG/STM_CONSOLE Aerocore2 port and to your computer. -The board should power ON. Force the board into DFU mode by keeping the BOOT0 -switch pressed while pressing and releasing the RST switch. - -The BOOT button is located at the back-side of the PCB. - -Confirm that the board is in DFU mode: - -.. code-block:: console - - $ sudo dfu-util -l - dfu-util 0.8 - Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. - Copyright 2010-2014 Tormod Volden and Stefan Schmidt - This program is Free Software and has ABSOLUTELY NO WARRANTY - Please report bugs to dfu-util@lists.gnumonks.org - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" - Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" - -You should see following confirmation on your Linux host: - -.. code-block:: console - - $ dmesg - usb 1-2.1: new full-speed USB device number 14 using xhci_hcd - usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 - usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - usb 1-2.1: Product: STM32 BOOTLOADER - usb 1-2.1: Manufacturer: STMicroelectronics - usb 1-2.1: SerialNumber: 3574364C3034 - -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_aerocore2 - :goals: build flash - -Connect a USB-TTL dongle to the UART_7 header port and to your computer. -Run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board 96Boards Aerocore2 -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. -The ``-b`` option sets baud rate ignoring the value from config. - -Press the Reset button and you should see the following message in your -terminal: - -.. code-block:: console - - Hello World! arm - -.. _96Boards website: - https://www.96boards.org/product/aerocore2/ - -.. _STM32F427 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32f427vi.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _AN2606: - https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf diff --git a/boards/arm/96b_argonkey/Kconfig.board b/boards/arm/96b_argonkey/Kconfig.board deleted file mode 100644 index e259d3b23f2c68..00000000000000 --- a/boards/arm/96b_argonkey/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Argonkey Board Configuration - -# Copyright (c) 2018 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_ARGONKEY - bool "96Boards Argonkey" - depends on SOC_STM32F412CX diff --git a/boards/arm/96b_argonkey/Kconfig.defconfig b/boards/arm/96b_argonkey/Kconfig.defconfig deleted file mode 100644 index 7ee85442eaee3d..00000000000000 --- a/boards/arm/96b_argonkey/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# 96Boards Argonkey Board Configuration - -# Copyright (c) 2018 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_ARGONKEY - -config BOARD - default "96b_argonkey" - -if LSM6DSL - -choice LSM6DSL_TRIGGER_MODE - default LSM6DSL_TRIGGER_GLOBAL_THREAD -endchoice - -config LSM6DSL_SENSORHUB - default y - -choice LSM6DSL_EXTERNAL_SENSOR_0 - default LSM6DSL_EXT0_LIS2MDL -endchoice - -endif # LSM6DSL - -endif # BOARD_96B_ARGONKEY diff --git a/boards/arm/96b_argonkey/doc/index.rst b/boards/arm/96b_argonkey/doc/index.rst deleted file mode 100644 index 6221adee72cb0f..00000000000000 --- a/boards/arm/96b_argonkey/doc/index.rst +++ /dev/null @@ -1,240 +0,0 @@ -.. _96b_argonkey: - -96Boards Argonkey -################# - -Overview -******** - -96Boards Argonkey board is based on the ST Microelectronics STM32F412CG -Cortex M4 CPU. - -This board acts as a sensor hub platform for all 96Boards compliant -family products. It can also be used as a standalone board. - -.. figure:: img/96b_argonkey.jpg - :align: center - :alt: 96Boards Argonkey - - 96Boards Argonkey - -Hardware -******** - -96Boards Argonkey provides the following hardware components: - -- STM32F412CG in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 100 MHz max CPU frequency -- 1.8V work voltage -- 1024 KB Flash -- 256 KB SRAM -- On board sensors: - - - Humidity: STMicro HTS221 - - Temperature/Pressure: STMicro LPS22HB - - ALS: Intersil ISL29034 - - Proximity: STMicro VL53L0X - - Accelerometer/Gyroscope: STMicro LSM6DSL - - Geomagnetic: STMicro LIS2MDL - - AMR Hall sensor: MRMS501A - - Microphone: STMicro MP34DT05 - -- 2 User LEDs -- 16 General purpose LEDs -- GPIO with external interrupt capability -- UART -- I2C (3) -- SPI (1) -- I2S (1) - -Supported Features -================== - -The Zephyr 96b_argonkey board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -More information about the board can be found at the -`ARGONKEY website`_. - -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_argonkey/96b_argonkey_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PB2 -- LED2 / User2 LED = PC13 - -Push buttons ------------- - -- BUTTON = RST (BT1) -- BUTTON = USR (BT2) - -System Clock -============ - -96Boards Argonkey can be driven by an internal oscillator as well as the main -PLL clock. In default board configuration, the 16MHz external oscillator is -used to drive the main PLL clock to generate a System Clock (SYSCLK) at 84MHz. -On the bus side, AHB clock runs at 84MHz, while APB1/APB2 clock runs at 42MHz. - -Serial Port -=========== - -On 96Boards Argonkey, Zephyr console output is assigned to USART1. -Default settings are 115200 8N1. - -I2C ---- - -96Boards Argonkey board has up to 3 I2Cs. The default I2C mapping is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB9 -- I2C3_SCL : PA8 -- I2C3_SCL : PB4 - -I2C3 goes to the P2 connector and can be used to attach external sensors. -It goes to 100Kbit maximum. - -SPI ---- -96Boards Argonkey board has 2 SPIs. SPI1 is used in slave mode as the communication -bus with the AP. SPI2 is used in master mode to control the LSM6DSL sensor. -The default SPI mapping is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 - -Programming and Debugging -************************* - -Building -======== - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_argonkey - :goals: build - -Flashing -======== - -96Boards Argonkey can be flashed by two methods, one using the ROM -bootloader and another using the SWD debug port (which requires additional -hardware). - -Flashing using the ROM bootloader requires a special activation pattern, -which can be triggered by using the BOOT0 pin. The ROM bootloader supports -flashing via USB (DFU), UART, I2C and SPI, but this document describes the -UART case only. You can read more about how to enable and use the ROM -bootloader by checking the application note `AN2606`_ . - -Using ROM bootloader: ---------------------- - -Hereafter the documents describes basic steps to perform ArgonKey firmware -flashing on a Linux PC using UART as communication channel. - -1. Connect ArgonKey UART to your Linux PC using, for example, a USB-TTL serial - cable. The flashing procedure has been tested using a `TTL-232RG`_ cable with - FTDI chip. The UART pins on ArgonKey can be found on the P3 low speed - expansion connector on the back of the board. - - - GND (black) to ArgonKey GND (P3.1) - - TXD (orange) to ArgonKey UART0_TXD (P3.5) - - RXD (yellow) to ArgonKey UART0_RXD (P3.7) - - When the USB cable is inserted to the Linux PC the following device will be - created: /dev/ttyUSBx (x is usually '0'). - -2. Force STM32F412CG to enter in Bootloader mode - - - Connect BOOT0 to 1V8 (link P2.1 to P3.30) - - Press and release the RST button - -3. Use stm32flash utility to flash the ArgonKey: - -.. code-block:: console - - $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyUSB0 - -See References section for more info on `stm32flash`_. - -Using SWD debugger: -------------------- - -Select a commercial JTAG/SWD h/w tool and connect it to ArgonKey P4 connector. - -The ArgonKey has been tested using the `ST-LINK/V2`_ tool. Once that the tool -is connected to the PC through USB, it presents itself as a USB composite -device with mass storage capability. The device can be then mounted in linux -and the f/w can be actually copied there and will be automatically flashed by -the ST-LINK onto the ArgonKey. - -Example: - -.. code-block:: console - - $ mount /dev/sdb /mnt - $ cp zephyr.bin /mnt - $ umount /mnt - -Debugging -========= - -References -********** - -.. target-notes:: - -.. _ARGONKEY website: - https://www.st.com/en/evaluation-tools/steval-mki187v1.html - -.. _AN2606: - https://www.st.com/resource/en/application_note/cd00167594.pdf - -.. _stm32flash: - https://sourceforge.net/p/stm32flash/wiki/Home/ - -.. _ST-LINK/V2: - https://www.st.com/en/development-tools/st-link-v2.html - -.. _TTL-232RG: - http://www.ftdichip.com/Support/Documents/DataSheets/Cables/DS_TTL-232RG_CABLES.pdf diff --git a/boards/arm/96b_avenger96/Kconfig.board b/boards/arm/96b_avenger96/Kconfig.board deleted file mode 100644 index 78012ba940c1be..00000000000000 --- a/boards/arm/96b_avenger96/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Avenger96 board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_AVENGER96 - bool "96Boards Avenger96 Board" - depends on SOC_STM32MP15_M4 diff --git a/boards/arm/96b_avenger96/Kconfig.defconfig b/boards/arm/96b_avenger96/Kconfig.defconfig deleted file mode 100644 index b5cf5e03d493a7..00000000000000 --- a/boards/arm/96b_avenger96/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# 96Boards Avenger96 board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_AVENGER96 - -config BOARD - default "96b_avenger96" - -endif # BOARD_96B_AVENGER96 diff --git a/boards/arm/96b_avenger96/doc/index.rst b/boards/arm/96b_avenger96/doc/index.rst deleted file mode 100644 index de7e1393182946..00000000000000 --- a/boards/arm/96b_avenger96/doc/index.rst +++ /dev/null @@ -1,279 +0,0 @@ -.. _96b_avenger96: - -96Boards Avenger96 -################## - -Overview -******** - -96Boards Avenger96 board is based on ST Microelectronics STM32MP157A -multi-core processor, composed of a dual Cortex®-A7 and a single Cortex®-M4 -core. Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - PMIC: STPMIC1A - - RAM: 1024 Mbyte @ 533MHz - - Storage: - - - eMMC: v4.51: 8 Gbyte - - QSPI: 2Mbyte - - EEPROM: 128 byte - - microSD Socket: UHS-1 v3.01 - - Ethernet: 10/100/1000 Mbit/s, IEEE 802.3 Compliant - - Wireless: - - - WiFi: 5 GHz & 2.4GHz IEEE 802.11a/b/g/n/ac - - Bluetooth: v4.2 (BR/EDR/BLE) - - USB: - - - Host - 2x type A, 2.0 high-speed - - OTG: - 1x type micro-AB, 2.0 high-speed - - HDMI: WXGA (1366x768)@ 60 fps, HDMI 1.4 - - Connectors: - - - 40-Pin Low Speed Header - - 60-Pin High Speed Header - - LEDs: - - - 4x Green user LEDs - - 1x Blue Bluetooth LED - - 1x Yellow WiFi LED - - 1x Red power supply LED - -.. image:: img/96b_avenger96.jpg - :align: center - :alt: 96Boards Avenger96 - -More information about the board can be found at the -`96Boards website`_. - -Hardware -******** - -The STM32MP157A SoC provides the following hardware capabilities: - -- Core: - - - 32-bit dual-core Arm® Cortex®-A7 - - - L1 32-Kbyte I / 32-Kbyte D for each core - - 256-Kbyte unified level 2 cache - - Arm® NEON™ - - - 32-bit Arm® Cortex®-M4 with FPU/MPU - - - Up to 209 MHz (Up to 703 CoreMark®) - -- Memories: - - - External DDR memory up to 1 Gbyte. - - 708 Kbytes of internal SRAM: 256 KB of AXI SYSRAM + 384 KB of AHB SRAM + - 64 KB of AHB SRAM in backup domain. - - Dual mode Quad-SPI memory interface - - Flexible external memory controller with up to 16-bit data bus - -- Clock management: - - - Internal oscillators: 64 MHz HSI oscillator, 4 MHz CSI oscillator, 32 kHz - LSI oscillator - - External oscillators: 8-48 MHz HSE oscillator, 32.768 kHz LSE oscillator - - 6 × PLLs with fractional mode - -- General-purpose input/outputs: - - - Up to 176 I/O ports with interrupt capability - -- Interconnect matrix - -- 3 DMA controllers - -- Communication peripherals: - - - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus) - - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave) - - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy) - - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx) - - SPDIF Rx with 4 inputs - - HDMI-CEC interface - - MDIO Slave interface - - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO) - - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability - - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously - - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI) - - 8- to 14-bit camera interface up to 140 Mbyte/s - - 6 analog peripherals - - 2 × ADCs with 16-bit max. resolution. - - 1 × temperature sensor - - 2 × 12-bit D/A converters (1 MHz) - - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6 - filters - - Internal or external ADC/DAC reference VREF+ - -- Graphics: - - - 3D GPU: Vivante® - OpenGL® ES 2.0 - - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps - - MIPI® DSI 2 data lanes up to 1 GHz each - -- Timers: - - - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature - (incremental) encoder input - - 2 × 16-bit advanced motor control timers - - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM) - - 5 × 16-bit low-power timers - - RTC with sub-second accuracy and hardware calendar - - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor) - - 1 × SysTick Cortex®-M4 timer - -- Hardware acceleration: - - - HASH (MD5, SHA-1, SHA224, SHA256), HMAC - - 2 × true random number generator (3 oscillators each) - - 2 × CRC calculation unit - -- Debug mode: - - - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces - - 8-Kbyte embedded trace buffer - - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user - -More information about STM32P157A can be found here: - -- `STM32MP157A on www.st.com`_ -- `STM32MP157A reference manual`_ - -Supported Features -================== - -The Zephyr 96b_avenger96 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/96b_avenger96/96b_avenger96_defconfig`` - - -Connections and IOs -=================== - -96Boards Avenger96 Board schematic is available here: -`Avenger96 board schematics`_. - - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_7 TX/RX/RTS/CTS : PE8/PE7/PE9/PE10 (UART console) -- UART_4 TX/RX : PD1/PB2 - -System Clock ------------- - -The Cortex®-M4 Core is configured to run at a 209 MHz clock speed. This value -must match the configured mlhclk_ck frequency. - -Serial Port ------------ - -96Boards Avenger96 board has 3 U(S)ARTs. The Zephyr console output is assigned -by default to the RAM console to be dumped by the Linux Remoteproc Framework -on Cortex®-A7 core. Alternatively, Zephyr console output can be assigned to -UART7 which is disabled by default. UART console can be enabled through -board's devicetree and 96b_avenger96_defconfig board file (or prj.conf -project files), and will disable existing RAM console output. Default UART -console settings are 115200 8N1. - -Programming and Debugging -************************* - -The STM32MP157A doesn't have QSPI flash for the Cortex®-M4 and it needs to be -started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the -Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset. -The Cortex®-A7 can perform these steps at bootloader level or after the Linux -system has booted. - -The Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at -address 0x00000000 (RETRAM), the vector table should be loaded at this address -These are the memory mappings for Cortex®-A7 and Cortex®-M4: - -+------------+-----------------------+------------------------+----------------+ -| Region | Cortex®-A7 | Cortex®-M4 | Size | -+============+=======================+========================+================+ -| RETRAM | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF | 64KB | -+------------+-----------------------+------------------------+----------------+ -| MCUSRAM | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF | 384KB | -+------------+-----------------------+------------------------+----------------+ -| DDR | 0xC0000000-0xFFFFFFFF | | up to 1 GB | -+------------+-----------------------+------------------------+----------------+ - - -Refer to `stm32mp157 boot Cortex-M4 firmware`_ wiki page for instruction -to load and start the Cortex-M4 firmware. - -Debugging -========= - -You can debug an application using OpenOCD and GDB. The Solution proposed below -is based on the Linux STM32MP1 SDK OpenOCD and is available only for a Linux -environment. The firmware must first be loaded by the Cortex®-A7. Developer -then attaches the debugger to the running Zephyr using OpenOCD. - -Prerequisite ------------- -install `stm32mp1 developer package`_. - -1) start OpenOCD in a dedicated terminal - - - Start up the sdk environment:: - - source /environment-setup-cortexa7hf-neon-vfpv4-openstlinux_weston-linux-gnueabi - - - Start OpenOCD:: - - ${OECORE_NATIVE_SYSROOT}/usr/bin/openocd -s ${OECORE_NATIVE_SYSROOT}/usr/share/openocd/scripts -f board/stm32mp15x_ev1_jlink_jtag.cfg - -2) run gdb in Zephyr environment - - .. code-block:: console - - # On Linux - cd $ZEPHYR_BASE/samples/hello_world - mkdir -p build && cd build - - # Use cmake to configure a Ninja-based build system: - cmake -GNinja -DBOARD=96b_avenger96 .. - - # Now run ninja on the generated build system: - ninja debug - -.. _96Boards website: - https://www.96boards.org/product/avenger96/ - -.. _STM32MP157A on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp157/stm32mp157a.html - -.. _STM32MP157A reference manual: - https://www.st.com/resource/en/reference_manual/DM00327659.pdf - -.. _Avenger96 board schematics: - https://www.96boards.org/documentation/consumer/avenger96/hardware-docs/files/avenger96-schematics.pdf - -.. _stm32mp1 developer package: - https://wiki.st.com/stm32mpu/index.php/STM32MP1_Developer_Package#Installing_the_SDK - -.. _stm32mp157 boot Cortex-M4 firmware: - https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework diff --git a/boards/arm/96b_carbon/96b_carbon.yaml b/boards/arm/96b_carbon/96b_carbon.yaml deleted file mode 100644 index 3b465d9e676e32..00000000000000 --- a/boards/arm/96b_carbon/96b_carbon.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: 96b_carbon -name: 96Boards Carbon -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - ble - - i2c - - counter - - spi - - usb_device -ram: 96 -flash: 512 -vendor: seeed diff --git a/boards/arm/96b_carbon/96b_carbon_defconfig b/boards/arm/96b_carbon/96b_carbon_defconfig deleted file mode 100644 index 92cb9c88b9dde2..00000000000000 --- a/boards/arm/96b_carbon/96b_carbon_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/96b_carbon/Kconfig.board b/boards/arm/96b_carbon/Kconfig.board deleted file mode 100644 index fc9e1d5df41378..00000000000000 --- a/boards/arm/96b_carbon/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96boards Carbon STMF401RE board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_CARBON - bool "96Boards Carbon (STM32F401)" - depends on SOC_STM32F401XE diff --git a/boards/arm/96b_carbon/Kconfig.defconfig b/boards/arm/96b_carbon/Kconfig.defconfig deleted file mode 100644 index e7d7a1bd3f807a..00000000000000 --- a/boards/arm/96b_carbon/Kconfig.defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# 96boards Carbon board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_CARBON - -config BOARD - default "96b_carbon" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -endif # BT - -if NETWORKING - -# Re-create the NET_L2_BT dependencies here -config BT - default y - -config BT_PERIPHERAL - default BT - -config BT_CENTRAL - default BT - -config BT_SMP - default BT - -config BT_L2CAP_DYNAMIC_CHANNEL - default BT - -# BT is the only onboard network iface, so use it for IP networking -# if it's enabled - -config NET_L2_BT - depends on NET_IPV6 - default BT - -config NET_L2_BT_ZEP1656 - depends on NET_IPV6 - default BT - -endif # NETWORKING - -endif # BOARD_96B_CARBON diff --git a/boards/arm/96b_carbon/doc/index.rst b/boards/arm/96b_carbon/doc/index.rst deleted file mode 100644 index 7b63bb20de9541..00000000000000 --- a/boards/arm/96b_carbon/doc/index.rst +++ /dev/null @@ -1,384 +0,0 @@ -.. _96b_carbon_board: - -96Boards Carbon -############### - -Overview -******** - -The 96Boards is based on the STMicroelectronics STM32F401RET Cortex-M4 CPU and -also contains a nRF51822 chip connected over SPI for BLE connectivity. - -The 96Boards Carbon board is built with two chips: an STMicroelectronics -STM32F401RET Cortex-M4 CPU and an nRF51822 chip connected to -the Cortex-M4 CPU over SPI for Bluetooth LE connectivity. Even though -both chips exist on the same physical board, they must be programmed -separately: - -- The ``96b_carbon`` configuration is used when developing programs for - the main chip on the board, the STM32F401RET. Users will likely want to - write applications targeting this chip, using the ``96b_carbon`` - configuration, since it is connected to all of the breakout - I/O headers. - -- The ``96b_carbon_nrf51`` configuration should be used for programming - the secondary nRF51822 chip. Most users will likely not develop - applications for this chip, since Zephyr already provides a - sample application that can be flashed onto the nRF51822 - to provide Bluetooth functionality to applications on the main - STM32F401RET chip. - -For instructions on how to set up the nRF51822 to develop Bluetooth -applications, see :ref:`96b_carbon_nrf51_bluetooth`. - -After you have flashed your nRF51, you can perform basic validation -of this Bluetooth setup using the instructions -:ref:`below <96b_carbon_verify_bluetooth>`. - -.. figure:: img/96b_carbon.jpg - :align: center - :alt: 96Boards Carbon - - 96Boards Carbon - -Hardware -******** - -96Boards Carbon provides the following hardware components: - -- STM32F401RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 96 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (7) -- Watchdog Timers (2) -- USART/UART (4) -- I2C (3) -- SPI (3) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- Bluetooth LE over SPI, provided by nRF51822 - -More information about STM32F401RE can be found here: - - `STM32F401RE on www.st.com`_ - - `STM32F401 reference manual`_ - -Supported Features -================== - -The Zephyr 96b_carbon board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -More details about the board can be found at `96Boards website`_. - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_carbon/96b_carbon_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PD2 -- LED2 / User2 LED = PA15 -- LED3 / BT LED = PB5 -- LED4 / Power LED = VCC - -Push buttons ------------- - -- BUTTON = BOOT0 (SW1) -- BUTTON = RST - -External Connectors -------------------- - -Low Speed Header - -+--------+-------------+----------------------+ -| PIN # | Signal Name | STM32F401 Functions | -+========+=============+======================+ -| 1 | UART2_CTS | PA0 | -+--------+-------------+----------------------+ -| 3 | UART2_TX | PA2 | -+--------+-------------+----------------------+ -| 5 | UART2_RX | PA3 | -+--------+-------------+----------------------+ -| 7 | UART2_RTS | PA1 | -+--------+-------------+----------------------+ -| 9 | GND | GND | -+--------+-------------+----------------------+ -| 11 | USB5V | USB5V | -+--------+-------------+----------------------+ -| 13 | AIN12 | PC2 | -+--------+-------------+----------------------+ -| 15 | AIN14 | PC4 | -+--------+-------------+----------------------+ -| 17 | UART6_TX | PC6 | -+--------+-------------+----------------------+ -| 19 | GPIO | PC8 | -+--------+-------------+----------------------+ -| 21 | I2C1_SCL | PB6 | -+--------+-------------+----------------------+ -| 23 | I2C1_SCA | PB7 | -+--------+-------------+----------------------+ -| 25 | I2C2_SCA | PB3 | -+--------+-------------+----------------------+ -| 27 | I2C2_SCL | PB10 | -+--------+-------------+----------------------+ -| 29 | RST_BTN | RST_BTN | -+--------+-------------+----------------------+ - -+--------+-------------+----------------------+ -| PIN # | Signal Name | STM32F401 Functions | -+========+=============+======================+ -| 2 | SPI2_SS | PB12 | -+--------+-------------+----------------------+ -| 4 | SPI2_MOSI | PB15 | -+--------+-------------+----------------------+ -| 6 | SPI2_MISO | PB14 | -+--------+-------------+----------------------+ -| 8 | SPI2_SCK | PB13 | -+--------+-------------+----------------------+ -| 10 | GND | GND | -+--------+-------------+----------------------+ -| 12 | VCC2 | VCC2 | -+--------+-------------+----------------------+ -| 14 | AIN13 | PC3 | -+--------+-------------+----------------------+ -| 16 | AIN15 | PC5 | -+--------+-------------+----------------------+ -| 18 | UART6_RX | PC7 | -+--------+-------------+----------------------+ -| 20 | GPIO | PC9 | -+--------+-------------+----------------------+ -| 22 | I2C1_SCL | PB8 | -+--------+-------------+----------------------+ -| 24 | I2C1_SDA | PB9 | -+--------+-------------+----------------------+ -| 26 | AIN10 | PC0 | -+--------+-------------+----------------------+ -| 28 | AIN11 | PC1 | -+--------+-------------+----------------------+ -| 30 | NC | NC | -+--------+-------------+----------------------+ - -More detailed information about the connectors can be found in -`96Boards IE Specification`_. - -External Clock Sources ----------------------- - -STM32F4 has two external oscillators. The frequency of the slow clock is -32.768 kHz. The frequency of the main clock is 16 MHz. - -Serial Port ------------ - -96Boards Carbon board has up to 4 U(S)ARTs. The Zephyr console output is -assigned to USART1. Default settings are 115200 8N1. - -I2C ---- - -96Boards Carbon board has up to 2 I2Cs. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB3 - -SPI ---- - -96Boards Carbon board has up to 2 SPIs. SPI1 is used for Bluetooth communication -over HCI. The default SPI mapping for Zephyr is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 - -USB -=== - -96Boards Carbon board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its mini "OTG" USB connector. -Only USB device functions are supported in Zephyr at the moment. - -- USB_DM : PA11 -- USB_DP : PA12 - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. The ROM bootloader -supports flashing via USB (DFU), UART, I2C and SPI. You can read more about -how to enable and use the ROM bootloader by checking the application -note `AN2606`_, page 109. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -Flashing an Application to 96Boards Carbon ------------------------------------------- - -Connect the micro-USB cable to the USB OTG Carbon port and to your computer. -The board should power ON. Force the board into DFU mode by keeping the BOOT0 -switch pressed while pressing and releasing the RST switch. - -Confirm that the board is in DFU mode: - -.. code-block:: console - - $ sudo dfu-util -l - dfu-util 0.8 - Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. - Copyright 2010-2014 Tormod Volden and Stefan Schmidt - This program is Free Software and has ABSOLUTELY NO WARRANTY - Please report bugs to dfu-util@lists.gnumonks.org - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=3, name="@Device Feature/0xFFFF0000/01*004 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=2, name="@OTP Memory /0x1FFF7800/01*512 e,01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=1, name="@Option Bytes /0x1FFFC000/01*016 e", serial="3574364C3034" - Found DFU: [0483:df11] ver=2200, devnum=15, cfg=1, intf=0, alt=0, name="@Internal Flash /0x08000000/04*016Kg,01*064Kg,03*128Kg", serial="3574364C3034" - Found Runtime: [05ac:8290] ver=0104, devnum=2, cfg=1, intf=5, alt=0, name="UNKNOWN", serial="UNKNOWN" - -You should see following confirmation on your Linux host: - -.. code-block:: console - - $ dmesg - usb 1-2.1: new full-speed USB device number 14 using xhci_hcd - usb 1-2.1: New USB device found, idVendor=0483, idProduct=df11 - usb 1-2.1: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - usb 1-2.1: Product: STM32 BOOTLOADER - usb 1-2.1: Manufacturer: STMicroelectronics - usb 1-2.1: SerialNumber: 3574364C3034 - -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_carbon - :goals: build flash - -Connect the micro-USB cable to the USB UART (FTDI) port and to your computer. -Run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board 96Boards Carbon -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. -The ``-b`` option sets baud rate ignoring the value from config. - -Press the Reset button and you should see the following message in your -terminal: - -.. code-block:: console - - Hello World! arm - -.. _96b_carbon_verify_bluetooth: - -Verifying Bluetooth Functionality ---------------------------------- - -This section contains instructions for verifying basic Bluetooth -functionality on the board. For help on Zephyr applications -in general, see :ref:`build_an_application`. - -1. Flash the nRF51 with the hci_spi sample application as described in - :ref:`96b_carbon_nrf51_bluetooth`. - -#. Install the dfu-util flashing app, as described above. - -#. Build and flash the ``samples/bluetooth/ipsp`` application for - 96b_carbon. See the instructions above for how to put your board - into DFU mode if you haven't done this before: - - .. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/ipsp - :board: 96b_carbon - :goals: build flash - -#. Refer to the instructions in :ref:`bluetooth-ipsp-sample` for how - to verify functionality. - -Congratulations! Your 96Boards Carbon now has Bluetooth -connectivity. Refer to :ref:`bluetooth` for additional information on -further Bluetooth application development. - -Debugging -========= - -The 96b_carbon can be debugged by installing a 100 mil (0.1 inch) header -into the header at the bottom right hand side of the board, and -attaching an SWD debugger to the 3V3 (3.3V), GND, CLK, DIO, and RST -pins on that header. Then apply power to the 96Boards Carbon via one -of its USB connectors. You can now attach your debugger to the -STM32F401RET using an SWD scan. - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _AN2606: - https://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf - -.. _96Boards website: - http://www.96boards.org/documentation - -.. _STM32F401RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f401re.html - -.. _STM32F401 reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf - -.. _96Boards IE Specification: - https://linaro.co/ie-specification diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.dts b/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.dts deleted file mode 100644 index f4cd9310023a86..00000000000000 --- a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.dts +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "96b_carbon_nrf51-pinctrl.dtsi" - -/ { - model = "Seeed Studio Carbon nRF51 96board"; - compatible = "seeed,carbon_nrf51"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - aliases { - watchdog0 = &wdt0; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi1 { - compatible = "nordic,nrf-spis"; - status = "okay"; - def-char = <0x00>; - - pinctrl-0 = <&spi1_default>; - pinctrl-names = "default"; - bt-hci@0 { - compatible = "zephyr,bt-hci-spi-slave"; - reg = <0>; - irq-gpios = <&gpio0 28 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; - }; -}; diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.yaml b/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.yaml deleted file mode 100644 index 5ae43e121c71bf..00000000000000 --- a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: 96b_carbon_nrf51 -name: 96Boards Carbon (nRF51) -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - ble -vendor: seeed diff --git a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig b/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig deleted file mode 100644 index e53e9565e4af47..00000000000000 --- a/boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/96b_carbon_nrf51/Kconfig.board b/boards/arm/96b_carbon_nrf51/Kconfig.board deleted file mode 100644 index 71833ec87c8786..00000000000000 --- a/boards/arm/96b_carbon_nrf51/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Carbon nRF51 board configuration - -# Copyright (c) 2016, 2017 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_CARBON_NRF51 - bool "96Boards Carbon (nRF51)" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/96b_carbon_nrf51/Kconfig.defconfig b/boards/arm/96b_carbon_nrf51/Kconfig.defconfig deleted file mode 100644 index 87875314cd36d5..00000000000000 --- a/boards/arm/96b_carbon_nrf51/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# 96Boards Carbon nRF51 board default configuration - -# Copyright (c) 2016, 2017 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_CARBON_NRF51 - -config BOARD - default "96b_carbon_nrf51" - -config BT_CTLR - default BT - -endif # BOARD_96B_CARBON_NRF51 diff --git a/boards/arm/96b_carbon_nrf51/doc/index.rst b/boards/arm/96b_carbon_nrf51/doc/index.rst deleted file mode 100644 index 5a17733d35ff89..00000000000000 --- a/boards/arm/96b_carbon_nrf51/doc/index.rst +++ /dev/null @@ -1,171 +0,0 @@ -.. _96b_carbon_nrf51_board: - -96Boards Carbon nRF51 -##################### - -Overview -******** - -This is the secondary nRF51822 chip on the 96Boards Carbon and provides -Bluetooth functionality to the main STM32F401RET chip via SPI. - -.. note:: - - If you're looking to reprogram the main STMicro part, see - :ref:`96b_carbon_board`. Users should not use this configuration - unless they want to reprogram the secondary chip which provides - Bluetooth connectivity. - - -Hardware -******** - -The 96Boards Carbon nRF51 has two external oscillators. The frequency -of the slow clock is 32.768 kHz. The frequency of the main clock is 16 -MHz. - -See :ref:`96b_carbon_board` for other general information about the -board; that configuration is for the same physical board, just a -different chip. - -Supported Features -================== - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPIS | on-chip | SPI slave | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_carbon_nrf51/96b_carbon_nrf51_defconfig`` - -Connections and IOs -=================== - -SPI ---- - -96Boards Carbon nRF51 has one SPI, which for providing Bluetooth -communication. The default SPI mapping for Zephyr is: - -- SPI1_NSS : P0.25 -- SPI1_SCK : P0.07 -- SPI1_MISO : P0.30 -- SPI1_MOSI : P0.00 - -The SWD debug pins are broken out to an external header; all other -connected pins are to the main STM32F401RET chip. - -.. _96b_carbon_nrf51_programming: - -Programming and Debugging -************************* - -Flashing -======== - -The 96Boards Carbon nRF51 can be flashed using an external SWD -debugger, via the debug header labeled "BLE" on the board's -silkscreen. The header is not populated; 0.1" male header must be -soldered on first. - -.. figure:: img/96b_carbon_nrf51.jpg - :align: center - :alt: 96Boards Carbon nRF51 Debug - - 96Boards Carbon nRF51 Debug - -The following example assumes a Zephyr binary ``zephyr.elf`` will be -flashed to the board. - -It uses the `Black Magic Debug Probe`_ as an SWD programmer, which can -be connected to the BLE debug header using flying leads and its 20 Pin -JTAG Adapter Board Kit. When plugged into your host PC, the Black -Magic Debug Probe enumerates as a USB serial device as documented on -its `Getting started page`_. - -It also uses the GDB binary provided with the Zephyr SDK, -``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC -ARM Embedded, can be used as well. - -.. code-block:: console - - $ arm-zephyr-eabi-gdb -q zephyr.elf - (gdb) target extended-remote /dev/ttyACM0 - Remote debugging using /dev/ttyACM0 - (gdb) monitor swdp_scan - Target voltage: 3.3V - Available Targets: - No. Att Driver - 1 nRF51 - (gdb) attach 1 - Attaching to Remote target - 0xabcdef12 in ?? () - (gdb) load - -Debugging -========= - -After you've flashed the chip, you can keep debugging using the same -GDB instance. To reattach, just follow the same steps above, but don't -run "load". You can then debug as usual with GDB. In particular, type -"run" at the GDB prompt to restart the program you've flashed. - -As an aid to debugging, this board configuration directs a console -output to a currently unused pin connected to the STM32F401RET. Users -who are experienced in electronics rework can remove a resistor (R22) -on the board and attach a wire to the nRF51822's UART output. - -.. _96b_carbon_nrf51_bluetooth: - -Providing Bluetooth to 96b_carbon -********************************* - -This 96b_carbon_nrf51 Zephyr configuration can be used to provide -Bluetooth functionality from the secondary nRF51822 chip to the -primary STM32F401RE chip on the :ref:`96b_carbon_board`. - -To do this, build the ``samples/bluetooth/hci_spi/`` application -provided with Zephyr with ``BOARD=96b_carbon_nrf51``, then flash it to -the nRF51822 chip using the instructions :ref:`above -<96b_carbon_nrf51_programming>`. (For instructions on how to build a -Zephyr application, see :ref:`build_an_application`.) - -.. warning:: - - Be sure to flash the hci_spi application to the nRF51822 chip and - not to the main STM32F401RET chip. While both chips are supported - by Zephyr, the hci_spi application providing Bluetooth support will - only run on the nRF51822 chip. - -References -********** - -- `Board documentation from 96Boards`_ -- `nRF51822 information from Nordic Semiconductor`_ - -.. _Black Magic Debug Probe: - https://github.com/blacksphere/blackmagic/wiki - -.. _Getting started page: - https://github.com/blacksphere/blackmagic/wiki/Getting-Started - -.. _Board documentation from 96Boards: - http://www.96boards.org/product/carbon/ - -.. _nRF51822 information from Nordic Semiconductor: - https://www.nordicsemi.com/eng/Products/Bluetooth-low-energy/nRF51822 diff --git a/boards/arm/96b_meerkat96/96b_meerkat96.yaml b/boards/arm/96b_meerkat96/96b_meerkat96.yaml deleted file mode 100644 index b06b2ef5268fac..00000000000000 --- a/boards/arm/96b_meerkat96/96b_meerkat96.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2019, Linaro Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: 96b_meerkat96 -name: 96Boards Meerkat96 -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - shell -testing: - ignore_tags: - - net - - bluetooth -vendor: novtech diff --git a/boards/arm/96b_meerkat96/96b_meerkat96_defconfig b/boards/arm/96b_meerkat96/96b_meerkat96_defconfig deleted file mode 100644 index 0bed95b7b32e11..00000000000000 --- a/boards/arm/96b_meerkat96/96b_meerkat96_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2019, Linaro Ltd. -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_96B_MEERKAT96=y - -# enable uart driver -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# pinctrl -CONFIG_PINCTRL=y - -CONFIG_XIP=y diff --git a/boards/arm/96b_meerkat96/Kconfig.board b/boards/arm/96b_meerkat96/Kconfig.board deleted file mode 100644 index 85c6c55a3229f0..00000000000000 --- a/boards/arm/96b_meerkat96/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# 96Boards Meerkat96 board - -# Copyright (c) 2019, Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_MEERKAT96 - bool "96Boards Meerkat96 board" - depends on SOC_SERIES_IMX7_M4 - select SOC_PART_NUMBER_MCIMX7D5EVM10SC diff --git a/boards/arm/96b_meerkat96/Kconfig.defconfig b/boards/arm/96b_meerkat96/Kconfig.defconfig deleted file mode 100644 index 7e758a53fa3460..00000000000000 --- a/boards/arm/96b_meerkat96/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# 96Boards Meerkat96 board - -# Copyright (c) 2019, Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_MEERKAT96 - -config BOARD - default "96b_meerkat96" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_96B_MEERKAT96 diff --git a/boards/arm/96b_meerkat96/doc/index.rst b/boards/arm/96b_meerkat96/doc/index.rst deleted file mode 100644 index d060076842c240..00000000000000 --- a/boards/arm/96b_meerkat96/doc/index.rst +++ /dev/null @@ -1,325 +0,0 @@ -.. _96b_meerkat96: - -96Boards Meerkat96 -################## - -Overview -******** - -96Boards Meerkat96 board is based on NXP i.MX7 Hybrid multi-core processor, -composed of a dual Cortex®-A7 and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - RAM: 512 Mbyte - - Storage: - - - microSD Socket - - Wireless: - - - WiFi: 2.4GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 (BR/EDR) - - USB: - - - Host - 2x type A - - OTG: - 1x type micro-B - - HDMI - - Connectors: - - - 40-Pin Low Speed Header - - 60-Pin High Speed Header - - LEDs: - - - 4x Green user LEDs - - 1x Blue Bluetooth LED - - 1x Yellow WiFi LED - -.. image:: img/96b_meerkat96.jpg - :align: center - :alt: 96Boards Meerkat96 - -More information about the board can be found at the -`96Boards website`_. - -Hardware -******** - -The i.MX7 SoC provides the following hardware capabilities: - -- Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core - -- Memory - - - External DDR memory up to 1 Gbyte - - Internal RAM -> A7: 256KB SRAM - - Internal RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - -- Display - - - RGB 1920x1080x24bpp - - 4-wire Resistive touch - -- Multimedia - - - 1x Camera Parallel Interface - - 1x Analog Audio Line in (Stereo) - - 1x Analog Audio Mic in (Mono) - - 1x Analog Audio Headphone out (Stereo) - -- Connectivity - - - USB 2.0 OTG (High Speed) - - USB 2.0 host (High Speed) - - 10/100 Mbit/s Ethernet PHY - - 4x I2C - - 4x SPI - - 7x UART - - 1x IrDA - - 20x PWM - - Up to 125 GPIO - - 4x Analog Input (12 Bit) - - 2x SDIO/SD/MMC (8 Bit) - - 2x CAN - -More information about the i.MX7 SoC can be found here: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Dual Datasheet`_ -- `i.MX 7 Dual Reference Manual`_ - -Supported Features -================== - -The Zephyr 96b_meerkat96 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_meerkat96/96b_meerkat96_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -96Boards Meerkat96 board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART_1 RXD | UART1_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART_1 TXD | UART1_RXD | UART Console | -+---------------+-----------------+---------------------------+ -| LED_R1 | GPIO1_IO04 | LED0 | -+---------------+-----------------+---------------------------+ -| LED_R2 | GPIO1_IO05 | LED1 | -+---------------+-----------------+---------------------------+ -| LED_R3 | GPIO1_IO06 | LED2 | -+---------------+-----------------+---------------------------+ -| LED_R4 | GPIO1_IO07 | LED3 | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7D SoC has seven UARTs. UART_1 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The 96Boards Meerkat96 board doesn't have QSPI flash for the M4 and it needs -to be started by the A7 core. The A7 core is responsible to load the M4 binary -application into the RAM, put the M4 in reset, set the M4 Program Counter and -Stack Pointer, and get the M4 out of reset. The A7 can perform these steps at -bootloader level or after the Linux system has booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 7 Dual Reference Manual`_ (section 2.1.2 and 2.1.3), and the -`Toradex Wiki`_. - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/96b_meerkat96/96b_meerkat96.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from -A7 using u-boot. - -Copy the compiled zephyr.bin to the first FAT partition of the SD card and -plug into the board. Power it up and stop the u-boot execution. -Set the u-boot environment variables and run the zephyr.bin from the -appropriated memory configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - -Debugging -========= - -96Boards Meerkat96 board can be debugged by connecting an external JLink -JTAG debugger to the J4 debug connector. Then download and install -`J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. - -To run Zephyr Binary using J-Link create the following script in order to -get the Program Counter and Stack Pointer from zephyr.bin. - -get-pc-sp.sh: -.. code-block:: console - - #!/bin/sh - - firmware=$1 - - pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') - sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') - - echo pc=$pc - echo sp=$sp - - -Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` -.. code-block:: console - - pc=00900f01 - sp=00905020 - -Plug in the J-Link into the board and PC and run the J-Link command line tool: - -.. code-block:: console - - /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript - -The following steps are necessary to run the zephyr.bin: - -1. Put the M4 core in reset -2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) -3. Set PC (Program Counter) -4. Set SP (Stack Pointer) -5. Get the M4 core out of reset - -Issue the following commands inside J-Link commander: - -.. code-block:: console - - w4 0x3039000C 0xAC - loadfile zephyr.bin,0x00900000 - w4 0x00180000 00900f01 - w4 0x00180004 00905020 - w4 0x3039000C 0xAA - -With these mechanisms, applications for the ``96b_meerkat96`` board -configuration can be built and debugged in the usual way (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _96Boards website: - https://www.96boards.org/product/imx7-96/ - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Dual Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf - -.. _i.MX 7 Dual Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7DRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/96b_neonkey/Kconfig.board b/boards/arm/96b_neonkey/Kconfig.board deleted file mode 100644 index 2246b448ec9ac8..00000000000000 --- a/boards/arm/96b_neonkey/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards Neonkey Board Configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_NEONKEY - bool "96Boards Neonkey" - depends on SOC_STM32F411XE diff --git a/boards/arm/96b_neonkey/Kconfig.defconfig b/boards/arm/96b_neonkey/Kconfig.defconfig deleted file mode 100644 index 54371886f73618..00000000000000 --- a/boards/arm/96b_neonkey/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# 96Boards Neonkey Board Configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_NEONKEY - -config BOARD - default "96b_neonkey" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_96B_NEONKEY diff --git a/boards/arm/96b_neonkey/doc/index.rst b/boards/arm/96b_neonkey/doc/index.rst deleted file mode 100644 index 8f0311259e1d89..00000000000000 --- a/boards/arm/96b_neonkey/doc/index.rst +++ /dev/null @@ -1,233 +0,0 @@ -.. _96b_neonkey: - -96Boards Neonkey -################ - -Overview -******** - -96Boards Neonkey board is based on the STMicroelectronics STM32F411CE -Cortex M4 CPU. - -.. figure:: img/96b_neonkey.jpg - :align: center - :alt: 96Boards Neonkey - - 96Boards Neonkey - -This board acts as a sensor hub platform for all 96Boards compliant -family products. It can also be used as a standalone board. - -Hardware -******** - -96Boards Neonkey provides the following hardware components: - -- STM32F411CE in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 84 MHz max CPU frequency -- 1.8V work voltage -- 512 KB Flash -- 128 KB SRAM -- On board sensors: - - - Temperature/Humidity: SI7034-A10 - - Pressure: BMP280 - - ALS/Proximity: RPR-0521RS - - Geomagnetic: BMM150 - - Accelerometer/Gyroscope: BMI160 - - AMR Hall sensor: MRMS501A - - Microphone: SPK0415HM4H-B - -- 4 User LEDs -- 15 General purpose LEDs -- GPIO with external interrupt capability -- I2C (3) -- SPI (1) -- I2S (1) - -Supported Features -================== - -The Zephyr 96b_neonkey board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -More details about the board can be found at `96Boards website`_. - -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_neonkey/96b_neonkey_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PB12 -- LED2 / User2 LED = PB13 -- LED3 / User3 LED = PB14 -- LED4 / User4 LED = PB15 - -Push buttons ------------- - -- BUTTON = RST (SW1) -- BUTTON = USR (SW2) - -System Clock -============ - -96Boards Neonkey can be driven by an internal oscillator as well as the main -PLL clock. By default System clock is sourced by PLL clock at 84MHz, driven -by internal oscillator. - -Serial Port -=========== - -On 96Boards Neonkey Zephyr console output is assigned to USART1. -Default settings are 115200 8N1. - -I2C ---- - -96Boards Neonkey board has up to 3 I2Cs. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB3 -- I2C3_SCL : PA8 -- I2C3_SCL : PB4 - -SPI ---- - -96Boards Neonkey board has one SPI. The default SPI mapping for Zephyr is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 - -Programming and Debugging -************************* - -Building -======== - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_neonkey - :goals: build - -Flashing -======== - -96Boards Neonkey can be flashed by two methods, one using the ROM -bootloader and another using the SWD debug port (which requires additional -hardware). - -Using ROM bootloader: ---------------------- - -ROM bootloader can be triggered by the following pattern: - -1. Connect BOOT0 to VDD (link JTAG pins 1 and 5 on P4 header) -2. Press and hold the USR button -3. Press and release the RST button - -More detailed information on activating the ROM bootloader can be found in -Chapter 29 of Application note `AN2606`_. The ROM bootloader supports flashing -via UART, I2C and SPI protocols. - -For flashing, `stm32flash`_ command line utility can be used. The following -command will flash the ``zephyr.bin`` binary to the Neonkey board using UART -and starts its execution: - -.. code-block:: console - - $ stm32flash -w zephyr.bin -v -g 0x08000000 /dev/ttyS0 - -.. note:: - The above command assumes that Neonkey board is connected to - serial port ``/dev/ttyS0``. - -Using SWD debugger: -------------------- - -For flashing via SWD debug port, 0.1" male header must be soldered at P4 -header available at the bottom of the board, near RST button. - -Use the `Black Magic Debug Probe`_ as an SWD programmer, which can -be connected to the P4 header using its flying leads and its 20 Pin -JTAG Adapter Board Kit. When plugged into your host PC, the Black -Magic Debug Probe enumerates as a USB serial device as documented on -its `Getting started page`_. - -It also uses the GDB binary provided with the Zephyr SDK, -``arm-zephyr-eabi-gdb``. Other GDB binaries, such as the GDB from GCC -ARM Embedded, can be used as well. - -.. code-block:: console - - $ arm-zephyr-eabi-gdb -q zephyr.elf - (gdb) target extended-remote /dev/ttyACM0 - Remote debugging using /dev/ttyACM0 - (gdb) monitor swdp_scan - Target voltage: 1.8V - Available Targets: - No. Att Driver - 1 STM32F4xx - (gdb) attach 1 - Attaching to Remote target - 0x080005d0 in ?? () - (gdb) load - -Debugging -========= - -After flashing 96Boards Neonkey, it can be debugged using the same -GDB instance. To reattach, just follow the same steps above, till -"attach 1". You can then debug as usual with GDB. In particular, type -"run" at the GDB prompt to restart the program you've flashed. - -References -********** - -.. _96Boards website: - https://www.96boards.org/product/neonkey/ - -.. _AN2606: - https://www.st.com/resource/en/application_note/cd00167594.pdf - -.. _stm32flash: - https://sourceforge.net/p/stm32flash/wiki/Home/ - -.. _Black Magic Debug Probe: - https://github.com/blacksphere/blackmagic/wiki - -.. _Getting started page: - https://github.com/blacksphere/blackmagic/wiki/Getting-Started diff --git a/boards/arm/96b_nitrogen/Kconfig b/boards/arm/96b_nitrogen/Kconfig deleted file mode 100644 index acaec810c794da..00000000000000 --- a/boards/arm/96b_nitrogen/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards NITROGEN board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_NITROGEN - -endif # BOARD_96B_NITROGEN diff --git a/boards/arm/96b_nitrogen/Kconfig.board b/boards/arm/96b_nitrogen/Kconfig.board deleted file mode 100644 index a771ff27019871..00000000000000 --- a/boards/arm/96b_nitrogen/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards NITROGEN board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_NITROGEN - bool "96Boards Nitrogen" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/96b_nitrogen/Kconfig.defconfig b/boards/arm/96b_nitrogen/Kconfig.defconfig deleted file mode 100644 index 00ff29cb2bc461..00000000000000 --- a/boards/arm/96b_nitrogen/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# 96Boards NITROGEN board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_NITROGEN - -config BOARD - default "96b_nitrogen" - -config BT_CTLR - default BT - -endif # BOARD_96B_NITROGEN diff --git a/boards/arm/96b_nitrogen/doc/index.rst b/boards/arm/96b_nitrogen/doc/index.rst deleted file mode 100644 index ea971f093a8952..00000000000000 --- a/boards/arm/96b_nitrogen/doc/index.rst +++ /dev/null @@ -1,330 +0,0 @@ -.. _96b_nitrogen_board: - -96Boards Nitrogen -################# - -Overview -******** - -The 96Boards Nitrogen hardware provides support for the Nordic Semiconductor -nRF52832 ARM Cortex-M4F CPU. - -.. figure:: img/96b_nitrogen.jpg - :align: center - :alt: 96Boards Nitrogen - - 96Boards Nitrogen - -More information about the board can be found at the `seeed BLE Nitrogen`_ -website. The `Nordic Semiconductor Infocenter`_ contains the processor's -information and the datasheet. - -Hardware -******** - -96Boards Nitrogen provides the following hardware components: - -- nRF52832 microcontroller with 512kB Flash, 64kB RAM -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Bluetooth LE -- NFC -- LPC11U35 on board SWD debugger - - - SWD debugger firmware - - USB to UART - - Drag and Drop firmware upgrade - -- 7 LEDs - - - USR1, BT, PWR, CDC, DAP, MSD, Battery charge - -- SWD debug connectors - - - nRF52832 SWD connector - - nRF52832 Uart connector - -- On board chip antenna -- 1.8V work voltage -- 2x20pin 2.0mm pitch Low speed connector - -Supported Features -================== - -The Zephyr 96b_nitrogen board configuration supports the following hardware -features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vectored interrupt controller | -+-----------+------------+--------------------------------------+ -| RTC | on-chip | system clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+--------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+--------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+--------------------------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+--------------------------------------+ -| RTT | on-chip | console | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ for a complete list of nRF52-based -board hardware features. - -The default configuration can be found in the defconfig file: - - ``boards/arm/96b_nitrogen/96b_nitrogen_defconfig`` - -Pin Mapping -=========== - -LED ---- - -- LED1 / User LED (green) = P0.29 -- LED2 / BT LED (blue) = P0.28 - -Push buttons ------------- - -- BUTTON = SW1 = P0.27 - -External Connectors -------------------- - -Low Speed Header - -+--------+-------------+----------------------+ -| PIN # | Signal Name | nRF52832 Functions | -+========+=============+======================+ -| 1 | GND | GND | -+--------+-------------+----------------------+ -| 3 | UART CTS | P.014 / TRACEDATA[3] | -+--------+-------------+----------------------+ -| 5 | UART TX | P0.13 | -+--------+-------------+----------------------+ -| 7 | UART RX | P0.15 / TRACEDATA[2] | -+--------+-------------+----------------------+ -| 9 | UART RTS | P0.12 | -+--------+-------------+----------------------+ -| 11 | UART TX | P0.13 | -+--------+-------------+----------------------+ -| 13 | UART RX | P0.15 / TRACEDATA[2] | -+--------+-------------+----------------------+ -| 15 | P0.22 | P0.22 | -+--------+-------------+----------------------+ -| 17 | P0.20 | P0.20 | -+--------+-------------+----------------------+ -| 19 | N/A | N/A | -+--------+-------------+----------------------+ -| 21 | N/A | N/A | -+--------+-------------+----------------------+ -| 23 | P0.02 | P0.02 | -+--------+-------------+----------------------+ -| 25 | P0.04 | P0.04 | -+--------+-------------+----------------------+ -| 27 | P0.06 | P0.06 | -+--------+-------------+----------------------+ -| 29 | P0.08 | P0.08 | -+--------+-------------+----------------------+ -| 31 | P0.16 | P0.16 | -+--------+-------------+----------------------+ -| 33 | P0.18 | P0.18 | -+--------+-------------+----------------------+ -| 35 | VCC | | -+--------+-------------+----------------------+ -| 37 | USB5V | | -+--------+-------------+----------------------+ -| 39 | GND | GND | -+--------+-------------+----------------------+ - -+--------+-------------+----------------------+ -| PIN # | Signal Name | nRF52832 Functions | -+========+=============+======================+ -| 2 | GND | GND | -+--------+-------------+----------------------+ -| 4 | PWR BTN | | -+--------+-------------+----------------------+ -| 6 | RST BTN | P0.21 / RESET | -+--------+-------------+----------------------+ -| 8 | P0.26 | P0.26 | -+--------+-------------+----------------------+ -| 10 | P0.25 | P0.25 | -+--------+-------------+----------------------+ -| 12 | P0.24 | P0.24 | -+--------+-------------+----------------------+ -| 14 | P0.23 | P0.23 | -+--------+-------------+----------------------+ -| 16 | N/A | N/A | -+--------+-------------+----------------------+ -| 18 | N/A | PC7 | -+--------+-------------+----------------------+ -| 20 | N/A | PC9 | -+--------+-------------+----------------------+ -| 22 | N/A | PB8 | -+--------+-------------+----------------------+ -| 24 | P0.03 | P0.03 | -+--------+-------------+----------------------+ -| 26 | P0.05 | P0.05 | -+--------+-------------+----------------------+ -| 28 | P0.07 | P0.07 | -+--------+-------------+----------------------+ -| 30 | P0.11 | P0.11 | -+--------+-------------+----------------------+ -| 32 | P0.17 | P0.17 | -+--------+-------------+----------------------+ -| 34 | P0.19 | P0.19 | -+--------+-------------+----------------------+ -| 36 | NC | | -+--------+-------------+----------------------+ -| 38 | NC | | -+--------+-------------+----------------------+ -| 40 | GND | GND | -+--------+-------------+----------------------+ - -More detailed information about the connectors can be found in -`96Boards IE Specification`_. - -System Clock -============ - -nRF52 has two external oscillators. The frequency of the slow clock is -32.768 kHz. The frequency of the main clock is 32 MHz. - -Serial Port ------------ - -96Boards Nitrogen has one UART, which is used as Zephyr console. -Default settings is 115200 8N1. - -I2C ---- - -96Boards Nitrogen has one I2C. The default I2C mapping for Zephyr is: - -- I2C0_SCL : P0.22 -- I2C0_SDA : P0.20 - -SPI ---- - -96Boards Nitrogen has one SPI. The default SPI mapping for Zephyr is: - -- SPI0_NSS : P0.24 -- SPI0_SCK : P0.26 -- SPI0_MISO : P0.25 -- SPI0_MOSI : P0.23 - -Flashing Zephyr onto 96Boards Nitrogen -************************************** - -The 96Boards Nitrogen board can be flashed via the `CMSIS DAP`_ interface, -which is provided by the micro USB interface to the LPC11U35 chip. - -Using the CMSIS-DAP interface, the board can be flashed via the USB storage -interface (drag-and-drop) and also via `pyOCD`_. - -To use ``pyOCD``, install the :ref:`pyocd-debug-host-tools` and make sure they -are in your search path. - -Common Errors -============= - -No connected boards -------------------- - -If you don't use sudo when invoking pyocd-flashtool, you might get any of the -following errors: - -.. code-block:: console - - No available boards are connected - -.. code-block:: console - - No connected boards - -.. code-block:: console - - Error: There is no board connected. - -To fix the permission issue, simply add the following udev rule for the -NXP LPC1768 interface: - -.. code-block:: console - - $ echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules - -Finally, unplug and plug the board again. - -ValueError: The device has no langid ------------------------------------- - -As described by `pyOCD issue 259`_, you might get the -:code:`ValueError: The device has no langid` error when not running -pyOCD as root (e.g. sudo). - -To fix the above error, add the udev rule shown in the previous section -and install a more recent version of pyOCD. - -Flashing an Application to 96Boards Nitrogen -============================================ - -Here is an example for the :ref:`hello_world` application. This -requires installing the :ref:`pyocd-debug-host-tools`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_nitrogen - :goals: build flash - -Run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board 96Boards Nitrogen -can be found. For example, under Linux, :code:`/dev/ttyACM0`. -The ``-b`` option sets baud rate ignoring the value from config. - -Press the Reset button and you should see the following message in your -terminal: - -.. code-block:: console - - Hello World! arm - -Debugging with GDB -================== - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. This also requires pyOCD. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_nitrogen - :maybe-skip-config: - :goals: debug - -.. _pyOCD: - https://github.com/mbedmicro/pyOCD - -.. _CMSIS DAP: - https://developer.mbed.org/handbook/CMSIS-DAP - -.. _Nordic Semiconductor Infocenter: - http://infocenter.nordicsemi.com/ - -.. _seeed BLE Nitrogen: - http://wiki.seeed.cc/BLE_Nitrogen/ - -.. _pyOCD issue 259: - https://github.com/mbedmicro/pyOCD/issues/259 - -.. _96Boards IE Specification: - https://linaro.co/ie-specification diff --git a/boards/arm/96b_stm32_sensor_mez/Kconfig.board b/boards/arm/96b_stm32_sensor_mez/Kconfig.board deleted file mode 100644 index 3d17d091ae4511..00000000000000 --- a/boards/arm/96b_stm32_sensor_mez/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96Boards STM32 Sensor Mezzanine board configuration - -# Copyright (c) 2018 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_STM32_SENSOR_MEZ - bool "96Boards STM32 Sensor Mezzanine Board" - depends on SOC_STM32F446XX diff --git a/boards/arm/96b_stm32_sensor_mez/Kconfig.defconfig b/boards/arm/96b_stm32_sensor_mez/Kconfig.defconfig deleted file mode 100644 index bfe0f730222ec6..00000000000000 --- a/boards/arm/96b_stm32_sensor_mez/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# 96Boards STM32 Sensor Mezzanine board configuration - -# Copyright (c) 2018 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_STM32_SENSOR_MEZ - -config BOARD - default "96b_stm32_sensor_mez" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_96B_STM32_SENSOR_MEZ diff --git a/boards/arm/96b_stm32_sensor_mez/doc/index.rst b/boards/arm/96b_stm32_sensor_mez/doc/index.rst deleted file mode 100644 index 95d11d2bacc8d7..00000000000000 --- a/boards/arm/96b_stm32_sensor_mez/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _96b_stm32_sensor_mez: - -96Boards STM32 Sensor Mezzanine -############################### - -Overview -******** - -96Boards STM32 Sensor Mezzanine is based on the ST Microelectronics -STM32F446VE Cortex M4 CPU. - -This board acts as a mezzanine platform for all 96Boards CE compliant -boards. It can also be used as a standalone board. - -.. figure:: img/96b_stm32_sensor_mez.jpg - :align: center - :alt: 96Boards STM32 Sensor Mezzanine - - 96Boards STM32 Sensor Mezzanine - -Hardware -******** - -96Boards STM32 Sensor Mezzanine provides the following hardware components: - -- STM32F446VE in LQFP100 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 180 MHz max CPU frequency -- 1.8V work voltage -- 512 KB Flash -- 128 KB SRAM -- On board sensors: - - - Temperature/Pressure: STMicro LPS22HB - - Accelerometer/Gyroscope: STMicro LSM6DS3H - - Magnetometer: STMicro LIS3MDL - - Microphone: STMicro MP34DT01 - -- 3User LEDs -- GPIO with external interrupt capability -- UART -- I2C (2) -- SPI (3) -- I2S (1) - -Supported Features -================== - -The Zephyr 96b_stm32_sensor_mez board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ - -The default board configuration can be found in the defconfig file: - - ``boards/arm/96b_stm32_sensor_mez/96b_stm32_sensor_mez_defconfig`` - -Connections and IOs -=================== - -LED ---- - -- LED1 / User1 LED = PD10 -- LED2 / User2 LED = PD11 -- LED3 / User3 LED = PD12 - -Push buttons ------------- - -- BUTTON = RST (BT1) -- BUTTON = USR (BT2) - -System Clock -============ - -96Boards STM32 Sensor Mezzanine can be driven by an internal oscillator as -well as the main PLL clock. In default board configuration, the 16MHz external -oscillator is used to drive the main PLL clock to generate a System Clock -(SYSCLK) at 84MHz. On the bus side, AHB/APB2 clocks runs at 84MHz, while APB1 -clock runs at 42MHz. - -Serial Port -=========== - -On 96Boards STM32 Sensor Mezzanine, Zephyr console output is assigned to UART4 -exposed via on-board Micro USB connector. Default settings are 115200 8N1. - -The default USART mappings for the remaining ones are: - -- USART1: Connected to AP via UART0 on the 96Boards Low-Speed Header. - - TX: PA9 - - RX: PA10 - -- USART2: Connected to D0(RX) and D1(TX) on the Arduino Header. - - TX: PD5 - - RX: PD6 - -- USART3: Broken out to Grove connector J10. - - TX: PD8 - - RX: PD9 - -I2C ---- - -96Boards STM32 Sensor Mezzanine board has up to 3 I2Cs. The default I2C -mapping is: - -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PC12 - -I2C2 goes to the Groove connectors and can be used to attach external sensors. - -SPI ---- -96Boards STM32 Sensor Mezzanine board has 3 SPIs. SPI1 is used in slave mode -as the communication bus with the AP. SPI2 is used in master mode to control -the LSM6DS3H sensor. SPI4 is broken out to Grove Connector J5. -The default SPI mapping is: - -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB9 -- SPI2_SCK : PD3 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- SPI4_NSS : PE11 -- SPI4_SCK : PE12 -- SPI4_MISO : PE13 -- SPI4_MOSI : PE14 - -PWM ---- -96Boards STM32 Sensor Mezzanine board exposes 6 PWM channels on the Arduino -connector. The default PWM mapping is: - -- PWM3_CH1 : PB4 : D9 -- PWM3_CH3 : PC8 : D3 -- PWM4_CH3 : PD14 : D6 -- PWM4_CH4 : PD15 : D5 -- PWM9_CH1 : PE5 : D12 -- PWM9_CH2 : PE6 : D11 - -I2S ---- - -96Boards STM32 Sensor Mezzanine board exposes 1 I2S port which is connected -to the on-board ST MP34DT01 DMIC. The default I2S mapping is: - -- I2S2_SD : PC1 -- I2S2_CK : PC7 - -Programming and Debugging -************************* - -Building -======== - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_stm32_sensor_mez - :goals: build - -Flashing -======== - -96Boards STM32 Sensor Mezzanine board includes an ST-LINK/V2-1 embedded -debug tool interface. This interface is supported by the openocd version -included in the Zephyr SDK. - -Flashing an application to 96Boards STM32 Sensor Mezzanine ----------------------------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your 96Boards STM32 Sensor Mezzanine -board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_stm32_sensor_mez - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! 96b_stm32_sensor_mez - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: 96b_stm32_sensor_mez - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _96Boards STM32 Sensor Mezzanine website: - https://www.96boards.org/documentation/mezzanine/stm32/ - -.. _STM32F446VE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f446ve.html - -.. _STM32F446 reference manual: - https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/96b_wistrio/Kconfig.board b/boards/arm/96b_wistrio/Kconfig.board deleted file mode 100644 index ac527a671b7d4e..00000000000000 --- a/boards/arm/96b_wistrio/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# 96boards WisTrio board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_96B_WISTRIO - bool "96boards WisTrio Development Board" - depends on SOC_STM32L151XBA diff --git a/boards/arm/96b_wistrio/Kconfig.defconfig b/boards/arm/96b_wistrio/Kconfig.defconfig deleted file mode 100644 index 0bb9b83220db73..00000000000000 --- a/boards/arm/96b_wistrio/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# 96boards WisTrio board configuration - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_96B_WISTRIO - -config BOARD - default "96b_wistrio" - -config REGULATOR - default y if LORA - -endif # BOARD_96B_WISTRIO diff --git a/boards/arm/acn52832/Kconfig.board b/boards/arm/acn52832/Kconfig.board deleted file mode 100644 index 6e19e79560ab37..00000000000000 --- a/boards/arm/acn52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# aconno acn52832 board configuration - -# Copyright (c) 2023 Sven Herrmann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ACN52832 - bool "aconno ACN52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/acn52832/Kconfig.defconfig b/boards/arm/acn52832/Kconfig.defconfig deleted file mode 100644 index e389aadf6e7966..00000000000000 --- a/boards/arm/acn52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# aconno acn52832 board configuration - -# Copyright (c) 2023 Sven Herrmann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACN52832 - -config BOARD - default "acn52832" - -config BT_CTLR - default BT - -endif # BOARD_ACN52832 diff --git a/boards/arm/acn52832/acn52832_defconfig b/boards/arm/acn52832/acn52832_defconfig deleted file mode 100644 index d35096cdd6eb50..00000000000000 --- a/boards/arm/acn52832/acn52832_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_ACN52832=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/CMakeLists.txt b/boards/arm/actinius_icarus/CMakeLists.txt deleted file mode 100644 index a747a3fdffa5b6..00000000000000 --- a/boards/arm/actinius_icarus/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2019-2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus/Kconfig.board b/boards/arm/actinius_icarus/Kconfig.board deleted file mode 100644 index bdf4d8e2c3661a..00000000000000 --- a/boards/arm/actinius_icarus/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus board configuration - -# Copyright (c) 2019 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS - bool "Actinius Icarus" - -config BOARD_ACTINIUS_ICARUS_NS - bool "Actinius Icarus Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus/Kconfig.defconfig b/boards/arm/actinius_icarus/Kconfig.defconfig deleted file mode 100644 index 6994aac280d67e..00000000000000 --- a/boards/arm/actinius_icarus/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus board configuration - -# Copyright (c) 2019 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS || BOARD_ACTINIUS_ICARUS_NS - -config BOARD - default "actinius_icarus" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_NS - -endif # BOARD_ACTINIUS_ICARUS || BOARD_ACTINIUS_ICARUS_NS diff --git a/boards/arm/actinius_icarus/actinius_icarus.yaml b/boards/arm/actinius_icarus/actinius_icarus.yaml deleted file mode 100644 index d547560af6f195..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: actinius_icarus -name: Actinius Icarus -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - feather_serial - - feather_i2c - - feather_spi - - arduino_i2c - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus/actinius_icarus_1_4_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_1_4_0.overlay deleted file mode 100644 index 07190f7553f34a..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_1_4_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_2_0_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_2_0_0.overlay deleted file mode 100644 index 79e7c3ff28d99f..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_2_0_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_defconfig b/boards/arm/actinius_icarus/actinius_icarus_defconfig deleted file mode 100644 index 58d15739a954cf..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns.yaml b/boards/arm/actinius_icarus/actinius_icarus_ns.yaml deleted file mode 100644 index 7fe1ea2ef47acb..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: actinius_icarus_ns -name: Actinius Icarus Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - feather_serial - - feather_i2c - - feather_spi - - arduino_i2c - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns_1_4_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_ns_1_4_0.overlay deleted file mode 100644 index 07190f7553f34a..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns_1_4_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_1_4_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns_2_0_0.overlay b/boards/arm/actinius_icarus/actinius_icarus_ns_2_0_0.overlay deleted file mode 100644 index 79e7c3ff28d99f..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns_2_0_0.overlay +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2022 Actinius - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include "actinius_icarus_common_2_0_0.dtsi" diff --git a/boards/arm/actinius_icarus/actinius_icarus_ns_defconfig b/boards/arm/actinius_icarus/actinius_icarus_ns_defconfig deleted file mode 100644 index e2e6e11584be8d..00000000000000 --- a/boards/arm/actinius_icarus/actinius_icarus_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus/doc/index.rst b/boards/arm/actinius_icarus/doc/index.rst deleted file mode 100644 index 7f040e6630ec8a..00000000000000 --- a/boards/arm/actinius_icarus/doc/index.rst +++ /dev/null @@ -1,238 +0,0 @@ -.. _actinius_icarus: - -Actinius Icarus -############### - -Overview -******** - -.. figure:: img/Icarus_front.jpg - :align: center - :alt: Icarus IoT Dev Board - - Icarus IoT Dev Board (nRF9160 Feather) - -The Icarus is a cost-effective cellular IoT board in Adafruit's Feather/FeatherWing -form factor. It is built around Nordic Semi's nRF9160 modem and combines -LTE-M, NB-IoT, GPS, accelerometer, USB, LiPo charger as well as -an eSIM and a nano SIM connector. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus Product Website`_. - -.. figure:: img/Icarus_pinouts.jpg - :align: center - :alt: Icarus IoT Dev Board w/ Pinouts - - Icarus IoT Dev Board w/ Pinouts - -Pin description -=============== - -External Pins available to user: - -+------------+----------------------------+----------------------------------------------+------------------+ -| Icarus pin | Function | Description | Device-tree node | -+============+============================+==============================================+==================+ -| RST | Reset | Active low reset with internal pullup | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| 3.3V | Power output | Main 3.3 V supply | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| NC | - | Not connected | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| GND | Power output | Ground | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| 14 / A1 | GPIO / Analog in | nRF9160 P0.14 / AIN1 | gpio0 / adc_1 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 15 / A2 | GPIO / Analog in | nRF9160 P0.15 / AIN2 | gpio0 / adc_2 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 16 / A3 | GPIO / Analog in | nRF9160 P0.16 / AIN3 | gpio0 / adc_3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 17 / A4 | GPIO / Analog in | nRF9160 P0.17 / AIN4 | gpio0 / adc_4 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 18 / A5 | GPIO / Analog in | nRF9160 P0.18 / AIN5 | gpio0 / adc_5 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 19 / A6 | GPIO / Analog in | nRF9160 P0.19 / AIN6 | gpio0 / adc_6 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 20 / SCK | GPIO / SPI pin | nRF9160 P0.20 / SPI SCK pin | gpio0 / spi3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 21 / MOSI | GPIO / SPI pin | nRF9160 P0.21 / SPI MOSI pin | gpio0 / spi3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 22 / MISO | GPIO / SPI pin | nRF9160 P0.22 / SPI MISO pin | gpio0 / spi3 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 23 / RX | GPIO / UART pin | nRF9160 P0.23 / UART RX pin | gpio0 / uart1 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 24 / TX | GPIO / UART pin | nRF9160 P0.24 / UART TX pin | gpio0 / uart1 | -+------------+----------------------------+----------------------------------------------+------------------+ -| VIN | Power input | Voltage input (maximum 10.2 V) | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| VBAT | Power input | Battery voltage input | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| EN | Power enable | Power enable pin (pull low to disable power) | - | -+------------+----------------------------+----------------------------------------------+------------------+ -| USB | Power input | USB voltage input | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 4 | GPIO | nRF9160 P0.04 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 3 | GPIO | nRF9160 P0.03 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 2 | GPIO | nRF9160 P0.02 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 1 | GPIO | nRF9160 P0.01 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 0 | GPIO | nRF9160 P0.00 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 30 | GPIO | nRF9160 P0.30 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| 31 | GPIO | nRF9160 P0.31 | gpio0 | -+------------+----------------------------+----------------------------------------------+------------------+ -| SCL | GPIO / I2C pin | nRF9160 P0.26 / I2C SCL pin | gpio0 / i2c2 | -+------------+----------------------------+----------------------------------------------+------------------+ -| SDA | GPIO / I2C pin | nRF9160 P0.27 / I2C SDA pin | gpio0 / i2c2 | -+------------+----------------------------+----------------------------------------------+------------------+ - -nRF9160 pins connected internally: - -+--------------+---------------------------------------+----------------------+ -| nRF9160 pin | Function | Device-tree node | -+==============+=======================================+======================+ -| P0.05 | User button | button0 | -+--------------+---------------------------------------+----------------------+ -| P0.10 | Red LED | led0 / pwm-led0 | -+--------------+---------------------------------------+----------------------+ -| P0.11 | Green LED | led1 / pwm-led1 | -+--------------+---------------------------------------+----------------------+ -| P0.12 | Blue LED | led2 / pwm-led2 | -+--------------+---------------------------------------+----------------------+ -| P0.28 | Accelerometer Interrupt 1 | lis2dh12-accel | -+--------------+---------------------------------------+----------------------+ -| P0.29 | Accelerometer Interrupt 2 | lis2dh12-accel | -+--------------+---------------------------------------+----------------------+ -| P0.08 | SIM select pin | gpio0 | -+--------------+---------------------------------------+----------------------+ -| P0.13 / AIN0 | Battery voltage measurement | adc_0 | -+--------------+---------------------------------------+----------------------+ -| P0.06 | USB - FTDI serial RX | uart0 | -+--------------+---------------------------------------+----------------------+ -| P0.09 | USB - FTDI serial TX | uart0 | -+--------------+---------------------------------------+----------------------+ -| P0.07 | USB - FTDI serial RTS | uart0 | -| | Charger enable pin (Icarus v2.0) | gpio0 (Icarus v2.0) | -+--------------+---------------------------------------+----------------------+ -| P0.25 | USB - FTDI serial CTS | uart0 | -| | FLASH memory SPI CS pin (Icarus v2.0) | gpio0 (Icarus v2.0) | -+--------------+---------------------------------------+----------------------+ - -Supported Features -================== - -The actinius_icarus board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM Selection -============= - -The SIM choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Charger Enable/Disable -====================== - -Since hardware version 2.0 the charger can be disabled by adjusting the ``charger`` -property of the ``charger_enable`` device tree node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus "Get Started" Guide`_ or the -`Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus Product Website: - https://www.actinius.com/icarus - -.. _Icarus "Get Started" Guide: - https://www.actinius.com/get-started - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/actinius_icarus/revision.cmake b/boards/arm/actinius_icarus/revision.cmake deleted file mode 100644 index d63947b74bf74d..00000000000000 --- a/boards/arm/actinius_icarus/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Actinius -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 2.0.0 - VALID_REVISIONS 1.4.0 2.0.0 -) diff --git a/boards/arm/actinius_icarus_bee/CMakeLists.txt b/boards/arm/actinius_icarus_bee/CMakeLists.txt deleted file mode 100644 index b54029984d15bb..00000000000000 --- a/boards/arm/actinius_icarus_bee/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021-2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus_bee/Kconfig.board b/boards/arm/actinius_icarus_bee/Kconfig.board deleted file mode 100644 index 39081152558f4c..00000000000000 --- a/boards/arm/actinius_icarus_bee/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus Bee board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS_BEE - bool "Actinius Icarus Bee" - -config BOARD_ACTINIUS_ICARUS_BEE_NS - bool "Actinius Icarus Bee Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus_bee/Kconfig.defconfig b/boards/arm/actinius_icarus_bee/Kconfig.defconfig deleted file mode 100644 index 309a45a61d42fa..00000000000000 --- a/boards/arm/actinius_icarus_bee/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus Bee board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS_BEE || BOARD_ACTINIUS_ICARUS_BEE_NS - -config BOARD - default "actinius_icarus_bee" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS_BEE && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_BEE_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_BEE_NS - -endif # BOARD_ACTINIUS_ICARUS_BEE || BOARD_ACTINIUS_ICARUS_BEE_NS diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee.yaml b/boards/arm/actinius_icarus_bee/actinius_icarus_bee.yaml deleted file mode 100644 index 87052c0a1491fa..00000000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: actinius_icarus_bee -name: Actinius Icarus Bee -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_defconfig b/boards/arm/actinius_icarus_bee/actinius_icarus_bee_defconfig deleted file mode 100644 index 64de49c899b0cd..00000000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_BEE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.yaml b/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.yaml deleted file mode 100644 index 6255c80c01037a..00000000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: actinius_icarus_bee_ns -name: Actinius Icarus Bee Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns_defconfig b/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns_defconfig deleted file mode 100644 index 7e0d1c6e2df524..00000000000000 --- a/boards/arm/actinius_icarus_bee/actinius_icarus_bee_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_BEE_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_bee/doc/index.rst b/boards/arm/actinius_icarus_bee/doc/index.rst deleted file mode 100644 index b6d166900aa269..00000000000000 --- a/boards/arm/actinius_icarus_bee/doc/index.rst +++ /dev/null @@ -1,137 +0,0 @@ -.. _actinius_icarus_bee: - -Actinius Icarus Bee -################### - -Overview -******** - -.. figure:: img/icarus-bee.jpg - :align: center - :alt: Icarus Bee - - Icarus Bee (nRF9160 Bee) - -The Icarus Bee is a cellular IoT board in Bee/xBee form factor. -It is built around Nordic Semi's nRF9160 modem and combines -LTE-M, NB-IoT, GPS, accelerometer, SPI Flash, RGB LED, Button, -as well as an eSIM and a nano SIM connector. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/icarus-bee-external-pins.jpg - :align: center - :alt: Icarus Bee w/ Pinouts - - Icarus Bee w/ Pinouts - -.. figure:: img/icarus-bee-peripherals-pins.jpg - :align: center - :alt: Icarus Bee - - Internal Pinouts - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus Bee Product Website`_. - -Supported Features -================== - -The actinius_icarus_bee board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM selection -************* - -The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_bee``. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_bee_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus Bee Product Website`_ or the -`Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus Bee Product Website: - https://www.actinius.com/icarus-bee - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som/CMakeLists.txt b/boards/arm/actinius_icarus_som/CMakeLists.txt deleted file mode 100644 index b54029984d15bb..00000000000000 --- a/boards/arm/actinius_icarus_som/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021-2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus_som/Kconfig.board b/boards/arm/actinius_icarus_som/Kconfig.board deleted file mode 100644 index e661fb2a00bc5c..00000000000000 --- a/boards/arm/actinius_icarus_som/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus SoM board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS_SOM - bool "Actinius Icarus SoM" - -config BOARD_ACTINIUS_ICARUS_SOM_NS - bool "Actinius Icarus SoM Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus_som/Kconfig.defconfig b/boards/arm/actinius_icarus_som/Kconfig.defconfig deleted file mode 100644 index 473acfea29febb..00000000000000 --- a/boards/arm/actinius_icarus_som/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus SoM board configuration - -# Copyright (c) 2021 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS_SOM || BOARD_ACTINIUS_ICARUS_SOM_NS - -config BOARD - default "actinius_icarus_som" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS_SOM && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_SOM_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_SOM_NS - -endif # BOARD_ACTINIUS_ICARUS_SOM || BOARD_ACTINIUS_ICARUS_SOM_NS diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som.yaml b/boards/arm/actinius_icarus_som/actinius_icarus_som.yaml deleted file mode 100644 index db7c14011b5a84..00000000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: actinius_icarus_som -name: Actinius Icarus SoM -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_defconfig b/boards/arm/actinius_icarus_som/actinius_icarus_som_defconfig deleted file mode 100644 index b2bbfdba52d895..00000000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.yaml b/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.yaml deleted file mode 100644 index 6f4d731867d37c..00000000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: actinius_icarus_som_ns -name: Actinius Icarus SoM Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - watchdog - - counter -vendor: actinius diff --git a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns_defconfig b/boards/arm/actinius_icarus_som/actinius_icarus_som_ns_defconfig deleted file mode 100644 index 81712f3aa1fe2a..00000000000000 --- a/boards/arm/actinius_icarus_som/actinius_icarus_som_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som/doc/index.rst b/boards/arm/actinius_icarus_som/doc/index.rst deleted file mode 100644 index 6c22d627e11d0e..00000000000000 --- a/boards/arm/actinius_icarus_som/doc/index.rst +++ /dev/null @@ -1,137 +0,0 @@ -.. _actinius_icarus_som: - -Actinius Icarus SoM -################### - -Overview -******** - -.. figure:: img/icarus-som.jpg - :align: center - :alt: Icarus SoM - - Icarus SoM (nRF9160) - -The Icarus SoM is a coin-sized, easy-to-solder cellular IoT Module -built around Nordic Semi's nRF9160 modem and combines -LTE-M, NB-IoT, GPS, accelerometer as well as an eSIM and option for -an external nano SIM connector. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/icarus-som-external-pins.jpg - :align: center - :alt: Icarus SoM Pins - - Icarus SoM Pins - -.. figure:: img/icarus-som-peripherals-pins.jpg - :align: center - :alt: Icarus SoM - - Internal Pinouts - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_. - -Supported Features -================== - -The actinius_icarus_som board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM selection -************* - -The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som``. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus SoM Product Website`_ or the -`Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus SoM Product Website: - https://www.actinius.com/icarus-som - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/actinius_icarus_som_dk/CMakeLists.txt b/boards/arm/actinius_icarus_som_dk/CMakeLists.txt deleted file mode 100644 index 1fff4c1e76c215..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2022 Actinius -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${ZEPHYR_BASE}/boards/common/actinius actinius_common) diff --git a/boards/arm/actinius_icarus_som_dk/Kconfig.board b/boards/arm/actinius_icarus_som_dk/Kconfig.board deleted file mode 100644 index d3d1bcacfd0f7d..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Actinius Icarus SoM DK board configuration - -# Copyright (c) 2022 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_ACTINIUS_ICARUS_SOM_DK - bool "Actinius Icarus SoM DK" - -config BOARD_ACTINIUS_ICARUS_SOM_DK_NS - bool "Actinius Icarus SoM DK Non-Secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/actinius_icarus_som_dk/Kconfig.defconfig b/boards/arm/actinius_icarus_som_dk/Kconfig.defconfig deleted file mode 100644 index 00024ae99ca7d1..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# Actinius Icarus SoM DK board configuration - -# Copyright (c) 2022 Actinius -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACTINIUS_ICARUS_SOM_DK || BOARD_ACTINIUS_ICARUS_SOM_DK_NS - -config BOARD - default "actinius_icarus_som_dk" - -source "boards/common/actinius/Kconfig" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_ACTINIUS_ICARUS_SOM_DK && TRUSTED_EXECUTION_SECURE - -if BOARD_ACTINIUS_ICARUS_SOM_DK_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_ACTINIUS_ICARUS_SOM_DK_NS - -endif # BOARD_ACTINIUS_ICARUS_SOM_DK || BOARD_ACTINIUS_ICARUS_SOM_DK_NS diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.yaml b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.yaml deleted file mode 100644 index aea5ef27753dc2..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: actinius_icarus_som_dk -name: Actinius Icarus SoM DK -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 256 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_defconfig b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_defconfig deleted file mode 100644 index 2542dbb901e573..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM_DK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.yaml b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.yaml deleted file mode 100644 index 2ecf72e7a574bb..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: actinius_icarus_som_dk_ns -name: Actinius Icarus SoM DK Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - gpio - - i2c - - pwm - - spi - - watchdog - - counter - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi -vendor: actinius diff --git a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns_defconfig b/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns_defconfig deleted file mode 100644 index 212dd785cd2cfd..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/actinius_icarus_som_dk_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_ACTINIUS_ICARUS_SOM_DK_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/actinius_icarus_som_dk/doc/index.rst b/boards/arm/actinius_icarus_som_dk/doc/index.rst deleted file mode 100644 index 94cda9e5c023c4..00000000000000 --- a/boards/arm/actinius_icarus_som_dk/doc/index.rst +++ /dev/null @@ -1,245 +0,0 @@ -.. _actinius_icarus_som_dk: - -Actinius Icarus SoM DK -###################### - -Overview -******** - -.. figure:: img/icarus-som-dk.jpg - :width: 450px - :align: center - :alt: Icarus SoM DK - - Icarus SoM Development Kit (nRF9160) - -The Icarus SoM DK is a single board development kit for -evaluation and development on the Icarus SoM (`Icarus SoM Docs`_). -The Icarus SoM features the nRF9160 SiP from Nordic Semiconductor, -a low-power 3-axis accelerometer and an on-board eSIM. -The development kit provides interfacing to the SoM through USB-C, -a set of user LEDs, a reset and a user button, a battery charging port, -and a external nano SIM connector. -The board is also Arduino Uno Rev3 compatible which makes -using external shields possible. - -The main uController is the Nordic Semiconductor nRF9160, with -ARM Cortex-M33F CPU, ARMv8-M Security Extension and the -following devices (provided directly by Nordic): - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/icarus-som-dk-block-diagram.jpg - :width: 450px - :align: center - :alt: Icarus SoM DK Block Diagram - - Icarus SoM DK Block Diagram - -Hardware -******** - -The detailed information about the on-board hardware can be found at the `Icarus SoM Product Website`_ -and the `Icarus SoM DK Product Website`_. - -Pin description -=============== - -External Pins available to user: - -+----+-------+------------------------------------+------------------+ -| # | Label | Description | Device-tree node | -+====+=======+====================================+==================+ -| 1 | NC | Not Connected | - | -+----+-------+------------------------------------+------------------+ -| 2 | IOREF | I/O reference, connected to 3.3V | - | -+----+-------+------------------------------------+------------------+ -| 3 | RST | Reset of the nRF9160 | - | -+----+-------+------------------------------------+------------------+ -| 4 | 3.3V | 3.3V Power output | - | -+----+-------+------------------------------------+------------------+ -| 5 | 4.4V | Power output between Vbat and 4.4V | - | -+----+-------+------------------------------------+------------------+ -| 6 | GND | Ground pin | - | -+----+-------+------------------------------------+------------------+ -| 7 | GND | Ground pin | - | -+----+-------+------------------------------------+------------------+ -| 8 | VIN | Power input pin (4.35V to 10.5V) | - | -+----+-------+------------------------------------+------------------+ -| 9 | A2 | AIN2 / nRF9160 P0.15 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 10 | A3 | AIN3 / nRF9160 P0.16 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 11 | A4 | AIN4 / nRF9160 P0.17 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 12 | A5 | AIN5 / nRF9160 P0.18 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 13 | A6 | AIN6 / nRF9160 P0.19 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 14 | A7 | AIN7 / nRF9160 P0.20 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 15 | P4 | nRF9160 P0.04 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 16 | P5 | nRF9160 P0.05 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 17 | P2 | nRF9160 P0.02 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 18 | P1 | nRF9160 P0.01 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 19 | P23 | nRF9160 P0.23 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 20 | P0 | nRF9160 P0.00 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 21 | P26 | nRF9160 P0.26 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 22 | P27 | nRF9160 P0.27 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 23 | P30 | nRF9160 P0.30 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 24 | P31 | nRF9160 P0.31 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 25 | P7 | nRF9160 P0.07 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 26 | P13 | nRF9160 P0.13 or NC (Jumper-dependent) | gpio0 | -+----+-------+------------------------------------+------------------+ -| 27 | P14 | nRF9160 P0.14 or NC (Jumper-dependent) | gpio0 | -+----+-------+------------------------------------+------------------+ -| 28 | P3 | nRF9160 P0.03 | gpio0 | -+----+-------+------------------------------------+------------------+ -| 29 | GND | Ground pin | - | -+----+-------+------------------------------------+------------------+ -| 30 | AREF | NC or AIN1 (Jumper-dependent) | gpio0 | -+----+-------+------------------------------------+------------------+ -| 31 | SDA | I2C SDA pin | i2c2 | -+----+-------+------------------------------------+------------------+ -| 32 | SCL | I2C SCL pin | i2c2 | -+----+-------+------------------------------------+------------------+ -| - | TS | Pin for optional battery thermistor| - | -+----+-------+------------------------------------+------------------+ -| - | CHG | Pin for battery charging indication| - | -+----+-------+------------------------------------+------------------+ -| - | CE | Pin for enabling/disabling charging| - | -+----+-------+------------------------------------+------------------+ - - -nRF9160 pins connected internally: - -+--------------+------------------------------+---------------------+ -| nRF9160 pin | Function | Device-tree node | -+==============+==============================+=====================+ -| P0.03 | Blue LED | led0 / pwm-led0 | -+--------------+------------------------------+---------------------+ -| P0.08 | NeoPixel RGB LED | spi1 | -+--------------+------------------------------+---------------------+ -| P0.12 | SIM select pin | gpio0 | -+--------------+------------------------------+---------------------+ -| P0.23 | Connected to the user button | gpio0 / button0 | -+--------------+------------------------------+---------------------+ -| P0.24 | SPI NOR Flash chip select | gpio0 / spi3 | -+--------------+------------------------------+---------------------+ -| P0.28 | Accelerometer Interrupt 2 | lis2dh12-accel | -+--------------+------------------------------+---------------------+ -| P0.29 | Accelerometer Interrupt 1 | lis2dh12-accel | -+--------------+------------------------------+---------------------+ - -Supported Features -================== - -The actinius_icarus_som_dk board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| ACCEL | st | lis2dh | -+-----------+------------+----------------------+ - -SIM selection -************* - -The sim choice (eSIM or nano-SIM) can be configured in Devicetree by adjusting -the ``sim`` property in the ``sim_select`` node. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk``. -2. Build the Non-Secure Zephyr application using ``-DBOARD=actinius_icarus_som_dk_ns``. -3. Merge the two binaries together. - -If you are using Segger Embedded Studio v4.18 or later, the two binaries are built, merged, and -burned automatically, unless you have disabled the feature. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -More information can be found in the `Icarus SoM Product Website`_, -the `Icarus SoM DK Product Website`_ or the `Actinius Documentation Portal`_. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau - -.. _Icarus SoM Product Website: - https://www.actinius.com/icarus-som - -.. _Icarus SoM DK Product Website: - https://www.actinius.com/icarus-som-dk - -.. _Icarus SoM Docs: - https://docs.actinius.com/icarus-som/introduction - -.. _Actinius Documentation Portal: - https://docs.actinius.com diff --git a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.board b/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.board deleted file mode 100644 index 9f33d8c05b71be..00000000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 Basic Proto board configuration - -# Copyright (c) 2018 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO - bool "Adafruit Feather M0 Basic Proto" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.defconfig b/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.defconfig deleted file mode 100644 index 834c8c14cea2c5..00000000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 Basic Proto board configuration - -# Copyright (c) 2018 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_feather_m0_basic_proto" - depends on BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO diff --git a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig b/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig deleted file mode 100644 index 5d8166f71e9f47..00000000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ADAFRUIT_FEATHER_M0_BASIC_PROTO=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/adafruit_feather_m0_basic_proto/doc/index.rst b/boards/arm/adafruit_feather_m0_basic_proto/doc/index.rst deleted file mode 100644 index 4b1af3d8d4935c..00000000000000 --- a/boards/arm/adafruit_feather_m0_basic_proto/doc/index.rst +++ /dev/null @@ -1,167 +0,0 @@ -.. _adafruit_feather_m0_basic_proto: - -Adafruit Feather M0 Basic Proto -############################### - -Overview -******** - -The Adafruit Feather M0 Basic Proto is a thin, light ARM development -board with an onboard battery connector and charger for 3.7 V lithium -polymer batteries, charging status indicator and user LEDs, native USB -connector, 20 I/O pins, and a small prototyping area. - -.. image:: img/adafruit_feather_m0_basic_proto.jpg - :align: center - :alt: Adafruit Feather M0 Basic Proto - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- User LED -- Reset button -- Native USB port - -Supported Features -================== - -The adafruit_feather_m0_basic_proto board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | Systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial port | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface port | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Feather M0 Basic Proto Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -Basic Proto, SERCOM0 is the Zephyr console and is available on pins 0 -(RX) and 1 (TX). - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -Basic Proto, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 -Basic Proto, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and -pin 24 (SCK). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Adafruit Feather M0 Basic Proto ships with a BOSSA compatible -SAM-BA bootloader. The bootloader can be entered by quickly tapping -the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_basic_proto - :goals: build - :compact: - -#. Connect the Adafruit Feather M0 Basic Proto to your host computer - using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_basic_proto - :goals: flash - :compact: - - You should see "Hello World! adafruit_feather_m0_basic_proto" in your terminal. - -References -********** - -.. target-notes:: - -.. _Adafruit Feather M0 Basic Proto Learn site: - https://learn.adafruit.com/adafruit-feather-m0-basic-proto/ - -.. _pinouts: - https://learn.adafruit.com/adafruit-feather-m0-basic-proto/pinouts - -.. _schematic: - https://learn.adafruit.com/adafruit-feather-m0-basic-proto/downloads diff --git a/boards/arm/adafruit_feather_m0_lora/Kconfig.board b/boards/arm/adafruit_feather_m0_lora/Kconfig.board deleted file mode 100644 index 002cf289f7a141..00000000000000 --- a/boards/arm/adafruit_feather_m0_lora/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 LoRa board configuration - -# Copyright (c) 2022 Miguel Dardenne -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_M0_LORA - bool "Adafruit Feather M0 LoRa" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/adafruit_feather_m0_lora/Kconfig.defconfig b/boards/arm/adafruit_feather_m0_lora/Kconfig.defconfig deleted file mode 100644 index 08a3c802d43180..00000000000000 --- a/boards/arm/adafruit_feather_m0_lora/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather M0 LoRa board configuration - -# Copyright (c) 2022 Miguel Dardenne -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_feather_m0_lora" - depends on BOARD_ADAFRUIT_FEATHER_M0_LORA diff --git a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig b/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig deleted file mode 100644 index 20bed381bb900c..00000000000000 --- a/boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ADAFRUIT_FEATHER_M0_LORA=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/adafruit_feather_m0_lora/doc/index.rst b/boards/arm/adafruit_feather_m0_lora/doc/index.rst deleted file mode 100644 index 154feb14539f43..00000000000000 --- a/boards/arm/adafruit_feather_m0_lora/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _adafruit_feather_m0_lora: - -Adafruit Feather M0 LoRa -######################## - -Overview -******** - -The Adafruit Feather M0 Lora is a thin, light ARM development -boards with an onboard battery connector and charger for 3.7 V lithium -polymer batteries, charging status indicator and user LEDs, native USB -connector, 20 I/O pins, and a LoRa radio module from Semtech. - -.. image:: img/adafruit_feather_m0_lora.jpg - :align: center - :alt: Adafruit Feather M0 LoRa - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- User LED -- Reset button -- Native USB port -- SX127x LoRa radio - -Supported Features -================== - -The adafruit_feather_m0_lora board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | Systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial port | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface port | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| RADIO | SPI | LoRa radio | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_feather_m0_lora/adafruit_feather_m0_lora_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Feather M0 with LoRa radio module Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -with LoRa, SERCOM0 is the Zephyr console and is available on pins 0 -(RX) and 1 (TX). - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Adafruit Feather M0 -with LoRa, SERCOM3 is available on pin 20 (SDA) and pin 21 (SCL). - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Adafruit Feather M0 -with LoRa, SERCOM4 is available on pin 22 (MISO), pin 23 (MOSI), and -pin 24 (SCK). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -LoRa Radio -========== -The Semtech SX127x radio chip on the Adafruit Feather M0 with LoRa -is attached to the SPI port (SERCOM4). Depending on the hardware -version, 433MHz or 900MHz is supported. - -Programming and Debugging -************************* - -The Adafruit Feather M0 with LoRa ships with a BOSSA compatible -SAM-BA bootloader. The bootloader can be entered by quickly tapping -the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_lora - :goals: build - :compact: - -#. Connect the Adafruit Feather M0 with LoRa to your host computer - using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_feather_m0_lora - :goals: flash - :compact: - - You should see "Hello World! adafruit_feather_m0_lora" in your terminal. - -References -********** - -.. target-notes:: - -.. _Adafruit Feather M0 with LoRa radio module Learn site: - https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module - -.. _pinouts: - https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/pinouts - -.. _schematic: - https://learn.adafruit.com/adafruit-feather-m0-radio-with-lora-radio-module/downloads diff --git a/boards/arm/adafruit_feather_nrf52840/Kconfig b/boards/arm/adafruit_feather_nrf52840/Kconfig deleted file mode 100644 index 4398595868f90d..00000000000000 --- a/boards/arm/adafruit_feather_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_ADAFRUIT_FEATHER_NRF52840 diff --git a/boards/arm/adafruit_feather_nrf52840/Kconfig.board b/boards/arm/adafruit_feather_nrf52840/Kconfig.board deleted file mode 100644 index 4e37d05303a0c6..00000000000000 --- a/boards/arm/adafruit_feather_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_NRF52840 - bool "Adafruit Feather nRF52840 Express" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig b/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig deleted file mode 100644 index f2d04d6cc48845..00000000000000 --- a/boards/arm/adafruit_feather_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Adafruit Feather nRF52840 Express board configuration - -# Copyright (c) 2020 Tobias Svehagen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_FEATHER_NRF52840 - -config BOARD - default "adafruit_feather_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_ADAFRUIT_FEATHER_NRF52840 diff --git a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840_defconfig b/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840_defconfig deleted file mode 100644 index 74b11931eb86b9..00000000000000 --- a/boards/arm/adafruit_feather_nrf52840/adafruit_feather_nrf52840_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ADAFRUIT_FEATHER_NRF52840=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/adafruit_feather_nrf52840/doc/index.rst b/boards/arm/adafruit_feather_nrf52840/doc/index.rst deleted file mode 100644 index 6d4af8ca296b18..00000000000000 --- a/boards/arm/adafruit_feather_nrf52840/doc/index.rst +++ /dev/null @@ -1,146 +0,0 @@ -.. _adafruit_feather_nrf52840: - -Adafruit Feather nRF52840 Express -################################# - -Overview -******** - -The Adafruit Feather nRF52840 provides support for the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/adafruit_feather_nrf52840.jpg - :align: center - :alt: Adafruit Feather nRF52840 Express - -Hardware -******** - -- nRF52840 ARM Cortex-M4F processor at 64 MHz -- 1 MB flash memory and 256 KB of SRAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- 2 User LEDs -- 1 NeoPixel LED -- Reset button -- SWD connector - -Supported Features -================== - -The Adafruit Feather nRF52840 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `Adafruit Feather nRF52840 Express Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -LED ---- - -* LED0 (red) = P1.15 -* LED1 (blue) = P1.10 - -Push buttons ------------- - -* SWITCH = P1.02 -* RESET = P0.18 - -Programming and Debugging -************************* - -Applications for the ``adafruit_feather_nrf52840`` board configuration -can be built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing -======== - -Flashing Zephyr onto the ``adafruit_feather_nrf52480`` board requires -an external programmer. The programmer is attached to the SWD header. - -Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application. - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_feather_nrf52840 - :goals: build - :compact: - -Flash the image. - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_feather_nrf52840 - :goals: flash - :compact: - -You should see the red LED blink. - -References -********** - -.. target-notes:: - -.. _Adafruit Feather nRF52840 Express Learn site: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/ - -.. _pinouts: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/pinouts - -.. _schematic: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/downloads diff --git a/boards/arm/adafruit_feather_stm32f405/Kconfig.board b/boards/arm/adafruit_feather_stm32f405/Kconfig.board deleted file mode 100644 index 8f563963fee322..00000000000000 --- a/boards/arm/adafruit_feather_stm32f405/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Feather STM32F405 Express board configuration - -# Copyright (c) 2020 Lucian Copeland for Adafruit Industries -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_FEATHER_STM32F405 - bool "Feather STM32F405 Express Board" - depends on SOC_STM32F405XG diff --git a/boards/arm/adafruit_feather_stm32f405/Kconfig.defconfig b/boards/arm/adafruit_feather_stm32f405/Kconfig.defconfig deleted file mode 100644 index 1e7e3593d3412f..00000000000000 --- a/boards/arm/adafruit_feather_stm32f405/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Adafruit Feather STM32F405 Express board configuration - -# Copyright (c) 2020 Lucian Copeland for Adafruit Industries. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_FEATHER_STM32F405 - -config BOARD - default "adafruit_feather_stm32f405" - -endif # BOARD_ADAFRUIT_FEATHER_STM32F405 diff --git a/boards/arm/adafruit_grand_central_m4_express/Kconfig.board b/boards/arm/adafruit_grand_central_m4_express/Kconfig.board deleted file mode 100644 index 4ca7a7126972b4..00000000000000 --- a/boards/arm/adafruit_grand_central_m4_express/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Grand Central M4 Express board configuration - -# Copyright (c) 2023 Lukas Jung -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS - bool "Adafruit Grand Central M4 Express" - depends on SOC_PART_NUMBER_SAMD51P20A diff --git a/boards/arm/adafruit_grand_central_m4_express/Kconfig.defconfig b/boards/arm/adafruit_grand_central_m4_express/Kconfig.defconfig deleted file mode 100644 index 72266e97bac697..00000000000000 --- a/boards/arm/adafruit_grand_central_m4_express/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Grand Central M4 Express board configuration - -# Copyright (c) 2023 Lukas Jung -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_grand_central_m4_express" - depends on BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS diff --git a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig b/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig deleted file mode 100644 index b5bfafe5b18c54..00000000000000 --- a/boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD51=y -CONFIG_SOC_PART_NUMBER_SAMD51P20A=y -CONFIG_BOARD_ADAFRUIT_GRAND_CENTRAL_M4_EXPRESS=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_GPIO=y - -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/adafruit_grand_central_m4_express/doc/index.rst b/boards/arm/adafruit_grand_central_m4_express/doc/index.rst deleted file mode 100644 index a5dba70f617377..00000000000000 --- a/boards/arm/adafruit_grand_central_m4_express/doc/index.rst +++ /dev/null @@ -1,195 +0,0 @@ -.. _adafruit_grand_central_m4_express: - -Adafruit Grand Central M4 Express -################################# - -Overview -******** - -The Adafruit Grand Central M4 Express is an ARM development board with the -form factor of an Arduino Mega. -It features 70 GPIO pins, a microSDHC slot and 8MiB of QSPI Flash. - -.. figure:: img/adafruit_grand_central_m4_express.webp - :width: 800px - :align: center - :alt: Adafruit Grand Central M4 Express - - Adafruit Grand Central M4 Express (Credit: Kattni Rembor / Adafruit) - -Hardware -******** - -- ATSAMD51P20A ARM Cortex-M4F processor at 120 MHz -- 1024 KiB of flash memory and 256 KiB of RAM -- 8 MiB of QSPI flash -- A red user LED -- A RGB "NeoPixel" / WS2812B LED -- A microSDHC slot (connected via SPI) -- Native USB port - -Supported Features -================== - -The adafruit_grand_central_m4_express board configuration supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | SysTick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports, User LED | -+-----------+------------+------------------------------------------+ -| UART | on-chip | Serial ports, Console | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | SPI ports, microSDHC slot | -+-----------+------------+------------------------------------------+ -| TRNG | on-chip | True Random Number Generator | -+-----------+------------+------------------------------------------+ -| RTC | on-chip | Real-Time Counter | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog Timer | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_grand_central_m4_express/adafruit_grand_central_m4_express_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Learning System`_ has detailed information about -the board including `pinouts`_ and the `schematics`_. - -System Clock -============ - -The SAMD51 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 120 MHz system clock. - -Serial Port -=========== - -The SAMD51 MCU has 8 SERCOM based UARTs. On the Grand Central, SERCOM0 is -the Zephyr console and is available on RX(PB25) and TX(PB24). - -SPI Port -======== - -The SAMD51 MCU has 8 SERCOM based SPIs. On the Grand Central, SERCOM7 has been -set into SPI mode to connect to devices over the SCK(PD09), MOSI(PD08), and MISO(PD11) pins. -Additionally SERCOM2 has been configured as SPI to access the microSDHC card. - -I2C Port -======== - -The SAMD51 MCU has 8 SERCOM based I2Cs. On the Grand Central, SERCOM3 has been -configured as I2C to connect to devices over the SCL(PB21) and SDA(PB20) pins. - -USB Device Port -=============== - -The SAMD51 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Grand Central ships with a BOSSA compatible UF2 bootloader. -The bootloader can be entered by quickly tapping the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: build - :compact: - -#. Connect the Grand Central to your host computer using USB. - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: flash - :compact: - - You should see "Hello World! adafruit_grand_central_m4_express" in your terminal. - -Debugging -========= - -In addition to the built-in bootloader, the Grand Central can be flashed and -debugged using a SWD probe such as the Segger J-Link. - -#. Connect the probe to the board using the 10-pin SWD interface. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: flash - :flash-args: -r openocd - :compact: - -#. Start debugging: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_grand_central_m4_express - :goals: debug - :compact: - -References -********** - -.. target-notes:: - -.. _Adafruit Learning System: - https://learn.adafruit.com/adafruit-grand-central - -.. _pinouts: - https://learn.adafruit.com/adafruit-grand-central/pinouts - -.. _schematics: - https://learn.adafruit.com/adafruit-grand-central/downloads - -.. _J-Link: - https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.board b/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.board deleted file mode 100644 index 79fd1eb629337d..00000000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit ItsyBitsy M4 Express board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS - bool "Adafruit ItsyBitsy M4 Express" - depends on SOC_PART_NUMBER_SAMD51G19A diff --git a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.defconfig b/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.defconfig deleted file mode 100644 index 922a2ab58bddbb..00000000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit ItsyBitsy M4 Express board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_itsybitsy_m4_express" - depends on BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS diff --git a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig b/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig deleted file mode 100644 index 9a06333e1176da..00000000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD51=y -CONFIG_SOC_PART_NUMBER_SAMD51G19A=y -CONFIG_BOARD_ADAFRUIT_ITSYBITSY_M4_EXPRESS=y -CONFIG_SOC_ATMEL_SAMD5X_OSCULP32K_AS_MAIN=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y diff --git a/boards/arm/adafruit_itsybitsy_m4_express/doc/index.rst b/boards/arm/adafruit_itsybitsy_m4_express/doc/index.rst deleted file mode 100644 index 401e28d6669529..00000000000000 --- a/boards/arm/adafruit_itsybitsy_m4_express/doc/index.rst +++ /dev/null @@ -1,209 +0,0 @@ -.. _adafruit_itsybitsy_m4_express: - -Adafruit ItsyBitsy M4 Express -############################# - -Overview -******** - -The Adafruit ItsyBitsy M4 express is a small (36 mm x 18 mm) ARM development -board with an onboard RGB LED, USB port, 2 MiB of SPI flash, and range of I/O -broken out onto 23 GPIO pins. - -.. image:: img/adafruit_itsybitsy_m4_express.jpg - :align: center - :alt: Adafruit ItsyBitsy M4 Express - -Hardware -******** - -- ATSAMD51G19A ARM Cortex-M4 processor at 120 MHz -- 512 KiB of flash memory and 192 KiB of RAM -- 2 MiB of SPI flash -- Internal trimmed 8 MHz oscillator -- A user LED -- An RGB DotStar LED -- Native USB port -- One reset button - -Supported Features -================== - -The adafruit_itsybitsy_m4_express board configuration supports the following -hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | Nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| TRNG | on-chip | True Random Number Generator | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Unique 128 bit serial number | -+-----------+------------+------------------------------------------+ -| RTC | on-chip | Real-Time Counter | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog Timer | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig`. - -Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. -To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set -:code:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided by 7, -i.e. no more than 4500. - -Connections and IOs -=================== - -The `Adafruit Learning System`_ has detailed information about -the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD51 MCU is configured to use the 32 kHz internal oscillator -with the on-chip PLL generating the 120 MHz system clock. - -Serial Port -=========== - -The SAMD51 MCU has 6 SERCOM based USARTs. On the ItsyBitsy, SERCOM3 is -the Zephyr console and is available on pins 0 (RX) and 1 (TX). - -SPI Port -======== - -The SAMD51 MCU has 6 SERCOM based SPIs. On the ItsyBitsy, SERCOM1 can be put -into SPI mode and used to connect to devices over the SCK (SCLK), MO (MOSI), and -MI (MISO) pins. - -PWM -=== - -The SAMD51 has three PWM generators with up to six channels each. :code:`TCC_0` -has a resolution of 24 bits and all other generators are 16 bit. :code:`TCC_1` -pin 2 is mapped to PA18 (D7) and pin 3 is mapped to PA19 (D9). - -USB Device Port -=============== - -The SAMD51 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The ItsyBitsy ships with a the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: build - :compact: - -#. Connect the ItsyBitsy to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: flash - :compact: - - You should see "Hello World! adafruit_itsybitsy_m4_express" in your terminal. - -Debugging -========= - -In addition to the built-in bootloader, the ItsyBitsy can be flashed and -debugged using a SWD probe such as the Segger J-Link. - -#. Connect the board to the probe by connecting the :code:`SWCLK`, - :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the - ItsyBitsy to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, :code:`GND`, - and :code:`VTref` pins on the `J-Link`_. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: flash - :flash-args: -r openocd - :compact: - -#. Start debugging: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_itsybitsy_m4_express - :goals: debug - :compact: - -References -********** - -.. target-notes:: - -.. _Adafruit Learning System: - https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4 - -.. _pinouts: - https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/pinouts - -.. _schematic: - https://learn.adafruit.com/introducing-adafruit-itsybitsy-m4/downloads - -.. _J-Link: - https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig b/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig deleted file mode 100644 index c01ef570cd5a1c..00000000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Adafruit ItsyBitsy nRF52840 Express board configuration - -# Copyright (c) 2022 Embla Flatlandsmo -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_ADAFRUIT_ITSYBITSY_NRF52840 - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.board b/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.board deleted file mode 100644 index f0a4444fd91be6..00000000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit ItsyBitsy nRF52840 Express board configuration - -# Copyright (c) 2022 Embla Flatlandsmo -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_ITSYBITSY_NRF52840 - bool "Adafruit ItsyBitsy nRF52840 Express" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.defconfig b/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.defconfig deleted file mode 100644 index a31f72aa40d9ff..00000000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# Adafruit ItsyBitsy nRF52840 Express board configuration - -# Copyright (c) 2022 Embla Flatlandsmo -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_ITSYBITSY_NRF52840 - -config BOARD - default "adafruit_itsybitsy_nrf52840" - -config BT_CTLR - default BT - -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -# Wait 1500ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 1500 - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -endif # BOARD_ADAFRUIT_ITSYBITSY_NRF52840 diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840_defconfig b/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840_defconfig deleted file mode 100644 index a88657578f3cf7..00000000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ADAFRUIT_ITSYBITSY_NRF52840=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Flashing -CONFIG_USE_DT_CODE_PARTITION=y -CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/arm/adafruit_itsybitsy_nrf52840/doc/index.rst b/boards/arm/adafruit_itsybitsy_nrf52840/doc/index.rst deleted file mode 100644 index aa28cb501c3034..00000000000000 --- a/boards/arm/adafruit_itsybitsy_nrf52840/doc/index.rst +++ /dev/null @@ -1,192 +0,0 @@ -.. _adafruit_itsybitsy_nrf52840: - -Adafruit ItsyBitsy nRF52840 -########################### - -Overview -******** - -The Adafruit ItsyBitsy nRF52840 Express is a small (36 mm x 18 mm) ARM -development board with an onboard RGB LED, USB port, 2 MB of QSPI flash, -and range of I/O broken out onto 21 GPIO pins. - -This development kit has the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`I2S (Inter-Integrated Sound)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. image:: img/adafruit_itsybitsy_nrf52840.jpeg - :align: center - :alt: Adafruit ItsyBitsy nRF52840 Express - -Hardware -******** -- nRF52840 ARM Cortex-M4F CPU at 64MHz -- 1 MB of flash memory and 256 KB of SRAM -- 2 MB of QSPI flash -- A user LED -- A user switch -- An RGB DotStar LED -- Native USB port -- One reset button - -Supported Features -================== - -The Adafruit ItsyBitsy nRF52840 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `Adafruit ItsyBitsy nRF52840 Express Learn site`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -LED ---- - -* LED0 (red) = P0.06 - -* LED1 (Adafruit DotStar) - - * DATA = P0.08 - - * CLK = P1.09 - -Push buttons ------------- - -* SWITCH = P0.29 - -* RESET = P0.18 - -Logging -------- - -Logging is done using the USB-CDC port. See the :zephyr:code-sample:`logging` sample -or the :zephyr:code-sample:`usb-cdc-acm-console` sample applications to see how this works. - -Testing LEDs and buttons on the Adafruit ItsyBitsy nRF52840 Express -******************************************************************* -The :zephyr:code-sample:`button` sample lets you test the buttons (switches) and the red LED. -The :zephyr:code-sample:`blinky` sample lets you test the red LED. - -The DotStar LED has been implemented as a SPI device and can be tested -with the :zephyr:code-sample:`led-apa102` sample application. - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/adafruit_itsybitsy_nrf52840/adafruit_itsybitsy_nrf52840.dts`. - -Programming and Debugging -************************* -The ItsyBitsy ships with the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -First time setup -================ -Some versions of this board were shipped with a buggy bootloader. -Ensure that the bootloader is up to date by following the -`Adafruit UF2 Bootloader update`_ tutorial. Note that this tutorial -was made for the Adafruit Feather nRF52840, but the steps to update -the bootloader are the same for the ItsyBitsy. The files for the -ItsyBitsy bootloader can be found in the `Adafruit nRF52 Bootloader repo`_. - -The building and flashing of Zephyr applications have been tested with -release 0.7.0 of the UF2 bootloader. - -Flashing -======== -Flashing is done by dragging and dropping the built Zephyr UF2-file -into the :code:`ITSY840BOOT` drive. - -#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` - sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: adafruit_itsybitsy_nrf52840 - :goals: build - :compact: - -#. Connect the ItsyBitsy to your host computer using USB - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - Drag and drop the file :code:`samples/basic/blinky/build/zephyr/zephyr.uf2` - into :code:`ITSY840BOOT` - -The device will disconnect and you should see the red LED blink. - -References -********** - -.. target-notes:: - -.. _Adafruit ItsyBitsy nRF52840 Express Learn site: - https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express - -.. _pinouts: - https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/pinouts - -.. _schematic: - https://learn.adafruit.com/adafruit-itsybitsy-nrf52840-express/downloads - -.. _Adafruit UF2 Bootloader update: - https://learn.adafruit.com/introducing-the-adafruit-nrf52840-feather/update-bootloader - -.. _Adafruit nRF52 Bootloader repo: - https://github.com/adafruit/Adafruit_nRF52_Bootloader/releases diff --git a/boards/arm/adafruit_kb2040/Kconfig.board b/boards/arm/adafruit_kb2040/Kconfig.board deleted file mode 100644 index 3b1b1ab5f00d0f..00000000000000 --- a/boards/arm/adafruit_kb2040/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Pete Johanson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_KB2040 - bool "Adafruit KB2040 Board" - depends on SOC_RP2040 diff --git a/boards/arm/adafruit_kb2040/Kconfig.defconfig b/boards/arm/adafruit_kb2040/Kconfig.defconfig deleted file mode 100644 index 026c89520181f9..00000000000000 --- a/boards/arm/adafruit_kb2040/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Peter Johanson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_KB2040 - -config BOARD - default "adafruit_kb2040" - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_ADAFRUIT_KB2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/Kconfig.board b/boards/arm/adafruit_qt_py_rp2040/Kconfig.board deleted file mode 100644 index f2c8db2c34163b..00000000000000 --- a/boards/arm/adafruit_qt_py_rp2040/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Kelly Lord -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_QT_PY_RP2040 - bool "Adafruit QT Py RP2040 Board" - depends on SOC_RP2040 diff --git a/boards/arm/adafruit_qt_py_rp2040/Kconfig.defconfig b/boards/arm/adafruit_qt_py_rp2040/Kconfig.defconfig deleted file mode 100644 index 705a49ac152364..00000000000000 --- a/boards/arm/adafruit_qt_py_rp2040/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Peter Johanson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADAFRUIT_QT_PY_RP2040 - -config BOARD - default "adafruit_qt_py_rp2040" - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_ADAFRUIT_QT_PY_RP2040 diff --git a/boards/arm/adafruit_trinket_m0/Kconfig.board b/boards/arm/adafruit_trinket_m0/Kconfig.board deleted file mode 100644 index 302a0da3feb5ed..00000000000000 --- a/boards/arm/adafruit_trinket_m0/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Trinket M0 board configuration - -# Copyright (c) 2018 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADAFRUIT_TRINKET_M0 - bool "Adafruit Trinket M0" - depends on SOC_PART_NUMBER_SAMD21E18A diff --git a/boards/arm/adafruit_trinket_m0/Kconfig.defconfig b/boards/arm/adafruit_trinket_m0/Kconfig.defconfig deleted file mode 100644 index 31c97cb7dc2fa7..00000000000000 --- a/boards/arm/adafruit_trinket_m0/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Adafruit Trinket M0 board configuration - -# Copyright (c) 2018 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adafruit_trinket_m0" - depends on BOARD_ADAFRUIT_TRINKET_M0 diff --git a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig b/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig deleted file mode 100644 index 86fa3a35e0079f..00000000000000 --- a/boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21E18A=y -CONFIG_BOARD_ADAFRUIT_TRINKET_M0=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_USE_DT_CODE_PARTITION=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y diff --git a/boards/arm/adafruit_trinket_m0/doc/index.rst b/boards/arm/adafruit_trinket_m0/doc/index.rst deleted file mode 100644 index 2512df3fd56ab3..00000000000000 --- a/boards/arm/adafruit_trinket_m0/doc/index.rst +++ /dev/null @@ -1,170 +0,0 @@ -.. _adafruit_trinket_m0: - -Adafruit Trinket M0 -################### - -Overview -******** - -The Adafruit Trinket M0 is a tiny (27 mm x 15 mm) ARM development -board with an onboard RGB LED, USB port, and range of I/O broken out -onto 5 pins. - -.. image:: img/adafruit_trinket_m0.jpg - :align: center - :alt: Adafruit Trinket M0 - -Hardware -******** - -- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- Internal trimmed 8 MHz oscillator -- A user LED -- An RGB DotStar LED -- Native USB port -- One reset button - -Supported Features -================== - -The adafruit_trinket_m0 board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/adafruit_trinket_m0/adafruit_trinket_m0_defconfig`. - -Connections and IOs -=================== - -The `Adafruit Trinket M0 Learn site`_ has detailed information about -the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 8 MHz internal oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the Trinket, SERCOM0 is -the Zephyr console and is available on pins 3 (RX) and 4 (TX). -SERCOM2 is available on pins 2 (RX) and 0 (TX). - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Trinket, SERCOM1 is -used to drive the DotStar RGB LED. SERCOM0 can be put into SPI mode -and used to connect to devices over pin 2 (MISO), pin 4 (MOSI), and -pin 3 (SCK). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Trinket M0 ships the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_trinket_m0 - :goals: build - :compact: - -#. Connect the Trinket M0 to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adafruit_trinket_m0 - :goals: flash - :compact: - - You should see "Hello World! adafruit_trinket_m0" in your terminal. - -References -********** - -.. target-notes:: - -.. _Adafruit Trinket M0 Learn site: - https://learn.adafruit.com/adafruit-trinket-m0-circuitpython-arduino - -.. _pinouts: - https://learn.adafruit.com/assets/49778 - -.. _schematic: - https://learn.adafruit.com/assets/45723 diff --git a/boards/arm/adi_eval_adin1110ebz/Kconfig.board b/boards/arm/adi_eval_adin1110ebz/Kconfig.board deleted file mode 100644 index 29f1e3b8dbcc28..00000000000000 --- a/boards/arm/adi_eval_adin1110ebz/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ADI EVAL-ADIN1110EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADI_EVAL_ADIN1110EBZ - bool "ADI EVAL-ADIN1110EBZ evaulation board" - depends on SOC_STM32L4S5XX diff --git a/boards/arm/adi_eval_adin1110ebz/Kconfig.defconfig b/boards/arm/adi_eval_adin1110ebz/Kconfig.defconfig deleted file mode 100644 index 79e309af4cd612..00000000000000 --- a/boards/arm/adi_eval_adin1110ebz/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# ADI EVAL-ADIN1110EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADI_EVAL_ADIN1110EBZ - -config BOARD - default "adi_eval_adin1110ebz" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config MDIO_INIT_PRIORITY - default 81 - depends on MDIO - -config PHY_INIT_PRIORITY - default 82 - depends on NET_L2_ETHERNET && ETH_DRIVER - -config MEMC - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_ADI_EVAL_ADIN1110EBZ diff --git a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig b/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig deleted file mode 100644 index 15174238c664cd..00000000000000 --- a/boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ADI_EVAL_ADIN1110EBZ=y -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4S5XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin1110ebz/doc/index.rst b/boards/arm/adi_eval_adin1110ebz/doc/index.rst deleted file mode 100644 index 3bcc3167596a4b..00000000000000 --- a/boards/arm/adi_eval_adin1110ebz/doc/index.rst +++ /dev/null @@ -1,183 +0,0 @@ -.. _adi_eval_adin1110ebz: - -ADI EVAL-ADIN1110EVB Evaluation board -##################################### - -Overview -******** - -The EVAL-ADIN1110EBZ is a flexible platform enabling quick evaluation of the ADIN1110, robust, -low power 10BASE-T1L MAC-PHY. It provides 10Mbit per second Single Pair Ethernet (SPE) connections -with devices across 1.7km of cable. - -The evaluation board offers two modes of operation for maximum flexibility. Connected to a PC -via USB port, the full set of ADIN1110 register settings and features such as link quality -monitoring and diagnostics can be accessed over the USB using serial command interface. -The board also provides an Arduino interface. - -Alternatively, the board can operate in stand-alone mode where it is configured by setting hardware -configuration links and switches. On-board LEDs provide status indication. - -The SPI interface provides configuration and data access to the ADIN1110. - -A small prototyping area and test points are provided for experimentation with alternative cable -connection topologies including isolation transformers and/or power coupling inductors. - -.. figure:: img/adi_eval_adin1110ebz.webp - :align: center - :alt: ADI EVAL-ADIN1110EBZ - - ADI EVAL-ADIN1110EBZ (Credit: Analog Devices, Inc.) - -.. important:: - - S201 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr - default board configuration is set to work as "Generic SPI, CRC enabled", - so the S201 DIP switches must be set as ``SPI_CFG0 OFF`` and ``SPI_CFG1 ON``. - An inconsistent S201 DIP switches configuration will halt the boot. - -Hardware -******** - -The ADI EVAL-ADIN1110EBZ hardware features list is available here: - -https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide - - -Supported Features -================== - -The ADI adi_eval_adin1110ebz board configuration supports the -following hardware features: - -+--------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+==============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+--------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+--------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+--------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+--------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+--------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+--------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+--------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+--------------+------------+-------------------------------------+ -| ADIN1110 | spi | adin1110 10BASE-T1L mac/phy | -+--------------+------------+-------------------------------------+ -| FT232 | uart | usb-uart | -+--------------+------------+-------------------------------------+ -| ADT7422 | i2c | temperature sensor | -+--------------+------------+-------------------------------------+ -| ISS66WVE4M16 | fmc | 8MB PSRAM | -+--------------+------------+-------------------------------------+ - - -The default configuration can be found in the defconfig file: - - ``boards/arm/adi_eval_adin1110ebz/adi_eval_adin1110ebz_defconfig`` - - -Connections and IOs -=================== - -ADI ADIN1110EBZ evaluation board has 7 GPIO controllers (from A to G). These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For mode details please refer to `EVAL-ADIN1110EBZ User Guide `_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (UART to FT232) -- UART_4 TX/RX : PA0/PA1 (Arduino Serial) -- I2C1 SCL/SDA : PG14/PG13 (Arduino I2C) -- I2C3 SCL/SDA : PG7/PG8 (Sensor I2C bus) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Simple SPI to nor Flash) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (ADIN1110) -- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (Arduino SPI) -- LD1 : PC13 (Green LED) -- LD2 : PE2 (Red LED) -- LD3 : PE6 (Yellow LED) -- LD4 : PG15 (Blue LED) -- PSRAM : PE0/PE1/PF0-PF15/PG0-PG5/PD11-PD13/PE3/PE4 - PD14/PD15/PD9/PD1/PE7-PE15/PD8-PD10 - - -System Clock ------------- - -EVAL-ADIN1110EBZ System Clock could be driven by an internal or external oscillator, as well as -the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the -16MHz high speed internal oscillator. - -Serial Port ------------ - -EVAL-ADIN1110EBZ has 2 U(S)ARTs. The Zephyr console output is assigned to UART1 that is connected -to a FT232, so available through Micro USB connector. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -EVAL-ADIN1110EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is -supported by the openocd version included in Zephyr SDK. - -Flashing an application to Discovery kit ------------------------------------------ - -Connect the EVAL-ADIN1110EBZ to your host computer using the USB port, then run a serial host -program to connect with your ADI board. For example: - -.. code-block:: console - - $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN1110EBZ_AVAS_XXXXXX-if00-port0 - -where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin1110ebz - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! adi_eval_adin1110ebz - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin1110ebz - :maybe-skip-config: - :goals: debug - -.. _EVAL-ADIN1110EBZ evaluation board website: - https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin1110.html - -.. _EVAL-ADIN1110EBZ board User Guide: - https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide - -.. _ADIN1110 Datasheet: - https://www.analog.com/media/en/technical-documentation/data-sheets/adin1110.pdf - -.. _STM32L4S5QII3P reference manual: - https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_eval_adin2111ebz/Kconfig.board b/boards/arm/adi_eval_adin2111ebz/Kconfig.board deleted file mode 100644 index f173947c39b60a..00000000000000 --- a/boards/arm/adi_eval_adin2111ebz/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ADI EVAL-ADIN2111EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADI_EVAL_ADIN2111EBZ - bool "ADI EVAL-ADIN2111EBZ evaulation board" - depends on SOC_STM32L4S5XX diff --git a/boards/arm/adi_eval_adin2111ebz/Kconfig.defconfig b/boards/arm/adi_eval_adin2111ebz/Kconfig.defconfig deleted file mode 100644 index 41dd579738c278..00000000000000 --- a/boards/arm/adi_eval_adin2111ebz/Kconfig.defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# ADI EVAL-ADIN2111EBZ board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADI_EVAL_ADIN2111EBZ - -config BOARD - default "adi_eval_adin2111ebz" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config MDIO_INIT_PRIORITY - default 81 - depends on MDIO - -config PHY_INIT_PRIORITY - default 82 - depends on NET_L2_ETHERNET && ETH_DRIVER - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_ADIN2111 - -config NET_IF_MAX_IPV4_COUNT - default 2 - -endif # ETH_ADIN2111 - -endif # NETWORKING - -endif # BOARD_ADI_EVAL_ADIN2111EBZ diff --git a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig b/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig deleted file mode 100644 index f7e4d9c4ab350a..00000000000000 --- a/boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ADI_EVAL_ADIN2111EBZ=y -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4S5XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/adi_eval_adin2111ebz/doc/index.rst b/boards/arm/adi_eval_adin2111ebz/doc/index.rst deleted file mode 100644 index ac9d33aa2853b3..00000000000000 --- a/boards/arm/adi_eval_adin2111ebz/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _adi_eval_adin2111ebz: - -ADI EVAL-ADIN2111EVB Evaluation board -##################################### - -Overview -******** - -The EVAL-ADIN2111EBZ is a flexible platform enabling quick evaluation of the ADIN2111, robust, -low power 10BASE-T1L 2-Port Ethernet switch. The evaluation board provides 2 10BASE-T1L channels -with 10Mbit per second Single Pair Ethernet (SPE) connections reaching up to 1.7km of link distance. - -The ADIN2111 internal switch can be configured in store and forward mode between the two 10BASE-T1L -channels and the SPI host. Cut through mode is also available between Port 1 and Port 2 and can -be used without the need of the SPI host (unmanaged configuration). - -The evaluation board offers two modes of operation for maximum flexibility: Connected to a PC -via USB port, the full set of ADIN2111 register settings and features such as link quality -monitoring and diagnostics can be accessed over the USB using the serial command interface -implemented in the evaluation firmware. - -Alternatively, the board can operate in cut-through mode between Port 1 and Port 2 (unmanaged -configuration without firmware) where the EVAL-ADIN2111EBZ acts as a network switch forwarding -packets between the 2x 10BASE-T1L ports. The 2x links are configured by setting the ADIN2111 -hardware configuration pins jumper and switches. The 2x On-board Activity LEDs provide Link -activity status indication for each port. - -Custom firmware can also be developed and the ADIN2111 driver support package includes simple -project examples to start a custom implementation. - -The SPI interface provides access to the management registers required for the switch configuration, -the 2 PHYs configuration and data exchange between SPI host and ports. - -.. important:: - - S1 DIP switches are shipped in Open Alliance SPI mode. The current Zephyr - default board configuration is set to work as "Generic SPI, CRC enabled", - so the S1 DIP switches must be set as ``SPI_CFG0 OFF and SPI_CFG1 OFF``. - An inconsistent S1 DIP switches configuration will halt the boot. - -.. figure:: img/adi_eval_adin2111ebz.webp - :align: center - :alt: ADI EVAL-ADIN2111EBZ - - ADI EVAL-ADIN2111EBZ (Credit: Analog Devices, Inc.) - -Hardware -******** - -The ADI EVAL-ADIN2111EBZ hardware features list is available here: - -https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide - - -Supported Features -================== - -The ADI adi_eval_adin2111ebz board configuration supports the -following hardware features: - -+--------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+==============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+--------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+--------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+--------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+--------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+--------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+--------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+--------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+--------------+------------+-------------------------------------+ -| ADIN2111 | spi | adin2111 10BASE-T1L mac/phy | -+--------------+------------+-------------------------------------+ -| FT232 | uart | usb-uart | -+--------------+------------+-------------------------------------+ - - -The default configuration can be found in the defconfig file: - - ``boards/arm/adi_eval_adin2111ebz/adi_eval_adin2111ebz_defconfig`` - - -Connections and IOs -=================== - -ADI ADIN2111EBZ evaluation board has 7 GPIO controllers (from A to G). -These controllers are responsible for pin muxing, input/output, pull-up, etc. - -For mode details please refer to `EVAL-ADIN2111EBZ User Guide `_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (UART to FT232, console) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (SPI to external nor flash IS25LP128) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 (SPI to external ADIN2111) -- LED1 : POWER (Green LED) -- UC_LED1 : PB6 (Blue LED) -- MOD LED1 : PE2 (SR LED) -- MOD LED2 : PE6 (BG LED) -- NET LED1 : PB10 (SR LED) -- NET LED2 : PB11 (BG LED) - - -System Clock ------------- - -EVAL-ADIN2111EBZ System Clock could be driven by an internal or external oscillator, as well as the -main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, driven by the -16MHz high speed internal oscillator. - -Serial Port ------------ - -EVAL-ADIN2111EBZ has 1 U(S)ART. The Zephyr console output is assigned to UART1 that is connected -to a FT232, available through Micro USB connector. Default settings are 115200 8N1. -Same UART1 TX and RX cmos signals are available before the FT232, at P9 connector. - - -Programming and Debugging -************************* - -Flashing -======== - -EVAL-ADIN2111EBZ includes an ST-LINK/V2-1 JTAG/SWD 10 or 20 pin connector. This interface is -supported by the openocd version included in Zephyr SDK. - -Flashing an application to Discovery kit ------------------------------------------ - -Connect the EVAL-ADIN2111EBZ to your host computer using the USB port, then run a serial host -program to connect with your ADI board. For example: - -.. code-block:: console - - $ minicom -D /dev/serial/by-id/usb-ADI_EVAL-ADIN2111EBZ_XXXXXX-12-if00-port0 - -where XXXXXX is the serial number of the connected device. -Then, build and flash in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin2111ebz - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! adi_eval_adin2111ebz - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_eval_adin2111ebz - :maybe-skip-config: - :goals: debug - -.. _EVAL-ADIN2111EBZ evaluation board website: - https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/eval-adin2111.html - -.. _EVAL-ADIN2111EBZ board User Guide: - https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide - -.. _ADIN2111 Datasheet: - https://www.analog.com/media/en/technical-documentation/data-sheets/adin2111.pdf - -.. _STM32L4S5QII3P reference manual: - https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/adi_sdp_k1/Kconfig.board b/boards/arm/adi_sdp_k1/Kconfig.board deleted file mode 100644 index 8aa4b969d613cd..00000000000000 --- a/boards/arm/adi_sdp_k1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ADI SDP-K1 board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADI_SDP_K1 - bool "ADI SDP-K1 Controller Board" - depends on SOC_STM32F469XX diff --git a/boards/arm/adi_sdp_k1/Kconfig.defconfig b/boards/arm/adi_sdp_k1/Kconfig.defconfig deleted file mode 100644 index 03e3bd4cdeb3cb..00000000000000 --- a/boards/arm/adi_sdp_k1/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# ADI SDP-K1 board configuration - -# Copyright (c) 2024 BayLibre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ADI_SDP_K1 - -config BOARD - default "adi_sdp_k1" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_ADI_SDP_K1 diff --git a/boards/arm/adi_sdp_k1/doc/index.rst b/boards/arm/adi_sdp_k1/doc/index.rst deleted file mode 100644 index 177f7bf3550219..00000000000000 --- a/boards/arm/adi_sdp_k1/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _adi_sdp_k1: - -ADI SDP-K1 -########## - -Overview -******** - -The EVAL-SDP-CK1Z (SDP-K1) controller board is a system demonstration platform -(SDP) from Analog Devices designed to connect to evaluation shields containing -ADI components. - -- STM32 microcontroller in BGA216 package -- USB 2.0 device with USB-C connector -- USB debug interface supporting CMSIS-DAP through a NXP Freescale - microcontroller -- Flexible board power supply - - USB VBUS 5 V max. 500 mA - - 5.5mm DC power jack 7 - 12 V min. 300 mA - - VIN from Arduino* compatible connectors - - VIN from 120-pin connector 5 V min. 300 mA -- 3 color LEDs (green, orange, red) and 1 status LED -- One push-buttons: RESET -- 16MB SDRAM -- Arduino UNO and 120-pin SDP connectors - -.. figure:: img/adi_sdp_k1.webp - :align: center - :alt: ADI SDP-K1 - - ADI SDP-K1 (Credit: Analog Devices, Inc.) - -More information about the board can be found on the `ADI SDP-K1 website`_. - -Hardware -******** - -ADI SDP-K1 provides the following hardware components: - -- STM32F469NIH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD of 1.8 V or 3.3 V -- 2 MB Flash -- 384 KB SRAM -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- LCD TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (6) -- 1xSAI (serial audio interface) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F469NI can be found here: - - `STM32F469NI product page`_ - - `STM32F469 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f469i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/adi_sdp_k1/adi_sdp_k1_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `EVAL-SDP-CK1Z User Guide`_. - -Arduino UNO headers -------------------- - -.. figure:: img/adi_sdp_k1_arduino.webp - :align: center - :alt: ADI SDP-K1 Arduino UNO headers pinout - - ADI SDP-K1 (Credit: Analog Devices, Inc.) - -120-pin SDP connector ---------------------- - -.. figure:: img/adi_sdp_k1_120pin.webp - :align: center - :alt: ADI SDP-K1 120-pin SDP connector pinout - - ADI SDP-K1 (Credit: Analog Devices, Inc.) - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_5 TX/RX : P2 (DAPLink USB-C) -- UART_5 TX/RX : P8 (DAPLink two position through hole) -- LED1 : DS6 (Red) -- LED2 : DS5 (Orange) -- LED3 : DS4 (Green) -- LED4 : DS4 (Status) - -Programming and Debugging -************************* - -The ADI SDP-K1 be programmed over USB using the DAPLink firmware running on an -embedded NXP Freescale microcontroller or a 10-pin ``DEBUG`` header connected -to a STLINK debugger. - -DAPLink exposes a storage device, as well as USB HID and CDC Endpoints, to the -host. For more details please refer to the `Official DAPLink website`_. - -Flashing -======== - -Flashing an application with a STLINK debugger ----------------------------------------------- - -First, connect the STLINK debugger to your host computer using the Micro-USB port. -Then attach the debugger to the 10-pin ``DEBUG`` header on the SDP-K1. Finally -connect the SDP-K1 to your host computer using the USB-C port. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/serial/by-id/usb-ARM_DAPLink_CMSIS-DAP_<...> - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adi_sdp_k1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! adi_sdp_k1 - -Debugging -========= - -.. _ADI SDP-K1 website: - https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/sdp-k1.html - -.. _EVAL-SDP-CK1Z User Guide: - https://www.analog.com/media/en/technical-documentation/user-guides/EVAL-SDP-CK1Z-UG-1539.pdf - -.. _STM32F469NI product page: - https://www.st.com/en/microcontrollers/stm32f469ni.html - -.. _STM32F469 reference manual: - https://www.st.com/resource/en/reference_manual/dm00127514.pdf - -.. _Official DAPLink website: - https://daplink.io/ diff --git a/boards/arm/am62x_m4/Kconfig.board b/boards/arm/am62x_m4/Kconfig.board deleted file mode 100644 index 963b5c6133d032..00000000000000 --- a/boards/arm/am62x_m4/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_AM62X_M4_SK - bool "TI AM62x M4 Starter Kit (SK) Evaluation Module (EVM)" - depends on SOC_SERIES_AM62X_M4 - -config BOARD_AM62X_M4_PHYBOARD_LYRA - bool "PHYTEC AM62x M4 phyBOARD-Lyra" - depends on SOC_SERIES_AM62X_M4 diff --git a/boards/arm/am62x_m4/Kconfig.defconfig b/boards/arm/am62x_m4/Kconfig.defconfig deleted file mode 100644 index 7b6182aa040f6d..00000000000000 --- a/boards/arm/am62x_m4/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_AM62X_M4_SK - -config BOARD - default "am62x_m4_sk" - -endif # BOARD_AM62X_M4_SK - -if BOARD_AM62X_M4_PHYBOARD_LYRA - -config BOARD - default "am62x_m4_phyboard_lyra" - -endif # BOARD_AM62X_M4_PHYBOARD_LYRA diff --git a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.yaml b/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.yaml deleted file mode 100644 index b77fb449347ea5..00000000000000 --- a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: am62x_m4_phyboard_lyra -name: PHYTEC AM62x M4 phyBOARD-Lyra -type: mcu -arch: arm -toolchain: - - zephyr -ram: 192 -vendor: phytec diff --git a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig b/boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig deleted file mode 100644 index 822222a8900fed..00000000000000 --- a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# PHYTEC AM62x M4 phyBOARD-Lyra -# -# Copyright (C) 2023 PHYTEC Messtechnik GmbH -# Author: Daniel Schultz -# -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_AM62X_M4=y -CONFIG_SOC_AM62x_M4=y -CONFIG_BOARD_AM62X_M4_PHYBOARD_LYRA=y -CONFIG_CORTEX_M_SYSTICK=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Enable Pinctrl -CONFIG_PINCTRL=y - -# Serial Driver -CONFIG_SERIAL=y - -# GPIO Driver -CONFIG_GPIO=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/am62x_m4/am62x_m4_sk.yaml b/boards/arm/am62x_m4/am62x_m4_sk.yaml deleted file mode 100644 index ef07d5a99d9643..00000000000000 --- a/boards/arm/am62x_m4/am62x_m4_sk.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: am62x_m4_sk -name: TI AM62X M4 Starter Kit (SK) -type: mcu -arch: arm -toolchain: - - zephyr -ram: 192 -vendor: ti diff --git a/boards/arm/am62x_m4/am62x_m4_sk_defconfig b/boards/arm/am62x_m4/am62x_m4_sk_defconfig deleted file mode 100644 index 561463888c0fdd..00000000000000 --- a/boards/arm/am62x_m4/am62x_m4_sk_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_AM62X_M4=y -CONFIG_SOC_AM62x_M4=y -CONFIG_BOARD_AM62X_M4_SK=y -CONFIG_CORTEX_M_SYSTICK=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Enable Pinctrl -CONFIG_PINCTRL=y - -# Serial Driver -CONFIG_SERIAL=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/am62x_m4/doc/am62x_m4_phyboard_lyra.rst b/boards/arm/am62x_m4/doc/am62x_m4_phyboard_lyra.rst deleted file mode 100644 index 189710b5e48dec..00000000000000 --- a/boards/arm/am62x_m4/doc/am62x_m4_phyboard_lyra.rst +++ /dev/null @@ -1,148 +0,0 @@ -.. _am62x_m4_phyboard_lyra: - -AM62x phyBOARD-Lyra M4F Core -############################ - -Overview -******** - -The AM62x phyBOARD-Lyra board configuration is used by Zephyr applications -that run on the TI AM62x platform. The board configuration provides support -for the ARM Cortex-M4F MCU core and the following features: - -- Nested Vector Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) - -The board configuration also enables support for the semihosting debugging console. - -See the `PHYTEC AM62x Product Page`_ for details. - -.. figure:: img/phyCORE-AM62x_Lyra_frontside.webp - :align: center - :alt: AM62x phyBOARD-Lyra - - PHYTEC phyBOARD-Lyra with the phyCORE-AM62x SoM - -Hardware -******** -The AM62x phyBOARD-Lyra kit features the AM62x SoC, which is composed of a -quad Cortex-A53 cluster and a single Cortex-M4 core in the MCU domain. Zephyr -is ported to run on the M4F core and the following listed hardware -specifications are used: - -- Low-power ARM Cortex-M4F -- Memory - - - 256KB of SRAM - - 2GB of DDR4 - -- Debug - - - XDS110 based JTAG - -Supported Features -================== - -The am62x_m4_phyboard_lyra configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 400 MHz. - -DDR RAM -------- - -The board has 2GB of DDR RAM available. This board configuration -allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -MCU domain UART (MCU_UART0). - -SD Card -******* - -Download PHYTEC's official `WIC`_ as well as `BMAP`_ and flash the WIC file with -an etching software onto an SD-card. This will boot Linux on the A53 application -cores of the SoM. These cores will then load the zephyr binary on the M4 core -using remoteproc. - -The default configuration can be found in the defconfig file: - -.. code-block:: console - - boards/arm/am62x_m4/am62x_m4_phyboard_lyra_defconfig - -Flashing -******** - -The Linux running on the A53 uses the remoteproc framework to manage the M4F co-processor. -Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to -load it while booting using remoteproc. - -To test the M4F core, we build the `hello_world` sample with the following command. - -.. code-block:: console - - # From the root of the Zephyr repository - west build -p -b am62x_m4_phyboard_lyra samples/hello_world - -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. - -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. - -.. code-block:: console - - # Mount the SD card at sdcard for example - sudo mount /dev/sdX sdcard - # copy the elf to the /lib/firmware directory - sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw - -The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. - -To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `phyBOARD SD Card Booting Essentials`_. - -After changing the boot mode, stop in U-Boot to enable the M4F co-processor. - -.. code-block:: console - - setenv overlays k3-am62-phyboard-lyra-rpmsg.dtbo - # Save the overlays variable permanently - saveenv - boot - -The board should boot into Linux and the binary will run and print Hello world to the MCU_UART0 -port. - - - -.. _PHYTEC AM62x Product Page: - https://www.phytec.com/product/phycore-am62x/ - -.. _WIC: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz - -.. _BMAP: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap - -.. _phyBOARD SD Card Booting Essentials: - https://docs.phytec.com/latest/phycore-am62x/bootingessentials/sdcard.html diff --git a/boards/arm/am62x_m4/doc/am62x_m4_sk.rst b/boards/arm/am62x_m4/doc/am62x_m4_sk.rst deleted file mode 100644 index e789c33d5f8adb..00000000000000 --- a/boards/arm/am62x_m4/doc/am62x_m4_sk.rst +++ /dev/null @@ -1,141 +0,0 @@ -.. _am62x_m4_sk: - -AM62x-SK M4F Core -################# - -Overview -******** - -The AM62x-SK board configuration is used by Zephyr applications that run on -the TI AM62x platform. The board configuration provides support for the ARM -Cortex-M4F MCU core and the following features: - -- Nested Vector Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) - -The board configuration also enables support for the semihosting debugging console. - -See the `TI AM62X Product Page`_ for details. - -.. figure:: img/sk_am62_angled.webp - :align: center - :alt: TI AM62x-SK EVM - - Texas Instruments AM62x SK EVM - -Hardware -******** -The AM62x-SK EVM features the AM62x SoC, which is composed of a quad Cortex-A53 -cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on -the M4F core and the following listed hardware specifications are used: - -- Low-power ARM Cortex-M4F -- Memory - - - 256KB of SRAM - - 2GB of DDR4 - -- Debug - - - XDS110 based JTAG - -Supported Features -================== - -The am62x_m4_sk configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 400 MHz. - -DDR RAM -------- - -The board has 2GB of DDR RAM available. This board configuration -allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -MCU domain UART (MCU_UART0). - -SD Card -******* - -Download TI's official `WIC`_ and flash the WIC file with an etching software -onto an SD-card. This will boot Linux on the A53 application cores of the EVM. -These cores will then load the zephyr binary on the M4 core using remoteproc. - -The default configuration can be found in the defconfig file: - -.. code-block:: console - - boards/arm/am62x_m4/am62x_m4_sk_defconfig - -Flashing -******** - -The board can using remoteproc, and uses the OpenAMP resource table to accomplish this. - -The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. - -To test the M4F core, we build the `hello_world` sample with the following command. - -.. code-block:: console - - # From the root of the Zephyr repository - west build -p -b am62x_m4_sk samples/hello_world - -This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. - -We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. - -.. code-block:: console - - # Mount the SD card at sdcard for example - sudo mount /dev/sdX sdcard - # copy the elf to the /lib/firmware directory - sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw - -The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. - -To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `EVM Setup Page`_. - -After changing the boot mode, the board should go through the boot sequence on powering up. -The binary will run and print Hello world to the MCU_UART0 port. - -References -********** - -AM62x SK EVM TRM: - https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf - -.. _TI AM62X Product Page: - https://www.ti.com/product/AM625 - -.. _WIC: - https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-PvdSyIiioq/08.06.00.42/tisdk-default-image-am62xx-evm.wic.xz - -.. _AM62x SK EVM TRM: - https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf - -.. _EVM Setup Page: - https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_06_00_18/exports/docs/api_guide_am62x/EVM_SETUP_PAGE.html diff --git a/boards/arm/am62x_m4/doc/index.rst b/boards/arm/am62x_m4/doc/index.rst deleted file mode 100644 index c542113e96221a..00000000000000 --- a/boards/arm/am62x_m4/doc/index.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. _am62x_m4: - -AM62x M4F Core -############## - -Overview -******** - -The Texas Instrument AM62x SoC contains a quad Cortex-A53 cluster and a single -Cortex-M4F core in the MCU domain. This chapter describes all boards with support -for the M4F subsystem. - -Currently the following hardware platforms are supported: - -.. toctree:: - :maxdepth: 1 - - am62x_m4_sk.rst - am62x_m4_phyboard_lyra.rst - -Supported Features -================== - -The AM62x M4F platform supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. diff --git a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.board b/boards/arm/apollo4p_blue_kxr_evb/Kconfig.board deleted file mode 100644 index 0ae2283f97d4a5..00000000000000 --- a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Ambiq Micro Inc. - -config BOARD_APOLLO4P_BLUE_KXR_EVB - bool "Ambiq Apollo4 Blue Plus KXR Evaluation Board" - depends on SOC_APOLLO4P_BLUE diff --git a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/arm/apollo4p_blue_kxr_evb/Kconfig.defconfig deleted file mode 100644 index 1edc7b5581bb34..00000000000000 --- a/boards/arm/apollo4p_blue_kxr_evb/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Ambiq Micro Inc. - -config BOARD - default "apollo4p_blue_kxr_evb" - depends on BOARD_APOLLO4P_BLUE_KXR_EVB - -if BT - -config MAIN_STACK_SIZE - default 2048 - -choice BT_HCI_BUS_TYPE - default BT_AMBIQ_HCI -endchoice - -config BT_BUF_ACL_TX_COUNT - default 14 - -config BT_BUF_CMD_TX_SIZE - default 255 - -config BT_BUF_EVT_RX_SIZE - default 255 - -config BT_BUF_ACL_TX_SIZE - default 251 - -config BT_BUF_ACL_RX_SIZE - default 251 - -# L2CAP SDU/PDU TX MTU -# BT_L2CAP_RX_MTU = CONFIG_BT_BUF_ACL_RX_SIZE - BT_L2CAP_HDR_SIZE -config BT_L2CAP_TX_MTU - default 247 - -endif # BT diff --git a/boards/arm/apollo4p_blue_kxr_evb/doc/index.rst b/boards/arm/apollo4p_blue_kxr_evb/doc/index.rst deleted file mode 100644 index 75aa74ac34e58f..00000000000000 --- a/boards/arm/apollo4p_blue_kxr_evb/doc/index.rst +++ /dev/null @@ -1,110 +0,0 @@ -.. _apollo4p_blue_kxr_evb: - -Ambiq Apollo4 Blue Plus KXR EVB -############################### - -Apollo4 Blue Plus KXR EVB is a board by Ambiq featuring their ultra-low power Apollo4 Blue Plus SoC. - -.. image:: ./apollo4-blue-plus-kxr-soc-eval-board.jpg - :align: center - :alt: Apollo4 Blue Plus KXR EVB - -Hardware -******** - -- Apollo4 Blue Plus SoC with upto 192 MHz operating frequency -- ARM® Cortex® M4F core -- 64 kB 2-way Associative/Direct-Mapped Cache per core -- Up to 2 MB of non-volatile memory (NVM) for code/data -- Up to 2.75 MB of low leakage / low power RAM for code/data -- 384 kB Tightly Coupled RAM -- 384 kB Extended RAM -- Bluetooth 5.1 Low Energy - -For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR EVB board: - -- `Apollo4 Blue Plus Website`_ -- `Apollo4 Blue Plus Datasheet`_ -- `Apollo4 Blue Plus KXR EVB Website`_ - -Supported Features -================== - -The Apollo4 Blue Plus KXR EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig``. - -Programming and Debugging -========================= - -Flashing an application ------------------------ - -Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application, then flash it to the device: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: apollo4p_blue_kxr_evb - :goals: flash - -.. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module - to be installed on you host computer. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! apollo4p_blue_kxr_evb - -.. _Apollo4 Blue Plus Website: - https://ambiq.com/apollo4-blue-plus/ - -.. _Apollo4 Blue Plus Datasheet: - https://contentportal.ambiq.com/documents/20123/388410/Apollo4-Blue-Plus-SoC-Datasheet.pdf - -.. _Apollo4 Blue Plus KXR EVB Website: - https://www.ambiq.top/en/apollo4-blue-plus-kxr-soc-eval-board - -.. _SEGGER J-Link software: - https://www.segger.com/downloads/jlink - -.. _pylink: - https://github.com/Square/pylink diff --git a/boards/arm/apollo4p_evb/Kconfig.board b/boards/arm/apollo4p_evb/Kconfig.board deleted file mode 100644 index f6c5256a98dad2..00000000000000 --- a/boards/arm/apollo4p_evb/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -config BOARD_APOLLO4P_EVB - bool "Ambiq Apollo4 Plus Evaluation Board" - depends on SOC_APOLLO4P diff --git a/boards/arm/apollo4p_evb/Kconfig.defconfig b/boards/arm/apollo4p_evb/Kconfig.defconfig deleted file mode 100644 index 0e3d55bc8f82e1..00000000000000 --- a/boards/arm/apollo4p_evb/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -config BOARD - default "apollo4p_evb" - depends on BOARD_APOLLO4P_EVB diff --git a/boards/arm/apollo4p_evb/doc/index.rst b/boards/arm/apollo4p_evb/doc/index.rst deleted file mode 100644 index 42f0f360329613..00000000000000 --- a/boards/arm/apollo4p_evb/doc/index.rst +++ /dev/null @@ -1,105 +0,0 @@ -.. _apollo4p_evb: - -Ambiq Apollo4P EVB -################## - -Apollo4P EVB is a board by Ambiq featuring their ultra-low power Apollo4 Plus SoC. - -.. image:: ./apollo4-plus-soc-eval-board.jpg - :align: center - :alt: Apollo4P EVB - -Hardware -******** - -- Apollo4 Plus SoC with upto 192 MHz operating frequency -- ARM® Cortex® M4F core -- 64 kB 2-way Associative/Direct-Mapped Cache per core -- Up to 2 MB of non-volatile memory (NVM) for code/data -- Up to 2.75 MB of low leakage / low power RAM for code/data -- 384 kB Tightly Coupled RAM -- 384 kB Extended RAM - -For more information about the Apollo4 Plus SoC and Apollo4P EVB board: - -- `Apollo4 Plus Website`_ -- `Apollo4 Plus Datasheet`_ -- `Apollo4P EVB Website`_ - -Supported Features -================== - -The Apollo4P EVB board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| STIMER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/apollo4p_evb/apollo4p_evb_defconfig``. - -Programming and Debugging -========================= - -Flashing an application ------------------------ - -Connect your device to your host computer using the JLINK USB port. -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application, then flash it to the device: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: apollo4p_evb - :goals: flash - -.. note:: - `west flash` requires `SEGGER J-Link software`_ and `pylink`_ Python module - to be installed on you host computer. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! apollo4p_evb - -.. _Apollo4 Plus Website: - https://ambiq.com/apollo4-plus/ - -.. _Apollo4 Plus Datasheet: - https://contentportal.ambiq.com/documents/20123/388415/Apollo4-Plus-SoC-Datasheet.pdf - -.. _Apollo4P EVB Website: - https://www.ambiq.top/en/apollo4-plus-soc-eval-board - -.. _SEGGER J-Link software: - https://www.segger.com/downloads/jlink - -.. _pylink: - https://github.com/Square/pylink diff --git a/boards/arm/arduino_due/Kconfig.board b/boards/arm/arduino_due/Kconfig.board deleted file mode 100644 index 8e0a7ae81b047c..00000000000000 --- a/boards/arm/arduino_due/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Due Board configuration - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_DUE - bool "Arduino Due Board" - depends on SOC_PART_NUMBER_SAM3X8E diff --git a/boards/arm/arduino_due/Kconfig.defconfig b/boards/arm/arduino_due/Kconfig.defconfig deleted file mode 100644 index 13c6fdf57225e0..00000000000000 --- a/boards/arm/arduino_due/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Arduino Due Board configuration - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_DUE - -config BOARD - default "arduino_due" - -endif # BOARD_ARDUINO_DUE diff --git a/boards/arm/arduino_due/arduino_due_defconfig b/boards/arm/arduino_due/arduino_due_defconfig deleted file mode 100644 index 32fa49bd002c35..00000000000000 --- a/boards/arm/arduino_due/arduino_due_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM3X=y -CONFIG_SOC_PART_NUMBER_SAM3X8E=y -CONFIG_BOARD_ARDUINO_DUE=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/arduino_due/doc/index.rst b/boards/arm/arduino_due/doc/index.rst deleted file mode 100644 index cbb5ce62ca5ffd..00000000000000 --- a/boards/arm/arduino_due/doc/index.rst +++ /dev/null @@ -1,214 +0,0 @@ -.. _arduino_due: - -Arduino Due -########### - -Overview -******** - -The arduino_due board configuration is used by Zephyr applications -that run on the Arduino Due board. It provides support for the Atmel -SAM3X8E ARM Cortex-M3 CPU and the following devices: - -* Nested Vectored Interrupt Controller (NVIC) - -* System Tick System Clock (SYSTICK) - -* Serial Port over USB (ATMEL_SAM3) - -More information about the board can be found at the `Arduino Due website`_. -The `Atmel SAM3X8E Datasheet`_ has the information and the datasheet about -the processor. - -.. note:: - This configuration is not supported by Arduino. - -.. image:: img/arduino_due.jpg - :align: center - :alt: Arduino Due - -Hardware -******** -Supported Features -================== - -The arduino_due board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| Watchdog | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not currently supported by the Zephyr kernel. -See `Arduino Due website`_ and `Atmel SAM3X8E Datasheet`_ for a complete -list of Arduino Due board hardware features. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_due/arduino_due_defconfig`. - -.. note:: - For I2C, pull-up resistors are required for using SCL1 and SDA1 (near IO13). - -Interrupt Controller -==================== - -There are 15 fixed exceptions including exceptions 12 (debug monitor) and 15 -(SYSTICK) that behave more as interrupts than exceptions. In addition, there can -be a variable number of IRQs. Exceptions 7-10 and 13 are reserved. They don't -need handlers. - -A Cortex-M3/4-based board uses vectored exceptions. This means each exception -calls a handler directly from the vector table. - -Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here -identifies the handlers used for each exception. - -+------+------------+----------------+-----------------------+ -| Exc# | Name | Remarks | Used by Zephyr Kernel | -+======+============+================+=======================+ -| 1 | Reset | | system initialization | -+------+------------+----------------+-----------------------+ -| 2 | NMI | | system fatal error | -+------+------------+----------------+-----------------------+ -| 3 | Hard fault | | system fatal error | -+------+------------+----------------+-----------------------+ -| 4 | MemManage | MPU fault | system fatal error | -+------+------------+----------------+-----------------------+ -| 5 | Bus | | system fatal error | -+------+------------+----------------+-----------------------+ -| 6 | Usage | undefined | system fatal error | -| | fault | instruction, | | -| | | or switch | | -| | | attempt to ARM | | -| | | mode | | -+------+------------+----------------+-----------------------+ -| 11 | SVC | | system calls, kernel | -| | | | run-time exceptions, | -| | | | and IRQ offloading | -+------+------------+----------------+-----------------------+ -| 12 | Debug | | system fatal error | -| | monitor | | | -+------+------------+----------------+-----------------------+ -| 14 | PendSV | | context switch | -+------+------------+----------------+-----------------------+ -| 15 | SYSTICK | | system clock | -+------+------------+----------------+-----------------------+ - -.. note:: - After a reset, all exceptions have a priority of 0. Interrupts cannot run - at priority 0 for the interrupt locking mechanism and exception handling - to function properly. - -System Clock -============ - -Arduino Due has two external oscillators/resonators. The slow clock is -32.768 kHz, and the main clock is 12 MHz. The processor can set up PLL to drive -the master clock, which can be set as high as 84 MHz. - -Serial Port -=========== - -The Atmel SAM3X8E processor has a single UART that is used by the SAM-BA -bootloader. This UART has only two wires for RX/TX and does not have flow -control (CTS/RTS) or FIFO. The RX/TX pins are connected to the ATmega16U2, -which provides USB-to-TTL serial function. The Zephyr console output, by -default, is utilizing this controller. - - -Programming and Debugging -************************* - -Flashing -======== - -BOSSA Tool ----------- - -Flashing the Zephyr kernel onto Arduino Due requires the `bossa tool`_. - -There are GUI and command line versions of the bossa tool. The following -section provides the steps to build the command line version. Please -refer to the bossa tool's README file on how to build the GUI version. - -To build the bossa tool, follow these steps: - -#. Checkout the bossa tool's code from the repository. - - .. code-block:: console - - $ git clone https://github.com/shumatech/BOSSA.git - $ cd BOSSA - -#. Checkout the arduino branch. The code on the master branch does not - work with Arduino Due. - - .. code-block:: console - - $ git checkout arduino - -#. Build the command line version of the bossa tool. - - .. code-block:: console - - $ make bin/bossac - -#. The resulting binary is available at :file:`bin/bossac`. - - -Flashing an Application to Arduino Due --------------------------------------- - -Applications for the ``arduino_due`` board configuration can be built -and flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. After -building the application, press the Reset button before running the -flash command, so the board will boot into the SAM-BA bootloader and -be prepared to receive the new program. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_due - :goals: build flash - -After flashing the application, run your favorite terminal program to -listen for output. For example, under Linux, the terminal should be -:code:`/dev/ttyACM0`. For example: - -.. code-block:: console - - $ sudo minicom -D /dev/ttyACM0 -o - -The -o option tells minicom not to send the modem initialization -string. - -Now press the Reset button and you should see "Hello World! arduino_due" in your terminal. - -.. note:: - Make sure your terminal program is closed before flashing the binary image, - or it will interfere with the flashing process. - -References -********** - -.. _Arduino Due website: https://www.arduino.cc/en/Main/ArduinoBoardDue - -.. _Atmel SAM3X8E Datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf - -.. _bossa tool: https://github.com/shumatech/BOSSA - -.. _bossa arduino branch: https://github.com/shumatech/BOSSA/tree/arduino diff --git a/boards/arm/arduino_giga_r1/Kconfig.board b/boards/arm/arduino_giga_r1/Kconfig.board deleted file mode 100644 index c810f6f31fc4ae..00000000000000 --- a/boards/arm/arduino_giga_r1/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_GIGA_R1_M7 - bool "Arduino GIGA R1 WiFi Board (M7)" - depends on SOC_STM32H747XX - select CPU_CORTEX_M7 - -config BOARD_ARDUINO_GIGA_R1_M4 - bool "Arduino GIGA R1 WiFi Board (M4)" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/arduino_giga_r1/Kconfig.defconfig b/boards/arm/arduino_giga_r1/Kconfig.defconfig deleted file mode 100644 index e72fb499055f5a..00000000000000 --- a/boards/arm/arduino_giga_r1/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_GIGA_R1_M7 || BOARD_ARDUINO_GIGA_R1_M4 - -config BOARD - default "arduino_giga_r1_m7" if BOARD_ARDUINO_GIGA_R1_M7 - default "arduino_giga_r1_m4" if BOARD_ARDUINO_GIGA_R1_M4 - -if BT - -choice AIROC_PART - default CYW4343W -endchoice - -choice CYW4343W_MODULE - default CYW4343W_MURATA_1DX -endchoice - -endif # BT - -endif # BOARD_ARDUINO_GIGA_R1_M7 || BOARD_ARDUINO_GIGA_R1_M4 diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.yaml b/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.yaml deleted file mode 100644 index 58b71369e123a4..00000000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: arduino_giga_r1_m4 -name: Arduino GIGA R1 WiFi (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - arduino_gpio - - gpio -testing: - ignore_tags: - - mpu - - nfc - - net -vendor: arduino diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4_defconfig b/boards/arm/arduino_giga_r1/arduino_giga_r1_m4_defconfig deleted file mode 100644 index 1ab438cb15a9c2..00000000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m4_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_GIGA_R1_M4=y - -# Enable GPIO -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.yaml b/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.yaml deleted file mode 100644 index 2e844a1480446f..00000000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: arduino_giga_r1_m7 -name: Arduino GIGA R1 WiFi (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - arduino_gpio - - gpio - - arduino_spi - - spi - - memc - - usb_cdc - - usb_device -vendor: arduino diff --git a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7_defconfig b/boards/arm/arduino_giga_r1/arduino_giga_r1_m7_defconfig deleted file mode 100644 index 8f4491908e611a..00000000000000 --- a/boards/arm/arduino_giga_r1/arduino_giga_r1_m7_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright 2023 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_GIGA_R1_M7=y - -# Disable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=n - -# Enable GPIO -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable pin controller -CONFIG_PINCTRL=y - -# Use zephyr,code-partition as flash offset -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_giga_r1/board.cmake b/boards/arm/arduino_giga_r1/board.cmake deleted file mode 100644 index 849f9f933f1fa6..00000000000000 --- a/boards/arm/arduino_giga_r1/board.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_ARDUINO_GIGA_R1_M7) -board_runner_args(jlink "--device=STM32H747XI_M7" "--speed=4000") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m7.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) -elseif(CONFIG_BOARD_ARDUINO_GIGA_R1_M4) -board_runner_args(jlink "--device=STM32H747XI_M4" "--speed=4000") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_arduino_giga_r1_m4.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) -endif() -board_runner_args(dfu-util "--pid=2341:0366" "--alt=0" "--dfuse") -board_runner_args(blackmagicprobe "--connect-rst") - -include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) -include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/arduino_giga_r1/doc/index.rst b/boards/arm/arduino_giga_r1/doc/index.rst deleted file mode 100644 index 2e2b03917cc68a..00000000000000 --- a/boards/arm/arduino_giga_r1/doc/index.rst +++ /dev/null @@ -1,186 +0,0 @@ -.. _arduino_giga_r1_board: - -Arduino GIGA R1 WiFi -#################### - -Overview -******** - -Arduino GIGA R1 WiFi is a development board by Arduino based on the -STM32H747XI, a dual core ARM Cortex-M7 + Cortex-M4 MCU, with 2MBytes of Flash -memory and 1MB SRAM. - -The board features: - -- RGB LED -- Reset and Boot buttons -- USB-C device -- USB Host -- 16MB external QSPI flash -- 8MB external SDRAM -- Murata Type 1DX Bluetooth + WiFi module (CYW4343W based) -- Audio jack -- ATECC608A secure element - -.. image:: img/arduino_giga_r1.jpg - :align: center - :alt: Arduino GIGA R1 WiFi - -More information about the board, including the datasheet, pinout and -schematics, can be found at the `Arduino GIGA website`_. - -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr ``arduino_giga_r1_m7`` board configuration supports the -following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| QSPI | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| RADIO | Murata 1DX | WiFi and Bluetooth module | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr port. - -Fetch Binary Blobs -****************** - -The board Bluetooth/WiFi module requires fetching some binary blob files, to do -that run the command: - -.. code-block:: console - - west blobs fetch hal_infineon - -.. note:: Only Bluetooth functionality is currently supported. - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``arduino_giga_r1`` board should be built per core target, -using either ``arduino_giga_r1_m7`` or ``arduino_giga_r1_m4`` as the target. - -See :ref:`build_an_application` for more information about application builds. - -Flashing -======== - -This board can be flashed either using dfu-util, or with an external debugging -probe, such as a J-Link or Black Magic Probe, connected to the on board MIPI-10 -SWD port marked as "JTAG". - -.. note:: - - The board ships with a custom Arduino bootloader programmed in the first - flash page that can be triggered by double clicking the ``RST`` button. This - bootloader is USB-DFU compatible and supports programming both the internal - and external flash and is the one used by ``west flash`` by default. The - internal STM32 ROM bootloader can also be used by pressing ``RST`` while - holding the ``BOOT0`` button, this also supports USB-DFU but can only - program the internal flash and can overwrite the Arduino bootloader. More - details can be found in the "Boot0" section of the `Arduino GIGA Cheat - Sheet`_. - -First, connect the Arduino GIGA R1 board to your host computer using the USB -port to prepare it for flashing. Double click the ``RST`` button to put the -board into the Arduino Bootloader mode. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_giga_r1_m7 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arduino_giga_r1_m7 - -Similarly, you can build and flash samples on the M4 target. - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: arduino_giga_r1_m4 - :goals: build flash - -Debugging -========= - -Debugging is supported by using ``west debug`` with an external probe such as a -J-Link or Black Magic Probe, connected to the on board MIPI-10 SWD port marked -as "JTAG". For example:: - - west debug -r jlink - -.. _Arduino GIGA website: - https://docs.arduino.cc/hardware/giga-r1-wifi - -.. _Arduino GIGA Cheat Sheet: - https://docs.arduino.cc/tutorials/giga-r1-wifi/cheat-sheet - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html diff --git a/boards/arm/arduino_mkrzero/Kconfig.board b/boards/arm/arduino_mkrzero/Kconfig.board deleted file mode 100644 index aa80faec588f9e..00000000000000 --- a/boards/arm/arduino_mkrzero/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino MKR Zero Board configuration - -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_MKRZERO - bool "Arduino MKR Zero" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/arduino_mkrzero/Kconfig.defconfig b/boards/arm/arduino_mkrzero/Kconfig.defconfig deleted file mode 100644 index 988edd82f1ba4b..00000000000000 --- a/boards/arm/arduino_mkrzero/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Arduino MKR Zero board configuration - -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "arduino_mkrzero" - depends on BOARD_ARDUINO_MKRZERO - -if DISK_DRIVERS - -config DISK_DRIVER_SDMMC - default y - -config SPI - default y - -config GPIO - default y - -endif # DISK_DRIVERS diff --git a/boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig b/boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig deleted file mode 100644 index 2101e5a8332c1e..00000000000000 --- a/boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ARDUINO_MKRZERO=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ARDUINO=y -CONFIG_GPIO=y diff --git a/boards/arm/arduino_mkrzero/doc/index.rst b/boards/arm/arduino_mkrzero/doc/index.rst deleted file mode 100644 index a64a9248bd03e2..00000000000000 --- a/boards/arm/arduino_mkrzero/doc/index.rst +++ /dev/null @@ -1,183 +0,0 @@ -.. _arduino_mkrzero: - -Arduino MKR Zero -#################### - -Overview -******** - -The Arduino MKR Zero built with smaller MKR form factor and powered by Atmel's SAMD21 MCU. -This board come with microSD card holder that allows you to play with music files with no extra hardware. - -.. image:: img/arduino_mkrzero.jpg - :align: center - :alt: Arduino MKR Zero - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One user LEDs -- One reset button -- microSD card slot -- ATECC508A secure element - -Supported Features -================== - -The arduino_mkrzero board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| ADC | on-chip | Analog to digital converter | -+-----------+------------+------------------------------------------+ -| COUNTER | on-chip | Pulse counter | -+-----------+------------+------------------------------------------+ -| DMA | on-chip | Direct memory access unit | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info and serial number | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit ports | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_mkrzero/arduino_mkrzero_defconfig`. - -Connections and IOs -=================== - -The `Arduino store`_ has detailed information about board -connections. Download the `Arduino MKR Zero Schematic`_ for more detail. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 13(PA23) and 14(PA22). - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino MKR Zero, SERCOM1 -is available on pin 8, 9, and 10. -SERCOM2 connect to microSD card slot as SPI interface. - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based I2Cs. SERCOM0 is available on pin 11(PA08) and 12(PA09). -This I2C bus also available as ESLOV(JST SH 5pin) socket. -ATECC508A secure element is connect to this I2C bus. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -DAC -=== - -The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the -Arduino MKR Zero, the DAC is available on pin A0. - -Programming and Debugging -************************* - -The Arduino MKR Zero ships the BOSSA compatible bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_mkrzero - :goals: build - :compact: - -#. Connect the MKR Zero to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_mkrzero - :goals: flash - :compact: - - You should see "Hello World! arduino_mkrzero" in your terminal. - -References -********** - -.. target-notes:: - -.. _Arduino Store: - https://store.arduino.cc/collections/boards/products/arduino-mkr-zero-i2s-bus-sd-for-sound-music-digital-audio-data - -.. _Arduino MKR Zero Schematic: - https://www.arduino.cc/en/uploads/Main/ArduinoMKRZero-schematic.pdf diff --git a/boards/arm/arduino_nano_33_ble/Kconfig.board b/boards/arm/arduino_nano_33_ble/Kconfig.board deleted file mode 100644 index 2492aea4c91ae8..00000000000000 --- a/boards/arm/arduino_nano_33_ble/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2020 Jefferson Lee. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_NANO_33_BLE - bool "Arduino Nano 33 BLE board" - depends on SOC_NRF52840_QIAA - -config BOARD_ARDUINO_NANO_33_BLE_SENSE - bool "Arduino Nano 33 BLE Sense board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/arduino_nano_33_ble/Kconfig.defconfig b/boards/arm/arduino_nano_33_ble/Kconfig.defconfig deleted file mode 100644 index 382e71f7e9feec..00000000000000 --- a/boards/arm/arduino_nano_33_ble/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020 Jefferson Lee. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_NANO_33_BLE || BOARD_ARDUINO_NANO_33_BLE_SENSE - -config BOARD - default "arduino_nano_33_ble" if BOARD_ARDUINO_NANO_33_BLE - default "arduino_nano_33_ble_sense" if BOARD_ARDUINO_NANO_33_BLE_SENSE - -config BT_CTLR - default BT - -config REGULATOR - default y if SENSOR - -endif # BOARD_ARDUINO_NANO_33_BLE || BOARD_ARDUINO_NANO_33_BLE_SENSE diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.yaml b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.yaml deleted file mode 100644 index cdd9ead370c0e5..00000000000000 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: arduino_nano_33_ble_sense -name: Arduino Nano 33 BLE Sense -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - ble - - i2c - - pwm - - serial - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: arduino diff --git a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense_defconfig b/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense_defconfig deleted file mode 100644 index 024c659ad377b7..00000000000000 --- a/boards/arm/arduino_nano_33_ble/arduino_nano_33_ble_sense_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_ARDUINO_NANO_33_BLE_SENSE=y - -# Enable MPU -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -# enable peripherals -CONFIG_GPIO=y -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable sam-ba bootloader on legacy mode -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_LEGACY=y diff --git a/boards/arm/arduino_nano_33_iot/Kconfig.board b/boards/arm/arduino_nano_33_iot/Kconfig.board deleted file mode 100644 index 87c65a0f142842..00000000000000 --- a/boards/arm/arduino_nano_33_iot/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Nano 33 IOT board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_NANO_33_IOT - bool "Arduino Nano 33 IOT" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/arduino_nano_33_iot/Kconfig.defconfig b/boards/arm/arduino_nano_33_iot/Kconfig.defconfig deleted file mode 100644 index b4fc2bbc21fe1f..00000000000000 --- a/boards/arm/arduino_nano_33_iot/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Nano 33 IOT board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "arduino_nano_33_iot" - depends on BOARD_ARDUINO_NANO_33_IOT diff --git a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig b/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig deleted file mode 100644 index 3bc5a6370aa4c1..00000000000000 --- a/boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ARDUINO_NANO_33_IOT=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ARDUINO=y diff --git a/boards/arm/arduino_nano_33_iot/doc/index.rst b/boards/arm/arduino_nano_33_iot/doc/index.rst deleted file mode 100644 index 62353ecbe1eb9a..00000000000000 --- a/boards/arm/arduino_nano_33_iot/doc/index.rst +++ /dev/null @@ -1,171 +0,0 @@ -.. _arduino_nano_33_iot: - -Arduino Nano 33 IOT -################### - -Overview -******** - -The Arduino Nano 33 IOT is a small form factor development board with USB, -Wifi, Bluetooth, a 6 axis IMU, and secure element. - -.. image:: img/nano_33_iot.jpg - :align: center - :alt: Arduino Nano 33 IOT - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- One user LED -- One reset button -- Native USB port -- Wifi and Bluetooth via a u-blox NINA-W102 -- ATECC608A secure element -- LSM6DS3 six axis accelerometer and gyro - -Supported Features -================== - -The arduino_nano_33_iot board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| ADC | on-chip | Analog to digital converter | -+-----------+------------+------------------------------------------+ -| COUNTER | on-chip | Pulse counter | -+-----------+------------+------------------------------------------+ -| DMA | on-chip | Direct memory access unit | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info and serial number | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_nano_33_iot/arduino_nano_33_iot_defconfig`. - -Connections and IOs -=================== - -The `Arduino store`_ has detailed information about board -connections. Download the `schematic`_ for more detail. - -System Clock -============ - -The SAMD21 MCU is configured to use the 8 MHz internal oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. SERCOM5 is available on pins 1 and 2. - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC2 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. SERCOM1 is available on pins 1, 14, -and 15. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -Programming and Debugging -************************* - -The Nano 33 IOT ships the BOSSA compatible UF2 bootloader. The -bootloader can be entered by quickly tapping the reset button twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_nano_33_iot - :goals: build - :compact: - -#. Connect the Nano 33 IOT to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_nano_33_iot - :goals: flash - :compact: - - You should see "Hello World! arduino_nano_33_iot" in your terminal. - -References -********** - -.. target-notes:: - -.. _Arduino Store: - https://store.arduino.cc/arduino-nano-33-iot - -.. _schematic: - https://content.arduino.cc/assets/NANO33IoTV2.0_sch.pdf diff --git a/boards/arm/arduino_nicla_sense_me/Kconfig.board b/boards/arm/arduino_nicla_sense_me/Kconfig.board deleted file mode 100644 index 47e9aabfbb2fe0..00000000000000 --- a/boards/arm/arduino_nicla_sense_me/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Nicla Sense ME board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_NICLA_SENSE_ME - bool "Arduino Nicla Sense ME" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/arduino_nicla_sense_me/Kconfig.defconfig b/boards/arm/arduino_nicla_sense_me/Kconfig.defconfig deleted file mode 100644 index c0293cec5c9b5f..00000000000000 --- a/boards/arm/arduino_nicla_sense_me/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Arduino Nicla Sense ME board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_NICLA_SENSE_ME - -config BOARD - default "arduino_nicla_sense_me" - -config BT_CTLR - default BT - -endif # BOARD_ARDUINO_NICLA_SENSE_ME diff --git a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me_defconfig b/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me_defconfig deleted file mode 100644 index c2f2b95cc7234f..00000000000000 --- a/boards/arm/arduino_nicla_sense_me/arduino_nicla_sense_me_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_ARDUINO_NICLA_SENSE_ME=y - -# Enable MPU -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/arduino_opta_m4/Kconfig.board b/boards/arm/arduino_opta_m4/Kconfig.board deleted file mode 100644 index cce1cd6337add6..00000000000000 --- a/boards/arm/arduino_opta_m4/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_OPTA_M4 - bool "Arduino OPTA Programmable Logic Controller M4 Core" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/arduino_opta_m4/Kconfig.defconfig b/boards/arm/arduino_opta_m4/Kconfig.defconfig deleted file mode 100644 index be17c009555e0e..00000000000000 --- a/boards/arm/arduino_opta_m4/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_OPTA_M4 - -config BOARD - default "arduino_opta_m4" - -endif # BOARD_ARDUINO_OPTA_M4 diff --git a/boards/arm/arduino_opta_m4/arduino_opta_m4.yaml b/boards/arm/arduino_opta_m4/arduino_opta_m4.yaml deleted file mode 100644 index 4030cb402f6671..00000000000000 --- a/boards/arm/arduino_opta_m4/arduino_opta_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: arduino_opta_m4 -name: ARDUINO OPTA (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 512 -supported: - - gpio -testing: - ignore_tags: - - mpu - - nfc - - net - - flash - - input - - mcumgr -vendor: arduino diff --git a/boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig b/boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig deleted file mode 100644 index bcf01ccabfbe7c..00000000000000 --- a/boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2023 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -CONFIG_BOARD_ARDUINO_OPTA_M4=y - -# enable GPIO -CONFIG_GPIO=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y - -# Use zephyr,code-partition as flash offset -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/arduino_opta_m4/doc/index.rst b/boards/arm/arduino_opta_m4/doc/index.rst deleted file mode 100644 index 90f9497db33a44..00000000000000 --- a/boards/arm/arduino_opta_m4/doc/index.rst +++ /dev/null @@ -1,177 +0,0 @@ -.. _arduino_opta_m4_board: - -Arduino OPTA M4-Core -####################### - -Overview -******** - -The Arduino™ Opta® is a secure micro Programmable Logic Controller (PLC) -with Industrial Internet of Things (IoT) capabilities. - -Developed in partnership with Finder®, this device supports both the Arduino -programming language and standard IEC-61131-3 PLC programming languages, -such as Ladder Diagram (LD), Sequential Function Chart (SFC), -Function Block Diagram (FBD), Structured Text (ST), and Instruction List (IL), -making it an ideal device for automation engineers. - -For Zephyr RTOS, only the M4 is supported for now, making the M7 run the PLC -tasks while the M4 core under Zephyr acts as a coprocessor. - -Additionally, the device features: - -- Ethernet compliant with IEEE802.3-2002 -- 16MB QSPI Flash -- 4 x green color status LEDs -- 1 x user push-button -- 1 x reset push-button accessible via pinhole -- 8 x analog inputs -- 4 x isolated relay outputs - -.. image:: img/arduino_opta.jpeg - :align: center - :alt: ARDUINO-OPTA - -More information about the board can be found at the `ARDUINO-OPTA website`_. -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr arduino_opta_m4 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig files: -``boards/arm/arduino_opta_m4/arduino_opta_m4_defconfig`` - -Pin Mapping -=========== - -ARDUINO OPTA M4 has access to the 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `ARDUINO-OPTA website`_. - -Default Zephyr Peripheral Mapping ---------------------------------- - -- Status LED1 : PI0 -- Status LED2 : PI1 -- Status LED3 : PI3 -- Status LED4 : PH15 -- User button : PE4 - -System Clock -============ - -The STM32H747I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the CPU2 (Cortex-M4) System clock -is driven at 240MHz. PLL clock is fed by a 25MHz high speed external clock. - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``arduino_opta_m4`` use the regular Zephyr build commands. -See :ref:`build_an_application` for more information about application builds. - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. The OPTA has a DFU capable bootloader which -can be accessed by connecting the device to the USB, and then pressing -the RESET button shortly twice, the RESET-LED on the board will fade -indicating the board is in bootloader mode. - -By default: - - - CPU2 (Cortex-M4) boot address is set to 0x08180000 (OB: BOOT_CM4_ADD0) - -Zephyr flash configuration has been set to meet these default settings. - -Flashing an application to ARDUINO OPTA M4 ------------------------------------------- - -First, connect the device to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: arduino_opta_m4 - :goals: build flash - -Starting the application on the ARDUINO OPTA M4 ------------------------------------------------ - -Make sure the option bytes are set to prevent the M4 from auto-starting, and -that the M7 side starts the M4 at the correct Flash address. - -This can be done by selecting in the Arduino IDE's "Tools" / "Flash Split" -menu the "1.5MB M7 + 0.5MB M4" option, and loading a sketch that contains -at least the following code: - - .. code-block:: cpp - - #include - - void setup() { - RPC.begin(); - } - - void loop() { } - -Debugging -========= - -Debugging is not yet supported by this board, since the debug port does -not have an easy access. - -.. _ARDUINO-OPTA website: - https://docs.arduino.cc/hardware/opta - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf diff --git a/boards/arm/arduino_portenta_h7/CMakeLists.txt b/boards/arm/arduino_portenta_h7/CMakeLists.txt deleted file mode 100644 index 6aaa80fcf41d76..00000000000000 --- a/boards/arm/arduino_portenta_h7/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_ARDUINO_PORTENTA_H7_M7) - -zephyr_library() -zephyr_library_sources(board.c) - -endif() diff --git a/boards/arm/arduino_portenta_h7/Kconfig.board b/boards/arm/arduino_portenta_h7/Kconfig.board deleted file mode 100644 index 75e401c5d4b65a..00000000000000 --- a/boards/arm/arduino_portenta_h7/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Arduino Portenta H7 board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_PORTENTA_H7_M7 - bool "Arduino Portenta H7 Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M7 - -config BOARD_ARDUINO_PORTENTA_H7_M4 - bool "Arduino Portenta H7 Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/arduino_portenta_h7/Kconfig.defconfig b/boards/arm/arduino_portenta_h7/Kconfig.defconfig deleted file mode 100644 index 7b537a6e466391..00000000000000 --- a/boards/arm/arduino_portenta_h7/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Arduino Portenta H7 board configuration - -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_PORTENTA_H7_M7 || BOARD_ARDUINO_PORTENTA_H7_M4 - -config BOARD - default "arduino_portenta_h7_m7" if BOARD_ARDUINO_PORTENTA_H7_M7 - default "arduino_portenta_h7_m4" if BOARD_ARDUINO_PORTENTA_H7_M4 - -endif # BOARD_ARDUINO_PORTENTA_H7_M7 || BOARD_ARDUINO_PORTENTA_H7_M4 diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.yaml b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.yaml deleted file mode 100644 index b84e35835c616c..00000000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: arduino_portenta_h7_m4 -name: Arduino Portenta H7 (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - gpio -testing: - ignore_tags: - - mpu - - nfc -vendor: arduino diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4_defconfig b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4_defconfig deleted file mode 100644 index bb6c8c99951395..00000000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m4_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_PORTENTA_H7_M4=y - -# Enable GPIO -CONFIG_GPIO=y - -# Clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable pin controller -CONFIG_PINCTRL=y - -# Enable uart driver -# CONFIG_SERIAL=y - -# By default CONSOLE is assigned to m7 -# CONFIG_CONSOLE=y -# CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.yaml b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.yaml deleted file mode 100644 index af23aee83d4a99..00000000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: arduino_portenta_h7_m7 -name: Arduino Portenta H7 (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - gpio -vendor: arduino diff --git a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7_defconfig b/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7_defconfig deleted file mode 100644 index f7e1a108631ce6..00000000000000 --- a/boards/arm/arduino_portenta_h7/arduino_portenta_h7_m7_defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2022 Benjamin Björnsson . -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_ARDUINO_PORTENTA_H7_M7=y - -# Enable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable pin controller -CONFIG_PINCTRL=y - -# Use zephyr,code-partition as flash offset -CONFIG_USE_DT_CODE_PARTITION=y - -# Disable following to assign serial ports to m4 core - -# Enable uart driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable regulator -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED=y diff --git a/boards/arm/arduino_portenta_h7/doc/index.rst b/boards/arm/arduino_portenta_h7/doc/index.rst deleted file mode 100644 index 999a659f7732d8..00000000000000 --- a/boards/arm/arduino_portenta_h7/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _arduino_portenta_h7_board: - -Arduino Portenta H7 -####################### - -Overview -******** - -The Portenta H7 enables a wide diversity of applications taking benefit -from Computer Vision, PLCs, Robotics controller, High-end industrial machinery -and high-speed booting computation (ms). - -The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, -with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, -large set of peripherals, SMPS, and MIPI-DSI. - -Additionally, the board features: -- USB OTG FS -- 3 color user LEDs - -.. image:: img/arduino_portenta_h7.jpeg - :width: 500px - :align: center - :height: 325px - :alt: ARDUINO_PORTENTA_H7 - -More information about the board can be found at the `ARDUINO_PORTENTA_H7 website`_. -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr arduino_portenta_h7 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Building and Flashing -************************* - -Applications for the ``arduino_portenta_h7`` board should be built per core target, -using either ``arduino_portenta_h7_m7`` or ``arduino_portenta_h7_m4`` as the target. -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Installing dfu-util -------------------- - -This board requires dfu-utils for flashing. It is recommended to use at least -v0.8 of `dfu-util`_. The package available in debian/ubuntu can be quite old, so you might -have to build dfu-util from source. - -Flashing an application to STM32H747I M7 Core ---------------------------------------------- - -First, connect the Arduino Portenta H7 board to your host computer using -the USB port to prepare it for flashing. Double tap the button to put the board -into the Arduino Bootloader mode. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_portenta_h7_m7 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arduino_portenta_m7 - -Similarly, you can build and flash samples on the M4 target. For this, please -take care of the resource sharing (UART port used for console for instance). - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: arduino_portenta_h7_m4 - :goals: build flash - -.. _ARDUINO_PORTENTA_H7 website: - https://docs.arduino.cc/hardware/portenta-h7 - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html diff --git a/boards/arm/arduino_uno_r4/Kconfig.board b/boards/arm/arduino_uno_r4/Kconfig.board deleted file mode 100644 index d56eff75387fa9..00000000000000 --- a/boards/arm/arduino_uno_r4/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_UNO_R4_MINIMA - bool "Arduino Uno R4 Minima board" - depends on SOC_R7FA4M1AB3CFM diff --git a/boards/arm/arduino_uno_r4/Kconfig.defconfig b/boards/arm/arduino_uno_r4/Kconfig.defconfig deleted file mode 100644 index 2d483f3bb384ba..00000000000000 --- a/boards/arm/arduino_uno_r4/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARDUINO_UNO_R4_MINIMA - -config BOARD - default "arduino_uno_r4_minima" if BOARD_ARDUINO_UNO_R4_MINIMA - -endif # BOARD_ARDUINO_UNO_R4_MINIMA diff --git a/boards/arm/arduino_zero/Kconfig.board b/boards/arm/arduino_zero/Kconfig.board deleted file mode 100644 index 646e4020e420e6..00000000000000 --- a/boards/arm/arduino_zero/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Zero Board configuration - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARDUINO_ZERO - bool "Arduino Zero" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/arduino_zero/Kconfig.defconfig b/boards/arm/arduino_zero/Kconfig.defconfig deleted file mode 100644 index 9cd148585cb269..00000000000000 --- a/boards/arm/arduino_zero/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Arduino Zero board configuration - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "arduino_zero" - depends on BOARD_ARDUINO_ZERO diff --git a/boards/arm/arduino_zero/arduino_zero_defconfig b/boards/arm/arduino_zero/arduino_zero_defconfig deleted file mode 100644 index 2448a6a65d0cd8..00000000000000 --- a/boards/arm/arduino_zero/arduino_zero_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_ARDUINO_ZERO=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y diff --git a/boards/arm/arduino_zero/doc/index.rst b/boards/arm/arduino_zero/doc/index.rst deleted file mode 100644 index 4c686daff5e055..00000000000000 --- a/boards/arm/arduino_zero/doc/index.rst +++ /dev/null @@ -1,166 +0,0 @@ -.. _arduino_zero: - -Arduino/Genuino Zero -#################### - -Overview -******** - -The Arduino Zero is a maker-friendly development board with -Atmel’s Embedded Debugger (EDBG), which provides a full -debug interface without the need for additional hardware. - -.. image:: img/arduino_zero.jpg - :align: center - :alt: Arduino Zero - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- 3 user LEDs -- One reset button -- On-board USB based EDBG unit with serial console -- Native USB port - -Supported Features -================== - -The arduino_zero board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| DAC | on-chip | Digital to analogue converter | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/arduino_zero/arduino_zero_defconfig`. - -Connections and IOs -=================== - -The `Arduino store`_ has detailed information about board -connections. Download the `Arduino Zero Schematic`_ for more detail. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. One of the USARTs -(SERCOM5) is connected to the onboard Atmel Embedded Debugger (EDBG). -SERCOM0 is available on the D0/D1 pins. - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC2 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the Arduino Zero, SERCOM4 -is available on the 6 pin connector at the edge of the board. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -DAC -=== - -The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On the -Arduino Zero, the DAC is available on pin A0. - -Programming and Debugging -************************* - -The Arduino Zero comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMD21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_zero - :goals: build - :compact: - -#. Connect the Arduino Zero to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arduino_zero - :goals: flash - :compact: - - You should see "Hello World! arduino_zero" in your terminal. - -References -********** - -.. target-notes:: - -.. _Arduino Store: - https://store.arduino.cc/genuino-zero - -.. _Arduino Zero Schematic: - https://www.arduino.cc/en/uploads/Main/Zero_V1.0.pdf diff --git a/boards/arm/arty/CMakeLists.txt b/boards/arm/arty/CMakeLists.txt deleted file mode 100644 index 1c060b9bbac2f1..00000000000000 --- a/boards/arm/arty/CMakeLists.txt +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(board.c) - -if((CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1) AND (CONFIG_BUILD_OUTPUT_BIN)) - # Generate zephyr.mem verilog memory hex dump file for initialising ITCM in - # Xilinx Vivado. - # - # This ought to be done using the objcopy verilog bfd, but it contains a bug - # affecting endianness: https://sourceware.org/bugzilla/show_bug.cgi?id=25202 - # - # Instead we use bin2hex from the SiFive elf2hex package, if available. - # https://github.com/sifive/elf2hex - find_program(BIN2HEX ${CROSS_COMPILE_TARGET}-bin2hex) - - if(NOT ${BIN2HEX} STREQUAL BIN2HEX-NOTFOUND) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${BIN2HEX} - ARGS --bit-width 32 - ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} - ) - message(STATUS "Verilog memory hex dump will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem") - else() - message(STATUS "The bin2hex (${CROSS_COMPILE_TARGET}-bin2hex) utility was not found, verilog memory hex dump file cannot be generated") - endif() -endif() diff --git a/boards/arm/arty/Kconfig b/boards/arm/arty/Kconfig deleted file mode 100644 index 78b1d148b51538..00000000000000 --- a/boards/arm/arty/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Digilent Arty board configuration - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INIT_PRIORITY - int "Board initialization priority" - default 50 - depends on BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - depends on "$(dt_nodelabel_enabled,daplink_qspi_mux)" - help - Board initialization priority. The board initialization must take - place after the GPIO driver is initialized. diff --git a/boards/arm/arty/Kconfig.board b/boards/arm/arty/Kconfig.board deleted file mode 100644 index 17a6e659748897..00000000000000 --- a/boards/arm/arty/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Digilent Arty board configuration - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ARTY_A7_ARM_DESIGNSTART_M1 - bool "Digilent Arty A7 ARM DesignStart Cortex-M1" - depends on SOC_SERIES_ARM_DESIGNSTART - -config BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - bool "Digilent Arty A7 ARM DesignStart Cortex-M3" - depends on SOC_SERIES_ARM_DESIGNSTART diff --git a/boards/arm/arty/Kconfig.defconfig b/boards/arm/arty/Kconfig.defconfig deleted file mode 100644 index c298a64aaf3ca4..00000000000000 --- a/boards/arm/arty/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Digilent Arty board configuration - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - -config BOARD - default "arty_a7_arm_designstart_m1" if BOARD_ARTY_A7_ARM_DESIGNSTART_M1 - default "arty_a7_arm_designstart_m3" if BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - -config CPU_CORTEX_M_HAS_SYSTICK - default y - -config CPU_HAS_ARM_MPU - default y if BOARD_ARTY_A7_ARM_DESIGNSTART_M3 - -config NUM_IRQS - default 7 - -config GPIO - default y if "$(dt_nodelabel_enabled,daplink_qspi_mux)" - -endif # BOARD_ARTY_A7_ARM_DESIGNSTART_M1 || BOARD_ARTY_A7_ARM_DESIGNSTART_M3 diff --git a/boards/arm/arty/arty_a7_arm_designstart_m1.yaml b/boards/arm/arty/arty_a7_arm_designstart_m1.yaml deleted file mode 100644 index 22068def69007e..00000000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m1.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: arty_a7_arm_designstart_m1 -name: Digilent Arty A7 ARM DesignStart Cortex-M1 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 64 -supported: - - flash - - spi - - gpio diff --git a/boards/arm/arty/arty_a7_arm_designstart_m1_defconfig b/boards/arm/arty/arty_a7_arm_designstart_m1_defconfig deleted file mode 100644 index a3ad6770d45df5..00000000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m1_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ARM_DESIGNSTART=y -CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1=y -CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/arty_a7_arm_designstart_m3.yaml b/boards/arm/arty/arty_a7_arm_designstart_m3.yaml deleted file mode 100644 index 3ea0ebbe1b09e1..00000000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m3.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: arty_a7_arm_designstart_m3 -name: Digilent Arty A7 ARM DesignStart Cortex-M3 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 32 -supported: - - flash - - spi - - gpio diff --git a/boards/arm/arty/arty_a7_arm_designstart_m3_defconfig b/boards/arm/arty/arty_a7_arm_designstart_m3_defconfig deleted file mode 100644 index 3753680a072eaa..00000000000000 --- a/boards/arm/arty/arty_a7_arm_designstart_m3_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ARM_DESIGNSTART=y -CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y -CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M3=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 -CONFIG_ARM_MPU=y - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/board.cmake b/boards/arm/arty/board.cmake deleted file mode 100644 index 529c142aa287db..00000000000000 --- a/boards/arm/arty/board.cmake +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M1) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg") - board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load") - - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -elseif(CONFIG_BOARD_ARTY_A7_ARM_DESIGNSTART_M3) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m3.cfg") - board_runner_args(jlink "--device=Cortex-M3" "--reset-after-load") - - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -endif() diff --git a/boards/arm/arty/doc/index.rst b/boards/arm/arty/doc/index.rst deleted file mode 100644 index 58f0e467f6c51d..00000000000000 --- a/boards/arm/arty/doc/index.rst +++ /dev/null @@ -1,228 +0,0 @@ -.. _arty: - -Digilent Arty -############# - -Overview -******** - -The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers -and hobbyists. The Arty is available in several configurations, each with a -different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series). - -Each board is equipped with on-board JTAG for FPGA programming and debugging, -LEDs, switches, buttons, DDR3 RAM, and QSPI flash for storing the FPGA -bitstream. - -.. figure:: arty_a7-35.jpg - :align: center - :alt: Digilent Arty A7-35 - - Digilent Arty A7-35 (Credit: Digilent Inc) - -The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a -so-called soft processor to be instantiated within the FPGA in order to run -Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr. - -ARM Cortex-M1/M3 DesignStart FPGA -********************************* - -One way of instantiating soft processors on the Arty is using the `ARM -DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports -both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design -targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3 -design only targets the Artix-7 based boards. Zephyr only supports the Artix-7 -targeted designs for now. - -For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the -following websites: - -- `Technical Resources for DesignStart FPGA`_ -- `Technical Resources for DesignStart FPGA on Xilinx`_ -- `ARM DesignStart FPGA Xilinx FAQs`_ - -Supported Features -================== - -The ``arty_a7_arm_designstart_m1`` board configuration supports the following -hardware features of the Cortex-M1 reference design: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio, non-interrupt | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| QSPI | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ - -The default configuration for the Cortex-M1 can be found in the defconfig file: -:file:`boards/arm/arty/arty_a7_arm_designstart_m1_defconfig`. - -In addition to the above, the ``arty_a7_arm_designstart_m3`` board configuration -supports the following hardware features of the Cortex-M3 reference design: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | Memory Protection Unit | -+-----------+------------+-------------------------------------+ - -The default configuration for the Cortex-M3 can be found in the defconfig file: -:file:`boards/arm/arty/arty_a7_arm_designstart_m3_defconfig`. - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The Cortex-M1 reference design is configured to use the 100 MHz external -oscillator on the board as CPU system clock whereas the Cortex-M3 reference -design is configured for 50MHz CPU system clock. - -Serial Port -=========== - -The reference design contains one Xilinx UART Lite. This UART is configured as -console and is accessible through the on-board JTAG adapter via USB connector -``J10``. - -Connecting the Debug Probes -=========================== - -Two different debug probes are needed in order to program the board; the -on-board Digilent JTAG connected to the FPGA, and an external Serial Wire Debug -(SWD) capable debug probe connected to the ARM Cortex-M1 CPU. - -The on-board JTAG is used for configuring and debugging the Xilinx FPGA -itself. It is available on USB connector ``J10``. - -The external SWD debug probe can be connected to connector ``J4`` (``nSRST`` on -``IO39``, ``SWDIO`` on ``IO40``, and ``SWCLK`` on ``IO41``). Another option is -to use the dedicated :ref:`v2c_daplink_shield`. - -Programming and Debugging -************************* - -First, configure the FPGA with the selected reference design FPGA bitstream -using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA -Xilinx edition user guide (available as part of the reference design download -from `Technical Resources for DesignStart FPGA on Xilinx`_). - -Another option for configuring the FPGA with the reference design bitstream is -to use the :ref:`openocd-debug-host-tools`: - -.. code-block:: console - - openocd -f board/arty_s7.cfg -c "init;\ - pld load 0 m1_for_arty_a7_reference.bit;\ - shutdown" - -or: - -.. code-block:: console - - openocd -f board/arty_s7.cfg -c "init;\ - pld load 0 m3_for_arty_a7_reference.bit;\ - shutdown" - -.. note:: - - The pre-built FPGA bitstream only works for Arty boards equipped with an - Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream - must be rebuilt. - -Next, build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Console -===================== - -The UART console is available via the on-board JTAG on USB connector -``J10``. The on-board JTAG will enumerate as two USB serial ports. The UART is -typically available on the second serial port. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for building and flashing the :ref:`hello_world` application -for the Cortex-M1 reference design: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arty_a7_arm_designstart_m1 - :goals: flash - -After flashing, you should see message similar to the following in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.3.99 *** - Hello World! arty_a7_arm_designstart_m1 - -The same procedure can be used for the Cortex-M3 reference design. - -Note, however, that the application was not persisted in flash memory by the -above steps. It was merely written to internal block RAM in the FPGA. It will -revert to the application stored in the block RAM within the FPGA bitstream -the next time the FPGA is configured. - -The steps to persist the application within the FPGA bitstream are covered by -the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the -:kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the `SiFive elf2hex`_ package -is available, the build system will automatically generate a Verilog memory hex -dump :file:`zephyr.mem` file suitable for initialising the block RAM using -`Xilinx Vivado`_. - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: arty_a7_arm_designstart_m1 - :goals: debug - -Step through the application in your debugger, and you should see a message -similar to the following in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.3.99 *** - Hello World! arty_a7_arm_designstart_m1 - -.. _Digilent Arty: - https://store.digilentinc.com/arty - -.. _ARM DesignStart FPGA: - https://www.arm.com/resources/designstart/designstart-fpga - -.. _Technical Resources for DesignStart FPGA: - https://developer.arm.com/ip-products/designstart/fpga - -.. _Technical Resources for DesignStart FPGA on Xilinx: - https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx - -.. _ARM DesignStart FPGA Xilinx FAQs: - https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx-faqs - -.. _SiFive elf2hex: - https://github.com/sifive/elf2hex - -.. _Xilinx Vivado: - https://www.xilinx.com/products/design-tools/vivado.html diff --git a/boards/arm/ast1030_evb/Kconfig.board b/boards/arm/ast1030_evb/Kconfig.board deleted file mode 100644 index 464e3f9370511c..00000000000000 --- a/boards/arm/ast1030_evb/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Aspeed AST1030 evaluation board configuration -# -# Copyright (c) 2021 Aspeed Technology Inc. - -config BOARD_AST1030_EVB - bool "ASPEED AST1030 Evaluation Board" - depends on SOC_AST1030 diff --git a/boards/arm/ast1030_evb/Kconfig.defconfig b/boards/arm/ast1030_evb/Kconfig.defconfig deleted file mode 100644 index 9402846fdade4e..00000000000000 --- a/boards/arm/ast1030_evb/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Aspeed AST1030 evaluation board configuration -# -# Copyright (c) 2021 Aspeed Technology Inc. - -if BOARD_AST1030_EVB -config BOARD - default "ast1030_evb" -endif # BOARD_AST1030_EVB diff --git a/boards/arm/ast1030_evb/doc/index.rst b/boards/arm/ast1030_evb/doc/index.rst deleted file mode 100644 index 0e00488b727217..00000000000000 --- a/boards/arm/ast1030_evb/doc/index.rst +++ /dev/null @@ -1,93 +0,0 @@ -.. _ast1030_evb: - -AST1030_EVB -################### - -Overview -******** - -The AST1030_EVB kit is a development platform to evaluate the -Aspeed AST10x0 series SOCs. This board needs to be mated with -part number AST1030. - -.. image:: ast1030_evb.jpg - :align: center - :alt: AST1030 Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 768 KB on-chip SRAM for instruction and data memory -- 1 MB on-chip Flash memory for boot ROM and data storage -- SPI interface -- UART interface -- I2C/I3C interface -- FAN PWM interface -- ADC interface -- JTAG interface -- USB interface -- LPC interface -- eSPI interface - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/ast1030_evb/ast1030_evb_defconfig`` - - -Connections and IOs -=================== - -Aspeed to provide the schematic for this board. - -System Clock -============ - -The AST1030 SOC is configured to use external 25MHz clock input to generate 200Mhz system clock by -the on-chip PLL. - -Serial Port -=========== - -UART5 is configured for serial logs. The default serial setup is 115200 8N1. - - -Programming and Debugging -************************* - -This board comes with a JTAG port which facilitates debugging using a single physical connection. - -Flashing -======== - -Build application as usual for the ``ast1030_evb`` board, and flash -using SF100 SPI Flash programmer. See the -`Aspeed Zephyr SDK User Guide`_ for more information. - - -Debugging -========= - -Use JTAG or SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Aspeed Zephyr SDK User Guide: - https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.03/Aspeed_Zephy_SDK_User_Guide_v00.01.03.pdf diff --git a/boards/arm/atsamc21n_xpro/Kconfig.board b/boards/arm/atsamc21n_xpro/Kconfig.board deleted file mode 100644 index ee0ee41e596dbd..00000000000000 --- a/boards/arm/atsamc21n_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM C21N Xplained Pro Board configuration - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMC21N_XPRO - bool "SAM C21N Xplained Pro" - depends on SOC_PART_NUMBER_SAMC21N18A diff --git a/boards/arm/atsamc21n_xpro/Kconfig.defconfig b/boards/arm/atsamc21n_xpro/Kconfig.defconfig deleted file mode 100644 index 8827f5c67a8260..00000000000000 --- a/boards/arm/atsamc21n_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM C21N Xplained Pro board configuration - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamc21n_xpro" - depends on BOARD_ATSAMC21N_XPRO diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts deleted file mode 100644 index da657b5788b84d..00000000000000 --- a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2022 Kamil Serwus - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include "atsamc21n_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM C21N Xplained Pro"; - compatible = "atsamc21n,xpro", "atmel,samc21n18a", "atmel,samc21"; - - chosen { - zephyr,console = &sercom4; - zephyr,shell-uart = &sercom4; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,canbus = &can0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - i2c-0 = &sercom1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portc 05 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc2 1 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&portb 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "User Button"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_default>; - pinctrl-names = "default"; -}; - -&adc1 { - pinctrl-0 = <&adc1_default>; - pinctrl-names = "default"; -}; - -&tcc2 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - prescaler = <256>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <9600>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom0_uart_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom1_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom2_uart_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <1>; - - pinctrl-0 = <&sercom4_uart_default>; - pinctrl-names = "default"; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_spi_default>; - pinctrl-names = "default"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@3c000 { - label = "storage"; - reg = <0x0003c000 0x00004000>; - }; - }; -}; - -&can0 { - status = "okay"; - - pinctrl-0 = <&can0_default>; - pinctrl-names = "default"; - - bus-speed = <125000>; - bus-speed-data = <1000000>; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; - -&can1 { - pinctrl-0 = <&can1_default>; - pinctrl-names = "default"; - - bus-speed = <125000>; - bus-speed-data = <1000000>; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml b/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml deleted file mode 100644 index 16420223b24ffe..00000000000000 --- a/boards/arm/atsamc21n_xpro/atsamc21n_xpro.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamc21n_xpro -name: SAM C21N Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - can - - dma - - gpio - - i2c - - pwm - - spi - - uart -vendor: atmel diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig b/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig deleted file mode 100644 index 7205b28aaad513..00000000000000 --- a/boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_SAMC21=y -CONFIG_SOC_PART_NUMBER_SAMC21N18A=y -CONFIG_BOARD_ATSAMC21N_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arm/atsamc21n_xpro/doc/index.rst b/boards/arm/atsamc21n_xpro/doc/index.rst deleted file mode 100644 index e7d7d2d58525cd..00000000000000 --- a/boards/arm/atsamc21n_xpro/doc/index.rst +++ /dev/null @@ -1,194 +0,0 @@ -.. _atsamc21n_xpro: - -SAM C21N Xplained Pro Evaluation Kit -#################################### - -Overview -******** - -The SAM C21N Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM C21N Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. image:: img/atsamc21n_xpro.jpg - :align: center - :alt: ATSAMC21N-XPRO - -Hardware -******** - -- ATSAMC21N18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory, 32 KiB of RAM, 8KB RRW flash -- One yellow user LED -- One mechanical user push button -- One reset button -- One QTouch® button -- On-board USB based EDBG unit with serial console -- Two CAN transceivers - -Supported Features -================== - -The atsamc21n_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - CAN - - on-chip - - CAN ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamc21n_xpro/atsamc21n_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM C21N Xplained Pro evaluation kit has 4 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM C21 Family Datasheet`_ and the `SAM C21N -Xplained Pro Schematic`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- ADC0 : PB09 -- ADC1 : PA08 -- CAN0 TX : PA24 -- CAN0 RX : PA25 -- CAN1 TX : PB14 -- CAN1 RX : PB15 -- SERCOM0 USART TX : PB24 -- SERCOM0 USART RX : PB25 -- SERCOM1 I2C SDA : PA16 -- SERCOM1 I2C SCL : PA17 -- SERCOM2 USART TX : PA12 -- SERCOM2 USART RX : PA13 -- SERCOM4 USART TX : PB10 -- SERCOM4 USART RX : PB11 -- SERCOM5 SPI MISO : PB00 -- SERCOM5 SPI MOSI : PB02 -- SERCOM5 SPI SCK : PB01 -- GPIO/PWM LED0 : PC05 - -System Clock -============ - -The SAMC21 MCU is configured to use the 32.768 kHz internal oscillator -with the on-chip internal oscillator generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMC21 MCU has eight SERCOM based USARTs with three configured as USARTs in -this BSP. SERCOM4 is the default Zephyr console. - -- SERCOM0 9600 8n1 -- SERCOM2 115200 8n1 -- SERCOM4 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMC21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC2 instead of by GPIO. - -Programming and Debugging -************************* - -The SAM C21N Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMC21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamc21n_xpro - :goals: build - :compact: - -#. Connect the SAM C21N Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamc21n_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamc21n_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - https://www.microchip.com/en-us/development-tool/ATSAMC21N-XPRO - -.. _SAM C21 Family Datasheet: - https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-C20-C21-Family-Data-Sheet-DS60001479J.pdf - -.. _SAM C21N Xplained Pro Schematic: - https://ww1.microchip.com/downloads/en/DeviceDoc/ATSAMC21N_Xplained_Pro_Design_Files.zip diff --git a/boards/arm/atsamd20_xpro/Kconfig.board b/boards/arm/atsamd20_xpro/Kconfig.board deleted file mode 100644 index f63891d49ace6e..00000000000000 --- a/boards/arm/atsamd20_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D20 Xplained Pro Board configuration - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMD20_XPRO - bool "SAM D20 Xplained Pro" - depends on SOC_PART_NUMBER_SAMD20J18 diff --git a/boards/arm/atsamd20_xpro/Kconfig.defconfig b/boards/arm/atsamd20_xpro/Kconfig.defconfig deleted file mode 100644 index ec29acbf76fb99..00000000000000 --- a/boards/arm/atsamd20_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D20 Xplained Pro board configuration - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamd20_xpro" - depends on BOARD_ATSAMD20_XPRO diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro.dts b/boards/arm/atsamd20_xpro/atsamd20_xpro.dts deleted file mode 100644 index 778d76b6017cb5..00000000000000 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro.dts +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2018 Sean Nyekjaer - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include -#include "atsamd20_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM D20 Xplained Pro"; - compatible = "atsamd20,xpro", "atmel,samd20j18", "atmel,samd20"; - - chosen { - zephyr,console = &sercom3; - zephyr,shell-uart = &sercom3; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &yellow_led; - sw0 = &user_button; - i2c-0 = &sercom2; - }; - - leds { - compatible = "gpio-leds"; - yellow_led: led_0 { - gpios = <&porta 14 GPIO_ACTIVE_LOW>; - label = "LED0"; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - cs-gpios = <&porta 5 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&sercom0_spi_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom3 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <1>; - - pinctrl-0 = <&sercom3_uart_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom4_uart_default>; - pinctrl-names = "default"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@3c000 { - label = "storage"; - reg = <0x0003c000 0x00004000>; - }; - }; -}; diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro.yaml b/boards/arm/atsamd20_xpro/atsamd20_xpro.yaml deleted file mode 100644 index 4138e137100292..00000000000000 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: atsamd20_xpro -name: SAM D20 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - flash - - gpio - - i2c - - spi - - uart - - watchdog -vendor: atmel diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig b/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig deleted file mode 100644 index 54946deee39bdb..00000000000000 --- a/boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD20=y -CONFIG_SOC_PART_NUMBER_SAMD20J18=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMD20_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd20_xpro/doc/index.rst b/boards/arm/atsamd20_xpro/doc/index.rst deleted file mode 100644 index b5b6d96eb03d46..00000000000000 --- a/boards/arm/atsamd20_xpro/doc/index.rst +++ /dev/null @@ -1,161 +0,0 @@ -.. _atsamd20_xpro: - -SAM D20 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM D20 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM D20 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. figure:: img/atsamd20_xpro.jpg - :width: 500px - :align: center - :alt: ATSAMD20-XPRO - - ATSAMD20-XPRO (Credit: `Microchip Technology`_) - -Hardware -******** - -- ATSAMD20J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamd20_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/atsamd20_xpro/atsamd20_xpro_defconfig`. - -Connections and IOs -=================== - -The `Microchip website`_ has detailed information about board -connections. Download the `SAM D20 Xplained Pro Schematic`_ for more detail. - -System Clock -============ - -The SAMD20 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs -(SERCOM3) is connected to the onboard Atmel Embedded Debugger (EDBG). -SERCOM4 is available on the EXT1 connector. - -SPI Port -======== - -The SAMD20 MCU has 6 SERCOM based SPIs. On the SAM D20 Xplained Pro, -SERCOM0 is available on the EXT1 connector. - -Programming and Debugging -************************* - -The SAM D20 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMD20 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd20_xpro - :goals: build - :compact: - -#. Connect the SAM D20 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd20_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamd20_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip Technology: - https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO - -.. _Microchip website: - https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO - -.. _SAM D20 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD20-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamd21_xpro/Kconfig.board b/boards/arm/atsamd21_xpro/Kconfig.board deleted file mode 100644 index 4070442f3ca970..00000000000000 --- a/boards/arm/atsamd21_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D21 Xplained Pro Board configuration - -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMD21_XPRO - bool "SAM D21 Xplained Pro" - depends on SOC_PART_NUMBER_SAMD21J18A diff --git a/boards/arm/atsamd21_xpro/Kconfig.defconfig b/boards/arm/atsamd21_xpro/Kconfig.defconfig deleted file mode 100644 index 6ebc627dd1b279..00000000000000 --- a/boards/arm/atsamd21_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM D21 Xplained Pro board configuration - -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamd21_xpro" - depends on BOARD_ATSAMD21_XPRO diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro.dts b/boards/arm/atsamd21_xpro/atsamd21_xpro.dts deleted file mode 100644 index d65d773a66fe86..00000000000000 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro.dts +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2018 Bryan O'Donoghue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include -#include "atsamd21_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM D21 Xplained Pro"; - compatible = "atsamd21,xpro", "atmel,samd21j18a", "atmel,samd21"; - - chosen { - zephyr,console = &sercom3; - zephyr,shell-uart = &sercom3; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - i2c-0 = &sercom2; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portb 30 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 0 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.4s */ - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <9600>; - rxpo = <3>; - txpo = <1>; - - pinctrl-0 = <&sercom0_uart_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <0>; - - pinctrl-0 = <&sercom1_uart_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom3 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom3_uart_default>; - pinctrl-names = "default"; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_spi_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb_dc_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml b/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml deleted file mode 100644 index 5eebbdfe813209..00000000000000 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamd21_xpro -name: SAM D21 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - counter - - dma - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: atmel diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig b/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig deleted file mode 100644 index d7ceba5171d865..00000000000000 --- a/boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2018 Bryan O'Donoghue -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21J18A=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMD21_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd21_xpro/doc/index.rst b/boards/arm/atsamd21_xpro/doc/index.rst deleted file mode 100644 index 78ed6da63ffebd..00000000000000 --- a/boards/arm/atsamd21_xpro/doc/index.rst +++ /dev/null @@ -1,202 +0,0 @@ -.. _atsamd21_xpro: - -SAM D21 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM D21 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM D21 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel's Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. figure:: img/atsamd21_xpro.jpg - :width: 500px - :align: center - :alt: ATSAMD21-XPRO - - ATSAMD21-XPRO (Credit: `Microchip Technology`_) - -Hardware -******** - -- ATSAMD21J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamd21_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - USB - - on-chip - - Universal Serial Bus device ports - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamd21_xpro/atsamd21_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM D21 Xplained Pro evaluation kit has 3 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM D21 Family Datasheet`_ and the `SAM D21 -Xplained Pro Schematic`_. - -.. image:: img/ATSAMD21-XPRO-pinout.jpg - :align: center - :alt: ATSAMD21-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 USART TX : PA10 -- SERCOM0 USART RX : PA11 -- SERCOM1 USART TX : PA16 -- SERCOM1 USART RX : PA19 -- SERCOM2 I2C SDA : PA08 -- SERCOM2 I2C SCL : PA09 -- SERCOM3 USART TX : PA22 -- SERCOM3 USART RX : PA23 -- SERCOM5 SPI MISO : PB16 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- USB DP : PA25 -- USB DM : PA24 -- GPIO SPI CS : PB17 -- GPIO/PWM LED0 : PB30 - -System Clock -============ - -The SAMD21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMD21 MCU has six SERCOM based USARTs with three configured as USARTs in -this BSP. SERCOM3 is the default Zephyr console. - -- SERCOM0 9600 8n1 -- SERCOM1 115200 8n1 -- SERCOM3 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the SAM D21 Xplained Pro, -SERCOM5 is connected to an 8 megabit SPI flash. - -Programming and Debugging -************************* - -The SAM D21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMD21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd21_xpro - :goals: build - :compact: - -#. Connect the SAM D21 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamd21_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamd21_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip Technology: - http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD21-XPRO - -.. _SAM D21 Family Datasheet: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21-Family-Datasheet-DS40001882C.pdf - -.. _SAM D21 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsame54_xpro/Kconfig.board b/boards/arm/atsame54_xpro/Kconfig.board deleted file mode 100644 index 2d451f1afefb0d..00000000000000 --- a/boards/arm/atsame54_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM E54 Xplained Pro Board configuration -# -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAME54_XPRO - bool "SAM E54 Xplained Pro" - depends on SOC_PART_NUMBER_SAME54P20A diff --git a/boards/arm/atsame54_xpro/Kconfig.defconfig b/boards/arm/atsame54_xpro/Kconfig.defconfig deleted file mode 100644 index c955d11d5f6b30..00000000000000 --- a/boards/arm/atsame54_xpro/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# SAM E54 Xplained Pro board configuration -# -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ATSAME54_XPRO - -config BOARD - default "atsame54_xpro" - -if ETH_SAM_GMAC - -# Read MAC address from AT24MAC402 EEPROM - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS - default 0x9A - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE - default 1 - -config ETH_SAM_GMAC_MAC_I2C_EEPROM - default y - select I2C - -endif # ETH_SAM_GMAC - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_ATSAME54_XPRO diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.dts b/boards/arm/atsame54_xpro/atsame54_xpro.dts deleted file mode 100644 index a9bc92ad8a703b..00000000000000 --- a/boards/arm/atsame54_xpro/atsame54_xpro.dts +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2019 Benjamin Valentin - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "atsame54_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM E54 Xplained Pro"; - compatible = "atsame54,xpro", "atmel,same54p20a", "atmel,same54"; - - chosen { - zephyr,console = &sercom2; - zephyr,shell-uart = &sercom2; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &button0; - i2c-0 = &sercom7; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portc 18 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 2 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&portb 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.1s for 120MHz main clock */ - prescaler = <8>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_uart_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <3>; - dopo = <0>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom4_spi_default>; - pinctrl-names = "default"; -}; - -&sercom7 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom7_i2c_default>; - pinctrl-names = "default"; - - eeprom: eeprom@5e { - compatible = "atmel,24mac402"; - reg = <0x5e>; - }; -}; - -&adc0 { - status = "okay"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb_dc_default>; - pinctrl-names = "default"; -}; - -&gmac { - status = "okay"; - - pinctrl-0 = <&gmac_rmii>; - pinctrl-names = "default"; - - mac-eeprom = <&eeprom>; - phy-handle = <&phy>; -}; - -&mdio { - status = "okay"; - - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy"; - status = "okay"; - reg = <0>; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@fc000 { - label = "storage"; - reg = <0x000fc000 0x00004000>; - }; - }; -}; diff --git a/boards/arm/atsame54_xpro/atsame54_xpro.yaml b/boards/arm/atsame54_xpro/atsame54_xpro.yaml deleted file mode 100644 index f23ef379363119..00000000000000 --- a/boards/arm/atsame54_xpro/atsame54_xpro.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 -identifier: atsame54_xpro -name: SAM E54 Xplained Pro -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - flash - - gpio - - pwm - - spi - - i2c - - uart - - usb_device - - netif:eth -vendor: atmel diff --git a/boards/arm/atsame54_xpro/atsame54_xpro_defconfig b/boards/arm/atsame54_xpro/atsame54_xpro_defconfig deleted file mode 100644 index 1fc88370a4459d..00000000000000 --- a/boards/arm/atsame54_xpro/atsame54_xpro_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME54=y -CONFIG_SOC_PART_NUMBER_SAME54P20A=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAME54_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsame54_xpro/doc/index.rst b/boards/arm/atsame54_xpro/doc/index.rst deleted file mode 100644 index b6cfd928645e66..00000000000000 --- a/boards/arm/atsame54_xpro/doc/index.rst +++ /dev/null @@ -1,230 +0,0 @@ -.. _atsame54_xpro: - -SAM E54 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM E54 Cortex®-M4F processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. image:: img/atsame54_xpro.jpg - :align: center - :alt: ATSAME54-XPRO - -Hardware -******** - -- ATSAME54P20A ARM Cortex-M4F processor at 120 MHz -- 32.768 kHz crystal oscillator -- 12 MHz crystal oscillator -- 1024 KiB flash memory and 256 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console -- One QTouch® PTC button -- 32 MiB QSPI Flash -- ATECC508 CryptoAuthentication™ device -- AT24MAC402 serial EEPROM with EUI-48™ MAC address -- Ethernet - - - RJ45 connector with built-in magnetics - - KSZ8091RNA PHY - - 10Base-T/100Base-TX IEE 802.3 compliant Ethernet transceiver - -- USB interface, host, and device -- SD/SDIO card connector - -Supported Features -================== - -The atsame54_xpro board configuration supports the following hardware -features: - -+---------------+------------+----------------------------+ -| Interface | Controller | Driver/Component | -+===============+============+============================+ -| ADC | on-chip | adc | -+---------------+------------+----------------------------+ -| DAC | on-chip | dac | -+---------------+------------+----------------------------+ -| DMAC | on-chip | dma | -+---------------+------------+----------------------------+ -| EEPROM | i2c | eeprom, EUI-48 MAC Address | -+---------------+------------+----------------------------+ -| EIC | on-chip | interrupt_controller | -+---------------+------------+----------------------------+ -| GMAC | on-chip | ethernet, mdio | -+---------------+------------+----------------------------+ -| GPIO | on-chip | gpio | -+---------------+------------+----------------------------+ -| MPU | on-chip | arch/arm | -+---------------+------------+----------------------------+ -| NVIC | on-chip | arch/arm | -+---------------+------------+----------------------------+ -| NVMCTRL | on-chip | flash | -+---------------+------------+----------------------------+ -| PORT | on-chip | pinctrl | -+---------------+------------+----------------------------+ -| RTC | on-chip | timer | -+---------------+------------+----------------------------+ -| SERCOM I2C | on-chip | i2c | -+---------------+------------+----------------------------+ -| SERCOM SPI | on-chip | spi | -+---------------+------------+----------------------------+ -| SERCOM USART | on-chip | serial, console | -+---------------+------------+----------------------------+ -| Serial Number | on-chip | hwinfo | -+---------------+------------+----------------------------+ -| SYSTICK | on-chip | timer | -+---------------+------------+----------------------------+ -| TC | on-chip | counter | -+---------------+------------+----------------------------+ -| TCC | on-chip | counter, pwm | -+---------------+------------+----------------------------+ -| TRNG | on-chip | entropy | -+---------------+------------+----------------------------+ -| USB | on-chip | usb | -+---------------+------------+----------------------------+ -| WDT | on-chip | watchdog | -+---------------+------------+----------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsame54_xpro/atsame54_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM E54 Xplained Pro evaluation kit has 4 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM D5x/E5x Family Datasheet`_ and the `SAM E54 -Xplained Pro Schematic`_. - -.. image:: img/ATSAME54-XPRO-pinout.jpg - :align: center - :alt: ATSAME54-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM2 USART TX : PB24 -- SERCOM2 USART RX : PB25 -- GPIO/PWM LED0 : PC18 -- GPIO SW0 : PB31 -- GMAC RMII REFCK : PA14 -- GMAC RMII TXEN : PA17 -- GMAC RMII TXD0 : PA18 -- GMAC RMII TXD1 : PA19 -- GMAC RMII CRSDV : PC20 -- GMAC RMII RXD0 : PA13 -- GMAC RMII RXD1 : PA12 -- GMAC RMII RXER : PA15 -- GMAC MDIO MDC : PC11 -- GMAC MDIO MDIO : PC12 -- SERCOM4 SPI SCK : PB26 -- SERCOM4 SPI MOSI : PB27 -- SERCOM4 SPI MISO : PB29 -- SERCOM7 I2C SDA : PD08 -- SERCOM7 I2C SCL : PD09 -- USB DP : PA25 -- USB DM : PA24 - -System Clock -============ - -The SAME54 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAME54 MCU has 8 SERCOM based USARTs with one configured as USARTs in -this BSP. SERCOM2 is the default Zephyr console. - -- SERCOM2 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAME54 MCU has 5 TCC based PWM units with up to 6 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAME54 MCU has 8 SERCOM based SPIs. - -I2C Port -======== - -The SAME54 MCU has 8 SERCOM based I2Cs. On the SAM E54 Xplained Pro, -SERCOM7 is connected to a AT24MAC402 EEPROM and a ATECC508A Crypto -Authentication device. - -Programming and Debugging -************************* - -The SAM E54 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAME54 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsame54_xpro - :goals: build - :compact: - -#. Connect the SAM E54 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsame54_xpro - :goals: flash - :compact: - - You should see "Hello World! atsame54_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAME54-XPRO - -.. _SAM D5x/E5x Family Datasheet: - http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf - -.. _SAM E54 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAME54-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsaml21_xpro/Kconfig.board b/boards/arm/atsaml21_xpro/Kconfig.board deleted file mode 100644 index a06c9e3d20a338..00000000000000 --- a/boards/arm/atsaml21_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM L21 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAML21_XPRO - bool "SAM L21 Xplained Pro" - depends on SOC_PART_NUMBER_SAML21J18B diff --git a/boards/arm/atsaml21_xpro/Kconfig.defconfig b/boards/arm/atsaml21_xpro/Kconfig.defconfig deleted file mode 100644 index 3c35f327bb20e9..00000000000000 --- a/boards/arm/atsaml21_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM L21 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsaml21_xpro" - depends on BOARD_ATSAML21_XPRO diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro.dts b/boards/arm/atsaml21_xpro/atsaml21_xpro.dts deleted file mode 100644 index ee800d7ae9525a..00000000000000 --- a/boards/arm/atsaml21_xpro/atsaml21_xpro.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "atsaml21_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM L21 Xplained Pro"; - compatible = "atsaml21,xpro", "atmel,saml21j18b", "atmel,saml21"; - - chosen { - zephyr,console = &sercom3; - zephyr,shell-uart = &sercom3; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&portb 10 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 0 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&adc { - status = "okay"; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.4s */ - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&tcc0_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom0_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <3>; - txpo = <0>; - - pinctrl-0 = <&sercom1_default>; - pinctrl-names = "default"; -}; - -&sercom2 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom2_default>; - pinctrl-names = "default"; -}; - -&sercom3 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom3_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom4_default>; - pinctrl-names = "default"; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb0_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml b/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml deleted file mode 100644 index 03c5c226209499..00000000000000 --- a/boards/arm/atsaml21_xpro/atsaml21_xpro.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 -identifier: atsaml21_xpro -name: SAM L21 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - counter - - dma - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: atmel diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig b/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig deleted file mode 100644 index 13ee4a4819052d..00000000000000 --- a/boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAML21=y -CONFIG_SOC_PART_NUMBER_SAML21J18B=y -CONFIG_SOC_ATMEL_SAML_XOSC32K=y -CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAML21_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsaml21_xpro/doc/index.rst b/boards/arm/atsaml21_xpro/doc/index.rst deleted file mode 100644 index 5c55f23d5874e7..00000000000000 --- a/boards/arm/atsaml21_xpro/doc/index.rst +++ /dev/null @@ -1,198 +0,0 @@ - .. _atsaml21_xpro: - -SAM L21 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM L21 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM L21 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -.. image:: img/atsaml21-xpro.jpg - :align: center - :alt: ATSAML21-XPRO - -Hardware -******** - -- ATSAML21J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsaml21_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - TRNG - - on-chip - - True Random Number Generator - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsaml21_xpro/atsaml21_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM L21 Xplained Pro evaluation kit has 2 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM L21 Family Datasheet`_ and the `SAM L21 -Xplained Pro Schematic`_. - -.. image:: img/atsaml21-xpro-pinout.jpg - :align: center - :alt: ATSAML21-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 SPI MISO : PA04 -- SERCOM0 SPI MOSI : PA06 -- SERCOM0 SPI SCK : PA07 -- SERCOM1 USART TX : PA18 -- SERCOM1 USART RX : PA19 -- SERCOM2 I2C SDA : PA08 -- SERCOM2 I2C SCL : PA09 -- SERCOM3 USART TX : PA22 -- SERCOM3 USART RX : PA23 -- SERCOM4 USART TX : PB08 -- SERCOM4 USART RX : PB09 -- SERCOM5 SPI MISO : PB16 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- USB DP : PA25 -- USB DM : PA24 -- GPIO SPI CS : PB17 -- GPIO/PWM LED0 : PB10 - -System Clock -============ - -The SAML21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAML21 MCU has six SERCOM based USARTs with two configured as USARTs in -this BSP. SERCOM3 is the default Zephyr console. - -- SERCOM1 115200 8n1 - connected to EXT2 and EXT3 -- SERCOM3 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) -- SERCOM4 115200 8n1 - connected to EXT1 - -PWM -=== - -The SAML21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAML21 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. - -- SERCOM0 - connected to EXT1 -- SERCOM5 - connected to EXT2 and EXT3 - -Programming and Debugging -************************* - -The SAM L21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAML21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsaml21_xpro - :goals: build - :compact: - -#. Connect the SAM L21 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ picocom -b 115200 /dev/ttyACM0 - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsaml21_xpro - :goals: flash - :compact: - - You should see "Hello World! atsaml21_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b - -.. _SAM L21 Family Datasheet: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf - -.. _SAM L21 Xplained Pro Schematic: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAML21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamr21_xpro/Kconfig.board b/boards/arm/atsamr21_xpro/Kconfig.board deleted file mode 100644 index 0293b0416f00d7..00000000000000 --- a/boards/arm/atsamr21_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM R21 Xplained Pro Board configuration - -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMR21_XPRO - bool "SAM R21 Xplained Pro" - depends on SOC_PART_NUMBER_SAMR21G18A diff --git a/boards/arm/atsamr21_xpro/Kconfig.defconfig b/boards/arm/atsamr21_xpro/Kconfig.defconfig deleted file mode 100644 index 4f0b72b150b18b..00000000000000 --- a/boards/arm/atsamr21_xpro/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SAM R21 Xplained Pro board configuration - -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ATSAMR21_XPRO - -config BOARD - default "atsamr21_xpro" - -endif # BOARD_ATSAMR21_XPRO diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro.dts b/boards/arm/atsamr21_xpro/atsamr21_xpro.dts deleted file mode 100644 index 86981d86cfecc7..00000000000000 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2019 Benjamin Valentin - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "atsamr21_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM R21 Xplained Pro"; - compatible = "atsamr21,xpro", "atmel,samr21g18a", "atmel,samr21"; - - chosen { - zephyr,console = &sercom0; - zephyr,shell-uart = &sercom0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,ieee802154 = &ieee802154; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - i2c-0 = &sercom1; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&porta 19 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 3 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; - - ext1_header: xplained-pro-connector1 { - compatible = "atmel-xplained-pro-header"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = <0 0 &porta 6 0>, /* ADC6 */ - <1 0 &porta 7 0>, /* ADC7 */ - <2 0 &porta 13 0>, /* GPIO */ - <3 0 &porta 28 0>, /* GPIO */ - <4 0 &porta 18 0>, /* PWM_T0_W2 */ - <5 0 &porta 19 0>, /* PWM_T0_W3 */ - <6 0 &porta 22 0>, /* GPIO */ - <7 0 &porta 23 0>, /* GPIO */ - <8 0 &porta 16 0>, /* TWD1 EXT2 */ - <9 0 &porta 17 0>, /* TWCK1 EXT2 */ - <10 0 &porta 5 0>, /* RXD0 */ - <11 0 &porta 4 0>, /* TXD0 */ - <12 0 &portb 3 0>, /* SPI5(SS) */ - <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ - <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ - <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ - }; - - ext2_header: xplained-pro-connector2 { - compatible = "atmel-xplained-pro-header"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; /* Shared */ - gpio-map = /*<0 0 - - 0>, - */ - /*<1 0 - - 0>, - */ - <2 0 &porta 15 0>, /* GPIO */ - /*<3 0 - - 0>, - */ - /*<4 0 - - 0>, - */ - /*<5 0 - - 0>, - */ - /*<6 0 - - 0>, - */ - <7 0 &porta 8 0>, /* GPIO */ - <8 0 &porta 16 0>, /* TWD1 EXT1 */ - <9 0 &porta 17 0>, /* TWCK1 EXT1 */ - /*<11 0 - - 0>, - */ - /*<12 0 - - 0>, - */ - <12 0 &porta 14 0>, /* GPIO */ - <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ - <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ - <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom0_uart_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom1_i2c_default>; - pinctrl-names = "default"; -}; - -&sercom4 { - status = "okay"; - compatible = "atmel,sam0-spi"; - /* - * CS-PB31; MOSI-PB30; MISO-PC19; SCLK-PC18 - * PAD[1]; PAD[2]; PAD[0]; PAD[3] - */ - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom4_spi_default>; - pinctrl-names = "default"; - - cs-gpios = <&portb 31 GPIO_ACTIVE_LOW>; - - ieee802154: rf2xx@0 { - compatible = "atmel,rf2xx"; - reg = <0x0>; - spi-max-frequency = <6000000>; - irq-gpios = <&portb 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; - reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; - slptr-gpios = <&porta 20 GPIO_ACTIVE_HIGH>; - dig2-gpios = <&portb 17 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; - status = "okay"; - tx-pwr-min = [01 11]; /* -17.0 dBm */ - tx-pwr-max = [00 04]; /* 4.0 dBm */ - tx-pwr-table = [00 01 03 04 05 05 06 06 - 07 07 07 08 08 09 09 0a - 0a 0a 0b 0b 0b 0b 0c 0c - 0c 0c 0d 0d 0d 0d 0d 0d - 0d 0d 0e 0e 0e 0e 0e 0e - 0e 0e 0e 0e 0e 0e 0f 0f]; - }; -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <2>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_spi_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb_dc_default>; - pinctrl-names = "default"; -}; - -ext1_spi: &sercom5 { -}; - -ext1_i2c: &sercom1 { -}; - -ext1_serial: &sercom0 { -}; - -ext2_spi: &sercom5 { -}; - -ext2_i2c: &sercom1 { -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The final 16 KiB is reserved for the application. - * Storage partition will be used by FCB/LittleFS/NVS - * if enabled. - */ - storage_partition: partition@3c000 { - label = "storage"; - reg = <0x0003c000 0x00004000>; - }; - }; -}; diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml b/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml deleted file mode 100644 index 04608ed2afbabf..00000000000000 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro.yaml +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2019-2020 Gerson Fernando Budke -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamr21_xpro -name: SAM R21 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - flash - - gpio - - i2c - - netif - - pwm - - spi - - uart - - usb_device - - xpro_gpio - - xpro_i2c - - xpro_serial - - xpro_spi -vendor: atmel diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig b/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig deleted file mode 100644 index 7437bfc1ca03b2..00000000000000 --- a/boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2019 Benjamin Valentin -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMR21=y -CONFIG_SOC_PART_NUMBER_SAMR21G18A=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K=y -CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMR21_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr21_xpro/doc/index.rst b/boards/arm/atsamr21_xpro/doc/index.rst deleted file mode 100644 index 60d2c36ea3226b..00000000000000 --- a/boards/arm/atsamr21_xpro/doc/index.rst +++ /dev/null @@ -1,225 +0,0 @@ -.. _atsamr21_xpro: - -SAM R21 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM R21 Xplained Pro is a compact evaluation board by Atmel featuring a -ATSAMR21G18A SoC. The SoC includes a SAMR21 ARM Cortex-M0+ micro-controller -bundled with Atmel's AT86RF233, a 2.4GHz IEEE802.15.4 compatible radio. -The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full -debug interface without the need for additional hardware. - -.. image:: img/atsamr21_xpro.jpg - :align: center - :alt: ATSAMR21-XPRO - -Hardware -******** - -- ATSAMR21G18A ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory and 32 KiB of RAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamr21_xpro board configuration supports the following hardware -features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+--------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+--------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+--------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+--------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+--------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+--------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+--------------------------------------+ -| I2C | on-chip | I2C Peripheral Interface ports | -+-----------+------------+--------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamr21_xpro/atsamr21_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM R21 Xplained Pro evaluation kit has 3 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM R21 Family Datasheet`_ and the `SAM R21 -Xplained Pro Schematic`_. - -.. image:: img/ATSAMR21-XPRO-pinout.jpg - :align: center - :alt: ATSAMR21-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 USART TX : PA5 -- SERCOM0 USART RX : PA4 -- SERCOM1 I2C SDA : PA16 -- SERCOM1 I2C SCL : PA17 -- SERCOM5 SPI MISO : PB02 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- GPIO SPI CS : PB03 -- GPIO/PWM LED0 : PA19 - -System Clock -============ - -The SAMR21 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMR21 MCU has six SERCOM based USARTs with two configured as USARTs in -this BSP. SERCOM0 is the default Zephyr console. - -- SERCOM0 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMR21 MCU has 3 TCC based PWM units with up to 4 outputs each and a -period of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then -LED0 is driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMR21 MCU has 6 SERCOM based SPIs. - -- SERCOM5 is exposed via Xplained Pro Standard Extension Header - -I2C Port -======== - -When connecting an I2C device and a logic analyzer to an I2C port at the same -time, the internal pull-up resistors are not sufficient for stable bus -operation. You probably have to connect external pull-ups to both bus lines. 10K -is a good value to start with. - -- SERCOM1 is exposed via Xplained Pro Standard Extension Header - -Radio -===== - -The SAMR21 SoC includes an on-chip AT86RF233 radio. It is internally -connected via SPI and some GPIO pins and behaves the same way as -externally connected SPI devices. - -+-------------+------------------------------------------------------------------------------------------+ -| Sensor | AT86RF233 | -+=============+==========================================================================================+ -| Type | 2.4GHz IEEE802.15.4 radio | -+-------------+------------------------------------------------------------------------------------------+ -| Vendor | Atmel | -+-------------+------------------------------------------------------------------------------------------+ -| Datasheet |`Datasheet `_| -+-------------+------------------------------------------------------------------------------------------+ -| connected to| SPI_0 | -+-------------+------------------------------------------------------------------------------------------+ -| Pin Config: | -+-------------+------------------------------------------------------------------------------------------+ -| Device | SERCOM4 | -+-------------+------------------------------------------------------------------------------------------+ -| MOSI | PB30 (OUT, SPI MOSI) | -+-------------+------------------------------------------------------------------------------------------+ -| MISO | PC19 (IN, SPI MISO) | -+-------------+------------------------------------------------------------------------------------------+ -| SCLK | PC18 (OUT, SPI SCLK) | -+-------------+------------------------------------------------------------------------------------------+ -| CS | PB31 (OUT, GPIO output) | -+-------------+------------------------------------------------------------------------------------------+ -| IRQ | PB00 (IN, GPIO external interrupt) | -+-------------+------------------------------------------------------------------------------------------+ -| RSTN | PB15 (OUT, GPIO output) | -+-------------+------------------------------------------------------------------------------------------+ -| SLP_TR | PA20 (OUT, GPIO output) | -+-------------+------------------------------------------------------------------------------------------+ - -Zephyr provide several samples that can use this technology. You can check -:zephyr:code-sample:`wpan-usb` and :zephyr:code-sample:`wpan-serial` examples as starting -points. Another good test can be done with IPv6 by using the server/client -echo demo. More information at :zephyr:code-sample:`sockets-echo-server` and -:zephyr:code-sample:`sockets-echo-client`. - -Programming and Debugging -************************* - -The SAM R21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMR21 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr21_xpro - :goals: build - :compact: - -#. Connect the SAM R21 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr21_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamr21_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMR21-XPRO - -.. _SAM R21 Family Datasheet: - http://ww1.microchip.com/downloads/en/devicedoc/sam-r21_datasheet.pdf - -.. _SAM R21 Xplained Pro Schematic: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAMR21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamr34_xpro/Kconfig.board b/boards/arm/atsamr34_xpro/Kconfig.board deleted file mode 100644 index d586efcbc7e7a2..00000000000000 --- a/boards/arm/atsamr34_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SAM R34 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ATSAMR34_XPRO - bool "SAM R34 Xplained Pro" - depends on SOC_PART_NUMBER_SAMR34J18B diff --git a/boards/arm/atsamr34_xpro/Kconfig.defconfig b/boards/arm/atsamr34_xpro/Kconfig.defconfig deleted file mode 100644 index e327820655a026..00000000000000 --- a/boards/arm/atsamr34_xpro/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SAM R34 Xplained Pro board configuration - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "atsamr34_xpro" - depends on BOARD_ATSAMR34_XPRO diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro.dts b/boards/arm/atsamr34_xpro/atsamr34_xpro.dts deleted file mode 100644 index fe0ae80ae35ccd..00000000000000 --- a/boards/arm/atsamr34_xpro/atsamr34_xpro.dts +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "atsamr34_xpro-pinctrl.dtsi" -#include - -/ { - model = "SAM R34 Xplained Pro"; - compatible = "atmel,atsamr34xpro", "atmel,samr34j18b", "atmel,samr34"; - - chosen { - zephyr,console = &sercom0; - zephyr,shell-uart = &sercom0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - pwm-led0 = &pwm_led0; - sw0 = &user_button; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&porta 19 GPIO_ACTIVE_LOW>; - label = "Yellow LED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&tcc0 3 PWM_MSEC(20)>; - }; - }; - - buttons { - compatible = "gpio-keys"; - user_button: button_0 { - gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW0"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = <48000000>; -}; - -&adc { - status = "okay"; -}; - -&tcc0 { - status = "okay"; - compatible = "atmel,sam0-tcc-pwm"; - /* Gives a maximum period of 1.4s */ - prescaler = <4>; - #pwm-cells = <2>; - - pinctrl-0 = <&tcc0_default>; - pinctrl-names = "default"; -}; - -&sercom0 { - status = "okay"; - compatible = "atmel,sam0-uart"; - current-speed = <115200>; - rxpo = <1>; - txpo = <0>; - - pinctrl-0 = <&sercom0_default>; - pinctrl-names = "default"; -}; - -&sercom1 { - status = "okay"; - compatible = "atmel,sam0-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom1_default>; - pinctrl-names = "default"; -}; - -/* SERCOM4 is used for the internal LoRa radio */ -&sercom4 { - status = "okay"; -}; - -&lora { - status = "okay"; - - tcxo-power-gpios = <&porta 9 GPIO_ACTIVE_HIGH>; /* TCXO_PWR */ - tcxo-power-startup-delay-ms = <5>; - rfi-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ - rfo-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ -}; - -&sercom5 { - status = "okay"; - compatible = "atmel,sam0-spi"; - dipo = <0>; - dopo = <1>; - #address-cells = <1>; - #size-cells = <0>; - - pinctrl-0 = <&sercom5_default>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usb0 { - status = "okay"; - - pinctrl-0 = <&usb0_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml b/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml deleted file mode 100644 index fb5c574b32168d..00000000000000 --- a/boards/arm/atsamr34_xpro/atsamr34_xpro.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 -identifier: atsamr34_xpro -name: SAM R34 Xplained Pro -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - counter - - dma - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: atmel diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig b/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig deleted file mode 100644 index ca12a0ed69e87e..00000000000000 --- a/boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMR34=y -CONFIG_SOC_PART_NUMBER_SAMR34J18B=y -CONFIG_SOC_ATMEL_SAML_XOSC32K=y -CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y -CONFIG_BOARD_ATSAMR34_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr34_xpro/doc/index.rst b/boards/arm/atsamr34_xpro/doc/index.rst deleted file mode 100644 index 6347b50dedbd67..00000000000000 --- a/boards/arm/atsamr34_xpro/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ - .. _atsamr34_xpro: - -SAM R34 Xplained Pro Evaluation Kit -################################### - -Overview -******** - -The SAM R34 Xplained Pro evaluation kit is ideal for evaluation and -prototyping with the SAM R34 Cortex®-M0+ processor-based -microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), -which provides a full debug interface without the need for additional -hardware. - -The SAMR34 and SAMR35 parts are produced as a System-in-Package (SiP), -including both a SAML21 die, and a Semtech SX1276 LoRa radio die. - -This board is also referred to as DM320111. - -.. image:: img/atsamr34-xpro.jpg - :align: center - :alt: ATSAMR34-XPRO - -Hardware -******** - -- ATSAMR34J18 ARM Cortex-M0+ processor at 48 MHz -- 32.768 kHz crystal oscillator -- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM -- One yellow user LED -- One mechanical user push button -- One reset button -- On-board USB based EDBG unit with serial console - -Supported Features -================== - -The atsamr34_xpro board configuration supports the following hardware -features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - PWM - - on-chip - - Pulse Width Modulation - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - * - TRNG - - on-chip - - True Random Number Generator - -The following hardware features are supported by Zephyr, but not yet fully -supported by the SOC: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - LoRa Radio - - on-chip - - Internal SX1276 LoRa Radio - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -``boards/arm/atsamr34_xpro/atsamr34_xpro_defconfig``. - -Pin Mapping -=========== - -The SAM R34 Xplained Pro evaluation kit has 3 GPIO controllers. These -controllers are responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `SAM R34 Family Datasheet`_ and the `SAM R34 -Xplained Pro Schematic`_. - -.. image:: img/atsamr34-xpro-pinout.jpg - :align: center - :alt: ATSAMR34-XPRO-pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- -- SERCOM0 UART TX : PA04 -- SERCOM0 UART RX : PA05 -- SERCOM1 I2C SDA : PA16 -- SERCOM1 I2C SCL : PA17 -- SERCOM4 SPI MISO : PC19 -- SERCOM4 SPI MOSI : PB30 -- SERCOM4 SPI SCK : PC18 -- SERCOM4 GPIO CS : PB31 -- SERCOM5 SPI MISO : PB02 -- SERCOM5 SPI MOSI : PB22 -- SERCOM5 SPI SCK : PB23 -- SERCOM5 GPIO CS0 : PA23 -- SERCOM5 GPIO CS1 : PA14 -- USB DP : PA25 -- USB DM : PA24 -- GPIO/PWM LED0 : PA19 - -System Clock -============ - -The SAMR34 MCU is configured to use the 32.768 kHz external oscillator -with the on-chip PLL generating the 48 MHz system clock. - -Serial Port -=========== - -The SAMR34 MCU has six SERCOM based USARTs with one configured as USART in -this BSP. SERCOM0 is the default Zephyr console. - -- SERCOM0 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) - -PWM -=== - -The SAMR34 MCU has 3 TCC based PWM units with up to 4 outputs each and a period -of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is -driven by TCC0 instead of by GPIO. - -SPI Port -======== - -The SAMR34 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. - -- SERCOM4 - connected to the internal LoRa radio -- SERCOM5 - connected to EXT1 and EXT3 - -Programming and Debugging -************************* - -The SAM R34 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This -provides a debug interface to the SAMR34 chip and is supported by -OpenOCD. - -Flashing -======== - -#. Build the Zephyr kernel and the ``hello_world`` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr34_xpro - :goals: build - :compact: - -#. Connect the SAM R34 Xplained Pro to your host computer using the USB debug - port. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ picocom -b 115200 /dev/ttyACM0 - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: atsamr34_xpro - :goals: flash - :compact: - - You should see "Hello World! atsamr34_xpro" in your terminal. - -References -********** - -.. target-notes:: - -.. _Microchip website: - https://www.microchip.com/en-us/development-tool/dm320111 - -.. _SAM L21 Family Datasheet: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf - -.. _SAM R34 Family Datasheet: - https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-R34-R35-Low-Power-LoRa-Sub-GHz-SiP-Data-Sheet-DS70005356C.pdf - -.. _SAM R34 Xplained Pro Schematic: - https://ww1.microchip.com/downloads/Secure/en/DeviceDoc/SAMR34_SiP_Reference_Design_Package_V3.0.exe - -.. _Semtech SX1276: - https://www.semtech.com/products/wireless-rf/lora-transceivers/sx1276 diff --git a/boards/arm/az3166_iotdevkit/Kconfig.board b/boards/arm/az3166_iotdevkit/Kconfig.board deleted file mode 100644 index 4750477ac43620..00000000000000 --- a/boards/arm/az3166_iotdevkit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# MXChip AZ3166 DevKit board configuration - -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_AZ3166_DEVKIT - bool "MXChip AZ3166 DevKit" - depends on SOC_STM32F412RX diff --git a/boards/arm/az3166_iotdevkit/Kconfig.defconfig b/boards/arm/az3166_iotdevkit/Kconfig.defconfig deleted file mode 100644 index af040b8a58db29..00000000000000 --- a/boards/arm/az3166_iotdevkit/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MXChip AZ3166 DevKit board configuration - -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_AZ3166_DEVKIT - -config BOARD - default "az3166_devkit" - -choice HTS221_TRIGGER_MODE - default HTS221_TRIGGER_NONE -endchoice - -endif # BOARD_AZ3166_DEVKIT diff --git a/boards/arm/b_g474e_dpow1/Kconfig.board b/boards/arm/b_g474e_dpow1/Kconfig.board deleted file mode 100644 index 405ce71cb7bb44..00000000000000 --- a/boards/arm/b_g474e_dpow1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# B-G474E-DPOW1 Discovery board configuration - -# Copyright 2022 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_G474E_DPOW1 - bool "B-G474E-DPOW1 Discovery Board" - depends on SOC_STM32G474XX diff --git a/boards/arm/b_g474e_dpow1/Kconfig.defconfig b/boards/arm/b_g474e_dpow1/Kconfig.defconfig deleted file mode 100644 index 88bcf76952804e..00000000000000 --- a/boards/arm/b_g474e_dpow1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# B-G474E-DPOW1 Discovery board configuration - -# Copyright 2022 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_G474E_DPOW1 - -config BOARD - default "b_g474e_bpow1" - -endif # BOARD_B_G474E_DPOW1 diff --git a/boards/arm/b_g474e_dpow1/doc/index.rst b/boards/arm/b_g474e_dpow1/doc/index.rst deleted file mode 100644 index 75d99572fbf24e..00000000000000 --- a/boards/arm/b_g474e_dpow1/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _b_g474e_dpow1_board: - -ST B-G474E-DPOW1 Discovery -########################## - -Overview -******** -The B-G474E-DPOW1 Discovery kit is a digital power solution and a complete -demonstration and development platform for the STMicroelectronics STM32G474RET6 -microcontroller. Leveraging the new HRTimer-oriented features, 96 Kbytes of -embedded RAM, math accelerator functions and USB-PD 3.0 offered by STM32G474RET6, -the B-G474E-DPOW1 Discovery kit, based on the USB 2.0 FS Type-C™ connector -interface, helps the user to prototype applications with digital power such as a -buck-boost converter, RGB power LED lighting or a class-D audio amplifier. The -B-G474E-DPOW1 Discovery kit does not require any separate probe, as it integrates -the STLINK-V3E debugger and programmer. - -- STM32G474RET6 Arm® Cortex®-M4 core-based microcontroller, featuring 512 Kbytes - of Flash memory and 128 Kbytes of SRAM, in LQFP64 package -- USB Type-C™ with USB 2.0 FS interface compatible with USB-PD 3.0 -- RGB power LED for a bright lighting -- Digital power buck-boost converter with internal or external Input voltage and - with onboard resistor loads -- Audio Class-D amplifier capable -- 4 user LEDs -- 3 LEDs for power and ST-LINK communication -- 4-direction joystick with a selection button -- Reset push-button -- Board connectors: - - USB Type-C™ - - USB Micro-B - - 2 x 32-pin header, 2.54 mm pitch, daughterboard extension connector for breadboard connection -- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS or external source -- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: mass storage, - Virtual COM port, and debug port - -.. image:: img/b_g474e_dpow1.jpg - :align: center - :alt: B-G474E-DPOW1 - -More information about the board can be found at the `B-G474E-DPOW1 website`_. - - -More information about STM32G474RE can be found here: -- `G474RE on www.st.com`_ -- `STM32G4 reference manual`_ - - -Supported Features -================== - -The Zephyr b_g474e_dpow1 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| UCPD | on-chip | ucpd | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) -- BUTTON (JOY_SEL) : PC13 -- BUTTON (JOY_LEFT) : PC4 -- BUTTON (JOY_DOWN) : PC5 -- BUTTON (JOY_RIGHT) : PB2 -- BUTTON (JOY_UP) : PB10 -- LED (DOWN BLUE) : PA15 -- LED (LEFT ORANGE) : PB1 -- LED (UP RED) : PB5 -- LED (RIGHT GREEN) : PB7 -- USB DM : PA11 -- USB DP : PA12 -- UCPD CC2 : PB4 -- UCPD CC1 : PB6 - -For more details please refer to `B-G474E-DPOW1 Discovery board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``b_g474e_dpow1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface. - -.. code-block:: console - - $ west flash - -Flashing an application to the B_G474E_DPOW1 --------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: b_g474e_dpow1 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_g474e_dpow1 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _B-G474E-DPOW1 website: - https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html - -.. _STM32G4 reference manual: - https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _B-G474E-DPOW1 Discovery board User Manual: - https://www.st.com/resource/en/user_manual/um2577-discovery-kit-with-stm32g474re-mcu-stmicroelectronics.pdf - -.. _G474RE on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32g474re.html diff --git a/boards/arm/b_l072z_lrwan1/Kconfig.board b/boards/arm/b_l072z_lrwan1/Kconfig.board deleted file mode 100644 index 27f6dfe2bd2efd..00000000000000 --- a/boards/arm/b_l072z_lrwan1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STMicroelectronics B-L072Z-LRWAN1 Discovery board configuration - -# Copyright (c) 2018 Aleksandr Makarov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_L072Z_LRWAN1 - bool "STMicroelectronics B-L072Z-LRWAN1 Discovery kit" - depends on SOC_STM32L072XX diff --git a/boards/arm/b_l072z_lrwan1/Kconfig.defconfig b/boards/arm/b_l072z_lrwan1/Kconfig.defconfig deleted file mode 100644 index 9e221e7d7f6497..00000000000000 --- a/boards/arm/b_l072z_lrwan1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STMicroelectronics B-L072Z-LRWAN1 Discovery board configuration - -# Copyright (c) 2018 Aleksandr Makarov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_L072Z_LRWAN1 - -config BOARD - default "b_l072z_lrwan1" - -endif # BOARD_B_L072Z_LRWAN1 diff --git a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig b/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig deleted file mode 100644 index cd14c09d3a6456..00000000000000 --- a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L072XX=y -CONFIG_BOARD_B_L072Z_LRWAN1=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/b_l072z_lrwan1/doc/index.rst b/boards/arm/b_l072z_lrwan1/doc/index.rst deleted file mode 100644 index a45ead85652225..00000000000000 --- a/boards/arm/b_l072z_lrwan1/doc/index.rst +++ /dev/null @@ -1,250 +0,0 @@ -.. _b_l072z_lrwan1_board: - -ST B-L072Z-LRWAN1 Discovery kit -############################### - -Overview -******** - -This Discovery kit features an all-in-one open module CMWX1ZZABZ-091 (by Murata). -The module is powered by an STM32L072CZ and an SX1276 transceiver. - -This kit provides: - -- CMWX1ZZABZ-091 LoRa* / Sigfox* module (Murata) - - - Embedded ultra-low-power STM32L072CZ Series MCUs, based on - Arm* Cortex* -M0+ core, with 192 Kbytes of Flash - memory, 20 Kbytes of RAM, 6 Kbytes of EEPROM - - Frequency range: 860 MHz - 930 MHz - - USB 2.0 FS - - 4-channel,12-bit ADC, 2xDAC - - 6-bit timers, LP-UART, I2C and SPI - - Embedded SX1276 transceiver - - LoRa* , FSK, GFSK, MSK, GMSK and OOK modulations (+ Sigfox* compatibility) - - +14 dBm or +20 dBm selectable output power - - 157 dB maximum link budget - - Programmable bit rate up to 300 kbit/s - - High sensitivity: down to -137 dBm - - Bullet-proof front end: IIP3 = -12.5 dBm - - 89 dB blocking immunity - - Low Rx current of 10 mA, 200 nA register retention - - Fully integrated synthesizer with a resolution of 61 Hz - - Built-in bit synchronizer for clock recovery - - Sync word recognition - - Preamble detection - - 127 dB+ dynamic range RSSI - -- SMA and U.FL RF interface connectors -- Including 50 ohm SMA RF antenna -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability - -- USB ST-LINK functions: -- Board power supply: - - - Through USB bus or external VIN/3.3 V supply voltage or batteries -- 3xAAA-type-battery holder for standalone operation -- 7 LEDs: - - - 4 general-purpose LEDs - - A 5 V-power LED - - An ST-LINK-communication LED - - A fault-power LED - - 2 push-buttons (user and reset) -- Arduino* Uno V3 connectors - -.. image:: img/b_l072z_lrwan1.jpg - :align: center - :alt: B-L072Z-LRWAN1 - -More information about the board can be found at the `B-L072Z-LRWAN1 website`_. - -Hardware -******** - -The STM32L072CZ SoC provides the following hardware IPs: - -- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM* 32-bit Cortex*-M0+ CPU, frequency up to 32 MHz -- Clock Sources: - - - 1 to 32 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) - - Internal multispeed low-power 65 kHz to 4.2 MHz RC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 2x 16-bit with up to 4 channels - - 2x 16-bit with up to 2 channels - - 1x 16-bit ultra-low-power timer - - 1x SysTick - - 1x RTC - - 2x 16-bit basic for DAC - - 2x watchdogs (independent/window) -- Up to 84 fast I/Os, most 5 V-tolerant. -- Memories - - - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 20 KB of SRAM - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 1.14 MSPS - - 2x 12-bit DAC - - 2x ultra-low-power comparators -- 11x communication interfaces - - - USB 2.0 full-speed device, LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 6x SPIs (4x SPIs with the Quad SPI) -- 7-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L072CZ can be found here: - -- `STM32L072CZ on www.st.com`_ -- `STM32L0x2 reference manual`_ - -Supported Features -================== - -The Zephyr B-L072Z-LRWAN1 Discovery board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| LoRa | on-module | sx1276 | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/b_l072z_lrwan1/b_l072z_lrwan1_defconfig`` - - -Connections and IOs -=================== - -B-L072Z-LRWAN1 Discovery kit has GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `B-L072Z-LRWAN1 website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX/RX: PA9/PA10 (Arduino Serial) -- UART_2_TX/RX: PA2/PA3 (ST-Link Virtual COM Port) -- SPI1 NSS/SCK/MISO/MOSI: PA15/PB3/PA6/PA7 (Semtech SX1276 LoRa* Transceiver) -- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 (Arduino SPI) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) - -System Clock ------------- - -B-L072Z-LRWAN1 Discovery board System Clock is at 32MHz. - -Serial Port ------------ - -B-L072Z-LRWAN1 Discovery board has 2 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -USB device ----------- - -B-L072Z-LRWAN1 Discovery board has 1 USB device controller. However, -the USB data lines are not connected to the MCU by default. To connect -the USB data lines to the MCU, short solder bridges SB15 and SB16. - -Programming and Debugging -************************* - -Applications for the ``b_l072z_lrwan1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -B-L072Z-LRWAN1 Discovery board includes an ST-LINK/V2-1 embedded debug -tool interface. This interface is supported by the openocd version included -in the Zephyr SDK since v0.9.2. - - -Flashing an application to B-L072Z-LRWAN1 Discovery board ---------------------------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Connect the B-L072Z-LRWAN1 Discovery board to a STLinkV2 to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l072z_lrwan1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l072z_lrwan1 - :maybe-skip-config: - :goals: debug - -.. _B-L072Z-LRWAN1 website: - https://www.st.com/en/evaluation-tools/b-l072z-lrwan1.html - -.. _STM32L072CZ on www.st.com: - https://www.st.com/en/microcontrollers/stm32l072cz.html - -.. _STM32L0x2 reference manual: - https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/b_l4s5i_iot01a/Kconfig.board b/boards/arm/b_l4s5i_iot01a/Kconfig.board deleted file mode 100644 index 927b683f71e188..00000000000000 --- a/boards/arm/b_l4s5i_iot01a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# B_L4S5I_IOT01A discovery kit configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_L4S5I_IOT01A - bool "STM32L4S5I IOT Discovery kit" - depends on SOC_STM32L4S5XX diff --git a/boards/arm/b_l4s5i_iot01a/Kconfig.defconfig b/boards/arm/b_l4s5i_iot01a/Kconfig.defconfig deleted file mode 100644 index 059f36907a28c5..00000000000000 --- a/boards/arm/b_l4s5i_iot01a/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# B_L4S5I_IOT01A discovery kit board configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_L4S5I_IOT01A - -config BOARD - default "b_l4s5i_iot01a" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -choice LIS3MDL_TRIGGER_MODE - default LIS3MDL_TRIGGER_NONE -endchoice - -choice HTS221_TRIGGER_MODE - default HTS221_TRIGGER_NONE -endchoice - -choice LSM6DSL_TRIGGER_MODE - default LSM6DSL_TRIGGER_GLOBAL_THREAD - depends on LSM6DSL -endchoice - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n -config BT_HCI_VS_EXT - default n - -endif # BT - -endif # BOARD_B_L4S5I_IOT01A diff --git a/boards/arm/b_l4s5i_iot01a/doc/index.rst b/boards/arm/b_l4s5i_iot01a/doc/index.rst deleted file mode 100644 index d5b11c8b30b3ab..00000000000000 --- a/boards/arm/b_l4s5i_iot01a/doc/index.rst +++ /dev/null @@ -1,233 +0,0 @@ -.. _b_l4s5i_iot01a_board: - -ST B_L4S5I_IOT01A Discovery kit -############################### - -Overview -******** - -The B_L4S5I_IOT01A Discovery kit features an ARM Cortex-M4 based STM32L4S5VI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the B_L4S5I_IOT01A Discovery kit: - - -- STM32L4S5VIT6 microcontroller featuring 2 Mbyte of Flash memory, 640 Kbytes of RAM in LQFP100 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Three different interfaces supported on USB: - - - Virtual com port - - Mass storage - - Debug port - -- ARDUINO ® Uno V3 and Pmod TM expansion connector -- 4 LEDs (2 for user, wifi, BLE) -- 2 push-buttons (user and reset) -- USB OTG FS with micro-AB connector -- Dynamic NFC tag -- 2 digital omnidirectional microphones -- Capacitive digital sensor for relative humidity and temperature -- Time-of-flight and gesture-detection sensors -- High-performance 3-axis magnetometer -- 3D accelerometer and 3D gyroscope -- 64-Mbit Quad-SPI Flash memory -- Bluetooth ® 4.1 module -- 802.11 b/g/n compliant Wi‐Fi ® module -- MCU current ammeter with 4 ranges and auto-calibration - -- Flexible power supply options: - - ST-LINK/V2-1 - - USB FS connector - - External 5 V - - -.. image:: img/b-l4s5i_iot01a.jpg - :align: center - :alt: B_L4S5I_IOT01A Discovery kit - -More information about the board can be found at the `B L4S5I IOT01A Discovery kit website`_. - -Hardware -******** - -The STM32L4S5VI SoC provides the following hardware features: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 120 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - 2x 16-bit advanced control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 83 fast I/Os, most 5 V-tolerant -- Memories - - Up to 2 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 640 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Octo SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SDMMC I/F - - DCMI camera interface -- 14-channel DMA controller with multiplex request router -- True random number generator -- CRC calculation unit, 96-bit unique ID -- AES and HASH hardware accelerators -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L4S5VI can be found here: - - `STM32L4S5VI on www.st.com`_ - - `STM32L4S5 reference manual`_ - - -Supported Features -================== - -The Zephyr b_l4s5i_iot01a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| BLE | module | bluetooth | -+-----------+------------+-------------------------------------+ -| WIFI | module | es-wifi | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig`` - - -Connections and IOs -=================== - -B_L4S5I_IOT01A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `B L47S5I IOT01A board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) -- UART_4 TX/RX : PA0/PA1 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) -- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) -- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) -- PWM_2_CH1 : PA15 -- LD1 : PA5 -- LD2 : PB14 -- user button : PC13 - -System Clock ------------- - -B_L4S5I_IOT01A Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -B_L4S5I_IOT01A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -B_L4S5I_IOT01A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to B_L4S5I_IOT01A Discovery kit -------------------------------------------------------- - -Connect the B_L4S5I_IOT01A Discovery kit to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l4s5i_iot01a - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_l4s5i_iot01a - :maybe-skip-config: - :goals: debug - -.. _B L4S5I IOT01A Discovery kit website: - https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html - -.. _B L47S5I IOT01A board User Manual: - https://www.st.com/resource/en/user_manual/dm00698410.pdf - -.. _STM32L4S5VI on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l4s5vi.html - -.. _STM32L4S5 reference manual: - https://www.st.com/resource/en/reference_manual/dm00310109.pdf diff --git a/boards/arm/b_u585i_iot02a/Kconfig.board b/boards/arm/b_u585i_iot02a/Kconfig.board deleted file mode 100644 index 2ef452a9fa5014..00000000000000 --- a/boards/arm/b_u585i_iot02a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# B_U585I_IOT02A discovery kit configuration - -# Copyright (c) 2021 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_B_U585I_IOT02A - bool "STM32U585I IOT Discovery kit" - depends on SOC_STM32U585XX diff --git a/boards/arm/b_u585i_iot02a/Kconfig.defconfig b/boards/arm/b_u585i_iot02a/Kconfig.defconfig deleted file mode 100644 index bc10deca7a21fb..00000000000000 --- a/boards/arm/b_u585i_iot02a/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# B_U585I_IOT02A discovery kit board configuration - -# Copyright (c) 2021 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_B_U585I_IOT02A - -config BOARD - default "b_u585i_iot02a" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -# Get flash configuration for NS image from dts flash partition -config USE_DT_CODE_PARTITION - default y if TRUSTED_EXECUTION_NONSECURE - -if BUILD_WITH_TFM - -# Initial Attestation key provisioned by the BL1 bootloader -config TFM_INITIAL_ATTESTATION_KEY - default y - -config TFM_DUMMY_PROVISIONING - default n - -endif # BUILD_WITH_TFM - -# Disable Flow control -if BT - -config BT_HCI_ACL_FLOW_CONTROL - default n - -endif # BT - -endif # BOARD_B_U585I_IOT02A diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.yaml b/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.yaml deleted file mode 100644 index 0867becc7019e3..00000000000000 --- a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: b_u585i_iot02a_ns -name: ST B_U585I_IOT02A Discovery kit non secure target -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 786 -flash: 512 -vendor: st diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns_defconfig b/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns_defconfig deleted file mode 100644 index 4b6f6ba7f5c53a..00000000000000 --- a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U585XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/b_u585i_iot02a/doc/index.rst b/boards/arm/b_u585i_iot02a/doc/index.rst deleted file mode 100644 index 3121cfc54710f0..00000000000000 --- a/boards/arm/b_u585i_iot02a/doc/index.rst +++ /dev/null @@ -1,439 +0,0 @@ -.. _b_u585i_iot02a_board: - -ST B_U585I_IOT02A Discovery kit -############################### - -Overview -******** - -The B_U585I_IOT02A Discovery kit features an ARM Cortex-M33 based STM32U585AI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the B_U585I_IOT02A Discovery kit: - - -- STM32U585AII6Q microcontroller featuring 2 Mbyte of Flash memory, 786 Kbytes of RAM in UFBGA169 package -- 512-Mbit octal-SPI Flash memory, 64-Mbit octal-SPI PSRAM, 256-Kbit I2C EEPROM -- USB FS, Sink and Source power, 2.5 W power capability -- 802.11 b/g/n compliant Wi-Fi® module from MXCHIP -- Bluetooth Low Energy from STMicroelectronics -- MEMS sensors from STMicroelectronics - - - 2 digital microphones - - Relative humidity and temperature sensor - - 3-axis magnetometer - - 3D accelerometer and 3D gyroscope - - Pressure sensor, 260-1260 hPa absolute digital output barometer - - Time-of-flight and gesture-detection sensor - - Ambient-light sensor - -- 2 push-buttons (user and reset) -- 2 user LEDs - -- Flexible power supply options: - - ST-LINK/V3 - - USB Vbus - - External sources - - -.. image:: img/b-u585i-iot02a.jpg - :align: center - :alt: B_U585I_IOT02A Discovery kit - -More information about the board can be found at the `B U585I IOT02A Discovery kit website`_. - -Hardware -******** - -The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) - -- Security and cryptography - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) and password protected debug - - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure data storage with hardware unique key (HUK) - - Secure Firmware Update support with TF-M - - 2 AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - Active tampers - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - - Active tampers - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - - Internal 48 MHz with clock recovery - -- Power management - - - Embedded regulator (LDO) - - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling - -- RTC with HW calendar and calibration -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 17 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5 x 16-bit general purpose - - 4x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- ART accelerator - - - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and - external memories: up to 160 MHz, MPU, 240 DMIPS and DSP - - 4-Kbyte data cache for external memories - -- Memories - - - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles - - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON - - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - 2 Octo-SPI memory interfaces - -- Rich analog peripherals (independent supply) - - - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling - - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 12-bit DAC, low-power sample and hold - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- Up to 22 communication interfaces - - - USB Type-C / USB power delivery controller - - USB OTG 2.0 full-speed controller - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) - - 1x FDCAN - - 2x SDMMC interface - - 16- and 4-channel DMA controllers, functional in Stop mode - - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with - sound-activity detection - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- True Random Number Generator (RNG) - -- Graphic features - - - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation - - 1 digital camera interface - -- Mathematical co-processor - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - - - -More information about STM32U585AI can be found here: - -- `STM32U585 on www.st.com`_ -- `STM32U585 reference manual`_ - - -Supported Features -================== - -The Zephyr b_u585i_iot02a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| BKP SRAM | on-chip | Backup SRAM | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| RADIO | STM32WB5MMG| Bluetooth Low Energy (BLE) | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig`` - -Zephyr board options -==================== - -The STM32U585i is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for both Secure and Non-Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| b_u585i_iot02a | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| b_u585i_iot02a_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ - -Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: - - .. code-block:: bash - - $ west build -b b_u585i_iot02a_ns samples/tfm_integration/tfm_ipc/ - -Once done, before flashing, you need to first run a generated script that -will set platform option bytes config and erase platform (among others, -option bit TZEN will be set). - - .. code-block:: bash - - $ ./build/tfm/regression.sh - $ west flash - -Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/regression.sh` once more to clean up the board from secure -options and get back the platform back to a "normal" state and be able to run -usual, non-TFM, binaries. -Also note that, even then, TZEN will remain set, and you will need to use -STM32CubeProgrammer_ to disable it fully, if required. - -Connections and IOs -=================== - -B_U585I_IOT02A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `B U585I IOT02A board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- LD1 : PH7 -- LD2 : PH6 -- user button : PC13 -- SPI1 NSS/SCK/MISO/MOSI : PE12/P13/P14/P15 (Arduino SPI) -- I2C_1 SDA/SDL : PB9/PB8 (Arduino I2C) -- I2C_2 SDA/SDL : PH5/PH4 -- DAC1 CH1 : PA4 (STMOD+1) -- ADC1_IN15 : PB0 -- USB OTG : PA11/PA12 -- PWM4 : CN14 PB6 -- PWM3 : CN4 PE4 - -System Clock ------------- - -B_U585I_IOT02A Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -B_U585I_IOT02A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB6`` jumper on the back side of the board. - - -Programming and Debugging -************************* - -B_U585I_IOT02A Discovery kit includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash the board using various tools. - - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -using ``-r openocd``. - -Connect the B_U585I_IOT02A Discovery kit to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: b_u585i_iot02a - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -Default flasher for this board is openocd. It could be used in the usual way. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: b_u585i_iot02a - :goals: debug - -Building a secure/non-secure with Arm |reg| TrustZone |reg| -=========================================================== - -The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| -support. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``b_u585i_iot02a_ns`` as build target. - -.. code-block:: bash - - $ west build -b b_u585i_iot02a_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/api_ns/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash - - -Disabling TrustZone |reg| on the board -====================================== - -If you have flashed a sample to the board that enables TrustZone, you will need -to disable it before you can flash and run a new non-TrustZone sample on the -board. - -To disable TrustZone, it's necessary to change AT THE SAME TIME the ``TZEN`` -and ``RDP`` bits. ``TZEN`` needs to get set from 1 to 0 and ``RDP``, -needs to be set from ``DC`` to ``AA`` (step 3 below). - -This is docummented in the `AN5347, in section 9`_, "TrustZone deactivation". - -However, it's possible that the ``RDP`` bit is not yet set to ``DC``, so you -first need to set it to ``DC`` (step 2). - -Finally you need to set the "Write Protection 1 & 2" bytes properly, otherwise -some memory regions won't be erasable and mass erase will fail (step 4). - -The following command sequence will fully deactivate TZ: - -Step 1: - -Ensure U23 BOOT0 switch is set to 1 (switch is on the left, assuming you read -"BOOT0" silkscreen label from left to right). You need to press "Reset" (B2 RST -switch) after changing the switch to make the change effective. - -Step 2: - -.. code-block:: console - - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob rdp=0xDC - -Step 3: - -.. code-block:: console - - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -tzenreg - -Step 4: - -.. code-block:: console - - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pend=0x0 - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pend=0x0 - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pend=0x0 - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pstrt=0x7f - $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pend=0x0 - - -.. _B U585I IOT02A Discovery kit website: - https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html - -.. _B U585I IOT02A board User Manual: - https://www.st.com/resource/en/user_manual/um2839-discovery-kit-for-iot-node-with-stm32u5-series-stmicroelectronics.pdf - -.. _STM32U585 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html - -.. _STM32U585 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STMicroelectronics customized version of OpenOCD: - https://github.com/STMicroelectronics/OpenOCD - -.. _AN5347, in section 9: - https://www.st.com/resource/en/application_note/dm00625692-stm32l5-series-trustzone-features-stmicroelectronics.pdf diff --git a/boards/arm/bbc_microbit/Kconfig.board b/boards/arm/bbc_microbit/Kconfig.board deleted file mode 100644 index 758673ff32c3b2..00000000000000 --- a/boards/arm/bbc_microbit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 BBC_MICROBIT board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BBC_MICROBIT - bool "BBC MICRO:BIT" - depends on SOC_NRF51822_QFAA diff --git a/boards/arm/bbc_microbit/Kconfig.defconfig b/boards/arm/bbc_microbit/Kconfig.defconfig deleted file mode 100644 index 17decdb0abe506..00000000000000 --- a/boards/arm/bbc_microbit/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# nRF51 BBC_MICROBIT board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BBC_MICROBIT - -config BOARD - default "bbc_microbit" - -config BT_CTLR - default BT - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -endif # FXOS8700 - -endif # BOARD_BBC_MICROBIT diff --git a/boards/arm/bbc_microbit/bbc_microbit_defconfig b/boards/arm/bbc_microbit/bbc_microbit_defconfig deleted file mode 100644 index 8396a17b16f921..00000000000000 --- a/boards/arm/bbc_microbit/bbc_microbit_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAA=y -CONFIG_BOARD_BBC_MICROBIT=y - -# enable GPIO -CONFIG_GPIO=y - -# clock control -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bbc_microbit_v2/Kconfig.board b/boards/arm/bbc_microbit_v2/Kconfig.board deleted file mode 100644 index 8a4457c0d4538b..00000000000000 --- a/boards/arm/bbc_microbit_v2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 BBC_MICROBIT_V2 board configuration - -# Copyright (c) 2020 Lingao Meng -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BBC_MICROBIT_V2 - bool "BBC MICRO:BIT_V2" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/bbc_microbit_v2/Kconfig.defconfig b/boards/arm/bbc_microbit_v2/Kconfig.defconfig deleted file mode 100644 index 4e1288c17d1d73..00000000000000 --- a/boards/arm/bbc_microbit_v2/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 BBC_MICROBIT_V2 board configuration - -# Copyright (c) 2020 Lingao Meng -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BBC_MICROBIT_V2 - -config BOARD - default "bbc_microbit_v2" - -config BT_CTLR - default BT - -endif # BOARD_BBC_MICROBIT_V2 diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2_defconfig b/boards/arm/bbc_microbit_v2/bbc_microbit_v2_defconfig deleted file mode 100644 index f4d34eb3599ba5..00000000000000 --- a/boards/arm/bbc_microbit_v2/bbc_microbit_v2_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_BBC_MICROBIT_V2=y - -# enable GPIO -CONFIG_GPIO=y - -# clock control -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bcm958401m2/Kconfig.board b/boards/arm/bcm958401m2/Kconfig.board deleted file mode 100644 index d7545481fc80f7..00000000000000 --- a/boards/arm/bcm958401m2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config BOARD_VALKYRIE_BCM958401M2 - bool "Broadcom Valkyrie BCM958401M2" - depends on SOC_BCM58400 diff --git a/boards/arm/bcm958401m2/Kconfig.defconfig b/boards/arm/bcm958401m2/Kconfig.defconfig deleted file mode 100644 index 87f3c72e589b32..00000000000000 --- a/boards/arm/bcm958401m2/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. - -config BOARD - default "bcm958401m2" - depends on BOARD_VALKYRIE_BCM958401M2 diff --git a/boards/arm/bcm958401m2/bcm958401m2_defconfig b/boards/arm/bcm958401m2/bcm958401m2_defconfig deleted file mode 100644 index bba050319cdbfc..00000000000000 --- a/boards/arm/bcm958401m2/bcm958401m2_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_VALKYRIE=y -CONFIG_SOC_BCM58400=y -CONFIG_BOARD_VALKYRIE_BCM958401M2=y -CONFIG_XIP=n -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/bcm958401m2/doc/index.rst b/boards/arm/bcm958401m2/doc/index.rst deleted file mode 100644 index a1c1a705c5dc78..00000000000000 --- a/boards/arm/bcm958401m2/doc/index.rst +++ /dev/null @@ -1,58 +0,0 @@ -.. _bcm958401m2: - -Broadcom BCM958401M2 -#################### - -Overview -******** -The Broadcom BCM958401M2 board utilizes the Valkyrie BCM58400 SoC to -provide support for PCIe offload engine functionality. - -Hardware -******** -The BCM958401M2 is a PCIe card with the following physical features: - -* PCIe Gen3 interface -* RS232 UART (optionally populated) -* JTAG (optionally populated) - -Supported Features -================== -The Broadcom BCM958401M2 board configuration supports the following hardware -features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vectored interrupt controller | -+-----------+------------+--------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm/bcm958401m2/bcm958401m2_defconfig`` - -Connections and IOs -=================== - - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. -Board is booted over PCIe interface. - -Debugging -========= -The bcm958401m2 board includes pads for soldering a JTAG connector. -Zephyr applications running on the M7 core can also be tested by observing UART console output. - - -References -********** diff --git a/boards/arm/bcm958402m2_m7/Kconfig.board b/boards/arm/bcm958402m2_m7/Kconfig.board deleted file mode 100644 index ad1491abea8979..00000000000000 --- a/boards/arm/bcm958402m2_m7/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BCM958402M2_M7 - bool "Broadcom Viper BCM958402M2_M7" - depends on SOC_BCM58402_M7 diff --git a/boards/arm/bcm958402m2_m7/Kconfig.defconfig b/boards/arm/bcm958402m2_m7/Kconfig.defconfig deleted file mode 100644 index ce3b9eec627bd4..00000000000000 --- a/boards/arm/bcm958402m2_m7/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "bcm958402m2_m7" - depends on BOARD_BCM958402M2_M7 diff --git a/boards/arm/bcm958402m2_m7/bcm958402m2_m7.yaml b/boards/arm/bcm958402m2_m7/bcm958402m2_m7.yaml deleted file mode 100644 index 21c94f61721305..00000000000000 --- a/boards/arm/bcm958402m2_m7/bcm958402m2_m7.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: bcm958402m2_m7 -name: Broadcom BCM958402M2_M7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -vendor: brcm diff --git a/boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig b/boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig deleted file mode 100644 index 19d83a9afd6d44..00000000000000 --- a/boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_VIPER=y -CONFIG_SOC_BCM58402_M7=y -CONFIG_BOARD_BCM958402M2_M7=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable PCIe EP -CONFIG_PCIE_ENDPOINT=y -CONFIG_PCIE_EP_IPROC=y -CONFIG_PCIE_EP_IPROC_V2=y - -# Enable DMA -CONFIG_DMA=y -CONFIG_DMA_64BIT=y diff --git a/boards/arm/bcm958402m2_m7/doc/index.rst b/boards/arm/bcm958402m2_m7/doc/index.rst deleted file mode 100644 index 7b7cab9e727e5e..00000000000000 --- a/boards/arm/bcm958402m2_m7/doc/index.rst +++ /dev/null @@ -1,51 +0,0 @@ -.. _bcm958402m2_m7: - -Broadcom BCM958402M2 (Cortex-M7) -################################ - -Overview -******** -The Broadcom bcm958402m2_m7 board utilizes the Viper BCM58402_M7 SoC to -provide support for PCIe offload engine functionality. - -Hardware -******** -The bcm958402m2_m7 is a PCIe card with the following physical features: - -* PCIe Gen4 interface -* RS232 UART (optionally populated) -* JTAG (optionally populated) - -Supported Features -================== -The Broadcom bcm958402m2_m7 board configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| NVIC | on-chip | nested vectored interrupt controller | -+-----------+------------+--------------------------------------+ -| UART | on-chip | Compatible with UART NS16550 | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm/bcm958402m2_m7/bcm958402m2_m7_defconfig`` - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. -Board is booted over PCIe interface. - -Debugging -========= -The bcm958402m2_m7 board includes pads for soldering a JTAG connector. -Zephyr applications running on the M7 core can also be tested -by observing UART console output. diff --git a/boards/arm/beagle_bcf/Kconfig.board b/boards/arm/beagle_bcf/Kconfig.board deleted file mode 100644 index f56ad623fa41bf..00000000000000 --- a/boards/arm/beagle_bcf/Kconfig.board +++ /dev/null @@ -1,21 +0,0 @@ -# BeagleConnect Freedom board configuration - -# Copyright (c) 2020 Erik Larson -# Copyright (c) 2021 Jason Kridner, BeagleBoard.org Foundation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BEAGLECONNECT_FREEDOM - bool "BeagleConnect Freedom" - depends on SOC_CC1352P7 - -if BOARD_BEAGLECONNECT_FREEDOM - -config BOARD_ANTENNA_INIT_PRIO - int "Board antenna switch initialization priority" - default 70 - help - Set the priority for board init, must be greater than - KERNEL_INIT_PRIORITY_DEVICE but smaller than - IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. - -endif # BOARD_BEAGLECONNECT_FREEDOM diff --git a/boards/arm/beagle_bcf/Kconfig.defconfig b/boards/arm/beagle_bcf/Kconfig.defconfig deleted file mode 100644 index 6dcf6a6824d10f..00000000000000 --- a/boards/arm/beagle_bcf/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# BeagleConnect Freedom board configuration - -# Copyright (c) 2020 Erik Larson -# Copyright (c) 2020 Jason Kridner, BeagleBoard.org Foundation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BEAGLECONNECT_FREEDOM - -config BOARD - default "beagleconnect_freedom" - -endif # BOARD_BEAGLECONNECT_FREEDOM diff --git a/boards/arm/bl5340_dvk/CMakeLists.txt b/boards/arm/bl5340_dvk/CMakeLists.txt deleted file mode 100644 index 863c8bb599e060..00000000000000 --- a/boards/arm/bl5340_dvk/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA. -# Copyright (c) 2021-2023 Laird Connectivity. -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) -zephyr_library() -zephyr_library_sources(bl5340_dvk_cpunet_reset.c) - -if (CONFIG_BUILD_WITH_TFM) - zephyr_library_include_directories( - $/api_ns/interface/include - ) -endif() - -endif() diff --git a/boards/arm/bl5340_dvk/Kconfig b/boards/arm/bl5340_dvk/Kconfig deleted file mode 100644 index 365da6269e1334..00000000000000 --- a/boards/arm/bl5340_dvk/Kconfig +++ /dev/null @@ -1,62 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2021 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the bl5340_dvk_cpunet for - Bluetooth applications. - -endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -if BOARD_BL5340_DVK_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_BL5340_DVK_CPUNET diff --git a/boards/arm/bl5340_dvk/Kconfig.board b/boards/arm/bl5340_dvk/Kconfig.board deleted file mode 100644 index b969ee535fa97a..00000000000000 --- a/boards/arm/bl5340_dvk/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_BL5340_DVK_CPUAPP - bool "BL5340-DVK (nRF5340) Application MCU" - -config BOARD_BL5340_DVK_CPUAPP_NS - bool "BL5340-DVK (nRF5340) Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_BL5340_DVK_CPUNET - bool "BL5340-DVK (nRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/bl5340_dvk/Kconfig.defconfig b/boards/arm/bl5340_dvk/Kconfig.defconfig deleted file mode 100644 index d87d6d75f37dcf..00000000000000 --- a/boards/arm/bl5340_dvk/Kconfig.defconfig +++ /dev/null @@ -1,131 +0,0 @@ -# BL5340-DVK board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# Copyright (c) 2021-2023 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -config BOARD - default "bl5340_dvk_cpuapp" if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - - -config I2C - default GPIO || DAC - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_BL5340_DVK_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_BL5340_DVK_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_BL5340_DVK_CPUAPP_NS - -endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -config BOARD - default "bl5340_dvk_cpunet" if BOARD_BL5340_DVK_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -config BT_HCI_VS - default y if BT - -# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module -# is mounted to the DVK using standoffs. -# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module -if DISPLAY - -config INPUT_FT5336_INTERRUPT - default y - - -if LVGL - -config LV_Z_VDB_SIZE - default 64 - -config LV_Z_BITS_PER_PIXEL - default 16 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -config LV_COLOR_16_SWAP - default y - -config INPUT - default y - -endif # LVGL - -endif # DISPLAY - -endif # BOARD_BL5340_DVK_CPUAPP || BOARD_BL5340_DVK_CPUAPP_NS - -if BOARD_BL5340_DVK_CPUNET - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT - -config BT_ECC - default y if BT - -endif # BOARD_BL5340_DVK_CPUNET diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts deleted file mode 100644 index 6052502552e635..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.dts +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (c) 2021 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "bl5340_dvk_cpuapp_common.dtsi" - -/ { - model = "Laird Connectivity BL5340 (nRF5340) Application"; - compatible = "lairdconnect,bl5340-dvk-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - zephyr,sram-non-secure-partition = &sram0_ns; - }; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml deleted file mode 100644 index 10ade88c8b192d..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: bl5340_dvk_cpuapp -name: BL5340-DVK-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - counter - - gpio - - i2c - - pwm - - qspi - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dtsi b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dtsi deleted file mode 100644 index 7b51c398c9ff0e..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common.dtsi +++ /dev/null @@ -1,381 +0,0 @@ -/* - * Copyright (c) 2019-2023 Nordic Semiconductor ASA - * Copyright (c) 2021-2023 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "bl5340_dvk_cpuapp_common-pinctrl.dtsi" -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,display = &ili9340; - zephyr,bt-hci-ipc = &ipc0; - }; - - /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ - /* Note TCA9538 does not have configurable internal pull ups/ downs */ - buttons { - compatible = "gpio-keys"; - boot_button0: boot_button { - gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; - label = "Bootloader button (S4)"; - zephyr,code = ; - }; - - button1: button_1 { - gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>; - label = "Push button switch 1 (S1)"; - zephyr,code = ; - }; - - button2: button_2 { - gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>; - label = "Push button switch 2 (S2)"; - zephyr,code = ; - }; - - button3: button_3 { - gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>; - label = "Push button switch 3 (S9)"; - zephyr,code = ; - }; - - button4: button_4 { - gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>; - label = "Push button switch 4 (S10)"; - zephyr,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - led1: led_1 { - gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>; - label = "Blue LED 1"; - }; - led2: led_2 { - gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; - label = "Blue LED 2"; - }; - led3: led_3 { - gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; - label = "Blue LED 3"; - }; - led4: led_4 { - gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>; - label = "Blue LED 4"; - }; - }; - - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft5336>; - swap-xy; - invert-x; - invert-y; - }; - - gpio_fwd: nrf-gpio-forwarder { - compatible = "nordic,nrf-gpio-forwarder"; - status = "okay"; - uart { - gpios = <&gpio1 8 0>, <&gpio1 10 0>, <&gpio1 7 0>, <&gpio1 9 0>; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led1; - led1 = &led2; - led2 = &led3; - led3 = &led4; - sw0 = &button1; - sw1 = &button2; - sw2 = &button3; - sw3 = &button4; - mcuboot-button0 = &button1; - mcuboot-led0 = &led1; - sdhc0 = &sdhc0; - watchdog0 = &wdt0; - accel0 = &lis3dh; - bbram0 = &extrtc0; - spi-flash0 = &mx25r64; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - spi-dev = <&spi2>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9340: ili9340@0 { - compatible = "ilitek,ili9340"; - reg = <0>; - mipi-max-frequency = <32000000>; - rotation = <270>; - width = <320>; - height = <240>; - }; - }; -}; - -&adc { - status = "okay"; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c1 { - compatible = "nordic,nrf-twim"; - status = "okay"; - - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; - at24c256@50 { - compatible = "atmel,at24"; - reg = <0x50>; - size = <32768>; - pagesize = <64>; - address-width = <16>; - timeout = <10>; - }; - - lis3dh: lis3dh@18 { - compatible = "st,lis2dh"; - reg = <0x18>; - irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>, <&gpio0 24 GPIO_ACTIVE_HIGH>; - }; - - ft5336: ft5336@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - }; - - bme680@76 { - compatible = "bosch,bme680"; - reg = <0x76>; - }; - - dac0: mcp4725@60 { - compatible = "microchip,mcp4725"; - reg = <0x60>; - #io-channel-cells = <1>; - }; - - extrtc0: mcp7940n@6f { - compatible = "microchip,mcp7940n"; - reg = <0x6f>; - status = "okay"; - }; - - gpio_exp0: tca9538@70 { - compatible = "ti,tca9538"; - reg = <0x70>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; - }; -}; - -&spi2 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; - pinctrl-names = "default", "sleep"; - enc424j600@0 { - compatible = "microchip,enc424j600"; - reg = <0>; - spi-max-frequency = <8000000>; - int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - }; -}; - -&spi3 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; - pinctrl-names = "default", "sleep"; - sdhc0: sdhc@0 { - reg = <0>; - compatible = "zephyr,sdhc-spi-slot"; - status = "okay"; - spi-max-frequency = <8000000>; - mmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - }; -}; - -&spi4 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&qspi { - status = "okay"; - pinctrl-0 = <&qspi_default>; - pinctrl-1 = <&qspi_sleep>; - pinctrl-names = "default", "sleep"; - mx25r64: mx25r6435f@0 { - compatible = "nordic,qspi-nor"; - reg = <0>; - /* MX25R64 supports only pp and pp4io */ - writeoc = "pp4io"; - /* MX25R64 supports all readoc options */ - readoc = "read4io"; - sck-frequency = <8000000>; - jedec-id = [c2 28 17]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - size = <67108864>; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <35000>; - }; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* 64K */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - /* 640K */ - slot0_partition: partition@10000 { - label = "image-0"; - }; - /* 256K */ - slot0_ns_partition: partition@b0000 { - label = "image-0-nonsecure"; - }; - - /* - * The flash starting at 0x000f8000 and ending at - * 0x000fffff is reserved for use by the application. - */ - - /* - * Storage partition will be used by FCB/NVS - * if enabled. 32K - */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -&mx25r64 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* 640K */ - slot1_partition: partition@0 { - label = "image-1"; - }; - /* 256K */ - slot1_ns_partition: partition@A0000 { - label = "image-1-nonsecure"; - }; - /* 128K */ - scratch_partition: partition@e0000 { - label = "image-scratch"; - reg = <0x000e0000 0x00020000>; - }; - /* 7MB */ - lfs_partition: partition@100000 { - label = "lfs_storage"; - reg = <0x00100000 0x00700000>; - }; - }; -}; - -/ { - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - - sram0_ns: image_ns@20040000 { - /* Non-Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "bl5340_dvk_cpuapp_partition_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig deleted file mode 100644 index 6c21af3695a1a7..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_BL5340_DVK_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Setup clocks -CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y -CONFIG_SOC_LFXO_CAP_INT_7PF=y -CONFIG_SOC_HFXO_CAP_INTERNAL=y -CONFIG_SOC_HFXO_CAP_INT_VALUE_X2=27 diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts deleted file mode 100644 index 9fdcba5f0e30bd..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.dts +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2021 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "bl5340_dvk_cpuapp_common.dtsi" - -/ { - model = "Laird Connectivity BL5340 (nRF5340) Application"; - compatible = "lairdconnect,bl5340-dvk-cpuapp"; - - chosen { - zephyr,sram = &sram0_ns; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_ns_partition; - }; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.yaml b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.yaml deleted file mode 100644 index 5d94e8e7629a55..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: bl5340_dvk_cpuapp_ns -name: BL5340-DVK-application-MCU-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 192 -flash: 192 -supported: - - counter - - gpio - - i2c - - pwm - - spi - - uart - - usb_cdc - - usb_device - - watchdog -vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns_defconfig b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns_defconfig deleted file mode 100644 index 27af7678a3442e..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_BL5340_DVK_CPUAPP_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dtsi b/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dtsi deleted file mode 100644 index b9bd8c73f773f8..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_partition_conf.dtsi +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2019-2020 Nordic Semiconductor ASA - * Copyright (c) 2021 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for bl5340_dvk CPUAPP (Application MCU). - * - * Zephyr build for BL5340 with ARM TrustZone-M support - * implies building Secure and Non-Secure Zephyr images. - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - * Non-Secure image will be placed in slot0_ns, and use - * sram0_ns for system memory. - * - * Note that the Secure image only requires knowledge of - * the beginning of the Non-Secure image (not its size). - */ - -&slot0_partition { - reg = <0x00010000 0xa0000>; -}; - -&slot0_ns_partition { - reg = <0x000b0000 0x40000>; -}; - -&slot1_partition { - reg = <0x00000000 0xa0000>; -}; - -&slot1_ns_partition { - reg = <0x000a0000 0x40000>; -}; - -/* Default SRAM planning when building for nRF5340 with - * ARM TrustZone-M support - * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) - * - Middle 192 kB allocated to Non-Secure image (sram0_ns) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see bl5340_dvk_shared_sram_planning_conf.dtsi) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x40000>; -}; - -&sram0_ns { - reg = <0x20040000 0x30000>; -}; - -/* Include shared RAM configuration file */ -#include "bl5340_dvk_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts deleted file mode 100644 index 2b3eb053283e6c..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021-2023 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "bl5340_dvk_cpunet-pinctrl.dtsi" -#include "bl5340_dvk_cpunet_common.dtsi" - -/ { - model = "Laird Connectivity BL5340 (nRF5340) Network"; - compatible = "lairdconnect,bl5340-dvk-cpunet"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - zephyr,bt-hci-ipc = &ipc0; - }; - - aliases { - watchdog0 = &wdt0; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml deleted file mode 100644 index d8a17394be7a60..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: bl5340_dvk_cpunet -name: BL5340-DVK-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - counter - - gpio - - i2c - - spi - - uart - - watchdog -vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_common.dtsi b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_common.dtsi deleted file mode 100644 index b7bb765444c238..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_common.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2021-2023 Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&flash1 { - /* - * For more information, see: - * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* 48K */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0xc000>; - }; - /* 88K */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x16000>; - }; - /* 88K */ - slot1_partition: partition@22000 { - label = "image-1"; - reg = <0x00022000 0x16000>; - }; - /* 32K */ - storage_partition: partition@38000 { - label = "storage"; - reg = <0x00038000 0x8000>; - }; - }; -}; - -/* Include shared RAM configuration file */ -#include "bl5340_dvk_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig b/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig deleted file mode 100644 index c68fdfc931218a..00000000000000 --- a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_BL5340_DVK_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl5340_dvk/board.cmake b/boards/arm/bl5340_dvk/board.cmake deleted file mode 100644 index 398b454e4a855f..00000000000000 --- a/boards/arm/bl5340_dvk/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_BL5340_DVK_CPUAPP_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_BOARD_BL5340_DVK_CPUAPP OR CONFIG_BOARD_BL5340_DVK_CPUAPP_NS) -board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_TFM_FLASH_MERGED_BINARY) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - -if(CONFIG_BOARD_BL5340_DVK_CPUNET) -board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/bl5340_dvk/doc/index.rst b/boards/arm/bl5340_dvk/doc/index.rst deleted file mode 100644 index 544250baa8420c..00000000000000 --- a/boards/arm/bl5340_dvk/doc/index.rst +++ /dev/null @@ -1,436 +0,0 @@ -.. _bl5340_dvk: - -Laird Connectivity BL5340 DVK -############################# - -Overview -******** -The BL5340 Development Kit provides support for the Laird Connectivity -BL5340 module which is powered by a dual-core Nordic Semiconductor -nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a -dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running - at a fixed 64 MHz, referred to as the **network core**. - -The bl5340_dvk_cpuapp build target provides support for the application -core on the BL5340 module. The bl5340_dvk_cpunet build target provides -support for the network core on the BL5340 module. If ARM TrustZone is -used then the bl5340_dvk_cpuapp build target provides support for the -non-secure partition of the application core on the BL5340 module. - -This development kit has the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`I2S (Inter-Integrated Sound)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/bl5340_dvk_top.jpg - :align: center - :alt: BL5340 DVK - - BL5340 DVK (Credit: Laird Connectivity) - -More information about the module can be found on the -`BL5340 homepage`_. - -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -The BL5340 DVK has two external oscillators. The frequency of -the slow clock is 32.768KHz. The frequency of the main clock -is 32MHz. - -Supported Features -================== - -The bl5340_dvk_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The bl5340_dvk_cpunet board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ -for a complete list of hardware features. - -Connections and IOs -=================== - -An eight-pin GPIO port expander is used to provide additional inputs -and outputs to the BL5340 module. - -Refer to the `TI TCA9538 datasheet`_ for further details. - -LEDs ----- - -* LED1 (blue) = via TCA9538 port expander channel P4 (active low) -* LED2 (blue) = via TCA9538 port expander channel P5 (active low) -* LED3 (blue) = via TCA9538 port expander channel P6 (active low) -* LED4 (blue) = via TCA9538 port expander channel P7 (active low) - -Push buttons ------------- - -* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low) -* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low) -* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low) -* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low) -* BOOT = boot (active low) - -External Memory -=============== - -Several external memory sources are available for the BL5340 DVK. These -are described as follows. - -Flash Memory ------------- - -A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is -incorporated for application image storage and large datasets. - -Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details. - -EEPROM Memory -------------- - -A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for -storage of infrequently updated data and small datasets. - -Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details. - -External Memory ---------------- - -An on-board micro SD card slot is available for use with micro SD cards. - -Sensors -======= - -The BL5340 DVK incorporates two sensors for user application testing. -These are described as follows. - -Temperature, Pressure, Humidity & Air Quality Sensor ----------------------------------------------------- - -A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is -available via I2C for environmental measurement applications. - -Refer to the `Bosch BME680 datasheet`_ for further details. - -3-Axis Accelerometer --------------------- - -An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C -for vibration and motion detection applications. - -Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details. - -Ethernet -======== - -Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip -ENC424J600 Ethernet controller. - -Refer to the `Microchip ENC424J600 datasheet`_ for further details. - -TFT Display & Capacitive Touch Screen Controller -================================================ - -A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch -controller is included with the BL5340 DVK for user interface -application features. - -Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the -display. - -An ILI9341 TFT controller is incorporated in the TFT module and -acts as the main controller, controlled via SPI. - -Refer to the `ILI9341 datasheet`_ for further details. - -An FT6206 Capacitive Touch Controller, controlled via I2C is -also incorporated in the TFT module. - -Refer to the `FT6206 datasheet`_ for further details. - -Real-Time Clock -=============== - -A real-time clock is available for accurate time data availability. - -Refer to the `Microchip MCP7940N datasheet`_ for further details. - -DAC -=== - -A 10-bit Digital to Analog Converter is incorporated for generation of -variable voltages. - -Refer to the `Microchip MCP4725 datasheet`_ for further details. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_) on the application - core. The IDAU is implemented with the System Protection Unit and is - used to define secure and non-secure memory maps. By default, all of - the memory space (Flash, SRAM, and peripheral address space) is - defined to be secure accessible only. -- Secure boot. - -Programming and Debugging -************************* - -The BL5340's application core supports the Armv8-M Security Extension. -Applications built for the bl5340_dvk_cpuapp board by default -boot in the Secure state. - -The BL5340's network core does not support the Armv8-M Security -Extension. The IDAU may configure bus accesses by the network core to -have Secure attribute set; the latter allows to build and run Secure -only applications on the BL5340 module. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the BL5340 module may contain a Secure and a Non-Secure -firmware image for the application core. The Secure image can be built -using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure -firmware images are always built using Zephyr. The two alternatives are -described below. - -.. note:: - - By default the Secure image for BL5340's application core is - built using TF-M. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the -Non-Secure firmware image using Zephyr requires the following steps: - -1. Build the Non-Secure Zephyr application - for the application core using ``-DBOARD=bl5340_dvk_cpuapp_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output image binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may - be required, to adjust the Non-Secure image Flash and SRAM starting - address and sizes. - -2. Build the application firmware for the network core using - ``-DBOARD=bl5340_dvk_cpunet``. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process to build the Secure and the Non-Secure firmware images -using Zephyr requires the following steps: - -1. Build the Secure Zephyr application for the application core - using ``-DBOARD=bl5340_dvk_cpuapp`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` - in the application project configuration file. -2. Build the Non-Secure Zephyr application for the application core - using ``-DBOARD=bl5340_dvk_cpuapp_ns``. -3. Merge the two binaries together. -4. Build the application firmware for the network core using - ``-DBOARD=bl5340_dvk_cpunet``. - -When building a Secure/Non-Secure application for the BL5340's -application core, the Secure application will have to set the IDAU -(SPU) configuration to allow Non-Secure access to all CPU resources -utilized by the Non-Secure application firmware. SPU configuration -shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=bl5340_dvk_cpuapp`` for -the firmware running on the BL5340's application core, and using -``-DBOARD=bl5340_dvk_cpunet`` for the firmware running -on the BL5340's network core. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then you can build and flash -applications as usual (:ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The BL5340 has a flash read-back protection feature. When flash - read-back protection is active, you will need to recover the chip - before reflashing. If you are flashing with - :ref:`west `, run this command for more - details on the related ``--recover`` option: - - .. code-block:: console - - west flash -H -r nrfjprog --skip-rebuild - -.. note:: - - Flashing and debugging applications on the BL5340 DVK requires - upgrading the nRF Command Line Tools to version 10.12.0 or newer. - Further information on how to install the nRF Command Line Tools can - be found in :ref:`nordic_segger_flashing`. - -Here is an example for the :ref:`hello_world` application running on the -BL5340's application core. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BL5340 DVK board -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: bl5340_dvk_cpuapp - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -boards with a Segger IC. - -Testing Bluetooth on the BL5340 DVK -*********************************** -Many of the Bluetooth examples will work on the BL5340 DVK. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _BL5340 homepage: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 -.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf -.. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C256C_DS_Cu.pdf -.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf -.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf -.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf -.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf -.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf -.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf -.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf -.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/bl652_dvk/Kconfig.board b/boards/arm/bl652_dvk/Kconfig.board deleted file mode 100644 index e5c2bf8bd4c095..00000000000000 --- a/boards/arm/bl652_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL652 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL652_DVK - bool "BL652 DVK" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/bl652_dvk/Kconfig.defconfig b/boards/arm/bl652_dvk/Kconfig.defconfig deleted file mode 100644 index 56dbfebfca9b86..00000000000000 --- a/boards/arm/bl652_dvk/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# BL652 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL652_DVK - -config BOARD - default "bl652_dvk" - -config BT_CTLR - default BT - -if DAC - -config I2C - default y - -endif # DAC - -endif # BOARD_BL652_DVK diff --git a/boards/arm/bl653_dvk/Kconfig.board b/boards/arm/bl653_dvk/Kconfig.board deleted file mode 100644 index 4a6ca61c3e6acd..00000000000000 --- a/boards/arm/bl653_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL653 DVK board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL653_DVK - bool "BL653 DVK" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/bl653_dvk/Kconfig.defconfig b/boards/arm/bl653_dvk/Kconfig.defconfig deleted file mode 100644 index e4f82f99c33d21..00000000000000 --- a/boards/arm/bl653_dvk/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# BL653 DVK board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL653_DVK - -config BOARD - default "bl653_dvk" - -config BT_CTLR - default BT - -if DAC - -config I2C - default y - -endif # DAC - -endif # BOARD_BL653_DVK diff --git a/boards/arm/bl654_dvk/Kconfig.board b/boards/arm/bl654_dvk/Kconfig.board deleted file mode 100644 index 4c666d5aabafc6..00000000000000 --- a/boards/arm/bl654_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL654 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL654_DVK - bool "BL654 DVK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bl654_dvk/Kconfig.defconfig b/boards/arm/bl654_dvk/Kconfig.defconfig deleted file mode 100644 index 53bf5238687541..00000000000000 --- a/boards/arm/bl654_dvk/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# BL654 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL654_DVK - -config BOARD - default "bl654_dvk" - -config BT_CTLR - default BT - -if DAC - -config I2C - default y - -endif # DAC - -endif # BOARD_BL654_DVK diff --git a/boards/arm/bl654_sensor_board/Kconfig.board b/boards/arm/bl654_sensor_board/Kconfig.board deleted file mode 100644 index 6e68f886c436e1..00000000000000 --- a/boards/arm/bl654_sensor_board/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL654 Sensor Board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL654_SENSOR_BOARD - bool "BL654 Sensor Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bl654_sensor_board/Kconfig.defconfig b/boards/arm/bl654_sensor_board/Kconfig.defconfig deleted file mode 100644 index 4ca294e8990694..00000000000000 --- a/boards/arm/bl654_sensor_board/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BL654 Sensor Board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL654_SENSOR_BOARD - -config BOARD - default "bl654_sensor_board" - -config BT_CTLR - default BT - -endif # BOARD_BL654_SENSOR_BOARD diff --git a/boards/arm/bl654_usb/Kconfig.board b/boards/arm/bl654_usb/Kconfig.board deleted file mode 100644 index 49f4dc67fad1b9..00000000000000 --- a/boards/arm/bl654_usb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BL654 USB adapter board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BL654_USB - bool "BL654 USB" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bl654_usb/Kconfig.defconfig b/boards/arm/bl654_usb/Kconfig.defconfig deleted file mode 100644 index 573746037f8a37..00000000000000 --- a/boards/arm/bl654_usb/Kconfig.defconfig +++ /dev/null @@ -1,62 +0,0 @@ -# BL654 USB adapter board configuration - -# Copyright (c) 2021-2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BL654_USB - -config BOARD - default "bl654_usb" - -# To let the nRF5 bootloader load an application, the application -# must be linked after Nordic MBR, that is factory-programmed on the board. - -# Nordic nRF5 bootloader exists outside of the partitions specified in the -# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR, and limit the maximum size to not protude into -# the bootloader at the end of flash. - -# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION -# which will make it link into the correct partition specified in DTS file, -# so no override or limit is necessary. - -config FLASH_LOAD_OFFSET - default 0x1000 - depends on !USE_DT_CODE_PARTITION - -config FLASH_LOAD_SIZE - default 0xdf000 - depends on !USE_DT_CODE_PARTITION - -config USB_CDC_ACM - default n if USB_DEVICE_BLUETOOTH - -if BL654_USB_SERIAL_BACKEND_CDCACM - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -endif #BL654_USB_SERIAL_BACKEND_CDCACM - -config BT_CTLR - default BT - -endif # BOARD_BL654_USB diff --git a/boards/arm/black_f407ve/Kconfig.board b/boards/arm/black_f407ve/Kconfig.board deleted file mode 100644 index c4711fb2c49c61..00000000000000 --- a/boards/arm/black_f407ve/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# black_f407ve board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BLACK_F407VE - bool "Black F407VE Development Board" - depends on SOC_STM32F407XE diff --git a/boards/arm/black_f407ve/Kconfig.defconfig b/boards/arm/black_f407ve/Kconfig.defconfig deleted file mode 100644 index ebc572bea3992f..00000000000000 --- a/boards/arm/black_f407ve/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# black_f407ve board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BLACK_F407VE - -config BOARD - default "black_f407ve" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACK_F407VE diff --git a/boards/arm/black_f407ve/doc/index.rst b/boards/arm/black_f407ve/doc/index.rst deleted file mode 100644 index 4862514d48034d..00000000000000 --- a/boards/arm/black_f407ve/doc/index.rst +++ /dev/null @@ -1,244 +0,0 @@ -.. _black_f407ve_board: - -Black STM32 F407VE Development Board -#################################### - -Overview -******** - -The BLACK_F407VE board features an ARM Cortex-M4 based STM32F407xx MCU -with a wide range of connectivity support and configurations. There are -multiple version of this board like ``black_f407ve``. -Here are some highlights of the BLACK_F407VE board: - -- STM32 microcontroller in LQFP100 package -- Extension header for all LQFP100 I/Os for quick connection to prototyping - board and easy probing -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V) - - Power management access point - -- Three LEDs: - - - 3.3 V power on (LD0) - - Two user LEDs: green (LD1), green (LD2) - -- Four push-buttons: RESET, K0, K1 and WK_UP -- Mini-AB connector - -.. image:: img/black_f407ve.jpg - :align: center - :alt: BLACK_F407VE - -See also board descriptions at `STM32-base website`_, -`STM32F407VET6 black board`_ and `MCUDev Black STM32F407VET6`_ - -.. warning:: The +5V pins on this board are directly connected to the +5V pin - of the USB connector. There is no protection in place. Do not - power this board through USB and an external power supply at - the same time. - - -Hardware -******** - -BLACK_F407VE board provides the following hardware components: - -- STM32F407VET6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 8MHz system crystal -- 32.768KHz RTC crystal -- JTAG/SWD header -- 512 kB Flash -- 192+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC battery CR1220 -- Advanced-control Timer (2) -- General Purpose Timers (12) -- Watchdog Timers (2) -- USART (3), UART (2) -- I2C (3) -- I2S (2) -- SPI (3) -- SDIO (1) -- CAN (2) -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- CRC calculation unit -- True random number generator -- DMA Controller -- Micro SD -- 1x 10/100 Ethernet MAC -- 1x 8 to 12-bit Parallel Camera interface -- Micro USB for power and comms -- 2x jumpers for bootloader selection -- 2x16 FMSC LCD Interface -- NRF24L01 socket -- Dimensions: 85.1mm x 72.45mm - -More information about STM32F407VE SOC can be found here: - - `STM32F407VE on www.st.com`_ - -Supported Features -================== - -The Zephyr black_f407ve board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver. - Zephyr default configuration uses CAN_2 exclusively, as - simultaneous use of CAN_1 and CAN_2 is not yet supported. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/black_f407_generic/black_f407ve_defconfig`` - - -Pin Mapping -=========== - -BLACK_F407VE has 5 GPIO controllers. These controllers are responsible for pin -muxing, input/output, pull-up, etc. - -.. image:: img/stm32f407vet6_left02.jpg - :align: center - :alt: left pins - -.. image:: img/stm32f407vet6_right01.jpg - :align: center - :alt: right pins - -.. image:: img/stm32f407vet6_st-link02.jpg - :align: center - :alt: bottom and top pins - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PA0 -- LD3 : PD13 -- LD4 : PD12 -- LD5 : PD14 -- LD6 : PD15 -- USB DM : PA11 -- USB DP : PA12 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- CAN2_RX : PB12 -- CAN2_TX : PB13 -- SPI1 MISO : PB4 -- SPI1 MOSI : PB5 -- SPI1 SCK : PB3 -- SPI1 Flash CS : PB0 -- SPI2 MISO : PC2 -- SPI2 MOSI : PC3 -- SPI2 SCK : PB10 - -System Clock -============ - -BLACK_F407VE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock -at 168MHz, driven by 8MHz high speed external clock. - -Serial Port -=========== - -BLACK_F407VE has up to 6 UARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. -Please note that ST-Link Virtual Com Port is not wired to chip serial port. -In order to enable console output you should use a serial cable and connect -it to UART1 pins (PA9/PA10). - - -Programming and Debugging -************************* - -Applications for the ``black_f407ve`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -BLACK_F407VE board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to BLACK_F407VE ---------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: black_f407ve - :goals: build flash - -You should see user led "LD1" blinking. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: black_f407ve - :maybe-skip-config: - :goals: debug - -.. _STM32-base website: - https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0.html - -.. _STM32F407VE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f407ve.html - -.. _STM32F407VET6 black board: - https://os.mbed.com/users/hudakz/code/STM32F407VET6_Hello/ - -.. _MCUDev Black STM32F407VET6: - https://github.com/mcauser/BLACK_F407VE diff --git a/boards/arm/black_f407zg_pro/Kconfig.board b/boards/arm/black_f407zg_pro/Kconfig.board deleted file mode 100644 index 8322175e4ba637..00000000000000 --- a/boards/arm/black_f407zg_pro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# black_f407zg board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BLACK_F407ZG_PRO - bool "Black F407ZG Pro Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/black_f407zg_pro/Kconfig.defconfig b/boards/arm/black_f407zg_pro/Kconfig.defconfig deleted file mode 100644 index bdfcf3314431f3..00000000000000 --- a/boards/arm/black_f407zg_pro/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# black_f407zg board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BLACK_F407ZG_PRO - -config BOARD - default "black_f407zg_pro" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACK_F407ZG_PRO diff --git a/boards/arm/black_f407zg_pro/doc/index.rst b/boards/arm/black_f407zg_pro/doc/index.rst deleted file mode 100644 index 4646149a71eb36..00000000000000 --- a/boards/arm/black_f407zg_pro/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _black_f407zg_pro_board: - -Black STM32 F407ZG Pro Development Board -######################################## - -Overview -******** - -The BLACK_F407ZG_PRO board features an ARM Cortex-M4 based STM32F407zg MCU -with a wide range of connectivity support and configurations. There are -multiple version of this board like ``black_f407ve``. -Here are some highlights of the BLACK_F407ZG_PRO board: - -- STM32 microcontroller in LQFP144 package -- Extension header for all LQFP144 I/Os for quick connection to prototyping - board and easy probing -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V) - - Power management access point - -- Three LEDs: - - - 3.3 V power on (LD0) - - Two user LEDs: green (LD1), green (LD2) - -- Four push-buttons: RESET, K0, K1 and WK_UP -- Mini-AB connector - -.. image:: img/black_f407zg_pro.jpg - :align: center - :alt: BLACK_F407ZG_PRO - -.. warning:: The +5V pins on this board are directly connected to the +5V pin - of the USB connector. There is no protection in place. Do not - power this board through USB and an external power supply at - the same time. - - -Hardware -******** - -BLACK_F407ZG_PRO board provides the following hardware components: - -- STM32F407ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 8MHz system crystal -- 32.768KHz RTC crystal -- JTAG/SWD header -- 1024 kB Flash -- 192+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC battery CR1220 -- Advanced-control Timer (2) -- General Purpose Timers (12) -- Watchdog Timers (2) -- USART (3), UART (2) -- I2C (3) -- I2S (2) -- SPI (3) -- SDIO (1) -- CAN (2) -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- CRC calculation unit -- True random number generator -- DMA Controller -- Micro SD -- 1x 10/100 Ethernet MAC -- 1x 8 to 12-bit Parallel Camera interface -- Micro USB for power and comms -- 2x jumpers for bootloader selection -- 2x16 FMSC LCD Interface -- NRF24L01 socket -- Dimensions: 102.5mm x 74.56mm - -More information about STM32F407ZG SOC can be found here: - - `STM32F407ZG on www.st.com`_ - -Supported Features -================== - -The Zephyr black_f407zg_pro board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver. - Zephyr default configuration uses CAN_2 exclusively, as - simultaneous use of CAN_1 and CAN_2 is not yet supported. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/black_f407_generic/black_f407zg_pro_defconfig`` - - -Pin Mapping -=========== - -BLACK_F407ZG_PRO has 7 GPIO controllers. These controllers are responsible for pin -muxing, input/output, pull-up, etc. - - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PA0 -- LD3 : PD13 -- LD4 : PD12 -- LD5 : PD14 -- LD6 : PD15 -- USB DM : PA11 -- USB DP : PA12 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- CAN2_RX : PB12 -- CAN2_TX : PB13 -- SPI2 MISO : PC2 -- SPI2 MOSI : PC3 -- SPI2 SCK : PB10 - -System Clock -============ - -BLACK_F407ZG_PRO System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock -at 168MHz, driven by 8MHz high speed external clock. - -Serial Port -=========== - -BLACK_F407ZG_PRO has up to 6 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. -Please note that ST-Link Virtual Com Port is not wired to chip serial port. -In order to enable console output you should use a serial cable and connect -it to UART2 pins (PA2/PA3). - - -Programming and Debugging -************************* - -Applications for the ``black_f407zg_pro`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -BLACK_F407ZG_PRO board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to BLACK_F407ZG_PRO -------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: black_f407zg_pro - :goals: build flash - -You should see user led "LD1" blinking. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: black_f407zg_pro - :maybe-skip-config: - :goals: debug - -.. _STM32F407ZG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32f407zg.html diff --git a/boards/arm/blackpill_f401cc/Kconfig.board b/boards/arm/blackpill_f401cc/Kconfig.board deleted file mode 100644 index cb4004e248a8e7..00000000000000 --- a/boards/arm/blackpill_f401cc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# STM32F401CC based Black Pill V3.0+ board configuration - -config BOARD_BLACKPILL_F401CC - bool "WeAct Studio Black Pill V3.0+ Board" - depends on SOC_STM32F401XC diff --git a/boards/arm/blackpill_f401cc/Kconfig.defconfig b/boards/arm/blackpill_f401cc/Kconfig.defconfig deleted file mode 100644 index fb31f4eff61eba..00000000000000 --- a/boards/arm/blackpill_f401cc/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# F401CE based Black Pill V3.0+ board board configuration - -if BOARD_BLACKPILL_F401CC - -config BOARD - default "blackpill_f401cc" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACKPILL_F401CC diff --git a/boards/arm/blackpill_f401cc/doc/index.rst b/boards/arm/blackpill_f401cc/doc/index.rst deleted file mode 100644 index 8c662a11fdad3c..00000000000000 --- a/boards/arm/blackpill_f401cc/doc/index.rst +++ /dev/null @@ -1,174 +0,0 @@ -.. _blackpill_f401cc: - -WeAct Studio Black Pill V1.2 -############################ - -Overview -******** - -The WeAct Black Pill V1.2 Board is an extremely low cost and bare-bones -development board featuring the STM32F401CC, see `STM32F401CC website`_. -This is the 48-pin variant of the STM32F401x series, -see `STM32F401x reference manual`_. More info about the board available -`here `_ and on `WeAct Github`_. - -.. image:: img/blackpill-v3.jpg - :align: center - :alt: Black Pill V3.0+ - -Hardware -******** - -The STM32F401CC based Black Pill V3.0+ Board provides the following -hardware components: - -- STM32F401CCU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 256 KB Flash -- 64 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr blackpill_f401ce board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig`` - -Pin Mapping -=========== - -Available pins: ---------------- -.. image:: img/Blackpill_Pinout.jpg - :align: center - :alt: Black Pill V1.2 Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- USER_PB : PA0 -- USER_LED : PC13 - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 84MHz, which is the maximum possible frequency -to achieve a stable USB clock (42MHz). - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: blackpill_f401cc - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _board release notes: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _WeAct Github: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F401CC website: - https://www.st.com/en/microcontrollers/stm32f401cc.html - -.. _STM32F401x reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f401ce/Kconfig.board b/boards/arm/blackpill_f401ce/Kconfig.board deleted file mode 100644 index 666a12a157d60c..00000000000000 --- a/boards/arm/blackpill_f401ce/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020 Kalyan Sriram -# SPDX-License-Identifier: Apache-2.0 - -# STM32F401CE based Black Pill V3.0+ board configuration - -config BOARD_BLACKPILL_F401CE - bool "WeAct Studio Black Pill V3.0+ Board" - depends on SOC_STM32F401XE diff --git a/boards/arm/blackpill_f401ce/Kconfig.defconfig b/boards/arm/blackpill_f401ce/Kconfig.defconfig deleted file mode 100644 index 739c5512170ede..00000000000000 --- a/boards/arm/blackpill_f401ce/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020 Kalyan Sriram -# SPDX-License-Identifier: Apache-2.0 - -# F401CE based Black Pill V3.0+ board board configuration - -if BOARD_BLACKPILL_F401CE - -config BOARD - default "blackpill_f401ce" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACKPILL_F401CE diff --git a/boards/arm/blackpill_f401ce/doc/index.rst b/boards/arm/blackpill_f401ce/doc/index.rst deleted file mode 100644 index 265d0fd038e68e..00000000000000 --- a/boards/arm/blackpill_f401ce/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _blackpill_f401ce: - -WeAct Studio Black Pill V3.0 -############################ - -Overview -******** - -The WeAct Black Pill V3.0 Board is an extremely low cost and bare-bones -development board featuring the STM32F401CE, see `STM32F401CE website`_. -This is the 48-pin variant of the STM32F401x series, -see `STM32F401x reference manual`_. More info about the board available -`here `_ and on `WeAct Github`_. - -.. image:: img/blackpill-v3.jpg - :align: center - :alt: Black Pill V3.0+ - -Hardware -******** - -The STM32F401CE based Black Pill V3.0+ Board provides the following -hardware components: - -- STM32F401CEU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 96 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr blackpill_f401ce board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig`` - -Pin Mapping -=========== - -Available pins: ---------------- -.. image:: img/Blackpill_Pinout.jpg - :align: center - :alt: Black Pill V3.0+ Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- USER_PB : PA0 -- USER_LED : PC13 - -Note on SPI pin mapping: According to the `board release notes`_, there was a brief -change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. -This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using -V2.0 and en external flash, the pinmux will need to be modified accordingly. - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 84MHz, which is the maximum possible frequency -to achieve a stable USB clock (42MHz). - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: blackpill_f401ce - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _board release notes: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _WeAct Github: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F401CEU6-WeAct-Black-Pill-V3.0.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F401CE website: - https://www.st.com/en/microcontrollers/stm32f401ce.html - -.. _STM32F401x reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f411ce/Kconfig.board b/boards/arm/blackpill_f411ce/Kconfig.board deleted file mode 100644 index c636f2af74a0ed..00000000000000 --- a/boards/arm/blackpill_f411ce/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# STM32F411CE based Black Pill V2.0+ board configuration - -config BOARD_BLACKPILL_F411CE - bool "WeAct Studio Black Pill V2.0+ Board" - depends on SOC_STM32F411XE diff --git a/boards/arm/blackpill_f411ce/Kconfig.defconfig b/boards/arm/blackpill_f411ce/Kconfig.defconfig deleted file mode 100644 index e54fc87004e640..00000000000000 --- a/boards/arm/blackpill_f411ce/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# F411CE based Black Pill V2.0+ board board configuration - -if BOARD_BLACKPILL_F411CE - -config BOARD - default "blackpill_f411ce" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_BLACKPILL_F411CE diff --git a/boards/arm/blackpill_f411ce/doc/index.rst b/boards/arm/blackpill_f411ce/doc/index.rst deleted file mode 100644 index 4d3023b462cd29..00000000000000 --- a/boards/arm/blackpill_f411ce/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _blackpill_f411ce: - -WeAct Studio Black Pill V2.0 -############################ - -Overview -******** - -The WeAct Black Pill V2.0 Board is an extremely low cost and bare-bones -development board featuring the STM32F411CE, see `STM32F411CE website`_. -This is the 48-pin variant of the STM32F411x series, -see `STM32F411x reference manual`_. More info about the board available -`here `_ and on `WeAct Github`_. - -.. image:: img/blackpill-v2.jpg - :align: center - :alt: Black Pill V2.0+ - -Hardware -******** - -The STM32F411CE based Black Pill V2.0+ Board provides the following -hardware components: - -- STM32F411CEU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr blackpill_f411ce board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32_blackpill_v2/stm32_blackpill_v2_defconfig`` - -Pin Mapping -=========== - -Available pins: ---------------- -.. image:: img/Blackpill_Pinout.jpg - :align: center - :alt: Black Pill V2.0+ Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- USER_PB : PA0 -- USER_LED : PC13 - -Note on SPI pin mapping: According to the `board release notes`_, there was a brief -change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. -This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using -V2.0 and en external flash, the pinmux will need to be modified accordingly. - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 96MHz, which is the maximum possible frequency -to achieve a stable USB clock (48MHz). - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: blackpill_f411ce - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _board release notes: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _WeAct Github: - https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0.html - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F411CE website: - https://www.st.com/en/microcontrollers/stm32f411ce.html - -.. _STM32F411x reference manual: - https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.board b/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.board deleted file mode 100644 index a4a2f1fab18daf..00000000000000 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Blue Clover PLT Demo V2 Configuration - -# Copyright (c) 2021 Blue Clover -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 - bool "Blue Clover PLT Demo Board V2" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.defconfig b/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.defconfig deleted file mode 100644 index d1d96ca9fb0393..00000000000000 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Blue Clover PLT Demo V2 Configuration - -# Copyright (c) 2021 Blue Clover -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 - -config BOARD - default "blueclover_plt_demo_v2_nrf52832" - -config BT_CTLR - default BT - -config I2C - default SENSOR - -endif # BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/index.rst b/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/index.rst deleted file mode 100644 index 7a41d95e6472de..00000000000000 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/index.rst +++ /dev/null @@ -1,153 +0,0 @@ -.. _blueclover_plt_demo_v2_nrf52832: - -Blue Clover PLT Demo V2 nRF52832 -################################ - -Overview -******** - -The Blue Clover PLT Demo V2 is an open source (OSWHA certified) hardware -product, featuring the Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU -and several useful external peripherals. - -The Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU features the following: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/blueclover_plt_demo_v2.jpg - :align: center - :alt: Blue Clover PLT Demo V2 nRF52832 - -Hardware -******** - -- nRF52832 ARM Cortex-M4F processor at 64 MHz -- 512 KB flash memory and 64 KB of SRAM -- Bosch BMI270 IMU -- Sensiron SHT30 Humidity and Temperature sensor -- Murata PKLCS1212E4001R1 Piezo Buzzer -- Battery connector and charger for 3.7 V lithium polymer batteries -- 4 APA102C Addressable LEDs -- Reset button (can be configured as user button) -- 1 User button -- Tag-Connect TC2030-FP 6-pin Debug Connector - -Supported Features -================== - -The Blue Clover PLT Demo V2 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -Push buttons ------------- - -* RESET = P0.21 -* STATUS = P0.26 - -UART ----- - -* TXD = P0.06 -* RXD = P0.08 - -Power ------ - -* USB-C Connector -* JST-PH Battery Connector - -NFC ---- - -* U.FL Connector, on NFC1/P0.09, NFC2/P0.10 - -Programming and Debugging -************************* - -Applications for the ``blueclover_plt_demo_v2_nrf52832`` board configuration -can be built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing -======== - -Flashing Zephyr onto the ``blueclover_plt_demo_v2_nrf52832`` board requires -an external programmer. The programmer is attached to the SWD header. - -Build the Zephyr kernel and the :zephyr:code-sample:`led-apa102` sample application. - - .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_apa102 - :board: blueclover_plt_demo_v2_nrf52832 - :goals: build - :compact: - -Flash the image. - - .. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_apa102 - :board: blueclover_plt_demo_v2_nrf52832 - :goals: flash - :compact: - -References -********** - -.. target-notes:: - -.. _Blue Clover PLT Demo V2 Product site: - https://bcdevices.com/products/plt-demo-board - -.. _Blue Clover PLT Demo V2 OSWHA Certification: - https://certification.oshwa.org/us002054.html - -.. _Schematic, layout, and gerbers: - https://github.com/bcdevices/plt-docs/tree/master/PLT-DEMOv2 diff --git a/boards/arm/bt510/Kconfig.board b/boards/arm/bt510/Kconfig.board deleted file mode 100644 index e1654936f5fabb..00000000000000 --- a/boards/arm/bt510/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BT510 DVK board configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BT510 - bool "BT510" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bt510/Kconfig.defconfig b/boards/arm/bt510/Kconfig.defconfig deleted file mode 100644 index dc622170dd1be6..00000000000000 --- a/boards/arm/bt510/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# BT510 Sensor configuration - -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BT510 - -config BOARD - default "bt510" - -config BT_CTLR - default BT - -config I2C - default SENSOR - -endif # BOARD_BT510 diff --git a/boards/arm/bt610/Kconfig.board b/boards/arm/bt610/Kconfig.board deleted file mode 100644 index cee1953cf3162d..00000000000000 --- a/boards/arm/bt610/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BT610 board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BT610 - bool "BT610" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/bt610/Kconfig.defconfig b/boards/arm/bt610/Kconfig.defconfig deleted file mode 100644 index 34620afc27f6f2..00000000000000 --- a/boards/arm/bt610/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# BT6X0 Sensor configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_BT610 - -config BOARD - default "bt610" - -config BT_CTLR - default BT - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_TI_TCA9538),i2c) - -endif # BOARD_BT610 diff --git a/boards/arm/cc1352p1_launchxl/CMakeLists.txt b/boards/arm/cc1352p1_launchxl/CMakeLists.txt deleted file mode 100644 index 4c3dbf723e66cc..00000000000000 --- a/boards/arm/cc1352p1_launchxl/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources( - board_antenna.c - ) diff --git a/boards/arm/cc1352p1_launchxl/Kconfig.board b/boards/arm/cc1352p1_launchxl/Kconfig.board deleted file mode 100644 index d6a880aa47a593..00000000000000 --- a/boards/arm/cc1352p1_launchxl/Kconfig.board +++ /dev/null @@ -1,20 +0,0 @@ -# TI CC1352R LaunchXL board - -# Copyright (c) 2021 Florin Stancu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC1352P1_LAUNCHXL - bool "TI CC1352P1 LaunchXL" - depends on SOC_CC1352P - -if BOARD_CC1352P1_LAUNCHXL - -config BOARD_ANTENNA_INIT_PRIO - int "Board antenna switch initialization priority" - default 70 - help - Set the priority for board init, must be greater than - KERNEL_INIT_PRIORITY_DEVICE but smaller than - IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. - -endif # BOARD_CC1352P1_LAUNCHXL diff --git a/boards/arm/cc1352p1_launchxl/Kconfig.defconfig b/boards/arm/cc1352p1_launchxl/Kconfig.defconfig deleted file mode 100644 index 907daaf00103d7..00000000000000 --- a/boards/arm/cc1352p1_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC1352P1 LaunchXL board - -# Copyright (c) 2021 Florin Stancu -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC1352P1_LAUNCHXL - -config BOARD - default "cc1352p1_launchxl" - -endif # BOARD_CC1352P1_LAUNCHXL diff --git a/boards/arm/cc1352r1_launchxl/Kconfig.board b/boards/arm/cc1352r1_launchxl/Kconfig.board deleted file mode 100644 index 3c874a13962845..00000000000000 --- a/boards/arm/cc1352r1_launchxl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TI CC1352R LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC1352R1_LAUNCHXL - bool "TI CC1352R1 LaunchXL" - depends on SOC_CC1352R diff --git a/boards/arm/cc1352r1_launchxl/Kconfig.defconfig b/boards/arm/cc1352r1_launchxl/Kconfig.defconfig deleted file mode 100644 index 8bee2c9aed2e50..00000000000000 --- a/boards/arm/cc1352r1_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC1352R LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC1352R1_LAUNCHXL - -config BOARD - default "cc1352r1_launchxl" - -endif # BOARD_CC1352R1_LAUNCHXL diff --git a/boards/arm/cc1352r_sensortag/Kconfig.board b/boards/arm/cc1352r_sensortag/Kconfig.board deleted file mode 100644 index 6364142ac0b996..00000000000000 --- a/boards/arm/cc1352r_sensortag/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# TI CC1352R SensorTag board - -# Copyright (c) 2019 Brett Witherspoon -# Copyright (c) 2020 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC1352R_SENSORTAG - bool "TI CC1352R SensorTag" - depends on SOC_CC1352R diff --git a/boards/arm/cc1352r_sensortag/Kconfig.defconfig b/boards/arm/cc1352r_sensortag/Kconfig.defconfig deleted file mode 100644 index 41bf913bb990ee..00000000000000 --- a/boards/arm/cc1352r_sensortag/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# TI CC1352R SensorTag board - -# Copyright (c) 2019 Brett Witherspoon -# Copyright (c) 2020 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC1352R_SENSORTAG - -config BOARD - default "cc1352r_sensortag" - -config SPI - default SENSOR - -endif # BOARD_CC1352R_SENSORTAG diff --git a/boards/arm/cc26x2r1_launchxl/Kconfig.board b/boards/arm/cc26x2r1_launchxl/Kconfig.board deleted file mode 100644 index cfc9da276fb2c7..00000000000000 --- a/boards/arm/cc26x2r1_launchxl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TI CC26x2R1 LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC26X2R1_LAUNCHXL - bool "TI CC26x2R1 LaunchXL" - depends on SOC_CC2652R diff --git a/boards/arm/cc26x2r1_launchxl/Kconfig.defconfig b/boards/arm/cc26x2r1_launchxl/Kconfig.defconfig deleted file mode 100644 index 33d6541f47dd75..00000000000000 --- a/boards/arm/cc26x2r1_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC26x2R1 LaunchXL board - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC26X2R1_LAUNCHXL - -config BOARD - default "cc26x2r1_launchxl" - -endif # BOARD_CC26X2R1_LAUNCHXL diff --git a/boards/arm/cc3220sf_launchxl/Kconfig.board b/boards/arm/cc3220sf_launchxl/Kconfig.board deleted file mode 100644 index c03cae76d6800d..00000000000000 --- a/boards/arm/cc3220sf_launchxl/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# TI SimpleLink CC3220SF LaunchXL Board - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC3220SF_LAUNCHXL - bool "TI CC3220SF LAUNCHXL" - depends on SOC_CC3220SF diff --git a/boards/arm/cc3220sf_launchxl/Kconfig.defconfig b/boards/arm/cc3220sf_launchxl/Kconfig.defconfig deleted file mode 100644 index 2b2f801ed68787..00000000000000 --- a/boards/arm/cc3220sf_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# TI CC3220SF LaunchXL board configuration - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC3220SF_LAUNCHXL - -config BOARD - default "cc3220sf_launchxl" - -endif # BOARD_CC3220SF_LAUNCHXL diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig b/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig deleted file mode 100644 index ac49971fa1457e..00000000000000 --- a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_CC3220SF_LAUNCHXL=y -CONFIG_SOC_SERIES_CC32XX=y -CONFIG_SOC_CC3220SF=y -CONFIG_BUILD_OUTPUT_HEX=y - - -#enable GPIO driver -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3220sf_launchxl/doc/index.rst b/boards/arm/cc3220sf_launchxl/doc/index.rst deleted file mode 100644 index 4e941cef91ed1f..00000000000000 --- a/boards/arm/cc3220sf_launchxl/doc/index.rst +++ /dev/null @@ -1,325 +0,0 @@ -.. _cc3220sf_launchxl: - -CC3220SF LaunchXL -################# - -Overview -******** -The SimpleLink Wi-Fi CC3220SF LaunchPad development kit (CC3220SF-LAUNCHXL) -highlights CC3220SF, a single-chip wireless microcontroller (MCU) with -1MB internal flash, 4MB external serial flash, 256KB of RAM and enhanced -security features. - -See the `TI CC3220 Product Page`_ for details. - -Features: -========= - -* Two separate execution environments: a user application dedicated ARM - Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and - internet logical layers -* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem -* On-board accelerometer and temperature sensor -* Two buttons and three LEDs for user interaction -* UART through USB to PC -* BoosterPack plug-in module for adding graphical displays, audio - codecs, antenna selection, environmental sensing, and more -* Power from USB for the LaunchPad and optional external BoosterPack -* XDS110-based JTAG emulation with serial port for flash programming - -Details on the CC3220SF LaunchXL development board can be found in the -`CC3220SF LaunchPad Dev Kit Hardware User's Guide`_. - -Hardware -******** - -The CC3220SF SoC has two MCUs: - -#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, - and access to external serial 4MB flash with bootloader and peripheral - drivers in ROM. - -#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely - offloads Wi-Fi and internet protocols from the application MCU. - -Complete details of the CC3220SF SoC can be found in the `CC3220 TRM`_. - -Supported Features -================== - -Zephyr has been ported to the Applications MCU, with basic peripheral -driver support. - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| UART | on-chip | serial port-interrupt | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-----------------------+ -| SPI_0 | on-chip | Wi-Fi host driver | -+-----------+------------+-----------------------+ - -.. note:: - - For consistency with TI SimpleLink SDK and BoosterPack examples, - the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed - on bootup. - -The accelerometer, temperature sensors, or other peripherals -accessible through the BoosterPack, are not currently supported. - -Connections and IOs -==================== - -Peripherals on the CC3220SF LaunchXL are mapped to the following pins in -the file :zephyr_file:`boards/arm/cc3220sf_launchxl/pinmux.c`. - -+------------+-------+-------+ -| Function | PIN | GPIO | -+============+=======+=======+ -| UART0_TX | 55 | N/A | -+------------+-------+-------+ -| UART0_RX | 57 | N/A | -+------------+-------+-------+ -| LED D7 (R) | 64 | 9 | -+------------+-------+-------+ -| LED D6 (O) | 01 | 10 | -+------------+-------+-------+ -| LED D5 (G) | 02 | 11 | -+------------+-------+-------+ -| Switch SW2 | 15 | 22 | -+------------+-------+-------+ -| Switch SW3 | 04 | 13 | -+------------+-------+-------+ - -The default configuration can be found in the Kconfig file at -:zephyr_file:`boards/arm/cc3220sf_launchxl/cc3220sf_launchxl_defconfig`. - - -Programming and Debugging -************************* - -TI officially supports development on the CC3220SF using the TI -`CC3220 SDK`_ on Windows and Linux using TI tools: Code Composer -Studio for debugging and `UniFlash`_ for flashing. - -For Windows developers, see the `CC3220 Getting Started Guide`_ for -instructions on installation of tools, and how to flash the board using -UniFlash. - -Note that zephyr.bin produced by the Zephyr SDK may not load via -UniFlash tool. If encountering difficulties, use the zephyr.elf -file and openocd instead (see below). - -The following instructions are geared towards Linux developers who -prefer command line tools to an IDE. - -Before flashing and debugging the board, there are a few one-time board -setup steps to follow. - -Prerequisites: -============== - -#. Download and install the latest version of `UniFlash`_. -#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. - - This should result in a new device "Texas Instruments XDS110 Embed - with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. - -#. Update the service pack, and place the board in "Development Mode". - - Setting "Development Mode" enables the JTAG interface, necessary - for subsequent use of OpenOCD and updating XDS110 firmware. - - Follow the instructions in Section 2.4 "Download the Application", - in the `CC3220 Getting Started Guide`_, except for steps 5 and 6 in - Section 2.4.1 which select an MCU image. - -#. Ensure the XDS-110 emulation firmware is updated. - - Download and install the latest `XDS-110 emulation package`_. - - Follow these `xds110 firmware update directions - `_ - - Note that the emulation package install may place the xdsdfu utility - in ``/ccs_base/common/uscif/xds110/``. - -#. Switch Jumper SOP[2..0] (J15) back to [001]. - - Remove power from the board (disconnect USB cable) before switching jumpers. - -#. Install OpenOCD - - You can obtain OpenOCD by following these - :ref:`installing the latest Zephyr SDK instructions `. - - After the installation, add the directory containing the OpenOCD executable - to your environment's PATH variable. For example, use this command in Linux: - - .. code-block:: console - - export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH - - If you had previously installed TI OpenOCD, you can simply switch to use - the one in the Zephyr SDK. If for some reason you wish to continue to use - your TI OpenOCD installation, you can set the OPENOCD and - OPENOCD_DEFAULT_PATH variables in - :zephyr_file:`boards/arm/cc3220sf_launchxl/board.cmake` to point the build - to the paths of the OpenOCD binary and its scripts, before - including the common openocd.board.cmake file: - - .. code-block:: cmake - - set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - -#. Ensure CONFIG_XIP=y (default) is set. - - This locates the program into flash, and sets CONFIG_CC3220SF_DEBUG=y, - which prepends a debug header enabling the flash to persist over - subsequent reboots, bypassing the bootloader flash signature - verification. - - See Section 21.10 "Debugging Flash User Application Using JTAG" of the - `CC3220 TRM`_ for details on the secure flash boot process. - - -Once the above prerequisites are met, applications for the ``_cc3220sf_launchxl`` -board can be built, flashed, and debugged with openocd and gdb per the Zephyr -Application Development Primer (see :ref:`build_an_application` and -:ref:`application_run`). - -Flashing -======== - -To build and flash an application, execute the following commands for : - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3220sf_launchxl - :goals: flash - -This will load the image into flash. - -To see program output from UART0, connect a separate terminal window: - -.. code-block:: console - - % screen /dev/ttyACM0 115200 8N1 - -Then press the reset button (SW1) on the board to run the program. - -When using OpenOCD from Zephyr SDK to flash the device, you may notice -the program hangs when starting the network processor on the device, if the -program uses it. There is a known issue with how that version of OpenOCD -resets the network processor. You would need to manually hit the reset button -on the board to properly reset the device after flashing. - -Debugging -========= - -To debug a previously flashed image, after resetting the board, use the 'debug' -build target: - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3220sf_launchxl - :maybe-skip-config: - :goals: debug - - -Wi-Fi Support -************* - -The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported -to Zephyr, and communicates over a dedicated SPI to the network co-processor. -It is available as a Zephyr Wi-Fi device driver in -:zephyr_file:`drivers/wifi/simplelink`. - -Usage: -====== - -Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` -to enable Wi-Fi. -See :zephyr_file:`samples/net/wifi/boards/cc3220sf_launchxl.conf`. - -Provisioning: -============= - -SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. -To keep it simple for Zephyr development and demos, the SimpleLink -"Fast Connect" policy is enabled, with one-shot scanning. -This enables the cc3220sf_launchxl to automatically reconnect to the last -good known access point (AP), without having to restart a scan, and -re-specify the SSID and password. - -To connect to an AP, first run the Zephyr Wi-Fi shell sample application, -and connect to a known AP with SSID and password. - -See :zephyr:code-sample:`wifi-shell` - -Once the connection succeeds, the network co-processor keeps the AP identity in -its persistent memory. Newly loaded Wi-Fi applications then need not explicitly -execute any Wi-Fi scan or connect operations, until the need to change to a new AP. - -Secure Socket Offload -********************* - -The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket -offload point, enabling Zephyr BSD socket API calls to be directed to the -SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` -to ``y``. - -Secure socket (TLS) communication is handled as part of the socket APIs, -and enabled by: - -- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` - and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, -- using the TI Uniflash tool to program the required certificates and - keys to the secure flash filesystem, and enabling the TI Trusted - Root-Certificate Catalog. - -See :zephyr:code-sample:`sockets-http-get` and -:zephyr_file:`samples/net/sockets/http_get/boards/cc3220sf_launchxl.conf` for an -example. - -See the document `Simplelink Wi-Fi Certificates Handling`_ for details on -using the TI UniFlash tool for certificate programming. - -References -********** - -CC32xx Wiki: - http://processors.wiki.ti.com/index.php/CC31xx_%26_CC32xx - -.. _TI CC3220 Product Page: - http://www.ti.com/product/cc3220 - -.. _CC3220 TRM: - http://www.ti.com/lit/pdf/swru465 - -.. _CC3220 Programmer's Guide: - http://www.ti.com/lit/pdf/swru464 - -.. _CC3220 Getting Started Guide: - http://www.ti.com/lit/pdf/swru461 - -.. _UniFlash: - http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash - -.. _CC3220 SDK: - http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK - -.. _CC3220SF LaunchPad Dev Kit Hardware User's Guide: - http://www.ti.com/lit/pdf/swru463 - -.. _XDS-110 emulation package: - http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download - -.. _Simplelink Wi-Fi Certificates Handling: - http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/cc3235sf_launchxl/CMakeLists.txt b/boards/arm/cc3235sf_launchxl/CMakeLists.txt deleted file mode 100644 index 750f93d4af9873..00000000000000 --- a/boards/arm/cc3235sf_launchxl/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(dbghdr.c) diff --git a/boards/arm/cc3235sf_launchxl/Kconfig.board b/boards/arm/cc3235sf_launchxl/Kconfig.board deleted file mode 100644 index b119bc1745645d..00000000000000 --- a/boards/arm/cc3235sf_launchxl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TI SimpleLink CC3235SF LaunchXL Board - -# Copyright (c) 2019, Texas Instruments Incorporated -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CC3235SF_LAUNCHXL - bool "TI CC3235SF LAUNCHXL" - depends on SOC_CC3235SF diff --git a/boards/arm/cc3235sf_launchxl/Kconfig.defconfig b/boards/arm/cc3235sf_launchxl/Kconfig.defconfig deleted file mode 100644 index 3653791886537d..00000000000000 --- a/boards/arm/cc3235sf_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TI CC3235SF LaunchXL board configuration - -# Copyright (c) 2019, Texas Instruments Incorporated -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CC3235SF_LAUNCHXL - -config BOARD - default "cc3235sf_launchxl" - -endif # BOARD_CC3235SF_LAUNCHXL diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig b/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig deleted file mode 100644 index a233de474a73ea..00000000000000 --- a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_CC3235SF_LAUNCHXL=y -CONFIG_SOC_SERIES_CC32XX=y -CONFIG_SOC_CC3235SF=y -CONFIG_BUILD_OUTPUT_HEX=y - - -#enable GPIO driver -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3235sf_launchxl/doc/index.rst b/boards/arm/cc3235sf_launchxl/doc/index.rst deleted file mode 100644 index 80a4fb3c0e9fa8..00000000000000 --- a/boards/arm/cc3235sf_launchxl/doc/index.rst +++ /dev/null @@ -1,325 +0,0 @@ -.. _cc3235sf_launchxl: - -CC3235SF LaunchXL -################# - -Overview -******** -The SimpleLink Wi-Fi CC3235SF LaunchPad development kit (CC3235SF-LAUNCHXL) -highlights CC3235SF, a single-chip wireless microcontroller (MCU) with -1MB internal flash, 4MB external serial flash, 256KB of RAM, and enhanced -security features. It supports 802.11 a/b/g/n, both 2.4 GHz and 5 GHz. - -See the `TI CC3235 Product Page`_ for details. - -Features: -========= - -* Two separate execution environments: a user application dedicated ARM - Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and - internet logical layers -* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem -* On-board accelerometer and temperature sensor -* Two buttons and a RGB LED for user interaction -* UART through USB to PC -* BoosterPack plug-in module for adding graphical displays, audio - codecs, antenna selection, environmental sensing, and more -* Power from USB for the LaunchPad and optional external BoosterPack -* XDS110-based JTAG emulation with serial port for flash programming - -Details on the CC3235SF LaunchXL development board can be found in the -`CC3235SF LaunchPad Dev Kit Hardware User's Guide`_. - -Hardware -******** - -The CC3235SF SoC has two MCUs: - -#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, - and access to external serial 4MB flash with bootloader and peripheral - drivers in ROM. - -#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely - offloads Wi-Fi and internet protocols from the application MCU. - -Complete details of the CC3235SF SoC can be found in the `CC3235 TRM`_. - -Supported Features -================== - -Zephyr has been ported to the Applications MCU, with basic peripheral -driver support. - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| UART | on-chip | serial port-interrupt | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-----------------------+ -| SPI_0 | on-chip | Wi-Fi host driver | -+-----------+------------+-----------------------+ - -.. note:: - - For consistency with TI SimpleLink SDK and BoosterPack examples, - the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed - on bootup. - -The accelerometer, temperature sensors, or other peripherals -accessible through the BoosterPack, are not currently supported. - -Connections and IOs -==================== - -Peripherals on the CC3235SF LaunchXL are mapped to the following pins in -the file :zephyr_file:`boards/arm/cc3235sf_launchxl/pinmux.c`. - -+------------+-------+-------+ -| Function | PIN | GPIO | -+============+=======+=======+ -| UART0_TX | 55 | N/A | -+------------+-------+-------+ -| UART0_RX | 57 | N/A | -+------------+-------+-------+ -| LED D7 (R) | 64 | 9 | -+------------+-------+-------+ -| LED D6 (O) | 01 | 10 | -+------------+-------+-------+ -| LED D5 (G) | 02 | 11 | -+------------+-------+-------+ -| Switch SW2 | 15 | 22 | -+------------+-------+-------+ -| Switch SW3 | 04 | 13 | -+------------+-------+-------+ - -The default configuration can be found in the Kconfig file at -:zephyr_file:`boards/arm/cc3235sf_launchxl/cc3235sf_launchxl_defconfig`. - - -Programming and Debugging -************************* - -TI officially supports development on the CC3235SF using the TI -`CC32xx SDK`_ on Windows and Linux using TI tools: Code Composer -Studio for debugging and `UniFlash`_ for flashing. - -For Windows developers, see the `CC32xx Quick Start Guide`_ for -instructions on installation of tools, and how to flash the board using -UniFlash. - -Note that ``zephyr.bin`` produced by the Zephyr SDK may not load via -UniFlash tool. If encountering difficulties, use the ``zephyr.elf`` -file and openocd instead (see below). - -The following instructions are geared towards Linux developers who -prefer command line tools to an IDE. - -Before flashing and debugging the board, there are a few one-time board -setup steps to follow. - -Prerequisites: -============== - -#. Download and install the latest version of `UniFlash`_. -#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. - - This should result in a new device "Texas Instruments XDS110 Embed - with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. - -#. Update the service pack, and place the board in "Development Mode". - - Setting "Development Mode" enables the JTAG interface, necessary - for subsequent use of OpenOCD and updating XDS110 firmware. - - Follow the instructions in Section 2.4 "Download the Application", - in the `CC32xx Quick Start Guide`_, except for steps 5 and 6 in - Section 2.4.1 which select an MCU image. - -#. Ensure the XDS-110 emulation firmware is updated. - - Download and install the latest `XDS-110 emulation package`_. - - Follow these `xds110 firmware update directions - `_ - - Note that the emulation package install may place the xdsdfu utility - in ``/ccs_base/common/uscif/xds110/``. - -#. Switch Jumper SOP[2..0] (J15) back to [001]. - - Remove power from the board (disconnect USB cable) before switching jumpers. - -#. Install OpenOCD - - You can obtain OpenOCD by following these - :ref:`installing the latest Zephyr SDK instructions `. - - After the installation, add the directory containing the OpenOCD executable - to your environment's PATH variable. For example, use this command in Linux: - - .. code-block:: console - - export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH - - If you had previously installed TI OpenOCD, you can simply switch to use - the one in the Zephyr SDK. If for some reason you wish to continue to use - your TI OpenOCD installation, you can set the OPENOCD and - OPENOCD_DEFAULT_PATH variables in - :zephyr_file:`boards/arm/cc3220sf_launchxl/board.cmake` to point the build - to the paths of the OpenOCD binary and its scripts, before - including the common openocd.board.cmake file: - - .. code-block:: cmake - - set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - -#. Ensure CONFIG_XIP=y (default) is set. - - This locates the program into flash, and sets CONFIG_CC3235SF_DEBUG=y, - which prepends a debug header enabling the flash to persist over - subsequent reboots, bypassing the bootloader flash signature - verification. - - See Section 21.10 "Debugging Flash User Application Using JTAG" of the - `CC3235 TRM`_ for details on the secure flash boot process. - - -Once the above prerequisites are met, applications for the ``_cc3235sf_launchxl`` -board can be built, flashed, and debugged with openocd and gdb per the Zephyr -Application Development Primer (see :ref:`build_an_application` and -:ref:`application_run`). - -Flashing -======== - -To build and flash an application, execute the following commands for : - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3235sf_launchxl - :goals: flash - -This will load the image into flash. - -To see program output from UART0, connect a separate terminal window: - -.. code-block:: console - - % screen /dev/ttyACM0 115200 8N1 - -Then press the reset button (SW1) on the board to run the program. - -When using OpenOCD from Zephyr SDK to flash the device, you may notice -the program hangs when starting the network processor on the device, if the -program uses it. There is a known issue with how that version of OpenOCD -resets the network processor. You would need to manually hit the reset button -on the board to properly reset the device after flashing. - -Debugging -========= - -To debug a previously flashed image, after resetting the board, use the 'debug' -build target: - -.. zephyr-app-commands:: - :zephyr-app: - :board: cc3235sf_launchxl - :maybe-skip-config: - :goals: debug - - -Wi-Fi Support -************* - -The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported -to Zephyr, and communicates over a dedicated SPI to the network co-processor. -It is available as a Zephyr Wi-Fi device driver in -:zephyr_file:`drivers/wifi/simplelink`. - -Usage: -====== - -Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` -to enable Wi-Fi. -See :zephyr_file:`samples/net/wifi/boards/cc3235sf_launchxl.conf`. - -Provisioning: -============= - -SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. -To keep it simple for Zephyr development and demos, the SimpleLink -"Fast Connect" policy is enabled, with one-shot scanning. -This enables the cc3235sf_launchxl to automatically reconnect to the last -good known access point (AP), without having to restart a scan, and -re-specify the SSID and password. - -To connect to an AP, first run the Zephyr Wi-Fi shell sample application, -and connect to a known AP with SSID and password. - -See :zephyr:code-sample:`wifi-shell` - -Once the connection succeeds, the network co-processor keeps the AP identity in -its persistent memory. Newly loaded Wi-Fi applications then need not explicitly -execute any Wi-Fi scan or connect operations, until the need to change to a new AP. - -Secure Socket Offload -********************* - -The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket -offload point, enabling Zephyr BSD socket API calls to be directed to the -SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` -to ``y``. - -Secure socket (TLS) communication is handled as part of the socket APIs, -and enabled by: - -- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` - and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, -- using the TI Uniflash tool to program the required certificates and - keys to the secure flash filesystem, and enabling the TI Trusted - Root-Certificate Catalog. - -See :zephyr:code-sample:`sockets-http-get` and -:zephyr_file:`samples/net/sockets/http_get/boards/cc3235sf_launchxl.conf` for an -example. - -See the document `Simplelink Wi-Fi Certificates Handling`_ for details on -using the TI UniFlash tool for certificate programming. - -References -********** - -TI SimpleLink MCUs: - http://www.ti.com/microcontrollers/simplelink-mcus/overview.html - -.. _TI CC3235 Product Page: - http://www.ti.com/product/cc3235SF - -.. _CC3235 TRM: - http://www.ti.com/lit/pdf/swru543 - -.. _CC3x20/CC3x35 SimpleLink Wi-Fi and IoT Network Processor Programmer's Guide: - http://www.ti.com/lit/pdf/swru455 - -.. _CC32xx Quick Start Guide: - http://dev.ti.com/tirex/content/simplelink_cc32xx_sdk_2_40_01_01/docs/simplelink_mcu_sdk/Quick_Start_Guide.html - -.. _UniFlash: - http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash - -.. _CC32xx SDK: - http://www.ti.com/tool/download/SIMPLELINK-CC32xx-SDK/2.40.01.01 - -.. _CC3235SF LaunchPad Dev Kit Hardware User's Guide: - http://www.ti.com/lit/pdf/swru539 - -.. _XDS-110 emulation package: - http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download - -.. _Simplelink Wi-Fi Certificates Handling: - http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/circuitdojo_feather_nrf9160/Kconfig b/boards/arm/circuitdojo_feather_nrf9160/Kconfig deleted file mode 100644 index 78e7bbd4530c07..00000000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.board b/boards/arm/circuitdojo_feather_nrf9160/Kconfig.board deleted file mode 100644 index d69bc53f55784c..00000000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_CIRCUITDOJO_FEATHER_NRF9160 - bool "Circuit Dojo nRF9160 Feather" - -config BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - bool "Circuit Dojo nRF9160 Feather non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.defconfig b/boards/arm/circuitdojo_feather_nrf9160/Kconfig.defconfig deleted file mode 100644 index 73648be3ef173a..00000000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CIRCUITDOJO_FEATHER_NRF9160 || BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - -config BOARD - default "circuitdojo_feather_nrf9160" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_CIRCUITDOJO_FEATHER_NRF9160 && TRUSTED_EXECUTION_SECURE - -if BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS - -endif # BOARD_CIRCUITDOJO_FEATHER_NRF9160 || BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_defconfig b/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_defconfig deleted file mode 100644 index f3dc6d6155ca7c..00000000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_CIRCUITDOJO_FEATHER_NRF9160=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# required to enable 3V3 power rail -CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns_defconfig b/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns_defconfig deleted file mode 100644 index 9f25a5dda67670..00000000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# required to enable 3V3 power rail -CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/doc/index.rst b/boards/arm/circuitdojo_feather_nrf9160/doc/index.rst deleted file mode 100644 index f089c468e0df8f..00000000000000 --- a/boards/arm/circuitdojo_feather_nrf9160/doc/index.rst +++ /dev/null @@ -1,161 +0,0 @@ -.. _circuitdojo_feather_nrf9160: - -nRF9160 Feather -############### - -.. figure:: img/circuitdojo_feather_nrf9160.jpg - :align: center - :alt: Circuit Dojo nRF9160 Feather - - nRF9160 Feather (Credit: Circuit Dojo) - -Overview -******** - -The nRF9160 Feather by Circuit Dojo is a single-board development -for bringing your LTE-M and NB-IoT applications to life. The circuitdojo_feather_nrf9160 -board configuration leverages the pre-existing support for the Nordic Semiconductor -nRF9160. Supported nRF9160 peripherals include: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9160 Feather Documentation`_. - - -Hardware -******** - -.. figure:: img/nrf9160-feather-v31-features.jpg - :align: center - :alt: nRF9160 Feather Features - -Connections and IOs -=================== - -The nRF9160 Feather has everything you know and love about -the Feather platform. Here are some of the highlights: - -LED ---- - -* D7 (blue) = P0.03 - -Push buttons and Switches -------------------------- - -* MODE = P0.12 -* RESET - -USB ---- - -Contains a USB/UART connection for both debugging and loading new -code using a UART Enabled MCUBoot. - -Standard Battery Connection ----------------------------- - -The nRF9160 Feather has a 2 pin battery connector on board. Lithium Polymer batteries > -300mA required. - -Nano SIM Holder ---------------- - -The nRF9160 Feather has a built-in nano SIM (4FF) holder located -on the bottom side. - - -Programming and Debugging -************************* - -circuitdojo_feather_nrf9160 has a Tag Connect TC2030-CTX-NL. It can be used -by most programmers like: - -* J-Link (the nRF53-DK is recommended) -* CMSIS-DAP based programmers - -Check out `Getting Started`_ for more info. - -Building an application -======================= - -In most cases you'll want to use the ``ns`` target with any of the Zephyr -or Nordic based examples. - -.. note:: - Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board. - -Some of the examples do not use secure mode, so they do not require the -``ns`` suffix. A great example of this is the `hello_world` below. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ screen /dev/ 115200 - -Replace :code:`` with the port where the nRF9160 Feather -can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: circuitdojo_feather_nrf9160 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons on the nRF9160 Feather -*************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dtsi`. - -References -********** - -.. target-notes:: - -**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for -developing a great platform! - -.. _nRF9160 Feather Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html -.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/colibri_imx7d_m4/Kconfig.board b/boards/arm/colibri_imx7d_m4/Kconfig.board deleted file mode 100644 index 016ebca5eff6ea..00000000000000 --- a/boards/arm/colibri_imx7d_m4/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Colibri iMX7D M4 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_COLIBRI_IMX7D_M4 - bool "Toradex Colibri iMX7 Dual" - depends on SOC_SERIES_IMX7_M4 - select SOC_PART_NUMBER_MCIMX7D5EVM10SC diff --git a/boards/arm/colibri_imx7d_m4/Kconfig.defconfig b/boards/arm/colibri_imx7d_m4/Kconfig.defconfig deleted file mode 100644 index 59253032e0a665..00000000000000 --- a/boards/arm/colibri_imx7d_m4/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Colibri iMX7D M4 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_COLIBRI_IMX7D_M4 - -config BOARD - default "colibri_imx7d_m4" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - - -endif # BOARD_COLIBRI_IMX7D_M4 diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts deleted file mode 100644 index fc78324c803de2..00000000000000 --- a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2017,2019 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "colibri_imx7d_m4-pinctrl.dtsi" -#include - -/ { - model = "TORADEX Colibri IMX7D board"; - compatible = "nxp,mcimx7d_m4"; - - aliases { - led0 = &green_led; - sw0 = &user_switch_1; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - }; - - leds { - compatible = "gpio-leds"; - green_led: led_0 { - gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; - label = "User LED1"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_switch_1: user_sw_1 { - gpios = <&gpio2 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; - label = "User SW1"; - zephyr,code = ; - }; - }; -}; - -&uart2 { - status = "okay"; - current-speed = <115200>; - modem-mode = <64>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm1 { - pinctrl-0 = <&pwm1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm2 { - pinctrl-0 = <&pwm2_default>; - pinctrl-names = "default"; -}; - -&pwm3 { - pinctrl-0 = <&pwm3_default>; - pinctrl-names = "default"; -}; - -&pwm4 { - pinctrl-0 = <&pwm4_default>; - pinctrl-names = "default"; -}; - -&mub { - status = "okay"; -}; diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.yaml b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.yaml deleted file mode 100644 index ce87d91e4cd9c8..00000000000000 --- a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: colibri_imx7d_m4 -name: TORADEX Colibri IMX7D -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - pwm -vendor: nxp diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig b/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig deleted file mode 100644 index 7ffa3899880891..00000000000000 --- a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_COLIBRI_IMX7D_M4=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/colibri_imx7d_m4/doc/index.rst b/boards/arm/colibri_imx7d_m4/doc/index.rst deleted file mode 100644 index f8de598f7947fb..00000000000000 --- a/boards/arm/colibri_imx7d_m4/doc/index.rst +++ /dev/null @@ -1,324 +0,0 @@ -.. _colibri_imx7d_m4: - -NXP i.MX 7 Computer on Module - Colibri iMX7 -############################################ - -Overview -******** - -The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 -core and Single Cortex M4 core. -Zephyr was ported to run on the M4 core. In a later release, it will also -communicate with the A7 core (running Linux) via RPmsg. - - -.. image:: colibri_imx7d_m4.jpg - :align: center - :alt: Colibri-iMX7 - -Hardware -******** - -- i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core - -- Memory - - - RAM -> A7: 256MB, 512MB and 1GB - - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A7: 4Gb eMMC and 512Mb NAND - -- Display - - - RGB 1920x1080x24bpp - - 4-wire Resistive touch - -- Multimedia - - - 1x Camera Parallel Interface - - 1x Analog Audio Line in (Stereo) - - 1x Analog Audio Mic in (Mono) - - 1x Analog Audio Headphone out (Stereo) - -- Connectivity - - - USB 2.0 OTG (High Speed) - - USB 2.0 host (High Speed) - - 10/100 Mbit/s Ethernet PHY - - 4x I2C - - 4x SPI - - 7x UART - - 1x IrDA - - 20x PWM - - Up to 125 GPIO - - 4x Analog Input (12 Bit) - - 2x SDIO/SD/MMC (8 Bit) - - 2x CAN - -For more information about the i.MX 7 SoC, Colibri iMX7 Computer on Module -and Colibri Evaluation Board, see these references: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Dual Datasheet`_ -- `i.MX 7 Dual Reference Manual`_ -- `Colibri iMX7 Website`_ -- `Colibri iMX7 User Guide`_ -- `Colibri iMX7 Datasheet`_ -- `Colibri Evaluation Board Website`_ -- `Colibri Evaluation Board Datasheet`_ - -Supported Features -================== - -The Colibri iMX7D Computer on Module with Colibri Evaluation Board configuration -supports the following hardware features on the Cortex M4 Core: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/colibri_imx7d_m4/colibri_imx7d_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The Colibri iMX7D Computer on Module with Colibri Evaluation Board -was tested with the following pinmux controller configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART_B RXD | UART2_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART_B TXD | UART2_RXD | UART Console | -+---------------+-----------------+---------------------------+ -| SODIMM_135 | GPIO1_IO02 | LED0 | -+---------------+-----------------+---------------------------+ -| SODIMM_133 | GPIO2_IO26 | SW0 | -+---------------+-----------------+---------------------------+ -| SODIMM_194 | I2C4_SDA | I2C_SDA | -+---------------+-----------------+---------------------------+ -| SODIMM_196 | I2C4_SCL | I2C_SCL | -+---------------+-----------------+---------------------------+ -| SODIMM_59 | PWM1/GPIO1_IO08 | PWM | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7D SoC has seven UARTs. The number 2 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The Colibri iMX7D doesn't have QSPI flash for the M4 and it needs to be started by -the A7 core. The A7 core is responsible to load the M4 binary application into the -RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get -the M4 out of reset. -The A7 can perform these steps at bootloader level or after the Linux system has -booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - - -References -========== - -- `i.MX 7 Dual Reference Manual`_ from page 190 (section 2.1.2 and 2.1.3) -- `Toradex Wiki`_ - - -At compilation time you have to choose which RAM will be used. This configuration is -done in the file ``boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts`` with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" -properties. The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from A7 using u-boot. - -Copy the compiled zephyr.bin to the first EXT partition of the SD card and plug into the -board. Power it up and stop the u-boot execution. -Set the u-boot environment variables and run the zephyr.bin from the appropriated memory -configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'ext4load mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - - -Debugging -========= - -Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. - -To run Zephyr Binary using J-Link create the following script in order to -get the Program Counter and Stack Pointer from zephyr.bin. - -get-pc-sp.sh: - -.. code-block:: console - - #!/bin/sh - - firmware=$1 - - pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') - sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') - - echo pc=$pc - echo sp=$sp - - -Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` - -.. code-block:: console - - pc=00900f01 - sp=00905020 - -Plug in the J-Link into the board and PC and run the J-Link command line tool: - -.. code-block:: console - - /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript - -The following steps are necessary to run the zephyr.bin: -1. Put the M4 core in reset -2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) -3. Set PC (Program Counter) -4. Set SP (Stack Pointer) -5. Get the M4 core out of reset - -Issue the following commands inside J-Link commander: - -.. code-block:: console - - w4 0x3039000C 0xAC - loadfile zephyr.bin,0x00900000 - w4 0x00180000 00900f01 - w4 0x00180004 00905020 - w4 0x3039000C 0xAA - -With these mechanisms, applications for the ``colibri_imx7d_m4`` board -configuration can be built and debugged in the usual way (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _Colibri Evaluation Board Website: - https://www.toradex.com/products/carrier-board/colibri-evaluation-carrier-board - -.. _Colibri Evaluation Board Datasheet: - https://docs.toradex.com/102284-colibri-evaluation-board-datasheet.pdf - -.. _Colibri iMX7 Website: - https://www.toradex.com/computer-on-modules/colibri-arm-family/nxp-freescale-imx7 - -.. _Colibri iMX7 User Guide: - https://developer.toradex.com/products/colibri-imx7 - -.. _Colibri iMX7 Datasheet: - https://docs.toradex.com/103125-colibri-arm-som-imx7-datasheet.pdf - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Dual Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf - -.. _i.MX 7 Dual Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7DRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/contextualelectronics_abc/Kconfig b/boards/arm/contextualelectronics_abc/Kconfig deleted file mode 100644 index 26558cc557c68c..00000000000000 --- a/boards/arm/contextualelectronics_abc/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# ABC board configuration - -# Copyright (c) 2020 Analog Life LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_CONTEXTELEC_ABC diff --git a/boards/arm/contextualelectronics_abc/Kconfig.board b/boards/arm/contextualelectronics_abc/Kconfig.board deleted file mode 100644 index f1dc7ce2fec7b6..00000000000000 --- a/boards/arm/contextualelectronics_abc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# ABC board configuration - -# Copyright (c) 2020 Analog Life LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CONTEXTELEC_ABC - bool "nRF52840 based Advanced BLE Cell" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/contextualelectronics_abc/Kconfig.defconfig b/boards/arm/contextualelectronics_abc/Kconfig.defconfig deleted file mode 100644 index da35c9e482abcf..00000000000000 --- a/boards/arm/contextualelectronics_abc/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840 BLE Cell board configuration - -# Copyright (c) 2020 Bilal Wasim -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CONTEXTELEC_ABC - -config BOARD - default "nrf52840_ble_cell" - -config BT_CTLR - default BT - -endif # BOARD_CONTEXTELEC_ABC diff --git a/boards/arm/contextualelectronics_abc/board.cmake b/boards/arm/contextualelectronics_abc/board.cmake deleted file mode 100644 index 720d557c48d663..00000000000000 --- a/boards/arm/contextualelectronics_abc/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set (OPENOCD_NRF5_SUBFAMILY "nrf52") -board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") -board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/cy8ckit_062_ble/Kconfig.board b/boards/arm/cy8ckit_062_ble/Kconfig.board deleted file mode 100644 index 6b7dd89566f6e0..00000000000000 --- a/boards/arm/cy8ckit_062_ble/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# PSoC6 BLE Pioneer Kit configuration - -# Copyright (c) 2018 Cypress -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CKIT_062_BLE_M0 - bool "PSoC6 BLE Pioneer Kit [M0 CPU0]" - depends on SOC_PART_NUMBER_CY8C6347BZI_BLD53 - -config BOARD_CY8CKIT_062_BLE_M4 - bool "PSoC6 BLE Pioneer Kit [M4 CPU1]" - depends on SOC_PART_NUMBER_CY8C6347BZI_BLD53 diff --git a/boards/arm/cy8ckit_062_ble/Kconfig.defconfig b/boards/arm/cy8ckit_062_ble/Kconfig.defconfig deleted file mode 100644 index 52da0daab3b532..00000000000000 --- a/boards/arm/cy8ckit_062_ble/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# PSoC6 BLE Pioneer Kit configuration - -# Copyright (c) 2018 Cypress -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CKIT_062_BLE_M0 || \ - BOARD_CY8CKIT_062_BLE_M4 - -config BOARD - default "cy8ckit_062_ble_m0" if BOARD_CY8CKIT_062_BLE_M0 - default "cy8ckit_062_ble_m4" if BOARD_CY8CKIT_062_BLE_M4 - -endif # BOARD_CY8CKIT_062_BLE_M0 || \ - # BOARD_CY8CKIT_062_BLE_M4 diff --git a/boards/arm/cy8ckit_062_ble/board.cmake b/boards/arm/cy8ckit_062_ble/board.cmake deleted file mode 100644 index f04a18a669790d..00000000000000 --- a/boards/arm/cy8ckit_062_ble/board.cmake +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_BOARD_CY8CKIT_062_BLE_M0) -board_runner_args(jlink "--device=CY8C6xx7_CM0p" "--speed=2000") -endif() -if(CONFIG_BOARD_CY8CKIT_062_BLE_M4) -board_runner_args(jlink "--device=CY8C6xx7_CM4" "--speed=2000") -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.yaml b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.yaml deleted file mode 100644 index ee63e4356a5b70..00000000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020-2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_ble_m0 -name: Cypress PSoC6 BLE Pioneer Kit (M0) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - arduino_gpio - - arduino_spi - - gpio - - spi -vendor: cypress diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.conf b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.conf deleted file mode 100644 index 4b132fd55094e7..00000000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.conf +++ /dev/null @@ -1,5 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.conf b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.conf deleted file mode 100644 index 4b132fd55094e7..00000000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.conf +++ /dev/null @@ -1,5 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig deleted file mode 100644 index c01d1a64400ecd..00000000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC63=y -CONFIG_SOC_PSOC6_M0=y -CONFIG_SOC_PART_NUMBER_CY8C6347BZI_BLD53=y -CONFIG_BOARD_CY8CKIT_062_BLE_M0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.yaml b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.yaml deleted file mode 100644 index b490c8f3fbe8bc..00000000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020-2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_ble_m4 -name: Cypress PSoC6 BLE Pioneer Kit (M4) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - arduino_gpio - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.conf b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.conf deleted file mode 100644 index 4b132fd55094e7..00000000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.conf +++ /dev/null @@ -1,5 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig b/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig deleted file mode 100644 index 34478a7c55359c..00000000000000 --- a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC63=y -CONFIG_SOC_PSOC6_M4=y -CONFIG_SOC_PART_NUMBER_CY8C6347BZI_BLD53=y -CONFIG_BOARD_CY8CKIT_062_BLE_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/doc/index.rst b/boards/arm/cy8ckit_062_ble/doc/index.rst deleted file mode 100644 index 7bf45437ca73e9..00000000000000 --- a/boards/arm/cy8ckit_062_ble/doc/index.rst +++ /dev/null @@ -1,305 +0,0 @@ -.. _cy8ckit_062_ble: - -INFINEON PSoC63 BLE Pioneer Kit -############################### - -Overview -******** - -The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that -enables design and debug of the Cypress PSoC 63 BLE MCU. - -The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a -150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm -Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM, -an integrated BLE 4.2 radio, 78 GPIO, 7 programmable analog blocks, 12 -programmable digital blocks, and capacitive-sensing with CapSense. - -The PSoC 6 BLE Pioneer board offers compatibility with Arduino shields, a -512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power -delivery system (EZ-PD™ CCG3), 5-segment CapSense slider, two CapSense -buttons, one CapSense proximity sensing header, an RGB LED, two user LEDs, -and one push button. - -The CY8CKIT-062-BLE package includes a CY8CKIT-028-EPD E-INK Display Shield -that contains a 2.7-inch E-INK display, a motion sensor, a thermistor, and a -PDM microphone. The kit package also contains a CY5677 CySmart BLE 4.2 USB -Dongle that is factory-programmed to emulate a BLE GAP Central device, -enabling you to emulate a BLE host on your computer. - -The Cortex-M0+ is a primary core on the board's SoC. It starts first and -enables the CM4 core. - -.. image:: img/cy8ckit-062-ble.jpg - :align: center - :alt: CY8CKIT_062_BLE - -1. Battery charging indicator (LED6) -2. USB PD output voltage availability indicator (LED7) -3. KitProg2 USB Type-C connector (J10) -4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) -5. KitProg2 programming mode selection button (SW3) -6. KitProg2 I/O header (J6)1 -7. KitProg2 programming/custom application header (J7)1 -8. External power supply connector (J9) -9. PSoC 6 BLE user button (SW2) -10. KitProg2 application selection button (SW4) -11. Digilent® Pmod™ compatible I/O header (J14)1 -12. Power LED (LED4) -13. KitProg2 status LEDs (LED1, LED2, and LED3) -14. PSoC 6 reset button (SW1) -15. PSoC 6 I/O header (J18, J19 and J20) -16. Arduino™ Uno R3 compatible power header (J1) -17. PSoC 6 debug and trace header (J12) -18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) -19. PSoC 6 program and debug header (J11) -20. KitProg2 programming target selection switch (SW6) -21. CapSense slider and buttons -22. CapSense proximity header (J13) -23. PSoC 6 BLE VDD selection switch (SW5) -24. PSoC 6 BLE power monitoring jumper (J8)2 -25. Arduino Uno R3 compatible ICSP header (J5)1 -26. PSoC 6 user LEDs (LED8 and LED9) -27. RGB LED (LED5) -28. Cypress 512-Mbit serial NOR Flash memory (S25FL512S, U4) -29. Cypress serial Ferroelectric RAM (U5)1 -30. VBACKUP and PMIC control selection switch (SW7)2 -31. Cypress PSoC 6 BLE (CY8C6347BZI-BLD53, U1) -32. BLE Antenna -33. U.FL connector for external antenna (J17)1 -34. Cypress main voltage regulator (MB39C022G, U6) -35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) -36. Battery connector (J15)1,2 -37. USB PD output voltage (9V/12V) connector (J16) - -Hardware -******** - -For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board: - -- `PSoC 63 BLE MCU SoC Website`_ -- `PSoC 63 BLE MCU Datasheet`_ -- `PSoC 63 BLE MCU Architecture Reference Manual`_ -- `PSoC 63 BLE MCU Register Reference Manual`_ -- `CY8CKIT-062-BLE Website`_ -- `CY8CKIT-062-BLE User Guide`_ -- `CY8CKIT-062-BLE Schematics`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| SPI | on-chip | spi | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configurations can be found in the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_defconfig` for -Cortex-M0+ and on the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_defconfig` for -Cortex-M4 - -System Clock -============ - -The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - -Serial Port -=========== - -The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as -UART/SPI/I2C interfaces for serial communication. At the moment UART5 on SCB5 -and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's -USB-UART Bridge working as a serial console interface. SCB6 to P13_0, P13_1 -pins on the J3 of the Arduino Uno R3 compatible PSoC6 I/O header for general -purposes. - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - -Programming and Debugging -************************* - -The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. There are also PSoC 6 program and debug headers J11 -and J12 that can be used with Segger J-Link [default]. -A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and -Cy_WDT_Disable(). - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0 - :goals: build - :compact: - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0 - :goals: flash - :compact: - - You should see "Hello World! cy8ckit_062_ble_m0" in your terminal. - -Running on Dual Core -******************** - -#. Build the Zephyr kernel and the :zephyr:code-sample:`button` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: cy8ckit_062_ble_m4 - :goals: build - :compact: - -#. If you have a USB-Serial adapter, you can connect SBC[UART]-6 on Arduino - header. Schematic should be checked for connections. Run your favorite - terminal program again now listen for another output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. To flash an image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: cy8ckit_062_ble_m4 - :goals: flash - :compact: - -#. Configure Cortex-M0+ to enable Cortex-M4: - - The last step flash the M4 image on the flash. However, Cortex-M0 by default - doesn't start the M4 and nothing will happen. To enable Cortex-M4 CPU, - repeat the steps on programming and debug and add the following parameter - when performing the build process. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0 - :goals: build flash - :gen-args: -DCONFIG_SOC_PSOC6_M0_ENABLES_M4=y - :compact: - - Now you can press button SW-2 and see LED-9 blink at same time you have the - "Hello World! cy8ckit_062_ble_m0" in the your terminal. - -Board Revision -************** - -The CY8CKIT-062-BLE KitProg2 shares connections with Arduino-R3 header. This -connections may not allow the correct use of shields. The default board -revision (0.0.0) allows use of default connections. The use of Arduino headers -are only possible after rework the board and using the revision 1.0.0. - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application for - board revision 1.0.0: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cy8ckit_062_ble_m0@1.0.0 - :goals: build - :compact: - -#. The differences from version 0.0.0 to 1.0.0: - -+-------------+------------+------------+ -| Connection | 0.0.0 | 1.0.0 | -+=============+============+============+ -| CDC-COM RX | P5_0 | P9_0 | -+-------------+------------+------------+ -| CDC-COM TX | P5_1 | P9_1 | -+-------------+------------+------------+ -| R77 | X | | -+-------------+------------+------------+ -| R78 | | X | -+-------------+------------+------------+ - - -The P9 pins are available at J2. Those signals should be routed to J6. - -J2-2 to J6-14 -J2-4 to J6-13 - -The most complex part is short circuit pins 14 and 15 from U13. That connect -UART_RTS with UART_CTS from KitProg2. - -References -********** - -.. _PSoC 63 BLE MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-cortex-m0-psoc-63-connectivity-line - -.. _PSoC 63 BLE MCU Datasheet: - https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-63-ble-datasheet-programmable-system-chip-psoc - -.. _PSoC 63 BLE MCU Architecture Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference - -.. _PSoC 63 BLE MCU Register Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c63x6-cy8c63x7-cy8c63x6-cy8c63x7-registers - -.. _CY8CKIT-062-BLE Website: - https://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit-cy8ckit-062-ble - -.. _CY8CKIT-062-BLE User Guide: - https://www.cypress.com/file/390496/download - -.. _CY8CKIT-062-BLE Schematics: - https://www.cypress.com/file/417021/download diff --git a/boards/arm/cy8ckit_062_ble/revision.cmake b/boards/arm/cy8ckit_062_ble/revision.cmake deleted file mode 100644 index c9c8841d61ed36..00000000000000 --- a/boards/arm/cy8ckit_062_ble/revision.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_check_revision(FORMAT MAJOR.MINOR.PATCH DEFAULT_REVISION 0.0.0) diff --git a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.board b/boards/arm/cy8ckit_062_wifi_bt/Kconfig.board deleted file mode 100644 index 62f30b443d2171..00000000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# PSoC6 WiFi-BT Pioneer Kit configuration - -# Copyright (c) 2018 Cypress -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CKIT_062_WIFI_BT_M0 - bool "PSoC6 WiFi-BT Pioneer Kit M0" - depends on SOC_PART_NUMBER_CY8C6247BZI_D54 - -config BOARD_CY8CKIT_062_WIFI_BT_M4 - bool "PSoC6 WiFi-BT Pioneer Kit M4" - depends on SOC_PART_NUMBER_CY8C6247BZI_D54 diff --git a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.defconfig b/boards/arm/cy8ckit_062_wifi_bt/Kconfig.defconfig deleted file mode 100644 index d30250160d6559..00000000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PSoC6 WiFi-BT Pioneer Kit configuration - -# Copyright (c) 2020 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CKIT_062_WIFI_BT_M0 || \ - BOARD_CY8CKIT_062_WIFI_BT_M4 - -config BOARD - default "cy8ckit_062_wifi_bt_m0" if BOARD_CY8CKIT_062_WIFI_BT_M0 - default "cy8ckit_062_wifi_bt_m4" if BOARD_CY8CKIT_062_WIFI_BT_M4 - -endif # BOARD_CY8CKIT_062_WIFI_BT_M0 || \ - # BOARD_CY8CKIT_062_WIFI_BT_M4 diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.yaml b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.yaml deleted file mode 100644 index a639fc9b7004e3..00000000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_wifi_bt_m0 -name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig deleted file mode 100644 index 0518f65026b646..00000000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC62=y -CONFIG_SOC_PSOC6_M0=y -CONFIG_SOC_PART_NUMBER_CY8C6247BZI_D54=y -CONFIG_BOARD_CY8CKIT_062_WIFI_BT_M0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.yaml b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.yaml deleted file mode 100644 index 70c6db9674007f..00000000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: cy8ckit_062_wifi_bt_m4 -name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4) -type: mcu -arch: arm -ram: 288 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4_defconfig b/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4_defconfig deleted file mode 100644 index 37cf0025685f16..00000000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_PSOC62=y -CONFIG_SOC_PSOC6_M4=y -CONFIG_SOC_PART_NUMBER_CY8C6247BZI_D54=y -CONFIG_BOARD_CY8CKIT_062_WIFI_BT_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_HEX=y - -# UART driver -CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/doc/index.rst b/boards/arm/cy8ckit_062_wifi_bt/doc/index.rst deleted file mode 100644 index e1d6d16ef0a7a6..00000000000000 --- a/boards/arm/cy8ckit_062_wifi_bt/doc/index.rst +++ /dev/null @@ -1,208 +0,0 @@ -.. _cy8ckit_062_wifi_bt: - -INFINEON PSoC6 WiFi-BT Pioneer Kit -################################## - -Overview -******** - -The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware -platform that enables design and debug of the PSoC 62 MCU and the Murata -LBEE5KL1DX Module (CYW4343W WiFi + Bluetooth Combo Chip). - -The PSoC 6 WiFi-BT Pioneer Kit features the PSoC 62 MCU: a -dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application -processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations, -1MB of Flash, 288KB of SRAM, 104 GPIO, 7 programmable analog blocks, -56 programmable digital blocks, Full-Speed USB, a serial memory interface, -a PDM-PCM digital microphone interface, and industry-leading capacitive-sensing -with CapSense. - -The PSoC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields. - -The Cortex-M0+ is a primary core on the board's SoC. It starts first and -enables the CM4 core. - -.. image:: img/cy8ckit_062_wifi_bt_m0.jpg - :align: center - :alt: CY8CKIT_062_WIFI_BT - -1. USB PD output voltage availability indicator (LED7) -2. Battery charging indicator (LED6) -3. KitProg2 USB Type-C connector (J10) -4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) -5. KitProg2 programming mode selection button (SW3) -6. KitProg2 I/O header (J6)1 -7. KitProg2 programming/custom application header (J7)1 -8. External power supply connector (J9) -9. PSoC 6 user button (SW2) -10. KitProg2 application selection button (SW4) -11. Digilent® Pmod™ compatible I/O header (J14)1 -12. Power LED (LED4) -13. KitProg2 status LEDs (LED1, LED2, and LED3) -14. PSoC 6 reset button (SW1) -15. PSoC 6 I/O header (J18, J19 and J20) -16. Arduino™ Uno R3 compatible power header (J1) -17. PSoC 6 debug and trace header (J12) -18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) -19. PSoC 6 program and debug header (J11) -20. CapSense proximity header (J13) -21. CapSense slider and buttons -22. PSoC 6 VDD selection switch (SW5) -23. Cypress 512-Mbit serial NOR Flash memory (S25-FL512S, U4) -24. PSoC 6 user LEDs (LED8 and LED9) -25. RGB LED (LED5) -26. WiFi/BT module (LBEE5KL 1DX, U6) -27. Cypress serial Ferroelectric RAM (U5)1 -28. WiFi-BT Antenna -29. VBACKUP and PMIC control selection switch (SW7)2 -30. PSoC 6 USB device Type-C connector (J28) -31. Cypress PSoC 6 (CY8C6247BZI-D54, U1) -32. PSoC 6 USB Host Type-A connector (J27) -33. Arduino Uno R3 compatible ICSP header (J5)1 -34. PSoC 6 power monitoring jumper (J8)2 -35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) -36. Battery connector (J15)1,2 -37. USB PD output voltage (9V/12V) connector (J16) - -Hardware -******** - -For more information about the PSoC 62 MCU SoC and CY8CKIT-062-WiFi-BT board: - -- `PSoC 62 MCU SoC Website`_ -- `PSoC 62 MCU Datasheet`_ -- `PSoC 62 MCU Architecture Reference Manual`_ -- `PSoC 62 MCU Register Reference Manual`_ -- `CY8CKIT-062-WiFi-BT Website`_ -- `CY8CKIT-062-WiFi-BT User Guide`_ -- `CY8CKIT-062-WiFi-BT Schematics`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0_defconfig`. - - -System Clock -============ - -The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - -Serial Port -=========== - -The PSoC 62 MCU SoC has 9 SCB blocks 8 of each can be configured as UART -interfaces for serial communication. At the moment UART5 on SCB5 and UART6 on -SCB6 are configured. SCB5 is connected to the onboard KitProg2's USB-UART -Bridge, SCB6 to P12_0, P12_1 pins on the J3 of the Arduino Uno R3 compatible -PSoC6 I/O header. - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - - -Programming and Debugging -************************* - -The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. There are also PSoC 6 program and debug headers J11 -and J12 that can be used with Segger J-Link. -A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and -Cy_WDT_Disable(). - -Only the CM0+ core starts by default after the MCU reset. In order to have -CM4 core working FW for both cores should be written into Flash. CM0+ FW -should starts the CM4 core at one point using -Cy_SysEnableCM4(CM4_START_ADDRESS); call. CM4_START_ADDRESS is 0x10060000 in -the current configuration. The CM0+/CM4 Flash/SRAM areas are defined in -:zephyr_file:`dts/arm/cypress/psoc6.dtsi`. - -Build the project for CM0+ - -.. zephyr-app-commands:: - :board: cy8ckit_062_wifi_bt_m0 - :goals: build - -Switch the DevKit into CMSIS-DAP mode using SW3 (LED2 should blink) and flash -the board: - -.. code-block:: console - - $\bin\openocd -c "source [find interface/cmsis-dap.cfg]" \ - -c "transport select swd" -c "source [find target/psoc6.cfg]" \ - -c "if [catch {program {\samples\hello_world\build\zephyr\zephyr.elf}} ] \ - { echo {** Program operation failed **} } \ - else { echo {** Program operation completed successfully **} }" \ - -c "reset_config srst_only;reset run;psoc6.dap dpreg 0x04 0x00;shutdown" - -Switch the DevKit back using SW3. Open a serial terminal (minicom, putty, -etc.) and connect to the board with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and the following message will appear on the corresponding -serial port: - -.. code-block:: console - - ***** Booting Zephyr OS zephyr-v1.13.0-1877-g9d14874db1 ***** - Hello World! cy8ckit_062_wifi_bt_m0 - - -References -********** - -.. _PSoC 62 MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 - -.. _PSoC 62 MCU Datasheet: - https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary - -.. _PSoC 62 MCU Architecture Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual - -.. _PSoC 62 MCU Register Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm - -.. _CY8CKIT-062-WiFi-BT Website: - https://www.cypress.com/documentation/development-kitsboards/psoc-6-wifi-bt-pioneer-kit - -.. _CY8CKIT-062-WiFi-BT User Guide: - https://www.cypress.com/file/407731/download - -.. _CY8CKIT-062-WiFi-BT Schematics: - https://www.cypress.com/file/420846/download diff --git a/boards/arm/cy8ckit_062s4/Kconfig.board b/boards/arm/cy8ckit_062s4/Kconfig.board deleted file mode 100644 index ab9cc0284e6148..00000000000000 --- a/boards/arm/cy8ckit_062s4/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CKIT_062S4_M4 - bool "PSoC 62S4 pioneer kit" - depends on SOC_CY8C6244LQI_S4D92 diff --git a/boards/arm/cy8ckit_062s4/Kconfig.defconfig b/boards/arm/cy8ckit_062s4/Kconfig.defconfig deleted file mode 100644 index 616fc65bb13055..00000000000000 --- a/boards/arm/cy8ckit_062s4/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CKIT_062S4_M4 - -config BOARD - default "cy8ckit_062s4_m4" if BOARD_CY8CKIT_062S4_M4 - - -endif #BOARD_CY8CKIT_062S4_M4 diff --git a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml b/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml deleted file mode 100644 index 19391fa39c448e..00000000000000 --- a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright (c) 2023 David Ullmann - -identifier: cy8ckit_062s4_m4 -name: CY8CKIT-062S4 PSoC 62S4 -type: mcu -arch: arm -ram: 128 -flash: 256 -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio -vendor: cypress diff --git a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig b/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig deleted file mode 100644 index 875c7f83f5507f..00000000000000 --- a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_PSOC_62=y -CONFIG_BOARD_CY8CKIT_062S4_M4=y -CONFIG_SOC_CY8C6244LQI_S4D92=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_PINCTRL=y -CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y - -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_XIP=y diff --git a/boards/arm/cy8ckit_062s4/doc/index.rst b/boards/arm/cy8ckit_062s4/doc/index.rst deleted file mode 100644 index 4e2cad8a0f126a..00000000000000 --- a/boards/arm/cy8ckit_062s4/doc/index.rst +++ /dev/null @@ -1,115 +0,0 @@ -.. _cy8ckit_062s4: - -[INFINEON PSoC 62S4 Pioneer Kit] -################################ - -Overview -******** -The PSOC 62S4 Pioneer kit has a CY8C62x4 MCU, which is an ultra-low-power PSoC device specifically designed for battery-operated analog -sensing applications. It includes a 150-MHz Arm® Cortex®-M4 CPU as the primary application processor, a 100-MHz Arm® Cortex®-M0+ CPU that -supports low-power operations, up to 256 KB Flash and 128 KB SRAM, programmable analog sensing, -CapSense™ touch-sensing, and programmable digital peripherals. - -The board features an onboard -programmer/debugger (KitProg3), a 512-Mbit Quad SPI NOR flash, a micro-B connector for USB device -interface, a thermistor, an ambient light sensor, a 5-segment CapSense™ slider, two CapSense™ buttons, two -user LEDs, and a push button. The board supports operating voltages from 1.8 V to 3.3 V for PSoC™ 6 MCU. - -.. figure::img/cy8ckit_062s4.png - :width: 800px - :align: center - :alt: Board Name - - Board Name (Credit: ) - -Hardware -******** - -`CY8CKIT 062S4 Pioneer Kit Website`_ -`CY8CKIT 062S4 Pioneer Kit Guide`_ -`CY8CKIT 062S4 Pioneer Kit Schematic`_ -`CY8CKIT 062S4 Pioneer Kit Technical Reference Manual`_ -`CY8CKIT 062S4 Pioneer Kit Datasheet`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -+-----------+------------+-----------------------+ - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4_defconfig`. - -Clock Configuration -=================== - -+-----------+------------+-----------------------+ -| Clock | Source | Output Frequency | -+===========+============+=======================+ -| FLL | IMO | 100.0 MHz | -+-----------+------------+-----------------------+ -| PLL | IMO | 48.0 MHz | -+-----------+------------+-----------------------+ -| CLK_HF0 | CLK_PATH0 | 100.0 MHz | -+-----------+------------+-----------------------+ - -Fetch Binary Blobs -================== - -.. code-block:: console - - west blobs fetch hal_infineon - - -Build and flash hello world sample -********************************** - - -.. code-block:: console - - cd zephyr/samples/hello_world - west build -p auto -b cy8ckit_062s4_m4 --pristine - west flash - picocom /dev/ttyACM0 -b 115200 - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - -References -********** - -.. _CY8CKIT 062S4 Pioneer Kit Guide: - https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S4_PSoC62S4_pioneer_kit_guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017e962f98992207 - -.. _CY8CKIT 062S4 Pioneer Kit Website: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062s4/?redirId=VL1508&utm_medium=referral&utm_source=cypress&utm_campaign=202110_globe_en_all_integration-dev_kit - -.. _CY8CKIT 062S4 Pioneer Kit Schematic: - https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S4_PSoC_62S4_Pioneer_Kit_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153484d2081 - -.. _CY8CKIT 062S4 Pioneer Kit Technical Reference Manual: - https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C61X4CY8C62X4_REGISTERS_TECHNICAL_REFERENCE_MANUAL_(TRM)_PSOC_61_PSOC_62_MCU-AdditionalTechnicalInformation-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0fb34f0627a7 - -.. _CY8CKIT 062S4 Pioneer Kit Datasheet: - https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_CY8C62X4-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7ddc01d7017ddd026d585901 diff --git a/boards/arm/cy8cproto_062_4343w/Kconfig.board b/boards/arm/cy8cproto_062_4343w/Kconfig.board deleted file mode 100644 index ab708cfb438437..00000000000000 --- a/boards/arm/cy8cproto_062_4343w/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit - -# Copyright (c) 2021 Cypress Semiconductor Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CPROTO_062_4343W - bool "CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit" diff --git a/boards/arm/cy8cproto_062_4343w/Kconfig.defconfig b/boards/arm/cy8cproto_062_4343w/Kconfig.defconfig deleted file mode 100644 index 0ed2d372835633..00000000000000 --- a/boards/arm/cy8cproto_062_4343w/Kconfig.defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit configuration - -# Copyright (c) 2021 Cypress Semiconductor Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CPROTO_062_4343W - -config BOARD - default "cy8cproto_062_4343w" - -if WIFI || BT - -# Select AIROC part and module -choice AIROC_PART - default CYW4343W -endchoice - -choice CYW4343W_MODULE - default CYW4343W_MURATA_1DX -endchoice - -endif # WIFI || BT - -if WIFI - -config WIFI_AIROC - default y - -# Enable L2 Ethernet -config NET_L2_ETHERNET - default y - -endif # WIFI - -if BT - -# Select HCI components -config UART - bool - default y - -config BT_UART - default y - -choice BT_HCI_BUS_TYPE - default BT_H4 -endchoice - -endif # BT - -# Heap Pool Size -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 15000 if WIFI - default 4096 - -endif # BOARD_CY8CPROTO_062_4343W diff --git a/boards/arm/cy8cproto_062_4343w/doc/index.rst b/boards/arm/cy8cproto_062_4343w/doc/index.rst deleted file mode 100644 index 9cf9c942591b7c..00000000000000 --- a/boards/arm/cy8cproto_062_4343w/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _cy8cproto_062_4343w: - -INFINEON CY8CPROTO-062-4343W -############################ - -Overview -******** - -The CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware -platform that enables design and debug of PSoC 6 MCUs. It comes with a Murata -LBEE5KL1DX module, based on the CYW4343W combo device, industry-leading CAPSENSE -for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD -card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. - -This kit is designed with a snap-away form-factor, allowing the user to separate -the different components and features that come with this kit and use independently. -In addition, support for Digilent's Pmod interface is also provided with this kit. - -.. image:: img/board.jpg - :align: center - :alt: CY8CPROTO-062-4343W - -Hardware -******** - -For more information about the PSoC 62 MCU SoC and CY8CPROTO-062-4343W board: - -- `PSoC 62 MCU SoC Website`_ -- `PSoC 62 MCU Datasheet`_ -- `PSoC 62 MCU Architecture Reference Manual`_ -- `PSoC 62 MCU Register Reference Manual`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide`_ -- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics`_ - -Kit Features: -============= - -- Support of up to 2MB Flash and 1MB SRAM -- Dedicated SDHC to interface with WICED wireless devices. -- Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary - application processor and a 100-MHz Arm Cortex-M0+ as the secondary - processor for low-power operations. -- Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM - digital microphone interface, a Quad-SPI interface, 13 serial communication - blocks, 7 programmable analog blocks, and 56 programmable digital blocks. - -Kit Contents: -============= - -- PSoC 6 Wi-Fi BT Prototyping Board -- USB Type-A to Micro-B cable -- Quick Start Guide - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | GPIO | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ - - -The default configuration can be found in the Kconfig - -:zephyr_file:`boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig` - - -System Clock -============ - -The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - - -Fetch Binary Blobs -****************** - -cy8cproto_062_4343w board requires fetch binary files -(e.g WIFI/Bluetooth chip firmware, CM0p prebuilt images, etc). - -To fetch Binary Blobs: - -.. code-block:: console - - west blobs fetch hal_infineon - - -Build blinking led sample -************************* - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. code-block:: console - - cd zephyr - west build -p auto -b cy8cproto_062_4343w samples/basic/blink - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - - -Programming and Debugging -************************* - -The CY8CPROTO-062-4343W includes an onboard programmer/debugger (KitProg2) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. Flash and debug commands must be pointed to the Cypress -OpenOCD you downloaded above. - -On Windows: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd.exe - west debug --openocd path/to/infineon/openocd/bin/openocd.exe - -On Linux: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd - west debug --openocd path/to/infineon/openocd/bin/openocd - -Once the gdb console starts after executing the west debug command, you may -now set breakpoints and perform other standard GDB debugging on the PSoC 6 CM4 core. - -Errata -====== - -+------------------------------------------------+----------------------------------------+ -| Problem | Solution | -+================================================+========================================+ -| The GPIO_INT_TRIG_BOTH interrupt is not raised | This will be fixed in a future release.| -| when the associated GPIO is asserted. | | -+------------------------------------------------+----------------------------------------+ -| GDB experiences a timeout error connecting to | This will be fixed in a future release.| -| a server instance started by west debugserver. | | -+------------------------------------------------+----------------------------------------+ - -.. _PSoC 62 MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 - -.. _PSoC 62 MCU Datasheet: - https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary - -.. _PSoC 62 MCU Architecture Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual - -.. _PSoC 62 MCU Register Reference Manual: - https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm - -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/ - -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f0118571844 - -.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f01126b183f - -.. _Infineon OpenOCD: - https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cy8cproto_063_ble/Kconfig.board b/boards/arm/cy8cproto_063_ble/Kconfig.board deleted file mode 100644 index f4fd16cef11bf3..00000000000000 --- a/boards/arm/cy8cproto_063_ble/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit -# -# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_CY8CPROTO_063_BLE - bool "CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit with single CPU" diff --git a/boards/arm/cy8cproto_063_ble/Kconfig.defconfig b/boards/arm/cy8cproto_063_ble/Kconfig.defconfig deleted file mode 100644 index d6e691e3f02b13..00000000000000 --- a/boards/arm/cy8cproto_063_ble/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit - -# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_CY8CPROTO_063_BLE - -config BOARD - default "cy8cproto_063_ble" - -choice BT_HCI_BUS_TYPE - default BT_PSOC6_BLESS if BT -endchoice - -endif # BOARD_CY8CPROTO_063_BLE diff --git a/boards/arm/cy8cproto_063_ble/doc/index.rst b/boards/arm/cy8cproto_063_ble/doc/index.rst deleted file mode 100644 index 58ac2a9818317f..00000000000000 --- a/boards/arm/cy8cproto_063_ble/doc/index.rst +++ /dev/null @@ -1,145 +0,0 @@ -.. _cy8cproto_063_ble: - -INFINEON CY8CPROTO-063-BLE -########################### - -Overview -******** - -The PSoC 6 BLE Proto Kit (CY8CPROTO-063-BLE) is a hardware platform that -enables design and debug of the Cypress PSoC 63 BLE MCU. - -.. image:: img/cy8cproto-063-ble.jpg - :align: center - :alt: CY8CPROTO-063-BLE - -Hardware -******** - -For more information about the PSoC 63 BLE MCU SoC and CY8CPROTO-063-BLE board: - -- `PSoC 63 BLE MCU SoC Website`_ -- `PSoC 63 BLE MCU Datasheet`_ -- `PSoC 63 BLE MCU Architecture Reference Manual`_ -- `PSoC 63 BLE MCU Register Reference Manual`_ -- `CY8CPROTO-063-BLE Website`_ -- `CY8CPROTO-063-BLE User Guide`_ -- `CY8CPROTO-063-BLE Schematics`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-----------------------+ -| PINCTRL | on-chip | pin control | -+-----------+------------+-----------------------+ -| SPI | on-chip | spi | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-----------------------+ -| I2C | on-chip | I2C | -+-----------+------------+-----------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-----------------------+ -| Counter | on-chip | Counter | -+-----------+------------+-----------------------+ -| Bluetooth | on-chip | Bluetooth | -+-----------+------------+-----------------------+ - - -The default configurations can be found in the Kconfig - -:zephyr_file:`boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` - -System Clock -============ - -The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for -the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the -system clock are provided in the SOC, depending on your system requirements. - - -OpenOCD Installation -==================== - -To get the OpenOCD package, it is required that you - -1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox -2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox - export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts -3. Add the OpenOCD executable file's path to west flash/debug. -4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd -5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd - - -Fetch Binary Blobs -****************** - -cy8cproto_063_ble board requires fetch binary files -(e.g Bluetooth controller firmware, CM0p prebuilt images, etc). - -To fetch Binary Blobs: - -.. code-block:: console - - west blobs fetch hal_infineon - -Programming and Debugging -************************* - -The CY8CPROTO-063-BLE includes an onboard programmer/debugger (KitProg3) with -mass storage programming to provide debugging, flash programming, and serial -communication over USB. Flash and debug commands must be pointed to the Cypress -OpenOCD you downloaded above. - -On Windows: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd.exe - west debug --openocd path/to/infineon/openocd/bin/openocd.exe - -On Linux: - -.. code-block:: console - - west flash --openocd path/to/infineon/openocd/bin/openocd - west debug --openocd path/to/infineon/openocd/bin/openocd - -References -********** - -.. _PSoC 63 BLE MCU SoC Website: - https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 - -.. _PSoC 63 BLE MCU Datasheet: - https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_PSoC_63_with_BLE_Datasheet_Programmable_System-on-Chip_(PSoC)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee4efe46c37&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files - -.. _PSoC 63 BLE MCU Architecture Reference Manual: - https://documentation.infineon.com/html/psoc6/zrs1651212645947.html - -.. _PSoC 63 BLE MCU Register Reference Manual: - https://documentation.infineon.com/html/psoc6/bnm1651211483724.html - -.. _CY8CPROTO-063-BLE Website: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/ - -.. _CY8CPROTO-063-BLE User Guide: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00d7eb1812 - -.. _CY8CPROTO-063-BLE Schematics: - https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00ea3c1821 - -.. _Infineon OpenOCD: - https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cyclonev_socdk/Kconfig.board b/boards/arm/cyclonev_socdk/Kconfig.board deleted file mode 100644 index 9743baf1cc5948..00000000000000 --- a/boards/arm/cyclonev_socdk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Cyclone V SoC development kit configuration option - -config BOARD_CVSXDEVKIT - bool "Intel Cyclone V Development Kit" - depends on SOC_CYCLONE5 diff --git a/boards/arm/cyclonev_socdk/Kconfig.defconfig b/boards/arm/cyclonev_socdk/Kconfig.defconfig deleted file mode 100644 index 240a85753806b0..00000000000000 --- a/boards/arm/cyclonev_socdk/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC DevKit - -if BOARD_CVSXDEVKIT - -config BOARD - default "cyclonev_socdk" -depends on BOARD_CVSXDEVKIT - -if I2C_DW -config I2C_DW_CLOCK_SPEED - default 200 -endif # I2C_DW - -if USB_DEVICE_STACK -config USB_DW_USB_2_0 - default y -config USB_DEVICE_DRIVER - default y -endif # USB_DEVICE_STACK - -if NETWORKING - -config NET_L2_ETHERNET - default y -config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif # BOARD_CVSXDEVKIT diff --git a/boards/arm/cyclonev_socdk/board.cmake b/boards/arm/cyclonev_socdk/board.cmake deleted file mode 100644 index fe4c06d5484709..00000000000000 --- a/boards/arm/cyclonev_socdk/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Cmake file for the OpenOCD runner for Cyclone V SoC DevKit - -board_set_flasher_ifnset(intel_cyclonev) -board_set_debugger_ifnset(intel_cyclonev) - -if(OPENOCD_USE_LOAD_IMAGE) - set_ifndef(OPENOCD_FLASH load_image) -else() - set_ifndef(OPENOCD_FLASH "flash write_image erase") -endif() - -set(OPENOCD_CMD_LOAD_DEFAULT "${OPENOCD_FLASH}") -set(OPENOCD_CMD_VERIFY_DEFAULT "verify_image") - -board_finalize_runner_args(intel_cyclonev - --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}" - --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}" - ) - diff --git a/boards/arm/cyclonev_socdk/cyclonev_socdk_defconfig b/boards/arm/cyclonev_socdk/cyclonev_socdk_defconfig deleted file mode 100644 index 110a703d4a1967..00000000000000 --- a/boards/arm/cyclonev_socdk/cyclonev_socdk_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Cyclone V SoC Development Kit Board configuration file - -CONFIG_SOC_SERIES_CYCLONE5=y -CONFIG_SOC_CYCLONE5=y -CONFIG_BOARD_CVSXDEVKIT=y -CONFIG_ARM_ARCH_TIMER=y - -CONFIG_SYSCON=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_NS16550_VARIANT_NS16950=y - -#Config Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -#Flash not used. -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 - -# GPIOs -CONFIG_GPIO=y diff --git a/boards/arm/cyclonev_socdk/doc/index.rst b/boards/arm/cyclonev_socdk/doc/index.rst deleted file mode 100644 index 1f51e20650c88c..00000000000000 --- a/boards/arm/cyclonev_socdk/doc/index.rst +++ /dev/null @@ -1,359 +0,0 @@ -.. _cyclonev_socdk: - -Intel® Cyclone® V SoC Development Kit -##################################### - -Overview -******** - - -The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit, -using its Hard Processor System (HPS) CPU. - -.. figure:: img/cv_soc_board.jpg - :align: center - :alt: Intel's Cyclone® V SoC FPGA DevKit - - Intel®'s Cyclone® V SoC FPGA DevKit (Credit: Intel®) - -Hardware -******** - -Jumpers and DIP Switch settings -=============================== - -Recommended board settings are the same as the GSRD for Cyclone® V -SoC Development Board. - -There are two sets of switches on the back of the board. Of particular -importance is SW2. First, the board jumpers need to be configured as follows: - -* J5 : Open -* J6 : Short -* J7 : Short -* J9 : Open -* J13: Short -* J16: Open -* J26: Short pins 1-2 -* J27: Short pins 2-3 -* J28: Short pins 1-2 -* J29: Short pins 2-3 -* J30: Short pins 1-2 -* J31: Open - -Then, the board switches need to be configured as follows: - -* SW1: All OFF -* SW2: All OFF -* SW3: ON-OFF-ON-OFF-ON-ON -* SW4: OFF-OFF-ON-ON - -Other switches are user switches, their position is application-specific. -Refer to the development kit user manual for specifics about jumpers and switches - -Necessary Software -================== - -You will need the Intel® Quartus® Prime SDK in order to work with this device. The -`Intel® Quartus® Prime Lite Edition `_ -for Linux may be obtained without charge. - -For your convenience using the SDK tools (such as ``quartus_pgm``), -you should put the binaries provided by the SDK -in your path. Below is an example, adjust ALTERA_BASE to where you installed the -SDK: - -.. code-block:: console - - export QUARTUS_ROOTDIR=/opt/intelFPGA_lite/21.1 - export PATH=$PATH:$QUARTUS_ROOTDIR/quartus/bin:$QUARTUS_ROOTDIR/programmer/bin - -You may need to adjust your udev rules so that you can talk to the USB Blaster -II peripheral, which is the built-in JTAG interface for this device. - -The following works for Ubuntu: - -.. code-block:: console - - # For Altera USB-Blaster permissions. - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6010",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6810",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - -You can test connectivity with the SDK jtagconfig tool, you should see something -like: - -.. code-block:: console - - $ jtagconfig - 1) USB-BlasterII [1-5] - 4ba00477 SOCVHPS - 02D020DD 5ZSEBA6(.|ES)/5CSEMA6/.. - - -Golden Reference Design -======================= - -The Golden System Reference Design (GSRD) provides a set of essential hardware -and software system componets that can be used as a starting point for various -custom user designs. - -The Zephyr support for Cyclone® V SoC Development Kit is based on GSRD hardware. -Please refer to `Intel® Cyclone® V SoC GSRD `_ - -The hardware use for this release is based on Intel® Quartus® version 21.1 -the hardware files can be found `here `_ - -The directory "cv_soc_devkit_ghrd" contains the necessary files to create -a Intel® Quartus® project: - -* ghrd_top.v : top level Verilog (HDL) file for the GSRD -* soc_system.qpf : Quartus® Prime Project File -* soc_system.qsf : Quartus® Prime Settings File -* soc_system.qsys : Platform Designer file (contains the SoC system) -* soc_system.sopcinfo : SOPC Information file contains details about modules instantiated in the project, parameter names and values. -* soc_system_timing.sdc : Synopsys Desing Constraint FILE. -* output_files/soc_system.sof : FPGA configuration file. - - -Flash this FPGA file (.sof) using the ``quartus_pgm`` SDK tool with the FPGA -configuration file soc_system.sof: - -.. code-block:: console - - $ quartus_pgm -m jtag -o "p;path/to/soc_system.sof" - -This system is composed by the HPS, ARM Cortex-A9. In this example the UART, timer, -USB, I2C, DDR memory are exposed. Please double check the peripheral you intend to -use have its corresponding driver support. -You can find more information of the Cyclone® V SoC Devkit GSRD in RocketBoards -or consult the "Cyclone® V Hard Processor System Technical Reference Manual" - - -Console Output -============== - -16550 UART ----------- - -By default, the kernel is configured to send console output to the 16550 UART. -You can monitor this on your workstation by connecting to the top right mini USB -port on the board (J8/UART) (it will show up in /dev as a ttyUSB node), and then running -minicom/PuTTy with flow control disabled, 115200-8N1 settings. - - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Kernel into the board ------------------------------- - -The usual ``flash`` target will work with the ``cyclonev_socdk`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -``Important!!!`` : Before flashing the board a ``preloader`` is required, -you can download `cv_soc_devkit_ghrd.tar.gz `_, -extract the file and copy ``cv_soc_devkit_ghrd/software/preloader/uboot-socfpga/spl/u-boot-spl`` -to ``boards/arm/cyclonev_socdk/support/`` - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cyclonev_socdk - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -This provisions the Zephyr kernel and the CPU configuration onto the board, -using the customized OpenOCD runner script :zephyr_file:`scripts/west_commands/runners/intel_cyclonev.py` -After it completes the kernel will immediately boot using the GSRD preloader. -Notice that there a lot of helper files to ``flash`` the application with -OpenOCD and GDB Debbuger (Zephyr SDK must be installed in your machine). -This files should be located in :zephyr_file:`boards/arm/cyclonev_socdk/support/` including: - -* blaster_6810.hex : USB-BlasterII firmware -* tmp_preloader_dl_cmd.txt : GDB helper file to load the preloader -* tmp_appli_dl_cmd.gdb : GDB helper file to load the zephyr.elf file -* tmp_appli_debug_cmd.gdb : GDB helper file to load the zephyr.elf file while debugging -* openocd.cfg : sources configuration files for OpenOCD -* download_all.gdb : GDB helper file to load the preloader -* u-boot-spl : Cyclone® V SoC DevKit GSRD preloader (copied from GSRD: cv_soc_devkit_ghrd.tar.gz) - -The following image shows the expected output (UART) after executing "west flash" using -the "hello world" sample design: - -.. figure:: img/cyclonev_westflash.jpg - :align: center - :alt: UART output after "west flash" example - - UART output after "west flash" example (Credit: Intel®) - -Debugging -========= - -The Zephyr SDK includes a GDB server which can be used to debug a Cyclone® V -SoC Development Kit board. -You can either debug a running image that was flashed onto the device in User -Flash Memory (UFM), or load an image over the JTAG using GDB. - -Debugging With Flashed Image ----------------------------- - -You can debug an application in the usual way. Here is an example. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: cyclonev_socdk - :goals: debug - -You will see output similar to the following: - -.. code-block:: console - - -- west debug: rebuilding - ninja: no work to do. - -- west debug: using runner intel_cyclonev - -- runners.intel_cyclonev: OpenOCD GDB server running on port 3333; no thread info available - Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) - Licensed under GNU GPL v2 - For bug reports, read http://openocd.org/doc/doxygen/bugs.html - Info : only one transport option; autoselect 'jtag' - cycv_dbginit - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - Info : Altera USB-Blaster II (uninitialized) found - Info : Loading firmware... - Info : Waiting for reenumerate... - Info : Waiting for reenumerate... - Info : Altera USB-Blaster II found (Firm. rev. = 1.39) - Info : This adapter doesn't support configurable speed - Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) - Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) - Info : DAP transaction stalled (WAIT) - slowing down - Info : DAP transaction stalled (WAIT) - slowing down - Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints - Info : starting gdb server for fpgasoc.cpu.0 on 3333 - Info : Listening on port 3333 for gdb connections - Info : accepting 'gdb' connection on tcp/3333 - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT - target halted in ARM state due to debug-request, current mode: Supervisor - cpsr: 0x600001d3 pc: 0x00002fa4 - MMU: disabled, D-Cache: disabled, I-Cache: enabled - warning: No executable has been specified and target does not support - determining executable automatically. Try using the "file" command. - 0x00002fa4 in ?? () - Restoring section .text (0xffff0000 to 0xffff6f84) - Info : DAP transaction stalled (WAIT) - slowing down - Warn : keep_alive() was not invoked in the 1000 ms timelimit. GDB alive packet not sent! (1469 ms). Workaround: increase "set remotetimeout" in GDB - Restoring section .rodata (0xffff6f84 to 0xffff8af9) - Restoring section .data (0xffff8b00 to 0xffff99d4) - Info : DAP transaction stalled (WAIT) - slowing down - Hardware assisted breakpoint 1 at 0xffff147e - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - - Temporary breakpoint 1, 0xffff147e in spl_boot_device () - [Inferior 1 (Remote target) detached] - Info : dropped 'gdb' connection - shutdown command invoked - Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) - Licensed under GNU GPL v2 - For bug reports, read http://openocd.org/doc/doxygen/bugs.html - Info : only one transport option; autoselect 'jtag' - cycv_dbginit - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - Info : Altera USB-Blaster II found (Firm. rev. = 1.39) - Info : This adapter doesn't support configurable speed - Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) - Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) - Info : DAP transaction stalled (WAIT) - slowing down - Info : DAP transaction stalled (WAIT) - slowing down - Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT - Info : starting gdb server for fpgasoc.cpu.0 on 3333 - Info : Listening on port 3333 for gdb connections - Info : accepting 'gdb' connection on tcp/3333 - warning: No executable has been specified and target does not support - determining executable automatically. Try using the "file" command. - 0xffff147c in ?? () - warning: /home/demo/zephyrproject/zephyr/boards/arm/cvsxdevkit/support/tmp_appli_debug_cmd.gdb: No such file or directory - [Inferior 1 (Remote target) detached] - Info : dropped 'gdb' connection - shutdown command invoked - Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) - Licensed under GNU GPL v2 - For bug reports, read http://openocd.org/doc/doxygen/bugs.html - Info : only one transport option; autoselect 'jtag' - cycv_dbginit - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - Info : Altera USB-Blaster II found (Firm. rev. = 1.39) - Info : This adapter doesn't support configurable speed - Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) - Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) - Info : DAP transaction stalled (WAIT) - slowing down - Info : DAP transaction stalled (WAIT) - slowing down - Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints - Reading symbols from /home/demo/zephyrproject/zephyr/build/zephyr/zephyr.elf... - Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 - Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT - Info : starting gdb server for fpgasoc.cpu.0 on 3333 - Info : Listening on port 3333 for gdb connections - Remote debugging using :3333 - Info : accepting 'gdb' connection on tcp/3333 - main () at /home/demo/zephyrproject/zephyr/samples/hello_world/src/main.c:11 - 11 printk("Hello World! %s\n", CONFIG_BOARD); - (gdb) - - -Try other examples -================== -There are varios examples that can be downloaded to the Cyclone® V SoC FPGA -Development Kit Board. Try to ``blink`` an LED from the HPS side of the chip: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: cyclonev_socdk - :goals: flash - -.. figure:: img/cyclonev_blinky.jpg - :align: center - :alt: HPS LED0 blinking example - - HPS LED0 blinking example (Credit: Intel®) - -Try writing characters to the LCD display connected to the i2c bus: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/lcd_cyclonev_socdk - :board: cyclonev_socdk - :goals: flash - - -References -********** - -* `Cyclone® V Hard Processor System Technical Reference Manual `_ -* `Cyclone® V SoC Development Kit and Intel® SoC FPGA Embedded Development Suite `_ -* `Cyclone® V SoC GSRD in RocketBoards.org `_ -* `Intel® FPGA Software Download Center `_ -* `Embedded Peripherals IP User Guide `_ -* `Quartus II Scripting Reference Manual `_ diff --git a/boards/arm/cyclonev_socdk/support/download_all.gdb b/boards/arm/cyclonev_socdk/support/download_all.gdb deleted file mode 100644 index a1c7a9a4760732..00000000000000 --- a/boards/arm/cyclonev_socdk/support/download_all.gdb +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Download preloader and .elf using GDB commands - -set confirm off -set pagination off - -#Download and Run preloader -source boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt - -#Stop watchdog timer -#permodrst Reg , reset watch dog timer -set $permodrst = (int *)0xffd05014 -set *$permodrst = (*$permodrst) | (1<<6) -set *$permodrst = (*$permodrst) & ~(1<<6) - -quit diff --git a/boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt b/boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt deleted file mode 100644 index 3a10f686902331..00000000000000 --- a/boards/arm/cyclonev_socdk/support/preloader_dl_cmd.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Helper file to download the GSRD preloader to the board before the application - -restore boards/arm/cyclonev_socdk/support/u-boot-spl -symbol-file -readnow boards/arm/cyclonev_socdk/support/u-boot-spl -thbreak spl_boot_device -jump _start diff --git a/boards/arm/da14695_dk_usb/Kconfig b/boards/arm/da14695_dk_usb/Kconfig deleted file mode 100644 index 38ccd8265071a4..00000000000000 --- a/boards/arm/da14695_dk_usb/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# DA14695 Development Kit USB board configuration - -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/da14695_dk_usb/Kconfig.board b/boards/arm/da14695_dk_usb/Kconfig.board deleted file mode 100644 index 67dbe731ffa538..00000000000000 --- a/boards/arm/da14695_dk_usb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# DA14695 Development Kit USB board configuration - -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DA14695_DK_USB - bool "DA14695 Development Kit USB board" - depends on SOC_SERIES_DA1469X diff --git a/boards/arm/da14695_dk_usb/Kconfig.defconfig b/boards/arm/da14695_dk_usb/Kconfig.defconfig deleted file mode 100644 index 8208a705bd8391..00000000000000 --- a/boards/arm/da14695_dk_usb/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# DA14695 Development Kit USB board configuration - -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DA14695_DK_USB - -config BOARD - default "da14695_dk_usb" - -endif # BOARD_DA14695_DK_USB diff --git a/boards/arm/da1469x_dk_pro/Kconfig b/boards/arm/da1469x_dk_pro/Kconfig deleted file mode 100644 index 0bca6654e153ab..00000000000000 --- a/boards/arm/da1469x_dk_pro/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# DA1469x series Development Kit Pro board configuration - -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/da1469x_dk_pro/Kconfig.board b/boards/arm/da1469x_dk_pro/Kconfig.board deleted file mode 100644 index 0c7f9e23b2fb2f..00000000000000 --- a/boards/arm/da1469x_dk_pro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# DA1469x series Development Kit Pro board configuration - -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DA1469X_DK_PRO - bool "DA1469x series Development Kit Pro board" - depends on SOC_SERIES_DA1469X diff --git a/boards/arm/da1469x_dk_pro/Kconfig.defconfig b/boards/arm/da1469x_dk_pro/Kconfig.defconfig deleted file mode 100644 index b0a50f80d54894..00000000000000 --- a/boards/arm/da1469x_dk_pro/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# DA1469x series Development Kit Pro board configuration - -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DA1469X_DK_PRO - -config BOARD - default "da1469x_dk_pro" - -endif # BOARD_DA1469X_DK_PRO diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro_defconfig b/boards/arm/da1469x_dk_pro/da1469x_dk_pro_defconfig deleted file mode 100644 index c0f0e461d2b366..00000000000000 --- a/boards/arm/da1469x_dk_pro/da1469x_dk_pro_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_DA1469X=y -CONFIG_SOC_DA14699=y -CONFIG_BOARD_DA1469X_DK_PRO=y - -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_GPIO=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_BUILD_OUTPUT_HEX=n - -CONFIG_I2C=y -CONFIG_I2C_CALLBACK=y diff --git a/boards/arm/decawave_dwm1001_dev/Kconfig.board b/boards/arm/decawave_dwm1001_dev/Kconfig.board deleted file mode 100644 index ebfd2c581bcb17..00000000000000 --- a/boards/arm/decawave_dwm1001_dev/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# DecaWave DWM1001 board configuration - -# Copyright (c) 2019 Stéphane D'Alu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DECAWAVE_DWM1001_DEV - bool "Decawave DWM1001-DEV" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/decawave_dwm1001_dev/Kconfig.defconfig b/boards/arm/decawave_dwm1001_dev/Kconfig.defconfig deleted file mode 100644 index c64fe40b645fb7..00000000000000 --- a/boards/arm/decawave_dwm1001_dev/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# DecaWave DWM1001 board configuration - -# Copyright (c) 2019 Stéphane D'Alu -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DECAWAVE_DWM1001_DEV - -config BOARD - default "decawave_dwm1001_dev" - -config BT_CTLR - default BT - -config I2C - default SENSOR - -config SPI - default y - depends on IEEE802154 - -endif # BOARD_DECAWAVE_DWM1001_DEV diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig b/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig deleted file mode 100644 index b77b8937a7751d..00000000000000 --- a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_DECAWAVE_DWM1001_DEV=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_RTT_CONSOLE=y diff --git a/boards/arm/degu_evk/Kconfig.board b/boards/arm/degu_evk/Kconfig.board deleted file mode 100644 index 99c579690e1626..00000000000000 --- a/boards/arm/degu_evk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Degu Evaluation Kit configuration - -# Copyright (c) 2019 Atmark Techno, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DEGU_EVK - bool "DEGU_EVK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/degu_evk/Kconfig.defconfig b/boards/arm/degu_evk/Kconfig.defconfig deleted file mode 100644 index cad67382531299..00000000000000 --- a/boards/arm/degu_evk/Kconfig.defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Degu Evaluation Kit configuration - -# Copyright (c) 2019 Atmark Techno, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DEGU_EVK - -config BOARD - default "degu_evk" - -if USB_DEVICE_STACK - -config USB_DEVICE_PRODUCT - default "Degu Evaluation Kit" - -config UART_INTERRUPT_DRIVEN - default y - -config UART_LINE_CTRL - default y - -endif # USB_DEVICE_STACK - -if LOG - -# Logger cannot use itself to log -config USB_CDC_ACM_LOG_LEVEL - default 0 - -# Set USB log level to error only -config USB_DEVICE_LOG_LEVEL - default 1 - -endif # LOG - -endif # BOARD_DEGU_EVK diff --git a/boards/arm/degu_evk/degu_evk_defconfig b/boards/arm/degu_evk/degu_evk_defconfig deleted file mode 100644 index 6123f6c756e0f6..00000000000000 --- a/boards/arm/degu_evk/degu_evk_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_DEGU_EVK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable USB (for CDC ACM console) -CONFIG_USB_DEVICE_STACK=y - -# additional board options -CONFIG_GPIO=y - -# required to enable 3V3 power rail and Vin1 monitor -CONFIG_REGULATOR=y diff --git a/boards/arm/disco_l475_iot1/Kconfig.board b/boards/arm/disco_l475_iot1/Kconfig.board deleted file mode 100644 index 98e8d2917827db..00000000000000 --- a/boards/arm/disco_l475_iot1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Discovery IoT L475 board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DISCO_L475_IOT1 - bool "Discovery IoT L475 Development Board" - depends on SOC_STM32L475XX diff --git a/boards/arm/disco_l475_iot1/Kconfig.defconfig b/boards/arm/disco_l475_iot1/Kconfig.defconfig deleted file mode 100644 index 3a53147decf641..00000000000000 --- a/boards/arm/disco_l475_iot1/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# Discovery IoT L475 board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DISCO_L475_IOT1 - -config BOARD - default "disco_l475_iot1" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -choice LIS3MDL_TRIGGER_MODE - default LIS3MDL_TRIGGER_NONE -endchoice - -choice HTS221_TRIGGER_MODE - default HTS221_TRIGGER_NONE -endchoice - -choice LSM6DSL_TRIGGER_MODE - default LSM6DSL_TRIGGER_GLOBAL_THREAD - depends on LSM6DSL -endchoice - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n -config BT_HCI_VS_EXT - default n - -endif # BT - -endif # BOARD_DISCO_L475_IOT1 diff --git a/boards/arm/disco_l475_iot1/doc/index.rst b/boards/arm/disco_l475_iot1/doc/index.rst deleted file mode 100644 index 906729fcf8e411..00000000000000 --- a/boards/arm/disco_l475_iot1/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _disco_l475_iot1_board: - -ST Disco L475 IOT01 (B-L475E-IOT01A) -#################################### - -Overview -******** - -The B-L475E-IOT01A Discovery kit for IoT node allows users to develop -applications with direct connection to cloud servers. -The Discovery kit enables a wide diversity of applications by exploiting -low-power communication, multiway sensing and ARM |reg| Cortex |reg|-M4 core-based -STM32L4 Series features. - -This kit provides: - -- 64-Mbit Quad-SPI (Macronix) Flash memory -- Bluetooth |reg| V4.1 module (SPBTLE-RF) -- Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868 or SPSGRF-915) -- Wi-Fi |reg| module Inventek ISM43362-M3G-L44 (802.11 b/g/n compliant) -- Dynamic NFC tag based on M24SR with its printed NFC antenna -- 2 digital omni-directional microphones (MP34DT01) -- Capacitive digital sensor for relative humidity and temperature (HTS221) -- High-performance 3-axis magnetometer (LIS3MDL) -- 3D accelerometer and 3D gyroscope (LSM6DSL) -- 260-1260 hPa absolute digital output barometer (LPS22HB) -- Time-of-Flight and gesture-detection sensor (VL53L0X) -- 2 push-buttons (user and reset) -- USB OTG FS with Micro-AB connector -- Expansion connectors: - - Arduino |trade| Uno V3 - - PMOD -- Flexible power-supply options: - - ST LINK USB VBUS or external sources -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: - - mass storage, virtual COM port and debug port - - -.. image:: img/disco_l475_iot1.jpg - :align: center - :alt: Disco L475 IoT1 - -More information about the board can be found at the `Disco L475 IoT1 website`_. - -Hardware -******** - -The STM32L475VG SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 120 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L475VG can be found here: - - `STM32L475VG on www.st.com`_ - - `STM32L475 reference manual`_ - -Supported Features -================== - -The Zephyr Disco L475 IoT board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig`` - - -Connections and IOs -=================== - -Disco L475 IoT Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `STM32 Disco L475 IoT1 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) -- UART_4 TX/RX : PA0/PA1 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) -- I2C3 SCL/SDA : PC0/PC1 -- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) -- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) -- PWM_2_CH1 : PA15 -- USER_PB : PC13 -- LD2 : PA5 -- ADC12_IN5 : PA0 -- ADC123_IN3 : PC2 -- ADC123_IN4 : PC3 -- ADC12_IN13 : PC4 -- ADC12_IN14 : PC5 -- DAC1_OUT1 : PA4 - -System Clock ------------- - -Disco L475 IoT System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Disco L475 IoT board has 6 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``disco_l475_iot1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Disco L475 IoT ------------------------------------------ - -Here is an example for the :ref:`hello_world` application. - -Connect the Disco L475 IoT to your host computer using the USB port, then -run a serial host program to connect with your Nucleo board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: disco_l475_iot1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: disco_l475_iot1 - :maybe-skip-config: - :goals: debug - -.. _Disco L475 IoT1 website: - https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/b-l475e-iot01a.html - -.. _STM32 Disco L475 IoT1 board User Manual: - https://www.st.com/resource/en/user_manual/dm00347848.pdf - -.. _STM32L475VG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l475vg.html - -.. _STM32L475 reference manual: - https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/dragino_lsn50/Kconfig.board b/boards/arm/dragino_lsn50/Kconfig.board deleted file mode 100644 index ba1b1277140c47..00000000000000 --- a/boards/arm/dragino_lsn50/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Dragino LSN50 LoRA Sensor Node board configuration - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DRAGINO_LSN50 - bool "Dragino LSN50 Sensor Node" - depends on SOC_STM32L072XX diff --git a/boards/arm/dragino_lsn50/Kconfig.defconfig b/boards/arm/dragino_lsn50/Kconfig.defconfig deleted file mode 100644 index 05f7b5fd5492fe..00000000000000 --- a/boards/arm/dragino_lsn50/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Dragino LSN50 LoRA Sensor Node board configuration - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DRAGINO_LSN50 - -config BOARD - default "dragino_lsn50" - -endif # BOARD_DRAGINO_LSN50 diff --git a/boards/arm/dragino_lsn50/doc/index.rst b/boards/arm/dragino_lsn50/doc/index.rst deleted file mode 100644 index 732e0ec1394b2f..00000000000000 --- a/boards/arm/dragino_lsn50/doc/index.rst +++ /dev/null @@ -1,194 +0,0 @@ -.. _dragino_lsn50_board: - -Dragino LSN50 LoRA Sensor Node -############################## - -Overview -******** - -The Dragino LSN50 LoRA Sensor Node for IoT allows users to develop -applications with LoraWAN connectivity via the HopeRF / SX1276/SX1278. -Dragino LSN50 enables a wide diversity of applications by exploiting -low-power communication, ARM |reg| Cortex |reg|-M0 core-based -STM32L0 Series features. - -This kit provides: - -- STM32L072CZ MCU -- SX1276/SX1278 LoRa Transceiver -- Expansion connectors: - - - PMOD -- Li/SOCI2 Unchargable Battery -- GPIOs exposed via screw terminals on the carrier board -- Housing - -.. image:: img/dragino_lsn50.jpg - :align: center - :alt: Dragino LSN50 - -More information about the board can be found at the `Dragino LSN50 website`_. - -Hardware -******** - -The STM32L072CZ SoC provides the following hardware IPs: - -- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz -- Clock Sources: - - - 1 to 32 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) - - Internal multispeed low-power 65 kHz to 4.2 MHz RC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 2x 16-bit with up to 4 channels - - 2x 16-bit with up to 2 channels - - 1x 16-bit ultra-low-power timer - - 1x SysTick - - 1x RTC - - 2x 16-bit basic for DAC - - 2x watchdogs (independent/window) -- Up to 84 fast I/Os, most 5 V-tolerant. -- Memories - - - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 20 KB of SRAM - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 1.14 MSPS - - 2x 12-bit DAC - - 2x ultra-low-power comparators -- 11x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 6x SPIs (4x SPIs with the Quad SPI) -- 7-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L072CZ can be found here: - - - `STM32L072CZ on www.st.com`_ - - `STM32L0x2 reference manual`_ - -Supported Features -================== - -The Zephyr Dragino LSN50 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/dragino_lsn50/dragino_lsn50_defconfig`` - - -Connections and IOs -=================== - -Dragino LSN50 Board has GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `Dragino LSN50 website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 - -System Clock ------------- - -Dragino LSN50 System Clock is at 32MHz, - -Serial Port ------------ - -Dragino LSN50 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``dragino_lsn50`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Dragino LSN50 board requires an external debugger. - -Flashing an application to Dragino LSN50 ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_lsn50 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_lsn50 - :maybe-skip-config: - :goals: debug - -.. _Dragino LSN50 website: - https://www.dragino.com/products/lora-lorawan-end-node/item/128-lsn50.html - -.. _STM32L072CZ on www.st.com: - https://www.st.com/en/microcontrollers/stm32l072cz.html - -.. _STM32L0x2 reference manual: - https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_lsn50/dragino_lsn50_defconfig b/boards/arm/dragino_lsn50/dragino_lsn50_defconfig deleted file mode 100644 index 7b6c7e6409d157..00000000000000 --- a/boards/arm/dragino_lsn50/dragino_lsn50_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L072XX=y -CONFIG_BOARD_DRAGINO_LSN50=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_nbsn95/Kconfig.board b/boards/arm/dragino_nbsn95/Kconfig.board deleted file mode 100644 index e308ae65287542..00000000000000 --- a/boards/arm/dragino_nbsn95/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Dragino NBSN95 NB-IoT Sensor Node board configuration - -# Copyright (c) 2021 Next Big Thing AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_DRAGINO_NBSN95 - bool "Dragino NBSN95 Sensor Node" - depends on SOC_STM32L072XX diff --git a/boards/arm/dragino_nbsn95/Kconfig.defconfig b/boards/arm/dragino_nbsn95/Kconfig.defconfig deleted file mode 100644 index 0dbadb732d0e4b..00000000000000 --- a/boards/arm/dragino_nbsn95/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Dragino NBSN95 NB-IoT Sensor Node board configuration - -# Copyright (c) 2021 Next Big Thing AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_DRAGINO_NBSN95 - -config BOARD - default "dragino_nbsn95" - -endif # BOARD_DRAGINO_NBSN95 diff --git a/boards/arm/dragino_nbsn95/doc/index.rst b/boards/arm/dragino_nbsn95/doc/index.rst deleted file mode 100644 index ca0b3d8cc1d31d..00000000000000 --- a/boards/arm/dragino_nbsn95/doc/index.rst +++ /dev/null @@ -1,193 +0,0 @@ -.. _dragino_nbsn95_board: - -Dragino NBSN95 NB-IoT Sensor Node -################################# - -Overview -******** - -The Dragino NBSN95 NB-IoT Sensor Node for IoT allows users to develop -applications with NB-IoT connectivity via the Quectel BC95-G. -Dragino NBSN95 enables a wide diversity of applications by exploiting -low-power communication, ARM |reg| Cortex |reg|-M0 core-based -STM32L0 Series features. - -This kit provides: - -- STM32L072CZ MCU -- Quectel BC95-G NB-IoT -- Expansion connectors: - - PMOD -- Li/SOCI2 Unchargable Battery -- GPIOs exposed via screw terminals on the carrier board -- Housing - -.. image:: img/dragino_nbsn95.jpg - :align: center - :alt: Dragino NBSN95 - -More information about the board can be found at the `Dragino NBSN95 website`_. - -Hardware -******** - -The STM32L072CZ SoC provides the following hardware IPs: - -- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz -- Clock Sources: - - - 1 to 32 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 37 kHz RC ( |plusminus| 5%) - - Internal multispeed low-power 65 kHz to 4.2 MHz RC -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 2x 16-bit with up to 4 channels - - 2x 16-bit with up to 2 channels - - 1x 16-bit ultra-low-power timer - - 1x SysTick - - 1x RTC - - 2x 16-bit basic for DAC - - 2x watchdogs (independent/window) -- Up to 84 fast I/Os, most 5 V-tolerant. -- Memories - - - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 20 KB of SRAM - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 1.14 MSPS - - 2x 12-bit DAC - - 2x ultra-low-power comparators -- 11x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 6x SPIs (4x SPIs with the Quad SPI) -- 7-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L072CZ can be found here: - - - `STM32L072CZ on www.st.com`_ - - `STM32L0x2 reference manual`_ - -Supported Features -================== - -The Zephyr Dragino NBSN95 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig`` - - -Connections and IOs -=================== - -Dragino NBSN95 Board has GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- - -For detailed information about available pins please refer to `Dragino NBSN95 website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 - -System Clock ------------- - -Dragino NBSN95 System Clock is at 32MHz, - -Serial Port ------------ - -Dragino NBSN95 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``dragino_nbsn95`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Dragino NBSN95 board requires an external debugger. - -Flashing an application to Dragino NBSN95 ------------------------------------------ - -Here is an example for the :ref:`hello_world` application. - -Connect the Dragino NBSN95 to a STLinkV2 to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_nbsn95 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! dragino_nbsn95 - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: dragino_nbsn95 - :maybe-skip-config: - :goals: debug - -.. _Dragino NBSN95 website: - https://www.dragino.com/products/nb-iot/item/163-nbsn95.html - -.. _STM32L072CZ on www.st.com: - https://www.st.com/en/microcontrollers/stm32l072cz.html - -.. _STM32L0x2 reference manual: - https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig b/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig deleted file mode 100644 index 20b5025cc578dc..00000000000000 --- a/boards/arm/dragino_nbsn95/dragino_nbsn95_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L072XX=y -CONFIG_BOARD_DRAGINO_NBSN95=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.board b/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.board deleted file mode 100644 index 5c69a63bb09257..00000000000000 --- a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# EBYTE-TBB board configuration - -# Copyright (c) 2021 Michal Morsisko -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EBYTE_E73_TBB_NRF52832 - bool "EBYTE E73-TBB NRF52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.defconfig b/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.defconfig deleted file mode 100644 index 3638e0b0b4b48c..00000000000000 --- a/boards/arm/ebyte_e73_tbb_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# EBYTE E73-TBB NRF52832 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# Copyright (c) 2021 Michal Morsisko -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EBYTE_E73_TBB_NRF52832 - -config BOARD - default "ebyte_e73_tbb_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_EBYTE_E73_TBB_NRF52832 diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/doc/index.rst b/boards/arm/ebyte_e73_tbb_nrf52832/doc/index.rst deleted file mode 100644 index 5b0f88f88a61ce..00000000000000 --- a/boards/arm/ebyte_e73_tbb_nrf52832/doc/index.rst +++ /dev/null @@ -1,222 +0,0 @@ -.. _ebyte_e73_tbb_nrf52832: - -EBYTE E73-TBB -############# - -Overview -******** - -The EBYTE E73-TBB hardware provides -support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/ebyte_e73_tbb_nrf52832.jpg - :align: center - :alt: EBYTE E73-TBB - - EBYTE E73-TBB (Credit: EBYTE) - -More information about the board can be found at the -`E73-TBB website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -E73-TBB has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. Additionally the board features CH340 USB-UART converter. -It is possible to connect external BT antenna using U.FL socket -and solder NFC antenna using NFC_ANT connector. - -Supported Features -================== - -The ebyte_e73_tbb_nrf52832 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not supported by the Zephyr kernel. -See `E73-TBB website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52832 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.17 -* LED1 (red) = P0.18 - -Push buttons ------------- - -* BUTTON0 = SW1 = P0.14 -* BUTTON1 = SW2 = P0.13 - -External Connectors -------------------- - -P1 Header - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | GND | -+-------+--------------+ -| 2 | 3.3V | -+-------+--------------+ -| 3 | P0.04 | -+-------+--------------+ -| 4 | P0.03 | -+-------+--------------+ -| 5 | P0.02 | -+-------+--------------+ -| 6 | P0.31 | -+-------+--------------+ -| 7 | P0.30 | -+-------+--------------+ -| 8 | P0.29 | -+-------+--------------+ -| 9 | P0.28 | -+-------+--------------+ -| 10 | P0.27 | -+-------+--------------+ -| 11 | P0.26 | -+-------+--------------+ -| 12 | P0.25 | -+-------+--------------+ - -P2 Header - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | P0.24 | -+-------+--------------+ -| 2 | P0.23 | -+-------+--------------+ -| 3 | P0.22 | -+-------+--------------+ -| 4 | SWDIO | -+-------+--------------+ -| 5 | SWDCLK | -+-------+--------------+ -| 6 | P0.21/RST | -+-------+--------------+ -| 7 | P0.20 | -+-------+--------------+ -| 8 | P0.19 | -+-------+--------------+ -| 9 | P0.16 | -+-------+--------------+ -| 10 | P0.15 | -+-------+--------------+ -| 11 | P0.12 | -+-------+--------------+ -| 12 | P0.11 | -+-------+--------------+ - -NFC_ANT - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | P0.10 | -+-------+--------------+ -| 2 | P0.09 | -+-------+--------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. -To flash the board connect pins: SWDIO, SWDCLK, RST, GND from E73-TBB -to corresponding pins on your J-Link device, then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ebyte_e73_tbb_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic chips with a -Segger IC. - - -Testing the LEDs and buttons in the E73-TBB -******************************************* - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - :zephyr:code-sample:`blinky` - :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _E73-TBB website: https://www.ebyte.com/en/product-view-news.html?id=889 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/efm32gg_sltb009a/Kconfig.board b/boards/arm/efm32gg_sltb009a/Kconfig.board deleted file mode 100644 index ae0968a19936dd..00000000000000 --- a/boards/arm/efm32gg_sltb009a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32GG SLTB009A board configuration -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_SLTB009A - bool "SiLabs EFM32GG-SLTB009A (Giant Gecko 12)" - depends on SOC_SERIES_EFM32GG12B - select SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/boards/arm/efm32gg_sltb009a/Kconfig.defconfig b/boards/arm/efm32gg_sltb009a/Kconfig.defconfig deleted file mode 100644 index 055b4925e782ec..00000000000000 --- a/boards/arm/efm32gg_sltb009a/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# EFM32GG SLTB009A default board configuration -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_SLTB009A - -config BOARD - string - default "efm32gg_sltb009a" - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -endif # BOARD_EFM32GG_SLTB009A diff --git a/boards/arm/efm32gg_sltb009a/doc/index.rst b/boards/arm/efm32gg_sltb009a/doc/index.rst deleted file mode 100644 index a3f54c6502556b..00000000000000 --- a/boards/arm/efm32gg_sltb009a/doc/index.rst +++ /dev/null @@ -1,167 +0,0 @@ -.. _efm32gg_sltb009a: - -EFM32GG12 Thunderboard Kit -########################## - -Overview -******** - -The EFM32GG12 Thunderboard Kit (SLTB009A) is an evaluation platform for the EFM32GG12 GiantGecko Microcontroller, -featuring an ARM Cortex-M4 with FPU, 1024kB flash, and 192kB RAM. - -.. figure:: efm32gg12-thunderboard-kit.jpg - :align: center - :alt: SLTB009A - - SLTB009A (Credit: Silicon Labs) - -Hardware -******** - -- PDM stereo microphones -- USB connectivity -- On-board Segger J-Link USB debugger -- 2 user buttons and 2 LEDs -- USB C connector - -For more information about the WGM160P and SLTB009A board: - -- `SLTB009A Website`_ -- `SLTB009A User Guide`_ -- `EFM32GG12 Datasheet`_ -- `EFM32GG12 Reference Manual`_ - -Supported Features -================== - -The efm32gg_sltb009a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig`` - - -Connections and IOs -=================== - -The EFM32GG12 MCU has six GPIO controllers (PORTA to PORTF), all of which are -currently enabled for the SLTB009A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PE12 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PA13 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PD5 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PD8 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | -+-------+-------------+-------------------------------------+ -| PC0 | I2C_SDA | SENSOR_I2C_SDA I2C0_SDA #1 | -+-------+-------------+-------------------------------------+ -| PC1 | I2C_SCL | SENSOR_I2C_SCL I2C0_SCL #1 | -+-------+-------------+-------------------------------------+ -| PC4 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | -+-------+-------------+-------------------------------------+ -| PC5 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG12 MCU is configured to work at 72 MHz. - -Serial Port -=========== - -The EFM32GG12 SoC has five USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The SLTB009A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to SLTB009A --------------------------------------- - -Connect the SLTB009A to your host computer using the USB port. - -Here is an example to build and flash the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_stb009a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_sltb009a - -.. _SLTB009A Website: - https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit - -.. _SLTB009A User Guide: - https://www.silabs.com/documents/public/user-guides/ug371-sltb009a-user-guide.pdf - -.. _EFM32GG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg12-datasheet.pdf - -.. _EFM32GG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_slwstk6121a/Kconfig.board b/boards/arm/efm32gg_slwstk6121a/Kconfig.board deleted file mode 100644 index e15929d5a0a808..00000000000000 --- a/boards/arm/efm32gg_slwstk6121a/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# EFM32GG SLWSTK6121A board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# Copyright (c) 2020 Thorvald Natvig -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_SLWSTK6121A - bool "SiLabs EFM32GG-SLWSTK6121A (WGM160P)" - depends on SOC_SERIES_EFM32GG11B - select SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/boards/arm/efm32gg_slwstk6121a/Kconfig.defconfig b/boards/arm/efm32gg_slwstk6121a/Kconfig.defconfig deleted file mode 100644 index 28139ff4b1ac9f..00000000000000 --- a/boards/arm/efm32gg_slwstk6121a/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# EFM32GG SLWSTK6121A default board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# Copyright (c) 2020 Thorvald Natvig -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_SLWSTK6121A - -config BOARD - string - default "efm32gg_slwstk6121a" - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_EFM32GG_SLWSTK6121A diff --git a/boards/arm/efm32gg_slwstk6121a/doc/index.rst b/boards/arm/efm32gg_slwstk6121a/doc/index.rst deleted file mode 100644 index be1f25efdaa786..00000000000000 --- a/boards/arm/efm32gg_slwstk6121a/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _efm32gg_slwstk6121a: - -WGM160P Starter Kit -################### - -Overview -******** - -The WGM160P Starter Kit SLWSTK6121A comes with the BRD4321A radio board. -This radio boards contains a WGM160P module, which combines the WF200 Wi-Fi -transceiver with an EFM32GG11 microcontroller. - -.. figure:: wgm160p-starter-kit.jpg - :align: center - :alt: SLWSTK6121A - - SLWSTK6121A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel color Memory-LCD -- 2 user buttons and 2 LEDs -- Si7021 Humidity and Temperature Sensor -- On-board Segger J-Link USB and Ethernet debugger -- 10/100Base-TX ethernet PHY and RJ-45 jack (on included expansion board) -- MicroSD card slot -- USB Micro-AB connector - -For more information about the WGM160P and SLWSTK6121A board: - -- `WGM160P Website`_ -- `WGM160P Datasheet`_ -- `SLWSTK6121A Website`_ -- `SLWSTK6121A User Guide`_ -- `EFM32GG11 Datasheet`_ -- `EFM32GG11 Reference Manual`_ -- `WF200 Datasheet`_ - -Supported Features -================== - -The efm32gg_slwstk6121a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig`` - -Other hardware features, including the WF200 WiFi transceiver, are -currently not supported by the port. - -Connections and IOs -=================== - -The WGM160P's EFM32GG11 SoC has six GPIO controllers (PORTA to PORTF), all of which are -currently enabled for the SLWSTK6121A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PA4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PD6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PD8 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | -+-------+-------------+-------------------------------------+ -| PB11 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | -+-------+-------------+-------------------------------------+ -| PB12 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32GG11 SoC has four USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The SLWSTK6121A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to SLWSTK6121A --------------------------------------- - -Connect the SLWSTK6121A to your host computer using the USB port. - -Here is an example to build and flash the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_slwstk6121a - :goals: flash - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_slwstk6121a - -.. _WGM160P Website: - https://www.silabs.com/wireless/wi-fi/wfm160-series-1-modules - -.. _WGM160P Datasheet: - https://www.silabs.com/documents/public/data-sheets/wgm160p-datasheet.pdf - -.. _SLWSTK6121A Website: - https://www.silabs.com/development-tools/wireless/wi-fi/wgm160p-wifi-module-starter-kit - -.. _SLWSTK6121A User Guide: - https://www.silabs.com/documents/public/user-guides/ug351-brd4321a-user-guide.pdf - -.. _EFM32GG11 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf - -.. _EFM32GG11 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf - -.. _WF200 Datasheet: - https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_stk3701a/Kconfig.board b/boards/arm/efm32gg_stk3701a/Kconfig.board deleted file mode 100644 index cbab0c8d3ff877..00000000000000 --- a/boards/arm/efm32gg_stk3701a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32GG STK3701A board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32GG_STK3701A - bool "SiLabs EFM32GG-STK3701A (Giant Gecko 11)" - depends on SOC_SERIES_EFM32GG11B - select SOC_PART_NUMBER_EFM32GG11B820F2048GL192 diff --git a/boards/arm/efm32gg_stk3701a/Kconfig.defconfig b/boards/arm/efm32gg_stk3701a/Kconfig.defconfig deleted file mode 100644 index 620efea317a0e7..00000000000000 --- a/boards/arm/efm32gg_stk3701a/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# EFM32GG STK3701A default board configuration -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32GG_STK3701A - -config BOARD - string - default "efm32gg_stk3701a" - -config CMU_HFXO_FREQ - default 50000000 - -config CMU_HFRCO_FREQ - default 72000000 - -config CMU_LFXO_FREQ - default 32768 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_EFM32GG_STK3701A diff --git a/boards/arm/efm32gg_stk3701a/doc/index.rst b/boards/arm/efm32gg_stk3701a/doc/index.rst deleted file mode 100644 index 50b3d9cd7850a5..00000000000000 --- a/boards/arm/efm32gg_stk3701a/doc/index.rst +++ /dev/null @@ -1,201 +0,0 @@ -.. _efm32gg_stk3701a: - -EFM32 Giant Gecko GG11 Starter Kit -################################## - -Overview -******** - -The EFM32 Giant Gecko Starter Kit EFM32GG-STK3701A contains an MCU from the -EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent -low power capabilities. - -.. figure:: efm32gg_stk3701a.jpg - :align: center - :alt: EFM32GG-SLSTK3701A - - EFM32GG-SLSTK3701A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel color Memory-LCD -- 2 user buttons, 2 LEDs and a touch slider -- Relative humidity, magnetic Hall Effect and inductive-capacitive metal sensor -- USB interface for Host/Device/OTG -- 32 Mb Quad-SPI Flash memory -- SD card slot -- RJ-45 Ethernet jack -- 2 digital microphones -- On-board Segger J-Link USB debugger - -For more information about the EFM32GG11 SoC and EFM32GG-STK3701A board: - -- `EFM32GG Series 1 Website`_ -- `EFM32GG11 Datasheet`_ -- `EFM32GG11 Reference Manual`_ -- `EFM32GG-STK3701A Website`_ -- `EFM32GG-STK3701A User Guide`_ -- `EFM32GG-STK3701A Schematics`_ - -Supported Features -================== - -The efm32gg_stk3701a board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32GG11 SoC has nine GPIO controllers (PORTA to PORTI), all of which are -currently enabled for the EFM32GG-STK3701A board. - -In the following table, the column **Name** contains pin names. For example, PE1 -means pin number 1 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PH10 | GPIO | LED0 red | -+-------+-------------+-------------------------------------+ -| PH11 | GPIO | LED0 green | -+-------+-------------+-------------------------------------+ -| PH12 | GPIO | LED0 blue | -+-------+-------------+-------------------------------------+ -| PH13 | GPIO | LED1 red | -+-------+-------------+-------------------------------------+ -| PH14 | GPIO | LED1 green | -+-------+-------------+-------------------------------------+ -| PH15 | GPIO | LED1 blue | -+-------+-------------+-------------------------------------+ -| PC8 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PC9 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PE1 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PH4 | UART_TX | UART TX Console VCOM_TX US0_TX #4 | -+-------+-------------+-------------------------------------+ -| PH5 | UART_RX | UART RX Console VCOM_RX US0_RX #4 | -+-------+-------------+-------------------------------------+ -| PI4 | I2C_SDA | SENSOR_I2C_SDA I2C2_SDA #7 | -+-------+-------------+-------------------------------------+ -| PI5 | I2C_SCL | SENSOR_I2C_SCL I2C2_SCL #7 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32GG11 SoC has six USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART4 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32GG-STK3701A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32GG-STK3701A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32gg_stk3701a - :goals: build - -Connect the EFM32GG-STK3701A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3701A) and -a USB Serial Port. Copy the generated zephyr.bin to the STK3701A drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efm32gg_stk3701a - - -.. _EFM32GG-STK3701A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-giant-gecko-gg11-starter-kit - -.. _EFM32GG-STK3701A User Guide: - https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf - -.. _EFM32GG-STK3701A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2204A-B00-schematic.pdf - -.. _EFM32GG Series 1 Website: - https://www.silabs.com/products/mcu/32-bit/efm32-giant-gecko-s1 - -.. _EFM32GG11 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf - -.. _EFM32GG11 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32hg_slstk3400a/Kconfig.board b/boards/arm/efm32hg_slstk3400a/Kconfig.board deleted file mode 100644 index eb3ca8af2cc597..00000000000000 --- a/boards/arm/efm32hg_slstk3400a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32HG SLSTK3400A board - -# Copyright (c) 2018, Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32HG_SLSTK3400A - bool "SiLabs EFM32HG-SLSTK3400A (Happy Gecko)" - depends on SOC_SERIES_EFM32HG - select SOC_PART_NUMBER_EFM32HG322F64 diff --git a/boards/arm/efm32hg_slstk3400a/Kconfig.defconfig b/boards/arm/efm32hg_slstk3400a/Kconfig.defconfig deleted file mode 100644 index 08b75e0857ffc4..00000000000000 --- a/boards/arm/efm32hg_slstk3400a/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFM32HG SLSTK3400A board - -# Copyright (c) 2018, Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32HG_SLSTK3400A - -config BOARD - default "efm32hg_slstk3400a" - -config CMU_HFXO_FREQ - default 24000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32HG_SLSTK3400A diff --git a/boards/arm/efm32hg_slstk3400a/doc/index.rst b/boards/arm/efm32hg_slstk3400a/doc/index.rst deleted file mode 100644 index 9db17c59acf13b..00000000000000 --- a/boards/arm/efm32hg_slstk3400a/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _efm32hg_slstk3400a: - -EFM32HG-SLSTK3400A -################## - -Overview -******** - -The EFM32 Happy Gecko Starter Kit EFM32HG-SLSTK3400A contains a MCU from the -EFM32HG family built on ARM® Cortex®-M0+ processor with excellent low -power capabilities. - -.. figure:: efm32hg_slstk3400a.jpg - :align: center - :alt: EFM32HG-SLSTK3400A - - EFM32HG-SLSTK3400A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring system for precise current tracking -- Real-time energy and power profiling -- ARM Cortex M0+ with 64 kB Flash and 8 kB RAM -- 128 X 128 pixel Memory LCD -- 2 user buttons, 2 user LEDs and 2 touch buttons -- 20 pin expansion header -- Silicon Labs Si7021 Relative Humidity/Temperature sensor -- USB device interface -- Integrated SEGGER J-Link USB debugger/emulator with debug out functionality - - -See these documents for more information - -- `EFM32HG Website`_ -- `EFM32HG Datasheet`_ -- `EFM32HG Reference Manual`_ -- `EFM32HG-SLSTK3400A Website`_ -- `EFM32HG-SLSTK3400A User Guide`_ -- `EFM32HG-SLSTK3400A Schematics`_ - -Supported Features -================== - -The efm32hg_slstk3400 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32HG SoC has six GPIO controllers (PORTA to PORTF), but only three are -currently enabled (PORTB, PORTE and PORTF) for the EFM32HG-SLSTK3400A board. - -In the following table, the column Name contains Pin names. For example, PF4 -means Pin number 4 on PORTF, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PC9 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PC10 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PF2 | USART0_TX | USART Console EFM_BC_TX U0_TX #4 | -+-------+-------------+-------------------------------------+ -| PA9 | USART0_RX | USART Console EFM_BC_RX U0_RX #4 | -+-------+-------------+-------------------------------------+ - -System Clock -============ - -The EFM32HG SoC is configured to use the 24 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32HG SoC has two USARTs, two UARTs and two Low Energy UARTs (LEUART). -USART1 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32HG-SLSTK3400 includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFM32-SLSTK3400A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32hg_slstk3400a - :goals: build - -Connect the EFM32HG-SLSTK3400A to your host computer using the USB port and -you should see a USB connection that exposes a mass storage device (STK3400) -and a USB Serial Port. Copy the generated ``zephyr.bin`` in the STK3400 drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you will see this message written to the serial port: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32HG-SLSTK3400A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-happy-gecko-starter-kit - -.. _EFM32HG-SLSTK3400A User Guide: - https://www.silabs.com/documents/public/user-guides/ug255-stk3400-user-guide.pdf - -.. _EFM32HG-SLSTK3400A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2012A-B01-schematic.pdf - -.. _EFM32HG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-happy-gecko - -.. _EFM32HG Datasheet: - https://www.silabs.com/documents/public/data-sheets/EFM32HG322.pdf - -.. _EFM32HG Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/EFM32HG-RM.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3401a/Kconfig.board b/boards/arm/efm32pg_stk3401a/Kconfig.board deleted file mode 100644 index 8c2222a9871627..00000000000000 --- a/boards/arm/efm32pg_stk3401a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32PG STK3401A board - -# Copyright (c) 2020, Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32PG_STK3401A - bool "SiLabs EFM32PG-STK3401A (Pearl Gecko)" - depends on SOC_SERIES_EFM32PG1B - select SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/boards/arm/efm32pg_stk3401a/Kconfig.defconfig b/boards/arm/efm32pg_stk3401a/Kconfig.defconfig deleted file mode 100644 index 33fe600d96f0ac..00000000000000 --- a/boards/arm/efm32pg_stk3401a/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFM32PG STK3401A board - -# Copyright (c) 2020, Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32PG_STK3401A - -config BOARD - default "efm32pg_stk3401a" if BOARD_EFM32PG_STK3401A - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32PG_STK3401A diff --git a/boards/arm/efm32pg_stk3401a/doc/index.rst b/boards/arm/efm32pg_stk3401a/doc/index.rst deleted file mode 100644 index 4d646060f257bb..00000000000000 --- a/boards/arm/efm32pg_stk3401a/doc/index.rst +++ /dev/null @@ -1,189 +0,0 @@ -.. _efm32pg_stk3401a: - -EFM32 Pearl Gecko Starter Kit -############################# - -Overview -******** - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3401A contains an MCU from the -EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32pg_stk3401a.jpg - :align: center - :alt: EFM32PG-SLSTK3401A - - EFM32PG-SLSTK3401A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel Memory-LCD -- 2 user buttons, 2 LEDs and 2 capacitive buttons -- Humidity and temperature sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32PG SoC and EFM32PG-STK3401A board: - -- `EFM32PG Website`_ -- `EFM32PG1 Datasheet`_ -- `EFM32PG1 Reference Manual`_ -- `EFM32PG-STK3401A Website`_ -- `EFM32PG-STK3401A User Guide`_ - -Supported Features -================== - -The efm32pg_stk3401a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32PG1 SoC has five GPIO controllers (PORTA to PORTD and PORTF) and -all are enabled for the EFM32PG-STK3401A board. - -In the following table, the column **Name** contains pin names. For example, PF4 -means pin number 4 on PORTF, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PF6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+-------+-------------+-------------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+-------+-------------+-------------------------------------+ -| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | -+-------+-------------+-------------------------------------+ -| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | -+-------+-------------+-------------------------------------+ -| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | -+-------+-------------+-------------------------------------+ -| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32PG SoC is configured to use the 40 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32PG SoC has two USARTs and one Low Energy UART (LEUART). - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32PG-STK3401A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32PG-STK3401A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32pg_stk3401a - :goals: build - -Connect the EFM32PG-STK3401A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3401A). -Copy the generated zephyr.bin to the STK3401A drive. - -Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the -expansion header. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32PG-STK3401A Website: - https://www.silabs.com/development-tools/mcu/32-bit/efm32pg1-starter-kit - -.. _EFM32PG-STK3401A User Guide: - https://www.silabs.com/documents/public/user-guides/ug154-stk3401-user-guide.pdf - -.. _EFM32PG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko - -.. _EFM32PG1 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32pg1-datasheet.pdf - -.. _EFM32PG1 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32pg1-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3402a/Kconfig.board b/boards/arm/efm32pg_stk3402a/Kconfig.board deleted file mode 100644 index dfb65d480862ec..00000000000000 --- a/boards/arm/efm32pg_stk3402a/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# EFM32PG STK3402A board - -# Copyright (c) 2018, Christian Taedcke -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32PG_STK3402A - bool "SiLabs EFM32PG-STK3402A (Pearl Gecko)" - depends on SOC_SERIES_EFM32PG12B - select SOC_PART_NUMBER_EFM32PG12B500F1024GL125 - -config BOARD_EFM32PG_STK3402A_JG - bool "SiLabs EFM32PG-STK3402A (Jade Gecko)" - depends on SOC_SERIES_EFM32JG12B - select SOC_PART_NUMBER_EFM32JG12B500F1024GL125 diff --git a/boards/arm/efm32pg_stk3402a/Kconfig.defconfig b/boards/arm/efm32pg_stk3402a/Kconfig.defconfig deleted file mode 100644 index 5f298e584c39ba..00000000000000 --- a/boards/arm/efm32pg_stk3402a/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# EFM32PG STK3402A board - -# Copyright (c) 2018, Christian Taedcke -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32PG_STK3402A || BOARD_EFM32PG_STK3402A_JG - -config BOARD - default "efm32pg_stk3402a" if BOARD_EFM32PG_STK3402A - default "efm32pg_stk3402a_jg" if BOARD_EFM32PG_STK3402A_JG - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32PG_STK3402A || BOARD_EFM32PG_STK3402A_JG diff --git a/boards/arm/efm32pg_stk3402a/doc/index.rst b/boards/arm/efm32pg_stk3402a/doc/index.rst deleted file mode 100644 index ca7ffe8471eb88..00000000000000 --- a/boards/arm/efm32pg_stk3402a/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _efm32pg_stk3402a: - -EFM32 Pearl Gecko Starter Kit -############################# - -Overview -******** - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A contains an MCU from the -EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32pg_stk3402a.jpg - :align: center - :alt: EFM32PG-SLSTK3402A - - EFM32PG-SLSTK3402A (image courtesy of Silicon Labs) - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- Ultra low power 128x128 pixel Memory-LCD -- 2 user buttons, 2 LEDs and a touch slider -- Humidity, temperature, and inductive-capacitive metal sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32PG SoC and EFM32PG-STK3402A board: - -- `EFM32PG Website`_ -- `EFM32PG12 Datasheet`_ -- `EFM32PG12 Reference Manual`_ -- `EFM32PG-STK3402A Website`_ -- `EFM32PG-STK3402A User Guide`_ -- `EFM32PG-STK3402A Schematics`_ - -Supported Features -================== - -The efm32pg_stk3402a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig`` - -The default configuration when building for this EFM32JG12B SoC can be found in -another defconfig file: - - ``boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig_jg`` - -Other hardware features are currently not supported by the port. - -EFM32 Jade Gecko SoC --------------------- - -The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A can also be used to evaluate -the EFM32 Jade Gecko SoC (EFM32JG12B). The only difference between the Pearl -Gecko and the Jade Gecko is their core. The Pearl Gecko contains an ARM® -Cortex®-M4F core, and the Jade Gecko an ARM® Cortex®-M3 core. Other features -such as memory and peripherals are the same. - -Code that is built for the Jade Gecko also runs on an equivalent Pearl Gecko. - -To build firmware for the Jade Gecko and run it on the EFM32 Pearl Gecko Starter -Kit, use the board ``efm32pg_stk3402a_jg`` instead of ``efm32pg_stk3402a``. - -Connections and IOs -=================== - -The EFM32PG12 SoC has twelve GPIO controllers (PORTA to PORTL), but only four -are currently enabled (PORTA, PORTB, PORTD and PORTF) for the EFM32PG-STK3402A -board. - -In the following table, the column **Name** contains pin names. For example, PE2 -means pin number 2 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PF4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PF5 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PF6 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PA5 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+-------+-------------+-------------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+-------+-------------+-------------------------------------+ -| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | -+-------+-------------+-------------------------------------+ -| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | -+-------+-------------+-------------------------------------+ -| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | -+-------+-------------+-------------------------------------+ -| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | -+-------+-------------+-------------------------------------+ - - -System Clock -============ - -The EFM32PG SoC is configured to use the 40 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32PG SoC has four USARTs and one Low Energy UART (LEUART). - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32PG-STK3402A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a mass storage device and a - USB serial port. -- A serial flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB serial port. - -Flashing an application to EFM32PG-STK3402A -------------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32pg_stk3402a - :goals: build - -Connect the EFM32PG-STK3402A to your host computer using the USB port and you -should see a USB connection which exposes a mass storage device(STK3402A). -Copy the generated zephyr.bin to the STK3402A drive. - -Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the -expansion header. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32PG-STK3402A Website: - https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-pearl-gecko-pg12-starter-kit - -.. _EFM32PG-STK3402A User Guide: - https://www.silabs.com/documents/public/user-guides/ug257-stk3402-usersguide.pdf - -.. _EFM32PG-STK3402A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD2501A-A01-schematic.pdf - -.. _EFM32PG Website: - https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko - -.. _EFM32PG12 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efm32pg12-datasheet.pdf - -.. _EFM32PG12 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efm32pg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.yaml b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.yaml deleted file mode 100644 index ebfe95c91bacbd..00000000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: efm32pg_stk3402a -name: EFM32PG-STK3402A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - nvs - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig deleted file mode 100644 index d3805477749ef8..00000000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFM32PG12B=y -CONFIG_BOARD_EFM32PG_STK3402A=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 -CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.yaml b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.yaml deleted file mode 100644 index 8d7e590e393faf..00000000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: efm32pg_stk3402a_jg -name: EFM32PG-STK3402A-JG -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - gpio - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg_defconfig b/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg_defconfig deleted file mode 100644 index 36c92f45d2e011..00000000000000 --- a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFM32JG12B=y -CONFIG_BOARD_EFM32PG_STK3402A_JG=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 -CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/arm/efm32wg_stk3800/Kconfig.board b/boards/arm/efm32wg_stk3800/Kconfig.board deleted file mode 100644 index d75311cbe146b0..00000000000000 --- a/boards/arm/efm32wg_stk3800/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFM32WG STK3800 board - -# Copyright (c) 2017, Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFM32WG_STK3800 - bool "SiLabs EFM32WG-STK3800 (Wonder Gecko)" - depends on SOC_SERIES_EFM32WG - select SOC_PART_NUMBER_EFM32WG990F256 diff --git a/boards/arm/efm32wg_stk3800/Kconfig.defconfig b/boards/arm/efm32wg_stk3800/Kconfig.defconfig deleted file mode 100644 index 90450ad0244bd3..00000000000000 --- a/boards/arm/efm32wg_stk3800/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFM32WG STK3800 board - -# Copyright (c) 2017, Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFM32WG_STK3800 - -config BOARD - default "efm32wg_stk3800" - -config CMU_HFXO_FREQ - default 48000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFM32WG_STK3800 diff --git a/boards/arm/efm32wg_stk3800/doc/index.rst b/boards/arm/efm32wg_stk3800/doc/index.rst deleted file mode 100644 index d624619d83fce6..00000000000000 --- a/boards/arm/efm32wg_stk3800/doc/index.rst +++ /dev/null @@ -1,178 +0,0 @@ -.. _efm32wg_stk3800: - -EFM32WG-STK3800 -############### - -Overview -******** - -The EFM32 Wonder Gecko Starter Kit EFM32WG-STK3800 contains a MCU from the -EFM32WG family built on ARM® Cortex®-M4F processor with excellent low -power capabilities. - -.. figure:: efm32wg_stk3800.jpg - :align: center - :alt: EFM32WG-STK3800 - - EFM32WG-STK3800 (image courtesy of Silicon Labs) - - -Hardware -******** - -- Advanced Energy Monitoring provides real-time information about the energy - consumption of an application or prototype design. -- 32MByte parallel NAND Flash -- 160 segment Energy Micro LCD -- 2 user buttons, 2 LEDs and a touch slider -- Ambient Light Sensor and Inductive-capacitive metal sensor -- On-board Segger J-Link USB debugger - -For more information about the EFM32WG SoC and EFM32WG-STK3800 board: - -- `EFM32WG Website`_ -- `EFM32WG Datasheet`_ -- `EFM32WG Reference Manual`_ -- `EFM32WG-STK3800 Website`_ -- `EFM32WG-STK3800 User Guide`_ -- `EFM32WG-STK3800 Schematics`_ - -Supported Features -================== - -The efm32wg_stk3800 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig`` - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFM32WG SoC has six gpio controllers (PORTA to PORTF), but only three are -currently enabled (PORTB, PORTE and PORTF) for the EFM32WG-STK3800 board. - -In the following table, the column Name contains Pin names. For example, PE2 -means Pin number 2 on PORTE, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PE2 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PE3 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PB9 | GPIO | Push Button PB0 | -+-------+-------------+-------------------------------------+ -| PB10 | GPIO | Push Button PB1 | -+-------+-------------+-------------------------------------+ -| PF7 | GPIO | Board Controller Enable | -| | | EFM_BC_EN | -+-------+-------------+-------------------------------------+ -| PE0 | UART0_TX | UART Console EFM_BC_TX U0_TX #1 | -+-------+-------------+-------------------------------------+ -| PE1 | UART0_RX | UART Console EFM_BC_RX U0_RX #1 | -+-------+-------------+-------------------------------------+ - -System Clock -============ - -The EFM32WG SoC is configured to use the 48 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFM32WG SoC has three USARTs, two UARTs and two Low Energy UARTs (LEUART). -UART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFM32WG-STK3800 includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFM32-STK3800 ----------------------------------------- - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efm32wg_stk3800 - :goals: build - -Connect the EFM32WG-STK3800 to your host computer using the USB port and you -should see a USB connection which exposes a Mass Storage (STK3800) and a -USB Serial Port. Copy the generated zephyr.bin in the STK3800 drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _EFM32WG-STK3800 Website: - http://www.silabs.com/products/development-tools/mcu/32-bit/efm32-wonder-gecko-starter-kit - -.. _EFM32WG-STK3800 User Guide: - http://www.silabs.com/documents/public/user-guides/efm32wg-stk3800-ug.pdf - -.. _EFM32WG-STK3800 Schematics: - http://www.silabs.com/documents/public/schematic-files/BRD2400A_A00.pdf - -.. _EFM32WG Website: - http://www.silabs.com/products/mcu/32-bit/efm32-wonder-gecko - -.. _EFM32WG Datasheet: - http://www.silabs.com/documents/public/data-sheets/EFM32WG990.pdf - -.. _EFM32WG Reference Manual: - http://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32_radio/Kconfig b/boards/arm/efr32_radio/Kconfig deleted file mode 100644 index 9de639f91bd716..00000000000000 --- a/boards/arm/efr32_radio/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# EFR32 radio board configuration - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32_RADIO - bool diff --git a/boards/arm/efr32_radio/Kconfig.board b/boards/arm/efr32_radio/Kconfig.board deleted file mode 100644 index bbae554ae698f4..00000000000000 --- a/boards/arm/efr32_radio/Kconfig.board +++ /dev/null @@ -1,48 +0,0 @@ -# EFR32BG13 BRD4104A / EFR32MG21 BRD4180A / -# EFR32FG1P BRD4250B / EFR32FG13P BRD4255A board - -# Copyright (c) 2020 Piotr Mienkowski -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32_RADIO_BRD4104A - bool "Silicon Labs BRD4104A (Blue Gecko Radio Board)" - depends on SOC_SERIES_EFR32BG13P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32BG13P632F512GM48 - -config BOARD_EFR32_RADIO_BRD4170A - bool "Silicon Labs BRD4170A (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG12P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG12P433F1024GM68 - -config BOARD_EFR32_RADIO_BRD4161A - bool "Silicon Labs BRD4161A (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG12P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG12P432F1024GL125 - -config BOARD_EFR32_RADIO_BRD4250B - bool "Silicon Labs BRD4250B (Flex Gecko Radio Board)" - depends on SOC_SERIES_EFR32FG1P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32FG1P133F256GM48 - -config BOARD_EFR32_RADIO_BRD4180A - bool "Silicon Labs BRD4180A (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG21 - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG21A020F1024IM32 - -config BOARD_EFR32_RADIO_BRD4187C - bool "Silicon Labs BRD4187C (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG24 - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32MG24B220F1536IM48 - -config BOARD_EFR32_RADIO_BRD4255A - bool "Silicon Labs BRD4255A (Flex Gecko Radio Board)" - depends on SOC_SERIES_EFR32FG13P - select BOARD_EFR32_RADIO - select SOC_PART_NUMBER_EFR32FG13P233F512GM48 diff --git a/boards/arm/efr32_radio/Kconfig.defconfig b/boards/arm/efr32_radio/Kconfig.defconfig deleted file mode 100644 index b91aa627b70612..00000000000000 --- a/boards/arm/efr32_radio/Kconfig.defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# EFR32 radio board - -# Copyright (c) 2020 Piotr Mienkowski -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32_RADIO - -config BOARD - default "efr32_radio_brd4104a" if BOARD_EFR32_RADIO_BRD4104A - default "efr32_radio_brd4170a" if BOARD_EFR32_RADIO_BRD4170A - default "efr32_radio_brd4161a" if BOARD_EFR32_RADIO_BRD4161A - default "efr32_radio_brd4250b" if BOARD_EFR32_RADIO_BRD4250B - default "efr32_radio_brd4180a" if BOARD_EFR32_RADIO_BRD4180A - default "efr32_radio_brd4187c" if BOARD_EFR32_RADIO_BRD4187C - default "efr32_radio_brd4255a" if BOARD_EFR32_RADIO_BRD4255A - -config CMU_HFXO_FREQ - default 39000000 if BOARD_EFR32_RADIO_BRD4187C - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 if BOARD_EFR32_RADIO_BRD4187C - default 0x0 - -config LOG_BACKEND_SWO_FREQ_HZ - default 875000 - depends on LOG_BACKEND_SWO - -if SOC_GECKO_USE_RAIL - -config FPU - default n if SOC_GECKO_SERIES1 - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config MINIMAL_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 3072 if PM - default 2304 - -choice BT_HCI_BUS_TYPE - default BT_SILABS_HCI -endchoice - -endif # BT - -endif # BOARD_EFR32_RADIO diff --git a/boards/arm/efr32_radio/board.cmake b/boards/arm/efr32_radio/board.cmake deleted file mode 100644 index d684946143e729..00000000000000 --- a/boards/arm/efr32_radio/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(openocd) - -if(CONFIG_BOARD_EFR32_RADIO_BRD4104A) -board_runner_args(jlink "--device=EFR32BG13PxxxF512") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4250B) -board_runner_args(jlink "--device=EFR32FG1PxxxF256") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4170A) -board_runner_args(jlink "--device=EFR32MG12PxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4161A) -board_runner_args(jlink "--device=EFR32MG12PxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4180A) -board_runner_args(jlink "--device=EFR32MG21AxxxF1024") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4187C) -board_runner_args(jlink "--device=EFR32MG24BxxxF1536") -elseif(CONFIG_BOARD_EFR32_RADIO_BRD4255A) -board_runner_args(jlink "--device=EFR32FG13PxxxF512") -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/efr32_radio/efr32_radio_brd4104a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4104a.yaml deleted file mode 100644 index 62e253011c7e61..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4104a.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio_brd4104a -name: BRD4104A -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig deleted file mode 100644 index 00991a6e4cd2f8..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG13P=y -CONFIG_BOARD_EFR32_RADIO_BRD4104A=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4161a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4161a.yaml deleted file mode 100644 index 108d6f16c0f711..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4161a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4161a -name: BRD4161A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig deleted file mode 100644 index fbf7cf383256d0..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32MG12P=y -CONFIG_BOARD_EFR32_RADIO_BRD4161A=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4170a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4170a.yaml deleted file mode 100644 index 88ed40893790f3..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4170a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4170a -name: BRD4170A -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig deleted file mode 100644 index 32222b89b31ef7..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32MG12P=y -CONFIG_BOARD_EFR32_RADIO_BRD4170A=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a.dts b/boards/arm/efr32_radio/efr32_radio_brd4180a.dts deleted file mode 100644 index 43f4290ff84297..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4180a.dts +++ /dev/null @@ -1,147 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio_brd4180a-pinctrl.dtsi" - -/ { - model = "Silicon Labs BRD4180A (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32mg21_brd4180a", "silabs,efr32mg21"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiob 0 0>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiob 1 0>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - /* gpio flags need validation */ - gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - /* gpio flags need validation */ - gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <38400000>; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&rtcc0 { - prescaler = <1>; - status = "okay"; -}; - -&gpio { - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <4 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&wdog0 { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 48 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x0000c000>; - read-only; - }; - - /* Reserve 464 kB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x00074000>; - }; - - /* Reserve 464 kB for the application in slot 1 */ - slot1_partition: partition@80000 { - label = "image-1"; - reg = <0x00080000 0x00074000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@f4000 { - label = "image-scratch"; - reg = <0x000f4000 0x00008000>; - }; - - /* Set 16Kb of storage at the end of the 1024Kb of flash */ - storage_partition: partition@fc000 { - label = "storage"; - reg = <0x000fc000 0x00004000>; - }; - - }; -}; diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4180a.yaml deleted file mode 100644 index ea286ce3c65a42..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4180a.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4180a -name: BRD4180A -type: mcu -arch: arm -ram: 96 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig deleted file mode 100644 index 0db69e5d9e1fec..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32MG21=y -CONFIG_BOARD_EFR32_RADIO_BRD4180A=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_PINCTRL=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c.dts b/boards/arm/efr32_radio/efr32_radio_brd4187c.dts deleted file mode 100644 index 6e8703fabbeae3..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4187c.dts +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2023 Fr. Sauter AG - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "efr32_radio_brd4187c-pinctrl.dtsi" - -/ { - model = "Silicon Labs BRD4187C (Mighty Gecko Radio Board)"; - compatible = "silabs,efr32mg24_brd4187c", "silabs,efr32mg24"; - - chosen { - zephyr,console = &usart0; - zephyr,shell-uart = &usart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - sw0 = &button0; - sw1 = &button1; - watchdog0 = &wdog0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>; - label = "LED 0"; - }; - led1: led_1 { - gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; - label = "LED 1"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; - label = "User Push Button 0"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; - label = "User Push Button 1"; - zephyr,code = ; - }; - }; - -}; - -&cpu0 { - clock-frequency = <39000000>; -}; - -&pstate_em3 { - status = "disabled"; -}; - -&usart0 { - current-speed = <115200>; - pinctrl-0 = <&usart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpio { - location-swo = <0>; - status = "okay"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; - - board-controller-enable { - gpio-hog; - gpios = <0 GPIO_ACTIVE_HIGH>; - output-high; - }; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&wdog0 { - status = "okay"; -}; - -&burtc0 { - status = "okay"; -}; - -&stimer0 { - status = "okay"; -}; - -&se { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 48 kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 DT_SIZE_K(48)>; - read-only; - }; - - /* Reserve 720 kB for the application in slot 0 */ - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000c000 0x000B4000>; - }; - - /* Reserve 720 kB for the application in slot 1 */ - slot1_partition: partition@C0000 { - label = "image-1"; - reg = <0x000C0000 0x000B4000>; - }; - - /* Reserve 32 kB for the scratch partition */ - scratch_partition: partition@174000 { - label = "image-scratch"; - reg = <0x00174000 DT_SIZE_K(32)>; - }; - - /* Set 16 kB of storage at the end of the 1536 kB of flash */ - storage_partition: partition@17c000 { - label = "storage"; - reg = <0x0017c000 DT_SIZE_K(16)>; - }; - }; -}; diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c.yaml b/boards/arm/efr32_radio/efr32_radio_brd4187c.yaml deleted file mode 100644 index a5602114a3677f..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4187c.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: efr32_radio_brd4187c -name: BRD4187C -type: mcu -arch: arm -ram: 256 -flash: 1536 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth - - pm - - hwinfo -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig deleted file mode 100644 index 046f8acfaeda9f..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32MG24=y -CONFIG_BOARD_EFR32_RADIO_BRD4187C=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=78000000 -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y -CONFIG_PINCTRL=y - -# Use BURTC as system clock source -CONFIG_GECKO_BURTC_TIMER=y -CONFIG_CMU_BURTCCLK_LFXO=y -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/arm/efr32_radio/efr32_radio_brd4250b.yaml b/boards/arm/efr32_radio/efr32_radio_brd4250b.yaml deleted file mode 100644 index 0d45527eced07e..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4250b.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio_brd4250b -name: BRD4250B -type: mcu -arch: arm -ram: 32 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig deleted file mode 100644 index d9be04bc9cd149..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32FG1P=y -CONFIG_BOARD_EFR32_RADIO_BRD4250B=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4255a.yaml b/boards/arm/efr32_radio/efr32_radio_brd4255a.yaml deleted file mode 100644 index a5b7fc7cb90b3c..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4255a.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: efr32_radio_brd4255a -name: BRD4255A -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - nvs - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: silabs diff --git a/boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig b/boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig deleted file mode 100644 index 8d409047b75768..00000000000000 --- a/boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_EFR32FG13P=y -CONFIG_BOARD_EFR32_RADIO_BRD4255A=y -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 -CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_thunderboard/Kconfig.board b/boards/arm/efr32_thunderboard/Kconfig.board deleted file mode 100644 index de6124d9e49a3e..00000000000000 --- a/boards/arm/efr32_thunderboard/Kconfig.board +++ /dev/null @@ -1,19 +0,0 @@ -# EFR32BG SLTB010A board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32BG22_BRD4184A - bool "SiLabs EFR32BG22-BRD4184A (Thunderboard EFR32BG22)" - depends on SOC_SERIES_EFR32BG22 - select SOC_PART_NUMBER_EFR32BG22C224F512IM40 - -config BOARD_EFR32BG22_BRD4184B - bool "SiLabs EFR32BG22-BRD4184B (Thunderboard EFR32BG22)" - depends on SOC_SERIES_EFR32BG22 - select SOC_PART_NUMBER_EFR32BG22C224F512IM40 - -config BOARD_EFR32BG27_BRD2602A - bool "SiLabs EFR32BG27-BRD2602A (EFR32BG27 +8 dBm Dev Kit Board)" - depends on SOC_SERIES_EFR32BG27 - select SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/boards/arm/efr32_thunderboard/Kconfig.defconfig b/boards/arm/efr32_thunderboard/Kconfig.defconfig deleted file mode 100644 index 71f5800df5ed74..00000000000000 --- a/boards/arm/efr32_thunderboard/Kconfig.defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# Thunderboard-style boards - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32BG22_BRD4184A - -config BOARD - default "efr32bg22_brd4184a" - -endif # BOARD_EFR32BG22_BRD4184A - -if BOARD_EFR32BG22_BRD4184B - -config BOARD - default "efr32bg22_brd4184b" - -endif # BOARD_EFR32BG22_BRD4184B - -if BOARD_EFR32BG27_BRD2602A - -config BOARD - default "efr32bg27_brd2602a" - -endif # BOARD_EFR32BG27_BRD2602A - -config CMU_HFXO_FREQ - default 38400000 - -config CMU_LFXO_FREQ - default 32768 - -if SOC_GECKO_USE_RAIL - -config FPU - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config COMMON_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 3072 if PM - default 2304 - -choice BT_HCI_BUS_TYPE - default BT_SILABS_HCI -endchoice - -endif # BT - -config REGULATOR - default y if SI7210 diff --git a/boards/arm/efr32_thunderboard/board.cmake b/boards/arm/efr32_thunderboard/board.cmake deleted file mode 100644 index cc0f48cee82d41..00000000000000 --- a/boards/arm/efr32_thunderboard/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_EFR32BG22_BRD4184A OR CONFIG_BOARD_EFR32BG22_BRD4184B) -board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) - -elseif(CONFIG_BOARD_EFR32BG27_BRD2602A) -board_runner_args(silabs_commander "--device=EFR32BG27C140F768IM40") -include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) - -endif() diff --git a/boards/arm/efr32mg_sltb004a/Kconfig.board b/boards/arm/efr32mg_sltb004a/Kconfig.board deleted file mode 100644 index 8e884faf35f7c3..00000000000000 --- a/boards/arm/efr32mg_sltb004a/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFR32MG SLTB004A board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32MG_SLTB004A - bool "SiLabs EFR32MG-SLTB004A (Thunderboard Sense 2)" - depends on SOC_SERIES_EFR32MG12P - select SOC_PART_NUMBER_EFR32MG12P332F1024GL125 diff --git a/boards/arm/efr32mg_sltb004a/Kconfig.defconfig b/boards/arm/efr32mg_sltb004a/Kconfig.defconfig deleted file mode 100644 index d8939cda5d636c..00000000000000 --- a/boards/arm/efr32mg_sltb004a/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# EFR32MG SLTB004A board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32MG_SLTB004A - -config BOARD - default "efr32mg_sltb004a" - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -endif # BOARD_EFR32MG_SLTB004A diff --git a/boards/arm/efr32mg_sltb004a/doc/index.rst b/boards/arm/efr32mg_sltb004a/doc/index.rst deleted file mode 100644 index a918a181be5c69..00000000000000 --- a/boards/arm/efr32mg_sltb004a/doc/index.rst +++ /dev/null @@ -1,220 +0,0 @@ -.. _efr32mg_sltb004a: - -EFR32MG-SLTB004A -################ - -Overview -******** - -The EFR32™ Mighty Gecko Starter Kit EFR32MG-SLTB004A (a.k.a Thunderboard -Sense 2) contains a MCU from the EFR32MG family built on ARM® Cortex®-M4F -processor with low power capabilities. - -.. image:: efr32mg_sltb004a.jpg - :align: center - :alt: EFR32MG-SLTB004A - -Hardware -******** - -- EFR32MG12 Mighty Gecko Wireless SoC with 38.4 MHz operating frequency -- ARM® Cortex® M4 core with 256 kB RAM and 1024 kB Flash -- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) -- 2.4 GHz ceramic antenna for wireless transmission -- Silicon Labs Si7021 relative humidity and temperature sensor -- Silicon Labs Si1133 UV index and ambient light sensor -- Silicon Labs Si7210 hall effect sensor -- Bosch Sensortec BMP280 barometric pressure sensor -- ams CCS811 indoor air quality gas sensor -- TDK InvenSense ICM-20648 6-axis inertial sensor -- TDK InvenSense ICS-43434 MEMS microphone -- Four high brightness RGB LEDs from Broadcom Limited (ASMT-YTB7-0AA02) -- One bi-color LED and two push buttons -- Power enable signals for fine grained power-control -- On-board SEGGER J-Link debugger for easy programming and debugging, which - includes a USB virtual COM port -- Mini Simplicity connector for access to energy profiling and advanced wireless - network debugging -- Breakout pads for GPIO access and connection to external hardware -- Reset button -- Automatic switch-over between USB and battery power -- CR2032 coin cell holder and external battery connector - -For more information about the EFR32MG SoC and Thunderboard Sense 2 -(EFR32MG-SLTB004A) board: - -- `EFR32MG Website`_ -- `EFR32MG Datasheet`_ -- `EFR32MG Reference Manual`_ -- `EFR32MG-SLTB004A Website`_ -- `EFR32MG-SLTB004A User Guide`_ -- `EFR32MG-SLTB004A Schematics`_ - -Supported Features -================== - -The efr32mg_sltb004a board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtcc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port-polling | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi port-polling | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | true random number generator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig``. - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -The EFR32MG SoC has eight gpio controllers (PORTA, PORTB, PORTC, PORTD, -PORTF, PORTI, PORTJ and PORTK). - -In the following table, the column Name contains Pin names. For example, PE2 -means Pin number 2 on PORTE and #27 represents the location bitfield , as used -in the board's and microcontroller's datasheets and manuals. - -+------+-------------+-----------------------------------+ -| Name | Function | Usage | -+======+=============+===================================+ -| PD8 | GPIO | LED0 (RED) | -+------+-------------+-----------------------------------+ -| PD9 | GPIO | LED1 (GREEN) | -+------+-------------+-----------------------------------+ -| PD14 | GPIO | SW0 Push Button PB0 | -+------+-------------+-----------------------------------+ -| PD15 | GPIO | Push Button PB1 | -+------+-------------+-----------------------------------+ -| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | -+------+-------------+-----------------------------------+ -| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | -+------+-------------+-----------------------------------+ -| PF3 | UART_TX | EXP12_UART_TX LEU0_TX #27 | -+------+-------------+-----------------------------------+ -| PF4 | UART_RX | EXP14_UART_RX LEU0_RX #27 | -+------+-------------+-----------------------------------+ -| PC10 | I2C_SDA | EXP16_I2C_SDA I2C0_SDA #15 | -+------+-------------+-----------------------------------+ -| PC11 | I2C_SCL | EXP15_I2C_SCL I2C0_SCL #15 | -+------+-------------+-----------------------------------+ -| PB6 | I2C_SDA | CCS811_I2C_SDA I2C1_SDA #6 | -+------+-------------+-----------------------------------+ -| PB7 | I2C_SCL | CCS811_I2C_SCL I2C1_SCL #6 | -+------+-------------+-----------------------------------+ -| PK0 | SPI_MOSI | Flash MOSI US2_TX #29 | -+------+-------------+-----------------------------------+ -| PK2 | SPI_MISO | Flash MISO US2_RX #30 | -+------+-------------+-----------------------------------+ -| PF7 | SPI_SCLK | Flash SCLK US2_CLK #18 | -+------+-------------+-----------------------------------+ -| PK1 | SPI_CS | Flash Chip Select (GPIO) | -+------+-------------+-----------------------------------+ - -System Clock -============ - -The EFR32MG SoC is configured to use the 38.4 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG SoC has four USARTs and one Low Energy UARTs (LEUART with 9600 -maximum baudrate). USART0 is configured as the Zephyr console and is connected -to the On-Board J-Link Debugger that presents a virtual COM port for general -purpose application serial data transfer with this interface. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The EFR32MG-SLTB004A includes an `J-Link`_ serial and debug adaptor built into the -board. The adaptor provides: - -- A USB connection to the host computer, which exposes a Mass Storage and a - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to EFR32-SLTB004A ------------------------------------------ - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32mg_sltb004a - :goals: build - -Connect the EFR32MG-SLTB004A to your host computer using the USB port and you -should see a USB connection which exposes a Mass Storage (TB004) and a -USB Serial Port. Copy the generated zephyr.bin in the SLTB004A drive. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _EFR32MG-SLTB004A Website: - https://www.silabs.com/products/development-tools/thunderboard/thunderboard-sense-two-kit - -.. _EFR32MG-SLTB004A User Guide: - https://www.silabs.com/documents/public/user-guides/ug309-sltb004a-user-guide.pdf - -.. _EFR32MG-SLTB004A Schematics: - https://www.silabs.com/documents/public/schematic-files/BRD4166A-D00-schematic.pdf - -.. _EFR32MG Website: - https://www.silabs.com/products/wireless/mesh-networking/efr32mg-mighty-gecko-zigbee-thread-soc - -.. _EFR32MG Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf - -.. _EFR32MG Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf - -.. _J-Link: - https://www.segger.com/jlink-debug-probes.html - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32xg24_dk2601b/Kconfig.board b/boards/arm/efr32xg24_dk2601b/Kconfig.board deleted file mode 100644 index 9b205615852b8d..00000000000000 --- a/boards/arm/efr32xg24_dk2601b/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EFR32XG24_DK2601B - bool "Silicon Labs BRD2601B (Mighty Gecko Radio Board)" - depends on SOC_SERIES_EFR32MG24 - select SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/boards/arm/efr32xg24_dk2601b/Kconfig.defconfig b/boards/arm/efr32xg24_dk2601b/Kconfig.defconfig deleted file mode 100644 index 0f0cf9aa16334b..00000000000000 --- a/boards/arm/efr32xg24_dk2601b/Kconfig.defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# EFR32XG24 DK2601B board - -# Copyright (c) 2021, Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_EFR32XG24_DK2601B - -config BOARD - default "efr32xg24_dk2601b" - -config CMU_HFXO_FREQ - default 40000000 - -config CMU_LFXO_FREQ - default 32768 - -config FLASH_BASE_ADDRESS - hex - default 0x08000000 - -if SOC_GECKO_USE_RAIL - -config FPU - default y - -endif # SOC_GECKO_USE_RAIL - -if BT - -config FPU - default y - -config MINIMAL_LIBC_MALLOC_ARENA_SIZE - default 8192 - -config MAIN_STACK_SIZE - default 2304 - -choice BT_HCI_BUS_TYPE - default BT_SILABS_HCI -endchoice - -endif # BT - -endif # BOARD_EFR32XG24_DK2601B diff --git a/boards/arm/efr32xg24_dk2601b/doc/index.rst b/boards/arm/efr32xg24_dk2601b/doc/index.rst deleted file mode 100644 index dc9766ed67cdb7..00000000000000 --- a/boards/arm/efr32xg24_dk2601b/doc/index.rst +++ /dev/null @@ -1,185 +0,0 @@ -.. _efr32mg24_dk2601b: - -xG24-DK2601B -########################### - -Overview -******** - -The EFR32MG24 Mighty Gecko Board dev kit contains -a Wireless System-On-Chip from the EFR32MG24 family built on an -ARM Cortex®-M33F processor with excellent low power capabilities. - -.. figure:: ./img/efr32xg24_dk2601b.jpg - :height: 260px - :align: center - :alt: SLWRB4180A Mighty Gecko Radio Board - - xG24-DK2601B (image courtesy of Silicon Labs) - -Hardware -******** - -- EFR32MG24B310F1536IM48-B Mighty Gecko SoC -- CPU core: ARM Cortex®-M33 with FPU -- Flash memory: 1536 kB -- RAM: 256 kB -- Transmit power: up to +20 dBm -- Operation frequency: 2.4 GHz -- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). -- On board sensors: - - - Silicon Labs Si7021 relative humidity & temperature sensor - - Silicon Labs Si7210 hall effect sensor - - 2x TDK InvenSense ICS-43434 MEMS microphones with I2S output - - TDK InvenSense ICM-20689 6-axis inertial measurement sensor - - Vishay VEML6035 ambient light sensor - - Bosch BMP384 pressure sensor with internal temperature sensor - -For more information about the EFR32MG24 SoC and BRD2601B board, refer to these -documents: - -- `EFR32MG24 Website`_ -- `EFR32MG24 Datasheet`_ -- `EFR32xG24 Reference Manual`_ -- `BRD2601B User Guide`_ - -Supported Features -================== - -The board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | stimer | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | semailbox | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| I2C(M/S) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | bluetooth | -+-----------+------------+-------------------------------------+ - -Other hardware features are currently not supported by the port. - -Connections and IOs -=================== - -In the following table, the column **Name** contains Pin names. For example, PA2 -means Pin number 2 on PORTA, as used in the board's datasheets and manuals. - -+-------+-------------+-------------------------------------+ -| Name | Function | Usage | -+=======+=============+=====================================+ -| PA4 | GPIO | LED0 | -+-------+-------------+-------------------------------------+ -| PB0 | GPIO | LED1 | -+-------+-------------+-------------------------------------+ -| PB2 | GPIO | Push Button 0 | -+-------+-------------+-------------------------------------+ -| PB3 | GPIO | Push Button 1 | -+-------+-------------+-------------------------------------+ -| PA5 | USART0_TX | UART Console EFM_BC_TX US0_TX | -+-------+-------------+-------------------------------------+ -| PA6 | USART0_RX | UART Console EFM_BC_RX US0_RX | -+-------+-------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig`` - -System Clock -============ - -The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the -board. - -Serial Port -=========== - -The EFR32MG24 SoC has one USART and two EUSARTs. -USART0 is connected to the board controller and is used for the console. - -Programming and Debugging -************************* - -.. note:: - Before using the kit the first time, you should update the J-Link firmware - from `J-Link-Downloads`_ - -Flashing -======== - -The sample application :ref:`hello_world` is used for this example. -Build the Zephyr kernel and application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: efr32xg24_dk2601b - :goals: build - -Connect the efr32xg24_dk2601b to your host computer using the USB port and you -should see a USB connection. - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board and you'll see the following message on the corresponding serial port -terminal session: - -.. code-block:: console - - Hello World! efr32xg24_dk2601b - -Bluetooth -========= - -To use the BLE function, run the command below to retrieve necessary binary -blobs from the SiLabs HAL repository. - -.. code-block:: console - - west blobs fetch silabs - -Then build the Zephyr kernel and a Bluetooth sample with the following -command. The :ref:`bluetooth-observer-sample` sample application is used in -this example. - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/observer - :board: efr32xg24_dk2601b - :goals: build - -.. _EFR32MG24 Website: - https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# - -.. _EFR32MG24 Datasheet: - https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf - -.. _EFR32xG24 Reference Manual: - https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf - -.. _BRD2601B User Guide: - https://www.silabs.com/documents/public/user-guides/ug524-brd2601b-user-guide.pdf - -.. _J-Link-Downloads: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/ev11l78a/Kconfig.board b/boards/arm/ev11l78a/Kconfig.board deleted file mode 100644 index 629eb3c624758f..00000000000000 --- a/boards/arm/ev11l78a/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Microchip EV11L78A Board configuration - -# Copyright (c) 2023 Meta Platforms, Inc. and its affiliates. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_EV11L78A - bool "Microchip EV11L78A" - depends on SOC_PART_NUMBER_SAMD20E16 diff --git a/boards/arm/ev11l78a/Kconfig.defconfig b/boards/arm/ev11l78a/Kconfig.defconfig deleted file mode 100644 index 54b74107814f5e..00000000000000 --- a/boards/arm/ev11l78a/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Microchip EV11L78A Board configuration - -# Copyright (c) 2023 Meta Platforms, Inc. and its affiliates. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "ev11l78a" - depends on BOARD_EV11L78A diff --git a/boards/arm/ev11l78a/doc/index.rst b/boards/arm/ev11l78a/doc/index.rst deleted file mode 100644 index cfa4f075eee0e5..00000000000000 --- a/boards/arm/ev11l78a/doc/index.rst +++ /dev/null @@ -1,105 +0,0 @@ -.. _ev11l78a: - -UPD301C Basic Sink Application Example -###################################### - -Overview -******** - -The UPD301C Basic Sink Application Example Evaluation Kit (EV11L78A) -is a low-cost evaluation platform for Microchip's UPD301C Standalone -Programmable USB Power Delivery (PD) Controller. This RoHS-compliant -evaluation platform comes in a small form factor and adheres to the -USB Type-C™ Connector Specification and USB PD 3.0 specification. - -.. figure:: img/ev11l78a.jpg - :width: 500px - :align: center - :alt: EV11L78A - - UPD301C Basic Sink Application Example (Credit: `Microchip Technology`_) - -Hardware -******** - -- ATSAMD20E16 ARM Cortex-M0+ processor at 48 MHz -- UPD301C combines a SAMD20 core and a UPD350 USB-PD controller -- Sink PDO Selector Switch -- Onboard LED Voltmeter - -Supported Features -================== - -The ev11l78a board configuration supports the following hardware -features: - - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - systick - * - WDT - - on-chip - - Watchdog - * - ADC - - on-chip - - Analog to Digital Converter - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial ports - * - I2C - - on-chip - - I2C ports - * - SPI - - on-chip - - Serial Peripheral Interface ports - -Other hardware features are not currently supported by Zephyr. - -Refer to the `EV11L78A Schematics`_ for a detailed hardware diagram. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/ev11l78a/ev11l78a_defconfig`. - -Serial Port -=========== - -The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs -(SERCOM1) is available on the Debug/Status header. - -SPI Port -======== - -The SAMD20 MCU has 6 SERCOM based SPIs. One of the SPIs (SERCOM0) -is internally connected between the SAMD20 core and the UPD350. - -I²C Port -======== - -The SAMD20 MCU has 6 SERCOM based I2Cs. One of the I2Cs (SERCOM3) -is available on the Debug/Status header. - -References -********** - -.. target-notes:: - -.. _Microchip Technology: - https://www.microchip.com/en-us/development-tool/ev11l78a - -.. _EV11L78A Schematics: - https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/SupportingCollateral/03-00056-R1.0.PDF diff --git a/boards/arm/ev11l78a/ev11l78a_defconfig b/boards/arm/ev11l78a/ev11l78a_defconfig deleted file mode 100644 index 5d9a8a9d651ede..00000000000000 --- a/boards/arm/ev11l78a/ev11l78a_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD20=y -CONFIG_SOC_PART_NUMBER_SAMD20E16=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_BOARD_EV11L78A=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Kernel Options due to Low Memory (4k) -CONFIG_LOG_BUFFER_SIZE=256 -CONFIG_MAIN_STACK_SIZE=640 -CONFIG_IDLE_STACK_SIZE=200 -CONFIG_ISR_STACK_SIZE=512 -CONFIG_USBC_STACK_SIZE=512 -# Prevent Interrupt Vector Table in RAM -CONFIG_SRAM_VECTOR_TABLE=n - -# This board only supports the sink role, so -# no need to ever implement source for it. -CONFIG_USBC_CSM_SINK_ONLY=y diff --git a/boards/arm/faze/Kconfig.board b/boards/arm/faze/Kconfig.board deleted file mode 100644 index 22f5bc769c1bc1..00000000000000 --- a/boards/arm/faze/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Seagate FireCuda Gaming SSD (FaZe) board - -# Copyright (c) 2020, Seagate Technology LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FAZE - bool "Seagate FireCuda Gaming SSD (FaZe)" - depends on SOC_SERIES_LPC11U6X - select SOC_PART_NUMBER_LPC11U67JBD48 diff --git a/boards/arm/faze/Kconfig.defconfig b/boards/arm/faze/Kconfig.defconfig deleted file mode 100644 index 39135dabeb84ff..00000000000000 --- a/boards/arm/faze/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Seagate FireCuda Gaming SSD (FaZe) board - -# Copyright (c) 2020, Seagate Technology LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FAZE - -config BOARD - default "faze" - -endif # BOARD_FAZE diff --git a/boards/arm/fk7b0m1_vbt6/Kconfig.board b/boards/arm/fk7b0m1_vbt6/Kconfig.board deleted file mode 100644 index 0b46551e95eae4..00000000000000 --- a/boards/arm/fk7b0m1_vbt6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H7B0VBT FK7B0M1_VBT6 board - -# Copyright (c) 2023 Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FK7B0M1_VBT6 - bool "FANKE FK7B0M1-VBT6 board" - depends on SOC_STM32H7B0XX diff --git a/boards/arm/fk7b0m1_vbt6/Kconfig.defconfig b/boards/arm/fk7b0m1_vbt6/Kconfig.defconfig deleted file mode 100644 index 39de99eb5f8cab..00000000000000 --- a/boards/arm/fk7b0m1_vbt6/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32H7B0VBT board configuration - -# Copyright (c) Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FK7B0M1_VBT6 - -config BOARD - default "fk7b0m1_vbt6" - -endif # BOARD_FK7B0M1_VBT6 diff --git a/boards/arm/fk7b0m1_vbt6/doc/index.rst b/boards/arm/fk7b0m1_vbt6/doc/index.rst deleted file mode 100644 index 2af182bc041428..00000000000000 --- a/boards/arm/fk7b0m1_vbt6/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _fk7b0m1_vbt6: - -FANKE FK7B0M1-VBT6 -################## - -Overview -******** - -The FK7B0M1-VBT6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller -platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H7B0VBT6 microcontroller. -This board is an ideal solution for developers looking to create high-performance -applications, especially in the field of Human-Machine Interface (HMI), leveraging its -robust capabilities and support for sophisticated display and touch technologies. - -The FK7B0M1-VBT6 is designed as a reference design for user application development before -transitioning to the final product, significantly simplifying the development process. -Its wide range of hardware features, including advanced display and touch capabilities, -make it exceptionally suitable for HMI applications, allowing for comprehensive evaluation -and testing of peripherals and functionalities. - -.. figure:: img/fk7b0m1_vbt6.webp - :width: 600px - :align: center - :alt: FK7B0M1-VBT6 - - FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) - -Hardware -******** - -FK7B0M1-VBT6 provides the following hardware components: - -- STM32H7B6VB in LQFP100 package -- ARM 32-bit Cortex-M7 CPU with FPU -- 280 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 128 KB Flash -- ~1.4 MB SRAM max (1.18 Mbytes user SRAM + 64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM + 4 Kbytes SRAM in Backup domain) -- Main clock: External 25MHz crystal oscillator. -- RTC: 32.768kHz crystal oscillator. -- 32-bit timers(2) -- 16-bit timers(12) -- 1 reset button, 1 user button, and 1 BOOT button -- 1 user LED -- External 64-Mbit QSPI (W25Q64) NOR Flash memory. -- External 64-Mbit SPI (W25Q64) NOR Flash memory. -- USB OTG Full Speed and High Speed(1) -- 1 micro SD card -- 1 RGB LCD interface -- SWD and serial port accessibility through a pin header -- Bring out 39 IO ports - -More information about STM32H7B0VB can be found here: - -- `STM32H7B0VB on www.st.com`_ - -Supported Features -================== - -The Zephyr nucleo_h723zg board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration per core can be found in the defconfig files: -``boards/arm/fk7b0m1-vbt6/fk7b0m1_vbt6_defconfig`` - -Connections and IOs -=================== - -Available pins: ---------------- - -Nucleo FK7B0M1-VBT6 board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -.. figure:: img/fk7b0m1_vbt6_pins.webp - :width: 600px - :align: center - :alt: FK7B0M1-VBT6 - - FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) - -LED ---- - -- User LED (blue) = PC1 - -Push buttons -------------------------- - -- BOOT = SW1 = BOOT0 -- RESET = SW2 = NRST -- User button = SW3 = PC13 - -UART ------ - -- TX device = USART1 PA9 -- RX device = USART1 PA10 - -USB ---- - -- USB D- = PA11 -- USB D+ = PA12 - -System Clock -============ - -The FK7B0M1-VBT6 System Clock could be driven by an internal or external oscillator, -as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 280MHz, -driven by an 25MHz external crystal oscillator. - -Serial Port -=========== - -The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1. - -Programming and Debugging -************************* - -The FK7B0M1-VBT6 board does not include an on-board debugger. As a result, it requires -an external debugger, such as ST-Link, for programming and debugging purposes. - -The board provides header pins for the Serial Wire Debug (SWD) interface. - -Flashing -======== - -To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using the SWD -interface. Next, connect the ST-Link to your host computer via a USB port. -Once this setup is complete, you can proceed to build and flash your application to the board - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: fk7b0m1_vbt6 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 -b 115200 - -Then, press the RESET button, you should see the following message: - -.. code-block:: console - - Hello World! fk7b0m1_vbt6 - -Debugging -========= - -This current Zephyr port does not support debugging. - -References -********** - -.. target-notes:: -.. _STM32H7B0VB on www.st.com: https://www.st.com/en/microcontrollers/stm32h7b0vb.html diff --git a/boards/arm/frdm_k22f/Kconfig.board b/boards/arm/frdm_k22f/Kconfig.board deleted file mode 100644 index 343dda21e42e35..00000000000000 --- a/boards/arm/frdm_k22f/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-K22F board - -# Copyright (c) 2018, Prevas A/S -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_K22F - bool "NXP FRDM-K22F" - depends on SOC_SERIES_KINETIS_K2X - select SOC_PART_NUMBER_MK22FN512VLH12 diff --git a/boards/arm/frdm_k22f/Kconfig.defconfig b/boards/arm/frdm_k22f/Kconfig.defconfig deleted file mode 100644 index 1f262619929491..00000000000000 --- a/boards/arm/frdm_k22f/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# FRDM-K22F board - -# Copyright (c) 2018 Prevas A/S -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_K22F - -config BOARD - default "frdm_k22f" - -config OSC_XTAL0_FREQ - default 8000000 - -config MCG_PRDIV0 - default 0x3 - -config MCG_VDIV0 - default 0xc - -config MCG_FCRDIV - default 0 - -endif # BOARD_FRDM_K22F diff --git a/boards/arm/frdm_k22f/doc/index.rst b/boards/arm/frdm_k22f/doc/index.rst deleted file mode 100644 index bdd34cc25f17d7..00000000000000 --- a/boards/arm/frdm_k22f/doc/index.rst +++ /dev/null @@ -1,298 +0,0 @@ -.. _frdm_k22f: - -NXP FRDM-K22F -############## - -Overview -******** - -The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22 -MCUs. - -- Form-factor compatible with the Arduino R3 pin layout -- Peripherals enable rapid prototyping, including a 6-axis digital - accelerometer and magnetometer to create full eCompass capabilities, a - tri-colored LED and 2 user push-buttons for direct interaction, a optional - microSD card slot, and headers for use with Bluetooth* and 2.4 GHz radio - add-on modules -- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter - running an open source bootloader, offers options for serial communication, - flash programming, and run-control debugging - -.. image:: frdm_k22f.jpg - :align: center - :alt: FRDM-K22F - -Hardware -******** - -- MK22FN512VLH12 (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 64 pin Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- Two user push buttons -- Flexible power supply option - OpenSDAv2 USB, Kinetis K22 USB, and external source -- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors -- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface - software that provides: - - - Mass storage device (MSD) flash programming interface - - CMSIS-DAP debug interface over a driver-less USB HID connection providing - run-control debugging and compatibility with IDE tools - - Virtual serial port interface - - Open source CMSIS-DAP software project - -- Optional SDHC - -For more information about the K22F SoC and FRDM-K22F board: - -- `K22F Website`_ -- `K22F Datasheet`_ -- `K22F Reference Manual`_ -- `FRDM-K22F Website`_ -- `FRDM-K22F User Guide`_ -- `FRDM-K22F Schematics`_ - -Supported Features -================== - -The frdm_k22f board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the frdm_k64f board may have additional features -already supported, which can also be re-used on this frdm_k22f board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| FTFE | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - -:zephyr_file:`boards/arm/frdm_k22f/frdm_k22f_defconfig` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The K22F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTA1 | GPIO | Red LED | -+-------+-----------------+---------------------------+ -| PTA2 | GPIO | Green LED | -+-------+-----------------+---------------------------+ -| PTD5 | GPIO | Blue LED | -+-------+-----------------+---------------------------+ -| PTC1 | GPIO | SW2 | -+-------+-----------------+---------------------------+ -| PTD0 | GPIO | FXOS8700 INT1 | -+-------+-----------------+---------------------------+ -| PTD1 | GPIO | FXOS8700 INT2 | -+-------+-----------------+---------------------------+ -| PTB17 | GPIO | SW3 | -+-------+-----------------+---------------------------+ -| PTE1 | UART1_RX | UART Console | -+-------+-----------------+---------------------------+ -| PTE0 | UART1_TX | UART Console | -+-------+-----------------+---------------------------+ -| PTD2 | UART2_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTD3 | UART2_TX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTC4 | SPI0_PCS0 | SPI | -+-------+-----------------+---------------------------+ -| PTD1 | SPI0_SCK | SPI | -+-------+-----------------+---------------------------+ -| PTD2 | SPI0_SOUT | SPI | -+-------+-----------------+---------------------------+ -| PTD3 | SPI0_SIN | SPI | -+-------+-----------------+---------------------------+ -| PTB2 | I2C0_SCL | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ -| PTB3 | I2C0_SDA | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ - -System Clock -============ - -The K22F SoC is configured to use the 8 MHz crystal oscillator on the board -with the on-chip PLL to generate a 72 MHz system clock in its RUN mode. This -clock was selected to allow for the maximum number of peripherals to be used -with the crystal and PLL clocks. Other clock configurations are possible -through NXP SDK currently. - -Serial Port -=========== - -The K22F SoC has three UARTs. One is configured for the console, another for BT -HCI, and the remaining are not used. - -USB -=== - -The K22F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (K22F USB). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink FRDM-K22F Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `Segger J-Link OpenSDA V2.1 Firmware`_. Note that Segger -does provide an OpenSDA J-Link Board-Specific Firmware for this board, however -it is not compatible with the DAPLink bootloader. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k22f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J26. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k22f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.0.0 ***** - Hello World! frdm_k22f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k22f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.0.0 ***** - Hello World! frdm_k22f - -.. _FRDM-K22F Website: - https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-kinetis-k22-mcus:FRDM-K22F - -.. _FRDM-K22F User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMK22FUG - -.. _FRDM-K22F Schematics: - https://www.nxp.com/webapp/Download?colCode=FRDM-K22F-SCH - -.. _K22F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k2x-usb/kinetis-k22-120-mhz-cost-effective-full-speed-usb-microcontrollers-mcus-based-on-arm-cortex-m4-core:K22_120 - -.. _K22F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K22P121M120SF7.pdf - -.. _K22F Reference Manual: - https://www.nxp.com/docs/en/reference-manual/K22P121M120SF7RM.pdf - -.. _OpenSDA DAPLink FRDM-K22F Firmware: - https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk22f_if_crc_legacy_0x8000.bin - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _Segger J-Link OpenSDA V2.1 Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin diff --git a/boards/arm/frdm_k64f/Kconfig.board b/boards/arm/frdm_k64f/Kconfig.board deleted file mode 100644 index d57ffc9070895a..00000000000000 --- a/boards/arm/frdm_k64f/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_K64F - bool "Freescale FRDM-K64F" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK64FN1M0VLL12 diff --git a/boards/arm/frdm_k64f/Kconfig.defconfig b/boards/arm/frdm_k64f/Kconfig.defconfig deleted file mode 100644 index f4ccc456eab00b..00000000000000 --- a/boards/arm/frdm_k64f/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# FRDM-K64F board - -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_K64F - -config BOARD - default "frdm_k64f" - -config OSC_XTAL0_FREQ - default 50000000 - -config MCG_PRDIV0 - default 0x13 - -config MCG_VDIV0 - default 0x18 - -config MCG_FCRDIV - default 1 - -config TEST_EXTRA_STACK_SIZE - default 128 - -if NETWORKING - -config NET_L2_ETHERNET - default y if !MODEM - -endif # NETWORKING - -endif # BOARD_FRDM_K64F diff --git a/boards/arm/frdm_k64f/doc/index.rst b/boards/arm/frdm_k64f/doc/index.rst deleted file mode 100644 index acbf22605613c0..00000000000000 --- a/boards/arm/frdm_k64f/doc/index.rst +++ /dev/null @@ -1,402 +0,0 @@ -.. _frdm_k64f: - -NXP FRDM-K64F -############## - -Overview -******** - -The Freedom-K64F is an ultra-low-cost development platform for Kinetis K64, -K63, and K24 MCUs. - -- Form-factor compatible with the Arduino R3 pin layout -- Peripherals enable rapid prototyping, including a 6-axis digital - accelerometer and magnetometer to create full eCompass capabilities, a - tri-colored LED and 2 user push-buttons for direct interaction, a microSD - card slot, and connectivity using onboard Ethernet port and headers for use - with Bluetooth* and 2.4 GHz radio add-on modules -- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter - running an open source bootloader, offers options for serial communication, - flash programming, and run-control debugging - -.. image:: frdm_k64f.jpg - :align: center - :alt: FRDM-K64F - -Hardware -******** - -- MK64FN1M0VLL12 MCU (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- Two user push buttons -- Flexible power supply option - OpenSDAv2 USB, Kinetis K64 USB, and external source -- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors -- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface - software that provides: - - - Mass storage device (MSD) flash programming interface - - CMSIS-DAP debug interface over a driver-less USB HID connection providing - run-control debugging and compatibility with IDE tools - - Virtual serial port interface - - Open source CMSIS-DAP software project - -- Ethernet -- SDHC - -For more information about the K64F SoC and FRDM-K64F board: - -- `K64F Website`_ -- `K64F Datasheet`_ -- `K64F Reference Manual`_ -- `FRDM-K64F Website`_ -- `FRDM-K64F User Guide`_ -- `FRDM-K64F Schematics`_ - -Supported Features -================== - -NXP considers the FRDM-K64F as the superset board for the Kinetis K -series of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire Kinetis K series. NXP prioritizes enabling -this board with new support for Zephyr features. The frdm_k64f board -configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| FTFE | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_k64f/frdm_k64f_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The K64F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTB22 | GPIO | Red LED | -+-------+-----------------+---------------------------+ -| PTE26 | GPIO | Green LED | -+-------+-----------------+---------------------------+ -| PTB21 | GPIO | Blue LED | -+-------+-----------------+---------------------------+ -| PTC6 | GPIO | SW2 / FXOS8700 INT1 | -+-------+-----------------+---------------------------+ -| PTC13 | GPIO | FXOS8700 INT2 | -+-------+-----------------+---------------------------+ -| PTA4 | GPIO | SW3 | -+-------+-----------------+---------------------------+ -| PTB10 | ADC | ADC1 channel 14 | -+-------+-----------------+---------------------------+ -| PTB16 | UART0_RX | UART Console | -+-------+-----------------+---------------------------+ -| PTB17 | UART0_TX | UART Console | -+-------+-----------------+---------------------------+ -| PTB18 | CAN0_TX | CAN TX | -+-------+-----------------+---------------------------+ -| PTB19 | CAN0_RX | CAN RX | -+-------+-----------------+---------------------------+ -| PTC8 | PWM | PWM_3 channel 4 | -+-------+-----------------+---------------------------+ -| PTC9 | PWM | PWM_3 channel 5 | -+-------+-----------------+---------------------------+ -| PTC16 | UART3_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTC17 | UART3_TX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTD0 | SPI0_PCS0 | SPI | -+-------+-----------------+---------------------------+ -| PTD1 | SPI0_SCK | SPI | -+-------+-----------------+---------------------------+ -| PTD2 | SPI0_SOUT | SPI | -+-------+-----------------+---------------------------+ -| PTD3 | SPI0_SIN | SPI | -+-------+-----------------+---------------------------+ -| PTE24 | I2C0_SCL | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ -| PTE25 | I2C0_SDA | I2C / FXOS8700 | -+-------+-----------------+---------------------------+ -| PTA5 | MII0_RXER | Ethernet | -+-------+-----------------+---------------------------+ -| PTA12 | MII0_RXD1 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA13 | MII0_RXD0 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA14 | MII0_RXDV | Ethernet | -+-------+-----------------+---------------------------+ -| PTA15 | MII0_TXEN | Ethernet | -+-------+-----------------+---------------------------+ -| PTA16 | MII0_TXD0 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA17 | MII0_TXD1 | Ethernet | -+-------+-----------------+---------------------------+ -| PTA28 | MII0_TXER | Ethernet | -+-------+-----------------+---------------------------+ -| PTB0 | MII0_MDIO | Ethernet | -+-------+-----------------+---------------------------+ -| PTB1 | MII0_MDC | Ethernet | -+-------+-----------------+---------------------------+ -| PTC16 | ENET0_1588_TMR0 | Ethernet | -+-------+-----------------+---------------------------+ -| PTC17 | ENET0_1588_TMR1 | Ethernet | -+-------+-----------------+---------------------------+ -| PTC18 | ENET0_1588_TMR2 | Ethernet | -+-------+-----------------+---------------------------+ -| PTC19 | ENET0_1588_TMR3 | Ethernet | -+-------+-----------------+---------------------------+ - -.. note:: - Do not enable Ethernet and UART BT HCI simultaneously because they conflict - on PTC16-17. - -System Clock -============ - -The K64F SoC is configured to use the 50 MHz external oscillator on the board -with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The K64F SoC has six UARTs. One is configured for the console, another for BT -HCI, and the remaining are not used. - -USB -=== - -The K64F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (K64F USB). -Only USB device function is supported in Zephyr at the moment. - -CAN -=== - -The FRDM-K64F board does not come with an onboard CAN transceiver. In order to -use the CAN bus, an external CAN bus transceiver must be connected to ``PTB18`` -(``CAN0_TX``) and ``PTB19`` (``CAN0_RX``). - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -.. tabs:: - - .. group-tab:: OpenSDA DAPLink Onboard (Recommended) - - Install the :ref:`linkserver-debug-host-tools` and make sure they are in your - search path. LinkServer works with the default CMSIS-DAP firmware included in - the on-board debugger. - - Linkserver is the default for this board, ``west flash`` and ``west debug`` will - call the linkserver runner. - - .. code-block:: console - - west flash - - Alternatively, pyOCD can be used to flash and debug the board by using the - ``-r pyocd`` option with West. pyOCD is installed when you complete the - :ref:`gs_python_deps` step in the Getting Started Guide. The runners supported - by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP - does not test or support the pyOCD runner. - - - .. group-tab:: OpenSDA JLink Onboard - - Install the :ref:`jlink-debug-host-tools` and make sure they are in your search - path. - - The version of J-Link firmware to program to the board depends on the version - of the DAPLink bootloader. Refer to `OpenSDA Serial and Debug Adapter`_ for - more details. On this page, change the pull-down menu for "Choose your board to - start" to FRDM-K64F, and review the section "To update your board with OpenSDA - applications". Note that Segger does provide an OpenSDA J-Link Board-Specific - Firmware for this board, however it is not compatible with the DAPLink - bootloader. After downloading the appropriate J-Link firmware, follow the - instructions in :ref:`opensda-jlink-onboard-debug-probe` to program to the - board. - - Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and - ``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the - default runner to J-Link: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k64f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J26. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k64f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_k64f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k64f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_k64f - -Troubleshooting -=============== - -If pyocd raises an uncaught ``DAPAccessIntf.TransferFaultError()`` exception -when you try to flash or debug, it's possible that the K64F flash may have been -locked by a corrupt application. You can unlock it with the following sequence -of pyocd commands: - -.. code-block:: console - - $ pyocd cmd - 0001915:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device - Connected to K64F [Halted]: 0240000026334e450028400d5e0e000e4eb1000097969900 - >>> unlock - 0016178:WARNING:target_kinetis:K64F secure state: unlocked successfully - >>> reinit - 0034584:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device - >>> load build/zephyr/zephyr.bin - [====================] 100% - >>> reset - Resetting target - >>> quit - -.. _FRDM-K64F Website: - https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F - -.. _FRDM-K64F User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMK64FUG - -.. _FRDM-K64F Schematics: - https://www.nxp.com/webapp/Download?colCode=FRDM-K64F-SCH-E4 - -.. _K64F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 - -.. _K64F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf - -.. _K64F Reference Manual: - https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink FRDM-K64F Firmware: - https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk64f_if_crc_legacy_0x5000.bin - -.. _OpenSDA Serial and Debug Adapter: - https://www.nxp.com/design/microcontrollers-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#FRDM-K64F - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/frdm_k82f/Kconfig.board b/boards/arm/frdm_k82f/Kconfig.board deleted file mode 100644 index 2c18f441b53cbb..00000000000000 --- a/boards/arm/frdm_k82f/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-K82F board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_K82F - bool "NXP FRDM-K82F" - depends on SOC_SERIES_KINETIS_K8X - select SOC_PART_NUMBER_MK82FN256VLL15 diff --git a/boards/arm/frdm_k82f/Kconfig.defconfig b/boards/arm/frdm_k82f/Kconfig.defconfig deleted file mode 100644 index 377b08c1be4b31..00000000000000 --- a/boards/arm/frdm_k82f/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# FRDM-K82F board - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_K82F - -config BOARD - default "frdm_k82f" - -config OSC_XTAL0_FREQ - default 12000000 - -config MCG_PRDIV0 - default 0x0 - -config MCG_VDIV0 - default 0x4 - -config MCG_FCRDIV - default 1 - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # BOARD_FRDM_K82F diff --git a/boards/arm/frdm_k82f/doc/index.rst b/boards/arm/frdm_k82f/doc/index.rst deleted file mode 100644 index 239201f2a6ccd1..00000000000000 --- a/boards/arm/frdm_k82f/doc/index.rst +++ /dev/null @@ -1,254 +0,0 @@ -.. _frdm_k82f: - -NXP FRDM-K82F -############## - -Overview -******** - -The FRDM-K82F is a low-cost development platform for Kinetis K80, K81, -and K82 MCUs. - -- Form-factor compatible with the Arduino R3 pin layout -- Peripherals enable rapid prototyping, including a six-axis digital - accelerometer and magnetometer to create full eCompass capabilities, a - tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb - QuadSPI external flash, FlexIO camera header, touchpads and headers for use - with Bluetooth and 2.4 GHz radio add-on modules -- OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter - running an open source bootloader, offers options for serial communication, - flash programming, and run-control debugging - -.. image:: frdm_k82f.jpg - :align: center - :alt: FRDM-K82F - -Hardware -******** - -- MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- Two user push buttons -- 2x 32 Mb QSPI flash -- Flexible power supply option - OpenSDAv2.1 USB, Kinetis K82 USB, and external source -- Easy access to MCU input/output through Arduino R3 compatible I/O connectors -- Programmable OpenSDAv2.1 debug circuit supporting the CMSIS-DAP Interface - software that provides: - - - Mass storage device (MSD) flash programming interface - - CMSIS-DAP debug interface over a driver-less USB HID connection providing - run-control debugging and compatibility with IDE tools - - Virtual serial port interface - - Open source CMSIS-DAP software project - -- FlexIO header - -For more information about the K82F SoC and FRDM-K82F board: - -- `K82F Website`_ -- `K82F Datasheet`_ -- `K82F Reference Manual`_ -- `FRDM-K82F Website`_ -- `FRDM-K82F User Guide`_ -- `FRDM-K82F Schematics`_ - -Supported Features -================== - -The frdm_k82f board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the frdm_k64f board may have additional features -already supported, which can also be re-used on this frdm_k82f board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| FLASH | off-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FTFA | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_k82f/frdm_k82f_defconfig`` - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The K82F SoC is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The K82F SoC has five UARTs. One is configured for the console, the remaining -ones are not used. - -USB -=== - -The K82F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (J11). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink FRDM-K82F Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Firmware for FRDM-K82F`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k82f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J5. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k82f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! frdm_k82f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_k82f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! frdm_k82f - -.. _FRDM-K82F Website: - https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k82-k81-and-k80-mcus:FRDM-K82F - -.. _FRDM-K82F User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMK82FUG - -.. _FRDM-K82F Schematics: - https://www.nxp.com/downloads/en/schematics/FRDM-K82F-SCH.pdf - -.. _K82F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k8x-secure/kinetis-k82-150-mhz-hw-cryptographic-co-processor-quadspi-microcontrollers-mcus-based-on-arm-cortex-m4-core:K82_150 - -.. _K82F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K82P121M150SF5.pdf - -.. _K82F Reference Manual: - https://www.nxp.com/webapp/Download?colCode=K82P121M150SF5RM - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink FRDM-K82F Firmware: - https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk82f_if_crc_legacy_0x8000.bin - -.. _OpenSDA J-Link Firmware for FRDM-K82F: - https://www.segger.com/downloads/jlink/OpenSDA_FRDM-K82F diff --git a/boards/arm/frdm_kl25z/Kconfig.board b/boards/arm/frdm_kl25z/Kconfig.board deleted file mode 100644 index 9a2a41841155d2..00000000000000 --- a/boards/arm/frdm_kl25z/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-KL25Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_KL25Z - bool "NXP FRDM-KL25Z" - depends on SOC_SERIES_KINETIS_KL2X - select SOC_PART_NUMBER_MKL25Z128VLK4 diff --git a/boards/arm/frdm_kl25z/Kconfig.defconfig b/boards/arm/frdm_kl25z/Kconfig.defconfig deleted file mode 100644 index c759787a2196d0..00000000000000 --- a/boards/arm/frdm_kl25z/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# FRDM-KL25Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_KL25Z - -config BOARD - default "frdm_kl25z" - -config OSC_XTAL0_FREQ - default 8000000 - -config MCG_PRDIV0 - default 0x01 - -config MCG_VDIV0 - default 0x00 - -config MCG_FRDIV - default 5 - -config MCG_FCRDIV - default 0 - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -endif # FXOS8700 - -endif # BOARD_FRDM_KL25Z diff --git a/boards/arm/frdm_kl25z/doc/index.rst b/boards/arm/frdm_kl25z/doc/index.rst deleted file mode 100644 index 22261a26e57ce6..00000000000000 --- a/boards/arm/frdm_kl25z/doc/index.rst +++ /dev/null @@ -1,251 +0,0 @@ -.. _frdm_kl25z: - -NXP FRDM-KL25Z -############## - -Overview -******** - -The Freedom KL25Z is an ultra-low-cost development platform for -Kinetis |reg| L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built -on ARM |reg| Cortex |reg|-M0+ processor. - -The FRDM-KL25Z features include easy access to MCU I/O, battery-ready, -low-power operation, a standard-based form factor with expansion board -options and a built-in debug interface for flash programming and run-control. - - -.. image:: frdm_kl25z.jpg - :align: center - :alt: FRDM-KL25Z - -Hardware -******** - -- MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP -- On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED -- OpenSDA debug interface - -For more information about the KL25Z SoC and FRDM-KL25Z board: - -- `KL25Z Website`_ -- `KL25Z Datasheet`_ -- `KL25Z Reference Manual`_ -- `FRDM-KL25Z Website`_ -- `FRDM-KL25Z User Guide`_ -- `FRDM-KL25Z Schematics`_ - -Supported Features -================== - -The frdm_kl25z board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_kl25z/frdm_kl25z_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KL25Z SoC has five pairs of pinmux/gpio controllers, and all are currently enabled -(PORTA/GPIOA, PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-KL25Z board. - -+-------+-------------+---------------------------+ -| Name | Function | Usage | -+=======+=============+===========================+ -| PTB2 | ADC | ADC0 channel 12 | -+-------+-------------+---------------------------+ -| PTB18 | GPIO | Red LED | -+-------+-------------+---------------------------+ -| PTB19 | GPIO | Green LED | -+-------+-------------+---------------------------+ -| PTD1 | GPIO | Blue LED | -+-------+-------------+---------------------------+ -| PTA1 | UART0_RX | UART Console | -+-------+-------------+---------------------------+ -| PTA2 | UART0_TX | UART Console | -+-------+-------------+---------------------------+ -| PTE24 | I2C0_SCL | I2C | -+-------+-------------+---------------------------+ -| PTE25 | I2C0_SDA | I2C | -+-------+-------------+---------------------------+ - - -System Clock -============ - -The KL25Z SoC is configured to use the 8 MHz external oscillator on the board -with the on-chip FLL to generate a 48 MHz system clock. - -Serial Port -=========== - -The KL25Z UART0 is used for the console. - -USB -=== - -The KL25Z SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its mini USB connector (USB KL25Z). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: Linkserver: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------------------- - - Install the :ref:`linkserver-debug-host-tools` and make sure they are in your - search path. LinkServer works with the CMSIS-DAP debug firmware. Please follow the - instructions on :ref:`opensda-daplink-onboard-debug-probe` and select the latest revision - of the firmware image. - - Linkserver is the default for this board, ``west flash`` and ``west debug`` will - call the linkserver runner. - - .. code-block:: console - - west flash - west debug - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link FRDM-KL25Z Firmware`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kl25z - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Note: ------ - -The runners supported by NXP are LinkServer and JLink. pyOCD is another potential option, -but NXP does not test or support the pyOCD runner. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J7. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kl25z - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kl25z - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kl25z - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kl25z - -.. _FRDM-KL25Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z - -.. _FRDM-KL25Z User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMKL25ZUM - -.. _FRDM-KL25Z Schematics: - https://www.nxp.com/downloads/en/schematics/FRDM-KL25Z_SCH_REV_E.pdf - -.. _KL25Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/kinetis-kl2x-72-96mhz-usb-ultra-low-power-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KL2x?&l - -.. _KL25Z Datasheet: - https://www.nxp.com/docs/en/data-sheet/KL25P80M48SF0.pdf - -.. _KL25Z Reference Manual: - https://www.nxp.com/webapp/Download?colCode=KL25P80M48SF0RM - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink FRDM-KL25Z Firmware: - https://www.nxp.com/downloads/en/ide-debug-compile-build-tools/OpenSDAv2.2_DAPLink_frdmkl25z_rev0242.zip - -.. _OpenSDA J-Link FRDM-KL25Z Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KL25Z diff --git a/boards/arm/frdm_kw41z/Kconfig.board b/boards/arm/frdm_kw41z/Kconfig.board deleted file mode 100644 index 7d4a5849f8b6d0..00000000000000 --- a/boards/arm/frdm_kw41z/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# FRDM-KW41Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FRDM_KW41Z - bool "NXP FRDM-KW41Z" - depends on SOC_SERIES_KINETIS_KWX - select SOC_PART_NUMBER_MKW41Z512VHT4 diff --git a/boards/arm/frdm_kw41z/Kconfig.defconfig b/boards/arm/frdm_kw41z/Kconfig.defconfig deleted file mode 100644 index 82f086cd7a5c6f..00000000000000 --- a/boards/arm/frdm_kw41z/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# FRDM-KW41Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FRDM_KW41Z - -config BOARD - default "frdm_kw41z" - -config OSC_XTAL0_FREQ - default 32000000 - -config MCG_FRDIV - default 5 - -config MCG_FCRDIV - default 0 - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -choice ADC_MCUX_ADC16_VREF - default ADC_MCUX_ADC16_VREF_ALTERNATE -endchoice - -endif # BOARD_FRDM_KW41Z diff --git a/boards/arm/frdm_kw41z/doc/index.rst b/boards/arm/frdm_kw41z/doc/index.rst deleted file mode 100644 index cf1557b136b17e..00000000000000 --- a/boards/arm/frdm_kw41z/doc/index.rst +++ /dev/null @@ -1,260 +0,0 @@ -.. _frdm_kw41z: - -NXP FRDM-KW41Z -############## - -Overview -******** - -The FRDM-KW41Z is a development kit enabled by the Kinetis |reg| W series -KW41Z/31Z/21Z (KW41Z) family built on ARM |reg| Cortex |reg|-M0+ processor with -integrated 2.4 GHz transceiver supporting Bluetooth |reg| Smart/Bluetooth -|reg| Low Energy -(BLE) v4.2, Generic FSK, IEEE |reg| 802.15.4 and Thread. - -The FRDM-KW41Z kit contains two Freedom boards that can be used as a -development board or a shield to connect to a host processor. The FRDM-KW41Z is -form-factor compatible with the Arduino |trade| R3 pin layout for more expansion -options. - -The FRDM-KW41Z highly-sensitive, optimized 2.4 GHz radio features a PCB -F-antenna which can be bypassed to test via SMA connection, multiple power -supply options, push/capacitive touch buttons, switches, LEDs and integrated -sensors. - -.. image:: frdm_kw41z.jpg - :align: center - :alt: FRDM-KW41Z - -Hardware -******** - -- Can be configured as Host or Shield for connection to Host Processor -- Supports all DC-DC configurations (Buck, Boost, Bypass) -- PCB inverted F-type antenna -- SMA RF Connector -- RF regulatory certified -- Serial Flash for OTA firmware upgrades -- On board NXP FXOS8700CQ digital sensor, 3D Accelerometer ( |plusminus| 2g/ - |plusminus| 4g/ |plusminus| 8g) + 3D - Magnetometer -- OpenSDA and JTAG debug - -For more information about the KW41Z SoC and FRDM-KW41Z board: - -- `KW41Z Website`_ -- `KW41Z Datasheet`_ -- `KW41Z Reference Manual`_ -- `FRDM-KW41Z Website`_ -- `FRDM-KW41Z User Guide`_ -- `FRDM-KW41Z Schematics`_ - -Supported Features -================== - -The frdm_kw41z board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling: | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | tpm | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FTFA | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/frdm_kw41z/frdm_kw41z_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KW41Z SoC has three pairs of pinmux/gpio controllers, but only two are -currently enabled (PORTA/GPIOA and PORTC/GPIOC) for the FRDM-KW41Z board. - -+-------+-------------+---------------------------+ -| Name | Function | Usage | -+=======+=============+===========================+ -| PTC1 | GPIO | Red LED / FXOS8700 INT1 | -+-------+-------------+---------------------------+ -| PTA19 | GPIO | Green LED | -+-------+-------------+---------------------------+ -| PTA18 | GPIO | Blue LED | -+-------+-------------+---------------------------+ -| PTB2 | ADC | ADC0 channel 3 | -+-------+-------------+---------------------------+ -| PTC2 | I2C1_SCL | I2C / FXOS8700 | -+-------+-------------+---------------------------+ -| PTC3 | I2C1_SDA | I2C / FXOS8700 | -+-------+-------------+---------------------------+ -| PTC4 | GPIO | SW3 | -+-------+-------------+---------------------------+ -| PTC5 | GPIO | SW4 | -+-------+-------------+---------------------------+ -| PTC6 | LPUART0_RX | UART Console | -+-------+-------------+---------------------------+ -| PTC7 | LPUART0_TX | UART Console | -+-------+-------------+---------------------------+ -| PTC16 | SPI0_SCK | SPI | -+-------+-------------+---------------------------+ -| PTC17 | SPI0_SOUT | SPI | -+-------+-------------+---------------------------+ -| PTC18 | SPI0_SIN | SPI | -+-------+-------------+---------------------------+ -| PTC19 | SPI0_PCS0 | SPI | -+-------+-------------+---------------------------+ - -System Clock -============ - -The KW41Z SoC is configured to use the 32 MHz external oscillator on the board -with the on-chip FLL to generate a 40 MHz system clock. - -Serial Port -=========== - -The KW41Z SoC has one UART, which is used for the console. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink FRDM-KW41Z Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link FRDM-KW41Z Firmware`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kw41z - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J6. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kw41z - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kw41z - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: frdm_kw41z - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! frdm_kw41z - -.. _FRDM-KW41Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/freedom-development-kit-for-kinetis-kw41z-31z-21z-mcus:FRDM-KW41Z - -.. _FRDM-KW41Z User Guide: - https://www.nxp.com/webapp/Download?colCode=FRDMKW41ZUG - -.. _FRDM-KW41Z Schematics: - https://www.nxp.com/webapp/Download?colCode=FRDM-KW41Z-SCH - -.. _KW41Z Website: - https://www.nxp.com/products/wireless/zigbee/kinetis-kw41z-2.4-ghz-dual-mode-bluetooth-low-energy-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW41Z - -.. _KW41Z Datasheet: - https://www.nxp.com/docs/en/data-sheet/MKW41Z512.pdf - -.. _KW41Z Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MKW41Z512RM - -.. _OpenSDA DAPLink FRDM-KW41Z Firmware: - https://www.nxp.com/downloads/en/reference-applications/OpenSDAv2.2_DAPLink_frdmkw41z_rev0241.zip - -.. _OpenSDA J-Link FRDM-KW41Z Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KW41Z diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/Kconfig rename to boards/arm/fvp_base_revc_2xaemv8a/Kconfig diff --git a/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.defconfig b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.defconfig new file mode 100644 index 00000000000000..3f1e48df8cc70f --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FVP_BASE_REVC_2XAEMV8A + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.fvp_base_revc_2xaemv8a b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.fvp_base_revc_2xaemv8a new file mode 100644 index 00000000000000..874f1dba015315 --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/Kconfig.fvp_base_revc_2xaemv8a @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FVP_BASE_REVC_2XAEMV8A + select SOC_SERIES_FVP_AEMV8A + select SOC_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/board.cmake b/boards/arm/fvp_base_revc_2xaemv8a/board.cmake similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/board.cmake rename to boards/arm/fvp_base_revc_2xaemv8a/board.cmake diff --git a/boards/arm/fvp_base_revc_2xaemv8a/board.yml b/boards/arm/fvp_base_revc_2xaemv8a/board.yml new file mode 100644 index 00000000000000..8c881c9d86a8af --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/board.yml @@ -0,0 +1,9 @@ +board: + name: fvp_base_revc_2xaemv8a + vendor: arm + socs: + - name: fvp_base_revc_2xaemv8a + variants: + - name: smp + variants: + - name: ns diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst b/boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/doc/index.rst rename to boards/arm/fvp_base_revc_2xaemv8a/doc/index.rst diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.dts diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a.yaml diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig similarity index 77% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig index 159682f9295d63..07b3195104ae13 100644 --- a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2021 Carlo Caione # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_FVP_AEMV8A=y -CONFIG_SOC_FVP_BASE_REVC_2XAEMV8A=y -CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A=y - CONFIG_XIP=n CONFIG_THREAD_STACK_INFO=y diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.dts b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.dts similarity index 100% rename from boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.dts rename to boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.dts diff --git a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml new file mode 100644 index 00000000000000..e64ed9f8e7cd4d --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns.yaml @@ -0,0 +1,13 @@ +# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_base_revc_2xaemv8a//smp/ns +name: FVP Emulation FVP_Base_RevC-2xAEMvA (SMP) +arch: arm64 +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +vendor: arm diff --git a/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns_defconfig b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns_defconfig new file mode 100644 index 00000000000000..31973c6ff16db9 --- /dev/null +++ b/boards/arm/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_fvp_base_revc_2xaemv8a_smp_ns_defconfig @@ -0,0 +1,33 @@ +# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable TFA +CONFIG_ARMV8_A_NS=y +CONFIG_BUILD_WITH_TFA=y + +# Enable SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_CACHE_MANAGEMENT=y +CONFIG_TIMEOUT_64BIT=y +CONFIG_ARM64_SET_VMPIDR_EL2=y +CONFIG_MAX_THREAD_BYTES=3 + +# PSCI is supported +CONFIG_PM_CPU_OPS=y diff --git a/boards/arm/fvp_baser_aemv8r/Kconfig.defconfig b/boards/arm/fvp_baser_aemv8r/Kconfig.defconfig new file mode 100644 index 00000000000000..980b88283d4fda --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FVP_BASER_AEMV8R + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_FVP_BASER_AEMV8R diff --git a/boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r b/boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r new file mode 100644 index 00000000000000..059a4ba694862b --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/Kconfig.fvp_baser_aemv8r @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FVP_BASER_AEMV8R + select SOC_FVP_AEMV8R_AARCH64 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64_SMP + select SOC_FVP_AEMV8R_AARCH32 if BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32 || BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32_SMP diff --git a/boards/arm/fvp_baser_aemv8r/board.cmake b/boards/arm/fvp_baser_aemv8r/board.cmake new file mode 100644 index 00000000000000..f7753bc5099b17 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/board.cmake @@ -0,0 +1,74 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS armfvp) +set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R) +set(ARMFVP_MIN_VERSION 11.16.16) + +if(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH64) + set(ARMFVP_FLAGS + -C cluster0.has_aarch64=1 + -C cluster0.VMSA_supported=0 + -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} + -C cluster0.gicv3.cpuintf-mmap-access-level=2 + -C cluster0.gicv3.SRE-enable-action-on-mmap=2 + -C cluster0.gicv3.SRE-EL2-enable-RAO=1 + -C cluster0.gicv3.extended-interrupt-range-support=1 + -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 + -C gic_distributor.has-two-security-states=0 + -C bp.refcounter.non_arch_start_at_default=1 + # UART0 config + -C bp.pl011_uart0.out_file=- + -C bp.pl011_uart0.unbuffered_output=1 + -C bp.terminal_0.start_telnet=0 + # UART1 config + -C bp.pl011_uart1.out_file=- + -C bp.pl011_uart1.unbuffered_output=1 + -C bp.terminal_1.start_telnet=0 + # UART2 config + -C bp.pl011_uart2.out_file=- + -C bp.pl011_uart2.unbuffered_output=1 + -C bp.terminal_2.start_telnet=0 + # UART3 config + -C bp.pl011_uart3.out_file=- + -C bp.pl011_uart3.unbuffered_output=1 + -C bp.terminal_3.start_telnet=0 + + -C bp.vis.disable_visualisation=1 + -C bp.vis.rate_limit-enable=0 + -C cache_state_modelled=1 + ) +elseif(CONFIG_BOARD_FVP_BASER_AEMV8R_FVP_AEMV8R_AARCH32) + set(ARMFVP_FLAGS + -C cluster0.has_aarch64=0 + -C cluster0.VMSA_supported=0 + -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} + -C cluster0.gicv3.cpuintf-mmap-access-level=2 + -C cluster0.gicv3.SRE-enable-action-on-mmap=2 + -C cluster0.gicv3.SRE-EL2-enable-RAO=1 + -C cluster0.gicv3.extended-interrupt-range-support=1 + -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 + -C gic_distributor.has-two-security-states=0 + -C bp.refcounter.non_arch_start_at_default=1 + # UART0 config + -C bp.pl011_uart0.out_file=- + -C bp.pl011_uart0.unbuffered_output=1 + -C bp.terminal_0.start_telnet=0 + # UART1 config + -C bp.pl011_uart1.out_file=- + -C bp.pl011_uart1.unbuffered_output=1 + -C bp.terminal_1.start_telnet=0 + # UART2 config + -C bp.pl011_uart2.out_file=- + -C bp.pl011_uart2.unbuffered_output=1 + -C bp.terminal_2.start_telnet=0 + # UART3 config + -C bp.pl011_uart3.out_file=- + -C bp.pl011_uart3.unbuffered_output=1 + -C bp.terminal_3.start_telnet=0 + + -C bp.vis.disable_visualisation=1 + -C bp.vis.rate_limit-enable=0 + -C cache_state_modelled=0 + ) +endif() diff --git a/boards/arm/fvp_baser_aemv8r/board.yml b/boards/arm/fvp_baser_aemv8r/board.yml new file mode 100644 index 00000000000000..f80eb3a6ed0962 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/board.yml @@ -0,0 +1,10 @@ +board: + name: fvp_baser_aemv8r + vendor: arm + socs: + - name: fvp_aemv8r_aarch64 + variants: + - name: 'smp' + - name: fvp_aemv8r_aarch32 + variants: + - name: 'smp' diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/doc/index.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst similarity index 100% rename from boards/arm/fvp_baser_aemv8r_aarch32/doc/index.rst rename to boards/arm/fvp_baser_aemv8r/doc/aarch32.rst diff --git a/boards/arm64/fvp_baser_aemv8r/doc/index.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/index.rst rename to boards/arm/fvp_baser_aemv8r/doc/aarch64.rst diff --git a/boards/arm64/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst b/boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst rename to boards/arm/fvp_baser_aemv8r/doc/debug-with-arm-ds.rst diff --git a/boards/arm64/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/DS-debug-working.jpg diff --git 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a/boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration.jpg diff --git a/boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-path.jpg diff --git a/boards/arm64/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-use-V8R64-Generic.jpg b/boards/arm/fvp_baser_aemv8r/doc/images/create-new-model-configuration_model-use-V8R64-Generic.jpg similarity index 100% rename from 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similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/doc/images/version-info.jpg rename to boards/arm/fvp_baser_aemv8r/doc/images/version-info.jpg diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts similarity index 100% rename from boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.dts rename to boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml new file mode 100644 index 00000000000000..0f7b38d648c8c9 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# Copyright (c) 2022 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32 +name: FVP Emulation FVP_BaseR_AEMv8R AArch32 +arch: arm +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +testing: + timeout_multiplier: 15 diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig new file mode 100644 index 00000000000000..bf9d919c6a3145 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# Copyright (c) 2022 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_ISR_STACK_SIZE=1024 +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE=n diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts new file mode 100644 index 00000000000000..b33ad9ca128390 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.dts @@ -0,0 +1,8 @@ +/* + * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "fvp_baser_aemv8r_fvp_aemv8r_aarch32.dts" diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml new file mode 100644 index 00000000000000..d056a315af6403 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp +name: FVP Emulation FVP_BaseR_AEMv8R AArch32 (SMP) +arch: arm +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +testing: + timeout_multiplier: 25 diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig new file mode 100644 index 00000000000000..a320c3486f794e --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch32_smp_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_SWITCH=y +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts similarity index 100% rename from boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.dts rename to boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml new file mode 100644 index 00000000000000..501a6b893743fa --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64.yaml @@ -0,0 +1,15 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64 +name: FVP Emulation FVP_BaseR_AEMv8R +arch: arm64 +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +testing: + timeout_multiplier: 8 +vendor: arm diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_defconfig new file mode 100644 index 00000000000000..fb029e44ab54e2 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +CONFIG_THREAD_STACK_INFO=y + +# Enable Timer and Sys clock +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_ARM_ARCH_TIMER=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts new file mode 100644 index 00000000000000..6e57c4d83bca55 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.dts @@ -0,0 +1,6 @@ +/* + * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "fvp_baser_aemv8r_fvp_aemv8r_aarch64.dts" diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml new file mode 100644 index 00000000000000..fa1baf892d9a82 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp.yaml @@ -0,0 +1,17 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +identifier: fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp +name: FVP Emulation FVP_BaseR_AEMv8R (SMP) +arch: arm64 +type: sim +toolchain: + - zephyr + - cross-compile +ram: 2048 +flash: 64 +supported: + - smp +testing: + timeout_multiplier: 20 +vendor: arm diff --git a/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig new file mode 100644 index 00000000000000..286fc28d189943 --- /dev/null +++ b/boards/arm/fvp_baser_aemv8r/fvp_baser_aemv8r_fvp_aemv8r_aarch64_smp_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +# Enable simulated CPU power management +CONFIG_SOC_FVP_AEMV8R_SIMULATE_CPU_PM=y +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=n +CONFIG_ARM64_SET_VMPIDR_EL2=y + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 + +CONFIG_MAX_THREAD_BYTES=3 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.board b/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.board deleted file mode 100644 index da1b202a128f67..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FVP_BASER_AEMV8R_AARCH32 - bool "FVP BaseR AEMv8R AArch32 simulation board" - depends on SOC_FVP_AEMV8R_AARCH32 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig b/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig deleted file mode 100644 index 262313658822ec..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FVP_BASER_AEMV8R_AARCH32 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "fvp_baser_aemv8r_aarch32" - -endif # BOARD_FVP_BASER_AEMV8R_AARCH32 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/board.cmake b/boards/arm/fvp_baser_aemv8r_aarch32/board.cmake deleted file mode 100644 index 2007c20e5cafa1..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/board.cmake +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS armfvp) -set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R) - -set(ARMFVP_FLAGS - -C cluster0.has_aarch64=0 - -C cluster0.VMSA_supported=0 - -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} - -C cluster0.gicv3.cpuintf-mmap-access-level=2 - -C cluster0.gicv3.SRE-enable-action-on-mmap=2 - -C cluster0.gicv3.SRE-EL2-enable-RAO=1 - -C cluster0.gicv3.extended-interrupt-range-support=1 - -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 - -C gic_distributor.has-two-security-states=0 - -C bp.refcounter.non_arch_start_at_default=1 - # UART0 config - -C bp.pl011_uart0.out_file=- - -C bp.pl011_uart0.unbuffered_output=1 - -C bp.terminal_0.start_telnet=0 - # UART1 config - -C bp.pl011_uart1.out_file=- - -C bp.pl011_uart1.unbuffered_output=1 - -C bp.terminal_1.start_telnet=0 - # UART2 config - -C bp.pl011_uart2.out_file=- - -C bp.pl011_uart2.unbuffered_output=1 - -C bp.terminal_2.start_telnet=0 - # UART3 config - -C bp.pl011_uart3.out_file=- - -C bp.pl011_uart3.unbuffered_output=1 - -C bp.terminal_3.start_telnet=0 - - -C bp.vis.disable_visualisation=1 - -C bp.vis.rate_limit-enable=0 - -C cache_state_modelled=0 - ) diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml deleted file mode 100644 index 23fc5a434c2a6e..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r_aarch32 -name: FVP Emulation FVP_BaseR_AEMv8R AArch32 -arch: arm -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -testing: - timeout_multiplier: 15 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_defconfig b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_defconfig deleted file mode 100644 index 034a1ed5014961..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y -CONFIG_SOC_FVP_AEMV8R_AARCH32=y -CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y -CONFIG_ARM_MPU=y - -CONFIG_ISR_STACK_SIZE=1024 -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE=n diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.dts b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.dts deleted file mode 100644 index cdc0a933ba373f..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.dts +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "fvp_baser_aemv8r_aarch32.dts" diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.yaml b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.yaml deleted file mode 100644 index 0ecd14f9076d12..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp.yaml +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r_aarch32_smp -name: FVP Emulation FVP_BaseR_AEMv8R AArch32 (SMP) -arch: arm -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -testing: - timeout_multiplier: 25 diff --git a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig b/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig deleted file mode 100644 index 3f7f981b46e7eb..00000000000000 --- a/boards/arm/fvp_baser_aemv8r_aarch32/fvp_baser_aemv8r_aarch32_smp_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R_AARCH32=y -CONFIG_SOC_FVP_AEMV8R_AARCH32=y -CONFIG_BOARD_FVP_BASER_AEMV8R_AARCH32=y -CONFIG_ARM_MPU=y - -CONFIG_ISR_STACK_SIZE=1024 -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CACHE_MANAGEMENT=y - -CONFIG_USE_SWITCH=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 - -CONFIG_DCACHE=n diff --git a/boards/arm/gd32a503v_eval/Kconfig.board b/boards/arm/gd32a503v_eval/Kconfig.board deleted file mode 100644 index 827b0b4dcb818c..00000000000000 --- a/boards/arm/gd32a503v_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32A503V_EVAL - bool "GigaDevice GD32A503V-EVAL" - depends on SOC_GD32A503 diff --git a/boards/arm/gd32a503v_eval/Kconfig.defconfig b/boards/arm/gd32a503v_eval/Kconfig.defconfig deleted file mode 100644 index 7c0c1ad2b7002b..00000000000000 --- a/boards/arm/gd32a503v_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32A503V_EVAL - -config BOARD - default "gd32a503v_eval" - -endif # BOARD_GD32A503V_EVAL diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig b/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig deleted file mode 100644 index dfcc85ee1e1b83..00000000000000 --- a/boards/arm/gd32a503v_eval/gd32a503v_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32A50X=y -CONFIG_SOC_GD32A503=y -CONFIG_BOARD_GD32A503V_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32e103v_eval/Kconfig.board b/boards/arm/gd32e103v_eval/Kconfig.board deleted file mode 100644 index 848f4d82a6a363..00000000000000 --- a/boards/arm/gd32e103v_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32E103V_EVAL - bool "GigaDevice GD32E103V Evaluation Kit" - depends on SOC_GD32E103 diff --git a/boards/arm/gd32e103v_eval/Kconfig.defconfig b/boards/arm/gd32e103v_eval/Kconfig.defconfig deleted file mode 100644 index 4681d2b2464a5d..00000000000000 --- a/boards/arm/gd32e103v_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32E103V_EVAL - -config BOARD - default "gd32e103v_eval" - -endif # BOARD_GD32E103V_EVAL diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig b/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig deleted file mode 100644 index 6af9eba773fc3f..00000000000000 --- a/boards/arm/gd32e103v_eval/gd32e103v_eval_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021, YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32E10X=y -CONFIG_SOC_GD32E103=y -CONFIG_BOARD_GD32E103V_EVAL=y - -CONFIG_GD32_HXTAL_8MHZ=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/gd32e507v_start/Kconfig.board b/boards/arm/gd32e507v_start/Kconfig.board deleted file mode 100644 index 427e3c414acdb3..00000000000000 --- a/boards/arm/gd32e507v_start/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32E507V_START - bool "GigaDevice GD32E507V-START" - depends on SOC_GD32E507 diff --git a/boards/arm/gd32e507v_start/Kconfig.defconfig b/boards/arm/gd32e507v_start/Kconfig.defconfig deleted file mode 100644 index c5ca16fd25be6c..00000000000000 --- a/boards/arm/gd32e507v_start/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32E507V_START - -config BOARD - default "gd32e507v_start" - -endif # BOARD_GD32E507V_START diff --git a/boards/arm/gd32e507v_start/gd32e507v_start_defconfig b/boards/arm/gd32e507v_start/gd32e507v_start_defconfig deleted file mode 100644 index 581cdd712b1018..00000000000000 --- a/boards/arm/gd32e507v_start/gd32e507v_start_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32E50X=y -CONFIG_SOC_GD32E507=y -CONFIG_BOARD_GD32E507V_START=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32e507z_eval/Kconfig.board b/boards/arm/gd32e507z_eval/Kconfig.board deleted file mode 100644 index 0b9208ff8b7913..00000000000000 --- a/boards/arm/gd32e507z_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32E507Z_EVAL - bool "GigaDevice GD32E507Z-EVAL" - depends on SOC_GD32E507 diff --git a/boards/arm/gd32e507z_eval/Kconfig.defconfig b/boards/arm/gd32e507z_eval/Kconfig.defconfig deleted file mode 100644 index 39e067ed59eead..00000000000000 --- a/boards/arm/gd32e507z_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32E507Z_EVAL - -config BOARD - default "gd32e507z_eval" - -endif # BOARD_GD32E507Z_EVAL diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval_defconfig b/boards/arm/gd32e507z_eval/gd32e507z_eval_defconfig deleted file mode 100644 index c6b1f6ad32ca3a..00000000000000 --- a/boards/arm/gd32e507z_eval/gd32e507z_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32E50X=y -CONFIG_SOC_GD32E507=y -CONFIG_BOARD_GD32E507Z_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f350r_eval/Kconfig.board b/boards/arm/gd32f350r_eval/Kconfig.board deleted file mode 100644 index b4fbc6635f7c80..00000000000000 --- a/boards/arm/gd32f350r_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F350R_EVAL - bool "GigaDevice GD32F350R Evaluation Kit" - depends on SOC_GD32F350 diff --git a/boards/arm/gd32f350r_eval/Kconfig.defconfig b/boards/arm/gd32f350r_eval/Kconfig.defconfig deleted file mode 100644 index 1de5675fb9cd13..00000000000000 --- a/boards/arm/gd32f350r_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F350R_EVAL - -config BOARD - default "gd32f350r_eval" - -endif # BOARD_GD32F350R_EVAL diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig b/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig deleted file mode 100644 index dfb61c38eb2adb..00000000000000 --- a/boards/arm/gd32f350r_eval/gd32f350r_eval_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F3X0=y -CONFIG_SOC_GD32F350=y -CONFIG_BOARD_GD32F350R_EVAL=y - - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/gd32f403z_eval/Kconfig.board b/boards/arm/gd32f403z_eval/Kconfig.board deleted file mode 100644 index 97273a13f995a2..00000000000000 --- a/boards/arm/gd32f403z_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F403Z_EVAL - bool "GigaDevice GD32F403Z Evaluation Kit" - depends on SOC_GD32F403 diff --git a/boards/arm/gd32f403z_eval/Kconfig.defconfig b/boards/arm/gd32f403z_eval/Kconfig.defconfig deleted file mode 100644 index 39f1df8e537649..00000000000000 --- a/boards/arm/gd32f403z_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F403Z_EVAL - -config BOARD - default "gd32f403z_eval" - -endif # BOARD_GD32F403Z_EVAL diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig b/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig deleted file mode 100644 index 759c53a00ad67e..00000000000000 --- a/boards/arm/gd32f403z_eval/gd32f403z_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F403=y -CONFIG_SOC_GD32F403=y -CONFIG_BOARD_GD32F403Z_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f407v_start/Kconfig.board b/boards/arm/gd32f407v_start/Kconfig.board deleted file mode 100644 index 541f1642e93129..00000000000000 --- a/boards/arm/gd32f407v_start/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F407V_START - bool "GigaDevice GD32F407V-START" - depends on SOC_GD32F407 diff --git a/boards/arm/gd32f407v_start/Kconfig.defconfig b/boards/arm/gd32f407v_start/Kconfig.defconfig deleted file mode 100644 index 888179c2f62311..00000000000000 --- a/boards/arm/gd32f407v_start/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F407V_START - -config BOARD - default "gd32f407v_start" - -endif # BOARD_GD32F407V_START diff --git a/boards/arm/gd32f407v_start/gd32f407v_start_defconfig b/boards/arm/gd32f407v_start/gd32f407v_start_defconfig deleted file mode 100644 index 1b9e3ff5e18b79..00000000000000 --- a/boards/arm/gd32f407v_start/gd32f407v_start_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F407=y -CONFIG_BOARD_GD32F407V_START=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f450i_eval/Kconfig.board b/boards/arm/gd32f450i_eval/Kconfig.board deleted file mode 100644 index 257da26fd035cb..00000000000000 --- a/boards/arm/gd32f450i_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F450I_EVAL - bool "GigaDevice GD32F450I-EVAL" - depends on SOC_GD32F450 diff --git a/boards/arm/gd32f450i_eval/Kconfig.defconfig b/boards/arm/gd32f450i_eval/Kconfig.defconfig deleted file mode 100644 index 3d7624c751e5d5..00000000000000 --- a/boards/arm/gd32f450i_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F450I_EVAL - -config BOARD - default "gd32f450i_eval" - -endif # BOARD_GD32F450I_EVAL diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig b/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig deleted file mode 100644 index 57db7c521eb58a..00000000000000 --- a/boards/arm/gd32f450i_eval/gd32f450i_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F450=y -CONFIG_BOARD_GD32F450I_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f450v_start/Kconfig.board b/boards/arm/gd32f450v_start/Kconfig.board deleted file mode 100644 index 7bd8cfbab73a89..00000000000000 --- a/boards/arm/gd32f450v_start/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F450V_START - bool "GigaDevice GD32F450V-START" - depends on SOC_GD32F450 diff --git a/boards/arm/gd32f450v_start/Kconfig.defconfig b/boards/arm/gd32f450v_start/Kconfig.defconfig deleted file mode 100644 index 3db890ec9d4a51..00000000000000 --- a/boards/arm/gd32f450v_start/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F450V_START - -config BOARD - default "gd32f450v_start" - -endif # BOARD_GD32F450V_START diff --git a/boards/arm/gd32f450v_start/gd32f450v_start_defconfig b/boards/arm/gd32f450v_start/gd32f450v_start_defconfig deleted file mode 100644 index 0767cf26db1d59..00000000000000 --- a/boards/arm/gd32f450v_start/gd32f450v_start_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F450=y -CONFIG_BOARD_GD32F450V_START=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f450z_eval/Kconfig.board b/boards/arm/gd32f450z_eval/Kconfig.board deleted file mode 100644 index 70ced41611024f..00000000000000 --- a/boards/arm/gd32f450z_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F450Z_EVAL - bool "GigaDevice GD32F450Z-EVAL" - depends on SOC_GD32F450 diff --git a/boards/arm/gd32f450z_eval/Kconfig.defconfig b/boards/arm/gd32f450z_eval/Kconfig.defconfig deleted file mode 100644 index 5c2ecc08b517e4..00000000000000 --- a/boards/arm/gd32f450z_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F450Z_EVAL - -config BOARD - default "gd32f450z_eval" - -endif # BOARD_GD32F450Z_EVAL diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval_defconfig b/boards/arm/gd32f450z_eval/gd32f450z_eval_defconfig deleted file mode 100644 index 59bc8e32ded2f3..00000000000000 --- a/boards/arm/gd32f450z_eval/gd32f450z_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F450=y -CONFIG_BOARD_GD32F450Z_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32f470i_eval/Kconfig.board b/boards/arm/gd32f470i_eval/Kconfig.board deleted file mode 100644 index e860b81a403526..00000000000000 --- a/boards/arm/gd32f470i_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32F470I_EVAL - bool "GigaDevice GD32F470I-EVAL" - depends on SOC_GD32F470 diff --git a/boards/arm/gd32f470i_eval/Kconfig.defconfig b/boards/arm/gd32f470i_eval/Kconfig.defconfig deleted file mode 100644 index 89cf5c68842d8d..00000000000000 --- a/boards/arm/gd32f470i_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32F470I_EVAL - -config BOARD - default "gd32f470i_eval" - -endif # BOARD_GD32F470I_EVAL diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval_defconfig b/boards/arm/gd32f470i_eval/gd32f470i_eval_defconfig deleted file mode 100644 index 9a6f3a893d6e3e..00000000000000 --- a/boards/arm/gd32f470i_eval/gd32f470i_eval_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32F4XX=y -CONFIG_SOC_GD32F470=y -CONFIG_BOARD_GD32F470I_EVAL=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -CONFIG_GPIO=y diff --git a/boards/arm/gd32l233r_eval/Kconfig.board b/boards/arm/gd32l233r_eval/Kconfig.board deleted file mode 100644 index 9ef6680e915134..00000000000000 --- a/boards/arm/gd32l233r_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32L233R_EVAL - bool "GigaDevice GD32L233R Evaluation Kit" - depends on SOC_GD32L233 diff --git a/boards/arm/gd32l233r_eval/Kconfig.defconfig b/boards/arm/gd32l233r_eval/Kconfig.defconfig deleted file mode 100644 index 2d25f793d38929..00000000000000 --- a/boards/arm/gd32l233r_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32L233R_EVAL - -config BOARD - default "gd32l233r_eval" - -endif # BOARD_GD32L233R_EVAL diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval_defconfig b/boards/arm/gd32l233r_eval/gd32l233r_eval_defconfig deleted file mode 100644 index 866f00cfabbad7..00000000000000 --- a/boards/arm/gd32l233r_eval/gd32l233r_eval_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32L23X=y -CONFIG_SOC_GD32L233=y -CONFIG_BOARD_GD32L233R_EVAL=y - -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/google_dragonclaw/Kconfig.board b/boards/arm/google_dragonclaw/Kconfig.board deleted file mode 100644 index 6a558693dcf287..00000000000000 --- a/boards/arm/google_dragonclaw/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GOOGLE_DRAGONCLAW - bool "Google Dragonclaw Development Board" - depends on SOC_STM32F412CX diff --git a/boards/arm/google_dragonclaw/Kconfig.defconfig b/boards/arm/google_dragonclaw/Kconfig.defconfig deleted file mode 100644 index 646e28fd70b31b..00000000000000 --- a/boards/arm/google_dragonclaw/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GOOGLE_DRAGONCLAW - -config BOARD - default "google_dragonclaw" - -endif # BOARD_GOOGLE_DRAGONCLAW diff --git a/boards/arm/google_kukui/Kconfig.board b/boards/arm/google_kukui/Kconfig.board deleted file mode 100644 index d3585a6bc2baef..00000000000000 --- a/boards/arm/google_kukui/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Google Kukui EC - -# Copyright 2019 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GOOGLE_KUKUI - bool "Google Kukui EC" - depends on SOC_STM32F098XX - help - This is the EC (Embedded Controller) inside a Lenovo Chromebook - Duet and 10e Chromebook Tablet. The EC handles battery charging, - keyboard scanning, USB Power Delivery and sensors. - - So far for Zephyr only a simple serial console and I2C are supported. diff --git a/boards/arm/google_kukui/Kconfig.defconfig b/boards/arm/google_kukui/Kconfig.defconfig deleted file mode 100644 index dc735470a35bf6..00000000000000 --- a/boards/arm/google_kukui/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Google Kukui EC - -# Copyright 2019 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GOOGLE_KUKUI - -config BOARD - default "google_kukui" - -endif # BOARD_GOOGLE_KUKUI diff --git a/boards/arm/google_kukui/doc/index.rst b/boards/arm/google_kukui/doc/index.rst deleted file mode 100644 index 434541c4f6a15e..00000000000000 --- a/boards/arm/google_kukui/doc/index.rst +++ /dev/null @@ -1,88 +0,0 @@ -.. _google_kukui_board: - -Google Kukui EC -############### - -Overview -******** - -Kukui is a reference board for Chromium OS-based devices Krane and -Kodama. These are known as the Lenovo Chromebook Duet and 10e Chromebook -Tablet, respectively. - -Zephyr has support for the STM32-based embedded controller (EC) on-board. - -Hardware -******** - -- STM32F098RCH6 -- MT6370 battery charger -- BMM150 compass -- BMM160 gyroscope -- Connections to the MediaTek AP - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other features (such as I2C) are not available in Zephyr. - -The default configuration can be found in the defconfig file: -``boards/arm/google_kukui/google_kukui_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output -(push-pull or open-drain), as input (with or without pull-up or -pull-down), or as peripheral alternate function. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA10/PA9 -- I2C_1 SCL/SDA : PB8/PB9 -- I2C_2 SCL/SDA : PA11/PA12 -- Volume down : GPIOB pin 11 -- Volume up : GPIOB pin 10 -- Power : GPIOA pin 0 - -Programming and Debugging -************************* - -Build application as usual for the ``google_kukui`` board, and flash -using Servo V2, μServo, or Servo V4 (CCD). See the -`Chromium EC Flashing Documentation`_ for more information. - -Debugging -========= - -Use SWD with a J-Link or ST-Link. - -References -********** - -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/google_kukui/google_kukui_defconfig b/boards/arm/google_kukui/google_kukui_defconfig deleted file mode 100644 index 3390acdaec5357..00000000000000 --- a/boards/arm/google_kukui/google_kukui_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F098XX=y -CONFIG_BOARD_GOOGLE_KUKUI=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/google_twinkie_v2/Kconfig.board b/boards/arm/google_twinkie_v2/Kconfig.board deleted file mode 100644 index 45f571ca2b0640..00000000000000 --- a/boards/arm/google_twinkie_v2/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2023 The ChromiumOS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GOOGLE_TWINKIE_V2 - bool "Google Twinkie V2 Board" - depends on SOC_STM32G0B1XX diff --git a/boards/arm/google_twinkie_v2/Kconfig.defconfig b/boards/arm/google_twinkie_v2/Kconfig.defconfig deleted file mode 100644 index 16350500a23234..00000000000000 --- a/boards/arm/google_twinkie_v2/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2023 The ChromiumOS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GOOGLE_TWINKIE_V2 - -config BOARD - default "google_twinkie_v2" - -endif # BOARD_GOOGLE_TWINKIE_V2 diff --git a/boards/arm/google_twinkie_v2/doc/index.rst b/boards/arm/google_twinkie_v2/doc/index.rst deleted file mode 100644 index 216e5747b7fc08..00000000000000 --- a/boards/arm/google_twinkie_v2/doc/index.rst +++ /dev/null @@ -1,57 +0,0 @@ -.. _google_twinkie_v2_board: - -Google Twinkie V2 -################# - -Overview -******** - -Google Twinkie V2 is a reference board for the google power delivery analyzer -(PDA) Twinkie V2. - -Hardware -******** - -- STM32G0B1REI6 - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig`` - -Pin Mapping -=========== - -Default Zephyr Peripheral Mapping: ----------------------------------- -- CC1_BUF : PA1 -- CC2_BUF : PA3 -- VBUS_READ_BUF : PB11 -- CSA_VBUS : PC4 -- CSA_CC2 : PC5 - -Programming and Debugging -************************* - -Build application as usual for the ``google_twinkie_v2`` board, and flash -using dfu-util or J-Link. - -Debugging -========= - -Use SWD with a J-Link or ST-Link. diff --git a/boards/arm/hexiwear_k64/Kconfig.board b/boards/arm/hexiwear_k64/Kconfig.board deleted file mode 100644 index 664294d51adc57..00000000000000 --- a/boards/arm/hexiwear_k64/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Hexiwear K64 board - -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HEXIWEAR_K64 - bool "NXP Hexiwear K64" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK64FN1M0VDC12 diff --git a/boards/arm/hexiwear_k64/Kconfig.defconfig b/boards/arm/hexiwear_k64/Kconfig.defconfig deleted file mode 100644 index 8c00ebed8fc148..00000000000000 --- a/boards/arm/hexiwear_k64/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Hexiwear K64 board - -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HEXIWEAR_K64 - -config BOARD - default "hexiwear_k64" - -config OSC_XTAL0_FREQ - default 12000000 - -config MCG_PRDIV0 - default 0x02 - -config MCG_VDIV0 - default 0x06 - -config MCG_FCRDIV - default 1 - -config REGULATOR - default y if ADC || SENSOR - -endif # BOARD_HEXIWEAR_K64 diff --git a/boards/arm/hexiwear_k64/board.cmake b/boards/arm/hexiwear_k64/board.cmake deleted file mode 100644 index 487cfeb0d0d7ca..00000000000000 --- a/boards/arm/hexiwear_k64/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(pyocd "--target=k64f") -board_runner_args(jlink "--device=MK64FN1M0xxx12") - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/hexiwear_k64/doc/index.rst b/boards/arm/hexiwear_k64/doc/index.rst deleted file mode 100644 index c9a9d03044a9ea..00000000000000 --- a/boards/arm/hexiwear_k64/doc/index.rst +++ /dev/null @@ -1,336 +0,0 @@ -.. _hexiwear_k64: - -Hexiwear -######## - -Overview -******** - -Hexiwear is powered by a Kinetis K64 microcontroller based on the ARM Cortex-M4 -core. Another Kinetis wireless MCU, the KW40Z, provides Bluetooth Low Energy -connectivity. Hexiwear also integrates a wide variety of sensors, as well as a -user interface consisting of a 1.1" 96px x 96px full color OLED display and six -capacitive buttons with haptic feedback. - -- Eye-catching Smart Watch form factor with powerful, low power Kinetis K6x MCU - and 6 on-board sensors. -- Designed for wearable applications with the onboard rechargeable battery, - OLED screen and onboard sensors such as optical heart rate, accelerometer, - magnetometer and gyroscope. -- Designed for IoT end node applications with the onboard sensor's such as - temperature, pressure, humidity and ambient light. -- Flexibility to let you add the sensors of your choice nearly 200 additional - sensors through click boards. - -.. image:: hexiwear_k64.jpg - :align: center - :alt: Hexiwear - -Hardware -******** - -- Main MCU: NXP Kinetis K64x (ARM Cortex-M4, 120 MHz, 1M Flash, 256K SRAM) -- Wireless MCU: NXP Kinetis KW4x (ARM Cortex-M0+, Bluetooth Low Energy & - 802.15.4 radio) -- 6-axis combo Accelerometer and Magnetometer NXP FXOS8700 -- 3-Axis Gyroscope: NXP FXAS21002 -- Absolute Pressure sensor NXP MPL3115 -- Li-Ion/Li-Po Battery Charger NXP MC34671 -- Optical heart rate sensor Maxim MAX30101 -- Ambient Light sensor, Humidity and Temperature sensor -- 1.1" full color OLED display -- Haptic feedback engine -- 190 mAh 2C Li-Po battery -- Capacitive touch interface -- RGB LED - -For more information about the K64F SoC and Hexiwear board: - -- `K64F Website`_ -- `K64F Datasheet`_ -- `K64F Reference Manual`_ -- `Hexiwear Website`_ -- `Hexiwear Fact Sheet`_ -- `Hexiwear Schematics`_ - -Supported Features -================== - -The hexiwear_k64 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -| | | fxas21002 polling; | -| | | fxas21002 trigger; | -| | | max30101 polling | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/hexiwear_k64/hexiwear_k64_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The K64F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTA29 | GPIO | LDO_EN | -+-------+-----------------+---------------------------+ -| PTB0 | I2C0_SCL | I2C / MAX30101 | -+-------+-----------------+---------------------------+ -| PTB1 | I2C0_SDA | I2C / MAX30101 | -+-------+-----------------+---------------------------+ -| PTB12 | GPIO | 3V3B EN | -+-------+-----------------+---------------------------+ -| PTB16 | UART0_RX | UART Console | -+-------+-----------------+---------------------------+ -| PTB17 | UART0_TX | UART Console | -+-------+-----------------+---------------------------+ -| PTC8 | GPIO / PWM | Red LED | -+-------+-----------------+---------------------------+ -| PTC9 | GPIO / PWM | Green LED | -+-------+-----------------+---------------------------+ -| PTC10 | I2C1_SCL | I2C / FXOS8700 / FXAS21002| -+-------+-----------------+---------------------------+ -| PTC11 | I2C1_SDA | I2C / FXOS8700 / FXAS21002| -+-------+-----------------+---------------------------+ -| PTC14 | GPIO | Battery sense enable | -+-------+-----------------+---------------------------+ -| PTC18 | GPIO | FXAS21002 INT2 | -+-------+-----------------+---------------------------+ -| PTD0 | GPIO / PWM | Blue LED | -+-------+-----------------+---------------------------+ -| PTD13 | GPIO | FXOS8700 INT2 | -+-------+-----------------+---------------------------+ -| PTE24 | UART4_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTE25 | UART4_TX | UART BT HCI | -+-------+-----------------+---------------------------+ - -.. note:: - - To enable battery sensing, you will need to enable the ``en_bat_sens`` - regulator in Devicetree. Similarly, to enable devices connected to the 1V8 - or 3V3 power rails (sensors), you will need to enable the ``en_ldo`` - and ``en_3v3b`` regulators in Devicetree. - -System Clock -============ - -The K64F SoC is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The K64F SoC has six UARTs. One is configured for the console, another for BT -HCI, and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -but because Segger RTT is required for a console on KW40Z, we recommend that -you reconfigure the board for the :ref:`opensda-jlink-onboard-debug-probe`. - -.. note:: - OpenSDA is shared between the K64 and the KW40Z via switches, therefore only - one SoC can be flashed, debugged, or have an open console at a time. - -Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) ----------------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches -SW1 and SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals -are connected to the OpenSDA microcontroller. - -Option 2: :ref:`opensda-daplink-onboard-debug-probe` ----------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to -program the `OpenSDA DAPLink Hexiwear Firmware`_. Check that switches SW1 and -SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals are -connected to the OpenSDA microcontroller. - -Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and -``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the -default runner from J-Link to pyOCD: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_k64 - :gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to CN1. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_k64 - :goals: flash - -Open a serial terminal, reset the board (press the T4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_k64 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_k64 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_k64 - -Using Bluetooth -*************** - -Configure the KW40Z as a Bluetooth controller -============================================= - -The K64 can support Zephyr Bluetooth host applications when you configure the -KW40Z as a Bluetooth controller. - -#. Download and install the `KW40Z Connectivity Software`_. This package - contains Bluetooth controller application for the KW40Z. -#. Flash the file ``tools/binaries/BLE_HCI_Modem.bin`` to the KW40Z. - -Now you can build and run the sample Zephyr Bluetooth host applications on the -K64. You do not need to repeat this step each time you flash a new Bluetooth -host application to the K64. - -Peripheral Heart Rate Sensor -============================ - -Navigate to the Zephyr ``samples/bluetooth/peripheral_hr`` sample -application, then build and flash it to the Hexiwear K64. Make sure -the OpenSDA switches on the docking station are configured for the -K64. - -.. zephyr-app-commands:: - :zephyr-app: samples/bluetooth/peripheral_hr - :board: hexiwear_k64 - :goals: build flash - -Reset the KW40Z and the K64 using the push buttons on the docking station. - -Install the Kinetis BLE Toolbox on your smartphone: - -- `Kinetis BLE Toolbox for iOS`_ -- `Kinetis BLE Toolbox for Android`_ - -Open the app, tap the **Heart Rate** feature, and you should see a **Zephyr -Heartrate Sensor** device. Tap the **Zephyr Heartrate Sensor** device and you -will then see a plot of the heart rate data that updates once per second. - - -.. _Hexiwear Website: - https://www.mikroe.com/hexiwear - -.. _Hexiwear Fact Sheet: - https://www.nxp.com/docs/en/fact-sheet/HEXIWEAR-FS.pdf - -.. _Hexiwear Schematics: - http://cdn-docs.mikroe.com/images/c/c0/Sch_Hexiwear_MainBoard_v106c.pdf - -.. _K64F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 - -.. _K64F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf - -.. _K64F Reference Manual: - https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf - -.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1 - -.. _OpenSDA DAPLink Hexiwear Firmware: - https://github.com/MikroElektronika/HEXIWEAR/blob/master/HW/HEXIWEAR_DockingStation/HEXIWEAR_DockingStation_DAPLINK_FW.bin - -.. _KW40Z Connectivity Software: - https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&location=null&fpsp=1&WT_TYPE=Protocol%20Stacks&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=exe&WT_ASSET=Downloads&fileExt=.exe&Parent_nodeId=1432854896956716810497&Parent_pageType=product - -.. _Kinetis BLE Toolbox for iOS: - https://itunes.apple.com/us/app/kinetis-ble-toolbox/id1049036961?mt=8 - -.. _Kinetis BLE Toolbox for Android: - https://play.google.com/store/apps/details?id=com.freescale.kinetisbletoolbox diff --git a/boards/arm/hexiwear_k64/hexiwear_k64.dts b/boards/arm/hexiwear_k64/hexiwear_k64.dts deleted file mode 100644 index 133acf81b4c559..00000000000000 --- a/boards/arm/hexiwear_k64/hexiwear_k64.dts +++ /dev/null @@ -1,209 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include -#include -#include "hexiwear_k64-pinctrl.dtsi" - -/ { - model = "Hexiwear K64 board"; - compatible = "nxp,hexiwear", "nxp,k64f", "nxp,k6x"; - - aliases { - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - pwm-led0 = &green_pwm_led; - red-pwm-led = &red_pwm_led; - green-pwm-led = &green_pwm_led; - blue-pwm-led = &blue_pwm_led; - magn0 = &fxos8700; - accel0 = &fxos8700; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,bt-uart = &uart4; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_0 { - gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; - label = "User LD1"; - }; - green_led: led_1 { - gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; - label = "User LD2"; - }; - blue_led: led_2 { - gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; - label = "User LD3"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - - red_pwm_led: red_pwm_led { - pwms = <&ftm3 4 15625000 PWM_POLARITY_INVERTED>; - }; - green_pwm_led: green_pwm_led { - pwms = <&ftm3 0 15625000 PWM_POLARITY_INVERTED>; - }; - blue_pwm_led: blue_pwm_led { - pwms = <&ftm3 5 15625000 PWM_POLARITY_INVERTED>; - }; - }; - - en_bat_sens: enable-battery-sense { - compatible = "regulator-fixed"; - regulator-name = "en_bat_sens"; - enable-gpios = <&gpioc 14 GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; - - en_ldo: enable-ldo { - compatible = "regulator-fixed"; - regulator-name = "en_ldo"; - enable-gpios = <&gpioa 29 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - en_3v3b: enable-3v3b { - compatible = "regulator-fixed"; - regulator-name = "en_3v3b"; - enable-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; - regulator-boot-on; - }; -}; - -&sim { - pllfll-select = ; - er32k-select = ; -}; - -&cpu0 { - clock-frequency = <120000000>; -}; - -&adc0 { - status = "okay"; -}; - -&adc1 { - status = "okay"; -}; - -&ftm3 { - status = "okay"; - compatible = "nxp,kinetis-ftm-pwm"; - #pwm-cells = <3>; - pinctrl-0 = <&ftm3_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - - max30101@57 { - status = "disabled"; - compatible = "maxim,max30101"; - reg = <0x57>; - }; -}; - -&i2c1 { - status = "okay"; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; - int2-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; - }; - - fxas21002@20 { - compatible = "nxp,fxas21002"; - reg = <0x20>; - int1-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>; - int2-gpios = <&gpioc 18 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpioa { - status = "okay"; -}; - -&gpiob { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; - -&gpiod { - status = "okay"; -}; - -&gpioe { - status = "okay"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* - * The flash starting at 0x00010000 and ending at - * 0x0001ffff (sectors 16-31) is reserved for use - * by the application. - */ - - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x00060000>; - }; - slot1_partition: partition@80000 { - label = "image-1"; - reg = <0x00080000 0x00060000>; - }; - scratch_partition: partition@e0000 { - label = "image-scratch"; - reg = <0x000e0000 0x00020000>; - }; - }; -}; diff --git a/boards/arm/hexiwear_k64/hexiwear_k64.yaml b/boards/arm/hexiwear_k64/hexiwear_k64.yaml deleted file mode 100644 index c14e75c35da9b2..00000000000000 --- a/boards/arm/hexiwear_k64/hexiwear_k64.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: hexiwear_k64 -name: Hexiwear -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - ble - - gpio - - i2c - - pwm - - watchdog -vendor: nxp diff --git a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig b/boards/arm/hexiwear_k64/hexiwear_k64_defconfig deleted file mode 100644 index 6a9303f32be6b5..00000000000000 --- a/boards/arm/hexiwear_k64/hexiwear_k64_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_MK64F12=y -CONFIG_SOC_SERIES_KINETIS_K6X=y -CONFIG_BOARD_HEXIWEAR_K64=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 -CONFIG_OSC_LOW_POWER=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/hexiwear_kw40z/Kconfig.board b/boards/arm/hexiwear_kw40z/Kconfig.board deleted file mode 100644 index 10b0a98a443604..00000000000000 --- a/boards/arm/hexiwear_kw40z/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Hexiwear KW40Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HEXIWEAR_KW40Z - bool "Hexiwear KW40Z" - depends on SOC_SERIES_KINETIS_KWX - select SOC_PART_NUMBER_MKW40Z160VHT4 diff --git a/boards/arm/hexiwear_kw40z/Kconfig.defconfig b/boards/arm/hexiwear_kw40z/Kconfig.defconfig deleted file mode 100644 index ef4f65381a8452..00000000000000 --- a/boards/arm/hexiwear_kw40z/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Hexiwear KW40Z board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HEXIWEAR_KW40Z - -config BOARD - default "hexiwear_kw40z" - -config OSC_XTAL0_FREQ - default 32000000 - -config MCG_FRDIV - default 5 - -config MCG_FCRDIV - default 0 - -endif # BOARD_HEXIWEAR_KW40Z diff --git a/boards/arm/hexiwear_kw40z/board.cmake b/boards/arm/hexiwear_kw40z/board.cmake deleted file mode 100644 index a93baa325e6f33..00000000000000 --- a/boards/arm/hexiwear_kw40z/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=MKW40Z160xxx4") -board_runner_args(pyocd "--target=kw40z4") - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/hexiwear_kw40z/doc/index.rst b/boards/arm/hexiwear_kw40z/doc/index.rst deleted file mode 100644 index 269f1b931243f9..00000000000000 --- a/boards/arm/hexiwear_kw40z/doc/index.rst +++ /dev/null @@ -1,182 +0,0 @@ -.. _hexiwear_kw40z: - -Hexiwear KW40Z -############## - -Overview -******** - -See :ref:`hexiwear_k64` for a general overview of the Hexiwear board and the -main application SoC, the K64. The KW40Z is a secondary SoC on the board that -provides wireless connectivity with a multimode BLE and 802.15.4 radio. - -For more information about the KW40Z SoC: - -- `KW40Z Website`_ -- `KW40Z Datasheet`_ -- `KW40Z Reference Manual`_ - -Supported Features -================== - -The hexiwear_kw40z board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| RTT | on-chip | console | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KW40Z SoC has three pairs of pinmux/gpio controllers, but only one is -currently enabled (PORTC/GPIOC) for the hexiwear_kw40z board. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTB1 | ADC | ADC0 channel 1 | -+-------+-----------------+---------------------------+ -| PTC6 | UART0_RX | UART BT HCI | -+-------+-----------------+---------------------------+ -| PTC7 | UART0_TX | UART BT HCI | -+-------+-----------------+---------------------------+ - -System Clock -============ - -The KW40Z SoC is configured to use the 32 MHz external oscillator on the board -with the on-chip FLL to generate a 40 MHz system clock. - -Serial Port -=========== - -The KW40Z SoC has one UART, which is used for BT HCI. There is no UART -available for a console. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -but because Segger RTT is required for a console, you must reconfigure the -board for one of the following debug probes instead. - -:ref:`opensda-jlink-onboard-debug-probe` ----------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches -SW1 and SW2 are **off**, and SW3 and SW4 are **on** to ensure KW40Z SWD signals -are connected to the OpenSDA microcontroller. - -Configuring a Console -===================== - -The console is available using `Segger RTT`_. - -Connect a USB cable from your PC to CN1. - -Once you have started a debug session, run telnet: - -.. code-block:: console - - $ telnet localhost 19021 - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - SEGGER J-Link V6.44 - Real time terminal output - J-Link OpenSDA 2 compiled Feb 28 2017 19:27:57 V1.0, SN=621000000 - Process: JLinkGDBServerCLExe - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_kw40z - :goals: flash - -The Segger RTT console is only available during a debug session. Use ``attach`` -to start one: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_kw40z - :goals: attach - -Run telnet as shown earlier, and you should see the following message in the -terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_kw40z - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: hexiwear_kw40z - :goals: debug - -Run telnet as shown earlier, step through the application in your debugger, and -you should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! hexiwear_kw40z - -.. _KW40Z Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/kinetis-kw40z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW40Z - -.. _KW40Z Datasheet: - https://www.nxp.com/docs/en/data-sheet/MKW40Z160.pdf - -.. _KW40Z Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MKW40Z160RM - -.. _Segger RTT: - https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ - -.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V2_1 diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts b/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts deleted file mode 100644 index 2b64e0bafd534a..00000000000000 --- a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.dts +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include -#include "hexiwear_kw40z-pinctrl.dtsi" - -/ { - model = "Hexiwear KW40 board"; - compatible = "nxp,kw40z", "nxp,mkw40z4"; - - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; -}; - -&sim { - pllfll-select = ; - er32k-select = ; -}; - -&adc0 { - status = "okay"; - pinctrl-0 = <&adc0_default>; - pinctrl-names = "default"; -}; - -&lpuart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&lpuart0_default>; - pinctrl-names = "default"; -}; - -&gpioa { - status = "okay"; -}; - -&gpioc { - status = "okay"; -}; diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.yaml b/boards/arm/hexiwear_kw40z/hexiwear_kw40z.yaml deleted file mode 100644 index 0e5b493567367f..00000000000000 --- a/boards/arm/hexiwear_kw40z/hexiwear_kw40z.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: hexiwear_kw40z -name: Hexiwear KW40Z -type: mcu -arch: arm -ram: 16 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net -vendor: nxp diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig b/boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig deleted file mode 100644 index e7bb17ffa8eb01..00000000000000 --- a/boards/arm/hexiwear_kw40z/hexiwear_kw40z_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_MKW40Z4=y -CONFIG_SOC_SERIES_KINETIS_KWX=y -CONFIG_BOARD_HEXIWEAR_KW40Z=y -CONFIG_CONSOLE=y -CONFIG_RTT_CONSOLE=y -CONFIG_USE_SEGGER_RTT=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 -CONFIG_OSC_EXTERNAL=y diff --git a/boards/arm/holyiot_yj16019/Kconfig b/boards/arm/holyiot_yj16019/Kconfig deleted file mode 100644 index c6c54fa5a0024f..00000000000000 --- a/boards/arm/holyiot_yj16019/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Holyiot YJ-16019 board configuration - -# Copyright (c) 2019 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/holyiot_yj16019/Kconfig.board b/boards/arm/holyiot_yj16019/Kconfig.board deleted file mode 100644 index e49ebf908735f4..00000000000000 --- a/boards/arm/holyiot_yj16019/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Holyiot YJ-16019 board configuration - -# Copyright (c) 2019 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HOLYIOT_YJ16019 - bool "Holyiot YJ-16019" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/holyiot_yj16019/Kconfig.defconfig b/boards/arm/holyiot_yj16019/Kconfig.defconfig deleted file mode 100644 index de2d63ad7c8d62..00000000000000 --- a/boards/arm/holyiot_yj16019/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Holyiot YJ-16019 board configuration - -# Copyright (c) 2019 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HOLYIOT_YJ16019 - -config BOARD - default "holyiot_yj16019" - -config BT_CTLR - default BT - -endif # BOARD_HOLYIOT_YJ16019 diff --git a/boards/arm/holyiot_yj16019/doc/index.rst b/boards/arm/holyiot_yj16019/doc/index.rst deleted file mode 100644 index 57990be93a14fc..00000000000000 --- a/boards/arm/holyiot_yj16019/doc/index.rst +++ /dev/null @@ -1,147 +0,0 @@ -.. _holyiot_yj16019: - -Holyiot YJ-16019 -################ - -Overview -******** - -The `Holyiot`_ YJ-16019 hardware provides support for the Nordic -Semiconductor nRF52832 ARM Cortex-M4 CPU and the following devices: - -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/holyiot_yj16019_front.jpg - :align: center - :alt: Holyiot YJ-16019 - - Holyiot YJ-16019 (Credit: Holyiot) - -The board is equipped with one LED, one push button, and is powered by -a CR2032 coin cell. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -The nRF52832 of the Holyiot YJ-16019 is clocked by an external crystal with a frequency of 32 MHz -(Y1). The 32.768 kHz crystal (Y2) shown on the board schematics is not mounted. - -Supported Features -================== - -The holyiot_yj16019 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LED and push button -------------------- - -* Push button = P0.28 -* LED = P0.29 - -Programming and Debugging -************************* - -Applications for the ``holyiot_yj16019`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, an external -Segger J-Link is required since the board does not have any on-board -debug IC. - -The following pins of the Segger J-Link must be connected to the following test -pads on the PCB (see image): - -* VTref = VCC -* GND = GND -* SWDIO = SDO -* SWCLK = SCK - -.. figure:: img/holyiot_yj16019_pcb.jpg - :align: center - :alt: Holyiot YJ-16019 PCB - - Holyiot YJ-16019 PCB (Credit: Holyiot) - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: holyiot_yj16019 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -nRF52x-based boards with a Segger debugger. - - -Testing the LED and button on the Holyiot YJ-16019 -************************************************** - -There are 2 samples that allow you to test that the button and LED on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in :zephyr_file:`boards/arm/holyiot_yj16019/holyiot_yj16019.dts`. - -References -********** - -.. target-notes:: - -.. _Holyiot: http://www.holyiot.com -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019_defconfig b/boards/arm/holyiot_yj16019/holyiot_yj16019_defconfig deleted file mode 100644 index 7a5c82fbdc83fe..00000000000000 --- a/boards/arm/holyiot_yj16019/holyiot_yj16019_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_HOLYIOT_YJ16019=y - -# 32kHz clock source -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - -# Enable GPIO -CONFIG_GPIO=y diff --git a/boards/arm/index.rst b/boards/arm/index.rst index baeeffe8ae7d7c..a9e114281f156d 100644 --- a/boards/arm/index.rst +++ b/boards/arm/index.rst @@ -1,7 +1,7 @@ .. _boards-arm: -ARM Boards -########## +ARM Ltd. +######## .. toctree:: :maxdepth: 1 diff --git a/boards/arm/ip_k66f/Kconfig.board b/boards/arm/ip_k66f/Kconfig.board deleted file mode 100644 index ec73f2a88b1b8f..00000000000000 --- a/boards/arm/ip_k66f/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 DENX Software Engineering GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IP_K66F - bool "Segger IP-K66F" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK66FN2M0VMD18 diff --git a/boards/arm/ip_k66f/Kconfig.defconfig b/boards/arm/ip_k66f/Kconfig.defconfig deleted file mode 100644 index 2543e52684a103..00000000000000 --- a/boards/arm/ip_k66f/Kconfig.defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# IP-K66F board - -# Copyright (c) 2020 DENX Software Engineering GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IP_K66F - -config BOARD - default "ip_k66f" - -config OSC_XTAL0_FREQ - default 12000000 - -config MCG_PRDIV0 - default 0x0 - -config MCG_VDIV0 - default 0xe - -config MCG_FCRDIV - default 1 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -config ETH_MCUX_RMII_EXT_CLK - default y if ETH_MCUX - -config ETH_MCUX_NO_PHY_SMI - default y if ETH_MCUX - -endif # NETWORKING - -endif # BOARD_IP_K66F diff --git a/boards/arm/ip_k66f/doc/index.rst b/boards/arm/ip_k66f/doc/index.rst deleted file mode 100644 index eb8ee3b3e999e9..00000000000000 --- a/boards/arm/ip_k66f/doc/index.rst +++ /dev/null @@ -1,175 +0,0 @@ -.. _ip_k66f: - -SEGGER IP Switch Board -###################### - -Overview -******** - -The Segger IP Switch Board is a Evaluation board based on NXP Kinetis K66 MCU. -It comes with Micrel/Microchip KSZ8794CNX integrated 4-port 10/100 managed -Ethernet switch with Gigabit RGMII/MII/RMII interface. - -- KSZ8794CNX enables evaluation for switch functions -- On-board debug probe J-Link-OB for programming - -.. image:: ip_k66f.jpg - :align: center - :alt: IP-K66F - -Hardware -******** - -- MK66FN2M0VMD18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, - crystal-less USB -- Dual role USB interface with micro-B USB connector -- 2 User LED -- On-board debug probe J-Link-OB for programming -- Micrel/Microchip Ethernet Switch KSZ8794CNX with 3 RJ45 connectors - -For more information about the K66F SoC and IP-K66F board: - -- `K66F Website`_ -- `K66F Datasheet`_ -- `K66F Reference Manual`_ -- `IP-K66F Website`_ -- `IP-K66F User Guide`_ -- `IP-K66F Schematics`_ - -Supported Features -================== - -The ip_k66f board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/ip_k66f/ip_k66f_defconfig`` - -Micrel/Microchip KSZ8794CNX Ethernet Switch is not currently -supported. - -Connections and IOs -=================== - -The K66F SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+---------------------------+ -| Name | Function | Usage | -+=======+=================+===========================+ -| PTA8 | GPIO | Red LED | -+-------+-----------------+---------------------------+ -| PTA10 | GPIO | RED LED | -+-------+-----------------+---------------------------+ - -System Clock -============ - -The K66F SoC is configured to use the 12 MHz low gain crystal oscillator on the -board with the on-chip PLL to generate a 180 MHz system clock. - -Serial Port -=========== - -The K66F SoC has six UARTs. None of them are used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-jlink-onboard-debug-probe`. - -:ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Generic Firmware for V3.2 Bootloader`_. Note that Segger -does provide an OpenSDA J-Link Board-Specific Firmware for this board, however -it is not compatible with the DAPLink bootloader. - -The default flasher is ``jlink`` using the built-in SEGGER Jlink interface. - -Flashing -======== - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ip_k66f - :goals: flash - -Red LED0 should blink at 1 second delay. - -Debugging -========= - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ip_k66f - :goals: debug - -Step through the application in your debugger. - -.. _IP-K66F Website: - https://www.segger.com/evaluate-our-software/segger/embosip-switch-board/ - -.. _IP-K66F User Guide: - https://www.segger.com/downloads/emnet/UM06002 - -.. _IP-K66F Schematics: - https://www.segger.com/downloads/emnet/embOSIP_SwitchBoard_V2.0_WEB_Schematic.pdf - -.. _K66F Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 - -.. _K66F Datasheet: - https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf - -.. _K66F Reference Manual: - https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 - -.. _OpenSDA J-Link Generic Firmware for V3.2 Bootloader: - https://www.segger.com/downloads/jlink/OpenSDA_V3_2 - -Serial console -============== - -The ``ip_k66f`` board only uses Segger's RTT console for providing serial -console. There is no physical serial port available. - -- To communicate with this board one needs in one console: - -``/opt/SEGGER/JLink_V664/JLinkRTTLogger -Device MK66FN2M0XXX18 -RTTChannel 1 -if SWD -Speed 4000 ~/rtt.log`` - -- In another one: - -``nc localhost 19021`` diff --git a/boards/arm/kv260_r5/Kconfig.board b/boards/arm/kv260_r5/Kconfig.board deleted file mode 100644 index 8bd28d7f10fd6c..00000000000000 --- a/boards/arm/kv260_r5/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Linaro. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_KV260_R5 - bool "Xilinx KV260 development board R5-core" - depends on SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/kv260_r5/Kconfig.defconfig b/boards/arm/kv260_r5/Kconfig.defconfig deleted file mode 100644 index a9df885cc1aa23..00000000000000 --- a/boards/arm/kv260_r5/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Linaro. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_KV260_R5 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "board_kv260_r5" - -if USERSPACE - -config COMPILER_ISA_THUMB2 - default n - -endif - -endif # BOARD_KV260_R5 diff --git a/boards/arm/kv260_r5/kv260_r5_defconfig b/boards/arm/kv260_r5/kv260_r5_defconfig deleted file mode 100644 index 6eb51f3849df74..00000000000000 --- a/boards/arm/kv260_r5/kv260_r5_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_SOC_XILINX_ZYNQMP_RPU=y -CONFIG_BOARD_KV260_R5=y -CONFIG_XIP=n - -CONFIG_ISR_STACK_SIZE=512 -CONFIG_THREAD_STACK_INFO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable serial port -CONFIG_UART_XLNX_PS=y - -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_ARM_MPU=y diff --git a/boards/arm/legend/Kconfig.board b/boards/arm/legend/Kconfig.board deleted file mode 100644 index 6820a8c0dcd6d9..00000000000000 --- a/boards/arm/legend/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Legend board family configuration - -# Copyright (c) 2021 Seagate Technology -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LEGEND - bool "Legend board" - depends on SOC_STM32F070XB diff --git a/boards/arm/legend/Kconfig.defconfig b/boards/arm/legend/Kconfig.defconfig deleted file mode 100644 index 06c47f232fd8d8..00000000000000 --- a/boards/arm/legend/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Legend board family configuration - -# Copyright (c) 2021, Seagate Technology LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LEGEND - -config BOARD - default "legend" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_LEGEND diff --git a/boards/arm/legend/legend.yaml b/boards/arm/legend/legend.yaml deleted file mode 100644 index 1762e786318b8c..00000000000000 --- a/boards/arm/legend/legend.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: legend -name: Legend -type: mcu -arch: arm -ram: 16 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio - - i2c - - pwm - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: seagate diff --git a/boards/arm/legend/legend_defconfig b/boards/arm/legend/legend_defconfig deleted file mode 100644 index 1ab444cc39b05a..00000000000000 --- a/boards/arm/legend/legend_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F070XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Clock Control -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/lora_e5_dev_board/Kconfig.board b/boards/arm/lora_e5_dev_board/Kconfig.board deleted file mode 100644 index 78fd5de63cd8e1..00000000000000 --- a/boards/arm/lora_e5_dev_board/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# LoRa-E5 Dev board configuration - -# Copyright (c) 2021 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LORA_E5_DEV_BOARD - bool "LoRa E5 Development Board" - depends on SOC_STM32WLE5XX diff --git a/boards/arm/lora_e5_dev_board/Kconfig.defconfig b/boards/arm/lora_e5_dev_board/Kconfig.defconfig deleted file mode 100644 index 857cd45e6842fb..00000000000000 --- a/boards/arm/lora_e5_dev_board/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LoRa-E5 Dev board configuration - -# Copyright (c) 2021 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LORA_E5_DEV_BOARD - -config BOARD - default "lora_e5_dev_board" - -endif # BOARD_LORA_E5_DEV_BOARD diff --git a/boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig b/boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig deleted file mode 100644 index 912493764e21d8..00000000000000 --- a/boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WLE5XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable regulator for the power-rails -CONFIG_REGULATOR=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/lora_e5_mini/Kconfig.board b/boards/arm/lora_e5_mini/Kconfig.board deleted file mode 100644 index 1b4e30a54c4fa3..00000000000000 --- a/boards/arm/lora_e5_mini/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# LoRa-E5 mini configuration - -# Copyright (c) 2023 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LORA_E5_MINI - bool "LoRa E5 mini" - depends on SOC_STM32WLE5XX diff --git a/boards/arm/lora_e5_mini/Kconfig.defconfig b/boards/arm/lora_e5_mini/Kconfig.defconfig deleted file mode 100644 index ca35c4321a0979..00000000000000 --- a/boards/arm/lora_e5_mini/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LoRa-E5 mini configuration - -# Copyright (c) 2023 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LORA_E5_MINI - -config BOARD - default "lora_e5_mini" - -endif # BOARD_LORA_E5_MINI diff --git a/boards/arm/lora_e5_mini/board.cmake b/boards/arm/lora_e5_mini/board.cmake deleted file mode 100644 index ac24f811559b67..00000000000000 --- a/boards/arm/lora_e5_mini/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(pyocd "--target=stm32wle5jcix") -board_runner_args(pyocd "--flash-opt=-O reset_type=hw") -board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") -board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load") -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") -board_runner_args(blackmagicprobe "--connect-rst") - -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/arm/lora_e5_mini/doc/index.rst b/boards/arm/lora_e5_mini/doc/index.rst deleted file mode 100644 index 6e6be186dd773e..00000000000000 --- a/boards/arm/lora_e5_mini/doc/index.rst +++ /dev/null @@ -1,226 +0,0 @@ -.. _lora_e5_mini: - -Seeed Studio LoRa-E5 mini -######################### - -Overview -******** - -LoRa-E5 mini is a compacted-sized development board suitable for the rapid -testing and building of small-sized LoRa device, exposing all capabilities of -Seeed Studio LoRa-E5 STM32WLE5JC module. - -.. image:: img/lora_e5_mini.jpg - :align: center - :alt: LoRa-E5 mini - -Hardware -******** - -The boards' LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO, -and a 32.768kHz crystal oscillator in a 28-pin SMD package. -This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech -SX126X LoRa IP to support (G)FSK, BPSK, (G)MSK, and LoRa modulations. - -- LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core - 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package - featuring: - - - Ultra-low-power MCU - - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®, - (G)FSK, (G)MSK, and BPSK modulations - - 256-Kbyte Flash memory and 64-Kbyte SRAM - - Hardware encryption AES256-bit and a True random number generator - -- 1 user LED -- 2 serial communication (RX/TX) LEDs -- 1 boot/user and 1 reset push-button -- 32.768 kHz LSE crystal oscillator -- 32 MHz HSE oscillator -- Board connectors: - - - USB Type-C connector - - +/- (battery) power input pins (3-5V) - - SMA-K and IPEX antenna connectors - -- Delivered with SMA antenna (per default IPEX connector is disconnected) -- Flexible power-supply options: USB Type C or 3-5V battery soldered to +/- pins -- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus, - and many other proprietary protocols -- All GPIOs led out from the LoRa-E5 STM32WLE5JC module -- 4x M2 mounting holes - -More information about the board can be found at the `LoRa-E5 mini Wiki`_. - -More information about LoRa-E5 STM32WLE5JC Module can be found here: - -- `LoRa-E5 STM32WLE5JC Module Wiki`_ -- `LoRa-E5 STM32WLE5JC Module datasheet`_ -- `STM32WLE5JC datasheet`_ -- `STM32WLE5JC reference manual`_ -- `STM32WLE5JC on www.st.com`_ - -Supported Features -================== - -The Zephyr LoRa-E5 mini configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| RADIO | on-chip | LoRa | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- :zephyr_file:`boards/arm/lora_e5_mini/lora_e5_mini_defconfig` -- :zephyr_file:`boards/arm/lora_e5_mini/lora_e5_mini.dts` - - -Connections and IOs -=================== - -LoRa-E5 mini has 4 GPIO controllers. These controllers are responsible for pin -muxing, input/output, pull-up, etc. - -Available pins: ---------------- - -.. image:: img/lora_e5_mini_pinout.jpg - :align: center - :alt: LoRa-E5 mini Pinout - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX : PB6 -- USART_1 RX : PB7 -- I2C_2_SCL : PB15 -- I2C_2_SDA : PA15 -- BOOT_PB : PB13 -- LED_1 : PB5 - -System Clock ------------- - -LoRa-E5 mini board System Clock could be driven by the low-power internal (MSI), -High-speed internal (HSI) or High-speed external (HSE) oscillator, as well as -main PLL clock. By default System clock is driven by the MSI clock at 48MHz. - -Programming and Debugging -************************* - -Applications for the ``lora_e5_mini`` board configuration can be built the -usual way (see :ref:`build_an_application`). - -In the factory the module is flashed with an DFU bootloader, an AT command -firmware, and the read protection level 1 is enabled. -So before you can program a Zephyr application to the module for the first time -you have to reset the read protection to level 0. -In case you use an st-link debugger you can use the STM32CubeProgrammer GUI to -set the RDP option byte to ``AA``, -or use the STM32_Programmer_CLI passing the ``--readunprotect`` command -to perform this read protection regression. -The RDP level 1 to RDP level 0 regression will erase the factory programmed AT -firmware, from which seeed has neither released the source code nor a binary. -Also, note that on the module the ``BOOT0`` pin of the SOC is not accessible, -so the system bootloader will only be executed if configured in the option bytes. - -Flashing -======== - -The LoRa-E5 mini does not include a on-board debug probe. -But the module can be debugged by connecting an external debug probe to the -2.54mm header. -Depending on the external probe used, ``openocd``, the ``stm32cubeprogrammer``, -``pyocd``, ``blackmagic``, or ``jlink`` runner can be used to flash the board. -Additional notes: - -- Pyocd: For STM32WL support Pyocd needs additional target information, which - can be installed by adding "pack" support with the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32wl - -Flashing an application to LoRa-E5 mini ---------------------------------------- - -Connect the LoRa-E5 to your host computer using the external debug probe. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your board: -Per default the console on ``usart1`` is available on the USB Type C connector -via the built-in USB to UART converter. - -.. code-block:: console - - $ picocom --baud 115200 /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lora_e5_mini - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: lora_e5_mini - :maybe-skip-config: - :goals: debug - -.. _LoRa-E5 mini Wiki: - https://wiki.seeedstudio.com/LoRa_E5_mini/ - -.. _LoRa-E5 STM32WLE5JC Module Wiki: - https://wiki.seeedstudio.com/LoRa-E5_STM32WLE5JC_Module/ - -.. _LoRa-E5 STM32WLE5JC Module datasheet: - https://files.seeedstudio.com/products/317990687/res/LoRa-E5%20module%20datasheet_V1.0.pdf - -.. _STM32WLE5JC on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32wle5jc.html - -.. _STM32WLE5JC datasheet: - https://www.st.com/resource/en/datasheet/stm32wle5jc.pdf - -.. _STM32WLE5JC reference manual: - https://www.st.com/resource/en/reference_manual/dm00530369-stm32wlex-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf diff --git a/boards/arm/lpcxpresso11u68/Kconfig.board b/boards/arm/lpcxpresso11u68/Kconfig.board deleted file mode 100644 index 721104975a2ded..00000000000000 --- a/boards/arm/lpcxpresso11u68/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso11U68 board - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO11U68 - bool "NXP LPCXPRESSO-11U68" - depends on SOC_SERIES_LPC11U6X - select SOC_PART_NUMBER_LPC11U68JBD100 diff --git a/boards/arm/lpcxpresso11u68/Kconfig.defconfig b/boards/arm/lpcxpresso11u68/Kconfig.defconfig deleted file mode 100644 index da0fd7aacacdf8..00000000000000 --- a/boards/arm/lpcxpresso11u68/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LPCXpresso11U68 board - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO11U68 - -config BOARD - default "lpcxpresso11u68" - -endif # BOARD_LPCXPRESSO11U68 diff --git a/boards/arm/lpcxpresso51u68/Kconfig.board b/boards/arm/lpcxpresso51u68/Kconfig.board deleted file mode 100644 index 21ae8f8571a2a6..00000000000000 --- a/boards/arm/lpcxpresso51u68/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso51U68 board - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO51U68 - bool "NXP LPCXPRESSO-51U68" - depends on SOC_SERIES_LPC51U68 - select SOC_PART_NUMBER_LPC51U68JBD64 diff --git a/boards/arm/lpcxpresso51u68/Kconfig.defconfig b/boards/arm/lpcxpresso51u68/Kconfig.defconfig deleted file mode 100644 index 6d8144da6921f6..00000000000000 --- a/boards/arm/lpcxpresso51u68/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# LPCXpresso51U68 board - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO51U68 - -config BOARD - default "lpcxpresso51u68" - -endif # BOARD_LPCXPRESSO51U68 diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68_defconfig b/boards/arm/lpcxpresso51u68/lpcxpresso51u68_defconfig deleted file mode 100644 index dd287658c061c6..00000000000000 --- a/boards/arm/lpcxpresso51u68/lpcxpresso51u68_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_SOC_SERIES_LPC51U68=y -CONFIG_SOC_LPC51U68=y -CONFIG_BOARD_LPCXPRESSO51U68=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 diff --git a/boards/arm/lpcxpresso54114/Kconfig.board b/boards/arm/lpcxpresso54114/Kconfig.board deleted file mode 100644 index ad0e5f55a6183a..00000000000000 --- a/boards/arm/lpcxpresso54114/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# LPCXpresso54114 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO54114_M4 - bool "NXP LPCXPRESSO-54114 M4" - depends on SOC_SERIES_LPC54XXX - select SOC_PART_NUMBER_LPC54114J256BD64 - -config BOARD_LPCXPRESSO54114_M0 - bool "NXP LPCXPRESSO-54114 M0" - depends on SOC_SERIES_LPC54XXX - select SOC_PART_NUMBER_LPC54114J256BD64 diff --git a/boards/arm/lpcxpresso54114/Kconfig.defconfig b/boards/arm/lpcxpresso54114/Kconfig.defconfig deleted file mode 100644 index 956e9da15286ff..00000000000000 --- a/boards/arm/lpcxpresso54114/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# LPCXpresso54114 board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO54114_M4 || BOARD_LPCXPRESSO54114_M0 - -config BOARD - default "lpcxpresso54114_m4" if BOARD_LPCXPRESSO54114_M4 - default "lpcxpresso54114_m0" if BOARD_LPCXPRESSO54114_M0 - -# Place size restrictions on first image if dual core is enabled -if SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_M4 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_M4 - -endif # BOARD_LPCXPRESSO54114_M4 || BOARD_LPCXPRESSO54114_M0 diff --git a/boards/arm/lpcxpresso54114/board.cmake b/boards/arm/lpcxpresso54114/board.cmake deleted file mode 100644 index f76bdf6a16c4ee..00000000000000 --- a/boards/arm/lpcxpresso54114/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_BOARD_LPCXPRESSO54114_M4 OR CONFIG_SECOND_CORE_MCUX) -board_runner_args(jlink "--device=LPC54114J256_M4" "--reset-after-load") -elseif(CONFIG_BOARD_LPCXPRESSO54114_M0) -board_runner_args(jlink "--device=LPC54114J256_M0" "--reset-after-load") -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/lpcxpresso54114/doc/index.rst b/boards/arm/lpcxpresso54114/doc/index.rst deleted file mode 100644 index e0d38c663ac3c7..00000000000000 --- a/boards/arm/lpcxpresso54114/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _lpcxpresso54114: - -NXP LPCXPRESSO54114 -################### - -Overview -******** - -The LPCXpresso54114 board has been developed by NXP to enable evaluation of and -prototyping with the low-power LPC54110 family of MCUs. LPCXpresso* is a -low-cost development platform available from NXP supporting NXP's ARM-based -microcontrollers. LPCXpresso is an end-to-end solution enabling embedded -engineers to develop their applications from initial evaluation to final -production. - -.. image:: lpcxpresso54114_m4.jpg - :align: center - :alt: LPCXPRESSO54114 - -Hardware -******** - -- LPC54114 dual-core (M4F and dual M0) MCU running at up to 100 MHz -- On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol - support, can debug the on-board LPC54114 or an external target -- External debug probe option -- Tri-color LED, target Reset, ISP & interrupt/user buttons for easy testing of - software functionality -- Expansion options based on Arduino UNO and Pmod™, plus additional expansion - port pins -- On-board 1.8 V and 3.3 V regulators plus external power supply option -- 8 Mb Macronix MX25R SPI flash -- Built-in MCU power consumption and supply voltage measurement -- UART, I²C and SPI port bridging from LPC54114 target to USB via the on-board - debug probe -- FTDI UART connector - -For more information about the LPC54114 SoC and LPCXPRESSO54114 board: - -- `LPC54114 SoC Website`_ -- `LPC54114 Datasheet`_ -- `LPC54114 Reference Manual`_ -- `LPCXPRESSO54114 Website`_ -- `LPCXPRESSO54114 User Guide`_ -- `LPCXPRESSO54114 Schematics`_ - -Supported Features -================== - -The lpcxpresso54114 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| IAP | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration for each core can be found in the defconfig files: - - ``boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig`` - ``boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The LPC54114 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_0 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_1 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_18 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO0_19 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO0_20 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO0_25 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO0_26 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO0_29 | GPIO | RED LED | -+---------+-----------------+----------------------------+ -| PIO1_1 | SPI | SPI SSEL2 | -+---------+-----------------+----------------------------+ -| PIO1_9 | GPIO | BLUE_LED | -+---------+-----------------+----------------------------+ -| PIO1_10 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ - -System Clock -============ - -The LPC54114 SoC is configured to use the internal FRO at 48MHz as a source for -the system clock. Other sources for the system clock are provided in the SOC, -depending on your system requirements. - -Serial Port -=========== - -The LPC54114 SoC has 8 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, -however the :ref:`pyocd-debug-host-tools` do not support this probe so you must -reconfigure the board for one of the following debug probes instead. - -:ref:`lpclink2-jlink-onboard-debug-probe` ------------------------------------------ - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program -the J-Link firmware. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the LPC-Link2 -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J5 - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso54114_m4 - :goals: flash - -Open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! lpcxpresso54114_m4 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso54114_m4 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! lpcxpresso54114_m4 - -.. _LPC54114 SoC Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc54000-series-cortex-m4-mcus/low-power-microcontrollers-mcus-based-on-arm-cortex-m4-cores-with-optional-cortex-m0-plus-co-processor:LPC541XX - -.. _LPC54114 Datasheet: - https://www.nxp.com/docs/en/data-sheet/LPC5411X.pdf - -.. _LPC54114 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=UM10914 - -.. _LPCXPRESSO54114 Website: - https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso54114-board:OM13089 - -.. _LPCXPRESSO54114 User Guide: - https://www.nxp.com/webapp/Download?colCode=UM10973 - -.. _LPCXPRESSO54114 Schematics: - https://www.nxp.com/downloads/en/design-support/LPCX5411x_Schematic_Rev_A1.pdf diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.yaml b/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.yaml deleted file mode 100644 index 4fea41d5526c0f..00000000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.yaml +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso54114_m0 -name: NXP LPCXpresso54114 M0 -type: mcu -arch: arm -ram: 32 -flash: 64 -testing: - ignore_tags: - - net -toolchain: - - xtools - - zephyr - - gnuarmemb -vendor: nxp diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig b/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig deleted file mode 100644 index a6a7ebc28a1307..00000000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_LPC54114_M0=y -CONFIG_SOC_SERIES_LPC54XXX=y -CONFIG_BOARD_LPCXPRESSO54114_M0=y -CONFIG_USE_SEGGER_RTT=y -CONFIG_SERIAL=n -CONFIG_GPIO=n -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_PINCTRL=y diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.yaml b/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.yaml deleted file mode 100644 index d8410a518937d5..00000000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso54114_m4 -name: NXP LPCXpresso54114 M4 -type: mcu -arch: arm -ram: 64 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - arduino_i2c - - arduino_spi - - gpio - - i2c - - spi -vendor: nxp diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig b/boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig deleted file mode 100644 index 3749cbba716f82..00000000000000 --- a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_LPC54114_M4=y -CONFIG_SOC_SERIES_LPC54XXX=y -CONFIG_BOARD_LPCXPRESSO54114_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/lpcxpresso55s06/Kconfig.board b/boards/arm/lpcxpresso55s06/Kconfig.board deleted file mode 100644 index 516f098775c0d7..00000000000000 --- a/boards/arm/lpcxpresso55s06/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S06 board - -# Copyright (c) 2022 metraTec -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S06 - bool "NXP LPCXPRESSO-55S06" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S06JBD64 diff --git a/boards/arm/lpcxpresso55s06/Kconfig.defconfig b/boards/arm/lpcxpresso55s06/Kconfig.defconfig deleted file mode 100644 index 48340c5f589f4c..00000000000000 --- a/boards/arm/lpcxpresso55s06/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# LPCXpresso55S06 board - -# Copyright (c) 2022 metraTec -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S06 - -config BOARD - default "lpcxpresso55s06" - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S06 diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06_defconfig b/boards/arm/lpcxpresso55s06/lpcxpresso55s06_defconfig deleted file mode 100644 index a743b67e2fd32e..00000000000000 --- a/boards/arm/lpcxpresso55s06/lpcxpresso55s06_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2022 metraTec -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S06=y -CONFIG_BOARD_LPCXPRESSO55S06=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_ARM_MPU=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s16/Kconfig.board b/boards/arm/lpcxpresso55s16/Kconfig.board deleted file mode 100644 index 0a39989427f250..00000000000000 --- a/boards/arm/lpcxpresso55s16/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S16 board - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S16 - bool "NXP LPCXPRESSO-55S16" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S16JBD100 diff --git a/boards/arm/lpcxpresso55s16/Kconfig.defconfig b/boards/arm/lpcxpresso55s16/Kconfig.defconfig deleted file mode 100644 index 2979ac8808d73f..00000000000000 --- a/boards/arm/lpcxpresso55s16/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# LPCXpresso55S16 board - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S16 - -config BOARD - default "lpcxpresso55S16" - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S16 diff --git a/boards/arm/lpcxpresso55s28/Kconfig.board b/boards/arm/lpcxpresso55s28/Kconfig.board deleted file mode 100644 index 871dd381a1f3f0..00000000000000 --- a/boards/arm/lpcxpresso55s28/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S28 board - -# Copyright (c) 2020 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S28 - bool "NXP LPCXPRESSO-55S28" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S28JBD100 diff --git a/boards/arm/lpcxpresso55s28/Kconfig.defconfig b/boards/arm/lpcxpresso55s28/Kconfig.defconfig deleted file mode 100644 index ee3fd9685c41e1..00000000000000 --- a/boards/arm/lpcxpresso55s28/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# LPCXpresso55S28 board - -# Copyright (c) 2020 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S28 - -config BOARD - default "lpcxpresso55S28" - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # FXOS8700 - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_LPCXPRESSO55S28 && TRUSTED_EXECUTION_SECURE - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S28 diff --git a/boards/arm/lpcxpresso55s36/Kconfig.board b/boards/arm/lpcxpresso55s36/Kconfig.board deleted file mode 100644 index afa4f1133852c0..00000000000000 --- a/boards/arm/lpcxpresso55s36/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# LPCXpresso55S36 board - -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S36 - bool "NXP LPCXPRESSO-55S36" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S36JBD100 diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36_defconfig b/boards/arm/lpcxpresso55s36/lpcxpresso55s36_defconfig deleted file mode 100644 index 4bf154138aff65..00000000000000 --- a/boards/arm/lpcxpresso55s36/lpcxpresso55s36_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S36=y -CONFIG_BOARD_LPCXPRESSO55S36=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_ARM_MPU=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/Kconfig.board b/boards/arm/lpcxpresso55s69/Kconfig.board deleted file mode 100644 index afdf017e36b7e0..00000000000000 --- a/boards/arm/lpcxpresso55s69/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# LPCXpresso55S69 board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LPCXPRESSO55S69_CPU0 - bool "NXP LPCXPRESSO-55S69 [CPU0]" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S69JBD100 - -config BOARD_LPCXPRESSO55S69_CPU1 - bool "NXP LPCXPRESSO-55S69 [CPU1]" - depends on SOC_SERIES_LPC55XXX - select SOC_PART_NUMBER_LPC55S69JBD100 diff --git a/boards/arm/lpcxpresso55s69/Kconfig.defconfig b/boards/arm/lpcxpresso55s69/Kconfig.defconfig deleted file mode 100644 index c8bc5421e098fe..00000000000000 --- a/boards/arm/lpcxpresso55s69/Kconfig.defconfig +++ /dev/null @@ -1,65 +0,0 @@ -# LPCXpresso55S69 board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LPCXPRESSO55S69_CPU0 || BOARD_LPCXPRESSO55S69_CPU1 - -config BOARD - default "lpcxpresso55S69_cpu0" if BOARD_LPCXPRESSO55S69_CPU0 - default "lpcxpresso55S69_cpu1" if BOARD_LPCXPRESSO55S69_CPU1 - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # FXOS8700 - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_LPCXPRESSO55S69_CPU0 && TRUSTED_EXECUTION_SECURE - -if TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_CPU1 - -config FLASH_LOAD_OFFSET - default 0x50000 if (!TFM_BL2 && BUILD_WITH_TFM) - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default 0x40000 if (!TFM_BL2 && BUILD_WITH_TFM) - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_CPU1 - -choice TFM_PROFILE_TYPE - depends on BUILD_WITH_TFM - default TFM_PROFILE_TYPE_MEDIUM -endchoice - -if BOOTLOADER_MCUBOOT -choice MCUBOOT_BOOTLOADER_MODE - # Board only supports MCUBoot via "upgrade only" method: - default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY -endchoice -endif #BOOTLOADER_MCUBOOT - -endif # BOARD_LPCXPRESSO55S69_CPU0 || BOARD_LPCXPRESSO55S69_CPU1 diff --git a/boards/arm/lpcxpresso55s69/board.cmake b/boards/arm/lpcxpresso55s69/board.cmake deleted file mode 100644 index ed9aedf4f4e4c6..00000000000000 --- a/boards/arm/lpcxpresso55s69/board.cmake +++ /dev/null @@ -1,28 +0,0 @@ -# -# Copyright 2019, 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -## DAP Link implementation in pyocd is underway, -## until then jlink can be used or copy image to storage - -if(CONFIG_BOARD_LPCXPRESSO55S69_CPU0 OR CONFIG_SECOND_CORE_MCUX) -board_runner_args(jlink "--device=LPC55S69_M33_0") -board_runner_args(linkserver "--device=LPC55S69:LPCXpresso55S69") -board_runner_args(linkserver "--override=/device/memory/0/flash-driver=LPC55xx_S.cfx") -board_runner_args(linkserver "--override=/device/memory/0/location=0x10000000") -elseif(CONFIG_BOARD_LPCXPRESSO55S69_CPU1) -board_runner_args(jlink "--device=LPC55S69_M33_1") -endif() - -board_runner_args(pyocd "--target=lpc55s69") - -if(CONFIG_BUILD_WITH_TFM) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/arm/lpcxpresso55s69/doc/index.rst b/boards/arm/lpcxpresso55s69/doc/index.rst deleted file mode 100644 index 1f8d46cef485eb..00000000000000 --- a/boards/arm/lpcxpresso55s69/doc/index.rst +++ /dev/null @@ -1,413 +0,0 @@ -.. _lpcxpresso55s69: - -NXP LPCXPRESSO55S69 -################### - -Overview -******** - -The LPCXpresso55S69 development board provides the ideal platform for evaluation -of and development with the LPC55S6x MCU based on the Arm® Cortex®-M33 -architecture. The board includes a high performance onboard debug probe, audio -subsystem, and accelerometer, with several options for adding off-the-shelf -add-on boards for networking, sensors, displays, and other interfaces. - -.. image:: lpcxpresso55s69.jpg - :align: center - :alt: LPCXPRESSO55S69 - -Hardware -******** - -- LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz -- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link - protocol options -- UART and SPI port bridging from LPC55S69 target to USB via the onboard debug - probe -- Hardware support for external debug probe -- 3 x user LEDs, plus Reset, ISP (3) and user buttons -- Micro SD card slot (4-bit SDIO) -- NXP MMA8652FCR1 accelerometer -- Stereo audio codec with line in/out -- High and full speed USB ports with micro A/B connector for host or device - functionality -- MikroEletronika Click expansion option -- LPCXpresso-V3 expansion option compatible with Arduino UNO -- PMod compatible expansion / host connector - -For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see: - -- `LPC55S69 SoC Website`_ -- `LPC55S69 Datasheet`_ -- `LPC55S69 Reference Manual`_ -- `LPCXPRESSO55S69 Website`_ -- `LPCXPRESSO55S69 User Guide`_ -- `LPCXPRESSO55S69 Schematics`_ -- `LPCXPRESSO55S69 Debug Firmware`_ - -Supported Features -================== - -NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx -series of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling -this board with new support for Zephyr features. The lpcxpresso55s69 board -configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WWDT | on-chip | windowed watchdog timer | -+-----------+------------+-------------------------------------+ -| TrustZone | on-chip | Trusted Firmware-M | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| MAILBOX | on-chip | ipm | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| USB HS | on-chip | USB High Speed device | -+-----------+------------+-------------------------------------+ -| USB FS | on-chip | USB Full Speed device | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| IAP | on-chip | flash programming | -+-----------+------------+-------------------------------------+ -| SDIF | on-chip | sdhc | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma (on CPU0) | -+-----------+------------+-------------------------------------+ - -Targets available -================== - -The default configuration file -``boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig`` -only enables the first core. -CPU0 is the only target that can run standalone. - -- *lpcxpresso55s69_cpu0* secure (S) address space for CPU0 -- *lpcxpresso55s69_ns* non-secure (NS) address space for CPU0 -- *lpcxpresso55s69_cpu1* CPU1 target, no security extensions - -NS target for CPU0 does not work correctly without a secure image to configure -the system, then hand execution over to the NS environment. To enable a secure -image, run any of the ``tfm_integration`` samples. When using the NS target -``CONFIG_BUILD_WITH_TFM`` is always enabled to ensure that a valid S image is -included during the build process. - -CPU1 does not work without CPU0 enabling it. -To enable it, run one of the following samples in ``subsys\ipc``: -- ``ipm_mcux`` -- ``openamp`` - -Connections and IOs -=================== - -The LPC55S69 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_26 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO0_27 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_29 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_30 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO1_1 | SPI | SPI SSEL | -+---------+-----------------+----------------------------+ -| PIO1_2 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO1_3 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO1_4 | GPIO | RED LED | -+---------+-----------------+----------------------------+ -| PIO1_6 | GPIO | BLUE_LED | -+---------+-----------------+----------------------------+ -| PIO1_7 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ -| PIO1_20 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO1_21 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO1_24 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_20 | I2S | I2S DATAOUT | -+---------+-----------------+----------------------------+ -| PIO0_19 | I2S | I2S TX WS | -+---------+-----------------+----------------------------+ -| PIO0_21 | I2S | I2S TX SCK | -+---------+-----------------+----------------------------+ -| PIO1_13 | I2S | I2S DATAIN | -+---------+-----------------+----------------------------+ -| PIO0_15 | SCT0_OUT2 | PWM | -+---------+-----------------+----------------------------+ -| PIO0_24 | SD0_D0 | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_25 | SD0_D1 | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_31 | SD0_D2 | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_7 | SD0_CLK | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_8 | SD0_CMD | SDHC | -+---------+-----------------+----------------------------+ -| PIO0_9 | SD0_POW_EN | SDHC | -+---------+-----------------+----------------------------+ -| PIO1_0 | SD0_D3 | SDHC | -+---------+-----------------+----------------------------+ - -Memory mappings -=============== - -There are multiple memory configurations, they all start from the -MCUboot partitioning which looks like the table below - -+----------+------------------+---------------------------------+ -| Name | Address[Size] | Comment | -+==========+==================+=================================+ -| boot | 0x00000000[32K] | Bootloader | -+----------+------------------+---------------------------------+ -| slot0 | 0x00008000[160k] | Image that runs after boot | -+----------+------------------+---------------------------------+ -| slot0_ns | 0x00030000[96k] | Second image, core 1 or NS | -+----------+------------------+---------------------------------+ -| slot1 | 0x00048000[160k] | Updates slot0 image | -+----------+------------------+---------------------------------+ -| slot1_ns | 0x00070000[96k] | Updates slot0_ns image | -+----------+------------------+---------------------------------+ -| storage | 0x00088000[50k] | File system, persistent storage | -+----------+------------------+---------------------------------+ - -See below examples of how this partitioning is used - -Trusted Execution -***************** - -+-----------+------------------+--------------------+ -| Memory | Address[Size] | Comment | -+===========+==================+====================+ -| MCUboot | 0x00000000[32K] | Secure bootloader | -+-----------+------------------+--------------------+ -| TFM_S | 0x00008000[160k] | Secure image | -+-----------+------------------+--------------------+ -| Zephyr_NS | 0x00030000[96k] | Non-Secure image | -+-----------+------------------+--------------------+ -| storage | 0x00088000[50k] | Persistent storage | -+-----------+------------------+--------------------+ - -+----------------+------------------+-------------------+ -| RAM | Address[Size] | Comment | -+================+==================+===================+ -| secure_ram | 0x20000000[136k] | Secure memory | -+----------------+------------------+-------------------+ -| non_secure_ram | 0x20022000[136k] | Non-Secure memory | -+----------------+------------------+-------------------+ - -Dual Core samples -***************** - -+--------+------------------+----------------------------+ -| Memory | Address[Size] | Comment | -+========+==================+============================+ -| CPU0 | 0x00000000[630K] | CPU0, can access all flash | -+--------+------------------+----------------------------+ -| CPU1 | 0x00030000[96k] | CPU1, has no MPU | -+--------+------------------+----------------------------+ - -+-------+------------------+-----------------------+ -| RAM | Address[Size] | Comment | -+=======+==================+=======================+ -| sram0 | 0x20000000[64k] | CPU0 memory | -+-------+------------------+-----------------------+ -| sram3 | 0x20030000[64k] | CPU1 memory | -+-------+------------------+-----------------------+ -| sram4 | 0x20040000[16k] | Mailbox/shared memory | -+-------+------------------+-----------------------+ - -System Clock -============ - -The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz -crystal, running at 144MHz as a source for the system clock. When the flash -controller is enabled, the core clock will be reduced to 96MHz. The application -may reconfigure clocks after initialization, provided that the core clock is -always set to 96MHz when flash programming operations are performed. - -Serial Port -=========== - -The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, -however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you -must reconfigure the board for one of the following debug probes instead. - -:ref:`lpclink2-jlink-onboard-debug-probe` ------------------------------------------ - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program -the J-Link firmware. Please make sure you have the latest firmware for this -board. - -:ref:`lpclink2-cmsis-onboard-debug-probe` ------------------------------------------ - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware` - -:ref:`opensda-daplink-onboard-debug-probe` ------------------------------------------- - -PyOCD support for this board is ongoing and not yet available. -To use DAPLink's flash memory programming on this board, follow the instructions -for `updating LPCXpresso firmware`_. - -Configuring a Console -===================== - -Connect a USB cable from your PC to P6, and use the serial terminal of your choice -(minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso55s69_cpu0 - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0 ***** - Hello World! lpcxpresso55s69_cpu0 - -Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| ----------------------------------------------------------------------- -The TF-M integration samples can be run using the ``lpcxpresso55s69_ns`` target. -To run we need to manually flash the resulting image (``tfm_merged.hex``) with -a J-Link as follows (reset and erase are for recovering a locked core): - - .. code-block:: console - - JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 - J-Link>r - J-Link>erase - J-Link>loadfile build/zephyr/tfm_merged.hex - -We need to reset the board manually after flashing the image to run this code. - -Building a dual-core image --------------------------- -The dual-core samples are run using ``lpcxpresso55s69_cpu0`` target, -``lpcxpresso55s69_cpu1`` will be automatically built and merged in a single -image when ``SECOND_CORE_MCUX`` is selected. -To run we need to manually flash the resulting image (``multicore.bin``) with a -J-Link as follows (reset and erase are for recovering a locked core): - - .. code-block:: console - - JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 - J-Link>r - J-Link>erase - J-Link>loadfile build/multicore.bin - -We need to reset the board manually after flashing the image to run this code. - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: lpcxpresso55s69_cpu0 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS zephyr-v1.14.0 ***** - Hello World! lpcxpresso55s69_cpu0 - -.. _LPC55S69 SoC Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x - -.. _LPC55S69 Datasheet: - https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf - -.. _LPC55S69 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=UM11126 - -.. _LPCXPRESSO55S69 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK - -.. _LPCXPRESSO55S69 User Guide: - https://www.nxp.com/webapp/Download?colCode=UM11158 - -.. _LPCXPRESSO55S69 Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _LPCXPRESSO55S69 Schematics: - https://www.nxp.com/webapp/Download?colCode=LPC55S69-SCH - -.. _updating LPCXpresso firmware: - https://os.mbed.com/teams/NXP/wiki/Updating-LPCXpresso-firmware diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml deleted file mode 100644 index d0bafc9cd4bbfa..00000000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.yaml +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso55s69_cpu0 -name: NXP LPCXpresso55S69 (CPU0) -type: mcu -arch: arm -ram: 64 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - arduino_i2c - - arduino_serial - - arduino_spi - - counter - - gpio - - i2c - - i2s - - spi - - sdhc - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig deleted file mode 100644 index ece94dd0b6f57b..00000000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S69_CPU0=y -CONFIG_BOARD_LPCXPRESSO55S69_CPU0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y - -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_ARM_TRUSTZONE_M=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.yaml deleted file mode 100644 index 818d29535fab37..00000000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso55s69_cpu1 -name: NXP LPCXpresso55S69 (CPU1) -type: mcu -arch: arm -ram: 64 -flash: 256 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - gpio -vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1_defconfig b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1_defconfig deleted file mode 100644 index d93ccd89329978..00000000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S69_CPU1=y -CONFIG_BOARD_LPCXPRESSO55S69_CPU1=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y - -CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml deleted file mode 100644 index d7333e026d7df2..00000000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.yaml +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: lpcxpresso55s69_ns -name: NXP LPCXpresso55S69 (Non-Secure) -type: mcu -arch: arm -ram: 136 -flash: 96 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - arduino_spi - - counter - - dma - - gpio - - spi - - watchdog -vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns_defconfig b/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns_defconfig deleted file mode 100644 index 451a92a74a6855..00000000000000 --- a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S69_CPU0=y -CONFIG_BOARD_LPCXPRESSO55S69_CPU0=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y - -# TFM sets up MPU_NS, can't correctly change this configuration yet -CONFIG_ARM_MPU=n - -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_BUILD_WITH_TFM=y - -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/mec1501modular_assy6885/Kconfig.board b/boards/arm/mec1501modular_assy6885/Kconfig.board deleted file mode 100644 index 0e9b720abb7cd5..00000000000000 --- a/boards/arm/mec1501modular_assy6885/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC1501MODULAR_ASSY6885 - bool "Microchip MEC1501 Modular ASSY 6885 Development board" - depends on SOC_MEC1501_HSZ diff --git a/boards/arm/mec1501modular_assy6885/Kconfig.defconfig b/boards/arm/mec1501modular_assy6885/Kconfig.defconfig deleted file mode 100644 index b22c410d8a30a7..00000000000000 --- a/boards/arm/mec1501modular_assy6885/Kconfig.defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC1501MODULAR_ASSY6885 - -config BOARD - default "mec1501modular_assy6885" - -#PS/2 driver is compiled in terms of this flag. -config ESPI_PERIPHERAL_8042_KBC - default y - depends on ESPI_XEC - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 -# The driver requires tickless mode and ticks per -# second to be 32768 for accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 48MHz divided by -# SOC_MEC1501_PROC_CLK_DIV. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -if ESPI - -config ESPI_PERIPHERAL_UART_SOC_MAPPING - default 1 - -endif # ESPI - -endif # RTOS_TIMER - -endif # BOARD_MEC1501MODULAR_ASSY6885 diff --git a/boards/arm/mec1501modular_assy6885/doc/index.rst b/boards/arm/mec1501modular_assy6885/doc/index.rst deleted file mode 100644 index cd1f8ef8b25ad4..00000000000000 --- a/boards/arm/mec1501modular_assy6885/doc/index.rst +++ /dev/null @@ -1,321 +0,0 @@ -.. _mec1501modular_assy6885: - -Microchip MEC1501 Modular card ASSY6885 -####################################### - -Overview -******** - -The MEC1501 Modular card ASSY6885 is a development board to evaluate the Microchip -MEC152X series microcontrollers. This board can work standalone or be mated with -any platform that complies with MECC specification. - -.. image:: mec1501modular_assy6885.jpg - :align: center - :alt: MEC1501 Modular ASSY 6885 - -Hardware -******** - -- MEC1521HA0SZ ARM Cortex-M4 Processor -- 256 KB RAM and 64 KB boot ROM -- GPIO headers -- UART1 using microUSB -- PECI interface 3.0 -- 10 SMBUS instances -- FAN, PMW and TACHO pins -- VCI interface -- Independent Hardware Driven PS/2 Ports - -At difference from MEC15xx evaluation board, modular MEC1521 exposes the pins -in 2 different ways: - -1) Standalone mode via headers - - - GPIOs - - PWM5 - - JTAG/SWD, ETM and MCHP Trace ports - - eSPI bus - - SMB0 - -2) Mated mode with another platform that has a high density MECC connector. - - - FAN0, PWM0, SMB0, SMB1, SMB4 and SMB5 - - eSPI bus - - Breathing/Blinking LEDs - -The board is powered through the +5V USB Micro A connector or from the MECC connector. - - -For more information about the SOC please see the `MEC152x Reference Manual`_ - -Supported Features -================== - -The mec1501modular_assy6885 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ESPI | on-chip | espi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| RTOS | on-chip | timer | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PS2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the -:zephyr_file:`boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig` -Kconfig file. - -Connections and IOs -=================== - -This evaluation board kit is comprised of the following HW blocks: - -- MEC1501 Modular Card ASSY 6885 Rev A0 `MEC1501 Modular EC Card - Assy_6885 Rev A0p1`_ - -System Clock -============ - -The MEC1501 MCU is configured to use the 48Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock -control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in -the references at the end of this document. - -Serial Port -=========== -UART1 is configured for serial logs. - -Jumper settings -*************** - -Please follow the jumper settings below to properly demo this -board. Advanced users may deviate from this recommendation. - -Jumper setting for MEC1501 Modular Assy 6885 Rev A1p0 -===================================================== - -Power-related jumpers ---------------------- - -If you wish to power from type A/B connector ``P10`` set the jumper ``JP35 1-2``. - -If you wish to power through MECC connector ``P1`` and mate to external platform, -set the jumper to ``JP35 3-4``. - -.. note:: A single jumper is required in JP35. - -+------+---------+---------+------+------+------+----------+ -| JP30 | JP31 | JP32 | JP33 | JP34 | JP40 | JP21 | -| VTR3 | VTR_PLL | VTR_REG | VTR1 | VTR2 | 3.3V | VREF_ADC | -+======+=========+=========+======+======+======+==========+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+---------+---------+------+------+------+----------+ - - -+------+------------+------+----------+ -| JP6 | JP36 | JP27 | JP4 | -| VBAT | VTR_ANALOG | PECI | VREF_VTT | -+======+============+======+==========+ -| 2-3 | 1-2 | 2-3 | open | -+------+------------+------+----------+ - -These jumpers configure nRESETI and JTAG_STRAP respectively. - -+-----------+---------------+ -| JP22 | JP29 | -| (nRESETI) | (JTAG_STRAP) | -+===========+===============+ -| 11-12 | 1-2 | -+-----------+---------------+ - -Boot-ROM Straps ---------------- - -These jumpers configure MEC1501 Boot-ROM straps. - -+-------------+------------+--------------+-------------+ -| JP37 | J6 | JP41 | JP23 | -| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | -+=============+============+==============+=============+ -| 1-2 | 1-2 | 1-2 | 3-4 | -+-------------+------------+--------------+-------------+ - - -``JP23 3-4`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples -SHD SPI CS0# and if high, it loads code from SHD SPI. -This is the recommended setup. - -+-------------+------------+----------------------------+ -| CR_STRAP | BSS_STRAP | SOURCE | -+-------------+------------+----------------------------+ -| 0 | X | Use 3.3V Private SPI | -+-------------+------------+----------------------------+ -| 1 | 0 | Use eSPI Flash channel | -+-------------+------------+----------------------------+ -| | 1 | Use 3.3V Shared channel(R)| -+-------------+------------+----------------------------+ - -Power management ----------------- -``JP20 2-3`` is required so all GPIOs powered by VTR3 rail worked at 1.8V. - -.. note:: External 1.8V needs to be connected to JP13.1 - -+-------------------+-----------------+ -| JP20 | JP13 | -| (VTR3 selection) | (1.8V source) | -+===================+=================+ -| 2-3 | 1.8V to pin 1 | -+-------------------+-----------------+ - - -Jumper location map -------------------- - -.. code-block:: none - - +--------------------------------------------------------------------------------------+ - | |------------| +----------+ J10 || | - | [BT1] + +------------+ J50 ++ ++ || | - | | JP38 JP43 ++ || || | - | + + + +-+ JP4 + + JP26 || || | - | JP6 + + + + + + + + || || | - | JP31 ++ JP32 JP36 +-+ JP27 + + + + J6 || | - | JP18 JP37 JP41 JP42 ++ | - | ++ + + +--------+ J48 | - | || JP21 + + +--------+ JP22 +----------+ | - | J2 || + JP34 JP30 J11 ++ | - | ++ + J44 || | - | ++ +----------------+ || | - | +---------------+ || + JP24 |----------------| ++ | - | |---------------| ++ + +----------+ +----------------+ J47 | - | JP20 +---------------+ JP23 JP40 +----------+ ++ | - | + ++ JP29 || | - | + + +----------+ + || | - | J52+---------------+ + + +----------+ J5 +-------------+ ++ | - | J45+---------------+ JP33 TP57 JP25 +-------------+ J4 J49 | - | | - | ++ TP4 +----------+ ++ | - | ++ + + + + + + TP61 +----------+ ++ | - | JP28 + + + + + TP65 + TP60 J51 JP35 | - | TP58 JP16 JP11 JP13 JP15 JP10 | - | TP5 | - | TP6 TP1 | - +--------------------------------------------------------------------------------------+ - - -Programming and Debugging -************************* - -Setup -===== - -#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within - that directory. For the pre-production MEC150x use the `MEC150x SPI Image Gen`_ - repository. - -#. Make the image generation available for Zephyr, by making the tool - searchable by path, or by setting an environment variable - ``EVERGLADES_SPI_GEN``, for example: - - .. code-block:: console - - export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE - - Note that the tools for Linux and Windows have different file names. - For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. - -#. If needed, a custom SPI image configuration file can be specified - to override the default one. - - .. code-block:: console - - export EVERGLADES_SPI_CFG=custom_spi_cfg.txt - - -Building -========== -#. Build :ref:`hello_world` application as you would normally do. - -#. Once you have ``zephyr.bin``, use the `MEC152x SPI Image Gen`_ microchip tool - to create the final binary. You need the output from this tool to flash - in the SHD SPI memory. - -Flashing -======== - -#. Connect Dediprog into header ``J2``. - -#. Flash the SPI NOR ``U3`` at offset 0x0 using Dediprog SF100 - or a similar tool for flashing SPI chips. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the MEC1501MODULAR_ASSY6885 board to your host computer using the - UART1 port and apply power. - - You should see ``"Hello World! mec1501modular_assy6885"`` in your terminal. - -Debugging -========= -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -HW Issues -========= -In case you don't see your application running, please make sure ``LED1`` is lit. -If is off, then check the power related jumpers again. - -References -********** -.. target-notes:: - -.. _MEC152x Preliminary Data Sheet: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC152x Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC1501 Modular EC Card - Assy_6885 Rev A0p1: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Modular%20EC%20Card%20-%20Assy_6885%20Rev%20A0p1%20-%20SCH.pdf -.. _MEC152x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen -.. _MEC150x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen diff --git a/boards/arm/mec15xxevb_assy6853/Kconfig.board b/boards/arm/mec15xxevb_assy6853/Kconfig.board deleted file mode 100644 index fb7158fb795c7e..00000000000000 --- a/boards/arm/mec15xxevb_assy6853/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC15XXEVB_ASSY6853 - bool "Microchip MEC15XX EVB ASSY 6853 Development board" - depends on SOC_MEC1501_HSZ diff --git a/boards/arm/mec15xxevb_assy6853/Kconfig.defconfig b/boards/arm/mec15xxevb_assy6853/Kconfig.defconfig deleted file mode 100644 index 99c5fbeb1dd411..00000000000000 --- a/boards/arm/mec15xxevb_assy6853/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC15XXEVB_ASSY6853 - -config BOARD - default "mec15xxevb_assy6853" - -config ESPI_XEC - default y - depends on ESPI - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 -# The driver requires tickless mode and ticks per -# second to be 32768 for accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 48MHz divided by -# SOC_MEC1501_PROC_CLK_DIV. -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC15XXEVB_ASSY6853 diff --git a/boards/arm/mec15xxevb_assy6853/doc/index.rst b/boards/arm/mec15xxevb_assy6853/doc/index.rst deleted file mode 100644 index 8497c28609653c..00000000000000 --- a/boards/arm/mec15xxevb_assy6853/doc/index.rst +++ /dev/null @@ -1,467 +0,0 @@ -.. _mec15xxevb_assy6853: - -Microchip MEC15xxEVB ASSY6853 -############################# - -Overview -******** - -The MEC15xxEVB_ASSY6853 kit is a future development platform to evaluate the -Microchip MEC15XX series microcontrollers. This board needs to be mated with -part number MEC1501 144WFBA SOLDER DC ASSY 6860(cpu board) in order to operate. -The MEC152x has superseded the MEC1501 in production. MEC152x is identical to -MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has -been updated requiring a new SPI image tool. MEC1501 and MEC152x SPI image -formats are not compatible with each other. Evaluation and cpu boards are -compatible. - -.. image:: mec15xxevb_assy6853.jpg - :align: center - :alt: MEC15XX EVB ASSY 6853 - -Hardware -******** - -- MEC1521HA0SZ ARM Cortex-M4 Processor -- 256 KB RAM and 64 KB boot ROM -- Keyboard interface -- ADC & GPIO headers -- UART0, UART1, and UART2 -- FAN0, FAN1, FAN2 headers -- FAN PWM interface -- JTAG/SWD, ETM and MCHP Trace ports -- PECI interface 3.0 -- I2C voltage translator -- 10 SMBUS headers -- 4 SGPIO headers -- VCI interface -- 5 independent Hardware Driven PS/2 Ports -- eSPI header -- 3 Breathing/Blinking LEDs -- 2 Sockets for SPI NOR chips -- One reset and VCC_PWRDGD pushbuttons -- One external PCA9555 I/O port with jumper selectable I2C address. -- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. -- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. - -For more information about the SOC's please see `MEC152x Reference Manual`_ - -Supported Features -================== - -The mec15xxevb_assy6853 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PS/2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ -| KSCAN | on-chip | kscan | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer | -+-----------+------------+-------------------------------------+ - - - - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the -:zephyr_file:`boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig` Kconfig file. - -Connections and IOs -=================== - -This evaluation board kit is comprised of the following HW blocks: - -- MEC15xx EVB ASSY 6853 Rev A `MEC15xx EVB Schematic`_ -- MEC1501 144WFBA SOLDER DC ASSY 6883 with MEC152x silicon `MEC1501 Daughter Card Schematic`_ -- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ - -System Clock -============ - -The MEC1521 MCU is configured to use the 48Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock -control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in -the references at the end of this document. - -Serial Port -=========== - -UART2 is configured for serial logs. - -Jumper settings -*************** - -Please follow the jumper settings below to properly demo this -board. Advanced users may deviate from this recommendation. - -Jumper setting for MEC15xx EVB Assy 6853 Rev A1p0 -================================================= - -Power-related jumpers ---------------------- - -If you wish to power from +5V power brick, then connect to barrel connector ``P11`` -(5.5mm OD, 2.1mm ID) and move the jumper to ``JP88 5-6``. - -If you wish to power from micro-USB type A/B connector ``P12``, move the -jumper to ``JP88 7-8``. - - -.. note:: A single jumper is required in JP88. - -+-------+------+------+------+------+------+------+------+------+------+------+ -| JP22 | JP32 | JP33 | JP37 | JP43 | JP47 | JP54 | JP56 | JP58 | JP64 | JP65 | -+=======+======+======+======+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+-------+------+------+------+------+------+------+------+------+------+------+ - -+------+------+------+------+------+------+------+------+------+------+ -| JP72 | JP73 | JP76 | JP79 | JP80 | JP81 | JP82 | JP84 | JP87 | JP89 | -+======+======+======+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+------+------+------+ - -+------+------+-------+-------+-------+ -| JP90 | JP91 | JP100 | JP101 | JP118 | -+======+======+=======+=======+=======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 2-3 | -+------+------+-------+-------+-------+ - -These jumpers configure VCC Power good, nRESETI and JTAG_STRAP respectively. - -+------------------+-----------+--------------+ -| JP5 | JP4 | JP45 | -| (VCC Power good) | (nRESETI) | (JTAG_STRAP) | -+==================+===========+==============+ -| 1-2 | 1-2 | 2-3 | -+------------------+-----------+--------------+ - -Boot-ROM Straps. ----------------- - -These jumpers configure MEC1501 Boot-ROM straps. - -+-------------+------------+--------------+-------------+ -| JP93 | JP11 | JP46 | JP96 | -| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | -+=============+============+==============+=============+ -| 2-3 | 1-2 | 2-3 | 1-2 | -+-------------+------------+--------------+-------------+ - -``JP96 1-2`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples -SHD SPI CS0# and if high, it loads code from SHD SPI. - -Peripheral Routing Jumpers --------------------------- - -Each column of the following table illustrates how to enable UART2, SWD, -PVT SPI, SHD SPI and LED0-2 respectively. - -+----------+----------+--------+-----------+----------+---------+ -| JP48 | JP9 | JP9 | JP38 | JP98 | JP41 | -| (UART2) | (UART2) | (SWD) | (PVT SPI) | (SHD SPI)| (LED0-2)| -+==========+==========+========+===========+==========+=========+ -| 1-2 | | 2-3 | 2-3 | 2-3 | 1-2 | -+----------+----------+--------+-----------+----------+---------+ -| 4-5 | 4-5 | | 5-6 | 5-6 | 3-4 | -+----------+----------+--------+-----------+----------+---------+ -| 7-8 | | 8-9 | 8-9 | 8-9 | 5-6 | -+----------+----------+--------+-----------+----------+---------+ -| 10-11 | 10-11 | | 11-12 | 11-12 | | -+----------+----------+--------+-----------+----------+---------+ -| | | | 14-15 | 14-15 | | -+----------+----------+--------+-----------+----------+---------+ -| | | | 17-18 | 20-21 | | -+----------+----------+--------+-----------+----------+---------+ - -.. note:: For UART2 make sure JP39 have jumpers connected 1-2, 3-4. - -To receive UART2 serial output, please refer to the picture below -to make sure that JP9 configured for UART2 output. - -.. image:: mec15xxevb_assy6853_jp9_1.jpg - :align: center - :alt: JP9 header Assy6853 - -Jumper settings for MEC1501 144WFBGA Socket DC Assy 6883 Rev B1p0 -================================================================= - -The jumper configuration explained above covers the base board. The ASSY -6883 MEC1501 CPU board provides capability for an optional, external 32KHz -clock source. The card includes a 32KHz crystal oscillator. The card can -also be configured to use an external 50% duty cycle 32KHz source on the -XTAL2/32KHZ_IN pin. Note, firmware must set the MEC15xx clock enable -register to select the external source matching the jumper settings. If -using the MEC15xx internal silicon oscillator then the 32K jumper settings -are don't cares. ``JP1`` is for scoping test clock outputs. Please refer to -the schematic in reference section below. - -Parallel 32KHz crystal configuration ------------------------------------- -+-------+-------+ -| JP2 | JP3 | -+=======+=======+ -| 1-2 | 2-3 | -+-------+-------+ - -External 32KHz 50% duty cycle configuration -------------------------------------------- -+-------+-------+ -| JP2 | JP3 | -+=======+=======+ -| NC | 1-2 | -+-------+-------+ - - -Jumper settings for MEC1503 144WFBGA Socket DC Assy 6856 Rev B1p0 -================================================================= - -The MEC1503 ASSY 6856 CPU card does not include an onboard external -32K crystal or oscillator. The one jumper block ``JP1`` is for scoping -test clock outputs not for configuration. Please refer to schematic -in reference section below. - -Programming and Debugging -************************* - -Setup -===== -#. If you use Dediprog SF100 programmer, then setup it. - - Windows version can be found at the `SF100 Product page`_. - - Linux version source code can be found at `SF100 Linux GitHub`_. - Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. - For Linux please make sure that you copied ``60-dediprog.rules`` - from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) - then restart service using: - - .. code-block:: console - - $ udevadm control --reload - - Add directory with program ``dpcmd`` (on Linux) - or ``dpcmd.exe`` (on Windows) to your ``PATH``. - -#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within - that directory. For the pre-production MEC150x use `MEC150x SPI Image Gen`_ - repository. - -#. Make the image generation available for Zephyr, by making the tool - searchable by path, or by setting an environment variable - ``EVERGLADES_SPI_GEN``, for example: - - .. code-block:: console - - export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE - - Note that the tools for Linux and Windows have different file names. - For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. - -#. If needed, a custom SPI image configuration file can be specified - to override the default one. - - .. code-block:: console - - export EVERGLADES_SPI_CFG=custom_spi_cfg.txt - -Wiring -======== -#. Connect the SPI Dongle ASSY 6791 to ``J44`` in the EVB. - - .. image:: spidongle_assy6791_view1.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip ``U3`` - Make sure that your programmer's offset is 0x0. - For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. - - .. list-table:: Microchip board wiring - :align: center - - * - - .. image:: spidongle_assy6791.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 - - - - .. image:: spidongle_assy6791_view2.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 view 2 - - | - - .. image:: dediprog_connector_2.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - - - .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! - Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. - Wiring connection is described in the table below. - - +------------+---------------+ - | Dediprog | Assy6791 | - | Connector | J6 Connector | - +============+===============+ - | VCC | 1 | - +------------+---------------+ - | GND | 2 | - +------------+---------------+ - | CS | 3 | - +------------+---------------+ - | CLK | 4 | - +------------+---------------+ - | MISO | 6 | - +------------+---------------+ - | MOSI | 5 | - +------------+---------------+ - -#. Connect UART2 port of the MEC15xxEVB_ASSY_6853 board - to your host computer using the RS232 cable. - -#. Apply power to the board via a micro-USB cable. - Configure this option by using a jumper between ``JP88 7-8``. - - .. image:: jp88_power_options.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -#. Final wiring for the board should look like this: - - .. image:: mec_board_setup.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -Building -======== -#. Build :ref:`hello_world` application as you would normally do. - -#. The file :file:`spi_image.bin` will be created if the build system - can find the image generation tool. This binary image can be used - to flash the SPI chip. - -Flashing -======== -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Flash your board using ``west`` from the second terminal window. - Split first and second terminal windows to view both of them. - - .. code-block:: console - - $ west flash - - .. note:: When west process started press Reset button and do not release it - till the whole west process will not be finished successfully. - - .. image:: reset_button_1.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - - - .. note:: If you don't want to press Reset button every time, you can disconnect - SPI Dongle ASSY 6791 from the EVB during the west flash programming. - Then connect it back to the ``J44`` header and apply power to the EVB. - Result will be the same. - - -#. You should see ``"Hello World! mec15xxevb_assy6853"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -Troubleshooting -=============== -#. In case you don't see your application running, please make sure ``LED7``, ``LED8``, and ``LED1`` - are lit. If one of these is off, then check the power-related jumpers again. - -#. If you can't program the board using Dediprog, disconnect the Assy6791 - from the main board Assy6853 and try again. - -#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. - -Notes -===== -#. To enable PCA9555PW and test the I2C on mec15xxevb_assy6853, additional works are needed: - - As the I2C slave device NXP pca95xx on mec15xxevb_assy6853 is connected to I2C00 port, - however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, - so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use - I2C01 port by making some jumpers setting as below: - - * JP99 1-2 Connected Connect I2C01_SDA from CPU to header J5 - * JP99 13-14 Connected Connect I2C01_SCL from CPU to header J5 - * JP25 21-22 Connected External pull-up for I2C01_SDA - * JP25 23-24 Connected External pull-up for I2C01_SCL - * - * JP44.1 J5.1 Connected Connect NXP PCA95xx to I2C01 - * JP44.3 J5.3 Connected Connect NXP PCA95xx to I2C01 - - -References -********** -.. target-notes:: - -.. _MEC1501 Preliminary Data Sheet: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf -.. _MEC1501 Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf -.. _MEC152x Preliminary Data Sheet: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC152x Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf -.. _MEC15xx EVB Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/Everglades%20EVB%20-%20Assy_6853%20Rev%20A1p1%20-%20SCH.pdf -.. _MEC1501 Daughter Card Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6883%20Rev%20A0p1%20-%20SCH.pdf -.. _MEC1503 Daughter Card Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1503%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6856%20Rev%20A1p0%20-%20SCH.pdf -.. _SPI Dongle Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf -.. _MEC152x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen -.. _MEC150x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen -.. _SF100 Linux GitHub: - https://github.com/DediProgSW/SF100Linux -.. _SF100 Product page: - https://www.dediprog.com/product/SF100 -.. _SF100 Linux manual: - https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec172xevb_assy6906/Kconfig.board b/boards/arm/mec172xevb_assy6906/Kconfig.board deleted file mode 100644 index df628d000ee028..00000000000000 --- a/boards/arm/mec172xevb_assy6906/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC172XEVB_ASSY6906 - bool "Microchip MEC172X EVB ASSY 6906 Development board" - depends on SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xevb_assy6906/Kconfig.defconfig b/boards/arm/mec172xevb_assy6906/Kconfig.defconfig deleted file mode 100644 index 8b23b520e1f6d4..00000000000000 --- a/boards/arm/mec172xevb_assy6906/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC172XEVB_ASSY6906 - -config BOARD - default "mec172xevb_assy6906" - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 Hz. -# The driver requires tickless mode and ticks per second to be 32768 for -# accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR -# processor clock divider register. We assume PCR processor clock divider -# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 96000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC172XEVB_ASSY6906 diff --git a/boards/arm/mec172xevb_assy6906/doc/index.rst b/boards/arm/mec172xevb_assy6906/doc/index.rst deleted file mode 100644 index b42aba76310d02..00000000000000 --- a/boards/arm/mec172xevb_assy6906/doc/index.rst +++ /dev/null @@ -1,479 +0,0 @@ -.. _mec172xevb_assy6906: - -Microchip MEC172xEVB ASSY6906 -############################# - -Overview -******** - -The MEC172xEVB_ASSY6906 kit is a future development platform to evaluate the -Microchip MEC172X series microcontrollers. This board needs to be mated with -part number MEC172x 144WFBGA SOLDER DC ASSY 6914 (cpu board) in order to operate. -MEC172x and MEC152x SPI image formats are not compatible with each other. - -.. image:: mec172xevb_assy6906.jpg - :align: center - :alt: MEC172X EVB ASSY 6906 - -Hardware -******** - -- MEC172x ARM Cortex-M4 Processor -- 416 KB RAM and 128 KB boot ROM -- Keyboard interface -- ADC & GPIO headers -- UART0 and UART1 -- FAN0, FAN1, FAN2 headers -- FAN PWM interface -- JTAG/SWD, ETM and MCHP Trace ports -- PECI interface 3.0 -- I2C voltage translator -- 10 SMBUS headers -- VCI interface -- 1 Hardware Driven PS/2 Port -- eSPI header -- 2 Sockets for SPI NOR chips -- One reset and VCC_PWRDGD pushbuttons -- One external PCA9555 I/O port with jumper selectable I2C address. -- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. -- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. - -For more information about the SOC's please see `MEC172x Reference Manual`_ - -Supported Features -================== - -The mec172xevb_assy6906 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PS/2 | on-chip | ps2 | -+-----------+------------+-------------------------------------+ -| KSCAN | on-chip | kscan | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer | -+-----------+------------+-------------------------------------+ -| RPMFAN | on-chip | Fan speed controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file. - -Connections and IOs -=================== - -This evaluation board kit is comprised of the following HW blocks: - -- MEC172x EVB ASSY 6906 Rev A `MEC172x EVB Schematic`_ -- MEC172x 144WFBGA SOLDER DC ASSY 6914 with MEC172x silicon `MEC172x Daughter Card Schematic`_ -- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ - -System Clock -============ - -The MEC1723 MCU is configured to use the 96Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock -control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in -the references at the end of this document. - -Serial Port -=========== - -UART1 is configured for serial logs. - -Jumper settings -*************** - -Please follow the jumper settings below to properly demo this -board. Advanced users may deviate from this recommendation. - -Jumper setting for MEC172x EVB Assy 6906 Rev A1p0 -================================================= - -Power-related jumpers ---------------------- - -If you wish to power from +5V power brick, then connect to barrel connector ``P1`` -(5.5mm OD, 2.1mm ID) and move the jumper to ``JP30 5-6``. - -If you wish to power from micro-USB type A/B connector ``P2``, move the -jumper to ``JP30 7-8``. - - -.. note:: A single jumper is required in ``JP30``. - -+------+-------+-------+------+------+ -| JP31 | JP158 | JP159 | JP40 | JP42 | -+======+=======+=======+======+======+ -| 2-3 | 2-3 | 2-3 | 1-2 | 1-2 | -+------+-------+-------+------+------+ - -+------+------+------+------+------+------+------+ -| JP36 | JP37 | JP38 | JP39 | JP41 | JP43 | JP44 | -+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+ - -+------+------+------+------+------+------+------+------+------+ -| JP45 | JP46 | JP47 | JP50 | JP51 | JP52 | JP55 | JP56 | JP57 | -+======+======+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+------+------+ - -+------+------+------+------+------+------+------+ -| JP59 | JP60 | JP61 | JP62 | JP63 | JP65 | JP66 | -+======+======+======+======+======+======+======+ -| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | -+------+------+------+------+------+------+------+ - -These jumpers configure VCC Power good and nRESET_IN. - -+------------------+-------------+ -| JP32 | JP33 | -| (VCC Power good) | (nRESET_IN) | -+==================+=============+ -| 1-2 | 1-2 | -+------------------+-------------+ - -Boot-ROM Straps ---------------- - -These jumpers configure MEC172x Boot-ROM straps. - -+------------+--------------+-------------+-------------+---------------+ -| JP1 | JP2 | JP3 | JP7 | JP160 | -| (CR_STRAP) | (JTAG_STRAP) | (CMP_STRAP) | (BSS_STRAP) | (UART_BSTRAP) | -+============+==============+=============+=============+===============+ -| 1-2 | 2-3 | 2-3 | 1-2 | 1-2 | -+------------+--------------+-------------+-------------+---------------+ - -``JP7 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples -SHD SPI CS0# and if high, it loads code from SHD SPI. - -Peripheral Routing Jumpers --------------------------- - -Each column of the following table illustrates how to enable UART0, UART1, SHD SPI -and SWD, respectively. - -+-------+-------+------+------+------+------+------+ -| UART0 (P11) | -+-------+-------+------+------+------+------+------+ -| JP13 | JP17 | JP19 | JP22 | JP88 | JP89 | JP93 | -+=======+=======+======+======+======+======+======+ -| 2-3 | 2-3 | 1-2 | 1-2 | 2-3 | 2-3 | 1-3 | -+-------+-------+------+------+------+------+------+ -| 5-6 | 5-6 | 4-5 | 4-5 | | | 2-4 | -+-------+-------+------+------+------+------+------+ -| 8-9 | 8-9 | | | | | | -+-------+-------+------+------+------+------+------+ -| 11-12 | 11-12 | | | | | | -+-------+-------+------+------+------+------+------+ -| 14-15 | 14-15 | | | | | | -+-------+-------+------+------+------+------+------+ -| 17-18 | 17-18 | | | | | | -+-------+-------+------+------+------+------+------+ -| | 20-21 | | | | | | -+-------+-------+------+------+------+------+------+ -| | 23-24 | | | | | | -+-------+-------+------+------+------+------+------+ - -+------+------+-------+-------+------+------+-------+-----+--------+------+------+------+-------+ -| UART1 | -+---------------------------------------------------+-------------------------------------------+ -| (P12) | (P2) | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| JP11 | JP14 | JP19 | JP24 | JP90 | JP94 | JP157 | JP11 | JP19 | JP24 | JP90 | JP94 | JP157 | -+======+======+=======+=======+======+======+=======+======+=======+======+======+======+=======+ -| 1-2 | 1-2 | 20-21 | 2-3 | 2-3 | 1-3 | 1-2 | 1-2 | 11-12 | 5-6 | 2-3 | 1-3 | 1-3 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| 4-5 | | | 5-6 | | 2-4 | 4-5 | 4-5 | | 8-9 | | 2-4 | 4-6 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| 8-9 | | | 8-9 | | | 7-8 | | |17-18 | | | 7-9 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| | | | 11-12 | | | 10-11 | | |23-24 | | | 10-12 | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| | | | 14-15 | | | | | | | | | | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ -| | | | 17-18 | | | | | | | | | | -+------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ - -NOTE: The "Hello World" example outputs at ``UART1 P12`` . - -+----------------------+-------+--------+ -| SHD_SPI | SWD | LED4-5 | -+-------+------+-------+-------+--------+ -| JP23 | JP25 | JP156 | J18 | JP21 | -+=======+======+=======+=======+========+ -| 2-3 | 1-2 | 1-2 | 8-9 | 4-5 | -+-------+------+-------+-------+--------+ -| 8-9 | | | 11-12 | 16-17 | -+-------+------+-------+-------+--------+ -| 14-15 | | | | | -+-------+------+-------+-------+--------+ -| 17-18 | | | | | -+-------+------+-------+-------+--------+ - -Jumper settings for MEC172x 144WFBGA Socket DC Assy 6914 Rev A0p1 -================================================================= - -The jumper configuration explained above covers the base board. The ASSY -6914 MEC172x CPU board provides capability for an optional, external 32KHz -clock source. The card includes a 32KHz crystal oscillator. The card can -also be configured to use an external 50% duty cycle 32KHz source on the -XTAL2/32KHZ_IN pin. Note, firmware must set the MEC172x clock enable -register to select the external source matching the jumper settings. If -using the MEC172x internal silicon oscillator then the 32K jumper settings -are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please -refer to the schematic in reference section below. - -Parallel 32KHz crystal configuration ------------------------------------- - -+-------+-------+ -| JP1 | JP2 | -+=======+=======+ -| 1-2 | 2-3 | -+-------+-------+ - -External 32KHz 50% duty cycle configuration -------------------------------------------- - -+-------+-------+ -| JP2 | JP3 | -+=======+=======+ -| NC | 1-2 | -+-------+-------+ - -NOTE: ``JP121 3-4`` on base board also needs to be loaded. - - -Programming and Debugging -************************* - -Setup -===== - -#. If you use Dediprog SF100 programmer, then setup it. - - Windows version can be found at the `SF100 Product page`_. - - Linux version source code can be found at `SF100 Linux GitHub`_. - Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. - For Linux please make sure that you copied ``60-dediprog.rules`` - from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) - then restart service using: - - .. code-block:: console - - $ udevadm control --reload - - Add directory with program ``dpcmd`` (on Linux) - or ``dpcmd.exe`` (on Windows) to your ``PATH``. - -#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within - that directory. - -#. Make the image generation available for Zephyr, by making the tool - searchable by path, or by setting an environment variable - ``MEC172X_SPI_GEN``, for example: - - .. code-block:: console - - export MEC172X_SPI_GEN=/mec172x_spi_gen_lin_x86_64 - - Note that the tools for Linux and Windows have different file names. - -#. The default MEC172X_SPI_CFG file is spi_cfg.txt located in ${BOARD_DIR}/support. - If needed, a custom SPI image configuration file can be specified to override the - default one. - - .. code-block:: console - - export MEC172X_SPI_CFG=custom_spi_cfg.txt - -Wiring -======== - -#. Connect the SPI Dongle ASSY 6791 to ``J34`` in the EVB. - - .. image:: spidongle_assy6791.jpg - :align: center - :alt: SPI DONGLE ASSY 6791 Connected - -#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip - ``U3``. Make sure that your programmer's offset is 0x0. - For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. - - .. image:: dediprog_connector.jpg - :align: center - :alt: SF100 Connected - - - .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! - Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. - Wiring connection is described in the table below. - - +------------+---------------+ - | Dediprog | Assy6791 | - | Connector | J6 Connector | - +============+===============+ - | VCC | 1 | - +------------+---------------+ - | GND | 2 | - +------------+---------------+ - | CS | 3 | - +------------+---------------+ - | CLK | 4 | - +------------+---------------+ - | MISO | 6 | - +------------+---------------+ - | MOSI | 5 | - +------------+---------------+ - -#. Connect UART1 port of the MEC17xxEVB_ASSY_6906 board - to your host computer using the RS232 cable. - -#. Apply power to the board via a micro-USB cable. - Configure this option by using a jumper between ``JP30 7-8``. - - .. image:: jp30_power_options.jpg - :align: center - :alt: Power Connection - -Building -======== - -#. Build :ref:`hello_world` application as you would normally do. - -#. The file :file:`spi_image.bin` will be created if the build system - can find the image generation tool. This binary image can be used - to flash the SPI chip. - -Flashing -======== - -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Flash your board using ``west`` from the second terminal window. - Split first and second terminal windows to view both of them. - - .. code-block:: console - - $ west flash - - .. note:: When west process started press Reset button ``S2`` and do not release it - till the whole west process will not be finished successfully. - - .. image:: Reset_Button.jpg - :align: center - :alt: Reset Button - - .. note:: If you don't want to press Reset button every time, you can disconnect - SPI Dongle ASSY 6791 from the EVB during the west flash programming. - Then connect it back to the ``J34`` header and apply power to the EVB. - Result will be the same. - - -#. You should see ``"Hello World! mec172xevb_assy6906"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -Troubleshooting -=============== - -#. In case you don't see your application running, please make sure ``LED1`` and ``LED2`` - are lit. If one of these is off, then check the power-related jumpers again. - -#. If you can't program the board using Dediprog, disconnect the Assy6791 - from the main board Assy6906 and try again. - -#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. - -PCA9555 Enabling -================ -#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed: - - As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port, - however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, - so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use - I2C01 port by making some jumpers setting as below: - - +---------+---------+------------------------------------------+ - | Pin 1 | Pin 2 | Comment | - +=========+=========+==========================================+ - | JP49.1 | JP49.2 | Connect PCA9555 VCC to +3.3V_STBY | - +---------+---------+------------------------------------------+ - | JP53.1 | JP53.2 | Select address 0100b, which means 0x26 | - +---------+---------+------------------------------------------+ - | JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 | - +---------+---------+------------------------------------------+ - | JP12.4 | JP12.5 | Connect I2C01_SCL from CPU to header J20 | - +---------+---------+------------------------------------------+ - | JP77.7 | JP77.8 | External pull-up for I2C01_SDA | - +---------+---------+------------------------------------------+ - | JP77.9 | JP77.10 | External pull-up for I2C01_SCL | - +---------+---------+------------------------------------------+ - | JP58.1 | JP20.1 | Connect NXP PCA9555 SCL to I2C01 | - +---------+---------+------------------------------------------+ - | JP58.3 | JP20.3 | Connect NXP PCA9555 SDA to I2C01 | - +---------+---------+------------------------------------------+ - -References -********** - -.. target-notes:: - -.. _MEC172x Reference Manual: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf -.. _MEC172x EVB Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-EVB-Assy_6906-A1p0-SCH.pdf -.. _MEC172x Daughter Card Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-144WFBGA-Socket-DC-Assy6914-Rev-A-SCH.pdf -.. _SPI Dongle Schematic: - https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf -.. _MEC172x SPI Image Gen: - https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC172x/SPI_image_gen -.. _SF100 Linux GitHub: - https://github.com/DediProgSW/SF100Linux -.. _SF100 Product page: - https://www.dediprog.com/product/SF100 -.. _SF100 Linux manual: - https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig deleted file mode 100644 index 63e6a6be73b776..00000000000000 --- a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021, Microchip Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MEC172X_NSZ=y -CONFIG_SOC_SERIES_MEC172X=y -CONFIG_BOARD_MEC172XEVB_ASSY6906=y -CONFIG_RTOS_TIMER=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/mec172xmodular_assy6930/Kconfig.board b/boards/arm/mec172xmodular_assy6930/Kconfig.board deleted file mode 100644 index bfcfda0bcc38f2..00000000000000 --- a/boards/arm/mec172xmodular_assy6930/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022, Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MEC172XMODULAR_ASSY6930 - bool "Microchip MEC172X MODULAR ASSY 6930 Development board" - depends on SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xmodular_assy6930/Kconfig.defconfig b/boards/arm/mec172xmodular_assy6930/Kconfig.defconfig deleted file mode 100644 index 347f4efdd6bef8..00000000000000 --- a/boards/arm/mec172xmodular_assy6930/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2022 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MEC172XMODULAR_ASSY6930 - -config BOARD - default "mec172xmodular_assy6930" - -if RTOS_TIMER - -# XEC RTOS timer HW frequency is fixed at 32768 Hz. -# The driver requires tickless mode and ticks per second to be 32768 for -# accurate operation. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -endif # RTOS_TIMER - -if !RTOS_TIMER - -# If RTOS timer is not enabled we use ARM Cortex-M -# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR -# processor clock divider register. We assume PCR processor clock divider -# is set to 1. Refer to SOC_MEC172X_PROC_CLK_DIV -# - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 96000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -endif # RTOS_TIMER - -endif # BOARD_MEC172XMODULAR_ASSY6930 diff --git a/boards/arm/mercury_xu/CMakeLists.txt b/boards/arm/mercury_xu/CMakeLists.txt deleted file mode 100644 index 191e22a607beb8..00000000000000 --- a/boards/arm/mercury_xu/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2020, Antmicro -# SPDX-License-Identifier: Apache-2.0 -zephyr_library() -zephyr_library_sources(board.c) diff --git a/boards/arm/mercury_xu/Kconfig.board b/boards/arm/mercury_xu/Kconfig.board deleted file mode 100644 index 929cf6db518abb..00000000000000 --- a/boards/arm/mercury_xu/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2020, Antmicro -# SPDX-License-Identifier: Apache-2.0 -config BOARD_MERCURY_XU - bool "Mercury XU Board" - depends on SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/mercury_xu/Kconfig.defconfig b/boards/arm/mercury_xu/Kconfig.defconfig deleted file mode 100644 index 856e4d2ac01767..00000000000000 --- a/boards/arm/mercury_xu/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020, Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MERCURY_XU - -config BOARD - default "mercury_xu" - -config FLASH_SIZE - int - default 64 - -config FLASH_BASE_ADDRESS - default 0x08000000 - -endif diff --git a/boards/arm/mercury_xu/mercury_xu_defconfig b/boards/arm/mercury_xu/mercury_xu_defconfig deleted file mode 100644 index d01d7082f946de..00000000000000 --- a/boards/arm/mercury_xu/mercury_xu_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020, Antmicro -CONFIG_SOC_XILINX_ZYNQMP_RPU=y -CONFIG_BOARD_MERCURY_XU=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable timer -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 - -CONFIG_PINCTRL=y diff --git a/boards/arm/mg100/Kconfig.board b/boards/arm/mg100/Kconfig.board deleted file mode 100644 index 59779d555c5ee2..00000000000000 --- a/boards/arm/mg100/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MG100 - bool "MG100" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/mg100/Kconfig.defconfig b/boards/arm/mg100/Kconfig.defconfig deleted file mode 100644 index 46091ee3b47e35..00000000000000 --- a/boards/arm/mg100/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2022 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MG100 - -config BOARD - default "mg100" - -config MODEM - default NETWORKING - -config MODEM_HL7800 - default NETWORKING - -config NORDIC_QSPI_NOR - default BOOTLOADER_MCUBOOT - -config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 if NORDIC_QSPI_NOR - -config REGULATOR - default DISK_DRIVER_SDMMC - -config BT_CTLR - default BT - -endif # BOARD_MG100 diff --git a/boards/arm/mg100/doc/index.rst b/boards/arm/mg100/doc/index.rst deleted file mode 100644 index 6e1ef2bfe531e3..00000000000000 --- a/boards/arm/mg100/doc/index.rst +++ /dev/null @@ -1,249 +0,0 @@ -.. _mg100: - -Laird Connectivity Sentrius™ MG100 Gateway -########################################## - -Overview -******** -The Sentrius™ MG100 Gateway offers a compact, out of box Bluetooth to low power cellular gateway -solution. - -Based on the Pinnacle 100 socket modem, the Sentrius™ MG100 gateway captures data from any -Bluetooth 5 modules or devices and sends it to the cloud via a global low power cellular -(LTE-M/NB-IoT) connection. The MG100 seamlessly incorporates a powerful Cortex M4F controller, -full Bluetooth 5 connectivity, and dual-mode LTE-M/NB-IoT capabilities. The MG100 has full regulatory -and network certifications and End Device carrier approvals. - -Develop your application directly on the integrated Cortex M4F microcontroller using Zephyr RTOS, -enabling your application development with a secure, open source RTOS with more than just kernel -services. Remotely debug your fleet of devices with the `Memfault Platform`_. Take advantage of the -Zephyr community and Laird Connectivity’s multi featured Out of Box (OOB) sample source code -covering all aspects of the product's capabilities and hardware interfaces. The MG100 also delivers -complete antenna flexibility with internal or external antenna options available, and the optional -battery backup provides uninterrupted reporting of remote Bluetooth sensor data. - -More information about the board can be found at the `MG100 website`_. - -The MG100 hardware provides support for the Nordic Semiconductor `nRF52840`_ ARM Cortex-M4F CPU, -`Sierra Wireless HL7800`_ -and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* :abbr:`LIS3DH (ST Micro 3-axis MEMS accelerometer)` -* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` -* :abbr:`SD Card` - -.. figure:: img/mg100.jpg - :align: center - :alt: MG100 - - MG100 (450-00054-K1) - -Hardware -******** - -Supported Features -================== - -The MG100 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| LIS3DH | I2C(M) | sensor/lis3dh | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ -| SDMMC | SPI(M) | SD Card via SPI | -+-----------+------------+----------------------+ - -See `MG100 website`_ for a complete list -of MG100 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P1.7 -* LED2 (blue) = P1.6 -* LED3 (green) = P1.5 - -Push buttons ------------- - -* BUTTON1 = P0.3 - -External flash memory ---------------------- - -A 64Mbit external flash memory part is available for storage of application -images and data. Refer to the `Macronix MX25R6435F datasheet`_ for further -details. - -The flash memory is connected to the on-board QSPI device controller. - -* MX25R64 = QSPI - -SCK = P0.19 -IO0 = P0.20 -IO1 = P0.21 -IO2 = P0.22 -IO3 = P0.23 -CSN = P0.17 - -LIS3DH Motion Sensor --------------------- - -Motion sensor to detect if the gateway moves. - -IRQ IO = P0.28 -I2C SDA = P0.26 -I2C SCL = P0.27 - -SD Card -------- - -SD card used to store large amounts of data. - -SPI CS = P0.29 -SPI SCK = P1.09 -SPI MOSI = P0.11 -SPI MISO = P0.12 - -Programming and Debugging -************************* - -Applications for the ``mg100`` board configuration can be -built and flashed in the usual way. (see :ref:`build_an_application` -and :ref:`application_run` for more details) - -The `Laird Connectivity USB-SWD Programming Kit`_ contains all the necessary -hardware to enable programming and debugging an MG100. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. note:: On the MG100, - the USB connector should be used to access the UART console. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board MG100 -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mg100 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Software -******** - -MG100 Out-of-Box Demo Software -============================== -The MG100 ships with an out of the box software demo. -Check out the `BLE Gateway OOB Demo`_ source code and documentation. - -Testing Bluetooth on the MG100 -============================== -Many of the Bluetooth examples will work on the MG100. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -Testing the LEDs and buttons in the MG100 -==================================================== - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/mg100/mg100.dts`. - -References -********** - -.. target-notes:: - -.. _MG100 website: https://www.lairdconnect.com/iot-devices/iot-gateways/sentrius-mg100-gateway-lte-mnb-iot-and-bluetooth-5 -.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf -.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _BLE Gateway OOB Demo: https://github.com/LairdCP/Pinnacle-100-Firmware-Manifest -.. _Macronix MX25R6435F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf -.. _Laird Connectivity USB-SWD Programming Kit: https://www.lairdconnect.com/wireless-modules/programming-kits/usb-swd-programming-kit -.. _Memfault Platform: https://docs.memfault.com/docs/mcu/pinnacle-100-guide -.. _nRF52840: https://www.nordicsemi.com/products/nrf52840 diff --git a/boards/arm/mikroe_clicker_2/Kconfig.board b/boards/arm/mikroe_clicker_2/Kconfig.board deleted file mode 100644 index 81e95e3fd3b45c..00000000000000 --- a/boards/arm/mikroe_clicker_2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# MikroE Clicker 2 board configuration - -# Copyright (c) 2020 Trifork -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIKROE_CLICKER_2 - bool "MikroE Clicker 2 for STM32 board" - depends on SOC_STM32F407XG diff --git a/boards/arm/mikroe_clicker_2/Kconfig.defconfig b/boards/arm/mikroe_clicker_2/Kconfig.defconfig deleted file mode 100644 index 08a87aeca7607b..00000000000000 --- a/boards/arm/mikroe_clicker_2/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MikroE Clicker 2 board configuration - -# Copyright (c) 2020 Trifork -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIKROE_CLICKER_2 - -config BOARD - default "mikroe_clicker_2" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif #BOARD_MIKROE_CLICKER_2 diff --git a/boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig b/boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig deleted file mode 100644 index 15ade5bcf58a3c..00000000000000 --- a/boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_BOARD_MIKROE_CLICKER_2=y -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.board b/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.board deleted file mode 100644 index 5680d9a0846005..00000000000000 --- a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Mikroe MINI-M4 for STM32 board configuration - -# Copyright (c) 2019, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIKROE_MINI_M4_FOR_STM32 - bool "Mikroe MINI-M4 for STM32 Board" - depends on SOC_STM32F415XX diff --git a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig b/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig deleted file mode 100644 index 3a2bbe8f5d4b74..00000000000000 --- a/boards/arm/mikroe_mini_m4_for_stm32/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Mikroe MINI-M4 for STM32 board configuration - -# Copyright (c) 2019, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIKROE_MINI_M4_FOR_STM32 - -config BOARD - default "mikroe_mini_m4_for_stm32" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_MIKROE_MINI_M4_FOR_STM32 diff --git a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig b/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig deleted file mode 100644 index 3f0ccc9cca7469..00000000000000 --- a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_BOARD_MIKROE_MINI_M4_FOR_STM32=y -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F415XX=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mm_evk/Kconfig.board b/boards/arm/mimx8mm_evk/Kconfig.board deleted file mode 100644 index 0e7c9865cf1b2c..00000000000000 --- a/boards/arm/mimx8mm_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MM EVK board - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MM_EVK - bool "NXP i.MX8M Mini EVK" - depends on SOC_SERIES_IMX8MM_M4 - select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/arm/mimx8mm_evk/Kconfig.defconfig b/boards/arm/mimx8mm_evk/Kconfig.defconfig deleted file mode 100644 index aee76b9834b99f..00000000000000 --- a/boards/arm/mimx8mm_evk/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# MIMX8MM EVK board defconfig - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MM_EVK - -config BOARD - default "mimx8mm_evk" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MM_EVK diff --git a/boards/arm/mimx8mm_evk/doc/img/mimx8mm_evk.jpg b/boards/arm/mimx8mm_evk/doc/img/mimx8mm_evk.jpg deleted file mode 100644 index b1ec0526df2902..00000000000000 Binary files a/boards/arm/mimx8mm_evk/doc/img/mimx8mm_evk.jpg and /dev/null differ diff --git a/boards/arm/mimx8mm_evk/doc/index.rst b/boards/arm/mimx8mm_evk/doc/index.rst deleted file mode 100644 index b482c28cfaa876..00000000000000 --- a/boards/arm/mimx8mm_evk/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _mimx8mm_evk: - -NXP MIMX8MM EVK -############### - -Overview -******** - -i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -.. image:: img/mimx8mm_evk.jpg - :align: center - :alt: MIMX8MM EVK - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mm_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig`. - -It is recommended to disable peripherals used by the M4 core on the Linux host. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -MIMX8MM EVK board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART4 RXD | UART4_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART4 TXD | UART4_RXD | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 400 MHz clock speed. - -Serial Port -=========== - -The i.MX8M Mini SoC has four UARTs. UART_4 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The MIMX8MM EVK board doesn't have QSPI flash for the M4 and it needs -to be started by the A53 core. The A53 core is responsible to load the M4 binary -application into the RAM, put the M4 in reset, set the M4 Program Counter and -Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/mimx8mm_evk/mimx8mm_evk.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &tcml_code - - &ocram_code - - &ocram_s_code - - "zephyr,sram" - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - -Load and run Zephyr on M4 from A53 using u-boot by copying the compiled -``zephyr.bin`` to the first FAT partition of the SD card and plug the SD -card into the board. Power it up and stop the u-boot execution at prompt. - -Load the M4 binary onto the desired memory and start its execution using: - -.. code-block:: console - - fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000 - -Debugging -========= - -MIMX8MM EVK board can be debugged by connecting an external JLink -JTAG debugger to the J902 debug connector and to the PC. Then -the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mm_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 ***** - Hello World! mimx8mm_evk - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MMRM diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi b/boards/arm/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi deleted file mode 100644 index c7b1943810eb03..00000000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022, NXP - * SPDX-License-Identifier: Apache-2.0 - * - * Note: File generated by gen_board_pinctrl.py - * from MIMX8MM-EVK-REV-C.mex - */ - -#include - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - slew-rate = "fast"; - drive-strength = "40-ohm"; - }; - }; - -}; diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk.dts b/boards/arm/mimx8mm_evk/mimx8mm_evk.dts deleted file mode 100644 index e0711636f55031..00000000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk.dts +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2020, Manivannan Sadhasivam - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -#include "mimx8mm_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8M Mini EVK board"; - compatible = "nxp,mimx8mm_evk"; - - aliases { - uart-4 = &uart4; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk.yaml b/boards/arm/mimx8mm_evk/mimx8mm_evk.yaml deleted file mode 100644 index 4c1779778ba799..00000000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2020, Manivannan Sadhasivam -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mm_evk -name: NXP i.MX8M Mini EVK -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig b/boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig deleted file mode 100644 index f51c8ac2b109d5..00000000000000 --- a/boards/arm/mimx8mm_evk/mimx8mm_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020, Manivannan Sadhasivam -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8MM_M4=y -CONFIG_SOC_MIMX8MM6=y -CONFIG_BOARD_MIMX8MM_EVK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mm_phyboard_polis/Kconfig.board b/boards/arm/mimx8mm_phyboard_polis/Kconfig.board deleted file mode 100644 index c7079f5d912a9a..00000000000000 --- a/boards/arm/mimx8mm_phyboard_polis/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MM_PHYBOARD_POLIS board configuration - -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MM_PHYBOARD_POLIS - bool "Phytec Phyboard Polis i.MX8M Mini" - depends on SOC_SERIES_IMX8MM_M4 - select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/arm/mimx8mm_phyboard_polis/Kconfig.defconfig b/boards/arm/mimx8mm_phyboard_polis/Kconfig.defconfig deleted file mode 100644 index 1e0191ff7ba4ed..00000000000000 --- a/boards/arm/mimx8mm_phyboard_polis/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# MIMX8MM_PHYBOARD_POLIS board defconfig -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MM_PHYBOARD_POLIS - -config BOARD - default "mimx8mm_phyboard_polis" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MM_PHYBOARD_POLIS diff --git a/boards/arm/mimx8mm_phyboard_polis/board.cmake b/boards/arm/mimx8mm_phyboard_polis/board.cmake deleted file mode 100644 index 3b202648575d9d..00000000000000 --- a/boards/arm/mimx8mm_phyboard_polis/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_set_debugger_ifnset(jlink) -board_set_flasher_ifnset(jlink) - -board_runner_args(jlink "--device=MIMX8MD6_M4") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/mimx8mm_phyboard_polis/doc/index.rst b/boards/arm/mimx8mm_phyboard_polis/doc/index.rst deleted file mode 100644 index 3d44ddcc87a833..00000000000000 --- a/boards/arm/mimx8mm_phyboard_polis/doc/index.rst +++ /dev/null @@ -1,342 +0,0 @@ -.. _mimx8mm_phyboard_polis: - -PhyBOARD Polis (NXP i.MX8M Mini) -################################ - -Overview -******** - -The phyBOARD-Polis, either a development platform for the -phyCORE-i.MX 8M Mini/Nano, or a powerful, industry-compatible single-board -computer for immediate implementation of your product idea. As a development -platform, the phyBOARD-Polis serves as reference design for your -customer-specific application and enables parallel development of the software -and carrier board for the phyCORE-i.MX 8M Mini/Nano. - - -As a powerful, industrial single-board computer (SBC), the phyBOARD-Polis is -equipped with a variety of standard interfaces which are available on standard -or socket/pin header connectors, while interesting extensions of the -phyCORE-i.MX 8M Mini/Nano features such as CAN FD, WLAN and an integrated -TPM chip further extend the range of applications that can be developed with -the phyCORE-i.MX 8M Mini/Nano. - -- Board features: - - - RAM: 512MB - 4GB (LPDDR4) - - Storage: - - - 4GB - 128GB eMMC - - 8MB - 128MB SPI NOR Flash - - microSD Interfacce - - 4kB EEPROM - - Wireless: - - - WiFi: 802.11 b/g/n (ac) 2,4 GHz / 5 GHz - - BLE 4.2 - - USB: - - - 1x USB2.0 OTG - - 1x USB2.0 - - Ethernet: 1x 10/100/1000BASE-T - - Interfaces: - - 1x RS232 / RS485 - - 2x UART - - 3x I²C - - 2x SPI - - Up to 4x PWM - - 4x SAI - - 1x MIPI CSI-2 - - 1x MIPI DSI-2 - - 2x MMC/SD/SDIO - - 1x PCIe (mini PCIE) - - LEDs: - - - 1x Status LED (3 Color LED) - - 1x Debug UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -.. image:: img/phyBOARD-Polis.jpg - :align: center - :alt: PhyBOARD Polis - :width: 500 - -More information about the board can be found at the -`PHYTEC website`_. - -Supported Features -================== - -The Zephyr mimx8mm_phyboard_polis board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig`. - -It is recommended to disable peripherals used by the M4 core on the Linux host. - -Other hardware features are not currently supported with Zephyr on the -M4-Core. - -Connections and IOs -=================== - -The following components are tested and working correctly. - -UART: ------ - -Zephyr is configured to use UART4 on the PhyBoard Polis by default to minimize -problems with the A53-Core because UART4 is only accessible from the M4-Core. - -+---------------+-----------------+-----------------------------------+ -| Board Name | SoM Name | Usage | -+===============+=================+===================================+ -| RS232/485 | UART1 | RS232 / RS485 with flow-control | -+---------------+-----------------+-----------------------------------+ -| To WiFi Module| UART2 | UART to WiFi/BLE Module | -+---------------+-----------------+-----------------------------------+ -| Debug USB(A53)| UART3 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ -| Debug USB(M4) | UART4 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ - -.. note:: - Please note, that the to UART2 connected Wifi/BLE Module isn't working with - Zephyr yet. - -.. warning:: - On Boards with the version number 1532.1 UART4 isn't connected to the Debug - USB. UART4 connects to pin 10(RX) and 12(TX) on the X8 pinheader. - - -LEDs: ------ - -Zephyr has the 3-color status LED configured. The led0 alias (the standard -Zephyr led) is configured to be the blue led. The LED can also light up in red -and green. - -GPIO: ------ - -The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mm devicetree -created by NXP. You can find it here: - -:zephyr_file:`dts/arm/nxp/nxp_imx8m_m4.dtsi`. - -The Pinout of the PhyBOARD Polis can be found here: - -`PHYTEC website`_ - -System Clock -============ - -The M4 Core is configured to run at a 400 MHz clock speed. - - -Programming and Debugging -************************* - -The i.MX8MM does not have a separate flash for the M4-Core. Because of this -the A53-Core has to load the program for the M4-Core to the right memory -address, set the PC and start the processor. -This can be done with U-Boot or Phytec's Linux BSP via remoteproc. - -Because remoteproc in Phytec's BSP only writes to the TCM memory area, -everything was tested in this memory area. - -You can read more about remoteproc in Phytec's BSP here: `Remoteproc BSP`_ - -These are the memory mapping for A53 and M4: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/mimx8mm_evk/mimx8mm_evk.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -If you don't want to use the TCM memory area, you can either overwrite the -boards devicetree in your program or edit the board devicetree located here: - -:zephyr_file:`boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.dts` - -You also have to set XIP=n or edit the boards defconfig file, if you don't want -the TCM memory area to be used. You can find the defconf file here: - -:zephyr_file:`boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig`. - -The following configurations are possible for the flash and sram chosen nodes -to change the used memory area: - -.. code-block:: none - - "zephyr,flash" - - &tcml_code - - &ocram_code - - &ocram_s_code - - "zephyr,sram" - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - -Starting the M4-Core via U-Boot -=============================== - -Load the compiled zephyr.bin to memory address 0x4800000. -This should output something like this: - -.. code-block:: console - - u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin - Using ethernet@30be0000 device - TFTP from server 192.168.3.10; our IP address is 192.168.3.11 - Filename 'zepyhr.bin'. - Load address: 0x48000000 - Loading: ## - 2 KiB/s - done - Bytes transferred = 27240 (6a68 hex) - -Because it's not possible to load directly to the TCM memory area you have to -copy the binaries. The last argument given is the size of the file in bytes, -you can copy it from the output of the last command. - -.. code-block:: console - - u-boot=> cp.b 0x48000000 0x7e0000 27240 - -And finaly starting the M4-Core at the right memory address: - -.. code-block:: console - - u-boot=> bootaux 0x7e0000 - ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... - - -Starting the M4-Core via remoteproc -=================================== - -Copy the zepyhr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample -will be included in a future BSP release. - -.. note:: - In order to use remoteproc you have to add ``imx8mm-phycore-rpmsg.dtbo`` at - the end of the line in the ``/boot/bootenv.txt``, then reboot the target. - -.. warning:: - Remoteproc only reads firmware files from the ``/lib/firmware`` directory! - If you try to load a binary from another location unexpected errors will - occur! - -To load and start a firmware use this commands: - -.. code-block:: console - - target$ echo /lib/firmware/zepyhr.elf > /sys/class/remoteproc/remoteproc0/firmware - target$ echo start > /sys/class/remoteproc/remoteproc0/state - [ 90.700611] remoteproc remoteproc0: powering up imx-rproc - [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zepyhr.elf failed w2 - [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zepyhr.elf - [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zepyhr.elf, size 599356 - [ 90.804448] remoteproc remoteproc0: remote processor imx-rproc is now up - - -The M4-Core is now started up and running. You can see the output from Zephyr -on UART4. - -Debugging -========= - -The PhyBOARD Polis can be debugged using a JTAG Debugger. -The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's -``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. -You can find the JLink Software package here: `JLink Software`_ - -.. figure:: img/PEB-EVAL-01.jpg - :alt: PEB-EVAL-01 - :width: 350 - - PEB-EVAL-01 - -To debug efficiently you should use multiple terminals: - -(But its also possible to use ``west debug``) - -After connecting everything and building with west use this command while in -the directory of the program you build earlier to start a debug server: - -.. code-block:: console - - host$ west debugserver - -West automatically connects via the JLink to the Target. And keeps open a -debug server. - -Use another terminal, start gdb, connect to target and load Zephyr on the -target: - -.. code-block:: console - - host$ gdb-multiarch build/zephyr/zephyr.elf -tui - (gdb) targ rem :2331 - Remote debugging using :2331 - 0x1ffe0008 in _vector_table () - (gdb) mon halt - (gdb) mon reset - (gdb) c - Continuing. - -The program can be debugged using standard gdb techniques. - -.. _PHYTEC website: - https://www.phytec.de/produkte/single-board-computer/phyboard-polis-imx8m-mini/ - -.. _PhyBOARD Polis pinout: - https://download.phytec.de/Products/phyBOARD-Polis-iMX8M_Mini/TechData/phyCORE-i.MX8M_MINI_Pin_Muxing_Table.A1.xlsx?_ga=2.237582016.1177557183.1660563641-1900651135.1634193918 - -.. _Remoteproc BSP: - https://wiki.phytec.com/pages/releaseview.action?pageId=472257137#L1002e.A3i.MX8MMini/NanoBSPManual-RunningExamplesfromLinuxusingRemoteproc - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MMRM - -.. _JLink Software: - https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.yaml b/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.yaml deleted file mode 100644 index 399336291f933e..00000000000000 --- a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2020 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mm_phyboard_polis -name: Phyboard Polis i.MX8M Mini -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig b/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig deleted file mode 100644 index 5b307dafaeceee..00000000000000 --- a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8MM_M4=y -CONFIG_SOC_MIMX8MM6=y -CONFIG_BOARD_MIMX8MM_PHYBOARD_POLIS=y -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y diff --git a/boards/arm/mimx8mp_evk/Kconfig.board b/boards/arm/mimx8mp_evk/Kconfig.board deleted file mode 100644 index 1595301fa29226..00000000000000 --- a/boards/arm/mimx8mp_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MP EVK board - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_EVK - bool "NXP i.MX8M Plus EVK" - depends on SOC_SERIES_IMX8ML_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/mimx8mp_evk/Kconfig.defconfig b/boards/arm/mimx8mp_evk/Kconfig.defconfig deleted file mode 100644 index 41d7a120fd1d50..00000000000000 --- a/boards/arm/mimx8mp_evk/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# MIMX8MP EVK board defconfig - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MP_EVK - -config BOARD - default "mimx8mp_evk" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MP_EVK diff --git a/boards/arm/mimx8mp_evk/board.cmake b/boards/arm/mimx8mp_evk/board.cmake deleted file mode 100644 index d773ef92919ca8..00000000000000 --- a/boards/arm/mimx8mp_evk/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_set_debugger_ifnset(jlink) -board_set_flasher_ifnset(jlink) - -board_runner_args(jlink "--device=MIMX8ML8_M7") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) \ No newline at end of file diff --git a/boards/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg b/boards/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg deleted file mode 100644 index d3cc7cb00dd51b..00000000000000 Binary files a/boards/arm/mimx8mp_evk/doc/img/I.MX8MPLUS-PLUS-EVK-TOP.jpg and /dev/null differ diff --git a/boards/arm/mimx8mp_evk/doc/index.rst b/boards/arm/mimx8mp_evk/doc/index.rst deleted file mode 100644 index 9a9d0ff15992d1..00000000000000 --- a/boards/arm/mimx8mp_evk/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. _mimx8ml_evk: - -NXP MIMX8MP EVK -############### - -Overview -******** - -i.MX8M Plus EVK board is based on NXP i.MX8M Plus applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. -Zephyr OS is ported to run on the Cortex®-M7 core. - -- Board features: - - - RAM: 6GB LPDDR4 - - Storage: - - - SanDisk 32GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n/ac - - Bluetooth: v4.2 - - USB: - - - USB 3.0 Type C for Power - - USB 3.0 Type A - - USB 3.0 Type C - - 2x 10/100/1000 Ethernet (1x w/ TSN) - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG connector - - MicroUSB for UART debug, two COM ports for A53 and one for M7 - -.. image:: img/I.MX8MPLUS-PLUS-EVK-TOP.jpg - :align: center - :alt: MIMX8MP EVK - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mp_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mp_evk/mimx8mp_evk_defconfig`. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -MIMX8MP EVK board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART4 RXD | UART4_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART4 TXD | UART4_RXD | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M7 Core is configured to run at a 800 MHz clock speed. - -Serial Port -=========== - -The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs -to be started by the A53 core. The A53 core is responsible to load the M7 binary -application into the RAM, put the M7 in reset, set the M7 Program Counter and -Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M7 can use up to 3 different RAMs (currently, only two configurations are -supported: ITCM and DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done based on board name (mimx8mp_evk_itcm for ITCM and -mimx8mp_evk_ddr for DDR). - -Load and run Zephyr on M7 from A53 using u-boot by copying the compiled -``zephyr.bin`` to the first FAT partition of the SD card and plug the SD -card into the board. Power it up and stop the u-boot execution at prompt. - -Load the M7 binary onto the desired memory and start its execution using: - -ITCM -=== - -.. code-block:: console - - fatload mmc 0:1 0x48000000 zephyr.bin - cp.b 0x48000000 0x7e0000 20000 - bootaux 0x7e0000 - -DDR -=== - -.. code-block:: console - - fatload mmc 0:1 0x80000000 zephyr.bin - dcache flush - bootaux 0x80000000 - -Debugging -========= - -MIMX8MP EVK board can be debugged by connecting an external JLink -JTAG debugger to the J24 debug connector and to the PC. Then -the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mp_evk_itcm - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91 *** - Hello World! mimx8mp_evk - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK - -.. _i.MX 8M Plus Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi b/boards/arm/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi deleted file mode 100644 index a690f201ba1563..00000000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2022, NXP - * SPDX-License-Identifier: Apache-2.0 - * - * Note: File generated by gen_board_pinctrl.py - * from MIMX8MP-EVK-REV-A.mex - */ - -#include - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; - -}; diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts b/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts deleted file mode 100644 index 0179f811eb9242..00000000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8M Plus EVK board"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml b/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml deleted file mode 100644 index 7e4b407380bf8c..00000000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mp_evk_ddr -name: NXP i.MX8M Plus EVK (DDR) -type: mcu -arch: arm -ram: 2048 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - uart -vendor: nxp diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig b/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig deleted file mode 100644 index 4a77ad558c24d9..00000000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_ddr_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_EVK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_DDR=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts b/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts deleted file mode 100644 index 2d3f171339e0ca..00000000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.dts +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2021, Laird Connectivity - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8M Plus EVK board"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml b/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml deleted file mode 100644 index 66c3c9b553d05c..00000000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mp_evk_itcm -name: NXP i.MX8M Plus EVK (ITCM) -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - uart -vendor: nxp diff --git a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig b/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig deleted file mode 100644 index 8b2a3b770540c0..00000000000000 --- a/boards/arm/mimx8mp_evk/mimx8mp_evk_itcm_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_EVK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_ITCM=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.board b/boards/arm/mimx8mp_phyboard_pollux/Kconfig.board deleted file mode 100644 index af7975bc3c9411..00000000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MP PhyBOARD Pollux (i.MX8MP) - -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_PHYBOARD_POLLUX - bool "PhyBOARD Pollux (i.MX8MP)" - depends on SOC_SERIES_IMX8ML_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.defconfig b/boards/arm/mimx8mp_phyboard_pollux/Kconfig.defconfig deleted file mode 100644 index 889b2b24dfaf44..00000000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# PhyBOARD Pollux (i.MX8MP) defconfig - -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MP_PHYBOARD_POLLUX - -config BOARD - default "mimx8mp_phyboard_pollux" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MP_PHYBOARD_POLLUX diff --git a/boards/arm/mimx8mp_phyboard_pollux/doc/index.rst b/boards/arm/mimx8mp_phyboard_pollux/doc/index.rst deleted file mode 100644 index 04da62c18edfcd..00000000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/doc/index.rst +++ /dev/null @@ -1,272 +0,0 @@ -.. _mimx8mp_phyboard_pollux: - -PhyBOARD Pollux (NXP i.MX8M Plus) -################################# - -Overview -******** - -The PhyBOARD Pollux is based upon the PhyCore-i.MX8M Plus SOM which is based on -the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one -Coretex-M7 core for real time applications like Zephyr. The PhyBOARD Pollux -can be used for various applications like SmartHomes, Industry 4.0, IoT etc. -It features a lots of interfaces and computing capacity. It can be used as -a reference, to develop or in the final product too. - - -Board features: - -- Memory: - - - RAM: 256MB - 8GB LPDDR4 - - EEPROM: 4kB - 32kB - - eMMC: 4GB - 64GB (eMMC 5.1) - - SPI NOR Flash: 4MB - 256MB -- Interfaces: - - - Ethernet: 2x 10/100/1000BASE-T (1x TSN Support) - - USB: 2x 3.0 Host - - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex - - CAN: 2x CAN FD - - Digital I/O: via Expansion Connector - - PCIe: 1x miniPCIe - - MMX/SD/SDIO: microSD slot - - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI - - Audio: SAI - - Camera: 2x MIPI CSI-2 (PhyCAM-M) - - Expansion Bus: I2C, SPI, SDIO, UART, USB - - JTAG: via PEB-EVAL-01 -- LEDs: - - - 1x Multicolor Status LED via I2C - - -.. image:: img/Phyboard_Pollux.jpg - :width: 720px - :align: center - :height: 405px - :alt: PhyBOARD Pollux - -More information about the board can be found at the -`PHYTEC website`_. - -Supported Features -================== - -The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig`. - -It's recommended to disable peripherals used by the M7-Core on the host running -on the Linux host. - -Other hardware features are not currently supported with Zephyr on the -M7-Core. - -Connections and IOs -=================== - -The following Compontens are tested and working correctly. - -UART ----- - -+---------------+-----------------+-----------------------------------+ -| Board Name | SoM Name | Usage | -+===============+=================+===================================+ -| Debug USB(A53)| UART1 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ -| Wo WiFi Module| UART3 | UART to WiFi/BLE Module | -+---------------+-----------------+-----------------------------------+ -| Debug USB(M4) | UART4 | UART Debug Console via USB | -+---------------+-----------------+-----------------------------------+ - -.. note:: - Please note, that the, to UART3 connected, Wifi/BLE Module isn't working with - Zephyr yet. UART3 can also be used through pin 31(RX) and 33(TX) of the - X6 Connector. - -GPIO ----- - -The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree -created by NXP. You can find it here: - -:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. - -The Pinout of the PhyBOARD Polis can be found here: - -`PHYTEC website`_ - -Programming and Debugging -************************* - -The i.MX8MP does not have a separate flash for the M7-Core. Because of this -the A53-Core has to load the program for the M7-Core to the right memory -address, set the PC and start the processor. -This can only by done with u-boot at the moment. We are working on our BSP to -enable remoteproc support. - -The M7 can use up to 3 different RAMs (currently, only two configurations are -supported: ITCM and DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which memory region will be used. This -configuration is done in the devicetree and the defconfig / the config of your -program. - -**By default Zephyr will use the TCM memory region.** You can configure it like -this for the DDR region: - -In the devicetree overwrite the following nodes like this: - -.. code-block:: DTS - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - }; - -change it to - -.. code-block:: DTS - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - }; - - -In your prj.conf overwrite the configuration like this for the **DDR** memory -region: - -.. code-block:: console - - CONFIG_CODE_DDR=y - CONFIG_CODE_ITCM=n - - -Starting the M7-Core via U-Boot -=============================== - -Load the compiled zephyr.bin to memory address 0x4800000. -This should output something like this: - -.. code-block:: console - - u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin - Using ethernet@30be0000 device - TFTP from server 192.168.3.10; our IP address is 192.168.3.11 - Filename 'zepyhr.bin'. - Load address: 0x48000000 - Loading: ## - 2 KiB/s - done - Bytes transferred = 27240 (6a68 hex) - -Because it's not possible to load directly to the TCM memory area you have to -copy the binaries. The last argument given is the size of the file in bytes, -you can copy it from the output of the last command. - -.. code-block:: console - - u-boot=> cp.b 0x48000000 0x7e0000 27240 - -And finaly starting the M7-Core at the right memory address: - -.. code-block:: console - - u-boot=> bootaux 0x7e0000 - ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... - -Debugging -========= - -The PhyBOARD Polis can be debugged using a JTAG Debugger. -The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's -``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. -You can find the JLink Software package here: `JLink Software`_ - -.. figure:: img/PEB-EVAL-01.jpg - :alt: PEB-EVAL-01 - :width: 350 - - PEB-EVAL-01 - -To debug efficiently you have to use multiple terminals: - -After connecting everything and building with west use this command while in -the directory of the program you build earlier to start a debug server: - -.. code-block:: console - - host$ west debugserver - -West automatically connects via the JLink to the Target and keeps open a -debug server. - -Use another terminal, start gdb, connect to target and load Zephyr on the -target: - -.. code-block:: console - - host$ gdb-multiarch build/zephyr/zephyr.elf -tui - (gdb) targ rem :2331 - Remote debugging using :2331 - 0x1ffe0008 in _vector_table () - (gdb) mon halt - (gdb) mon reset - (gdb) c - Continuing. - -The program can be debugged using standard gdb techniques. - -References -========== - -.. _PHYTEC website: - https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/ - -.. _i.MX 8M Plus Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM - -.. _JLink Software: - https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.yaml b/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.yaml deleted file mode 100644 index c696532393d478..00000000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mp_phyboard_pollux -name: PhyBOARD Pollux (i.MX8MP) -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - uart - - gpio -vendor: nxp diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig b/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig deleted file mode 100644 index 9c2fae84c13c30..00000000000000 --- a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2022 PHYTEC Messtechnik GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_MIMX8MP_PHYBOARD_POLLUX=y -CONFIG_CORTEX_M_SYSTICK=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y - -# y for TCM memory space -CONFIG_CODE_ITCM=y - -# y for DDR memory space -CONFIG_CODE_DDR=n - -CONFIG_PINCTRL=y diff --git a/boards/arm/mimx8mq_evk/Kconfig.board b/boards/arm/mimx8mq_evk/Kconfig.board deleted file mode 100644 index 7f0533f7053998..00000000000000 --- a/boards/arm/mimx8mq_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# MIMX8MQ EVK board - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MQ_EVK_CM4 - bool "NXP i.MX8MQ EVK" - depends on SOC_SERIES_IMX8MQ_M4 - select SOC_PART_NUMBER_MIMX8MQ6DVAJZ diff --git a/boards/arm/mimx8mq_evk/Kconfig.defconfig b/boards/arm/mimx8mq_evk/Kconfig.defconfig deleted file mode 100644 index fa66b520e6e85b..00000000000000 --- a/boards/arm/mimx8mq_evk/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# MIMX8MQ EVK board defconfig - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MQ_EVK_CM4 - -config BOARD - default "mimx8mq_evk_cm4" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_MIMX8MQ_EVK_CM4 diff --git a/boards/arm/mimx8mq_evk/doc/index.rst b/boards/arm/mimx8mq_evk/doc/index.rst deleted file mode 100644 index 486bf298fec5d9..00000000000000 --- a/boards/arm/mimx8mq_evk/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _mimx8mq_evk: - -NXP MIMX8MQ EVK -############### - -Overview -******** - -i.MX8MQ EVK board is based on NXP i.MX8MQ applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-M4 core. - -- Board features: - - - RAM: 3GB LPDDR4 - - Storage: - - - 16GB eMMC5.0 - - 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11 a/b/g/n/ac - - Bluetooth: v4.1 - - USB: - - - OTG - 1x type C - - HOST - 1x type A - - Ethernet - - PCI-E M.2 - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 10-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -.. image:: img/mimx8mq_evk.jpg - :align: center - :alt: MIMX8MQ EVK - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mq_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -:zephyr_file:`boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig`. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -MIMX8MQ EVK board was tested with the following pinmux controller -configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART2 RXD | UART2_TXD | UART Console | -+---------------+-----------------+---------------------------+ -| UART2 TXD | UART2_RXD | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 266 MHz clock speed. - -Serial Port -=========== - -The i.MX8MQ SoC has four UARTs. UART_2 is configured for the console and -the remaining are not used/tested. - -Programming and Debugging -************************* - -The MIMX8MQ EVK board doesn't have QSPI flash for the M4 and it needs -to be started by the A53 core. The A53 core is responsible to load the M4 binary -application into the RAM, put the M4 in reset, set the M4 Program Counter and -Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at -bootloader level or after the Linux system has booted. - -The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the -`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts`` -with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. -The available configurations are: - -.. code-block:: none - - "zephyr,flash" - - &tcml_code - - &ocram_code - - &ocram_s_code - - "zephyr,sram" - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - -Load and run Zephyr on M4 from A53 using u-boot. - -.. tabs:: - - .. group-tab:: From an SD card - Copy the compiled ``zephyr.bin`` to the first FAT partition of the - SD card and plug the SD card into the board. Power it up and stop the u-boot - execution at prompt. - - Load the M4 binary onto the desired memory and start its execution using: - - .. code-block:: console - - fatload mmc 0:1 0x40480000 zephyr.bin - cp.b 0x40480000 0x7e0000 0x8000 - bootaux 0x7e0000 - - .. group-tab:: From serial - This procedure requires ``screen`` and ``lrzsz`` to be installed. - - Start ``screen``, power up the board, and stop the u-boot execution at prompt: - - .. code-block:: console - - screen 115200 - - Start ``loadx`` with offset ``7e0000``: - - .. code-block:: console - - loadx 7e0000 115200 - - Send the compiled ``zephyr.bin`` with ``sx`` by pressing :kbd:`Ctrl-a` followed by :kbd:`:` - and write: - - .. code-block:: console - - exec !! sx - - Start execution: - - .. code-block:: console - - bootaux 0x7e0000 - -Debugging -========= - -MIMX8MQ EVK board can be debugged by connecting an external JLink -JTAG debugger to the J401 debug connector and to the PC. Then -the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimx8mq_evk_cm4 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS build zephyr-v2.6.99-30942-g6ee70bd22058 ***** - Hello World! mimx8mq_evk_cm4 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-applications-processor:MCIMX8M-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts b/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts deleted file mode 100644 index 9197477e8ead7c..00000000000000 --- a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2021, Kwon Tae-young - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mq_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MQ EVK board"; - compatible = "nxp,mimx8mq_evk"; - - aliases { - uart-2 = &uart2; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - }; -}; - -&uart2 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml b/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml deleted file mode 100644 index f5fee9cea2fc9d..00000000000000 --- a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2021, Kwon Tae-young -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimx8mq_evk_cm4 -name: NXP i.MX8MQ EVK CM4 -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig b/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig deleted file mode 100644 index d1b9de332f6b48..00000000000000 --- a/boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2021, Kwon Tae-young -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8MQ_M4=y -CONFIG_SOC_MIMX8MQ6=y -CONFIG_BOARD_MIMX8MQ_EVK_CM4=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1010_evk/CMakeLists.txt b/boards/arm/mimxrt1010_evk/CMakeLists.txt deleted file mode 100644 index 53422e1b03058a..00000000000000 --- a/boards/arm/mimxrt1010_evk/CMakeLists.txt +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(init.c) - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT1010_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1010-EVK, but targeting a custom board. You may need to " - "update your flash configuration data blocks") - endif() - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1010 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT1010_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1010") - zephyr_library_sources(${RT1010_BOARD_DIR}/xip/evkmimxrt1010_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1010_BOARD_DIR}/xip) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1010_evk/Kconfig.board b/boards/arm/mimxrt1010_evk/Kconfig.board deleted file mode 100644 index 7ccc20510739de..00000000000000 --- a/boards/arm/mimxrt1010_evk/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_MIMXRT1010_EVK - bool "NXP MIMXRT1010-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1011DAE5A diff --git a/boards/arm/mimxrt1010_evk/Kconfig.defconfig b/boards/arm/mimxrt1010_evk/Kconfig.defconfig deleted file mode 100644 index da98cdf9ffaec1..00000000000000 --- a/boards/arm/mimxrt1010_evk/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MIMXRT1010-EVK board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1010_EVK - -config BOARD - default "mimxrt1010_evk" if BOARD_MIMXRT1010_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -endif # BOARD_MIMXRT1010_EVK diff --git a/boards/arm/mimxrt1015_evk/CMakeLists.txt b/boards/arm/mimxrt1015_evk/CMakeLists.txt deleted file mode 100644 index 005b4f2398d46c..00000000000000 --- a/boards/arm/mimxrt1015_evk/CMakeLists.txt +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1015_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1015-EVK, but targeting a custom board. You may need to " - "update your flash configuration data blocks") - endif() - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1015 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT1015_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1015") - zephyr_library_sources(${RT1015_BOARD_DIR}/xip/evkmimxrt1015_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1015_BOARD_DIR}/xip) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1015_evk/Kconfig.board b/boards/arm/mimxrt1015_evk/Kconfig.board deleted file mode 100644 index a5dee5762f866b..00000000000000 --- a/boards/arm/mimxrt1015_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1015_EVK - bool "NXP MIMXRT1015-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1015DAF5A diff --git a/boards/arm/mimxrt1015_evk/Kconfig.defconfig b/boards/arm/mimxrt1015_evk/Kconfig.defconfig deleted file mode 100644 index 215f75a827ee6a..00000000000000 --- a/boards/arm/mimxrt1015_evk/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# MIMXRT1015-EVK board - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1015_EVK - -config BOARD - default "mimxrt1015_evk" if BOARD_MIMXRT1015_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -endif # BOARD_MIMXRT1015_EVK diff --git a/boards/arm/mimxrt1020_evk/CMakeLists.txt b/boards/arm/mimxrt1020_evk/CMakeLists.txt deleted file mode 100644 index 09e7641d928d9d..00000000000000 --- a/boards/arm/mimxrt1020_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1020_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1020-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1020_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1020") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1020 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1020_BOARD_DIR}/xip/evkmimxrt1020_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1020_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1020 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1020_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1020_evk/Kconfig.board b/boards/arm/mimxrt1020_evk/Kconfig.board deleted file mode 100644 index e8ac44ef192697..00000000000000 --- a/boards/arm/mimxrt1020_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1020_EVK - bool "NXP MIMXRT1020-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1021DAG5A diff --git a/boards/arm/mimxrt1020_evk/Kconfig.defconfig b/boards/arm/mimxrt1020_evk/Kconfig.defconfig deleted file mode 100644 index 4ecf9c39c1d8c4..00000000000000 --- a/boards/arm/mimxrt1020_evk/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# MIMXRT1020-EVK board - -# Copyright 2018,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1020_EVK - -config BOARD - default "mimxrt1020_evk" if BOARD_MIMXRT1020_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -config ETH_MCUX_PHY_RESET - default y - -endif # NETWORKING - -endif # BOARD_MIMXRT1020_EVK diff --git a/boards/arm/mimxrt1024_evk/CMakeLists.txt b/boards/arm/mimxrt1024_evk/CMakeLists.txt deleted file mode 100644 index b7e94224cc7532..00000000000000 --- a/boards/arm/mimxrt1024_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1024_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1024-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1024_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1024") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1024 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1024_BOARD_DIR}/xip/evkmimxrt1024_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1024_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1024 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1024_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1024_evk/Kconfig.board b/boards/arm/mimxrt1024_evk/Kconfig.board deleted file mode 100644 index e3468871e2a1e5..00000000000000 --- a/boards/arm/mimxrt1024_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1024_EVK - bool "NXP MIMXRT1024-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1024DAG5A diff --git a/boards/arm/mimxrt1024_evk/Kconfig.defconfig b/boards/arm/mimxrt1024_evk/Kconfig.defconfig deleted file mode 100644 index db0a2eb1fedc90..00000000000000 --- a/boards/arm/mimxrt1024_evk/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# MIMXRT1024-EVK board - -# Copyright 2020,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1024_EVK - -config BOARD - default "mimxrt1024_evk" if BOARD_MIMXRT1024_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config I2C_MCUX_LPI2C_BUS_RECOVERY - default y - depends on I2C_MCUX_LPI2C && PINCTRL - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -endif # BOARD_MIMXRT1024_EVK diff --git a/boards/arm/mimxrt1040_evk/CMakeLists.txt b/boards/arm/mimxrt1040_evk/CMakeLists.txt deleted file mode 100644 index 98ff54d4bc2312..00000000000000 --- a/boards/arm/mimxrt1040_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1040_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1040-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1040_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1040") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1040 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1040_BOARD_DIR}/xip/evkmimxrt1040_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1040_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1040 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1040_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1040_evk/Kconfig.board b/boards/arm/mimxrt1040_evk/Kconfig.board deleted file mode 100644 index d8374b6bfadb07..00000000000000 --- a/boards/arm/mimxrt1040_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1040_EVK - bool "NXP MIMXRT1040-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1042XJM5B diff --git a/boards/arm/mimxrt1040_evk/Kconfig.defconfig b/boards/arm/mimxrt1040_evk/Kconfig.defconfig deleted file mode 100644 index 683da9279ed691..00000000000000 --- a/boards/arm/mimxrt1040_evk/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1040_EVK - -config BOARD - default "mimxrt1040_evk" if BOARD_MIMXRT1040_EVK - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -endif # BOARD_MIMXRT1040_EVK diff --git a/boards/arm/mimxrt1040_evk/doc/index.rst b/boards/arm/mimxrt1040_evk/doc/index.rst deleted file mode 100644 index 651a0aebff9a35..00000000000000 --- a/boards/arm/mimxrt1040_evk/doc/index.rst +++ /dev/null @@ -1,372 +0,0 @@ -.. _mimxrt1040_evk: - -NXP MIMXRT1040-EVK -################## - -Overview -******** - -i.MX RT1040 crossover MCUs add additional flexibility with new packages and an -extended temperature range up to 125° C. The i.MX RT1040 MCU has a compact -9x9 mm package, as well as the 11x11 mm package that supports implementing a -2-layer PCB design. The i.MX RT1040 MCUs run on the Arm® Cortex®-M7 core at -600 MHz. - -.. image:: mimxrt1040_evk.jpg - :align: center - :alt: MIMXRT1040-EVK - -Hardware -******** - -- MIMXRT1042XJM5B MCU (600 MHz, 512 KB TCM) - -- Memory - - - 256 MBit SDRAM (Winbond W9825G6KH) - - 64 Mbit QSPI Flash (Winbond W25Q64JVSSIQ) - -- Display - - - LCD connector - - Touch connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1040 SoC and MIMXRT1040-EVK board, see -these references: - -- `i.MX RT1040 Website`_ -- `i.MX RT1040 Datasheet`_ -- `i.MX RT1040 Reference Manual`_ -- `MIMXRT1040-EVK Website`_ -- `MIMXRT1040-EVK User Guide`_ -- `MIMXRT1040-EVK Design Files`_ - -External Memory -=============== - -This platform has the following external memories: - -+----------------+------------+-------------------------------------+ -| Device | Controller | Status | -+================+============+=====================================+ -| W9825G6KH | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+----------------+------------+-------------------------------------+ -| W25Q64JVSSIQ | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. Supported for XIP only. | -+----------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1040_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1064_evk board may have additional features -already supported, which can also be re-used on this mimxrt1040_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT1040 SoC has five pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_08 | GPIO | User LD1 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | FLEXPWM1 PWM3A | PWM Output | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_14 | ADC0 IN3 | ADC0 Input | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_15 | ADC0 IN4 | ADC0 Input | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | LPSPI1_SDO | SPI Output | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | LPSPI1_SDI | SPI Input | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_00 | LPI2C1_SCL | I2C Clock | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_01 | LPI2C1_SDA | I2C Data | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R350, R346, - and R360 must be populated with zero ohm resistors. - -System Clock -============ - -The MIMXRT1040 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1040 SoC has eight UARTs. ``LPUART1`` is configured for the console, -and the remaining UARTs are not used. - - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) ----------------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Check that jumpers J9 and J10 are **on** to ensure SWD signals are connected to -the OpenSDA microcontroller. Then, follow the instructions in `NXP AN13206`_ to -program a JLink based firmware to the LPC4322 based debugger on this board. - -Once the JLink based firmware is present on this board, the SOC will no longer -be powered via the USB connection to J1. Move J40 to short pins 3 and 4 in -order to use J48 for USB power, and connect another USB cable to power the SoC. -LED D16 should illuminate to indicate the board is powered, and it should now be -possible to program the SoC. - -Option 2: :ref:`jlink-external-debug-probe` -------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -The board can be programmed using the :ref:`jlink-external-debug-probe`, -provided the onboard debug circuit's SWD signals are isolated from the MCU. -To do so, ensure that jumpers J9 and J10 are **off** (they are on by default -when the board ships from the factory). The external probe's 20 pin connector -can then be connected to J2 to program the SOC. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J11 and J13 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J1. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1040_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** - Hello World! mimxrt1040_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1040_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** - Hello World! mimxrt1040_evk - -Troubleshooting -=============== - -USER_LED D8 ------------ -The MIMXRT1040-EVK board ships with the wireless module in the M.2 connector, -and with jumper J80 shorted. This causes a conflict with the USER_LED D8, -and the LED will not turn off. Samples and applications using USER_LED D8, -like blinky, require removal of J80 jumper. - -Boot Header ------------ - -If the debug probe fails to connect with the following error, it's possible -that the boot header in QSPI is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the QSPI with the following -steps: - -#. Set the SW4 DIP switches to OFF-OFF-OFF-ON to boot into the ROM bootloader. - -#. Reset by pressing SW1 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW4 DIP switches to OFF-OFF-ON-OFF to boot from QSPI. - -#. Reset by pressing SW1 - - -WiFi Module ------------ - -If the debugger fails to connect with the following error, it's possible -the M.2 WiFi module is interfering with the debug signals - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -To resolve this, you may remove the M.2 WiFi module from the board when -flashing or debugging it, or remove jumper J80. - - -.. _MIMXRT1040-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1040-evaluation-kit:MIMXRT1040-EVK - -.. _MIMXRT1040-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVKUM - -.. _MIMXRT1040-EVK Design Files: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVK-DESIGNFILES - -.. _i.MX RT1040 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1040-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1040 - -.. _i.MX RT1040 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1040CEC.pdf - -.. _i.MX RT1040 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1040RM - -.. _NXP AN13206: - https://www.nxp.com/docs/en/application-note/AN13206.pdf diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig b/boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig deleted file mode 100644 index 94b11471e04a38..00000000000000 --- a/boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1042=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1040_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1050_evk/CMakeLists.txt b/boards/arm/mimxrt1050_evk/CMakeLists.txt deleted file mode 100644 index 9a136bb8d8242d..00000000000000 --- a/boards/arm/mimxrt1050_evk/CMakeLists.txt +++ /dev/null @@ -1,55 +0,0 @@ -# -# Copyright 2017-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if (CONFIG_DISPLAY) -message(WARNING " -CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board -") -endif() - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(CONFIG_BOARD_MIMXRT1050_EVK) - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - elseif(CONFIG_BOARD_MIMXRT1050_EVK_QSPI) - set(FLASH_CONF evkbimxrt1050_flexspi_nor_qspi_config.c) - else() - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1050-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - # Default EVK configuration uses hyperflash, so use that file - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - endif() - set(RT1050_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkbimxrt1050") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1050_BOARD_DIR}/xip/${FLASH_CONF}) - zephyr_library_include_directories(${RT1050_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1050_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1050_evk/Kconfig.board b/boards/arm/mimxrt1050_evk/Kconfig.board deleted file mode 100644 index 9627ee203198b7..00000000000000 --- a/boards/arm/mimxrt1050_evk/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1050_EVK - bool "NXP MIMXRT1050-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1052DVL6A - -config BOARD_MIMXRT1050_EVK_QSPI - bool "NXP MIMXRT1050-EVK-QSPI" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1052DVL6A diff --git a/boards/arm/mimxrt1050_evk/Kconfig.defconfig b/boards/arm/mimxrt1050_evk/Kconfig.defconfig deleted file mode 100644 index 79660c08e781c9..00000000000000 --- a/boards/arm/mimxrt1050_evk/Kconfig.defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# MIMXRT1050-EVK board - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1050_EVK || BOARD_MIMXRT1050_EVK_QSPI - -config BOARD - default "mimxrt1050_evk" if BOARD_MIMXRT1050_EVK - default "mimxrt1050_evk_qspi" if BOARD_MIMXRT1050_EVK_QSPI - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if FLASH - -config FLASH_MCUX_FLEXSPI_HYPERFLASH - default y if BOARD_MIMXRT1050_EVK - default n if BOARD_MIMXRT1050_EVK_QSPI - -config FLASH_MCUX_FLEXSPI_NOR - default y if BOARD_MIMXRT1050_EVK_QSPI - default n if BOARD_MIMXRT1050_EVK - -endif #FLASH - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -if LVGL - -config LV_Z_VDB_SIZE - default 16 - -config LV_DPI_DEF - default 128 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - -endif # BOARD_MIMXRT1050_EVK || BOARD_MIMXRT1050_EVK_QSPI diff --git a/boards/arm/mimxrt1050_evk/board.cmake b/boards/arm/mimxrt1050_evk/board.cmake deleted file mode 100644 index 265ce1cd5f8d5f..00000000000000 --- a/boards/arm/mimxrt1050_evk/board.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -board_runner_args(jlink "--device=MCIMXRT1052") - -if(${CONFIG_BOARD_MIMXRT1050_EVK_QSPI}) - board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") - board_runner_args(pyocd "--target=mimxrt1050_quadspi") -else() - board_runner_args(pyocd "--target=mimxrt1050_hyperflash") - board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") - include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/mimxrt1050_evk/doc/index.rst b/boards/arm/mimxrt1050_evk/doc/index.rst deleted file mode 100644 index de225ae56f330c..00000000000000 --- a/boards/arm/mimxrt1050_evk/doc/index.rst +++ /dev/null @@ -1,499 +0,0 @@ -.. _mimxrt1050_evk: - -NXP MIMXRT1050-EVK -################## - -Overview -******** - -The i.MX RT1050 is a new processor family featuring NXP's advanced -implementation of the ARM Cortex-M7 Core. It provides high CPU performance and -real-time response. - -The i.MX RT1050 provides various memory interfaces, including SDRAM, Raw NAND -FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a wide range of other -interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, -and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich -audio and video features, including LCD display, basic 2D graphics, camera -interface, SPDIF, and I2S audio interface. - -The following document refers to the discontinued MIMXRT1050-EVK board. For the -MIMXRT1050-EVKB board, refer to `Board Revisions`_ section. - -.. image:: mimxrt1050_evk.jpg - :align: center - :alt: MIMXRT1050-EVK - -Hardware -******** - -- MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM) - -- Memory - - - 256 KB SDRAM - - 64 Mbit QSPI Flash - - 512 Mbit Hyper Flash - -- Display - - - LCD connector - - Touch connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - CMOS camera sensor interface - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see -these references: - -- `i.MX RT1050 Website`_ -- `i.MX RT1050 Datasheet`_ -- `i.MX RT1050 Reference Manual`_ -- `MIMXRT1050-EVK Website`_ -- `MIMXRT1050-EVK User Guide`_ -- `MIMXRT1050-EVK Schematics`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| IS42S16160J | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ -| S26KS512SDPBHI020 | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1050_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1064_evk board may have additional features -already supported, which can also be re-used on this mimxrt1050_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| ENET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_05 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_11 | GPIO | Touch Interrupt | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_11 | ADC | ADC1 channel 0 | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_B0_00 | LCD_CLK | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_01 | LCD_ENABLE | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_02 | LCD_HSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_03 | LCD_VSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_04 | LCD_DATA00 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_05 | LCD_DATA01 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_06 | LCD_DATA02 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_07 | LCD_DATA03 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_08 | LCD_DATA04 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_09 | LCD_DATA05 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_10 | LCD_DATA06 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_11 | LCD_DATA07 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_12 | LCD_DATA08 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_13 | LCD_DATA09 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_14 | LCD_DATA10 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_15 | LCD_DATA11 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_00 | LCD_DATA12 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_01 | LCD_DATA13 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_02 | LCD_DATA14 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_03 | LCD_DATA15 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_06 | ENET_RX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_09 | ENET_TX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_10 | ENET_REF_CLK | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_11 | ENET_RX_ER | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_12 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_14 | USDHC1_VSELECT | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_40 | ENET_MDC | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_41 | ENET_MDIO | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | ENET_RST | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | ENET_INT | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R278, - R279, R280, and R281 must be populated with zero ohm resistors - -System Clock -============ - -The MIMXRT1050 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1050 SoC has eight UARTs. ``LPUART1`` is configured for the console, -``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the -remaining are not used. - -USB -=== - -The RT1050 SoC has two USB OTG (USBOTG) controllers that supports both -device and host functions through its micro USB connectors. -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -Using LinkServer ----------------- - -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the default CMSIS-DAP firmware included in -the on-board debugger. - -Linkserver is the default runner. You may also se the ``-r linkserver`` option -with West to use the LinkServer runner. - -.. code-block:: console - - west flash - west debug - -JLink (on-board): :ref:`opensda-jlink-onboard-debug-probe` ----------------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware`_. Check that jumpers -J32 and J33 are **on** (they are on by default when boards ship from the -factory) to ensure SWD signals are connected to the OpenSDA microcontroller. - -Follow the instructions in `Enable QSPI flash support in SEGGER JLink`_ -in order to support your EVK if you have modified it to boot from QSPI NOR -flash as specified by NXP AN12108. - -External JLink :ref:`jlink-external-debug-probe` ------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Attach a J-Link 20-pin connector to J21. Check that jumpers J32 and J33 are -**off** (they are on by default when boards ship from the factory) to ensure -SWD signals are disconnected from the OpenSDA microcontroller. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J30 and J31 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J28. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1050_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1050_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1050_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1050_evk - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the boot header in HyperFlash is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the HyperFlash with the following -steps: - -#. Set the SW7 DIP switches to ON-ON-ON-OFF to prevent booting from HyperFlash. - -#. Reset by pressing SW4 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW7 DIP switches to OFF-ON-ON-OFF to boot from HyperFlash. - -#. Reset by pressing SW4 - -Board Revisions -*************** - -The original MIMXRT1050-EVK (rev A0) board was updated with a newer -MIMXRT1050-EVKB (rev A1) board, with these major hardware differences: - -- SoC changed from MIMXRT1052DVL6\ **A** to MIMXRT1052DVL6\ **B** -- Hardware bug fixes for: power, interfaces, and memory -- Arduino headers included - -For more details, please see the following `NXP i.MXRT1050 A0 to A1 Migration Guide`_. - -Current Zephyr build supports the new MIMXRT1050-EVKB - -.. _MIMXRT1050-EVK Website: - https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK - -.. _MIMXRT1050-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=IMXRT1050EVKBHUG - -.. _MIMXRT1050-EVK Schematics: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1050-EVK-DESIGNFILES - -.. _i.MX RT1050 Website: - https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1050 - -.. _i.MX RT1050 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf - -.. _i.MX RT1050 Reference Manual: - https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf - -.. _OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware: - https://www.segger.com/downloads/jlink/OpenSDA_MIMXRT1050-EVK-Hyperflash - -.. _NXP i.MXRT1050 A0 to A1 Migration Guide: - https://www.nxp.com/docs/en/nxp/application-notes/AN12146.pdf - -.. _Enable QSPI flash support in SEGGER JLink: - https://wiki.segger.com/i.MXRT1050#QSPI_flash - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig deleted file mode 100644 index 0c3fd3485d8bec..00000000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1052=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1050_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts deleted file mode 100644 index 27542b88bfd0d8..00000000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.dts +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1050_evk.dts" - -/delete-node/ &s26ks512s0; - -/ { - chosen { - zephyr,flash-controller = &is25wp064; - zephyr,flash = &is25wp064; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - rx-clock-source = <1>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - is25wp064: is25wp064@0 { - compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@311000 { - label = "image-1"; - reg = <0x00311000 DT_SIZE_M(3)>; - }; - storage_partition: partition@611000 { - label = "storage"; - reg = <0x00611000 DT_SIZE_K(1980)>; - }; - }; - }; -}; diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.yaml b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.yaml deleted file mode 100644 index baadda8c061b92..00000000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi.yaml +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1050_evk_qspi -name: NXP MIMXRT1050-EVK-QSPI -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32768 -flash: 8192 -supported: - - arduino_gpio - - arduino_serial - - counter - - display - - dma - - gpio - - i2c - - netif:eth - - sdhc - - spi - - usb_device - - watchdog - - adc -vendor: nxp diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig b/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig deleted file mode 100644 index 5ad5307db8caab..00000000000000 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk_qspi_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1052=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1050_EVK_QSPI=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1060_evk/CMakeLists.txt b/boards/arm/mimxrt1060_evk/CMakeLists.txt deleted file mode 100644 index 84e3812e9a0f9e..00000000000000 --- a/boards/arm/mimxrt1060_evk/CMakeLists.txt +++ /dev/null @@ -1,64 +0,0 @@ -# -# Copyright 2018-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if (CONFIG_DISPLAY) -message(WARNING " -CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board -") -endif() - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(CONFIG_BOARD_MIMXRT1060_EVK) - set(FLASH_CONF evkmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkmimxrt1060) - elseif(CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH) - # No flash configuration block exists for the RT1060 with HyperFlash in - # the SDK, but we can reuse the block for the RT1050 as both boards use - # the same HyperFlash chip - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - set(BOARD_NAME evkbimxrt1050) - elseif(CONFIG_BOARD_MIMXRT1060_EVKB) - set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkbmimxrt1060) - else() - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1060-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - # Default EVK configuration uses qspi, so use that file - set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) - set(BOARD_NAME evkbmimxrt1060) - endif() - set(RT1060_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1060 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1060_BOARD_DIR}/xip/${FLASH_CONF}) - zephyr_library_include_directories(${RT1060_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1060 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1060_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1060_evk/Kconfig.board b/boards/arm/mimxrt1060_evk/Kconfig.board deleted file mode 100644 index d075c432477e7f..00000000000000 --- a/boards/arm/mimxrt1060_evk/Kconfig.board +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1060_EVK - bool "NXP MIMXRT1060-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A - -config BOARD_MIMXRT1060_EVK_HYPERFLASH - bool "NXP MIMXRT1060-EVK-HYPERFLASH" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A - -config BOARD_MIMXRT1060_EVKB - bool "NXP MIMXRT1060-EVKB" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mimxrt1060_evk/Kconfig.defconfig b/boards/arm/mimxrt1060_evk/Kconfig.defconfig deleted file mode 100644 index b3b325805fa6ea..00000000000000 --- a/boards/arm/mimxrt1060_evk/Kconfig.defconfig +++ /dev/null @@ -1,96 +0,0 @@ -# MIMXRT1060-EVK board - -# Copyright 2018,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVK_HYPERFLASH || BOARD_MIMXRT1060_EVKB - -config BOARD - default "mimxrt1060_evk" if BOARD_MIMXRT1060_EVK - default "mimxrt1060_evk_hyperflash" if BOARD_MIMXRT1060_EVK_HYPERFLASH - default "mimxrt1060_evkb" if BOARD_MIMXRT1060_EVKB - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if FLASH - -config FLASH_MCUX_FLEXSPI_NOR - default y if BOARD_MIMXRT1060_EVK - default y if BOARD_MIMXRT1060_EVKB - default n if BOARD_MIMXRT1060_EVK_HYPERFLASH - -config FLASH_MCUX_FLEXSPI_HYPERFLASH - default y if BOARD_MIMXRT1060_EVK_HYPERFLASH - default n if BOARD_MIMXRT1060_EVK - default n if BOARD_MIMXRT1060_EVKB - -endif #FLASH - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -if LVGL - -# LVGL should allocate buffers equal to size of display -config LV_Z_VDB_SIZE - default 100 - -# Enable double buffering -config LV_Z_DOUBLE_VDB - default y - -# Force full refresh. This prevents memory copy associated with partial -# display refreshes, which is not necessary for the eLCDIF driver -config LV_Z_FULL_REFRESH - default y - -config LV_DPI_DEF - default 128 - -config LV_Z_BITS_PER_PIXEL - default 16 - -# Force display buffers to be aligned to cache line size (32 bytes) -config LV_Z_VDB_ALIGN - default 32 - -# Use offloaded render thread -config LV_Z_FLUSH_THREAD - default y - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - -endif # BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVK_HYPERFLASH || BOARD_MIMXRT1060_EVKB diff --git a/boards/arm/mimxrt1060_evk/board.cmake b/boards/arm/mimxrt1060_evk/board.cmake deleted file mode 100644 index d3031f1542e3a7..00000000000000 --- a/boards/arm/mimxrt1060_evk/board.cmake +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2018, 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_runner_args(pyocd "--target=mimxrt1060") -board_runner_args(jlink "--device=MIMXRT1062xxx6A") -board_runner_args(linkserver "--device=MIMXRT1062xxxxA:EVK-MIMXRT1060") - -if ((${CONFIG_BOARD_MIMXRT1060_EVK}) OR (${CONFIG_BOARD_MIMXRT1060_EVKB})) - board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") -elseif (${CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH}) - board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash") -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/arm/mimxrt1060_evk/doc/index.rst b/boards/arm/mimxrt1060_evk/doc/index.rst deleted file mode 100644 index cfd546e5b37c69..00000000000000 --- a/boards/arm/mimxrt1060_evk/doc/index.rst +++ /dev/null @@ -1,484 +0,0 @@ -.. _mimxrt1060_evk: - -NXP MIMXRT1060-EVK -################## - -Overview -******** - -The i.MX RT1060 adds to the industry's first crossover -processor series and expands the i.MX RT series to three scalable families. - -The i.MX RT1060 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin -compatibility with i.MX RT1050. This series introduces additional features -ideal for real-time applications such as High-Speed GPIO, CAN FD, and -synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1060 runs on the -Arm® Cortex-M7® core up to 600 MHz. - -.. image:: mimxrt1060_evk.jpg - :align: center - :alt: MIMXRT1060-EVK - -Hardware -******** - -- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory) - -- Memory - - - 256 Mbit SDRAM - - 64 Mbit QSPI Flash - - 512 Mbit Hyper Flash - - TF socket for SD card - -- Display - - - LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - CMOS camera sensor interface - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1060 SoC and MIMXRT1060-EVK board, see -these references: - -- `i.MX RT1060 Website`_ -- `i.MX RT1060 Datasheet`_ -- `i.MX RT1060 Reference Manual`_ -- `MIMXRT1060-EVK Website`_ -- `MIMXRT1060-EVK User Guide`_ -- `MIMXRT1060-EVK Schematics`_ -- `MIMXRT1060-EVK Debug Firmware`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| IS25WP064AJBLE | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ -| IS42S16160J | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1060_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1064_evk board may have additional features -already supported, which can also be re-used on this mimxrt1060_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| ENET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| SAI | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and I/Os -==================== - -The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_05 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_11 | GPIO | Touch Interrupt | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_B0_00 | LCD_CLK | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_01 | LCD_ENABLE | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_02 | LCD_HSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_03 | LCD_VSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_04 | LCD_DATA00 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_05 | LCD_DATA01 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_06 | LCD_DATA02 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_07 | LCD_DATA03 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_08 | LCD_DATA04 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_09 | LCD_DATA05 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_10 | LCD_DATA06 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_11 | LCD_DATA07 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_12 | LCD_DATA08 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_13 | LCD_DATA09 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_14 | LCD_DATA10 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_15 | LCD_DATA11 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_00 | LCD_DATA12 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_01 | LCD_DATA13 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_02 | LCD_DATA14 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_03 | LCD_DATA15 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_06 | ENET_RX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_09 | ENET_TX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_10 | ENET_REF_CLK | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_11 | ENET_RX_ER | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_12 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_14 | USDHC1_VSELECT | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_40 | ENET_MDC | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_41 | ENET_MDIO | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | ENET_RST | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | ENET_INT | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_10 | ADC | ADC1 Channel 15 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_09 | SAI1_MCLK | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_12 | SAI1_RX | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_13 | SAI1_TX | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_14 | SAI1_TX_BCLK | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_15 | SAI1_TX_SYNC | I2S | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R278, R279, - R280 and R281 must be populated with zero ohm resistors. - -System Clock -============ - -The MIMXRT1060 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - - -Serial Port -=========== - -The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console, -``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the -remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -.. _Using LinkServer: - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT1060-EVK Debug Firmware` - -.. _Using J-Link RT1060: - -Using J-Link ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ or -`Using J-Link with MIMXRT1060-EVKB`_ for more details. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J45 and J46 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J41. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Using SWO ---------- -SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. -Your SWO viewer should be configured with a CPU frequency of 132MHz, and -SWO frequency of 7500KHz. - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1060_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW9 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1060_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1060_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1060_evk - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the boot header in QSPI flash is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the QSPI flash with the following -steps: - -#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. - -#. Reset by pressing SW9 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. - -#. Reset by pressing SW9 - -If the west flash or debug commands fail, and the command hangs while executing -runners.jlink, confirm the J-Link debug probe is configured, powered, and -connected to the EVK properly. See :ref:`Using J-Link RT1060` for more details. - -.. _MIMXRT1060-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1060-evaluation-kit:MIMXRT1060-EVKB - -.. _MIMXRT1060-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT10601064EKBHUG - -.. _MIMXRT1060-EVK Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _MIMXRT1060-EVK Schematics: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1060-EVK-DESIGNFILE-A3 - -.. _i.MX RT1060 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060 - -.. _i.MX RT1060 Datasheet: - https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf - -.. _i.MX RT1060 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM - -.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 - -.. _Using J-Link with MIMXRT1060-EVKB: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVKB/ta-p/1452717 - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig deleted file mode 100644 index 40d615261b37a3..00000000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1060_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.dts b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.dts deleted file mode 100644 index efdf5e2ff229db..00000000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.dts +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2018, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1060_evk.dts" - -/delete-node/ &is25wp064; - -/ { - chosen { - zephyr,flash-controller = &s26ks512s0; - zephyr,flash = &s26ks512s0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - ahb-bufferable; - ahb-cacheable; - sck-differential-clock; - combination-mode; - rx-clock-source = <3>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; - s26ks512s0: s26ks512s@0 { - compatible = "nxp,imx-flexspi-hyperflash"; - size = ; - reg = <0>; - spi-max-frequency = <166000000>; - word-addressable; - cs-interval-unit = <1>; - cs-interval = <2>; - cs-hold-time = <0>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <3>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <20>; - status = "okay"; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(256)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@40000 { - label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@341000 { - label = "image-1"; - reg = <0x00341000 DT_SIZE_M(3)>; - }; - storage_partition: partition@641000 { - label = "storage"; - reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; - }; - }; - }; -}; diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.yaml b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.yaml deleted file mode 100644 index fa29bdfaa14429..00000000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1060_evk_hyperflash -name: NXP MIMXRT1060-EVK-HYPERFLASH -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32768 -flash: 65536 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - counter - - display - - dma - - gpio - - i2c - - netif:eth - - sdhc - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash_defconfig b/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash_defconfig deleted file mode 100644 index 418a8293e11dd6..00000000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk_hyperflash_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1060_EVK_HYPERFLASH=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb_defconfig b/boards/arm/mimxrt1060_evk/mimxrt1060_evkb_defconfig deleted file mode 100644 index bb1a6edb668766..00000000000000 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2022, Whisper.ai -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1060_EVKB=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1062_fmurt6/CMakeLists.txt b/boards/arm/mimxrt1062_fmurt6/CMakeLists.txt deleted file mode 100644 index 29f92cc83c6e06..00000000000000 --- a/boards/arm/mimxrt1062_fmurt6/CMakeLists.txt +++ /dev/null @@ -1,40 +0,0 @@ -# -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2023 NXP -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(CONFIG_BOARD_MIMXRT1062_FMURT6) - # No flash configuration block exists for the RT1060 with HyperFlash in - # the SDK, but we can reuse the block for the RT1050 as FMURT6 also uses - # the same HyperFlash chip - set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) - set(BOARD_NAME evkbimxrt1050) - endif() - set(RT1062_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1062_BOARD_DIR}/xip/${FLASH_CONF}) - zephyr_library_include_directories(${RT1062_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1050 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1062_BOARD_DIR}/dcd.c) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1062_fmurt6/Kconfig.board b/boards/arm/mimxrt1062_fmurt6/Kconfig.board deleted file mode 100644 index 97c653e75f2a83..00000000000000 --- a/boards/arm/mimxrt1062_fmurt6/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# Copyright 2023 NXP - -config BOARD_MIMXRT1062_FMURT6 - bool "NXP MIMXRT1062-FMURT6" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mimxrt1062_fmurt6/Kconfig.defconfig b/boards/arm/mimxrt1062_fmurt6/Kconfig.defconfig deleted file mode 100644 index 8e349eb07ed09e..00000000000000 --- a/boards/arm/mimxrt1062_fmurt6/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# MIMXRT1062-FMURT6 board - -# SPDX-License-Identifier: Apache-2.0 -# Copyright 2023 NXP - -if BOARD_MIMXRT1062_FMURT6 - -config BOARD - default "mimxrt1062_fmurt6" if BOARD_MIMXRT1062_FMURT6 - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - - -endif # BOARD_MIMXRT1062_FMURT6 diff --git a/boards/arm/mimxrt1064_evk/CMakeLists.txt b/boards/arm/mimxrt1064_evk/CMakeLists.txt deleted file mode 100644 index 630fac7d67d07d..00000000000000 --- a/boards/arm/mimxrt1064_evk/CMakeLists.txt +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright 2018-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if (CONFIG_DISPLAY) -message(WARNING " -CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board -") -endif() - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT DEFINED CONFIG_BOARD_MIMXRT1064_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1064-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1064_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1064") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1064 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1064_BOARD_DIR}/xip/evkmimxrt1064_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1064_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1064 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1064_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1064_evk/Kconfig.board b/boards/arm/mimxrt1064_evk/Kconfig.board deleted file mode 100644 index 0ce09d06fd4414..00000000000000 --- a/boards/arm/mimxrt1064_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1064_EVK - bool "NXP MIMXRT1064-EVK" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1064DVL6A diff --git a/boards/arm/mimxrt1064_evk/Kconfig.defconfig b/boards/arm/mimxrt1064_evk/Kconfig.defconfig deleted file mode 100644 index e0604d39621012..00000000000000 --- a/boards/arm/mimxrt1064_evk/Kconfig.defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# MIMXRT1064-EVK board - -# Copyright 2018,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1064_EVK - -config BOARD - default "mimxrt1064_evk" - -choice CODE_LOCATION - default CODE_FLEXSPI2 -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -if NETWORKING - -config NET_L2_ETHERNET - default y - -if ETH_MCUX - -config ETH_MCUX_PHY_RESET - default y - -endif # ETH_MCUX - -endif # NETWORKING - -if LVGL - -config LV_Z_VDB_SIZE - default 16 - -config LV_DPI_DEF - default 128 - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_16 -endchoice - -endif # LVGL - -endif # BOARD_MIMXRT1064_EVK diff --git a/boards/arm/mimxrt1064_evk/doc/index.rst b/boards/arm/mimxrt1064_evk/doc/index.rst deleted file mode 100644 index 24abf5ca76f57b..00000000000000 --- a/boards/arm/mimxrt1064_evk/doc/index.rst +++ /dev/null @@ -1,477 +0,0 @@ -.. _mimxrt1064_evk: - -NXP MIMXRT1064-EVK -################## - -Overview -******** - -The i.MX RT1064 adds to the industry's first crossover -processor series and expands the i.MX RT series to three scalable families. -The i.MX RT1064 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin -compatibility with i.MX RT1050. This series introduces additional features -ideal for real-time applications such as High-Speed GPIO, CAN FD, and -synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1064 runs on the -Arm® Cortex-M7® core up to 600 MHz. - -.. image:: mimxrt1064_evk.jpg - :align: center - :alt: MIMXRT1064-EVK - -Hardware -******** - -- MIMXRT1064DVL6A MCU (600 MHz, 1024 KB on-chip memory, 4096KB on-chip QSPI - flash) - -- Memory - - - 256 Mbit SDRAM - - 64 Mbit QSPI Flash - - 512 Mbit Hyper Flash - - TF socket for SD card - -- Display - - - LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - CMOS camera sensor interface - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1064 SoC and MIMXRT1064-EVK board, see -these references: - -- `i.MX RT1064 Website`_ -- `i.MX RT1064 Datasheet`_ -- `i.MX RT1064 Reference Manual`_ -- `MIMXRT1064-EVK Website`_ -- `MIMXRT1064-EVK Quick Reference Guide`_ -- `MIMXRT1064-EVK User Guide`_ -- `MIMXRT1064-EVK Schematics`_ -- `MIMXRT1064-EVK Debug Firmware`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| MT48LC16M16A2 | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -NXP considers the MIMXRT1064-EVK as the superset board for the i.MX RT10xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT10xx family. NXP prioritizes enabling -this board with new support for Zephyr features. The mimxrt1064_evk board -configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | display | -+-----------+------------+-------------------------------------+ -| VIDEO | on-chip | video, using CSI | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | QSPI flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| ENET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and I/Os -==================== - -The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_05 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | GPIO/ENET_RST | LED/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_11 | GPIO | Touch Interrupt | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_12 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_13 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_06 | LPUART3_TX | UART Arduino | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_07 | LPUART3_RX | UART Arduino | -+---------------+-----------------+---------------------------+ -| WAKEUP | GPIO | SW0 | -+---------------+-----------------+---------------------------+ -| GPIO_B0_00 | LCD_CLK | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_01 | LCD_ENABLE | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_02 | LCD_HSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_03 | LCD_VSYNC | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_04 | LCD_DATA00 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_05 | LCD_DATA01 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_06 | LCD_DATA02 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_07 | LCD_DATA03 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_08 | LCD_DATA04 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_09 | LCD_DATA05 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_10 | LCD_DATA06 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_11 | LCD_DATA07 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_12 | LCD_DATA08 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_13 | LCD_DATA09 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_14 | LCD_DATA10 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B0_15 | LCD_DATA11 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_00 | LCD_DATA12 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_01 | LCD_DATA13 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_02 | LCD_DATA14 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_03 | LCD_DATA15 | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_06 | ENET_RX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_09 | ENET_TX_EN | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_10 | ENET_REF_CLK | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_11 | ENET_RX_ER | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_B1_12 | GPIO | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_14 | USDHC1_VSELECT | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_40 | ENET_MDC | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_EMC_41 | ENET_MDIO | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_09 | ENET_RST | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B0_10 | ENET_INT | Ethernet | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_05 | FLEXSPIA_DQS | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_06 | FLEXSPIA_SS0_B | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_07 | FLEXSPIA_SCLK | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_08 | FLEXSPIA_DATA00 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_09 | FLEXSPIA_DATA01 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_10 | FLEXSPIA_DATA02 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_SD_B1_11 | FLEXSPIA_DATA03 | QSPI Flash | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_B1_10 | ADC | ADC1 Channel 1 | -+---------------+-----------------+---------------------------+ - -.. note:: - In order to use the SPI peripheral on this board, resistors R278, R279, - R280 and R281 must be populated with zero ohm resistors - -System Clock -============ - -The MIMXRT1064 SoC is configured to use SysTick as the system clock source, -running at 600MHz. - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1064 SoC has eight UARTs. ``LPUART1`` is configured for the console -and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -.. note:: - When the device transitions into low power states, the debugger may be - unable to access the chip. Use caution when enabling ``CONFIG_PM``, and - if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064` - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -.. _Using LinkServer: - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT1064-EVK Debug Firmware` - -.. _Using J-Link RT1064: - -Using J-Link ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ for more -details. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J45 and J46 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J41. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Using SWO ---------- -SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. -Your SWO viewer should be configured with a CPU frequency of 132MHz, and -SWO frequency of 7500KHz. - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1064_evk - :goals: flash - -Open a serial terminal, reset the board (press the SW9 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1064_evk - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1064_evk - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! mimxrt1064_evk - - -.. _Troubleshooting RT1064: - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the boot header in QSPI flash is invalid or corrupted. The boot header is -configured by :kconfig:option:`CONFIG_NXP_IMX_RT_BOOT_HEADER`. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the QSPI flash with the following -steps: - -#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. - -#. Reset by pressing SW9 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application. - -#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. - -#. Reset by pressing SW9 - -If the west flash or debug commands fail, and the command hangs while executing -runners.jlink, confirm the J-Link debug probe is configured, powered, and -connected to the EVK properly. See :ref:`Using J-Link RT1064` for more -details. - -.. _MIMXRT1064-EVK Website: - https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK - -.. _MIMXRT1064-EVK Quick Reference Guide: - https://www.nxp.com/webapp/Download?colCode=IMXRT1064QSG - -.. _MIMXRT1064-EVK User Guide: - https://www.nxp.com/docs/en/data-sheet/MIMXRT10601064EKBHUG.pdf - -.. _MIMXRT1064-EVK Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _MIMXRT1064-EVK Schematics: - https://www.nxp.com/webapp/Download?colCode=i.MXRT160EVKDS&Parent_nodeId=1537930933174731284155&Parent_pageType=product - -.. _i.MX RT1064 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1064-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1064 - -.. _i.MX RT1064 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1064CEC.pdf - -.. _i.MX RT1064 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1064RM - -.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 diff --git a/boards/arm/mimxrt1160_evk/CMakeLists.txt b/boards/arm/mimxrt1160_evk/CMakeLists.txt deleted file mode 100644 index 62d5ed6a61cec9..00000000000000 --- a/boards/arm/mimxrt1160_evk/CMakeLists.txt +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT (DEFINED CONFIG_BOARD_MIMXRT1160_EVK_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1160_EVK_CM4)) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1160-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - set(RT1160_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1160") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1160 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1160_BOARD_DIR}/xip/evkmimxrt1160_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1160_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1160 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1160_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1160_evk/Kconfig.board b/boards/arm/mimxrt1160_evk/Kconfig.board deleted file mode 100644 index 2f7b3533bf7bfd..00000000000000 --- a/boards/arm/mimxrt1160_evk/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1160_EVK_CM7 - bool "NXP MIMXRT1160-EVK CM7" - depends on SOC_MIMXRT1166_CM7 - select SOC_PART_NUMBER_MIMXRT1166DVM6A - -config BOARD_MIMXRT1160_EVK_CM4 - bool "NXP MIMXRT1160-EVK CM4" - depends on SOC_MIMXRT1166_CM4 - select SOC_PART_NUMBER_MIMXRT1166DVM6A diff --git a/boards/arm/mimxrt1160_evk/Kconfig.defconfig b/boards/arm/mimxrt1160_evk/Kconfig.defconfig deleted file mode 100644 index 9f7f09e84c2ee5..00000000000000 --- a/boards/arm/mimxrt1160_evk/Kconfig.defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# MIMXRT1160-EVK board - -# Copyright 2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4 - -config BOARD - default "mimxrt1160_evk_cm7" if BOARD_MIMXRT1160_EVK_CM7 - default "mimxrt1160_evk_cm4" if BOARD_MIMXRT1160_EVK_CM4 - -choice CODE_LOCATION - default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7 - default CODE_OCRAM if BOARD_MIMXRT1160_EVK_CM4 && SECOND_CORE_MCUX - default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4 -endchoice - -# Only use DCD when booting primary core (M7) -config DEVICE_CONFIGURATION_DATA - default y if CPU_CORTEX_M7 - -config NXP_IMX_EXTERNAL_SDRAM - default y if CPU_CORTEX_M7 - -if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_CM4 - -config BUILD_OUTPUT_INFO_HEADER - default y - -DT_CHOSEN_IMAGE_M4 = nxp,m4-partition - -# Adjust the offset of the output image if building for RT11xx SOC -config BUILD_OUTPUT_ADJUST_LMA - default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ - $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ - $(dt_node_reg_addr_hex,/soc/ocram@20200000)" - -endif - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK - default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK - -if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif #FLASH - -if NETWORKING - -config NET_L2_ETHERNET - default y if CPU_CORTEX_M7 # No cache memory support is required for driver - -config ETH_MCUX_PHY_RESET - default y - -endif # NETWORKING - -endif # BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4 diff --git a/boards/arm/mimxrt1160_evk/doc/index.rst b/boards/arm/mimxrt1160_evk/doc/index.rst deleted file mode 100644 index 2449429a891e88..00000000000000 --- a/boards/arm/mimxrt1160_evk/doc/index.rst +++ /dev/null @@ -1,366 +0,0 @@ -.. _mimxrt1160_evk: - -NXP MIMXRT1160-EVK -################## - -Overview -******** - -The dual core i.MX RT1160 runs on the Cortex-M7 core at 600 MHz and on the -Cortex-M4 at 240 MHz. The i.MX RT1160 MCU offers support over a wide -temperature range and is qualified for consumer, industrial and automotive -markets. - -.. image:: mimxrt1160_evk.jpg - :align: center - :alt: MIMXRT1160-EVK - -Hardware -******** - -- MIMXRT1166DVM6A MCU - - - 600MHz Cortex-M7 & 240Mhz Cortex-M4 - - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 - -- Memory - - - 512 Mbit SDRAM - - 128 Mbit QSPI Flash - - 512 Mbit Octal Flash - - TF socket for SD card - -- Display - - - MIPI LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - - 10/100/1000 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - OpenSDA with DAPLink - -- Sensor - - - MIPI camera sensor connector - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1160 SoC and MIMXRT1160-EVK board, see -these references: - -- `i.MX RT1160 Website`_ -- `i.MX RT1160 Datasheet`_ -- `i.MX RT1160 Reference Manual`_ -- `MIMXRT1160-EVK Website`_ -- `MIMXRT1160-EVK Board Hardware User's Guide`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| W9825G6KH | SEMC | Enabled via device configuration | -| | | data block, which sets up SEMC at | -| | | boot time | -+--------------------+------------+-------------------------------------+ -| IS25WP128 | FLEXSPI | Enabled via flash configurationn | -| | | block, which sets up FLEXSPI at | -| | | boot time. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -The mimxrt1160_evk board configuration supports the hardware features listed -below. For additional features not yet supported, please also refer to the -:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family. -NXP prioritizes enabling the superset board with NXP's Full Platform Support for -Zephyr. Therefore, the mimxrt1170_evk board may have additional features -already supported, which can also be re-used on this mimxrt1160_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | flexcan | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ -| GPT | on-chip | gpt | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB Device | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| CAAM RNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig`` - -Other hardware features are not currently supported by the port. - - -Connections and I/Os -==================== - -The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers. - -+---------------+-----------------+---------------------------+ -| Name | Function | Usage | -+===============+=================+===========================+ -| WAKEUP | GPIO | SW7 | -+---------------+-----------------+---------------------------+ -| GPIO_AD_04 | GPIO | LED | -+---------------+-----------------+---------------------------+ -| GPIO_AD_24 | LPUART1_TX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_AD_25 | LPUART1_RX | UART Console | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_00 | CAN3_TX | flexcan | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_01 | CAN3_RX | flexcan | -+---------------+-----------------+---------------------------+ -| GPIO_AD_29 | SPI1_CS0 | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_28 | SPI1_CLK | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_30 | SPI1_SDO | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_31 | SPI1_SDI | spi | -+---------------+-----------------+---------------------------+ -| GPIO_AD_08 | LPI2C1_SCL | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_AD_09 | LPI2C1_SDA | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_05 | LPI2C5_SCL | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_LPSR_04 | LPI2C5_SDA | i2c | -+---------------+-----------------+---------------------------+ -| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | -+---------------+-----------------+---------------------------+ - - -Dual Core samples -***************** - -+-----------+------------------+----------------------------+ -| Core | Boot Address | Comment | -+===========+==================+============================+ -| Cortex M7 | 0x30000000[630K] | primary core | -+-----------+------------------+----------------------------+ -| Cortex M4 | 0x20020000[96k] | boots from OCRAM | -+-----------+------------------+----------------------------+ - -+----------+------------------+-----------------------+ -| Memory | Address[Size] | Comment | -+==========+==================+=======================+ -| flexspi1 | 0x30000000[16M] | Cortex M7 flash | -+----------+------------------+-----------------------+ -| sdram0 | 0x80030000[64M] | Cortex M7 ram | -+----------+------------------+-----------------------+ -| ocram | 0x20020000[512K] | Cortex M4 "flash" | -+----------+------------------+-----------------------+ -| sram1 | 0x20000000[128K] | Cortex M4 ram | -+----------+------------------+-----------------------+ -| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | -+----------+------------------+-----------------------+ - -Only the first 16K of ocram2 has the correct MPU region attributes set to be -used as shared memory - -System Clock -============ - -The MIMXRT1160 SoC is configured to use SysTick as the system clock source, -running at 600MHz. When targeting the M4 core, SysTick will also be used, -running at 240MHz - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1160 SoC has 12 UARTs. One is configured for the console and the -remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Building a Dual-Core Image -========================== -Dual core samples load the M4 core image from flash into the shared ``ocram`` -region. The M7 core then sets the M4 boot address to this region. The only -sample currently enabled for dual core builds is the ``openamp`` sample. -To flash a dual core sample, the M4 image must be flashed first, so that it is -written to flash. Then, the M7 image must be flashed. The openamp sysbuild -sample will do this automatically by setting the image order. - -The secondary core can be debugged normally in single core builds -(where the target is ``mimxrt1160_evk_cm4``). For dual core builds, the -secondary core should be placed into a loop, then a debugger can be attached -(see `AN13264`_, section 4.2.3 for more information) - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, -however the :ref:`pyocd-debug-host-tools` do not yet support programming the -external flashes on this board so you must reconfigure the board for one of the -following debug probes instead. - -.. _Using J-Link RT1160: - -Using J-Link ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. Check that -jumpers J5 and J8 are **on** (they are on by default when boards ship from -the factory) to connect UART signals to the OpenSDA microcontroller. - -Connect a USB cable from your PC to J11. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -Before power on the board, make sure SW1 is set to 0001b - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1160_evk_cm7 - :goals: flash - -Power off the board, and change SW1 to 0010b. Then power on the board and -open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.6.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1160_evk_cm7 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1160_evk_cm7 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1160_evk_cm7 - -.. _MIMXRT1160-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1160-evaluation-kit:MIMXRT1160-EVK - -.. _MIMXRT1160-EVK Board Hardware User's Guide: - https://www.nxp.com/webapp/Download?colCode=UM11617 - -.. _i.MX RT1160 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1160-crossover-mcu-family-high-performance-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1160 - -.. _i.MX RT1160 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1160CEC.pdf - -.. _i.MX RT1160 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1160RM - -.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 - -.. _AN13264: - https://www.nxp.com/docs/en/application-note/AN13264.pdf - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml deleted file mode 100644 index 8d0d041c14fbf4..00000000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1160_evk_cm4 -name: NXP MIMXRT1160-EVK CM4 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 128 -flash: 128 -supported: - - dma - - i2c - - gpio - - pwm - - uart -vendor: nxp diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig deleted file mode 100644 index ac3f4bf5b930d1..00000000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1166_CM4=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml deleted file mode 100644 index 48e4f372355bab..00000000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1160_evk_cm7 -name: NXP MIMXRT1160-EVK CM7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 256 -flash: 16384 -supported: - - counter - - can - - dma - - gpio - - hwinfo - - i2c - - netif:eth - - pwm - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig deleted file mode 100644 index 7cdde24c5a0abd..00000000000000 --- a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT1166_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/CMakeLists.txt b/boards/arm/mimxrt1170_evk/CMakeLists.txt deleted file mode 100644 index 48cec3f9786822..00000000000000 --- a/boards/arm/mimxrt1170_evk/CMakeLists.txt +++ /dev/null @@ -1,53 +0,0 @@ -# -# Copyright 2022-2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM4) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM4))) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT1170-EVK, but targeting a custom board. You may need to " - "update your flash configuration or device configuration data blocks") - endif() - if ((DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVK_CM4)) - set(RT1170_BOARD_NAME "evkmimxrt1170") - elseif((DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM7) - OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVKB_CM4)) - set(RT1170_BOARD_NAME "evkbmimxrt1170") - endif() - set(RT1170_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${RT1170_BOARD_NAME}") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(${RT1170_BOARD_DIR}/xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) - zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) - endif() - if(CONFIG_DEVICE_CONFIGURATION_DATA) - # Include device configuration data block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another SDRAM chip - # is used on your custom board. - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_library_sources(${RT1170_BOARD_DIR}/dcd.c) - else() - if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) - message(WARNING "You are using SDRAM as RAM but no device " - "configuration data (DCD) is included. This configuration may not boot") - endif() - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/mimxrt1170_evk/Kconfig.board b/boards/arm/mimxrt1170_evk/Kconfig.board deleted file mode 100644 index b3b5a6e78f8759..00000000000000 --- a/boards/arm/mimxrt1170_evk/Kconfig.board +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright 2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT1170_EVK_CM7 - bool "NXP MIMXRT1170-EVK CM7" - depends on SOC_MIMXRT1176_CM7 - select SOC_PART_NUMBER_MIMXRT1176DVMAA - -config BOARD_MIMXRT1170_EVK_CM4 - bool "NXP MIMXRT1170-EVK CM4" - depends on SOC_MIMXRT1176_CM4 - select SOC_PART_NUMBER_MIMXRT1176DVMAA - -config BOARD_MIMXRT1170_EVKB_CM7 - bool "NXP MIMXRT1170-EVKB CM7" - depends on SOC_MIMXRT1176_CM7 - select SOC_PART_NUMBER_MIMXRT1176DVMAA - -config BOARD_MIMXRT1170_EVKB_CM4 - bool "NXP MIMXRT1170-EVKB CM4" - depends on SOC_MIMXRT1176_CM4 - select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/arm/mimxrt1170_evk/Kconfig.defconfig b/boards/arm/mimxrt1170_evk/Kconfig.defconfig deleted file mode 100644 index 867999f701c8d2..00000000000000 --- a/boards/arm/mimxrt1170_evk/Kconfig.defconfig +++ /dev/null @@ -1,69 +0,0 @@ -# MIMXRT1170-EVK board - -# Copyright 2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT1170_EVK_CM7 || BOARD_MIMXRT1170_EVK_CM4 || \ - BOARD_MIMXRT1170_EVKB_CM7 || BOARD_MIMXRT1170_EVKB_CM4 - -config BOARD - default "mimxrt1170_evk_cm7" if BOARD_MIMXRT1170_EVK_CM7 - default "mimxrt1170_evk_cm4" if BOARD_MIMXRT1170_EVK_CM4 - default "mimxrt1170_evkb_cm7" if BOARD_MIMXRT1170_EVKB_CM7 - default "mimxrt1170_evkb_cm4" if BOARD_MIMXRT1170_EVKB_CM4 - -choice CODE_LOCATION - default CODE_FLEXSPI if CPU_CORTEX_M7 - default CODE_OCRAM if CPU_CORTEX_M4 && SECOND_CORE_MCUX - default CODE_SRAM0 if CPU_CORTEX_M4 -endchoice - -# Only use DCD when booting primary core (M7) -config DEVICE_CONFIGURATION_DATA - default y if CPU_CORTEX_M7 - -config NXP_IMX_EXTERNAL_SDRAM - default y if CPU_CORTEX_M7 - -if SECOND_CORE_MCUX && CPU_CORTEX_M4 - -config BUILD_OUTPUT_INFO_HEADER - default y - -DT_CHOSEN_IMAGE_M4 = nxp,m4-partition - -# Adjust the offset of the output image if building for RT11xx SOC -config BUILD_OUTPUT_ADJUST_LMA - default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ - $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ - $(dt_node_reg_addr_hex,/soc/ocram@20200000)" - -endif - -if DISK_DRIVERS - -config IMX_USDHC_DAT3_PWR_TOGGLE - default y - -endif # DISK_DRIVERS - -if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif #FLASH - -if NETWORKING - -config NET_L2_ETHERNET - default y if CPU_CORTEX_M7 # No cache memory support is required for driver - -config ETH_MCUX_PHY_RESET - default y - -endif # NETWORKING - -endif diff --git a/boards/arm/mimxrt1170_evk/board.cmake b/boards/arm/mimxrt1170_evk/board.cmake deleted file mode 100644 index d543dce8821d8b..00000000000000 --- a/boards/arm/mimxrt1170_evk/board.cmake +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) - board_runner_args(pyocd "--target=mimxrt1170_cm7") - board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load") - - if(CONFIG_BOARD_MIMXRT1170_EVK_CM7) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") - elseif(CONFIG_BOARD_MIMXRT1170_EVKB_CM7) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") - endif() - - board_runner_args(linkserver "--core=cm7") -elseif(CONFIG_SOC_MIMXRT1176_CM4) - board_runner_args(pyocd "--target=mimxrt1170_cm4") - # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core) - board_runner_args(jlink "--device=MIMXRT1176xxxA_M4") - if(CONFIG_BOARD_MIMXRT1170_EVK_CM4) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") - elseif(CONFIG_BOARD_MIMXRT1170_EVKB_CM4) - board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") - endif() - board_runner_args(linkserver "--core=cm4") -endif() - -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/arm/mimxrt1170_evk/doc/index.rst b/boards/arm/mimxrt1170_evk/doc/index.rst deleted file mode 100644 index faff1975ca81e4..00000000000000 --- a/boards/arm/mimxrt1170_evk/doc/index.rst +++ /dev/null @@ -1,454 +0,0 @@ -.. _mimxrt1170_evk: - -NXP MIMXRT1170-EVK/EVKB -####################### - -Overview -******** - -The dual core i.MX RT1170 runs on the Cortex-M7 core at 1 GHz and on the Cortex-M4 -at 400 MHz. The i.MX RT1170 MCU offers support over a wide temperature range -and is qualified for consumer, industrial and automotive markets. Zephyr -supports the initial revision of this EVK, as well as rev EVKB. - -.. image:: mimxrt1170_evk.jpg - :align: center - :alt: MIMXRT1170-EVK - -Hardware -******** - -- MIMXRT1176DVMAA MCU - - - 1GHz Cortex-M7 & 400Mhz Cortex-M4 - - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 - -- Memory - - - 512 Mbit SDRAM - - 128 Mbit QSPI Flash - - 512 Mbit Octal Flash - - 2 Gbit raw NAND flash - - 64 Mbit LPSPI flash - - TF socket for SD card - -- Display - - - MIPI LCD connector - -- Ethernet - - - 10/100 Mbit/s Ethernet PHY - - 10/100/1000 Mbit/s Ethernet PHY - -- USB - - - USB 2.0 OTG connector - - USB 2.0 host connector - -- Audio - - - 3.5 mm audio stereo headphone jack - - Board-mounted microphone - - Left and right speaker out connectors - -- Power - - - 5 V DC jack - -- Debug - - - JTAG 20-pin connector - - on-board debugger - -- Sensor - - - FXOS8700CQ 6-axis e-compass - - MIPI camera sensor connector - -- Expansion port - - - Arduino interface - -- CAN bus connector - -For more information about the MIMXRT1170 SoC and MIMXRT1170-EVK board, see -these references: - -- `i.MX RT1170 Website`_ -- `i.MX RT1170 Datasheet`_ -- `i.MX RT1170 Reference Manual`_ -- `MIMXRT1170-EVK Website`_ -- `MIMXRT1170-EVK Board Hardware User's Guide`_ - -External Memory -=============== - -This platform has the following external memories: - -+--------------------+------------+-------------------------------------+ -| Device | Controller | Status | -+====================+============+=====================================+ -| W9825G6KH | SEMC | Enabled via device configuration | -| SDRAM | | data (DCD) block, which sets up | -| | | the SEMC at boot time | -+--------------------+------------+-------------------------------------+ -| IS25WP128 | FLEXSPI | Enabled via flash configuration | -| QSPI flash | | block (FCB), which sets up the | -| (RT1170 EVK) | | FLEXSPI at boot time. | -+--------------------+------------+-------------------------------------+ -| W25Q512NWEIQ | FLEXSPI | Enabled via flash configuration | -| QSPI flash | | block (FCB), which sets up the | -| (RT1170 EVKB) | | FLEXSPI at boot time. Supported for | -| | | XIP only. | -+--------------------+------------+-------------------------------------+ - -Supported Features -================== - -NXP considers the MIMXRT1170-EVK as the superset board for the i.MX RT11xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT11xx family. NXP prioritizes enabling -this board with new support for Zephyr features. Note that this table -covers two boards: the RT1170 EVK (`mimxrt1170_evk_cm7/cm4`), and -RT1170 EVKB (`mimxrt1170_evkb_cm7/cm4`) - -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB | -+===========+============+=====================================+=================+=================+ -| NVIC | on-chip | nested vector interrupt controller | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SYSTICK | on-chip | systick | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| GPIO | on-chip | gpio | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| COUNTER | on-chip | gpt | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| TIMER | on-chip | gpt | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| CAN | on-chip | flexcan | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SPI | on-chip | spi | Supported (M7) | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| I2C | on-chip | i2c | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| PWM | on-chip | pwm | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| ADC | on-chip | adc | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| UART | on-chip | serial port-polling; | Supported | Supported | -| | | serial port-interrupt; | | | -| | | serial port-async | | | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| DMA | on-chip | dma | Supported | Supported | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| WATCHDOG | on-chip | watchdog | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| ENET | on-chip | ethernet - 10/100M (ENET_QOS or | Supported (M7) | No support | -| ENET1G | | GigE not supported yet) | | | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SAI | on-chip | i2s | Supported | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| USB | on-chip | USB Device | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| HWINFO | on-chip | Unique device serial number | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with | Supported (M7) | Supported (M7) | -| | | :ref:`rk055hdmipi4m`, | | | -| | | :ref:`rk055hdmipi4ma0`, | | | -| | | and :ref:`g1120b0mipi` shields | | | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| ACMP | on-chip | analog comparator | Supported | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| CAAM RNG | on-chip | entropy | Supported (M7) | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| FLEXSPI | on-chip | flash programming | Supported (M7) | No support | -+-----------+------------+-------------------------------------+-----------------+-----------------+ -| SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) | -+-----------+------------+-------------------------------------+-----------------+-----------------+ - -The default configuration can be found in the defconfig files: -``boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig`` -``boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig`` - -Connections and I/Os -==================== - -The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. - -+---------------------------+----------------+------------------+ -| Name | Function | Usage | -+---------------------------+----------------+------------------+ -| WAKEUP | GPIO | SW7 | -+---------------------------+----------------+------------------+ -| GPIO_AD_04 | GPIO | LED | -+---------------------------+----------------+------------------+ -| GPIO_AD_24 | LPUART1_TX | UART Console | -+---------------------------+----------------+------------------+ -| GPIO_AD_25 | LPUART1_RX | UART Console | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_00 | CAN3_TX | flexcan | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_01 | CAN3_RX | flexcan | -+---------------------------+----------------+------------------+ -| GPIO_AD_29 | SPI1_CS0 | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_28 | SPI1_CLK | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_30 | SPI1_SDO | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_31 | SPI1_SDI | spi | -+---------------------------+----------------+------------------+ -| GPIO_AD_08 | LPI2C1_SCL | i2c | -+---------------------------+----------------+------------------+ -| GPIO_AD_09 | LPI2C1_SDA | i2c | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_05 | LPI2C5_SCL | i2c | -+---------------------------+----------------+------------------+ -| GPIO_LPSR_04 | LPI2C5_SDA | i2c | -+---------------------------+----------------+------------------+ -| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | -+---------------------------+----------------+------------------+ -| GPIO_AD_32 | ENET_MDC | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_AD_33 | ENET_MDIO | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_05 | ENET_REF_CLK | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet | -+---------------------------+----------------+------------------+ -| GPIO_AD_17_SAI1_MCLK | SAI_MCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_21_SAI1_TX_DATA00 | SAI1_TX_DATA | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_22_SAI1_TX_BCLK | SAI1_TX_BCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_23_SAI1_TX_SYNC | SAI1_TX_SYNC | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_17_SAI1_MCLK | SAI1_MCLK | SAI | -+---------------------------+----------------+------------------+ -| GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | SAI | -+---------------------------+----------------+------------------+ - -Dual Core samples -***************** - -+-----------+------------------+----------------------------+ -| Core | Boot Address | Comment | -+===========+==================+============================+ -| Cortex M7 | 0x30000000[630K] | primary core | -+-----------+------------------+----------------------------+ -| Cortex M4 | 0x20020000[96k] | boots from OCRAM | -+-----------+------------------+----------------------------+ - -+----------+------------------+-----------------------+ -| Memory | Address[Size] | Comment | -+==========+==================+=======================+ -| flexspi1 | 0x30000000[16M] | Cortex M7 flash | -+----------+------------------+-----------------------+ -| sdram0 | 0x80030000[64M] | Cortex M7 ram | -+----------+------------------+-----------------------+ -| ocram | 0x20020000[512K] | Cortex M4 "flash" | -+----------+------------------+-----------------------+ -| sram1 | 0x20000000[128K] | Cortex M4 ram | -+----------+------------------+-----------------------+ -| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | -+----------+------------------+-----------------------+ - -Only the first 16K of ocram2 has the correct MPU region attributes set to be -used as shared memory - -System Clock -============ - -The MIMXRT1170 SoC is configured to use SysTick as the system clock source, -running at 996MHz. When targeting the M4 core, SysTick will also be used, -running at 400MHz - -When power management is enabled, the 32 KHz low frequency -oscillator on the board will be used as a source for the GPT timer to -generate a system clock. This clock enables lower power states, at the -cost of reduced resolution - -Serial Port -=========== - -The MIMXRT1170 SoC has 12 UARTs. One is configured for the console and the -remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Building a Dual-Core Image -========================== -Dual core samples load the M4 core image from flash into the shared ``ocram`` -region. The M7 core then sets the M4 boot address to this region. The only -sample currently enabled for dual core builds is the ``openamp`` sample. -To flash a dual core sample, the M4 image must be flashed first, so that it is -written to flash. Then, the M7 image must be flashed. The openamp sysbuild -sample will do this automatically by setting the image order. - -The secondary core can be debugged normally in single core builds -(where the target is ``mimxrt1170_evk_cm4``). For dual core builds, the -secondary core should be placed into a loop, then a debugger can be attached -(see `AN13264`_, section 4.2.3 for more information) - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. The on-board -debugger listed below works with the LinkServer runner by default, or can be -reprogrammed with JLink firmware. -- MIMXRT1170-EVKB: :ref:`mcu-link-cmsis-onboard-debug-probe` -- MIMXRT1170-EVK: :ref:`opensda-daplink-onboard-debug-probe` - -Using J-Link ------------- - -JLink is the default runner for this board. Install the -:ref:`jlink-debug-host-tools` and make sure they are in your search path. - -There are two options: the onboard debug circuit can be updated with Segger -J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the -EVK. See `Using J-Link with MIMXRT1170-EVKB`_ or -`Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. - -Using LinkServer ----------------- - -Known limitations with LinkServer and these boards include: -- ``west debug`` does not yet work correctly, and the application image is not -properly written to the memory. `NXP MCUXpresso for Visual Studio Code`_ -can be used to debug Zephyr applications with LinkServer. -- ``west flash`` will not write images to non-flash locations. The flash -command only works when all data in the image is written to flash memory -regions. - -Install the :ref:`linkserver-debug-host-tools` and make sure they are in your -search path. LinkServer works with the default CMSIS-DAP firmware included in -the on-board debugger. - -Use the ``-r linkserver`` option with West to use the LinkServer runner. - -.. code-block:: console - - west flash -r linkserver - -Alternatively, pyOCD can be used to flash and debug the board by using the -``-r pyocd`` option with West. pyOCD is installed when you complete the -:ref:`gs_python_deps` step in the Getting Started Guide. The runners supported -by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP -does not test or support the pyOCD runner. - -Configuring a Console -===================== - -We will use the on-board debugger -microcontroller as a usb-to-serial adapter for the serial console. The following -jumper settings are default on these boards, and are required to connect the -UART signals to the USB bridge circuit: -- MIMXRT1170-EVKB: JP2 open (default) -- MIMXRT1170-EVK: J31 and J32 shorted (default) - -Connect a USB cable from your PC to the on-board debugger USB port: -- MIMXRT1170-EVKB: J86 -- MIMXRT1170-EVK: J11 - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -Before powering the board, make sure SW1 is set to 0001b - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1170_evk_cm7 - :goals: flash - -Power off the board, and change SW1 to 0010b. Then power on the board and -open a serial terminal, reset the board (press the SW4 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1170_evk_cm7 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt1170_evk_cm7 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** - Hello World! mimxrt1170_evk_cm7 - -.. _MIMXRT1170-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK - -.. _MIMXRT1170-EVK Board Hardware User's Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKHUG - -.. _i.MX RT1170 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170 - -.. _i.MX RT1170 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT1170CEC.pdf - -.. _i.MX RT1170 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM - -.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 - -.. _Using J-Link with MIMXRT1170-EVKB: - https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1170-EVKB/ta-p/1715138 - -.. _AN13264: - https://www.nxp.com/docs/en/application-note/AN13264.pdf - -.. _NXP MCUXpresso for Visual Studio Code: - https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC - -Experimental ENET Driver -======================== - -Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new -driver with binding `nxp,enet`, which is experimental and undergoing development, but will have -enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. - -To build for this EVK with the new driver, include the experimental overlay to west build with -the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.yaml deleted file mode 100644 index 69232196b62ec1..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.yaml +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evk_cm4 -name: NXP MIMXRT1170-EVK CM4 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 128 -flash: 128 -supported: - - dma - - gpio - - i2c - - pwm -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig deleted file mode 100644 index dacbbf3e1d2a8c..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2021,2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVK_CM4=y -CONFIG_SOC_MIMXRT1176_CM4=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml deleted file mode 100644 index ba3ae1b201b5b1..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.yaml +++ /dev/null @@ -1,31 +0,0 @@ -# -# Copyright (c) 2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evk_cm7 -name: NXP MIMXRT1170-EVK CM7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 256 -flash: 16384 -supported: - - adc - - counter - - can - - dma - - gpio - - hwinfo - - i2c - - mipi_dsi - - netif:eth - - pwm - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig deleted file mode 100644 index db4c2d5c5a88a7..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2021,2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVK_CM7=y -CONFIG_SOC_MIMXRT1176_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.dts b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.dts deleted file mode 100644 index 79725d1ac35229..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.dts +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1170_evk_cm4.dts" - -/ { - chosen { - /delete-property/ zephyr,flash-controller; - /delete-property/ zephyr,code-partition; - }; - - aliases { - /delete-property/ magn0; - /delete-property/ accel0; - }; -}; - -&flexspi { - /* RT1170 EVKB uses a different QSPI flash chip */ - /delete-node/ is25wp128@0; - status = "okay"; - reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; - w25q512nw:w25q512nw@0 { - /* IS25WP128 flash chip not currently enabled */ - compatible = "nxp,imx-flexspi-nor"; - size = ; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [ef 60 20]; - erase-block-size = <4096>; - write-block-size = <1>; - - /* - * Partitions are present to support dual core operation. - * as flash write is not supported, MCUBoot is not enabled. - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x301000>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 0x300000>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; - }; - }; - }; -}; - -&lpspi1 { - dmas = <&edma_lpsr0 0 36>, <&edma_lpsr0 1 37>; - dma-names = "rx", "tx"; - status = "okay"; -}; - -&lpi2c5 { - /* FXOS accelerometer is not present in this board */ - /delete-node/ fxos8700@1f; -}; - -/* Disable ethernet, as PHY is not supported */ -&enet { - status = "disabled"; -}; diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.yaml deleted file mode 100644 index 77a684f23edd41..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4.yaml +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evkb_cm4 -name: NXP MIMXRT1170-EVKB CM4 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 128 -flash: 128 -supported: - - dma - - gpio - - i2c - - spi - - pwm -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4_defconfig deleted file mode 100644 index b1dd310aa4bf22..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVKB_CM4=y -CONFIG_SOC_MIMXRT1176_CM4=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.dts b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.dts deleted file mode 100644 index feceb9eaa30dfb..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "mimxrt1170_evk_cm7.dts" - -/ { - chosen { - zephyr,flash = &w25q512nw; - /delete-property/ zephyr,flash-controller; - /delete-property/ zephyr,code-partition; - }; - - aliases { - /delete-property/ magn0; - /delete-property/ accel0; - }; -}; - -&flexspi { - /* RT1170 EVKB uses a different QSPI flash chip */ - /delete-node/ is25wp128@0; - status = "okay"; - reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; - w25q512nw:w25q512nw@0 { - /* IS25WP128 flash chip not currently enabled */ - compatible = "nxp,imx-flexspi-nor"; - size = ; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [ef 60 20]; - erase-block-size = <4096>; - write-block-size = <1>; - - /* - * Partitions are present to support dual core operation. - * as flash write is not supported, MCUBoot is not enabled. - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x301000>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 0x300000>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_K(1984)>; - }; - }; - }; -}; - -&lpi2c5 { - /* FXOS accelerometer is not present in this board */ - /delete-node/ fxos8700@1f; -}; - -/* Disable ethernet, as PHY is not supported */ -&enet { - status = "disabled"; -}; diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.yaml b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.yaml deleted file mode 100644 index 03376fd15c3b49..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7.yaml +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt1170_evkb_cm7 -name: NXP MIMXRT1170-EVKB CM7 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 65536 -flash: 65536 -supported: - - adc - - counter - - can - - dma - - gpio - - hwinfo - - i2c - - mipi_dsi - - spi - - usb_device - - watchdog -vendor: nxp diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig b/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig deleted file mode 100644 index a59d2e39e47961..00000000000000 --- a/boards/arm/mimxrt1170_evk/mimxrt1170_evkb_cm7_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_BOARD_MIMXRT1170_EVKB_CM7=y -CONFIG_SOC_MIMXRT1176_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 -CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt595_evk/CMakeLists.txt b/boards/arm/mimxrt595_evk/CMakeLists.txt deleted file mode 100644 index 002c69765453c5..00000000000000 --- a/boards/arm/mimxrt595_evk/CMakeLists.txt +++ /dev/null @@ -1,30 +0,0 @@ -# -# Copyright 2022-2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(board.c) -zephyr_library_include_directories(.) - -if(CONFIG_NXP_IMX_RT5XX_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT595_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT595-EVK, but targeting a custom board. You may need to " - "update your flash configuration block data") - endif() - # Include flash configuration block for R595 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN13304 for more information. - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT595_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt595") - zephyr_library_sources(${RT595_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RT595_BOARD_DIR}/flash_config) -endif() - -# Add custom linker section to relocate framebuffers to PSRAM -zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION - SECTIONS dc_ram.ld) diff --git a/boards/arm/mimxrt595_evk/Kconfig b/boards/arm/mimxrt595_evk/Kconfig deleted file mode 100644 index dcd15490773887..00000000000000 --- a/boards/arm/mimxrt595_evk/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INIT_PRIORITY - int "Board initialization priority" - default 45 - help - Board initialization priority. diff --git a/boards/arm/mimxrt595_evk/Kconfig.board b/boards/arm/mimxrt595_evk/Kconfig.board deleted file mode 100644 index 3716c5ec334c54..00000000000000 --- a/boards/arm/mimxrt595_evk/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT595_EVK - bool "NXP MIMXRT595-EVK" - depends on SOC_SERIES_IMX_RT5XX - select CODE_DATA_RELOCATION_SRAM - select SOC_PART_NUMBER_MIMXRT595SFFOC - select NXP_IMX_RT5XX_BOOT_HEADER if !BOOTLOADER_MCUBOOT diff --git a/boards/arm/mimxrt595_evk/Kconfig.defconfig b/boards/arm/mimxrt595_evk/Kconfig.defconfig deleted file mode 100644 index 96779115e141cf..00000000000000 --- a/boards/arm/mimxrt595_evk/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# MIMXRT595-EVK board - -# Copyright 2022-2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT595_EVK - -config BOARD - default "mimxrt595_evk_cm33" - -config FLASH_MCUX_FLEXSPI_MX25UM51345G - default y if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -if DMA_MCUX_LPC - -# Memory from the heap pool is used to allocate DMA descriptors for -# channels that use multiple blocks for a DMA transfer. -# Adjust HEAP_MEM_POOL_MIN_SIZE in case you need more memory. -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 - -endif # DMA_MCUX_LPC - -# Turn on Device Level Power Management as we wish -# to reconfigure the FlexSPI pins for power savings -# when transitioning the SoC to Deep Low Power modes. -config PM_DEVICE - default y if PM - -config REGULATOR - default y if PM || POWEROFF - -endif # BOARD_MIMXRT595_EVK diff --git a/boards/arm/mimxrt595_evk/doc/index.rst b/boards/arm/mimxrt595_evk/doc/index.rst deleted file mode 100644 index 8bdbd864a4e086..00000000000000 --- a/boards/arm/mimxrt595_evk/doc/index.rst +++ /dev/null @@ -1,334 +0,0 @@ -.. _mimxrt595_evk: - -NXP MIMXRT595-EVK -################## - -Overview -******** - -i.MX RT500 crossover MCUs are part of the edge computing family and are optimized -for low-power HMI applications by combining a graphics engine and a streamlined -Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33 -core. These devices are designed to unlock the potential of display-based applications -with a secure, power-optimized embedded processor. - -i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces -to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly -decryption engine. - -.. image:: mimxrt595_evk.jpg - :align: center - :alt: MIMXRT595-EVK - -Hardware -******** - -- MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP -- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) -- USB2.0 high-speed host and device with micro USB connector and external crystal -- Octal/Quad/pSRAM external memories via FlexSPI -- 5 MB system SRAM -- Full size SD card slot (SDIO) -- On-board eMMC chip -- On-board 5 V inputs NXP PCA9420UK PMIC providing 1.2 V, 1.8 V, 3.3 V -- User LEDs -- Reset and User buttons -- MIPI-DSI connector -- Single row headers for ARDUINO signals and MikroBus connector -- FlexIO connector for MikroElektronica TFT Proto 5 inch capacitive touch display -- One motion sensor combo accelero-/magneto-meter NXP FXOS8700CQ -- Stereo audio codec with line-In/ line-Out/ and Microphone -- Pmod/host expansion connector -- NXP TFA9896 audio digital amplifier -- Support for up to eight off-board digital microphones via 12-pin header -- Two on-board digital microphones - -For more information about the MIMXRT595 SoC and MIMXRT595-EVK board, see -these references: - -- `i.MX RT595 Website`_ -- `i.MX RT595 Datasheet`_ -- `i.MX RT595 Reference Manual`_ -- `MIMXRT595-EVK Website`_ -- `MIMXRT595-EVK User Guide`_ -- `MIMXRT595-EVK Schematics`_ -- `MIMXRT595-EVK Debug Firmware`_ - -Supported Features -================== - -NXP considers the MIMXRT595-EVK as a superset board for the i.MX RT5xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT5xx family. NXP prioritizes enabling -this board with new support for Zephyr features. The mimxrt595_evk board -configuration supports the hardware features below. Another very similar -board is the :ref:`mimxrt685_evk`, and that board may have additional features -already supported, which can also be re-used on this mimxrt595_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| OS_TIMER | on-chip | os timer | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | OctalSPI Flash | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PM | on-chip | power management; uses SoC sleep, | -| | | deep sleep and deep-powerdown modes | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access (works with eMMC & SD) | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with | -| | | :ref:`rk055hdmipi4m`, | -| | | :ref:`rk055hdmipi4ma0`, and | -| | | :ref:`g1120b0mipi` display shields | -+-----------+------------+-------------------------------------+ -| DMIC | on-chip | dmic | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT595 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_2 | USART0 | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_1 | USART0 | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_14 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ -| PIO0_25 | GPIO | SW0 | -+---------+-----------------+----------------------------+ -| PIO0_10 | GPIO | SW1 | -+---------+-----------------+----------------------------+ -| PIO4_30 | USART12 | USART TX | -+---------+-----------------+----------------------------+ -| PIO4_31 | USART12 | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_29 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO0_30 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO0_22 | GPIO | FXOS8700 TRIGGER | -+---------+-----------------+----------------------------+ -| PIO1_5 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO1_4 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO1_3 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO1_6 | SPI | SPI SSEL | -+---------+-----------------+----------------------------+ -| PIO0_5 | SCT0 | SCT0 GPI0 | -+---------+-----------------+----------------------------+ -| PIO0_6 | SCT0 | SCT0 GPI1 | -+---------+-----------------+----------------------------+ - -System Clock -============ - -The MIMXRT595 EVK is configured to use the OS Event timer -as a source for the system clock. - -Serial Port -=========== - -The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Fusion F1 DSP Core -================== - -You can build a Zephyr application for the RT500 DSP core using nxp_adsp_rt595 -board. Xtensa toolchain supporting RT500 DSP core is included in Zephyr SDK. -To build the hello_world sample for the RT500 DSP core: - -.. code-block:: shell - - $ west build -b nxp_adsp_rt595 samples/hello_world - -For detailed instructions on how to debug DSP firmware, please refer to -this document: `Getting Started with Xplorer for EVK-MIMXRT595`_ - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2. - -.. tabs:: - - .. group-tab:: LPCLink2 JLink Onboard - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, - if not already done (these jumpers are installed by default). - 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the - J-Link firmware. Please make sure you have the latest firmware for this board. - - .. group-tab:: JLink External - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - - 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, - and J19 (these are installed by default). - - 3. Connect the J-Link probe to J2 10-pin header. - - See :ref:`jlink-external-debug-probe` for more information. - - .. group-tab:: Linkserver - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. - 2. To update the debug firmware, please follow the instructions on `MIMXRT595-EVK Debug Firmware` - -Configuring a Console -===================== - -Connect a USB cable from your PC to J40, and use the serial terminal of your choice -(minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt595_evk_cm33 - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS v2.7 *** - Hello World! mimxrt595_evk_cm33 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`jlink-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt595_evk_cm33 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS v2.7 *** - Hello World! mimxrt595_evk_cm33 - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the image in flash is interfering and causing this issue. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the flash with the following -steps: - -#. Set the SW7 DIP switches to ON-ON-ON to prevent booting from flash. - -#. Reset by pressing SW3 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application (example "Hello World"). - -#. Set the SW5 DIP switches to OFF-OFF-ON to boot from flash. - -#. Reset by pressing SW3 - -.. _MIMXRT595-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK - -.. _MIMXRT595-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=MIMXRT595EVKHUG - -.. _MIMXRT595-EVK Debug Firmware: - https://www.nxp.com/docs/en/application-note/AN13206.pdf - -.. _MIMXRT595-EVK Schematics: - https://www.nxp.com/downloads/en/schematics/MIMXRT595-EVK-DESIGN-FILES.zip - -.. _i.MX RT595 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt500-crossover-mcu-with-arm-cortex-m33-dsp-and-gpu-cores:i.MX-RT500 - -.. _i.MX RT595 Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMXRT500EC.pdf - -.. _i.MX RT595 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMXRT500RM - -.. _Getting Started with Xplorer for EVK-MIMXRT595: - https://www.nxp.com/docs/en/supporting-information/GSXEVKMIMXRT595.pdf diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts deleted file mode 100644 index f32420304df7f2..00000000000000 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.dts +++ /dev/null @@ -1,512 +0,0 @@ -/* - * Copyright 2022-2023, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include - -#include "mimxrt595_evk_cm33-pinctrl.dtsi" - - -/ { - model = "NXP MIMXRT595-EVK board"; - compatible = "nxp,mimxrt595"; - - aliases { - sw0 = &user_button_1; - sw1 = &user_button_2; - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - usart-0 = &flexcomm0; - watchdog0 = &wwdt0; - magn0 = &fxos8700; - accel0 = &fxos8700; - sdhc0 = &usdhc0; - pwm-0 = &sc_timer; - dmic-dev = &dmic0; - }; - - chosen { - zephyr,flash-controller = &mx25um51345g; - zephyr,flash = &mx25um51345g; - zephyr,code-partition = &slot0_partition; - zephyr,sram = &sram0; - zephyr,console = &flexcomm0; - zephyr,shell-uart = &flexcomm0; - zephyr,display = &lcdif; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_1: button_0 { - label = "User SW1"; - gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_2: button_1 { - label = "User SW2"; - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - leds { - compatible = "gpio-leds"; - green_led: led_1 { - gpios = <&gpio1 0 0>; - label = "User LED_GREEN"; - }; - blue_led: led_2 { - gpios = <&gpio3 17 0>; - label = "User LED_BLUE"; - }; - red_led: led_3 { - gpios = <&gpio0 14 0>; - label = "User LED_RED"; - }; - }; - - arduino_header: arduino-connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 5 0>, /* A0 */ - <1 0 &gpio0 6 0>, /* A1 */ - <2 0 &gpio0 19 0>, /* A2 */ - <3 0 &gpio0 13 0>, /* A3 */ - <4 0 &gpio4 22 0>, /* A4 */ - <5 0 &gpio4 21 0>, /* A5 */ - <6 0 &gpio4 31 0>, /* D0 */ - <7 0 &gpio4 30 0>, /* D1 */ - <8 0 &gpio4 20 0>, /* D2 */ - <9 0 &gpio4 23 0>, /* D3 */ - <10 0 &gpio4 24 0>, /* D4 */ - <11 0 &gpio4 25 0>, /* D5 */ - <12 0 &gpio4 26 0>, /* D6 */ - <13 0 &gpio4 27 0>, /* D7 */ - <14 0 &gpio4 28 0>, /* D8 */ - <15 0 &gpio4 29 0>, /* D9 */ - <16 0 &gpio5 0 0>, /* D10 */ - <17 0 &gpio5 1 0>, /* D11 */ - <18 0 &gpio5 2 0>, /* D12 */ - <19 0 &gpio5 3 0>, /* D13 */ - <20 0 &gpio4 22 0>, /* D14 */ - <21 0 &gpio4 21 0>; /* D15 */ - }; - - /* - * This node describes the GPIO pins of the MIPI FPC interface, - * J44 on the EVK. This interface is standard to several - * NXP EVKs, and is used with several MIPI displays - * (available as zephyr shields) - */ - nxp_mipi_connector: mipi-connector { - compatible = "gpio-nexus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 12 0>, /* Pin 1, LEDK */ - <21 0 &gpio3 21 0>, /* Pin 21, RESET */ - <22 0 &gpio3 18 0>, /* Pin 22, LPTE */ - <26 0 &gpio0 30 0>, /* Pin 26, CTP_I2C SDA */ - <27 0 &gpio0 29 0>, /* Pin 27, CTP_I2C SCL */ - <28 0 &gpio4 4 0>, /* Pin 28, CTP_RST */ - <29 0 &gpio3 19 0>, /* Pin 29, CTP_INT */ - <32 0 &gpio3 15 0>, /* Pin 32, PWR_EN */ - <34 0 &gpio0 12 0>; /* Pin 34, BL_PWM */ - }; - - en_mipi_display: enable-mipi-display { - compatible = "regulator-fixed"; - regulator-name = "en_mipi_display"; - enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; -}; - -/* - * RT595 EVK board uses OS timer as the kernel timer - * In case we need to switch to SYSTICK timer, then - * replace &os_timer with &systick - */ -&os_timer { - status = "okay"; - wakeup-source; -}; - -&rtc { - status = "okay"; -}; - -&flexcomm0 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm0_usart>; - pinctrl-names = "default"; - dmas = <&dma0 0>, <&dma0 1>; - dma-names = "rx", "tx"; -}; - -arduino_i2c: &flexcomm4 { - compatible = "nxp,lpc-i2c"; - status = "okay"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pinmux_flexcomm4_i2c>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -nxp_mipi_i2c: &arduino_i2c {}; - -zephyr_mipi_dsi: &mipi_dsi {}; - -zephyr_lcdif: &lcdif {}; - - -hs_spi1: &hs_lspi1 { - compatible = "nxp,lpc-spi"; - pinctrl-0 = <&pinmux_flexcomm16_spi>; - pinctrl-names = "default"; - dmas = <&dma0 28>, <&dma0 29>; - dma-names = "rx", "tx"; - status = "okay"; -}; - -/* I2S RX */ -i2s0: &flexcomm1 { - compatible = "nxp,lpc-i2s"; - pinctrl-0 = <&pinmux_flexcomm1_i2s>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 2>; - dma-names = "rx"; - status = "disabled"; -}; - -/* I2S TX */ -i2s1: &flexcomm3 { - compatible = "nxp,lpc-i2s"; - pinctrl-0 = <&pinmux_flexcomm3_i2s>; - pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 7>; - dma-names = "tx"; - status = "disabled"; -}; - -arduino_serial: &flexcomm12 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm12_usart>; - pinctrl-names = "default"; - dmas = <&dma0 34>, <&dma0 35>; - dma-names = "rx", "tx"; -}; - -/* PCA9420 PMIC */ -&pmic_i2c { - status = "okay"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pinmux_pmic_i2c>; - pinctrl-names = "default"; - - pca9420: pca9420@61 { - compatible = "nxp,pca9420"; - reg = <0x61>; - nxp,enable-modesel-pins; - - pca9420_sw1: BUCK1 { - regulator-boot-on; - nxp,mode0-microvolt = <1100000>; - nxp,mode1-microvolt = <600000>; - nxp,mode2-microvolt = <900000>; - nxp,mode3-microvolt = <800000>; - }; - - pca9420_sw2: BUCK2 { - regulator-boot-on; - nxp,mode0-microvolt = <1800000>; - nxp,mode1-microvolt = <1800000>; - nxp,mode2-microvolt = <1800000>; - nxp,mode3-microvolt = <1800000>; - }; - - pca9420_ldo1: LDO1 { - regulator-boot-on; - nxp,mode0-microvolt = <1800000>; - nxp,mode1-microvolt = <1800000>; - nxp,mode2-microvolt = <1800000>; - nxp,mode3-microvolt = <1800000>; - }; - - pca9420_ldo2: LDO2 { - regulator-boot-on; - nxp,mode0-microvolt = <3300000>; - nxp,mode1-microvolt = <3300000>; - nxp,mode2-microvolt = <3300000>; - nxp,mode3-microvolt = <3300000>; - }; - }; -}; - -&lpadc0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpadc0>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -/* - * GPIO module interrupts are shared between all GPIO devices on this - * SOC, but Zephyr does not currently support sharing interrupts between - * devices. The user can select GPIO modules to support interrupts by - * setting the appropriate `int-source` and `interrupt` property for - * a given module. On this board, GPIO3 and GPIO4 are configured to support - * interrupts. - */ -&gpio3 { - status = "okay"; - int-source = "int-a"; - interrupts = <2 0>; -}; - -&gpio4 { - status = "okay"; - int-source = "int-b"; - interrupts = <3 0>; -}; - -&gpio5 { - status = "okay"; -}; - -&gpio6 { - status = "okay"; -}; - -&user_button_1 { - status = "okay"; -}; - -&user_button_2 { - status = "okay"; -}; - -&green_led { - status = "okay"; -}; - -&blue_led { - status = "okay"; -}; - -&red_led { - status = "okay"; -}; - -&dma0 { - status = "okay"; -}; - -zephyr_udc0: &usbhs { - status = "okay"; -}; - -&ctimer0 { - status = "okay"; -}; - -&ctimer1 { - status = "okay"; -}; - -&ctimer2 { - status = "okay"; -}; - -&ctimer3 { - status = "okay"; -}; - -&ctimer4 { - status = "okay"; -}; - -&usdhc0 { - status = "okay"; - pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - mmc { - compatible = "zephyr,mmc-disk"; - status = "okay"; - }; - pinctrl-0 = <&pinmux_usdhc>; - pinctrl-names = "default"; - mmc-hs200-1_8v; - mmc-hs400-1_8v; -}; - -&wwdt0 { - status = "okay"; -}; - -&flexspi { - status = "okay"; - pinctrl-0 = <&pinmux_flexspi>; - pinctrl-1 = <&pinmux_flexspi_sleep>; - pinctrl-names = "default", "sleep"; - - mx25um51345g: mx25um51345g@0 { - compatible = "nxp,imx-flexspi-mx25um51345g"; - /* MX25UM51245G is 64MB, 512MBit flash part */ - size = ; - reg = <0>; - spi-max-frequency = <200000000>; - status = "okay"; - jedec-id = [c2 81 3a]; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 DT_SIZE_K(3076)>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 DT_SIZE_K(3072)>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_M(57)>; - }; - }; - }; -}; - -&flexspi2 { - status = "okay"; - pinctrl-0 = <&pinmux_flexspi2>; - pinctrl-names = "default"; - rx-clock-source = <3>; - ahb-prefetch; - ahb-bufferable; - ahb-cacheable; - ahb-read-addr-opt; - aps6408l: aps6408l@0 { - compatible = "nxp,imx-flexspi-aps6408l"; - /* APS6408L is 8MB, 64MBit pSRAM */ - size = ; - reg = <0>; - spi-max-frequency = <198000000>; - status = "okay"; - cs-interval-unit = <1>; - cs-interval = <5>; - cs-hold-time = <3>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <0>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <0>; - }; -}; - -&sc_timer { - pinctrl-0 = <&pinmux_sctimer_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i3c0 { - pinctrl-0 = <&pinmux_i3c>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&mbox { - status = "okay"; -}; - -/* Disable this node if not using USB and need another MPU region */ -&sram1 { - status = "okay"; -}; - -/* Enable smartDMA controller */ -&smartdma { - status = "okay"; -}; - -/* Add smartDMA to mipi DSI */ -&mipi_dsi { - dmas = <&smartdma>; - dma-names = "smartdma"; -}; - -&dmic0 { - status = "okay"; - pinctrl-0 = <&pinmux_dmic0>; - pinctrl-names = "default"; - use2fs; -}; - -/* Configure pdm channels 0 and 1 with gain, and cutoff settings - * appropriate for the attached MEMS microphones. - */ -&pdmc0 { - status = "okay"; - gainshift = <3>; - dc-cutoff = "155hz"; - dc-gain = <1>; -}; - -&pdmc1 { - status = "okay"; - gainshift = <3>; - dc-cutoff = "155hz"; - dc-gain = <1>; -}; - -&mrt_channel0 { - status = "okay"; -}; diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml deleted file mode 100644 index 95b17cb059fd90..00000000000000 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33.yaml +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt595_evk_cm33 -name: NXP MIMXRT595-EVK -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 4608 -flash: 65536 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - counter - - dma - - gpio - - i2c - - spi - - usb_device - - watchdog - - sdhc - - pwm - - i2s - - dmic -vendor: nxp diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig b/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig deleted file mode 100644 index 054e0f219133a6..00000000000000 --- a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT595S_CM33=y -CONFIG_SOC_SERIES_IMX_RT5XX=y -CONFIG_BOARD_MIMXRT595_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_PINCTRL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_SECURE=y -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mimxrt685_evk/CMakeLists.txt b/boards/arm/mimxrt685_evk/CMakeLists.txt deleted file mode 100644 index 35c6f881ff7234..00000000000000 --- a/boards/arm/mimxrt685_evk/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright 2020-2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(init.c) - -if(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER) - if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK) - message(WARNING "It appears you are using the board definition for " - "the MIMXRT685-EVK, but targeting a custom board. You may need to " - "update your flash configuration block data") - endif() - # Include flash configuration block for R685 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN13386 for more information. - zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - set(RT685_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt685") - zephyr_library_sources(${RT685_BOARD_DIR}/flash_config/flash_config.c) - zephyr_library_include_directories(${RT685_BOARD_DIR}/flash_config) -endif() diff --git a/boards/arm/mimxrt685_evk/Kconfig.board b/boards/arm/mimxrt685_evk/Kconfig.board deleted file mode 100644 index e1223fa03f398e..00000000000000 --- a/boards/arm/mimxrt685_evk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMXRT685_EVK - bool "NXP MIMXRT685-EVK" - depends on SOC_SERIES_IMX_RT6XX - select SOC_PART_NUMBER_MIMXRT685SFVKB - select NXP_IMX_RT6XX_BOOT_HEADER if !BOOTLOADER_MCUBOOT diff --git a/boards/arm/mimxrt685_evk/Kconfig.defconfig b/boards/arm/mimxrt685_evk/Kconfig.defconfig deleted file mode 100644 index db2679a3d4d170..00000000000000 --- a/boards/arm/mimxrt685_evk/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# MIMXRT685-EVK board - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMXRT685_EVK - -config BOARD - default "mimxrt685_evk_cm33" - -config XTAL_SYS_CLK_HZ - default 24000000 - -config SYSOSC_SETTLING_US - default 260 - -choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE - default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR -endchoice - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM -endchoice - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -endif # BOARD_MIMXRT685_EVK diff --git a/boards/arm/mimxrt685_evk/doc/index.rst b/boards/arm/mimxrt685_evk/doc/index.rst deleted file mode 100644 index 579cd1e4087d11..00000000000000 --- a/boards/arm/mimxrt685_evk/doc/index.rst +++ /dev/null @@ -1,370 +0,0 @@ -.. _mimxrt685_evk: - -NXP MIMXRT685-EVK -################## - -Overview -******** - -The i.MX RT600 is a crossover MCU family optimized for 32-bit immersive audio -playback and voice user interface applications combining a high-performance -Cadence Tensilica HiFi 4 audio DSP core with a next-generation Cortex-M33 -core. The i.MX RT600 family of crossover MCUs is designed to unlock the -potential of voice-assisted end nodes with a secure, power-optimized embedded -processor. - -The i.MX RT600 family provides up to 4.5MB of on-chip SRAM and several -high-bandwidth interfaces to access off-chip flash, including an Octal/Quad SPI -interface with an on-the-fly decryption engine. - -.. image:: mimxrt685_evk.jpg - :align: center - :alt: MIMXRT685-EVK - -Hardware -******** - -- MIMXRT685SFVKB Cortex-M33 (300 MHz, 128 KB TCM) core processor with Cadence Xtensa HiFi4 DSP -- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) -- High speed USB port with micro A/B connector for the host or device functionality -- UART, I2C and SPI port bridging from i.MX RT685 target to USB via the on-board debug probe -- 512 MB Macronix Octal SPI Flash operating at 1.8 V -- 4.5 MB Apmemory PSRAM -- Full size SD card slot (SDIO) -- NXP PCA9420UK PMIC -- User LEDs -- Reset and User buttons -- Arduino and PMod/Host expansion connectors -- NXP FXOS8700CQ accelerometer -- Stereo audio codec with line in/out and electret microphone -- Stereo NXP TFA9894 digital amplifiers, with option for external +5V power for higher performance speakers -- Support for up to eight off-board digital microphones via 12-pin header -- Two on-board DMICS - -For more information about the MIMXRT685 SoC and MIMXRT685-EVK board, see -these references: - -- `i.MX RT685 Website`_ -- `i.MX RT685 Datasheet`_ -- `i.MX RT685 Reference Manual`_ -- `MIMXRT685-EVK Website`_ -- `MIMXRT685-EVK User Guide`_ -- `MIMXRT685-EVK Schematics`_ - -Supported Features -================== - -NXP considers the MIMXRT685-EVK as a superset board for the i.MX RT6xx -family of MCUs. This board is a focus for NXP's Full Platform Support for -Zephyr, to better enable the entire RT6xx family. NXP prioritizes enabling -this board with new support for Zephyr features. The mimxrt685_evk board -configuration supports the hardware features below. Another very similar -board is the :ref:`mimxrt595_evk`, and that board may have additional features -already supported, which can also be re-used on this mimxrt685_evk board: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| OS_TIMER | on-chip | os timer | -+-----------+------------+-------------------------------------+ -| IOCON | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | OctalSPI Flash | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| SDHC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| FLEXSPI | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The MIMXRT685 SoC has IOCON registers, which can be used to configure the -functionality of a pin. - -+---------+-----------------+----------------------------+ -| Name | Function | Usage | -+=========+=================+============================+ -| PIO0_2 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO0_1 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_14 | GPIO | GREEN LED | -+---------+-----------------+----------------------------+ -| PIO1_1 | GPIO | SW0 | -+---------+-----------------+----------------------------+ -| PIO0_17 | I2C | I2C SDA | -+---------+-----------------+----------------------------+ -| PIO0_18 | I2C | I2C SCL | -+---------+-----------------+----------------------------+ -| PIO1_5 | GPIO | FXOS8700 TRIGGER | -+---------+-----------------+----------------------------+ -| PIO1_5 | SPI | SPI MOSI | -+---------+-----------------+----------------------------+ -| PIO1_4 | SPI | SPI MISO | -+---------+-----------------+----------------------------+ -| PIO1_3 | SPI | SPI SCK | -+---------+-----------------+----------------------------+ -| PIO1_6 | SPI | SPI SSEL | -+---------+-----------------+----------------------------+ -| PIO0_23 | I2S | I2S DATAOUT | -+---------+-----------------+----------------------------+ -| PIO0_22 | I2S | I2S TX WS | -+---------+-----------------+----------------------------+ -| PIO0_21 | I2S | I2S TX SCK | -+---------+-----------------+----------------------------+ -| PIO0_9 | I2S | I2S DATAIN | -+---------+-----------------+----------------------------+ -| PIO0_29 | USART | USART TX | -+---------+-----------------+----------------------------+ -| PIO0_30 | USART | USART RX | -+---------+-----------------+----------------------------+ -| PIO1_11 | FLEXSPI0B_DATA0 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_12 | FLEXSPI0B_DATA1 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_13 | FLEXSPI0B_DATA2 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_14 | FLEXSPI0B_DATA3 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO1_29 | FLEXSPI0B_SCLK | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_12 | PIO2_12 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_17 | FLEXSPI0B_DATA4 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_18 | FLEXSPI0B_DATA5 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_19 | FLEXSPI0B_SS0_N | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_22 | FLEXSPI0B_DATA6 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO2_23 | FLEXSPI0B_DATA7 | OctalSPI Flash | -+---------+-----------------+----------------------------+ -| PIO0_27 | SCT0_OUT7 | PWM | -+---------+-----------------+----------------------------+ -| PIO1_30 | SD0_CLK | SD card | -+---------+-----------------+----------------------------+ -| PIO1_31 | SD0_CMD | SD card | -+---------+-----------------+----------------------------+ -| PIO2_0 | SD0_D0 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_1 | SD0_D1 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_2 | SD0_D2 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_3 | SD0_D3 | SD card | -+---------+-----------------+----------------------------+ -| PIO2_4 | SD0_WR_PRT | SD card | -+---------+-----------------+----------------------------+ -| PIO2_9 | SD0_CD | SD card | -+---------+-----------------+----------------------------+ -| PIO2_10 | SD0_RST | SD card | -+---------+-----------------+----------------------------+ - -System Clock -============ - -The MIMXRT685 EVK is configured to use the OS Event timer -as a source for the system clock. - -Serial Port -=========== - -The MIMXRT685 SoC has 8 FLEXCOMM interfaces for serial communication. One is -configured as USART for the console and the remaining are not used. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the LPC-Link2. - -.. tabs:: - - .. group-tab:: LinkServer CMSIS-DAP - - 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your - search path. LinkServer works with the default CMSIS-DAP firmware included in - the on-board debugger. - 2. Make sure the jumpers JP17, JP18 and JP19 are installed. - - linkserver is the default runner for this board - - .. code-block:: console - - west flash - west debug - - .. group-tab:: LPCLink2 JLink Onboard - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, - if not already done (these jumpers are installed by default). - 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the - J-Link firmware. Please make sure you have the latest firmware for this board. - - .. code-block:: console - - west flash -r jlink - west debug -r jlink - - .. group-tab:: JLink External - - - 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. - - 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, - and J19 (these are installed by default). - - 3. Connect the J-Link probe to J2 10-pin header. - - See :ref:`jlink-external-debug-probe` for more information. - - .. code-block:: console - - west flash -r jlink - west debug -r jlink - -Configuring a Console -===================== - -Connect a USB cable from your PC to J16, and use the serial terminal of your choice -(minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`linkserver-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt685_evk_cm33 - :goals: flash - -Open a serial terminal, reset the board (press the RESET button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0 ***** - Hello World! mimxrt685_evk_cm33 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. This example uses the -:ref:`linkserver-debug-host-tools` as default. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mimxrt685_evk_cm33 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS zephyr-v2.3.0 ***** - Hello World! mimxrt685_evk_cm33 - -Troubleshooting -=============== - -If the debug probe fails to connect with the following error, it's possible -that the image in flash is interfering and causing this issue. - -.. code-block:: console - - Remote debugging using :2331 - Remote communication error. Target disconnected.: Connection reset by peer. - "monitor" command not supported by this target. - "monitor" command not supported by this target. - You can't do that when your target is `exec' - (gdb) Could not connect to target. - Please check power, connection and settings. - -You can fix it by erasing and reprogramming the flash with the following -steps: - -#. Set the SW5 DIP switches to ON-ON-ON to prevent booting from flash. - -#. Reset by pressing SW3 - -#. Run ``west debug`` or ``west flash`` again with a known working Zephyr - application (example "Hello World"). - -#. Set the SW5 DIP switches to ON-OFF-ON to boot from flash. - -#. Reset by pressing SW3 - -.. _MIMXRT685-EVK Website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK - -.. _MIMXRT685-EVK User Guide: - https://www.nxp.com/webapp/Download?colCode=UM11159 - -.. _MIMXRT685-EVK Schematics: - https://www.nxp.com/downloads/en/design-support/RT685-DESIGNFILES.zip - -.. _i.MX RT685 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt600-crossover-mcu-with-arm-cortex-m33-and-dsp-cores:i.MX-RT600 - -.. _i.MX RT685 Datasheet: - https://www.nxp.com/docs/en/data-sheet/DS-RT600.pdf - -.. _i.MX RT685 Reference Manual: - https://www.nxp.com/webapp/Download?colCode=UM11147 diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts deleted file mode 100644 index 245e9833c3ef66..00000000000000 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.dts +++ /dev/null @@ -1,387 +0,0 @@ -/* - * Copyright (c) 2020-2023, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include -#include - -#include "mimxrt685_evk_cm33-pinctrl.dtsi" - -/ { - model = "NXP MIMXRT685-EVK board"; - compatible = "nxp,mimxrt685"; - - aliases { - sw0 = &user_button_1; - sw1 = &user_button_2; - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - usart-0 = &flexcomm0; - /* For pwm test suites */ - pwm-0 = &sc_timer; - pwm-led0 = &green_pwm_led; - green-pwm-led = &green_pwm_led; - blue-pwm-led = &blue_pwm_led; - red-pwm-led = &red_pwm_led; - watchdog0 = &wwdt0; - magn0 = &fxos8700; - accel0 = &fxos8700; - sdhc0 = &usdhc0; - }; - - chosen { - zephyr,flash-controller = &mx25um51345g; - zephyr,flash = &mx25um51345g; - zephyr,code-partition = &slot0_partition; - zephyr,sram = &sram0; - zephyr,console = &flexcomm0; - zephyr,shell-uart = &flexcomm0; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_1: button_0 { - label = "User SW1"; - gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_2: button_1 { - label = "User SW2"; - gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - leds: leds { - compatible = "gpio-leds"; - green_led: led_1 { - gpios = <&gpio0 14 0>; - label = "User LED_GREEN"; - }; - blue_led: led_2 { - gpios = <&gpio0 26 0>; - label = "User LED_BLUE"; - }; - red_led: led_3 { - gpios = <&gpio0 31 0>; - label = "User LED_RED"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - green_pwm_led: green_pwm_led { - pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "Green PWM LED"; - status = "okay"; - }; - blue_pwm_led: blue_pwm_led { - pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "Blue PWM LED"; - status = "okay"; - }; - red_pwm_led: red_pwm_led { - pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "Red PWM LED"; - status = "disabled"; - }; - }; - - arduino_header: arduino-connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 5 0>, /* A0 */ - <1 0 &gpio0 6 0>, /* A1 */ - <2 0 &gpio0 19 0>, /* A2 */ - <3 0 &gpio0 20 0>, /* A3 */ - <4 0 &gpio0 17 0>, /* A4 */ - <5 0 &gpio0 18 0>, /* A5 */ - <6 0 &gpio0 30 0>, /* D0 */ - <7 0 &gpio0 29 0>, /* D1 */ - <8 0 &gpio0 28 0>, /* D2 */ - <9 0 &gpio0 27 0>, /* D3 */ - <10 0 &gpio1 0 0>, /* D4 */ - <11 0 &gpio1 10 0>, /* D5 */ - <12 0 &gpio1 2 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 9 0>, /* D8 */ - <15 0 &gpio1 7 0>, /* D9 */ - <16 0 &gpio1 6 0>, /* D10 */ - <17 0 &gpio1 5 0>, /* D11 */ - <18 0 &gpio1 4 0>, /* D12 */ - <19 0 &gpio1 3 0>, /* D13 */ - <20 0 &gpio0 17 0>, /* D14 */ - <21 0 &gpio0 18 0>; /* D15 */ - }; -}; - -/* - * RT600 EVK board uses OS timer as the kernel timer - * In case we need to switch to SYSTICK timer, then - * replace &os_timer with &systick - */ -&os_timer { - status = "okay"; - wakeup-source; -}; - -&rtc { - status = "okay"; -}; - -&flexcomm0 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm0_usart>; - pinctrl-names = "default"; - dmas = <&dma0 0>, <&dma0 1>; - dma-names = "rx", "tx"; -}; - -arduino_i2c: &flexcomm2 { - compatible = "nxp,lpc-i2c"; - status = "okay"; - pinctrl-0 = <&pinmux_flexcomm2_i2c>; - pinctrl-names = "default"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - }; -}; - -arduino_serial: &flexcomm4 { - compatible = "nxp,lpc-usart"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&pinmux_flexcomm4_usart>; - pinctrl-names = "default"; - dmas = <&dma0 8>, <&dma0 9>; - dma-names = "rx", "tx"; -}; - -arduino_spi: &flexcomm5 { - compatible = "nxp,lpc-spi"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 10>, <&dma0 11>; - dma-names = "rx", "tx"; - pinctrl-0 = <&pinmux_flexcomm5_spi>; - pinctrl-names = "default"; -}; - -/* I2S receive channel */ -i2s0: &flexcomm1 { - status = "okay"; - compatible = "nxp,lpc-i2s"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 2>; - dma-names = "rx"; - pinctrl-0 = <&pinmux_flexcomm1_i2s>; - pinctrl-names = "default"; -}; - -/* I2S transmit channel */ -i2s1: &flexcomm3 { - status = "okay"; - compatible = "nxp,lpc-i2s"; - #address-cells = <1>; - #size-cells = <0>; - dmas = <&dma0 7>; - dma-names = "tx"; - pinctrl-0 = <&pinmux_flexcomm3_i2s>; - pinctrl-names = "default"; -}; - -/* PCA9420 PMIC */ -&pmic_i2c { - status = "okay"; - compatible = "nxp,lpc-i2c"; - clock-frequency = ; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-0 = <&pinmux_pmic_i2c>; - pinctrl-names = "default"; - - pca9420: pca9420@61 { - compatible = "nxp,pca9420"; - reg = <0x61>; - nxp,enable-modesel-pins; - - buck1: BUCK1 { - regulator-boot-on; - }; - - buck2: BUCK2 { - regulator-boot-on; - }; - - ldo1: LDO1 { - regulator-boot-on; - }; - - ldo2: LDO2 { - regulator-boot-on; - }; - - - }; -}; - -&flexspi { - pinctrl-0 = <&pinmux_flexspi>; - pinctrl-names = "default"; - status = "okay"; - mx25um51345g: mx25um51345g@2 { - compatible = "nxp,imx-flexspi-mx25um51345g"; - /* MX25UM51245G is 64MB, 512MBit flash part */ - size = ; - reg = <2>; - spi-max-frequency = <200000000>; - status = "okay"; - jedec-id = [c2 81 3a]; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(128)>; - }; - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 DT_SIZE_K(3076)>; - }; - slot1_partition: partition@321000 { - label = "image-1"; - reg = <0x00321000 DT_SIZE_K(3072)>; - }; - storage_partition: partition@621000 { - label = "storage"; - reg = <0x00621000 DT_SIZE_M(57)>; - }; - }; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&gpio2 { - status = "okay"; -}; - -&dma0 { - status = "okay"; -}; - -&wwdt0 { - status = "okay"; -}; - -&user_button_1 { - status = "okay"; -}; - -&user_button_2 { - status = "okay"; -}; - -&green_led { - status = "okay"; -}; - -&blue_led { - status = "okay"; -}; - -&red_led { - status = "okay"; -}; - -&sc_timer { - status = "okay"; - pinctrl-0 = <&pinmux_sctimer>; - pinctrl-names = "default"; -}; - -&usdhc0 { - status = "okay"; - /* Quick fix for 1.8V SD cards on RT600- disable 1.8V negotiation */ - no-1-8-v; - pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; - sdmmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - pinctrl-0 = <&pinmux_usdhc>; - pinctrl-names = "default"; -}; - -&lpadc0 { - status = "okay"; - pinctrl-0 = <&pinmux_lpadc0>; - pinctrl-names = "default"; -}; - -zephyr_udc0: &usbhs { - status = "okay"; -}; - -&ctimer0 { - status = "okay"; -}; - -&ctimer1 { - status = "okay"; -}; - -&ctimer2 { - status = "okay"; -}; - -&ctimer3 { - status = "okay"; -}; - -&ctimer4 { - status = "okay"; -}; - -&i3c0 { - pinctrl-0 = <&pinmux_i3c>; - pinctrl-names = "default"; - - status = "okay"; -}; - -/* Disable this node if not using USB and need another MPU region */ -&sram1 { - status = "okay"; -}; diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml deleted file mode 100644 index d940cbe35f8b4d..00000000000000 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33.yaml +++ /dev/null @@ -1,34 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: mimxrt685_evk_cm33 -name: NXP MIMXRT685-EVK -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 4608 -flash: 65536 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - counter - - dma - - pwm - - gpio - - hwinfo - - i2c - - i3c - - i2s - - sdhc - - spi - - watchdog - - usb_device -vendor: nxp diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig b/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig deleted file mode 100644 index 05673abdd6b7b0..00000000000000 --- a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MIMXRT685S_CM33=y -CONFIG_SOC_SERIES_IMX_RT6XX=y -CONFIG_BOARD_MIMXRT685_EVK=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_PINCTRL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -# Enable TrustZone-M -CONFIG_TRUSTED_EXECUTION_SECURE=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mm_feather/CMakeLists.txt b/boards/arm/mm_feather/CMakeLists.txt deleted file mode 100644 index e20be4b42e0737..00000000000000 --- a/boards/arm/mm_feather/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 2021 MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) - zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmfeather_sdram_ini_dcd.c) -endif() diff --git a/boards/arm/mm_feather/Kconfig.board b/boards/arm/mm_feather/Kconfig.board deleted file mode 100644 index c003514fdab122..00000000000000 --- a/boards/arm/mm_feather/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2021, MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_MM_FEATHER - bool "MM MM-FEATHER" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mm_feather/Kconfig.defconfig b/boards/arm/mm_feather/Kconfig.defconfig deleted file mode 100644 index 80201fdcb8645f..00000000000000 --- a/boards/arm/mm_feather/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# MM-FEATHER board - -# Copyright (c) 2021, MADMACHINE LIMITED -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MM_FEATHER - -config BOARD - default "mm_feather" - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_MM_FEATHER diff --git a/boards/arm/mm_feather/flexspi_nor_config.c b/boards/arm/mm_feather/flexspi_nor_config.c deleted file mode 100644 index 647dac001c92ae..00000000000000 --- a/boards/arm/mm_feather/flexspi_nor_config.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0xEB, RADDR_SDR, - FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, - 0x06, READ_SDR, - FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/mm_swiftio/CMakeLists.txt b/boards/arm/mm_swiftio/CMakeLists.txt deleted file mode 100644 index 8fb1964f3209ac..00000000000000 --- a/boards/arm/mm_swiftio/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright (c) 20179 MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) - zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmswiftio_sdram_ini_dcd.c) -endif() diff --git a/boards/arm/mm_swiftio/Kconfig.board b/boards/arm/mm_swiftio/Kconfig.board deleted file mode 100644 index 65352dfdc01cc3..00000000000000 --- a/boards/arm/mm_swiftio/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# -# Copyright (c) 2019, MADMACHINE LIMITED -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_MM_SWIFTIO - bool "MM MM-SWIFTIO" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1052DVL6A diff --git a/boards/arm/mm_swiftio/Kconfig.defconfig b/boards/arm/mm_swiftio/Kconfig.defconfig deleted file mode 100644 index 95fe8e06d9c8e9..00000000000000 --- a/boards/arm/mm_swiftio/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# MM-SWIFTIO board - -# Copyright (c) 2019, MADMACHINE LIMITED -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MM_SWIFTIO - -config BOARD - default "mm_swiftio" - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DEVICE_CONFIGURATION_DATA - default y - -config NXP_IMX_EXTERNAL_SDRAM - default y - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_MM_SWIFTIO diff --git a/boards/arm/mm_swiftio/flexspi_nor_config.c b/boards/arm/mm_swiftio/flexspi_nor_config.c deleted file mode 100644 index 647dac001c92ae..00000000000000 --- a/boards/arm/mm_swiftio/flexspi_nor_config.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0xEB, RADDR_SDR, - FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, - 0x06, READ_SDR, - FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/mps2/CMakeLists.txt b/boards/arm/mps2/CMakeLists.txt new file mode 100644 index 00000000000000..2f6cea861c66c6 --- /dev/null +++ b/boards/arm/mps2/CMakeLists.txt @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(pinmux.c) + +if(CONFIG_BOARD_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP) + # Building a firmware image for CPU1: this requires a binary + # for CPU0, which will boot the device and wake up CPU1. + # However, if building with OPENAMP, there is no need to build + # any binary for CPU0, as this is built by the dual core sample. + set(CPU0_BINARY_DIR ${BOARD_DIR}/empty_cpu0-prefix/src/empty-cpu0-build/zephyr) + + include(ExternalProject) + + ExternalProject_Add( + empty_cpu0 + SOURCE_DIR ${BOARD_DIR}/empty_cpu0 + INSTALL_COMMAND "" + CMAKE_CACHE_ARGS -DBOARD:STRING=${BOARD}/an521/cpu0 + BUILD_BYPRODUCTS "${CPU0_BINARY_DIR}/${KERNEL_BIN_NAME}" + BUILD_ALWAYS True + ) +endif() diff --git a/boards/arm/mps2/Kconfig b/boards/arm/mps2/Kconfig new file mode 100644 index 00000000000000..4beda641d532d3 --- /dev/null +++ b/boards/arm/mps2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS2 + select QEMU_TARGET + select HAS_COVERAGE_SUPPORT diff --git a/boards/arm/mps2/Kconfig.defconfig b/boards/arm/mps2/Kconfig.defconfig new file mode 100644 index 00000000000000..b14613b4880815 --- /dev/null +++ b/boards/arm/mps2/Kconfig.defconfig @@ -0,0 +1,60 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MPS2_AN385 + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +config ZTEST_STACK_SIZE + default 4096 if ZTEST + +if COVERAGE_GCOV + +config MAIN_STACK_SIZE + default 4096 + +config IDLE_STACK_SIZE + default 4096 + +config PRIVILEGED_STACK_SIZE + default 4096 + +config ISR_STACK_SIZE + default 4096 + +config TEST_EXTRA_STACK_SIZE + default 4096 + +endif # COVERAGE_GCOV + +endif + +if BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1 + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped but QEMU +# will still permit bus access. +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET + +endchoice + +# By default, if we build for a Non-Secure version of the board, +# force building with TF-M as the Secure Execution Environment. +config BUILD_WITH_TFM + default y if TRUSTED_EXECUTION_NONSECURE + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +endif diff --git a/boards/arm/mps2/Kconfig.mps2 b/boards/arm/mps2/Kconfig.mps2 new file mode 100644 index 00000000000000..0731c5d2855080 --- /dev/null +++ b/boards/arm/mps2/Kconfig.mps2 @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS2 + select SOC_MPS2_AN385 if BOARD_MPS2_AN385 + select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0 + select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0_NS + select SOC_MPS2_AN521_CPU1 if BOARD_MPS2_AN521_CPU1 diff --git a/boards/arm/mps2/board.cmake b/boards/arm/mps2/board.cmake new file mode 100644 index 00000000000000..21d98c39bfa0dd --- /dev/null +++ b/boards/arm/mps2/board.cmake @@ -0,0 +1,43 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +if(CONFIG_BOARD_MPS2_AN385) + set(QEMU_CPU_TYPE_${ARCH} cortex-m3) + set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -machine mps2-an385 + -nographic + -vga none + ) +elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1) + set(QEMU_CPU_TYPE_${ARCH} cortex-m33) + set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -machine mps2-an521 + -nographic + -m 16 + -vga none + ) +endif() + +board_set_debugger_ifnset(qemu) + +if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1) + # To enable a host tty switch between serial and pty + # -chardev serial,path=/dev/ttyS0,id=hostS0 + list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0) + + if(CONFIG_BUILD_WITH_TFM) + # Override the binary used by qemu, to use the combined + # TF-M (Secure) & Zephyr (Non Secure) image (when running + # in-tree tests). + set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") + elseif(CONFIG_OPENAMP) + set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf") + elseif(CONFIG_BOARD_MPS2_AN521_CPU1) + set(CPU0_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr/boards/arm/mps2/empty_cpu0-prefix/src/empty_cpu0-build/zephyr) + set(QEMU_KERNEL_OPTION "-device;loader,file=${CPU0_BINARY_DIR}/zephyr.elf") + list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}") + endif() +endif() diff --git a/boards/arm/mps2/board.yml b/boards/arm/mps2/board.yml new file mode 100644 index 00000000000000..a069852c1c60f3 --- /dev/null +++ b/boards/arm/mps2/board.yml @@ -0,0 +1,9 @@ +board: + name: mps2 + vendor: arm + socs: + - name: an385 + - name: an521 + variants: + - name: ns + cpucluster: cpu0 diff --git a/boards/arm/mps2_an385/doc/img/mps2_an385.jpg b/boards/arm/mps2/doc/img/mps2_an385.jpg similarity index 100% rename from boards/arm/mps2_an385/doc/img/mps2_an385.jpg rename to boards/arm/mps2/doc/img/mps2_an385.jpg diff --git a/boards/arm/mps2_an521/doc/img/mps2_an521.jpg b/boards/arm/mps2/doc/img/mps2_an521.jpg similarity index 100% rename from boards/arm/mps2_an521/doc/img/mps2_an521.jpg rename to boards/arm/mps2/doc/img/mps2_an521.jpg diff --git a/boards/arm/mps2/doc/mps2_an385.rst b/boards/arm/mps2/doc/mps2_an385.rst new file mode 100644 index 00000000000000..ffd8942dbfddf6 --- /dev/null +++ b/boards/arm/mps2/doc/mps2_an385.rst @@ -0,0 +1,281 @@ +.. _mps2_an385_board: + +ARM V2M MPS2 +############ + +Overview +******** + +The mps2/an385 board configuration is used by Zephyr applications that run on +the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and +the following devices: + +- Nested Vectored Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) +- Cortex-M System Design Kit UART + +.. image:: img/mps2_an385.jpg + :align: center + :alt: ARM V2M MPS2 + +In addition to enabling actual hardware usage, this board configuration can +also use QEMU to emulate the AN385 platform running on the MPS2+. + +More information about the board can be found at the `V2M MPS2 Website`_. + +The Application Note AN385 can be found at `Application Note AN385`_. + +.. note:: + This board configuration makes no claims about its suitability for use + with actual MPS2 hardware systems using AN385, or any other hardware + system. It has been tested on actual hardware, but its primary purpose is + for use with QEMU and unit tests. + +Hardware +******** + +ARM V2M MPS2 provides the following hardware components: + +- ARM Cortex-M3 (AN385) +- ARM IoT Subsystem for Cortex-M +- Form factor: 140x120cm +- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM +- Video: QSVGA touch screen panel, 4bit RGB VGA connector +- Audio: Audio Codec +- Debug: + + - ARM JTAG20 connector + - ARM parallel trace connector (MICTOR38) + - 20 pin Cortex debug connector + - 10 pin Cortex debug connector + - ILA connector for FPGA debug + +- Expansion + + - GPIO + - SPI + +.. note:: + 4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM + (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available. + +Supported Features +================== + +The mps2/an385 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| DUALTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. +See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware +features. + +The default configuration can be found in +:zephyr_file:`boards/arm/mps2/mps2_an385_defconfig` + +Interrupt Controller +==================== + +MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs. + +A Cortex-M3/4-based board uses vectored exceptions. This means each exception +calls a handler directly from the vector table. + +Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here +identifies the handlers used for each exception. + ++------+------------+----------------+--------------------------+ +| Exc# | Name | Remarks | Used by Zephyr Kernel | ++======+============+================+==========================+ +| 1 | Reset | | system initialization | ++------+------------+----------------+--------------------------+ +| 2 | NMI | | system fatal error | ++------+------------+----------------+--------------------------+ +| 3 | Hard fault | | system fatal error | ++------+------------+----------------+--------------------------+ +| 4 | MemManage | MPU fault | system fatal error | ++------+------------+----------------+--------------------------+ +| 5 | Bus | | system fatal error | ++------+------------+----------------+--------------------------+ +| 6 | Usage | undefined | system fatal error | +| | fault | instruction, | | +| | | or switch | | +| | | attempt to ARM | | +| | | mode | | ++------+------------+----------------+--------------------------+ +| 11 | SVC | | system calls, kernel | +| | | | run-time exceptions, | +| | | | and IRQ offloading | ++------+------------+----------------+--------------------------+ +| 12 | Debug | | system fatal error | +| | monitor | | | ++------+------------+----------------+--------------------------+ +| 14 | PendSV | | context switch | ++------+------------+----------------+--------------------------+ +| 15 | SYSTICK | | system clock | ++------+------------+----------------+--------------------------+ + +Pin Mapping +=========== + +The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible +for pin muxing, input/output, pull-up, etc. + +All GPIO controller pins are exposed via the following sequence of pin numbers: + +- Pins 0 - 15 are for GPIO 0 +- Pins 16 - 31 are for GPIO 1 +- Pins 32 - 47 are for GPIO 2 +- Pins 48 - 51 are for GPIO 3 + +Mapping from the ARM MPS2 Board pins to GPIO controllers: + +.. rst-class:: rst-columns + + - D0 : EXT_0 + - D1 : EXT_4 + - D2 : EXT_2 + - D3 : EXT_3 + - D4 : EXT_1 + - D5 : EXT_6 + - D6 : EXT_7 + - D7 : EXT_8 + - D8 : EXT_9 + - D9 : EXT_10 + - D10 : EXT_12 + - D11 : EXT_13 + - D12 : EXT_14 + - D13 : EXT_11 + - D14 : EXT_15 + - D15 : EXT_5 + - D16 : EXT_16 + - D17 : EXT_17 + - D18 : EXT_18 + - D19 : EXT_19 + - D20 : EXT_20 + - D21 : EXT_21 + - D22 : EXT_22 + - D23 : EXT_23 + - D24 : EXT_24 + - D25 : EXT_25 + - D26 : EXT_26 + - D27 : EXT_30 + - D28 : EXT_28 + - D29 : EXT_29 + - D30 : EXT_27 + - D31 : EXT_32 + - D32 : EXT_33 + - D33 : EXT_34 + - D34 : EXT_35 + - D35 : EXT_36 + - D36 : EXT_38 + - D37 : EXT_39 + - D38 : EXT_40 + - D39 : EXT_44 + - D40 : EXT_41 + - D41 : EXT_31 + - D42 : EXT_37 + - D43 : EXT_42 + - D44 : EXT_43 + - D45 : EXT_45 + - D46 : EXT_46 + - D47 : EXT_47 + - D48 : EXT_48 + - D49 : EXT_49 + - D50 : EXT_50 + - D51 : EXT_51 + +Peripheral Mapping: + +.. rst-class:: rst-columns + + - UART_3_RX : D0 + - UART_3_TX : D1 + - SPI_3_CS : D10 + - SPI_3_MOSI : D11 + - SPI_3_MISO : D12 + - SPI_3_SCLK : D13 + - I2C_3_SDA : D14 + - I2C_3_SCL : D15 + - UART_4_RX : D26 + - UART_4_TX : D30 + - SPI_4_CS : D36 + - SPI_4_MOSI : D37 + - SPI_4_MISO : D38 + - SPI_4_SCK : D39 + - I2C_4_SDA : D40 + - I2C_4_SCL : D41 + +For more details please refer to `MPS2 Technical Reference Manual (TRM)`_. + +System Clock +============ + +The V2M MPS2 main clock is 24 MHz. + +Serial Port +=========== + +The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for +RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by +default, is utilizing UART0. + +Programming and Debugging +************************* + +Flashing +======== + +V2M MPS2 provides: + +- A USB connection to the host computer, which exposes a Mass Storage and an + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to V2M MPS2 +----------------------------------- + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps2/an385 + :goals: build + +Connect the V2M MPS2 to your host computer using the USB port and you should +see a USB connection which exposes a Mass Storage and a USB Serial Port. +Copy the generated zephyr.bin in the exposed drive. +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! arm + + +.. _V2M MPS2 Website: + https://developer.mbed.org/platforms/ARM-MPS2/ + +.. _MPS2 Technical Reference Manual (TRM): + http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf + +.. _Application Note AN385: + http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf diff --git a/boards/arm/mps2/doc/mps2_an521.rst b/boards/arm/mps2/doc/mps2_an521.rst new file mode 100644 index 00000000000000..7149902b0db238 --- /dev/null +++ b/boards/arm/mps2/doc/mps2_an521.rst @@ -0,0 +1,574 @@ +.. _mps2_an521_board: + +ARM MPS2+ AN521 +############### + +Overview +******** + +The mps2/an521 board configuration is used by Zephyr applications that run +on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33 +CPU and the following devices: + +- Nested Vectored Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) +- Cortex-M System Design Kit GPIO +- Cortex-M System Design Kit UART + +.. image:: img/mps2_an521.jpg + :align: center + :alt: ARM MPS2+ AN521 + +In addition to enabling actual hardware usage, this board configuration can +also use QEMU to emulate the AN521 platform running on the MPS2+. + +More information about the board can be found at the `MPS2 FPGA Website`_. + +.. note:: + This board configuration makes no claims about its suitability for use + with actual MPS2 hardware systems using AN521, or any other hardware + system. It has been tested on actual hardware, but its primary purpose is + for use with QEMU and unit tests for the ARM Cortex-M33. + + +Zephyr board options +==================== + +The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores +(CPU0 and CPU1). Zephyr provides support for building firmware +images for both CPU0 and CPU1. For CPU0 supporting ARM Security Extensions +both Secure and Non-Secure firmware images may be built. + +The BOARD options are summarized below: + ++----------------------+-------------------------------------------------------+ +| BOARD | Description | ++======================+=======================================================+ +| mps2/an521/cpu0 | For building Secure (or Secure-only) firmware on CPU0 | ++----------------------+-------------------------------------------------------+ +| mps2/an521/cpu0/ns | For building Non-Secure firmware for CPU0 | ++----------------------+-------------------------------------------------------+ +| mps2/an521/cpu1 | For building firmware on CPU1 | ++----------------------+-------------------------------------------------------+ + +Memory Partitioning +=================== + +The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory +regions are shared across both cores, and are aliased in both secure and +non-secure regions, where the secure memory alias has an offset of +0x10000000 relative to non-secure. + +The following memory map and partitioning schemes are used by default, where +the offset value is the offset from the base of the 4MB code or SRAM block, +ignoring the S/NS alias difference. + ++-------------------------+-----+----------------+----------------+------------+ +| Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias | ++=========================+=====+================+================+============+ +| mps2/an521/cpu0 | 0 | 4MB (0) | 4MB (0) | S | ++-------------------------+-----+----------------+----------------+------------+ +| mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS | ++-------------------------+-----+----------------+----------------+------------+ +| mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS | ++-------------------------+-----+----------------+----------------+------------+ + +The ``mps2/an521/cpu0/ns`` board target is intended to be used with TF-M, with the +Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M +boots the secure processing environment before initialising Zephyr in the +non-secure processing environment. The non-secure Zephyr image is offset to +make room for the secure bootloader, and the secure firmware (TF-M), resulting +in a starting address of 0x00100000. SRAM begins with a 1MB offset at +0x28100000. + +The ``mps2/an521/cpu1`` board target is setup for the second core on the +AN521, using the final 468KB code memory in the 4MB code block. This value +is chosen to maintain compatibility with TF-M, which marks that final 468KB +code region as ``Unused``. Code memory thus starts with an offset of +3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB +(address 0x28180000). + +This memory map enables the two alternative board targets to be used together +if required, at the cost of reducing the amount of code memory available on +the second core to the worst-case scenario from TF-M. + +When using one of the alternative board targets (``mps2/an521/cpu0/ns`` or +``mps2/an521/cpu1``), care needs to be taken with the amount of code or +SRAM memory used on the primary board target (``mps2/an521``) since there is +some overlap in the memory maps. + +Hardware +******** + +ARM MPS2+ AN521 provides the following hardware components: + +- Dual core ARM Cortex-M33 +- Soft Macro Model (SMM) implementation of SSE-200 subsystem +- Memory + + - 4MB of code memory (SSRAM1) + - 4MB of SRAM (SSRAM2 and SSRAM3) + - 16MB of parallel SRAM (PSRAM, non-secure only) + - 8KB of NVM code + +- Debug + + - P-JTAG, SWD & 16-bit TRACE + - UART port + +- Interface + + - AHB GPIO connected to the EXP port + - UART + - SPI + - I2C + - I2S + - Color LCD serial interface + - Ethernet + - VGA + +- On-board Peripherals + + - Color LCD + - 8 LEDs + - 8 Switches + - External SSRAM1, SSRAM2 & SSRAM3 + - SMSC9220 + - CS42L52 + + +User push buttons +================= + +The mps2/an521 board provides the following user push buttons: + +- ON power on +- nSRST: Cortex-M33 system reset and CoreSight debug reset +- USERPB0 and USERPB1: User defined buttons + + +Supported Features +=================== + +The mps2/an521 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TIMER | on-chip | timer | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. +See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware +features. + +The default configuration can be found in +:zephyr_file:`boards/arm/mps2/mps2_an521_cpu0_defconfig`. + +Interrupt Controller +==================== + +MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs. + +A Cortex-M33-based board uses vectored exceptions. This means each exception +calls a handler directly from the vector table. + +Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed +in the following table: + ++------+------------+----------------+--------------------------+ +| Exc# | Name | Remarks | Used by Zephyr Kernel | ++======+============+================+==========================+ +| 1 | Reset | | system initialization | ++------+------------+----------------+--------------------------+ +| 2 | NMI | | system fatal error | ++------+------------+----------------+--------------------------+ +| 3 | Hard fault | | system fatal error | ++------+------------+----------------+--------------------------+ +| 4 | MemManage | MPU fault | system fatal error | ++------+------------+----------------+--------------------------+ +| 5 | Bus | | system fatal error | ++------+------------+----------------+--------------------------+ +| 6 | Usage | Undefined | system fatal error | +| | fault | instruction, | | +| | | or switch | | +| | | attempt to ARM | | +| | | mode | | ++------+------------+----------------+--------------------------+ +| 7 | SecureFault| Unauthorized | system fatal error | +| | | access to | | +| | | secure region | | +| | | from ns space | | ++------+------------+----------------+--------------------------+ +| 8 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 9 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 10 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 11 | SVC | | system calls, kernel | +| | | | run-time exceptions, | +| | | | and IRQ offloading | ++------+------------+----------------+--------------------------+ +| 12 | Debug | | system fatal error | +| | monitor | | | ++------+------------+----------------+--------------------------+ +| 13 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 14 | PendSV | | context switch | ++------+------------+----------------+--------------------------+ +| 15 | SYSTICK | | system clock | ++------+------------+----------------+--------------------------+ +| 16 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 17 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ +| 18 | Reserved | | not handled | ++------+------------+----------------+--------------------------+ + +Pin Mapping +=========== + +The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16 +bits of IO. These controllers are responsible for pin-muxing, input/output, +pull-up, etc. + +All GPIO controller pins are exposed via the following sequence of pin numbers: + +- Pins 0 - 15 are for GPIO0 +- Pins 16 - 31 are for GPIO1 +- Pins 32 - 47 are for GPIO2 +- Pins 48 - 51 are for GPIO3 + +Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers: + +.. rst-class:: rst-columns + + - D0 : EXT_0 + - D1 : EXT_4 + - D2 : EXT_2 + - D3 : EXT_3 + - D4 : EXT_1 + - D5 : EXT_6 + - D6 : EXT_7 + - D7 : EXT_8 + - D8 : EXT_9 + - D9 : EXT_10 + - D10 : EXT_12 + - D11 : EXT_13 + - D12 : EXT_14 + - D13 : EXT_11 + - D14 : EXT_15 + - D15 : EXT_5 + - D16 : EXT_16 + - D17 : EXT_17 + - D18 : EXT_18 + - D19 : EXT_19 + - D20 : EXT_20 + - D21 : EXT_21 + - D22 : EXT_22 + - D23 : EXT_23 + - D24 : EXT_24 + - D25 : EXT_25 + - D26 : EXT_26 + - D27 : EXT_30 + - D28 : EXT_28 + - D29 : EXT_29 + - D30 : EXT_27 + - D31 : EXT_32 + - D32 : EXT_33 + - D33 : EXT_34 + - D34 : EXT_35 + - D35 : EXT_36 + - D36 : EXT_38 + - D37 : EXT_39 + - D38 : EXT_40 + - D39 : EXT_44 + - D40 : EXT_41 + - D41 : EXT_31 + - D42 : EXT_37 + - D43 : EXT_42 + - D44 : EXT_43 + - D45 : EXT_45 + - D46 : EXT_46 + - D47 : EXT_47 + - D48 : EXT_48 + - D49 : EXT_49 + - D50 : EXT_50 + - D51 : EXT_51 + +Peripheral Mapping: + +.. rst-class:: rst-columns + + - UART_3_RX : D0 + - UART_3_TX : D1 + - SPI_3_CS : D10 + - SPI_3_MOSI : D11 + - SPI_3_MISO : D12 + - SPI_3_SCLK : D13 + - I2C_3_SDA : D14 + - I2C_3_SCL : D15 + - UART_4_RX : D26 + - UART_4_TX : D30 + - SPI_4_CS : D36 + - SPI_4_MOSI : D37 + - SPI_4_MISO : D38 + - SPI_4_SCK : D39 + - I2C_4_SDA : D40 + - I2C_4_SCL : D41 + +For more details refer to `MPS2+ AN521 Technical Reference Manual (TRM)`_. + +LED +============ + +MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC). + +.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON. + +System Clock +============ + +MPS2+ AN521 has several clocks connected: + +.. rst-class:: rst-columns + + - MAINCLK : 20MHz + - SYSCLK : 20MHz + - S32KCLK : 32kHz + - TRACECLK : 20MHz + - SWCLKTCK : 20MHz + - TRACECLKIN : 20MHz + +Serial Port +=========== + +The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses +UART0, which is J10 on the board. + +UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define + secure and non-secure memory maps. By default, all of the memory space is + defined to be secure accessible only +- Secure and Non-secure peripherals via the Peripheral Protection Controller + (PPC). Peripherals can be assigned as secure or non-secure accessible +- Secure boot +- Secure `AMBA®`_ interconnect + +Serial Configuration Controller (SCC) +===================================== + +The MPS2+ AN521 implements a Serial Configuration Control (SCC) register. +The purpose of this register is to allow individual control of clocks, +reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and +switches. + +Programming and Debugging +************************* + +MPS2+ AN521 (CPU0) supports the Armv8m Security Extension. +Applications built for the mps2/an521 board by default +boot in the Secure state. + +MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure +firmware image. The Secure image can be built using either Zephyr +or `Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built +using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for the MPS2+ AN521 (CPU0) is built + using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2/an521/cpu0/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for MPS2+ AN521 (CPU0) + using ``-DBOARD=mps2/an521`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0) + using ``-DBOARD=mps2/an521/cpu0/ns``. +3. Merge the two binaries together. + +Building a Secure only application on MPS2+ AN521 (CPU0) +======================================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=mps2/an521`` for +the firmware running on the MPS2+ AN521 (CPU0). + +When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0), +the Secure application will have to set the SAU/IDAU configuration to allow +Non-Secure access to all CPU resources utilized by the Non-Secure application +firmware. SAU/IDAU configuration shall take place before jumping to the +Non-Secure application. + +The following system components are required to be properly configured during the +secure firmware: + +- AHB5 TrustZone Memory Protection Controller (MPC) +- AHB5 TrustZone Peripheral Protection Controller (PPC) +- Implementation-Defined Attribution Unit (IDAU) + +For more details refer to `Corelink SSE-200 Subsystem`_. + + + +Building standalone applications on MPS2+ AN521 CPU1 +==================================================== + +Applications may be built for the second Cortex-M33 +(remote) core of MPS2+ AN521. The core is referred to as CPU1. + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=mps2/an521/cpu1`` for +the firmware running on the MPS2+ AN521 (CPU1). + +The Zephyr build will automatically trigger building a minimal (empty) +secure-only firmware for CPU0, which will be used to boot the remote +core (CPU1). + + +Flashing +======== + +MPS2+ AN521 provides: + +- A USB connection to the host computer, which exposes a Mass Storage +- A Serial Port which is J10 on MPS2+ board + +Build applications as described above. +Here is an example for the :ref:`hello_world` application built as +a secure-only application for CPU0. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps2/an521 + :goals: build + + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps2_an521 + + +Uploading an application to MPS2+ AN521 +--------------------------------------- + +Applications can be in elf, hex or bin format. The binaries are flashed when +the board boots up, using files stored on the on-board Micro SD card. The +Motherboard Configuration Controller (MCC) is responsible for loading the FPGA +image and binaries. + +Connect the MPS2+ to your host computer using the USB port. You should see a +USB connection exposing a Mass Storage (``V2M_MPS2`` by default). + +The update requires 3 steps: + +1. Copy application files to ``/SOFTWARE/``. +2. Open ``/MB/HBI0263C/AN521/images.txt``. +3. Update the ``AN521/images.txt`` file as follows: + +.. code-block:: bash + + TITLE: Versatile Express Images Configuration File + + [IMAGES] + TOTALIMAGES: 1 ;Number of Images (Max: 32) + + IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program + + IMAGE0FILE: \SOFTWARE\zephyr.bin + + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps2_an521 + +.. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and multiple images scenario. + + +.. _MPS2 FPGA Website: + https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2 + +.. _MPS2+ AN521 Technical Reference Manual (TRM): + https://developer.arm.com/documentation/dai0521/latest/ + +.. _Cortex M33 Generic User Guide: + https://developer.arm.com/documentation/100235/latest/ + +.. _Trusted Firmware M: + https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html + +.. _Corelink SSE-200 Subsystem: + https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200 + +.. _IDAU: + https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU- + +.. _AMBA®: + https://developer.arm.com/products/architecture/system-architectures/amba diff --git a/boards/arm/mps2_an521/empty_cpu0/CMakeLists.txt b/boards/arm/mps2/empty_cpu0/CMakeLists.txt similarity index 100% rename from boards/arm/mps2_an521/empty_cpu0/CMakeLists.txt rename to boards/arm/mps2/empty_cpu0/CMakeLists.txt diff --git a/boards/arm/mps2_an521/empty_cpu0/prj.conf b/boards/arm/mps2/empty_cpu0/prj.conf similarity index 100% rename from boards/arm/mps2_an521/empty_cpu0/prj.conf rename to boards/arm/mps2/empty_cpu0/prj.conf diff --git a/boards/arm/mps2_an521/empty_cpu0/src/main.c b/boards/arm/mps2/empty_cpu0/src/main.c similarity index 100% rename from boards/arm/mps2_an521/empty_cpu0/src/main.c rename to boards/arm/mps2/empty_cpu0/src/main.c diff --git a/boards/arm/mps2_an385/mps2_an385.dts b/boards/arm/mps2/mps2_an385.dts similarity index 100% rename from boards/arm/mps2_an385/mps2_an385.dts rename to boards/arm/mps2/mps2_an385.dts diff --git a/boards/arm/mps2_an385/mps2_an385.yaml b/boards/arm/mps2/mps2_an385.yaml similarity index 89% rename from boards/arm/mps2_an385/mps2_an385.yaml rename to boards/arm/mps2/mps2_an385.yaml index 0236f2a137d2bc..7ad92b98996e33 100644 --- a/boards/arm/mps2_an385/mps2_an385.yaml +++ b/boards/arm/mps2/mps2_an385.yaml @@ -1,4 +1,4 @@ -identifier: mps2_an385 +identifier: mps2/an385 name: ARM V2M MPS2 type: mcu arch: arm diff --git a/boards/arm/mps2_an385/mps2_an385_defconfig b/boards/arm/mps2/mps2_an385_defconfig similarity index 75% rename from boards/arm/mps2_an385/mps2_an385_defconfig rename to boards/arm/mps2/mps2_an385_defconfig index a32334189532d9..1d55b8fe94919f 100644 --- a/boards/arm/mps2_an385/mps2_an385_defconfig +++ b/boards/arm/mps2/mps2_an385_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN385=y -CONFIG_BOARD_MPS2_AN385=y CONFIG_RUNTIME_NMI=y CONFIG_QEMU_ICOUNT_SHIFT=7 diff --git a/boards/arm/mps2_an521/mps2_an521-common.dtsi b/boards/arm/mps2/mps2_an521-common.dtsi similarity index 100% rename from boards/arm/mps2_an521/mps2_an521-common.dtsi rename to boards/arm/mps2/mps2_an521-common.dtsi diff --git a/boards/arm/mps2_an521/mps2_an521.dts b/boards/arm/mps2/mps2_an521_cpu0.dts similarity index 100% rename from boards/arm/mps2_an521/mps2_an521.dts rename to boards/arm/mps2/mps2_an521_cpu0.dts diff --git a/boards/arm/mps2/mps2_an521_cpu0.yaml b/boards/arm/mps2/mps2_an521_cpu0.yaml new file mode 100644 index 00000000000000..e5247a292e5aa1 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0.yaml @@ -0,0 +1,21 @@ +identifier: mps2/an521/cpu0 +name: ARM V2M MPS2-AN521 +type: mcu +arch: arm +ram: 4096 +flash: 4096 +simulation: qemu +toolchain: + - gnuarmemb + - zephyr + - xtools +supported: + - gpio +testing: + default: true + ignore_tags: + - drivers + - bluetooth + - net + - timer +vendor: arm diff --git a/boards/arm/mps2/mps2_an521_cpu0_defconfig b/boards/arm/mps2/mps2_an521_cpu0_defconfig new file mode 100644 index 00000000000000..413c8cdc5c3acd --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0_defconfig @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018-2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=7 + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +# Build a Secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps2_an521/mps2_an521_ns.dts b/boards/arm/mps2/mps2_an521_cpu0_ns.dts similarity index 100% rename from boards/arm/mps2_an521/mps2_an521_ns.dts rename to boards/arm/mps2/mps2_an521_cpu0_ns.dts diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml new file mode 100644 index 00000000000000..b5dcadf7fe94e2 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml @@ -0,0 +1,19 @@ +identifier: mps2/an521/cpu0/ns +name: ARM V2M MPS2-AN521_ns +type: mcu +arch: arm +ram: 512 +flash: 512 +simulation: qemu +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - arm + - kernel + - tfm + - userspace + - trusted-firmware-m diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig b/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig new file mode 100644 index 00000000000000..7c02187aaef6a8 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu0_ns_defconfig @@ -0,0 +1,11 @@ +# +# Copyright (c) 2018-2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_QEMU_ICOUNT_SHIFT=6 + +# Build a non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps2_an521/mps2_an521_remote.dts b/boards/arm/mps2/mps2_an521_cpu1.dts similarity index 100% rename from boards/arm/mps2_an521/mps2_an521_remote.dts rename to boards/arm/mps2/mps2_an521_cpu1.dts diff --git a/boards/arm/mps2/mps2_an521_cpu1.yaml b/boards/arm/mps2/mps2_an521_cpu1.yaml new file mode 100644 index 00000000000000..29bd722157b406 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu1.yaml @@ -0,0 +1,16 @@ +identifier: mps2/an521/cpu1 +name: ARM V2M MPS2-AN521_cpu1 +type: mcu +arch: arm +ram: 512 +flash: 468 +simulation: qemu +toolchain: + - gnuarmemb + - zephyr + - xtools +testing: + default: true + only_tags: + - arm + - fpu diff --git a/boards/arm/mps2/mps2_an521_cpu1_defconfig b/boards/arm/mps2/mps2_an521_cpu1_defconfig new file mode 100644 index 00000000000000..0c8740a2fb9923 --- /dev/null +++ b/boards/arm/mps2/mps2_an521_cpu1_defconfig @@ -0,0 +1,18 @@ +# +# Copyright (c) 2018-2019 Linaro Limited +# Copyright (c) 2021 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RUNTIME_NMI=y +CONFIG_ARM_MPU=y +CONFIG_QEMU_ICOUNT_SHIFT=7 + +# GPIOs +CONFIG_GPIO=y + +# Serial +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/mps2_an385/pinmux.c b/boards/arm/mps2/pinmux.c similarity index 100% rename from boards/arm/mps2_an385/pinmux.c rename to boards/arm/mps2/pinmux.c diff --git a/boards/arm/mps2_an385/CMakeLists.txt b/boards/arm/mps2_an385/CMakeLists.txt deleted file mode 100644 index 9bc25bae4c64e6..00000000000000 --- a/boards/arm/mps2_an385/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(pinmux.c) diff --git a/boards/arm/mps2_an385/Kconfig.board b/boards/arm/mps2_an385/Kconfig.board deleted file mode 100644 index f2f9be26f503eb..00000000000000 --- a/boards/arm/mps2_an385/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPS2_AN385 - bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)" - depends on SOC_MPS2_AN385 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT diff --git a/boards/arm/mps2_an385/Kconfig.defconfig b/boards/arm/mps2_an385/Kconfig.defconfig deleted file mode 100644 index 114e5d6dbf3c95..00000000000000 --- a/boards/arm/mps2_an385/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MPS2_AN385 - -config BOARD - default "mps2_an385" - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -config ZTEST_STACK_SIZE - default 4096 if ZTEST - -if COVERAGE_GCOV - -config MAIN_STACK_SIZE - default 4096 - -config IDLE_STACK_SIZE - default 4096 - -config PRIVILEGED_STACK_SIZE - default 4096 - -config ISR_STACK_SIZE - default 4096 - -config TEST_EXTRA_STACK_SIZE - default 4096 - -endif # COVERAGE_GCOV - -endif diff --git a/boards/arm/mps2_an385/board.cmake b/boards/arm/mps2_an385/board.cmake deleted file mode 100644 index 1f2d4957d66c49..00000000000000 --- a/boards/arm/mps2_an385/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} cortex-m3) -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -machine mps2-an385 - -nographic - -vga none - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/mps2_an385/doc/index.rst b/boards/arm/mps2_an385/doc/index.rst deleted file mode 100644 index ac27e70e593819..00000000000000 --- a/boards/arm/mps2_an385/doc/index.rst +++ /dev/null @@ -1,284 +0,0 @@ -.. _mps2_an385_board: - -ARM V2M MPS2 -############ - -Overview -******** - -The mps2_an385 board configuration is used by Zephyr applications that run on -the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and -the following devices: - -- Nested Vectored Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) -- Cortex-M System Design Kit UART - -.. image:: img/mps2_an385.jpg - :align: center - :alt: ARM V2M MPS2 - -In addition to enabling actual hardware usage, this board configuration can -also use QEMU to emulate the AN385 platform running on the MPS2+. - -More information about the board can be found at the `V2M MPS2 Website`_. - -The Application Note AN385 can be found at `Application Note AN385`_. - -.. note:: - This board configuration makes no claims about its suitability for use - with actual MPS2 hardware systems using AN385, or any other hardware - system. It has been tested on actual hardware, but its primary purpose is - for use with QEMU and unit tests. - -Hardware -******** - -ARM V2M MPS2 provides the following hardware components: - -- ARM Cortex-M3 (AN385) -- ARM IoT Subsystem for Cortex-M -- Form factor: 140x120cm -- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM -- Video: QSVGA touch screen panel, 4bit RGB VGA connector -- Audio: Audio Codec -- Debug: - - - ARM JTAG20 connector - - ARM parallel trace connector (MICTOR38) - - 20 pin Cortex debug connector - - 10 pin Cortex debug connector - - ILA connector for FPGA debug - -- Expansion - - - GPIO - - SPI - -.. note:: - 4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM - (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available. - -Supported Features -================== - -The mps2_an385 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ -| DUALTIMER | on-chip | counter | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware -features. - -The default configuration can be found in the defconfig file: - -.. code-block:: console - - boards/arm/mps2_an385/mps2_an385_defconfig - -Interrupt Controller -==================== - -MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs. - -A Cortex-M3/4-based board uses vectored exceptions. This means each exception -calls a handler directly from the vector table. - -Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here -identifies the handlers used for each exception. - -+------+------------+----------------+--------------------------+ -| Exc# | Name | Remarks | Used by Zephyr Kernel | -+======+============+================+==========================+ -| 1 | Reset | | system initialization | -+------+------------+----------------+--------------------------+ -| 2 | NMI | | system fatal error | -+------+------------+----------------+--------------------------+ -| 3 | Hard fault | | system fatal error | -+------+------------+----------------+--------------------------+ -| 4 | MemManage | MPU fault | system fatal error | -+------+------------+----------------+--------------------------+ -| 5 | Bus | | system fatal error | -+------+------------+----------------+--------------------------+ -| 6 | Usage | undefined | system fatal error | -| | fault | instruction, | | -| | | or switch | | -| | | attempt to ARM | | -| | | mode | | -+------+------------+----------------+--------------------------+ -| 11 | SVC | | system calls, kernel | -| | | | run-time exceptions, | -| | | | and IRQ offloading | -+------+------------+----------------+--------------------------+ -| 12 | Debug | | system fatal error | -| | monitor | | | -+------+------------+----------------+--------------------------+ -| 14 | PendSV | | context switch | -+------+------------+----------------+--------------------------+ -| 15 | SYSTICK | | system clock | -+------+------------+----------------+--------------------------+ - -Pin Mapping -=========== - -The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible -for pin muxing, input/output, pull-up, etc. - -All GPIO controller pins are exposed via the following sequence of pin numbers: - -- Pins 0 - 15 are for GPIO 0 -- Pins 16 - 31 are for GPIO 1 -- Pins 32 - 47 are for GPIO 2 -- Pins 48 - 51 are for GPIO 3 - -Mapping from the ARM MPS2 Board pins to GPIO controllers: - -.. rst-class:: rst-columns - - - D0 : EXT_0 - - D1 : EXT_4 - - D2 : EXT_2 - - D3 : EXT_3 - - D4 : EXT_1 - - D5 : EXT_6 - - D6 : EXT_7 - - D7 : EXT_8 - - D8 : EXT_9 - - D9 : EXT_10 - - D10 : EXT_12 - - D11 : EXT_13 - - D12 : EXT_14 - - D13 : EXT_11 - - D14 : EXT_15 - - D15 : EXT_5 - - D16 : EXT_16 - - D17 : EXT_17 - - D18 : EXT_18 - - D19 : EXT_19 - - D20 : EXT_20 - - D21 : EXT_21 - - D22 : EXT_22 - - D23 : EXT_23 - - D24 : EXT_24 - - D25 : EXT_25 - - D26 : EXT_26 - - D27 : EXT_30 - - D28 : EXT_28 - - D29 : EXT_29 - - D30 : EXT_27 - - D31 : EXT_32 - - D32 : EXT_33 - - D33 : EXT_34 - - D34 : EXT_35 - - D35 : EXT_36 - - D36 : EXT_38 - - D37 : EXT_39 - - D38 : EXT_40 - - D39 : EXT_44 - - D40 : EXT_41 - - D41 : EXT_31 - - D42 : EXT_37 - - D43 : EXT_42 - - D44 : EXT_43 - - D45 : EXT_45 - - D46 : EXT_46 - - D47 : EXT_47 - - D48 : EXT_48 - - D49 : EXT_49 - - D50 : EXT_50 - - D51 : EXT_51 - -Peripheral Mapping: - -.. rst-class:: rst-columns - - - UART_3_RX : D0 - - UART_3_TX : D1 - - SPI_3_CS : D10 - - SPI_3_MOSI : D11 - - SPI_3_MISO : D12 - - SPI_3_SCLK : D13 - - I2C_3_SDA : D14 - - I2C_3_SCL : D15 - - UART_4_RX : D26 - - UART_4_TX : D30 - - SPI_4_CS : D36 - - SPI_4_MOSI : D37 - - SPI_4_MISO : D38 - - SPI_4_SCK : D39 - - I2C_4_SDA : D40 - - I2C_4_SCL : D41 - -For more details please refer to `MPS2 Technical Reference Manual (TRM)`_. - -System Clock -============ - -The V2M MPS2 main clock is 24 MHz. - -Serial Port -=========== - -The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for -RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by -default, is utilizing UART0. - -Programming and Debugging -************************* - -Flashing -======== - -V2M MPS2 provides: - -- A USB connection to the host computer, which exposes a Mass Storage and an - USB Serial Port. -- A Serial Flash device, which implements the USB flash disk file storage. -- A physical UART connection which is relayed over interface USB Serial port. - -Flashing an application to V2M MPS2 ------------------------------------ - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mps2_an385 - :goals: build - -Connect the V2M MPS2 to your host computer using the USB port and you should -see a USB connection which exposes a Mass Storage and a USB Serial Port. -Copy the generated zephyr.bin in the exposed drive. -Reset the board and you should be able to see on the corresponding Serial Port -the following message: - -.. code-block:: console - - Hello World! arm - - -.. _V2M MPS2 Website: - https://developer.mbed.org/platforms/ARM-MPS2/ - -.. _MPS2 Technical Reference Manual (TRM): - http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf - -.. _Application Note AN385: - http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf diff --git a/boards/arm/mps2_an521/CMakeLists.txt b/boards/arm/mps2_an521/CMakeLists.txt deleted file mode 100644 index 7f6917842743ba..00000000000000 --- a/boards/arm/mps2_an521/CMakeLists.txt +++ /dev/null @@ -1,29 +0,0 @@ -# -# Copyright (c) 2019,2020 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -zephyr_library_sources(pinmux.c) - -if(CONFIG_SOC_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP) -# Building a firmware image for CPU1: this requires a binary -# for CPU0, which will boot the device and wake up CPU1. -# However, if building with OPENAMP, there is no need to build -# any binary for CPU0, as this is built by the dual core sample. - - set(CPU0_BINARY_DIR ${BOARD_DIR}/empty_cpu0-prefix/src/empty-cpu0-build/zephyr) - - include(ExternalProject) - - ExternalProject_Add( - empty_cpu0 - SOURCE_DIR ${BOARD_DIR}/empty_cpu0 - INSTALL_COMMAND "" - CMAKE_CACHE_ARGS -DBOARD:STRING=mps2_an521 - BUILD_BYPRODUCTS "${CPU0_BINARY_DIR}/${KERNEL_BIN_NAME}" - BUILD_ALWAYS True - ) - -endif() diff --git a/boards/arm/mps2_an521/Kconfig.board b/boards/arm/mps2_an521/Kconfig.board deleted file mode 100644 index 6fff4bd21f502d..00000000000000 --- a/boards/arm/mps2_an521/Kconfig.board +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2018-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPS2_AN521_CPU0 - bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0)" - depends on SOC_MPS2_AN521_CPU0 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - -config BOARD_MPS2_AN521_CPU0_NS - bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) (CPU0 Non-Secure)" - depends on SOC_MPS2_AN521_CPU0 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - -config BOARD_MPS2_AN521_CPU1 - bool "ARM Cortex-M33 SMM on V2M-MPS2 (AN521) CPU1" - depends on SOC_MPS2_AN521_CPU1 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT diff --git a/boards/arm/mps2_an521/Kconfig.defconfig b/boards/arm/mps2_an521/Kconfig.defconfig deleted file mode 100644 index ff999de184178d..00000000000000 --- a/boards/arm/mps2_an521/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2018-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1 - -# MPU-based null-pointer dereferencing detection cannot -# be applied as the (0x0 - 0x400) is unmapped but QEMU -# will still permit bus access. -choice NULL_POINTER_EXCEPTION_DETECTION - bool - default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET -endchoice - -config BOARD - default "mps2_an521_ns" if TRUSTED_EXECUTION_NONSECURE - default "mps2_an521_remote" if BOARD_MPS2_AN521_CPU1 - default "mps2_an521" - -# By default, if we build for a Non-Secure version of the board, -# force building with TF-M as the Secure Execution Environment. -config BUILD_WITH_TFM - default y if TRUSTED_EXECUTION_NONSECURE - - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -endif diff --git a/boards/arm/mps2_an521/board.cmake b/boards/arm/mps2_an521/board.cmake deleted file mode 100644 index 51e09ba282d638..00000000000000 --- a/boards/arm/mps2_an521/board.cmake +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} cortex-m33) -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -machine mps2-an521 - -nographic - -m 16 - -vga none - ) -board_set_debugger_ifnset(qemu) - -board_runner_args(pyocd "--target=mps2_an521") - -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) - # To enable a host tty switch between serial and pty - # -chardev serial,path=/dev/ttyS0,id=hostS0 -list(APPEND QEMU_EXTRA_FLAGS -chardev pty,id=hostS0 -serial chardev:hostS0) - -if (CONFIG_BUILD_WITH_TFM) - # Override the binary used by qemu, to use the combined - # TF-M (Secure) & Zephyr (Non Secure) image (when running - # in-tree tests). - set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex") -elseif(CONFIG_OPENAMP) - set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf") -elseif (CONFIG_SOC_MPS2_AN521_CPU1) - set(CPU0_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/zephyr/boards/arm/mps2_an521/empty_cpu0-prefix/src/empty_cpu0-build/zephyr) - set(QEMU_KERNEL_OPTION "-device;loader,file=${CPU0_BINARY_DIR}/zephyr.elf") - list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}") -endif() diff --git a/boards/arm/mps2_an521/doc/index.rst b/boards/arm/mps2_an521/doc/index.rst deleted file mode 100644 index e8789e72e18d50..00000000000000 --- a/boards/arm/mps2_an521/doc/index.rst +++ /dev/null @@ -1,574 +0,0 @@ -.. _mps2_an521_board: - -ARM MPS2+ AN521 -############### - -Overview -******** - -The mps2_an521 board configuration is used by Zephyr applications that run -on the MPS2+ AN521 board. It provides support for the MPS2+ AN521 ARM Cortex-M33 -CPU and the following devices: - -- Nested Vectored Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) -- Cortex-M System Design Kit GPIO -- Cortex-M System Design Kit UART - -.. image:: img/mps2_an521.jpg - :align: center - :alt: ARM MPS2+ AN521 - -In addition to enabling actual hardware usage, this board configuration can -also use QEMU to emulate the AN521 platform running on the MPS2+. - -More information about the board can be found at the `MPS2 FPGA Website`_. - -.. note:: - This board configuration makes no claims about its suitability for use - with actual MPS2 hardware systems using AN521, or any other hardware - system. It has been tested on actual hardware, but its primary purpose is - for use with QEMU and unit tests for the ARM Cortex-M33. - - -Zephyr board options -==================== - -The MPS2+ AN521 is a dual core SoC with Cortex-M33 architecture on both cores -(CPU0 and CPU1). Zephyr provides support for building firmware -images for both CPU0 and CPU1. For CPU0 supporting ARM Security Extensions -both Secure and Non-Secure firmware images may be built. - -The BOARD options are summarized below: - -+----------------------+-------------------------------------------------------+ -| BOARD | Description | -+======================+=======================================================+ -| mps2_an521 | For building Secure (or Secure-only) firmware on CPU0 | -+----------------------+-------------------------------------------------------+ -| mps2_an521_ns | For building Non-Secure firmware for CPU0 | -+----------------------+-------------------------------------------------------+ -| mps2_an521_remote | For building firmware on CPU1 | -+----------------------+-------------------------------------------------------+ - -Memory Partitioning -=================== - -The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory -regions are shared across both cores, and are aliased in both secure and -non-secure regions, where the secure memory alias has an offset of -0x10000000 relative to non-secure. - -The following memory map and partitioning schemes are used by default, where -the offset value is the offset from the base of the 4MB code or SRAM block, -ignoring the S/NS alias difference. - -+-------------------+-----+----------------+----------------+------------+ -| Board | CPU | Code (Offset) | SRAM (Offset) | S/NS Alias | -+===================+=====+================+================+============+ -| mps2_an521 | 0 | 4MB (0) | 4MB (0) | S | -+-------------------+-----+----------------+----------------+------------+ -| mps2_an521_ns | 0 | 512KB (1MB) | 512KB (1MB) | NS | -+-------------------+-----+----------------+----------------+------------+ -| mps2_an521_remote | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS | -+-------------------+-----+----------------+----------------+------------+ - -The ``mps2_an521_ns`` board target is intended to be used with TF-M, with the -Zephyr memory map matching the AN521 memory map defined upstream in TF-M. TF-M -boots the secure processing environment before initialising Zephyr in the -non-secure processing environment. The non-secure Zephyr image is offset to -make room for the secure bootloader, and the secure firmware (TF-M), resulting -in a starting address of 0x00100000. SRAM begins with a 1MB offset at -0x28100000. - -The ``mps2_an521_remote`` board target is setup for the second core on the -AN521, using the final 468KB code memory in the 4MB code block. This value -is chosen to maintain compatibility with TF-M, which marks that final 468KB -code region as ``Unused``. Code memory thus starts with an offset of -3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB -(address 0x28180000). - -This memory map enables the two alternative board targets to be used together -if required, at the cost of reducing the amount of code memory available on -the second core to the worst-case scenario from TF-M. - -When using one of the alternative board targets (``mps2_an521_ns`` or -``mps2_an521_remote``), care needs to be taken with the amount of code or -SRAM memory used on the primary board target (``mps2_an521``) since there is -some overlap in the memory maps. - -Hardware -******** - -ARM MPS2+ AN521 provides the following hardware components: - -- Dual core ARM Cortex-M33 -- Soft Macro Model (SMM) implementation of SSE-200 subsystem -- Memory - - - 4MB of code memory (SSRAM1) - - 4MB of SRAM (SSRAM2 and SSRAM3) - - 16MB of parallel SRAM (PSRAM, non-secure only) - - 8KB of NVM code - -- Debug - - - P-JTAG, SWD & 16-bit TRACE - - UART port - -- Interface - - - AHB GPIO connected to the EXP port - - UART - - SPI - - I2C - - I2S - - Color LCD serial interface - - Ethernet - - VGA - -- On-board Peripherals - - - Color LCD - - 8 LEDs - - 8 Switches - - External SSRAM1, SSRAM2 & SSRAM3 - - SMSC9220 - - CS42L52 - - -User push buttons -================= - -The mps2_an521 board provides the following user push buttons: - -- ON power on -- nSRST: Cortex-M33 system reset and CoreSight debug reset -- USERPB0 and USERPB1: User defined buttons - - -Supported Features -=================== - -The mps2_an521 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| TIMER | on-chip | timer | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `MPS2 FPGA Website`_ for a complete list of MPS2+ AN521 board hardware -features. - -The default configuration can be found in the defconfig file: -``boards/arm/mps2_an521/mps2_an521_defconfig``. - -Interrupt Controller -==================== - -MPS2+ AN521 is a Cortex-M33 based SoC and has 15 fixed exceptions and 77 IRQs. - -A Cortex-M33-based board uses vectored exceptions. This means each exception -calls a handler directly from the vector table. - -Zephyr provides handlers for exceptions 1-7, 11, 12, 14, and 15, as listed -in the following table: - -+------+------------+----------------+--------------------------+ -| Exc# | Name | Remarks | Used by Zephyr Kernel | -+======+============+================+==========================+ -| 1 | Reset | | system initialization | -+------+------------+----------------+--------------------------+ -| 2 | NMI | | system fatal error | -+------+------------+----------------+--------------------------+ -| 3 | Hard fault | | system fatal error | -+------+------------+----------------+--------------------------+ -| 4 | MemManage | MPU fault | system fatal error | -+------+------------+----------------+--------------------------+ -| 5 | Bus | | system fatal error | -+------+------------+----------------+--------------------------+ -| 6 | Usage | Undefined | system fatal error | -| | fault | instruction, | | -| | | or switch | | -| | | attempt to ARM | | -| | | mode | | -+------+------------+----------------+--------------------------+ -| 7 | SecureFault| Unauthorized | system fatal error | -| | | access to | | -| | | secure region | | -| | | from ns space | | -+------+------------+----------------+--------------------------+ -| 8 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 9 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 10 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 11 | SVC | | system calls, kernel | -| | | | run-time exceptions, | -| | | | and IRQ offloading | -+------+------------+----------------+--------------------------+ -| 12 | Debug | | system fatal error | -| | monitor | | | -+------+------------+----------------+--------------------------+ -| 13 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 14 | PendSV | | context switch | -+------+------------+----------------+--------------------------+ -| 15 | SYSTICK | | system clock | -+------+------------+----------------+--------------------------+ -| 16 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 17 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ -| 18 | Reserved | | not handled | -+------+------------+----------------+--------------------------+ - -Pin Mapping -=========== - -The ARM MPS2+ AN521 Board has 4 CMSDK AHB GPIO controllers. Each providing 16 -bits of IO. These controllers are responsible for pin-muxing, input/output, -pull-up, etc. - -All GPIO controller pins are exposed via the following sequence of pin numbers: - -- Pins 0 - 15 are for GPIO0 -- Pins 16 - 31 are for GPIO1 -- Pins 32 - 47 are for GPIO2 -- Pins 48 - 51 are for GPIO3 - -Mapping from the ARM MPS2+ AN521 Board pins to GPIO controllers: - -.. rst-class:: rst-columns - - - D0 : EXT_0 - - D1 : EXT_4 - - D2 : EXT_2 - - D3 : EXT_3 - - D4 : EXT_1 - - D5 : EXT_6 - - D6 : EXT_7 - - D7 : EXT_8 - - D8 : EXT_9 - - D9 : EXT_10 - - D10 : EXT_12 - - D11 : EXT_13 - - D12 : EXT_14 - - D13 : EXT_11 - - D14 : EXT_15 - - D15 : EXT_5 - - D16 : EXT_16 - - D17 : EXT_17 - - D18 : EXT_18 - - D19 : EXT_19 - - D20 : EXT_20 - - D21 : EXT_21 - - D22 : EXT_22 - - D23 : EXT_23 - - D24 : EXT_24 - - D25 : EXT_25 - - D26 : EXT_26 - - D27 : EXT_30 - - D28 : EXT_28 - - D29 : EXT_29 - - D30 : EXT_27 - - D31 : EXT_32 - - D32 : EXT_33 - - D33 : EXT_34 - - D34 : EXT_35 - - D35 : EXT_36 - - D36 : EXT_38 - - D37 : EXT_39 - - D38 : EXT_40 - - D39 : EXT_44 - - D40 : EXT_41 - - D41 : EXT_31 - - D42 : EXT_37 - - D43 : EXT_42 - - D44 : EXT_43 - - D45 : EXT_45 - - D46 : EXT_46 - - D47 : EXT_47 - - D48 : EXT_48 - - D49 : EXT_49 - - D50 : EXT_50 - - D51 : EXT_51 - -Peripheral Mapping: - -.. rst-class:: rst-columns - - - UART_3_RX : D0 - - UART_3_TX : D1 - - SPI_3_CS : D10 - - SPI_3_MOSI : D11 - - SPI_3_MISO : D12 - - SPI_3_SCLK : D13 - - I2C_3_SDA : D14 - - I2C_3_SCL : D15 - - UART_4_RX : D26 - - UART_4_TX : D30 - - SPI_4_CS : D36 - - SPI_4_MOSI : D37 - - SPI_4_MISO : D38 - - SPI_4_SCK : D39 - - I2C_4_SDA : D40 - - I2C_4_SCL : D41 - -For more details refer to `MPS2+ AN521 Technical Reference Manual (TRM)`_. - -LED -============ - -MPS2+ has 8 built-in LEDs connected to Serial Configuration Controller (SCC). - -.. note:: The SCC register CFG_REG1 Bits [7:0] for LEDa, 0 = OFF 1 = ON. - -System Clock -============ - -MPS2+ AN521 has several clocks connected: - -.. rst-class:: rst-columns - - - MAINCLK : 20MHz - - SYSCLK : 20MHz - - S32KCLK : 32kHz - - TRACECLK : 20MHz - - SWCLKTCK : 20MHz - - TRACECLKIN : 20MHz - -Serial Port -=========== - -The MPS2+ AN521 has five UARTs. The Zephyr console output by default, uses -UART0, which is J10 on the board. - -UART2 is reserved. And UART 1, 3 and 4 are alt-functions on the EXP ports. - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is used to define - secure and non-secure memory maps. By default, all of the memory space is - defined to be secure accessible only -- Secure and Non-secure peripherals via the Peripheral Protection Controller - (PPC). Peripherals can be assigned as secure or non-secure accessible -- Secure boot -- Secure `AMBA®`_ interconnect - -Serial Configuration Controller (SCC) -===================================== - -The MPS2+ AN521 implements a Serial Configuration Control (SCC) register. -The purpose of this register is to allow individual control of clocks, -reset-signals and interrupts to peripherals, and pin-muxing, and the LEDs and -switches. - -Programming and Debugging -************************* - -MPS2+ AN521 (CPU0) supports the Armv8m Security Extension. -Applications built for the mps2_an521 board by default -boot in the Secure state. - -MPS2+ AN521 (CPU1) does not support the Armv8m Security Extension. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the MPS2+ AN521 (CPU0) may contain a Secure and a Non-Secure -firmware image. The Secure image can be built using either Zephyr -or `Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built -using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for the MPS2+ AN521 (CPU0) is built - using TF-M. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following steps: - -1. Build the Non-Secure Zephyr application - for MPS2+ AN521 (CPU0) using ``-DBOARD=mps2_an521_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output image binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process to build the Secure and the Non-Secure firmware images -using Zephyr requires the following steps: - -1. Build the Secure Zephyr application for MPS2+ AN521 (CPU0) - using ``-DBOARD=mps2_an521`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` - in the application project configuration file. -2. Build the Non-Secure Zephyr application for MPS2+ AN521 (CPU0) - using ``-DBOARD=mps2_an521_ns``. -3. Merge the two binaries together. - -Building a Secure only application on MPS2+ AN521 (CPU0) -======================================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=mps2_an521`` for -the firmware running on the MPS2+ AN521 (CPU0). - -When building a Secure/Non-Secure application for the MPS2+ AN521 (CPU0), -the Secure application will have to set the SAU/IDAU configuration to allow -Non-Secure access to all CPU resources utilized by the Non-Secure application -firmware. SAU/IDAU configuration shall take place before jumping to the -Non-Secure application. - -The following system components are required to be properly configured during the -secure firmware: - -- AHB5 TrustZone Memory Protection Controller (MPC) -- AHB5 TrustZone Peripheral Protection Controller (PPC) -- Implementation-Defined Attribution Unit (IDAU) - -For more details refer to `Corelink SSE-200 Subsystem`_. - - - -Building standalone applications on MPS2+ AN521 CPU1 -==================================================== - -Applications may be built for the second Cortex-M33 -(remote) core of MPS2+ AN521. The core is referred to as CPU1. - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=mps2_an521_remote`` for -the firmware running on the MPS2+ AN521 (CPU1). - -The Zephyr build will automatically trigger building a minimal (empty) -secure-only firmware for CPU0, which will be used to boot the remote -core (CPU1). - - -Flashing -======== - -MPS2+ AN521 provides: - -- A USB connection to the host computer, which exposes a Mass Storage -- A Serial Port which is J10 on MPS2+ board - -Build applications as described above. -Here is an example for the :ref:`hello_world` application built as -a secure-only application for CPU0. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mps2_an521 - :goals: build - - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps2_an521 - - -Uploading an application to MPS2+ AN521 ---------------------------------------- - -Applications can be in elf, hex or bin format. The binaries are flashed when -the board boots up, using files stored on the on-board Micro SD card. The -Motherboard Configuration Controller (MCC) is responsible for loading the FPGA -image and binaries. - -Connect the MPS2+ to your host computer using the USB port. You should see a -USB connection exposing a Mass Storage (``V2M_MPS2`` by default). - -The update requires 3 steps: - -1. Copy application files to ``/SOFTWARE/``. -2. Open ``/MB/HBI0263C/AN521/images.txt``. -3. Update the ``AN521/images.txt`` file as follows: - -.. code-block:: bash - - TITLE: Versatile Express Images Configuration File - - [IMAGES] - TOTALIMAGES: 1 ;Number of Images (Max: 32) - - IMAGE0ADDRESS: 0x10000000 ;Please select the required executable program - - IMAGE0FILE: \SOFTWARE\zephyr.bin - - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps2_an521 - -.. note:: Refer to the tfm_integration sample for more details about integrating with TF-M and multiple images scenario. - - -.. _MPS2 FPGA Website: - https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps2 - -.. _MPS2+ AN521 Technical Reference Manual (TRM): - https://developer.arm.com/documentation/dai0521/latest/ - -.. _Cortex M33 Generic User Guide: - https://developer.arm.com/documentation/100235/latest/ - -.. _Trusted Firmware M: - https://tf-m-user-guide.trustedfirmware.org/building/tfm_build_instruction.html - -.. _Corelink SSE-200 Subsystem: - https://developer.arm.com/documentation/dto0051/latest/subsystem-overview/about-the-sse-200 - -.. _IDAU: - https://developer.arm.com/documentation/100690/latest/Attribution-units--SAU-and-IDAU- - -.. _AMBA®: - https://developer.arm.com/products/architecture/system-architectures/amba diff --git a/boards/arm/mps2_an521/mps2_an521.yaml b/boards/arm/mps2_an521/mps2_an521.yaml deleted file mode 100644 index acc2d95127be6f..00000000000000 --- a/boards/arm/mps2_an521/mps2_an521.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: mps2_an521 -name: ARM V2M MPS2-AN521 -type: mcu -arch: arm -ram: 4096 -flash: 4096 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -supported: - - gpio -testing: - default: true - ignore_tags: - - drivers - - bluetooth - - net - - timer -vendor: arm diff --git a/boards/arm/mps2_an521/mps2_an521_defconfig b/boards/arm/mps2_an521/mps2_an521_defconfig deleted file mode 100644 index 032f9bad9d1123..00000000000000 --- a/boards/arm/mps2_an521/mps2_an521_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2018-2019 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN521_CPU0=y -CONFIG_BOARD_MPS2_AN521_CPU0=y -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=7 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y - -# Build a Secure firmware image -CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arm/mps2_an521/mps2_an521_ns.yaml b/boards/arm/mps2_an521/mps2_an521_ns.yaml deleted file mode 100644 index bf8d5edc24392b..00000000000000 --- a/boards/arm/mps2_an521/mps2_an521_ns.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: mps2_an521_ns -name: ARM V2M MPS2-AN521_ns -type: mcu -arch: arm -ram: 512 -flash: 512 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -testing: - default: true - only_tags: - - arm - - kernel - - tfm - - userspace - - trusted-firmware-m diff --git a/boards/arm/mps2_an521/mps2_an521_ns_defconfig b/boards/arm/mps2_an521/mps2_an521_ns_defconfig deleted file mode 100644 index 780fdaf097f487..00000000000000 --- a/boards/arm/mps2_an521/mps2_an521_ns_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright (c) 2018-2019 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN521_CPU0=y -CONFIG_BOARD_MPS2_AN521_CPU0_NS=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=6 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/mps2_an521/mps2_an521_remote.yaml b/boards/arm/mps2_an521/mps2_an521_remote.yaml deleted file mode 100644 index 1371fd01cadab6..00000000000000 --- a/boards/arm/mps2_an521/mps2_an521_remote.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: mps2_an521_remote -name: ARM V2M MPS2-AN521_remote -type: mcu -arch: arm -ram: 512 -flash: 468 -simulation: qemu -toolchain: - - gnuarmemb - - zephyr - - xtools -testing: - default: true - only_tags: - - arm - - fpu diff --git a/boards/arm/mps2_an521/mps2_an521_remote_defconfig b/boards/arm/mps2_an521/mps2_an521_remote_defconfig deleted file mode 100644 index 9bc7f496873db1..00000000000000 --- a/boards/arm/mps2_an521/mps2_an521_remote_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018-2019 Linaro Limited -# Copyright (c) 2021 Nordic Semiconductor ASA -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MPS2=y -CONFIG_SOC_MPS2_AN521_CPU1=y -CONFIG_BOARD_MPS2_AN521_CPU1=y -CONFIG_RUNTIME_NMI=y -CONFIG_ARM_MPU=y -CONFIG_QEMU_ICOUNT_SHIFT=7 - -# GPIOs -CONFIG_GPIO=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/mps2_an521/pinmux.c b/boards/arm/mps2_an521/pinmux.c deleted file mode 100644 index bc92dc747d19b4..00000000000000 --- a/boards/arm/mps2_an521/pinmux.c +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Copyright (c) 2018-2019 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include - -/** - * @brief Pinmux driver for ARM MPS2 AN521 Board - * - * The ARM MPS2 AN521 Board has 4 GPIO controllers. These controllers - * are responsible for pin muxing, input/output, pull-up, etc. - * - * All GPIO controller pins are exposed via the following sequence of pin - * numbers: - * Pins 0 - 15 are for GPIO0 - * Pins 16 - 31 are for GPIO1 - * Pins 32 - 47 are for GPIO2 - * Pins 48 - 51 are for GPIO3 - * - * For the GPIO controllers configuration ARM MPS2 AN521 Board follows the - * Arduino compliant pin out. - */ - -#define CMSDK_AHB_GPIO0_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0))) -#define CMSDK_AHB_GPIO1_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1))) -#define CMSDK_AHB_GPIO2_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2))) -#define CMSDK_AHB_GPIO3_DEV \ - ((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3))) - -/* - * This is the mapping from the ARM MPS2 AN521 Board pins to GPIO - * controllers. - * - * D0 : EXT_0 - * D1 : EXT_4 - * D2 : EXT_2 - * D3 : EXT_3 - * D4 : EXT_1 - * D5 : EXT_6 - * D6 : EXT_7 - * D7 : EXT_8 - * D8 : EXT_9 - * D9 : EXT_10 - * D10 : EXT_12 - * D11 : EXT_13 - * D12 : EXT_14 - * D13 : EXT_11 - * D14 : EXT_15 - * D15 : EXT_5 - * D16 : EXT_16 - * D17 : EXT_17 - * D18 : EXT_18 - * D19 : EXT_19 - * D20 : EXT_20 - * D21 : EXT_21 - * D22 : EXT_22 - * D23 : EXT_23 - * D24 : EXT_24 - * D25 : EXT_25 - * D26 : EXT_26 - * D27 : EXT_30 - * D28 : EXT_28 - * D29 : EXT_29 - * D30 : EXT_27 - * D31 : EXT_32 - * D32 : EXT_33 - * D33 : EXT_34 - * D34 : EXT_35 - * D35 : EXT_36 - * D36 : EXT_38 - * D37 : EXT_39 - * D38 : EXT_40 - * D39 : EXT_44 - * D40 : EXT_41 - * D41 : EXT_31 - * D42 : EXT_37 - * D43 : EXT_42 - * D44 : EXT_43 - * D45 : EXT_45 - * D46 : EXT_46 - * D47 : EXT_47 - * D48 : EXT_48 - * D49 : EXT_49 - * D50 : EXT_50 - * D51 : EXT_51 - * - * UART_3_RX : D0 - * UART_3_TX : D1 - * SPI_3_CS : D10 - * SPI_3_MOSI : D11 - * SPI_3_MISO : D12 - * SPI_3_SCLK : D13 - * I2C_3_SDA : D14 - * I2C_3_SCL : D15 - * UART_4_RX : D26 - * UART_4_TX : D30 - * SPI_4_CS : D36 - * SPI_4_MOSI : D37 - * SPI_4_MISO : D38 - * SPI_4_SCK : D39 - * I2C_4_SDA : D40 - * I2C_4_SCL : D41 - * - */ -static void arm_mps2_pinmux_defaults(void) -{ - uint32_t gpio_0 = 0; - uint32_t gpio_1 = 0; - uint32_t gpio_2 = 0; - - /* Set GPIO Alternate Functions */ - - gpio_0 = (1<<0) /* Shield 0 UART 3 RXD */ - | (1<<4) /* Shield 0 UART 3 TXD */ - | (1<<5) /* Shield 0 I2C SCL SBCON2 */ - | (1<<15) /* Shield 0 I2C SDA SBCON2 */ - | (1<<11) /* Shield 0 SPI 3 SCK */ - | (1<<12) /* Shield 0 SPI 3 SS */ - | (1<<13) /* Shield 0 SPI 3 MOSI */ - | (1<<14); /* Shield 0 SPI 3 MISO */ - - CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0; - - gpio_1 = (1<<10) /* Shield 1 UART 4 RXD */ - | (1<<14) /* Shield 1 UART 4 TXD */ - | (1<<15) /* Shield 1 I2C SCL SBCON3 */ - | (1<<0) /* ADC SPI 2 SS */ - | (1<<1) /* ADC SPI 2 MISO */ - | (1<<2) /* ADC SPI 2 MOSI */ - | (1<<3) /* ADC SPI 2 SCK */ - | (1<<5) /* USER BUTTON 0 */ - | (1<<6); /* USER BUTTON 1 */ - - CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1; - - gpio_2 = (1<<9) /* Shield 1 I2C SDA SBCON3 */ - | (1<<6) /* Shield 1 SPI 4 SS */ - | (1<<7) /* Shield 1 SPI 4 MOSI */ - | (1<<8) /* Shield 1 SPI 4 MISO */ - | (1<<12); /* Shield 1 SPI 4 SCK */ - - CMSDK_AHB_GPIO2_DEV->altfuncset = gpio_2; -} - -static int arm_mps2_pinmux_init(void) -{ - - arm_mps2_pinmux_defaults(); - - return 0; -} - -SYS_INIT(arm_mps2_pinmux_init, PRE_KERNEL_1, - CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); diff --git a/boards/arm/mps3/Kconfig b/boards/arm/mps3/Kconfig new file mode 100644 index 00000000000000..019f22aae49dd3 --- /dev/null +++ b/boards/arm/mps3/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS3 + select QEMU_TARGET diff --git a/boards/arm/mps3/Kconfig.defconfig b/boards/arm/mps3/Kconfig.defconfig new file mode 100644 index 00000000000000..078012e46a760e --- /dev/null +++ b/boards/arm/mps3/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2018-2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MPS3_AN547 + +# MPU-based null-pointer dereferencing detection cannot +# be applied as the (0x0 - 0x400) is unmapped but QEMU +# will still permit bus access. +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET +endchoice + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +endif diff --git a/boards/arm/mps3/Kconfig.mps3 b/boards/arm/mps3/Kconfig.mps3 new file mode 100644 index 00000000000000..84dd3fff095316 --- /dev/null +++ b/boards/arm/mps3/Kconfig.mps3 @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Nordic Semiconductor +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPS3 + select SOC_SERIES_MPS3 + select SOC_MPS3_AN547 diff --git a/boards/arm/mps3_an547/board.cmake b/boards/arm/mps3/board.cmake similarity index 100% rename from boards/arm/mps3_an547/board.cmake rename to boards/arm/mps3/board.cmake diff --git a/boards/arm/mps3/board.yml b/boards/arm/mps3/board.yml new file mode 100644 index 00000000000000..5ee7ed7c03789f --- /dev/null +++ b/boards/arm/mps3/board.yml @@ -0,0 +1,7 @@ +board: + name: mps3 + vendor: arm + socs: + - name: 'an547' + variants: + - name: 'ns' diff --git a/boards/arm/mps3_an547/doc/img/mps3_an547.jpg b/boards/arm/mps3/doc/img/mps3_an547.jpg similarity index 100% rename from boards/arm/mps3_an547/doc/img/mps3_an547.jpg rename to boards/arm/mps3/doc/img/mps3_an547.jpg diff --git a/boards/arm/mps3/doc/index.rst b/boards/arm/mps3/doc/index.rst new file mode 100644 index 00000000000000..530999206d4ffc --- /dev/null +++ b/boards/arm/mps3/doc/index.rst @@ -0,0 +1,245 @@ +.. _mps3_an547_board: + +ARM MPS3 AN547 +############### + +Overview +******** + +The mps3_an547 board configuration is used by Zephyr applications that run +on the MPS3 AN547 board. It provides support for the MPS3 AN547 ARM Cortex-M55 +CPU and the following devices: + +- Nested Vectored Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) +- Cortex-M System Design Kit GPIO +- Cortex-M System Design Kit UART +- Ethos-U55 NPU + +.. image:: img/mps3_an547.jpg + :align: center + :alt: ARM MPS3 AN547 + +This board configuration also supports using the `Corstone-300 FVP`_ to emulate +a MPS3 AN547 hardware platform. + +The Corstone-300 FVP (Fixed Virtual Platform) is a complete simulation of the +Arm system, including processor, memory and peripherals. It is a available free +of charge for Linux and Windows systems. The FVP has been selected for +simulation since it provides access to the Ethos-U55 NPU, which is unavailable +in QEMU or other simulation platforms. + +To run the Fixed Virtual Platform simulation tool you must download "FVP model +for the Corstone-300 MPS3" from Arm and install it on your host PC. This board +has been tested with version 11.12.57 (Nov 2 2020). + +Zephyr board options +==================== + +The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support +for building for both Secure and Non-Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| ``mps3/an547`` | For building Secure (or Secure-only) firmware | ++----------------------+-----------------------------------------------+ +| ``mps3/an547/ns`` | For building Non-Secure firmware | ++----------------------+-----------------------------------------------+ + +Hardware +******** + +ARM MPS3 AN547 provides the following hardware components: + +- ARM Cortex-M55 +- Soft Macro Model (SMM) implementation of SSE-300 subsystem +- Memory + + - 8MB BRAM + - 4GB DDR4 SODIMM (by default, upgradeable to 8GB) + - 16GB eMMC + - 8MB QSPI Flash + +- Debug + + - P‐JTAG, F-JTAG, SWD, 4-bit trace, 16-bit trace + - Four serial ports over USB + +- Interface + + - AHB GPIO + - UART + - SPI + - I2C + - I2S + - Color LCD serial interface + - Ethernet + - VGA + +- On-board Peripherals + + - Color LCD + - 10 LEDs + - 8 Switches + - 2 user push buttons + +Supported Features +=================== + +The ``mps3/an547`` board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. +See the `MPS3 FPGA Website`_ for a complete list of MPS3 AN547 board hardware +features. + +The default configuration can be found in +:zephyr_file:`boards/arm/mps3/mps3_an547_defconfig`. + +For more details refer to `MPS3 AN547 Technical Reference Manual (TRM)`_. + +Serial Port +=========== + +The MPS3 AN547 has six UARTs. The Zephyr console output by default, uses +UART0, which is exposed over the Debug USB interface (J8). + +Serial port 0 on the Debug USB interface is the MCC board control console. + +Serial port 1 on the Debug USB interface is connected to UART 0. + +Serial port 2 on the Debug USB interface is connected to UART 1. + +Serial port 3 on the Debug USB interface is connected to UART 2. + +Programming and Debugging +************************* + +Flashing +======== + +MPS3 AN547 provides: + +- A USB connection to the host computer, which exposes Mass Storage and + CMSIS-DAP, and serial ports. + +Building an application +----------------------- + +You can build applications in the usual way. Here is an example for +the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mps3/an547 + :goals: build + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps3 + +Uploading an application to MPS3 AN547 +--------------------------------------- + +Applications can be in elf, hex or bin format. The binaries are flashed when +the board boots up, using files stored on the on-board Micro SD card. The +Motherboard Configuration Controller (MCC) is responsible for loading the FPGA +image and binaries. + +Connect the MPS3 to your host computer using the USB port. You should see a +USB connection exposing a Mass Storage (``V2M-MPS3`` by default). + +The update requires 3 steps: + +1. Copy application files to ``/SOFTWARE/``. +2. Open ``/MB/HBI0309C/AN547/images.txt``. +3. Update the ``AN547/images.txt`` file as follows: + +.. code-block:: bash + + TITLE: Versatile Express Images Configuration File + + [IMAGES] + TOTALIMAGES: 1 ;Number of Images (Max: 32) + + IMAGE0ADDRESS: 0x01000000 ;Please select the required executable program + + IMAGE0FILE: \SOFTWARE\zephyr.elf + + +Reset the board, and you should see the following message on the corresponding +serial port: + +.. code-block:: console + + Hello World! mps3 + + +FVP Usage +========= + +To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before +using it. Then you can run it with ``west build -t run``. + +.. code-block:: bash + + export ARMFVP_BIN_PATH=/path/to/fvp/directory + west build -t run + + +QEMU Usage +========== + +To run with QEMU instead of the default FVP, override the emulator selection +at build time via: + +.. code-block:: bash + + $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run + + +Note, however, that the Ethos-U55 NPU is not available in QEMU. If you require +the use of the NPU, please use the default FVP for device emulation. + +.. _Corstone-300 FVP: + https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps + +.. _MPS3 FPGA Website: + https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3 + +.. _MPS3 AN547 Technical Reference Manual (TRM): + https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf + +.. _MPS3 FPGA Prototyping Board Technical Reference Manual (TRM): + https://developer.arm.com/documentation/100765/latest + +.. _Cortex M55 Generic User Guide: + https://developer.arm.com/documentation/101051/latest + +.. _Corelink SSE-300 Example Subsystem: + https://developer.arm.com/documentation/101772/latest diff --git a/boards/arm/mps3_an547/mps3_an547-common.dtsi b/boards/arm/mps3/mps3_an547-common.dtsi similarity index 100% rename from boards/arm/mps3_an547/mps3_an547-common.dtsi rename to boards/arm/mps3/mps3_an547-common.dtsi diff --git a/boards/arm/mps3_an547/mps3_an547.dts b/boards/arm/mps3/mps3_an547.dts similarity index 100% rename from boards/arm/mps3_an547/mps3_an547.dts rename to boards/arm/mps3/mps3_an547.dts diff --git a/boards/arm/mps3_an547/mps3_an547.yaml b/boards/arm/mps3/mps3_an547.yaml similarity index 93% rename from boards/arm/mps3_an547/mps3_an547.yaml rename to boards/arm/mps3/mps3_an547.yaml index 3ade98161c8cf6..538fa24db67d9e 100644 --- a/boards/arm/mps3_an547/mps3_an547.yaml +++ b/boards/arm/mps3/mps3_an547.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mps3_an547 +identifier: mps3/an547 name: Arm MPS3-AN547 type: mcu arch: arm diff --git a/boards/arm/mps3_an547/mps3_an547_defconfig b/boards/arm/mps3/mps3_an547_defconfig similarity index 81% rename from boards/arm/mps3_an547/mps3_an547_defconfig rename to boards/arm/mps3/mps3_an547_defconfig index ec0c9fccc3303d..90c9b6a9f8e425 100644 --- a/boards/arm/mps3_an547/mps3_an547_defconfig +++ b/boards/arm/mps3/mps3_an547_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MPS3=y -CONFIG_SOC_MPS3_AN547=y -CONFIG_BOARD_MPS3_AN547=y CONFIG_RUNTIME_NMI=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_ARM_MPU=y diff --git a/boards/arm/mps3_an547/mps3_an547_ns.dts b/boards/arm/mps3/mps3_an547_ns.dts similarity index 100% rename from boards/arm/mps3_an547/mps3_an547_ns.dts rename to boards/arm/mps3/mps3_an547_ns.dts diff --git a/boards/arm/mps3_an547/mps3_an547_ns.yaml b/boards/arm/mps3/mps3_an547_ns.yaml similarity index 91% rename from boards/arm/mps3_an547/mps3_an547_ns.yaml rename to boards/arm/mps3/mps3_an547_ns.yaml index 665962c62ecbc9..3852415834f69d 100644 --- a/boards/arm/mps3_an547/mps3_an547_ns.yaml +++ b/boards/arm/mps3/mps3_an547_ns.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: mps3_an547_ns +identifier: mps3/an547/ns name: Arm MPS3-AN547_ns type: mcu arch: arm diff --git a/boards/arm/mps3_an547/mps3_an547_ns_defconfig b/boards/arm/mps3/mps3_an547_ns_defconfig similarity index 80% rename from boards/arm/mps3_an547/mps3_an547_ns_defconfig rename to boards/arm/mps3/mps3_an547_ns_defconfig index f782f9f8623c04..ccc25c35019c16 100644 --- a/boards/arm/mps3_an547/mps3_an547_ns_defconfig +++ b/boards/arm/mps3/mps3_an547_ns_defconfig @@ -4,12 +4,8 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MPS3=y -CONFIG_SOC_MPS3_AN547=y -CONFIG_BOARD_MPS3_AN547=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y CONFIG_ARM_MPU=y CONFIG_QEMU_ICOUNT_SHIFT=6 @@ -20,3 +16,7 @@ CONFIG_GPIO=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y + +# Build a Non-secure firmware image +CONFIG_TRUSTED_EXECUTION_SECURE=n +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/mps3_an547/Kconfig.board b/boards/arm/mps3_an547/Kconfig.board deleted file mode 100644 index f8e755f12ed55d..00000000000000 --- a/boards/arm/mps3_an547/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPS3_AN547 - bool "Arm Cortex-M55 (Corstone-300, SSE-300 w/Ethos-U55) on MPS3 (AN547)" - depends on SOC_MPS3_AN547 - select QEMU_TARGET diff --git a/boards/arm/mps3_an547/Kconfig.defconfig b/boards/arm/mps3_an547/Kconfig.defconfig deleted file mode 100644 index a318d14aefe6c1..00000000000000 --- a/boards/arm/mps3_an547/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2018-2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MPS3_AN547 - -config BOARD - default "mps3_an547" - -# MPU-based null-pointer dereferencing detection cannot -# be applied as the (0x0 - 0x400) is unmapped but QEMU -# will still permit bus access. -choice NULL_POINTER_EXCEPTION_DETECTION - bool - default NULL_POINTER_EXCEPTION_DETECTION_NONE if QEMU_TARGET -endchoice - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -endif diff --git a/boards/arm/mps3_an547/doc/index.rst b/boards/arm/mps3_an547/doc/index.rst deleted file mode 100644 index b5f383d546a07c..00000000000000 --- a/boards/arm/mps3_an547/doc/index.rst +++ /dev/null @@ -1,245 +0,0 @@ -.. _mps3_an547_board: - -ARM MPS3 AN547 -############### - -Overview -******** - -The mps3_an547 board configuration is used by Zephyr applications that run -on the MPS3 AN547 board. It provides support for the MPS3 AN547 ARM Cortex-M55 -CPU and the following devices: - -- Nested Vectored Interrupt Controller (NVIC) -- System Tick System Clock (SYSTICK) -- Cortex-M System Design Kit GPIO -- Cortex-M System Design Kit UART -- Ethos-U55 NPU - -.. image:: img/mps3_an547.jpg - :align: center - :alt: ARM MPS3 AN547 - -This board configuration also supports using the `Corstone-300 FVP`_ to emulate -a MPS3 AN547 hardware platform. - -The Corstone-300 FVP (Fixed Virtual Platform) is a complete simulation of the -Arm system, including processor, memory and peripherals. It is a available free -of charge for Linux and Windows systems. The FVP has been selected for -simulation since it provides access to the Ethos-U55 NPU, which is unavailable -in QEMU or other simulation platforms. - -To run the Fixed Virtual Platform simulation tool you must download "FVP model -for the Corstone-300 MPS3" from Arm and install it on your host PC. This board -has been tested with version 11.12.57 (Nov 2 2020). - -Zephyr board options -==================== - -The MPS3+ AN547 is an SoC with Cortex-M55 architecture. Zephyr provides support -for building for both Secure and Non-Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| mps3_an547 | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| mps3_an547_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ - -Hardware -******** - -ARM MPS3 AN547 provides the following hardware components: - -- ARM Cortex-M55 -- Soft Macro Model (SMM) implementation of SSE-300 subsystem -- Memory - - - 8MB BRAM - - 4GB DDR4 SODIMM (by default, upgradeable to 8GB) - - 16GB eMMC - - 8MB QSPI Flash - -- Debug - - - P‐JTAG, F-JTAG, SWD, 4-bit trace, 16-bit trace - - Four serial ports over USB - -- Interface - - - AHB GPIO - - UART - - SPI - - I2C - - I2S - - Color LCD serial interface - - Ethernet - - VGA - -- On-board Peripherals - - - Color LCD - - 10 LEDs - - 8 Switches - - 2 user push buttons - -Supported Features -=================== - -The mps3_an547 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. -See the `MPS3 FPGA Website`_ for a complete list of MPS3 AN547 board hardware -features. - -The default configuration can be found in the defconfig file: -``boards/arm/mps3_an547/mps3_an547_defconfig``. - -For more details refer to `MPS3 AN547 Technical Reference Manual (TRM)`_. - -Serial Port -=========== - -The MPS3 AN547 has six UARTs. The Zephyr console output by default, uses -UART0, which is exposed over the Debug USB interface (J8). - -Serial port 0 on the Debug USB interface is the MCC board control console. - -Serial port 1 on the Debug USB interface is connected to UART 0. - -Serial port 2 on the Debug USB interface is connected to UART 1. - -Serial port 3 on the Debug USB interface is connected to UART 2. - -Programming and Debugging -************************* - -Flashing -======== - -MPS3 AN547 provides: - -- A USB connection to the host computer, which exposes Mass Storage and - CMSIS-DAP, and serial ports. - -Building an application ------------------------ - -You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: mps3_an547 - :goals: build - -Open a serial terminal (minicom, putty, etc.) with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps3_an547 - -Uploading an application to MPS3 AN547 ---------------------------------------- - -Applications can be in elf, hex or bin format. The binaries are flashed when -the board boots up, using files stored on the on-board Micro SD card. The -Motherboard Configuration Controller (MCC) is responsible for loading the FPGA -image and binaries. - -Connect the MPS3 to your host computer using the USB port. You should see a -USB connection exposing a Mass Storage (``V2M-MPS3`` by default). - -The update requires 3 steps: - -1. Copy application files to ``/SOFTWARE/``. -2. Open ``/MB/HBI0309C/AN547/images.txt``. -3. Update the ``AN547/images.txt`` file as follows: - -.. code-block:: bash - - TITLE: Versatile Express Images Configuration File - - [IMAGES] - TOTALIMAGES: 1 ;Number of Images (Max: 32) - - IMAGE0ADDRESS: 0x01000000 ;Please select the required executable program - - IMAGE0FILE: \SOFTWARE\zephyr.elf - - -Reset the board, and you should see the following message on the corresponding -serial port: - -.. code-block:: console - - Hello World! mps3_an547 - - -FVP Usage -========= - -To run with the FVP, first set environment variable ``ARMFVP_BIN_PATH`` before -using it. Then you can run it with ``west build -t run``. - -.. code-block:: bash - - export ARMFVP_BIN_PATH=/path/to/fvp/directory - west build -t run - - -QEMU Usage -========== - -To run with QEMU instead of the default FVP, override the emulator selection -at build time via: - -.. code-block:: bash - - $ west build -b mps3_an547 samples/hello_world -DEMU_PLATFORM=qemu -t run - - -Note, however, that the Ethos-U55 NPU is not available in QEMU. If you require -the use of the NPU, please use the default FVP for device emulation. - -.. _Corstone-300 FVP: - https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps - -.. _MPS3 FPGA Website: - https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3 - -.. _MPS3 AN547 Technical Reference Manual (TRM): - https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf - -.. _MPS3 FPGA Prototyping Board Technical Reference Manual (TRM): - https://developer.arm.com/documentation/100765/latest - -.. _Cortex M55 Generic User Guide: - https://developer.arm.com/documentation/101051/latest - -.. _Corelink SSE-300 Example Subsystem: - https://developer.arm.com/documentation/101772/latest diff --git a/boards/arm/mr_canhubk3/Kconfig.board b/boards/arm/mr_canhubk3/Kconfig.board deleted file mode 100644 index af9a09391cd738..00000000000000 --- a/boards/arm/mr_canhubk3/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MR_CANHUBK3 - bool "mr_canhubk3" - depends on SOC_SERIES_S32K3XX - select SOC_PART_NUMBER_PS32K344EHVPBS diff --git a/boards/arm/mr_canhubk3/Kconfig.defconfig b/boards/arm/mr_canhubk3/Kconfig.defconfig deleted file mode 100644 index 53e554da88f8b4..00000000000000 --- a/boards/arm/mr_canhubk3/Kconfig.defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MR_CANHUBK3 - -config BOARD - default "mr_canhubk3" - -if SERIAL - -config UART_CONSOLE - default y - -endif # SERIAL - -if SPI - -config SPI_INIT_PRIORITY - default 50 - -if WDT_NXP_FS26 - -config WDT_NXP_FS26_INIT_PRIORITY - default 51 - -endif # WDT_NXP_FS26 -endif # SPI - -if CAN - -config GPIO - default y - -endif # CAN - -if NETWORKING - -config NET_L2_ETHERNET - default y if !NET_LOOPBACK && !NET_TEST - -config MDIO - default y if NET_L2_ETHERNET - -endif # NETWORKING - -endif # BOARD_MR_CANHUBK3 diff --git a/boards/arm/mr_canhubk3/doc/index.rst b/boards/arm/mr_canhubk3/doc/index.rst deleted file mode 100644 index 711ee43a0ca546..00000000000000 --- a/boards/arm/mr_canhubk3/doc/index.rst +++ /dev/null @@ -1,339 +0,0 @@ -.. _mr_canhubk3: - -NXP MR-CANHUBK3 -############### - -Overview -******** - -`NXP MR-CANHUBK3`_ is an evaluation board for mobile robotics applications such -as autonomous mobile robots (AMR) and automated guided vehicles (AGV). It -features an `NXP S32K344`_ general-purpose automotive microcontroller based on -an Arm Cortex-M7 core (Lock-Step). - -.. image:: img/mr_canhubk3_top.jpg - :align: center - :alt: NXP MR-CANHUBK3 (TOP) - -Hardware -******** - -- NXP S32K344 - - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.) - - 4 MB of program flash, with ECC - - 320 KB RAM, with ECC - - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI - - 12-bit 1 Msps ADC, 16-bit eMIOS timer - -- `NXP FS26 Safety System Basis Chip`_ - -- Interfaces: - - Console UART - - 6x CAN FD - - 100Base-T1 Ethernet - - JST-GH connectors and I/O headers for I2C, SPI, GPIO, - PWM, etc. - -More information about the hardware and design resources can be found at -`NXP MR-CANHUBK3`_ website. - -Supported Features -================== - -The ``mr_canhubk3`` board configuration supports the following hardware features: - -============ ========== ================================ -Interface Controller Driver/Component -============ ========== ================================ -SIUL2 on-chip | pinctrl - | gpio - | external interrupt controller -WKPU on-chip interrupt controller -LPUART on-chip serial -QSPI on-chip flash -FLEXCAN on-chip can -LPI2C on-chip i2c -ADC SAR on-chip adc -LPSPI on-chip spi -WDT FS26 SBC watchdog -EMAC on-chip ethernet - mdio -eMIOS on-chip pwm -EDMA on-chip dma -============ ========== ================================ - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/mr_canhubk3/mr_canhubk3_defconfig`. - -Connections and IOs -=================== - -Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high -bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low -bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank). - -The GPIO controller provides the option to route external input pad interrupts -to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. -By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, -unless they are explicity configured to be directed to the WKPU interrupt -controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,s32-gpio.yaml`. - -To find information about which GPIOs are compatible with each interrupt -controller, refer to the device reference manual. - -.. note:: - - It is important to highlight that the current board configuration lacks - support for wake-up events and power-management features. WKPU functionality - is restricted solely to serving as an interrupt controller. - -LEDs ----- - -The MR-CANHUBK3 board has one user RGB LED: - -======================= ===== ===== =================================== -Devicetree node Color Pin Pin Functions -======================= ===== ===== =================================== -led0 / user_led1_red Red PTE14 FXIO D7 / EMIOS0 CH19 -led1 / user_led1_green Green PTA27 FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10 -led2 / user_led1_blue Blue PTE12 FXIO D8 / EMIOS1 CH5 -======================= ===== ===== =================================== - -The user can control the LEDs in any way. An output of ``0`` illuminates the LED. - -Buttons -------- - -The MR-CANHUBK3 board has two user buttons: - -======================= ===== ===== ============== -Devicetree node Label Pin Pin Functions -======================= ===== ===== ============== -sw0 / user_button_1 SW1 PTD15 EIRQ31 -sw0 / user_button_2 SW2 PTA25 EIRQ5 / WKPU34 -======================= ===== ===== ============== - -System Clock -============ - -The Arm Cortex-M7 (Lock-Step) are configured to run at 160 MHz. - -Serial Console -============== - -By default, the serial console is provided through ``lpuart2`` on the 7-pin -DCD-LZ debug connector ``P6``. - -========= ===== ============ -Connector Pin Pin Function -========= ===== ============ -P6.2 PTA9 LPUART2_TX -P6.3 PTA8 LPUART2_RX -========= ===== ============ - -CAN -=== - -CAN is provided through FLEXCAN interface with 6 instances. - -=============== ======= =============== ============= -Devicetree node Pin Pin Function Bus Connector -=============== ======= =============== ============= -flexcan0 | PTA6 | PTA6_CAN0_RX P12/P13 - | PTA7 | PTA7_CAN0_TX -flexcan1 | PTC9 | PTC9_CAN0_RX P14/P15 - | PTC8 | PTC8_CAN0_TX -flexcan2 | PTE25 | PTE25_CAN0_RX P16/P17 - | PTE24 | PTE24_CAN0_TX -flexcan3 | PTC29 | PTC29_CAN0_RX P18/019 - | PTC28 | PTC28_CAN0_TX -flexcan4 | PTC31 | PTC31_CAN0_RX P20/P21 - | PTC30 | PTC30_CAN0_TX -flexcan5 | PTC11 | PTC11_CAN0_RX P22/P23 - | PTC10 | PTC10_CAN0_TX -=============== ======= =============== ============= - -.. note:: - There is limitation by HAL SDK, so CAN only has support maximum 64 message buffers (MBs) - and support maximum 32 message buffers for concurrent active instances with 8 bytes - payload. We need to pay attention to configuration options: - - 1. :kconfig:option:`CONFIG_CAN_MAX_MB` must be less or equal than the - maximum number of message buffers that is according to the table below. - - 2. :kconfig:option:`CONFIG_CAN_MAX_FILTER` must be less or equal than - :kconfig:option:`CONFIG_CAN_MAX_MB`. - -=============== ========== ================ ================ -Devicetree node Payload Hardware support Software support -=============== ========== ================ ================ -flexcan0 | 8 bytes | 96 MBs | 64 MBs - | 16 bytes | 63 MBs | 42 MBs - | 32 bytes | 36 MBs | 24 MBs - | 64 bytes | 21 MBs | 14 MBs -flexcan1 | 8 bytes | 64 MBs | 64 MBs - | 16 bytes | 42 MBs | 42 MBs - | 32 bytes | 24 MBs | 24 MBs - | 64 bytes | 14 MBs | 14 MBs -flexcan2 | 8 bytes | 64 MBs | 64 MBs - | 16 bytes | 42 MBs | 42 MBs - | 32 bytes | 24 MBs | 24 MBs - | 64 bytes | 14 MBs | 14 MBs -flexcan3 | 8 bytes | 32 MBs | 32 MBs - | 16 bytes | 21 MBs | 21 MBs - | 32 bytes | 12 MBs | 12 MBs - | 64 bytes | 7 MBs | 7 MBs -flexcan4 | 8 bytes | 32 MBs | 32 MBs - | 16 bytes | 21 MBs | 21 MBs - | 32 bytes | 12 MBs | 12 MBs - | 64 bytes | 7 MBs | 7 MBs -flexcan5 | 8 bytes | 32 MBs | 32 MBs - | 16 bytes | 21 MBs | 21 MBs - | 32 bytes | 12 MBs | 12 MBs - | 64 bytes | 7 MBs | 7 MBs -=============== ========== ================ ================ - -.. note:: - A CAN bus usually requires 60 Ohm termination at both ends of the bus. This may be - accomplished using one of the included CAN termination boards. For more details, refer - to the section ``6.3 CAN Connectors`` in the Hardware User Manual of `NXP MR-CANHUBK3`_. - -I2C -=== - -I2C is provided through LPI2C interface with 2 instances ``lpi2c0`` and ``lpi2c1`` -on corresponding connectors ``P4``, ``P3``. - -========= ===== ============ -Connector Pin Pin Function -========= ===== ============ -P3.2 PTD9 LPI2C1_SCL -P3.3 PTD8 LPI2C1_SDA -P4.3 PTD14 LPI2C0_SCL -P4.4 PTD13 LPI2C0_SDA -========= ===== ============ - -ADC -=== - -ADC is provided through ADC SAR controller with 3 instances. ADC channels are divided into -3 groups (precision, standard and external). - -.. note:: - All channels of an instance only run on 1 group channel at the same time. - -FS26 SBC Watchdog -================= - -On normal operation after the board is powered on, there is a window of 256 ms -on which the FS26 watchdog must be serviced with a good token refresh, otherwise -the watchdog will signal a reset to the MCU. This board configuration enables -the FS26 watchdog driver that handles this initialization. - -.. note:: - - The FS26 can also be started in debug mode (watchdog disabled) following - these steps: - - 1. Power off the board. - 2. Remove the jumper ``JP1`` (pins 1-2 open), which is connected by default. - 3. Power on the board. - 4. Reconnect the jumper ``JP1`` (pins 1-2 shorted). - -External Flash -============== - -The on-board MX25L6433F 64M-bit multi-I/O Serial NOR Flash memory is connected -to the QSPI controller port A1. This board configuration selects it as the -default flash controller. - -Ethernet -======== - -This board has a single instance of Ethernet Media Access Controller (EMAC) -interfacing with a `NXP TJA1103`_ 100Base-T1 Ethernet PHY. Currently, there is -limited driver for this PHY that allows for overiding the default pin strapping configuration for -the PHY (RMII, master, autonomous mode enabled, polarity correction enabled) -to slave mode. - -The 100Base-T1 signals are available in connector ``P9`` and can be converted to -100Base-T using a Ethernet media converter such as `RDDRONE-T1ADAPT`_. - -Programming and Debugging -************************* - -Applications for the ``mr_canhubk3`` board can be built in the usual way as -documented in :ref:`build_an_application`. - -This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ -West runners for flashing and debugging applications. Follow the steps described -in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, -to setup the flash and debug host tools for these runners, respectively. The -default runner is J-Link. - -Flashing -======== - -Run the ``west flash`` command to flash the application using SEGGER J-Link. -Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. - -The Lauterbach TRACE32 runner supports additional options that can be passed -through command line: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile= loadTo= - eraseFlash= verifyFlash= - -Where: - -- ```` is the path to the Zephyr application ELF in the output - directory -- ``loadTo=flash`` loads the application to the SoC internal program flash - (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the - application to SRAM. Default is ``flash``. -- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the - application is downloaded to either Flash or SRAM. This routine takes time to - execute. Default is ``no``. -- ``verifyFlash=yes`` verify the SoC internal flash content after programming - (use together with ``loadTo=flash``). Default is ``no``. - -For example, to erase and verify flash content: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes - -Debugging -========= - -Run the ``west debug`` command to start a GDB session using SEGGER J-Link. -Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 -software debugging interface. - -References -********** - -.. target-notes:: - -.. _NXP MR-CANHUBK3: - https://www.nxp.com/design/development-boards/automotive-development-platforms/s32k-mcu-platforms/s32k344-evaluation-board-for-mobile-robotics-incorporating-100baset1-and-six-can-fd:MR-CANHUBK344 - -.. _NXP S32K344: - https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 - -.. _NXP FS26 Safety System Basis Chip: - https://www.nxp.com/products/power-management/pmics-and-sbcs/safety-sbcs/safety-system-basis-chip-with-low-power-fit-for-asil-d:FS26 - -.. _NXP TJA1103: - https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/asil-b-compliant-100base-t1-ethernet-phy:TJA1103 - -.. _RDDRONE-T1ADAPT: - https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/ethernet-media-converter-for-drones-rovers-mobile-robotics-and-automotive:RDDRONE-T1ADAPT - -.. _Lauterbach TRACE32: - https://www.lauterbach.com - -.. _SEGGER J-Link: - https://wiki.segger.com/NXP_S32K3xx diff --git a/boards/arm/msp_exp432p401r_launchxl/Kconfig b/boards/arm/msp_exp432p401r_launchxl/Kconfig deleted file mode 100644 index 13d6b2ad41a063..00000000000000 --- a/boards/arm/msp_exp432p401r_launchxl/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -# TI MSP-EXP432P401R LaunchXL configuration - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MSP_EXP432P401R_LAUNCHXL - -endif # BOARD_MSP_EXP432P401R_LAUNCHXL diff --git a/boards/arm/msp_exp432p401r_launchxl/Kconfig.board b/boards/arm/msp_exp432p401r_launchxl/Kconfig.board deleted file mode 100644 index 3a15e56a5d4360..00000000000000 --- a/boards/arm/msp_exp432p401r_launchxl/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# TI SimpleLink MSP-EXP432P401R LaunchXL Development Board - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MSP_EXP432P401R_LAUNCHXL - bool "TI MSP-EXP432P401R LAUNCHXL" - depends on SOC_MSP432P401R diff --git a/boards/arm/msp_exp432p401r_launchxl/Kconfig.defconfig b/boards/arm/msp_exp432p401r_launchxl/Kconfig.defconfig deleted file mode 100644 index f3a70f2bb6ba06..00000000000000 --- a/boards/arm/msp_exp432p401r_launchxl/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# TI MSP-EXP432P401R LaunchXL development board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "msp_exp432p401r_launchxl" - depends on BOARD_MSP_EXP432P401R_LAUNCHXL diff --git a/boards/arm/msp_exp432p401r_launchxl/board.cmake b/boards/arm/msp_exp432p401r_launchxl/board.cmake deleted file mode 100644 index cbeaea2e4564b5..00000000000000 --- a/boards/arm/msp_exp432p401r_launchxl/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/msp_exp432p401r_launchxl/doc/index.rst b/boards/arm/msp_exp432p401r_launchxl/doc/index.rst deleted file mode 100644 index d2a2e12153a6ab..00000000000000 --- a/boards/arm/msp_exp432p401r_launchxl/doc/index.rst +++ /dev/null @@ -1,152 +0,0 @@ -.. _msp_exp432p401r_launchxl: - -MSP-EXP432P401R LaunchXL -######################## - -Overview -******** - -The SimpleLink MSP‐EXP432P401R LaunchPad development kit is an easy-to-use evaluation -module for the SimpleLink MSP432P401R microcontroller. It contains everything needed to start -developing on the SimpleLink MSP432 low-power + performance ARM |reg| 32-bit Cortex |reg|-M4F -microcontroller (MCU). - -.. figure:: img/msp_exp432p401r_launchxl.jpg - :align: center - :alt: MSP-EXP432P401R LaunchXL development board - -Features: -========= - -* Low-power ARM Cortex-M4F MSP432P401R -* 40-pin LaunchPad development kit standard that leverages the BoosterPack plug-in module ecosystem -* XDS110-ET, an open-source onboard debug probe featuring EnergyTrace+ technology and application - UART -* Two buttons and two LEDs for user interaction -* Backchannel UART through USB to PC - -Details on the MSP-EXP432P401R LaunchXL development board can be found in the -MSP-EXP432P401R LaunchXL User's Guide. - -Supported Features -================== - -* The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the - default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low- - power modes to be used. -* The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK. - -The MSP-EXP432P401R LaunchXL development board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port | -+-----------+------------+-----------------------+ - -More details about the supported peripherals are available in MSP432P4XX TRM -Other hardware features are not currently supported by the Zephyr kernel. - -Building and Flashing -********************* - -Prerequisites: -============== - -#. Ensure the XDS-110 emulation firmware is updated. - - Download and install the latest `XDS-110 emulation package`_. - - Follow these `xds110 firmware update directions - `_ - - Note that the emulation package install may place the xdsdfu utility - in ``/ccs_base/common/uscif/xds110/``. - -#. Install OpenOCD - - You can obtain OpenOCD by following these - :ref:`installing the latest Zephyr SDK instructions `. - - After the installation, add the directory containing the OpenOCD executable - to your environment's PATH variable. For example, use this command in Linux: - - .. code-block:: console - - export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH - - If you had previously installed TI OpenOCD, you can simply switch to use - the one in the Zephyr SDK. If for some reason you wish to continue to use - your TI OpenOCD installation, you can set the OPENOCD and - OPENOCD_DEFAULT_PATH variables in - :zephyr_file:`boards/arm/msp_exp432p401r_launchxl/board.cmake` to point the build - to the paths of the OpenOCD binary and its scripts, before - including the common openocd.board.cmake file: - - .. code-block:: cmake - - set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) - set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) - -Flashing -======== - -Follow the :ref:`getting_started` instructions for Zephyr application -development. - -For example, to build and flash the :ref:`hello_world` application for the -MSP-EXP432P401R LaunchXL: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: msp_exp432p401r_launchxl - :goals: flash - -This will load the image into flash. - -To see program output from UART0, connect a separate terminal window: - -.. code-block:: console - - % screen /dev/ttyACM0 115200 8N1 - -Then press the reset button (S3) on the board to run the program. - -Debugging -========= - -To debug a previously flashed image, after resetting the board, use the 'debug' -build target: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: msp_exp432p401r_launchxl - :maybe-skip-config: - :goals: debug - -References -********** - -TI MSP432 Wiki: - https://en.wikipedia.org/wiki/TI_MSP432 - -TI MSP432P401R Product Page: - http://www.ti.com/product/msp432p401r - -TI MSP432 SDK: - http://www.ti.com/tool/SIMPLELINK-MSP432-SDK - -.. _UniFlash: - http://processors.wiki.ti.com/index.php/UniFlash_v4_Quick_Guide#Command_Line_Interface - -.. _CCS IDE: - http://www.ti.com/tool/ccstudio - -.. _XDS-110 emulation package: - http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download diff --git a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig b/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig deleted file mode 100644 index 01559c8be949d8..00000000000000 --- a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_MSP_EXP432P401R_LAUNCHXL=y -CONFIG_SOC_SERIES_MSP432P4XX=y -CONFIG_SOC_MSP432P401R=y -CONFIG_BUILD_OUTPUT_HEX=y - -# Floating point options -CONFIG_FPU=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/npcx4m8f_evb/Kconfig.board b/boards/arm/npcx4m8f_evb/Kconfig.board deleted file mode 100644 index 093faa1cade02a..00000000000000 --- a/boards/arm/npcx4m8f_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NPCX4M8F_EVB - bool "Nuvoton NPCX4M8F EVB Development board" - depends on SOC_NPCX4M8F diff --git a/boards/arm/npcx4m8f_evb/Kconfig.defconfig b/boards/arm/npcx4m8f_evb/Kconfig.defconfig deleted file mode 100644 index ae6ce2135953c9..00000000000000 --- a/boards/arm/npcx4m8f_evb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NPCX4M8F_EVB - -config BOARD - default "npcx4m8f_evb" - -endif # BOARD_NPCX4M8F_EVB - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config INPUT - default y if KSCAN diff --git a/boards/arm/npcx4m8f_evb/doc/index.rst b/boards/arm/npcx4m8f_evb/doc/index.rst deleted file mode 100644 index a73d65d33da3fa..00000000000000 --- a/boards/arm/npcx4m8f_evb/doc/index.rst +++ /dev/null @@ -1,131 +0,0 @@ -.. _npcx4m8f_evb: - -Nuvoton NPCX4M8F_EVB -#################### - -Overview -******** - -The NPCX4M8F_EVB kit is a development platform to evaluate the -Nuvoton NPCX4 series microcontrollers. This board needs to be mated with -part number NPCX498F. - -.. image:: npcx4m8f_evb.jpg - :align: center - :alt: NPCX4M8F Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 512 KB RAM and 64 KB boot ROM -- ADC & GPIO headers -- UART0 and UART1 -- FAN PWM interface -- Jtag interface -- Intel Modular Embedded Controller Card (MECC) headers - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port/controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PM | on-chip | power management | -+-----------+------------+-------------------------------------+ -| PSL | on-chip | power switch logic | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pulse width modulator | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer sensor | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig`` - - -Connections and IOs -=================== - -Nuvoton to provide the schematic for this board. - -System Clock -============ - -The NPCX4M8F MCU is configured to use the 120Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock -control register (chapter 4 in user manual) - -Serial Port -=========== - -UART1 is configured for serial logs. - -Programming and Debugging -************************* - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG-only sessions. - -Flashing -======== - -If the correct headers are installed, this board supports both J-TAG and also -the ChromiumOS servo. - -To flash using Servo V2, μServo, or Servo V4 (CCD), see the -`Chromium EC Flashing Documentation`_ for more information. - -To flash with J-TAG, install the drivers for your programmer, for example: -SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ - -The openocd from Zephyr SDK 0.16.1 doesn't include npcx4 support, so build openocd from source.:: - - sudo apt-get install libftdi-dev libusb-1.0.0-dev - git clone https://git.code.sf.net/p/openocd/code ~/openocd - cd ~/openocd - ./bootstrap - ./configure --enable-jlink --enable-ftdi - make clean - make - sudo make install - -Build and flash the blinky sample.:: - - west build -t clean && \ - west build -c -p auto -b npcx4m8f_evb samples/basic/blinky && \ - west flash --openocd /usr/local/bin/openocd - -Debugging -========= - -Use JTAG/SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx7m6fb_evb/Kconfig.board b/boards/arm/npcx7m6fb_evb/Kconfig.board deleted file mode 100644 index 84b39c5a9ae6c9..00000000000000 --- a/boards/arm/npcx7m6fb_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NPCX7M6FB_EVB - bool "Nuvoton NPCX7M6FB EVB Development board" - depends on SOC_NPCX7M6FB diff --git a/boards/arm/npcx7m6fb_evb/Kconfig.defconfig b/boards/arm/npcx7m6fb_evb/Kconfig.defconfig deleted file mode 100644 index 70a12bbdcb0652..00000000000000 --- a/boards/arm/npcx7m6fb_evb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NPCX7M6FB_EVB - -config BOARD - default "npcx7m6fb_evb" - -endif # BOARD_NPCX7M6FB_EVB - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config INPUT - default y if KSCAN diff --git a/boards/arm/npcx7m6fb_evb/doc/index.rst b/boards/arm/npcx7m6fb_evb/doc/index.rst deleted file mode 100644 index 7222aac1ebbee2..00000000000000 --- a/boards/arm/npcx7m6fb_evb/doc/index.rst +++ /dev/null @@ -1,107 +0,0 @@ -.. _npcx7m6fb_evb: - -Nuvoton NPCX7M6FB_EVB -##################### - -Overview -******** - -The NPCX7M6FB_EVB kit is a development platform to evaluate the -Nuvoton NPCX7 series microcontrollers. This board needs to be mated with -part number NPCX796FB. - -.. image:: npcx7m6fb_evb.jpg - :align: center - :alt: NPCX7M6FB Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 256 KB RAM and 64 KB boot ROM -- ADC & GPIO headers -- UART0 and UART1 -- FAN PWM interface -- Jtag interface -- Intel Modular Embedded Controller Card (MECC) headers - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig`` - - -Connections and IOs -=================== - -Nuvoton to provide the schematic for this board. - -System Clock -============ - -The NPCX7M6FB MCU is configured to use the 90Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock -control register (chapter 4 in user manual) - -Serial Port -=========== - -UART1 is configured for serial logs. - - -Programming and Debugging -************************* - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG only sessions. - -Flashing -======== - -If the correct IDC headers are installed, this board supports both J-TAG and -also the ChromiumOS servo. - -To flash using Servo V2, μServo, or Servo V4 (CCD), see the -`Chromium EC Flashing Documentation`_ for more information. - -To flash with J-TAG, install the drivers for your programmer, for example: -SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: npcx7m6fb_evb - :maybe-skip-config: - :goals: build flash - -Debugging -========= - -Use JTAG/SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx9m6f_evb/Kconfig.board b/boards/arm/npcx9m6f_evb/Kconfig.board deleted file mode 100644 index a652be619d039b..00000000000000 --- a/boards/arm/npcx9m6f_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NPCX9M6F_EVB - bool "Nuvoton NPCX9M6F EVB Development board" - depends on SOC_NPCX9M6F diff --git a/boards/arm/npcx9m6f_evb/Kconfig.defconfig b/boards/arm/npcx9m6f_evb/Kconfig.defconfig deleted file mode 100644 index d5953dd04febeb..00000000000000 --- a/boards/arm/npcx9m6f_evb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NPCX9M6F_EVB - -config BOARD - default "npcx9m6f_evb" - -endif # BOARD_NPCX9M6F_EVB - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config INPUT - default y if KSCAN diff --git a/boards/arm/npcx9m6f_evb/doc/index.rst b/boards/arm/npcx9m6f_evb/doc/index.rst deleted file mode 100644 index 898f3051220cdd..00000000000000 --- a/boards/arm/npcx9m6f_evb/doc/index.rst +++ /dev/null @@ -1,121 +0,0 @@ -.. _npcx9m6f_evb: - -Nuvoton NPCX9M6F_EVB -#################### - -Overview -******** - -The NPCX9M6F_EVB kit is a development platform to evaluate the -Nuvoton NPCX9 series microcontrollers. This board needs to be mated with -part number NPCX996F. - -.. image:: npcx9m6f_evb.jpg - :align: center - :alt: NPCX9M6F Evaluation Board - -Hardware -******** - -- ARM Cortex-M4F Processor -- 256 KB RAM and 64 KB boot ROM -- ADC & GPIO headers -- UART0 and UART1 -- FAN PWM interface -- Jtag interface -- Intel Modular Embedded Controller Card (MECC) headers - -Supported Features -================== - -The following features are supported: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c port/controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PM | on-chip | power management | -+-----------+------------+-------------------------------------+ -| PSL | on-chip | power switch logic | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pulse width modulator | -+-----------+------------+-------------------------------------+ -| TACH | on-chip | tachometer sensor | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr (at the moment) - -The default configuration can be found in the defconfig file: -``boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig`` - - -Connections and IOs -=================== - -Nuvoton to provide the schematic for this board. - -System Clock -============ - -The NPCX9M6F MCU is configured to use the 90Mhz internal oscillator with the -on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock -control register (chapter 4 in user manual) - -Serial Port -=========== - -UART1 is configured for serial logs. - - -Programming and Debugging -************************* - -This board comes with a Cortex ETM port which facilitates tracing and debugging -using a single physical connection. In addition, it comes with sockets for -JTAG-only sessions. - -Flashing -======== - -If the correct IDC headers are installed, this board supports both J-TAG and -also the ChromiumOS servo. - -To flash using Servo V2, μServo, or Servo V4 (CCD), see the -`Chromium EC Flashing Documentation`_ for more information. - -To flash with J-TAG, install the drivers for your programmer, for example: -SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: npcx9m6f_evb - :maybe-skip-config: - :goals: build flash - -Debugging -========= - -Use JTAG/SWD with a J-Link - -References -********** -.. target-notes:: - -.. _Chromium EC Flashing Documentation: - https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/nrf21540dk_nrf52840/Kconfig b/boards/arm/nrf21540dk_nrf52840/Kconfig deleted file mode 100644 index 67b25837390d4a..00000000000000 --- a/boards/arm/nrf21540dk_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF21540 DK NRF52840 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF21540DK_NRF52840 diff --git a/boards/arm/nrf21540dk_nrf52840/Kconfig.board b/boards/arm/nrf21540dk_nrf52840/Kconfig.board deleted file mode 100644 index b2c9c86d53eb00..00000000000000 --- a/boards/arm/nrf21540dk_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF21540 DK NRF52840 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF21540DK_NRF52840 - bool "nRF21540 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig deleted file mode 100644 index 71cb76615ed547..00000000000000 --- a/boards/arm/nrf21540dk_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF21540 DK NRF52840 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF21540DK_NRF52840 - -config BOARD - default "nrf21540dk_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_NRF21540DK_NRF52840 diff --git a/boards/arm/nrf21540dk_nrf52840/doc/index.rst b/boards/arm/nrf21540dk_nrf52840/doc/index.rst deleted file mode 100644 index 617f240b0a999a..00000000000000 --- a/boards/arm/nrf21540dk_nrf52840/doc/index.rst +++ /dev/null @@ -1,236 +0,0 @@ -.. _nrf21540dk_nrf52840: - -nRF21540 DK -########### - -Overview -******** -The nRF21540 DK (PCA10112) shows possibility of the Nordic Semiconductor -nRF21540 Front End Module connected with nRF52840 ARM Cortex-M4F CPU. -The CPU provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf21540dk_nrf52840.jpg - :align: center - :alt: nRF21540 DK - - nRF21540 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the `nRF21540 website`_. -The `Nordic Semiconductor Infocenter`_ contains the processor's and front end -module's information and the datasheet. - -Hardware -******** - -The nRF52840 on the nRF21540 DK has two external oscillators. The frequency -of the slow clock is 32.768 kHz. The frequency of the main clock is 32 MHz. - -Supported Features -================== - -The nrf21540dk_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52840 Product Specification`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF21540 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (green) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -Front End Module ----------------- - -* MOSI = P1.13 -* MISO = P1.14 -* CLOCK = P1.15 -* CHIP SELECT = P0.21 -* PDN = P0.23 -* MODE = P0.17 -* RXEN = P0.19 -* ANTSEL = P0.20 -* TXEN = P0.22 - -Programming and Debugging -************************* - -Applications for the ``nrf21540dk_nrf52840`` board configuration can be built, -flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF21540 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf21540dk_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF21540 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts`. - -Changing UART1 pins -******************* - -The following approach can be used when an application needs to use another set -of pins for UART1: - -1. Add devicetree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep_alt: uart1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - pinctrl-0 = <&uart1_default_alt>; - /* if sleep state is not used, use /delete-property/ pinctrl-1; and - * skip the "sleep" entry. - */ - pinctrl-1 = <&uart1_sleep_alt>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -See :ref:`set-devicetree-overlays` for further details. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. -In the table 7.1.1 'aQFN73 ball assignments' select the pins marked -'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used -in under-10KHz applications. They are not suitable for 115200 speed of UART. - -References -********** - -.. target-notes:: - -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF21540 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF21540 -.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf -.. _nRF21540 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF21540_PS_v1.0.pdf diff --git a/boards/arm/nrf51_ble400/Kconfig.board b/boards/arm/nrf51_ble400/Kconfig.board deleted file mode 100644 index 111b359355ba0f..00000000000000 --- a/boards/arm/nrf51_ble400/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 BLE400 board configuration - -# Copyright (c) 2018 Roman Tataurov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51_BLE400 - bool "nRF51 BLE400" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_ble400/Kconfig.defconfig b/boards/arm/nrf51_ble400/Kconfig.defconfig deleted file mode 100644 index 7f453a497bd189..00000000000000 --- a/boards/arm/nrf51_ble400/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 BLE400 board configuration - -# Copyright (c) 2018 Roman Tataurov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51_BLE400 - -config BOARD - default "nrf51_ble400" - -config BT_CTLR - default BT - -endif # BOARD_NRF51_BLE400 diff --git a/boards/arm/nrf51_ble400/doc/index.rst b/boards/arm/nrf51_ble400/doc/index.rst deleted file mode 100644 index d746806faa1b51..00000000000000 --- a/boards/arm/nrf51_ble400/doc/index.rst +++ /dev/null @@ -1,223 +0,0 @@ -.. _nrf51_ble400: - -Waveshare BLE400 -################# - -Overview -******** - -BLE400 is a motherboard designed for BLE Bluetooth 2.4G Wireless Module. Used together with core board -- Core51822. - -Supported Features -================== - -Motherboard ------------- - -- Onboard battery holder, multi power supplies are available -- All the IOs are accessible for easy expansion -- Integrates CP2102 for debugging -- LEDs and user keys, compatible with other official boards, easy to use - -Core board ----------- - -- Onboard chip: nRF51822 -- Communication distance (open outdoor 1M data rate): 30m -- Frequency range: 2.4GHz -- Operating voltage: 2.0V ~ 3.6V -- Operating temperature: -40℃ ~ 85℃ -- Expansion pinheader: all the I/Os except P0.26 and P0.27 -- Pinheader pitch: 2.00mm -- Antenna: onboard antenna - -Features -======== - -- 2.4 GHz multiprotocol RF transceiver -- ARM® Cortex™-M0 32 bit processor -- 128 bit AES HW encryption -- 256kB flash & 32kB RAM -- Programmable Peripheral Interconnect (PPI) -- Digital interfaces: SPI, I2C, UART -- 10 bit ADC -- Programmable output power: -20 to +4 dBm -- Independent application development and protocol stack -- Fully compatible with NRF24L series -- Pinout compatible with NRF51xxx series -- Global separate power management -- Operating voltage: 1.8 V ~ 3.6 V - -Revision History -================ - -Core board ----------- - -In June of 2015, Core51822 and its variant, Core51822 (B), upgraded the onboard chip to Rev3 (nRF51822_QFAC) that features 32kB RAM. - -.. image:: img/Core51822-Compare.jpg - :align: center - :alt: Compare - -Top: Core51822 -Bottom: Core51822 (B) - -Connections and IOs -==================== - -Motherboard ------------- - -.. image:: img/nrf51_ble400.jpg - :align: center - :alt: BLE400 - -1. Wireless module connector: for easily connecting modules like Core51822 -2. MCU pins expansion connector -3. I2C interface -4. SPI interface -5. 5V/3.3V power input/output: usually used as power output, also common-grounding with other user board -6. USB connector: USB TO UART via onboard converter CP2102 -7. Debugging interface -8. UART interface -9. Battery holder -10. User LEDs -11. User keys -12. Reset button -13. CP2102 -14. USB TO UART jumper -15. LEDs & Keys jumper - -Core board ----------- - -.. image:: img/Core51822-pin.jpg - :align: center - :alt: Core board pinout - -BLE400 dimensions -================= - -.. image:: img/BLE400-size.jpg - :align: center - :alt: BLE400 size - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.18 -* LED1 (red) = P0.19 -* LED2 (red) = P0.20 -* LED3 (red) = P0.21 -* LED4 (red) = P0.22 -* SUSPEND = SUSPEND -* RXD1 = P0.9 -* TXD1 = P0.11 - -Push buttons ------------- - -* KEY1 = P0.16 -* KEY2 = P0.17 -* RESET = SWDIO - -I2C ---- - -* SMBA = P0.02 -* SCL = P0.01 -* SDA = P0.00 - -SPI ---- - -* NSS = P0.30 -* SCK = P0.25 -* MOSI = P0.24 -* MISO = P0.23 - -USART1 ------- - -* RX = P0.05 -* TX = P0.06 -* CTS = P0.07 -* RTS = P0.12 - -UART (USB) ----------- - -* RX = P0.9 -* TX = P0.11 -* CTS = P0.8 -* RTS = P0.10 - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF51 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf51_ble400 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF51 DK -******************************************** - -There are samples below that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -- :zephyr:code-sample:`blinky` -- :zephyr:code-sample:`button` -- :zephyr:code-sample:`fade-led` -- :zephyr:code-sample:`multi-thread-blinky` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf51_ble400/nrf51_ble400.dts`. - -References -********** - -.. target-notes:: - -.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Waveshare Wiki BLE400: https://www.waveshare.com/wiki/BLE400 -.. _Waveshare WiKi Core51822: https://www.waveshare.com/wiki/Core51822 -.. _User manual: https://www.waveshare.com/w/upload/b/b7/NRF51822-Eval-Kit-UserManual-EN.pdf -.. _Schematic: https://www.waveshare.com/w/upload/1/1b/BLE400-Schematic.pdf -.. _Code samples: https://www.waveshare.com/w/upload/5/53/NRF51822-Code.7z -.. _Core board schematics: https://www.waveshare.com/w/upload/5/57/Core51822-Schematic.pdf diff --git a/boards/arm/nrf51_ble400/nrf51_ble400_defconfig b/boards/arm/nrf51_ble400/nrf51_ble400_defconfig deleted file mode 100644 index 34fd08c47d5606..00000000000000 --- a/boards/arm/nrf51_ble400/nrf51_ble400_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51_BLE400=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_blenano/Kconfig.board b/boards/arm/nrf51_blenano/Kconfig.board deleted file mode 100644 index a708a1ac5df962..00000000000000 --- a/boards/arm/nrf51_blenano/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 BLENANO board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51_BLENANO - bool "nRF51 BLENANO" - depends on SOC_NRF51822_QFAA diff --git a/boards/arm/nrf51_blenano/Kconfig.defconfig b/boards/arm/nrf51_blenano/Kconfig.defconfig deleted file mode 100644 index 57a6b286d4df8d..00000000000000 --- a/boards/arm/nrf51_blenano/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 BLENANO board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51_BLENANO - -config BOARD - default "nrf51_blenano" - -config BT_CTLR - default BT - -endif # BOARD_NRF51_BLENANO diff --git a/boards/arm/nrf51_blenano/nrf51_blenano_defconfig b/boards/arm/nrf51_blenano/nrf51_blenano_defconfig deleted file mode 100644 index 7bd3f7c6736055..00000000000000 --- a/boards/arm/nrf51_blenano/nrf51_blenano_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAA=y -CONFIG_BOARD_NRF51_BLENANO=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_vbluno51/Kconfig.board b/boards/arm/nrf51_vbluno51/Kconfig.board deleted file mode 100644 index d0e686662a4a1b..00000000000000 --- a/boards/arm/nrf51_vbluno51/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51-VBLUNO51 board configuration - -# Copyright (c) 2017 VNG IoT Lab Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51_VBLUNO51 - bool "nRF51 VBLUno51 BLE" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_vbluno51/Kconfig.defconfig b/boards/arm/nrf51_vbluno51/Kconfig.defconfig deleted file mode 100644 index bcb1c0d21602ab..00000000000000 --- a/boards/arm/nrf51_vbluno51/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 VBLUno51 board configuration - -# Copyright (c) 2017 VNG IoT Lab Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51_VBLUNO51 - -config BOARD - default "nrf51_vbluno51" - -config BT_CTLR - default BT - -endif # BOARD_NRF51_VBLUNO51 diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51_defconfig b/boards/arm/nrf51_vbluno51/nrf51_vbluno51_defconfig deleted file mode 100644 index 09836ecc779515..00000000000000 --- a/boards/arm/nrf51_vbluno51/nrf51_vbluno51_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51_VBLUNO51=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51dk_nrf51422/Kconfig.board b/boards/arm/nrf51dk_nrf51422/Kconfig.board deleted file mode 100644 index 0d93e231820064..00000000000000 --- a/boards/arm/nrf51dk_nrf51422/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 DK NRF51422 board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51DK_NRF51422 - bool "nRF51 DK NRF51422" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dk_nrf51422/Kconfig.defconfig b/boards/arm/nrf51dk_nrf51422/Kconfig.defconfig deleted file mode 100644 index 54d65d88a5e94e..00000000000000 --- a/boards/arm/nrf51dk_nrf51422/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 DK NRF51422 board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51DK_NRF51422 - -config BOARD - default "nrf51dk_nrf51422" - -config BT_CTLR - default BT - -endif # BOARD_NRF51DK_NRF51422 diff --git a/boards/arm/nrf51dk_nrf51422/doc/index.rst b/boards/arm/nrf51dk_nrf51422/doc/index.rst deleted file mode 100644 index 5a3b11bf17acf2..00000000000000 --- a/boards/arm/nrf51dk_nrf51422/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _nrf51dk_nrf51422: - -nRF51 DK -######## - -Overview -******** - -The nRF51 Development Kit (PCA10028) hardware provides support for the Nordic -Semiconductor nRF51422 ARM Cortex-M0 CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf51dk_nrf51422.jpg - :align: center - :alt: nRF51 DK - - nRF51 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF51 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF51 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 16 MHz. - -Supported Features -================== - -The nrf51dk_nrf51422 board configuration supports the following nRF51 -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF51 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF51 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.21 -* LED2 (green) = P0.22 -* LED3 (green) = P0.23 -* LED4 (green) = P0.24 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.17 -* BUTTON2 = SW2 = P0.18 -* BUTTON3 = SW3 = P0.19 -* BUTTON4 = SW4 = P0.20 -* BOOT = SW5 = boot/reset - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF51 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf51dk_nrf51422 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF51 DK -******************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts`. - -References -********** - -.. target-notes:: - -.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts b/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts deleted file mode 100644 index cf18877f017f81..00000000000000 --- a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.dts +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf51dk_nrf51422-pinctrl.dtsi" -#include - -/ { - model = "Nordic nRF51 DK NRF51422"; - compatible = "nordic,nrf51-dk-nrf51422"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; - }; - led1: led_1 { - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - label = "Green LED 1"; - }; - led2: led_2 { - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - label = "Green LED 2"; - }; - led3: led_3 { - gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; - label = "Green LED 3"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 0"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 1"; - zephyr,code = ; - }; - button2: button_2 { - gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 2"; - zephyr,code = ; - }; - button3: button_3 { - gpios = <&gpio0 20 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 3"; - zephyr,code = ; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - pwm-led0 = &pwm_led0; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - bootloader-led0 = &led0; - mcuboot-button0 = &button0; - mcuboot-led0 = &led0; - watchdog0 = &wdt0; - }; -}; - -&sw_pwm { - status ="okay"; - channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; - clock-prescaler = <8>; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&adc { - status = "okay"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c0 { - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c1 { - /* Cannot be used together with spi1. */ - /* status = "okay"; */ - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi0 { - /* Cannot be used together with i2c0. */ - /* status = "okay"; */ - pinctrl-0 = <&spi0_default>; - pinctrl-1 = <&spi0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi1 { - compatible = "nordic,nrf-spi"; - status = "okay"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x8000>; - }; - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x1b000>; - }; - slot1_partition: partition@23000 { - label = "image-1"; - reg = <0x00023000 0x1b000>; - }; - storage_partition: partition@3e000 { - label = "storage"; - reg = <0x0003e000 0x00002000>; - }; - }; -}; diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.yaml b/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.yaml deleted file mode 100644 index 8b521b57d908ca..00000000000000 --- a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: nrf51dk_nrf51422 -name: nRF51-DK-NRF51422 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 256 -supported: - - adc - - ble - - counter - - gpio - - i2c - - nvs - - pwm - - spi - - watchdog -testing: - ignore_tags: - - net -vendor: nordic diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422_defconfig b/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422_defconfig deleted file mode 100644 index 7cd29568889af3..00000000000000 --- a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51DK_NRF51422=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51dongle_nrf51422/Kconfig.board b/boards/arm/nrf51dongle_nrf51422/Kconfig.board deleted file mode 100644 index 733c12ea3a66fd..00000000000000 --- a/boards/arm/nrf51dongle_nrf51422/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF51 Dongle NRF51422 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF51DONGLE_NRF51422 - bool "nRF51 Dongle NRF51422" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dongle_nrf51422/Kconfig.defconfig b/boards/arm/nrf51dongle_nrf51422/Kconfig.defconfig deleted file mode 100644 index baad053bacaadc..00000000000000 --- a/boards/arm/nrf51dongle_nrf51422/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF51 Dongle NRF51422 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF51DONGLE_NRF51422 - -config BOARD - default "nrf51dongle_nrf51422" - -config BT_CTLR - default BT - -endif # BOARD_NRF51DONGLE_NRF51422 diff --git a/boards/arm/nrf51dongle_nrf51422/doc/index.rst b/boards/arm/nrf51dongle_nrf51422/doc/index.rst deleted file mode 100644 index 1f73d1f9e08c7b..00000000000000 --- a/boards/arm/nrf51dongle_nrf51422/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _nrf51dongle_nrf51422: - -nRF51 Dongle -############ - -Overview -******** - -The nRF51 Dongle (PCA10031) hardware provides support for the Nordic -Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf51dongle_nrf51422.jpg - :align: center - :alt: nRF51 Dongle - - nRF51 Dongle (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF51 Dongle website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF51 Dongle has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 16 MHz. - -Supported Features -================== - -The nrf51dongle_nrf51422 board configuration supports the following nRF51 -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF51 Dongle website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF51 Dongle hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.21 -* LED1 (green) = P0.22 -* LED1 (blue) = P0.23 - -Push buttons ------------- - -* BOOT = SW1 = boot/reset - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF51 Dongle -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf51dongle_nrf51422 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Testing the LEDs on the nRF51 Dongle -************************************ - -Build and flash the :zephyr:code-sample:`blinky` sample to test that the onboard LED -is working properly with Zephyr. - -References -********** - -.. target-notes:: - -.. _nRF51 Dongle website: http://www.nordicsemi.com/eng/Products/nRF51-Dongle -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.dts b/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.dts deleted file mode 100644 index 59751e808409a2..00000000000000 --- a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.dts +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2018 Nordic Semiconductor ASA. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf51dongle_nrf51422-pinctrl.dtsi" - -/ { - model = "Nordic nRF51 Dongle NRF51422"; - compatible = "nordic,nrf51-dongle-nrf51422"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led0_red: led_0 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "Red LED 0"; - }; - led0_green: led_1 { - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; - }; - led0_blue: led_2 { - gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; - label = "Blue LED 0"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0_red; - led1 = &led0_green; - led2 = &led0_blue; - pwm-led0 = &pwm_led0; - watchdog0 = &wdt0; - }; -}; - -&sw_pwm { - status ="okay"; - channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; - clock-prescaler = <8>; -}; - -&gpiote { - status ="okay"; -}; - -&gpio0 { - status ="okay"; -}; - -&adc { - status ="okay"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x8000>; - }; - slot0_partition: partition@8000 { - label = "image-0"; - reg = <0x00008000 0x1b000>; - }; - slot1_partition: partition@23000 { - label = "image-1"; - reg = <0x00023000 0x1b000>; - }; - storage_partition: partition@3e000 { - label = "storage"; - reg = <0x0003e000 0x00002000>; - }; - }; -}; diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.yaml b/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.yaml deleted file mode 100644 index 906fce5febf3bf..00000000000000 --- a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf51dongle_nrf51422 -name: nRF51-Dongle-nRF51422 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 32 -flash: 256 -supported: - - ble - - nvs -vendor: nordic diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422_defconfig b/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422_defconfig deleted file mode 100644 index c937ab159c8a59..00000000000000 --- a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_NRF51DONGLE_NRF51422=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52832_mdk/Kconfig.board b/boards/arm/nrf52832_mdk/Kconfig.board deleted file mode 100644 index 1707bf292164b6..00000000000000 --- a/boards/arm/nrf52832_mdk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52832-MDK board configuration - -# Copyright (c) 2018 makerdiary.com. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52832_MDK - bool "nRF52832-MDK" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52832_mdk/Kconfig.defconfig b/boards/arm/nrf52832_mdk/Kconfig.defconfig deleted file mode 100644 index 0e5c3fd78174c8..00000000000000 --- a/boards/arm/nrf52832_mdk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52832-MDK board configuration - -# Copyright (c) 2018 makerdiary.com. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52832_MDK - -config BOARD - default "nrf52832_mdk" - -config BT_CTLR - default BT - -endif # BOARD_NRF52832_MDK diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk_defconfig b/boards/arm/nrf52832_mdk/nrf52832_mdk_defconfig deleted file mode 100644 index 732b02a3610f33..00000000000000 --- a/boards/arm/nrf52832_mdk/nrf52832_mdk_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52832_MDK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52833dk_nrf52820/CMakeLists.txt b/boards/arm/nrf52833dk_nrf52820/CMakeLists.txt deleted file mode 100644 index 413dee8fe2a044..00000000000000 --- a/boards/arm/nrf52833dk_nrf52820/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52833dk_nrf52820 board mirrors the nRF52833 DK hardware. This -# needs to be considered by certain system initialization functionality -# residing in system_nrf52820.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52833) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52833dk_nrf52820/Kconfig b/boards/arm/nrf52833dk_nrf52820/Kconfig deleted file mode 100644 index 03f71c60aea1ac..00000000000000 --- a/boards/arm/nrf52833dk_nrf52820/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52833DK nRF52820 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52833DK_NRF52820 diff --git a/boards/arm/nrf52833dk_nrf52820/Kconfig.board b/boards/arm/nrf52833dk_nrf52820/Kconfig.board deleted file mode 100644 index 5be8867d804199..00000000000000 --- a/boards/arm/nrf52833dk_nrf52820/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52833DK nRF52820 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52833DK_NRF52820 - bool "nRF52833 DK NRF52820" - depends on SOC_NRF52820_QDAA diff --git a/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig b/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig deleted file mode 100644 index 705821fa71d2a0..00000000000000 --- a/boards/arm/nrf52833dk_nrf52820/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52833DK nRF52820 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52833DK_NRF52820 - -config BOARD - default "nrf52833dk_nrf52820" - -config BT_CTLR - default BT - -endif # BOARD_NRF52833DK_NRF52820 diff --git a/boards/arm/nrf52833dk_nrf52820/board.cmake b/boards/arm/nrf52833dk_nrf52820/board.cmake deleted file mode 100644 index f7046fc0a1fa6e..00000000000000 --- a/boards/arm/nrf52833dk_nrf52820/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52833_xxAA" "--speed=4000") -board_runner_args(pyocd "--target=nrf52820" "--frequency=4000000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52833dk_nrf52820/doc/index.rst b/boards/arm/nrf52833dk_nrf52820/doc/index.rst deleted file mode 100644 index e652e8735eb189..00000000000000 --- a/boards/arm/nrf52833dk_nrf52820/doc/index.rst +++ /dev/null @@ -1,23 +0,0 @@ -.. _nrf52833dk_nrf52820: - -nRF52820 emulation on nRF52833 DK -################################# - -Overview -******** - -The nrf52833dk_nrf52820 board is a modified version of the -:ref:`nrf52833dk_nrf52833` that enforces the limitations imposed by the nRF52820 -IC, which is a variant of the original nRF52833. Since Nordic does not offer a -development kit for the nRF52820 you can use this board to develop for this IC -while using the nRF52833 Development Kit (PCA10100). - -See :ref:`nrf52833dk_nrf52833` for more information about the development board -and `nRF52820 website`_ for the official reference on the IC itself. - -References -********** - -.. target-notes:: - -.. _nRF52820 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52820 diff --git a/boards/arm/nrf52833dk_nrf52833/Kconfig b/boards/arm/nrf52833dk_nrf52833/Kconfig deleted file mode 100644 index 4b620ad55570b5..00000000000000 --- a/boards/arm/nrf52833dk_nrf52833/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52833 DK NRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52833DK_NRF52833 diff --git a/boards/arm/nrf52833dk_nrf52833/Kconfig.board b/boards/arm/nrf52833dk_nrf52833/Kconfig.board deleted file mode 100644 index 11ab4befc97851..00000000000000 --- a/boards/arm/nrf52833dk_nrf52833/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52833 DK NRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52833DK_NRF52833 - bool "NRF52833 DK NRF52833" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig b/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig deleted file mode 100644 index 6ec17b788646be..00000000000000 --- a/boards/arm/nrf52833dk_nrf52833/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52833 DK NRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52833DK_NRF52833 - -config BOARD - default "nrf52833dk_nrf52833" - -config BT_CTLR - default BT - -endif # BOARD_NRF52833DK_NRF52833 diff --git a/boards/arm/nrf52833dk_nrf52833/doc/index.rst b/boards/arm/nrf52833dk_nrf52833/doc/index.rst deleted file mode 100644 index 126b1266d52f5b..00000000000000 --- a/boards/arm/nrf52833dk_nrf52833/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _nrf52833dk_nrf52833: - -nRF52833 DK -########### - -Overview -******** - -The nRF52833 Development Kit (PCA10100) hardware provides -support for the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -More information about the board can be found at the -`nRF52833 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF52833 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf52833dk_nrf52833 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52833 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52833 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (green) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -Programming and Debugging -************************* - -Applications for the ``nrf52833dk_nrf52833`` board configuration can be built, -flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52833dk_nrf52833 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF52833 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts`. - -Changing UART1 pins -******************* - -The following approach can be used when an application needs to use another set -of pins for UART1: - -1. Add devicetree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep_alt: uart1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - pinctrl-0 = <&uart1_default_alt>; - /* if sleep state is not used, use /delete-property/ pinctrl-1; and - * skip the "sleep" entry. - */ - pinctrl-1 = <&uart1_sleep_alt>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -See :ref:`set-devicetree-overlays` for further details. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `nRF52833 Product Specification`_, chapter 7 'Hardware and Layout'. -In the table 7.1.1 'aQFN73 ball assignments' select the pins marked -'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used -in under-10KHz applications. They are not suitable for 115200 speed of UART. - -References -********** - -.. target-notes:: - -.. _nRF52833 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF52833 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52833_OPS_v0.7.pdf diff --git a/boards/arm/nrf52840_blip/Kconfig.board b/boards/arm/nrf52840_blip/Kconfig.board deleted file mode 100644 index 12236998c6deaf..00000000000000 --- a/boards/arm/nrf52840_blip/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Electronut Labs Blip board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_BLIP - bool "Electronut Labs Blip" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_blip/Kconfig.defconfig b/boards/arm/nrf52840_blip/Kconfig.defconfig deleted file mode 100644 index ab5424a1dd01f8..00000000000000 --- a/boards/arm/nrf52840_blip/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Electronut Labs Blip board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_BLIP - -config BOARD - default "nrf52840_blip" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_BLIP diff --git a/boards/arm/nrf52840_blip/doc/index.rst b/boards/arm/nrf52840_blip/doc/index.rst deleted file mode 100644 index e9dc8ad939b667..00000000000000 --- a/boards/arm/nrf52840_blip/doc/index.rst +++ /dev/null @@ -1,196 +0,0 @@ -.. _nrf52840_blip: - -Electronut Labs Blip -#################### - -Overview -******** - -The Electronut Labs Blip hardware provides support for the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52840_blip.jpg - :align: center - :alt: Electronut Labs Blip - - Electronut Labs Blip (Credit: Electronut Labs) - -More information about the board is available at https://github.com/electronut/ElectronutLabs-blip. - -Hardware -******** - -Blip has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf52840_blip board configuration supports the following -hardware features currently: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (red) = P0.14 -* LED3 (blue) = P0.15 - -Push buttons ------------- - -* BUTTON1 = SW1 = P1.07 -* Reset = SW5 = P0.18 (can be used as GPIO also) - -UART ----- - -BMP does not support hardware flow control, so only RX/TX pins are connected. - -* TX = P0.6 -* RX = P0.8 - -I2C ---- - -I2C pins connected to onboard sensors: - -* SDA = P0.12 -* SCL = P0.11 - -SPI ---- - -* SCK = P0.25 -* MOSI = P1.02 -* MISO = P0.24 - -MicroSD is connected to these pins, and CS pin is connected to P0.17. - -Programming and Debugging -************************* - -Applications for the ``nrf52840_blip`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); The onboard Black Magic -Probe debugger presents itself as two USB-serial ports. On Linux, -they may come up as ``/dev/ttyACM0`` and ``/dev/ttyACM1``. The first -one of these (``/dev/ttyACM0`` here) is the debugger port. -GDB can directly connect to this port without requiring a GDB server by specifying -``target external /dev/ttyACM0``. The second port acts as a -serial port, connected to the SoC. - -Flashing -======== - -Applications are flashed and run as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the serial port of Black Magic Probe. -For example, under Linux, :code:`/dev/ttyACM1`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52840_blip - :goals: build flash - -Debugging -========= - -Debug and attach configurations are available using Black Magic Probe, and -``ninja debug``, or ``ninja attach`` (or with ``make``) are available. - -NOTE: You may need to press the reset button once after using ``ninja flash`` -to start executing the code. (not required with ``debug`` or ``attach``) - - -Testing the LEDs and buttons in the nRF52840 PDK -************************************************ - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52840_blip/nrf52840_blip.dts`. - - -References -********** - -.. target-notes:: - -.. _Electronut Labs website: https://electronut.in -.. _Store link: https://www.tindie.com/stores/ElectronutLabs/ -.. _Blip website: https://github.com/electronut/ElectronutLabs-blip -.. _Schematic: https://github.com/electronut/ElectronutLabs-blip/blob/master/blip_v0.3_schematic.pdf -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ -.. _Black Magic Probe website: https://github.com/blacksphere/blackmagic diff --git a/boards/arm/nrf52840_blip/nrf52840_blip_defconfig b/boards/arm/nrf52840_blip/nrf52840_blip_defconfig deleted file mode 100644 index 526283ef3d483b..00000000000000 --- a/boards/arm/nrf52840_blip/nrf52840_blip_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_BLIP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840_mdk/Kconfig.board b/boards/arm/nrf52840_mdk/Kconfig.board deleted file mode 100644 index 81f9b3a88f75fa..00000000000000 --- a/boards/arm/nrf52840_mdk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840-MDK board configuration - -# Copyright (c) 2018 makerdiary.com -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_MDK - bool "NRF52840-MDK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk/Kconfig.defconfig b/boards/arm/nrf52840_mdk/Kconfig.defconfig deleted file mode 100644 index 8c321634996dde..00000000000000 --- a/boards/arm/nrf52840_mdk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840-MDK board configuration - -# Copyright (c) 2018 makerdiary.com -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_MDK - -config BOARD - default "nrf52840_mdk" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_MDK diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk_defconfig b/boards/arm/nrf52840_mdk/nrf52840_mdk_defconfig deleted file mode 100644 index 76c73a15a048d2..00000000000000 --- a/boards/arm/nrf52840_mdk/nrf52840_mdk_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_MDK=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.board b/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.board deleted file mode 100644 index 975e4bd9e9e671..00000000000000 --- a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# nRF52840 MDK USB Dongle board configuration - -# Copyright (c) 2022 Nikola Trifunovic -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_MDK_USB_DONGLE - bool "nRF52840 MDK USB DONGLE" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig b/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig deleted file mode 100644 index 7fb8a5fde94c6e..00000000000000 --- a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# nRF52840 MDK USB Dongle board configuration -# -# Copyright (c) 2018 Nordic Semiconductor ASA -# -# Copyright (c) 2022 Nikola Trifunovic -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_MDK_USB_DONGLE - -config BOARD - default "nrf52840_mdk_usb_dongle" - -# To let the nRF5 bootloader load an application, the application -# must be linked after Nordic MBR, that is factory-programmed on the board. - -# Nordic nRF5 bootloader exists outside of the partitions specified in the -# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR. - -# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION -# which will make it link into the correct partition specified in DTS file, -# so no override is necessary. - -config FLASH_LOAD_OFFSET - default 0x1000 - depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION - -if USB_DEVICE_STACK - -# Enable UART driver, needed for CDC ACM -config SERIAL - default y - -endif # USB_DEVICE_STACK - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_MDK_USB_DONGLE diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig b/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig deleted file mode 100644 index 63decf69707d83..00000000000000 --- a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_MDK_USB_DONGLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Console -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y diff --git a/boards/arm/nrf52840_papyr/Kconfig.board b/boards/arm/nrf52840_papyr/Kconfig.board deleted file mode 100644 index 574b885163e7f2..00000000000000 --- a/boards/arm/nrf52840_papyr/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Electronut Labs Papyr board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840_PAPYR - bool "NRF52840 PAPYR" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_papyr/Kconfig.defconfig b/boards/arm/nrf52840_papyr/Kconfig.defconfig deleted file mode 100644 index 339d481404b4e9..00000000000000 --- a/boards/arm/nrf52840_papyr/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Electronut Labs Papyr board configuration - -# Copyright (c) 2018 Electronut Labs -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840_PAPYR - -config BOARD - default "nrf52840_papyr" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840_PAPYR diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr_defconfig b/boards/arm/nrf52840_papyr/nrf52840_papyr_defconfig deleted file mode 100644 index 9d0226eed01ac5..00000000000000 --- a/boards/arm/nrf52840_papyr/nrf52840_papyr_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840_PAPYR=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840dk_nrf52811/CMakeLists.txt b/boards/arm/nrf52840dk_nrf52811/CMakeLists.txt deleted file mode 100644 index d07679ce3f45b6..00000000000000 --- a/boards/arm/nrf52840dk_nrf52811/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA - -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52840dk_nrf52811 board mirrors the nRF52840 DK hardware. This -# needs to be considered by certain system initialization functionality -# residing in system_nrf52811.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52840) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52840dk_nrf52811/Kconfig b/boards/arm/nrf52840dk_nrf52811/Kconfig deleted file mode 100644 index 5d25d66f11ebcb..00000000000000 --- a/boards/arm/nrf52840dk_nrf52811/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52840 DK NRF52811 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52840DK_NRF52811 diff --git a/boards/arm/nrf52840dk_nrf52811/Kconfig.board b/boards/arm/nrf52840dk_nrf52811/Kconfig.board deleted file mode 100644 index 5eefb967cd7a34..00000000000000 --- a/boards/arm/nrf52840dk_nrf52811/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840 DK NRF52811 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840DK_NRF52811 - bool "nRF52840 DK NRF52811" - depends on SOC_NRF52811_QFAA diff --git a/boards/arm/nrf52840dk_nrf52811/Kconfig.defconfig b/boards/arm/nrf52840dk_nrf52811/Kconfig.defconfig deleted file mode 100644 index 2d933bf12b3d17..00000000000000 --- a/boards/arm/nrf52840dk_nrf52811/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840 DK NRF52811 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DK_NRF52811 - -config BOARD - default "nrf52840dk_nrf52811" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840DK_NRF52811 diff --git a/boards/arm/nrf52840dk_nrf52811/board.cmake b/boards/arm/nrf52840dk_nrf52811/board.cmake deleted file mode 100644 index af01781dd29e83..00000000000000 --- a/boards/arm/nrf52840dk_nrf52811/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA - -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52840dk_nrf52811/doc/index.rst b/boards/arm/nrf52840dk_nrf52811/doc/index.rst deleted file mode 100644 index b33d1caea4e0ce..00000000000000 --- a/boards/arm/nrf52840dk_nrf52811/doc/index.rst +++ /dev/null @@ -1,24 +0,0 @@ -.. _nrf52840dk_nrf52811: - -nRF52811 emulation on nRF52840 DK -################################# - -Overview -******** - -The nrf52840dk_nrf52811 board is a modified version of the -:ref:`nrf52840dk_nrf52840` that enforces the limitations imposed by the nRF52811 -IC, which is a variant of the original nRF52840. Since Nordic does not offer a -development kit for the nRF52811 you can use this board to develop for this IC -while using the nRF52840 Development Kit (PCA10056). - -See :ref:`nrf52840dk_nrf52840` for more information about the development board -and `nRF52811 website`_ for the official reference on the IC itself. - - -References -********** - -.. target-notes:: - -.. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811 diff --git a/boards/arm/nrf52840dk_nrf52840/Kconfig b/boards/arm/nrf52840dk_nrf52840/Kconfig deleted file mode 100644 index 037d1dc9216d07..00000000000000 --- a/boards/arm/nrf52840dk_nrf52840/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# nRF52840 DK NRF52840 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DK_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_NRF52840DK_NRF52840 diff --git a/boards/arm/nrf52840dk_nrf52840/Kconfig.board b/boards/arm/nrf52840dk_nrf52840/Kconfig.board deleted file mode 100644 index dcfdb550a43619..00000000000000 --- a/boards/arm/nrf52840dk_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840 DK NRF52840 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840DK_NRF52840 - bool "nRF52840 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig deleted file mode 100644 index 31850c65937546..00000000000000 --- a/boards/arm/nrf52840dk_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52840 DK NRF52840 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DK_NRF52840 - -config BOARD - default "nrf52840dk_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_NRF52840DK_NRF52840 diff --git a/boards/arm/nrf52840dk_nrf52840/doc/index.rst b/boards/arm/nrf52840dk_nrf52840/doc/index.rst deleted file mode 100644 index 9734af91e7f7f9..00000000000000 --- a/boards/arm/nrf52840dk_nrf52840/doc/index.rst +++ /dev/null @@ -1,224 +0,0 @@ -.. _nrf52840dk_nrf52840: - -nRF52840 DK -########### - -Overview -******** - -The nRF52840 Development Kit (PCA10056) hardware provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52840dk_nrf52840.jpg - :align: center - :alt: nRF52840 DK - - nRF52840 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the `nRF52840 DK website`_. -The `Nordic Semiconductor Infocenter`_ contains the processor's information -and the datasheet. - - -Hardware -******** - -nRF52840 DK has two external oscillators. The frequency of the slow clock -is 32.768 kHz. The frequency of the main clock is 32 MHz. - -Supported Features -================== - -The nrf52840dk_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52840 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52840 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (green) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -Programming and Debugging -************************* - -Applications for the ``nrf52840dk_nrf52840`` board configuration can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52840 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52840dk_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF52840 DK -*********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts`. - -Changing UART1 pins -******************* - -The following approach can be used when an application needs to use another set -of pins for UART1: - -1. Add devicetree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default_alt: uart1_default_alt { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep_alt: uart1_sleep_alt { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - pinctrl-0 = <&uart1_default_alt>; - /* if sleep state is not used, use /delete-property/ pinctrl-1; and - * skip the "sleep" entry. - */ - pinctrl-1 = <&uart1_sleep_alt>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -See :ref:`set-devicetree-overlays` for further details. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. -In the table 7.1.1 'aQFN73 ball assignments' select the pins marked -'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used -in under-10KHz applications. They are not suitable for 115200 speed of UART. - -References -********** - -.. target-notes:: - -.. _nRF52840 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/arm/nrf52840dongle_nrf52840/Kconfig b/boards/arm/nrf52840dongle_nrf52840/Kconfig deleted file mode 100644 index d07ac16faef6e0..00000000000000 --- a/boards/arm/nrf52840dongle_nrf52840/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# nRF52840 Dongle NRF52840 board configuration - -# Copyright (c) 2018-2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DONGLE_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -config BOARD_HAS_NRF5_BOOTLOADER - bool "Board has nRF5 bootloader" - default y - help - If selected, applications are linked so that they can be loaded by Nordic - nRF5 bootloader. - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - -endif # BOARD_NRF52840DONGLE_NRF52840 diff --git a/boards/arm/nrf52840dongle_nrf52840/Kconfig.board b/boards/arm/nrf52840dongle_nrf52840/Kconfig.board deleted file mode 100644 index 463bd53b38180f..00000000000000 --- a/boards/arm/nrf52840dongle_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52840 Dongle NRF52840 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52840DONGLE_NRF52840 - bool "nRF52840 DONGLE NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig b/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig deleted file mode 100644 index 76c7559be8d762..00000000000000 --- a/boards/arm/nrf52840dongle_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,86 +0,0 @@ -# nRF52840 Dongle NRF52840 board configuration -# -# Copyright (c) 2018-2023 Nordic Semiconductor ASA -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52840DONGLE_NRF52840 - -config BOARD - default "nrf52840dongle_nrf52840" - -# To let the nRF5 bootloader load an application, the application -# must be linked after Nordic MBR, that is factory-programmed on the board. - -# Nordic nRF5 bootloader exists outside of the partitions specified in the -# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application -# correctly, after Nordic MBR. - -# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION -# which will make it link into the correct partition specified in DTS file, -# the offset is applied here so that the full partition size can be used when -# the bootloader Kconfig option has been disabled. - -config FLASH_LOAD_OFFSET - default 0x1000 - depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) - -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default SERIAL - -config CONSOLE - default y - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT && CONSOLE - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR -endchoice - -# Wait 4000ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 4000 - -endif # LOG - -if USB_DEVICE_STACK - -# Enable UART driver, needed for CDC ACM -config SERIAL - default y - -endif # USB_DEVICE_STACK - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -config BT_CTLR - default BT - -endif # BOARD_NRF52840DONGLE_NRF52840 diff --git a/boards/arm/nrf52840dongle_nrf52840/doc/index.rst b/boards/arm/nrf52840dongle_nrf52840/doc/index.rst deleted file mode 100644 index 6cfe7329d2cdac..00000000000000 --- a/boards/arm/nrf52840dongle_nrf52840/doc/index.rst +++ /dev/null @@ -1,348 +0,0 @@ -.. _nrf52840dongle_nrf52840: - -nRF52840 Dongle -############### - -Overview -******** - -The nRF52840 Dongle (PCA10059) hardware provides support for the Nordic -Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52840dongle_nrf52840.jpg - :align: center - :alt: nRF52840 Dongle - - nRF52840 Dongle - -More information about the board can be found at the -`nRF52840 Dongle website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -The ``nrf52840dongle_nrf52840`` has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The ``nrf52840dongle_nrf52840`` board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52840 Dongle website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52840 Dongle board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (green) = P0.6 -* LED1 (red) = P0.8 -* LED1 (green) = P1.9 -* LED1 (blue) = P0.12 - -Push buttons ------------- - -* BUTTON1 = SW1 = P1.6 -* RESET = SW2 = P0.18 - -Programming and Debugging -************************* - -Applications for the ``nrf52840dongle_nrf52840`` board configuration can be -built in the usual way (see :ref:`build_an_application` for more details). - -Flashing -======== - -The board supports the following programming options: - -1. Using the built-in bootloader only -2. Using MCUboot in serial recovery mode -3. Using an external :ref:`debug probe ` - -These instructions use the :ref:`west ` tool and assume you are in the -root directory of your :term:`west installation`. - -Option 1: Using the Built-In Bootloader Only --------------------------------------------- - -The board is factory-programmed with Nordic's bootloader from Nordic's nRF5 -SDK. With this option, you'll use Nordic's `nrfutil`_ program to create -firmware packages supported by this bootloader and flash them to the -device. Make sure ``nrfutil`` is installed before proceeding. - -#. Reset the board into the Nordic bootloader by pressing the RESET button. - - The push button is on the far side of the board from the USB connector. Note - that the button does not face up. You will have to push it from the outside - in, towards the USB connector: - - .. image:: img/nRF52840_dongle_press_reset.svg - :alt: Location of RESET button and direction of push - - The red LED should start a fade pattern, signalling the bootloader is - running. - -#. Compile a Zephyr application; we'll use :zephyr:code-sample:`blinky`. - - .. zephyr-app-commands:: - :app: zephyr/samples/basic/blinky - :board: nrf52840dongle_nrf52840 - :goals: build - -#. Package the application for the bootloader using ``nrfutil``: - - .. code-block:: console - - nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ - --application build/zephyr/zephyr.hex \ - --application-version 1 blinky.zip - -#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be - something like ``COMx`` on Windows, and something else on macOS. - - .. code-block:: console - - nrfutil dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0 - - When this command exits, observe the green LED on the board blinking, - instead of the red LED used by the bootloader. - -For more information, see `Nordic Semiconductor USB DFU`_. - -Option 2: Using MCUboot in Serial Recovery Mode ------------------------------------------------ - -It is also possible to use the MCUboot bootloader with this board to flash -Zephyr applications. You need to do some one-time set-up to build and flash -MCUboot on your board. From that point on, you can build and flash other Zephyr -applications using MCUboot's serial recovery mode. This process does not -overwrite the built-in Nordic bootloader, so you can always go back to using -Option 1 later. - -Install `nrfutil`_ and `mcumgr`_ first, and make sure MCUboot's ``imgtool`` is -available for signing your binary for MCUboot as described on :ref:`west-sign`. - -Next, do the **one-time setup** to flash MCUboot. We'll assume you've cloned -the `MCUboot`_ repository into the directory ``mcuboot``, and that it is next -to the zephyr repository on your computer. - -#. Reset the board into the Nordic bootloader as described above. - -#. Compile MCUboot as a Zephyr application. - - .. zephyr-app-commands:: - :app: mcuboot/boot/zephyr - :board: nrf52840dongle_nrf52840 - :build-dir: mcuboot - :goals: build - -#. Package the application for the bootloader using ``nrfutil``: - - .. code-block:: console - - nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ - --application build/mcuboot/zephyr/zephyr.hex \ - --application-version 1 mcuboot.zip - -#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be - something like ``COMx`` on Windows, and something else on macOS. - - .. code-block:: console - - nrfutil dfu usb-serial -pkg mcuboot.zip -p /dev/ttyACM0 - -You can now flash a Zephyr application to the board using MCUboot's serial -recovery mode. We'll use the :zephyr:code-sample:`smp-svr` sample since it's ready to be -compiled for chain-loading by MCUboot (and itself supports firmware updates -over Bluetooth). - -#. Boot into MCUboot serial recovery mode by plugging the board in with the SW1 - button pressed down. See above for a picture showing where SW1 is. - - **Do not press RESET**; that will run the Nordic bootloader, which is - different than MCUboot. - - A serial port will enumerate on your board. On Windows, "MCUBOOT" should - appear under "Other Devices" in the Device Manager (in addition to the usual - ``COMx`` device). On Linux, something like - :file:`/dev/serial/by-id/usb-ZEPHYR_MCUBOOT_0.01-if00` should be created. - - If no serial port appears, try plugging it in again, making sure SW1 is - pressed. If it still doesn't appear, retry the one-time MCUboot setup. - -#. Compile ``smp_svr``. - - .. zephyr-app-commands:: - :app: zephyr/samples/subsys/mgmt/mcumgr/smp_svr - :board: nrf52840dongle_nrf52840 - :build-dir: smp_svr - :goals: build - -#. Sign ``smp_svr`` for chain-loading by MCUboot. - - .. code-block:: console - - west sign -t imgtool --bin --no-hex -d build/smp_svr \ - -B smp_svr.signed.bin -- --key mcuboot/root-rsa-2048.pem - -#. Flash the application to the MCUboot serial port using ``mcumgr``: - - .. code-block:: console - - mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' \ - image upload -e smp_svr.signed.bin - -#. Reset the device: - - .. code-block:: console - - mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' reset - -You should now be able to scan for Bluetooth devices using a smartphone or -computer. The device you just flashed will be listed with ``Zephyr`` in its -name. - -.. note:: - - This board supports building other Zephyr applications for flashing with - MCUboot in this way also. Just make sure :kconfig:option:`CONFIG_BOOTLOADER_MCUBOOT` - is set when building your application. For example, to compile blinky for - loading by MCUboot, use this: - - .. zephyr-app-commands:: - :app: zephyr/samples/basic/blinky - :board: nrf52840dongle_nrf52840 - :build-dir: blinky - :goals: build - :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y - - You can then sign and flash it using the steps above. - -Option 3: Using an External Debug Probe ---------------------------------------- - -If you have one, you can also use an external :ref:`debug probe ` -to flash and debug Zephyr applications, but you need to solder an SWD header -onto the back side of the board. - -For Segger J-Link debug probes, follow the instructions in the -:ref:`nordic_segger` page to install and configure all the necessary -software. Further information can be found in :ref:`nordic_segger_flashing`. - -Locate the DTS file for the board under: boards/arm/nrf52840dongle_nrf52840. -This file requires a small modification to use a different partition table. -Edit the include directive to include "fstab-debugger" instead of "fstab-stock". - -In addition, the Kconfig file in the same directory must be modified by setting -``BOARD_HAS_NRF5_BOOTLOADER`` to be default ``n``, otherwise the code will be -flashed with an offset. - -Then build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nrf52840dongle_nrf52840 - :goals: build flash - -Observe the LED on the board blinking. - -Debugging -========= - -The ``nrf52840dongle_nrf52840`` board does not have an on-board J-Link debug IC -as some nRF5x development boards, however, instructions from the -:ref:`nordic_segger` page also apply to this board, with the additional step -of connecting an external debugger. - -Testing the LEDs and buttons on the nRF52840 Dongle -*************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` - -You can build and program the examples to make sure Zephyr is running correctly -on your board. - - -References -********** - -.. target-notes:: - -.. _nRF52840 Dongle website: - https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle -.. _Nordic Semiconductor Infocenter: - https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html -.. _Nordic Semiconductor USB DFU: - https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v15.2.0%2Fsdk_app_serial_dfu_bootloader.html -.. _nrfutil: - https://github.com/NordicSemiconductor/pc-nrfutil -.. _MCUboot: - https://github.com/JuulLabs-OSS/mcuboot -.. _mcumgr: - https://github.com/apache/mynewt-mcumgr-cli diff --git a/boards/arm/nrf52_adafruit_feather/Kconfig.board b/boards/arm/nrf52_adafruit_feather/Kconfig.board deleted file mode 100644 index 0f629d853df00c..00000000000000 --- a/boards/arm/nrf52_adafruit_feather/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 ADAFRUIT FEATHER board configuration - -# Copyright (c) 2018 LEDCity AG. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_ADAFRUIT_FEATHER - bool "nRF52 ADAFRUIT FEATHER" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_adafruit_feather/Kconfig.defconfig b/boards/arm/nrf52_adafruit_feather/Kconfig.defconfig deleted file mode 100644 index c75ff94e5203c6..00000000000000 --- a/boards/arm/nrf52_adafruit_feather/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 ADAFRUIT FEATHER board configuration - -# Copyright (c) 2018 LEDCity AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_ADAFRUIT_FEATHER - -config BOARD - default "nrf52_adafruit_feather" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_ADAFRUIT_FEATHER diff --git a/boards/arm/nrf52_adafruit_feather/doc/index.rst b/boards/arm/nrf52_adafruit_feather/doc/index.rst deleted file mode 100644 index 3555803b4498bd..00000000000000 --- a/boards/arm/nrf52_adafruit_feather/doc/index.rst +++ /dev/null @@ -1,192 +0,0 @@ -.. _nrf52_adafruit_feather: - -nRF52 Adafruit Feather -###################### - -Overview -******** - -The nRF52 Adafruit Bluefruit Feather hardware provides -support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`RTC (nRF RTC System Clock)` -* UART -* GPIO -* FLASH -* RADIO (Bluetooth Low Energy) -* Segger RTT (RTT Console) - -.. figure:: img/nrf52_adafruit_feather.jpg - :align: center - :alt: nRF52 Adafruit Feather Board - - nRF52 Adafruit Feather Board (Credit: Adafruit) - -More information about the board and its features can be found at the -`Adafruit Feather nRF52 Bluefruit Learning Guide`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -Hardware -******** - -- nRF52832 ARM Cortex-M4F processor at 64 MHz -- 32.768 kHz crystal oscillator -- 512 KiB flash memory and 64 KiB of SRAM -- Battery connector and charger for 3.7 V lithium polymer batteries -- Charging indicator LED -- 2 User LEDs -- Reset button -- SWD connector -- USB serial converter - -Supported Features -================== - -The nRF52 Adafruit Feather board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTT | on-chip | console | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `Adafruit Feather nRF52 Bluefruit Learning Guide`_ has detailed -information about the board including `pinouts`_ and the `schematic`_. - -LED ---- - -* LED0 (red) = P0.17 -* LED1 (blue) = P0.19 - -Push buttons ------------- - -* DFU = SW0 = P0.20 -* RESET = SW1 = P0.21/reset - -Programming and Debugging -************************* - -The ``nrf52_adafruit_feather`` board is available in two different versions: - -- `Adafruit Feather nRF52 Pro with myNewt Bootloader`_ - This board version is the recommended one to use. It has the SWD header - already populated and comes with the Mynewt serial bootloader installed by - default. - -- `Adafruit Feather nRF52 Bluefruit LE`_ - This board is identical to the board above, but the SWD header is not - populated and ships with an Arduino friendly bootloader. To be able to work - with this version a 2*5pin 0.5" SWD header (e.g. `Adafruit SWD connector`_) - needs to be soldered. - -Applications for the ``nrf52_adafruit_feather`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. - -Flashing -======== - -Flashing Zephyr onto the ``nrf52_adafruit_feather`` board requires an external -J-Link programmer. The programmer is attached to the X1 SWD header. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52_adafruit_feather - :goals: build - :compact: - -#. Connect the Adafruit nRF52 Feather to your host computer using USB - -#. Run your favorite terminal program to listen for output. - - .. code-block:: console - - $ minicom -D -b 115200 - - Replace :code:`` with the port where the nRF52 Adafruit Feather - board can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52_adafruit_feather - :goals: flash - :compact: - - You should see "Hello World! nrf52_adafruit_feather" in your terminal. - - -Debugging -========= - -The ``nrf52_adafruit_feather`` board does not have an on-board J-Link debug IC -as some nRF5x development boards, however, instructions from the -:ref:`nordic_segger` page also apply to this board, with the additional step -of connecting an external debugger. - - -Testing the LEDs and buttons on the nRF52 Adafruit Feather -********************************************************** - -There are several samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -- :zephyr:code-sample:`blinky` -- :zephyr:code-sample:`button` -- :zephyr:code-sample:`fade-led` -- :zephyr:code-sample:`pwm-blinky` -- :zephyr:code-sample:`multi-thread-blinky` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52_adafruit_feather/board.h`. - - -References -********** - -.. target-notes:: - -.. _Adafruit Feather nRF52 Bluefruit Learning Guide: https://learn.adafruit.com/bluefruit-nrf52-feather-learning-guide/introduction -.. _schematic: https://learn.adafruit.com/assets/39913 -.. _pinouts: https://cdn-learn.adafruit.com/assets/assets/000/046/210/original/Feather_NRF52_Pinout_v1.2.pdf?1504807075 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _Adafruit Feather nRF52 Bluefruit LE: https://www.adafruit.com/product/3406 -.. _Adafruit Feather nRF52 Pro with myNewt Bootloader: https://www.adafruit.com/product/3574 -.. _Adafruit SWD connector: https://www.adafruit.com/product/752 diff --git a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig b/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig deleted file mode 100644 index b434b22401db60..00000000000000 --- a/boards/arm/nrf52_adafruit_feather/nrf52_adafruit_feather_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_ADAFRUIT_FEATHER=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52_blenano2/Kconfig.board b/boards/arm/nrf52_blenano2/Kconfig.board deleted file mode 100644 index 05fe6ab53d52a8..00000000000000 --- a/boards/arm/nrf52_blenano2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 BLENANO 2 board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_BLENANO2 - bool "nRF52 BLENANO2" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_blenano2/Kconfig.defconfig b/boards/arm/nrf52_blenano2/Kconfig.defconfig deleted file mode 100644 index b5a7184c1a80ce..00000000000000 --- a/boards/arm/nrf52_blenano2/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 BLENANO 2 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_BLENANO2 - -config BOARD - default "nrf52_blenano2" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_BLENANO2 diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig b/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig deleted file mode 100644 index 318b8de69222e6..00000000000000 --- a/boards/arm/nrf52_blenano2/nrf52_blenano2_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_BLENANO2=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52_sparkfun/Kconfig.board b/boards/arm/nrf52_sparkfun/Kconfig.board deleted file mode 100644 index 3f290f593cf343..00000000000000 --- a/boards/arm/nrf52_sparkfun/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Sparkfun nRF52832 breakout board configuration - -# Copyright (c) 2017 Shawn Nock -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_SPARKFUN - bool "nRF52 SPARKFUN" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_sparkfun/Kconfig.defconfig b/boards/arm/nrf52_sparkfun/Kconfig.defconfig deleted file mode 100644 index 7629db89439cdb..00000000000000 --- a/boards/arm/nrf52_sparkfun/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Sparkfun nRF52832 breakout board configuration - -# Copyright (c) 2017 Shawn Nock -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_SPARKFUN - -config BOARD - default "nrf52_sparkfun" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_SPARKFUN diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun_defconfig b/boards/arm/nrf52_sparkfun/nrf52_sparkfun_defconfig deleted file mode 100644 index 3c893c08bc745e..00000000000000 --- a/boards/arm/nrf52_sparkfun/nrf52_sparkfun_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_SPARKFUN=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52_vbluno52/Kconfig b/boards/arm/nrf52_vbluno52/Kconfig deleted file mode 100644 index 026b4b301a7af3..00000000000000 --- a/boards/arm/nrf52_vbluno52/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 VBLUno52 board configuration - -# Copyright (c) 2017 VNG IoT Lab -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_VBLUNO52 - -endif # BOARD_NRF52_VBLUNO52 diff --git a/boards/arm/nrf52_vbluno52/Kconfig.board b/boards/arm/nrf52_vbluno52/Kconfig.board deleted file mode 100644 index bb1c223f4801a4..00000000000000 --- a/boards/arm/nrf52_vbluno52/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 VBLUno52 board configuration -# Copyright (c) 2017 VNG IoT Lab - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_VBLUNO52 - bool "nRF52 VBLUno52" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_vbluno52/Kconfig.defconfig b/boards/arm/nrf52_vbluno52/Kconfig.defconfig deleted file mode 100644 index 28f61496367882..00000000000000 --- a/boards/arm/nrf52_vbluno52/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 VBLUno52 board configuration - -# Copyright (c) 2017 VNG IoT Lab -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52_VBLUNO52 - -config BOARD - default "nrf52_vbluno52" - -config BT_CTLR - default BT - -endif # BOARD_NRF52_VBLUNO52 diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52_defconfig b/boards/arm/nrf52_vbluno52/nrf52_vbluno52_defconfig deleted file mode 100644 index 074355f29a1271..00000000000000 --- a/boards/arm/nrf52_vbluno52/nrf52_vbluno52_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52_VBLUNO52=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52dk_nrf52805/CMakeLists.txt b/boards/arm/nrf52dk_nrf52805/CMakeLists.txt deleted file mode 100644 index d708ea8ca2169e..00000000000000 --- a/boards/arm/nrf52dk_nrf52805/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52dk_nrf52805 board mirrors the nRF52 DK hardware. This needs -# to be considered by certain system initialization functionality residing -# in system_nrf52805.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52832) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52dk_nrf52805/Kconfig b/boards/arm/nrf52dk_nrf52805/Kconfig deleted file mode 100644 index 89f210e7e37cfd..00000000000000 --- a/boards/arm/nrf52dk_nrf52805/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52 DK nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52DK_NRF52805 diff --git a/boards/arm/nrf52dk_nrf52805/Kconfig.board b/boards/arm/nrf52dk_nrf52805/Kconfig.board deleted file mode 100644 index cf5fede2872659..00000000000000 --- a/boards/arm/nrf52dk_nrf52805/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 DK nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52DK_NRF52805 - bool "nRF52 DK NRF52805" - depends on SOC_NRF52805_CAAA diff --git a/boards/arm/nrf52dk_nrf52805/Kconfig.defconfig b/boards/arm/nrf52dk_nrf52805/Kconfig.defconfig deleted file mode 100644 index 6fa1686219e0ff..00000000000000 --- a/boards/arm/nrf52dk_nrf52805/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 DK nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52805 - -config BOARD - default "nrf52dk_nrf52805" - -config BT_CTLR - default BT - -endif # BOARD_NRF52DK_NRF52805 diff --git a/boards/arm/nrf52dk_nrf52805/board.cmake b/boards/arm/nrf52dk_nrf52805/board.cmake deleted file mode 100644 index e3f77214027d65..00000000000000 --- a/boards/arm/nrf52dk_nrf52805/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52dk_nrf52805/doc/index.rst b/boards/arm/nrf52dk_nrf52805/doc/index.rst deleted file mode 100644 index 121d1d508d04b2..00000000000000 --- a/boards/arm/nrf52dk_nrf52805/doc/index.rst +++ /dev/null @@ -1,23 +0,0 @@ -.. _nrf52dk_nrf52805: - -nRF52805 emulation on nRF52 DK -############################## - -Overview -******** - -The nrf52dk_nrf52805 board is a modified version of the :ref:`nrf52dk_nrf52832` -that enforces the limitations imposed by the nRF52805 IC, which is a -cost-reduced variant of the original nRF52832. Since Nordic does not offer a -development kit for the nRF52805, you can use this board to develop for this -IC while using the nRF52 Development Kit (PCA10040). - -See :ref:`nrf52dk_nrf52832` for more information about the development board and -`nRF52805 website`_ for the official reference on the IC itself. - -References -********** - -.. target-notes:: - -.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 diff --git a/boards/arm/nrf52dk_nrf52810/CMakeLists.txt b/boards/arm/nrf52dk_nrf52810/CMakeLists.txt deleted file mode 100644 index a36a95351a17d2..00000000000000 --- a/boards/arm/nrf52dk_nrf52810/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The nrf52dk_nrf52810 board mirrors the nRF52832 DK hardware. This -# needs to be considered by certain system initialization functionality -# residing in system_nrf52810.c and SoC dependent routines in nrfx_coredep.h. -zephyr_compile_definitions(DEVELOP_IN_NRF52832) -zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) diff --git a/boards/arm/nrf52dk_nrf52810/Kconfig b/boards/arm/nrf52dk_nrf52810/Kconfig deleted file mode 100644 index 4bb3d0a20ccb1c..00000000000000 --- a/boards/arm/nrf52dk_nrf52810/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# nRF52 DK nRF52810 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52810 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT - -endif # BOARD_NRF52DK_NRF52810 diff --git a/boards/arm/nrf52dk_nrf52810/Kconfig.board b/boards/arm/nrf52dk_nrf52810/Kconfig.board deleted file mode 100644 index 03004863b14db9..00000000000000 --- a/boards/arm/nrf52dk_nrf52810/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 DK nRF52810 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52DK_NRF52810 - bool "nRF52 DK NRF52810" - depends on SOC_NRF52810_QFAA diff --git a/boards/arm/nrf52dk_nrf52810/Kconfig.defconfig b/boards/arm/nrf52dk_nrf52810/Kconfig.defconfig deleted file mode 100644 index d98b71c5e61c23..00000000000000 --- a/boards/arm/nrf52dk_nrf52810/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# nRF52 DK nRF52810 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52810 - -config BOARD - default "nrf52dk_nrf52810" - -endif # BOARD_NRF52DK_NRF52810 diff --git a/boards/arm/nrf52dk_nrf52810/board.cmake b/boards/arm/nrf52dk_nrf52810/board.cmake deleted file mode 100644 index e3f77214027d65..00000000000000 --- a/boards/arm/nrf52dk_nrf52810/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52832_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf52dk_nrf52810/doc/index.rst b/boards/arm/nrf52dk_nrf52810/doc/index.rst deleted file mode 100644 index 8a767ca1b5b25d..00000000000000 --- a/boards/arm/nrf52dk_nrf52810/doc/index.rst +++ /dev/null @@ -1,24 +0,0 @@ -.. _nrf52dk_nrf52810: - -nRF52810 emulation on nRF52 DK -############################## - -Overview -******** - -The nrf52dk_nrf52810 board is a modified version of the :ref:`nrf52dk_nrf52832` -that enforces the limitations imposed by the nRF52810 IC, which is a -cost-reduced variant of the original nRF52832. Since Nordic does not offer a -development kit for the nRF52810 you can use this board to develop for this -IC while using the nRF52 Development Kit (PCA10040). - -See :ref:`nrf52dk_nrf52832` for more information about the development board and -`nRF52810 website`_ for the official reference on the IC itself. - - -References -********** - -.. target-notes:: - -.. _nRF52810 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52810 diff --git a/boards/arm/nrf52dk_nrf52832/Kconfig b/boards/arm/nrf52dk_nrf52832/Kconfig deleted file mode 100644 index 3ed080aa6d1c5e..00000000000000 --- a/boards/arm/nrf52dk_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# nRF52 DK board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_NRF52DK_NRF52832 diff --git a/boards/arm/nrf52dk_nrf52832/Kconfig.board b/boards/arm/nrf52dk_nrf52832/Kconfig.board deleted file mode 100644 index b853f2023b8a9c..00000000000000 --- a/boards/arm/nrf52dk_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# nRF52 DK NRF52832 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52DK_NRF52832 - bool "nRF52 DK NRF52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52dk_nrf52832/Kconfig.defconfig b/boards/arm/nrf52dk_nrf52832/Kconfig.defconfig deleted file mode 100644 index 648ea4de83d298..00000000000000 --- a/boards/arm/nrf52dk_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# nRF52 DK NRF52832 board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF52DK_NRF52832 - -config BOARD - default "nrf52dk_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_NRF52DK_NRF52832 diff --git a/boards/arm/nrf52dk_nrf52832/doc/index.rst b/boards/arm/nrf52dk_nrf52832/doc/index.rst deleted file mode 100644 index 77bf7df995b7fb..00000000000000 --- a/boards/arm/nrf52dk_nrf52832/doc/index.rst +++ /dev/null @@ -1,406 +0,0 @@ -.. _nrf52dk_nrf52832: - -nRF52 DK -######## - -Overview -******** - -The nRF52 Development Kit (PCA10040) hardware provides -support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf52dk_nrf52832.jpg - :align: center - :alt: nRF52 DK - - nRF52 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF52 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF52 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf52dk_nrf52832 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `nRF52 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF52 Development Kit board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.17 -* LED2 (green) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* LD5 (red/green) = OB LED 1/2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -J-Link Prog Connector - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug IN - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | VDD | N/A | -+-------+--------------+-------------------------+ -| 2 | SWDIO | SWDIO | -+-------+--------------+-------------------------+ -| 3 | GND | N/A | -+-------+--------------+-------------------------+ -| 4 | SWDCLK | SWDCLK | -+-------+--------------+-------------------------+ -| 5 | GND | N/A | -+-------+--------------+-------------------------+ -| 6 | P0.18 | P0.18 / TRACEDATA[0] / | -| | | SWO | -+-------+--------------+-------------------------+ -| 7 | Cut off | N/A | -+-------+--------------+-------------------------+ -| 8 | Cut off | N/A | -+-------+--------------+-------------------------+ -| 9 | GND | N/A | -+-------+--------------+-------------------------+ -| 10 | P0.21 | P0.21 / RESET | -+-------+--------------+-------------------------+ - -Debug OUT - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -| | | -+-------+----------------+ -| 7 | Cut off | -+-------+----------------+ -| 8 | Cut off | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Shield Debug and Current measurement - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | VDD_nRF | -+-------+----------------+ -| 2 | VDD | -+-------+----------------+ -| 3 | SH_VTG | -+-------+----------------+ -| 4 | SH_SWDIO | -+-------+----------------+ -| 5 | SH_SWDCLK | -+-------+----------------+ -| 6 | SH_SWO | -+-------+----------------+ -| 7 | SH_RESET | -+-------+----------------+ -| 8 | SH_GND_DETECT | -+-------+----------------+ - -Auxiliary - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | P0.00 | P0.00 / XL1 | -+-------+--------------+-------------------------+ -| 2 | P0.01 | P0.01 / XL2 | -+-------+--------------+-------------------------+ -| 3 | P0.21 | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | P0.05_C | P0.05 / AIN3 | -+-------+--------------+-------------------------+ -| 5 | P0.06_C | P0.06 | -+-------+--------------+-------------------------+ -| 6 | P0.07_C | P0.07 | -+-------+--------------+-------------------------+ -| 7 | P0.08_C | P0.08 | -+-------+--------------+-------------------------+ -| 8 | P0.09 | P0.09 / NFC1 | -+-------+--------------+-------------------------+ -| 9 | P0.10 | P0.10 / NFC2 | -+-------+--------------+-------------------------+ - -Arduino Headers ---------------- - -P1/P7 Power - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | VDD | N/A | -+-------+--------------+-------------------------+ -| 2 | VDD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | VDD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | VIN | N/A | -+-------+--------------+-------------------------+ - -P2/P8 Analog in - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -P3/P9 Digital I/O - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | D0 (RX) | P0.11 | -+-------+--------------+-------------------------+ -| 2 | D1 (TX) | P0.12 | -+-------+--------------+-------------------------+ -| 3 | D2 | P0.13 | -+-------+--------------+-------------------------+ -| 4 | D3 | P0.14 / TRACEDATA[3] | -+-------+--------------+-------------------------+ -| 5 | D4 | P0.15 / TRACEDATA[2] | -+-------+--------------+-------------------------+ -| 6 | D5 | P0.16 / TRACEDATA[1] | -+-------+--------------+-------------------------+ -| 7 | D6 | P0.17 | -+-------+--------------+-------------------------+ -| 8 | D7 | P0.18 / TRACEDATA[3] / | -| | | SWO | -+-------+--------------+-------------------------+ - -P4/P10 Digital I/O - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | D8 | P0.19 | -+-------+--------------+-------------------------+ -| 2 | D9 | P0.20 / TRACECLK | -+-------+--------------+-------------------------+ -| 3 | D10 (SS) | P0.22 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 6 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 9 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 10 | SCL | P0.27 | -+-------+--------------+-------------------------+ - -P5/P11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NRF52832 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52dk_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF52 DK -******************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/CMakeLists.txt b/boards/arm/nrf5340_audio_dk_nrf5340/CMakeLists.txt deleted file mode 100644 index fa1c1ba14d9325..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(nrf5340_audio_dk_cpunet_reset.c) - - if (CONFIG_BUILD_WITH_TFM) - zephyr_library_include_directories( - $/api_ns/interface/include - ) - endif() - -endif() diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig b/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig deleted file mode 100644 index 00e48c605429f1..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# nRF5340 Audio DK board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "nRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "nrf5340_audio_dk_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "nrf5340_audio_dk_nrf5340_cpuapp" - depends on BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.board b/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.board deleted file mode 100644 index 5b407f0356440e..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# nRF5340 Audio DK board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP - bool "nrf5340 Audio DK nRF5340 Application MCU" - -config BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - bool "nrf5340 Audio DK nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - bool "nrf5340 Audio DK NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.defconfig deleted file mode 100644 index 685ebc49b63a4c..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# nRF5340 Audio DK board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340_audio_dk_nrf5340_cpuapp" if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340_audio_dk_nrf5340_cpunet" if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS - -if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/board.cmake b/boards/arm/nrf5340_audio_dk_nrf5340/board.cmake deleted file mode 100644 index 4a0cab6c11ea5c..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/board.cmake +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/doc/index.rst b/boards/arm/nrf5340_audio_dk_nrf5340/doc/index.rst deleted file mode 100644 index 3d8d2413e9176d..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/doc/index.rst +++ /dev/null @@ -1,109 +0,0 @@ -.. _nrf5340_audio_dk_nrf5340: - -nRF5340 Audio DK -################ - -Overview -******** - -The nRF5340 Audio DK (PCA10121) is designed for showcasing, developing and experimenting -with Bluetooth® LE Audio. - -You can use this board for developing LE-Audio-compatible applications that support Auracast™, -connected isochronous streams (CIS) and broadcast isochronous streams (BIS), -and offer support for acting as a audio source, audio sink and source + sink. - -Zephyr uses the nrf5340_audio_dk_nrf5340 board configuration for building -for the nRF5340 Audio DK. - -Hardware -******** - -The nRF5340 Audio DK comes with the following hardware features: - -* nRF5340 dual-core SoC based on the Arm® Cortex®-M33 architecture -* CS47L63 Low-Power Audio DSP with mono differential headphone driver -* nPM1100 Ultra-small form-factor Power Management IC -* On-board digital microphone -* On-board power measurement -* SD card slot -* Built-in debugger -* Stereo analog input using 3.5 mm jack -* USB soundcard capability - -.. figure:: img/nrf5340_audio_dk.jpg - :align: center - :alt: nRF5340 DK - -More information about the board can be found at the `nRF5340 Audio DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - -nRF5340 SoC -=========== - -The nRF5340 Audio DK is built around the nRF5340 SoC, which has the following characteristics: - -* A full-featured Arm Cortex-M33F core with DSP instructions, - FPU, and Armv8-M Security Extension, running at up to 128 MHz, - referred to as the **application core**. -* A secondary Arm Cortex-M33 core, with a reduced feature set, - running at a fixed 64 MHz, referred to as the **network core**. - -The nrf5340_audio_dk_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The nrf5340_audio_dk_nrf5340_cpunet build target provides -support for the network core on the nRF5340 SoC. - -The `Nordic Semiconductor Infocenter`_ contains the processor's information and -the datasheet. - -Supported Features -================== - -See :ref:`nrf5340dk_nrf5340` and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF5340 Audio DK board hardware features. - - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then you can build and flash -applications as usual (:ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The nRF5340 has a flash read-back protection feature. When flash read-back - protection is active, you will need to recover the chip before reflashing. - If you are flashing with :ref:`west `, run - this command for more details on the related ``--recover`` option: - - .. code-block:: console - - west flash -H -r nrfjprog --skip-rebuild - -.. note:: - - Flashing and debugging applications on the nRF5340 Audio DK requires - upgrading the nRF Command Line Tools to version 10.12.0. Further - information on how to install the nRF Command Line Tools can be - found in :ref:`nordic_segger_flashing`. - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - -References -********** - -.. target-notes:: - -.. _nRF5340 Audio DK website: - https://www.nordicsemi.com/Products/Development-hardware/nrf5340-audio-dk -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_defconfig deleted file mode 100644 index 2e7ac0ea3cc20b..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP=y - -CONFIG_ARM_MPU=y - -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_ARM_TRUSTZONE_M=y - -CONFIG_GPIO=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig deleted file mode 100644 index 425ae71842637e..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS=y - -CONFIG_ARM_MPU=y - -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -CONFIG_GPIO=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet_defconfig b/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet_defconfig deleted file mode 100644 index d0844088568be4..00000000000000 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf5340dk_nrf5340/Kconfig b/boards/arm/nrf5340dk_nrf5340/Kconfig deleted file mode 100644 index 518328e57e818e..00000000000000 --- a/boards/arm/nrf5340dk_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# nRF5340 DK board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "nrf5340dk_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "nrf5340dk_nrf5340_cpuapp" - depends on BOARD_NRF5340DK_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/nrf5340dk_nrf5340/Kconfig.board b/boards/arm/nrf5340dk_nrf5340/Kconfig.board deleted file mode 100644 index e73cb122d80ff3..00000000000000 --- a/boards/arm/nrf5340dk_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# nRF5340 DK NRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340DK_NRF5340_CPUAPP - bool "nRF5340 DK nRF5340 Application MCU" - -config BOARD_NRF5340DK_NRF5340_CPUAPP_NS - bool "nRF5340 DK nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_NRF5340DK_NRF5340_CPUNET - bool "nRF5340 DK NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig b/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig deleted file mode 100644 index 84f19365cc53da..00000000000000 --- a/boards/arm/nrf5340dk_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,84 +0,0 @@ -# nRF5340 DK nRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340dk_nrf5340_cpuapp" if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -config BOARD - default "nrf5340dk_nrf5340_cpunet" if BOARD_NRF5340DK_NRF5340_CPUNET - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS - -if BOARD_NRF5340DK_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_NRF5340DK_NRF5340_CPUNET diff --git a/boards/arm/nrf5340dk_nrf5340/doc/index.rst b/boards/arm/nrf5340dk_nrf5340/doc/index.rst deleted file mode 100644 index 984090f3879d9d..00000000000000 --- a/boards/arm/nrf5340dk_nrf5340/doc/index.rst +++ /dev/null @@ -1,330 +0,0 @@ -.. _nrf5340dk_nrf5340: - -nRF5340 DK -########## - -Overview -******** - -The nRF5340 DK (PCA10095) is a single-board development kit for evaluation -and development on the Nordic nRF5340 System-on-Chip (SoC). - -The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running at - a fixed 64 MHz, referred to as the **network core**. - -The nrf5340dk_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The nrf5340dk_nrf5340_cpunet build target provides -support for the network core on the nRF5340 SoC. - -nRF5340 SoC provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf5340dk.jpg - :align: center - :alt: nRF5340 DK - - nRF5340 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF5340 DK website`_. -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF5340 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf5340dk_nrf5340_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The nrf5340dk_nrf5340_cpunet board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `Nordic Semiconductor Infocenter`_ -for a complete list of nRF5340 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.28 -* LED2 (green) = P0.29 -* LED3 (green) = P0.30 -* LED4 (green) = P0.31 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.23 -* BUTTON2 = SW2 = P0.24 -* BUTTON3 = SW3 = P0.8 -* BUTTON4 = SW4 = P0.9 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_) on the application core. - The IDAU is implemented with the System Protection Unit and is used to - define secure and non-secure memory maps. By default, all of the memory - space (Flash, SRAM, and peripheral address space) is defined to be secure - accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nRF5340 application core supports the Armv8-M Security Extension. -Applications built for the nrf5340dk_nrf5340_cpuapp board by default -boot in the Secure state. - -nRF5340 network core does not support the Armv8-M Security Extension. -nRF5340 IDAU may configure bus accesses by the nRF5340 network core -to have Secure attribute set; the latter allows to build and run -Secure only applications on the nRF5340 SoC. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the nRF5340 may contain a Secure and a Non-Secure firmware -image for the application core. The Secure image can be built using either -Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware -images are always built using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for nRF5340 application core is built - using TF-M. - - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following steps: - -1. Build the Non-Secure Zephyr application - for the application core using ``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output image binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -2. Build the application firmware for the network core using - ``-DBOARD=nrf5340dk_nrf5340_cpunet``. - - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process to build the Secure and the Non-Secure firmware images -using Zephyr requires the following steps: - -1. Build the Secure Zephyr application for the application core - using ``-DBOARD=nrf5340dk_nrf5340_cpuapp`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` - in the application project configuration file. -2. Build the Non-Secure Zephyr application for the application core - using ``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns``. -3. Merge the two binaries together. -4. Build the application firmware for the network core using - ``-DBOARD=nrf5340dk_nrf5340_cpunet``. - - -When building a Secure/Non-Secure application for the nRF5340 application core, -the Secure application will have to set the IDAU (SPU) configuration to allow -Non-Secure access to all CPU resources utilized by the Non-Secure application -firmware. SPU configuration shall take place before jumping to the Non-Secure -application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf5340dk_nrf5340_cpuapp`` for -the firmware running on the nRF5340 application core, and using -``-DBOARD=nrf5340dk_nrf5340_cpunet`` for the firmware running -on the nRF5340 network core. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then you can build and flash -applications as usual (:ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The nRF5340 has a flash read-back protection feature. When flash read-back - protection is active, you will need to recover the chip before reflashing. - If you are flashing with :ref:`west `, run - this command for more details on the related ``--recover`` option: - - .. code-block:: console - - west flash -H -r nrfjprog --skip-rebuild - -.. note:: - - Flashing and debugging applications on the nRF5340 DK requires - upgrading the nRF Command Line Tools to version 10.12.0. Further - information on how to install the nRF Command Line Tools can be - found in :ref:`nordic_segger_flashing`. - -Here is an example for the :ref:`hello_world` application running on the -nRF5340 application core. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF5340 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf5340dk_nrf5340_cpuapp - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - - -Testing the LEDs and buttons in the nRF5340 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and -LEDs on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF5340 DK website: - https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF5340-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet_defconfig b/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet_defconfig deleted file mode 100644 index 47f7b157d06c26..00000000000000 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board deleted file mode 100644 index b76cfce6800b28..00000000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54H20PDK_NRF54H20_CPUAPP - bool "nRF54H20 PDK nRF54H20 Application MCU" - depends on SOC_NRF54H20_ENGA_CPUAPP - -config BOARD_NRF54H20PDK_NRF54H20_CPURAD - bool "nRF54H20 PDK nRF54H20 Radio MCU" - depends on SOC_NRF54H20_ENGA_CPURAD diff --git a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig b/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig deleted file mode 100644 index 954276ec82993b..00000000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "nrf54h20pdk_nrf54h20_cpuapp" if BOARD_NRF54H20PDK_NRF54H20_CPUAPP - default "nrf54h20pdk_nrf54h20_cpurad" if BOARD_NRF54H20PDK_NRF54H20_CPURAD - -if BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD - -# Data cache is disabled due to a HW issue in the EngA SoC revision. -config DCACHE - default n - -endif # BOARD_NRF54H20PDK_NRF54H20_CPUAPP || BOARD_NRF54H20PDK_NRF54H20_CPURAD diff --git a/boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst b/boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst deleted file mode 100644 index 3ac79bc791ea7c..00000000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/doc/index.rst +++ /dev/null @@ -1,153 +0,0 @@ -.. _nrf54h20pdk_nrf54h20: - -nRF54H20 PDK -############ - -Overview -******** - -.. note:: - - All software for the nRF54H20 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF54H20 PDK is a single-board preview development kit for evaluation -and development on the Nordic nRF54H20 System-on-Chip (SoC). - -The nRF54H20 is a multicore SoC with: - -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 320 MHz, referred to as the **application core** -* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security - Extensions, running at up to 256 MHz, referred to as the **radio core**. - -The ``nrf54h20pdk_nrf54h20_cpuapp`` build target provides support for -the application core on the nRF54H20 SoC. -The ``nrf54h20pdk_nrf54h20_cpurad`` build target provides support for -the radio core on the nRF54H20 SoC. - -nRF54H20 SoC provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`GPIOTE (General Purpose Input Output tasks and events)` -* :abbr:`GRTC (Global real-time counter)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* MRAM -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf54h20pdk_nrf54h20.webp - :align: center - :alt: nRF54H20 PDK - - nRF54H20 PDK (Credit: Nordic Semiconductor) - -Hardware -******** - -nRF54H20 PDK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -Supported Features -================== - -The nrf54h20pdk_nrf54h20_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIOTE | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ - -The nrf54h20pdk_nrf54h20_cpurad board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIOTE | on-chip | gpio | -+-----------+------------+----------------------+ -| GRTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LEDs ----- - -* LED1 (green) = P9.0 -* LED2 (green) = P9.1 -* LED3 (green) = P9.2 -* LED4 (green) = P9.3 - -Push buttons ------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* BUTTON3 = P0.10 -* BUTTON4 = P0.11 -* RESET (SW1) - -Programming and Debugging -************************* - -Applications for both the ``nrf54h20pdk_nrf54h20_cpuapp`` and -``nrf54h20pdk_nrf54h20_cpurad`` targets can be built, flashed, -and debugged in the usual way. See :ref:`build_an_application` -and :ref:`application_run` for more details on building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :ref:`hello_world` -application. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF54H20 PDK, complete the following steps: - -First, connect the nRF54H20 PDK to you computer using the IMCU USB port on the PDK. -Next, build the sample by running the following command: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf54h20pdk_nrf54h20_cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF54H20 PDK -************************************************ - -There are 2 samples that allow you to test that the buttons (switches) and LEDs -on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts`. diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig deleted file mode 100644 index 1f7ef38a7fc67a..00000000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_ENGA_CPUAPP=y -CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUAPP=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig b/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig deleted file mode 100644 index 254d8656e61180..00000000000000 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_ENGA_CPURAD=y -CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPURAD=y - -CONFIG_USE_DT_CODE_PARTITION=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# MPU-based null-pointer dereferencing detection cannot be applied -# as the (0x0 - 0x400) region is unmapped for this target. -CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y - -# Enable cache -CONFIG_CACHE_MANAGEMENT=y -CONFIG_EXTERNAL_CACHE=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board deleted file mode 100644 index d95fe51009f36e..00000000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54L15PDK_NRF54L15_CPUAPP - bool "nRF54L15 PDK nRF54L15 Application MCU" - depends on SOC_NRF54L15_ENGA_CPUAPP diff --git a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig b/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig deleted file mode 100644 index 532ea07c859bc6..00000000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF54L15PDK_NRF54L15_CPUAPP - -config BOARD - default "nrf54l15pdk_nrf54l15_cpuapp" - -config BT_CTLR - default BT - -endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP diff --git a/boards/arm/nrf54l15pdk_nrf54l15/doc/index.rst b/boards/arm/nrf54l15pdk_nrf54l15/doc/index.rst deleted file mode 100644 index dce1c841b1c969..00000000000000 --- a/boards/arm/nrf54l15pdk_nrf54l15/doc/index.rst +++ /dev/null @@ -1,139 +0,0 @@ -.. _nrf54l15pdk_nrf54l15: - -nRF54L15 PDK -############ - -Overview -******** - -.. note:: - - All software for the nRF54L15 SoC is experimental and hardware availability - is restricted to the participants in the limited sampling program. - -The nRF54L15 Preview Development Kit hardware provides -support for the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU and -the following devices: - -* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` -* CLOCK -* RRAM -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`GRTC (Global real-time counter)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/nrf54l15pdk_nrf54l15.webp - :align: center - :alt: nRF54L15 PDK - - nRF54L15 PDK (Credit: Nordic Semiconductor) - -Hardware -******** - -nRF54L15 PDK has two crystal oscillators: - -* High-frequency 32 MHz crystal oscillator (HFXO) -* Low-frequency 32.768 kHz crystal oscillator (LFXO) - -The crystal oscillators can be configured to use either -internal or external capacitors. - -Supported Features -================== - -The nrf54l15pdk_nrf54l15 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| SAADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| RRAM | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| TWIM | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| GRTC | on-chip | counter | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Programming and Debugging -************************* - -Applications for the ``nrf54l15pdk_nrf54l15_cpuapp`` board can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -As an example, this section shows how to build and flash the :ref:`hello_world` -application. - -.. warning:: - - When programming the device, you might get an error similar to the following message:: - - ERROR: The operation attempted is unavailable due to readback protection in - ERROR: your device. Please use --recover to unlock the device. - - This error occurs when readback protection is enabled. - To disable the readback protection, you must *recover* your device. - - Enter the following command to recover the core:: - - west flash --recover - - The ``--recover`` command erases the flash memory and then writes a small binary into - the recovered flash memory. - This binary prevents the readback protection from enabling itself again after a pin - reset or power cycle. - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. - -To build and program the sample to the nRF54L15 PDK, complete the following steps: - -First, connect the nRF54L15 PDK to you computer using the IMCU USB port on the PDK. -Next, build the sample by running the following command: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf54l15pdk_nrf54l15_cpuapp - :goals: build flash - -Testing the LEDs and buttons in the nRF54L15 PDK -************************************************ - -Test the nRF54L15 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/arm/nrf9131ek_nrf9131/Kconfig.board b/boards/arm/nrf9131ek_nrf9131/Kconfig.board deleted file mode 100644 index 4a237e3fb617a7..00000000000000 --- a/boards/arm/nrf9131ek_nrf9131/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9131-EK board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9131_LACA - -config BOARD_NRF9131EK_NRF9131 - bool "nRF9131 EK NRF9131" - -config BOARD_NRF9131EK_NRF9131_NS - bool "nRF9131 EK NRF9131 non-secure" - -endif # SOC_NRF9131_LACA diff --git a/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig b/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig deleted file mode 100644 index 0ece4f9a2ac1cf..00000000000000 --- a/boards/arm/nrf9131ek_nrf9131/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# nRF9131 EK NRF9131 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS - -config BOARD - default "nrf9131ek_nrf9131" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9131EK_NRF9131 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9131EK_NRF9131_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9131EK_NRF9131_NS - -endif # BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS diff --git a/boards/arm/nrf9131ek_nrf9131/doc/index.rst b/boards/arm/nrf9131ek_nrf9131/doc/index.rst deleted file mode 100644 index 57473c631ed541..00000000000000 --- a/boards/arm/nrf9131ek_nrf9131/doc/index.rst +++ /dev/null @@ -1,229 +0,0 @@ -.. _nrf9131ek_nrf9131: - -nRF9131 EK -########## - -Overview -******** - -The nRF9131 EK (PCA10165) is a single-board evaluation kit for the nRF9131 SiP -for DECT NR+ and LTE-M/NB-IoT with GNSS. -The nrf9131ek_nrf9131 board configuration provides support for the Nordic Semiconductor nRF9131 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/nrf9131ek_nrf9131.webp - :align: center - :alt: nRF9131 EK - - nRF9131 EK (Credit: Nordic Semiconductor) - -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9131 EK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9131ek_nrf9131 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED (red) = P0.29 -* LED (green) = P0.30 -* LED (blue) = P0.31 - -Push buttons and Switches -------------------------- - -* BUTTON = P0.28 -* RESET - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9131ek_nrf9131 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the nRF9131 may contain a Secure and a Non-Secure firmware -image. The Secure image can be built using either Zephyr or -`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built -using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for nRF9131 is built using TF-M. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9131ek_nrf9131`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9131ek_nrf9131_ns``. -3. Merge the two binaries together. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following action: - -1. Build the Non-Secure Zephyr application - using ``-DBOARD=nrf9131ek_nrf9131_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9131ek_nrf9131``. - - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9131 EK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9131ek_nrf9131 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9131 EK -********************************************** - -There are 2 samples that allow you to test that the button and LED on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_defconfig b/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_defconfig deleted file mode 100644 index fc77ffe0d13a85..00000000000000 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9131_LACA=y -CONFIG_BOARD_NRF9131EK_NRF9131=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns_defconfig b/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns_defconfig deleted file mode 100644 index 83af1cf6b74ad1..00000000000000 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns_defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9131_LACA=y -CONFIG_BOARD_NRF9131EK_NRF9131_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y - -# enable PMIC -CONFIG_I2C=y -CONFIG_REGULATOR=y -CONFIG_SENSOR=y -CONFIG_NPM1300_CHARGER=y diff --git a/boards/arm/nrf9151dk_nrf9151/Kconfig.board b/boards/arm/nrf9151dk_nrf9151/Kconfig.board deleted file mode 100644 index 92352ddc16fa36..00000000000000 --- a/boards/arm/nrf9151dk_nrf9151/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9151 DK NRF9151 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9151_LACA - -config BOARD_NRF9151DK_NRF9151 - bool "nRF9151 DK NRF9151" - -config BOARD_NRF9151DK_NRF9151_NS - bool "nRF9151 DK NRF9151 non-secure" - -endif # SOC_NRF9151_LACA diff --git a/boards/arm/nrf9151dk_nrf9151/Kconfig.defconfig b/boards/arm/nrf9151dk_nrf9151/Kconfig.defconfig deleted file mode 100644 index 3cbff101d63624..00000000000000 --- a/boards/arm/nrf9151dk_nrf9151/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# nRF9151 DK NRF9151 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS - -config BOARD - default "nrf9151dk_nrf9151" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9151DK_NRF9151 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9151DK_NRF9151_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9151DK_NRF9151_NS - -config BT_HCI_VS - default y if BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,nrf5340_reset) - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) - -endif # BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS diff --git a/boards/arm/nrf9151dk_nrf9151/doc/index.rst b/boards/arm/nrf9151dk_nrf9151/doc/index.rst deleted file mode 100644 index 4c02e7ed372d83..00000000000000 --- a/boards/arm/nrf9151dk_nrf9151/doc/index.rst +++ /dev/null @@ -1,203 +0,0 @@ -.. _nrf9151dk_nrf9151: - -nRF9151 DK -########## - -Overview -******** - -The nRF9151 DK (PCA10171) is a single-board development kit for evaluation and -development on the nRF9151 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The nrf9151dk_nrf9151 -board configuration provides support for the Nordic Semiconductor nRF9151 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9151 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9151 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9151dk_nrf9151 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| FLASH | external | spi | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIO | external | i2c | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | nRF53 | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - - -.. _nrf9151dk_additional_hardware: - -Other hardware features have not been enabled yet for this board. -See `nRF9151 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF9151 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.0 -* LED2 (green) = P0.1 -* LED3 (green) = P0.4 -* LED4 (green) = P0.5 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* SWITCH1 = P0.18 -* SWITCH2 = P0.19 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9151dk_nrf9151 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9151dk_nrf9151`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9151dk_nrf9151_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9151dk_nrf9151``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9151 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9151dk_nrf9151 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9151 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9151 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9151-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_defconfig b/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_defconfig deleted file mode 100644 index 7afe5ac7aa995d..00000000000000 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9151_LACA=y -CONFIG_BOARD_NRF9151DK_NRF9151=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns_defconfig b/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns_defconfig deleted file mode 100644 index 949ef39f856df0..00000000000000 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9151_LACA=y -CONFIG_BOARD_NRF9151DK_NRF9151_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue21/Kconfig.board b/boards/arm/nrf9160_innblue21/Kconfig.board deleted file mode 100644 index af6b5478f9e98e..00000000000000 --- a/boards/arm/nrf9160_innblue21/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9160 innblue V2.1 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_NRF9160_INNBLUE21 - bool "nRF9160 innblue v2.1" - -config BOARD_NRF9160_INNBLUE21_NS - bool "nRF9160 innblue v2.1 non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue21/Kconfig.defconfig b/boards/arm/nrf9160_innblue21/Kconfig.defconfig deleted file mode 100644 index 08d0409c9af8d8..00000000000000 --- a/boards/arm/nrf9160_innblue21/Kconfig.defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# nRF9160 innblue V2.1 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160_INNBLUE21 || BOARD_NRF9160_INNBLUE21_NS - -config BOARD - default "nrf9160_innblue21" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -if BOARD_NRF9160_INNBLUE21 && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE21 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9160_INNBLUE21_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE21_NS - -config BT_HCI_VS - default y if BT - -config REGULATOR - default y if SENSOR - -endif # BOARD_NRF9160_INNBLUE21 || BOARD_NRF9160_INNBLUE21_NS diff --git a/boards/arm/nrf9160_innblue21/doc/index.rst b/boards/arm/nrf9160_innblue21/doc/index.rst deleted file mode 100644 index c0f9e33cd759b0..00000000000000 --- a/boards/arm/nrf9160_innblue21/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _nrf9160_innblue21: - -nRF9160 INNBLUE21 -################# - -Overview -******** - -The nRF9160 innblue21 is a cellular IoT sensor development board, which -is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. - -.. figure:: img/nrf9160_innblue21.jpg - :align: center - :alt: nRF9160 innblue21 - - nRF9160 innblue21 (Credit: innblue) - -Hardware -******** - -The following parts are built into the board: - -* Accelerometer: ST LIS2DH12 -* CryptoElement: Atmel ATECC608a -* Humidity Sensor: ST HTS221 -* Qi charger: TI BQ51013 -* Battery fuel gauge: TI BQ27421 - -Supported Features -================== - -The nrf9160_innblue21 board configuration supports the following -hardware (as of nRF9160) features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED1 ( red ) = P0.7 -* LED2 (green) = P0.6 -* LED3 ( blue) = P0.5 -* LED4 ( red ) = P0.4 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.31 - -Security components -=================== - -- Implementation Defined Attribution Unit. The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nrf9160_innblue21 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9160_innblue21`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160_innblue21_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9160_innblue21``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9160 innblue21 -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160_innblue21 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.dts b/boards/arm/nrf9160_innblue21/nrf9160_innblue21.dts deleted file mode 100644 index af9e3a2e784b9a..00000000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue21_common.dtsi" - -/ { - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.yaml b/boards/arm/nrf9160_innblue21/nrf9160_innblue21.yaml deleted file mode 100644 index 3c5100852c9659..00000000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue21 -name: nRF9160-INNBLUE21 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common.dtsi b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common.dtsi deleted file mode 100644 index 0ec5de5dfb1af1..00000000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common.dtsi +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "nrf9160_innblue21_common-pinctrl.dtsi" -#include - -/ { - model = "innblue v21 Dev Kit"; - compatible = "innblue,innblue21"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_1 { - gpios = <&gpio0 7 0>; - label = "RGB red channel"; - }; - green_led: led_2 { - gpios = <&gpio0 6 0>; - label = "RGB green channel"; - }; - blue_led: led_3 { - gpios = <&gpio0 5 0>; - label = "RGB blue channel"; - }; - - mode_led: led_4 { - gpios = <&gpio0 4 0>; - label = "mode red channel"; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 31 GPIO_PULL_UP>; - label = "Button 0"; - zephyr,code = ; - }; - }; - - en_3v3_sensor: enable-3v3-sensor { - compatible = "regulator-fixed"; - regulator-name = "en_3v3_sensor"; - enable-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; - startup-delay-us = <10000>; - regulator-boot-on; - }; - - en_5v0_boost: enable-5v0-boost { - compatible = "regulator-fixed"; - regulator-name = "en_5v0_boost"; - enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - startup-delay-us = <10000>; - regulator-boot-on; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &red_led; - led1 = &green_led; - led2 = &blue_led; - led3 = &mode_led; - sw0 = &button0; - rgb-pwm = &pwm0; - mode-pwm = &pwm1; - watchdog0 = &wdt0; - accel0 = &lis2dh12_accel; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-1 = <&uart2_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c2 { - compatible = "nordic,nrf-twim"; - status = "okay"; - - clock-frequency = ; - - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - pinctrl-names = "default", "sleep"; - lis2dh12_accel: lis2dh12-accel@19 { - compatible = "st,lis2dh"; - reg = <0x19>; - irq-gpios = <&gpio0 0 0>, <&gpio0 1 0>; - }; - - hts221@5f { - compatible = "st,hts221"; - reg = <0x5f>; - drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - }; - - lps22hb-press@5c { - compatible = "st,lps22hb-press"; - reg = <0x5c>; - }; - - ccs811: ccs811@5a { - compatible = "ams,ccs811"; - reg = <0x5a>; - }; - - bme680@76 { - compatible = "bosch,bme680"; - reg = <0x76>; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm1 { - status = "okay"; - pinctrl-0 = <&pwm1_default>; - pinctrl-1 = <&pwm1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - /* SRAM allocated and used by the BSD library */ - sram0_bsd: memory@20010000 { - compatible = "mmio-sram"; - }; - - /* SRAM allocated to the Non-Secure image */ - sram0_ns: memory@20020000 { - compatible = "mmio-sram"; - }; -}; - -/* Include partition configuration file */ -#include "nrf9160_innblue21_partition_conf.dtsi" diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_defconfig b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_defconfig deleted file mode 100644 index 7c0e84c1abdbb0..00000000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE21=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.dts b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.dts deleted file mode 100644 index 8343318db220e5..00000000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue21_common.dtsi" - -/ { - chosen { - zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; - zephyr,code-partition = &slot0_ns_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.yaml b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.yaml deleted file mode 100644 index 4584ad0e6a49ef..00000000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue21_ns -name: nRF9160-INNBLUE21-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns_defconfig b/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns_defconfig deleted file mode 100644 index 4f5410848bca58..00000000000000 --- a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE21_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue22/Kconfig.board b/boards/arm/nrf9160_innblue22/Kconfig.board deleted file mode 100644 index e805798790a702..00000000000000 --- a/boards/arm/nrf9160_innblue22/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9160 innblue V2.2 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_NRF9160_INNBLUE22 - bool "nRF9160 innblue v2.2" - -config BOARD_NRF9160_INNBLUE22_NS - bool "nRF9160 innblue V2.2 non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue22/Kconfig.defconfig b/boards/arm/nrf9160_innblue22/Kconfig.defconfig deleted file mode 100644 index d50bdcc9d9757c..00000000000000 --- a/boards/arm/nrf9160_innblue22/Kconfig.defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# nRF9160 innblue V2.2 board configuration - -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160_INNBLUE22 || BOARD_NRF9160_INNBLUE22_NS - -config BOARD - default "nrf9160_innblue22" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -if BOARD_NRF9160_INNBLUE22 && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE22 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9160_INNBLUE22_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160_INNBLUE22_NS - -config BT_HCI_VS - default y if BT - -config REGULATOR - default y if SENSOR - -endif # BOARD_NRF9160_INNBLUE22 || BOARD_NRF9160_INNBLUE22_NS diff --git a/boards/arm/nrf9160_innblue22/doc/index.rst b/boards/arm/nrf9160_innblue22/doc/index.rst deleted file mode 100644 index 0f2f83bcfe1e98..00000000000000 --- a/boards/arm/nrf9160_innblue22/doc/index.rst +++ /dev/null @@ -1,144 +0,0 @@ -.. _nrf9160_innblue22: - -nRF9160 INNBLUE22 -################# - -Overview -******** - -The nRF9160 innblue22 is a cellular IoT sensor development board, which -is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. - -.. figure:: img/nrf9160_innblue22.jpg - :align: center - :alt: nRF9160 innblue22 - - nRF9160 innblue22 (Credit: innblue) - -Hardware -******** - -The following parts are built into the board: - -* Accelerometer: ST LIS2DH12 -* CryptoElement: Atmel ATECC608a -* Humidity Sensor: ST HTS221 -* Qi charger: TI BQ51013 -* Battery fuel gauge: TI BQ27421 - -Supported Features -================== - -The nrf9160_innblue22 board configuration supports the following -hardware (as of nRF9160) features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED1 ( red ) = P0.7 -* LED2 (green) = P0.6 -* LED3 ( blue) = P0.5 -* LED4 ( red ) = P0.4 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.31 - -Security components -=================== - -- Implementation Defined Attribution Unit. The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nrf9160_innblue22 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications -============================================== - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9160_innblue22`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160_innblue22_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9160_innblue22``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9160 innblue22 -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160_innblue22 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.dts b/boards/arm/nrf9160_innblue22/nrf9160_innblue22.dts deleted file mode 100644 index 61c376e61e7ff7..00000000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue22_common.dtsi" - -/ { - chosen { - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.yaml b/boards/arm/nrf9160_innblue22/nrf9160_innblue22.yaml deleted file mode 100644 index a4ec1d1266e5d2..00000000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue22 -name: nRF9160-INNBLUE22 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common.dtsi b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common.dtsi deleted file mode 100644 index 4738dd84a63481..00000000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common.dtsi +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "nrf9160_innblue22_common-pinctrl.dtsi" -#include - -/ { - model = "innblue v22 Dev Kit"; - compatible = "innblue,innblue22"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_1 { - gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; - label = "RGB red channel"; - }; - green_led: led_2 { - gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; - label = "RGB green channel"; - }; - blue_led: led_3 { - gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; - label = "RGB blue channel"; - }; - - mode_led: led_4 { - gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; - label = "mode red channel"; - }; - }; - - buttons { - compatible = "gpio-keys"; - - button0: button_0 { - gpios = <&gpio0 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Button 0"; - zephyr,code = ; - }; - }; - - en_5v0_boost: enable-5v0-boost { - compatible = "regulator-fixed"; - regulator-name = "en_5v0_boost"; - enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - startup-delay-us = <10000>; - regulator-boot-on; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &red_led; - led1 = &green_led; - led2 = &blue_led; - led3 = &mode_led; - sw0 = &button0; - rgb-pwm = &pwm0; - mode-pwm = &pwm1; - watchdog0 = &wdt0; - accel0 = &lis2dh12_accel; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-1 = <&uart2_sleep>; - pinctrl-names = "default", "sleep"; -}; - - -&i2c2 { - compatible = "nordic,nrf-twim"; - status = "okay"; - - clock-frequency = ; - - pinctrl-0 = <&i2c2_default>; - pinctrl-1 = <&i2c2_sleep>; - pinctrl-names = "default", "sleep"; - bq27421@55 { - compatible = "ti,bq274xx"; - reg = <0x55>; - design-voltage = <3700>; - design-capacity = <1800>; - taper-current = <45>; - terminate-voltage = <3000>; - }; - - lis2dh12_accel: lis2dh12-accel@19 { - compatible = "st,lis2dh"; - reg = <0x19>; - irq-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>; - }; - - hts221@5f { - compatible = "st,hts221"; - reg = <0x5f>; - drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; - }; - - lps22hb-press@5c { - compatible = "st,lps22hb-press"; - reg = <0x5c>; - }; - - ccs811: ccs811@5a { - compatible = "ams,ccs811"; - reg = <0x5a>; - }; - - bme680@76 { - compatible = "bosch,bme680"; - reg = <0x76>; - }; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm1 { - status = "okay"; - pinctrl-0 = <&pwm1_default>; - pinctrl-1 = <&pwm1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x10000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot0_ns_partition: partition@50000 { - label = "image-0-nonsecure"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - slot1_ns_partition: partition@c0000 { - label = "image-1-nonsecure"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -/ { - /* SRAM allocated and used by the BSD library */ - sram0_bsd: memory@20010000 { - compatible = "mmio-sram"; - }; - - /* SRAM allocated to the Non-Secure image */ - sram0_ns: memory@20020000 { - compatible = "mmio-sram"; - }; -}; - -/* Include partition configuration file */ -#include "nrf9160_innblue22_partition_conf.dtsi" diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_defconfig b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_defconfig deleted file mode 100644 index ae9e2e2413e803..00000000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE22=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.dts b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.dts deleted file mode 100644 index f68b35059256cb..00000000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2020 InnBlue - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nrf9160_innblue22_common.dtsi" - -/ { - chosen { - zephyr,flash = &flash0; - zephyr,sram = &sram0_ns; - zephyr,code-partition = &slot0_ns_partition; - }; -}; diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.yaml b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.yaml deleted file mode 100644 index 0186c26a377db5..00000000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160_innblue22_ns -name: nRF9160-INNBLUE22-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - i2c - - pwm - - watchdog diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns_defconfig b/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns_defconfig deleted file mode 100644 index e956d4d8b75282..00000000000000 --- a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2020 InnBlue -# SPDX-License-Identifier: Apache-2.0 - -# SOC / Board -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160_INNBLUE22_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf52840/Kconfig b/boards/arm/nrf9160dk_nrf52840/Kconfig deleted file mode 100644 index c126d2509cb9ed..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# nRF9160 DK NRF52840 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160DK_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -module = BOARD_NRF9160DK -module-str = Board Control -source "subsys/logging/Kconfig.template.log_config" - -endif # BOARD_NRF52840_NRF9160DK diff --git a/boards/arm/nrf9160dk_nrf52840/Kconfig.board b/boards/arm/nrf9160dk_nrf52840/Kconfig.board deleted file mode 100644 index b4a46cc9eca6fa..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# nRF9160 DK NRF52840 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF9160DK_NRF52840 - bool "NRF9160 DK NRF52840" - depends on SOC_NRF52840_QIAA - # The GPIO driver is required by this board's initialization code - # (board.c), so it is forced here to be enabled always, not only - # enabled by default (in defconfig). - select GPIO diff --git a/boards/arm/nrf9160dk_nrf52840/Kconfig.defconfig b/boards/arm/nrf9160dk_nrf52840/Kconfig.defconfig deleted file mode 100644 index dc3c3c3caae35b..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# nRF9160 DK NRF52840 board configuration - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160DK_NRF52840 - -config BOARD - default "nrf9160dk_nrf52840" - -config BT_CTLR - default BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,reset_input) - -endif # BOARD_NRF9160DK_NRF52840 diff --git a/boards/arm/nrf9160dk_nrf52840/board.cmake b/boards/arm/nrf9160dk_nrf52840/board.cmake deleted file mode 100644 index f505d2c380e74b..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/arm/nrf9160dk_nrf52840/doc/index.rst b/boards/arm/nrf9160dk_nrf52840/doc/index.rst deleted file mode 100644 index e16d6bc30e4e9d..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/doc/index.rst +++ /dev/null @@ -1,266 +0,0 @@ -.. _nrf9160dk_nrf52840: - -nRF9160 DK - nRF52840 -##################### - -Overview -******** - -The nRF52840 SoC on the nRF9160 DK (PCA10090) hardware provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -The nRF52840 SoC does not have any connection to the any of the LEDs, -buttons, switches, and Arduino pin headers on the nRF9160 DK board. It is, -however, possible to route some of the pins of the nRF52840 SoC to the nRF9160 -SiP. - -More information about the board can be found at -the `Nordic Low power cellular IoT`_ website. -The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -The nRF9160 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9160dk_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Programming and Debugging -************************* - -Applications for the ``nrf9160dk_nrf52840`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Make sure that the PROG/DEBUG switch on the DK is set to nRF52. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Remember to set the PROG/DEBUG switch on the DK to nRF52. - -See the following example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF52840 SoC is connected -to. Usually, under Linux it will be ``/dev/ttyACM1``. The ``/dev/ttyACM0`` -port is connected to the nRF9160 SiP on the board. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160dk_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards -with a Segger IC. - -Remember to set the PROG/DEBUG switch on the DK to nRF52. - -.. _nrf9160dk_board_controller_firmware: - -Board controller firmware -************************* - -The board controller firmware is a small snippet of code that takes care of -routing specific pins of the nRF9160 SiP to different components on the DK, -such as LEDs and buttons, UART interfaces (VCOMx) of the interface MCU, and -specific nRF52840 SoC pins. - -.. note:: - In nRF9160 DK revisions earlier than v0.14.0, nRF9160 signals routed to - other components on the DK are not simultaneously available on the DK - connectors. - -When compiling a project for nrf9160dk_nrf52840, the board controller firmware -will be compiled and run automatically after the Kernel has been initialized. - -By default, the board controller firmware will route the following: - -+--------------------------------+----------------------------------+ -| nRF9160 pins | Routed to | -+================================+==================================+ -| P0.26, P0.27, P0.28, and P0.29 | VCOM0 | -+--------------------------------+----------------------------------+ -| P0.01, P0.00, P0.15, and P0.14 | VCOM2 | -+--------------------------------+----------------------------------+ -| P0.02 | LED1 | -+--------------------------------+----------------------------------+ -| P0.03 | LED2 | -+--------------------------------+----------------------------------+ -| P0.04 | LED3 | -+--------------------------------+----------------------------------+ -| P0.05 | LED4 | -+--------------------------------+----------------------------------+ -| P0.08 | Switch 1 | -+--------------------------------+----------------------------------+ -| P0.09 | Switch 2 | -+--------------------------------+----------------------------------+ -| P0.06 | Button 1 | -+--------------------------------+----------------------------------+ -| P0.07 | Button 2 | -+--------------------------------+----------------------------------+ -| P0.17, P0.18, and P0.19 | Arduino pin headers | -+--------------------------------+----------------------------------+ -| P0.21, P0.22, and P0.23 | Trace interface | -+--------------------------------+----------------------------------+ -| COEX0, COEX1, and COEX2 | COEX interface | -+--------------------------------+----------------------------------+ - -For a complete list of all the routing options available, -see the `nRF9160 DK board control section in the nRF9160 DK User Guide`_. - -If you want to route some of the above pins differently or enable any of the -other available routing options, enable or disable the devicetree node that -represents the analog switch that provides the given routing. - -The following devicetree nodes are defined for the analog switches present -on the nRF9160 DK: - -+------------------------------------+------------------------------+ -| Devicetree node label | Analog switch name | -+====================================+==============================+ -| ``vcom0_pins_routing`` | nRF91_UART1 (nRF91_APP1) | -+------------------------------------+------------------------------+ -| ``vcom2_pins_routing`` | nRF91_UART2 (nRF91_APP2) | -+------------------------------------+------------------------------+ -| ``led1_pin_routing`` | nRF91_LED1 | -+------------------------------------+------------------------------+ -| ``led2_pin_routing`` | nRF91_LED2 | -+------------------------------------+------------------------------+ -| ``led3_pin_routing`` | nRF91_LED3 | -+------------------------------------+------------------------------+ -| ``led4_pin_routing`` | nRF91_LED4 | -+------------------------------------+------------------------------+ -| ``switch1_pin_routing`` | nRF91_SWITCH1 | -+------------------------------------+------------------------------+ -| ``switch2_pin_routing`` | nRF91_SWITCH2 | -+------------------------------------+------------------------------+ -| ``button1_pin_routing`` | nRF91_BUTTON1 | -+------------------------------------+------------------------------+ -| ``button2_pin_routing`` | nRF91_BUTTON2 | -+------------------------------------+------------------------------+ -| ``nrf_interface_pins_0_2_routing`` | nRF_IF0-2_CTRL (nRF91_GPIO) | -+------------------------------------+------------------------------+ -| ``nrf_interface_pins_3_5_routing`` | nRF_IF3-5_CTRL (nRF91_TRACE) | -+------------------------------------+------------------------------+ -| ``nrf_interface_pins_6_8_routing`` | nRF_IF6-8_CTRL (nRF91_COEX) | -+------------------------------------+------------------------------+ - -When building for the DK revision 0.14.0 or later, you can use the following -additional nodes (see :ref:`application_board_version` for information how to -build for specific revisions of the board): - -+------------------------------------+------------------------------+ -| Devicetree node label | Analog switch name | -+====================================+==============================+ -| ``nrf_interface_pin_9_routing`` | nRF_IF9_CTRL | -+------------------------------------+------------------------------+ -| ``io_expander_pins_routing`` | IO_EXP_EN | -+------------------------------------+------------------------------+ -| ``external_flash_pins_routing`` | EXT_MEM_CTRL | -+------------------------------------+------------------------------+ - -For example, if you want to enable the optional routing for the nRF9160 pins -P0.17, P0.18, and P0.19 so that they are routed to nRF52840 pins P0.17, P0.20, -and P0.15, respectively, add the following in the devicetree overlay in your -application: - -.. code-block:: devicetree - - &nrf_interface_pins_0_2_routing { - status = "okay"; - }; - -And if you want to, for example, disable routing for the VCOM2 pins, add the -following: - -.. code-block:: devicetree - - &vcom2_pins_routing { - status = "disabled"; - }; - -A few helper .dtsi files are provided in the directories -:zephyr_file:`boards/arm/nrf9160dk_nrf52840/dts` and -:zephyr_file:`boards/arm/nrf9160dk_nrf9160/dts`. They can serve as examples of -how to configure and use the above routings. You can also include them from -respective devicetree overlay files in your applications to conveniently -configure the signal routing between nRF9160 and nRF52840 on the nRF9160 DK. -For example, to use ``uart1`` on both these chips for communication between -them, add the following line in the overlays for applications on both sides: - -.. code-block:: devicetree - - #include - -References -********** - -.. target-notes:: -.. _Nordic Low power cellular IoT: https://www.nordicsemi.com/Products/Low-power-cellular-IoT -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF9160 DK board control section in the nRF9160 DK User Guide: https://infocenter.nordicsemi.com/topic/ug_nrf91_dk/UG/nrf91_DK/board_controller.html diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.yaml b/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.yaml deleted file mode 100644 index 4b9ffc34035b3d..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: nrf9160dk_nrf52840 -name: nRF9160-DK-NRF52840 -type: mcu -arch: arm -ram: 64 -flash: 512 -toolchain: - - zephyr - - gnuarmemb -supported: - - ble - - netif:openthread - - gpio -vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_defconfig b/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_defconfig deleted file mode 100644 index 58f290ba2710bc..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF9160DK_NRF52840=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf52840/revision.cmake b/boards/arm/nrf9160dk_nrf52840/revision.cmake deleted file mode 100644 index 585aae3dfdb901..00000000000000 --- a/boards/arm/nrf9160dk_nrf52840/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 0.14.0 - VALID_REVISIONS 0.7.0 0.14.0 -) diff --git a/boards/arm/nrf9160dk_nrf9160/CMakeLists.txt b/boards/arm/nrf9160dk_nrf9160/CMakeLists.txt deleted file mode 100644 index 75fa51e564c902..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2019 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(nrf52840_reset.c) diff --git a/boards/arm/nrf9160dk_nrf9160/Kconfig.board b/boards/arm/nrf9160dk_nrf9160/Kconfig.board deleted file mode 100644 index 180d60b18d8d5a..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9160 DK NRF9160 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_NRF9160DK_NRF9160 - bool "nRF9160 DK NRF9160" - -config BOARD_NRF9160DK_NRF9160_NS - bool "nRF9160 DK NRF9160 non-secure" - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160dk_nrf9160/Kconfig.defconfig b/boards/arm/nrf9160dk_nrf9160/Kconfig.defconfig deleted file mode 100644 index 7d9046f63b500d..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# nRF9160 DK NRF9160 board configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS - -config BOARD - default "nrf9160dk_nrf9160" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9160DK_NRF9160 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9160DK_NRF9160_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9160DK_NRF9160_NS - -config BT_HCI_VS - default y if BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,nrf52840_reset) - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) - -endif # BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS diff --git a/boards/arm/nrf9160dk_nrf9160/board.cmake b/boards/arm/nrf9160dk_nrf9160/board.cmake deleted file mode 100644 index fb5779f2967443..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/board.cmake +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_NRF9160DK_NRF9160_NS) - set(TFM_PUBLIC_KEY_FORMAT "full") -endif() - -if(CONFIG_TFM_FLASH_MERGED_BINARY) - set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) -endif() - -board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/nrf9160dk_nrf9160/doc/index.rst b/boards/arm/nrf9160dk_nrf9160/doc/index.rst deleted file mode 100644 index 8deb4848255548..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/doc/index.rst +++ /dev/null @@ -1,264 +0,0 @@ -.. _nrf9160dk_nrf9160: - -nRF9160 DK -########## - -Overview -******** - -The nRF9160 DK (PCA10090) is a single-board development kit for evaluation and -development on the nRF9160 SiP for LTE-M and NB-IoT. The nrf9160dk_nrf9160 -board configuration provides support for the Nordic Semiconductor nRF9160 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -.. figure:: img/nrf9160dk_nrf9160.jpg - :align: center - :alt: nRF9160 DK - - nRF9160 DK (Credit: Nordic Semiconductor) - -More information about the board can be found at the -`nRF9160 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9160 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9160dk_nrf9160 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -.. _nrf9160dk_additional_hardware: - -Additional hardware in v0.14.0+ -------------------------------- - -Starting from v0.14.0, additional hardware is available on the DK: - -* External flash memory (MX25R6435F, 64 Mb) -* I/O expander (PCAL6408A) that can be used to interface LEDs, slide switches, - and buttons - -To use this additional hardware, specify the revision of the board that -should be used when building your application (for more information, see -:ref:`application_board_version`). For example, to build for nRF9160 DK v1.0.0: - -.. zephyr-app-commands:: - :tool: all - :cd-into: - :board: nrf9160dk_nrf9160@1.0.0 - :goals: build - :compact: - -Remember to also enable routing for this additional hardware in the firmware for -:ref:`nrf9160dk_nrf52840` (see :ref:`nrf9160dk_board_controller_firmware`). - -Other hardware features have not been enabled yet for this board. -See `nRF9160 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF9160 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.2 -* LED2 (green) = P0.3 -* LED3 (green) = P0.4 -* LED4 (green) = P0.5 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.6 -* BUTTON2 = P0.7 -* SWITCH1 = P0.8 -* SWITCH2 = P0.9 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9160dk_nrf9160 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -Applications on the nRF9160 may contain a Secure and a Non-Secure firmware -image. The Secure image can be built using either Zephyr or -`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built -using Zephyr. The two alternatives are described below. - -.. note:: - - By default the Secure image for nRF9160 is built using TF-M. - -Building the Secure firmware using Zephyr ------------------------------------------ - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9160dk_nrf9160`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160dk_nrf9160_ns``. -3. Merge the two binaries together. - -Building the Secure firmware with TF-M --------------------------------------- - -The process to build the Secure firmware image using TF-M and the Non-Secure -firmware image using Zephyr requires the following action: - -1. Build the Non-Secure Zephyr application - using ``-DBOARD=nrf9160dk_nrf9160_ns``. - To invoke the building of TF-M the Zephyr build system requires the - Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by - default when building Zephyr as a Non-Secure application. - The Zephyr build system will perform the following steps automatically: - - * Build the Non-Secure firmware image as a regular Zephyr application - * Build a TF-M (secure) firmware image - * Merge the output binaries together - * Optionally build a bootloader image (MCUboot) - -.. note:: - - Depending on the TF-M configuration, an application DTS overlay may be - required, to adjust the Non-Secure image Flash and SRAM starting address - and sizes. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9160dk_nrf9160``. - - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9160 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9160dk_nrf9160 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9160 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9160 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9160-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml b/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml deleted file mode 100644 index 4b58b15317a579..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# NOTE: This file is replicated in nrf9160dk_nrf9160 and nrf9160dk_nrf52840. -# Any changes should be done in both instances. - -description: | - nRF9160 DK GPIO interface between nRF9160 and nRF52840 - - This interface can be used for inter-SoC communication on the DK. - The connections are as follows: - - | nRF9160 | | nRF52840 | - | P0.17 | -- nRF interface line 0 -- | P0.17 | - | P0.18 | -- nRF interface line 1 -- | P0.20 | - | P0.19 | -- nRF interface line 2 -- | P0.15 | - | P0.21 | -- nRF interface line 3 -- | P0.22 | - | P0.22 | -- nRF interface line 4 -- | P1.04 | - | P0.23 | -- nRF interface line 5 -- | P1.02 | - | COEX0 | -- nRF interface line 6 -- | P1.13 | - | COEX1 | -- nRF interface line 7 -- | P1.11 | - | COEX2 | -- nRF interface line 8 -- | P1.15 | - | P0.24 | -- nRF interface line 9 -- | P0.18 (nRESET) | (in v0.14.0 or later) - - Before particular lines of this interface can be used, the corresponding - analog switches that control the routing of involved nRF9160 pins must be - configured to provide the optional routing (i.e. to nRF52840). To achieve - this, set the status of respective devicetree nodes in the firmware for - the nrf9160dk_nrf52840 board to "okay": - - `nrf_interface_pins_0_2_routing` to enable lines 0-2 - - `nrf_interface_pins_3_5_routing` to enable lines 3-5 - - `nrf_interface_pins_6_8_routing` to enable lines 6-8 - - `nrf_interface_pin_9_routing` to enable line 9 (this line is only - available in nRF9160 DK v0.14.0 or later) - - NOTE: In nRF9160 DK revisions earlier than v0.14.0, when the above signals - from nRF9160 are routed to nRF52840, they are not available on the DK - connectors. - -compatible: "nordic,nrf9160dk-nrf52840-interface" - -include: [gpio-nexus.yaml, base.yaml] diff --git a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml b/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml deleted file mode 100644 index 1804fc51d4a0d3..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -# NOTE: This file is replicated in nrf9160dk_nrf9160 and nrf9160dk_nrf52840. -# Any changes should be done in both instances. - -description: GPIO used to reset nRF52840 on nRF9160 DK - -compatible: "nordic,nrf9160dk-nrf52840-reset" - -include: base.yaml - -properties: - status: - required: true - - gpios: - type: phandle-array - required: true - description: | - GPIO to use as nRF52840 reset line: output in nRF9160, input in nRF52840. diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.yaml b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.yaml deleted file mode 100644 index 7a6d3362b2308a..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: nrf9160dk_nrf9160 -name: nRF9160-DK-NRF9160 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 1024 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_defconfig b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_defconfig deleted file mode 100644 index aa61cc4ca3549e..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160DK_NRF9160=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.yaml b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.yaml deleted file mode 100644 index c2a98dcad05f2c..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: nrf9160dk_nrf9160_ns -name: nRF9160-DK-NRF9160-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - i2c - - pwm - - watchdog - - netif:modem - - gpio -vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_defconfig b/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_defconfig deleted file mode 100644 index 93343cc026430b..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_NRF9160DK_NRF9160_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/revision.cmake b/boards/arm/nrf9160dk_nrf9160/revision.cmake deleted file mode 100644 index 585aae3dfdb901..00000000000000 --- a/boards/arm/nrf9160dk_nrf9160/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 0.14.0 - VALID_REVISIONS 0.7.0 0.14.0 -) diff --git a/boards/arm/nrf9161dk_nrf9161/Kconfig.board b/boards/arm/nrf9161dk_nrf9161/Kconfig.board deleted file mode 100644 index 15bcdb167b377e..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# nRF9161 DK NRF9161 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9161_LACA - -config BOARD_NRF9161DK_NRF9161 - bool "nRF9161 DK NRF9161" - -config BOARD_NRF9161DK_NRF9161_NS - bool "nRF9161 DK NRF9161 non-secure" - -endif # SOC_NRF9161_LACA diff --git a/boards/arm/nrf9161dk_nrf9161/Kconfig.defconfig b/boards/arm/nrf9161dk_nrf9161/Kconfig.defconfig deleted file mode 100644 index ea7150ede5fe57..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/Kconfig.defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# nRF9161 DK NRF9161 board configuration - -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS - -config BOARD - default "nrf9161dk_nrf9161" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_NRF9161DK_NRF9161 && TRUSTED_EXECUTION_SECURE - -if BOARD_NRF9161DK_NRF9161_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_NRF9161DK_NRF9161_NS - -config BT_HCI_VS - default y if BT - -config BT_WAIT_NOP - default BT && $(dt_nodelabel_enabled,nrf5340_reset) - -config I2C - default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) - -endif # BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS diff --git a/boards/arm/nrf9161dk_nrf9161/doc/index.rst b/boards/arm/nrf9161dk_nrf9161/doc/index.rst deleted file mode 100644 index 18b214a7fde918..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/doc/index.rst +++ /dev/null @@ -1,203 +0,0 @@ -.. _nrf9161dk_nrf9161: - -nRF9161 DK -########## - -Overview -******** - -The nRF9161 DK (PCA10153) is a single-board development kit for evaluation and -development on the nRF9161 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The nrf9161dk_nrf9161 -board configuration provides support for the Nordic Semiconductor nRF9161 ARM -Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9161 DK website`_. The `Nordic Semiconductor Infocenter`_ -contains the processor's information and the datasheet. - - -Hardware -******** - -nRF9161 DK has two external oscillators. The frequency of -the slow clock is 32.768 kHz. The frequency of the main clock -is 32 MHz. - -Supported Features -================== - -The nrf9161dk_nrf9161 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| FLASH | external | spi | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIO | external | i2c | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | nRF53 | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - - -.. _nrf9161dk_additional_hardware: - -Other hardware features have not been enabled yet for this board. -See `nRF9161 DK website`_ and `Nordic Semiconductor Infocenter`_ -for a complete list of nRF9161 DK board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.0 -* LED2 (green) = P0.1 -* LED3 (green) = P0.4 -* LED4 (green) = P0.5 - -Push buttons and Switches -------------------------- - -* BUTTON1 = P0.8 -* BUTTON2 = P0.9 -* SWITCH1 = P0.18 -* SWITCH2 = P0.19 -* BOOT = SW5 = boot/reset - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented - with the System Protection Unit and is used to define secure and non-secure - memory maps. By default, all of the memory space (Flash, SRAM, and - peripheral address space) is defined to be secure accessible only. -- Secure boot. - - -Programming and Debugging -************************* - -nrf9161dk_nrf9161 supports the Armv8m Security Extension, and by default boots -in the Secure state. - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| -============================================================================= - -The process requires the following steps: - -1. Build the Secure Zephyr application using ``-DBOARD=nrf9161dk_nrf9161`` and - ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. -2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9161dk_nrf9161_ns``. -3. Merge the two binaries together. - -When building a Secure/Non-Secure application, the Secure application will -have to set the IDAU (SPU) configuration to allow Non-Secure access to all -CPU resources utilized by the Non-Secure application firmware. SPU -configuration shall take place before jumping to the Non-Secure application. - -Building a Secure only application -================================== - -Build the Zephyr app in the usual way (see :ref:`build_an_application` -and :ref:`application_run`), using ``-DBOARD=nrf9161dk_nrf9161``. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the nRF9161 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf9161dk_nrf9161 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the nRF9161 DK -********************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common.dtsi`. - -References -********** - -.. target-notes:: - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _nRF9161 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9161-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.yaml b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.yaml deleted file mode 100644 index af07642881096a..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: nrf9161dk_nrf9161 -name: nRF9161-DK-NRF9161 -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 88 -flash: 1024 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - gpio - - i2c - - pwm - - spi - - watchdog - - counter -vendor: nordic diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_defconfig b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_defconfig deleted file mode 100644 index 1e04a544d95897..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9161_LACA=y -CONFIG_BOARD_NRF9161DK_NRF9161=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.yaml b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.yaml deleted file mode 100644 index 2d2da2026f4761..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: nrf9161dk_nrf9161_ns -name: nRF9161-DK-NRF9161-Non-Secure -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 128 -flash: 192 -supported: - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - i2c - - pwm - - watchdog - - netif:modem -vendor: nordic diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_defconfig b/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_defconfig deleted file mode 100644 index 97649b3d4d81df..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9161_LACA=y -CONFIG_BOARD_NRF9161DK_NRF9161_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/pre_dt_board.cmake b/boards/arm/nrf9161dk_nrf9161/pre_dt_board.cmake deleted file mode 100644 index c8267afd1b470a..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - flash-controller@39000 & kmu@39000 -# - power@5000 & clock@5000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/nrf9161dk_nrf9161/revision.cmake b/boards/arm/nrf9161dk_nrf9161/revision.cmake deleted file mode 100644 index 2a899f61a83b18..00000000000000 --- a/boards/arm/nrf9161dk_nrf9161/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 0.9.0 - VALID_REVISIONS 0.7.0 0.9.0 -) diff --git a/boards/arm/nucleo_c031c6/Kconfig.board b/boards/arm/nucleo_c031c6/Kconfig.board deleted file mode 100644 index 7cc977547553b1..00000000000000 --- a/boards/arm/nucleo_c031c6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32C031C6 MCU configuration - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_C031C6 - bool "NUCLEO-64 C031C6 Development Board" - depends on SOC_STM32C031XX diff --git a/boards/arm/nucleo_c031c6/Kconfig.defconfig b/boards/arm/nucleo_c031c6/Kconfig.defconfig deleted file mode 100644 index acaa8c977eb464..00000000000000 --- a/boards/arm/nucleo_c031c6/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32C031C6 MCU - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_C031C6 - -config BOARD - default "nucleo_c031c6" - -endif # BOARD_NUCLEO_C031C6 diff --git a/boards/arm/nucleo_c031c6/doc/index.rst b/boards/arm/nucleo_c031c6/doc/index.rst deleted file mode 100644 index 3e28230cba2d77..00000000000000 --- a/boards/arm/nucleo_c031c6/doc/index.rst +++ /dev/null @@ -1,151 +0,0 @@ -.. _nucleo_c031c6_board: - -ST Nucleo C031C6 -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32C031C6 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_c031c6.jpg - :align: center - :alt: Nucleo C031C6 - -More information about the board can be found at the `Nucleo C031C6 website`_. - -Hardware -******** -Nucleo C031C6 provides the following hardware components: - -- STM32 microcontroller in 48-pin package featuring 32 Kbytes of Flash memory - and 12 Kbytes of SRAM. -- Extension resource: - - - Arduino* Uno V3 connectivity - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Current consumption measurement (IDD) - -- Four LEDs: - - - USB communication (LD1), USB power fault LED (LD2), power LED (LD3), - user LED (LD4) - -- Two push-button: USER and RESET - -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32C031C6 can be found here: -`STM32C0x1 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_c031c6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| IWDG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| WWDG | on-chip | window watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- LD4 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_c031c6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo C031C6 board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo C031C6 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_c031c6 - :goals: build flash - -You will see the LED blinking every second. - -References -********** - -.. target-notes:: - -.. _Nucleo C031C6 website: - https://www.st.com/en/evaluation-tools/nucleo-c031c6.html - -.. _STM32C0x1 reference manual: - https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-64bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/um2953-stm32c0-nucleo64-board-mb1717-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig b/boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig deleted file mode 100644 index c955a55e0e45be..00000000000000 --- a/boards/arm/nucleo_c031c6/nucleo_c031c6_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32C0X=y - -# Platform Configuration -CONFIG_SOC_STM32C031XX=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f030r8/Kconfig.board b/boards/arm/nucleo_f030r8/Kconfig.board deleted file mode 100644 index 39bd7c786d8fc2..00000000000000 --- a/boards/arm/nucleo_f030r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F030R8 MCU configuration - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F030R8 - bool "NUCLEO-64 F030R8 Development Board" - depends on SOC_STM32F030X8 diff --git a/boards/arm/nucleo_f030r8/Kconfig.defconfig b/boards/arm/nucleo_f030r8/Kconfig.defconfig deleted file mode 100644 index 7b5331693fe788..00000000000000 --- a/boards/arm/nucleo_f030r8/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F030R8 MCU - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F030R8 - -config BOARD - default "nucleo_f030r8" - -endif # BOARD_NUCLEO_F030R8 diff --git a/boards/arm/nucleo_f030r8/doc/index.rst b/boards/arm/nucleo_f030r8/doc/index.rst deleted file mode 100644 index a6f104398c75e4..00000000000000 --- a/boards/arm/nucleo_f030r8/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _nucleo_f030r8_board: - -ST Nucleo F030R8 -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F030R8 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f030r8.jpg - :align: center - :alt: Nucleo F030R8 - -More information about the board can be found at the `Nucleo F030R8 website`_. - -Hardware -******** -Nucleo F030R8 provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F030R8 can be found here: - -- `STM32F030 reference manual`_ -- `STM32F030 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f030r8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f030r8_connectors.jpg - :align: center - :alt: Nucleo F030R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 -- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD1 : PA5 -- ADC : PA0 - - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f030r8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. _nucleo-f030r8-flashing: - -Flashing -======== - -Nucleo F030R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F030R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8 - :goals: build flash - -You will see the LED blinking every second. - -If using the C-01 board, select revision '1' that supports the board. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8@1 - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8 - :maybe-skip-config: - :goals: debug - -Again you have to use the adapted command for C-01. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f030r8@1 - :maybe-skip-config: - :goals: debug - -Board Revisions -*************** - -Nucleo F030R8 has some version of board variants. -`STM32 Nucleo-64 board User Manual`_ mentions to Nucleo board variants. - - | *The board version MB1136 C-01 or MB1136 C-02 is mentioned on the sticker, placed on the bottom side of the PCB.* - | *The board marking MB1136 C-01 corresponds to a board, configured as HSE not used.* - | *The board marking MB1136 C-02 (or higher) corresponds to a board, configured to use ST-LINK MCO as the clock input.* - -Using revision **2** adapted for C-02(or higher) as default when not explicitly selecting revisions. -If using the C-01 board, select revision **1**. -Please see :ref:`Flashing ` section. - -References -********** - -.. target-notes:: - -.. _Nucleo F030R8 website: - https://www.st.com/en/evaluation-tools/nucleo-f030r8.html - -.. _STM32F030 reference manual: - https://www.st.com/resource/en/reference_manual/dm00091010.pdf - -.. _STM32F030 data sheet: - https://www.st.com/resource/en/datasheet/stm32f030r8.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_1.conf b/boards/arm/nucleo_f030r8/nucleo_f030r8_1.conf deleted file mode 100644 index 39cc277d78d60b..00000000000000 --- a/boards/arm/nucleo_f030r8/nucleo_f030r8_1.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_2.conf b/boards/arm/nucleo_f030r8/nucleo_f030r8_2.conf deleted file mode 100644 index 39cc277d78d60b..00000000000000 --- a/boards/arm/nucleo_f030r8/nucleo_f030r8_2.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/nucleo_f030r8/revision.cmake b/boards/arm/nucleo_f030r8/revision.cmake deleted file mode 100644 index 7e5ddf37782c60..00000000000000 --- a/boards/arm/nucleo_f030r8/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2022 TOKITA Hiroshi -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_check_revision(FORMAT NUMBER - DEFAULT_REVISION 2) diff --git a/boards/arm/nucleo_f031k6/Kconfig.board b/boards/arm/nucleo_f031k6/Kconfig.board deleted file mode 100644 index d0095535765166..00000000000000 --- a/boards/arm/nucleo_f031k6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F031K6 MCU configuration - -# Copyright (c) 2021 Sebastian Schwabe -# SPDX -License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F031K6 - bool "NUCLEO-32 F031K6 Development Board" - depends on SOC_STM32F031X6 diff --git a/boards/arm/nucleo_f031k6/Kconfig.defconfig b/boards/arm/nucleo_f031k6/Kconfig.defconfig deleted file mode 100644 index 6120548e9e2cae..00000000000000 --- a/boards/arm/nucleo_f031k6/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F031K6 MCU - -# Copyright (c) 2021 Sebastian Schwabe -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F031K6 - -config BOARD - default "nucleo_f031k6" - -endif # BOARD_NUCLEO_F031K6 diff --git a/boards/arm/nucleo_f031k6/doc/index.rst b/boards/arm/nucleo_f031k6/doc/index.rst deleted file mode 100644 index ccfb1540f26f3b..00000000000000 --- a/boards/arm/nucleo_f031k6/doc/index.rst +++ /dev/null @@ -1,155 +0,0 @@ -.. _nucleo_f031k6_board: - -ST Nucleo F031K6 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32F031K6 MCU, supports Arduino nano connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f031k6.jpg - :align: center - :alt: Nucleo F031k6 - -More information about the board can be found at the `Nucleo F031K6 website`_. - -Hardware -******** -Nucleo F031K6 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- reset push button - -More information about STM32F031K6 can be found here: - -- `STM32F031 reference manual`_ -- `STM32F031 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f031k6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. - -Board connectors: ------------------ -.. image:: img/nucleo_f031k6_connectors.jpg - :align: center - :alt: Nucleo F031K6 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f031k6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F030R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f031k6 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f031k6 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F031K6 website: - https://www.st.com/en/evaluation-tools/nucleo-f031k6.html - -.. _STM32F031 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32F031 data sheet: - https://www.st.com/resource/en/datasheet/stm32f031k6.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f042k6/Kconfig.board b/boards/arm/nucleo_f042k6/Kconfig.board deleted file mode 100644 index e9663d72e0a2fe..00000000000000 --- a/boards/arm/nucleo_f042k6/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F031K6 MCU configuration - -# Copyright (c) 2023 STMicroelectronics - -# SPDX -License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F042K6 - bool "NUCLEO-32 F042K6 Development Board" - depends on SOC_STM32F042X6 diff --git a/boards/arm/nucleo_f042k6/Kconfig.defconfig b/boards/arm/nucleo_f042k6/Kconfig.defconfig deleted file mode 100644 index dab2333ef375e1..00000000000000 --- a/boards/arm/nucleo_f042k6/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Nucleo-32 development board with STM32F042K6 MCU - -# Copyright (c) 2023 STMicroelectronics - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F042K6 - -config BOARD - default "nucleo_f042k6" - -endif # BOARD_NUCLEO_F042K6 diff --git a/boards/arm/nucleo_f042k6/doc/index.rst b/boards/arm/nucleo_f042k6/doc/index.rst deleted file mode 100644 index 66ad80adeedc05..00000000000000 --- a/boards/arm/nucleo_f042k6/doc/index.rst +++ /dev/null @@ -1,155 +0,0 @@ -.. _nucleo_f042k6_board: - -ST Nucleo F042K6 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32F042K6 MCU, supports Arduino nano connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f042k6.jpg - :align: center - :alt: Nucleo F042k6 - -More information about the board can be found at the `Nucleo F042K6 website`_. - -Hardware -******** -Nucleo F042K6 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- reset push button - -More information about STM32F042K6 can be found here: - -- `STM32F042 reference manual`_ -- `STM32F042 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f042k6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. - -Board connectors: ------------------ -.. image:: img/nucleo_f042k6_connectors.jpg - :align: center - :alt: Nucleo F042K6 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f042k6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F042K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F042K6 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f042k6 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f042k6 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F042K6 website: - https://www.st.com/en/evaluation-tools/nucleo-f042k6.html - -.. _STM32F042 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32F042 data sheet: - https://www.st.com/resource/en/datasheet/stm32f042k6.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig b/boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig deleted file mode 100644 index 0f69a1be64cbe5..00000000000000 --- a/boards/arm/nucleo_f042k6/nucleo_f042k6_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F042X6=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f070rb/Kconfig.board b/boards/arm/nucleo_f070rb/Kconfig.board deleted file mode 100644 index 2745ba2a20c12e..00000000000000 --- a/boards/arm/nucleo_f070rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO_F070RB board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F070RB - bool "NUCLEO-64 F070RB Development Board" - depends on SOC_STM32F070XB diff --git a/boards/arm/nucleo_f070rb/Kconfig.defconfig b/boards/arm/nucleo_f070rb/Kconfig.defconfig deleted file mode 100644 index 970df859b3611a..00000000000000 --- a/boards/arm/nucleo_f070rb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# NUCLEO_F070RB board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F070RB - -config BOARD - default "nucleo_f070rb" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F070RB diff --git a/boards/arm/nucleo_f070rb/doc/index.rst b/boards/arm/nucleo_f070rb/doc/index.rst deleted file mode 100644 index 50a96e3fed4a21..00000000000000 --- a/boards/arm/nucleo_f070rb/doc/index.rst +++ /dev/null @@ -1,180 +0,0 @@ -.. _nucleo_f070rb_board: - -ST Nucleo F070RB -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F070RB MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f070rb.jpg - :align: center - :alt: Nucleo F070RB - -More information about the board can be found at the `Nucleo F070RB website`_. - -Hardware -******** -Nucleo F070RB provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F070RB can be found in -the `STM32F070 reference manual`_ . - - -Supported Features -================== - -The Zephyr nucleo_f070rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | SPI controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f070rb_connectors.jpg - :align: center - :alt: Nucleo F070RB connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB11 -- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 -- USER_PB : PC13 -- LD1 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f070rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F070RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F070RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f070rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f070rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F070RB website: - https://www.st.com/en/evaluation-tools/nucleo-f070rb.html - -.. _STM32F070 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig b/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig deleted file mode 100644 index 088920775b4f61..00000000000000 --- a/boards/arm/nucleo_f070rb/nucleo_f070rb_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F070XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f091rc/Kconfig.board b/boards/arm/nucleo_f091rc/Kconfig.board deleted file mode 100644 index d109e7c4898329..00000000000000 --- a/boards/arm/nucleo_f091rc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F091RC MCU configuration - -# Copyright (c) 2017 Bobby Noelte -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F091RC - bool "NUCLEO-64 F091RC Development Board" - depends on SOC_STM32F091XC diff --git a/boards/arm/nucleo_f091rc/Kconfig.defconfig b/boards/arm/nucleo_f091rc/Kconfig.defconfig deleted file mode 100644 index bd4fedf1b5a948..00000000000000 --- a/boards/arm/nucleo_f091rc/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F091RC MCU - -# Copyright (c) 2017 Bobby Noelte -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F091RC - -config BOARD - default "nucleo_f091rc" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F091RC diff --git a/boards/arm/nucleo_f091rc/doc/index.rst b/boards/arm/nucleo_f091rc/doc/index.rst deleted file mode 100644 index 9ff09e28770bb1..00000000000000 --- a/boards/arm/nucleo_f091rc/doc/index.rst +++ /dev/null @@ -1,197 +0,0 @@ -.. _nucleo_f091rc_board: - -ST Nucleo F091RC -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F091RC MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f091rc.jpg - :align: center - :alt: Nucleo F091RC - -More information about the board can be found at the `Nucleo F091RC website`_. - -Hardware -******** -Nucleo F091RC provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F091RC can be found in the -`STM32F091 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_f091rc board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | SPI controller | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f091rc_connectors.jpg - :align: center - :alt: Nucleo F091RC connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 (disabled by default, uses same pins as CAN) -- CAN RX/TX : PA11/PA12 -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 -- USER_PB : PC13 -- LD2 : PA5 -- DAC_OUT1 : PA4 -- PWM_2_CH1 : PA5 (might conflict with SPI1) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f091rc`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F091RC ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f091rc - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f091rc - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F091RC website: - https://www.st.com/en/evaluation-tools/nucleo-f091rc.html - -.. _STM32F091 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig b/boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig deleted file mode 100644 index c166772f8e33f3..00000000000000 --- a/boards/arm/nucleo_f091rc/nucleo_f091rc_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F091XC=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f103rb/Kconfig.board b/boards/arm/nucleo_f103rb/Kconfig.board deleted file mode 100644 index e175a30e368fb8..00000000000000 --- a/boards/arm/nucleo_f103rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F103RB board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F103RB - bool "NUCLEO-64 F103RB Development Board" - depends on SOC_STM32F103XB diff --git a/boards/arm/nucleo_f103rb/Kconfig.defconfig b/boards/arm/nucleo_f103rb/Kconfig.defconfig deleted file mode 100644 index 3d4c0581a96c2f..00000000000000 --- a/boards/arm/nucleo_f103rb/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# NUCLEO-64 F103RB board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F103RB - -config BOARD - default "nucleo_f103rb" - -endif # BOARD_NUCLEO_F103RB diff --git a/boards/arm/nucleo_f103rb/doc/index.rst b/boards/arm/nucleo_f103rb/doc/index.rst deleted file mode 100644 index 8f67b04ad62649..00000000000000 --- a/boards/arm/nucleo_f103rb/doc/index.rst +++ /dev/null @@ -1,190 +0,0 @@ -.. _nucleo_f103rb_board: - -ST Nucleo F103RB -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32F103RB MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f103rb.jpg - :align: center - :alt: Nucleo F103RB - -More information about the board can be found at the `Nucleo F103RB website`_. - -Hardware -******** -Nucleo F103RB provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F103RB can be found here: - -- `STM32F103 reference manual`_ -- `STM32F103 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_f103rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f103rb_connectors.jpg - :align: center - :alt: Nucleo F103RB connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI2 SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- I2C1 SDA/SCL: PB9/PB8 (Arduino I2C) -- PWM1_CH1: PA8 -- USER_PB : PC13 -- LD1 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f103rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F103RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F103RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f103rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f103rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F103RB website: - https://www.st.com/en/evaluation-tools/nucleo-f103rb.html - -.. _STM32F103 reference manual: - https://www.st.com/resource/en/reference_manual/cd00171190.pdf - -.. _STM32F103 data sheet: - https://www.st.com/resource/en/datasheet/stm32f103rb.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f207zg/Kconfig.board b/boards/arm/nucleo_f207zg/Kconfig.board deleted file mode 100644 index b3054d4ae341b0..00000000000000 --- a/boards/arm/nucleo_f207zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F207ZG board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F207ZG - bool "NUCLEO-144 F207ZG Development Board" - depends on SOC_STM32F207XX diff --git a/boards/arm/nucleo_f207zg/Kconfig.defconfig b/boards/arm/nucleo_f207zg/Kconfig.defconfig deleted file mode 100644 index b3b48232483acb..00000000000000 --- a/boards/arm/nucleo_f207zg/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# NUCLEO-144 F207ZG board configuration - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F207ZG - -config BOARD - default "nucleo_f207zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F207ZG diff --git a/boards/arm/nucleo_f207zg/doc/index.rst b/boards/arm/nucleo_f207zg/doc/index.rst deleted file mode 100644 index e9696365b1cc69..00000000000000 --- a/boards/arm/nucleo_f207zg/doc/index.rst +++ /dev/null @@ -1,206 +0,0 @@ -.. _nucleo_f207zg_board: - -ST Nucleo F207ZG -################ - -Overview -******** - -The Nucleo F207ZG board features an ARM Cortex-M3 based STM32F207ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F207ZG board: - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f207zg.jpg - :align: center - :alt: Nucleo F207ZG - -More information about the board can be found at the `Nucleo F207ZG website`_. - -Hardware -******** - -Nucleo F207ZG provides the following hardware components: - -- STM32F207ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M3 CPU -- 120 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 24 channels -- RTC -- 17 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (6) -- I2C (3) -- SPI (3) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- 10/100 Ethernet MAC with dedicated DMA -- CRC calculation unit -- True random number generator - -More information about STM32F207ZG can be found here: - -- `STM32F207ZG on www.st.com`_ -- `STM32F207 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_207zg board configuration supports the following hardware features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | Random Number Generator | -+-------------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-------------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo F207ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f207zg_zio_left.jpg - :align: center - :alt: Nucleo F207ZG ZIO connectors (left) -.. image:: img/nucleo_f207zg_zio_right.jpg - :align: center - :alt: Nucleo F207ZG ZIO connectors (right) -.. image:: img/nucleo_f207zg_morpho_left.jpg - :align: center - :alt: Nucleo F207ZG Morpho connectors (left) -.. image:: img/nucleo_f207zg_morpho_right.jpg - :align: center - :alt: Nucleo F207ZG Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB_DM : PA11 -- USB_DP : PA12 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- DAC: PA4 -- ADC: PA0 -- PWM_1_CH1 : PE9 - -System Clock ------------- - -Nucleo F207ZG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 120MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F207ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - -Network interface ------------------ - -Ethernet configured as the default network interface - -USB ---- -Nucleo F207ZG board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its micro USB connector -(USB USER). Only USB device function is supported in Zephyr at the moment. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -Programming and Debugging -************************* - -Nucleo F207ZG board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F207ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f207zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F207ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f207zg.html - -.. _STM32F207 reference manual: - https://www.st.com/resource/en/reference_manual/cd00225773.pdf diff --git a/boards/arm/nucleo_f302r8/Kconfig.board b/boards/arm/nucleo_f302r8/Kconfig.board deleted file mode 100644 index cc238c11040dfa..00000000000000 --- a/boards/arm/nucleo_f302r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F302R8 board configuration - -# Copyright (c) 2018 Seitz & Associates -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F302R8 - bool "NUCLEO-64 F302R8 Development Board" - depends on SOC_STM32F302X8 diff --git a/boards/arm/nucleo_f302r8/Kconfig.defconfig b/boards/arm/nucleo_f302r8/Kconfig.defconfig deleted file mode 100644 index abf1484c1b6996..00000000000000 --- a/boards/arm/nucleo_f302r8/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# NUCLEO-64 F302R8 board configuration - -# Copyright (c) 2018 Seitz & Associates -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F302R8 - -config BOARD - default "nucleo_f302r8" - -endif # BOARD_NUCLEO_F302R8 diff --git a/boards/arm/nucleo_f302r8/doc/index.rst b/boards/arm/nucleo_f302r8/doc/index.rst deleted file mode 100644 index e554549a6feca8..00000000000000 --- a/boards/arm/nucleo_f302r8/doc/index.rst +++ /dev/null @@ -1,168 +0,0 @@ -.. _nucleo_f302r8_board: - -ST Nucleo F302R8 -################ - -Overview -******** - -The Nucleo F302R8 board features an ARM Cortex-M4 based STM32F302R8 -mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. -Here are some highlights of the Nucleo F302R8 board: - -- STM32 microcontroller in LQFP64 package -- LSE crystal: 32.768 kHz crystal oscillator -- Two types of extension resources: - - - Arduino* Uno V3 connectors - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- One user LED -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f302r8.jpg - :align: center - :alt: Nucleo F302R8 - -More information about the board can be found at the `Nucleo F302R8 website`_, -and in the `STM32 Nucleo-64 board User Manual`_. - -Hardware -******** - -The Nucleo F302R8 provides the following hardware components: - -- STM32F302R8T6 in QFP64 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 64 MB Flash -- 16 KB SRAM -- RTC -- Advanced-control Timer -- General Purpose Timers (4) -- Basic Timer -- Watchdog Timers (2) -- PWM channels (18) -- SPI/I2S (2) -- I2C (3) -- USART/UART (3/3) -- USB 2.0 FS with on-chip PHY -- CAN (2) -- GPIO with external interrupt capability -- DMA channels (7) -- Capacitive sensing channels (18) -- 12-bit ADC with 15 channels -- 12-bit D/A converter -- Analog comparator (3) -- Op amp - - -More information about the STM32F302R8 can be found here: - -- `STM32F302R8 on www.st.com`_ -- `STM32F302R8 reference manual`_ -- `STM32F302R8 datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f302r8 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig`` - -Connections and IOs -=================== - -The Nucleo F302R8 Board has 5 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -Board connectors: ------------------ -.. image:: img/nucleo_f302r8_connectors.jpg - :align: center - :alt: Nucleo F302R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F302R8 board features an Arduino Uno V3 connector and a ST -morpho connector. Board is configured as follows: - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- UART_3 TX/RX : PC10/PC11 -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI2 CS/SCK/MISO/MOSI : PB6/PB13/PB14/P15 (Arduino SPI) -- PWM_2_CH2 : PA0 -- USER_PB : PC13 -- LD2 : PB13 - -System Clock ------------- - -The Nucleo F302R8 System Clock can be driven by an internal or -external oscillator, as well as by the main PLL clock. By default the -System Clock is driven by the PLL clock at 72 MHz. The input to the -PLL is an 8 MHz external clock supplied by the processor of the -on-board ST-LINK/V2-1 debugger/programmer. - -Serial Port ------------ - -The Nucleo F302R8 board has 3 UARTs. The Zephyr console output is assigned -to UART2. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -The Nucleo F302R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F302R8 website: - https://www.st.com/en/evaluation-tools/nucleo-f302r8.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F302R8 on www.st.com: - https://www.st.com/en/microcontrollers/stm32f302r8.html - -.. _STM32F302R8 reference manual: - https://www.st.com/resource/en/reference_manual/dm00094349.pdf - -.. _STM32F302R8 datasheet: - https://www.st.com/resource/en/datasheet/stm32f302r8.pdf diff --git a/boards/arm/nucleo_f303k8/Kconfig.board b/boards/arm/nucleo_f303k8/Kconfig.board deleted file mode 100644 index 88b26aab9a38b5..00000000000000 --- a/boards/arm/nucleo_f303k8/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# NUCLEO-32 F303k8 board configuration - -# Copyright (c) 2020 Sebastian Schwabe -# Fabian Paschke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F303K8 - bool "NUCLEO-32 F303K8 Development Board" - depends on SOC_STM32F303X8 diff --git a/boards/arm/nucleo_f303k8/Kconfig.defconfig b/boards/arm/nucleo_f303k8/Kconfig.defconfig deleted file mode 100644 index c52e0887f31fc7..00000000000000 --- a/boards/arm/nucleo_f303k8/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# NUCLEO-32 F303k8 board configuration - -# Copyright (c) 2020 Sebastian Schwabe -# Fabian Paschke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F303K8 - -config BOARD - default "nucleo_f303k8" - -endif # BOARD_NUCLEO_F303K8 diff --git a/boards/arm/nucleo_f303k8/doc/index.rst b/boards/arm/nucleo_f303k8/doc/index.rst deleted file mode 100644 index 5aab35406634b7..00000000000000 --- a/boards/arm/nucleo_f303k8/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _nucleo_f303k8_board: - -ST Nucleo F303K8 -################ - -Overview -******** - -The Nucleo F303K8 board features an ARM Cortex-M4 based STM32F303K8 -mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. -Here are some highlights of the Nucleo F303K8 board: - -- STM32 microcontroller in LQFP32 package -- one type of extension resources: - -- Arduino™ Nano V3 connectivity support - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - -- 5 V from ST-LINK/V2-1 USB VBUS -- External power sources: 3.3 V, 5V and 7 - 12 V - -- One user LED -- One push-buttons: RESET - -.. image:: img/nucleo_f303k8.jpg - :align: center - :alt: Nucleo F303K8 - -More information about the board can be found at the `Nucleo F303K8 website`_, -and in the `STM32 Nucleo-32 board User Manual`_. - -Hardware -******** - -The Nucleo F303K8 provides the following hardware components: - -- STM32F303K8T6 in LQFP32 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 64 MB Flash -- 12 KB SRAM -- RTC -- Advanced-control Timer -- General Purpose Timers (5) -- Basic Timer (2) -- Watchdog Timers (2) -- PWM channels (12) -- SPI/I2S (1) -- I2C (1) -- USART/UART (2) -- CAN (1) -- GPIO with external interrupt capability -- DMA channels (7) -- Capacitive sensing channels (18) -- 12-bit ADC with 21 channels -- 12-bit D/A converter -- Analog comparator (3) -- Op amp - - -More information about the STM32F303K8 can be found here: - -- `STM32F303K8 on www.st.com`_ -- `STM32F303K8 reference manual`_ -- `STM32F303K8 datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f303k8 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig`` - -Connections and IOs -=================== - -The Nucleo F303K8 Board has 1 GPIO controller. This controllers is responsible -for input/output, pull-up, etc. - -Board connectors: ------------------ -.. image:: img/nucleo_f303k8_pinout.jpg - :align: center - :alt: Nucleo F303K8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F303K8 board features an Arduino Zero V3 connector. Board is configured as follows: - -- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB7/PB6 -- SPI1 CS/SCK/MISO/MOSI : PA_4/PA_5/PB_4/PA_7 -- LD2 : PB3 - -System Clock ------------- - -The Nucleo F303K8 System Clock can be driven by an internal or -external oscillator, as well as by the main PLL clock. By default the -System Clock is driven by the PLL clock at 72 MHz. The input to the -PLL is an 8 MHz internal clock supply. - -Serial Port ------------ - -The Nucleo F303K8 board has 2 UARTs. The Zephyr console output is assigned -to UART2. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -The Nucleo F303K8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F303K8 website: - https://www.st.com/en/evaluation-tools/nucleo-F303K8.html - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf - -.. _STM32F303K8 on www.st.com: - https://www.st.com/en/microcontrollers/stm32F303K8.html - -.. _STM32F303K8 reference manual: - https://www.st.com/resource/en/reference_manual/dm00043574-stm32f303xbcde-stm32f303x68-stm32f328x8-stm32f358xc-stm32f398xe-advanced-armbased-mcus-stmicroelectronics.pdf - -.. _STM32F303K8 datasheet: - https://www.st.com/resource/en/datasheet/stm32f303k8.pdf diff --git a/boards/arm/nucleo_f303re/Kconfig.board b/boards/arm/nucleo_f303re/Kconfig.board deleted file mode 100644 index 0b9bc11bf96fda..00000000000000 --- a/boards/arm/nucleo_f303re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F303RE board configuration - -# Copyright (c) 2020 Paul M. Bendixen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F303RE - bool "NUCLEO-64 F303RE Development Board" - depends on SOC_STM32F303XE diff --git a/boards/arm/nucleo_f303re/Kconfig.defconfig b/boards/arm/nucleo_f303re/Kconfig.defconfig deleted file mode 100644 index 97aa8100d7216a..00000000000000 --- a/boards/arm/nucleo_f303re/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# NUCLEO-64 F302R8 board configuration - -# Copyright (c) 2020 Paul M. Bendixen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F303RE - -config BOARD - default "nucleo_f303re" - -endif # BOARD_NUCLEO_F303RE diff --git a/boards/arm/nucleo_f303re/doc/index.rst b/boards/arm/nucleo_f303re/doc/index.rst deleted file mode 100644 index 387a2bc28d2a21..00000000000000 --- a/boards/arm/nucleo_f303re/doc/index.rst +++ /dev/null @@ -1,162 +0,0 @@ -.. _nucleo_f303re_board: - -ST Nucleo F303RE -################ - -Overview -******** - -The Nucleo F303RE board features an ARM Cortex-M4 based STM32F303RE -mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. -Here are some highlights of the Nucleo F303RE board: - -- STM32 microcontroller in LQFP64 package -- LSE crystal: 32.768 kHz crystal oscillator -- Two types of extension resources: - - - Arduino* Uno V3 connectors - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- One user LED -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f303re.jpg - :align: center - :alt: Nucleo F303RE - -More information about the board can be found at the `Nucleo F303RE website`_, -and in the `STM32 Nucleo-64 board User Manual`_. - -Hardware -******** - -The Nucleo F303RE provides the following hardware components: - -- STM32F303RET6 in QFP64 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 512 MB Flash -- 64 + 16 KB SRAM -- RTC -- Advanced-control Timer -- General Purpose Timers (4) -- Basic Timer -- Watchdog Timers (2) -- PWM channels (18) -- SPI/I2S (2) -- I2C (3) -- USART/UART (3/3) -- USB 2.0 FS with on-chip PHY -- CAN (2) -- GPIO with external interrupt capability -- DMA channels (12) -- Capacitive sensing channels (18) -- 12-bit ADC with 40 channels (4) -- 12-bit D/A converter with two channels -- Analog comparator (7) -- Op amp (4) -- Capacitive sensing 24 channels - - -More information about the STM32F303RE can be found here: - -- `STM32F303RE on www.st.com`_ -- `STM32F303RE reference manual`_ -- `STM32F303RE datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f303re board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f303re/nucleo_f303re_defconfig`` - -Connections and IOs -=================== - -The Nucleo F303RE Board has 5 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -Board connectors: ------------------ -.. image:: img/nucleo_connectors.jpg - :align: center - :alt: Nucleo F303RE connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F303RE board features an Arduino Uno V3 connector and a ST -morpho connector. Board is configured as follows: - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD2 : PA5 - -System Clock ------------- - -The Nucleo F303RE System Clock can be driven by an internal or -external oscillator, as well as by the main PLL clock. By default the -System Clock is driven by the PLL clock at 72 MHz. The input to the -PLL is an 8 MHz external clock supplied by the processor of the -on-board ST-LINK/V2-1 debugger/programmer. - -Serial Port ------------ - -The Nucleo F303RE board has 2 UARTs. The Zephyr console output is assigned -to UART2. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -The Nucleo F303RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F303RE website: - https://www.st.com/en/evaluation-tools/nucleo-f303re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F303RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f303re.html - -.. _STM32F303RE reference manual: - https://www.st.com/resource/en/reference_manual/dm00043574.pdf - -.. _STM32F303RE datasheet: - https://www.st.com/resource/en/datasheet/stm32f303re.pdf diff --git a/boards/arm/nucleo_f334r8/Kconfig.board b/boards/arm/nucleo_f334r8/Kconfig.board deleted file mode 100644 index 2c2e312c83738b..00000000000000 --- a/boards/arm/nucleo_f334r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F334R8 MCU configuration - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F334R8 - bool "NUCLEO-64 F334R8 Development Board" - depends on SOC_STM32F334X8 diff --git a/boards/arm/nucleo_f334r8/Kconfig.defconfig b/boards/arm/nucleo_f334r8/Kconfig.defconfig deleted file mode 100644 index ad4f0b8979f2e0..00000000000000 --- a/boards/arm/nucleo_f334r8/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32F334R8 MCU - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F334R8 - -config BOARD - default "nucleo_f334r8" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F334R8 diff --git a/boards/arm/nucleo_f334r8/doc/index.rst b/boards/arm/nucleo_f334r8/doc/index.rst deleted file mode 100644 index 64824e787ebab3..00000000000000 --- a/boards/arm/nucleo_f334r8/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _nucleo_f334r8_board: - -ST Nucleo F334R8 -################ - -Overview -******** -STM32 Nucleo-64 development board with STM32F334R8 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board does not require any separate probe as it integrates the ST-LINK/V2-1 -debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_f334r8.jpg - :align: center - :alt: Nucleo F334R8 - -More information about the board can be found at the `Nucleo F334R8 website`_. - -Hardware -******** -Nucleo F334R8 provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32F334R8 can be found in the -`STM32F334 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_f334r8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_f334r8_connectors.jpg - :align: center - :alt: Nucleo F334R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- UART_3 TX/RX : PB10/PB11 -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- PWM_1_CH1 : PA8 -- USER_PB : PC13 -- LD2 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f334r8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F334R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to Nucleo F334R8 ----------------------------------------- - -Connect the Nucleo F334R8 to your host computer using the USB port, -then build and flash an application. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f334r8 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for -the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_f334r8 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo F334R8 website: - https://www.st.com/en/evaluation-tools/nucleo-f334r8.html - -.. _STM32F334 reference manual: - https://www.st.com/resource/en/reference_manual/dm00093941.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig b/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig deleted file mode 100644 index a7a22c2096d119..00000000000000 --- a/boards/arm/nucleo_f334r8/nucleo_f334r8_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F3X=y - -# Platform Configuration -CONFIG_SOC_STM32F334X8=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f401re/Kconfig.board b/boards/arm/nucleo_f401re/Kconfig.board deleted file mode 100644 index 21b9b7451a3d39..00000000000000 --- a/boards/arm/nucleo_f401re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F401RE board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F401RE - bool "NUCLEO-64 F401RE Development Board" - depends on SOC_STM32F401XE diff --git a/boards/arm/nucleo_f401re/Kconfig.defconfig b/boards/arm/nucleo_f401re/Kconfig.defconfig deleted file mode 100644 index a634aca6a73548..00000000000000 --- a/boards/arm/nucleo_f401re/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# NUCLEO-64 F401RE board configuration - -# Copyright (c) 2016 Linaro Limited. -# Copyright (c) 2019 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F401RE - -config BOARD - default "nucleo_f401re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F401RE diff --git a/boards/arm/nucleo_f401re/doc/index.rst b/boards/arm/nucleo_f401re/doc/index.rst deleted file mode 100644 index aa01b1ad3ad4cb..00000000000000 --- a/boards/arm/nucleo_f401re/doc/index.rst +++ /dev/null @@ -1,206 +0,0 @@ -.. _nucleo_f401re_board: - -ST Nucleo F401RE -################ - -Overview -******** - -The Nucleo F401RE board features an ARM Cortex-M4 based STM32F401RE MCU -with a wide range of connectivity support and configurations Here are -some highlights of the Nucleo F401RE board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f401re.jpg - :align: center - :alt: Nucleo F401RE - -More information about the board can be found at the `Nucleo F401RE website`_. - -Hardware -******** - -Nucleo F401RE provides the following hardware components: - -- STM32F401RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 96 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (7) -- Watchdog Timers (2) -- USART/UART (3) -- I2C (3) -- SPI (4) -- SDIO -- USB 2.0 OTG FS -- DMA Controller - -More information about STM32F401RE can be found here: - -- `STM32F401RE on www.st.com`_ -- `STM32F401 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_401re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | System Window Watchdog | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f401re/nucleo_f401re_defconfig`` - - -Pin Mapping -=========== - -Nucleo F401RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f401re_arduino.jpg - :align: center - :alt: Nucleo F401RE Arduino connectors -.. image:: img/nucleo_f401re_morpho.jpg - :align: center - :alt: Nucleo F401RE Morpho connectors - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD2 : PA5 - -System Clock -============ - -Nucleo F401RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, -driven by 8MHz high speed external clock. - -Serial Port -=========== - -Nucleo F401RE board has 3 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -I2C -=== - -Nucleo F401RE board has up to 3 I2Cs. The default I2C mapping for Zephyr is: - -- I2C1_SCL : PB8 -- I2C1_SDA : PB9 - -Programming and Debugging -************************* - -Applications for the ``nucleo_f401re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to Nucleo F401RE ----------------------------------------- - -Connect the Nucleo F401RE to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f401re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f401re - :maybe-skip-config: - :goals: debug - -.. _Nucleo F401RE website: - https://www.st.com/en/evaluation-tools/nucleo-f401re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F401RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f401re.html - -.. _STM32F401 reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/nucleo_f410rb/Kconfig.board b/boards/arm/nucleo_f410rb/Kconfig.board deleted file mode 100644 index 8dcfa890169cfd..00000000000000 --- a/boards/arm/nucleo_f410rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F410RB Nucleo board configuration - -# Copyright (c) 2020 Hans Unzner -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F410RB - bool "Nucleo F410RB Development Board" - depends on SOC_STM32F410RX diff --git a/boards/arm/nucleo_f410rb/Kconfig.defconfig b/boards/arm/nucleo_f410rb/Kconfig.defconfig deleted file mode 100644 index df64f4ca9d33f7..00000000000000 --- a/boards/arm/nucleo_f410rb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F410RB Nucleo board configuration - -# Copyright (c) 2020 Hans Unzner -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F410RB - -config BOARD - default "nucleo_f410rb" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F410RB diff --git a/boards/arm/nucleo_f410rb/doc/index.rst b/boards/arm/nucleo_f410rb/doc/index.rst deleted file mode 100644 index 23c979e49aaa15..00000000000000 --- a/boards/arm/nucleo_f410rb/doc/index.rst +++ /dev/null @@ -1,212 +0,0 @@ -.. _nucleo_f410rb_board: - -ST Nucleo F410RB -################ - -Overview -******** - -The Nucleo F410RB board features an ARM Cortex-M4 based STM32F410RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F410RB board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f410rb.jpg - :align: center - :alt: Nucleo F410RB - -More information about the board can be found at the `Nucleo F410RB website`_. - -Hardware -******** - -Nucleo F410RB provides the following hardware components: - -- STM32F410RBT6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Adaptive real-time accelerator (ART Accelerator) -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 128 KB Flash -- 32 KB SRAM -- General purpose timer (4) -- Low-power timer (1) -- Advanced-control timer (1) -- Random number generator (TRNG for HW entropy) -- SPI/I2S (3) -- I2C (3) -- USART (3) -- GPIO (50) with external interrupt capability -- 12-bit ADC with 16 channels -- 12-bit DAC with 1 channel -- RTC - - -More information about STM32F410RB can be found here: - -- `STM32F410RB on www.st.com`_ -- `STM32F410 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f410rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | window & independent | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig`` - - -Connections and IOs -=================== - -Nucleo F410RB Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f410rb_arduino_top_left.jpg - :align: center - :alt: Nucleo F410RB Arduino connectors (top left) -.. image:: img/nucleo_f410rb_arduino_top_right.jpg - :align: center - :alt: Nucleo F410RB Arduino connectors (top right) -.. image:: img/nucleo_f410rb_morpho_top_left.jpg - :align: center - :alt: Nucleo F410RB Morpho connectors (top left) -.. image:: img/nucleo_f410rb_morpho_top_right.jpg - :align: center - :alt: Nucleo F410RB Morpho connectors (top right) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PC13 -- LD2 : PA5 -- I2C1_SDA : PB9 -- I2C1_SCL : PB8 -- I2C2_SDA : PB3 -- I2C2_SCL : PB10 - -System Clock ------------- - -Nucleo F410RB System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, -driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F410RB board has 3 USARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f410rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F410RB board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F410RB ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f410rb - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f410rb - :maybe-skip-config: - :goals: debug - -.. _Nucleo F410RB website: - https://www.st.com/en/evaluation-tools/nucleo-F410RB.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F410RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32f410rb.html - -.. _STM32F410 reference manual: - https://www.st.com/resource/en/reference_manual/dm00180366.pdf diff --git a/boards/arm/nucleo_f411re/Kconfig.board b/boards/arm/nucleo_f411re/Kconfig.board deleted file mode 100644 index 8d14124ab07a97..00000000000000 --- a/boards/arm/nucleo_f411re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-64 F411RE board configuration - -# Copyright (c) 2016 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F411RE - bool "NUCLEO-64 F411RE Development Board" - depends on SOC_STM32F411XE diff --git a/boards/arm/nucleo_f411re/Kconfig.defconfig b/boards/arm/nucleo_f411re/Kconfig.defconfig deleted file mode 100644 index ca331991f94217..00000000000000 --- a/boards/arm/nucleo_f411re/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# NUCLEO-64 F411RE board configuration - -# Copyright (c) 2016 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F411RE - -config BOARD - default "nucleo_f411re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F411RE diff --git a/boards/arm/nucleo_f411re/doc/index.rst b/boards/arm/nucleo_f411re/doc/index.rst deleted file mode 100644 index 908dfbf9a2a20b..00000000000000 --- a/boards/arm/nucleo_f411re/doc/index.rst +++ /dev/null @@ -1,200 +0,0 @@ -.. _nucleo_f411re_board: - -ST Nucleo F411RE -################ - -Overview -******** - -The Nucleo F411RE board features an ARM Cortex-M4 based STM32F411RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F411RE board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f411re.jpg - :align: center - :alt: Nucleo F411RE - -More information about the board can be found at the `Nucleo F411RE website`_. - -Hardware -******** - -Nucleo F411RE provides the following hardware components: - -- STM32F411RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels, with FIFO and burst support -- RTC -- 8 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- CRC calculation unit - -More information about STM32F411RE can be found here: - -- `STM32F411RE on www.st.com`_ -- `STM32F411 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f411re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| I2S | on-chip | i2s | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f411re/nucleo_f411re_defconfig`` - - -Connections and IOs -=================== - -Nucleo F411RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f411re_arduino.jpg - :align: center - :alt: Nucleo F411RE Arduino connectors -.. image:: img/nucleo_f411re_morpho.jpg - :align: center - :alt: Nucleo F411RE Morpho connectors - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PB10/PB3 -- I2C1 SCL/SDA : PA8/B4 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) -- I2S1 SCK/SD : PA5/PA7 (Arduino I2S) -- USER_PB : PC13 -- LD2 : PA5 - -.. note:: Please note that SPI1 and I2S1 are connected to the same mcu pins, as the h/w controller is the same one. - -System Clock ------------- - -Nucleo F411RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F411RE board has 3 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f411re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F411RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to Nucleo F411RE ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f411re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f411re - :maybe-skip-config: - :goals: debug - -.. _Nucleo F411RE website: - https://www.st.com/en/evaluation-tools/nucleo-f411re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F411RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f411re.html - -.. _STM32F411 reference manual: - https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/nucleo_f412zg/Kconfig.board b/boards/arm/nucleo_f412zg/Kconfig.board deleted file mode 100644 index 4df2769a2a13f8..00000000000000 --- a/boards/arm/nucleo_f412zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F412ZG board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F412ZG - bool "NUCLEO-144 F412ZG Development Board" - depends on SOC_STM32F412ZX diff --git a/boards/arm/nucleo_f412zg/Kconfig.defconfig b/boards/arm/nucleo_f412zg/Kconfig.defconfig deleted file mode 100644 index 428368d5927965..00000000000000 --- a/boards/arm/nucleo_f412zg/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# NUCLEO-144 F412ZG board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F412ZG - -config BOARD - default "nucleo_f412zg" - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_ECM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F412ZG diff --git a/boards/arm/nucleo_f412zg/doc/index.rst b/boards/arm/nucleo_f412zg/doc/index.rst deleted file mode 100644 index 678971ecf1e917..00000000000000 --- a/boards/arm/nucleo_f412zg/doc/index.rst +++ /dev/null @@ -1,172 +0,0 @@ -.. _nucleo_f412zg_board: - -ST Nucleo F412ZG -################ - -Overview -******** - -The Nucleo F412ZG board features an ARM Cortex-M4 based STM32F412ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F412ZG board: - -- STM32 microcontroller in LQFP144 package -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f412zg.jpg - :align: center - :alt: Nucleo F412ZG - -More information about the board can be found at the `Nucleo F412ZG website`_. - -Hardware -******** - -Nucleo F412ZG provides the following hardware components: - -- STM32F412ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 256 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 16 channels, with FIFO and burst support -- RTC -- 14 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (4) -- I2C (4) -- SPI (5) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- CRC calculation unit - -More information about STM32F412ZG can be found here: - -- `STM32F412ZG on www.st.com`_ -- `STM32F412 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_412zg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo F412ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f412zg_zio_left.jpg - :align: center - :alt: Nucleo F412ZG ZIO connectors (left) -.. image:: img/nucleo_f412zg_zio_right.jpg - :align: center - :alt: Nucleo F412ZG ZIO connectors (right) -.. image:: img/nucleo_f412zg_morpho_left.jpg - :align: center - :alt: Nucleo F412ZG Morpho connectors (left) -.. image:: img/nucleo_f412zg_morpho_right.jpg - :align: center - :alt: Nucleo F412ZG Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- USB DM : PA11 -- USB DP : PA12 - -System Clock ------------- - -Nucleo F412ZG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F412ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - -Network interface ------------------ - -Ethernet over USB is configured as the default network interface - -Programming and Debugging -************************* - -Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F412ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f412zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F412ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f412zg.html - -.. _STM32F412 reference manual: - https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/nucleo_f413zh/Kconfig.board b/boards/arm/nucleo_f413zh/Kconfig.board deleted file mode 100644 index ae28485aeb61ef..00000000000000 --- a/boards/arm/nucleo_f413zh/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F413ZH board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F413ZH - bool "NUCLEO-144 F413ZH Development Board" - depends on SOC_STM32F413XX diff --git a/boards/arm/nucleo_f413zh/Kconfig.defconfig b/boards/arm/nucleo_f413zh/Kconfig.defconfig deleted file mode 100644 index e340a26c99d5b8..00000000000000 --- a/boards/arm/nucleo_f413zh/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# NUCLEO-144 F413ZH board configuration - -# Copyright (c) 2017 Florian Vaussard, HEIG-VD -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F413ZH - -config BOARD - default "nucleo_f413zh" - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_ECM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F413ZH diff --git a/boards/arm/nucleo_f413zh/doc/index.rst b/boards/arm/nucleo_f413zh/doc/index.rst deleted file mode 100644 index 7979171472e1c3..00000000000000 --- a/boards/arm/nucleo_f413zh/doc/index.rst +++ /dev/null @@ -1,174 +0,0 @@ -.. _nucleo_f413zh_board: - -ST Nucleo F413ZH -################ - -Overview -******** - -The Nucleo F413ZH board features an ARM Cortex-M4 based STM32F413ZH MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F413ZH board: - -- STM32 microcontroller in LQFP144 package -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f413zh.jpg - :align: center - :alt: Nucleo F413ZH - -More information about the board can be found at the `Nucleo F413ZH website`_. - -Hardware -******** - -Nucleo F413ZH provides the following hardware components: - -- STM32F413ZHT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1.5 MB Flash -- 320 KB SRAM -- GPIO with external interrupt capability -- 2 12-bit ADC with 16 channels, with FIFO and burst support -- RTC -- 14 General purpose timers -- 2 watchdog timers (independent and window) -- SysTick timer -- USART/UART (10) -- I2C (4) -- SPI (5) -- SDIO -- USB 2.0 OTG FS -- DMA Controller -- CRC calculation unit - -More information about STM32F413ZH can be found here: - -- `STM32F413ZH on www.st.com`_ -- `STM32F413/423 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_413zh board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig`` - - -Connections and IOs -=================== - -Nucleo F413ZH Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f413zh_zio_left.jpg - :align: center - :alt: Nucleo F413ZH ZIO connectors (left) -.. image:: img/nucleo_f413zh_zio_right.jpg - :align: center - :alt: Nucleo F413ZH ZIO connectors (right) -.. image:: img/nucleo_f413zh_morpho_left.jpg - :align: center - :alt: Nucleo F413ZH Morpho connectors (left) -.. image:: img/nucleo_f413zh_morpho_right.jpg - :align: center - :alt: Nucleo F413ZH Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PA0 -- USB_DM : PA11 -- USB_DP : PA12 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 - -System Clock ------------- - -Nucleo F413ZH System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, -driven by 8MHz high speed external clock. - -Serial Port ------------ - -Nucleo F413ZH board has 10 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - -USB -=== -Nucleo F413ZH board has a USB OTG dual-role device (DRD) controller that -supports both device and host functions through its micro USB connector -(USB USER). Only USB device function is supported in Zephyr at the moment. - - -Programming and Debugging -************************* - -Nucleo F413ZH board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - - -.. _Nucleo F413ZH website: - https://www.st.com/en/evaluation-tools/nucleo-f413zh.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F413ZH on www.st.com: - https://www.st.com/en/microcontrollers/stm32f413zh.html - -.. _STM32F413/423 reference manual: - https://www.st.com/resource/en/reference_manual/dm00305666.pdf diff --git a/boards/arm/nucleo_f429zi/Kconfig.board b/boards/arm/nucleo_f429zi/Kconfig.board deleted file mode 100644 index b9e033f86223ba..00000000000000 --- a/boards/arm/nucleo_f429zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NUCLEO-144 F429ZI board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F429ZI - bool "NUCLEO-144 F429ZI Development Board" - depends on SOC_STM32F429XX diff --git a/boards/arm/nucleo_f429zi/Kconfig.defconfig b/boards/arm/nucleo_f429zi/Kconfig.defconfig deleted file mode 100644 index 99fdd74ade1162..00000000000000 --- a/boards/arm/nucleo_f429zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# NUCLEO-144 F429ZI board configuration - -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F429ZI - -config BOARD - default "nucleo_f429zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F429ZI diff --git a/boards/arm/nucleo_f429zi/doc/index.rst b/boards/arm/nucleo_f429zi/doc/index.rst deleted file mode 100644 index e65e9194ad4d7b..00000000000000 --- a/boards/arm/nucleo_f429zi/doc/index.rst +++ /dev/null @@ -1,217 +0,0 @@ -.. _nucleo_f429zi_board: - -ST Nucleo F429ZI -################ - -Overview -******** - -The Nucleo F429ZI board features an ARM Cortex-M4 based STM32F429ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F429ZI board: - -- STM32 microcontroller in LQFP144 package -- LSE crystal: 32.768 kHz crystal oscillator -- USB OTG -- Ethernet compliant with IEEE-802.3-2002 -- Two types of extension resources: - - - ST Zio connector including: support for Arduino* Uno V3 connectivity - (A0 to A5, D0 to D15) and additional signals exposing a wide range of - peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5 V from ST-LINK/V2-1 USB VBUS - - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho - connectors, 5 V on ST morpho connector - -- Three user LEDs -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f429zi.jpg - :align: center - :alt: Nucleo F429ZI - -More information about the board can be found at the `Nucleo F429ZI website`_. - -Hardware -******** - -The Nucleo F429ZI provides the following hardware components: - -- STM32F429ZIT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 256+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (4/4) -- I2C (3) -- SPI (6) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F429ZI can be found here: - -- `STM32F429ZI on www.st.com`_ -- `STM32F429 reference manual`_ -- `STM32F429 datasheet`_ - -Supported Features -================== - -The Zephyr nucleo_f429zi board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig`` - - -Connections and IOs -=================== - -The Nucleo F429ZI Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f429zi_cn8.jpg - :align: center - :alt: Nucleo F429ZI ZIO connectors (left) -.. image:: img/nucleo_f429zi_cn7.jpg - :align: center - :alt: Nucleo F429ZI ZIO connectors (right) -.. image:: img/nucleo_f429zi_cn11.jpg - :align: center - :alt: Nucleo F429ZI Morpho connectors (left) -.. image:: img/nucleo_f429zi_cn12.jpg - :align: center - :alt: Nucleo F429ZI Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F429ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) -- PWM_2_CH1 : PE13 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- USB DM : PA11 -- USB DP : PA12 -- ADC1 : PA0 - -System Clock ------------- - -The Nucleo F429ZI System Clock could be driven by an internal or external oscillator, -as well as by the main PLL clock. By default System clock is driven by PLL clock at 180MHz, -driven by an 8MHz high speed external clock. - -Serial Port ------------ - -The Nucleo F429ZI board has 8 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -The Nucleo F429ZI board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flash partitions for MCUBoot bootloader -*************************************** - -The on-board STM32F429ZI MCU has 2MBs of internal flash memory. To use `MCUboot`_, -define a :ref:`Zephyr partition table ` for the flash memory in -its devicetree file ``nucleo_f429zi.dts``. As a reference, a partition table for -MCUBoot is already defined in the devicetree file, with these settings: - -- `MCUBoot`_ bootloader partition takes 64K bytes. -- Zephyr settings partition takes 64K bytes. -- Application image takes 256K bytes in Slot 0 partition. -- Updating image takes another 256K bytes in Slot 1 partition. -- A scratch partition with 128K is required for image swap. - -A specific application can adjust each partition size based on its needs. - - -.. _Nucleo F429ZI website: - https://www.st.com/en/evaluation-tools/nucleo-f429zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F429ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32f429zi.html - -.. _STM32F429 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031020.pdf - -.. _STM32F429 datasheet: - https://www.st.com/resource/en/datasheet/DM00071990.pdf - -.. _MCUBoot: - https://github.com/JuulLabs-OSS/mcuboot/blob/master/README.md diff --git a/boards/arm/nucleo_f446re/Kconfig.board b/boards/arm/nucleo_f446re/Kconfig.board deleted file mode 100644 index 71f63f7b8e1e31..00000000000000 --- a/boards/arm/nucleo_f446re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F446RE Nucleo board configuration - -# Copyright (c) 2018 Philémon Jaermann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F446RE - bool "Nucleo F446RE Development Board" - depends on SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446re/Kconfig.defconfig b/boards/arm/nucleo_f446re/Kconfig.defconfig deleted file mode 100644 index 409b8bd5d4768d..00000000000000 --- a/boards/arm/nucleo_f446re/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F446RE Nucleo board configuration - -# Copyright (c) 2018 Philémon Jaermann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F446RE - -config BOARD - default "nucleo_f446re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F446RE diff --git a/boards/arm/nucleo_f446re/doc/index.rst b/boards/arm/nucleo_f446re/doc/index.rst deleted file mode 100644 index 37d62c043107cf..00000000000000 --- a/boards/arm/nucleo_f446re/doc/index.rst +++ /dev/null @@ -1,226 +0,0 @@ -.. _nucleo_f446re_board: - -ST Nucleo F446RE -################ - -Overview -******** - -The Nucleo F446RE board features an ARM Cortex-M4 based STM32F446RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F446RE board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f446re.jpg - :align: center - :alt: Nucleo F446RE - -More information about the board can be found at the `Nucleo F446RE website`_. - -Hardware -******** - -Nucleo F446RE provides the following hardware components: - -- STM32F446RET6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Adaptive real-time accelerator (ART Accelerator) -- 180 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- 10 General purpose timers -- 2 Advanced control timers -- 2 basic timers -- SPI(4) -- I2C(3) -- USART(4) -- UART(2) -- USB OTG Full Speed and High Speed -- CAN(2) -- SAI(2) -- SPDIF_Rx(1) -- HDMI_CEC(1) -- Quad SPI(1) -- Camera Interface -- GPIO(50) with external interrupt capability -- 12-bit ADC(3) with 16 channels -- 12-bit DAC with 2 channels - -More information about STM32F446RE can be found here: - -- `STM32F446RE on www.st.com`_ -- `STM32F446 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f446re board configuration supports the following hardware features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| CAN 1/2 | on-chip | Controller Area Network | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f446re/nucleo_f446re_defconfig`` - - -Connections and IOs -=================== - -Nucleo F446RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f446re_arduino_top_left.jpg - :align: center - :alt: Nucleo F446RE Arduino connectors (top left) -.. image:: img/nucleo_f446re_arduino_top_right.jpg - :align: center - :alt: Nucleo F446RE Arduino connectors (top right) -.. image:: img/nucleo_f446re_morpho_top_left.jpg - :align: center - :alt: Nucleo F446RE Morpho connectors (top left) -.. image:: img/nucleo_f446re_morpho_top_right.jpg - :align: center - :alt: Nucleo F446RE Morpho connectors (top right) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PC13 -- LD2 : PA5 -- I2C1_SDA : PB9 -- I2C1_SCL : PB8 -- I2C2_SDA : PB3 -- I2C2_SCL : PB10 -- I2C3_SDA : PB4 -- I2C3_SCL : PA8 - -System Clock ------------- - -Nucleo F446RE System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, -driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F446RE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB45`` jumper on the back side of the board. - -Controller Area Network ------------------------ - -The TX/RX wires connected with D14/D15 of CN5 connector. Thus the board can be -used with `RS485 CAN Shield`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f446re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F446RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F446RE ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446re - :maybe-skip-config: - :goals: debug - -.. _Nucleo F446RE website: - https://www.st.com/en/evaluation-tools/nucleo-f446re.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F446RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f446re.html - -.. _STM32F446 reference manual: - https://www.st.com/resource/en/reference_manual/dm00135183.pdf - -.. _RS485 CAN Shield: - https://www.waveshare.com/wiki/RS485_CAN_Shield diff --git a/boards/arm/nucleo_f446ze/Kconfig.board b/boards/arm/nucleo_f446ze/Kconfig.board deleted file mode 100644 index f926632c73c378..00000000000000 --- a/boards/arm/nucleo_f446ze/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F446ZE Nucleo board configuration - -# Copyright (c) 2021 Tom Owen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F446ZE - bool "Nucleo F446ZE Development Board" - depends on SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446ze/Kconfig.defconfig b/boards/arm/nucleo_f446ze/Kconfig.defconfig deleted file mode 100644 index a256cd1c42aec8..00000000000000 --- a/boards/arm/nucleo_f446ze/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F446ZE Nucleo board configuration - -# Copyright (c) 2021 Tom Owen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F446ZE - -config BOARD - default "nucleo_f446ze" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F446ZE diff --git a/boards/arm/nucleo_f446ze/doc/index.rst b/boards/arm/nucleo_f446ze/doc/index.rst deleted file mode 100644 index 697324e84fab9c..00000000000000 --- a/boards/arm/nucleo_f446ze/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _nucleo_f446ze_board: - -ST Nucleo F446ZE -################ - - -Overview -******** - -The Nucleo F446ZE board features an ARM Cortex-M4 based STM32F446ZE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo F446ZE board: - -- STM32F446 microcontroller in QFP144 package -- Two types of extension resources: - - - ST zio support for Arduino™ Uno V3 connectivity (A0 to A5, D0 to D15) and additional signals exposing a wide range of peripherals - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- USB re-enumeration capability. Three different interfaces supported on USB: - - Virtual Com port - - Mass storage (USB Disk drive) for drag'n'drop programming - - Debug port -- Flexible board power supply: - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - - USB OTG - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_f446ze.jpg - :align: center - :alt: Nucleo F446ZE - -More information about the board can be found at the `Nucleo F446ZE website`_. - -Hardware -******** - -Nucleo F446ZE provides the following hardware components: - -- STM32F446ZET6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU -- Adaptive real-time accelerator (ART Accelerator) -- 180 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- 10 General purpose timers -- 2 Advanced control timers -- 2 basic timers -- SPI(4) -- I2C(4) -- USART(4) -- UART(2) -- USB OTG Full Speed and High Speed -- CAN(2) -- SAI(2) -- SPDIF_Rx(1) -- HDMI_CEC(1) -- Quad SPI(1) -- Camera Interface -- GPIO(50) with external interrupt capability -- 12-bit ADC(3) with 16 channels -- 12-bit DAC with 2 channels - -More information about STM32F446ZE can be found here: - -- `STM32F446ZE on www.st.com`_ -- `STM32F446 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_f446ze board configuration supports the following hardware features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| CAN 1/2 | on-chip | Controller Area Network | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | Analog Input | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | Analog Output | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig`` - - -Connections and IOs -=================== - -Nucleo F446ZE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_f446ze_zio_left_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Zio/Arduino connectors (left) -.. image:: img/nucleo_f446ze_zio_right_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Zio/Arduino connectors (right) -.. image:: img/nucleo_f446ze_morpho_left_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Morpho connectors (left) -.. image:: img/nucleo_f446ze_morpho_right_2019_8_29.jpg - :align: center - :alt: Nucleo F446ZE Morpho connectors (right) - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- UART_3_TX : PD8 -- UART_3_RX : PD9 -- USER_PB : PC13 -- LD0 : PB0 -- LD1 : PB7 -- LD2 : PB14 -- I2C1_SDA : PB9 -- I2C1_SCL : PB8 -- I2C2_SDA : PF0 -- I2C2_SCL : PF1 -- SPI1_CS : PD14 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- USB_DP : PA11 -- USB_DM : PA12 -- ADC1_IN0 : PA0 -- DAC_OUT1 : PA4 - - -System Clock ------------- - -Nucleo F446ZE System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, -driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F446ZE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to USART3. -Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -Controller Area Network ------------------------ - -The TX/RX wires are connected with pins 25/27 of CN9 connector. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f446ze`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F446ZE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F446ZE ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446ze - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f446ze - :maybe-skip-config: - :goals: debug - -.. _Nucleo F446ZE website: - https://www.st.com/en/evaluation-tools/nucleo-f446ze.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um1974-stm32-nucleo144-boards-mb1137-stmicroelectronics.pdf - -.. _STM32F446ZE on www.st.com: - https://www.st.com/en/microcontrollers/stm32f446ze.html - -.. _STM32F446 reference manual: - https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/nucleo_f722ze/Kconfig.board b/boards/arm/nucleo_f722ze/Kconfig.board deleted file mode 100644 index f15e218e16167e..00000000000000 --- a/boards/arm/nucleo_f722ze/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F722ZE Nucleo board configuration - -# Copyright (c) 2023 Evan Perry Grove -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F722ZE - bool "Nucleo F722ZE Development Board" - depends on SOC_STM32F722XX diff --git a/boards/arm/nucleo_f722ze/Kconfig.defconfig b/boards/arm/nucleo_f722ze/Kconfig.defconfig deleted file mode 100644 index 1dfff0c9d44110..00000000000000 --- a/boards/arm/nucleo_f722ze/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F722ZE Nucleo board configuration -# -# Copyright (c) 2023 Evan Perry Grove -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F722ZE - -config BOARD - default "nucleo_f722ze" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_F722ZE diff --git a/boards/arm/nucleo_f746zg/Kconfig.board b/boards/arm/nucleo_f746zg/Kconfig.board deleted file mode 100644 index 1b533d6b8ddad6..00000000000000 --- a/boards/arm/nucleo_f746zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F746ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F746ZG - bool "Nucleo F746ZG Development Board" - depends on SOC_STM32F746XX diff --git a/boards/arm/nucleo_f746zg/Kconfig.defconfig b/boards/arm/nucleo_f746zg/Kconfig.defconfig deleted file mode 100644 index 8e021fdf61af2e..00000000000000 --- a/boards/arm/nucleo_f746zg/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32F746ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F746ZG - -config BOARD - default "nucleo_f746zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F746ZG diff --git a/boards/arm/nucleo_f746zg/doc/index.rst b/boards/arm/nucleo_f746zg/doc/index.rst deleted file mode 100644 index 8bc083bcc3f6e5..00000000000000 --- a/boards/arm/nucleo_f746zg/doc/index.rst +++ /dev/null @@ -1,235 +0,0 @@ -.. _nucleo_f746zg_board: - -ST Nucleo F746ZG -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS significantly reduces power -consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_f746zg.jpg - :align: center - :alt: Nucleo F746ZG - -More information about the board can be found at the `Nucleo F746ZG website`_. - -Hardware -******** - -Nucleo F746ZG provides the following hardware components: - -- STM32F746ZG in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- ART Accelerator -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 320 KB SRAM -- 16-bit timers(10) -- 32-bit timers(2) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO(up to 168) with external interrupt capability -- 12-bit ADC(3) with 24 channels / 2.4 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_f746zg board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-------------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-------------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F746ZG board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino UART) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB DM : PA11 -- USB DP : PA12 -- I2C : PB8, PB9 -- PWM : PE13 -- SPI : PD14, PA5, PA6, PA7 -- ADC1_IN0 : PA0 -- DAC1_OUT1 : PA4 - -Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH -device on pin PA7. - -System Clock ------------- - -Nucleo F746ZG System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F746ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -Programming and Debugging -************************* - -Applications for the ``nucleo_f746zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo F746ZG ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f746zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_f746zg - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f746zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo F746ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f746zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32F746ZG on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746zg.html - -.. _STM32F746 reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f756zg/Kconfig.board b/boards/arm/nucleo_f756zg/Kconfig.board deleted file mode 100644 index 46f61135b86709..00000000000000 --- a/boards/arm/nucleo_f756zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F756ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F756ZG - bool "Nucleo F756ZG Development Board" - depends on SOC_STM32F756XX diff --git a/boards/arm/nucleo_f756zg/Kconfig.defconfig b/boards/arm/nucleo_f756zg/Kconfig.defconfig deleted file mode 100644 index d6b1759beb51de..00000000000000 --- a/boards/arm/nucleo_f756zg/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32F756ZG Nucleo board configuration - -# Copyright (c) 2018 AJ Palmer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F756ZG - -config BOARD - default "nucleo_f756zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F756ZG diff --git a/boards/arm/nucleo_f756zg/doc/index.rst b/boards/arm/nucleo_f756zg/doc/index.rst deleted file mode 100644 index aa13ddb7f20090..00000000000000 --- a/boards/arm/nucleo_f756zg/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _nucleo_f756zg_board: - -ST Nucleo F756ZG -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS significantly reduces power -consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration - capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the -- STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_f756zg.jpg - :align: center - :alt: Nucleo F756ZG - -More information about the board can be found at the `Nucleo F756ZG website`_. - -Hardware -******** - -Nucleo F756ZG provides the following hardware components: - -- STM32F756ZG in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- ART Accelerator -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 320 KB SRAM -- 16-bit timers(10) -- 32-bit timers(2) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO(up to 168) with external interrupt capability -- 12-bit ADC(3) with 24 channels / 2.4 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_f756zg board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F756ZG board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino UART) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB DM : PA11 -- USB DP : PA12 -- I2C : PB8, PB9 -- PWM : PE13 -- SPI : PD14, PA5, PA6, PA7 - -Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH -device on pin PA7. - -System Clock ------------- - -Nucleo F756ZG System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F756ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f756zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo F756ZG ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f756zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_f756zg - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f756zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo F756ZG website: - https://www.st.com/en/evaluation-tools/nucleo-f756zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32F756ZG on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f756zg.html - -.. _STM32F756 reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f767zi/Kconfig.board b/boards/arm/nucleo_f767zi/Kconfig.board deleted file mode 100644 index d76625a7e5993e..00000000000000 --- a/boards/arm/nucleo_f767zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F767ZI Nucleo board configuration - -# Copyright (c) 2019 Roland Ma -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_F767ZI - bool "Nucleo F767ZI Development Board" - depends on SOC_STM32F767XX diff --git a/boards/arm/nucleo_f767zi/Kconfig.defconfig b/boards/arm/nucleo_f767zi/Kconfig.defconfig deleted file mode 100644 index b53353b2b06602..00000000000000 --- a/boards/arm/nucleo_f767zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32F767ZI Nucleo board configuration - -# Copyright (c) 2019 Roland Ma -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_F767ZI - -config BOARD - default "nucleo_f767zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_F767ZI diff --git a/boards/arm/nucleo_f767zi/doc/index.rst b/boards/arm/nucleo_f767zi/doc/index.rst deleted file mode 100644 index 7eca2af1edaa19..00000000000000 --- a/boards/arm/nucleo_f767zi/doc/index.rst +++ /dev/null @@ -1,236 +0,0 @@ -.. _nucleo_f767zi_board: - -ST Nucleo F767ZI -################ - -Overview -******** - -The STM32 Nucleo-144 F767ZI boards offer combinations of performance and -power that provide an affordable and flexible way for users to build -prototypes and try out new concepts. For compatible boards, the SMPS -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_f767zi.jpg - :align: center - :alt: Nucleo F767ZI - -More information about the board can be found at the `Nucleo F767ZI website`_. - -Hardware -******** - -Nucleo F767ZI provides the following hardware components: - -- STM32F767ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- ART Accelerator -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 2 MB Flash -- 512 KB SRAM -- 16-bit timers(10) -- 32-bit timers(2) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO(up to 168) with external interrupt capability -- 12-bit ADC(3) with 24 channels / 2.4 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_f767zi board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet (*) | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ - - -(*) nucleo_f767zi with soc cut-A (Device marking A) has some ethernet - instability (:github:`26519`). - Use of cut-Z is advised. - see restrictions errata: - https://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/23/a6/11/0b/30/24/46/a5/DM00257543/files/DM00257543.pdf/jcr:content/translations/en.DM00257543.pdf - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo F767ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino UART) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- USB DM : PA11 -- USB DP : PA12 -- I2C : PB8, PB9 -- PWM : PE13 -- SPI : PD14, PA5, PA6, PA7 - -.. note:: - The Arduino Uno v3 specified SPI device conflicts with the on-board ETH - device on pin PA7. - -System Clock ------------- - -Nucleo F767ZI System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo F767ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_f767zi`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo F767ZI board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo F767ZI ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f767zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_f767zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_f767zi - :maybe-skip-config: - :goals: debug - -.. _Nucleo f767zi website: - https://www.st.com/en/evaluation-tools/nucleo-f767zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32f767zi on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x&/stm32f767zi.html - -.. _STM32F767 reference manual: - https://www.st.com/resource/en/reference_manual/DM00224583.pdf diff --git a/boards/arm/nucleo_g031k8/Kconfig.board b/boards/arm/nucleo_g031k8/Kconfig.board deleted file mode 100644 index 02133d332572bc..00000000000000 --- a/boards/arm/nucleo_g031k8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32G031K8 MCU configuration - -# Copyright (c) 2022 Joylab AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G031K8 - bool "NUCLEO-32 G031K8 Development Board" - depends on SOC_STM32G031XX diff --git a/boards/arm/nucleo_g031k8/Kconfig.defconfig b/boards/arm/nucleo_g031k8/Kconfig.defconfig deleted file mode 100644 index b448461f39ec2f..00000000000000 --- a/boards/arm/nucleo_g031k8/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-32 development board with STM32G031K8 MCU - -# Copyright (c) 2022 Joylab AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G031K8 - -config BOARD - default "nucleo_g031k8" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_G031K8 diff --git a/boards/arm/nucleo_g031k8/doc/index.rst b/boards/arm/nucleo_g031k8/doc/index.rst deleted file mode 100644 index 93a10b553ab865..00000000000000 --- a/boards/arm/nucleo_g031k8/doc/index.rst +++ /dev/null @@ -1,168 +0,0 @@ -.. _nucleo_g031k8_board: - -ST Nucleo G031K8 -################ - -Overview -******** -The STM32 Nucleo-32 board provides an affordable and flexible way for users to try -out new concepts and build prototypes by choosing from the various combinations of -performance and power consumption features, provided by the STM32 -microcontroller. - -The Arduino™ Nano V3 connectivity support allows the easy expansion of the -functionality of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo-32 board does not require any separate probe as it integrates the -ST-LINK debugger/programmer. - -The STM32 Nucleo-32 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - - -.. image:: img/nucleo_g031k8.jpg - :align: center - :alt: Nucleo G031K8 - -More information about the board can be found at the `Nucleo G031K8 website`_. - -Hardware -******** -Nucleo G031K8 provides the following hardware components: - -- STM32 microcontroller in 32-pin package featuring 64 Kbytes of Flash memory - and 8 Kbytes of SRAM. -- Extension resource: - - - Arduino* Nano V3 connectivity - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Current consumption measurement (IDD) - -- Four LEDs: - - - USB communication (LD1), power LED (LD2), user LED (LD3), - USB power fault LED (LD4) - -- One push-button: RESET - -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32G031K8 can be found in the -`STM32G0x1 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_g031k8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C2 SCL/SDA : PA9/PA10 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PB3/PB4/PB5 (Arduino SPI) -- LD3 : PC6 - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g031k8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G031K8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo G031K8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g031k8 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g031k8 - :maybe-skip-config: - :goals: debug - -Restriction -*********** - -On some boards, the board reset line is not used by the controller. -Therefore the reset button, reset-pin and the ST-Link reset have no effect. -To enable those functionalities, the option byte NRST_mode in the User -Configuration needs to be changed from 2 to 1 or 3 - depending on the -requirements. - -References -********** - -.. target-notes:: - -.. _Nucleo G031K8 website: - https://www.st.com/en/evaluation-tools/nucleo-g031k8.html - -.. _STM32G0x1 reference manual: - https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/um2591-stm32g0-nucleo32-board-mb1455-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_g070rb/Kconfig.board b/boards/arm/nucleo_g070rb/Kconfig.board deleted file mode 100644 index eb32da85a2e3da..00000000000000 --- a/boards/arm/nucleo_g070rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G070RB MCU configuration - -# Copyright (c) 2023 Marin Jurjević -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G070RB - bool "NUCLEO-64 G070RB Development Board" - depends on SOC_STM32G070XX diff --git a/boards/arm/nucleo_g070rb/Kconfig.defconfig b/boards/arm/nucleo_g070rb/Kconfig.defconfig deleted file mode 100644 index 7fd80219e44f0b..00000000000000 --- a/boards/arm/nucleo_g070rb/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G070RB MCU - -# Copyright (c) 2023 Marin Jurjević -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G070RB - -config BOARD - default "nucleo_g070rb" - -endif # BOARD_NUCLEO_G070RB diff --git a/boards/arm/nucleo_g070rb/doc/index.rst b/boards/arm/nucleo_g070rb/doc/index.rst deleted file mode 100644 index 8908ed5ce43c6e..00000000000000 --- a/boards/arm/nucleo_g070rb/doc/index.rst +++ /dev/null @@ -1,191 +0,0 @@ -.. _nucleo_g070rb_board: - -ST Nucleo G070RB -################ - -Overview -******** -The Nucleo G070RB board features an ARM Cortex-M0+ based STM32G070RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G070RB board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_g070rb.jpg - :align: center - :alt: Nucleo G070RB - -More information about the board can be found at the `Nucleo G070RB website`_. - -Hardware -******** -Nucleo G070RB provides the following hardware components: - -- STM32 microcontroller in LQFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD4), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32G070RB can be found here: - -- `G070RB on www.st.com`_ - -Supported Features -================== - -The Zephyr nucleo_g070rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | arm memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PC4/PC5 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 -- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD4 : PA5 -- PWM : PA6 -- ADC1 IN0 : PA0 -- ADC1 IN1 : PA1 -- DAC1_OUT1 : PA4 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g070rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G070RB board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo G070RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g070rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g070rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo G070RB website: - https://www.st.com/en/evaluation-tools/nucleo-g070rb.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00452640.pdf - -.. _G070RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g070rb.html diff --git a/boards/arm/nucleo_g071rb/Kconfig.board b/boards/arm/nucleo_g071rb/Kconfig.board deleted file mode 100644 index 97a74c8dfc5028..00000000000000 --- a/boards/arm/nucleo_g071rb/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G071RB MCU configuration - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G071RB - bool "NUCLEO-64 G071RB Development Board" - depends on SOC_STM32G071XX diff --git a/boards/arm/nucleo_g071rb/Kconfig.defconfig b/boards/arm/nucleo_g071rb/Kconfig.defconfig deleted file mode 100644 index 9333f392112390..00000000000000 --- a/boards/arm/nucleo_g071rb/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G071RB MCU - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G071RB - -config BOARD - default "nucleo_g071rb" - -endif # BOARD_NUCLEO_G071RB diff --git a/boards/arm/nucleo_g071rb/doc/index.rst b/boards/arm/nucleo_g071rb/doc/index.rst deleted file mode 100644 index 424f1ade9f7736..00000000000000 --- a/boards/arm/nucleo_g071rb/doc/index.rst +++ /dev/null @@ -1,198 +0,0 @@ -.. _nucleo_g071rb_board: - -ST Nucleo G071RB -################ - -Overview -******** -The Nucleo G071RB board features an ARM Cortex-M0+ based STM32G071RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G071RB board: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_g071rb.jpg - :align: center - :alt: Nucleo G071RB - -More information about the board can be found at the `Nucleo G071RB website`_. - -Hardware -******** -Nucleo G071RB provides the following hardware components: - -- STM32 microcontroller in LQFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD4), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32G071RB can be found here: - -- `G071RB on www.st.com`_ -- `STM32G071 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_g071rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | arm memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PC4/PC5 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 -- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD4 : PA5 -- PWM : PA6 -- ADC1 IN0 : PA0 -- ADC1 IN1 : PA1 -- DAC1_OUT1 : PA4 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g071rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface. - -Flashing an application to Nucleo G071RB ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g071rb - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g071rb - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo G071RB website: - https://www.st.com/en/evaluation-tools/nucleo-g071rb.html - -.. _STM32G071 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00452640.pdf - -.. _G071RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/nucleo_g0b1re/Kconfig.board b/boards/arm/nucleo_g0b1re/Kconfig.board deleted file mode 100644 index cce6734f45d651..00000000000000 --- a/boards/arm/nucleo_g0b1re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G0B1RE MCU configuration - -# Copyright (c) 2019 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G0B1RE - bool "NUCLEO-64 G0B1RE Development Board" - depends on SOC_STM32G0B1XX diff --git a/boards/arm/nucleo_g0b1re/Kconfig.defconfig b/boards/arm/nucleo_g0b1re/Kconfig.defconfig deleted file mode 100644 index 92a2c028d30ef2..00000000000000 --- a/boards/arm/nucleo_g0b1re/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Nucleo-64 development board with STM32G0B1RE MCU - -# Copyright (c) 2020 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G0B1RE - -config BOARD - default "nucleo_g0b1re" - -endif # BOARD_NUCLEO_G0B1RE diff --git a/boards/arm/nucleo_g0b1re/doc/index.rst b/boards/arm/nucleo_g0b1re/doc/index.rst deleted file mode 100644 index 9627b094fc0066..00000000000000 --- a/boards/arm/nucleo_g0b1re/doc/index.rst +++ /dev/null @@ -1,211 +0,0 @@ -.. _nucleo_g0b1re_board: - -ST Nucleo G0B1RE -################ - -Overview -******** -The Nucleo G0B1RE board features an ARM Cortex-M0+ based STM32G0B1RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G0B1RE board: - -- STM32 microcontroller in QFP64 package -- Board connectors: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - 5V_USB_STLK from ST-Link USB connector - - VIN (7 - 12V) from ARDUINO connector or ST morpho connector - - E5V from ST morpho connector - - 5V_USB_CHG from ST-LINK USB connector - - 3.3V on ARDUINO connector or ST morpho connector - -- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) -- Two push-buttons: USER and RESET -- 32.768 kHz crystal oscillator - -.. image:: img/nucleo_g0b1re.jpg - :align: center - :alt: Nucleo G0B1RE - -More information about the board can be found at the `Nucleo G0B1RE website`_. - -Hardware -******** -Nucleo G0B1RE provides the following hardware components: - -- STM32G0B1RE in LQFP64 package -- ARM 32-bit Cortex-M0+ CPU -- 64 MHz max CPU frequency -- Voltage range from 1.7 V to 3.6 V -- 512 KB Flash -- 144 kB SRAM -- 32-bit timers(1) -- 16-bit timers(11) -- watchdogs(2) -- systick(1) -- Calendar RTC with alarm and periodic wakeup -- I2C(3) -- USART(6) -- LPUART(2) -- 32 Mbit/s SPI(3) multiplexed with I2S(2) -- HDMI_CEC(1) -- USB 2.0 FS device (crystal-less) and host controller(1) -- USB Type-C Power Delivery controller -- CAN FD(2) -- GPIO (up to 94) with external interrupt capability -- Tamper Pins(3) -- 12-bit ADC with 16 channels -- 12-bit DAC with 2 channels(2) -- Analog Comparator(3) -- 12-channel DMA - - -More information about STM32G0B1RE can be found here: - -- `G0B1RE on www.st.com`_ -- `STM32G0B1 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_g0b1re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| MPU | on-chip | arm memory protection unit | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| FDCAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PC4/PC5 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C2 SCL/SDA : PA11/PA12 -- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) -- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- USER_PB : PC13 -- LD4 : PA5 -- PWM : PA6 -- ADC1 IN0 : PA0 -- ADC1 IN1 : PA1 -- DAC1_OUT1 : PA4 -- FDCAN1 RX/TX: PA11/PA12 -- FDCAN2 RX/TX: PB0/PB1 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g0b1re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface. - -This interface is not yet supported by the openocd version included in the Zephyr SDK. -But JLink, STM32CubeProgrammer and Pyocd interfaces are supported. -Pyocd support is currently limited: As the stm32g0b1 target causes issues, -the stm32g071 target is used. For STM32G0 support pyocd needs additional target -information, which can be installed by adding "pack" support with the -following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g0 - - -Flashing an application to Nucleo G0B1RE ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_g0b1re - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g0b1re - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo G0B1RE website: - https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html - -.. _STM32G0B1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00452640.pdf - -.. _G0B1RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32g0b1re.html diff --git a/boards/arm/nucleo_g431rb/Kconfig.board b/boards/arm/nucleo_g431rb/Kconfig.board deleted file mode 100644 index 27de2edbdad417..00000000000000 --- a/boards/arm/nucleo_g431rb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G431RB Nucleo board configuration - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G431RB - bool "Nucleo G431RB Development Board" - depends on SOC_STM32G431XX diff --git a/boards/arm/nucleo_g431rb/Kconfig.defconfig b/boards/arm/nucleo_g431rb/Kconfig.defconfig deleted file mode 100644 index 62c8e061965f24..00000000000000 --- a/boards/arm/nucleo_g431rb/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32G431RB Nucleo board configuration - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G431RB - -config BOARD - default "nucleo_g431rb" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_G431RB diff --git a/boards/arm/nucleo_g431rb/doc/index.rst b/boards/arm/nucleo_g431rb/doc/index.rst deleted file mode 100644 index 0359a29b231e9f..00000000000000 --- a/boards/arm/nucleo_g431rb/doc/index.rst +++ /dev/null @@ -1,263 +0,0 @@ -.. _nucleo_g431rb_board: - -ST Nucleo G431RB -################ - -Overview -******** - -The Nucleo G431RB board features an ARM Cortex-M4 based STM32G431RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G431RB board: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V3E debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) -- Two push-buttons: RESET and USER - -.. image:: img/nucleo_g431rb.jpg - :align: center - :alt: Nucleo G431RB - -More information about the board can be found at the `Nucleo G431RB website`_. - -Hardware -******** - -The STM32G431RB SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz -- Clock Sources: - - - 4 to 48 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- 14x timers: - - - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop - - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop - - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - - 2x watchdog timers (independent, window) - - 2x 16-bit basic timers - - SysTick timer - - 1x low-power timer - -- Up to 86 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 128 KB single bank Flash, proprietary code readout protection - - Up to 22 KB of SRAM including 16 KB with hardware parity check - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 4x 12-bit DAC, low-power sample and hold - - 3x operational amplifiers with built-in PGA - - 4x ultra-fast rail-to-rail analog comparators - -- 16x communication interfaces - - - 1 x FDCAN controller supporting flexible data rate - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (2x with multiplexed half duplex I2S interface) - - 1x SAI (serial audio interface) - - USB 2.0 full-speed interface with LPM and BCD support - - IRTIM (Infrared interface) - - USB Type-C™ /USB power delivery controller (UCPD) - -- 12-channel DMA controller -- True random number generator (RNG) -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32G431RB can be found here: - -- `STM32G431RB on www.st.com`_ -- `STM32G4 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_g431rb board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | rng | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig`` - - -Connections and IOs -=================== - -Nucleo G431RB Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PC4 -- UART_1_RX : PC5 -- LPUART_1_TX : PA2 -- LPUART_1_RX : PA3 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- SPI_1_NSS : PB6 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PB12 -- SPI_2_SCK : PB13 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PA15 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_3_CH1 : PB4 -- USER_PB : PC13 -- LD2 : PA5 -- DAC1_OUT1 : PA4 - -System Clock ------------- - -Nucleo G431RB System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, -driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode -is selected. - -Serial Port ------------ - -Nucleo G431RB board has 3 U(S)ARTs and one LPUART. The Zephyr console output is assigned to LPUART1. -Default settings are 115200 8N1. - -Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in -low power mode. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g431rb`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G431RB board includes an ST-LINK/V3E embedded debug tool interface. - -This interface is not yet supported by the openocd version included in the Zephyr SDK. - -Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g431rb - -Note: -To manually enable the openocd interface, You can still update, compile and install -a 'local' openocd from the official openocd repo http://openocd.zylin.com . -Then run the following openocd command where the '/usr/local/bin/openocd'is your path -for the freshly installed openocd, given by "$ which openocd" : - -.. code-block:: console - - $ west flash --openocd /usr/local/bin/openocd - -Flashing an application to Nucleo G431RB ----------------------------------------- - -Connect the Nucleo G431RB to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g431rb - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g431rb - :maybe-skip-config: - :goals: debug - -.. _Nucleo G431RB website: - https://www.st.com/en/evaluation-tools/nucleo-g431rb.html - -.. _STM32G4 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00556337.pdf - -.. _STM32G431RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g431rb.html - -.. _STM32G4 reference manual: - https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_g474re/Kconfig.board b/boards/arm/nucleo_g474re/Kconfig.board deleted file mode 100644 index 157e93af1ec66c..00000000000000 --- a/boards/arm/nucleo_g474re/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G474RE Nucleo board configuration - -# Copyright (c) 2019 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_G474RE - bool "Nucleo G474RE Development Board" - depends on SOC_STM32G474XX diff --git a/boards/arm/nucleo_g474re/Kconfig.defconfig b/boards/arm/nucleo_g474re/Kconfig.defconfig deleted file mode 100644 index 5af458d22620b9..00000000000000 --- a/boards/arm/nucleo_g474re/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32G474RE Nucleo board configuration - -# Copyright (c) 2019 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_G474RE - -config BOARD - default "nucleo_g474re" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_G431RB diff --git a/boards/arm/nucleo_g474re/doc/index.rst b/boards/arm/nucleo_g474re/doc/index.rst deleted file mode 100644 index 87fca388905a45..00000000000000 --- a/boards/arm/nucleo_g474re/doc/index.rst +++ /dev/null @@ -1,255 +0,0 @@ -.. _nucleo_g474re_board: - -ST Nucleo G474RE -################ - -Overview -******** - -The Nucleo G474RE board features an ARM Cortex-M4 based STM32G474RE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo G474RE board: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V3E debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) -- Two push-buttons: RESET and USER - -.. image:: img/nucleo_g474re.jpg - :align: center - :alt: Nucleo G474RE - -More information about the board can be found at the `Nucleo G474RE website`_. - -Hardware -******** - -The STM32G474RE SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz -- Clock Sources: - - - 4 to 48 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- 14x timers: - - - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop - - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop - - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop - - 2x watchdog timers (independent, window) - - 2x 16-bit basic timers - - SysTick timer - - 1x low-power timer - -- Up to 86 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 128 KB single bank Flash, proprietary code readout protection - - Up to 22 KB of SRAM including 16 KB with hardware parity check - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 4x 12-bit DAC, low-power sample and hold - - 3x operational amplifiers with built-in PGA - - 4x ultra-fast rail-to-rail analog comparators - -- 16x communication interfaces - - - 1 x FDCAN controller supporting flexible data rate - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (2x with multiplexed half duplex I2S interface) - - 1x SAI (serial audio interface) - - USB 2.0 full-speed interface with LPM and BCD support - - IRTIM (Infrared interface) - - USB Type-C™ /USB power delivery controller (UCPD) - -- 12-channel DMA controller -- True random number generator (RNG) -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32G474RE can be found here: - -- `STM32G474RE on www.st.com`_ -- `STM32G4 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_g474re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ -| FDCAN1 | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_g474re/nucleo_g474re_defconfig`` - - -Connections and IOs -=================== - -Nucleo G474RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PC4 -- UART_1_RX : PC5 -- LPUART_1_TX : PA2 -- LPUART_1_RX : PA3 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- SPI_1_NSS : PB6 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PB12 -- SPI_2_SCK : PB13 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PA15 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_2_CH1 : PA5 (might conflict with SPI1) -- PWM_3_CH1 : PB4 -- USER_PB : PC13 -- LD2 : PA5 -- ADC1_IN1 : PA0 -- DAC1_OUT1 : PA4 -- FDCAN1_RX: PA11 -- FDCAN1_TX: PA12 - -System Clock ------------- - -Nucleo G474RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, -driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode -is selected. - -Serial Port ------------ - -Nucleo G474RE board has 3 U(S)ARTs. The Zephyr console output is assigned to LPUART1. -Default settings are 115200 8N1. - -Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in -low power mode. - -Programming and Debugging -************************* - -Applications for the ``nucleo_g474re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface. - -Flashing an application to Nucleo G474RE ----------------------------------------- - -Connect the Nucleo G474RE to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g474re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_g474re - :maybe-skip-config: - :goals: debug - -.. _Nucleo G474RE website: - https://www.st.com/en/evaluation-tools/nucleo-g474re.html - -.. _STM32G4 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00556337.pdf - -.. _STM32G474RE on www.st.com: - https://www.st.com/en/microcontrollers/stm32g474re.html - -.. _STM32G4 reference manual: - https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_h563zi/Kconfig.board b/boards/arm/nucleo_h563zi/Kconfig.board deleted file mode 100644 index debcb2a4ab8921..00000000000000 --- a/boards/arm/nucleo_h563zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H563ZI Nucleo board configuration - -# Copyright (c) 2023 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H563ZI - bool "Nucleo H563ZI Development Board" - depends on SOC_STM32H563XX diff --git a/boards/arm/nucleo_h563zi/Kconfig.defconfig b/boards/arm/nucleo_h563zi/Kconfig.defconfig deleted file mode 100644 index 4730fdb7a7972f..00000000000000 --- a/boards/arm/nucleo_h563zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32H563ZI Nucleo board configuration - -# Copyright (c) 2023 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H563ZI - -config BOARD - default "nucleo_h563zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H563ZI diff --git a/boards/arm/nucleo_h563zi/doc/index.rst b/boards/arm/nucleo_h563zi/doc/index.rst deleted file mode 100644 index 7d1ac5c5b5aeae..00000000000000 --- a/boards/arm/nucleo_h563zi/doc/index.rst +++ /dev/null @@ -1,317 +0,0 @@ -.. _nucleo_h563zi_board: - -ST Nucleo H563ZI -################ - -Overview -******** - -The Nucleo H563ZI board is designed as an affordable development platform for -STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H563ZIT6 -microcontroller with TrustZone |reg|. -Here are some highlights of the Nucleo H563ZI board: - -- STM32H563ZI microcontroller featuring 2 Mbytes of Flash memory and 640Kbyte of - SRAM in LQFP144 package -- Board connectors: - - - USB Type-C |trade| Sink device FS - - Ethernet RJ45 connector compliant with IEEE-802.3-2002 (depending on STM32 support) - - ST Zio expansion connector including Arduino Uno V3 connectivity (CN7, CN8, CN9, CN10) - - ST morpho extension connector (CN11, CN12) - -- Flexible board power supply: - - - 5V_USB_STLK from ST-Link USB connector - - VIN (7 - 12V, 0.8A) supplied via pin header CN8 pin 15 or CN11 pin 24 - - 5V_EXT on the ST morpho connector CN11 Pin 6 (5V, 1.3) - - CHGR from a USB charger via the ST-LINK USB connector - - USB_USER from the USB user connector (5V, 3A) - - 3V3_EXT supplied via a pin header CN8 pin 7 or CN11 pin 16 (3.3V, 1.3A) - -- On-board ST-LINK/V3EC debugger/programmer - - - mass storage - - Virtual COM port - - debug port - -- Three users LEDs -- Two push-buttons: USER and RESET -- 32.789 kHz crystal oscillator - -More information about the board can be found at the `NUCLEO_H563ZI website`_. - -.. image:: img/nucleo_h563zi.jpg - :align: center - :alt: NUCLEO H563ZI - -Hardware -******** - -The STM32H563xx devices are high-performance microcontrollers from the STM32H5 -Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. -They operate at a frequency of up to 250 MHz. - -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 375 DMPIS/MHz (Dhrystone 2.1) - -- Security - - - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension - - Up to 8 configurable SAU regions - - TrustZone |reg| aware and securable peripherals - - Flexible lifecycle scheme with secure debug authentication - - SFI (secure firmware installation) - - Secure firmware upgrade support with TF-M - - HASH hardware accelerator - - True random number generator, NIST SP800-90B compliant - - 96-bit unique ID - - Active tampers - -- Clock management: - - - 25 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 64 MHz (HSI) trimmable by software - - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) - - Internal 4 MHz oscillator (CSI), trimmable by software - - Internal 48 MHz (HSI48) with recovery system - - 3 PLLs for system clock, USB, audio, ADC - -- Power management - - - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry - - Embedded SMPS step-down converter - -- RTC with HW calendar, alarms and calibration -- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V -- Up to 16 timers and 2 watchdogs - - - 12x 16-bit - - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 6x 16-bit low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- Memories - - - Up to 2 MB Flash, 2 banks read-while-write - - 1 Kbyte OTP (one-time programmable) - - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC - - 4 Kbytes of backup SRAM available in the lowest power modes - - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories - - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats - - 2x SD/SDIO/MMC interfaces - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC with up to 5 MSPS in 12-bit - - 1x 12-bit D/A with 2 channels - - 1x Digital temperature sensor - -- 34x communication interfaces - - - 1x USB Type-C / USB power-delivery controller - - 1x USB 2.0 full-speed host and device - - 4x I2C FM+ interfaces (SMBus/PMBus) - - 1x I3C interface - - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) - - 1x LP UART - - 6x SPIs including 3 muxed with full-duplex I2S - - 5x additional SPI from 5x USART when configured in Synchronous mode - - 2x SAI - - 2x FDCAN - - 1x SDMMC interface - - 2x 16 channel DMA controllers - - 1x 8- to 14- bit camera interface - - 1x HDMI-CEC - - 1x Ethernel MAC interface with DMA controller - - 1x 16-bit parallel slave synchronous-interface - -- CORDIC for trigonometric functions acceleration -- FMAC (filter mathematical accelerator) -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - -More information about STM32H563ZI can be found here: - -- `STM32H563ZI on www.st.com`_ -- `STM32H563 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_h563zi board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | Real Time Clock | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi bus | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB full-speed host/device bus | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- Secure target: - - - :zephyr_file:`boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig` - - :zephyr_file:`boards/arm/nucleo_h563zi/nucleo_h563zi.dts` - -Zephyr board options -==================== - -The STM32H563 is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| nucleo_h563zi | For building Secure firmware | -+----------------------+-----------------------------------------------+ - -Connections and IOs -=================== - -Nucleo H563ZI Board has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32H5 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- ADC1 channel 3 input: PA6 -- ADC1 channel 15 input: PA3 -- DAC1 channel 2 output: PA5 -- LD1 (green): PB0 -- LD2 (yellow): PF4 -- LD3 (red): PG4 -- LPUART1 TX/RX : PB6/PB7 (Arduino LPUART1) -- SPI1 SCK/MISO/MOSI/CS: PA5/PG9/PB5/PD14 -- UART3 TX/RX : PD8/PD9 (VCP) -- USER_PB : PC13 - -System Clock ------------- - -Nucleo H563ZI System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -240MHz, driven by 8MHz external clock provided from the STLINK-V3EC. - -Serial Port ------------ - -Nucleo H563ZI board has up to 12 U(S)ARTs. The Zephyr console output is assigned -to USART3. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h563zi`` board can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo H563ZI board includes an ST-LINK/V3EC embedded debug tool interface. -This probe allows to flash the board using various tools. - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, pyocd or jlink via an external probe can also be used to flash -and debug the board if west is told to use it as runner, which can be done by -passing either or ``-r pyocd``, or ``-r jlink``. - -For pyocd additional target information needs to be installed. -This can be done by executing the following commands. - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32h5 - - -Flashing an application to Nucleo H563ZI ------------------------------------------- - -Connect the Nucleo H563ZI to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h563zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! nucleo_h563zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_h563zi - :goals: debug - -.. _NUCLEO_H563ZI website: - https://www.st.com/en/evaluation-tools/nucleo-h563zi - -.. _STM32H5 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um3115-stm32h5-nucleo144-board-mb1404-stmicroelectronics.pdf - -.. _STM32H563ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32h563zi.html - -.. _STM32H563 reference manual: - https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_h723zg/Kconfig.board b/boards/arm/nucleo_h723zg/Kconfig.board deleted file mode 100644 index da658f90c6d068..00000000000000 --- a/boards/arm/nucleo_h723zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H723ZG Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H723ZG - bool "NUCLEO-H723ZG Development Board" - depends on SOC_STM32H723XX diff --git a/boards/arm/nucleo_h723zg/Kconfig.defconfig b/boards/arm/nucleo_h723zg/Kconfig.defconfig deleted file mode 100644 index 26f4491a7ad067..00000000000000 --- a/boards/arm/nucleo_h723zg/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H723ZG Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H723ZG - -config BOARD - default "nucleo_h723zg" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config USB_DC_HAS_HS_SUPPORT - default y - depends on USB_DC_STM32 - -endif # BOARD_NUCLEO_H723ZG diff --git a/boards/arm/nucleo_h723zg/doc/index.rst b/boards/arm/nucleo_h723zg/doc/index.rst deleted file mode 100644 index 44a87bb512930a..00000000000000 --- a/boards/arm/nucleo_h723zg/doc/index.rst +++ /dev/null @@ -1,248 +0,0 @@ -.. _nucleo_h723zg_board: - -ST Nucleo H723ZG -################ - -Overview -******** - -The STM32 Nucleo-144 board provides an affordable and flexible way for users -to try out new concepts and build prototypes by choosing from the various combinations -of performance and power consumption features, provided by the STM32 microcontroller. -For the compatible boards, the internal or external SMPS significantly reduces power -consumption in Run mode. - -The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and -the ST morpho headers provide an easy means of expanding the functionality of the Nucleo -open development platform with a wide choice of specialized shields. -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK V3 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - Ethernet RJ45 (depending on STM32 support) - - SWDST Zio connector including Arduino* Uno V3ST - - ST morpho expansion - -- Flexible power-supply options: ST-LINK USB VBUS or external sources -- External or internal SMPS to generate Vcore logic supply -- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port -- USB OTG full speed or device only - -.. image:: img/nucleo_h723zg.jpg - :align: center - :alt: Nucleo H723ZG - -More information about the board can be found at the `Nucleo H723ZG website`_. - -Hardware -******** - -Nucleo H723ZG provides the following hardware components: - -- STM32H723ZG in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 550 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 1 MB Flash -- 562 kB SRAM max (376 kb used currently) -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h723zg board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration per core can be found in the defconfig files: -``boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H723ZG board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 -- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) - -System Clock ------------- - -Nucleo H723ZG System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 550MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H723ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB52`` jumper on the back side of the board. - -Programming and Debugging -************************* - -Currently the ``nucleo_h723zg`` board supports stm32cubeprogrammer (default), OpenOCD and J-Link debuggers. - -.. note:: - - Official OpenOCD support for this board was added on October '20. - Make sure your openocd version is older than that. - Following links may be helpful: `OpenOCD installing Debug Version`_ - and `OpenOCD installing with ST-LINK V3 support`_ - -.. note:: - - Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ - -Flashing -======== - -Nucleo H723ZG board includes an ST-LINK/V3 embedded debug tool interface. - -First, connect the NUCLEO-H723ZG to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your NUCLEO-H723ZG board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -or use screen: - -.. code-block:: console - - $ screen /dev/ttyACM0 115200 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h723zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h723zg - -Blinky example can also be used: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_h723zg - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h723zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo H723ZG website: - https://www.st.com/en/evaluation-tools/nucleo-h723zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00499160-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf - -.. _STM32H723ZG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h723zg.html - -.. _STM32H723 reference manual: - https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _OpenOCD installing Debug Version: - https://github.com/zephyrproject-rtos/openocd - -.. _OpenOCD installing with ST-LINK V3 support: - https://mbd.kleier.net/integrating-st-link-v3.html - -.. _STM32CubeIDE: - https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h743zi/Kconfig.board b/boards/arm/nucleo_h743zi/Kconfig.board deleted file mode 100644 index 9417b98e6709b5..00000000000000 --- a/boards/arm/nucleo_h743zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H743ZI Nucleo board configuration - -# Copyright (c) 2020 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H743ZI - bool "Nucleo H743ZI Development Board" - depends on SOC_STM32H743XX diff --git a/boards/arm/nucleo_h743zi/Kconfig.defconfig b/boards/arm/nucleo_h743zi/Kconfig.defconfig deleted file mode 100644 index e426be48d7f113..00000000000000 --- a/boards/arm/nucleo_h743zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32H743ZI Nucleo board configuration - -# Copyright (c) 2020 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H743ZI - -config BOARD - default "nucleo_h743zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H743ZI diff --git a/boards/arm/nucleo_h743zi/doc/index.rst b/boards/arm/nucleo_h743zi/doc/index.rst deleted file mode 100644 index e6cb6e242cddff..00000000000000 --- a/boards/arm/nucleo_h743zi/doc/index.rst +++ /dev/null @@ -1,246 +0,0 @@ -.. _nucleo_h743zi_board: - -ST Nucleo H743ZI -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h743zi.jpg - :align: center - :alt: Nucleo H743ZI - -More information about the board can be found at the `Nucleo H743ZI website`_. - -Hardware -******** - -Nucleo H743ZI provides the following hardware components: - -- STM32H743ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 480 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- 1 MB SRAM -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h743zi board configuration supports the following hardware -features: - -+-------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-------------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-------------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-------------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-------------+------------+-------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-------------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-------------+------------+-------------------------------------+ -| CAN/CANFD | on-chip | canbus | -+-------------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-------------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H743ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 -- ADC1_INP15 : PA3 -- DAC1_OUT1 : PA4 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PB5 (Arduino SPI) -- CAN/CANFD : PD0, PD1 - -System Clock ------------- - -Nucleo H743ZI System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H743ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB156`` jumper on the back side of the board. - -CAN, CANFD ----------- - -Requires an external CAN or CANFD transceiver. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h743zi`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series yet. You can also choose the - ``stm32cubeprogrammer`` runner. - -Flashing -======== - -Nucleo H743ZI board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo H743ZI ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h743zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h743zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h743zi - :maybe-skip-config: - :goals: debug - -.. _Nucleo H743ZI website: - https://www.st.com/en/evaluation-tools/nucleo-h743zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32H743ZI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h743zi.html - -.. _STM32H743 reference manual: - https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h745zi_q/Kconfig.board b/boards/arm/nucleo_h745zi_q/Kconfig.board deleted file mode 100644 index 0b5c572861077b..00000000000000 --- a/boards/arm/nucleo_h745zi_q/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# STM32H745ZI Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H745ZI_Q_M7 - bool "NUCLEO-H745ZI-Q Development Board" - depends on SOC_STM32H745XX - select CPU_CORTEX_M7 - -config BOARD_NUCLEO_H745ZI_Q_M4 - bool "NUCLEO-H745ZI-Q Development Board" - depends on SOC_STM32H745XX - select CPU_CORTEX_M4 diff --git a/boards/arm/nucleo_h745zi_q/Kconfig.defconfig b/boards/arm/nucleo_h745zi_q/Kconfig.defconfig deleted file mode 100644 index 0d7f628f8ac56a..00000000000000 --- a/boards/arm/nucleo_h745zi_q/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# STM32H745ZI Nucleo board configuration - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H745ZI_Q_M7 || BOARD_NUCLEO_H745ZI_Q_M4 - -config BOARD - default "nucleo_h745zi_q_m7" if BOARD_NUCLEO_H745ZI_Q_M7 - default "nucleo_h745zi_q_m4" if BOARD_NUCLEO_H745ZI_Q_M4 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H745ZI_Q_M7 or BOARD_NUCLEO_H745ZI_Q_M4 diff --git a/boards/arm/nucleo_h745zi_q/board.cmake b/boards/arm/nucleo_h745zi_q/board.cmake deleted file mode 100644 index b5ca36713e8f41..00000000000000 --- a/boards/arm/nucleo_h745zi_q/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=STM32H745ZI" "--speed=4000") -if(CONFIG_BOARD_NUCLEO_H745ZI_Q_M7) -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) -elseif(CONFIG_BOARD_NUCLEO_H745ZI_Q_M4) -board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/nucleo_h745zi_q/doc/index.rst b/boards/arm/nucleo_h745zi_q/doc/index.rst deleted file mode 100644 index 36c4b80bc58add..00000000000000 --- a/boards/arm/nucleo_h745zi_q/doc/index.rst +++ /dev/null @@ -1,290 +0,0 @@ -.. _nucleo_h745zi_q_board: - -ST Nucleo H745ZI-Q -################### - -Overview -******** - -The STM32 Nucleo-144 board provides an affordable and flexible way for users -to try out new concepts and build prototypes by choosing from the various combinations -of performance and power consumption features, provided by the STM32 microcontroller. -For the compatible boards, the internal or external SMPS significantly reduces power -consumption in Run mode. - -The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and -the ST morpho headers provide an easy means of expanding the functionality of the Nucleo -open development platform with a wide choice of specialized shields. -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK V3 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - Ethernet RJ45 (depending on STM32 support) - - SWDST Zio connector including Arduino* Uno V3ST - - ST morpho expansion - -- Flexible power-supply options: ST-LINK USB VBUS or external sources -- External or internal SMPS to generate Vcore logic supply -- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port -- USB OTG full speed or device only -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h745zi_q.jpg - :align: center - :alt: Nucleo H745ZI-Q - -More information about the board can be found at the `Nucleo H745ZI-Q website`_. - -Hardware -******** - -Nucleo H745ZI-Q provides the following hardware components: - -- STM32H745ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- ARM 32-bit Cortex-M4 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 480 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- 1 MB SRAM -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h745zi_q board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration per core can be found in the defconfig files: -``boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig`` and -``boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H745ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 - -System Clock ------------- - -Nucleo H745ZI-Q System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H745ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -Resources sharing ------------------ - -The dual core nature of STM32H745 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h745zi_q`` board should be built per core target, -using either ``nucleo_h745zi_q_m7`` or ```nucleo_h745zi_q_m4`` as the target -(see :ref:`build_an_application` and :ref:`application_run` for more details). - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series and ST-LINK V3 yet. - Following links may be helpful: `OpenOCD installing Debug Version`_ - and `OpenOCD installing with ST-LINK V3 support`_ - -.. note:: - - Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ - -Flashing -======== - -Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. - -By default: - - - CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) - - CPU1 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) - -Also, default out of the box board configuration enables CM7 and CM4 boot when -board is powered (Option bytes BCM7 and BCM4 are checked). -In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected. -Zephyr flash configuration has been set to meet these default settings. - -Flashing an application to STM32H745ZI M7 Core ----------------------------------------------- -First, connect the NUCLEO-H745ZI-Q to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your NUCLEO-H745ZI-Q board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -or use screen: - -.. code-block:: console - - $ screen /dev/ttyACM0 115200 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h745zi_q_m7 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h745zi_q_m7 - -.. note:: - Sometimes, flashing is not working. It is necessary to erase the flash - (with STM32CubeProgrammer for example) to make it work again. - -Similarly, you can build and flash samples on the M4 target. For this, please -take care of the resource sharing (UART port used for console for instance). - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_h745zi_q_m4 - :goals: build flash - -.. note:: - - Flashing both M4 and M7 and pushing RESTART button on the board leads - to LD1 and LD2 flashing simultaneously. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h745zi_q_m7 - :maybe-skip-config: - :goals: debug - -Debugging with west is currently not available on Cortex M4 side. -In order to debug a Zephyr application on Cortex M4 side, you can use -`STM32CubeIDE`_. - -.. _Nucleo H745ZI-Q website: - https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00499171-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf - -.. _STM32H745ZI on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h745zi.html - -.. _STM32H745 reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _OpenOCD installing Debug Version: - https://github.com/zephyrproject-rtos/openocd - -.. _OpenOCD installing with ST-LINK V3 support: - https://mbd.kleier.net/integrating-st-link-v3.html - -.. _STM32CubeIDE: - https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.yaml b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.yaml deleted file mode 100644 index 3299fb7849678f..00000000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: nucleo_h745zi_q_m4 -name: ST Nucleo H745ZI-Q (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - arduino_gpio - - gpio - - netif:eth -testing: - ignore_tags: - - mpu - - nfc -vendor: st diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig deleted file mode 100644 index b6233762bbd975..00000000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H745XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_NUCLEO_H745ZI_Q_M4=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable clock -CONFIG_CLOCK_CONTROL=y - -# By default SERIAL peripherals are assigned to m7 - -# Enable uart driver -#CONFIG_SERIAL=y - -# Console -#CONFIG_CONSOLE=y -#CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.yaml b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.yaml deleted file mode 100644 index 8c124a0a906d42..00000000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: nucleo_h745zi_q_m7 -name: ST Nucleo H745ZI-Q (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - arduino_gpio - - arduino_i2c - - uart - - gpio - - counter - - i2c - - pwm - - netif:eth -vendor: st diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig b/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig deleted file mode 100644 index d57388f06ad5ba..00000000000000 --- a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H745XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_NUCLEO_H745ZI_Q_M7=y - -# Enable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable UART ( disable to assign to M4 core) -CONFIG_SERIAL=y - -# Console ( disable to assign to M4 core) -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable Clock -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h753zi/Kconfig.board b/boards/arm/nucleo_h753zi/Kconfig.board deleted file mode 100644 index 15d573da300b8c..00000000000000 --- a/boards/arm/nucleo_h753zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H753ZI Nucleo board configuration - -# Copyright (c) 2021 Blue Clover Devices -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H753ZI - bool "Nucleo H753ZI Development Board" - depends on SOC_STM32H753XX diff --git a/boards/arm/nucleo_h753zi/Kconfig.defconfig b/boards/arm/nucleo_h753zi/Kconfig.defconfig deleted file mode 100644 index 60abed56e42330..00000000000000 --- a/boards/arm/nucleo_h753zi/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32H753ZI Nucleo board configuration - -# Copyright (c) 2021 Blue Clover Devices -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H753ZI - -config BOARD - default "nucleo_h753zi" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_H753ZI diff --git a/boards/arm/nucleo_h753zi/doc/index.rst b/boards/arm/nucleo_h753zi/doc/index.rst deleted file mode 100644 index eab88c9952a7a4..00000000000000 --- a/boards/arm/nucleo_h753zi/doc/index.rst +++ /dev/null @@ -1,233 +0,0 @@ -.. _nucleo_h753zi_board: - -ST Nucleo H753ZI -################ - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V2-1 debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - Ethernet RJ45 (depending on STM32 support) - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h753zi.jpg - :align: center - :alt: Nucleo H753ZI - -More information about the board can be found at the `Nucleo H753ZI website`_. - -Hardware -******** - -Nucleo H753ZI provides the following hardware components: - -- STM32H753ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 480 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- 1 MB SRAM -- High-resolution timer (2.1 ns) -- 32-bit timers(2) -- 16-bit timers(12) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(4) -- UART(4) -- USB OTG Full Speed and High Speed(1) -- USB OTG Full Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(3) with 36 channels / 3.6 MSPS -- 12-bit DAC with 2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution -- Cryptographic acceleration: AES 128, 192, 256, TDES, HASH (MD5, SHA-1, SHA-2), HMAC -- Secure firmware upgrade support, Secure access mode - -Supported Features -================== - -The Zephyr nucleo_h753zi board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | counter | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ -| CAN/CANFD | on-chip | canbus | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H753ZI board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PB7 -- LD3 : PB14 -- I2C : PB8, PB9 -- ADC1_INP15 : PA3 -- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 -- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) -- CAN/CANFD : PD0, PD1 - -System Clock ------------- - -Nucleo H753ZI System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H753ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to UART3. Default settings are 115200 8N1. - -CAN, CANFD ----------- - -Requires an external CAN or CANFD transceiver. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h753zi`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 series yet. You can also choose the - ``stm32cubeprogrammer`` runner. - -Flashing -======== - -Nucleo H753ZI board includes an ST-LINK/V2-1 embedded debug tool interface. - -Flashing an application to Nucleo H753ZI ----------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h753zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h753zi - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h753zi - :maybe-skip-config: - :goals: debug - -.. _Nucleo H753ZI website: - https://www.st.com/en/evaluation-tools/nucleo-h753zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00244518.pdf - -.. _STM32H753ZI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h753zi.html - -.. _STM32H753 reference manual: - https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h7a3zi_q/Kconfig.board b/boards/arm/nucleo_h7a3zi_q/Kconfig.board deleted file mode 100644 index 3d8317ac2864fb..00000000000000 --- a/boards/arm/nucleo_h7a3zi_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H7A3ZI-Q Nucleo board configuration - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_H7A3ZI_Q - bool "Nucleo H75A3ZI-Q Development Board" - depends on SOC_STM32H7A3XXQ diff --git a/boards/arm/nucleo_h7a3zi_q/Kconfig.defconfig b/boards/arm/nucleo_h7a3zi_q/Kconfig.defconfig deleted file mode 100644 index ec43ace7dcb5cf..00000000000000 --- a/boards/arm/nucleo_h7a3zi_q/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32H7A3ZI-Q Nucleo board configuration - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_H7A3ZI_Q - -config BOARD - default "nucleo_h7a3zi_q" - -config USB_DC_HAS_HS_SUPPORT - default y - depends on USB_DC_STM32 - -endif # BOARD_NUCLEO_H7A3ZI_Q diff --git a/boards/arm/nucleo_h7a3zi_q/doc/index.rst b/boards/arm/nucleo_h7a3zi_q/doc/index.rst deleted file mode 100644 index 1144f13e731406..00000000000000 --- a/boards/arm/nucleo_h7a3zi_q/doc/index.rst +++ /dev/null @@ -1,206 +0,0 @@ -.. _nucleo_h7a3zi_q_board: - -ST Nucleo H7A3ZI-Q -################## - -Overview -******** - -The STM32 Nucleo-144 boards offer combinations of performance and power that -provide an affordable and flexible way for users to build prototypes and try -out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) -significantly reduces power consumption in Run mode. - -The Arduino-compatible ST Zio connector expands functionality of the Nucleo -open development platform, with a wide choice of specialized Arduino* Uno V3 -shields. - -The STM32 Nucleo-144 board does not require any separate probe as it integrates -the ST-LINK/V3E debugger/programmer. - -The STM32 Nucleo-144 board comes with the STM32 comprehensive free software -libraries and examples available with the STM32Cube MCU Package. - -Key Features - -- STM32 microcontroller in LQFP144 package -- USB OTG or full-speed device (depending on STM32 support) -- 3 user LEDs -- 2 user and reset push-buttons -- 32.768 kHz crystal oscillator -- Board connectors: - - - USB with Micro-AB - - SWD - - ST Zio connector including Arduino* Uno V3 - - ST morpho - -- Flexible power-supply options: ST-LINK USB VBUS or external sources. -- On-board ST-LINK/V3E debugger/programmer with USB re-enumeration -- capability: mass storage, virtual COM port and debug port. -- Comprehensive free software libraries and examples available with the - STM32Cube MCU package. -- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) - -.. image:: img/nucleo_h7a3zi_q.jpg - :align: center - :alt: Nucleo H7A3ZI-Q - -More information about the board can be found at the `Nucleo H7A3ZI-Q website`_. - -Hardware -******** - -Nucleo H7A3ZI-Q provides the following hardware components: - -- STM32H7A3ZI in LQFP144 package -- ARM 32-bit Cortex-M7 CPU with FPU -- Chrom-ART Accelerator -- Hardware JPEG Codec -- 280 MHz max CPU frequency -- VDD from 1.62 V to 3.6 V -- 2 MB Flash -- ~1.4 Mbytes SRAM -- 32-bit timers(2) -- 16-bit timers(15) -- SPI(6) -- I2C(4) -- I2S (3) -- USART(5) -- UART(5) -- USB OTG Full Speed and High Speed(1) -- CAN FD(2) -- SAI(2) -- SPDIF_Rx(4) -- HDMI_CEC(1) -- Dual Mode Quad SPI(1) -- Camera Interface -- GPIO (up to 114) with external interrupt capability -- 16-bit ADC(2) with 24 channels / 3.6 MSPS -- 12-bit DAC with 1/2 channels(2) -- True Random Number Generator (RNG) -- 16-channel DMA -- LCD-TFT Controller with XGA resolution - -Supported Features -================== - -The Zephyr nucleo_h7a3zi_q board configuration supports the following hardware -features: - -+-------------+------------+------------------------------------+ -| Interface | Controller | Driver/Component | -+=============+============+====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-------------+------------+------------------------------------+ -| UART | on-chip | serial port | -+-------------+------------+------------------------------------+ -| PINMUX | on-chip | pinmux | -+-------------+------------+------------------------------------+ -| GPIO | on-chip | gpio | -+-------------+------------+------------------------------------+ -| PWM | on-chip | pwm | -+-------------+------------+------------------------------------+ -| ADC | on-chip | adc | -+-------------+------------+------------------------------------+ -| Backup SRAM | on-chip | Backup SRAM | -+-------------+------------+------------------------------------+ -| USB OTG HS | on-chip | USB device | -+-------------+------------+------------------------------------+ -| RNG | on-chip | True Random number generator | -+-------------+------------+------------------------------------+ - - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig`` - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The Nucleo H7A3ZI-Q board features a ST Zio connector (extended Arduino Uno V3) -and a ST morpho connector. Board is configured as follows: - -- USART3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- USER_PB : PC13 -- LD1 : PB0 -- LD2 : PE1 -- LD3 : PB14 -- ADC1_INP15 : PA3 (Arduino analog, A0) - -System Clock ------------- - -Nucleo H7A3ZI-Q System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. - -Serial Port ------------ - -Nucleo H7A3ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is -assigned to USART3. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``nucleo_h7a3zi_q`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo H7A3ZI-Q board includes an ST-LINK/V3E embedded debug tool interface. - -Flashing an application to Nucleo H7A3ZI-Q ------------------------------------------- - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h7a3zi_q - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_h7a3zi_q - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_h7a3zi_q - :maybe-skip-config: - :goals: debug - -.. _Nucleo H7A3ZI-Q website: - https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html#overview - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um2408-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf - -.. _STM32H7A3ZI-Q on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3zi.html - -.. _STM32H7A3ZI-Q reference manual: - https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l011k4/Kconfig.board b/boards/arm/nucleo_l011k4/Kconfig.board deleted file mode 100644 index aa6401045f7e4b..00000000000000 --- a/boards/arm/nucleo_l011k4/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L011K4 MCU configuration - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L011K4 - bool "NUCLEO-32 L011K4 Development Board" - depends on SOC_STM32L011XX diff --git a/boards/arm/nucleo_l011k4/Kconfig.defconfig b/boards/arm/nucleo_l011k4/Kconfig.defconfig deleted file mode 100644 index 527a93140cb065..00000000000000 --- a/boards/arm/nucleo_l011k4/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L011K4 MCU - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L011K4 - -config BOARD - default "nucleo_l011k4" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L011K4 diff --git a/boards/arm/nucleo_l011k4/doc/index.rst b/boards/arm/nucleo_l011k4/doc/index.rst deleted file mode 100644 index 04fc12c53f32b4..00000000000000 --- a/boards/arm/nucleo_l011k4/doc/index.rst +++ /dev/null @@ -1,167 +0,0 @@ -.. _nucleo_l011k4_board: - -ST Nucleo L011K4 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32L011K4 MCU, supports Arduino Nano V3 connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Nano V3 connectivity support allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l011k4.jpg - :align: center - :alt: Nucleo L011K4 - -More information about the board can be found at the `Nucleo L011K4 website`_. - -Hardware -******** -Nucleo L011K4 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package -- Extension resource: - - - Arduino* Nano V3 connectivity - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- One push-button: RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32L011K4 can be found in the -`STM32L0x1 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_l011k4 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PA4/PA10 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l011k4`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L011K4 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L011K4 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l011k4 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l011k4 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L011K4 website: - https://www.st.com/en/evaluation-tools/nucleo-l011k4.html - -.. _STM32L0x1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l031k6/Kconfig.board b/boards/arm/nucleo_l031k6/Kconfig.board deleted file mode 100644 index 43b52d42020a03..00000000000000 --- a/boards/arm/nucleo_l031k6/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L031K6 MCU configuration - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L031K6 - bool "NUCLEO-32 L031K6 Development Board" - depends on SOC_STM32L031XX diff --git a/boards/arm/nucleo_l031k6/Kconfig.defconfig b/boards/arm/nucleo_l031k6/Kconfig.defconfig deleted file mode 100644 index 0c84a21c58795f..00000000000000 --- a/boards/arm/nucleo_l031k6/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-32 development board with STM32L031K6 MCU - -# Copyright (c) 2020 Steven Daglish -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L031K6 - -config BOARD - default "nucleo_l031k6" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L031K6 diff --git a/boards/arm/nucleo_l031k6/doc/index.rst b/boards/arm/nucleo_l031k6/doc/index.rst deleted file mode 100644 index da0fcaa271e3ce..00000000000000 --- a/boards/arm/nucleo_l031k6/doc/index.rst +++ /dev/null @@ -1,160 +0,0 @@ -.. _nucleo_l031k6_board: - -ST Nucleo L031K6 -################ - -Overview -******** -The STM32 Nucleo-32 development board with STM32L031K6 MCU, supports Arduino Nano V3 connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Nano V3 connectivity support allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l031k6.jpg - :align: center - :alt: Nucleo L031K6 - -More information about the board can be found at the `Nucleo L031K6 website`_. - -Hardware -******** -Nucleo L031K6 provides the following hardware components: - -- STM32 microcontroller in LQFP32 package -- Extension resource: - - - Arduino* Nano V3 connectivity - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- One push-button: RESET - -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32L031K6 can be found in the -`STM32L0x1 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l031k6 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PA9/PA10 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- LD2 : PB3 - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l031k6`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L031K6 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l031k6 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l031k6 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L031K6 website: - https://www.st.com/en/evaluation-tools/nucleo-l031k6.html - -.. _STM32L0x1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l053r8/Kconfig.board b/boards/arm/nucleo_l053r8/Kconfig.board deleted file mode 100644 index 2500f89b00be45..00000000000000 --- a/boards/arm/nucleo_l053r8/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L053R8 MCU configuration - -# Copyright (c) 2018 Anthony Kreft -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L053R8 - bool "NUCLEO-64 L053R8 Development Board" - depends on SOC_STM32L053XX diff --git a/boards/arm/nucleo_l053r8/Kconfig.defconfig b/boards/arm/nucleo_l053r8/Kconfig.defconfig deleted file mode 100644 index bcf55dcc95e687..00000000000000 --- a/boards/arm/nucleo_l053r8/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L053R8 MCU - -# Copyright (c) 2018 Anthony Kreft -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L053R8 - -config BOARD - default "nucleo_l053r8" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L053R8 diff --git a/boards/arm/nucleo_l053r8/doc/index.rst b/boards/arm/nucleo_l053r8/doc/index.rst deleted file mode 100644 index ba448176fcad9b..00000000000000 --- a/boards/arm/nucleo_l053r8/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _nucleo_l053r8_board: - -ST Nucleo L053R8 -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32L053R8 MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l053r8.jpg - :align: center - :alt: Nucleo L053R8 - -More information about the board can be found at the `Nucleo L053R8 website`_. - -Hardware -******** -Nucleo L053R8 provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32L053R8 can be found in the -`STM32L0x3 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_l053r8 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_l053r8_connectors.jpg - :align: center - :alt: Nucleo L053R8 connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- USER_PB : PC13 -- LD2 : PA5 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l053r8`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L053R8 board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L053R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l053r8 - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l053r8 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L053R8 website: - https://www.st.com/en/evaluation-tools/nucleo-l053r8.html - -.. _STM32L0x3 reference manual: - https://www.st.com/resource/en/reference_manual/dm00095744.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l073rz/Kconfig.board b/boards/arm/nucleo_l073rz/Kconfig.board deleted file mode 100644 index 4354ccf843313b..00000000000000 --- a/boards/arm/nucleo_l073rz/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L073RZ MCU configuration - -# Copyright (c) 2018 Ilya Tagunov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L073RZ - bool "NUCLEO-64 L073RZ Development Board" - depends on SOC_STM32L073XX diff --git a/boards/arm/nucleo_l073rz/Kconfig.defconfig b/boards/arm/nucleo_l073rz/Kconfig.defconfig deleted file mode 100644 index 6a73209134a8f8..00000000000000 --- a/boards/arm/nucleo_l073rz/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32 Nucleo-64 development board with STM32L073RZ MCU - -# Copyright (c) 2018 Ilya Tagunov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L073RZ - -config BOARD - default "nucleo_l073rz" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L073RZ diff --git a/boards/arm/nucleo_l073rz/doc/index.rst b/boards/arm/nucleo_l073rz/doc/index.rst deleted file mode 100644 index a828a5b70eb69d..00000000000000 --- a/boards/arm/nucleo_l073rz/doc/index.rst +++ /dev/null @@ -1,190 +0,0 @@ -.. _nucleo_l073rz_board: - -ST Nucleo L073RZ -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32L073RZ MCU, supports Arduino and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption, and features. - -The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l073rz.jpg - :align: center - :alt: Nucleo L073RZ - -More information about the board can be found at the `Nucleo L073RZ website`_. - -Hardware -******** -Nucleo L073RZ provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino* Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- ARM* mbed* -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: USER and RESET -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -- Support of wide choice of Integrated Development Environments (IDEs) including: - - - IAR - - ARM Keil - - GCC-based IDEs - -More information about STM32L073RZ can be found in the -`STM32L0x3 reference manual`_ - - -Supported Features -================== - -The Zephyr nucleo_l073rz board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi controller | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | Random Number Generator | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_l073rz_connectors.jpg - :align: center - :alt: Nucleo L073RZ connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PB7 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) -- USER_PB : PC13 -- LD2 : PA5 -- DAC : PA4 -- PWM_2_CH1 : PA5 (might conflict with SPI1) - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l073rz`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L073RZ board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L073RZ ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l073rz - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l073rz - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L073RZ website: - https://www.st.com/en/evaluation-tools/nucleo-l073rz.html - -.. _STM32L0x3 reference manual: - https://www.st.com/resource/en/reference_manual/dm00095744.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig b/boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig deleted file mode 100644 index 06c6cdfe5daff5..00000000000000 --- a/boards/arm/nucleo_l073rz/nucleo_l073rz_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L073XX=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l152re/Kconfig.board b/boards/arm/nucleo_l152re/Kconfig.board deleted file mode 100644 index c87af1608017a3..00000000000000 --- a/boards/arm/nucleo_l152re/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2019 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_NUCLEO_L152RE - bool "NUCLEO-64 L152RE Development Board" - depends on SOC_STM32L152XE diff --git a/boards/arm/nucleo_l152re/Kconfig.defconfig b/boards/arm/nucleo_l152re/Kconfig.defconfig deleted file mode 100644 index 70a209468fc816..00000000000000 --- a/boards/arm/nucleo_l152re/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2019 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_NUCLEO_L152RE - -config BOARD - default "nucleo_l152re" - -endif # BOARD_NUCLEO_L152RE diff --git a/boards/arm/nucleo_l152re/board.cmake b/boards/arm/nucleo_l152re/board.cmake deleted file mode 100644 index cbeaea2e4564b5..00000000000000 --- a/boards/arm/nucleo_l152re/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/nucleo_l152re/doc/index.rst b/boards/arm/nucleo_l152re/doc/index.rst deleted file mode 100644 index 020beb6583f4e0..00000000000000 --- a/boards/arm/nucleo_l152re/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _nucleo_l152re_board: - -ST Nucleo L152RE -################ - -Overview -******** -The STM32 Nucleo-64 development board with STM32L152RE MCU, supports Arduino™ and ST morpho connectivity. - -The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, -and build prototypes with the STM32 microcontroller, choosing from the various -combinations of performance, power consumption and features. - -The Arduino Uno V3 connectivity support and the ST morpho headers allow easy functionality -expansion of the STM32 Nucleo open development platform with a wide choice of -specialized shields. - -The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. - -The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together -with various packaged software examples. - -.. image:: img/nucleo_l152re.jpg - :align: center - :alt: NUCLEO-L152RE - -More information about the board can be found at the `Nucleo L152RE website`_. - -Hardware -******** -Nucleo L152RE provides the following hardware components: - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: - - - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: - - - USB communication (LD1), user LED (LD2), power LED (LD3) - -- Two push-buttons: B1 (USER/blue) and B2 (RESET/black) -- USB re-enumeration capability. Three different interfaces supported on USB: - - - Virtual COM port - - Mass storage - - Debug port - -More information about STM32L152RE can be found here: - -- `STM32L152 reference manual`_ -- `STM32L152 data sheet`_ - -Supported Features -================== - -The Zephyr nucleo_l152re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| EEPROM | on-chip | eeprom | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l152re/nucleo_l152re_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/nucleo_l152re_connectors.jpg - :align: center - :alt: Nucleo L152RE connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- B1 (USER/blue) : PC13 -- LD1 : PA5 -- DAC : PA4 -- PWM_3_CH1 : PA6 - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``nucleo_l152re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L152RE board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo L152RE ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_l152re - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l152re - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _Nucleo L152RE website: - https://www.st.com/en/evaluation-tools/nucleo-l152re.html - -.. _STM32L152 reference manual: - https://www.st.com/resource/en/reference_manual/cd00240193.pdf - -.. _STM32L152 data sheet: - https://www.st.com/resource/en/datasheet/stm32l152re.pdf - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l412rb_p/Kconfig.board b/boards/arm/nucleo_l412rb_p/Kconfig.board deleted file mode 100644 index b81257b7eb7d11..00000000000000 --- a/boards/arm/nucleo_l412rb_p/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L412RB Nucleo board configuration - -# Copyright (c) 2021 Guðni Már Gilbert -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L412RB_P - bool "Nucleo L412RB-P Development Board" - depends on SOC_STM32L412XX diff --git a/boards/arm/nucleo_l412rb_p/Kconfig.defconfig b/boards/arm/nucleo_l412rb_p/Kconfig.defconfig deleted file mode 100644 index 210607bd31d80b..00000000000000 --- a/boards/arm/nucleo_l412rb_p/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L412RB Nucleo board configuration - -# Copyright (c) 2021 Guðni Már Gilbert -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L412RB_P - -config BOARD - default "nucleo_l412rb_p" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L412RB_P diff --git a/boards/arm/nucleo_l412rb_p/doc/index.rst b/boards/arm/nucleo_l412rb_p/doc/index.rst deleted file mode 100644 index 3485d01cba1d6f..00000000000000 --- a/boards/arm/nucleo_l412rb_p/doc/index.rst +++ /dev/null @@ -1,269 +0,0 @@ -.. _nucleo_l412rb_p_board: - -ST Nucleo L412RB-P -################## - -Overview -******** - -The Nucleo L412RB board features an ARM Cortex-M4 based STM32L412RB MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L412RB board: - -- STM32 microcontroller in LQFP64 package -- 1 user LED shared with ARDUINO |reg| -- 1 user and 1 reset push-buttons -- 32.768 kHz crystal oscillator -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port and debug port -- Flexible power-supply options: ST-LINK, USB VBUS, or external sources - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Board specific features - - - External SMPS to generate Vcore logic supply - - 24 MHz HSE - - Board connectors: - - - External SMPS experimentation dedicated connector - - Micro-AB or Mini-AB USB connector for the ST-LINK - - MIPI® debug connector - - - Arm® Mbed Enabled |trade| compliant - -.. image:: img/nucleo_l412rb_p.jpg - :align: center - :alt: Nucleo L412RB - -More information about the board can be found at the `Nucleo L412RB-P website`_. - -Hardware -******** - -Nucleo L412RB-P provides the following hardware components: - -- STM32L412RBT6 in LQFP64 package -- Ultra-low-power with FlexPowerControl - - - 1.71 V to 3.6 V power supply - - -40 °C to 85/125 °C temperature range - - 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers - - 16 nA Shutdown mode (4 wakeup pins) - - 32 nA Standby mode (4 wakeup pins) - - 245 nA Standby mode with RTC - - 0.7 |micro| A Stop 2 mode, 0.95 |micro| A with RTC - - 79 |micro| A/MHz run mode (LDO Mode) - - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode) - - Batch acquisition mode (BAM) - - 4 |micro| s wakeup from Stop mode - - Brown out reset (BOR) - - Interconnect matrix - -- Core: Arm |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator |trade| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions -- Performance benchmark - - - 1.25 DMIPS/MHz (Drystone 2.1) - - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz) - -- Energy benchmark - - - 442 ULPMark-CP® - - 165 ULPMark-PP® - -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0.25 % accuracy) - - Internal 48 MHz with clock recovery - - PLL for system clock - -- Up to 52 fast I/Os, most 5 V-tolerant -- RTC with HW calendar, alarms and calibration -- Up to 12 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 10x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 2x 16-bit general purpose - - 1x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Memories - - - 128 KB single bank Flash, proprietary code readout protection - - 40 KB of SRAM including 8 KB with hardware parity check - - Quad SPI memory interface with XIP capability - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 |micro| A/Msps - - 2x operational amplifiers with built-in PGA - - 1x ultra-low-power comparator - - Accurate 2.5 V or 2.048 V reference voltage buffered output - -- 12x communication interfaces - - USB 2.0 full-speed crystal less solution with LPM and BCD - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 3x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART (Stop 2 wake-up) - - 2x SPIs (and 1x Quad SPI) - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- All packages are ECOPACK2 compliant - -Note: the current board revision is C. (MB1319C) - -More information about STM32L412RB can be found here: - -- `STM32L412RB on www.st.com`_ -- `STM32L412 reference manual`_ - -Supported Features -================== - -The Zephyr ``nucleo_l412rb_p`` board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig`` - - -Connections and IOs -=================== - -Nucleo L412RB-P Board has 5 GPIO controllers (Ports A, B, C, D and H). These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l412rb_p_pinout.jpg - :align: center - :alt: Nucleo L412RB-P - -For more details please refer to `ST Nucleo L412RB-P User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- LPUART1 TX/RX : PA2/PA3 -- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) -- SPI2 CS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) -- UART1 TX/RX : PA9/PA10 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD4 : PB13 - -Note: SPI2 CS pin (PB12) is not located on the Arduino connector. - -System Clock ------------- - -Nucleo L412RB-P System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L412RB-P board has 3 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned to LPUART1. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l412rb_p`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L412RB-P board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L412RB-P ------------------------------------------- - -Connect the Nucleo L412RB-P to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l412rb_p - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_l412rb_p - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l412rb_p - :maybe-skip-config: - :goals: debug - -.. _Nucleo L412RB-P website: - https://www.st.com/en/evaluation-tools/nucleo-l412rb-p.html - -.. _ST Nucleo L412RB-P User Manual: - https://www.st.com/resource/en/user_manual/dm00387966-stm32-nucleo-64-p-boards-stmicroelectronics.pdf - -.. _STM32L412RB on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l412rb.html - -.. _STM32L412 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940-stm32l41xxx42xxx43xxx44xxx45xxx46xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l432kc/Kconfig.board b/boards/arm/nucleo_l432kc/Kconfig.board deleted file mode 100644 index 5340455df002ad..00000000000000 --- a/boards/arm/nucleo_l432kc/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32L432KC Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L432KC - bool "Nucleo L432KC Development Board" - depends on SOC_STM32L432XX diff --git a/boards/arm/nucleo_l432kc/Kconfig.defconfig b/boards/arm/nucleo_l432kc/Kconfig.defconfig deleted file mode 100644 index d76ef2633af2c3..00000000000000 --- a/boards/arm/nucleo_l432kc/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32L432KC Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L432KC - -config BOARD - default "nucleo_l432kc" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L432KC diff --git a/boards/arm/nucleo_l432kc/doc/index.rst b/boards/arm/nucleo_l432kc/doc/index.rst deleted file mode 100644 index b054c472f22603..00000000000000 --- a/boards/arm/nucleo_l432kc/doc/index.rst +++ /dev/null @@ -1,229 +0,0 @@ -.. _nucleo_l432kc_board: - -ST Nucleo L432KC -################ - -Overview -******** - -The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L432KC board: - -- STM32 microcontroller in UFQFPN32 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD2), user LED (LD3) -- One push-button: RESET - -.. image:: img/nucleo_l432kc.jpg - :align: center - :alt: Nucleo L432KC - -More information about the board can be found at the `Nucleo L432KC website`_. - -Hardware -******** - -The STM32L432KC SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 2x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 26 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 256 KB single bank Flash, proprietary code readout protection - - Up to 64 KB of SRAM including 16 KB with hardware parity check - - Quad SPI memory interface - -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 1x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 13x communication interfaces - - - USB OTG 2.0 full-speed crystal less solution with LPM and BCD - - 1x SAIs (serial audio interface) - - 2x I2C FM+(1 Mbit/s), SMBus/PMBus - - 3x USARTs (ISO 7816, LIN, IrDA, modem) - - 2x SPIs (3x SPIs with the Quad SPI) - - CAN (2.0B Active) - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L432KC can be found here: - -- `STM32L432KC on www.st.com`_ -- `STM32L432 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l432kc board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig`` - - -Connections and IOs -=================== - -Nucleo L432KC Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l432kc_arduino_nano.jpg - :align: center - :alt: Nucleo L432KC Arduino connectors - -For more details please refer to `STM32 Nucleo-32 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- LD3 : PB3 - -System Clock ------------- - -Nucleo L432KC System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L432KC board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l432kc`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L432KC ----------------------------------------- - -Connect the Nucleo L432KC to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l432kc - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l432kc - :maybe-skip-config: - :goals: debug - -.. _Nucleo L432KC website: - https://www.st.com/en/evaluation-tools/nucleo-l432kc.html - -.. _STM32 Nucleo-32 board User Manual: - https://www.st.com/resource/en/user_manual/dm00231744.pdf - -.. _STM32L432KC on www.st.com: - https://www.st.com/en/microcontrollers/stm32l432kc.html - -.. _STM32L432 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l433rc_p/Kconfig.board b/boards/arm/nucleo_l433rc_p/Kconfig.board deleted file mode 100644 index 3a53d91bc258a2..00000000000000 --- a/boards/arm/nucleo_l433rc_p/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L433RC Nucleo board configuration - -# Copyright (c) 2021 Matija Tudan -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L433RC_P - bool "Nucleo L433RC-P Development Board" - depends on SOC_STM32L433XX diff --git a/boards/arm/nucleo_l433rc_p/Kconfig.defconfig b/boards/arm/nucleo_l433rc_p/Kconfig.defconfig deleted file mode 100644 index 62136895033403..00000000000000 --- a/boards/arm/nucleo_l433rc_p/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L433RC Nucleo board configuration - -# Copyright (c) 2021 Matija Tudan -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L433RC_P - -config BOARD - default "nucleo_l433rc_p" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L433RC_P diff --git a/boards/arm/nucleo_l433rc_p/doc/index.rst b/boards/arm/nucleo_l433rc_p/doc/index.rst deleted file mode 100644 index 6e86a44cee0ccf..00000000000000 --- a/boards/arm/nucleo_l433rc_p/doc/index.rst +++ /dev/null @@ -1,234 +0,0 @@ -.. _nucleo_l433rc_board: - -ST Nucleo L433RC -################ - -Overview -******** - -The Nucleo L433RC board features an ARM Cortex-M4 based STM32L433RC MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L433RC board: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD4) -- One push-button: RESET - -.. image:: img/nucleo_l433rc_p.jpg - :align: center - :alt: Nucleo L433RC - -More information about the board can be found at the `Nucleo L433RC-P website`_. - -Hardware -******** - -The STM32L433RC SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 11x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 2x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 83 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 256 KB single bank Flash, proprietary code readout protection - - 64 KB of SRAM including 16 KB with hardware parity check - - Quad SPI memory interface - -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC output channels, low-power sample and hold - - 1x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 17x communication interfaces - - - USB 2.0 full-speed crystal less solution with LPM and BCD - - 1x SAI (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 4x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART (Stop 2 wake-up) - - 3x SPIs (and 1x Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L433RC can be found here: - -- `STM32L433RC on www.st.com`_ -- `STM32L432 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l433rc_p board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig`` - - -Connections and IOs -=================== - -Nucleo L433RC-P Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l433rc_p_pinout.jpg - :align: center - :alt: Nucleo L433RC-P - -For more details please refer to `ST Nucleo L433RC-P User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- LPUART_1_TX : PA2 -- LPUART_1_RX : PA3 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- LD4 : PB13 -- SPI_1: NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 -- SPI_2: NSS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) - -System Clock ------------- - -Nucleo L433RC-P System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L433RC-P board has 4 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned -to LPUART1. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l433rc_p`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L433RC-P board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L433RC-P ------------------------------------------- - -Connect the Nucleo L433RC-P to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ picocom /dev/ttyACM0 -b 115200 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l433rc_p - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! nucleo_l433rc_p - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l433rc_p - :maybe-skip-config: - :goals: debug - -.. _Nucleo L433RC-P website: - https://www.st.com/en/evaluation-tools/nucleo-l433rc-p.html - -.. _ST Nucleo L433RC-P User Manual: - https://www.st.com/resource/en/user_manual/dm00387966.pdf - -.. _STM32L433RC on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l433rc.html - -.. _STM32L432 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l452re/Kconfig.board b/boards/arm/nucleo_l452re/Kconfig.board deleted file mode 100644 index ba69b24e6e6ed2..00000000000000 --- a/boards/arm/nucleo_l452re/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# STM32L452RE Nucleo board configuration -# -# Copyright (c) 2019 Libre Solar Technologies GmbH -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L452RE - bool "Nucleo L452RE Development Board" - depends on SOC_STM32L452XX - -config BOARD_NUCLEO_L452RE_P - bool "Nucleo L452RE-P Development Board" - depends on SOC_STM32L452XX diff --git a/boards/arm/nucleo_l452re/Kconfig.defconfig b/boards/arm/nucleo_l452re/Kconfig.defconfig deleted file mode 100644 index 3da8b18ec74239..00000000000000 --- a/boards/arm/nucleo_l452re/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# STM32L452RE Nucleo board configuration -# -# Copyright (c) 2019 Libre Solar Technologies GmbH -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L452RE || BOARD_NUCLEO_L452RE_P - -config BOARD - default "nucleo_l452re" if BOARD_NUCLEO_L452RE - default "nucleo_l452re_p" if BOARD_NUCLEO_L452RE_P - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L452RE || BOARD_NUCLEO_L452RE_P diff --git a/boards/arm/nucleo_l452re/doc/index.rst b/boards/arm/nucleo_l452re/doc/index.rst deleted file mode 100644 index 4b68d032be1781..00000000000000 --- a/boards/arm/nucleo_l452re/doc/index.rst +++ /dev/null @@ -1,256 +0,0 @@ -.. _nucleo_l452re_board: - -ST Nucleo L452RE -################ - -Overview -******** - -The Nucleo L452RE(-P) boards feature an ARM Cortex-M4 based STM32L452RE MCU -with a wide range of connectivity support and configurations. There are two variants: - -- ST Nucleo L452RE -- ST Nucleo L452RE-P - -Here some highlights of these boards: - -- STM32 microcontroller in LQFP64 package -- Arduino Uno V3 connectivity -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- One push-button: RESET - -.. image:: img/nucleo_l452re_p.jpg - :align: center - :alt: Nucleo L452RE-P - -The main difference between the ST Nucleo L452RE and the L452RE-P (note the missing -"-P" at the end) lays in the External Switched Mode Power Supply (SMPS) included in -the P series. - -More information about the boards can be found at the `Nucleo L452RE website`_ and -the `Nucleo L452RE-P website`_. - -Hardware -******** - -The STM32L452RE SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 2 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 12x timers: - - - 1x 16-bit advanced motor-control - - 1x 32-bit and 3x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 26 fast I/Os, most 5 V-tolerant -- Memories - - - Up to 512 KB single bank Flash, proprietary code readout protection - - 160 KB of SRAM including 32 KB with hardware parity check - - Quad SPI memory interface - -- Rich analog peripherals (independent supply) - - - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 1x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 17x communication interfaces - - USB 2.0 full-speed crystal less solution with LPM and BCD - - 1x SAI (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 3x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x UART (LIN, IrDA, modem) - - 1x LPUART (Stop 2 wake-up) - - 3x SPIs (and 1x Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L452RE can be found here: - -- `STM32L452RE on www.st.com`_ -- `STM32L452 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l452re board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l452re/nucleo_l452re_defconfig`` - - -Connections and IOs -=================== - -Nucleo L452RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l452re_pinout.jpg - :align: center - :alt: Nucleo L452RE Pinout - -.. image:: img/nucleo_l452re_p_pinout.jpg - :align: center - :alt: Nucleo L452RE-P Pinout - -For more details please refer to `ST Nucleo L452RE User Manual`_ or -`ST Nucleo L452RE-P User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- SPI_NSS : PB6 -- SPI_SCK : PA5 -- SPI_MISO : PA6 -- SPI_MOSI : PA7 -- CAN_TX : PA11 -- CAN_RX : PA12 -- LD2 : PA5 - -System Clock ------------- - -Nucleo L452RE System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L452RE board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l452re`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L452RE ----------------------------------------- - -Connect the Nucleo L452RE to your host computer using the USB port, -then run a serial host program to connect with your Nucleo board. - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Now build and flash an application. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l452re - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - $ Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l452re - :maybe-skip-config: - :goals: debug - -.. _Nucleo L452RE website: - https://www.st.com/en/evaluation-tools/nucleo-l452re.html - -.. _Nucleo L452RE-P website: - https://www.st.com/en/evaluation-tools/nucleo-l452re-p.html - -.. _ST Nucleo L452RE User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _ST Nucleo L452RE-P User Manual: - https://www.st.com/resource/en/user_manual/dm00387966.pdf - -.. _STM32L452RE on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l452re.html - -.. _STM32L452 reference manual: - https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_p.yaml b/boards/arm/nucleo_l452re/nucleo_l452re_p.yaml deleted file mode 100644 index 7ca93a9c9bc43e..00000000000000 --- a/boards/arm/nucleo_l452re/nucleo_l452re_p.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: nucleo_l452re_p -name: ST Nucleo L452RE-P -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 160 -flash: 512 -supported: - - nvs - - pwm - - can - - counter - - spi -vendor: st diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_p_defconfig b/boards/arm/nucleo_l452re/nucleo_l452re_p_defconfig deleted file mode 100644 index 14b7ffdd20928b..00000000000000 --- a/boards/arm/nucleo_l452re/nucleo_l452re_p_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L452XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l476rg/Kconfig.board b/boards/arm/nucleo_l476rg/Kconfig.board deleted file mode 100644 index b83025518a28a2..00000000000000 --- a/boards/arm/nucleo_l476rg/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# STM32L476RG Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L476RG - bool "Nucleo L476RG Development Board" - depends on SOC_STM32L476XX diff --git a/boards/arm/nucleo_l476rg/Kconfig.defconfig b/boards/arm/nucleo_l476rg/Kconfig.defconfig deleted file mode 100644 index cbbef016161a43..00000000000000 --- a/boards/arm/nucleo_l476rg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32L476RG Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L476RG - -config BOARD - default "nucleo_l476rg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L476RG diff --git a/boards/arm/nucleo_l476rg/doc/index.rst b/boards/arm/nucleo_l476rg/doc/index.rst deleted file mode 100644 index 10dff333643841..00000000000000 --- a/boards/arm/nucleo_l476rg/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _nucleo_l476rg_board: - -ST Nucleo L476RG -################ - -Overview -******** - -The Nucleo L476RG board features an ARM Cortex-M4 based STM32L476RG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L476RG board: - - -- STM32 microcontroller in QFP64 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_l476rg.jpg - :align: center - :alt: Nucleo L476RG - -More information about the board can be found at the `Nucleo L476RG website`_. - -Hardware -******** - -The STM32L476RG SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 18x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L476RG can be found here: - -- `STM32L476RG on www.st.com`_ -- `STM32L476 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l476rg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig`` - - -Connections and IOs -=================== - -Nucleo L476RG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo_l476rg_arduino.jpg - :align: center - :alt: Nucleo L476RG Arduino connectors -.. image:: img/nucleo_l476rg_morpho.jpg - :align: center - :alt: Nucleo L476RG Morpho connectors - -For more details please refer to `STM32 Nucleo-64 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1 TX/RX : PA9/PA10 -- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) -- UART_3 TX/RX : PB10/PB11 -- I2C_1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C_3 SCL/SDA : PC0/PC1 -- SPI_1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) -- SPI_2 CS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 -- SPI_3 CS/SCK/MISO/MOSI : PA15/PC10/PC11/PC12 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD2 : PA5 - -System Clock ------------- - -Nucleo L476RG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L476RG board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l476rg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.2. - -Flashing an application to Nucleo L476RG ----------------------------------------- - -Connect the Nucleo L476RG to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l476rg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l476rg - :maybe-skip-config: - :goals: debug - -.. _Nucleo L476RG website: - https://www.st.com/en/evaluation-tools/nucleo-l476rg.html - -.. _STM32 Nucleo-64 board User Manual: - https://www.st.com/resource/en/user_manual/dm00105823.pdf - -.. _STM32L476RG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l476rg.html - -.. _STM32L476 reference manual: - https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/nucleo_l496zg/Kconfig.board b/boards/arm/nucleo_l496zg/Kconfig.board deleted file mode 100644 index 908385c5f53ba9..00000000000000 --- a/boards/arm/nucleo_l496zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L496ZG Nucleo board configuration - -# Copyright (c) 2018-2019 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L496ZG - bool "Nucleo L496ZG Development Board" - depends on SOC_STM32L496XX diff --git a/boards/arm/nucleo_l496zg/Kconfig.defconfig b/boards/arm/nucleo_l496zg/Kconfig.defconfig deleted file mode 100644 index 34fcc96575a220..00000000000000 --- a/boards/arm/nucleo_l496zg/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L496ZG Nucleo board configuration - -# Copyright (c) 2018 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L496ZG - -config BOARD - default "nucleo_l496zg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L496ZG diff --git a/boards/arm/nucleo_l496zg/doc/index.rst b/boards/arm/nucleo_l496zg/doc/index.rst deleted file mode 100644 index 49d011b8846751..00000000000000 --- a/boards/arm/nucleo_l496zg/doc/index.rst +++ /dev/null @@ -1,244 +0,0 @@ -.. _nucleo_l496zg_board: - -ST Nucleo L496ZG -################ - -Overview -******** - -The Nucleo L496ZG board features an ARM Cortex-M4 based STM32L496ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L476ZG board: - - -- STM32 microcontroller in QFP144 package -- USB OTG FS with Micro-AB connector -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB - power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) -- 2 push buttons: USER and RESET - -.. image:: img/nucleo_l496zg.jpg - :align: center - :alt: Nucleo L496ZG - -More information about the board can be found at the `Nucleo L496ZG website`_. - -Hardware -******** - -The STM32L496ZG SoC provides the following hardware capabilities: - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 320 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (4x SPIs with the Quad SPI) - - 2x CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L496ZG can be found here: - -- `STM32L496ZG on www.st.com`_ -- `STM32L496 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l496zg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | System Window Watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo L496ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PD5/PD6 -- UART_3 TX/RX : PD8/PD9 -- LPUART_1 TX/RX : PG7/PG8 -- PWM_1_CH1: PE9 -- PWM_1_CH2: PE11 -- PWM_1_CH3: PE13 -- PWM_2_CH1: PA0 -- I2C_1_SCL: PB8 -- I2C_1_SDA: PB7 -- SPI_1_NSS: PD14 -- SPI_1_SCK: PA5 -- SPI_1_MISO: PA6 -- SPI_1_MOSI: PA7 -- USER_PB : PC13 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PB14 - -System Clock ------------- - -Nucleo L496ZG System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -Nucleo L496ZG board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l496zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the openocd version -included in the Zephyr SDK since v0.9.5. - -Flashing an application to Nucleo L496ZG ----------------------------------------- - -Connect the Nucleo L496ZG to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyUSB0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l496zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l496zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo L496ZG website: - https://www.st.com/en/evaluation-tools/nucleo-l496zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00368330.pdf - -.. _STM32L496ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l496zg.html - -.. _STM32L496 reference manual: - https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l4a6zg/Kconfig.board b/boards/arm/nucleo_l4a6zg/Kconfig.board deleted file mode 100644 index ad15c2540fd7eb..00000000000000 --- a/boards/arm/nucleo_l4a6zg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L4A6ZG Nucleo board configuration - -# Copyright (c) 2022 Tomislav Milkovic -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L4A6ZG - bool "Nucleo L4A6ZG Development Board" - depends on SOC_STM32L4A6XX diff --git a/boards/arm/nucleo_l4a6zg/Kconfig.defconfig b/boards/arm/nucleo_l4a6zg/Kconfig.defconfig deleted file mode 100644 index c08656612952be..00000000000000 --- a/boards/arm/nucleo_l4a6zg/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32L4A6ZG Nucleo board configuration - -# Copyright (c) 2022 Tomislav Milkovic -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L4A6ZG - -config BOARD - default "nucleo_l4a6zg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_L4A6ZG diff --git a/boards/arm/nucleo_l4a6zg/doc/index.rst b/boards/arm/nucleo_l4a6zg/doc/index.rst deleted file mode 100644 index 7e61d9f8907679..00000000000000 --- a/boards/arm/nucleo_l4a6zg/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _nucleo_l4a6zg_board: - -ST Nucleo L4A6ZG -################ - -Overview -******** - -The Nucleo L4A6ZG board features an ARM Cortex-M4 based STM32L4A6ZG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L4A6ZG board: - - -- STM32 microcontroller in QFP144 package -- USB OTG FS with Micro-AB connector -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB - power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) -- 2 push buttons: USER and RESET - -.. image:: ../../nucleo_l496zg/doc/img/nucleo_l496zg.jpg - :align: center - :alt: Nucleo L4A6ZG - -More information about the board can be found at the `Nucleo L4A6ZG website`_. - -Hardware -******** - -The STM32L4A6ZG SoC provides the following hardware capabilities: - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 320 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (4x SPIs with the Quad SPI) - - 2x CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- AES and HASH hardware accelerators -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L4A6ZG can be found here: - -- `STM32L4A6ZG on www.st.com`_ -- `STM32L4A6 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l4a6zg board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | System Window Watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig`` - - -Connections and IOs -=================== - -Nucleo L4A6ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- LPUART_1 TX/RX : PG7/PG8 (ST-Link Virtual COM Port) -- UART_3 TX/RX : PD8/PD9 (Arduino Serial) -- I2C_1 SCL/SDA : PB8/PB7 (Arduino I2C) -- SPI_1 SCK/MISO/MOSI/NSS : PA5/PA6/PA7/PD14 (Arduino SPI) -- USER_PB : PC13 -- PWM_15_CH1 : PB14 (Red LED) -- LD1 : PC7 (Green LED) -- LD2 : PB7 (Blue LED) -- LD3 : PB14 (Red LED) - -System Clock ------------- - -Nucleo L4A6ZG system clock could be driven by internal or external oscillator, -as well as main PLL clock. By default, system clock is driven by PLL at 80MHz, which is -driven by 16MHz high speed internal oscillator (HSI). High speed external oscillator -(HSE) is not soldered on the board, so it cannot be used to drive the PLL. - -Serial Port ------------ - -Nucleo L4A6ZG board has 5 UARTs. The Zephyr console output is assigned to LPUART1, -which is connected to the onboard ST-LINK/V2-1. Virtual COM port interface. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``nucleo_l4a6zg`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Nucleo L4A6ZG board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is supported by the OpenOCD version -included in the Zephyr SDK since v0.9.5. - -Flashing an application to Nucleo L4A6ZG ----------------------------------------- - -Connect the Nucleo L4A6ZG to your host computer using the ST-LINK USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyUSB0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l4a6zg - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! nucleo_l4a6zg - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l4a6zg - :maybe-skip-config: - :goals: debug - -.. _Nucleo L4A6ZG website: - https://www.st.com/en/evaluation-tools/nucleo-l4a6zg.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00368330.pdf - -.. _STM32L4A6ZG on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l4a6zg.html - -.. _STM32L4A6 reference manual: - https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l4r5zi/Kconfig.board b/boards/arm/nucleo_l4r5zi/Kconfig.board deleted file mode 100644 index aebd712289bfa9..00000000000000 --- a/boards/arm/nucleo_l4r5zi/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L4R5ZI Nucleo board configuration - -# Copyright (c) 2018 Pushpal Sidhu -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L4R5ZI - bool "Nucleo L4R5ZI Development Board" - depends on SOC_STM32L4R5XX diff --git a/boards/arm/nucleo_l4r5zi/Kconfig.defconfig b/boards/arm/nucleo_l4r5zi/Kconfig.defconfig deleted file mode 100644 index 5b3db7604cbd99..00000000000000 --- a/boards/arm/nucleo_l4r5zi/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# STM32L4R5ZI Nucleo board configuration - -# Copyright (c) 2018 Pushpal Sidhu -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L4R5ZI - -config BOARD - default "nucleo_l4r5zi" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_EEM - default y - -endif # NETWORKING - -endif # BOARD_NUCLEO_L4R5ZI diff --git a/boards/arm/nucleo_l4r5zi/doc/index.rst b/boards/arm/nucleo_l4r5zi/doc/index.rst deleted file mode 100644 index b132403ce2adbd..00000000000000 --- a/boards/arm/nucleo_l4r5zi/doc/index.rst +++ /dev/null @@ -1,275 +0,0 @@ -.. _nucleo_l4r5zi_board: - -ST Nucleo L4R5ZI -################ - -Overview -******** - -The Nucleo L4R5ZI board features an ARM Cortex-M4 based STM32L4R5ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the Nucleo L4R5ZI board: - - -- STM32 microcontroller in LQFP144 package -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Three User LEDs: LD1 (Green), LD2 (Blue), LD3 (Red) -- Two push-buttons: USER and RESET - -.. image:: img/nucleo_l4r5zi.jpg - :align: center - :alt: Nucleo L4R5ZI - -More information about the board can be found at the `Nucleo L4R5ZI website`_. - -Hardware -******** - -The STM32L4R5ZI SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode - and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive - real-time accelerator (ART Accelerator) allowing 0-wait-state - execution from Flash memory, frequency up to 120 MHz, MPU, 150 - DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - Internal 48 MHz with clock recovery - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- Up to 24 capacitive sensing channels: support touchkey, linear and - rotary touch sensors -- Advanced graphics features - - - Chrom-ART Accelerator™ (DMA2D) for enhanced graphic content creation - - Chrom-GRC™ (GFXMMU) allowing up to 20% of graphic resources optimization - - MIPI® DSI Host controller with two DSI lanes running at up to 500 - Mbits/s each - - LCD-TFT controller - -- 16x timers - - - 2 x 16-bit advanced motor-control - - 2 x 32-bit and 5 x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with - independent supply down to 1.08 V -- Memories - - - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection - - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check - - External memory interface for static memories supporting SRAM, - PSRAM, NOR, NAND and FRAM memories - - 2 x OctoSPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with the dual OctoSPI) - - CAN (2.0B Active) and SDMMC - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color) -- Development support: serial wire debug (SWD), JTAG, Embedded Trace - Macrocell (ETM) - -More information about STM32L4R5ZI can be found here: - -- `STM32L4R5ZI on www.st.com`_ -- `STM32L4R5 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_l4r5zi board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig`` - - -Connections and IOs -=================== - -Nucleo L4R5ZI Board has 8 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -Available pins: ---------------- -.. image:: img/nucleo144_layout.jpg - :align: center - :alt: Nucleo L4R5ZI Arduino connectors - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- UART_3_TX : PB10 -- UART_3_RX : PB11 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- SPI_1_NSS : PD14 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PB12 -- SPI_2_SCK : PB13 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PB12 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PB14 -- USB DM : PA11 -- USB DP : PA12 -- ADC1 : PC0 - -System Clock ------------- - -Nucleo L4R5ZI System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default, the System clock is -driven by the PLL clock at 80MHz, driven by a 16MHz high speed -internal oscillator. The clock can be boosted to 120MHz if boost mode -is selected. - -Serial Port ------------ - -Nucleo L4R5ZI board has 5 U(S)ARTs. The Zephyr console output is -assigned to UART2. Default settings are 115200 8N1. - -Network interface ------------------ - -Ethernet over USB is configured as the default network interface (EEM) - -Programming and Debugging -************************* - -The NUCLEO-L4R5ZI board includes a ST-LINK/V2 embedded debug tool interface. - -The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, -so its installation is required to be able to flash the board. - -Alternatively, openocd (provided in Zephyr SDK) or JLink can also be used to -flash the board using the ``--runner`` (or ``-r``) option: - -.. code-block:: console - - $ west flash --runner openocd - $ west flash --runner jlink - -Connect the Nucleo L4R5ZI to your host computer using the USB port. -Then build and flash an application. - -Here is an example for the :ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_l4r5zi - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -.. _Nucleo L4R5ZI website: - https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00368330.pdf - -.. _STM32L4R5ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32l4r5zi.html - -.. _STM32L4R5 reference manual: - https://www.st.com/resource/en/reference_manual/DM00310109.pdf - -.. _STM32 ST-LINK utility: - https://www.st.com/content/st_com/en/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-programmers/stsw-link004.html - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_l552ze_q/Kconfig.board b/boards/arm/nucleo_l552ze_q/Kconfig.board deleted file mode 100644 index a79e9274d0bf83..00000000000000 --- a/boards/arm/nucleo_l552ze_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L552ZE Q Nucleo board configuration - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_L552ZE_Q - bool "Nucleo L552ZE Q Development Board" - depends on SOC_STM32L552XX diff --git a/boards/arm/nucleo_l552ze_q/Kconfig.defconfig b/boards/arm/nucleo_l552ze_q/Kconfig.defconfig deleted file mode 100644 index 3d832d3390446c..00000000000000 --- a/boards/arm/nucleo_l552ze_q/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# STM32L552ZE Q Nucleo board configuration - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_L552ZE_Q - -config BOARD - default "nucleo_l552ze_q" - -if TRUSTED_EXECUTION_NONSECURE - -# Get flash configuration for NS image from dts flash partition -config USE_DT_CODE_PARTITION - default y - -endif # TRUSTED_EXECUTION_NONSECURE - -endif # BOARD_NUCLEO_L552ZE_Q diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.yaml b/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.yaml deleted file mode 100644 index 1eb62f85b96164..00000000000000 --- a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: nucleo_l552ze_q_ns -name: ST Nucleo L552ZE Q non secure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio - - dac -ram: 192 -flash: 328 -vendor: st diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig b/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig deleted file mode 100644 index 93f551efc34b6c..00000000000000 --- a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L552XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable clock -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_u575zi_q/Kconfig.board b/boards/arm/nucleo_u575zi_q/Kconfig.board deleted file mode 100644 index 1f08c09447e41d..00000000000000 --- a/boards/arm/nucleo_u575zi_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32U575ZI Q Nucleo board configuration - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_U575ZI_Q - bool "Nucleo U575ZI Q Development Board" - depends on SOC_STM32U575XX diff --git a/boards/arm/nucleo_u575zi_q/Kconfig.defconfig b/boards/arm/nucleo_u575zi_q/Kconfig.defconfig deleted file mode 100644 index 901d86a255155f..00000000000000 --- a/boards/arm/nucleo_u575zi_q/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32U575ZI Q Nucleo board configuration - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_U575ZI_Q - -config BOARD - default "nucleo_u575zi_q" - -endif # BOARD_NUCLEO_U575ZI_Q diff --git a/boards/arm/nucleo_u575zi_q/doc/index.rst b/boards/arm/nucleo_u575zi_q/doc/index.rst deleted file mode 100644 index bbb547130d86a5..00000000000000 --- a/boards/arm/nucleo_u575zi_q/doc/index.rst +++ /dev/null @@ -1,343 +0,0 @@ -.. _nucleo_u575zi_q_board: - -ST Nucleo U575ZI Q -################## - -Overview -******** - -The Nucleo U575ZI Q board, featuring an ARM Cortex-M33 based STM32U575ZI MCU, -provides an affordable and flexible way for users to try out new concepts and -build prototypes by choosing from the various combinations of performance and -power consumption features. Here are some highlights of the Nucleo U575ZI Q -board: - - -- STM32U575ZI microcontroller in LQFP144 package -- Internal SMPS to generate V core logic supply -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V3E debugger/programmer -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - ST-Link V3E - -- Three users LEDs -- Two push-buttons: USER and RESET -- USB Type-C |trade| Sink device FS - -Hardware -******** - -The STM32U575xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) - -- Security - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) and password protected debug - - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure Firmware Update support with TF-M - - HASH hardware accelerator - - Active tampers - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - - Internal 48 MHz with clock recovery - -- Power management - - - Embedded regulator (LDO) - - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling - -- RTC with HW calendar and calibration -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 17 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5 x 16-bit general purpose - - 4x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- ART accelerator - - - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and - external memories: up to 160 MHz, MPU, 240 DMIPS and DSP - - 4-Kbyte data cache for external memories - -- Memories - - - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles - - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON - - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - 2 Octo-SPI memory interfaces - -- Rich analog peripherals (independent supply) - - - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling - - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 2 12-bit DAC, low-power sample and hold - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- Up to 22 communication interfaces - - - USB Type-C / USB power delivery controller - - USB OTG 2.0 full-speed controller - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) - - 1x FDCAN - - 2x SDMMC interface - - 16- and 4-channel DMA controllers, functional in Stop mode - - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with - sound-activity detection - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- True Random Number Generator (RNG) - -- Graphic features - - - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation - - 1 digital camera interface - -- Mathematical co-processor - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - -More information about STM32U575ZI can be found here: - -- `STM32U575ZI on www.st.com`_ -- `STM32U575 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_u575zi_q board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| CAN/CANFD | on-chip | canbus | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| BKP SRAM | on-chip | Backup SRAM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig`` - - -Connections and IOs -=================== - -Nucleo U575ZI Q Board has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - - -- CAN/CANFD_TX: PD1 -- CAN/CANFD_RX: PD0 -- DAC1_OUT1 : PA4 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- I2C_2_SCL : PF1 -- I2C_2_SDA : PF0 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PG2 -- LPUART_1_TX : PG7 -- LPUART_1_RX : PG8 -- SPI_1_NSS : PA4 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PC13 - -System Clock ------------- - -Nucleo U575ZI Q System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -160MHz, driven by 4MHz medium speed internal oscillator. - -Serial Port ------------ - -Nucleo U575ZI Q board has 6 U(S)ARTs. The Zephyr console output is assigned to -USART1. Default settings are 115200 8N1. - - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB50`` jumper on the back side of the board. - - -Programming and Debugging -************************* - -Nucleo U575ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash the board using various tools. - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. - -For pyocd additional target information needs to be installed. -This can be done by executing the following commands. - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32u5 - - -Flashing an application to Nucleo U575ZI Q ------------------------------------------- - -Connect the Nucleo U575ZI Q to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_u575zi_q - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -Default flasher for this board is openocd. It could be used in the usual way. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_u575zi_q - :goals: debug - -Building a secure/non-secure with Arm |reg| TrustZone |reg| -=========================================================== - -The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| -support. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``nucleo_u575zi_q_ns`` as build target. - -.. code-block:: bash - - $ west build -b nucleo_u575zi_q_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash - -Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts -(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` -(which is used for initialization) is available in the PATH. - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/dm00615305.pdf - -.. _STM32U575ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32u575zi.html - -.. _STM32U575 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STMicroelectronics customized version of OpenOCD: - https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_u5a5zj_q/Kconfig.board b/boards/arm/nucleo_u5a5zj_q/Kconfig.board deleted file mode 100644 index 2a1713e0b4fdf2..00000000000000 --- a/boards/arm/nucleo_u5a5zj_q/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32U5A5ZJ Q Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_U5A5ZJ_Q - bool "Nucleo U5A5ZJ Q Development Board" - depends on SOC_STM32U5A5XX diff --git a/boards/arm/nucleo_u5a5zj_q/Kconfig.defconfig b/boards/arm/nucleo_u5a5zj_q/Kconfig.defconfig deleted file mode 100644 index ab56632726488c..00000000000000 --- a/boards/arm/nucleo_u5a5zj_q/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32U5A5ZJ Q Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_U5A5ZJ_Q - -config BOARD - default "nucleo_u5a5zj_q" - -endif # BOARD_NUCLEO_U5A5ZJ_Q diff --git a/boards/arm/nucleo_u5a5zj_q/doc/index.rst b/boards/arm/nucleo_u5a5zj_q/doc/index.rst deleted file mode 100644 index f6e96c635171d5..00000000000000 --- a/boards/arm/nucleo_u5a5zj_q/doc/index.rst +++ /dev/null @@ -1,377 +0,0 @@ -.. _nucleo_u5a5zj_q_board: - -ST Nucleo U5A5ZJ Q -################## - -Overview -******** - -The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU, -provides an affordable and flexible way for users to try out new concepts and -build prototypes by choosing from the various combinations of performance and -power consumption features. Here are some highlights of the Nucleo U5A5ZJ Q -board: - - -- STM32U5A5ZJ microcontroller in LQFP144 package -- Internal SMPS to generate V core logic supply -- Two types of extension resources: - - - Arduino Uno V3 connectivity - - ST morpho extension pin headers for full access to all STM32 I/Os - -- On-board ST-LINK/V3E debugger/programmer -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - ST-Link V3E - -- Three users LEDs -- Two push-buttons: USER and RESET -- USB Type-C ™ Sink device FS - -Hardware -******** - -The STM32U5A5xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Includes ST state-of-the-art patented technology -- Ultra-low-power with FlexPowerControl: - - - 1.71 V to 3.6 V power supply - - -40 °C to +85/125 °C temperature range - - Low-power background autonomous mode (LPBAM): autonomous peripherals with - DMA, functional down to Stop 2 mode - - VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM - - 150 nA Shutdown mode (24 wake-up pins) - - 195 nA Standby mode (24 wake-up pins) - - 480 nA Standby mode with RTC - - 2 µA Stop 3 mode with 40-Kbyte SRAM - - 8.2 µA Stop 3 mode with 2.5-Mbyte SRAM - - 4.65 µA Stop 2 mode with 40-Kbyte SRAM - - 17.5 µA Stop 2 mode with 2.5-Mbyte SRAM - - 18.5 µA/MHz Run mode at 3.3 V - -- Core: - - - Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, - and FPU ART Accelerator - - 32-Kbyte ICACHE allowing 0-wait-state execution from flash and external - memories: frequency up to 160 MHz, 240 DMIPS - - 16-Kbyte DCACHE1 for external memories - -- Power management: - - - Embedded regulator (LDO) and SMPSstep-down converter supporting switch - on-the-fly and voltage scaling - -- Benchmarks: - - - 1.5 DMIPS/MHz (Drystone 2.1) - - 655 CoreMark® (4.09 CoreMark®/MHz) - - 369 ULPMark™-CP - - 89 ULPMark™-PP - - 47.2 ULPMark™-CM - - 120000 SecureMark™-TLS - -- Memories: - - - 4-Mbyte flash memory with ECC, 2 banks readwhile-write, including 512 Kbytes - with 100 kcycles - - With SRAM3 ECC off: 2514-Kbyte RAM including 66 Kbytes with ECC - - With SRAM3 ECC on: 2450-Kbyte RAMincluding 322 Kbytes with ECC - - External memory interface supporting SRAM,PSRAM, NOR, NAND, and FRAM memories - - 2 Octo-SPI memory interfaces - - 16-bit HSPI memory interface up to 160 MHz - -- Rich graphic features: - - - Neo-Chrom GPU (GPU2D) accelerating any angle rotation, scaling, and - perspective correct texture mapping - - 16-Kbyte DCACHE2 - - Chrom-ART Accelerator (DMA2D) for smoothmotion and transparency effects - - Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization - - MIPI® DSI host controller with two DSI lanes running at up to 500 Mbit/s each - - LCD-TFT controller (LTDC) - - Digital camera interface - -- General-purpose input/outputs: - - - Up to 156 fast I/Os with interrupt capability most 5V-tolerant and - up to 14 I/Os with independent supply down to 1.08 V - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC (± 1 %) - - Internal low-power 32 kHz RC (± 5 %) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one - autotrimmed by LSE (better than ± 0.25 % accuracy) - - Internal 48 MHz - - 5 PLLs for system clock, USB, audio, ADC, DSI - -- Security and cryptography: - - - SESIP3 and PSA Level 3 Certified Assurance Target - - Arm® TrustZone® and securable I/Os, memories, and peripherals - - Flexible life cycle scheme with RDP andpassword-protected debug - - Root of trust thanks to unique boot entry and secure hide-protection area (HDP) - - Secure firmware installation (SFI) thanks to embedded root secure services (RSS) - - Secure data storage with hardware unique key (HUK) - - Secure firmware upgrade support with TF-M - - 2 AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - True random number generator, NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte OTP (one-time programmable) - - Active tampers - -- Up to 17 timers, 2 watchdogs and RTC: - - - 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general - purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode), - 2 SysTick timers, and 2 watchdogs - - RTC with hardware calendar, alarms, and calibration - -- Up to 25 communication peripherals: - - - 1 USB Type-C®/USB power delivery controller - - 1 USB OTG high-speed with embedded PHY - - 2 SAIs (serial audio interface) - - 6 I2C FM+(1 Mbit/s), SMBus/PMBus™ - - 7 USARTs (ISO 7816, LIN, IrDA, modem) - - 3 SPIs (6x SPIs with OCTOSPI/HSPI) - - 1 CAN FD controller - - 2 SDMMC interfaces - - 1 multifunction digital filter (6 filters) + 1 audio digital filter - with sound-activity detection - - Parallel synchronous slave interface - -- Mathematical coprocessor: - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - -- Rich analog peripherals (independent supply): - - - 2 14-bit ADC 2.5-Msps with hardware oversampling - - 1 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 12-bit DAC (2 channels), low-power sample, and hold, autonomous in Stop 2 mode - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- ECOPACK2 compliant packages - -More information about STM32U5A5ZJ can be found here: - -- `STM32U5A5ZJ on www.st.com`_ -- `STM32U5A5 reference manual`_ - -Supported Features -================== - -The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| CAN/CANFD | on-chip | canbus | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| BKP SRAM | on-chip | Backup SRAM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig`` - - -Connections and IOs -=================== - -Nucleo U5A5ZJ Q Board has 10 GPIO controllers. These controllers are responsible -for pin muxing, input/output, pull-up, etc. - -For more details please refer to `STM32 Nucleo-144 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - - -- CAN/CANFD_TX: PD1 -- CAN/CANFD_RX: PD0 -- DAC1_OUT1 : PA4 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- I2C_2_SCL : PF1 -- I2C_2_SDA : PF0 -- LD1 : PC7 -- LD2 : PB7 -- LD3 : PG2 -- LPUART_1_TX : PG7 -- LPUART_1_RX : PG8 -- SPI_1_NSS : PA4 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PC13 - -System Clock ------------- - -Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -160MHz, driven by 4MHz medium speed internal oscillator. - -Serial Port ------------ - -Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to -USART1. Default settings are 115200 8N1. - - -Backup SRAM ------------ - -In order to test backup SRAM you may want to disconnect VBAT from VDD. You can -do it by removing ``SB50`` jumper on the back side of the board. - - -Programming and Debugging -************************* - -Nucleo U5A5ZJ-Q board includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash the board using various tools. - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board. - -Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be -used to flash and debug the board if west is told to use it as runner, -which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. - -For pyocd additional target information needs to be installed. -This can be done by executing the following commands. - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32u5 - - -Flashing an application to Nucleo U5A5ZJ Q ------------------------------------------- - -Connect the Nucleo U5A5ZJ Q to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nucleo_u5a5zj_q - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -Default flasher for this board is openocd. It could be used in the usual way. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: nucleo_u5a5zj_q - :goals: debug - -Building a secure/non-secure with Arm ® TrustZone ® -=========================================================== - -The TF-M applications can be run on this board, thanks to its Arm ® TrustZone ® -support. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``nucleo_u5a5zj_q_ns`` as build target. - -.. code-block:: bash - - $ west build -b nucleo_u5a5zj_q_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash - -Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts -(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` -(which is used for initialization) is available in the PATH. - -.. _STM32 Nucleo-144 board User Manual: - https://www.st.com/resource/en/user_manual/um2861-stm32u5-nucleo144-board-mb1549-stmicroelectronics.pdf - -.. _STM32U5A5ZJ on www.st.com: - https://www.st.com/en/microcontrollers/stm32u5a5zj.html - -.. _STM32U5A5 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STMicroelectronics customized version of OpenOCD: - https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_wb55rg/Kconfig.board b/boards/arm/nucleo_wb55rg/Kconfig.board deleted file mode 100644 index a81009c125962a..00000000000000 --- a/boards/arm/nucleo_wb55rg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WB55RG Nucleo board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WB55RG - bool "Nucleo WB55RG Development Board" - depends on SOC_STM32WB55XX diff --git a/boards/arm/nucleo_wb55rg/Kconfig.defconfig b/boards/arm/nucleo_wb55rg/Kconfig.defconfig deleted file mode 100644 index 66c77220d3adc9..00000000000000 --- a/boards/arm/nucleo_wb55rg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32LWB55RG Nucleo board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WB55RG - -config BOARD - default "nucleo_wb55rg" - -choice BT_HCI_BUS_TYPE - default BT_STM32_IPM - depends on BT -endchoice - -endif # BOARD_NUCLEO_WB55RG diff --git a/boards/arm/nucleo_wba52cg/Kconfig.board b/boards/arm/nucleo_wba52cg/Kconfig.board deleted file mode 100644 index 819c5e1b1f0195..00000000000000 --- a/boards/arm/nucleo_wba52cg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WBA52CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WBA52CG - bool "Nucleo WBA52CG Development Board" - depends on SOC_STM32WBA52XX diff --git a/boards/arm/nucleo_wba52cg/Kconfig.defconfig b/boards/arm/nucleo_wba52cg/Kconfig.defconfig deleted file mode 100644 index dfdac1bba98b6f..00000000000000 --- a/boards/arm/nucleo_wba52cg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WBA52CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WBA52CG - -config BOARD - default "nucleo_wba52cg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_WBA52CG diff --git a/boards/arm/nucleo_wba55cg/Kconfig.board b/boards/arm/nucleo_wba55cg/Kconfig.board deleted file mode 100644 index 44bb0e5dcd8058..00000000000000 --- a/boards/arm/nucleo_wba55cg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WBA55CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WBA55CG - bool "Nucleo WBA55CG Development Board" - depends on SOC_STM32WBA55XX diff --git a/boards/arm/nucleo_wba55cg/Kconfig.defconfig b/boards/arm/nucleo_wba55cg/Kconfig.defconfig deleted file mode 100644 index ed24776ee4e4b1..00000000000000 --- a/boards/arm/nucleo_wba55cg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WBA52CG Nucleo board configuration - -# Copyright (c) 2023 STMicroelectronics - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WBA55CG - -config BOARD - default "nucleo_wba55cg" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_NUCLEO_WBA55CG diff --git a/boards/arm/nucleo_wl55jc/Kconfig.board b/boards/arm/nucleo_wl55jc/Kconfig.board deleted file mode 100644 index ece57d57da035a..00000000000000 --- a/boards/arm/nucleo_wl55jc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WL55JC Nucleo board configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NUCLEO_WL55JC - bool "Nucleo WL55JC Development Board" - depends on SOC_STM32WL55XX diff --git a/boards/arm/nucleo_wl55jc/Kconfig.defconfig b/boards/arm/nucleo_wl55jc/Kconfig.defconfig deleted file mode 100644 index 981e20f030646f..00000000000000 --- a/boards/arm/nucleo_wl55jc/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32WL55JC Nucleo board configuration - -# Copyright (c) 2020 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NUCLEO_WL55JC - -config BOARD - default "nucleo_wl55jc" - -endif # BOARD_NUCLEO_WL55JC diff --git a/boards/arm/numaker_pfm_m467/Kconfig.board b/boards/arm/numaker_pfm_m467/Kconfig.board deleted file mode 100644 index 8773aeeacc913d..00000000000000 --- a/boards/arm/numaker_pfm_m467/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M467 board configuration -# -# Copyright (c) 2023 Nuvoton Technology Corporation. - -config BOARD_NUMAKER_PFM_M467 - bool "NUVOTON PFM M467 Development Board" - depends on SOC_M467 diff --git a/boards/arm/numaker_pfm_m467/Kconfig.defconfig b/boards/arm/numaker_pfm_m467/Kconfig.defconfig deleted file mode 100644 index 97024136df88f2..00000000000000 --- a/boards/arm/numaker_pfm_m467/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M467 board configuration -# -# Copyright (c) 2023 Nuvoton Technology Corporation. - -if BOARD_NUMAKER_PFM_M467 - -config BOARD - default "numaker_pfm_m467" - -if NETWORKING - -config NET_L2_ETHERNET - default y if !MODEM - -endif # NETWORKING - -endif # BOARD_NUMAKER_PFM_M467 diff --git a/boards/arm/numaker_pfm_m467/board.cmake b/boards/arm/numaker_pfm_m467/board.cmake deleted file mode 100644 index 73a61385fd6340..00000000000000 --- a/boards/arm/numaker_pfm_m467/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(nulink "-f") -board_runner_args(pyocd "--target=m467hjhae") - -include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nulink.board.cmake) -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake) diff --git a/boards/arm/nuvoton_pfm_m487/Kconfig.board b/boards/arm/nuvoton_pfm_m487/Kconfig.board deleted file mode 100644 index ab31e205a3a6d1..00000000000000 --- a/boards/arm/nuvoton_pfm_m487/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M487 board configuration -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -config BOARD_NUVOTON_PFM_M487 - bool "NUVOTON PFM MP487 Development Board" - depends on SOC_M487 diff --git a/boards/arm/nuvoton_pfm_m487/Kconfig.defconfig b/boards/arm/nuvoton_pfm_m487/Kconfig.defconfig deleted file mode 100644 index d9657b64fa4296..00000000000000 --- a/boards/arm/nuvoton_pfm_m487/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Nuvoton PFM M487 board configuration -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -if BOARD_NUVOTON_PFM_M487 - -config BOARD - default "nuvoton_pfm_m487" - -endif # BOARD_NUVOTON_PFM_M487 diff --git a/boards/arm/nuvoton_pfm_m487/doc/index.rst b/boards/arm/nuvoton_pfm_m487/doc/index.rst deleted file mode 100644 index e5d30c7b764b2e..00000000000000 --- a/boards/arm/nuvoton_pfm_m487/doc/index.rst +++ /dev/null @@ -1,98 +0,0 @@ -.. _nuvoton_pfm_m487: - -NUVOTON NUMAKER PFM M487 -######################## - -Overview -******** - -The NuMaker PFM M487 is an Internet of Things (IoT) application focused platform -specially developed by Nuvoton. The PFM-M487 is based on the NuMicro® M487 -Ethernet series MCU with ARM® -Cortex®-M4F core. - -.. image:: pfm_m487.jpg - :align: center - :alt: PFM-M487 - -Features: -========= -- 32-bit Arm Cortex®-M4 M487JIDAE MCU -- Core clock up to 192 MHz -- 512 KB embedded Dual Bank Flash and 160 KB SRAM -- Audio codec (NAU88L25) with Microphone In and Headphone Out -- Ethernet (IP101GR) for network application -- USB 2.0 High-Speed OTG / Host / Device -- USB 1.1 Full-Speed OTG / Host / Device -- External SPI Flash (Winbond W25Q20) which can be regarded as ROM module -- MicroSD Card slot for T-Flash -- M487 extended interface 4 connector with 36 pins each -- Arduino UNO compatible interface -- Three push-buttons: one is for reset and the other two are for user-defined -- Four LEDs: one is for power indication and the other three are for user-defined -- On-board NU-Link-Me ICE debugger/programmer with SWD connector - -More information about the board can be found at the `PFM M487 User Manual`_. - -Supported Features -================== - -* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 192MHz. - -The development board configuration supports the following hardware features: - -+-----------+------------+-----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+-----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+-----------------------+ -| UART | on-chip | serial port | -+-----------+------------+-----------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -More details about the supported peripherals are available in `M480 TRM`_ -Other hardware features are not currently supported by the Zephyr kernel. - -Building and Flashing -********************* -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -On board debugger Nu-link-Me can emulate UART0 as a virtual COM port over usb, -To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. -Connect the PFM M487 IoT to your host computer using the USB port, then -run a serial host program to connect with your board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nuvoton_pfm_m487 - :goals: flash - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nuvoton_pfm_m487 - :goals: debug - -Step through the application in your debugger. - -References -********** - -.. _PFM M487 User Manual: - https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.01.pdf -.. _M480 TRM: - https://www.nuvoton.com/export/resource-files/TRM_M480_Series_EN_Rev2.02.pdf diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.dts b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.dts deleted file mode 100644 index f9c537307b310b..00000000000000 --- a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.dts +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2020 Linumiz - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "nuvoton_pfm_m487-pinctrl.dtsi" -#include - -/ { - model = "Nuvoton PFM M487 board"; - compatible = "nuvoton,pfm-m487", "nuvoton,m487"; - - aliases { - led0 = &red_led; - led1 = &yellow_led; - led2 = &green_led; - sw0 = &sw2; - sw1 = &sw3; - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_0 { - gpios = <&gpioh 0 GPIO_ACTIVE_LOW>; - label = "User LED Red"; - }; - yellow_led: led_1 { - gpios = <&gpioh 1 GPIO_ACTIVE_LOW>; - label = "User LED Yellow"; - }; - green_led: led_2 { - gpios = <&gpioh 2 GPIO_ACTIVE_LOW>; - label = "User LED Green"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - sw2: button_0 { - gpios = <&gpiog 15 GPIO_ACTIVE_LOW>; - label = "User SW2"; - zephyr,code = ; - }; - sw3: button_1 { - gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; - label = "User SW3"; - zephyr,code = ; - }; - }; -}; - -&flash0 { - reg = <0x0 DT_SIZE_K(512)>; -}; - -&sram0 { - reg = <0x20000000 DT_SIZE_K(160)>; -}; - -&gpiob { - status = "okay"; -}; - -&gpiof { - status = "okay"; -}; - -&gpiog { - status = "okay"; -}; - -&gpioh { - status = "okay"; -}; - -&uart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.yaml b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.yaml deleted file mode 100644 index c56fb1fd78e11f..00000000000000 --- a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: nuvoton_pfm_m487 -name: NUVOTON-PFM-M487 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 160 -flash: 512 -vendor: nuvoton diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig b/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig deleted file mode 100644 index 7c800edd1ba2aa..00000000000000 --- a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_M48X=y -CONFIG_SOC_M487=y -CONFIG_BOARD_NUVOTON_PFM_M487=y - -# Enable MPU -CONFIG_ARM_MPU=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=192000000 - -# Enable GPIO and pinctrl drivers -CONFIG_GPIO=y -CONFIG_PINCTRL=y - -# enable uart driver -CONFIG_SERIAL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.board b/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.board deleted file mode 100644 index ce50e16b3fb30e..00000000000000 --- a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Olimex LoRa STM32WL DevKit configuration - -# Copyright (c) 2022 Martin Jäger -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_LORA_STM32WL_DEVKIT - bool "Olimex LoRa STM32WL DevKit" - depends on SOC_STM32WLE5XX diff --git a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.defconfig b/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.defconfig deleted file mode 100644 index 21efeea2fc71b6..00000000000000 --- a/boards/arm/olimex_lora_stm32wl_devkit/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Olimex LoRa STM32WL DevKit configuration - -# Copyright (c) 2022 Martin Jäger -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_LORA_STM32WL_DEVKIT - -config BOARD - default "olimex_lora_stm32wl_devkit" - -endif # BOARD_OLIMEX_LORA_STM32WL_DEVKIT diff --git a/boards/arm/olimex_lora_stm32wl_devkit/revision.cmake b/boards/arm/olimex_lora_stm32wl_devkit/revision.cmake deleted file mode 100644 index 96501fe7e0b592..00000000000000 --- a/boards/arm/olimex_lora_stm32wl_devkit/revision.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2023 Kenneth J. Miller -# -# SPDX-License-Identifier: Apache-2.0 -# - -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION B - VALID_REVISIONS A B C D -) diff --git a/boards/arm/olimex_stm32_e407/Kconfig.board b/boards/arm/olimex_stm32_e407/Kconfig.board deleted file mode 100644 index ff09270835838c..00000000000000 --- a/boards/arm/olimex_stm32_e407/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-E407 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_E407 - bool "OLIMEX-STM32-E407 Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/olimex_stm32_e407/Kconfig.defconfig b/boards/arm/olimex_stm32_e407/Kconfig.defconfig deleted file mode 100644 index 28fb1c3f76e93a..00000000000000 --- a/boards/arm/olimex_stm32_e407/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-E407 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_E407 - -config BOARD - default "olimex_stm32_e407" - -endif # BOARD_OLIMEX_STM32_E407 diff --git a/boards/arm/olimex_stm32_h103/Kconfig.board b/boards/arm/olimex_stm32_h103/Kconfig.board deleted file mode 100644 index d2f9e76ae4a5ca..00000000000000 --- a/boards/arm/olimex_stm32_h103/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-H103 board configuration - -# Copyright (c) 2020, Josep Puigdemont -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_H103 - bool "OLIMEX-STM32-H103 Development Board" - depends on SOC_STM32F103XB diff --git a/boards/arm/olimex_stm32_h103/Kconfig.defconfig b/boards/arm/olimex_stm32_h103/Kconfig.defconfig deleted file mode 100644 index 5dd2426b5f6288..00000000000000 --- a/boards/arm/olimex_stm32_h103/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-H103 board configuration - -# Copyright (c) 2020, Josep Puigdemont -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_H103 - -config BOARD - default "olimex_stm32_h103" - -endif # BOARD_OLIMEX_STM32_H103 diff --git a/boards/arm/olimex_stm32_h405/Kconfig.board b/boards/arm/olimex_stm32_h405/Kconfig.board deleted file mode 100644 index 6559afd8b35946..00000000000000 --- a/boards/arm/olimex_stm32_h405/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-H405 board configuration - -# Copyright (c) 2020, 2021 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_H405 - bool "OLIMEX STM32-H405 Development Board" - depends on SOC_STM32F405XG diff --git a/boards/arm/olimex_stm32_h405/Kconfig.defconfig b/boards/arm/olimex_stm32_h405/Kconfig.defconfig deleted file mode 100644 index bd334c78807a70..00000000000000 --- a/boards/arm/olimex_stm32_h405/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-H405 board configuration - -# Copyright (c) 2020, Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_H405 - -config BOARD - default "olimex_stm32_h405" - -endif # BOARD_OLIMEX_STM32_H405 diff --git a/boards/arm/olimex_stm32_h407/Kconfig.board b/boards/arm/olimex_stm32_h407/Kconfig.board deleted file mode 100644 index c08552cd65b5c6..00000000000000 --- a/boards/arm/olimex_stm32_h407/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-H407 board configuration - -# Copyright (c) 2018, Reto Schneider -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_H407 - bool "OLIMEX-STM32-H407 Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/olimex_stm32_h407/Kconfig.defconfig b/boards/arm/olimex_stm32_h407/Kconfig.defconfig deleted file mode 100644 index 01a8e749d59d2b..00000000000000 --- a/boards/arm/olimex_stm32_h407/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-H407 board configuration - -# Copyright (c) 2018, Reto Schneider -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_H407 - -config BOARD - default "olimex_stm32_h407" - -endif # BOARD_OLIMEX_STM32_H407 diff --git a/boards/arm/olimex_stm32_p405/Kconfig.board b/boards/arm/olimex_stm32_p405/Kconfig.board deleted file mode 100644 index fdc33309849eec..00000000000000 --- a/boards/arm/olimex_stm32_p405/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEX-STM32-P405 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_STM32_P405 - bool "OLIMEX-STM32-P405 Development Board" - depends on SOC_STM32F405XG diff --git a/boards/arm/olimex_stm32_p405/Kconfig.defconfig b/boards/arm/olimex_stm32_p405/Kconfig.defconfig deleted file mode 100644 index 8dc0211bd7f1c1..00000000000000 --- a/boards/arm/olimex_stm32_p405/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# OLIMEX-STM32-P405 board configuration - -# Copyright (c) 2017, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_STM32_P405 - -config BOARD - default "olimex_stm32_p405" - -endif # BOARD_OLIMEX_STM32_P405 diff --git a/boards/arm/olimexino_stm32/Kconfig.board b/boards/arm/olimexino_stm32/Kconfig.board deleted file mode 100644 index 902efe68813c04..00000000000000 --- a/boards/arm/olimexino_stm32/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# OLIMEXINO-STM32 board configuration - -# Copyright (c) 2016, I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEXINO_STM32 - bool "OLIMEXINO-STM32 Development Board" - depends on SOC_STM32F103XB diff --git a/boards/arm/olimexino_stm32/Kconfig.defconfig b/boards/arm/olimexino_stm32/Kconfig.defconfig deleted file mode 100644 index 1c90ddc74e290c..00000000000000 --- a/boards/arm/olimexino_stm32/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# OLIMEXINO-STM32 board configuration - -# Copyright (c) 2016, I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEXINO_STM32 - -config BOARD - default "olimexino_stm32" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_OLIMEXINO_STM32 diff --git a/boards/arm/pan1770_evb/Kconfig.board b/boards/arm/pan1770_evb/Kconfig.board deleted file mode 100644 index af61b03670145e..00000000000000 --- a/boards/arm/pan1770_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1770 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1770_EVB - bool "pan1770-evb" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/pan1770_evb/Kconfig.defconfig b/boards/arm/pan1770_evb/Kconfig.defconfig deleted file mode 100644 index e4f718cfb040a1..00000000000000 --- a/boards/arm/pan1770_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1770 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1770_EVB - -config BOARD - default "pan1770_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1770_EVB diff --git a/boards/arm/pan1780_evb/Kconfig.board b/boards/arm/pan1780_evb/Kconfig.board deleted file mode 100644 index 54e8be6cfc3d6a..00000000000000 --- a/boards/arm/pan1780_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1780 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1780_EVB - bool "pan1780-evb" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/pan1780_evb/Kconfig.defconfig b/boards/arm/pan1780_evb/Kconfig.defconfig deleted file mode 100644 index 4ce48bcab5996f..00000000000000 --- a/boards/arm/pan1780_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1780 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1780_EVB - -config BOARD - default "pan1780_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1780_EVB diff --git a/boards/arm/pan1781_evb/Kconfig.board b/boards/arm/pan1781_evb/Kconfig.board deleted file mode 100644 index 04c8680dba84cf..00000000000000 --- a/boards/arm/pan1781_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1781 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1781_EVB - bool "pan1781-evb" - depends on SOC_NRF52820_QDAA diff --git a/boards/arm/pan1781_evb/Kconfig.defconfig b/boards/arm/pan1781_evb/Kconfig.defconfig deleted file mode 100644 index 551d01ddd31783..00000000000000 --- a/boards/arm/pan1781_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1781 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1781_EVB - -config BOARD - default "pan1781_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1781_EVB diff --git a/boards/arm/pan1782_evb/Kconfig.board b/boards/arm/pan1782_evb/Kconfig.board deleted file mode 100644 index 734f1f5dfee6e3..00000000000000 --- a/boards/arm/pan1782_evb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PAN1782 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1782_EVB - bool "pan1782-evb" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/pan1782_evb/Kconfig.defconfig b/boards/arm/pan1782_evb/Kconfig.defconfig deleted file mode 100644 index 465794a8b21e4d..00000000000000 --- a/boards/arm/pan1782_evb/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# PAN1782 EVB configuration - -# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1782_EVB - -config BOARD - default "pan1782_evb" - -config BT_CTLR - default BT - -endif # BOARD_PAN1782_EVB diff --git a/boards/arm/pan1783/CMakeLists.txt b/boards/arm/pan1783/CMakeLists.txt deleted file mode 100644 index a582b3cc819ea1..00000000000000 --- a/boards/arm/pan1783/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if((CONFIG_BOARD_PAN1783_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP) AND (CONFIG_BOARD_ENABLE_CPUNET)) - zephyr_library() - zephyr_library_sources(pan1783_cpunet_reset.c) -endif() diff --git a/boards/arm/pan1783/Kconfig b/boards/arm/pan1783/Kconfig deleted file mode 100644 index e4f583984590e1..00000000000000 --- a/boards/arm/pan1783/Kconfig +++ /dev/null @@ -1,56 +0,0 @@ -# PAN1783 EVB board configuration - -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "pan1783_evb_cpunet" if BOARD_PAN1783_EVB_CPUAPP - default "pan1783a_evb_cpunet" if BOARD_PAN1783A_EVB_CPUAPP - default "pan1783a_pa_evb_cpunet" if BOARD_PAN1783A_PA_EVB_CPUAPP - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -config DOMAIN_CPUAPP_BOARD - string - default "pan1783_evb_cpuapp" if BOARD_PAN1783_EVB_CPUNET - default "pan1783a_evb_cpuapp" if BOARD_PAN1783A_EVB_CPUNET - default "pan1783a_pa_evb_cpuapp" if BOARD_PAN1783A_PA_EVB_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/pan1783/Kconfig.board b/boards/arm/pan1783/Kconfig.board deleted file mode 100644 index 3fcaaf39e563cb..00000000000000 --- a/boards/arm/pan1783/Kconfig.board +++ /dev/null @@ -1,28 +0,0 @@ -# PAN1783 EVB board configuration - -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PAN1783_EVB_CPUAPP - bool "PAN1783 EVB (nRF5340) Application MCU" - depends on SOC_NRF5340_CPUAPP_QKAA - -config BOARD_PAN1783A_EVB_CPUAPP - bool "PAN1783A EVB (nRF5340) Application MCU" - depends on SOC_NRF5340_CPUAPP_QKAA - -config BOARD_PAN1783A_PA_EVB_CPUAPP - bool "PAN1783A-PA EVB (nRF5340) Application MCU" - depends on SOC_NRF5340_CPUAPP_QKAA - -config BOARD_PAN1783_EVB_CPUNET - bool "PAN1783 EVB (NRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA - -config BOARD_PAN1783A_EVB_CPUNET - bool "PAN1783A EVB (NRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA - -config BOARD_PAN1783A_PA_EVB_CPUNET - bool "PAN1783A-PA EVB (NRF5340) Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/pan1783/Kconfig.defconfig b/boards/arm/pan1783/Kconfig.defconfig deleted file mode 100644 index 47c02a95b7f7be..00000000000000 --- a/boards/arm/pan1783/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# PAN1783 EVB board configuration - -# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "pan1783_evb_cpuapp" if BOARD_PAN1783_EVB_CPUAPP - default "pan1783a_evb_cpuapp" if BOARD_PAN1783A_EVB_CPUAPP - default "pan1783a_pa_evb_cpuapp" if BOARD_PAN1783A_PA_EVB_CPUAPP - default "pan1783_evb_cpunet" if BOARD_PAN1783_EVB_CPUNET - default "pan1783a_evb_cpunet" if BOARD_PAN1783A_EVB_CPUNET - default "pan1783a_pa_evb_cpunet" if BOARD_PAN1783A_PA_EVB_CPUNET - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_PAN1783_EVB_CPUAPP || BOARD_PAN1783A_EVB_CPUAPP || BOARD_PAN1783A_PA_EVB_CPUAPP - -if BOARD_PAN1783_EVB_CPUNET || BOARD_PAN1783A_EVB_CPUNET || BOARD_PAN1783A_PA_EVB_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_PAN1783_EVB_CPUNET || BOARD_PAN1783A_EVB_CPUNET || BOARD_PAN1783A_PA_EVB_CPUNET diff --git a/boards/arm/pan1783/board.cmake b/boards/arm/pan1783/board.cmake deleted file mode 100644 index e8a33e8c7bf129..00000000000000 --- a/boards/arm/pan1783/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_PAN1783_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_EVB_CPUAPP OR CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_PAN1783_EVB_CPUNET OR CONFIG_BOARD_PAN1783A_EVB_CPUNET OR CONFIG_BOARD_PAN1783A_PA_EVB_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/pan1783/pan1783_cpuapp_common.dtsi b/boards/arm/pan1783/pan1783_cpuapp_common.dtsi deleted file mode 100644 index 77d093a5d4003e..00000000000000 --- a/boards/arm/pan1783/pan1783_cpuapp_common.dtsi +++ /dev/null @@ -1,300 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "pan1783_cpuapp_common-pinctrl.dtsi" -#include - -/ { - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,bt-hci-ipc = &ipc0; - nordic,802154-spinel-ipc = &ipc0; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; - evb_led1: evb_led_1 { - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - label = "LED1 on EVB"; - }; - evb_led2: evb_led_2 { - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - label = "LED2 on EVB"; - }; - evb_led3: evb_led_3 { - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - label = "LED3 on EVB"; - }; - evb_led4: evb_led_4 { - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - label = "LED4 on EVB"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_evb_led1: pwm_evb_led_1 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - buttons { - compatible = "gpio-keys"; - evb_sw1: evb_sw_1 { - gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW1 on EVB"; - zephyr,code = ; - }; - evb_sw2: evb_sw_2 { - gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW2 on EVB"; - zephyr,code = ; - }; - evb_sw3: evb_sw_3 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW3 on EVB"; - zephyr,code = ; - }; - evb_sw4: evb_sw_4 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW4 on EVB"; - zephyr,code = ; - }; - }; - - mikrobus_header: mikrobus-connector { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* AN */ - /* Not a GPIO*/ /* RST */ - <2 0 &gpio1 12 0>, /* CS */ - <3 0 &gpio1 15 0>, /* SCK */ - <4 0 &gpio1 14 0>, /* MISO */ - <5 0 &gpio1 13 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpio1 7 0>, /* PWM */ - <7 0 &gpio1 4 0>, /* INT */ - <8 0 &gpio1 0 0>, /* RX */ - <9 0 &gpio1 1 0>, /* TX */ - <10 0 &gpio1 3 0>, /* SCL */ - <11 0 &gpio1 2 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ - }; - - arduino_adc: analog-connector { - compatible = "arduino,uno-adc"; - #io-channel-cells = <1>; - io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */ - <1 &adc 1>, /* A1 = P0.5 = AIN1 */ - <2 &adc 2>, /* A2 = P0.6 = AIN2 */ - <3 &adc 3>, /* A3 = P0.7 = AIN3 */ - <4 &adc 4>, /* A4 = P0.25 = AIN4 */ - <5 &adc 5>; /* A5 = P0.26 = AIN5 */ - }; - - gpio_fwd: nrf-gpio-forwarder { - compatible = "nordic,nrf-gpio-forwarder"; - status = "disabled"; - uart { - gpios = <&gpio0 20 0>, <&gpio0 22 0>, <&gpio0 11 0>, <&gpio0 10 0>; - }; - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &evb_led1; - led1 = &evb_led2; - led2 = &evb_led3; - led3 = &evb_led4; - pwm-led0 = &pwm_evb_led1; - sw0 = &evb_sw1; - sw1 = &evb_sw2; - sw2 = &evb_sw3; - sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; - mcuboot-button0 = &evb_sw1; - mcuboot-led0 = &evb_led1; - watchdog0 = &wdt0; - spi-flash0 = &mx25r64; - }; -}; - -&adc { - status = "okay"; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c1 { - compatible = "nordic,nrf-twim"; - status = "okay"; - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&qspi { - status = "okay"; - pinctrl-0 = <&qspi_default>; - pinctrl-1 = <&qspi_sleep>; - pinctrl-names = "default", "sleep"; - mx25r64: mx25r6435f@0 { - compatible = "nordic,qspi-nor"; - reg = <0>; - /* MX25R64 supports only pp and pp4io */ - writeoc = "pp4io"; - /* MX25R64 supports all readoc options */ - readoc = "read4io"; - sck-frequency = <8000000>; - jedec-id = [ c2 28 17 ]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - size = <67108864>; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <35000>; - }; -}; - -arduino_serial: &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_i2c: &i2c1 {}; - -arduino_spi: &spi4 { - compatible = "nordic,nrf-spim"; - status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ - pinctrl-0 = <&spi4_default>; - pinctrl-1 = <&spi4_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash0 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - }; - slot0_partition: partition@10000 { - label = "image-0"; - }; - slot1_partition: partition@80000 { - label = "image-1"; - }; - /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ - storage_partition: partition@f8000 { - label = "storage"; - reg = <0x000f8000 0x00008000>; - }; - }; -}; - -&ieee802154 { - status = "okay"; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; - -/ { - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - sram0_image: image@20000000 { - /* Zephyr image(s) memory */ - }; - - sram0_s: image_s@20000000 { - /* Secure image memory */ - }; - }; -}; - -/* Include partition configuration file */ -#include "pan1783_cpuapp_partition_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpuapp_partition_conf.dtsi b/boards/arm/pan1783/pan1783_cpuapp_partition_conf.dtsi deleted file mode 100644 index 6eb6792c996959..00000000000000 --- a/boards/arm/pan1783/pan1783_cpuapp_partition_conf.dtsi +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* - * Default Flash planning for pan1783_evb CPUAPP (Application MCU). - * - * Secure image will be placed, by default, in flash0 - * (or in slot0, if MCUboot is present). - * Secure image will use sram0 for system memory. - * - */ - -&slot0_partition { - reg = <0x00010000 0x40000>; -}; - -&slot1_partition { - reg = <0x00080000 0x40000>; -}; - -/* Default SRAM planning when building for nRF5340 - * - Lowest 448 kB SRAM allocated to Secure image (sram0_s) - * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) - * (see shared_sram_planning_conf.dtsi) - */ -&sram0_image { - reg = <0x20000000 DT_SIZE_K(448)>; -}; - -&sram0_s { - reg = <0x20000000 0x70000>; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpunet_common.dtsi b/boards/arm/pan1783/pan1783_cpunet_common.dtsi deleted file mode 100644 index 5b5e7735e4a4c3..00000000000000 --- a/boards/arm/pan1783/pan1783_cpunet_common.dtsi +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ -#include "pan1783_cpunet-pinctrl.dtsi" -#include - -/ { - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,bt-hci-ipc = &ipc0; - nordic,802154-spinel-ipc = &ipc0; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; - evb_led1: evb_led_1 { - gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; - label = "LED1 on EVB"; - }; - evb_led2: evb_led_2 { - gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; - label = "LED2 on EVB"; - }; - evb_led3: evb_led_3 { - gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; - label = "LED3 on EVB"; - }; - evb_led4: evb_led_4 { - gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; - label = "LED4 on EVB"; - }; - }; - - buttons { - compatible = "gpio-keys"; - evb_sw1: evb_sw_1 { - gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW1 on EVB"; - zephyr,code = ; - }; - evb_sw2: evb_sw_2 { - gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW2 on EVB"; - zephyr,code = ; - }; - evb_sw3: evb_sw_3 { - gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW3 on EVB"; - zephyr,code = ; - }; - evb_sw4: evb_sw_4 { - gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "SW4 on EVB"; - zephyr,code = ; - }; - }; - - mikrobus_header: mikrobus-connector { - compatible = "mikro-bus"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* AN */ - /* Not a GPIO*/ /* RST */ - <2 0 &gpio1 12 0>, /* CS */ - <3 0 &gpio1 15 0>, /* SCK */ - <4 0 &gpio1 14 0>, /* MISO */ - <5 0 &gpio1 13 0>, /* MOSI */ - /* +3.3V */ - /* GND */ - <6 0 &gpio1 7 0>, /* PWM */ - <7 0 &gpio1 4 0>, /* INT */ - <8 0 &gpio1 0 0>, /* RX */ - <9 0 &gpio1 1 0>, /* TX */ - <10 0 &gpio1 3 0>, /* SCL */ - <11 0 &gpio1 2 0>; /* SDA */ - /* +5V */ - /* GND */ - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 4 0>, /* A0 */ - <1 0 &gpio0 5 0>, /* A1 */ - <2 0 &gpio0 6 0>, /* A2 */ - <3 0 &gpio0 7 0>, /* A3 */ - <4 0 &gpio0 25 0>, /* A4 */ - <5 0 &gpio0 26 0>, /* A5 */ - <6 0 &gpio1 0 0>, /* D0 */ - <7 0 &gpio1 1 0>, /* D1 */ - <8 0 &gpio1 4 0>, /* D2 */ - <9 0 &gpio1 5 0>, /* D3 */ - <10 0 &gpio1 6 0>, /* D4 */ - <11 0 &gpio1 7 0>, /* D5 */ - <12 0 &gpio1 8 0>, /* D6 */ - <13 0 &gpio1 9 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio1 2 0>, /* D14 */ - <21 0 &gpio1 3 0>; /* D15 */ - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &evb_led1; - led1 = &evb_led2; - led2 = &evb_led3; - led3 = &evb_led4; - sw0 = &evb_sw1; - sw1 = &evb_sw2; - sw2 = &evb_sw3; - sw3 = &evb_sw4; - bootloader-led0 = &evb_led1; - mcuboot-button0 = &evb_sw1; - mcuboot-led0 = &evb_led1; - watchdog0 = &wdt0; - }; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&uart0 { - status = "disabled"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_serial: &uart0 {}; - -arduino_i2c: &i2c0 { - compatible = "nordic,nrf-twim"; - /* Cannot be used together with uart0. */ - /* status = "okay"; */ - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_spi: &spi0 { - compatible = "nordic,nrf-spim"; - /* Cannot be used together with uart0. */ - /* status = "okay"; */ - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ - pinctrl-0 = <&spi0_default>; - pinctrl-1 = <&spi0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&flash1 { - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0xc000>; - }; - slot0_partition: partition@c000 { - label = "image-0"; - reg = <0x0000C000 0x17000>; - }; - slot1_partition: partition@23000 { - label = "image-1"; - reg = <0x00023000 0x17000>; - }; - storage_partition: partition@3a000 { - label = "storage"; - reg = <0x0003a000 0x6000>; - }; - }; -}; - -&ieee802154 { - status = "okay"; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpunet_reset.c b/boards/arm/pan1783/pan1783_cpunet_reset.c deleted file mode 100644 index 529051ec62943f..00000000000000 --- a/boards/arm/pan1783/pan1783_cpunet_reset.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - -#include -#include - -#if defined(CONFIG_BOARD_PAN1783_EVB_CPUAPP) -LOG_MODULE_REGISTER(pan1783_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#elif defined(CONFIG_BOARD_PAN1783A_EVB_CPUAPP) -LOG_MODULE_REGISTER(pan1783a_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#elif defined(CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP) -LOG_MODULE_REGISTER(pan1783a_pa_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); -#else -#error "No board selected!" -#endif - -#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) -#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> -#else -#define DEBUG_SETUP() -#endif - -static void remoteproc_mgr_config(void) -{ - /* Route Bluetooth Controller Debug Pins */ - DEBUG_SETUP(); - - /* Retain nRF5340 Network MCU */ - NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; -} - -static int remoteproc_mgr_boot(void) -{ - /* Configure permissions for the Network MCU. */ - remoteproc_mgr_config(); - - /* Release the Network MCU, 'Release force off signal' */ - nrf_reset_network_force_off(NRF_RESET, false); - - LOG_DBG("Network MCU released."); - - return 0; -} - -SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/arm/pan1783/pan1783_evb_cpuapp.dts b/boards/arm/pan1783/pan1783_evb_cpuapp.dts deleted file mode 100644 index 54f71dd87d5b20..00000000000000 --- a/boards/arm/pan1783/pan1783_evb_cpuapp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpuapp_common.dtsi" - -/ { - model = "Panasonic PAN1783 EVB (NRF5340) Application"; - compatible = "panasonic,pan1783-evb-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - }; -}; diff --git a/boards/arm/pan1783/pan1783_evb_cpuapp.yaml b/boards/arm/pan1783/pan1783_evb_cpuapp.yaml deleted file mode 100644 index a0242b83252b03..00000000000000 --- a/boards/arm/pan1783/pan1783_evb_cpuapp.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: pan1783_evb_cpuapp -name: PAN1783-EVB-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - gpio - - i2c - - i2s - - pwm - - watchdog - - usb_cdc - - usb_device - - netif:openthread - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783_evb_cpuapp_defconfig b/boards/arm/pan1783/pan1783_evb_cpuapp_defconfig deleted file mode 100644 index b709d16dc54d14..00000000000000 --- a/boards/arm/pan1783/pan1783_evb_cpuapp_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_PAN1783_EVB_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783_evb_cpunet.dts b/boards/arm/pan1783/pan1783_evb_cpunet.dts deleted file mode 100644 index 7063e53af46d50..00000000000000 --- a/boards/arm/pan1783/pan1783_evb_cpunet.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpunet_common.dtsi" - -/ { - model = "Panasonic PAN1783 EVB (NRF5340) Network"; - compatible = "panasonic,pan1783-evb-cpunet"; - - chosen { - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - }; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_evb_cpunet.yaml b/boards/arm/pan1783/pan1783_evb_cpunet.yaml deleted file mode 100644 index 725fae94cc5bf1..00000000000000 --- a/boards/arm/pan1783/pan1783_evb_cpunet.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: pan1783_evb_cpunet -name: PAN1783-EVB-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - watchdog - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783_evb_cpunet_defconfig b/boards/arm/pan1783/pan1783_evb_cpunet_defconfig deleted file mode 100644 index f83ea00045534e..00000000000000 --- a/boards/arm/pan1783/pan1783_evb_cpunet_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_PAN1783_EVB_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_evb_cpuapp.dts b/boards/arm/pan1783/pan1783a_evb_cpuapp.dts deleted file mode 100644 index 29f0dcb796c4d9..00000000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpuapp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpuapp_common.dtsi" - -/ { - model = "Panasonic PAN1783A EVB (NRF5340) Application"; - compatible = "panasonic,pan1783a-evb-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - }; -}; diff --git a/boards/arm/pan1783/pan1783a_evb_cpuapp.yaml b/boards/arm/pan1783/pan1783a_evb_cpuapp.yaml deleted file mode 100644 index 2a89c3f1f375d7..00000000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpuapp.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: pan1783a_evb_cpuapp -name: PAN1783A-EVB-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - gpio - - i2c - - i2s - - pwm - - watchdog - - usb_cdc - - usb_device - - netif:openthread - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_evb_cpuapp_defconfig b/boards/arm/pan1783/pan1783a_evb_cpuapp_defconfig deleted file mode 100644 index 2f624e1db0cf5f..00000000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpuapp_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_PAN1783A_EVB_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_evb_cpunet.dts b/boards/arm/pan1783/pan1783a_evb_cpunet.dts deleted file mode 100644 index 9cd0409a432694..00000000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpunet.dts +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpunet_common.dtsi" - -/ { - model = "Panasonic PAN1783A EVB (NRF5340) Network"; - compatible = "panasonic,pan1783a-evb-cpunet"; - - chosen { - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - }; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783a_evb_cpunet.yaml b/boards/arm/pan1783/pan1783a_evb_cpunet.yaml deleted file mode 100644 index 2dd985f61ff42f..00000000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpunet.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: pan1783a_evb_cpunet -name: PAN1783A-EVB-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - watchdog - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_evb_cpunet_defconfig b/boards/arm/pan1783/pan1783a_evb_cpunet_defconfig deleted file mode 100644 index 3e44ff7338cfc9..00000000000000 --- a/boards/arm/pan1783/pan1783a_evb_cpunet_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_PAN1783A_EVB_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.dts b/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.dts deleted file mode 100644 index aba6e9281e2111..00000000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpuapp_common.dtsi" - -/ { - model = "Panasonic PAN1783A-PA EVB (NRF5340) Application"; - compatible = "panasonic,pan1783a_pa-evb-cpuapp"; - - chosen { - zephyr,sram = &sram0_image; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,sram-secure-partition = &sram0_s; - }; -}; - -&gpio_fwd { - /delete-node/ uart; - - status = "okay"; - fem { - gpios = <&gpio0 19 0>, <&gpio0 21 0>; - }; -}; diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.yaml b/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.yaml deleted file mode 100644 index 0bc70dab27375a..00000000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: pan1783a_pa_evb_cpuapp -name: PAN1783A-PA-EVB-application-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 448 -flash: 1024 -supported: - - gpio - - i2c - - i2s - - pwm - - watchdog - - usb_cdc - - usb_device - - netif:openthread - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp_defconfig b/boards/arm/pan1783/pan1783a_pa_evb_cpuapp_defconfig deleted file mode 100644 index f58bdce8bfc0c0..00000000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpuapp_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_PAN1783A_PA_EVB_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.dts b/boards/arm/pan1783/pan1783a_pa_evb_cpunet.dts deleted file mode 100644 index 1b345aaa94526b..00000000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "pan1783_cpunet_common.dtsi" - -/ { - model = "Panasonic PAN1783A-PA EVB (NRF5340) Network"; - compatible = "panasonic,pan1783a_pa-evb-cpunet"; - - chosen { - zephyr,sram = &sram1; - zephyr,flash = &flash1; - zephyr,code-partition = &slot0_partition; - }; - - nrf_radio_fem: fem_node { - compatible = "skyworks,sky66407-11", "generic-fem-two-ctrl-pins"; - ctx-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; - crx-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - }; -}; - -&radio { - fem = <&nrf_radio_fem>; -}; - -/* Include shared RAM configuration file */ -#include "pan1783_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.yaml b/boards/arm/pan1783/pan1783a_pa_evb_cpunet.yaml deleted file mode 100644 index 98a2f2908de226..00000000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpunet.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: pan1783a_pa_evb_cpunet -name: PAN1783A-PA-EVB-network-MCU -type: mcu -arch: arm -toolchain: - - gnuarmemb - - xtools - - zephyr -ram: 64 -flash: 256 -supported: - - watchdog - - gpio -vendor: panasonic diff --git a/boards/arm/pan1783/pan1783a_pa_evb_cpunet_defconfig b/boards/arm/pan1783/pan1783a_pa_evb_cpunet_defconfig deleted file mode 100644 index 3ba18cd433a00c..00000000000000 --- a/boards/arm/pan1783/pan1783a_pa_evb_cpunet_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_PAN1783A_PA_EVB_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# clock config -CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pandora_stm32l475/Kconfig.board b/boards/arm/pandora_stm32l475/Kconfig.board deleted file mode 100644 index 89ba1c54b98971..00000000000000 --- a/boards/arm/pandora_stm32l475/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L475 Pandora board configuration - -# Copyright (c) 2023 Tisilicon -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PANDORA_STM32L475 - bool "STM32L475 Pandora Development Board" - depends on SOC_STM32L475XX diff --git a/boards/arm/pandora_stm32l475/Kconfig.defconfig b/boards/arm/pandora_stm32l475/Kconfig.defconfig deleted file mode 100644 index 2d0f4e8c456ff6..00000000000000 --- a/boards/arm/pandora_stm32l475/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32L475 Pandora board configuration - -# Copyright (c) 2023 Tisilicon -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PANDORA_STM32L475 - -config BOARD - default "pandora_stm32l475" - -endif # BOARD_PANDORA_STM32L475 diff --git a/boards/arm/pandora_stm32l475/doc/index.rst b/boards/arm/pandora_stm32l475/doc/index.rst deleted file mode 100644 index 76da038e9ec4b0..00000000000000 --- a/boards/arm/pandora_stm32l475/doc/index.rst +++ /dev/null @@ -1,214 +0,0 @@ -.. _stm32l475ve_pandora_board: - -Alientek STM32L475 Pandora -########################## - -Overview -******** - -The STM32L475 Pandora board features an ARM Cortex-M4 based STM32L475VE MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32L475 Pandora board: - - -- STM32L475Vx microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Three different interfaces supported on USB: - - - Virtual com port - - Mass storage - - Debug port - -- Pushbutton (reset) -- Four directions Joystick with selection -- USB OTG FS with micro-AB connector -- SAI Audio DAC, Stereo with output jack -- Digital microphone, accelerometer, magnetometer and gyroscope MEMS -- 128-Mbit Quad-SPI Flash memory -- MCU current ammeter with 4 ranges and auto-calibration -- Connector for external board or RF-EEPROM -- Four power supply options: - - ST-LINK/V2-1 - - USB FS connector - - External 5 V - - CR2032 battery (not provided) - -.. image:: img/pandora_stm32l475.jpg - :align: center - :alt: STM32L475 Pandora - -More information about the board can be found at the `STM32L475 Pandora website`_. - -Hardware -******** - -The STM32L475VE SoC provides the following hardware features: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- 16x timers: - - 2x 16-bit advanced motor-control - - 2x 32-bit and 7x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 82 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -Supported Features -================== - -The Zephyr stm32l475ve_pandora board configuration supports the following hardware features: - -+-----------+------------+----------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==============================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+----------------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+----------------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+----------------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------------------------------+ -| I2C | on-chip | I2C-AHT10(Temperature and humidity sensor) | -| | | I2C-ICM2068(light environment sensor) | -+-----------+------------+----------------------------------------------+ -| I2S | on-chip | I2S-ES8388(Audio Decoder) | -+-----------+------------+----------------------------------------------+ -| USB | on-chip | I2S-OTG | -+-----------+------------+----------------------------------------------+ -| SDIO | on-chip | SDIO-AP6181(WIFI) | -+-----------+------------+----------------------------------------------+ -| SPI | on-chip | LCD-TFT | -+-----------+------------+----------------------------------------------+ -| QSPI NOR | on-chip | flash | -+-----------+------------+----------------------------------------------+ -| IR-RX/TX | on-board | Infrared Receiver(38Khz)/Transmitter | -+-----------+------------+----------------------------------------------+ -| STLINK-V2 | on-board | STLINK-V2 Debugger | -+-----------+------------+----------------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/pandora_stm32l475/pandora_stm32l475_defconfig`` - - -Connections and IOs -=================== - -STM32L475 Pandora Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L475 Pandora board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- LED_R : PE7 -- LED_G : PE8 -- LED_B : PE9 - -System Clock ------------- - -STM32L475 Pandora System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -STM32L475 Pandora board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -STM32L475 Pandora board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32L475 Pandora --------------------------------------------- - -Connect the STM32L475 Pandora to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l475ve_pandora - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l475ve_pandora - :maybe-skip-config: - :goals: debug - -.. _STM32L475 Pandora website: - http://www.openedv.com/docs/boards/iot/zdyz_panduola.html - -.. _STM32L475 Pandora board User Manual: - http://www.openedv.com/thread-284556-1-1.html diff --git a/boards/arm/particle_argon/Kconfig.board b/boards/arm/particle_argon/Kconfig.board deleted file mode 100644 index 8b8aa29e3bc426..00000000000000 --- a/boards/arm/particle_argon/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Particle Argon configuration - -# Copyright (c) 2018 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PARTICLE_ARGON - bool "Particle Argon Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/particle_argon/Kconfig.defconfig b/boards/arm/particle_argon/Kconfig.defconfig deleted file mode 100644 index df988c09cd80a3..00000000000000 --- a/boards/arm/particle_argon/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Particle Argon board configuration - -# Copyright (c) 2018 Matthias Boesl -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PARTICLE_ARGON - -config BOARD - default "particle_argon" - -config BT_CTLR - default BT - -endif # BOARD_PARTICLE_ARGON diff --git a/boards/arm/particle_boron/Kconfig.board b/boards/arm/particle_boron/Kconfig.board deleted file mode 100644 index 17273fbf7617af..00000000000000 --- a/boards/arm/particle_boron/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Particle Boron configuration - -# Copyright (c) 2018 Peter Bigot Consulting, LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PARTICLE_BORON - bool "Particle Boron Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/particle_boron/Kconfig.defconfig b/boards/arm/particle_boron/Kconfig.defconfig deleted file mode 100644 index 9352289086c62b..00000000000000 --- a/boards/arm/particle_boron/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Particle Boron board configuration - -# Copyright (c) 2018 Peter Bigot Consulting, LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PARTICLE_BORON - -config BOARD - default "particle_boron" - -config BT_CTLR - default BT - -if MODEM - -config MODEM_UBLOX_SARA - default y - -choice MODEM_UBLOX_SARA_VARIANT - default MODEM_UBLOX_SARA_R4 -endchoice - -config UART_INTERRUPT_DRIVEN - default y - -endif # MODEM - -endif # BOARD_PARTICLE_BORON diff --git a/boards/arm/particle_xenon/Kconfig.board b/boards/arm/particle_xenon/Kconfig.board deleted file mode 100644 index 918ad23e8cd644..00000000000000 --- a/boards/arm/particle_xenon/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Particle Xenon configuration - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PARTICLE_XENON - bool "Particle Xenon Board" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/particle_xenon/Kconfig.defconfig b/boards/arm/particle_xenon/Kconfig.defconfig deleted file mode 100644 index 858a1230726d7d..00000000000000 --- a/boards/arm/particle_xenon/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Particle Xenon board configuration - -# Copyright (c) 2018 Endre Karlson -# Copyright (c) 2018 Peter Bigot Consulting, LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PARTICLE_XENON - -config BOARD - default "particle_xenon" - -config BT_CTLR - default BT - -endif # BOARD_PARTICLE_XENON diff --git a/boards/arm/particle_xenon/particle_xenon_defconfig b/boards/arm/particle_xenon/particle_xenon_defconfig deleted file mode 100644 index 8c7246fad1cc45..00000000000000 --- a/boards/arm/particle_xenon/particle_xenon_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018, Endre Karlson -# -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PARTICLE_XENON=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/pico_pi_m4/Kconfig.board b/boards/arm/pico_pi_m4/Kconfig.board deleted file mode 100644 index e980c3d1ec996d..00000000000000 --- a/boards/arm/pico_pi_m4/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Pico-Pi iMX7D M4 board - -# Copyright (c) 2019, Joris Offouga -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PICO_PI_M4 - bool "Pico-PI iMX7D Dual" - depends on SOC_SERIES_IMX7_M4 diff --git a/boards/arm/pico_pi_m4/Kconfig.defconfig b/boards/arm/pico_pi_m4/Kconfig.defconfig deleted file mode 100644 index fb3f7cd2f894c8..00000000000000 --- a/boards/arm/pico_pi_m4/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Pico-Pi iMX7D M4 board - -# Copyright (c) 2019, Joris Offouga -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PICO_PI_M4 - -config BOARD - default "pico_pi_m4" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_PICO_PI_M4 diff --git a/boards/arm/pico_pi_m4/doc/index.rst b/boards/arm/pico_pi_m4/doc/index.rst deleted file mode 100644 index 8e3c4e832c81ad..00000000000000 --- a/boards/arm/pico_pi_m4/doc/index.rst +++ /dev/null @@ -1,239 +0,0 @@ -.. _pico_pi_m4: - -Pico-Pi i.MX7D - Android Things IoT Development Platform -############################################################# - -Overview -******** - -The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7 -core and Single Cortex M4 core. -Zephyr was ported to run on the M4 core. In a later release, it will also -communicate with the A7 core (running Linux) via RPmsg. - - -.. image:: pico_pi_m4.jpg - :align: center - :alt: Pico-Pi i.MX7D - -Hardware -******** - -The Pico-Pi Platform is composed of a CPU and IO board. - -Pico-Pi IO Board -================ -- S1 - On/Off (MX7_ONOFF signal) -- Board to board connector : Edison compatible connector (70 configurable pins) -- mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART) -- 10-pin needle JTAG Connector -- Debug USB exposing One UART -- MIPI DSI 1 lane Connector -- LCD Touch Connector -- Audio Jack: Mic and Stereo Headphone - -Pico-Pi CPU Board -================= - -- CPU i.MX7 Dual with a Single Cortex A7 (1 GHz) core and - Single Cortex M4 (200MHz) core -- Memory - - - RAM -> A7: 4GB - - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A7: 8GB eMMC - -For more information about the i.MX7 SoC and Pico-Pi i.MX7D, see these references: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Dual Datasheet`_ -- `i.MX 7 Dual Reference Manual`_ - -Supported Features -================== - -The Pico-Pi i.MX7D configuration supports the following hardware features on the -Cortex M4 Core: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/pico_pi_m4/pico_pi_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The Pico-Pi board Board was tested with the following pinmux controller -configuration. - -+---------------+---------------------+--------------------------------+ -| Board Name | SoC Name | Usage | -+===============+=====================+================================+ -| UART_TX232 | UART1_TX | UART Console | -+---------------+---------------------+--------------------------------+ -| UART_RX232 | UART1_RX | UART Console | -+---------------+---------------------+--------------------------------+ -| RX_E | UART6_TX | UART (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ -| TX_E | UART6_RX | UART (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ -| I2CX_SDA_3V | I2C1_SDA | I2C (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ -| I2CX_SCL_3V | I2C1_SCL | I2C (mikroBUS and Edison) | -+---------------+---------------------+--------------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7D SoC has seven UARTs. The number 6 is configured for the console and -the number 2 is used in the mikroBUS connector. - -Programming and Debugging -************************* - -The Pico-Pi i.MX7D doesn't have QSPI flash for the M4 and it needs to be started by -the A7 core. The A7 core is responsible to load the M4 binary application into -the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and -get the M4 out of reset. -The A7 can perform these steps at bootloader level or after the Linux system -has booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and -M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - -References -========== - -- `i.MX 7 Dual Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) -- `Toradex Wiki`_ - - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/pico_pi_m4/pico_pi_m4.dts`` with -"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available -configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from A7 using -u-boot. - -Connect both micro USB interfaces into the PC. This is the A7 console and the -UART6 in the Edison connector is M4 console for Zephyr with both configured to work at 115200 8N1. -The USB interface is used to power the CPU and IO boards and is connected -to the USB OTG interface of the i.MX7D. - -After powering up the platform stop the u-boot execution on the A7 core and -expose the eMMC as mass storage with the following command in the u-boot -prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT -partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the -u-boot prompt. -Set the u-boot environment variables and run the zephyr.bin from the -appropriated memory configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Dual Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf - -.. _i.MX 7 Dual Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7DRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/pico_pi_m4/pico_pi_m4.dts b/boards/arm/pico_pi_m4/pico_pi_m4.dts deleted file mode 100644 index ecc1b2d41d973e..00000000000000 --- a/boards/arm/pico_pi_m4/pico_pi_m4.dts +++ /dev/null @@ -1,65 +0,0 @@ -/* - * Copyright (c) 2019, Joris Offouga - * Copyright 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "pico_pi_m4-pinctrl.dtsi" - -/ { - model = "Pico-Pi IMX7D board"; - compatible = "nxp,mcimx7d_m4"; - - aliases { - uart-6 = &uart6; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart6; - zephyr,shell-uart = &uart6; - }; -}; - -&uart2 { - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&uart5 { - pinctrl-0 = <&uart5_default>; - pinctrl-names = "default"; -}; - -&uart6 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart6_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - pinctrl-0 = <&i2c4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/pico_pi_m4/pico_pi_m4.yaml b/boards/arm/pico_pi_m4/pico_pi_m4.yaml deleted file mode 100644 index 8cc013a4e361af..00000000000000 --- a/boards/arm/pico_pi_m4/pico_pi_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2019, Joris Offouga -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: pico_pi_m4 -name: Pico-Pi IMX7D -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -vendor: nxp diff --git a/boards/arm/pico_pi_m4/pico_pi_m4_defconfig b/boards/arm/pico_pi_m4/pico_pi_m4_defconfig deleted file mode 100644 index d2e77138089ea0..00000000000000 --- a/boards/arm/pico_pi_m4/pico_pi_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2019, Joris Offouga -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_PICO_PI_M4=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_GPIO=n -CONFIG_PINCTRL=y diff --git a/boards/arm/pinetime_devkit0/Kconfig.board b/boards/arm/pinetime_devkit0/Kconfig.board deleted file mode 100644 index 7b4cd93e7181b4..00000000000000 --- a/boards/arm/pinetime_devkit0/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# PineTime DevKit0 board configuration - -# Copyright (c) 2020 Stephane Dorre -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PINETIME_DEVKIT0 - bool "PineTime DevKit0" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/pinetime_devkit0/Kconfig.defconfig b/boards/arm/pinetime_devkit0/Kconfig.defconfig deleted file mode 100644 index a90333d54a79f0..00000000000000 --- a/boards/arm/pinetime_devkit0/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# PineTime DevKit0 board configuration - -# Copyright (c) 2020 Stephane Dorre -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PINETIME_DEVKIT0 - -config BOARD - default "pinetime_devkit0" - -config BT_CTLR - default BT - -config INPUT - default y if LVGL - -if FLASH - -config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 - -endif # FLASH - -endif # BOARD_PINETIME_DEVKIT0 diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0_defconfig b/boards/arm/pinetime_devkit0/pinetime_devkit0_defconfig deleted file mode 100644 index ce594faf969cf4..00000000000000 --- a/boards/arm/pinetime_devkit0/pinetime_devkit0_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_PINETIME_DEVKIT0=y - -CONFIG_ARM_MPU=y - -CONFIG_GPIO=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/pinnacle_100_dvk/Kconfig.board b/boards/arm/pinnacle_100_dvk/Kconfig.board deleted file mode 100644 index adbb23e41d8683..00000000000000 --- a/boards/arm/pinnacle_100_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Pinnacle(TM) 100 DVK board configuration -# -# Copyright (c) 2020 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PINNACLE_100_DVK - bool "Pinnacle 100 DVK" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/pinnacle_100_dvk/Kconfig.defconfig b/boards/arm/pinnacle_100_dvk/Kconfig.defconfig deleted file mode 100644 index e2496016997329..00000000000000 --- a/boards/arm/pinnacle_100_dvk/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# Pinnacle(TM) 100 DVK board configuration - -# Copyright (c) 2019 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PINNACLE_100_DVK - -config BOARD - default "pinnacle_100_dvk" - -config MODEM - default NETWORKING - -config MODEM_HL7800 - default NETWORKING - -config NORDIC_QSPI_NOR - default BOOTLOADER_MCUBOOT - -config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE - default 4096 if NORDIC_QSPI_NOR - -config BT_CTLR - default BT - -endif # BOARD_PINNACLE_100_DVK diff --git a/boards/arm/pinnacle_100_dvk/doc/index.rst b/boards/arm/pinnacle_100_dvk/doc/index.rst deleted file mode 100644 index 528b0f731f5e6e..00000000000000 --- a/boards/arm/pinnacle_100_dvk/doc/index.rst +++ /dev/null @@ -1,220 +0,0 @@ -.. _pinnacle_100_dvk: - -Laird Connectivity Pinnacle 100 DVK -################################### - -Overview -******** -The Pinnacle™ 100 cellular modem seamlessly incorporates a powerful Cortex M4F -controller, full Bluetooth 5 and LTE-M/NB-IoT capabilities – all with full -regulatory certifications and LTE carrier approvals. The Pinnacle 100 also -delivers complete antenna flexibility, with pre-integrated internal or external -antenna options such as the Revie Flex family of LTE and NB-IoT -internal antennas. - -Develop your application directly on the M4F controller using Zephyr RTOS to -cut BOM costs and power consumption. Take advantage of the Zephyr community, -Laird Connectivity’s sample code (cellular, Bluetooth) and hardware interfaces, -or use our hosted mode AT commands set firmware. - -Extremely power conscious, the Pinnacle 100 is ideal for battery-powered -devices operating at the edge of your IoT networks, seamlessly bridging the -cellular WAN to BLE. It’s never been easier to bridge wireless -Bluetooth 5 sensor data to cloud services like AWS IoT over a -low-power LTE connection. - -More information about the board can be found at the `Pinnacle 100 website`_. - -The Pinnacle 100 Development Kit (453-00010-K1 or 453-00011-K1) hardware -provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU, `Sierra Wireless HL7800`_ (Altair ALT1250) -and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* :abbr:`BME680 (Bosch Sensortec BME680 environmental sensor)` -* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` - -.. figure:: img/pinnacle_100_dvk.jpg - :align: center - :alt: Pinnacle 100 DVK - - Pinnacle 100 DVK (453-00010-K1) - -Hardware -******** - -Supported Features -================== - -The Pinnacle 100 development board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| QSPI | on-chip | qspi/MX25R64(8MB) | -+-----------+------------+----------------------+ -| BME680 | I2C(M) | sensor/bme680 | -+-----------+------------+----------------------+ -| HL7800 | UART | HL7800 modem driver | -+-----------+------------+----------------------+ - -See `Pinnacle 100 website`_ for a complete list -of Pinnacle 100 Development Kit hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (blue) = P1.4 -* LED2 (green) = P1.5 -* LED3 (red) = P1.6 -* LED4 (green) = P1.7 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.31 -* BUTTON2 = SW2 = P0.3 -* BUTTON3 = SW3 = P0.4 -* BUTTON4 = SW4 = P0.2 -* NRF RESET = SW5 = reset - -Programming and Debugging -************************* - -Applications for the ``pinnacle_100_dvk`` board configuration can be -built and flashed in the usual way. (see :ref:`build_an_application` -and :ref:`application_run` for more details) - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. note:: On the Pinnacle 100 development board, - the FTDI USB should be used to access the UART console. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board Pinnacle 100 DVK -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: pinnacle_100_dvk - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Software -******** - -Pinnacle 100 Out-of-Box Demo Software -===================================== -The Pinnacle 100 development kit ships with an out of the box software demo. -Check out the `Pinnacle 100 OOB Demo`_ source code and documentation. - -Sample Applications -=================== -`Pinnacle 100 Sample Applications`_ are available. - -Testing Bluetooth on the Pinnacle 100 DVK -========================================= -Many of the Bluetooth examples will work on the Pinnacle 100 DVK. -Try them out: - -* :ref:`ble_peripheral` -* :ref:`bluetooth-eddystone-sample` -* :ref:`bluetooth-ibeacon-sample` - -Testing the LEDs and buttons in the Pinnacle 100 DVK -==================================================== - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts`. - -References -********** - -.. target-notes:: - -.. _Pinnacle 100 website: https://www.lairdconnect.com/wireless-modules/cellular-solutions/pinnacle-100-cellular-modem -.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf -.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _Pinnacle 100 OOB Demo: https://github.com/LairdCP/Pinnacle_100_oob_demo -.. _Pinnacle 100 Sample Applications: https://github.com/LairdCP/Pinnacle_100_Sample_Applications diff --git a/boards/arm/qemu_cortex_a9/Kconfig.board b/boards/arm/qemu_cortex_a9/Kconfig.board deleted file mode 100644 index c8fcdf1ccdb383..00000000000000 --- a/boards/arm/qemu_cortex_a9/Kconfig.board +++ /dev/null @@ -1,11 +0,0 @@ -# -# Kconfig - Cortex-A9 QEMU Emulation -# -# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_QEMU_CORTEX_A9 - bool "Cortex-A9 Emulation (QEMU)" - depends on SOC_XILINX_XC7Z007S - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_a9/Kconfig.defconfig b/boards/arm/qemu_cortex_a9/Kconfig.defconfig deleted file mode 100644 index 09c6afaae64cf2..00000000000000 --- a/boards/arm/qemu_cortex_a9/Kconfig.defconfig +++ /dev/null @@ -1,80 +0,0 @@ -# -# Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation -# -# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_QEMU_CORTEX_A9 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_cortex_a9" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 111111111 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -if LOG - - if LOG_PROCESS_THREAD - - config LOG_PROCESS_THREAD_STACK_SIZE - default 8192 - - endif # LOG_PROCESS_THREAD - -endif # LOG - -if NETWORKING - - config NET_L2_ETHERNET - default y - - config NET_TX_STACK_SIZE - default 8192 - - config NET_RX_STACK_SIZE - default 8192 - - if NET_TCP - - config NET_TCP_WORKQ_STACK_SIZE - default 8192 - - endif # NET_TCP - - if NET_MGMT_EVENT - - config NET_MGMT_EVENT_STACK_SIZE - default 8192 - - endif # NET_MGMT_EVENT - - config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -if QEMU_ICOUNT - - config QEMU_ICOUNT_SHIFT - default 3 - config QEMU_ICOUNT_SLEEP - default y - -endif # QEMU_ICOUNT - -if SHELL - - config SHELL_STACK_SIZE - default 8192 - -endif # SHELL - -endif # BOARD_QEMU_CORTEX_A9 diff --git a/boards/arm/qemu_cortex_a9/board.cmake b/boards/arm/qemu_cortex_a9/board.cmake deleted file mode 100644 index 3aad89a09ce63c..00000000000000 --- a/boards/arm/qemu_cortex_a9/board.cmake +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_ARCH xilinx-aarch64) - -set(QEMU_CPU_TYPE_${ARCH} cortex-a9) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine arm-generic-fdt-7series - -dtb ${ZEPHYR_BASE}/boards/${ARCH}/${BOARD}/fdt-zynq7000s.dtb - ) - -set(QEMU_KERNEL_OPTION - "-device;loader,file=\$,cpu-num=0" - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/qemu_cortex_m0/Kconfig b/boards/arm/qemu_cortex_m0/Kconfig deleted file mode 100644 index 3dcbf4298dd86f..00000000000000 --- a/boards/arm/qemu_cortex_m0/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config NRF_TIMER_TIMER - bool "nRF Timer Counter (NRF_TIMER0) Timer" - depends on CLOCK_CONTROL - depends on SOC_COMPATIBLE_NRF - depends on SYS_CLOCK_EXISTS - select TICKLESS_CAPABLE - default y - help - This module implements a kernel device driver for the nRF Timer - Counter NRF_TIMER0 and provides the standard "system clock driver" - interfaces. diff --git a/boards/arm/qemu_cortex_m0/Kconfig.board b/boards/arm/qemu_cortex_m0/Kconfig.board deleted file mode 100644 index 8a6473d852164c..00000000000000 --- a/boards/arm/qemu_cortex_m0/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# QEMU Cortex-M0 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_M0 - bool "Cortex-M0 Emulation (QEMU)" - depends on SOC_NRF51822_QFAA - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_m0/Kconfig.defconfig b/boards/arm/qemu_cortex_m0/Kconfig.defconfig deleted file mode 100644 index 3f203f2adbc5cc..00000000000000 --- a/boards/arm/qemu_cortex_m0/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# QEMU Cortex-M0 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_M0 - -config BOARD - default "qemu_cortex_m0" - -config NRF_RTC_TIMER - default n if SYS_CLOCK_EXISTS - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 100 - -endif # BOARD_QEMU_CORTEX_M0 diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0_defconfig b/boards/arm/qemu_cortex_m0/qemu_cortex_m0_defconfig deleted file mode 100644 index a169a86f8de4b3..00000000000000 --- a/boards/arm/qemu_cortex_m0/qemu_cortex_m0_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAA=y -CONFIG_BOARD_QEMU_CORTEX_M0=y -CONFIG_QEMU_ICOUNT_SHIFT=6 - -# enable GPIO -CONFIG_GPIO=y - -# clock control -CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# icount is kinda broken when the NRF timer emulation is used -CONFIG_QEMU_ICOUNT=n diff --git a/boards/arm/qemu_cortex_m3/Kconfig.board b/boards/arm/qemu_cortex_m3/Kconfig.board deleted file mode 100644 index 6322724df89286..00000000000000 --- a/boards/arm/qemu_cortex_m3/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_M3 - bool "Cortex-M3 Emulation (QEMU)" - depends on SOC_TI_LM3S6965 - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_m3/Kconfig.defconfig b/boards/arm/qemu_cortex_m3/Kconfig.defconfig deleted file mode 100644 index bfbda98cb73ecb..00000000000000 --- a/boards/arm/qemu_cortex_m3/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_M3 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_cortex_m3" - -# DWT is not properly emulated in QEMU -choice NULL_POINTER_EXCEPTION_DETECTION - bool - default NULL_POINTER_EXCEPTION_DETECTION_NONE -endchoice - -endif # BOARD_QEMU_CORTEX_M3 diff --git a/boards/arm/qemu_cortex_m3/board.cmake b/boards/arm/qemu_cortex_m3/board.cmake deleted file mode 100644 index 51f04bfd2dc14e..00000000000000 --- a/boards/arm/qemu_cortex_m3/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} cortex-m3) -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -machine lm3s6965evb - -nographic - -vga none - ) -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/qemu_cortex_r5/Kconfig.board b/boards/arm/qemu_cortex_r5/Kconfig.board deleted file mode 100644 index 9824aeb5bc1e1c..00000000000000 --- a/boards/arm/qemu_cortex_r5/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_R5 - bool "Cortex-R5 Emulation (QEMU)" - depends on SOC_XILINX_ZYNQMP_RPU - select QEMU_TARGET diff --git a/boards/arm/qemu_cortex_r5/Kconfig.defconfig b/boards/arm/qemu_cortex_r5/Kconfig.defconfig deleted file mode 100644 index 9cac36e1ee6b93..00000000000000 --- a/boards/arm/qemu_cortex_r5/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_R5 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_cortex_r5" - -if USERSPACE - -config COMPILER_ISA_THUMB2 - default n - -endif - -endif # BOARD_QEMU_CORTEX_R5 diff --git a/boards/arm/qemu_cortex_r5/board.cmake b/boards/arm/qemu_cortex_r5/board.cmake deleted file mode 100644 index 7ac21d345c9952..00000000000000 --- a/boards/arm/qemu_cortex_r5/board.cmake +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_ARCH xilinx-aarch64) - -set(QEMU_CPU_TYPE_${ARCH} cortex-r5) -set(QEMU_FLAGS_${ARCH} - -nographic - -machine arm-generic-fdt - -dtb ${ZEPHYR_BASE}/boards/${ARCH}/${BOARD}/fdt-single_arch-zcu102-arm.dtb - ) - -set(QEMU_KERNEL_OPTION - "-device;loader,file=\$,cpu-num=4" - "-device;loader,addr=0xff5e023c,data=0x80008fde,data-len=4" - "-device;loader,addr=0xff9a0000,data=0x80000218,data-len=4" - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm/qomu/Kconfig.board b/boards/arm/qomu/Kconfig.board deleted file mode 100644 index fd1caf385d2b1d..00000000000000 --- a/boards/arm/qomu/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# QuickLogic Qomu board - -# Copyright (c) 2022 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QOMU - bool "QuickLogic Qomu target" - depends on SOC_EOS_S3 diff --git a/boards/arm/qomu/Kconfig.defconfig b/boards/arm/qomu/Kconfig.defconfig deleted file mode 100644 index 31125f4f62f1a8..00000000000000 --- a/boards/arm/qomu/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# QuickLogic Qomu board - -# Copyright (c) 2022 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QOMU - -config BOARD - default "qomu" - -endif # BOARD_QOMU diff --git a/boards/arm/quick_feather/Kconfig.board b/boards/arm/quick_feather/Kconfig.board deleted file mode 100644 index e85b49bc4e48ad..00000000000000 --- a/boards/arm/quick_feather/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Quick Feather board - -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QUICK_FEATHER - bool "QuickLogic Quick Feather target" - depends on SOC_EOS_S3 diff --git a/boards/arm/quick_feather/Kconfig.defconfig b/boards/arm/quick_feather/Kconfig.defconfig deleted file mode 100644 index cf328e50b1b3ea..00000000000000 --- a/boards/arm/quick_feather/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# QuickLogic Quick Feather board - -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QUICK_FEATHER - -config BOARD - default "quick_feather" - -endif # BOARD_QUICK_FEATHER diff --git a/boards/arm/quick_feather/doc/index.rst b/boards/arm/quick_feather/doc/index.rst deleted file mode 100644 index dd79c8c8f74d67..00000000000000 --- a/boards/arm/quick_feather/doc/index.rst +++ /dev/null @@ -1,125 +0,0 @@ -.. _quickfeather: - -QuickFeather -############ - -Overview -******** - -The QuickFeather development board is a platform with an on-board QuickLogic -EOS S3 Sensor Processing Platform. - - -.. figure:: img/feather-board.jpg - :align: center - :alt: QuickFeather - - QuickFeather (Credit: QuickLogic) - -Hardware -******** - -- QuickLogic EOS S3 MCU Platform -- mCube MC3635 accelerometer -- Infineon DPS310 pressure sensor -- Infineon IM69D130 MEMS microphone -- 16 Mbit of on-board flash memory -- User button -- RGB LED -- Integrated battery charger - -Detailed information about the board can be found in a `QuickFeather repository`_. - -Supported Features -================== - -The QuickFeather configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/quick_feather/quick_feather_defconfig`. - -Connections and IOs -=================== - -Detailed information about pinouts is available in the `schematics document`_. - -Programming and Debugging -************************* - -Flashing -======== - -The QuickFeather platform by default boots from flash. Currently -the Zephyr port only enables loading the program directly to SRAM using either -OpenOCD and a SWD programmer or SEGGER JLink. - -OpenOCD -------- - -In order to connect to the target a SWD programmer supported in -OpenOCD is needed. To connect to the board run: - -.. code-block:: console - - openocd -f /path/to/swd-programmer.cfg -f tcl/board/quicklogic_quickfeather.cfg -c "init" -c "reset halt" - -`The QuickFeather OpenOCD config`_ can be found in the OpenOCD mainline repository. - -JLink ------ - -To connect to the QuickFeather board with JLink please follow instructions -in the `QuickFeather User Guide`_. - -Debugging -========= - -To debug the QuickFeather board please connect to the target with either -OpenOCD or JLink and use GDB distributed in Zephyr's SDK in *arm-zephyr-eabi/bin* -directory. - -To load basic sample via GDB: - -- Build the sample in an usual way: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: quick_feather - :goals: build - -- Connect to the target using either OpenOCD or JLink -- Connect via GDB and load an ELF file: - -.. code-block:: console - - /path/to/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-gdb - target remote - file - load - continue - -References -********** - -.. target-notes:: - -.. _QuickFeather repository: - https://github.com/QuickLogic-Corp/quick-feather-dev-board - -.. _schematics document: - https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/quickfeather-board.pdf - -.. _The QuickFeather OpenOCD config: - https://sourceforge.net/p/openocd/code/ci/master/tree/tcl/board/quicklogic_quickfeather.cfg - -.. _QuickFeather User Guide: - https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/QuickFeather_UserGuide.pdf diff --git a/boards/arm/rak4631_nrf52840/Kconfig.board b/boards/arm/rak4631_nrf52840/Kconfig.board deleted file mode 100644 index f5db017218979e..00000000000000 --- a/boards/arm/rak4631_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# RAKWIRELESS RAK4631 selection - -# Copyright (c) 2021 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAK4631_NRF52840 - bool "RAK4631 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/rak4631_nrf52840/Kconfig.defconfig b/boards/arm/rak4631_nrf52840/Kconfig.defconfig deleted file mode 100644 index 10a6070f95b685..00000000000000 --- a/boards/arm/rak4631_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# RAKWIRELESS RAK4631 Board configuration - -# Copyright (c) 2021 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAK4631_NRF52840 - -config BOARD - default "rak4631_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_RAK4631_NRF52840 diff --git a/boards/arm/rak4631_nrf52840/doc/index.rst b/boards/arm/rak4631_nrf52840/doc/index.rst deleted file mode 100644 index e25593816d5b50..00000000000000 --- a/boards/arm/rak4631_nrf52840/doc/index.rst +++ /dev/null @@ -1,155 +0,0 @@ -.. _rak4631_nrf52840: - -RAK4631 -####### - -Overview -******** - -RAK4631 is a WisBlock Core module for RAK WisBlock. -It extends the WisBlock series with a powerful -Nordic nRF52840 MCU that supports Bluetooth 5.0 -(Bluetooth Low Energy) and the newest LoRa transceiver -from Semtech, the SX1262. The Semtech SX1262 has compared -to the older SX127x series a lower power consumption at -the same TX power. This makes the RAK4631 an ultra-low -power communication solution. RAK4631 can be comfortably -programmed with ZephyrRTOS. - -.. image:: img/rak4631-front-parts.jpg - :align: center - :alt: RAK4631-NRF52840 - -Hardware -******** - -To use a RAK4631, you need at least a WisBlock Base -to plug the module in. WisBlock Base is the power -supply for the RAK4631 module and has the -programming/debug interface. - -- nRF52840 ARM Cortex-M4F Processor -- 64 MHz CPU clock -- 1 Micro-AB USB OTG host/device -- Semtech SX1262 low power high range LoRa transceiver -- iPEX connectors for the LORA antenna and BLE antenna. -- Multiple interfaces, I2C, UART, GPIO, ADC -- 2 user LEDs on RAK5005 mother Board -- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port - -Supported Features -================== - -The rak4631_nrf52840 board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RADIO | on-board | LoRa (SX1262) | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The default board configuration can be found in the defconfig file: - - ``boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig`` - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P1.3 -* LED2 (blue) = P1.4 - -Programming and Debugging -************************* - -The RAK4631 board shall be connected to a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the NRF52840 chip. You can use JLink to communicate with -the NRF52840. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the RAK4631 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak4631_nrf52840 - :goals: build flash - - You should see "Hello World! rak4631_nrf52840" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak4631_nrf52840 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _RAK4631 Product Description: - https://docs.rakwireless.com/Product-Categories/WisBlock/RAK4631/Datasheet/#overview - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/rak5010_nrf52840/Kconfig.board b/boards/arm/rak5010_nrf52840/Kconfig.board deleted file mode 100644 index c5a5ab2d3a1e30..00000000000000 --- a/boards/arm/rak5010_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# RAKWIRELESS RAK5010 selection - -# Copyright (c) 2020 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAK5010_NRF52840 - bool "RAK5010 DK NRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/rak5010_nrf52840/Kconfig.defconfig b/boards/arm/rak5010_nrf52840/Kconfig.defconfig deleted file mode 100644 index 2361185f0f79eb..00000000000000 --- a/boards/arm/rak5010_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# RAKWIRELESS RAK5010 Board configuration - -# Copyright (c) 2020 Guillaume Paquet -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAK5010_NRF52840 - -config BOARD - default "rak5010_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_RAK5010_NRF52840 diff --git a/boards/arm/rak5010_nrf52840/doc/index.rst b/boards/arm/rak5010_nrf52840/doc/index.rst deleted file mode 100644 index 9ca09035d009bb..00000000000000 --- a/boards/arm/rak5010_nrf52840/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _rak5010_nrf52840: - -RAK5010 -####### - -Overview -******** - -WisTrio NB-IoT Tracker Pro (RAK5010) is a tracker -with integrated LTE CAT M1 & NB1, GPS, BLE, and sensors. -It is built on the Quectel BG96 LTE CAT M1 & NB1 module, -which has an integrated GPS receiver. The MCU running -the board is a Nordic nRF52840 controller. - -As it has both GPS and BLE it can be used for outdoor -and indoor scenarios, where location-based services need be present. - -The built-in sensors for RAK5010 are temperature and -humidity sensor, motion sensor, pressure sensor, and light sensor. -The extension IOs allow adding more sensors in addition to the on-board ones. - -This board is particularly suitable to be used as a -quick testing and prototyping tool for applications -requiring NB-IoT connectivity. Application development -supports the GCC environment. - -.. image:: img/rak5010-front-parts.jpg - :align: center - :alt: RAK5010-NRF52840 - -Hardware -******** - -- nRF52840 ARM Cortex-M4F Processor -- 32.768 kHz crystal oscillator -- 1 Micro-AB USB OTG host/device -- Quectel BG96, with LTE CAT M1, LTE NB1, and GNSS -- iPEX connectors for the LTE and GPS antenna and an on-board ceramic antenna for the BLE. -- nano-SIM and ESIM options. -- Multiple interfaces, I2C, UART, GPIO, ADC -- 1 user LED -- 1 SHTC3 Humidity and Temperature Sensor -- 1 OPT3001DNPR Ambient Light Sensor -- 1 LPS22HB Pressure Sensor -- 1 LIS3DH Motion Sensor -- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port - -Supported Features -================== - -The rak5010_nrf52840 board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -LED ---- - -* LED0 (green) = P0.12 - - -Programming and Debugging -************************* - -The RAK5010 board shall be connected to a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the NRF52840 chip. You can use JLink to communicate with -the NRF52840. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the RAK5010 board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak5010_nrf52840 - :goals: build flash - - You should see "Hello World! rak5010_nrf52840" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rak5010_nrf52840 - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _RAK5010 Product Description: - https://doc.rakwireless.com/datasheet/rakproducts/rak5010-wistrio-nb-iot-tracker-datasheet - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig b/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig deleted file mode 100644 index 2c11d6d2f795fb..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Raytac MDBT50Q-DB-33 nRF52833 board configuration - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833 diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.board b/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.board deleted file mode 100644 index 9bea6b03f4f43e..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Raytac MDBT50Q-DB-33 nRF52833 board configuration - -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833 - bool "Raytac MDBT50Q-DB-33 nRF52833" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.defconfig b/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.defconfig deleted file mode 100644 index ebb90a80bfa673..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Raytac MDBT50Q-DB-33 NRF52833 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833 - -config BOARD - default "raytac_mdbt50q_db_33_nrf52833" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/index.rst b/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/index.rst deleted file mode 100644 index 84c241a799aa74..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/index.rst +++ /dev/null @@ -1,213 +0,0 @@ -.. _raytac_mdbt50q_db_33_nrf52833: - -Raytac MDBT50Q-DB-33 -#################### - -Overview -******** - -The Raytac MDBT50Q-DB-33 hardware provides support for the -Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/mdbt50q_db_33.jpg - :width: 442px - :align: center - :alt: MDBT50Q-DB-33 - -More information about the board can be found at the `MDBT50Q-DB-33 website`_. -The `MDBT50Q-DB-33 Specification`_ contains the demo board's datasheet. -The `MDBT50Q-DB-33 Schematic`_ contains the demo board's schematic. - -Hardware -******** -- Module Demo Board build by MDBT50Q-512K -- Nordic nRF52833 SoC Solution -- A recommnded 3rd-party module by Nordic Semiconductor. -- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified -- Supports BT5 Long Range Features -- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC -- 32-bit ARM® Cortex™ M4F CPU -- 512kB Flash Memory/128kB RAM -- RoHs & Reach Compiant. -- 42 GPIO -- Chip Antenna -- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB -- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. -- 3 User LEDs -- 4 User buttons -- 1 Mini USB connector for power supply and USB communication -- SWD connector for FW programing -- J-Link interface for FW programing -- UART interface for UART communication - -Supported Features -================== - -The raytac_mdbt50q_db_33_nrf52833 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `MDBT50Q-DB-33 website`_ and `MDBT50Q-DB-33 Specification`_ -for a complete list of Raytac MDBT50Q-DB-33 board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (red) = P0.14 -* LED3 (blue) = P0.15 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 - -UART ----- -* RXD = P0.08 -* TXD = P0.06 -* RTS = P0.05 -* CTS = P0.07 - -Programming and Debugging -************************* - -Applications for the ``raytac_mdbt50q_db_33_nrf52833`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -.. note:: - Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_33_nrf52833 board - requires an external J-Link programmer. The programmer is attached to the J1 - or J9 SWD connector. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_33_nrf52833 -J10 connector. Then run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the USB to TTL converter -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: raytac_mdbt50q_db_33_nrf52833 - :goals: build flash - -Debugging -========= - -The ``raytac_mdbt50q_db_33_nrf52833`` board does not have an on-board-J-Link debug IC, -however, instructions from the :ref:`nordic_segger` page also apply to this board. -Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER -J-Link OB IF to debug. - -Testing the LEDs and buttons in the Raytac MDBT50Q-DB-33 -******************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.dts`. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `MDBT50Q-DB-33 Specification`_, chapter 2.5 'Pin Assignment'. -Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O -only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, -UART, and PWM. - -References -********** - -.. target-notes:: - -.. _MDBT50Q-DB-33 website: - https://www.raytac.com/product/ins.php?index_id=97 -.. _MDBT50Q-DB-33 Specification: - https://www.raytac.com/download/index.php?index_id=46 -.. _MDBT50Q-DB-33 Schematic: - https://www.raytac.com/upload/catalog_b/407c1150fa33511a47e8a2f85d106ff3.jpg -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig b/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig deleted file mode 100644 index bab7358485d5f9..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Raytac MDBT50Q-DB-40 nRF52840 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.board b/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.board deleted file mode 100644 index 9384b2743c8627..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Raytac MDBT50Q-DB-40 nRF52840 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 - bool "Raytac MDBT50Q_DB_40_nRF52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.defconfig b/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.defconfig deleted file mode 100644 index 12044d8e4855b6..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Raytac MDBT50Q-DB-40 NRF52840 board configuration - -# Copyright (c) 2022 Raytac Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840 - -config BOARD - default "raytac_mdbt50q_db_40_nrf52840" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/index.rst b/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/index.rst deleted file mode 100644 index 99b57d2200212b..00000000000000 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _raytac_mdbt50q_db_40_nrf52840: - -Raytac MDBT50Q-DB-40 -#################### - -Overview -******** - -The Raytac MDBT50Q-DB-40 hardware provides support for the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/mdbt50q_db_40.jpg - :width: 442px - :align: center - :alt: MDBT50Q-DB-40 - -More information about the board can be found at the `MDBT50Q-DB-40 website`_. -The `MDBT50Q-DB-40 Specification`_ contains the demo board's datasheet. -The `MDBT50Q-DB-40 Schematic`_ contains the demo board's schematic. - -Hardware -******** -- Module Demo Board build by MDBT50Q-1MV2 -- Nordic nRF52840 SoC Solution Version: 2 -- A recommnded 3rd-party module by Nordic Semiconductor. -- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified -- Supports BT5 Long Range Features -- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC -- 32-bit ARM® Cortex™ M4F CPU -- 1MB Flash Memory/256kB RAM -- RoHs & Reach Compiant. -- 48 GPIO -- Chip Antenna -- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB -- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. -- 3 User LEDs -- 4 User buttons -- 1 Mini USB connector for power supply and USB communication -- SWD connector for FW programing -- J-Link interface for FW programing -- UART interface for UART communication - -Supported Features -================== - -The raytac_mdbt50q_db_40_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | qspi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `MDBT50Q-DB-40 website`_ and `MDBT50Q-DB-40 Specification`_ -for a complete list of Raytac MDBT50Q-DB-40 board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.13 -* LED2 (red) = P0.14 -* LED3 (blue) = P0.15 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 - -UART ----- -* RXD = P0.08 -* TXD = P0.06 -* RTS = P0.05 -* CTS = P0.07 - -Programming and Debugging -************************* - -Applications for the ``raytac_mdbt50q_db_40_nrf52840`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -.. note:: - Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_40_nrf52840 board - requires an external J-Link programmer. The programmer is attached to the J1 - or J9 SWD connector. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_40_nrf52840 -J10 connector. Then run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the USB to TTL converter -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: raytac_mdbt50q_db_40_nrf52840 - :goals: build flash - -Debugging -========= - -The ``raytac_mdbt50q_db_40_nrf52840`` board does not have an on-board-J-Link debug IC, -however, instructions from the :ref:`nordic_segger` page also apply to this board. -Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER -J-Link OB IF to debug. - -Testing the LEDs and buttons in the MDBT50Q-DB-40 -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.dts`. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the `MDBT50Q-DB-40 Specification`_, chapter 2.5 'Pin Assignment'. -Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O -only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, -UART, and PWM. - -References -********** - -.. target-notes:: - -.. _MDBT50Q-DB-40 website: - https://www.raytac.com/product/ins.php?index_id=81 -.. _MDBT50Q-DB-40 Specification: - https://www.raytac.com/download/index.php?index_id=43 -.. _MDBT50Q-DB-40 Schematic: - https://www.raytac.com/upload/catalog_b/134ade06b5db3dd5803d27c5b17f22f3.jpg -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/CMakeLists.txt b/boards/arm/raytac_mdbt53_db_40_nrf5340/CMakeLists.txt deleted file mode 100644 index 6a13dbb534e790..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(raytac_mdbt53_db_40_nrf5340_cpunet_reset.c) -endif() diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig deleted file mode 100644 index caf06f347d5f64..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# Ratac MDBT53-DB-40 nRF5340 board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "raytac_mdbt53_db_40_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "raytac_mdbt53_db_40_nrf5340_cpuapp" - depends on BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.board b/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.board deleted file mode 100644 index ff4b1ac698623c..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Raytac MDBT53-DB-40 NRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP - bool "Raytac MDBT53-DB-40 nRF5340 Application MCU" - -config BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - bool "Raytac MDBT53-DB-40 nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - bool "Raytac MDBT53-DB-40 NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.defconfig deleted file mode 100644 index fb5a6b85630628..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# Raytac MDBT53-DB-40 nRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53_db_40_nrf5340_cpuapp" - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53_dv_40_nrf5340_cpunet" if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS - -if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/board.cmake b/boards/arm/raytac_mdbt53_db_40_nrf5340/board.cmake deleted file mode 100644 index 8657aa50f1c089..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/index.rst b/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/index.rst deleted file mode 100644 index bcff494f91b1b4..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/index.rst +++ /dev/null @@ -1,271 +0,0 @@ -.. _raytac_mdbt53_db_40_nrf5340: - -Raytac MDBT53-DB-40 -################### - -Overview -******** - -Raytac MDBT53-DB-40 demo board is a development board based on the Raytac MDBT53-1M module, -using Nordic Semiconductor nRF5340 ARM Cortex-M33 SoC. Its design concept is to connect all -of the module's pins to 2.54mm pin headers. It is convenient for developers to verify whether -the modules are connected to other peripheral devices or sensors as a tool for software development. - -The nRF5340 inside the MDBT53-1M module is a -dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running - at a fixed 64 MHz, referred to as the **network core**. - -The raytac_mdbt53_db_40_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The raytac_mdbt53_db_40_nrf5340_cpuapp build target provides -support for the network core on the nRF5340 SoC. - -nRF5340 SoC provides support for the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`QSPI (Quad Serial Peripheral Interface)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/MDBT53-DB-40.jpg - :width: 442px - :align: center - :alt: MDBT53-DB-40 - - MDBT53-DB-40 (Credit: Raytac Corporation) - -More information about the board can be found at the `MDBT53-DB-40 website`_. -The `MDBT53-DB-40 Specification`_ contains the demo board's datasheet. -The `MDBT53-DB-40 Schematic`_ contains the demo board's schematic. - -Hardware -******** -- Module Demo Board build by MDBT53-1M -- Nordic nRF5340 SoC Solution -- A recommnded 3rd-party module by Nordic Semiconductor. -- Dual-core Arm® Cortex® M33 -- 1MB/256KB Flash Memory; 512kB/ 64kB RAM -- Supports BT5 Long Range Features -- Bluetooth specification v5.2 -- Supports Bluetooth Direction Finding & Mesh -- Supports Bluetooth low energy audio -- Certifications: FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC -- RoHs & Reach Compiant. -- 48 GPIO -- Chip Antenna -- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB -- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. -- 4 User LEDs -- 4 User buttons -- 1 Mini USB connector for power supply -- SWD connector for FW programing -- J-Link interface for FW programing -- UART interface for UART communication - -Supported Features -================== - -The raytac_mdbt53_db_40_nrf52840_cpuapp board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| QSPI(M) | on-chip | nor | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| SPU | on-chip | system protection | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -The raytac_mdbt53_db_40_nrf5340_cpunet board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UARTE | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `MDBT53-DB-40 website`_ and `MDBT53-DB-40 Specification`_ -for a complete list of Raytac MDBT53-DB-40 board hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (green) = P0.28 -* LED2 (red) = P0.30 -* LED3 = P0.31 -* LED4 = P0.29 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.24 -* BUTTON2 = SW2 = P0.08 -* BUTTON3 = SW3 = P0.23 -* BUTTON4 = SW4 = P0.09 - -UART ----- -* RX = P0.22 -* TX = P0.20 -* RTS = P0.19 -* CTS = P0.21 - - -Security components -=================== - -- Implementation Defined Attribution Unit (`IDAU`_) on the application core. - The IDAU is implemented with the System Protection Unit and is used to - define secure and non-secure memory maps. By default, all of the memory - space (Flash, SRAM, and peripheral address space) is defined to be secure - accessible only. -- Secure boot. - -Programming and Debugging -************************* - -nRF5340 application core supports the Armv8-M Security Extension. -Applications built for the raytac_mdbt53_db_40_nrf5340_cpuapp board by -default boot in the Secure state. - -nRF5340 network core does not support the Armv8-M Security Extension. -nRF5340 IDAU may configure bus accesses by the nRF5340 network core -to have Secure attribute set; the latter allows to build and run -Secure only applications on the nRF5340 SoC. - -Applications for the ``raytac_mdbt53_db_40_nrf5340`` board configuration can be -built, flashed, and debugged in the usual way. See :ref:`build_an_application` and -:ref:`application_run` for more details on building and running. - -.. note:: - Flashing and Debugging Zephyr onto the raytac_mdbt53_db_40_nrf5340 board - requires an external J-Link programmer. The programmer is attached to the J1 - or J9 SWD connector. - - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. warning:: - - The nRF5340 has a flash read-back protection feature. When flash read-back - protection is active, you will need to recover the chip before reflashing. - If you are flashing with :ref:`west `, run - this command for more details on the related ``--recover`` option: - -Here is an example for the :ref:`hello_world` application. - -Use a USB to TTL converter to connect the computer and raytac_mdbt53_db_40_nrf5340 -J10 connector. Then run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the USB to TTL converter -can be found. For example, under Linux, :code:`/dev/ttyUSB0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: raytac_mdbt53_db_40_nrf5340 - :goals: build flash - -Debugging -========= - -The ``raytac_mdbt53_db_40_nrf5340`` board does not have an on-board-J-Link debug IC, -however, instructions from the :ref:`nordic_segger` page also apply to this board. -Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER -J-Link OB IF to debug. - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - - -References -********** - -.. _IDAU: - https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau -.. _MDBT53-DB-40 website: - https://www.raytac.com/product/ins.php?index_id=139 -.. _MDBT53-DB-40 Specification: - https://www.raytac.com/download/index.php?index_id=60 -.. _MDBT53-DB-40 Schematic: - https://www.raytac.com/upload/catalog_b/8b5e364600a9cc8c53a869733e97f07e.jpg -.. _J-Link Software and documentation pack: - https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig deleted file mode 100644 index cf048d3d213716..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig deleted file mode 100644 index e0759063b9ab46..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Enable GPIO -CONFIG_GPIO=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig b/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig deleted file mode 100644 index 92b1660131421a..00000000000000 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/CMakeLists.txt b/boards/arm/raytac_mdbt53v_db_40_nrf5340/CMakeLists.txt deleted file mode 100644 index 556e084598c42e..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if ((CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) - AND CONFIG_BOARD_ENABLE_CPUNET) - zephyr_library() - zephyr_library_sources(raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c) -endif() diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig deleted file mode 100644 index 02b44de6198a06..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# Ratac MDBT53V-DB-40 nRF5340 board configuration - -# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "raytac_mdbt53v_db_40_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config DOMAIN_CPUAPP_BOARD - string - default "raytac_mdbt53v_db_40_nrf5340_cpuapp" - depends on BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.board b/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.board deleted file mode 100644 index 69bb4b876ea797..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Raytac MDBT53-DB-40 NRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP - bool "Raytac MDBT53V-DB-40 nRF5340 Application MCU" - -config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - bool "Raytac MDBT53V-DB-40 nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -config BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - bool "Raytac MDBT53V-DB-40 NRF5340 Network MCU" - depends on SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.defconfig deleted file mode 100644 index fd3e5210d287b7..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,87 +0,0 @@ -# Raytac MDBT53V-DB-40 nRF5340 board configuration - -# Copyright (c) 2019-2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53v_db_40_nrf5340_cpuapp" if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -config BOARD - default "raytac_mdbt53v_dv_40_nrf5340_cpunet" if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - -config IPM_NRFX - default IPM - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS - -if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET - -config BT_CTLR - default y if BT - -endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/board.cmake b/boards/arm/raytac_mdbt53v_db_40_nrf5340/board.cmake deleted file mode 100644 index 8662675aba39f4..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) - board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET) - board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig deleted file mode 100644 index 6966d7d728c919..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig deleted file mode 100644 index 44e16cd65ac68c..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig b/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig deleted file mode 100644 index 94f21fb4c98181..00000000000000 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/rcar_h3_salvatorx/Kconfig.board b/boards/arm/rcar_h3_salvatorx/Kconfig.board deleted file mode 100644 index f0236267f08005..00000000000000 --- a/boards/arm/rcar_h3_salvatorx/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_H3_SALVATORX_CR7 - bool "Cortex-R7 for Renesas H3 Salvator-X" - depends on SOC_R8A77951 diff --git a/boards/arm/rcar_h3_salvatorx/Kconfig.defconfig b/boards/arm/rcar_h3_salvatorx/Kconfig.defconfig deleted file mode 100644 index ccc3ffa89a5535..00000000000000 --- a/boards/arm/rcar_h3_salvatorx/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_H3_SALVATORX_CR7 -config BOARD - default "rcar_h3_salvatorx_cr7" -endif # BOARD_RCAR_H3_SALVATORX_CR7 diff --git a/boards/arm/rcar_h3_salvatorx/doc/rcar_h3_salvatorx.rst b/boards/arm/rcar_h3_salvatorx/doc/rcar_h3_salvatorx.rst deleted file mode 100644 index d3b9b292867d96..00000000000000 --- a/boards/arm/rcar_h3_salvatorx/doc/rcar_h3_salvatorx.rst +++ /dev/null @@ -1,183 +0,0 @@ -.. _rcar_h3_salvatorx_boards: - -Renesas R-Car H3 Salvator-X -########################### - -Overview -******** -- The H3 Salvator-X board is designed for evaluating the features and performance - of the R-CAR H3 device from Renesas Electronics and it is also used for developing - and evaluating application software for these R-CAR H3. - -- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, - each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces - like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, - via 440pin connector on bottom side. - -.. figure:: img/rcar_h3_salvatorx.jpg - :align: center - :alt: R-Car Salvator-X kit - -More information about the board can be found at `Renesas R-Car Development Support website`_. - -Hardware -******** - -Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_ -of the board. - -.. figure:: img/rcar_h3_features.jpg - :align: center - :alt: R-Car Salvator-X features - -.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. - -More information about the SoC that equips the board can be found here: - -- `Renesas R-Car H3 chip`_ - -Supported Features -================== - -Here is the current supported features when running Zephyr Project on the R-Car Salvator-X CR7: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| GPIO | gpio | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+ + + + -| | FT232RQ / CP2102 | serial port-interrupt | -+-----------+------------------------------+--------------------------------+ -| CAN | can | normal mode | -+ + + + -| | TCAN332GDCNT | loopback mode | -+-----------+------------------------------+--------------------------------+ -| I2C | i2c | interrupt driven | -+-----------+------------------------------+--------------------------------+ - -It's also currently possible to write on the ram console. - -Connections and IOs -=================== - -.. figure:: img/r-car-h3-salvator-x-connections.jpg - :align: center - :alt: R-Car Salvator-X connections - -GPIO ----- - -By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', -'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', -'LED5', 'LED6' can be used as output. - -UART ----- - -Salvator-X board is providing two serial ports: - -- one is for A53/A57 processors -- the other one is for CR7 - -Both ports are converted to USB through CP2102 converters and they are exposed -as follows: - -+-----------+-----------+ -| Connector | Processor | -+===========+===========+ -| CN25 | A53/A57 | -+-----------+-----------+ -| CN26 | CR7 | -+-----------+-----------+ - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This -probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN25 and/or CN26 then use the following -settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_h3_salvatorx_cr7`` board configuration can be built -in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3_salvatorx_cr7 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3_salvatorx_cr7 - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3_salvatorx_cr7 - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3_salvatorx_cr7 - -References -********** - -- `Renesas R-Car H3 chip`_ -- `Renesas R-Car Development Support website`_ -- `eLinux H3 Salvator-X page`_ - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux H3 Salvator-X page: - https://elinux.org/R-Car/Boards/Salvator-X - -.. _Install a toolchain: - https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.dts b/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.dts deleted file mode 100644 index f953a93a4ed415..00000000000000 --- a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2022 BayLibre, SAS - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include "rcar_h3_salvatorx_cr7-pinctrl.dtsi" -#include - -/ { - model = "Renesas h3 Salvator-X board"; - compatible = "renesas,h3-salvatorx-cr7"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &scif1; - zephyr,shell-uart = &scif1; - zephyr,canbus = &can0; - }; - - leds { - compatible = "gpio-leds"; - user_led_0: led_4 { - gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; - label = "led4"; - }; - user_led_1: led_5 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - label = "led5"; - }; - user_led_2: led_6 { - gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; - label = "led6"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_0: sw20 { - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - label = "sw20"; - zephyr,code = ; - }; - user_button_1: sw21 { - gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; - label = "sw21"; - zephyr,code = ; - }; - user_button_2: sw22 { - gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; - label = "sw22"; - zephyr,code = ; - }; - }; - - aliases { - led0 = &user_led_1; - sw0 = &user_button_0; - }; -}; - -&cmt0 { - status = "okay"; - clock-frequency = <32000>; -}; - -&gpio6 { - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; - bus-speed = <125000>; -}; - -&scif1 { - pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.yaml b/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.yaml deleted file mode 100644 index f751adbcc473bd..00000000000000 --- a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: rcar_h3_salvatorx_cr7 -name: Cortex r7 for Renesas H3 Salvator-X -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - i2c - - gpio - - clock_control - - uart -testing: - ignore_tags: - - isotp -vendor: renesas diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7_defconfig b/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7_defconfig deleted file mode 100644 index 3cf6bbaa0f26fc..00000000000000 --- a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_SOC_R8A77951=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_H3_SALVATORX_CR7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 -CONFIG_CONSOLE=y -CONFIG_RAM_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0 -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/rcar_h3ulcb/Kconfig.board b/boards/arm/rcar_h3ulcb/Kconfig.board deleted file mode 100644 index eec48844f2a113..00000000000000 --- a/boards/arm/rcar_h3ulcb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_H3ULCB_CR7 - bool "Cortex-R7 for Renesas H3ULCB" - depends on SOC_R8A77951 diff --git a/boards/arm/rcar_h3ulcb/Kconfig.defconfig b/boards/arm/rcar_h3ulcb/Kconfig.defconfig deleted file mode 100644 index 61504744fa19f8..00000000000000 --- a/boards/arm/rcar_h3ulcb/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_H3ULCB_CR7 -config BOARD - default "rcar_h3ulcb_cr7" -endif # BOARD_RCAR_H3ULCB_CR7 diff --git a/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst b/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst deleted file mode 100644 index cf02569df83f2d..00000000000000 --- a/boards/arm/rcar_h3ulcb/doc/rcar_h3ulcb.rst +++ /dev/null @@ -1,276 +0,0 @@ -.. _rcar_h3ulcb_boards: - -Renesas R-Car H3ULCB -#################### - -Overview -******** -- The H3 Starter Kit board is designed for evaluating the features and performance of the R-CAR H3 device from Renesas Electronics and it is also used for developing and evaluating application software for these R-CAR H3. - -- The H3 Starter Kit, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, via 440pin connector on bottom side. - -It is possible to order 2 different types of H3 Starter Kit Boards, one with Ethernet connection onboard and one with Ethernet connection on ComExpress. - -.. figure:: img/rcar_h3ulcb_starter_kit.jpg - :align: center - :alt: R-Car starter kit - -.. note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION: In this case, power supply is managed by the daughter board. - -More information about the board can be found at `Renesas R-Car Starter Kit website`_. - -Hardware -******** - -Hardware capabilities for the H3ULCB for can be found on the `eLinux H3SK page`_ of the board. - -.. figure:: img/rcar_h3ulcb_features.jpg - :align: center - :alt: R-Car starter kit features - -.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. - -More information about the SoC that equips the board can be found here: - -- `Renesas R-Car H3 chip`_ - -Supported Features -================== - -Here is the current supported features when running Zephyr Project on the R-Car ULCB CR7: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINMUX | pinmux | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| GPIO | gpio | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+ + + + -| | FT232RQ / CP2102 | serial port-interrupt | -+-----------+------------------------------+--------------------------------+ -| CAN | can | normal mode | -+ + + + -| | TCAN332GDCNT | loopback mode | -+-----------+------------------------------+--------------------------------+ -| I2C | i2c | interrupt driven | -+-----------+------------------------------+--------------------------------+ -| PWM | pwm | All channels | -+-----------+------------------------------+--------------------------------+ - -It's also currently possible to write on the ram console. - -More features will be supported soon. - -Connections and IOs -=================== - -H3ULCB Board ------------- - -Here are official IOs figures from eLinux for H3ULCB board: - -`H3SK top view`_ - -`H3SK bottom view`_ - -Kingfisher Infotainment daughter board --------------------------------------- - -When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. - -Here are official IOs figures from eLinux for Kingfisher Infotainment board: - -`Kingfisher top view`_ - -`Kingfisher bottom view`_ - -GPIO ----- - -By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. - -UART ----- - -H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. - -Here is information about these serial ports: - -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| Physical Interface | Physical Location | Software Interface | Converter | Further Information | -+====================+===================+====================+===========+======================================+ -| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ -| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | -+--------------------+-------------------+--------------------+-----------+--------------------------------------+ - -.. note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. - -Here is CN04 UART interface pinout (depending on your Kingfisher board version): - -+--------+----------+----------+ -| Signal | Pin KF03 | Pin KF04 | -+========+==========+==========+ -| RXD | 3 | 4 | -+--------+----------+----------+ -| TXD | 5 | 2 | -+--------+----------+----------+ -| RTS | 4 | 1 | -+--------+----------+----------+ -| CTS | 6 | 3 | -+--------+----------+----------+ -| GND | 9 | 6 | -+--------+----------+----------+ - -CAN ---- - -H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. - -+--------------------+--------------------+--------------+ -| Physical Interface | Software Interface | Transceiver | -+====================+====================+==============+ -| CN17 | CAN0 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ -| CN18 | CAN1 | TCAN332GDCNT | -+--------------------+--------------------+--------------+ - -.. note:: Interfaces are set to 125 kbit/s by default. - -The following table lists CAN physical interfaces pinout: - -+-----+--------+ -| Pin | Signal | -+=====+========+ -| 1 | CANH | -+-----+--------+ -| 2 | CANL | -+-----+--------+ -| 3 | GND | -+-----+--------+ - -I2C ---- - -H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. - -I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. - -Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. - -PWM ---- - -ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. - -When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Supported Debug Probe -===================== - -The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. - -The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. - -.. note:: - See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. - -Configuring a Console -===================== - -Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -First of all, open your serial terminal. - -Applications for the ``rcar_h3ulcb_cr7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb_cr7 - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb_cr7 - -Debugging -========= - -First of all, open your serial terminal. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rcar_h3ulcb_cr7 - :goals: debug - -You will then get access to a GDB session for debug. - -By continuing the app, you should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build v2.6.0-rc1 *** - Hello World! rcar_h3ulcb_cr7 - -References -********** - -- `Renesas R-Car Starter Kit website`_ -- `Renesas R-Car H3 chip`_ -- `eLinux H3SK page`_ -- `eLinux Kingfisher page`_ - -.. _Renesas R-Car Starter Kit website: - https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit - -.. _Renesas R-Car H3 chip: - https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support - -.. _eLinux H3SK page: - https://elinux.org/R-Car/Boards/H3SK - -.. _H3SK top view: - https://elinux.org/images/1/1f/R-Car-H3-topview.jpg - -.. _H3SK bottom view: - https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg - -.. _eLinux Kingfisher page: - https://elinux.org/R-Car/Boards/Kingfisher - -.. _Kingfisher top view: - https://elinux.org/images/0/08/Kfisher_top_specs.png - -.. _Kingfisher bottom view: - https://elinux.org/images/0/06/Kfisher_bot_specs.png - -.. _Install a toolchain: - https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts deleted file mode 100644 index 073f89fadb2f85..00000000000000 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.dts +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2021 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include "rcar_h3ulcb_cr7-pinctrl.dtsi" -#include - -/ { - model = "Renesas h3ulcb board"; - compatible = "renesas,h3ulcb-cr7"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &scif1; - zephyr,shell-uart = &scif1; - zephyr,canbus = &can0; - }; - - leds { - compatible = "gpio-leds"; - user_led: led_5 { - gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button: sw3 { - gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; - label = "User switch"; - zephyr,code = ; - }; - }; - - aliases { - pwm-0 = &pwm0; - led0 = &user_led; - sw0 = &user_button; - }; -}; - -&cmt0 { - status = "okay"; - clock-frequency = <32000>; -}; - -&gpio6 { - status = "okay"; -}; - -&pwm0 { - pinctrl-0 = <&pwm0_default>; - pinctrl-names = "default"; -}; - -&can0 { - pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; - bus-speed = <125000>; - - can-transceiver { - max-bitrate = <5000000>; - }; -}; - -&scif1 { - pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c4 { - status = "okay"; -}; diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml deleted file mode 100644 index 09d5ae1c93f109..00000000000000 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: rcar_h3ulcb_cr7 -name: Cortex r7 for Renesas H3ULCB -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - i2c - - can - - gpio - - clock_control - - uart -testing: - ignore_tags: - - isotp -vendor: renesas diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7_defconfig b/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7_defconfig deleted file mode 100644 index e4fb3c34a35df3..00000000000000 --- a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_SOC_R8A77951=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_H3ULCB_CR7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 -CONFIG_CONSOLE=y -CONFIG_RAM_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0 -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/rcar_h3ulcb/support/openocd.cfg b/boards/arm/rcar_h3ulcb/support/openocd.cfg deleted file mode 100644 index 0395cb3efebfdf..00000000000000 --- a/boards/arm/rcar_h3ulcb/support/openocd.cfg +++ /dev/null @@ -1,88 +0,0 @@ -# Renesas R-Car Gen3 H3ULCB Cortex-R7 Board Config - -source [find interface/ftdi/olimex-arm-usb-ocd-h.cfg] -source [find target/renesas_rcar_reset_common.cfg] -set _CHIPNAME r8a77951 -set DAP_TAPID 0x5ba00477 -set CA57_0_DBGBASE 0x80410000 -set CA57_0_CTIBASE 0x80420000 -set CR7_DBGBASE 0x80910000 -set CR7_CTIBASE 0x80918000 - -adapter srst delay 1000 -adapter speed 20000 -global $_CHIPNAME -transport select jtag - -jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $DAP_TAPID -dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu - -cti create $_CHIPNAME.r7.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CR7_CTIBASE -target create $_CHIPNAME.r7 cortex_r4 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CR7_DBGBASE -defer-examine - -$_CHIPNAME.r7 configure -rtos auto - -cti create $_CHIPNAME.a57.0.cti -dap $_CHIPNAME.dap -ap-num 1 -baseaddr $CA57_0_CTIBASE -target create $_CHIPNAME.a57.0 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase $CA57_0_DBGBASE -cti $_CHIPNAME.a57.0.cti - -proc reset_cr7 { assert } { - global _CHIPNAME - if { $assert == 1 } { - # Software Reset Register 2 Bit(22) Arm Realtime core - $_CHIPNAME.a57.0 mww 0xe61500b0 0x00400000 - } else { - # Software Reset Clearing Register 2 Bit(22) Arm Realtime core - $_CHIPNAME.a57.0 mww 0xe6150948 0x00400000 - } -} - -# This function make use of A5x processor to: -# - Power on the CR7 (PWRONCR7) -# - Set the boot address (CR7BAR) -# - Halt the processor -# - Deassert the CR7 reset -proc start_cr7 { args } { - global _CHIPNAME - - targets $_CHIPNAME.a57.0 - $_CHIPNAME.a57.0 arp_halt - - # CR7BAR RBAR [31:18] BAREN bit(4) - $_CHIPNAME.a57.0 mww 0xe6160070 0x40040010 - - # PWRONCR7 - $_CHIPNAME.a57.0 mww 0xe618024c 1 - # Wait until power is on. Also possible to - # poll PWRSR7 and CR7PSTR register. - sleep 100 - - $_CHIPNAME.r7 arp_examine - catch { $_CHIPNAME.r7 arp_halt } - reset_cr7 0 - - # resume a5x processor or cmt timer will not run - resume - # set CR7 processor as default target for future commands - targets $_CHIPNAME.r7 -} - -$_CHIPNAME.r7 configure -event reset-end { - global _CHIPNAME - targets $_CHIPNAME.a57.0 - # Resume the A57 processor and gives - # enough time to A57 bootloaders to set-up dram - # clocks, power management, security groups - resume - sleep 500 - $_CHIPNAME.a57.0 arp_halt - $_CHIPNAME.a57.0 arp_poll - start_cr7 -} - -$_CHIPNAME.a57.0 configure -event examine-end { - start_cr7 -} - -$_CHIPNAME.r7 configure -event gdb-attach { - reset halt -} diff --git a/boards/arm/rcar_spider/Kconfig.board b/boards/arm/rcar_spider/Kconfig.board deleted file mode 100644 index 1ff4c7e794d458..00000000000000 --- a/boards/arm/rcar_spider/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_SPIDER_CR52 - bool "Cortex-R52 for Renesas Spider" - depends on SOC_R8A779F0 diff --git a/boards/arm/rcar_spider/Kconfig.defconfig b/boards/arm/rcar_spider/Kconfig.defconfig deleted file mode 100644 index b2a590250f9bd7..00000000000000 --- a/boards/arm/rcar_spider/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_SPIDER_CR52 - -config BOARD - default "rcar_spider_cr52" - -endif # BOARD_RCAR_SPIDER_CR52 diff --git a/boards/arm/rcar_spider/board.cmake b/boards/arm/rcar_spider/board.cmake deleted file mode 100644 index b106c562c540b1..00000000000000 --- a/boards/arm/rcar_spider/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(openocd "--use-elf") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/arm/rcar_spider/rcar_spider_cr52.dts b/boards/arm/rcar_spider/rcar_spider_cr52.dts deleted file mode 100644 index 6d89b3ede94d53..00000000000000 --- a/boards/arm/rcar_spider/rcar_spider_cr52.dts +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2023 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include "rcar_spider_cr52-pinctrl.dtsi" -#include - -/ { - model = "Renesas Spider board"; - compatible = "renesas,spider-cr52"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &scif0; - zephyr,shell-uart = &scif0; - }; - - leds { - compatible = "gpio-leds"; - user_led: led_8 { - gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button: sw10 { - gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; - label = "User switch"; - zephyr,code = ; - }; - }; - - aliases { - led0 = &user_led; - sw0 = &user_button; - }; -}; - -&scif0 { - pinctrl-0 = <&scif0_data_tx_default &scif0_data_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio4 { - status = "okay"; -}; diff --git a/boards/arm/rcar_spider/rcar_spider_cr52.yaml b/boards/arm/rcar_spider/rcar_spider_cr52.yaml deleted file mode 100644 index 6dea2b344b70cb..00000000000000 --- a/boards/arm/rcar_spider/rcar_spider_cr52.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: rcar_spider_cr52 -name: Cortex r52 for Renesas Spider -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - gpio - - clock_control - - uart diff --git a/boards/arm/rcar_spider/rcar_spider_cr52_defconfig b/boards/arm/rcar_spider/rcar_spider_cr52_defconfig deleted file mode 100644 index 7eea72fd80a52f..00000000000000 --- a/boards/arm/rcar_spider/rcar_spider_cr52_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_SOC_R8A779F0=y -CONFIG_SOC_SERIES_RCAR_GEN4=y -CONFIG_BOARD_RCAR_SPIDER_CR52=y -CONFIG_CLOCK_CONTROL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12500000 -CONFIG_CONSOLE=y -CONFIG_RAM_CONSOLE=y -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0 -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y diff --git a/boards/arm/rddrone_fmuk66/Kconfig.board b/boards/arm/rddrone_fmuk66/Kconfig.board deleted file mode 100644 index b6a2829208e0d5..00000000000000 --- a/boards/arm/rddrone_fmuk66/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021, Electromaticus LLC, 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RDDRONE_FMUK66 - bool "NXP RDDRONE-FMUK66" - depends on SOC_SERIES_KINETIS_K6X - select SOC_PART_NUMBER_MK66FN2M0VLQ18 diff --git a/boards/arm/rddrone_fmuk66/Kconfig.defconfig b/boards/arm/rddrone_fmuk66/Kconfig.defconfig deleted file mode 100644 index 0e70ab80ea0a77..00000000000000 --- a/boards/arm/rddrone_fmuk66/Kconfig.defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# RDDRONE-FMUK66 board - -# Copyright (c) 2021, Electromaticus LLC, 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RDDRONE_FMUK66 - -config BOARD - default "rddrone_fmuk66" - -config OSC_XTAL0_FREQ - default 16000000 - -config MCG_PRDIV0 - default 0x0 - -config MCG_VDIV0 - default 0x4 - -config MCG_FCRDIV - default 1 - -if NETWORKING - -config NET_L2_ETHERNET - default y if !MODEM - -endif # NETWORKING - -endif # BOARD_RDDRONE_FMUK66 diff --git a/boards/arm/rddrone_fmuk66/doc/index.rst b/boards/arm/rddrone_fmuk66/doc/index.rst deleted file mode 100644 index 7c348cc6e97df8..00000000000000 --- a/boards/arm/rddrone_fmuk66/doc/index.rst +++ /dev/null @@ -1,203 +0,0 @@ -.. _rddrone_fmuk66: - -NXP RDDRONE-FMUK66 -################## - -Overview -******** - -The RDDRONE FMUK66 is an drone control board with commonly used peripheral -connectors and a Kinetis K66 on board. - -- Comes with a J-Link Edu Mini for programming and UART console. - -.. image:: rddrone_fmuk66.jpg - :align: center - :alt: RDDRONE-FMUK66 - -Hardware -******** - -- MK66FN2MOVLQ18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, - crystal-less USB, and 144 Low profile Quad Flat Package (LQFP)) -- Dual role USB interface with micro-B USB connector -- RGB LED -- FXOS8700CQ accelerometer and magnetometer -- FXAS21002CQ gyro -- BMM150 magnetometer -- ML3114A2 barometer -- BMP280 barometer -- Connector for PWM servo/motor controls -- Connector for UART GPS/GLONASS -- SDHC - -For more information about the K64F SoC and FRDM-K64F board: - -- `K66F Website`_ -- `K66F Datasheet`_ -- `K66F Reference Manual`_ -- `RDDRONE-FMUK66 Website`_ -- `RDDRONE-FMUK66 User Guide`_ -- `RDDRONE-FMUK66 Schematics`_ - -Supported Features -================== - -The rddrone-fmuk66 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | dma | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig`` - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The K66F SoC is configured to use the 16 MHz external oscillator on the board -with the on-chip PLL to generate a 160 MHz system clock. - -Serial Port -=========== - -The K66F SoC has six UARTs. LPUART0 is configured for the console, UART0 is labeled Serial 2, -UART2 is labeled GPS, UART4 is labeled Serial 1. Any of these UARTs may be used as the console by -overlaying the board device tree. - -USB -=== - -The K66F SoC has a USB OTG (USBOTG) controller that supports both -device and host functions through its micro USB connector (K66F USB). -Only USB device function is supported in Zephyr at the moment. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use jlink. The board package -with accessories comes with a jlink mini edu and cable specifically for this board -along with a usb to uart that connects directly to the jlink mini edu. This is the expected -default configuration for programming and getting a console. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rddrone-fmuk66 - :gen-args: - :goals: build - -Configuring a Console -===================== - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rddrone-fmuk66 - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.7.0 ***** - Hello World! rddrone-fmuk66 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: rddrone-fmuk66 - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.7.0 ***** - Hello World! rddrone-fmuk66 - -.. _RDDRONE-FMUK66 Website: - -https://www.nxp.com/design/designs/px4-robotic-drone-vehicle-flight-management-unit-vmu-fmu-rddrone-fmuk66:RDDRONE-FMUK66 - -.. _RDDRONE-FMUK66 User Guide: - -https://nxp.gitbook.io/hovergames/userguide/getting-started - -.. _RDDRONE-FMUK66 Schematics: - -https://www.nxp.com/webapp/Download?colCode=SPF-39053 - -.. _K66F Website: - -https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 - -.. _K66F Datasheet: - -https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf - -.. _K66F Reference Manual: - -https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 diff --git a/boards/arm/reel_board/Kconfig b/boards/arm/reel_board/Kconfig deleted file mode 100644 index 9b9c32f4209a02..00000000000000 --- a/boards/arm/reel_board/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# reel board configuration - -# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_REEL_BOARD || BOARD_REEL_BOARD_V2 diff --git a/boards/arm/reel_board/Kconfig.board b/boards/arm/reel_board/Kconfig.board deleted file mode 100644 index 552aa3f9b52b17..00000000000000 --- a/boards/arm/reel_board/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# reel board configuration - -# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_REEL_BOARD - bool "reel board equipped with GDEH0213B1 display" - depends on SOC_NRF52840_QIAA - -config BOARD_REEL_BOARD_V2 - bool "reel board equipped with GDEH0213B72 display" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/reel_board/Kconfig.defconfig b/boards/arm/reel_board/Kconfig.defconfig deleted file mode 100644 index 5bacbb05c5d705..00000000000000 --- a/boards/arm/reel_board/Kconfig.defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# reel board configuration - -# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_REEL_BOARD || BOARD_REEL_BOARD_V2 - -config BOARD - default "reel_board" if BOARD_REEL_BOARD - default "reel_board_v2" if BOARD_REEL_BOARD_V2 - -config I2C - default y - -config BT_CTLR - default y - depends on BT - -if FXOS8700 - -choice FXOS8700_MODE - default FXOS8700_MODE_ACCEL -endchoice - -endif # FXOS8700 - -if LVGL - -choice LV_COLOR_DEPTH - default LV_COLOR_DEPTH_1 -endchoice - -config LV_Z_BITS_PER_PIXEL - default 1 - -config LV_DPI_DEF - default 130 - -config LV_Z_VDB_SIZE - default 16 - -endif # LVGL - -endif # BOARD_REEL_BOARD || BOARD_REEL_BOARD_V2 diff --git a/boards/arm/reel_board/doc/index.rst b/boards/arm/reel_board/doc/index.rst deleted file mode 100644 index dec81bd88ec61c..00000000000000 --- a/boards/arm/reel_board/doc/index.rst +++ /dev/null @@ -1,564 +0,0 @@ -.. _reel_board: - -reel board -########## - -Overview -******** - -`reel board`_ is a evaluation board based on the Nordic Semiconductor -nRF52840 SoC. The board was developed by PHYTEC Messtechnik GmbH in -cooperation with Zephyr Project for the Hackathon - "Get Connected". -The board has a built-in debug adapter based on the DAPLink interface -firmware and NXP MK20DX128VFM5 SoC. - -It is equipped with the Electrophoretic (electronic ink) Display (EPD), -environmental (temperature, humidity, light, accelerometer) sensors, and -Bluetooth connectivity making it easy to experiment and evaluate the -Zephyr OS in these kinds of use cases: - -* battery powered sensor node -* low-power, low-cost human-machine interface (HMI) for remote - control and environmental sensor monitoring -* temperature and humidity monitor on your table -* product, name or price tag -* interactive badge for meetings and conferences - -The board provides support for the Nordic Semiconductor nRF52840 ARM |reg| -Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting Bluetooth -|reg| Low Energy and IEEE |reg| 802.15.4. - -The schematic can be found on the `reel board website`_. - -Hardware -******** - -On the front of the board are RGB-LED, ADPS9960 and HDC1010 sensors, -and Electrophoretic Display. -The RGB-LED is controlled by the nRF52840 via GPIO pins. -Display is controlled by the nRF52840 via SPI and 3 GPIOs. - -On the back side of the board are all other components such as nRF52840, -a circuit for the Debug Adapter, On/Off and power source switch, battery holder, -buttons and the MMA8652FC (accelerometer) sensor. - -ADPS9960 is a Digital Proximity, Ambient Light, RGB and Gesture sensor. -HDC1010 is a digital humidity and temperature sensor. -MMA8652FC is a 12-bit Digital Accelerometer. -All sensors are connected to the I2C bus and one GPIO pin each, -which can be used as an interrupt source. - -.. figure:: img/reel_board.jpg - :align: center - :alt: reel board front - - reel board front (Credit: PHYTEC) - -.. figure:: img/reel_board_descr_back.jpg - :align: center - :alt: reel board back - - reel board back (Credit: PHYTEC) - -Since PCB version 1507.2, the nRF52840 SoC is not soldered directly to -the board but integrated as a module on a NOTM.2 adapter. -The wiring is identical for versions 1507.1 and 1507.2. - -.. _reel_board_display: - -Display -======= - -GDEH0213B1 is the display with which the board was introduced -in 2018. Unfortunately, this display has been discontinued. -Currently the board is delivered with the display GDEH0213B72. -It is expected that the display will be replaced over time -due the short product lifecycle of this type of displays. -The following table lists the displays used on the reel board. -The label on the ribbon cable can help to distinguish the displays. -According to the display type, the correct designation must be -used for building an application. - -+--------------+--------------------+----------------------+-------------------+ -| Display | Ribbon Cable Label | Controller / Driver | Board Designation | -+==============+====================+======================+===================+ -| Good Display | HINK-E0213 | SSD1673 / | reel_board | -| GDEH0213B1 | | ssd16xx | | -+--------------+--------------------+----------------------+-------------------+ -| Good Display | HINK-E0213A22 | SSD1675A / | reel_board_v2 | -| GDEH0213B72 | | ssd16xx | | -+--------------+--------------------+----------------------+-------------------+ - -Power supply -============ - -The board is optimized for low power applications and supports two -power source configurations, battery and micro USB connector. - -The On/Off switch can choose which power source is used. - -reel board uses a TPS610981 boost converter to generate supply voltage -for nRF52840 and peripherals (sensors and EPD). -The boost converter has two modes: - -* Active mode - supply voltages for nRF52840 and peripherals are on -* Low Power mode - only supply voltage for nRF52840 is on - -The mode is controlled by MODE pin (P1.00). - -.. note:: - Actually there is no possibility to reduce energy consumption by the - Low Power mode. Both voltages are always on, see: - :zephyr_file:`boards/arm/reel_board/board.c` - -Supported Features -================== - -The reel_board board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| SENSOR | off-chip | MMA8652FC polling: | -| | | ADPS9960 polling: | -| | | HDC1010 polling | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -Port P0 -------- - -+-------+----------------------------+---------------------------+ -| Name | Function | Usage | -+=======+============================+===========================+ -| P0.00 | XL1 | 32.768 kHz oscillator | -+-------+----------------------------+---------------------------+ -| P0.01 | XL2 | 32.768 kHz oscillator | -+-------+----------------------------+---------------------------+ -| P0.02 | expansion connector pin 30 | None | -+-------+----------------------------+---------------------------+ -| P0.03 | expansion connector pin 31 | None | -+-------+----------------------------+---------------------------+ -| P0.04 | expansion connector pin 19 | None | -+-------+----------------------------+---------------------------+ -| P0.05 | expansion connector pin 11 | None | -+-------+----------------------------+---------------------------+ -| P0.06 | UART0_TX | UART Console over USB | -+-------+----------------------------+---------------------------+ -| P0.07 | Button | user button (S5) | -+-------+----------------------------+---------------------------+ -| P0.08 | UART0_RX | UART Console over USB | -+-------+----------------------------+---------------------------+ -| P0.09 | expansion connector pin 27 | None | -+-------+----------------------------+---------------------------+ -| P0.10 | expansion connector pin 29 | None | -+-------+----------------------------+---------------------------+ -| P0.11 | RGB LED (red) | GPIO | -+-------+----------------------------+---------------------------+ -| P0.12 | RGB LED (green) | GPIO | -+-------+----------------------------+---------------------------+ -| P0.13 | PWM LED | Buzzer | GPIO | -+-------+----------------------------+---------------------------+ -| P0.14 | EPD Busy output | GPIO | -+-------+----------------------------+---------------------------+ -| P0.15 | EPD Reset input | GPIO | -+-------+----------------------------+---------------------------+ -| P0.16 | EPD DC input | GPIO | -+-------+----------------------------+---------------------------+ -| P0.17 | EPD SPI3_CS | SPI | -+-------+----------------------------+---------------------------+ -| P0.18 | CPU Reset | Reset (S4) | -+-------+----------------------------+---------------------------+ -| P0.19 | EPD SPI3_CLK | SPI | -+-------+----------------------------+---------------------------+ -| P0.20 | EPD SPI3_MOSI | SPI | -+-------+----------------------------+---------------------------+ -| P0.21 | SPI3_MISO | SPI (not connected) | -+-------+----------------------------+---------------------------+ -| P0.22 | HDC1010 DRDYn | GPIO | -+-------+----------------------------+---------------------------+ -| P0.23 | APDS9960 INT | GPIO | -+-------+----------------------------+---------------------------+ -| P0.24 | MMA8652FC INT1 | GPIO | -+-------+----------------------------+---------------------------+ -| P0.25 | MMA8652FC INT2 | GPIO | -+-------+----------------------------+---------------------------+ -| P0.26 | I2C_0 | I2C | -+-------+----------------------------+---------------------------+ -| P0.27 | I2C_0 | I2C | -+-------+----------------------------+---------------------------+ -| P0.28 | expansion connector pin 3 | None | -+-------+----------------------------+---------------------------+ -| P0.29 | expansion connector pin 52 | None | -+-------+----------------------------+---------------------------+ -| P0.30 | expansion connector pin 1 | None | -+-------+----------------------------+---------------------------+ -| P0.31 | expansion connector pin 37 | None | -+-------+----------------------------+---------------------------+ - -Port P1 -------- - -+-------+----------------------------+---------------------------+ -| Name | Function | Usage | -+=======+============================+===========================+ -| P1.00 | peripheral power on | GPIO | -+-------+----------------------------+---------------------------+ -| P1.01 | expansion connector pin 32 | None | -+-------+----------------------------+---------------------------+ -| P1.02 | expansion connector pin 34 | None | -+-------+----------------------------+---------------------------+ -| P1.03 | expansion connector pin 17 | None | -+-------+----------------------------+---------------------------+ -| P1.04 | expansion connector pin 15 | None | -+-------+----------------------------+---------------------------+ -| P1.05 | expansion connector pin 13 | None | -+-------+----------------------------+---------------------------+ -| P1.06 | expansion connector pin 33 | None | -+-------+----------------------------+---------------------------+ -| P1.07 | expansion connector pin 35 | None | -+-------+----------------------------+---------------------------+ -| P1.08 | expansion connector pin 45 | None | -+-------+----------------------------+---------------------------+ -| P1.09 | RGB LED (blue) | GPIO | -+-------+----------------------------+---------------------------+ -| P1.10 | expansion connector pin 47 | None | -+-------+----------------------------+---------------------------+ -| P1.11 | expansion connector pin 49 | None | -+-------+----------------------------+---------------------------+ -| P1.12 | expansion connector pin 51 | None | -+-------+----------------------------+---------------------------+ -| P1.13 | expansion connector pin 36 | None | -+-------+----------------------------+---------------------------+ -| P1.14 | expansion connector pin 48 | None | -+-------+----------------------------+---------------------------+ -| P1.15 | expansion connector pin 50 | None | -+-------+----------------------------+---------------------------+ - -Solder Jumper and Testpoints -============================ - -There are several labeled solder jumpers on the board. -These can be used to connect a logic analyzer to check the behavior of a -driver or to measure the voltage of a signal. - -.. figure:: img/reel_board_tp.jpg - :align: center - :alt: reel board Jumper and Testpoints - - reel board testpoints (Credit: PHYTEC) - -I2C bus and sensors testpoints ------------------------------- - -+-------+-----------------------+---------------------------+ -| Name | Type | Usage | -+=======+=======================+===========================+ -| J19 | closed solder jumper | testpoint I2C SDA | -+-------+-----------------------+---------------------------+ -| J20 | closed solder jumper | testpoint I2C SCL | -+-------+-----------------------+---------------------------+ -| J7 | closed solder jumper | testpoint INT1 MMA8652FC | -+-------+-----------------------+---------------------------+ -| J24 | closed solder jumper | testpoint INT2 MMA8652FC | -+-------+-----------------------+---------------------------+ -| J11 | closed solder jumper | testpoint INT APDS9960 | -+-------+-----------------------+---------------------------+ -| J12 | closed solder jumper | testpoint DRDYn HDC1010 | -+-------+-----------------------+---------------------------+ - -EPD testpoints --------------- - -+-------+-----------------------+---------------------------+ -| Name | Type | Usage | -+=======+=======================+===========================+ -| J13 | closed solder jumper | testpoint EPD Busy | -+-------+-----------------------+---------------------------+ -| J14 | closed solder jumper | testpoint EPD Reset | -+-------+-----------------------+---------------------------+ -| J15 | closed solder jumper | testpoint EPD DC | -+-------+-----------------------+---------------------------+ -| J16 | closed solder jumper | testpoint EPD SPI_CS | -+-------+-----------------------+---------------------------+ -| J17 | closed solder jumper | testpoint EPD SPI_CLK | -+-------+-----------------------+---------------------------+ -| J18 | closed solder jumper | testpoint EPD SPI_MOSI | -+-------+-----------------------+---------------------------+ - -Power supply testpoint ----------------------- - -+-------+-----------------------+-------------------------------------------+ -| Name | Type | Usage | -+=======+=======================+===========================================+ -| J21 | closed solder jumper | testpoint peripheral voltage on/off | -+-------+-----------------------+-------------------------------------------+ -| TP11 | testpoint | testpoint peripheral voltage | -+-------+-----------------------+-------------------------------------------+ -| TP12 | testpoint | testpoint nRF52840 supply voltage VDD_nRF | -+-------+-----------------------+-------------------------------------------+ -| TP13 | testpoint | testpoint boost converter input voltage | -+-------+-----------------------+-------------------------------------------+ - -Built-in Debug Adapter -====================== - -The debug adapter is based on the DAPLink interface firmware and -NXP MK20DX128VFM5 SoC. The adapter is powered via a micro USB connector and -is always on when the board is connected to the USB host. -reel board can be flashed and debugged, powered either from battery or USB. -If the Adapter is powered via USB, the Adapter circuit heats the board -slightly and the temperature sensor can output values up to 1.5 degrees higher. - -.. figure:: img/reel_board_debug.jpg - :align: center - :alt: reel board Debug Adapter - - reel board Debug Adapter overview (Credit: PHYTEC) - -Debug Adapter Firmware ----------------------- - -DAPLink firmware for the adapter can be found at `DAPLink reel board Firmware`_. -To update the firmware (if necessary), the adapter must be started in bootloader -mode. For this, the board should be disconnected from the USB host, -the J22 should be closed (use tweezers for this) and the board reconnected to -the USB host. - -Debug Adapter Jumper --------------------- - -+-------+-----------------------+----------------------------------------------+ -| Name | Type | Usage | -+=======+=======================+==============================================+ -| J3 | open solder jumper | close to pass UART TX to external adapter | -+-------+-----------------------+----------------------------------------------+ -| J4 | open solder jumper | close to pass UART RX to external adapter | -+-------+-----------------------+----------------------------------------------+ -| J22 | open solder jumper | close to start adapter in bootloader mode | -+-------+-----------------------+----------------------------------------------+ - -Adapter LEDs ------------- - -+-------+-----------------------+--------------------------------+ -| Name | Type | Usage | -+=======+=======================+================================+ -| D11 | green | flashes when adapter is active | -+-------+-----------------------+--------------------------------+ -| D14 | red | reserved | -+-------+-----------------------+--------------------------------+ -| D15 | yellow | reserved | -+-------+-----------------------+--------------------------------+ - -Expansion Connector -************************ - -The expansion connector has the same dimensions and similar pinout -as the BBC MicroBit edge connector. The expansion components that are -designed especially for the reel board are called link boards. - -.. figure:: img/reel_board_excon.jpg - :align: center - :alt: reel board Expansion Connector - - reel board Expansion Connector (Credit: PHYTEC) - -link board BASE -=============== - -link board BASE is a passive expansion board and allows other link boards or -third party shields in Arduino UNO R3 format to be connected to the reel board. -In addition, it includes a NOTM.2 connector and more powerful DCDC converter -then reel board. - -.. figure:: img/rb_lb_shield.jpg - :align: center - :alt: reel board and link board BASE - - reel board and link board BASE (Credit: PHYTEC) - -link board BASE can be used in combination with other link boards or -third party shields in two ways: - - As an adapter - reel board is plugged into the link board BASE. Both peripherals on - reel board and shields can be used as long as there is no conflict - between I2C devices. Care should be taken to provide enough power - to the complete circuit. - - Stand-alone - NOTM.2 adapter is removed from the reel board and - connected to NOTM.2 connector on the link board BASE. - The wiring to the shield connector is identical to the - configuration above and no software modifications for the shield - are necessary. - Stand-alone configuration is more suitable for applications where - peripherals on the reel board are not used or in conflict, - power provided by the reel board is not enough, - or for prototypes in the field. - -.. figure:: img/link_board_base.jpg - :align: center - :alt: link board BASE - - link board BASE (Credit: PHYTEC) - -Components on the link board BASE: - - reel board Connector: - 2x40 position edge connector. - - Micro USB Connector: - USB can be used as power source. USB data lines are wired - to NOTM.2 connector. - - NOTM.2 Connector: - Connector for NOTM.2 adapter. If the connector is used then - reel board should be removed from reel board connector. - - SWD Connector X11: - Wired to NOTM.2 connector. A debug probe can - be connected to program or debug MCU in Stand-alone configuration. - - Alternative Power Source X5 or X9: - Positive pin is closer to the + character. Nominal voltage is - 3.3V, there is no protection against reverse polarity or overvoltage. - Use it with care. - - Shield Connector: - Connector for link boards and third party shields in Arduino UNO R3 - format. Only shields designed for 3.3V supply voltage are supported. - -Meaning of the Power Source Switch positions: - - EXT - link board BASE is powered from Alternative Power Source Connector - X9 or X5. - - USB - link board BASE is powered from USB connector (via DCDC converter). - - RB - link board BASE is powered from reel board. The available power is - below 0.3W and depends on which source is used to power the reel board. - -Programming and Debugging -************************* - -Applications for the ``reel_board`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing -======== - -If you use Linux, create a udev rule (as ``root``) to fix a permission issue -when not using root for flashing. - -.. code-block:: console - - # echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules - -Reload the rules and replug the device. - -.. code-block:: console - - $ sudo udevadm control --reload-rules - -Finally, unplug and plug the board again for the rules to take effect. - -Build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the reel board -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: reel_board - :goals: build flash - -.. note:: - Please use reel_board_v2 to build a application for the board equipped with - the GDEH0213B72, see :ref:`reel_board_display`. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: reel_board_v2 - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: reel_board - :maybe-skip-config: - :goals: debug - - -Testing the LEDs and buttons -**************************** - -There are 2 samples that allow you to test that the buttons (switches) and -LEDs on the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. - -References -********** - -.. _reel board Website: - https://www.phytec.de/reelboard/ - -.. target-notes:: - -.. _reel board: - https://www.phytec.de/reelboard/ - -.. _DAPLink reel board Firmware: - https://github.com/PHYTEC-Messtechnik-GmbH/DAPLink/tree/reel-board diff --git a/boards/arm/reel_board/reel_board_defconfig b/boards/arm/reel_board/reel_board_defconfig deleted file mode 100644 index 8e88a3b3231a62..00000000000000 --- a/boards/arm/reel_board/reel_board_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_REEL_BOARD=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/reel_board/reel_board_v2.dts b/boards/arm/reel_board/reel_board_v2.dts deleted file mode 100644 index 37c0f6c1397fc2..00000000000000 --- a/boards/arm/reel_board/reel_board_v2.dts +++ /dev/null @@ -1,119 +0,0 @@ -/* - * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "reel_board.dtsi" -#include "reel_board_v2-pinctrl.dtsi" - -/ { - model = "reel board v2"; - compatible = "phytec,reel_board_v2"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &ssd16xx; - }; - - aliases { - watchdog0 = &wdt0; - }; -}; - -&spi1 { - compatible = "nordic,nrf-spi"; - status = "okay"; - cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; - ssd16xx: ssd16xxfb@0 { - compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; - spi-max-frequency = <4000000>; - reg = <0>; - width = <250>; - height = <122>; - reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - dc-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - - full { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x26>; - border-waveform = <0x03>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - /* - * Waveform Composition - * - * There are 7 Voltage Source (VS) Level groups - * n = {0,1,2...6}, each group contains - * 4 phases x = {A,B,C,D}. - * 2 bits represent the voltage in a phase: - * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2 - * - * For example 0x80 represents sequence VSL-VSS-VSS-VSS, - */ - 80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */ - 10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */ - 80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */ - 10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */ - 00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */ - /* - * TPnx determines the length of each phase, - * and RPn repeat count of a sequence. - * TPnA, TPnB, TPnC, TPnD, RPn - * - * For example TP0A=3, TP0B=3, and RP0=2: - * VS sequence : VSL-VSS-VSS-VSS - * number of Gate Pulses (length) : 3 3 0 0 - * repeat count : 2 - */ - 03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */ - 09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */ - 03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */ - 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ - 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ - 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ - 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ - ]; - }; - - partial { - gdv = [15]; - sdv = [41 a8 32]; - vcom = <0x26>; - border-waveform = <0x01>; - dummy-line = <0x30>; - gate-line-width = <0x0a>; - lut = [ - 00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */ - 80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */ - 40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */ - 80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */ - 00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */ - 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ - 00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */ - 00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */ - 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ - 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ - 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ - 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ - ]; - }; - }; -}; diff --git a/boards/arm/reel_board/reel_board_v2.yaml b/boards/arm/reel_board/reel_board_v2.yaml deleted file mode 100644 index 2b27622e089e14..00000000000000 --- a/boards/arm/reel_board/reel_board_v2.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: reel_board_v2 -name: reel-board-v2 -type: mcu -arch: arm -ram: 512 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - i2c - - spi - - gpio - - usb_device - - usb_cdc - - ble - - pwm - - arduino_i2c - - arduino_spi - - arduino_gpio -vendor: phytec diff --git a/boards/arm/reel_board/reel_board_v2_defconfig b/boards/arm/reel_board/reel_board_v2_defconfig deleted file mode 100644 index fcec54b6d0cd64..00000000000000 --- a/boards/arm/reel_board/reel_board_v2_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_REEL_BOARD_V2=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/rm1xx_dvk/Kconfig.board b/boards/arm/rm1xx_dvk/Kconfig.board deleted file mode 100644 index f5c1f23b932a7b..00000000000000 --- a/boards/arm/rm1xx_dvk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# rm1xx_dvk board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RM1XX_DVK - bool "RM1XX_DVK" - depends on SOC_NRF51822_QFAC diff --git a/boards/arm/rm1xx_dvk/Kconfig.defconfig b/boards/arm/rm1xx_dvk/Kconfig.defconfig deleted file mode 100644 index 22a717477d21da..00000000000000 --- a/boards/arm/rm1xx_dvk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# rm1xx_dvk board configuration - -# Copyright (c) 2021 Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RM1XX_DVK - -config BOARD - default "rm1xx_dvk" - -config BT_CTLR - default BT - -endif # BOARD_RM1XX_DVK diff --git a/boards/arm/rm1xx_dvk/pre_dt_board.cmake b/boards/arm/rm1xx_dvk/pre_dt_board.cmake deleted file mode 100644 index 5cdf5c021e8e31..00000000000000 --- a/boards/arm/rm1xx_dvk/pre_dt_board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - power@40000000 & clock@40000000 & nrf-mpu@40000000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk_defconfig b/boards/arm/rm1xx_dvk/rm1xx_dvk_defconfig deleted file mode 100644 index cee5bb0b4a01fa..00000000000000 --- a/boards/arm/rm1xx_dvk/rm1xx_dvk_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF51X=y -CONFIG_SOC_NRF51822_QFAC=y -CONFIG_BOARD_RM1XX_DVK=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_PINCTRL=y diff --git a/boards/arm/ronoth_lodev/Kconfig.board b/boards/arm/ronoth_lodev/Kconfig.board deleted file mode 100644 index c0135583575c4b..00000000000000 --- a/boards/arm/ronoth_lodev/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Ronoth LoDev board configuration -# Copyright (c) 2020/2021 Dean Weiten -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RONOTH_LODEV - bool "Ronoth LoDev" - depends on SOC_STM32L073XX diff --git a/boards/arm/ronoth_lodev/Kconfig.defconfig b/boards/arm/ronoth_lodev/Kconfig.defconfig deleted file mode 100644 index 5e3a44a811e8ae..00000000000000 --- a/boards/arm/ronoth_lodev/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Ronoth LoDev board configuration -# Copyright (c) 2020/2021 Dean Weiten -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RONOTH_LODEV - -config BOARD - default "ronoth_lodev" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_RONOTH_LODEV diff --git a/boards/arm/rpi_pico/Kconfig.board b/boards/arm/rpi_pico/Kconfig.board deleted file mode 100644 index e2c1318db67bc2..00000000000000 --- a/boards/arm/rpi_pico/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RPI_PICO - bool "Raspberry Pi Pico Board" - depends on SOC_RP2040 - -config BOARD_RPI_PICO_W - bool "Raspberry Pi Pico W Board" - depends on SOC_RP2040 diff --git a/boards/arm/rpi_pico/Kconfig.defconfig b/boards/arm/rpi_pico/Kconfig.defconfig deleted file mode 100644 index a664665480ba34..00000000000000 --- a/boards/arm/rpi_pico/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RPI_PICO || BOARD_RPI_PICO_W - -config BOARD - default "rpi_pico" if BOARD_RPI_PICO - default "rpi_pico_w" if BOARD_RPI_PICO_W - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_RPI_PICO || BOARD_RPI_PICO_W diff --git a/boards/arm/rpi_pico/rpi_pico_w.yaml b/boards/arm/rpi_pico/rpi_pico_w.yaml deleted file mode 100644 index d0acab19cc6eed..00000000000000 --- a/boards/arm/rpi_pico/rpi_pico_w.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: rpi_pico_w -name: RaspberryPi-Pico-w -type: mcu -arch: arm -flash: 2048 -ram: 264 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - uart - - gpio - - adc - - i2c - - spi - - hwinfo - - watchdog - - pwm - - flash - - dma - - pio - - counter - - clock diff --git a/boards/arm/rpi_pico/rpi_pico_w_defconfig b/boards/arm/rpi_pico/rpi_pico_w_defconfig deleted file mode 100644 index 9b3868541d19f3..00000000000000 --- a/boards/arm/rpi_pico/rpi_pico_w_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_RPI_PICO_W=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_USE_DT_CODE_PARTITION=y -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_RESET=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/ruuvi_ruuvitag/Kconfig.board b/boards/arm/ruuvi_ruuvitag/Kconfig.board deleted file mode 100644 index 39a7af5dee9442..00000000000000 --- a/boards/arm/ruuvi_ruuvitag/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RUUVI_RUUVITAG - bool "Ruuvi-RuuviTag" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ruuvi_ruuvitag/Kconfig.defconfig b/boards/arm/ruuvi_ruuvitag/Kconfig.defconfig deleted file mode 100644 index fb5618995ff24b..00000000000000 --- a/boards/arm/ruuvi_ruuvitag/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Ruuvi RuuviTag configuration - -# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RUUVI_RUUVITAG - -config BOARD - default "ruuvi_ruuvitag" - -config SPI - default y - -config BT_CTLR - default BT - -endif # BOARD_RUUVI_RUUVITAG diff --git a/boards/arm/ruuvi_ruuvitag/doc/index.rst b/boards/arm/ruuvi_ruuvitag/doc/index.rst deleted file mode 100644 index 5ab0ea9cfc037e..00000000000000 --- a/boards/arm/ruuvi_ruuvitag/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _ruuvi_ruuvitag: - -Ruuvi RuuviTag -############## - -Overview -******** - -RuuviTag is an advanced battery-operated open-source Bluetooth -enabled sensor beacon platform capable of sending temperature, humidity, -pressure, and motion information over Bluetooth Low Energy. - -.. figure:: img/ruuvitag.jpg - :align: center - :alt: RUUVI RuuviTag - - RUUVI RuuviTag (Credit: https://ruuvi.com/) - -More information about the board can be found at the -`ruuvitag website`_. - -Hardware -******** - -RuuviTag's have the following physical features: - -* Nordic Semiconductor nRF52832 System-on-Chip -* STMicroelectronics LIS2DH12 accelerometer -* Bosch BME 280 temperature + relative air humidity + air pressure sensor -* NFC™-A tag antenna -* 1000mAh CR2477 battery -* 2 buttons -* 1 Green LED -* 1 Red LED -* IP67 Enclosure -* Long range RF antenna - -Supported Features -================== - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ -| Humidity, | on-board | bme280 | -| Temp & Air| | | -| Pressure | | | -+-----------+------------+----------------------+ -| Acc | on-board | lis2dh12 | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.17 -* LED1 (green) = P0.19 - -Push buttons ------------- - -* BUTTON0 = SW1 = P0.13 - -Pin descriptions ----------------- - -.. figure:: img/pinout.jpg - :align: center - :alt: RUUVI Pinout - -* 2 = P0.29 = SPI_SCK -* 3 = P0.28 = SPI_MISO -* 10 = P0.04 = GPIO (can be used as a GPIO / ADC pin) -* 11 = P0.05 = GPIO (can be used as a GPIO / ADC pin) -* 12 = P0.25 = SPI_MOSI -* 13 = P0.19 = LED2 (green) / GPIO (can be used as a GPIO pin but the LED will blink) -* 14 = P0.17 = LED1 (red) / GPIO (can be used as a GPIO pin but the LED will blink) -* 15 = P0.13 = Button / GPIO (can be used as a GPIO pin) -* 16 = GND (Battery's negative contact) -* 17 = Battery's positive contact -* 18 = Battery's positive contact -* 19 = SWDIO -* 20 = SWDCLK -* 21 = P0.18 = SWO / GPIO (can be used as a GPIO pin) -* 22 = P0.21 = Reset / GPIO (can be used as a GPIO pin if no need to reset the device) -* 23 = GND (Battery's negative contact) -* 24 = P0.31 = GPIO (can be used as a GPIO / ADC pin) -* 25 = P0.30 = GPIO (can be used as a GPIO / ADC pin) - -GPIO = General Purpose Input Output pin - -P1 = Standard 10-pin ARM Cortex debug connector (on RuuviTag Rev.B1-B5) - -* 1 = VDD -* 2 = SWDIO -* 3 = GND (Battery's negative contact) -* 4 = SWDCLK -* 5 = GND (Battery's negative contact) -* 6 = SWO -* 7 = No Connect -* 8 = No Connect -* 9 = GND (Battery's negative contact) -* 10 = Reset - -P1 = TC2030 TagConnect (on RuuviTag Rev.B6) - -* 1 = Battery's positive contact -* 2 = SWDIO -* 3 = Reset -* 4 = SWDCLK -* 5 = GND (Battery's negative contact) -* 6 = SWO - - -Programming and Debugging -************************* - -Flashing -======== - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -The easiest way to flash Zephyr onto a RuuviTag requires an external Ruuvi DEVKIT. More information about the board can be found at the -`ruuvitag devkit`_. - -Once your tag is connected to the DEVKIT and connected to your PC, build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: ruuvi_ruuvitag - :goals: build flash - -Advanced users may want to program the RuuviTag without the DEVKIT, this can be achieved via the SWDIO and SWDCLK pins located on the back of the RuuviTag. - -Debugging -========= - -If using the Ruuvi DEVKIT refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -Testing the LEDs and buttons on the RuuviTag -******************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in :file:`boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.dts`. - -References -********** - -.. target-notes:: - -.. _ruuvitag website: https://ruuvi.com -.. _ruuvitag datasheet: https://ruuvi.com/files/ruuvitag-tech-spec-2019-7.pdf -.. _ruuvitag devkit: https://lab.ruuvi.com/devshield/ diff --git a/boards/arm/rzt2m_starterkit/Kconfig.board b/boards/arm/rzt2m_starterkit/Kconfig.board deleted file mode 100644 index 9fddcf006a4f14..00000000000000 --- a/boards/arm/rzt2m_starterkit/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RZT2M_STARTER_KIT - bool "RZ/T2M Starter Kit Board" - depends on SOC_RENESAS_RZT2M diff --git a/boards/arm/rzt2m_starterkit/Kconfig.defconfig b/boards/arm/rzt2m_starterkit/Kconfig.defconfig deleted file mode 100644 index 9699b23963c96f..00000000000000 --- a/boards/arm/rzt2m_starterkit/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RZT2M_STARTER_KIT - -config BOARD - default "rzt2m_starter_kit" - -endif diff --git a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig b/boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig deleted file mode 100644 index 8b994e00082f14..00000000000000 --- a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RENESAS_RZT2M=y -CONFIG_BOARD_RZT2M_STARTER_KIT=y - -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/s32z270dc2_r52/Kconfig.board b/boards/arm/s32z270dc2_r52/Kconfig.board deleted file mode 100644 index 9e54998880dc37..00000000000000 --- a/boards/arm/s32z270dc2_r52/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_S32Z270DC2_RTU0_R52 - bool "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores" - depends on SOC_SERIES_S32ZE_R52 - select SOC_PART_NUMBER_S32Z27 - -config BOARD_S32Z270DC2_RTU1_R52 - bool "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores" - depends on SOC_SERIES_S32ZE_R52 - select SOC_PART_NUMBER_S32Z27 diff --git a/boards/arm/s32z270dc2_r52/Kconfig.defconfig b/boards/arm/s32z270dc2_r52/Kconfig.defconfig deleted file mode 100644 index 6d32c923542c2c..00000000000000 --- a/boards/arm/s32z270dc2_r52/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "s32z270dc2_rtu0_r52" if BOARD_S32Z270DC2_RTU0_R52 - default "s32z270dc2_rtu1_r52" if BOARD_S32Z270DC2_RTU1_R52 - -config NXP_S32_RTU_INDEX - default 0 if BOARD_S32Z270DC2_RTU0_R52 - default 1 if BOARD_S32Z270DC2_RTU1_R52 - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -config UART_CONSOLE - default y - -endif # SERIAL - -if SHELL - -config SHELL_STACK_SIZE - default 4096 - -endif # SHELL - -endif # BOARD_S32Z270DC2_RTU0_R52 || BOARD_S32Z270DC2_RTU1_R52 diff --git a/boards/arm/s32z270dc2_r52/doc/index.rst b/boards/arm/s32z270dc2_r52/doc/index.rst deleted file mode 100644 index e940a144f1f92f..00000000000000 --- a/boards/arm/s32z270dc2_r52/doc/index.rst +++ /dev/null @@ -1,311 +0,0 @@ -.. _s32z270dc2_r52: - -NXP X-S32Z27X-DC (DC2) -###################### - -Overview -******** - -The X-S32Z27X-DC (DC2) board is based on the NXP S32Z270 Real-Time Processor, -which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores -each, with flexible split/lock configurations. - -There is one Zephyr board per RTU: - -- ``s32z270dc2_rtu0_r52``, for RTU0 -- ``s32z270dc2_rtu1_r52``, for RTU1. - -Hardware -******** - -Information about the hardware and design resources can be found at -`NXP S32Z2 Real-Time Processors website`_. - -Supported Features -================== - -The boards support the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| Arm GIC | on-chip | interrupt_controller | -+-----------+------------+-------------------------------------+ -| Arm Timer | on-chip | timer | -+-----------+------------+-------------------------------------+ -| LINFlexD | on-chip | serial | -+-----------+------------+-------------------------------------+ -| MRU | on-chip | mbox | -+-----------+------------+-------------------------------------+ -| NETC | on-chip | ethernet | -| | | | -| | | mdio | -+-----------+------------+-------------------------------------+ -| SIUL2 | on-chip | pinctrl | -| | | | -| | | gpio | -| | | | -| | | external interrupt controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| SWT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| CANEXCEL | on-chip | can | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The SoC's pads are grouped into ports and pins for consistency with GPIO driver -and the HAL drivers used by this Zephyr port. The following table summarizes -the mapping between pads and ports/pins. This must be taken into account when -using GPIO driver or configuring the pinmuxing for the device drivers. - -+-------------------+-------------+ -| Pads | Port/Pins | -+===================+=============+ -| PAD_000 - PAD_015 | PA0 - PA15 | -+-------------------+-------------+ -| PAD_016 - PAD_030 | PB0 - PB14 | -+-------------------+-------------+ -| PAD_031 | PC15 | -+-------------------+-------------+ -| PAD_032 - PAD_047 | PD0 - PD15 | -+-------------------+-------------+ -| PAD_048 - PAD_063 | PE0 - PE15 | -+-------------------+-------------+ -| PAD_064 - PAD_079 | PF0 - PF15 | -+-------------------+-------------+ -| PAD_080 - PAD_091 | PG0 - PG11 | -+-------------------+-------------+ -| PAD_092 - PAD_095 | PH12 - PH15 | -+-------------------+-------------+ -| PAD_096 - PAD_111 | PI0 - PI15 | -+-------------------+-------------+ -| PAD_112 - PAD_127 | PJ0 - PJ15 | -+-------------------+-------------+ -| PAD_128 - PAD_143 | PK0 - PK15 | -+-------------------+-------------+ -| PAD_144 - PAD_145 | PL0 - PL1 | -+-------------------+-------------+ -| PAD_146 - PAD_159 | PM2 - PM15 | -+-------------------+-------------+ -| PAD_160 - PAD_169 | PN0 - PN9 | -+-------------------+-------------+ -| PAD_170 - PAD_173 | PO10 - PO13 | -+-------------------+-------------+ - -This board does not include user LED's or switches, which are needed for some -of the samples such as :zephyr:code-sample:`blinky` or :zephyr:code-sample:`button`. -Follow the steps described in the sample description to enable support for this -board. - -System Clock -============ - -The Cortex-R52 cores are configured to run at 800 MHz. - -Serial Port -=========== - -The SoC has 12 LINFlexD instances that can be used in UART mode. The console can -be accessed by default on the USB micro-B connector `J119`. - -Watchdog -======== - -The watchdog driver only supports triggering an interrupt upon timer expiration. -Zephyr is currently running from SRAM on this board, thus system reset is not -supported. - -Ethernet -======== - -NETC driver supports to manage the Physical Station Interface (PSI0) and/or a -single Virtual SI (VSI). The rest of the VSI's shall be assigned to different -cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to -configure the Ethernet network controller. - -Controller Area Network (CAN) -============================= - -Currently, the CANXL transceiver is not populated in this board. So CAN transceiver -connection is required for running external traffic. We can use any CAN transceiver, -which supports CAN 2.0 and CAN FD protocol. - -CAN driver supports classic (CAN 2.0) and CAN FD mode. Remote transmission request is -not supported as this feature is not available on NXP S32 CANXL HAL. - -Programming and Debugging -************************* - -Applications for the ``s32z270dc2_rtu0_r52`` and ``s32z270dc2_rtu1_r52`` boards -can be built in the usual way as documented in :ref:`build_an_application`. - -Currently is only possible to load and execute a Zephyr application binary on -this board from the core internal SRAM. - -This board supports West runners for the following debug tools: - -- :ref:`NXP S32 Debug Probe ` (default) -- :ref:`Lauterbach TRACE32 ` - -Follow the installation steps of the debug tool you plan to use before loading -your firmware. - -Set-up the Board -================ - -Connect the external debugger probe to the board's JTAG connector (``J134``) -and to the host computer via USB or Ethernet, as supported by the probe. - -For visualizing the serial output, connect the board's USB/UART port (``J119``) to -the host computer and run your favorite terminal program to listen for output. -For example, using the cross-platform `pySerial miniterm`_ terminal: - -.. code-block:: console - - python -m serial.tools.miniterm 115200 - -Replace ```` with the port where the board can be found. For example, -under Linux, ``/dev/ttyUSB0``. - -Debugging -========= - -You can build and debug the :ref:`hello_world` sample for the board -``s32z270dc2_rtu0_r52`` with: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build debug - -In case you are using a newer PCB revision, you have to use an adapted board -definition as the default PCB revision is B. For example, if using revision D: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52@D - :goals: build debug - :compact: - -At this point you can do your normal debug session. Set breakpoints and then -:kbd:`c` to continue into the program. You should see the following message in -the terminal: - -.. code-block:: console - - Hello World! s32z270dc2_rtu0_r52 - -To debug with Lauterbach TRACE32 softare run instead: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build debug -r trace32 - :compact: - -Flashing -======== - -Follow these steps if you just want to download the application to the board -SRAM and run. - -``flash`` command is supported only by the Lauterbach TRACE32 runner: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build flash -r trace32 - :compact: - -.. note:: - Currently, the Lauterbach start-up scripts executed with ``flash`` and - ``debug`` commands perform the same steps to initialize the SoC and - load the application to SRAM. The difference is that ``flash`` hides the - Lauterbach TRACE32 interface, executes the application and exits. - -To imitate a similar behavior using NXP S32 Debug Probe runner, you can run the -``debug`` command with GDB in batch mode: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build debug --tool-opt='--batch' - :compact: - -RTU and Core Configuration -========================== - -This Zephyr port can only run single core in any of the Cortex-R52 cores, -either in lock-step or split-lock mode. By default, Zephyr runs on the first -core of the RTU chosen and in lock-step mode (which is the reset -configuration). - -To build for split-lock mode, the :kconfig:option:`CONFIG_DCLS` must be -disabled from your application Kconfig file. - -By default the board configuration will set the runner arguments according to -the build configuration. To debug for a core different than the default use: - -.. tabs:: - - .. group-tab:: lockstep configuration - - .. code-block:: console - - west debug --core-name='R52___LS' - - .. group-tab:: split-lock configuration - - .. code-block:: console - - west debug --core-name='R52__' - -Where: - -- ```` is the zero-based RTU index (0 for ``s32z270dc2_rtu0_r52`` - and 1 for ``s32z270dc2_rtu1_r52``) -- ```` is the zero-based core index relative to the RTU on which to - run the Zephyr application (0, 1, 2 or 3) - -For example, to build the :ref:`hello_world` sample for the board -``s32z270dc2_rtu0_r52`` with split-lock core configuration: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: s32z270dc2_rtu0_r52 - :goals: build - :gen-args: -DCONFIG_DCLS=n - :compact: - -To execute this sample in the second core of RTU0 in split-lock mode: - -.. code-block:: console - - west debug --core-name='R52_0_1' - -If using Lauterbach TRACE32, all runner parameters must be overridden from command -line: - -.. code-block:: console - - west debug --startup-args elfFile= rtu= core= lockstep= - -Where ```` is the path to the Zephyr application ELF in the output -directory. - -References -********** - -.. target-notes:: - -.. _NXP S32Z2 Real-Time Processors website: - https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32z-and-s32e-real-time-processors/s32z2-safe-and-secure-high-performance-real-time-processors:S32Z2 - -.. _pySerial miniterm: - https://pyserial.readthedocs.io/en/latest/tools.html#module-serial.tools.miniterm diff --git a/boards/arm/s32z270dc2_r52/revision.cmake b/boards/arm/s32z270dc2_r52/revision.cmake deleted file mode 100644 index 87399444b71fbc..00000000000000 --- a/boards/arm/s32z270dc2_r52/revision.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION B - VALID_REVISIONS B D -) diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi b/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi deleted file mode 100644 index 884f1d802bb2ca..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "s32z270dc2_r52-pinctrl-common.dtsi" - -&swt0 { - status = "okay"; -}; - -&emdio { - pinctrl-0 = <&emdio_default>; - pinctrl-names = "default"; - status = "okay"; - - phy0: ethernet-phy@7 { - compatible = "ethernet-phy"; - reg = <0x7>; - status = "okay"; - }; -}; - -&enetc_psi0 { - local-mac-address = [00 00 00 01 02 00]; - pinctrl-0 = <ð0_default>; - pinctrl-names = "default"; - clock-frequency = <300000000>; - phy-handle = <&phy0>; - status = "okay"; -}; - -&can0 { - pinctrl-0 = <&can0_default>; - pinctrl-names = "default"; - bus-speed = <125000>; - sample-point = <875>; - bus-speed-data = <1000000>; - sample-point-data = <875>; - status = "okay"; -}; - -&can1 { - pinctrl-0 = <&can1_default>; - pinctrl-names = "default"; - bus-speed = <125000>; - sample-point = <875>; - bus-speed-data = <1000000>; - sample-point-data = <875>; -}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts deleted file mode 100644 index a865075808956d..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.dts +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "s32z270dc2_r52.dtsi" - -/ { - model = "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores"; - compatible = "nxp,s32z270"; - - chosen { - zephyr,sram = &sram0; - zephyr,canbus = &can0; - }; - - aliases { - watchdog0 = &swt0; - }; -}; - -&mru0 { - rx-channels = <1>; - status = "okay"; -}; - -&enetc_psi0 { - mboxes = <&mru0 0>; - mbox-names = "rx"; -}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml deleted file mode 100644 index 891f6b3cce5982..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu0_r52 -name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml deleted file mode 100644 index 481ce3e63b2523..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu0_r52@D -name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores (rev. D) -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_defconfig b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_defconfig deleted file mode 100644 index 24074439953e31..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_S32Z270DC2_RTU0_R52=y -CONFIG_SOC_SERIES_S32ZE_R52=y -CONFIG_SOC_S32Z27_R52=y -CONFIG_XIP=n -CONFIG_ISR_STACK_SIZE=512 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 -CONFIG_ARM_MPU=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts deleted file mode 100644 index 1f74fe4a3a9a01..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.dts +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include "s32z270dc2_r52.dtsi" - -/ { - model = "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores"; - compatible = "nxp,s32z270"; - - chosen { - zephyr,sram = &sram1; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,canbus = &can0; - }; - - aliases { - watchdog0 = &swt0; - }; -}; - -&mru4 { - rx-channels = <1>; - status = "okay"; -}; - -&enetc_psi0 { - mboxes = <&mru4 0>; - mbox-names = "rx"; -}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml deleted file mode 100644 index de48e46091a723..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu1_r52 -name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml deleted file mode 100644 index 9f0a55547c1173..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.yaml +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -identifier: s32z270dc2_rtu1_r52@D -name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores (rev. D) -type: mcu -arch: arm -ram: 1024 -toolchain: - - zephyr -supported: - - uart - - gpio - - watchdog - - netif:eth - - can - - spi - - counter -vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_defconfig b/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_defconfig deleted file mode 100644 index e6c8aa46055784..00000000000000 --- a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_S32Z270DC2_RTU1_R52=y -CONFIG_SOC_SERIES_S32ZE_R52=y -CONFIG_SOC_S32Z27_R52=y -CONFIG_XIP=n -CONFIG_ISR_STACK_SIZE=512 -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 -CONFIG_ARM_MPU=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y diff --git a/boards/arm/sam4e_xpro/Kconfig.board b/boards/arm/sam4e_xpro/Kconfig.board deleted file mode 100644 index e0e214469923f9..00000000000000 --- a/boards/arm/sam4e_xpro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SAM4E Xplained Pro Board selection - -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM4E_XPRO - bool "Atmel SAM4E Xplained Pro" - depends on SOC_PART_NUMBER_SAM4E16E diff --git a/boards/arm/sam4e_xpro/Kconfig.defconfig b/boards/arm/sam4e_xpro/Kconfig.defconfig deleted file mode 100644 index e11bd8b37eeea6..00000000000000 --- a/boards/arm/sam4e_xpro/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Atmel SAM4E Xplained Pro Board configuration - -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM4E_XPRO - -config BOARD - default "sam4e_xpro" - -endif # BOARD_SAM4E_XPRO diff --git a/boards/arm/sam4e_xpro/doc/index.rst b/boards/arm/sam4e_xpro/doc/index.rst deleted file mode 100644 index dce8fc7a5c527d..00000000000000 --- a/boards/arm/sam4e_xpro/doc/index.rst +++ /dev/null @@ -1,191 +0,0 @@ -.. _sam4e_xpro: - -SAM4E Xplained Pro -################### - -Overview -******** - -The SAM4E Xplained Pro evaluation kit is a development platform to evaluate the -Atmel SAM4E series microcontrollers. - -.. image:: img/sam4e_xpro.jpg - :align: center - :alt: SAM4E Xplained Pro - -Hardware -******** - -- ATSAM4E16E ARM Cortex-M4F Processor -- 12 MHz crystal oscillator -- internal 32.768 kHz crystal oscillator -- 2 x IS61WV5128BLL 4Mb SRAM -- MT29F2G08ABAEAWP 2Gb NAND -- SD card connector -- CAN-bus (TLE7250GVIOXUMA1 CAN Transceiver) -- Ethernet port (KSZ8081MNXIA phy) -- Micro-AB USB device -- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data - Gateway Interface (DGI) -- One reset and one user pushbutton -- 1 yellow user LEDs - - -Supported Features -================== - -The sam4e_xpro board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam4e_xpro/sam4e_xpro_defconfig`. - -Connections and IOs -=================== - -The `SAM4E Xplained Pro User Guide`_ has detailed information about board -connections. Download the `SAM4E Xplained Pro documentation`_ for more detail. - -System Clock -============ - -The SAM4E MCU is configured to use the 12 MHz internal oscillator on the board -with the on-chip PLL to generate an 120 MHz system clock. - -Serial Port -=========== - -The ATSAM4E16E MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is -configured for the console and is available as a Virtual COM Port by EDBG USB -chip. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM4E MCU requires the `OpenOCD tool`_. -By default a factory new SAM4E chip will boot SAM-BA boot loader located in -the ROM, not the flashed image. This is determined by the value of GPNVM1 -(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is -set to 1 changing the default behavior to boot from Flash. - -If your chip has a security bit GPNVM0 set you will be unable to program flash -memory or connect to it via a debug interface. The only way to clear GPNVM0 -is to perform a chip erase procedure that will erase all GPNVM bits and the full -contents of the SAM4E flash memory: - -- With the board power off, set a jumper on the J304 header. -- Turn the board power on. The jumper can be removed soon after the power is on - (flash erasing procedure is started when the erase line is asserted for at - least 230ms) - -Flashing -======== - -For flash the board Zephyr provides two paths. One uses the default OpenOCD -tool and the second one uses :ref:`atmel_sam_ba_bootloader`. - -Using OpenOCD -------------- - -#. Connect the SAM4E Xplained Pro board to your host computer using the USB - debug port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4e_xpro - :goals: build flash - -Using SAM-BA bootloader ------------------------ - -#. Close the ``ERASE`` jumper on the SAM4E Xplained Pro board. Power on the - board for 10s. - -#. Open the ``ERASE`` jumper. - -#. Connect the SAM4E Xplained Pro board to your host computer using the SoC - USB port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4e_xpro - :goals: build - - .. code-block:: console - - $ west flash -r bossac - -Visualizing the message ------------------------ - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Press reset button - - You should see "Hello World! sam4e_xpro" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4e_xpro - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _SAM4E Xplained Pro User Guide: - http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42216-SAM4E-Xplained-Pro_User-Guide.pdf - -.. _SAM4E Xplained Pro documentation: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4E-Xplained-Pro_Design-Documentation.zip - -.. _OpenOCD tool: - http://openocd.org/ - -.. _SAM-BA: - https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/arm/sam4e_xpro/sam4e_xpro_defconfig b/boards/arm/sam4e_xpro/sam4e_xpro_defconfig deleted file mode 100644 index c5380342d78247..00000000000000 --- a/boards/arm/sam4e_xpro/sam4e_xpro_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM4E=y -CONFIG_SOC_PART_NUMBER_SAM4E16E=y -CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK=y -CONFIG_BOARD_SAM4E_XPRO=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam4l_ek/Kconfig.board b/boards/arm/sam4l_ek/Kconfig.board deleted file mode 100644 index 1c0987a045f80c..00000000000000 --- a/boards/arm/sam4l_ek/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SAM4L-EK selection - -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM4L_EK - bool "Atmel SAM4L-EK" - depends on SOC_PART_NUMBER_SAM4LC4C diff --git a/boards/arm/sam4l_ek/Kconfig.defconfig b/boards/arm/sam4l_ek/Kconfig.defconfig deleted file mode 100644 index 315afa1b31261c..00000000000000 --- a/boards/arm/sam4l_ek/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Atmel SAM4L-EK Board configuration - -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM4L_EK - -config BOARD - default "sam4l_ek" - -endif # BOARD_SAM4L_EK diff --git a/boards/arm/sam4l_ek/doc/index.rst b/boards/arm/sam4l_ek/doc/index.rst deleted file mode 100644 index ee5d71201718d9..00000000000000 --- a/boards/arm/sam4l_ek/doc/index.rst +++ /dev/null @@ -1,172 +0,0 @@ -.. _sam4l_ek: - -SAM4L-EK -######## - -Overview -******** - -The SAM4L series embeds picoPower technology for ultra-low power consumption. -Combined power control techniques are used to bring active current consumption -down to 90μA/MHz. The device allows a wide range of configurations giving the -user the ability to balance between the lowest possible power consumption and -the feature set selected for the application. The WAIT and RETENTION modes -provide full logic and RAM retention, associated with fast wake-up capability -(<1.5μs) and a very low consumption of, respectively, 3 μA and 1.5 μA. In -addition, WAIT mode supports SleepWalking features. In BACKUP mode, CPU, -peripherals and RAM are powered off consuming less than 0.9μA with external -interrupt wake-up support. - -The SAM4L-EK is a full featured design to develop for Atmel SAM4L SoC series. -The kit is equipped with a rich set of peripherals that make the ATSAM4L-EK a -perfect evaluation platform. Download the `SAM4L-EK Online User Guide`_ for -more details. - -.. image:: img/atmel-sam4l-ek-callouts.jpg - :align: center - :alt: SAM4L-EK - -Hardware -******** - -- ATSAM4LC4C ARM Cortex-M4 Processor -- 12 MHz crystal oscillator -- 32.768 kHz crystal oscillator -- 1 Micro-AB USB OTG host/device -- 1 AT86RF2xx IEEE 802.15.4 transceiver connector -- 1 RS-485 full duplex interface -- 1 Sensor Xplained board connector -- 1 Audio Jack connector 3.5mm -- 1 Dedicated Board Monitor MCU - - - Power measurement (VDDIN, VDDIO, VDDANA) - - 1 OLED Display (128x64) - - 5 LEDs - - 1 Joystick - - 1 USART - - 1 TWI -- 1 40x4 LCD Segment Display -- 1 user touch button and One user pushbutton -- 1 user LED -- 1 QTouch Slider -- 1 QTouch Button -- 1 TEMT6000 Light Sensor -- 1 AT25DF641A Serial NOR Flash - -Supported Features -================== - -The sam4l_ek board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique 120 bit serial number | -+-----------+------------+-------------------------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | 32-bit True Random Number Generator | -+-----------+------------+-------------------------------------+ -| TWIM | on-chip | i2c master port-interrupt | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam4l_ek/sam4l_ek_defconfig`. - -Connections and IOs -=================== - -The `SAM4L-EK Design Documentation`_ has detailed information about board -connections. Download the `SAM4L-EK Design Documentation`_ for more details. - -System Clock -============ - -The SAM4L MCU is configured to use the 12 MHz internal oscillator on the board -with the on-chip PLL to generate an 48 MHz system clock. - -Serial Port -=========== - -The ATSAM4LC4C MCU has 4 USARTs. One of the USARTs (USART2) is connected on -the embedded debug unit and can works as a console. The USART0 is shared -between all others headers and RS-485 port. - -Programming and Debugging -************************* - -The SAM4L-EK board have a Segger Embedded Debugger Unit -`J-Link OB `_. This provides a debug -interface to the SAM4LC4C chip. You can use Ozone or JLink to communicate with -the SAM4LC4C. - -Flashing -======== - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the SAM4L-EK board to your host computer using the USB debug port. - Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4l_ek - :goals: build flash - - You should see "Hello World! sam4l_ek" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4l_ek - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _SAM4L-EK Online User Guide: - http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42026-ATSAM4L-EK-User-Guide_ApplicationNote_AVR32850.pdf - -.. _SAM4L-EK Design Documentation: - http://ww1.microchip.com/downloads/en/DeviceDoc/doc42027_SAM4L-EK_Design_Documentation.PDF - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink diff --git a/boards/arm/sam4l_ek/sam4l_ek_defconfig b/boards/arm/sam4l_ek/sam4l_ek_defconfig deleted file mode 100644 index c5faaad19834be..00000000000000 --- a/boards/arm/sam4l_ek/sam4l_ek_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM4L=y -CONFIG_SOC_PART_NUMBER_SAM4LC4C=y -CONFIG_BOARD_SAM4L_EK=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam4s_xplained/Kconfig.board b/boards/arm/sam4s_xplained/Kconfig.board deleted file mode 100644 index 65ec186370b329..00000000000000 --- a/boards/arm/sam4s_xplained/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SAM4S Xplained Board selection - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM4S_XPLAINED - bool "Atmel SAM4S Xplained" - depends on SOC_PART_NUMBER_SAM4S16C diff --git a/boards/arm/sam4s_xplained/Kconfig.defconfig b/boards/arm/sam4s_xplained/Kconfig.defconfig deleted file mode 100644 index d201fa44209e67..00000000000000 --- a/boards/arm/sam4s_xplained/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Atmel SAM4S Xplained Board configuration - -# Copyright (c) 2017 Justin Watson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM4S_XPLAINED - -config BOARD - default "sam4s_xplained" - -endif # BOARD_SAM4S_XPLAINED diff --git a/boards/arm/sam4s_xplained/doc/index.rst b/boards/arm/sam4s_xplained/doc/index.rst deleted file mode 100644 index 092079cb984c2d..00000000000000 --- a/boards/arm/sam4s_xplained/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _sam4s_xplained: - -SAM4S Xplained -################ - -Overview -******** - -The SAM4S Xplained evaluation kit is a development platform to evaluate the -Atmel SAM4S series microcontrollers. - -.. image:: img/sam4s_xplained.jpg - :align: center - :alt: SAM4S Xplained - -Hardware -******** - -- ATSAM4S16C ARM Cortex-M4 Processor -- 12 MHz crystal oscillator -- internal 32.768 kHz crystal oscillator -- IS66WV51216DALL 8 Mb SRAM -- Micro-AB USB device -- Micro-AB USB debug interface supporting SEGGER OB and Virtual COM Port and - Data -- One reset and one user pushbutton -- 2 yellow user LEDs -- IC pads for external flash chip - -Supported Features -================== - -The sam4s_xplained board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ -| SMC | on-chip | memc (PSRAM) | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam4s_xplained/sam4s_xplained_defconfig`. - -Connections and IOs -=================== - -Download the `SAM4S Xplained Design Files`_ for more information. It has -full schematic and gerbers files. - -System Clock -============ - -The SAM4S MCU is configured to use the 12 MHz internal oscillator on the board -with the on-chip PLL to generate an 84 MHz system clock. - -Serial Port -=========== - -The ATSAM4S16C MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is -connected to the Segger J-Link OB chip (the AT91SAM3U4 is programmed to be -Segger J-Link OB). Segger J-Link OB brings the UART out as a virtual COM port. -The section flashing uses the UART from the Segger USB debug connection. - -Programming and Debugging -************************* - -The SAM4S Xplained board comes with Segger `J-Link OB `_. This provides a debug -interface to the SAM4S16C chip. You can use Ozone or JLink to communicate with -the SAM4S16C. - -Flashing -======== - -For flash the board Zephyr provides two paths. One uses the default JLink -tool and the second one uses :ref:`atmel_sam_ba_bootloader`. - -Using JLink -------------- - -#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section - "J-Link Software and Documentation Pack" and install the "J-Link Software - and Documentation pack for Linux". The application JLinkExe needs to be - accessible from your path. - -#. Connect the SAM4S Xplained board to your host computer using the USB debug - port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4s_xplained - :goals: build flash - - -Using SAM-BA bootloader ------------------------ - -#. Close the ``J25`` jumper on the SAM4S Xplained board. Power on the board - for 10s. - -#. Open the ``J25`` jumper. - -#. Connect the SAM4S Xplained board to your host computer using the SoC USB - port. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4s_xplained - :goals: build - - .. code-block:: console - - $ west flash -r bossac - - -Visualizing the message ------------------------ - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization string. - Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Press reset button - - You should see "Hello World! sam4s_xplained" in your terminal. - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam4s_xplained - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _SAM4S Xplained Online User Guide: - http://ww1.microchip.com/downloads/en/devicedoc/atmel-42075-sam4s-xplained-pro_user-guide.pdf - -.. _JLink Downloads Page: - https://www.segger.com/downloads/jlink - -.. _SAM4S Xplained Design Files: - http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4S-XPLD__KitsFiles.zip diff --git a/boards/arm/sam4s_xplained/sam4s_xplained_defconfig b/boards/arm/sam4s_xplained/sam4s_xplained_defconfig deleted file mode 100644 index 09f69d3220b69f..00000000000000 --- a/boards/arm/sam4s_xplained/sam4s_xplained_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAM4S=y -CONFIG_SOC_PART_NUMBER_SAM4S16C=y -CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK=y -CONFIG_BOARD_SAM4S_XPLAINED=y - -CONFIG_ARM_MPU=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_MEMC=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam_e70_xplained/Kconfig.board b/boards/arm/sam_e70_xplained/Kconfig.board deleted file mode 100644 index f7ff0b7c37d6a1..00000000000000 --- a/boards/arm/sam_e70_xplained/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Atmel SMART SAM E70 Xplained Board selection - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM_E70_XPLAINED - bool "Atmel SMART SAM E70 Xplained Board" - depends on SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70Q21B diff --git a/boards/arm/sam_e70_xplained/Kconfig.defconfig b/boards/arm/sam_e70_xplained/Kconfig.defconfig deleted file mode 100644 index ab33a8333f7d47..00000000000000 --- a/boards/arm/sam_e70_xplained/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# Atmel SMART SAM E70 Xplained Board configuration - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM_E70_XPLAINED - -config BOARD - default "sam_e70_xplained" - -if ETH_SAM_GMAC - -# Read MAC address from AT24MAC402 EEPROM - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS - default 0x9A - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE - default 1 - -config ETH_SAM_GMAC_MAC_I2C_EEPROM - default y - select I2C - -endif # ETH_SAM_GMAC - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_SAM_E70_XPLAINED diff --git a/boards/arm/sam_e70_xplained/doc/index.rst b/boards/arm/sam_e70_xplained/doc/index.rst deleted file mode 100644 index c7abfac8cc83bd..00000000000000 --- a/boards/arm/sam_e70_xplained/doc/index.rst +++ /dev/null @@ -1,187 +0,0 @@ -.. _sam_e70_xplained: - -SAM E70(B) Xplained -################### - -Overview -******** - -The SAM E70 Xplained evaluation kit is a development platform to evaluate the -Atmel SAM E70 series microcontrollers. The current version allows to use both -IC variations ATSAME70Q21A(B). - -.. image:: img/sam_e70_xplained.jpg - :align: center - :alt: SAM E70 Xplained - -Hardware -******** - -- ATSAME70Q21A(B) ARM Cortex-M7 Processor -- 12 MHz crystal oscillator -- 32.768 kHz crystal oscillator (not populated) -- AT24MAC402 EEPROM -- IS42S16100E 16 Mb SDRAM -- SD card connector -- Ethernet port -- Micro-AB USB device -- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data - Gateway Interface (DGI) -- JTAG interface connector -- One reset and one user pushbutton -- One green user LED - -Supported Features -================== - -The sam_e70_xplained board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC via AFEC | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | canbus | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig`. - -Connections and IOs -=================== - -The `SAME70-XPLD User Guide`_ has detailed information about board connections. - -System Clock -============ - -The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 300 MHz system clock. - -Serial Port -=========== - -The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the USARTs is -configured for the console and is available as a Virtual COM Port via EDBG USB -chip. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. -Support for Atmel SAM E microcontroller series was added in OpenOCD release -0.10.0, which was added in Zephyr SDK 0.9.2. - -By default a factory new SAM E70 chip will boot SAM-BA boot loader located in -the ROM, not the flashed image. This is determined by the value of GPNVM1 -(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is -set to 1 changing the default behavior to boot from Flash. - -If your chip has a security bit GPNVM0 set you will be unable to program flash -memory or connect to it via a debug interface. The only way to clear GPNVM0 -is to perform a chip erase procedure that will erase all GPNVM bits and the full -contents of the SAM E70 flash memory: - -- With the board power off, set a jumper on the J200 header. -- Turn the board power on. The jumper can be removed soon after the power is on - (flash erasing procedure is started when the erase line is asserted for at - least 230ms) - -Flashing -======== - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the SAM E70 Xplained board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` - application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_e70_xplained - :goals: build flash - - You should see "Hello World! sam_e70_xplained" in your terminal. - -#. To use the SoC variation B IC, you need type "sam_e70b_xplained". - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_e70b_xplained - :goals: build flash - - You should see "Hello World! sam_e70b_xplained" in your terminal. - -You can flash the image using an external debug adapter such as J-Link -or ULINK, connected to the 20-pin JTAG header. Supply the name of the -debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment -variable. OpenOCD will look for the appropriate interface -configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its -internal search path. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_e70_xplained - :maybe-skip-config: - :goals: debug - -References -********** - -SAM E70 Product Page: - http://www.atmel.com/products/microcontrollers/arm/sam-e.aspx - -.. _SAME70-XPLD User Guide: - http://www.atmel.com/Images/Atmel-44050-Cortex-M7-Microcontroller-SAM-E70-XPLD-Xplained_User-guide.pdf - -.. _OpenOCD tool: - http://openocd.org/ - -.. _SAM-BA: - http://www.atmel.com/tools/ATMELSAM-BAIN-SYSTEMPROGRAMMER.aspx diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained.dts b/boards/arm/sam_e70_xplained/sam_e70_xplained.dts deleted file mode 100644 index ee002c846fa98d..00000000000000 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained.dts +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2017 Piotr Mienkowski - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2020-2023 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_e70_xplained-common.dtsi" - -/ { - model = "Atmel SAM E70 Xplained board"; - compatible = "atmel,sam_e70_xplained", "atmel,same70q21", "atmel,same70"; -}; - -&tc0 { - status = "okay"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc0_qdec_default>; - pinctrl-names = "default"; -}; - -&tc1 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc1_qdec_default>; - pinctrl-names = "default"; -}; - -&tc2 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc2_qdec_default>; - pinctrl-names = "default"; -}; - -&tc3 { - status = "disabled"; - compatible = "atmel,sam-tc-qdec"; - - pinctrl-0 = <&tc3_qdec_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml b/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml deleted file mode 100644 index 714795a2104d3c..00000000000000 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: sam_e70_xplained -name: SAM E70 Xplained -type: mcu -arch: arm -ram: 384 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - dma - - netif:eth - - adc - - i2s - - gpio - - spi - - watchdog - - usb_device - - pwm - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig b/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig deleted file mode 100644 index 30cb50e4512625..00000000000000 --- a/boards/arm/sam_e70_xplained/sam_e70_xplained_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME70=y -CONFIG_SOC_PART_NUMBER_SAME70Q21=y -CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAME70_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA=1 -CONFIG_BOARD_SAM_E70_XPLAINED=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained.dts b/boards/arm/sam_e70_xplained/sam_e70b_xplained.dts deleted file mode 100644 index a26b519d4afe8d..00000000000000 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2020 Stephanos Ioannidis - * Copyright (c) 2020 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_e70_xplained-common.dtsi" - -/ { - model = "Atmel SAM E70B Xplained board"; - compatible = "atmel,sam_e70b_xplained", "atmel,same70q21b", "atmel,same70b"; -}; diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml b/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml deleted file mode 100644 index 8cd515dca40a69..00000000000000 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: sam_e70b_xplained -name: SAM E70 Xplained (Revision B) -type: mcu -arch: arm -ram: 384 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - netif:eth - - adc - - dac - - gpio - - spi - - watchdog - - usb_device - - pwm - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig b/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig deleted file mode 100644 index 5aba40c44008cb..00000000000000 --- a/boards/arm/sam_e70_xplained/sam_e70b_xplained_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME70=y -CONFIG_SOC_PART_NUMBER_SAME70Q21B=y -CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAME70_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA=1 -CONFIG_BOARD_SAM_E70_XPLAINED=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/sam_v71_xult/Kconfig.board b/boards/arm/sam_v71_xult/Kconfig.board deleted file mode 100644 index 9ca0469360e4c8..00000000000000 --- a/boards/arm/sam_v71_xult/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Atmel SMART SAM V71 Xplained Board selection - -# Copyright (c) 2019 Gerson Fernando Budke -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SAM_V71_XULT - bool "Atmel SMART SAM V71 Xplained Ultra Board" - depends on SOC_PART_NUMBER_SAMV71Q21 || SOC_PART_NUMBER_SAMV71Q21B diff --git a/boards/arm/sam_v71_xult/Kconfig.defconfig b/boards/arm/sam_v71_xult/Kconfig.defconfig deleted file mode 100644 index dca80a82289f77..00000000000000 --- a/boards/arm/sam_v71_xult/Kconfig.defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SMART SAM V71 Xplained Board configuration - -# Copyright (c) 2019 Gerson Fernando Budke -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SAM_V71_XULT - -config BOARD - default "sam_v71_xult" - -if ETH_SAM_GMAC - -# Read MAC address from AT24MAC402 EEPROM - -config ETH_SAM_GMAC_MAC_I2C_EEPROM - default y - select I2C - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS - default 0x9A - -config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE - default 1 - -endif # ETH_SAM_GMAC - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_SAM_V71_XULT diff --git a/boards/arm/sam_v71_xult/doc/index.rst b/boards/arm/sam_v71_xult/doc/index.rst deleted file mode 100644 index a61fe887d6a877..00000000000000 --- a/boards/arm/sam_v71_xult/doc/index.rst +++ /dev/null @@ -1,190 +0,0 @@ -.. _sam_v71_xplained_ultra: - -SAM V71(B) Xplained Ultra -######################### - -Overview -******** - -The SAM V71 Xplained Ultra evaluation kit is a development platform to -evaluate the Atmel SAM V71 series microcontrollers. The current version -allows to use both IC variations ATSAMV71Q21A(B). - -.. image:: img/sam_v71_xult.jpg - :align: center - :alt: SAM V71 Xplained Ultra - -Hardware -******** - -- ATSAMV71Q21A(B) ARM Cortex-M7 Processor -- 12 MHz crystal oscillator -- 32.768 kHz crystal oscillator -- Supercap backup -- AT24MAC402 EEPROM -- IS42S16100E 16 Mb SDRAM -- S25FL116K 16 Mb QSPI -- WM8904 low power stereo audio codec -- ATA6561 CAN Transceiver -- SD card connector with SDIO support -- Camera interface connector -- MediaLB connector -- Ethernet port -- Micro-AB USB device -- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data - Gateway Interface (DGI) -- JTAG interface connector -- One reset and two user pushbuttons -- Two yellow user LEDs - -Supported Features -================== - -The sam_v71_xplained_ultra board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| USART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC via AFEC | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CAN FD | on-chip | can | -+-----------+------------+-------------------------------------+ -| HWINFO | on-chip | Unique device serial number | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/sam_v71_xult/sam_v71_xult_defconfig`. - -Connections and IOs -=================== - -The `SAMV71-XULT User Guide`_ has detailed information about board -connections. - -System Clock -============ - -The SAM V71 MCU is configured to use the 12 MHz external oscillator on the -board with the on-chip PLL to generate a 300 MHz system clock. - -Serial Port -=========== - -The ATSAMV71Q21 MCU has five UARTs and three USARTs. USART1 is configured -for the console and is available as a Virtual COM Port via EDBG USB chip. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM V71 MCU requires the `OpenOCD tool`_. -By default a factory new SAM V71 chip will boot the `SAM-BA`_ boot loader -located in the ROM, not the flashed image. This is determined by the value -of GPNVM1 (General-Purpose NVM bit 1). The flash procedure will ensure that -GPNVM1 is set to 1 changing the default behavior to boot from Flash. - -If your chip has a security bit GPNVM0 set you will be unable to program flash -memory or connect to it via a debug interface. The only way to clear GPNVM0 -is to perform a chip erase procedure that will erase all GPNVM bits and the -full contents of the SAM V71 flash memory: - -- With the board power off, set a jumper on the J200 header. -- Turn the board power on. The jumper can be removed soon after the power is - on (flash erasing procedure is started when the erase line is asserted for - at least 230ms) - -Flashing -======== - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyACM0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the SAM V71 Xplained Ultra board to your host computer using the - USB debug port. Then build and flash the :ref:`hello_world` - application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_v71_xult - :goals: build flash - - You should see "Hello World! sam_v71_xult" in your terminal. - -#. To use the SoC variation B IC, you need type "sam_v71b_xult". - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_v71b_xult - :goals: build flash - - You should see "Hello World! sam_v71b_xult" in your terminal. - -You can flash the image using an external debug adapter such as J-Link -or ULINK, connected to the 20-pin JTAG header. Supply the name of the -debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment -variable. OpenOCD will look for the appropriate interface -configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its -internal search path. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sam_v71_xult - :maybe-skip-config: - :goals: debug - -References -********** - -SAM V71 Product Page: - https://www.microchip.com/design-centers/32-bit/sam-32-bit-mcus/sam-v-mcus - -.. _SAMV71-XULT User Guide: - http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42408-SAMV71-Xplained-Ultra_User-Guide.pdf - -.. _OpenOCD tool: - http://openocd.org/ - -.. _SAM-BA: - https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/arm/sam_v71_xult/sam_v71_xult.dts b/boards/arm/sam_v71_xult/sam_v71_xult.dts deleted file mode 100644 index 634da676e964d7..00000000000000 --- a/boards/arm/sam_v71_xult/sam_v71_xult.dts +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2017 Piotr Mienkowski - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2019-2020 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_v71_xult-common.dtsi" - -/ { - model = "Atmel SAM V71 Xplained Ultra board"; - compatible = "atmel,sam_v71_xult", "atmel,samv71q21", "atmel,samv71"; -}; diff --git a/boards/arm/sam_v71_xult/sam_v71_xult.yaml b/boards/arm/sam_v71_xult/sam_v71_xult.yaml deleted file mode 100644 index 010552029502b2..00000000000000 --- a/boards/arm/sam_v71_xult/sam_v71_xult.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: sam_v71_xult -name: SAM V71 Xplained Ultra -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - dma - - netif:eth - - adc - - arduino_gpio - - arduino_i2c - - arduino_spi - - gpio - - spi - - watchdog - - usb_device - - pwm - - xpro_gpio - - xpro_i2c - - xpro_serial - - xpro_spi - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_v71_xult/sam_v71_xult_defconfig b/boards/arm/sam_v71_xult/sam_v71_xult_defconfig deleted file mode 100644 index 3c82428d40e086..00000000000000 --- a/boards/arm/sam_v71_xult/sam_v71_xult_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMV71=y -CONFIG_SOC_PART_NUMBER_SAMV71Q21=y -CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA=1 -CONFIG_BOARD_SAM_V71_XULT=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult.dts b/boards/arm/sam_v71_xult/sam_v71b_xult.dts deleted file mode 100644 index 8f16beb951fe1b..00000000000000 --- a/boards/arm/sam_v71_xult/sam_v71b_xult.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2020 Stephanos Ioannidis - * Copyright (c) 2020 Gerson Fernando Budke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "sam_v71_xult-common.dtsi" - -/ { - model = "Atmel SAM V71B Xplained Ultra board"; - compatible = "atmel,sam_v71b_xult", "atmel,samv71q21b", "atmel,samv71b"; -}; diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult.yaml b/boards/arm/sam_v71_xult/sam_v71b_xult.yaml deleted file mode 100644 index 9dbb670075f53d..00000000000000 --- a/boards/arm/sam_v71_xult/sam_v71b_xult.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: sam_v71b_xult -name: SAM V71 Xplained Ultra (Revision B) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - netif:eth - - adc - - arduino_gpio - - arduino_i2c - - arduino_spi - - dac - - gpio - - spi - - watchdog - - usb_device - - pwm - - xpro_gpio - - xpro_i2c - - xpro_serial - - xpro_spi - - can - - hwinfo -vendor: atmel diff --git a/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig b/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig deleted file mode 100644 index bf9eea03a5d3b5..00000000000000 --- a/boards/arm/sam_v71_xult/sam_v71b_xult_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMV71=y -CONFIG_SOC_PART_NUMBER_SAMV71Q21B=y -CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA=1 -CONFIG_BOARD_SAM_V71_XULT=y -CONFIG_BUILD_OUTPUT_HEX=y - -CONFIG_ARM_MPU=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_HW_STACK_PROTECTION=y -CONFIG_WDT_DISABLE_AT_BOOT=y - -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_USART_SAM=y diff --git a/boards/arm/scobc_module1/Kconfig.board b/boards/arm/scobc_module1/Kconfig.board deleted file mode 100644 index 4a74754fb186a8..00000000000000 --- a/boards/arm/scobc_module1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Space Cubics OBC module 1 configuration - -# Copyright (c) 2021 Space Cubics, LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SCOBC_MODULE1 - bool "Space Cubics OBC Module 1" - depends on SOC_SERIES_ARM_DESIGNSTART diff --git a/boards/arm/scobc_module1/Kconfig.defconfig b/boards/arm/scobc_module1/Kconfig.defconfig deleted file mode 100644 index e80eb2226c83f5..00000000000000 --- a/boards/arm/scobc_module1/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Space Cubics OBC module 1 - -# Copyright (c) 2021 Space Cubics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SCOBC_MODULE1 - -config BOARD - default "scobc_module1" - -config CPU_CORTEX_M_HAS_SYSTICK - default y - -config CPU_HAS_ARM_MPU - default y - -config NUM_IRQS - default 7 - -endif # BOARD_SCOBC_MODULE1 diff --git a/boards/arm/scobc_module1/board.cmake b/boards/arm/scobc_module1/board.cmake deleted file mode 100644 index 50979050e38596..00000000000000 --- a/boards/arm/scobc_module1/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_SCOBC_MODULE1) - board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd-ftdi.cfg") - - include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -endif() diff --git a/boards/arm/scobc_module1/scobc_module1_defconfig b/boards/arm/scobc_module1/scobc_module1_defconfig deleted file mode 100644 index ecadcfc07bd92f..00000000000000 --- a/boards/arm/scobc_module1/scobc_module1_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ARM_DESIGNSTART=y -CONFIG_SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3=y -CONFIG_BOARD_SCOBC_MODULE1=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_ARM_MPU=n - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_XIP=n -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/seeeduino_xiao/Kconfig.board b/boards/arm/seeeduino_xiao/Kconfig.board deleted file mode 100644 index fb5a3d971b5ad8..00000000000000 --- a/boards/arm/seeeduino_xiao/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Seeeduino XIAO board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SEEEDUINO_XIAO - bool "Seeeduino XIAO" - depends on SOC_PART_NUMBER_SAMD21G18A diff --git a/boards/arm/seeeduino_xiao/Kconfig.defconfig b/boards/arm/seeeduino_xiao/Kconfig.defconfig deleted file mode 100644 index fb8f07b2e9da57..00000000000000 --- a/boards/arm/seeeduino_xiao/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Seeedunio XIAO board configuration - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "seeeduino_xiao" - depends on BOARD_SEEEDUINO_XIAO diff --git a/boards/arm/seeeduino_xiao/doc/index.rst b/boards/arm/seeeduino_xiao/doc/index.rst deleted file mode 100644 index 22693fed2ab6de..00000000000000 --- a/boards/arm/seeeduino_xiao/doc/index.rst +++ /dev/null @@ -1,176 +0,0 @@ -.. _seeeduino_xiao: - -Seeeduino XIAO -############## - -Overview -******** - -The Seeeduino XIAO is a tiny (20 mm x 17.5 mm) ARM development -board with onboard LEDs, USB port, and range of I/O broken out -onto 14 pins. - -.. image:: img/seeeduino_xiao.jpg - :align: center - :alt: Seeeduino XIAO - -Hardware -******** - -- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- Three user LEDs -- Native USB port - -Supported Features -================== - -The seeeduino_xiao board configuration supports the following hardware -features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| DMA | on-chip | Direct memory access | -+-----------+------------+------------------------------------------+ -| DAC | on-chip | Digital to analogue converter | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| HWINFO | on-chip | Hardware info | -+-----------+------------+------------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| I2C | on-chip | Inter-Integrated Circuit | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig`. - -Connections and IOs -=================== - -The `Seeeduino XIAO wiki`_ has detailed information about -the board including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 32 kHz external crystal -with the on-chip PLL generating the 48 MHz system clock. The internal -APB and GCLK unit are set up in the same way as the upstream Arduino -libraries. - -SPI Port -======== - -The SAMD21 MCU has 6 SERCOM based SPIs. On the XIAO, SERCOM0 can be put -into SPI mode and used to connect to devices over pin 9 (MISO), pin 10 -(MOSI), and pin 8 (SCK). - -I2C Port -======== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM2 is available on -pin 4 (SDA) and pin 5 (SCL). - -Serial Port -=========== - -The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM4 is -the Zephyr console and is available on pins 7 (RX) and 6 (TX). - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual -serial port that echos characters back to the host PC. - -DAC -=== - -The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On -the XIAO, the DAC is available on pin 0. - -Programming and Debugging -************************* - -The XIAO ships the BOSSA compatible UF2 bootloader. The bootloader can be -entered by shorting the RST and GND pads twice. - -Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader -will be entered automatically when you run :code:`west flash`. - -Flashing -======== - -#. Build the Zephyr kernel and the :ref:`hello_world` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: seeeduino_xiao - :goals: build - :compact: - -#. Connect the XIAO to your host computer using USB - -#. Connect a 3.3 V USB to serial adapter to the board and to the - host. See the `Serial Port`_ section above for the board's pin - connections. - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyUSB0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Short the RST and GND pads twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: seeeduino_xiao - :goals: flash - :compact: - - You should see "Hello World! seeeduino_xiao" in your terminal. - -References -********** - -.. target-notes:: - -.. _Seeeduino XIAO wiki: - https://wiki.seeedstudio.com/Seeeduino-XIAO/ - -.. _pinouts: - https://wiki.seeedstudio.com/Seeeduino-XIAO/#hardware-overview - -.. _schematic: - https://wiki.seeedstudio.com/Seeeduino-XIAO/#resourses diff --git a/boards/arm/segger_trb_stm32f407/Kconfig.board b/boards/arm/segger_trb_stm32f407/Kconfig.board deleted file mode 100644 index 2c1251e0bd6adc..00000000000000 --- a/boards/arm/segger_trb_stm32f407/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SEGGER-TRB-STM32F407 board configuration - -# Copyright (c) 2020, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SEGGER_TRB_STM32F407 - bool "SEGGER STM32F407 Trace Reference Board" - depends on SOC_STM32F407XE diff --git a/boards/arm/segger_trb_stm32f407/Kconfig.defconfig b/boards/arm/segger_trb_stm32f407/Kconfig.defconfig deleted file mode 100644 index a519fbf853f409..00000000000000 --- a/boards/arm/segger_trb_stm32f407/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SEGGER-TRB-STM32F407 board configuration - -# Copyright (c) 2020, Erwin Rol -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SEGGER_TRB_STM32F407 - -config BOARD - default "segger_trb_stm32f407" - -endif # BOARD_SEGGER_TRB_STM32F407 diff --git a/boards/arm/sensortile_box/Kconfig.board b/boards/arm/sensortile_box/Kconfig.board deleted file mode 100644 index 5341a09871afdb..00000000000000 --- a/boards/arm/sensortile_box/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SensorTile.box board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SENSORTILE_BOX - bool "SensorTile.box Development Board" - depends on SOC_STM32L4R9XX diff --git a/boards/arm/sensortile_box/Kconfig.defconfig b/boards/arm/sensortile_box/Kconfig.defconfig deleted file mode 100644 index 1f3d19b39cadae..00000000000000 --- a/boards/arm/sensortile_box/Kconfig.defconfig +++ /dev/null @@ -1,34 +0,0 @@ -# SensorTile.box board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SENSORTILE_BOX - -config BOARD - default "sensortile_box" - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n -config BT_HCI_VS_EXT - default n - -endif # BT - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_SENSORTILE_BOX diff --git a/boards/arm/sensortile_box/board.cmake b/boards/arm/sensortile_box/board.cmake deleted file mode 100644 index 2e222be114cfdf..00000000000000 --- a/boards/arm/sensortile_box/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") - -include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) diff --git a/boards/arm/sensortile_box_pro/Kconfig.board b/boards/arm/sensortile_box_pro/Kconfig.board deleted file mode 100644 index 14429705999101..00000000000000 --- a/boards/arm/sensortile_box_pro/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SENSORTILE_BOX_PRO board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SENSORTILE_BOX_PRO - bool "SENSORTILE_BOX_PRO Board" - depends on SOC_STM32U585XX diff --git a/boards/arm/sensortile_box_pro/Kconfig.defconfig b/boards/arm/sensortile_box_pro/Kconfig.defconfig deleted file mode 100644 index 48b55275be3dd7..00000000000000 --- a/boards/arm/sensortile_box_pro/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# SENSORTILE_BOX_PRO board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SENSORTILE_BOX_PRO - -config BOARD - default "sensortile_box_pro" - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y - -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n - -endif # BT - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -endif # LOG - -endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/arm/sensortile_box_pro/doc/index.rst b/boards/arm/sensortile_box_pro/doc/index.rst deleted file mode 100644 index bba5a4cb288be7..00000000000000 --- a/boards/arm/sensortile_box_pro/doc/index.rst +++ /dev/null @@ -1,386 +0,0 @@ -.. _sensortile_box_pro_board: - -ST SensorTile.box PRO -##################### - -Overview -******** - -The STEVAL-MKBOXPRO (SensorTile.box PRO) features an ARM Cortex-M33 based STM32U585AI MCU -and is a ready-to-use box kit for wireless IoT and wearable sensor platforms to help using -and developing apps based on remote motion and environmental sensor data. - -The SensorTile.box PRO board fits into a small plastic box with a long-life rechargeable -battery, and communicates with a standard smartphone through its Bluetooth interface, -providing data coming from the sensors. - -.. image:: img/sensortile_box_pro.jpg - :align: center - :alt: SensorTile.box PRO - -More information about the board can be found at the `SensorTile.box PRO website`_. - -Supported Features -****************** - -The SensorTile.box PRO provides motion, environmental, and audio -sensor data through either the BLE or USB protocols to a host application running -on a smartphone/PC to implement applications such as: - -- Pedometer optimized for belt positioning -- Baby crying detection with Cloud AI learning -- Barometer / environmental monitoring -- Vehicle / goods tracking -- Vibration monitoring -- Compass and inclinometer -- Sensor data logger - -(see `Motion and environmental sensors`_ section for the complete lists of available -sensors on board) - -Hardware -******** - -The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 -Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. -They operate at a frequency of up to 160 MHz. - -- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) - -- Security and cryptography - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) and password protected debug - - Root of trust thanks to unique boot entry and secure hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure data storage with hardware unique key (HUK) - - Secure Firmware Update support with TF-M - - 2 AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - Active tampers - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - - Active tampers - -- Clock management: - - - 4 to 50 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - - Internal 48 MHz with clock recovery - -- Power management - - - Embedded regulator (LDO) - - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling - -- RTC with HW calendar and calibration -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 17 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5 x 16-bit general purpose - - 4x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- ART accelerator - - - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and - external memories: up to 160 MHz, MPU, 240 DMIPS and DSP - - 4-Kbyte data cache for external memories - -- Memories - - - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles - - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON - - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - 2 Octo-SPI memory interfaces - -- Rich analog peripherals (independent supply) - - - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling - - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode - - 12-bit DAC, low-power sample and hold - - 2 operational amplifiers with built-in PGA - - 2 ultra-low-power comparators - -- Up to 22 communication interfaces - - - USB Type-C / USB power delivery controller - - USB OTG 2.0 full-speed controller - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) - - 1x FDCAN - - 2x SDMMC interface - - 16- and 4-channel DMA controllers, functional in Stop mode - - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with - sound-activity detection - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| -- True Random Number Generator (RNG) - -- Graphic features - - - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation - - 1 digital camera interface - -- Mathematical co-processor - - - CORDIC for trigonometric functions acceleration - - FMAC (filter mathematical accelerator) - - -More information about STM32U585AI can be found here: - -- `STM32U585 on www.st.com`_ -- `STM32U585 reference manual`_ - -Motion and environmental sensors -================================ - - - **LSM6DSV16X** 6-axis inertial measurement unit - (`lsm6dsv16x datasheet`_) - - **LIS2MDL** 3-axis magnetometer - (`lis2mdl datasheet`_) - - **LPS22DF** Altimeter / pressure sensor - (`lps22df datasheet`_) - - **LIS2DU12** 3-axis accelerometer - (`lis2du12 datasheet`_) - - **HTS221** Humidity sensor - (`hts221 datasheet`_) - - **STTS22H** Digital temperature sensor - (`stts22hh datasheet`_) - - **MP23db01HP** Microphone / audio sensor - (`mp23db01hp datasheet`_) - -Connections and IOs -=================== - -- 4x user LEDs - - - **led0** (Green) - - **led1** (Red - shared with BLE) - - **led2** (Yellow) - - **led3** (Blue) - - -- 4x buttons/switch - - - **User BT1** button, available to user application - - **User BT2** / **boot0** button, available to user application - but useful to let the SensorTile.box PRO enter DFU mode - if found pressed after h/w reset (see **rst** button and - `Programming and Debugging`_ section) - - **rst** button, used to reset the board (not available on case) - - **power** switch, used to Power on/off the board - -System Clock -============ - -SensorTile.box PRO System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default, the System clock is -driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator. -The system clock can be boosted to 120MHz. -The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz. - -Serial Port -=========== - -The SensorTile.box PRO has 4 U(S)ARTs. The UART4 is connected to JTAG/SWD connector -and may be used as console. - -USB interface -============= - -SensorTile.box PRO can be connected as a USB device to a PC host through its USB-C connector. -The final application may use it to declare SensorTile.box PRO device as belonging to a -certain standard or vendor class, e.g. a CDC, a mass storage or a composite device with both -functions. - -Console -======= - -There are two possible options for Zephyr console output: - -- through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter - can be used to connect SensorTile.box PRO and have both SWD and console lines available. - - To enable console and shell over UART - - - switch the console lines from cdc_acm to uart4 - (:file:`boards/arm/sensortile_box_pro/sensortile_box_pro.dts`) - - - comment out the USB configuration macros - (:file:`boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig`) - -.. code-block:: dts - :caption: boards/arm/sensortile_box_pro/sensortile_box_pro.dts - - / { - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - //zephyr,console = &cdc_acm_uart0; - //zephyr,shell-uart = &cdc_acm_uart0; - }; - }; - -.. code-block:: Kconfig - :caption: boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig - - # Comment out following USB config lines when - # switching console to UART - #CONFIG_USB_DEVICE_STACK=y - #CONFIG_USB_DEVICE_VID=0x0483 - #CONFIG_USB_DEVICE_PID=0x1235 - #CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC SensorTile.box PRO" - #CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - #CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n - - -- through USB as USB CDC/ACM class. This is the default case present in the board dts file. - -.. code-block:: dts - :caption: boards/arm/sensortile_box_pro/sensortile_box_pro.dts - - / { - chosen { - zephyr,console = &cdc_acm_uart0; - }; - }; - - &zephyr_udc0 { - cdc_acm_uart0: cdc_acm_uart0 { - compatible = "zephyr,cdc-acm-uart"; - }; - }; - - - -Console default settings are 115200 8N1. - -Programming and Debugging -************************* - -There are two alternative methods of flashing ST Sensortile.box Pro board: - -1. Using DFU software tools - - This method requires to enter STM32U585 ROM bootloader DFU mode - by powering up (or reset) the board while keeping the BOOT0 button pressed. - No additional hardware is required except a USB-C cable. This method is fully - supported by :ref:`flash-debug-host-tools`. - You can read more about how to enable and use the ROM bootloader by checking - the application note `AN2606`_ (STM32U585xx section). - -2. Using SWD hardware tools - - This method requires to connect additional hardware, like a ST-LINK/V3 - embedded debug tool, to the board SWD connector. - -DFU flashing -============ - -Install dfu-util ----------------- - -It is recommended to use at least v0.9 of dfu-util. The package available in -Debian and Ubuntu can be quite old, so you might have to build dfu-util from source. -Information about how to get the source code and how to build it can be found -at the `DFU-UTIL website`_ - -Flash an Application to SensorTile.box PRO ------------------------------------------- - -While pressing the BOOT0 button, connect the USB-C cable to the USB OTG SensorTile.box PRO -port and to your computer. The board should be forced to enter DFU mode. - -Check that the board is indeed in DFU mode: - -.. code-block:: console - - $ sudo dfu-util -l - dfu-util 0.9 - - Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. - Copyright 2010-2019 Tormod Volden and Stefan Schmidt - This program is Free Software and has ABSOLUTELY NO WARRANTY - Please report bugs to http://sourceforge.net/p/dfu-util/tickets/ - - Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=2, name="@OTP Memory /0x1FFF7000/01*0001Ke", serial="204A325D574D" - Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=1, name="@Option Bytes /0x1FF00000/01*040 e/0x1FF01000/01*040 e", serial="204A325D574D" - Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=0, name="@Internal Flash /0x08000000/512*0004Kg", serial="204A325D574D" - -You should see following confirmation on your Linux host: - -.. code-block:: console - - $ dmesg - usb 2-2: new full-speed USB device number 74 using xhci_hcd - usb 2-2: New USB device found, idVendor=0483, idProduct=df11 - usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 - usb 2-2: Product: STM32 BOOTLOADER - usb 2-2: Manufacturer: STMicroelectronics - usb 2-2: SerialNumber: 204A325D574D - -You can build and flash the provided sample application -(:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs -values on the console. - -References -********** - -.. target-notes:: - -.. _SensorTile.box PRO website: - https://www.st.com/en/evaluation-tools/steval-mkboxpro.html - -.. _STM32U585 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html - -.. _STM32U585 reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _lsm6dsv16x datasheet: - https://www.st.com/en/mems-and-sensors/lsm6dsv16x.html - -.. _lis2mdl datasheet: - https://www.st.com/en/mems-and-sensors/lis2mdl.html - -.. _lps22df datasheet: - https://www.st.com/en/mems-and-sensors/lps22df.html - -.. _lis2du12 datasheet: - https://www.st.com/en/mems-and-sensors/lis2du12.html - -.. _hts221 datasheet: - https://www.st.com/en/mems-and-sensors/hts221.html - -.. _stts22hh datasheet: - https://www.st.com/en/mems-and-sensors/stts22h.html - -.. _mp23db01hp datasheet: - https://www.st.com/en/mems-and-sensors/mp23db01hp.html - -.. _AN2606: - http://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf - -.. _DFU-UTIL website: - http://dfu-util.sourceforge.net/ diff --git a/boards/arm/serpente/Kconfig.board b/boards/arm/serpente/Kconfig.board deleted file mode 100644 index 5c2cb6dc83ef05..00000000000000 --- a/boards/arm/serpente/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Serpente board configuration -# Copyright (c) 2020 Alexander Falb -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SERPENTE - bool "Serpente" - depends on SOC_PART_NUMBER_SAMD21E18A diff --git a/boards/arm/serpente/Kconfig.defconfig b/boards/arm/serpente/Kconfig.defconfig deleted file mode 100644 index 911f7021ff7cc6..00000000000000 --- a/boards/arm/serpente/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# Serpente board configuration -# Copyright (c) 2020 Alexander Falb -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "serpente" - depends on BOARD_SERPENTE diff --git a/boards/arm/serpente/doc/index.rst b/boards/arm/serpente/doc/index.rst deleted file mode 100644 index c446103c71212d..00000000000000 --- a/boards/arm/serpente/doc/index.rst +++ /dev/null @@ -1,125 +0,0 @@ -.. _serpente: - -Arturo182 Serpente -################## - -Overview -******** - -The Serpente is a very small low-cost development and prototyping -board equipped with 4MiB flash storage, a PWM enabled RGB led and 6 I/O pins. -The board comes with 3 different USB connector options: USB Type-C plug, -USB Type-C socket and USB Type-A plug. - -.. image:: img/serpente.jpg - :align: center - :alt: Serpente Boards - -Hardware -******** - -- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz -- 256 KiB flash memory and 32 KiB of RAM -- Extra 4MiB SPI flash memory -- RGB User LED -- Reset button -- Native USB port - -Supported Features -================== - -The Serpente board configuration supports the -following hardware features: - -+-----------+------------+------------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==========================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------------+ -| Flash | on-chip | Can be used with LittleFS to store files | -+-----------+------------+------------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+------------------------------------------+ -| WDT | on-chip | Watchdog | -+-----------+------------+------------------------------------------+ -| GPIO | on-chip | I/O ports | -+-----------+------------+------------------------------------------+ -| PWM | on-chip | Pulse Width Modulation | -+-----------+------------+------------------------------------------+ -| USART | on-chip | Serial ports | -+-----------+------------+------------------------------------------+ -| SPI | on-chip | Serial Peripheral Interface ports | -+-----------+------------+------------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+------------------------------------------+ - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/serpente/serpente_defconfig`. - -Connections and IOs -=================== - -The `Serpente documentation`_ has detailed information about the board -including `pinouts`_ and the `schematic`_. - -System Clock -============ - -The SAMD21 MCU is configured to use the 8MHz internal oscillator -with the on-chip PLL generating the 48 MHz system clock. - -USB Device Port -=============== - -The SAMD21 MCU has a USB device port that can be used to communicate -with a host PC. See the :ref:`usb-samples` sample applications for -more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which prints "Hello World!" -to the host PC. - -Programming and Debugging -========================= - -The Serpente ships the BOSSA compatible UF2 bootloader. The bootloader -can be entered by quickly tapping the reset button twice. - -Flashing -======== - -#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: serpente - :goals: build - :compact: - -#. Connect the Serpente to your host computer using USB - - -#. Tap the reset button twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: serpente - :goals: flash - :compact: - - You should see the User LED blink. - -References -********** - -.. target-notes:: - -.. _Serpente documentation: - https://www.solder.party/docs/serpente/r2/ - -.. _pinouts: - https://www.solder.party/docs/serpente/r2/pinout/ - -.. _schematic: - https://www.solder.party/docs/serpente/r2/downloads/ diff --git a/boards/arm/serpente/pre_dt_board.cmake b/boards/arm/serpente/pre_dt_board.cmake deleted file mode 100644 index 9be9a0b97715c6..00000000000000 --- a/boards/arm/serpente/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - /soc/pinmux@41004400 & /soc/gpio@41004400 -# - /soc/pinmux@41004480 & /soc/gpio@41004480 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/serpente/serpente_defconfig b/boards/arm/serpente/serpente_defconfig deleted file mode 100644 index b670a7b0476c18..00000000000000 --- a/boards/arm/serpente/serpente_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21E18A=y -CONFIG_BOARD_SERPENTE=y -CONFIG_SOC_ATMEL_SAMD_OSC8M=y -CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y diff --git a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.board b/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.board deleted file mode 100644 index c27c19c2812a23..00000000000000 --- a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Pete Johanson -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SPARKFUN_PRO_MICRO_RP2040 - bool "Sparkfun Pro-Micro RP2040 Board" - depends on SOC_RP2040 diff --git a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.defconfig b/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.defconfig deleted file mode 100644 index eb2066e98a98b9..00000000000000 --- a/boards/arm/sparkfun_pro_micro_rp2040/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2021 Pete Johanson -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SPARKFUN_PRO_MICRO_RP2040 - -config BOARD - default "sparkfun_pro_micro_rp2040" - -config RP2_FLASH_W25Q080 - default y - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_SPARKFUN_PRO_MICRO_RP2040 diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig b/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig deleted file mode 100644 index 78e7bbd4530c07..00000000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.board b/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.board deleted file mode 100644 index 504107a7b2cbe7..00000000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.board +++ /dev/null @@ -1,23 +0,0 @@ -# Sparkfun nRF9160 Thing Plus configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF9160_SICA - -config BOARD_SPARKFUN_THING_PLUS_NRF9160 - bool "Sparkfun nRF9160 Thing Plus" - # The GPIO driver is required by this board's initialization code - # (board.c), so it is forced here to be enabled always, not only - # enabled by default (in defconfig). - select GPIO - -config BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - bool "Sparkfun nRF9160 Thing Plus non-secure" - # The GPIO driver is required by this board's initialization code - # (board.c), so it is forced here to be enabled always, not only - # enabled by default (in defconfig). - select GPIO - -endif # SOC_NRF9160_SICA diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.defconfig b/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.defconfig deleted file mode 100644 index 8ae5b832d8951b..00000000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Circuit Dojo nRF9160 Feather configuration - -# Copyright (c) 2018-2020 Nordic Semiconductor ASA -# Copyright (c) 2020 Circuit Dojo LLC -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SPARKFUN_THING_PLUS_NRF9160 || BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - -config BOARD - default "sparkfun_thing_plus_nrf9160" - -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - depends on BOARD_SPARKFUN_THING_PLUS_NRF9160 && TRUSTED_EXECUTION_SECURE - -if BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_SPARKFUN_THING_PLUS_NRF9160_NS - -endif # BOARD_SPARKFUN_THING_PLUS_NRF9160 || BOARD_SPARKFUN_THING_PLUS_NRF9160_NS diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/doc/index.rst b/boards/arm/sparkfun_thing_plus_nrf9160/doc/index.rst deleted file mode 100644 index 8ee7a38cb338e2..00000000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/doc/index.rst +++ /dev/null @@ -1,153 +0,0 @@ -.. _sparkfun_thing_plus_nrf9160: - -nRF9160 Thing Plus -################## - -.. figure:: img/sparkfun_thing_plus_nrf9160.jpg - :align: center - :alt: Sparkfun nRF9160 Thing Plus - - nRF9160 Thing Plus (Credit: Sparkfun) - -Overview -******** - -The nRF9160 Thing Plus designed by Circuit Dojo is a single-board development -for bringing your LTE-M and NB-IoT applications to life. The sparkfun_thing_plus_nrf9160 -board configuration leverages the pre-existing support for the Nordic Semiconductor -nRF9160. Supported nRF9160 peripherals include: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` -* :abbr:`WDT (Watchdog Timer)` -* :abbr:`IDAU (Implementation Defined Attribution Unit)` - -More information about the board can be found at the -`nRF9160 Thing Plus Documentation`_. - - -Hardware -******** - -Connections and IOs -=================== - -The nRF9160 Thing Plus has everything you know and love about -the Feather platform. Here are some of the highlights: - -LED ---- - -* D7 (blue) = P0.03 - -Push buttons and Switches -------------------------- - -* MODE = P0.12 -* RESET - -USB ---- - -Contains a USB/UART connection for both debugging and loading new -code using a UART Enabled MCUBoot. - -Standard Battery Connection ----------------------------- - -The nRF9160 Thing Plus has a 2 pin battery connector on board. Lithium Polymer batteries > -300mA required. - -Nano SIM Holder ---------------- - -The nRF9160 Thing Plus has a built-in nano SIM (4FF) holder located -on the bottom side. - - -Programming and Debugging -************************* - -sparkfun_thing_plus_nrf9160 can be used with most programmers like: - -* J-Link (the nRF53-DK is recommended) -* CMSIS-DAP based programmers - -Check out `Getting Started`_ for more info. - -Building an application -======================= - -In most cases you'll want to use the ``ns`` target with any of the Zephyr -or Nordic based examples. - -Some of the examples do not use secure mode, so they do not required the ``ns`` suffix. -A great example of this is the `hello_world` below. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ screen /dev/ 115200 - -Replace :code:`` with the port where the nRF9160 Thing Plus -can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: sparkfun_thing_plus_nrf9160 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons on the nRF9160 Thing Plus -****************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -* :zephyr:code-sample:`blinky` -* :zephyr:code-sample:`button` - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common.dtsi`. - -References -********** - -.. target-notes:: - -**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for -developing a great platform! - -.. _nRF9160 Thing Plus Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html -.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_defconfig b/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_defconfig deleted file mode 100644 index 8748d5dd83ce73..00000000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_SPARKFUN_THING_PLUS_NRF9160=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns_defconfig b/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns_defconfig deleted file mode 100644 index 92818ef157baef..00000000000000 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns_defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF91X=y -CONFIG_SOC_NRF9160_SICA=y -CONFIG_BOARD_SPARKFUN_THING_PLUS_NRF9160_NS=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable TrustZone-M -CONFIG_ARM_TRUSTZONE_M=y - -# This Board implies building Non-Secure firmware -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# Hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_REGULATOR=y diff --git a/boards/arm/steval_fcu001v1/Kconfig.board b/boards/arm/steval_fcu001v1/Kconfig.board deleted file mode 100644 index dc0b41e59e401a..00000000000000 --- a/boards/arm/steval_fcu001v1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32 Flight Controller Unit board configuration - -# Copyright (c) 2019 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STEVAL_FCU001V1 - bool "STM32 Flight Controller Unit" - depends on SOC_STM32F401XC diff --git a/boards/arm/steval_fcu001v1/Kconfig.defconfig b/boards/arm/steval_fcu001v1/Kconfig.defconfig deleted file mode 100644 index 6c4e715a676830..00000000000000 --- a/boards/arm/steval_fcu001v1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32 Flight Controller Unit board configuration - -# Copyright (c) 2019 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STEVAL_FCU001V1 - -config BOARD - default "steval_fcu001v1" - -endif # BOARD_STEVAL_FCU001V1 diff --git a/boards/arm/steval_fcu001v1/doc/index.rst b/boards/arm/steval_fcu001v1/doc/index.rst deleted file mode 100644 index 823631dd12079e..00000000000000 --- a/boards/arm/steval_fcu001v1/doc/index.rst +++ /dev/null @@ -1,158 +0,0 @@ -.. _steval_fcu001v1: - -ST STM32 Flight Controller Unit -############################### - -Overview -******** - -The STEVAL-FCU001V1 is a Cortex M4 MCU-based flight controller unit for toy quad-copter drones. - -.. figure:: img/steval_fcu001v1.jpg - :align: center - :alt: STM32 Flight Controller Unit - -Hardware -******** - -STM32 Flight Controller Unit provides the following hardware components: - -- STM32F401CC in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg|-M4 MCU with FPU -- 84MHz max MCU frequency -- VDD from 1.7 V to 3.6 V -- 256 KB FLASH -- 64 KB SRAM -- General Purpose Timers -- Watchdog Timers (2) -- On board sensors: - - - 3D Accelerometer and 3D Gyroscope: LSM6DSL - - 3D Magnetometer: LIS2MDL - - MEMS Pressure sensor: LPS22HD - -- 2 User LEDS -- USART/UART (1) -- I2C (1) -- Bluetooth LE over SPI - -More information about the STM32 Flight Controller Unit -can be found in these documents: - -- `STEVAL_FCU001V1 website`_ -- `STM32F401 reference manual`_ -- `STM32F401CC on www.st.com`_ - -Supported Features -================== - -The Zephyr steval_fcu001v1 board configuration supports the following hardware features: - -+-----------+------------+------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+------------------------------------+ - - -The default configuration can be found in the defconfig file: -``boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig`` - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C2 SCL/SDA : PB10/PB3 -- PWM_2_CH1 : PA0 -- LD1 : PB5 -- LD2 : PB4 - -System Clock -============ - -The steval_fcu001v1 system clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the system clock is driven by the PLL clock at 84MHz, -driven by a 16MHz high-speed external clock. - -Serial Port -=========== - -The steval_fcu001v1 board has one UART. The Zephyr console output is assigned to UART1. -Default settings are 115200 8N1. - -I2C -=== - -The steval_fcu001v1 board has one I2C. The default I2C mapping for Zephyr is: - -- I2C2_SCL : PB10 -- I2C2_SDA : PB3 - -Programming and Debugging -************************* - -Applications for the ``steval_fcu001v1`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Flashing Zephyr onto the steval_fcu001v1 board requires an external ST-LINK/V2-1 programmer. -The programmer is attached to the P8 programming header with ARM-JTAG-20-10-Plug-in Adapter. - -Flashing an application to STEVAL_FCU001V1 ------------------------------------------- - -Connect the FT232-to-USB port to host system, and RX, TX, Gnd pins to -the P7 header of the steval_fcu001v1 board. Then run a serial host -program to connect with your steval_fcu001v1 via the FT232 board: - -.. code-block:: console - - $ minicom -D /dev/ttyUSB0 - -Now build and flash an application. Here is an example for :ref:`hello_world` - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: steval_fcu001v1 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! steval_fcu001v1 - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: steval_fcu001v1 - :maybe-skip-config: - :goals: debug - -.. _STEVAL_FCU001V1 website: - https://www.st.com/en/evaluation-tools/steval-fcu001v1.html - -.. _STM32F401CC on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html - -.. _STM32F401 reference manual: - https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/stm3210c_eval/Kconfig.board b/boards/arm/stm3210c_eval/Kconfig.board deleted file mode 100644 index 8e55fc27f860e1..00000000000000 --- a/boards/arm/stm3210c_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM3210C-EVAL board configuration - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM3210C_EVAL - bool "STM3210C-EVAL Evaluation Board" - depends on SOC_STM32F107XC diff --git a/boards/arm/stm3210c_eval/Kconfig.defconfig b/boards/arm/stm3210c_eval/Kconfig.defconfig deleted file mode 100644 index 2f60b5842744b6..00000000000000 --- a/boards/arm/stm3210c_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM3210C-EVAL board configuration - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM3210C_EVAL - -config BOARD - default "stm3210c_eval" - -endif # BOARD_STM3210C_EVAL diff --git a/boards/arm/stm3210c_eval/doc/index.rst b/boards/arm/stm3210c_eval/doc/index.rst deleted file mode 100644 index 9d9278e1614be0..00000000000000 --- a/boards/arm/stm3210c_eval/doc/index.rst +++ /dev/null @@ -1,165 +0,0 @@ -.. _stm3210c_eval_board: - -ST STM3210C Evaluation -###################### - -Overview -******** -The STM3210C-EVAL evaluation board is a complete development platform for STMicroelectronic's -ARM Cortex-M3 core-based STM32F107VCT microcontroller. - -The range of hardware features on the board help you to evaluate all peripherals -(USB-OTG FS, ethernet, motor control, CAN, microSD CardTM, smartcard, USART, -audio DAC, MEMS, EEPROM and more) and develop your own applications. - -Extension headers make it easy to connect a daughterboard or wrapping board for your specific -application. - -.. image:: img/stm3210c_eval.jpg - :align: center - :alt: STM3210C-EVAL - -More information about the board can be found at the `STM3210C-EVAL website`_. - -Hardware -******** - -STM3210C-EVAL provides the following hardware components: - -- Three 5 V power supply options: - - Power jack - - USB connector - - daughterboard -- Boot from user Flash, system memory or SRAM. -- I2S audio DAC, stereo audio jack. -- 2 GByte (or more) microSD CardTM. -- Both type A and B smartcard support. -- I2C compatible serial interface 64 Kbit EEPROM, MEMS and I/O expander. -- RS-232 communication. -- IrDA transceiver. -- USB-OTG full speed, USB microAB connector. -- IEEE-802.3-2002 compliant ethernet connector. -- Two channels of CAN2.0A/B compliant connection. -- Inductor motor control connector. -- JTAG and trace debug support. -- 3.2" 240x320 TFT color LCD with touch screen. -- Joystick with 4-direction control and selector. -- Reset, Wakeup, Tamper and User button. -- 4 color LEDs. -- RTC with backup battery. -- MCU consumption measurement circuit. -- Extension connector for daughterboard or wrapping board. - -More information about STM32F107VCT can be found here: - - `STM32F107VCT reference manual`_ - - -Supported Features -================== - -The Zephyr stm3210c_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file -:zephyr_file:`boards/arm/stm3210c_eval/stm3210c_eval_defconfig`. - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/stm3210c_eval_connectors.jpg - :align: center - :alt: STM3210C_EVAL connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PB9 -- LED2 : PD13 - -Programming and Debugging -************************* - -Flashing -======== - -STM3210C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. -At power-on, the board is in firmware-upgrade mode (also called DFU for -"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. -This interface is supported by the openocd version included in Zephyr SDK. - -Applications for the ``stm3210c_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing an application to STM3210C-EVAL ----------------------------------------- - -Connect the STM3210C-EVAL to your host computer using the USB port, then build -and flash an application in the usual way. - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm3210c_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can run a serial host program to connect with your STM3210C-EVAL board. For -example, on Linux: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm3210c_eval - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM3210C-EVAL website: - https://www.st.com/en/evaluation-tools/stm3210c-eval.html - -.. _STM32F107VCT reference manual: - https://www.st.com/resource/en/reference_manual/CD00171190.pdf diff --git a/boards/arm/stm3210c_eval/stm3210c_eval_defconfig b/boards/arm/stm3210c_eval/stm3210c_eval_defconfig deleted file mode 100644 index c282e80fd587c5..00000000000000 --- a/boards/arm/stm3210c_eval/stm3210c_eval_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F1X=y - -# Platform Configuration -CONFIG_SOC_STM32F107XC=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# RCC Controller -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32373c_eval/Kconfig.board b/boards/arm/stm32373c_eval/Kconfig.board deleted file mode 100644 index 5348461a9d3871..00000000000000 --- a/boards/arm/stm32373c_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32373C-EVAL evaluation board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32373C_EVAL - bool "STM32373C_EVAL Evaluation Board" - depends on SOC_STM32F373XC diff --git a/boards/arm/stm32373c_eval/Kconfig.defconfig b/boards/arm/stm32373c_eval/Kconfig.defconfig deleted file mode 100644 index aa615e68bdb78e..00000000000000 --- a/boards/arm/stm32373c_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32373C-EVAL evaluation board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32373C_EVAL - -config BOARD - default "stm32373c_eval" - -endif # BOARD_STM32373C_EVAL diff --git a/boards/arm/stm32373c_eval/doc/index.rst b/boards/arm/stm32373c_eval/doc/index.rst deleted file mode 100644 index 9f6ed1d750b663..00000000000000 --- a/boards/arm/stm32373c_eval/doc/index.rst +++ /dev/null @@ -1,159 +0,0 @@ -.. _stm32373c_eval_board: - -ST STM32373C Evaluation -####################### - -Overview -******** -The STM32373C-EVAL evaluation board is designed as a complete demonstration and development platform for STMicroelectronics ARM Cortex-M4 core-based STM32F373VCT6 microcontroller. - -The full range of hardware features on the board can help the user evaluate all peripherals (USB FS, USART, audio DAC, microphone ADC, dot-matrix LCD, IrDA, LDR, MicroSD card, HDMI CEC, ECG, pressure sensor, CAN, IR transmitter and receiver, EEPROM, touch slider, temperature sensor, etc.) and develop their own applications. - -Extension headers make it possible to easily connect a daughter board or wrapping board for a specific application. - -.. image:: img/stm32373c_eval.jpg - :align: center - :alt: STM32373C-EVAL - -More information about the board can be found at the `STM32373C-EVAL website`_. - -Hardware -******** - -STM32373C-EVAL provides the following hardware components: - -- STM32F373VCT6 microcontroller -- Four 5 V power supply options: - - Power jack - - ST-LINK/V2 USB connector - - User USB connector - - Daughter board -- Audio jack connected to I2 S DAC -- Microphone connected to ADC through an amplifier -- 2-GByte (or more) MicroSD card on SPI -- Three components on I2 C bus: temperature sensor, EEPROM and dual interface RF EEPROM -- RS-232 communication configurable for communication of Flash loader -- IrDA transceiver -- 240x320 TFT color LCD connected to SPI interface -- Joystick with 4-direction control and selector -- Reset, Wakeup or Tamper, and Key buttons -- 4 color user LEDs -- 2 LEDs for MCU power range indicator -- ECG, pressure sensor and PT100 temperature sensor connected to the 16-bit Sigma Delta ADC of STM32F373VCT6 -- Extension connectors for daughter board or wrapping board -- MCU voltage: 3.3 V or adjustable 2.0 V - 3.6 V -- USB FS connector -- Touch slider -- RTC with backup battery -- CAN 2.0 A/B compliant connection -- Light dependent resistor (LDR) -- Two HDMI connectors with DDC and CEC -- IR transmitter and receiver -- Two ADC & DAC input and output signal connectors and one Sigma Delta ADC input signal connector -- Potentiometer -- JTAG/SWD and ETM trace debug support -- Embedded ST-LINK/V2 - -More information about STM32F373VCT6 can be found here: - - `STM32F373VCT6 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32373c_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file -:zephyr_file:`boards/arm/stm32373c_eval/stm32373c_eval_defconfig` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/stm32373c_eval_connectors.jpg - :align: center - :alt: STM32373C_EVAL connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- USER_PB : PA2 -- LED2 : PC1 - -Programming and Debugging -************************* - -Applications for the ``stm32373c_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32373C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. -At power-on, the board is in firmware-upgrade mode (also called DFU for -"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32373C-EVAL ------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32373c_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32373c_eval - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32373C-EVAL website: - https://www.st.com/en/evaluation-tools/stm32373c-eval.html - -.. _STM32F373VCT6 reference manual: - https://www.st.com/resource/en/reference_manual/dm00041563.pdf diff --git a/boards/arm/stm32_min_dev/Kconfig.board b/boards/arm/stm32_min_dev/Kconfig.board deleted file mode 100644 index 3b648714ddbd39..00000000000000 --- a/boards/arm/stm32_min_dev/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Minimum Development Board Configuration - -# Copyright (c) 2017, embedjournal.com -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32_MIN_DEV_BLUE - bool "STM32 Minimum Development Board (Blue)" - depends on SOC_STM32F103X8 - -config BOARD_STM32_MIN_DEV_BLACK - bool "STM32 Minimum Development Board (Black)" - depends on SOC_STM32F103X8 diff --git a/boards/arm/stm32_min_dev/Kconfig.defconfig b/boards/arm/stm32_min_dev/Kconfig.defconfig deleted file mode 100644 index 6e38ec4db12334..00000000000000 --- a/boards/arm/stm32_min_dev/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# STM32 Minimum Development Board Configuration - -# Copyright (c) 2017, embedjournal.com -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32_MIN_DEV_BLUE || BOARD_STM32_MIN_DEV_BLACK - -config BOARD - default "stm32_min_dev_blue" if BOARD_STM32_MIN_DEV_BLUE - default "stm32_min_dev_black" if BOARD_STM32_MIN_DEV_BLACK - -endif # BOARD_STM32_MIN_DEV_BLUE || BOARD_STM32_MIN_DEV_BLACK diff --git a/boards/arm/stm32_min_dev/doc/index.rst b/boards/arm/stm32_min_dev/doc/index.rst deleted file mode 100644 index 6d83f0f7ec783c..00000000000000 --- a/boards/arm/stm32_min_dev/doc/index.rst +++ /dev/null @@ -1,186 +0,0 @@ -.. _stm32_min_dev: - -STM32 Minimum Development Board -############################### - -Overview -******** - -The STM32 Minimum Development Board, is a popular and inexpensive -breadboard-friendly breakout board for the `STM32F103x8`_ CPU. There -are two variants of the board: - -- Blue Pill Board -- Black Pill Board - -Zephyr applications can use the stm32_min_dev_blue or stm32_min_dev_black board -configuration to use these boards. - -.. figure:: img/stm32_min_dev.jpg - :align: center - :alt: STM32 Minimum Development Board - - STM32 Minimum Development Board - -As the name suggests, these boards have the bare minimum components required to -power on the CPU. For practical use, you'll need to add additional components -and circuits using a breadboard, for example. - -Pin Mapping -=========== - -This port is a starting point for your own customizations and not a complete -port for a specific board. Most of the GPIOs on the STM32 SoC has been exposed -in the external header with silk screen labels that match the SoC's pin names. - -Each board vendor has their own variations in pin mapping on their boards' -external connectors and placement of components. Many vendors use port PC13/PB12 -for connecting an LED, so only this device is supported by our Zephyr port. -Additional device support is left for the user to implement. - -More information on hooking up peripherals and lengthy how to articles can be -found at `EmbedJournal`_. - -The pinout diagram of STM32 Minimum Development Blue Pill board can be seen -below. The Black Pill's one is similar: - -.. figure:: img/stm32_min_dev_pinout_blue.jpg - :align: center - :alt: Pinout for STM32 Minimum Development Blue Pill Board - - Pinout for STM32 Minimum Development Blue Pill Board - - -STLinkV2 connection: -==================== - -The board can be flashed by using STLinkV2 with the following connections. - -+--------+---------------+ -| Pin | STLINKv2 | -+========+===============+ -| G | GND | -+--------+---------------+ -| CLK | Clock | -+--------+---------------+ -| IO | SW IO | -+--------+---------------+ -| V3 | VCC | -+--------+---------------+ - -Boot Configuration -================== - -The boot configuration for this board is configured through jumpers on B0 (Boot 0) -and B1 (Boot 1). The pins B0 and B1 are present in between logic 0 and 1 lines. The -silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1 -respectively. - -+--------+--------+-------------------+---------------------------------------------+ -| Boot 1 | Boot 0 | Boot Mode | Aliasing | -+========+========+===================+=============================================+ -| X | 0 | Main Flash Memory | Main flash memory is selected as boot space | -+--------+--------+-------------------+---------------------------------------------+ -| 0 | 1 | System Memory | System memory is selected as boot space | -+--------+--------+-------------------+---------------------------------------------+ -| 1 | 1 | Embedded SRAM | Embedded SRAM is selected as boot space | -+--------+--------+-------------------+---------------------------------------------+ - - -Supported Features -================== - -The stm32_min_dev board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| NVIC | on-chip | nested vectored | -| | | interrupt controller | -+-----------+------------+----------------------+ -| SYSTICK | on-chip | system clock | -+-----------+------------+----------------------+ -| UART | on-chip | serial port | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C | on-chip | i2c | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| SPI | on-chip | spi | -+-----------+------------+----------------------+ -| USB | on-chip | USB device | -+-----------+------------+----------------------+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX: PA9/PA10 -- UART_2 TX/RX: PA2/PA3 -- UART_3 TX/RX: PB10/PB11 -- I2C_1 SCL/SDA : PB6/PB7 -- I2C_2 SCL/SDA : PB10/PB11 -- PWM_1_CH1: PA8 -- SPI_1 NSS_OE/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 -- SPI_2 NSS_OE/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 -- USB_DC DM/DP: PA11/PA12 -- ADC_1: PA0 - -System Clock ------------- - -The on-board 8Mhz crystal is used to produce a 72Mhz system clock with PLL. - -Serial Port ------------ - -STM32 Minimum Development Board has 3 U(S)ARTs. The Zephyr console output is -assigned to UART_1. Default settings are 115200 8N1. - -On-Board LEDs -------------- - -The board has one on-board LED that is connected to PB12/PC13 on the black/blue -variants respectively. - -Programming and Debugging -************************* - -Applications for the ``stm32_min_dev_(blue|black)`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32_min_dev_blue - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32_min_dev_blue - :maybe-skip-config: - :goals: debug - -.. _STM32F103x8: - https://www.st.com/resource/en/datasheet/stm32f103c8.pdf -.. _EmbedJournal: - https://embedjournal.com/tag/stm32-min-dev/ diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_black.dts b/boards/arm/stm32_min_dev/stm32_min_dev_black.dts deleted file mode 100644 index 80c283d24d93f8..00000000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_black.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2019, embedjournal.com - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include "stm32_min_dev.dtsi" - -/ { - model = "STM32 Minimum Development Board (Black)"; - compatible = "stm32_min_dev_black", "st,stm32f103c8"; - - leds { - led: led { - gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_black.yaml b/boards/arm/stm32_min_dev/stm32_min_dev_black.yaml deleted file mode 100644 index 28739cf2b63d51..00000000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_black.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: stm32_min_dev_black -name: STM32 Minimum Development Board (Black) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 20 -supported: - - i2c - - pwm - - spi - - adc - - gpio -vendor: st diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig b/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig deleted file mode 100644 index 53876bb7d4b4be..00000000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_black_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# STM32 Minimum Development Board Configuration -# -# Copyright (c) 2019, embedjournal.com -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103X8=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# enable clock control -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_blue.dts b/boards/arm/stm32_min_dev/stm32_min_dev_blue.dts deleted file mode 100644 index 8d0f3419b86694..00000000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_blue.dts +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2017, embedjournal.com - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include "stm32_min_dev.dtsi" - -/ { - model = "STM32 Minimum Development Board (Blue)"; - compatible = "stm32_min_dev_blue", "st,stm32f103c8"; - - leds { - led: led { - gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; - }; - }; -}; diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_blue.yaml b/boards/arm/stm32_min_dev/stm32_min_dev_blue.yaml deleted file mode 100644 index ed907a960ceea2..00000000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_blue.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: stm32_min_dev_blue -name: STM32 Minimum Development Board (Blue) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 20 -supported: - - i2c - - pwm - - spi - - adc -vendor: st diff --git a/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig b/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig deleted file mode 100644 index efc78388025d89..00000000000000 --- a/boards/arm/stm32_min_dev/stm32_min_dev_blue_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103X8=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable GPIO -CONFIG_GPIO=y - -# enable clock control -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f030_demo/Kconfig.board b/boards/arm/stm32f030_demo/Kconfig.board deleted file mode 100644 index 3a34ac759627ff..00000000000000 --- a/boards/arm/stm32f030_demo/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F030_DEMO - bool "STM32F030 DEMO Board" - depends on SOC_STM32F030X4 diff --git a/boards/arm/stm32f030_demo/Kconfig.defconfig b/boards/arm/stm32f030_demo/Kconfig.defconfig deleted file mode 100644 index 86e0233adad629..00000000000000 --- a/boards/arm/stm32f030_demo/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F030_DEMO - -config BOARD - default "stm32f030_demo" - -endif # BOARD_STM32F030_DEMO diff --git a/boards/arm/stm32f030_demo/doc/index.rst b/boards/arm/stm32f030_demo/doc/index.rst deleted file mode 100644 index a1f3ecd68e2001..00000000000000 --- a/boards/arm/stm32f030_demo/doc/index.rst +++ /dev/null @@ -1,123 +0,0 @@ -.. _stm32f030_demo: - -STM32F030 DEMO BOARD -#################### - -This board has the bare minimum components required to power on -the STM32F030F4P6 MCU. Most of the GPIOs on the STM32 SoC have -been exposed in the external headers with silk screen labels -that match the SoC's pin names. - -For practical use, you'll need to add additional components -and circuits using a breadboard, for example. - -.. image:: img/stm32f030_demo.jpg - :align: center - :alt: STM32F030 DEMO BOARD - -More information about the board can be found at the `stm32-base.org website`_. - -More information about STM32F030F4P6 can be found here: - -- `STM32F030 reference manual`_ -- `STM32F030 data sheet`_ - -Hardware -******** - -- STM32F030F4P6 ARM Cortex-M0 processor, frequency up to 48 MHz -- 16 KiB of flash memory and 4 KiB of RAM -- 8 MHz quartz crystal -- 1 user LED -- One reset button -- 2-way jumper (BOOT0) -- Serial (1x4 male dupont (2.54mm)) -- SWD (1x4 male dupont (2.54mm)) -- USB port (power only) - -Supported Features -================== - -The Zephyr stm32f030_demo board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f030_demo/stm32f030_demo_defconfig`` - -Pin Mapping -=========== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- LED : PA4 - -Programming and Debugging -************************* - -Applications for the ``stm32f030_demo`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The board can be flashed by using ST-LINKV2 in-circuit debugger and programmer. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F030 DEMO BOARD ------------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f030_demo - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f030_demo - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _stm32-base.org website: - https://stm32-base.org/boards/STM32F030F4P6-STM32F030-DEMO-BOARD-V1.1 - -.. _STM32F030 reference manual: - https://www.st.com/resource/en/reference_manual/dm00091010.pdf - -.. _STM32F030 data sheet: - https://www.st.com/resource/en/datasheet/stm32f030f4.pdf diff --git a/boards/arm/stm32f072_eval/Kconfig.board b/boards/arm/stm32f072_eval/Kconfig.board deleted file mode 100644 index 9db08b5f96ad24..00000000000000 --- a/boards/arm/stm32f072_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F072-EVAL board configuration - -# Copyright (c) 2017 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F072_EVAL - bool "STM32F072-EVAL Development Board" - depends on SOC_STM32F072XB diff --git a/boards/arm/stm32f072_eval/Kconfig.defconfig b/boards/arm/stm32f072_eval/Kconfig.defconfig deleted file mode 100644 index fa23a88cf1a646..00000000000000 --- a/boards/arm/stm32f072_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F072-EVAL board configuration - -# Copyright (c) 2017 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F072_EVAL - -config BOARD - default "stm32f072_eval" - -endif # BOARD_STM32F072_EVAL diff --git a/boards/arm/stm32f072_eval/doc/index.rst b/boards/arm/stm32f072_eval/doc/index.rst deleted file mode 100644 index 49b6577935c7c4..00000000000000 --- a/boards/arm/stm32f072_eval/doc/index.rst +++ /dev/null @@ -1,185 +0,0 @@ -.. _stm32f072_eval_board: - -ST STM32F072 Evaluation -####################### - -Overview -******** - -The STM32F072-EVAL Discovery kit features an ARM Cortex-M0 based STM32F072VBT6 MCU -with a wide range of connectivity support and configurations. -Here are some highlights of the STM32F072-EVAL board: - -- Four 5 V power supply options: power jack, ST-LINK/V2 USB connector, user USB connector, or daughter board -- Stereo audio jack, which supports a headset with microphone connected to DAC and ADC of STM32F072VBT6. -- 2G Byte (or more) SPI interface MicroSD card -- I2C compatible serial interface temperature sensor -- RF E2PROM -- RS232 and RS485 communication -- IrDA transceiver -- IR LED and IR receiver -- SWD debug support, ST-LINK/V2 embedded -- 240x320 TFT color LCD connected to SPI interface of STM32F072VBT6 -- Joystick with 4-direction control and selector -- Reset and tamper buttons -- Four color user LEDs and two LEDs as MCU low power alarm -- Extension connector for daughter board or wrapping board -- MCU voltage choice: fixed 3.3 V or adjustable from 1.65 V to 3.6 V -- USB full-speed connector -- Touch sensing buttons -- RTC with backup battery -- CAN2.0A/B compliant connector -- Light Dependent Resistor (LDR) -- Potentiometer -- Two HDMI connectors with DDC and CEC -- Smart Card slot -- Motor control connector - - -.. image:: img/stm32f072_eval.jpg - :align: center - :alt: STM32F072-EVAL - -Hardware -******** - -STM32F072-EVAL Discovery kit provides the following hardware components: - -- STM32F072VBT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M0 CPU -- 48 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 128 KB Flash -- 16 KB SRAM with HW parity -- GPIO with external interrupt capability -- one 12-bit ADC with 16 channels -- one 12-bit D/A converters with 2 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (8) -- Watchdog Timers (2) -- USART (4) -- I2C (2) -- SPI (2) -- CAN -- USB 2.0 OTG FS with on-chip PHY -- CRC calculation unit -- DMA Controller -- HDMI CEC Controller -- 24 capacitive sensing channels for touchkey, linear, and rotary touch sensors -- Up to 87 fast I/Os: 68 I/Os with 5V tolerant capability and 19 with independent supply - -More information about STM32F072VB can be found here: - - `STM32F072VB on www.st.com`_ - - `STM32F072 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f072_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f072_eval/stm32f072_eval_defconfig`` - - -Pin Mapping -=========== - -STM32F072-EVAL Discovery kit has 6 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to STM32F072-EVAL board User Manual. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- TAMPER_PB : PC13 -- JOYSTICK_RIGHT_PB : PE3 -- JOYSTICK_LEFT_PB : PF2 -- JOYSTICK_UP_PB : PF9 -- JOYSTICK_DOWN_PB : PF10 -- JOYSTICK_SEL_PB : PA0 -- LD1 : PD8 -- LD2 : PD9 -- LD3 : PD10 -- LD4 : PD11 - -System Clock -============ - -STM32F072-EVAL System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 48MHz, -driven by an 8MHz high speed internal clock. - -Serial Port -=========== - -STM32F072-EVAL Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f072_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F072-EVAL Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F072-EVAL -------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f072_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f072_eval - :maybe-skip-config: - :goals: debug - - -.. _STM32F072VB on www.st.com: - https://www.st.com/en/microcontrollers/stm32f072vb.html - -.. _STM32F072 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf diff --git a/boards/arm/stm32f072_eval/stm32f072_eval_defconfig b/boards/arm/stm32f072_eval/stm32f072_eval_defconfig deleted file mode 100644 index b5a9b9a376877c..00000000000000 --- a/boards/arm/stm32f072_eval/stm32f072_eval_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F072XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f072b_disco/Kconfig.board b/boards/arm/stm32f072b_disco/Kconfig.board deleted file mode 100644 index 26be5a346e89ae..00000000000000 --- a/boards/arm/stm32f072b_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F072B-DISCO board configuration - -# Copyright (c) 2017 Clage GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F072B_DISCO - bool "STM32F072B-DISCO Development Board" - depends on SOC_STM32F072XB diff --git a/boards/arm/stm32f072b_disco/Kconfig.defconfig b/boards/arm/stm32f072b_disco/Kconfig.defconfig deleted file mode 100644 index 75472bbad3d30c..00000000000000 --- a/boards/arm/stm32f072b_disco/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# STM32F072B-DISCO board configuration - -# Copyright (c) 2017 Clage GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F072B_DISCO - -config BOARD - default "stm32f072b_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_STM32F072B_DISCO diff --git a/boards/arm/stm32f072b_disco/doc/index.rst b/boards/arm/stm32f072b_disco/doc/index.rst deleted file mode 100644 index a2c51e51cddd74..00000000000000 --- a/boards/arm/stm32f072b_disco/doc/index.rst +++ /dev/null @@ -1,219 +0,0 @@ -.. _stm32f072b_disco_board: - -ST STM32F072B Discovery -####################### - -Overview -******** - -The STM32F072B-DISCO Discovery kit features an ARM Cortex-M0 based STM32F072RB -MCU with everything required for beginners and experienced users to get -started quickly. Here are some highlights of the STM32F072B-DISCO board: - -- STM32 microcontroller in LQFP64 package -- Extension header for LQFP64 I/Os for a quick connection to the prototyping - board and easy probing -- On-board ST-LINK/V2, debugger/programmer with SWD connector -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V - -- Six LEDs: - - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power on - - Four user LEDs: LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) - -- Two push-buttons: USER and RESET -- USB USER with Mini-B connector -- L3GD20, ST MEMS motion sensor, 3-axis digital output gyroscope -- One linear touch sensor or four touch keys -- RF EEprom daughter board connector - -.. image:: img/stm32f072b_disco.jpg - :align: center - :alt: STM32F072B-DISCO - -More information about the board can be found at the -`STM32F072B-DISCO website`_. - -Hardware -******** - -STM32F072B-DISCO Discovery kit provides the following hardware components: - -- STM32F072RBTT6 in LQFP64 package -- ARM |reg| 32-bit Cortex |reg| -M0 CPU -- 48 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 128 KB Flash -- 16 KB SRAM -- GPIO with external interrupt capability -- 12-bit ADC with 39 channels -- 12-bit D/A converters -- RTC -- General Purpose Timers (12) -- USART/UART (4) -- I2C (2) -- SPI (2) -- CAN -- USB 2.0 full speed interface -- DMA Controller -- 24 capacitive sensing channels for touchkey, linear and rotary touch sensors - -More information about STM32F072RB can be found here: - - `STM32F072RB on www.st.com`_ - - `STM32F072xB reference manual`_ - -Supported Features -================== - -The Zephyr stm32f072b_disco board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c controller | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | SPI controller | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F072B-DISCO Discovery kit has 6 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `STM32F072B-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- I2C1_SCL : PB8 -- I2C1_SDA : PB9 -- I2C2_SCL : PB10 -- I2C2_SDA : PB11 -- SPI1_SCK : PB3 -- SPI1_MISO : PB4 -- SPI1_MOSI : PB5 -- USER_PB : PA0 -- LD3 : PC6 -- LD4 : PC8 -- LD5 : PC9 -- LD6 : PC7 -- CAN_RX : PB8 -- CAN_TX : PB9 - -System Clock -============ - -STM32F072B-DISCO System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default System clock is driven -by PLL clock at 72 MHz, driven by internal 8 MHz oscillator. - -Serial Port -=========== - -STM32F072B-DISCO Discovery kit has up to 4 UARTs. The Zephyr console output -is assigned to UART 1. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f072b_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - - -Flashing an application to STM32F072B-DISCO -------------------------------------------- - -First, connect the STM32F072B-DISCO Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f072b_disco - :goals: build flash - -Run a serial host program to connect with your board. A TTL(3.3V) serial -adapter is required. - -.. code-block:: console - - $ minicom -D /dev/ - -Replace with the port where the serial adapter can be found. -For example, under Linux, /dev/ttyUSB0. - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f072b_disco - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32F072B-DISCO website: - https://www.st.com/en/evaluation-tools/32f072bdiscovery.html - - -.. _STM32F072B-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00099401.pdf - -.. _STM32F072RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32f072rb.html - -.. _STM32F072xB reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _SK Pang CAN breakout board: - https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-5v-logic diff --git a/boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig b/boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig deleted file mode 100644 index b5a9b9a376877c..00000000000000 --- a/boards/arm/stm32f072b_disco/stm32f072b_disco_defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F072XB=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# GPIO Controller -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f0_disco/Kconfig.board b/boards/arm/stm32f0_disco/Kconfig.board deleted file mode 100644 index 82e26ac2b2dee4..00000000000000 --- a/boards/arm/stm32f0_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F0DISCOVERY development board with STM32F051R8 MCU configuration - -# Copyright (c) 2018 Nathan Tsoi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F0_DISCO - bool "STM32F0DISCOVERY Development Board" - depends on SOC_STM32F051X8 diff --git a/boards/arm/stm32f0_disco/Kconfig.defconfig b/boards/arm/stm32f0_disco/Kconfig.defconfig deleted file mode 100644 index 638b4239522634..00000000000000 --- a/boards/arm/stm32f0_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F0 development board with STM32F051R8T6 MCU - -# Copyright (c) 2018 Nathan Tsoi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F0_DISCO - -config BOARD - default "stm32f0_disco" - -endif # BOARD_STM32F0_DISCO diff --git a/boards/arm/stm32f0_disco/doc/index.rst b/boards/arm/stm32f0_disco/doc/index.rst deleted file mode 100644 index daf0e1f06d39a6..00000000000000 --- a/boards/arm/stm32f0_disco/doc/index.rst +++ /dev/null @@ -1,143 +0,0 @@ -.. _stm32f0_disco_board: - -ST STM32F0 Discovery -#################### - -Overview -******** - -The STM32F0 Discovery development board uses an STM32F051R8T6 MCU and -integrates the ST-LINK/V2-1 debugger and programmer. It also comes with a -comprehensive STM32 software HAL library and various packaged software -examples. - -.. image:: img/stm32f0_disco.jpg - :align: center - :alt: STM32F0DISCOVERY - -More information about the board can be found at the `STM32F0DISCOVERY website`_. - -Hardware -******** - -The STM32 Discovery board features: - -- STM32F051R8T6 microcontroller featuring 64 KB Flash memory, 8 KB RAM in an - LQFP64 package -- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone - ST-LINK/V2 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- Four LEDs: - - - LD1 (red) for 3.3 V power on - - LD2 (red/green) for USB communication - - LD3 (green) for PC9 output - - LD4 (blue) for PC8 output -- Two push buttons (user and reset) -- Extension header for all LQFP64 I/Os for quick connection to prototyping board - and easy probing -- An additional board is provided which can be connected to the extension - connector for even easier prototyping and probing. -- Comprehensive free software including a variety of examples, part of - STM32CubeF0 package or STSW-STM32049 for legacy Standard Libraries usage - -More information about STM32F051R8 can be found in the `STM32F0x8 reference manual`_. - -Supported Features -================== - -The Zephyr stm32f0_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f0_disco/stm32f0_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 - -For more details please refer to `STM32F0DISCOVERY board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32f0_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F0DISCOVERY board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to Nucleo F030R8 ----------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f0_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f0_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32F0DISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32f0discovery.html - -.. _STM32F0x8 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031936.pdf - -.. _STM32F0DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00050135.pdf diff --git a/boards/arm/stm32f103_mini/Kconfig.board b/boards/arm/stm32f103_mini/Kconfig.board deleted file mode 100644 index c719f989076c51..00000000000000 --- a/boards/arm/stm32f103_mini/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F103RCT6 Mini board configuration - -# Copyright (c) 2020 WuhanStudio -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F103_MINI - bool "STM32F103RCT6 Mini Board" - depends on SOC_STM32F103XE diff --git a/boards/arm/stm32f103_mini/Kconfig.defconfig b/boards/arm/stm32f103_mini/Kconfig.defconfig deleted file mode 100644 index 294d123ccb1702..00000000000000 --- a/boards/arm/stm32f103_mini/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F103RCT6 Mini board configuration - -# Copyright (c) 2020 WuhanStudio -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F103_MINI - -config BOARD - default "stm32f103_mini" - -endif # BOARD_STM32F103_mini diff --git a/boards/arm/stm32f103_mini/doc/index.rst b/boards/arm/stm32f103_mini/doc/index.rst deleted file mode 100644 index 57e812d0c3a643..00000000000000 --- a/boards/arm/stm32f103_mini/doc/index.rst +++ /dev/null @@ -1,166 +0,0 @@ -.. _stm32f103_mini_board: - -STM32F103 Mini -################ - -Overview -******** - -The STM32F103_MINI board features an ARM Cortex-M3 based STM32F103RC MCU -with a wide range of connectivity support and configurations. There are -multiple version of this board like ``stm32f103_mini``. - -.. image:: img/stm32f103_mini_yellow.jpg - :align: center - :alt: STM32F103 Mini Yellow - -.. image:: img/stm32f103_mini_blue.jpg - :align: center - :alt: STM32F103 Mini Blue - -Hardware -******** -STM32F103 Mini provides the following hardware components: - -- STM32 microcontroller in QFP64 package - -- Flexible board power supply: - - - USB VBUS or external source (3.3V, 5V, 7 - 12V) - - Power management access point - -- Two LEDs: - - - User LED (LD1), power LED (LD2) - -- USB re-enumeration capability: - - - Mass storage - -More information about STM32F103RC can be found here: - -- `STM32F103 reference manual`_ -- `STM32F103 data sheet`_ - -Supported Features -================== - -The Zephyr stm32f103_mini board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f103_mini/stm32f103_mini_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Board connectors: ------------------ -.. image:: img/stm32f103_mini_pin.jpg - :align: center - :alt: Nucleo F103RB connectors - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX: PA9/PA10 -- UART_2 TX/RX: PA2/PA3 (ST-Link Virtual COM Port) -- SPI1 NSS/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 -- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 -- I2C1 SDA/SCL: PB9/PB8 -- PWM1_CH1: PA8 -- USER_PB: PC13 -- LD1: PA5 -- USB_DC DM/DP: PA11/PA12 - -System Clock ------------- - -The on-board 8MHz crystal is used to produce a 72MHz system clock with PLL. - -Programming and Debugging -************************* - -Applications for the ``stm32f103_mini`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -There are 2 main entry points for flashing STM32F1X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin. - -Flashing an application to stm32f103 mini ------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f103_mini - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f103_mini - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32F103 reference manual: - https://www.st.com/resource/en/reference_manual/cd00171190.pdf - -.. _STM32F103 data sheet: - https://www.st.com/resource/en/datasheet/stm32f103rc.pdf diff --git a/boards/arm/stm32f3_disco/Kconfig.board b/boards/arm/stm32f3_disco/Kconfig.board deleted file mode 100644 index 280b48f7cb575b..00000000000000 --- a/boards/arm/stm32f3_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F3DISCOVERY board configuration - -# Copyright (c) 2017 I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F3_DISCO - bool "STM32F3DISCOVERY Development Board" - depends on SOC_STM32F303XC diff --git a/boards/arm/stm32f3_disco/Kconfig.defconfig b/boards/arm/stm32f3_disco/Kconfig.defconfig deleted file mode 100644 index f2def3315709a8..00000000000000 --- a/boards/arm/stm32f3_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F3DISCOVERY board configuration - -# Copyright (c) 2017 I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F3_DISCO - -config BOARD - default "stm32f3_disco" - -endif # BOARD_STM32F3_DISCO diff --git a/boards/arm/stm32f3_disco/doc/index.rst b/boards/arm/stm32f3_disco/doc/index.rst deleted file mode 100644 index 5a0dc214e06ed4..00000000000000 --- a/boards/arm/stm32f3_disco/doc/index.rst +++ /dev/null @@ -1,281 +0,0 @@ -.. _stm32f3_disco_board: - -ST STM32F3 Discovery -#################### - -Overview -******** - -The STM32F3DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F303VC -MCU with everything required for beginners and experienced users to get -started quickly. Here are some highlights of the STM32F3DISCOVERY board: - -- STM32 microcontroller in LQFP100 package -- Extension header for all LQFP100 I/Os for quick connection to prototyping - board and easy probing -- On-board, ST-LINK/V2 for PCB version A or B or ST-LINK/V2-B for PCB version - C and newer, debugger/programmer with SWD connector -- Board power supply: through USB bus or from an external 3 V or 5 V supply - voltage -- External application power supply: 3 V and 5 V - -- Ten LEDs: - - - 3.3 V power on (LD1) - - USB communication (LD2) - - Eight user LEDs: red (LD3/LD10), blue (LD4/LD9), orange (LD5/LD9) - and green (LD6/LD7) - -- Two push-buttons: USER and RESET -- USB USER with Mini-B connector -- L3GD20 or I3G4250D, ST MEMS motion sensor, 3-axis digital output gyroscope -- LSM303DLHC or LSM303AGR, ST MEMS system-in-package featuring a 3D digital linear - acceleration sensor and a 3D digital magnetic sensor; - -.. HINT:: - Recent PCB revisions (E and newer) are shipped with I3G4250D and LSM303AGR. - -.. image:: img/stm32f3_disco.jpg - :align: center - :alt: STM32F3DISCOVERY - -More information about the board can be found at the -`STM32F3DISCOVERY website`_. - -Hardware -******** - -STM32F3DISCOVERY Discovery kit provides the following hardware components: - -- STM32F303VCT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 72 MHz max CPU frequency -- VDD from 2.0 V to 3.6 V -- 256 KB Flash -- 40 KB SRAM -- Routine booster: 8 Kbytes of SRAM on instruction and data bus -- GPIO with external interrupt capability -- 4x12-bit ADC with 39 channels -- 2x12-bit D/A converters -- RTC -- General Purpose Timers (13) -- USART/UART (5) -- I2C (2) -- SPI (3) -- CAN -- USB 2.0 full speed interface -- Infrared transmitter -- DMA Controller - -More information about STM32F303VC can be found here: - - `STM32F303VC on www.st.com`_ - - `STM32F303xC reference manual`_ - -Supported Features -================== - -The Zephyr stm32f3_disco board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN | -+-----------+------------+-------------------------------------+ -| IWDG | on-chip | Independent WatchDoG | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f3_disco/stm32f3_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F3DISCOVERY Discovery kit has 6 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `STM32F3DISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PC4 -- UART_1_RX : PC5 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- UART_4_TX : PC10 -- UART_4_RX : PC11 -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PA9 -- I2C2_SDA : PA10 -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- CAN1_RX : PD0 -- CAN1_TX : PD1 -- USB_DM : PA11 -- USB_DP : PA12 -- USER_PB : PA0 -- LD3 : PE9 -- LD4 : PE8 -- LD5 : PE10 -- LD6 : PE15 -- LD7 : PE11 -- LD8 : PE14 -- LD9 : PE12 -- LD10 : PE13 -- PWM : PA8 -- ADC1 : PA0 -- DAC1 : PA4 - -System Clock -============ - -STM32F3DISCOVERY System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default System clock is driven -by PLL clock at 72 MHz, driven by 8 MHz MCO from the ST Link. - -Serial Port -=========== - -STM32F3DISCOVERY Discovery kit has up to 5 UARTs. The Zephyr console output -is assigned to UART1. Default settings are 115200 8N1. - -I2C -=== - -STM32F3DISCOVERY has up to 2 I2Cs. I2C1 is connected to the LSM303DLHC and is -an ultra-compact low-power system-in-package featuring a 3D digital linear -acceleration sensor and a 3D digital magnetic sensor. - -USB -=== -STM32F3DISCOVERY has a USB 2.0 full-speed device interface available through -its mini USB connector (USB USER). - -CAN -=== -The STM32F3DISCOVERY does not have an onboard CAN transceiver. In -order to use the CAN bus on the this board, an external CAN bus -transceiver must be connected to ``PD0`` (``CAN1_RX``) and ``PD1`` -(``CAN1_TX``). - -Programming and Debugging -************************* - -Flashing -======== - -STM32F3DISCOVERY Discovery kit includes a ST-LINK/V2 or ST-LINK/V2-B embedded -debug tool interface. - -Applications for the ``stm32f3_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing an application to STM32F3DISCOVERY -------------------------------------------- - -First, connect the STM32F3DISCOVERY Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco - :goals: build flash - - -In case you are using a recent PCB revision (E or newer), you have to use an -adapted board definition: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco@E - :goals: build flash - -Run a serial host program to connect with your board. For PCB version A or B a -TTL(3.3V) serial adapter is required. For PCB version C and newer a Virtual Com -Port (VCP) is available on the USB ST-LINK port. - -.. code-block:: console - - $ minicom -D /dev/ - -Replace with the port where the STM32F3DISCOVERY board can be -found. For example, under Linux, /dev/ttyUSB0. - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco - :goals: debug - -Again you have to use the adapted command for newer PCB revisions (E and newer): - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f3_disco@E - :goals: debug - -.. _STM32F3DISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32f3discovery.html - -.. _STM32F3DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00063382.pdf - -.. _STM32F303VC on www.st.com: - https://www.st.com/en/microcontrollers/stm32f303vc.html - -.. _STM32F303xC reference manual: - https://www.st.com/resource/en/reference_manual/dm00043574.pdf diff --git a/boards/arm/stm32f3_disco/revision.cmake b/boards/arm/stm32f3_disco/revision.cmake deleted file mode 100644 index 0bacf78187d7c3..00000000000000 --- a/boards/arm/stm32f3_disco/revision.cmake +++ /dev/null @@ -1,4 +0,0 @@ -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION B -) \ No newline at end of file diff --git a/boards/arm/stm32f3_disco/stm32f3_disco.yaml b/boards/arm/stm32f3_disco/stm32f3_disco.yaml deleted file mode 100644 index 0d0aafdc5a25e2..00000000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: stm32f3_disco -name: ST STM32F3 Discovery -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 40 -supported: - - gpio - - i2c - - counter - - spi - - watchdog - - usb_device - - lsm303dlhc - - nvs - - can - - pwm - - adc - - dac - - dma -vendor: st diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_B.conf b/boards/arm/stm32f3_disco/stm32f3_disco_B.conf deleted file mode 100644 index 039adb70c587a1..00000000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco_B.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Jonathan Hahn -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_E.conf b/boards/arm/stm32f3_disco/stm32f3_disco_E.conf deleted file mode 100644 index 039adb70c587a1..00000000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco_E.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Jonathan Hahn -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_E.yaml b/boards/arm/stm32f3_disco/stm32f3_disco_E.yaml deleted file mode 100644 index 596deb44834def..00000000000000 --- a/boards/arm/stm32f3_disco/stm32f3_disco_E.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: stm32f3_disco@E -name: ST STM32F3 Discovery rev E -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 40 -supported: - - gpio - - i2c - - counter - - spi - - watchdog - - usb_device - - i3g4250d - - nvs - - can - - pwm - - adc - - dac diff --git a/boards/arm/stm32f3_seco_d23/Kconfig.board b/boards/arm/stm32f3_seco_d23/Kconfig.board deleted file mode 100644 index 94536f8f05e90d..00000000000000 --- a/boards/arm/stm32f3_seco_d23/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SECO SBC-3.5-PX30 board configuration - -# Copyright (c) 2022, SECO Spa -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F3_SECO_D23 - bool "SECO SBC-3.5-PX30 (STM32F302VC) Board" - depends on SOC_STM32F302XC diff --git a/boards/arm/stm32f3_seco_d23/Kconfig.defconfig b/boards/arm/stm32f3_seco_d23/Kconfig.defconfig deleted file mode 100644 index 4af3bbc0022b32..00000000000000 --- a/boards/arm/stm32f3_seco_d23/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SECO SBC-3.5-PX30 board configuration - -# Copyright (c) 2022, SECO Spa -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F3_SECO_D23 - -config BOARD - default "stm32f3_seco_d23" - -endif # BOARD_STM32F3_SECO_D23 diff --git a/boards/arm/stm32f401_mini/Kconfig.board b/boards/arm/stm32f401_mini/Kconfig.board deleted file mode 100644 index f2dc8bdfa612df..00000000000000 --- a/boards/arm/stm32f401_mini/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# STM32 Mini F401 Board - -config BOARD_STM32F401_MINI - bool "STM32 Mini F401 Board" - depends on SOC_STM32F401XC diff --git a/boards/arm/stm32f401_mini/Kconfig.defconfig b/boards/arm/stm32f401_mini/Kconfig.defconfig deleted file mode 100644 index 7279666dbcc744..00000000000000 --- a/boards/arm/stm32f401_mini/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Brian Bradley -# SPDX-License-Identifier: Apache-2.0 - -# STM32 Mini F401 board definitions - -if BOARD_STM32F401_MINI - -config BOARD - default "stm32f401_mini" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_STM32F401_MINI diff --git a/boards/arm/stm32f401_mini/doc/index.rst b/boards/arm/stm32f401_mini/doc/index.rst deleted file mode 100644 index 6465aec5ff507c..00000000000000 --- a/boards/arm/stm32f401_mini/doc/index.rst +++ /dev/null @@ -1,154 +0,0 @@ -.. _stm32f401_mini: - -STM32 Mini F401 -############### - -Overview -******** - -The STM32 Mini F401 is an extremely low cost and bare-bones -development board featuring the STM32F401CC, see `STM32F401CC website`_. -More info about the board with schematics available `here `_ - -.. image:: img/STM32_Mini_F401-1.jpg - :align: center - :alt: STM32 Mini F401 - -Hardware -******** - -The STM32F401CC based board provides the following -hardware components: - -- STM32F401CCU6 in UFQFPN48 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 84 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 256 KB Flash -- 64 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (4) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -Supported Features -================== - -The Zephyr stm32f401_mini board configuration supports the following -hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| SYSTICK | on-chip | system clock | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| FLASH | on-chip | flash | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB OTG FS | on-chip | USB device | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f401_mini/stm32f401_mini_defconfig`` - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 -- I2C1 SCL/SDA : PB8/PB9 -- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 -- PWM_4_CH1 : PB6 -- PWM_4_CH2 : PB7 -- ADC_1 : PA1 -- SW0 : PB2 (routed to BOOT1 dip switch) -- LED0 : PC13 - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is -32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. - -The default configuration sources the system clock from the PLL, which is -derived from HSE, and is set at 84MHz. - -Programming and Debugging -************************* - -There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM -bootloader, and another by using the SWD debug port (which requires additional -hardware). Flashing using the ROM bootloader requires a special activation -pattern, which can be triggered by using the BOOT0 pin, which on this board -is a dip switch. - -Flashing -======== - -Installing dfu-util -------------------- - -It is recommended to use at least v0.8 of `dfu-util`_. The package available in -debian/ubuntu can be quite old, so you might have to build dfu-util from source. - -There is also a Windows version which works, but you may have to install the -right USB drivers with a tool like `Zadig`_. - -Flashing an Application ------------------------ - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode -by setting the BOOT0 dip switch position to ON. Reset the board with the NRST button. - -The dfu-util runner is supported on this board and so a sample can be built and -tested easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f401_mini - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, -and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO -pins on that header. - -References -********** - -.. target-notes:: - -.. _Zadig: - https://zadig.akeo.ie/ - -.. _stm32-base-board-page: - https://stm32-base.org/boards/STM32F401CCU6-STM32-Mini-F401 - -.. _dfu-util: - http://dfu-util.sourceforge.net/build.html - -.. _STM32F401CC website: - https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html diff --git a/boards/arm/stm32f411e_disco/Kconfig.board b/boards/arm/stm32f411e_disco/Kconfig.board deleted file mode 100644 index 20906de1171efa..00000000000000 --- a/boards/arm/stm32f411e_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F411E-DISCO board configuration - -# Copyright (c) 2017 Fenix Engineering Solutions -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F411E_DISCO - bool "STM32F411E-DISCO Development Board" - depends on SOC_STM32F411XE diff --git a/boards/arm/stm32f411e_disco/Kconfig.defconfig b/boards/arm/stm32f411e_disco/Kconfig.defconfig deleted file mode 100644 index 28169b926e3051..00000000000000 --- a/boards/arm/stm32f411e_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F411E-DISCO board configuration - -# Copyright (c) 2017 Fenix Engineering Solutions -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F411E_DISCO - -config BOARD - default "stm32f411e_disco" - -endif # BOARD_STM32F411E_DISCO diff --git a/boards/arm/stm32f411e_disco/doc/index.rst b/boards/arm/stm32f411e_disco/doc/index.rst deleted file mode 100644 index 12a057ff1ade34..00000000000000 --- a/boards/arm/stm32f411e_disco/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. _stm32f411e_disco_board: - -ST STM32F411E Discovery -####################### - -Overview -******** - -The STM32F411E Discovery kit features an ARM Cortex-M4 based STM32F411VE MCU -with a wide range of connectivity support and configurations. -Here are some highlights of the STM32F411E-DISCO board: - -- STM32F411VET6 microcontroller featuring 512 KB of Flash memory, 128 KB of RAM in an LQFP100 package -- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone STLINK/V2 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- L3GD20(rev B) or I3G4250D(rev D): ST MEMS motion sensor, 3-axis digital output gyroscope. -- LSM303DLHC(rev B) or LSM303AGR(rev D): ST MEMS system-in-package featuring a 3D digital linear acceleration sensor and a 3D digital magnetic sensor. -- MP45DT02(rev B) or IMP34DT05(rev D), ST MEMS audio sensor, omnidirectional digital microphone -- CS43L22, audio DAC with integrated class D speaker driver -- Eight LEDs: - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power on - - Four user LEDs: - LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) - - Two USB OTG LEDs: - LD7 (green) VBus and LD8 (red) over-current -- Two pushbuttons (user and reset) -- USB OTG with micro-AB connector -- Extension header for LQFP100 I/Os for a quick connection to the prototyping board and an easy probing - -.. image:: img/stm32f411e_disco.jpg - :align: center - :alt: STM32F411E-DISCO - -More information about the board can be found at the `32F411EDISCOVERY website`_. - -Hardware -******** - -STM32F411E-DISCO Discovery kit provides the following hardware components: - -- STM32F411VET6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 512 KB Flash -- 128 KB SRAM -- GPIO with external interrupt capability -- 1x12-bit, 2.4 MSPS ADC with 16 channels -- DMA Controller -- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) -- USART/UART (3) -- I2C (3) -- SPI/I2S (5) -- SDIO -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- CRC calculation unit -- 96-bit unique ID -- RTC - -More information about STM32F411VE can be found here: - - `STM32F411VE website`_ - - `STM32F411x reference manual`_ - -Supported Features -================== - -The Zephyr stm32f411e_disco board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file -:zephyr_file:`boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig` - - -Pin Mapping -=========== - -STM32F411E-DISCO Discovery kit has 5 GPIO controllers. These controllers are -responsible for pin muxing, input/output, pull-up, etc. - -For more details please refer to `32F411EDISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- LD3 : PD13 (PWM4 CH2) -- LD4 : PD12 (PWM4 CH1) -- LD5 : PD14 (PWM4 CH3) -- LD6 : PD15 (PWM4 CH4) - -System Clock -============ - -STM32F411E-DISCO System Clock could be driven by an internal or external -oscillator, as well as the main PLL clock. By default, the System clock is -driven by the PLL clock at 100MHz, driven by the internal oscillator. - -Serial Port -=========== - -The STM32F411G Discovery kit has up to 3 UARTs. The Zephyr console output is -assigned to UART2. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32f411e_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F411E-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool -interface. This interface is supported by the openocd version included in -Zephyr SDK. - -Flashing an application to STM32F411E-DISCO -------------------------------------------- - -Connect the STM32F411E-DISCO Discovery kit to your host computer using the -USB port. Then build and flash an application. - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f411e_disco - :goals: build flash - -In case you are using PCB revision B, you have to use an -adapted board definition as the default PCB rev here is D: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f411e_disco@B - :goals: build flash - -You should see the orange led (LD3) blinking every second. - -Debugging -========= - -You can debug applications in the usual way. Here is an example for -the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f411e_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _32F411EDISCOVERY website: - https://www.st.com/en/evaluation-tools/32f411ediscovery.html - -.. _32F411EDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00148985.pdf - -.. _STM32F411VE website: - https://www.st.com/en/microcontrollers/stm32f411ve.html - -.. _STM32F411x reference manual: - https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/stm32f411e_disco/revision.cmake b/boards/arm/stm32f411e_disco/revision.cmake deleted file mode 100644 index 3a653a431a9911..00000000000000 --- a/boards/arm/stm32f411e_disco/revision.cmake +++ /dev/null @@ -1,4 +0,0 @@ -board_check_revision( - FORMAT LETTER - DEFAULT_REVISION D -) diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_B.conf b/boards/arm/stm32f411e_disco/stm32f411e_disco_B.conf deleted file mode 100644 index a6756435b9c6f2..00000000000000 --- a/boards/arm/stm32f411e_disco/stm32f411e_disco_B.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_D.conf b/boards/arm/stm32f411e_disco/stm32f411e_disco_D.conf deleted file mode 100644 index a6756435b9c6f2..00000000000000 --- a/boards/arm/stm32f411e_disco/stm32f411e_disco_D.conf +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/arm/stm32f412g_disco/Kconfig.board b/boards/arm/stm32f412g_disco/Kconfig.board deleted file mode 100644 index 1e0ba7aaae27df..00000000000000 --- a/boards/arm/stm32f412g_disco/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# STM32F412G-DISCO board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F412G_DISCO - bool "STM32F412G-DISCO Development Board" - depends on SOC_STM32F412ZX diff --git a/boards/arm/stm32f412g_disco/Kconfig.defconfig b/boards/arm/stm32f412g_disco/Kconfig.defconfig deleted file mode 100644 index d91c45fd1e841f..00000000000000 --- a/boards/arm/stm32f412g_disco/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# STM32F412G-DISCO board configuration - -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F412G_DISCO - -config BOARD - default "stm32f412g_disco" - -endif # BOARD_STM32F412G_DISCO diff --git a/boards/arm/stm32f412g_disco/doc/index.rst b/boards/arm/stm32f412g_disco/doc/index.rst deleted file mode 100644 index 8bd0bd588f10c4..00000000000000 --- a/boards/arm/stm32f412g_disco/doc/index.rst +++ /dev/null @@ -1,202 +0,0 @@ -.. _stm32f412g_disco_board: - -ST STM32F412G Discovery -####################### - -Overview -******** - -The STM32F412 Discovery kit features an ARM Cortex-M4 based STM32F412ZG MCU -with a wide range of connectivity support and configurations Here are -some highlights of the STM32F412G-DISCO board: - - -- STM32F412ZGT6 microcontroller featuring 1 Mbyte of Flash memory and 256 Kbytes of RAM in an LQFP144 package -- On-board ST-LINK/V2-1 SWD debugger supporting USB re-enumeration capability: - - - USB virtual COM port - - mass storage - - debug port - -- 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen -- I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker output -- Stereo digital MEMS microphones -- MicroSD card connector extension -- I2C extension connector -- 128 Mbit Quad-SPI Nor Flash -- Reset button and Joystick -- Four color user LEDs. -- USB OTG FS with Micro-AB connector -- Four power supply options: - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino* connectors - - + 5 V from Arduino* connectors - -- Two power supplies for MCU: 2.0 V and 3.3 V -- Compatible with Arduino(tm) Uno revision 3 connectors -- Extension connector for direct access to various features of STM32F412ZGT6 MCU -- Comprehensive free software including a variety of examples, part of STM32Cube package - -.. image:: img/stm32f412g_disco.jpg - :align: center - :alt: STM32F412G-DISCO - -More information about the board can be found at the `32F412GDISCOVERY website`_. - -Hardware -******** - -STM32F469I-DISCO Discovery kit provides the following hardware components: - -- STM32F412ZGT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 100 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 1 MB Flash -- 256 KB SRAM -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- 1x12-bit ADC with 16 channels -- RTC -- Advanced-control Timer -- General Purpose Timers (12) -- Watchdog Timers (2) -- USART/UART (4) -- I2C (4) -- SPI (5) -- SDIO -- 2xCAN -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F412ZG can be found here: - - `STM32F412ZG on www.st.com`_ - - `STM32F412 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f412g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F412G-DISCO Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F412GDISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- LD1 : PE0 -- LD2 : PE1 -- LD3 : PE2 -- LD4 : PE3 - -System Clock -============ - -STM32F412G-DISCO System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 100MHz, -driven internal oscillator. - -Serial Port -=========== - -The STM32F412G Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32f412g_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F412G-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F412G-DISCO -------------------------------------------- - -Connect the STM32F412G-DISCO Discovery kit to your host computer using -the USB port, then run a serial host program to connect with your -board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f412g_disco - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f412g_disco - :maybe-skip-config: - :goals: debug - -.. _32F412GDISCOVERY website: - https://www.st.com/en/evaluation-tools/32f412gdiscovery.html - -.. _32F412GDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00275919.pdf - -.. _STM32F412ZG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f412zg.html - -.. _STM32F412 reference manual: - https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/stm32f429i_disc1/Kconfig.board b/boards/arm/stm32f429i_disc1/Kconfig.board deleted file mode 100644 index 07ecfb82b69037..00000000000000 --- a/boards/arm/stm32f429i_disc1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F429I_DISC1 - bool "STM32F429I-DISC1 Development Board" - depends on SOC_STM32F429XX diff --git a/boards/arm/stm32f429i_disc1/Kconfig.defconfig b/boards/arm/stm32f429i_disc1/Kconfig.defconfig deleted file mode 100644 index b6e1113e010740..00000000000000 --- a/boards/arm/stm32f429i_disc1/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F429I_DISC1 - -config BOARD - default "stm32f429i_disc1" - -config INPUT - default y if DISPLAY - -config MEMC - default y if DISPLAY - -endif # BOARD_STM32F429I_DISC1 diff --git a/boards/arm/stm32f429i_disc1/doc/index.rst b/boards/arm/stm32f429i_disc1/doc/index.rst deleted file mode 100644 index 9b90abf0dbbb21..00000000000000 --- a/boards/arm/stm32f429i_disc1/doc/index.rst +++ /dev/null @@ -1,230 +0,0 @@ -.. _stm32f429i_disc1_board: - -ST STM32F429I Discovery -####################### - -Overview -******** - -The STM32F429I-DISC1 Discovery kit features an ARM Cortex-M4 based STM32F429ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32F429I-DISC1 board: - -- STM32 microcontroller in LQFP144 package -- Extension header for all LQFP144 I/Os for quick connection to prototyping board and easy probing -- On-board ST-LINK/V2-B debugger/programmer with SWD connector -- Flexible board power supply: - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino* compatible connectors - -- Two push-buttons: USER and RESET -- USB OTG FS with micro-AB connector -- 2.4-inch QVGA LCD with MIPI DSI interface and capacitive touch screen -- 64Mbit SDRAM -- L3GD20, ST-MEMS motion sensor 3-axis digital output gyroscope -- Six LEDs - - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power-on - - Two user LEDs: LD3 (green), LD4 (red) - - Two USB OTG LEDs: LD5 (green) VBUS and LD6 (red) OC (over-current) - -.. image:: img/stm32f429i_disc1.jpg - :align: center - :alt: STM32F429I-DISC1 - -More information about the board can be found at the `STM32F429I-DISC1 website`_. - -Hardware -******** - -The STM32F429I-DISC1 Discovery kit provides the following hardware components: - -- STM32F429ZIT6 in LQFP144 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 256+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (4/4) -- I2C (3) -- SPI (6) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F429ZI can be found here: - - `STM32F429ZI on www.st.com`_ - - `STM32F429 Reference Manual`_ - -Supported Features -================== - -The Zephyr stm32f429i_disc1 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| OTG_HS | on-chip | usbotg_hs | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig`` - - -Pin Mapping -=========== - -The STM32F429I-DISC1 Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32F429I-DISC1 board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- USER_PB : PA0 -- LD3 : PG13 -- LD4 : PG12 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB9 -- I2C_2_SCL : PB10 -- I2C_2_SDA : PB11 -- I2C_3_SCL : PA8 -- I2C_3_SDA : PC9 -- SPI_5_CS : PF6 -- SPI_5_SCK : PF7 -- SPI_5_MISO : PF8 -- SPI_5_MOSI : PF9 -- OTG_HS_ID : PB12 -- OTG_HS_DM : PB14 -- OTG_HS_DP : PB15 - -System Clock -============ - -The STM32F429I-DISC1 System Clock could be driven by an internal or external oscillator, -as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 168MHz, -driven by an 8MHz high speed external clock. - -Serial Port -=========== - -The STM32F429I-DISC1 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1. -The default communication settings are 115200 8N1. - -USB Port -=========== - -The STM32F429I-DISC1 Discovery kit has a USB FS capable Micro-B port. It is connected to the on-chip -OTG_HS peripheral, but operates in FS mode only since no HS PHY is present. The board supports device -and host OTG operation, but only device mode has been tested with Zephyr at this time. - -Programming and Debugging -************************* - -Applications for the ``stm32f429i_disc1`` board configuration can be built -and flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The STM32F429I-DISC1 Discovery kit includes a ST-LINK/V2-B embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F429I-DISC1 -------------------------------------------- - -The board is configured to be flashed using west OpenOCD runner. -Alternatively, you can use `STM32CubeProgrammer`_ (after installing it) using the ``--runner`` -(or ``-r``) option: - -.. code-block:: console - - $ west flash --runner stm32cubeprogrammer - -First, connect the STM32F429I-DISC1 Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f429i_disc1 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, press the RESET button (The black one), you should see the following message: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f429i_disc1 - :goals: debug - -.. _STM32F429I-DISC1 website: - https://www.st.com/en/evaluation-tools/32f429idiscovery.html - -.. _STM32F429I-DISC1 board User Manual: - https://www.st.com/web/en/resource/technical/document/user_manual/DM00097320.pdf - -.. _STM32F429ZI on www.st.com: - https://www.st.com/en/microcontrollers/stm32f429-439.html - -.. _STM32F429 Reference Manual: - https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32f469i_disco/Kconfig.board b/boards/arm/stm32f469i_disco/Kconfig.board deleted file mode 100644 index 5dc1cf80449386..00000000000000 --- a/boards/arm/stm32f469i_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F469I-DISCO board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F469I_DISCO - bool "STM32F469I-DISCO Development Board" - depends on SOC_STM32F469XX diff --git a/boards/arm/stm32f469i_disco/Kconfig.defconfig b/boards/arm/stm32f469i_disco/Kconfig.defconfig deleted file mode 100644 index 0afb292c333638..00000000000000 --- a/boards/arm/stm32f469i_disco/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32F469I-DISCO board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F469I_DISCO - -config BOARD - default "stm32f469i_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - - -endif # BOARD_STM32F469I_DISCO diff --git a/boards/arm/stm32f469i_disco/doc/index.rst b/boards/arm/stm32f469i_disco/doc/index.rst deleted file mode 100644 index 658f2a7b75e755..00000000000000 --- a/boards/arm/stm32f469i_disco/doc/index.rst +++ /dev/null @@ -1,208 +0,0 @@ -.. _stm32f469i_disco_board: - -ST STM32F469I Discovery -####################### - -Overview -******** - -The STM32F469 Discovery kit features an ARM Cortex-M4 based STM32F469NI MCU -with a wide range of connectivity support and configurations Here are -some highlights of the STM32F469I-DISCO board: - - -- STM32 microcontroller in BGA216 package -- On-board ST-LINK/V2-1 debugger/programmer, supporting USB reenumeration capability -- Flexible board power supply: - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino* compatible connectors - -- Four user LEDs -- Two push-buttons: USER and RESET -- USB OTG FS with micro-AB connector -- 4-inch 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive touch screen -- SAI Audio DAC, with a stereo headphone output jack -- Three MEMS microphones -- MicroSD card connector -- I2C extension connector -- 4Mx32bit SDRAM -- 128-Mbit Quad-SPI NOR Flash -- Expansion connectors and Arduino UNO V3 connectors - -.. image:: img/stm32f469i_disco.jpg - :align: center - :alt: STM32F469I-DISCO - -More information about the board can be found at the `32F469IDISCOVERY website`_. - -Hardware -******** - -STM32F469I-DISCO Discovery kit provides the following hardware components: - -- STM32F469NIH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 180 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 384+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- LCD TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (6) -- 1xSAI (serial audio interface) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F469NI can be found here: - - `STM32F469NI on www.st.com`_ - - `STM32F469 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f469i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| SDIO | on-chip | SD-card controller | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F469I-DISCO Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F469IDISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PG14/PG9 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SPI2 NSS/SCK/MISO/MOSI : PH6/PD3/PB14/PB15 (Arduino SPI) -- SDIO D0/D1/D2/D3/CLK/Detect : PC8/PC9/PC10/PC11/PC12/PG2 -- USB DM : PA11 -- USB DP : PA12 -- USER_PB : PA0 -- LD1 : PG6 -- LD2 : PD4 -- LD3 : PD5 -- LD4 : PK3 - -System Clock -============ - -STM32F469I-DISCO System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 180MHz, -driven by 8MHz high speed external clock. - -Serial Port -=========== - -The STM32F469 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART3. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32f469i_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F469I-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F469I-DISCO -------------------------------------------- - -First, connect the STM32F469I-DISCO Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f469i_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f469i_disco - :goals: debug - - -.. _32F469IDISCOVERY website: - https://www.st.com/en/evaluation-tools/32f469idiscovery.html - -.. _32F469IDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00218846.pdf - -.. _STM32F469NI on www.st.com: - https://www.st.com/en/microcontrollers/stm32f469ni.html - -.. _STM32F469 reference manual: - https://www.st.com/resource/en/reference_manual/dm00127514.pdf diff --git a/boards/arm/stm32f4_disco/Kconfig.board b/boards/arm/stm32f4_disco/Kconfig.board deleted file mode 100644 index e3788007766219..00000000000000 --- a/boards/arm/stm32f4_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F4_DISCO - bool "STM32F4DISCOVERY Development Board" - depends on SOC_STM32F407XG diff --git a/boards/arm/stm32f4_disco/Kconfig.defconfig b/boards/arm/stm32f4_disco/Kconfig.defconfig deleted file mode 100644 index 5d8c5341bbb793..00000000000000 --- a/boards/arm/stm32f4_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32F4DISCOVERY board configuration - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F4_DISCO - -config BOARD - default "stm32f4_disco" - -endif # BOARD_STM32F4_DISCO diff --git a/boards/arm/stm32f4_disco/doc/index.rst b/boards/arm/stm32f4_disco/doc/index.rst deleted file mode 100644 index 15dadab7fbf094..00000000000000 --- a/boards/arm/stm32f4_disco/doc/index.rst +++ /dev/null @@ -1,214 +0,0 @@ -.. _stm32f4_disco_board: - -ST STM32F4 Discovery -#################### - -Overview -******** - -The STM32F4DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F407VG MCU -with a wide range of connectivity support and configurations Here are -some highlights of the STM32F4DISCOVERY board: - - -- STM32 microcontroller in LQFP100 package -- Extension header for all LQFP100 I/Os for quick connection to prototyping board and easy probing -- On-board ST-LINK/V2 debugger/programmer with SWD connector -- Flexible board power supply: - - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- Eight LEDs: - - - USB communication (LD1) - - 3.3 V power on (LD2) - - Four user LEDs: orange (LD3), green (LD4), red (LD5), and blue (LD6) - - 2 USB OTG LEDs for VBUS (LD7) and over-current (LD8) - -- Two push-buttons: USER and RESET -- USB OTG FS with micro-AB connector -- LIS302DL or LIS3DSH ST MEMS 3-axis accelerometer -- MP45DT02 ST-MEMS audio sensor omni-directional digital microphone -- CS43L22 audio DAC with integrated class D speaker driver - -.. image:: img/stm32f4_disco.jpg - :align: center - :alt: STM32F4DISCOVERY - -More information about the board can be found at the `STM32F4DISCOVERY website`_. - -Hardware -******** - -STM32F4DISCOVERY Discovery kit provides the following hardware components: - -- STM32F407VGT6 in LQFP100 package -- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU -- 168 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 1 MB Flash -- 192+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (6) -- I2C (3) -- SPI (3) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F407VG can be found here: - - `STM32F407VG on www.st.com`_ - - `STM32F407 reference manual`_ - -Supported Features -================== - -The Zephyr stm32f4_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ - -.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. - Zephyr default configuration uses CAN_2 exclusively, as simultaneous use - of CAN_1 and CAN_2 is not yet supported. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32f4_disco/stm32f4_disco_defconfig`` - - -Pin Mapping -=========== - -STM32F4DISCOVERY Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32F4DISCOVERY board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PB6 -- UART_1_RX : PB7 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- USER_PB : PA0 -- LD3 : PD13 -- LD4 : PD12 -- LD5 : PD14 -- LD6 : PD15 -- USB DM : PA11 -- USB DP : PA12 -- CAN1_RX : PB8 -- CAN1_TX : PB9 -- CAN2_RX : PB5 -- CAN2_TX : PB13 - -System Clock -============ - -STM32F4DISCOVERY System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at 168MHz, -driven by 8MHz high speed external clock. - -Serial Port -=========== - -STM32F4DISCOVERY Discovery kit has up to 6 UARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. -Please note that ST-Link Virtual Com Port is not wired to chip serial port. In order to -enable console output you should use a serial cable and connect it to UART2 pins (PA2/PA3). - - -Programming and Debugging -************************* - -Applications for the ``stm32f4_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F4DISCOVERY Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32F4DISCOVERY -------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Build and flash the application: - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32f4_disco - :goals: build flash - -You should see user led "LD4" blinking. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f4_disco - :maybe-skip-config: - :goals: debug - -.. _STM32F4DISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32f4discovery.html - -.. _STM32F4DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00039084.pdf - -.. _STM32F407VG on www.st.com: - https://www.st.com/en/microcontrollers/stm32f407vg.html - -.. _STM32F407 reference manual: - https://www.st.com/resource/en/reference_manual/dm00031020.pdf - -.. _SK Pang CAN breakout board: - https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-3-3v-logic diff --git a/boards/arm/stm32f723e_disco/Kconfig.board b/boards/arm/stm32f723e_disco/Kconfig.board deleted file mode 100644 index 87101062904af7..00000000000000 --- a/boards/arm/stm32f723e_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F723E Discovery board configuration - -# Copyright (c) 2018 Aurelien Jarno -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F723E_DISCO - bool "STM32F723E Discovery Development Board" - depends on SOC_STM32F723XX diff --git a/boards/arm/stm32f723e_disco/Kconfig.defconfig b/boards/arm/stm32f723e_disco/Kconfig.defconfig deleted file mode 100644 index f8406381d3f4a1..00000000000000 --- a/boards/arm/stm32f723e_disco/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32F723E DISCOVERY board configuration - -# Copyright (c) 2018 Aurelien Jarno -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F723E_DISCO - -config BOARD - default "stm32f723e_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - - -endif # BOARD_STM32F723E_DISCO diff --git a/boards/arm/stm32f723e_disco/doc/index.rst b/boards/arm/stm32f723e_disco/doc/index.rst deleted file mode 100644 index c6e34cbbe91e3d..00000000000000 --- a/boards/arm/stm32f723e_disco/doc/index.rst +++ /dev/null @@ -1,192 +0,0 @@ -.. _stm32f723e_disco_board: - -ST STM32F723E Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F723IEK6 microcontroller featuring 512 Kbytes of Flash memory and 256+16+4 Kbytes of RAM, in BGA176 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- TFT LCD 240x240 pixels with touch panel -- SAI audio codec -- Audio line in and line out jack -- Stereo speaker outputs -- Four ST MEMS microphones -- Two pushbuttons (user and reset) -- 512-Mbit Quad-SPI Flash memory -- 8-Mbit external PSRAM -- USB OTG HS with Micro-AB connectors -- USB OTG FS with Micro-AB connectors - -.. image:: img/stm32f723e_disco.jpg - :align: center - :alt: STM32F723E-DISCO - -More information about the board can be found at the `32F723E-DISCO website`_. - -Hardware -******** - -The STM32F723E Discovery kit provides the following hardware components: - -- STM32F723IEK6 in BGA176 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 1 MB Flash -- 256+16+4 KB SRAM including 64KB of tightly coupled memory -- GPIO with external interrupt capability -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer (2) -- General Purpose Timers (13) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (5) -- 2xSAI (serial audio interface) -- SDIO (2) -- CAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and on-chip hi-speed PHY -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F723IEK6 can be found here: - -- `STM32F723IEK6 on www.st.com`_ -- `STM32F72xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f723e_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig`` - -Pin Mapping -=========== - -STM32F723E Discovery kit has 7 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F723E-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- -- UART_2 TX/RX : PA2/PA3 (Arduino Serial) -- UART_6 TX/RX : PC6/PC7 (ST-Link Virtual Port Com) -- I2C1 SCL/SDA : PB8/PB9 -- I2C2 SCL/SDA : PH4/PH5 (Arduino I2C) -- I2C3 SCL/SDA : PA8/PH8 -- SPI1 SCK/MISO/MOSI : PA5/PB4/PB5 (Arduino SPI) -- LD1 : PA5 -- LD5 : PA7 -- LD6 : PB1 -- OTG_FS_DM : PA11 -- OTG_FS_DP : PA12 - -System Clock -============ - -The STM32F723E System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F723E Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART6 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f723e_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F723E Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F723E-DISCO -------------------------------------------- - -First, connect the STM32F723E Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f723e_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f723e_disco - :goals: debug - - -.. _32F723E-DISCO website: - https://www.st.com/en/evaluation-tools/32f723ediscovery.html - -.. _32F723E-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00342318.pdf - -.. _STM32F723IEK6 on www.st.com: - https://www.st.com/en/microcontrollers/stm32f723ie.html - -.. _STM32F72xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00305990.pdf diff --git a/boards/arm/stm32f746g_disco/Kconfig.board b/boards/arm/stm32f746g_disco/Kconfig.board deleted file mode 100644 index b1916605531a0a..00000000000000 --- a/boards/arm/stm32f746g_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F746G Discovery board configuration - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F746G_DISCO - bool "STM32F746G Discovery Development Board" - depends on SOC_STM32F746XX diff --git a/boards/arm/stm32f746g_disco/Kconfig.defconfig b/boards/arm/stm32f746g_disco/Kconfig.defconfig deleted file mode 100644 index cd653cd18c99aa..00000000000000 --- a/boards/arm/stm32f746g_disco/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# STM32F746G DISCOVERY board configuration - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F746G_DISCO - -config BOARD - default "stm32f746g_disco" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config INPUT - default y if LVGL - -if DISPLAY - -# MEMC needs to be enabled in order to store -# display buffer to external SDRAM connected to FMC -config MEMC - default y - -endif # DISPLAY - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32F746G_DISCO diff --git a/boards/arm/stm32f746g_disco/doc/index.rst b/boards/arm/stm32f746g_disco/doc/index.rst deleted file mode 100644 index 714a627ec4a07c..00000000000000 --- a/boards/arm/stm32f746g_disco/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _stm32f746g_disco_board: - -ST STM32F746G Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F746NGH6 microcontroller featuring 1 Mbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Five power supply options: - - - ST LINK/V2-1 - - USB FS connector - - USB HS connector - - VIN from Arduino connector - - External 5 V from connector - -- Two pushbuttons (user and reset) -- USB functions: virtual COM port, mass storage, debug port -- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen -- SAI audio codec -- Audio line in and line out jack -- Stereo speaker outputs -- Two ST MEMS microphones -- SPDIF RCA input connector -- 128-Mbit Quad-SPI Flash memory -- 128-Mbit SDRAM (64 Mbits accessible) -- Connector for microSD card -- USB OTG HS with Micro-AB connectors -- USB OTG FS with Micro-AB connectors -- Ethernet connector compliant with IEEE-802.3-2002 - -.. image:: img/stm32f746g_disco.jpg - :align: center - :alt: STM32F746G-DISCO - -More information about the board can be found at the `32F746G-DISCO website`_. - -Hardware -******** - -The STM32F746G Discovery kit provides the following hardware components: - -- STM32F746NGH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- VDD from 1.8 V to 3.6 V -- 2 MB Flash -- 384+4 KB SRAM including 64-Kbyte of core coupled memory -- GPIO with external interrupt capability -- LCD parallel interface, 8080/6800 modes -- LCD TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (3) -- SPI (6) -- 1xSAI (serial audio interface) -- SDIO -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F746NGH6 can be found here: - -- `STM32F746NGH6 on www.st.com`_ -- `STM32F74xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f746g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| LTDC | on-chip | display | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig`` - -Pin Mapping -=========== - -STM32F746G Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F746G-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The STM32F746G Discovery kit features an Arduino Uno V3 connector. Board is -configured as follows - -- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PC6/PC7 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 -- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) -- PWM_3_CH1 : PB4 -- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 -- USER_PB : PI11 -- LD1 : PI1 -- USB DM : PA11 -- USB DP : PA12 -- FMC SDRAM : - - - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 - - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 - - A14/A15 : PG4/PG5 - - SDNRAS/SDNCAS : PF11/PG15 - - NBL0/NBL1 : PE0/PE1 - - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 - -- LTDC : - - - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 - - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 - - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 - - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 - - -System Clock -============ - -The STM32F746G System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F746G Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f746g_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F746G -------------------------------------------- - -First, connect the STM32F746G Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f746g_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f746g_disco - :goals: debug - - -.. _32F746G-DISCO website: - https://www.st.com/en/evaluation-tools/32f746gdiscovery.html - -.. _32F746G-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00190424.pdf - -.. _STM32F746NGH6 on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html - -.. _STM32F74xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f7508_dk/Kconfig.board b/boards/arm/stm32f7508_dk/Kconfig.board deleted file mode 100644 index 5f6e707d522d78..00000000000000 --- a/boards/arm/stm32f7508_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F7508-DK Discovery board configuration - -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F7508_DK - bool "STM32F7508-DK Discovery Kit" - depends on SOC_STM32F750XX diff --git a/boards/arm/stm32f7508_dk/Kconfig.defconfig b/boards/arm/stm32f7508_dk/Kconfig.defconfig deleted file mode 100644 index 7995c1fbae7d59..00000000000000 --- a/boards/arm/stm32f7508_dk/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# STM32F7508-DK Discovery board configuration - -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F7508_DK - -config BOARD - default "stm32f7508_dk" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -if DISPLAY - -# MEMC needs to be enabled in order to store -# display buffer to external SDRAM connected to FMC -config MEMC - default y - -endif # DISPLAY - -config INPUT - default y if LVGL - -if INPUT - -config INPUT_FT5336_INTERRUPT - default y - -endif # INPUT - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32F7508_DK diff --git a/boards/arm/stm32f7508_dk/doc/index.rst b/boards/arm/stm32f7508_dk/doc/index.rst deleted file mode 100644 index 699285fcd90748..00000000000000 --- a/boards/arm/stm32f7508_dk/doc/index.rst +++ /dev/null @@ -1,238 +0,0 @@ -.. _stm32f7508_dk_board: - -ST STM32F7508-DK Discovery Kit -############################## - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F750N8H6 microcontroller featuring 64 Kbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Five power supply options: - - - ST LINK/V2-1 - - USB FS connector - - USB HS connector - - VIN from Arduino connector - - External 5 V from connector - -- Two pushbuttons (user and reset) -- USB functions: virtual COM port, mass storage, debug port -- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen -- SAI audio codec -- Audio line in and line out jack -- Two ST MEMS microphones -- SPDIF RCA input connector -- 128-Mbit Quad-SPI Flash memory -- 128-Mbit SDRAM (64 Mbits accessible) -- Connector for microSD card -- USB OTG HS with Micro-AB connectors -- USB OTG FS with Micro-AB connectors -- Ethernet connector compliant with IEEE-802.3-2002 - -.. image:: img/stm32f7508_dk.jpg - :align: center - :alt: STM32F7508-DK - -More information about the board can be found at the `32F7508-DK website`_. - -Hardware -******** - -The STM32F7508-DK Discovery kit provides the following hardware components: - -- STM32F750N8H6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- 64 KB Flash -- 320+16+4 KB SRAM -- GPIO with external interrupt capability -- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen -- 3x12-bit ADC -- 2x12-bit D/A converters -- RTC -- Advanced-control Timer -- General Purpose Timers (17) -- Watchdog Timers (2) -- USART/UART (8) -- I2C (4) -- SPI (6) -- 2xSAI (serial audio interface) -- 2xCAN -- USB 2.0 OTG FS with on-chip PHY -- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA -- 8- to 14-bit parallel camera -- CRC calculation unit -- True random number generator -- DMA Controller - -More information about STM32F750x8 can be found here: - -- `STM32F750x8 on www.st.com`_ -- `STM32F74xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f7508_dk board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| LTDC | on-chip | display | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig`` - -Pin Mapping -=========== - -STM32F7508-DK Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F7508-DK board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -The STM32F7508 Discovery kit features an Arduino Uno V3 connector. Board is -configured as follows - -- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PC6/PC7 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 -- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) -- PWM_3_CH1 : PB4 -- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 -- USER_PB : PI11 -- LD1 : PI1 -- USB DM : PA11 -- USB DP : PA12 -- FMC SDRAM : - - - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 - - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 - - A14/A15 : PG4/PG5 - - SDNRAS/SDNCAS : PF11/PG15 - - NBL0/NBL1 : PE0/PE1 - - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 - -- LTDC : - - - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 - - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 - - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 - - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 - - -System Clock -============ - -The STM32F7508 System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F7508-DK Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f7508_dk`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F7508-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F7508-DK -------------------------------------------- - -First, connect the STM32F746G Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f7508_dk - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f7508_dk - :goals: debug - - -.. _32F7508-DK website: - https://www.st.com/en/evaluation-tools/stm32f7508-dk.html - -.. _32F7508-DK board User Manual: - https://www.st.com/resource/en/user_manual/dm00537062-discovery-kit-for-stm32f7-series-with-stm32f750n8-mcu-stmicroelectronics.pdf - -.. _STM32F750x8 on www.st.com: - https://www.st.com/resource/en/datasheet/stm32f750z8.pdf - -.. _STM32F74xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f769i_disco/Kconfig.board b/boards/arm/stm32f769i_disco/Kconfig.board deleted file mode 100644 index 80c1b3ef5cbea8..00000000000000 --- a/boards/arm/stm32f769i_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32F769I Discovery board configuration - -# Copyright (c) 2018 Yong Jin -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32F769I_DISCO - bool "STM32F769I Discovery Development Board" - depends on SOC_STM32F769XX diff --git a/boards/arm/stm32f769i_disco/Kconfig.defconfig b/boards/arm/stm32f769i_disco/Kconfig.defconfig deleted file mode 100644 index 8689d03c656a35..00000000000000 --- a/boards/arm/stm32f769i_disco/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# STM32F769I DISCOVERY board configuration - -# Copyright (c) 2018 Yong Jin -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32F769I_DISCO - -config BOARD - default "stm32f769i_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config INPUT - default y if LVGL - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_STM32F769I_DISCO diff --git a/boards/arm/stm32f769i_disco/doc/index.rst b/boards/arm/stm32f769i_disco/doc/index.rst deleted file mode 100644 index 203beb6f48a923..00000000000000 --- a/boards/arm/stm32f769i_disco/doc/index.rst +++ /dev/null @@ -1,225 +0,0 @@ -.. _stm32f769i_disco_board: - -ST STM32F769I Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, security, video, -and high-speed connectivity features. Important board features include: - -- STM32F769NIH6 microcontroller featuring 2 Mbytes of Flash memory and 512 Kbytes of RAM, in BGA216 package -- On-board ST-LINK/V2-1 supporting USB reenumeration capability -- USB ST-LINK functions: virtual COM port, mass storage, debug port -- Five power supply options: - - - ST LINK/V2-1 - - USB HS connector - - 5 V from RJ45 (Power Over Ethernet) - - 5 V from Arduino™ or external connector - - USB charger - -- 4-inch capacitive touch LCD display with MIPI-DSI connector -- SAI audio codec -- Two audio line jacks, one for input and one for output -- Stereo speaker outputs -- Four ST MEMS microphones on DFSDM inputs -- Two SPDIF RCA input and output connectors -- Two push-buttons (user and reset) -- 512-Mbit Quad-SPI Flash memory -- 128-Mbit SDRAM -- Connector for microSD card -- Wi-Fi or Ext-EEP daughterboard connector -- USB OTG HS with Micro-AB connector -- Ethernet connector compliant with IEEE-802.3-2002 -- Power Over Ethernet based on IEEE 802.3af (Powered Device, 48 V to 5 V, 3 W) -- Power supply output for external applications: 3.3 V or 5 V -- Arduino Uno V3 connectors -- Comprehensive free software including a variety of examples, part of the STM32Cube package -- Supported by a wide choice of integrated development environments - -.. image:: img/stm32f769i_disco.jpg - :align: center - :alt: STM32F769I-DISCO - -More information about the board can be found at the `32F769I-DISCO website`_. - -Hardware -******** - -The STM32F769I Discovery kit provides the following hardware components: - -- STM32F769NIH6 in BGA216 package -- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU -- 216 MHz max CPU frequency -- VDD from 1.7 V to 3.6 V -- 2 MB Flash -- 512 + 16 + 4 KB SRAM -- Flexible external memory controller with up to 32-bit data bus -- Dual mode Quad-SPI -- Chrom-ART Accelerator(DMA2D), graphical hardware accelerator enabling enhanced graphical user interface -- Hardware JPEG codec -- LCD-TFT controller supporting up to XGA resolution -- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution -- 3x12-bit ADC with 24 channels -- 2x12-bit D/A converters -- DMA Controller -- General Purpose Timers (15) -- Watchdog Timers (2) -- I2C (4) -- USART/UART (8) -- SPI (6) -- SAI (2) -- CAN (3) -- SDMMC (2) -- SPDIFRX interface -- HDMI-CEC -- MDIO slave interface -- USB 2.0 full-speed device/host/OTG controller with on-chip PHY -- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI -- 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII -- 8- to 14-bit camera interface up to 54 Mbyte/s -- True random number generator -- CRC calculation unit -- RTC: sub-second accuracy, hardware calendar -- 96-bit unique ID - -More information about STM32F769NIH6 can be found here: - -- `STM32F769NIH6 on www.st.com`_ -- `STM32F76xxx reference manual`_ - -Supported Features -================== - -The Zephyr stm32f769i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | Ethernet | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | flash | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| TOUCH | off-chip | ft5336(FT6202) | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig`` - -Pin Mapping -=========== - -STM32F769I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `32F769I-DISCO board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- UART_6 TX/RX : PC6/PC7 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) -- I2C4 SCL/SDA : PD12/PB7 (Touchscreen FT6202, PI13 Interrupt Pin) -- SPI2 SCK/MISO/MOSI : PA12/PB14/PB15 (Arduino SPI) -- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 -- LD1 : PJ13 -- LD2 : PJ5 -- LD3 : PA12 -- LD4 : PD4 - -System Clock -============ - -The STM32F769I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by the PLL -clock at 216MHz, driven by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32F769I Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 -which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication -settings are 115200 8N1. - -Programming and Debugging -************************* - -Applications for the ``stm32f769i_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32F769I Discovery kit includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application to STM32F769I -------------------------------------------- - -First, connect the STM32F769I Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f769i_disco - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32f769i_disco - :goals: debug - - -.. _32F769I-DISCO website: - https://www.st.com/en/evaluation-tools/32f769idiscovery.html - -.. _32F769I-DISCO board User Manual: - https://www.st.com/resource/en/user_manual/dm00276557.pdf - -.. _STM32F769NIH6 on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html - -.. _STM32F76xxx reference manual: - https://www.st.com/resource/en/reference_manual/dm00224583.pdf diff --git a/boards/arm/stm32g0316_disco/Kconfig.board b/boards/arm/stm32g0316_disco/Kconfig.board deleted file mode 100644 index 3f00f126fe3d0b..00000000000000 --- a/boards/arm/stm32g0316_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G0316 Discovery board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32G0316_DISCO - bool "STM32G0316 Discovery Development Board" - depends on SOC_STM32G031XX diff --git a/boards/arm/stm32g0316_disco/Kconfig.defconfig b/boards/arm/stm32g0316_disco/Kconfig.defconfig deleted file mode 100644 index 3016470eb561d1..00000000000000 --- a/boards/arm/stm32g0316_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32G0316 Discovery board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32G0316_DISCO - -config BOARD - default "stm32g0316_disco" - -endif # BOARD_STM32G0316_DISCO diff --git a/boards/arm/stm32g0316_disco/doc/index.rst b/boards/arm/stm32g0316_disco/doc/index.rst deleted file mode 100644 index ed68a7b5dd4361..00000000000000 --- a/boards/arm/stm32g0316_disco/doc/index.rst +++ /dev/null @@ -1,134 +0,0 @@ -.. _stm32g0316_disco_board: - -ST STM32G0316 Discovery -####################### - -Overview -******** - -The STM32G0316-DISCO Discovery kit helps to discover features of STM32G0 in SO8 package. -This discovery kit offers an SO8 to DIL8 module designed with the STM32G031J6 microcontroller -and allows the user to develop applications. It includes an on-board ST-LINK/V2-1 to debug -and program the embedded STM32 microcontroller. - -.. image:: img/stm32g0316_disco.jpg - :align: center - :alt: STM32G0316-DISCO - -Hardware -******** - -- STM32G031J6 Arm |reg| Cortex |reg|-M0+ core-based microcontroller, - featuring 32 Kbytes of Flash memory and 8 Kbytes of SRAM, in an SO8 package -- 1 user LED -- 1 reset/user push-button -- Individual and breakable STM32 SO8 to DIL8 module -- ST-LINK Micro-B USB connector -- DIL8 socket to ease programming of the STM32 MCU -- On-board ST-LINK/V2-1 debugger/programmer - -For more information about the STM32G03x SoC and the STM32G0316-DISCO board, see these ST reference documents: - -- `STM32G031J6 website`_ -- `STM32G031 datasheet`_ -- `STM32G0x1 reference manual`_ -- `STM32G0316-DISCO website`_ - -Supported Features -================== - -The Zephyr stm32g0316_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not currently supported by the port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig`` - -Connections and IOs -=================== - -Due to the small number of I/O pins on the SO8 package, multiple die I/Os are bonded -to the same package pins to maximize the number of peripherals which can be used. -Care must be taken not to set two I/Os which are connected together to conflicting -states (e.g. both as outputs, one low, the other high). - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1 TX/RX : PA9/PB7 (pins 5/1) -- USER_PB : PA0 (pin 4) -- LD2 : PA12 (pin 6) - -Programming and Debugging -************************* - -Applications for the ``stm32g0316_disco`` board configuration can be built the -usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). - -Flashing -======== - -The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool -interface. This interface is not yet supported by the openocd version included in -the Zephyr SDK. Instead, support can be enabled on pyocd by adding "pack" support with -the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32g031j6 - -Flashing an application to the STM32G0316-DISCO ------------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32g0316_disco - :goals: build flash - -You should see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32g0316_disco - :maybe-skip-config: - :goals: debug - -.. _STM32G031J6 website: - https://www.st.com/en/microcontrollers-microprocessors/stm32g031j6.html - -.. _STM32G031 datasheet: - https://www.st.com/resource/en/datasheet/stm32g031j6.pdf - -.. _STM32G0x1 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32G0316-DISCO website: - https://www.st.com/en/evaluation-tools/stm32g0316-disco.html diff --git a/boards/arm/stm32g071b_disco/Kconfig.board b/boards/arm/stm32g071b_disco/Kconfig.board deleted file mode 100644 index 897dcce606db1d..00000000000000 --- a/boards/arm/stm32g071b_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G071B Discovery board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32G071B_DISCO - bool "STM32G071B Discovery Board" - depends on SOC_STM32G071XX diff --git a/boards/arm/stm32g071b_disco/Kconfig.defconfig b/boards/arm/stm32g071b_disco/Kconfig.defconfig deleted file mode 100644 index 195b8ecdf4ffc1..00000000000000 --- a/boards/arm/stm32g071b_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32G071B Discovery board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32G071B_DISCO - -config BOARD - default "stm32g071b_disco" - -endif # BOARD_STM32G071B_DISCO diff --git a/boards/arm/stm32g071b_disco/doc/index.rst b/boards/arm/stm32g071b_disco/doc/index.rst deleted file mode 100644 index 2c9cbea31767ee..00000000000000 --- a/boards/arm/stm32g071b_disco/doc/index.rst +++ /dev/null @@ -1,169 +0,0 @@ -.. _stm32g071b_disco_board: - -ST STM32G071B Discovery -####################### - -Overview -******** -The STM32G071B-DISCO Discovery board is a demonstration and development platform -for the STMicroelectronics Arm® Cortex® -M0+ core-based STM32G071RB USB Type-C™ -and Power Delivery microcontroller. The STM32G071B-DISCO Discovery board is -presented with all necessary interfaces for easy connection and -interoperability with other USB Type-C™ devices. The STM32G071B-DISCO Discovery -board is intended for discovery and display of USB Type-C™ port characteristics -such as data role, power role, VBUS and IBUS monitoring. It offers an advanced -user mode when associated with the STM32CubeMonUCPD software GUI and can be used -as a USB Type-C™ and Power Delivery analyzer. - -- STM32G071RBT6 microcontroller featuring 128 Kbytes of Flash memory and - 32 Kbytes of RAM in LQFP64 package -- Plastic case -- 1” 128 x 64 pixels OLED LCD module with SPI interface -- USB Type-C™ interface plug cable and receptacle connector accessible by door - with reed sensor detection -- 3 bidirectional current and power monitors with I2C interface to measure VBUS, - CC1 and CC2 protected and isolated lines -- On-board DC/DC converter to sustain power supply with VBUS varying from 3 V to - 20 V (+/- 5 %) -- 4 user status LEDs about USB Type-C™ configuration -- 3 LEDs for power and ST-LINK communication -- 4-way joystick with selection button -- 1 reset push-button -- Board external connectors: - - USB Type-C™ plug cable - - USB Type-C™ receptacle connector - - 8-pin user extension connector including ADC, SPI, USART and - I2C communication signals - - USB with Micro-AB (ST-LINK) -- Board internal connectors: - - 2 x 8-pin GPIOs free pins from microcontroller - (accessible internally when case is removed) - - USB Type-C™ test points for main signals -- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS -- On-board ST-LINK/V2-1 debugger/programmer with USB enumeration capability: - mass storage, Virtual COM port and debug port - -.. image:: img/stm32g071b_disco.jpg - :align: center - :alt: STM32G071B-DISCO - -More information about the board can be found at the `STM32G071B-DISCO website`_. - - -More information about STM32G071RB can be found here: -- `G071RB on www.st.com`_ -- `STM32G071 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32g071b_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UCPD | on-chip | ucpd | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) -- UCPD1 : PA8/PB15 -- BUTTON (JOY_SEL) : PC0 -- BUTTON (JOY_LEFT) : PC1 -- BUTTON (JOY_DOWN) : PC2 -- BUTTON (JOY_RIGHT) : PC3 -- BUTTON (JOY_UP) : PC4 -- LED (TO_REC) : PD9 -- LED (TO_PLUG) : PD8 -- LED (SINK_SPY) : PD5 -- LED (SOURCE) : PC12 -- ENCC1 : PB10 (Enable CC1) -- ENCC2 : PB11 (Enable CC2) -- RDCC1 : PB12 (Enable Door Sense on CC1) - - -For more details please refer to `STM32G0 Discovery board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32g071b_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The STM32G071B Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. - -.. code-block:: console - - $ west flash - -Flashing an application to the STM32G071B_DISCO ------------------------------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32g071b_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32g071b_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32G071B-DISCO website: - https://www.st.com/en/evaluation-tools/stm32g071b-disco.html - -.. _STM32G071 reference manual: - https://www.st.com/resource/en/reference_manual/dm00371828.pdf - -.. _STM32G0 Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00496511.pdf - -.. _G071RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/stm32g081b_eval/Kconfig.board b/boards/arm/stm32g081b_eval/Kconfig.board deleted file mode 100644 index 2f2299670f5209..00000000000000 --- a/boards/arm/stm32g081b_eval/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32G081B Evaluation board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32G081B_EVAL - bool "STM32G081B Evaluation Board" - depends on SOC_STM32G081XX diff --git a/boards/arm/stm32g081b_eval/Kconfig.defconfig b/boards/arm/stm32g081b_eval/Kconfig.defconfig deleted file mode 100644 index 548b4d75cc13ab..00000000000000 --- a/boards/arm/stm32g081b_eval/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32G081B evaluation board configuration - -# Copyright 2021 The Chromium OS Authors -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32G081B_EVAL - -config BOARD - default "stm32g081b_eval" - -endif # BOARD_STM32G081B_EVAL diff --git a/boards/arm/stm32g081b_eval/doc/index.rst b/boards/arm/stm32g081b_eval/doc/index.rst deleted file mode 100644 index 970ec32dd0ab5b..00000000000000 --- a/boards/arm/stm32g081b_eval/doc/index.rst +++ /dev/null @@ -1,207 +0,0 @@ -.. _stm32g081b_eval_board: - -ST STM32G081B Evaluation -######################## - -Overview -******** -The STM32G081B-EVAL Evaluation board is a high-end development platform, for -Arm Cortex-M0+ core-based STM32G081RBT6 microcontroller, with USB Type-C and -power delivery controller interfaces (UCPD), compliant with USB type-C r1.2 -and USB PD specification r3.0, two I2Cs, two SPIs, five USARTs, one LP UART, -one 12-bit ADC, two 12-bit DACs, two GP comparators, two LP timers, internal -32 KB SRAM and 128 KB Flash, CEC, SWD debugging support. The full range of -hardware features on the STM32G081B-EVAL Evaluation board includes a mother -board, a legacy peripheral daughterboard and a USB-C and Power Delivery -daughterboard, which help to evaluate all peripherals (USB Type-C connector -with USB PD, motor control connector, RS232, RS485, Audio DAC, microphone ADC, -TFT LCD, IrDA, IR LED, IR receiver, LDR, MicroSD card, CEC on two HDMI -connectors, smart card slot, RF E2PROM & Temperature sensor…), and to develop -applications. - -The board integrates an ST-LINK/V2-1 as an embedded in-circuit debugger and -programmer for the STM32 MCU. The daughterboard and extension connectors -provide an easy way to connect a daughterboard or wrapping board for the -user's specific applications. - -The USB-C and Power Delivery daughterboard -features two independent USB-C ports controlled by an STM32G0. USB-C port 1 -is dual role power (DRP) and can provide up-to 45 W. USB-C Port 2 is sink -only. Both support USB PD protocol and alternate mode functionality. - -Application firmware examples are provided to evaluate the USB-C technology -through various use cases. - - - -- Mother board - - STM32G081RBT6 microcontroller with 128 Kbytes of Flash memory and - 32 Kbytes of RAM in LQFP64 package - - MCU voltage choice fixed 3.3 V or adjustable from 1.65 V to 3.6 V - - I2C compatible serial interface - - RTC with backup battery - - 8-Gbyte or more SPI interface microSD card - - Potentiometer - - 4 color user LEDs and one LED as MCU low-power alarm - - Reset, Tamper and User buttons - - 4-direction control and selection joystick - - Board connectors: - - 5 V power jack - - RS-232 and RS485 communications - - Stereo audio jack including analog microphone input - - microSD card - - Extension I2C connector - - Motor-control connector - - Board extension connectors: - - Daughterboard connectors for legacy peripheral daughter board or - USB-C daughterboard - - Extension connectors for daughterboard or wire-wrap board - - Flexible power-supply options: - - 5 V power jack - - ST-LINK/V2-1 USB connector - - Daughterboard - - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration - capability: mass storage, virtual COM port and debug port - - Legacy peripheral daughterboard - - IrDA transceiver - - IR LED and IR receiver - - Light dependent resistor (LDR) - - Temperature Sensor - - Board connectors: - - Two HDMI connectors with DDC and CEC - - Smart card slot - - USB-C and Power Delivery daughterboard - - Mux for USB3.1 Gen1 / DisplayPort input and Type-C port1 output - - Mux for Type-C port2 input and DisplayPort output / USB2.0 - - VCONN on Type-C port1 - - USB PD on Type-C port1 - - Board connectors: - - Type-C port1 DRP (dual-role port) - - Type-C port2 Sink - - DisplayPort input - - DisplayPort output - - USB 3.1 Gen1 Type-B receptacle - - USB2.0 Type-A receptacle - - 19 V power jack for USB PD - -.. image:: img/stm32g081b_eval.jpg - :align: center - :alt: STM32G081B-EVAL - -More information about the board can be found at the `STM32G081B-EVAL website`_. - - -More information about STM32G081RB can be found here: -- `G081RB on www.st.com`_ -- `STM32G081 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32g081b_eval board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| UCPD | on-chip + ucpd | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) -- UCPD2 : PD0/PD2 -- BUTTON (JOY_SEL) : PA0 -- BUTTON (JOY_LEFT) : PC8 -- BUTTON (JOY_DOWN) : PC3 -- BUTTON (JOY_RIGHT) : PC7 -- BUTTON (JOY_UP) : PC2 -- VBUS DISCHARGE : PB14 -- LED1 : PD5 -- LED2 : PD6 -- LED3 : PD8 -- LED4 : PD9 - -For more details please refer to `STM32G0 Evaluation board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32g081b_eval`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -The STM32G081B Evaluation board includes an ST-LINK/V2-1 embedded debug tool interface. - -.. code-block:: console - - $ west flash - -Flashing an application to the STM32G081B_EVAL ----------------------------------------------- - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32g081b_eval - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32g081b_eval - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32G081B-EVAL website: - https://www.st.com/en/evaluation-tools/stm32g081b-eval.html - -.. _STM32G081 reference manual: - https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32G0 Evaluation board User Manual: - https://www.st.com/resource/en/user_manual/um2403-evaluation-board-with-stm32g081rb-mcu-stmicroelectronics.pdf - -.. _G081RB on www.st.com: - https://www.st.com/en/microcontrollers/stm32g081rb.html diff --git a/boards/arm/stm32h573i_dk/Kconfig.board b/boards/arm/stm32h573i_dk/Kconfig.board deleted file mode 100644 index adb46f39300536..00000000000000 --- a/boards/arm/stm32h573i_dk/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# STM32H573I-DK Discovery kit board configuration -# -# Copyright (c) 2023 STMicroelectronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_STM32H573I_DK - bool "STM32H573I-DK Discovery Development Board" - depends on SOC_STM32H573XX diff --git a/boards/arm/stm32h573i_dk/Kconfig.defconfig b/boards/arm/stm32h573i_dk/Kconfig.defconfig deleted file mode 100644 index d9bf4c722894e2..00000000000000 --- a/boards/arm/stm32h573i_dk/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# STM32H573I DISCOVERY KIT board configuration -# -# Copyright (c) 2023 STMicroelectronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_STM32H573I_DK - -config BOARD - default "stm32h573i_dk" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_STM32H573I_DK diff --git a/boards/arm/stm32h573i_dk/doc/index.rst b/boards/arm/stm32h573i_dk/doc/index.rst deleted file mode 100644 index db83ec2f7a2d6d..00000000000000 --- a/boards/arm/stm32h573i_dk/doc/index.rst +++ /dev/null @@ -1,326 +0,0 @@ -.. _stm32h573i_dk_board: - -ST STM32H573I-DK Discovery -########################## - -Overview -******** - -The STM32H573I-DK Discovery kit is designed as a complete demonstration and -development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based -STM32H573IIK3Q microcontroller with TrustZone |reg|. Here are some highlights of -the STM32H573I-DK Discovery board: - - -- STM32H573IIK3Q microcontroller featuring 2 Mbytes of Flash memory and 640 Kbytes of SRAM in 176-pin BGA package -- 1.54-inch 240x240 pixels TFT-LCD with LED backlight and touch panel -- USB Type-C |trade| Host and device with USB power-delivery controller -- SAI Audio DAC stereo with one audio jacks for input/output, -- ST MEMS digital microphone with PDM interface -- Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX25LM51245GXDI00 from MACRONIX) -- 10/100-Mbit Ethernet, -- microSD |trade| -- A Wi‑Fi® add-on board -- Board connectors - - - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors - - Pmod |trade| expansion connector - - Audio MEMS daughterboard expansion connector - - ARDUINO |reg| Uno V3 expansion connector - -- Flexible power-supply options - - - ST-LINK - - USB VBUS - - external sources - -- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: - - - mass storage - - Virtual COM port - - debug port - -- 4 user LEDs -- User and reset push-buttons - -.. image:: img/stm32h573i_dk.jpg - :align: center - :alt: STM32H573I-DK Discovery - -More information about the board can be found at the `STM32H573I-DK Discovery website`_. - -Hardware -******** - -The STM32H573xx devices are an high-performance microcontrollers family (STM32H5 -Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. -They operate at a frequency of up to 250 MHz. - -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 375 DMPIS/MHz (Dhrystone 2.1) - -- Security - - - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension - - Up to 8 configurable SAU regions - - TrustZone |reg| aware and securable peripherals - - Flexible lifecycle scheme with secure debug authentication - - Preconfigured immutable root of trust (ST-iROT) - - SFI (secure firmware installation) - - Secure data storage with hardware unique key (HUK) - - Secure firmware upgrade support with TF-M - - 2x AES coprocessors including one with DPA resistance - - Public key accelerator, DPA resistant - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - True random number generator, NIST SP800-90B compliant - - 96-bit unique ID - - Active tampers - - True Random Number Generator (RNG) NIST SP800-90B compliant - -- Clock management: - - - 25 MHz crystal oscillator (HSE) - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 64 MHz (HSI) trimmable by software - - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) - - Internal 4 MHz oscillator (CSI), trimmable by software - - Internal 48 MHz (HSI48) with recovery system - - 3 PLLs for system clock, USB, audio, ADC - -- Power management - - - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry - - Embedded SMPS step-down converter - -- RTC with HW calendar, alarms and calibration -- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V -- Up to 16 timers and 2 watchdogs - - - 12x 16-bit - - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - - 6x 16-bit low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- Memories - - - Up to 2 MB Flash, 2 banks read-while-write - - 1 Kbyte OTP (one-time programmable) - - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC - - 4 Kbytes of backup SRAM available in the lowest power modes - - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories - - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats - - 2x SD/SDIO/MMC interfaces - -- Rich analog peripherals (independent supply) - - - 2x 12-bit ADC with up to 5 MSPS in 12-bit - - 2x 12-bit D/A converters - - 1x Digital temperature sensor - -- 34x communication interfaces - - - 1x USB Type-C / USB power-delivery controller - - 1x USB 2.0 full-speed host and device - - 4x I2C FM+ interfaces (SMBus/PMBus) - - 1x I3C interface - - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) - - 1x LP UART - - 6x SPIs including 3 muxed with full-duplex I2S - - 5x additional SPI from 5x USART when configured in Synchronous mode - - 2x SAI - - 2x FDCAN - - 1x SDMMC interface - - 2x 16 channel DMA controllers - - 1x 8- to 14- bit camera interface - - 1x HDMI-CEC - - 1x Ethernel MAC interface with DMA controller - - 1x 16-bit parallel slave synchronous-interface - -- CORDIC for trigonometric functions acceleration -- FMAC (filter mathematical accelerator) -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32H573 can be found here: - -- `STM32H573 on www.st.com`_ -- `STM32H573 reference manual`_ - -Supported Features -================== - -The Zephyr STM32H573I_DK board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | Real Time Clock | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi bus | -+-----------+------------+-------------------------------------+ -| OCTOSPI | on-chip | octospi | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can bus | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB full-speed host/device bus | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- Secure target: - - - :zephyr_file:`boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig` - - :zephyr_file:`boards/arm/stm32h573i_dk/stm32h573i_dk.dts` - -Zephyr board options -==================== - -The STM32H573 is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| stm32h573i_dk | For building Secure firmware | -+----------------------+-----------------------------------------------+ - -Connections and IOs -=================== - -STM32H573I-DK Discovery Board has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32H573I-DK Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX/RX : PA9/PA10 (VCP) -- USART_3 TX/RX : PB11/PB10 (Arduino USART3) -- USER_PB : PC13 -- LD1 (green) : PI9 -- DAC1 channel 1 output : PA4 -- ADC1 channel 6 input : PF12 - -System Clock ------------- - -STM32H573I-DK System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -240MHz, driven by 25MHz external oscillator (HSE). - -Serial Port ------------ - -STM32H573I-DK Discovery board has 3 U(S)ARTs. The Zephyr console output is -assigned to USART1. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32h573i_dk`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool -interface. Support is available on STM32CubeProgrammer V2.13.0. - -Alternatively, this interface will be supported by a next openocd version. - -Flashing an application to STM32H573I-DK Discovery --------------------------------------------------- - -Connect the STM32H573I-DK Discovery to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h573i_dk - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32h573i_dk - -Debugging -========= - -Waiting for openocd support, debugging could be performed with pyocd which -requires to enable "pack" support with the following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32h5 - -Once installed, you can debug an application in the usual way. Here is an -example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h573i_dk - :maybe-skip-config: - :goals: debug - -.. _STM32H573I-DK Discovery website: - https://www.st.com/en/evaluation-tools/stm32h573i-dk.html - -.. _STM32H573I-DK Discovery board User Manual: - https://www.st.com/en/evaluation-tools/stm32h573i-dk.html - -.. _STM32H573 on www.st.com: - https://www.st.com/en/microcontrollers/stm32h573ii.html - -.. _STM32H573 reference manual: - https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h735g_disco/Kconfig.board b/boards/arm/stm32h735g_disco/Kconfig.board deleted file mode 100644 index 78a8af8bc01601..00000000000000 --- a/boards/arm/stm32h735g_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H735G Discovery board configuration - -# Copyright (c) 2021 SILA Embedded Solutions GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H735G_DISCO - bool "STM32H735G Discovery Development Board" - depends on SOC_STM32H735XX diff --git a/boards/arm/stm32h735g_disco/Kconfig.defconfig b/boards/arm/stm32h735g_disco/Kconfig.defconfig deleted file mode 100644 index 72308958d7b37b..00000000000000 --- a/boards/arm/stm32h735g_disco/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H735G DISCOVERY board configuration - -# Copyright (c) 2021 SILA Embedded Solutions GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H735G_DISCO - -config BOARD - default "stm32h735g_disco" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -endif # BOARD_STM32H735G_DISCO diff --git a/boards/arm/stm32h735g_disco/doc/index.rst b/boards/arm/stm32h735g_disco/doc/index.rst deleted file mode 100644 index e4bf324650be36..00000000000000 --- a/boards/arm/stm32h735g_disco/doc/index.rst +++ /dev/null @@ -1,152 +0,0 @@ -.. _stm32h735g_disco_board: - -ST STM32H735G Discovery -####################### - -Overview -******** - -The STM32H735G-DK Discovery kit is a complete demonstration and development -platform for Arm® Cortex®-M7 core-based STM32H735IGK6U microcontroller, with -1 Mbyte of Flash memory and 564 Kbytes of SRAM. - -The STM32H735G-DK Discovery kit is used as a reference design for user -application development before porting to the final product, thus simplifying -the application development. - -The full range of hardware features available on the board helps users to enhance -their application development by an evaluation of all the peripherals (such as -USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with -audio jack input and output, MEMS digital microphone, HyperRAM™, -Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). -ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension -shields or daughterboards for specific applications. - -STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and -programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H735G-DK board -comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive -software HAL library as well as various software examples. - -.. image:: img/stm32h735g_disco.jpg - :align: center - :alt: STM32H735G-DISCO - -More information about the board can be found at the `STM32H735G-DISCO website`_. -More information about STM32H735 can be found here: - -- `STM32H725/735 on www.st.com`_ -- `STM32H735xx reference manual`_ -- `STM32H735xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h735g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| FDCAN1 | on-chip | CAN-FD Controller | -+-----------+------------+-------------------------------------+ -| FDCAN2 | on-chip | CAN-FD Controller | -+-----------+------------+-------------------------------------+ -| FDCAN2 | on-chip | CAN-FD Controller (disabled by | -| | | default. Solder bridges SB29 and | -| | | SB30 need to be closed for FDCAN3 | -| | | to work) | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32H735G-DISCO website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) -- UART_7 TX/RX : PF7/PF6 (Arduino Serial) -- LD1 : PC2 -- LD2 : PC3 -- FDCAN1 : CAN - -System Clock -============ - -The STM32H735G System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock -is driven by the PLL clock at 550MHz. PLL clock is feed by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32H735G Discovery kit has up to 6 UARTs. -The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual -COM port interface. Default communication settings are 115200 8N1. - - -Programming and Debugging -************************* - -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash the ``stm32h735g_disco`` target. - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h735g_disco - :goals: debug - - -.. _STM32H735G-DISCO website: - https://www.st.com/en/evaluation-tools/stm32h735g-dk.html - -.. _STM32H725/735 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h725-735.html - -.. _STM32H735xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32H735xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h735ag.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h747i_disco/Kconfig.board b/boards/arm/stm32h747i_disco/Kconfig.board deleted file mode 100644 index 819e6f08a605c4..00000000000000 --- a/boards/arm/stm32h747i_disco/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# STM32H747I Discovery board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H747I_DISCO_M7 - bool "STM32H747I Discovery Development Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M7 - -config BOARD_STM32H747I_DISCO_M4 - bool "STM32H747I Discovery Development Board" - depends on SOC_STM32H747XX - select CPU_CORTEX_M4 diff --git a/boards/arm/stm32h747i_disco/Kconfig.defconfig b/boards/arm/stm32h747i_disco/Kconfig.defconfig deleted file mode 100644 index b9c3ba7161ac65..00000000000000 --- a/boards/arm/stm32h747i_disco/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H747I DISCOVERY board configuration - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H747I_DISCO_M7 || BOARD_STM32H747I_DISCO_M4 - -config BOARD - default "stm32h747i_disco_m7" if BOARD_STM32H747I_DISCO_M7 - default "stm32h747i_disco_m4" if BOARD_STM32H747I_DISCO_M4 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32H747I_DISCO_M7 diff --git a/boards/arm/stm32h747i_disco/board.cmake b/boards/arm/stm32h747i_disco/board.cmake deleted file mode 100644 index 00da755afb03e3..00000000000000 --- a/boards/arm/stm32h747i_disco/board.cmake +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_STM32H747I_DISCO_M7) -board_runner_args(jlink "--device=STM32H747ZI_M7") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m7.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) -elseif(CONFIG_BOARD_STM32H747I_DISCO_M4) -board_runner_args(jlink "--device=STM32H747ZI_M4") -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m4.cfg") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) -endif() -board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/stm32h747i_disco/doc/index.rst b/boards/arm/stm32h747i_disco/doc/index.rst deleted file mode 100644 index fa668e964c7503..00000000000000 --- a/boards/arm/stm32h747i_disco/doc/index.rst +++ /dev/null @@ -1,313 +0,0 @@ -.. _stm32h747i_disco_board: - -ST STM32H747I Discovery -####################### - -Overview -******** - -The discovery kit enables a wide diversity of applications taking benefit -from audio, multi-sensor support, graphics, security, video, -and high-speed connectivity features. - -The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, -with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, -large set of peripherals, SMPS, and MIPI-DSI. - -Additionally, the board features: - -- On-board ST-LINK/V3E supporting USB reenumeration capability -- USB ST-LINK functions: virtual COM port, mass storage, debug port -- Flexible power-supply options: - - - ST-LINK USB VBUS, USB OTG HS connector, or external sources - -- 4” capacitive touch LCD display module with MIPI® DSI interface -- Ethernet compliant with IEEE802.3-2002 -- USB OTG HS -- Stereo speaker outputs -- ST-MEMS digital microphones -- 2 x 512-Mbit QUAD-SPI NOR Flash memory -- 256-Mbit SDRAM -- 4 color user LEDs -- 1 user and reset push-button -- 4-direction joystick with selection button -- Arduino Uno V3 connectors - -.. image:: img/stm32h747i_disco.jpg - :align: center - :alt: STM32H747I-DISCO - -More information about the board can be found at the `STM32H747I-DISCO website`_. -More information about STM32H747XIH6 can be found here: - -- `STM32H747XI on www.st.com`_ -- `STM32H747xx reference manual`_ -- `STM32H747xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h747i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ETHERNET | on-chip | ethernet (*) | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| IPM | on-chip | virtual mailbox based on HSEM | -+-----------+------------+-------------------------------------+ -| DISPLAY | on-chip | MIPI DSI Host with shield (MP1166) | -| | | st_b_lcd40_dsi1_mb1166 | -+-----------+------------+-------------------------------------+ - -(*) From UM2411 Rev 4: - With the default setting, the Ethernet feature is not working because of - a conflict between ETH_MDC and SAI4_D1 of the MEMs digital microphone. - Make sure you have SB8 closed and SB21 open to get Ethernet working. - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig files: -``boards/arm/stm32h747i_disco/stm32h747i_disco_defconfig_m7`` and -``boards/arm/stm32h747i_disco/stm32h747i_disco_defconfig_m4`` - -Pin Mapping -=========== - -STM32H747I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32H747I-DISCO website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- UART_8 TX/RX : PJ8/PJ9 (Arduino Serial) -- SPI_5 NSS/SCK/MISO/MOSI : PK1/PK0/PJ11/PJ10 (Arduino SPI) -- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 -- LD1 : PI12 -- LD2 : PI13 -- LD3 : PI14 -- LD4 : PI15 -- W-UP : PC13 -- J-CENTER : PK2 -- J-DOWN : PK3 -- J-LEFT : PK4 -- J-RIGHT : PK5 -- J-UP : PK6 - -System Clock -============ - -The STM32H747I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock -is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock -is driven at 200MHz. PLL clock is feed by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32H747I Discovery kit has up to 8 UARTs. -Default configuration assigns USART1 and UART8 to the CPU1. The Zephyr console -output is assigned to UART1 which connected to the onboard ST-LINK/V3.0. Virtual -COM port interface. Default communication settings are 115200 8N1. - -Ethernet -======== - -**Disclaimer:** This section is mostly copy-paste of corresponding -`DISCO_H747I modifications for Ethernet`_ mbed blog post. The author of this -article sincerely allowed to use the images and his knowledge about necessary -HW modifications to get Ethernet working with this board. - -To get Ethernet working following HW modifications are required: - -- **SB21**, **SB45** and **R87** should be opened -- **SB22**, **SB44**, **SB17** and **SB8** should be closed - -Following two images shows necessary changes on the board marked: - -.. image:: img/disco_h747i_ethernet_modification_1.jpg - :align: center - :alt: STM32H747I-DISCO - Ethernet modification 1 (**SB44**, **SB45**) - -.. image:: img/disco_h747i_ethernet_modification_2.jpg - :align: center - :alt: STM32H747I-DISCO - Ethernet modification 2 (**SB21**, **R87**, **SB22**, **SB17** and **SB8**) - -Display -======= - -The STM32H747I Discovery kit has a dedicated DSI LCD connector **CN15**, where -the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display -support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` to your build -command, for example: - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/display - :board: stm32h747i_disco_m7 - :shield: st_b_lcd40_dsi1_mb1166 - :goals: build flash - -.. note:: - Currently only the older version MB1166-A03 is supported by Zephyr. - The newer version MB1166-A09 does not get initialized correctly (see :github:`60888`). - -Resources sharing -================= - -The dual core nature of STM32H747 SoC requires sharing HW resources between the -two cores. This is done in 3 ways: - -- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only - has access to bus clock activation and deactivation. -- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in - devicetree before compilation. The user must ensure peripherals are not assigned - to both cores at the same time. -- **Run time protection**: Interrupt-controller and GPIO configurations could be - accessed by both cores at run time. Accesses are protected by a hardware semaphore - to avoid potential concurrent access issues. - -Programming and Debugging -************************* - -Applications for the ``stm32h747i_disco`` board should be built per core target, -using either ``stm32h747i_disco_m7`` or ```stm32h747i_disco_m4`` as the target. -See :ref:`build_an_application` for more information about application builds. - -.. note:: - - If using OpenOCD you will need a recent development version as the last - official release does not support H7 dualcore yet. - Also, with OpenOCD, sometimes, flashing is not working. It is necessary to - erase the flash (with STM32CubeProgrammer for example) to make it work again. - Debugging with OpenOCD is currently working for this board only with Cortex M7, - not Cortex M4. - - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash ``stm32h747i_disco_m7`` and ``stm32h747i_disco_m4`` targets. - -By default: - - - CPU1 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) - - CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) - -Also, default out of the box board configuration enables CM7 and CM4 boot when -board is powered (Option bytes BCM7 and BCM4 are checked). -It is possible to change Option Bytes so that CM7 boots first in stand alone, -and CM7 will wakeup CM4 after clock initialization. -Drivers are able to take into account both Option Bytes configurations -automatically. - -Zephyr flash configuration has been set to meet these default settings. - -Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing -it, to flash applications for both cores. The target core is detected automatically. - -.. code-block:: console - - $ west flash --runner stm32cubeprogrammer - -Flashing an application to STM32H747I M7 Core ---------------------------------------------- - -First, connect the STM32H747I Discovery kit to your host computer using -the USB port to prepare it for flashing. Then build and flash your application. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h747i_disco_m7 - :goals: build flash - -Run a serial host program to connect with your board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32h747i_disco_m7 - -.. note:: - Sometimes, flashing is not working. It is necessary to erase the flash - (with STM32CubeProgrammer for example) to make it work again. - -Similarly, you can build and flash samples on the M4 target. For this, please -take care of the resource sharing (UART port used for console for instance). - -Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32h747i_disco_m4 - :goals: build flash - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h747i_disco_m7 - :goals: debug - -Debugging with west is currently not available on Cortex M4 side. -In order to debug a Zephyr application on Cortex M4 side, you can use -`STM32CubeIDE`_. - -.. _STM32H747I-DISCO website: - https://www.st.com/en/evaluation-tools/stm32h747i-disco.html - -.. _STM32H747XI on www.st.com: - https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html - -.. _STM32H747xx reference manual: - https://www.st.com/resource/en/reference_manual/dm00176879.pdf - -.. _STM32H747xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h747xi.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _DISCO_H747I modifications for Ethernet: - https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet - -.. _STM32CubeIDE: - https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.yaml b/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.yaml deleted file mode 100644 index e167c87f64dfd3..00000000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: stm32h747i_disco_m4 -name: ST STM32H747I Discovery (M4) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 288 -flash: 1024 -supported: - - arduino_gpio - - gpio -testing: - ignore_tags: - - mpu - - nfc - - net -vendor: st diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4_defconfig b/boards/arm/stm32h747i_disco/stm32h747i_disco_m4_defconfig deleted file mode 100644 index 2f437301c85078..00000000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_STM32H747I_DISCO_M4=y - -# enable GPIO -CONFIG_GPIO=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable uart driver -CONFIG_SERIAL=y - -# By default CONSOLE is assigned to m7 -#CONFIG_CONSOLE=y -#CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.yaml b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.yaml deleted file mode 100644 index 52e516cda9561e..00000000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: stm32h747i_disco_m7 -name: ST STM32H747I Discovery (M7) -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 512 -flash: 1024 -supported: - - arduino_gpio - - gpio - - arduino_spi - - spi - - netif:eth - - qspi - - memc - - usb_cdc - - usb_device -vendor: st diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig b/boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig deleted file mode 100644 index c288ddfc5e4cbe..00000000000000 --- a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H747XX=y - -# Board config should be specified since there are 2 possible targets -CONFIG_BOARD_STM32H747I_DISCO_M7=y - -# Enable the internal SMPS regulator -CONFIG_POWER_SUPPLY_DIRECT_SMPS=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable clocks -CONFIG_CLOCK_CONTROL=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Disable following to assign serial ports to m4 core - -# enable uart driver -CONFIG_SERIAL=y -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h750b_dk/Kconfig.board b/boards/arm/stm32h750b_dk/Kconfig.board deleted file mode 100644 index afa01489528212..00000000000000 --- a/boards/arm/stm32h750b_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H735G Discovery board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H750B_DK - bool "STM32H750B Discovery Kit" - depends on SOC_STM32H750XX diff --git a/boards/arm/stm32h750b_dk/Kconfig.defconfig b/boards/arm/stm32h750b_dk/Kconfig.defconfig deleted file mode 100644 index 48576f5706d3e0..00000000000000 --- a/boards/arm/stm32h750b_dk/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32H750B DK board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H750B_DK - -config BOARD - default "stm32h750b_dk" - -endif # BOARD_STM32H750B_DK diff --git a/boards/arm/stm32h750b_dk/board.cmake b/boards/arm/stm32h750b_dk/board.cmake deleted file mode 100644 index 6500e7b1a4a914..00000000000000 --- a/boards/arm/stm32h750b_dk/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") -board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/stm32h750b_dk/doc/index.rst b/boards/arm/stm32h750b_dk/doc/index.rst deleted file mode 100644 index 6ac1aa15d34d8a..00000000000000 --- a/boards/arm/stm32h750b_dk/doc/index.rst +++ /dev/null @@ -1,145 +0,0 @@ -.. _stm32h750b_dk_board: - -ST STM32H750B Discovery Kit -########################### - -Overview -******** - -The STM32H750B-DK Discovery kit is a complete demonstration and development -platform for Arm® Cortex®-M7 core-based STM32H750XBH6 microcontroller, with -128Kbytes of Flash memory and 1 Mbytes of SRAM. - -The STM32H750B-DK Discovery kit is used as a reference design for user -application development before porting to the final product, thus simplifying -the application development. - -The full range of hardware features available on the board helps users to enhance -their application development by an evaluation of all the peripherals (such as -USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with -audio jack input and output, MEMS digital microphone, HyperRAM™, -Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). -ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension -shields or daughterboards for specific applications. - -STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and -programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H750B-DK board -comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive -software HAL library as well as various software examples. - -.. image:: img/stm32h750b_dk.png - :align: center - :alt: STM32H750B-DK - -More information about the board can be found at the `STM32H750B-DK website`_. -More information about STM32H750 can be found here: - -- `STM32H750 on www.st.com`_ -- `STM32H750xx reference manual`_ -- `STM32H750xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h750b_dk board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32H750B-DK website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) -- LD1 : PJ2 -- LD2 : PI13 - -System Clock -============ - -The STM32H750B System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock -is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock. - -Serial Port -=========== - -The STM32H750B Discovery kit has up to 6 UARTs. -The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual -COM port interface. Default communication settings are 115200 8N1. - - -Programming and Debugging -************************* - -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Connect the STM32H750B-DK to your host computer using the ST-LINK -USB port, then run a serial host program to connect with the board. For example: - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h750b_dk - :goals: build flash - -You should see the following message in the serial host program: - -.. code-block:: console - - $ Hello World! stm32h750b_dk - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h750b_dk - :goals: debug - - -.. _STM32H750B-DK website: - https://www.st.com/en/evaluation-tools/stm32h750b-dk.html - -.. _STM32H750 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html - -.. _STM32H750xx reference manual: - https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32H750xx datasheet: - https://www.st.com/resource/en/datasheet/stm32h750ib.pdf diff --git a/boards/arm/stm32h7b3i_dk/Kconfig.board b/boards/arm/stm32h7b3i_dk/Kconfig.board deleted file mode 100644 index c3912d786e0ca8..00000000000000 --- a/boards/arm/stm32h7b3i_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32H7B3I Discovery kit board configuration - -# Copyright (c) 2022 Byte-Lab d.o.o. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32H7B3I_DK - bool "STM32H7B3I Discovery Kit Development Board" - depends on SOC_STM32H7B3XXQ diff --git a/boards/arm/stm32h7b3i_dk/Kconfig.defconfig b/boards/arm/stm32h7b3i_dk/Kconfig.defconfig deleted file mode 100644 index 8a32fb1c68fcb8..00000000000000 --- a/boards/arm/stm32h7b3i_dk/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# STM32H7B3I DISCOVERY KIT board configuration - -# Copyright (c) 2022 Byte-Lab d.o.o. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32H7B3I_DK - -config BOARD - default "stm32h7b3i_dk" - -config INPUT - default y if LVGL - -config INPUT_FT5336_INTERRUPT - default y if INPUT_FT5336 - -# MEMC needs to be enabled in order to store -# display buffer to external SDRAM connected to FMC -config MEMC - default y if DISPLAY - -endif # BOARD_STM32H7B3I_DK diff --git a/boards/arm/stm32h7b3i_dk/doc/index.rst b/boards/arm/stm32h7b3i_dk/doc/index.rst deleted file mode 100644 index 83d18858426509..00000000000000 --- a/boards/arm/stm32h7b3i_dk/doc/index.rst +++ /dev/null @@ -1,171 +0,0 @@ -.. _stm32h7b3i_dk_board: - -ST STM32H7B3I Discovery Kit -########################### - -Overview -******** - -The STM32H7B3I-DK Discovery kit is a complete demonstration and development -platform for STMicroelectronics Arm® Cortex®-M7 core-based STM32H7B3LIH6QU -microcontroller. - -The STM32H7B3I-DK Discovery kit is used as a reference design for user -application development before porting to the final product, thus simplifying -the application development. - -The full range of hardware features available on the board helps users enhance -their application development by an evaluation of almost all peripherals (such as -USB OTG_HS, microSD, USART, FDCAN, audio DAC stereo with audio jack input and output, -camera, SDRAM, Octo-SPI Flash memory and RGB interface LCD with capacitive touch -panel). ARDUINO® Uno V3 connectors provide easy connection to extension shields or -daughterboards for specific applications. - -STLINK-V3E is integrated into the board, as an embedded in-circuit debugger and -programmer for the STM32 MCU and the USB Virtual COM port bridge. The STM32H7B3I-DK -board comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive -software HAL library as well as various software examples. - -.. image:: img/stm32h7b3i_dk.jpg - :align: center - :alt: STM32H7B3I-DK - -More information about the board can be found at the `STM32H7B3I-DK website`_. -More information about STM32H7B3 can be found here: - -- `STM32H7A3/7B3 on www.st.com`_ -- `STM32H7A3/7B3/7B0 reference manual`_ -- `STM32H7B3xI datasheet`_ - -Supported Features -================== - -The current Zephyr stm32h7b3i_dk board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| FMC | on-chip | memc (SDRAM) | -+-----------+------------+-------------------------------------+ -| LTDC | on-chip | display | -+-----------+------------+-------------------------------------+ -| CANFD | on-chip | can | -+-----------+------------+-------------------------------------+ - - -Other hardware features have not been enabled yet for this board. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32H7B3I-DK website`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- UART_4 TX/RX : PH13/PH14 (Arduino Serial) -- I2C4 SCL/SDA : PD12/PD13 (Arduino I2C, Touchscreen FT5336 with PH2 Interrupt Pin) -- SPI2 SCK/MISO/MOSI/NSS : PA12/PB14/PB15/PI0 (Arduino SPI) -- LD1 : PG11 -- LD2 : PG2 -- USER_PB : PC13 -- SDMMC D0/D1/D2/D3/CK/CMD/CD : PC8/PC9/PC10/PC11/PC12/PD2/PI8 -- CANFD RX/TX/WAKE [#]_ : PA11/PA12/PH8 -- FMC SDRAM : - - - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 - - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 - - A14/A15 : PG4/PG5 - - SDNRAS/SDNCAS : PF11/PG15 - - NBL0/NBL1 : PE0/PE1 - - SDCLK/SDNWE/SDCKE1/SDNE1 : PG8/PH5/PH7/PH6 - -- LTDC : - - - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 - - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 - - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 - - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 - - -System Clock -============ - -The STM32H7B3I System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven -by the PLL clock at 280MHz. PLL clock is fed by a 24MHz high speed external clock. - -Serial Port -=========== - -The STM32H7B3I Discovery kit has up to 8 UARTs. -The Zephyr console output is assigned to UART1 which connected to the onboard -ST-LINK/V3.0. Virtual COM port interface. Default communication settings are -115200 8N1. - - -Programming and Debugging -************************* - -See :ref:`build_an_application` for more information about application builds. - - -Flashing -======== - -Flashing operation will depend on the target to be flashed and the SoC -option bytes configuration. -It is advised to use `STM32CubeProgrammer`_ to check and update option bytes -configuration and flash the ``stm32h7b3i_dk`` target. - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32h7b3i_dk - :goals: debug - - -.. _STM32H7B3I-DK website: - https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html - -.. _STM32H7A3/7B3 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3-7b3.html - -.. _STM32H7A3/7B3/7B0 reference manual: - https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32H7B3xI datasheet: - https://www.st.com/resource/en/datasheet/stm32h7b3ai.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STM32H7B3I_DK board schematics: - https://www.st.com/resource/en/schematic_pack/mb1332-h7b3i-c02_schematic.pdf - -.. [#] To use CAN, solder bridges SB3, SB4 and SB5 need to be connected. - Take note that CANFD pins are shared with STMOD+ connector (P1), so please check - `STM32H7B3I_DK board schematics`_ for possible collisions if using that connector. diff --git a/boards/arm/stm32l1_disco/Kconfig.board b/boards/arm/stm32l1_disco/Kconfig.board deleted file mode 100644 index e9621b560b0760..00000000000000 --- a/boards/arm/stm32l1_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Board configuration - -# Copyright (c) 2019 eTactica ehf -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L1_DISCO - bool "STM32L1DISCOVERY Development Board" - depends on SOC_STM32L151XB diff --git a/boards/arm/stm32l1_disco/Kconfig.defconfig b/boards/arm/stm32l1_disco/Kconfig.defconfig deleted file mode 100644 index 8159f9c1abbecd..00000000000000 --- a/boards/arm/stm32l1_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Board configuration - -# Copyright (c) 2019 eTactica ehf -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L1_DISCO - -config BOARD - default "stm32l1_disco" - -endif # BOARD_STM32L1_DISCO diff --git a/boards/arm/stm32l1_disco/doc/index.rst b/boards/arm/stm32l1_disco/doc/index.rst deleted file mode 100644 index a968cebc7928f4..00000000000000 --- a/boards/arm/stm32l1_disco/doc/index.rst +++ /dev/null @@ -1,179 +0,0 @@ -.. _stm32l1_disco_board: - -ST STM32L1 Discovery -#################### - -Overview -******** - -The two generations of the STM32L1 Discovery development boards come with -an integrated ST-LINK/V2 debugger and programmer. The boards have a -24-segment LCD and a touch slider, along with two user LEDs and a user button. -Support circuitry for measuring power consumption is also available. -It also comes with a comprehensive STM32 software HAL library and various -packaged software examples. - -There -are two variants of the board: - -- STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM -- 32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM - -The STM32LDISCOVERY is no longer sold, but was widely available. The current -configuration assumes only 128K flash and 16K RAM, so it builds and runs -on both variants out of the box. - -.. image:: img/stm32l1_disco.jpg - :align: center - :alt: STM32LDISCOVERY - -More information about the board can be found at the `STM32LDISCOVERY website`_. - -Hardware -******** - -The STM32 Discovery board features: - -- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone - ST-LINK/V2 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- Four LEDs: - - - LD1 (red) for 3.3 V power on - - LD2 (red/green) for USB communication - - LD3 (green) for PC9 output - - LD4 (blue) for PC8 output -- Two push buttons (user and reset) -- Extension header for all LQFP64 I/Os for quick connection to prototyping board - and easy probing - -More information about STM32L151x can be found in the `STM32L1x reference manual`_. - -Supported Features -================== - -The Zephyr stm32l1_disco board configuration supports the following hardware features: - -.. list-table:: Supported hardware - :header-rows: 1 - - * - Interface - - Controller - - Driver/component - * - NVIC - - on-chip - - nested vector interrupt controller - * - UART - - on-chip - - serial port-polling - serial port-interrupt - * - PINMUX - - on-chip - - pinmux - * - GPIO - - on-chip - - gpio - * - CLOCK - - on-chip - - reset and clock control - * - FLASH - - on-chip - - flash memory - * - WATCHDOG - - on-chip - - window watchdog - * - I2C - - on-chip - - i2c - * - SPI - - on-chip - - spi - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32l1_disco/stm32l1_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB11 -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 - -For more details please refer to `STM32L1DISCOVERY board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32l1_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32L1DISCOVERY board includes an ST-LINK/V2 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application ------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32l1_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32l1_disco - :maybe-skip-config: - :goals: debug - -References -********** - -.. target-notes:: - -.. _STM32LDISCOVERY website: - https://www.st.com/en/evaluation-tools/32l152cdiscovery.html - -.. _STM32L1x reference manual: - https://www.st.com/resource/en/reference_manual/cd00240193.pdf - -.. _STM32L1DISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/dm00027954.pdf diff --git a/boards/arm/stm32l476g_disco/Kconfig.board b/boards/arm/stm32l476g_disco/Kconfig.board deleted file mode 100644 index 2aa9ec78b19306..00000000000000 --- a/boards/arm/stm32l476g_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L476G Discovery board configuration - -# Copyright (c) 2017 Arthur Sfez -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L476G_DISCO - bool "STM32L476G Discovery Development Board" - depends on SOC_STM32L476XX diff --git a/boards/arm/stm32l476g_disco/Kconfig.defconfig b/boards/arm/stm32l476g_disco/Kconfig.defconfig deleted file mode 100644 index 77e423642a3d58..00000000000000 --- a/boards/arm/stm32l476g_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32L476G DISCOVERY board configuration - -# Copyright (c) 2017 Arthur Sfez -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L476G_DISCO - -config BOARD - default "stm32l476g_disco" - -endif # BOARD_STM32L476G_DISCO diff --git a/boards/arm/stm32l476g_disco/doc/index.rst b/boards/arm/stm32l476g_disco/doc/index.rst deleted file mode 100644 index 65eef57c609f9c..00000000000000 --- a/boards/arm/stm32l476g_disco/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _stm32l476g_disco_board: - -ST STM32L476G Discovery -####################### - -Overview -******** - -The STM32L476G Discovery board features an ARM Cortex-M4 based STM32L476VG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32L476G Discovery board: - - -- STM32L476VGT6 microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package -- On-board ST-LINK/V2-1 supporting USB re-enumeration capability -- Three different interfaces supported on USB: - - - Virtual com port - - Mass storage - - Debug port - -- LCD 24 segments, 4 commons in DIP 28 package -- Seven LEDs: - - - LD1 (red/green) for USB communication - - LD2 (red) for 3.3 V power on - - LD3 Over current (red) - - LD4 (red), LD5 (green) two user LEDs - - LD6 (green), LD7 (red) USB OTG FS LEDs - -- Pushbutton (reset) -- Four directions Joystick with selection -- USB OTG FS with micro-AB connector -- SAI Audio DAC, Stereo with output jack -- Digital microphone, accelerometer, magnetometer and gyroscope MEMS -- 128-Mbit Quad-SPI Flash memory -- MCU current ammeter with 4 ranges and auto-calibration -- Connector for external board or RF-EEPROM -- Four power supply options: - - ST-LINK/V2-1 - - USB FS connector - - External 5 V - - CR2032 battery (not provided) - -.. image:: img/stm32l476g_disco.jpg - :align: center - :alt: STM32L476G Discovery - -More information about the board can be found at the `STM32L476G Discovery website`_. - -Hardware -******** - -The STM32L476VG SoC provides the following hardware features: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - Up to 128 KB of SRAM including 32 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories - - Quad SPI memory interface -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators -- 18x communication interfaces - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 3x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (4x SPIs with the Quad SPI) - - CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L476VG can be found here: - - `STM32L476VG on www.st.com`_ - - `STM32L476 reference manual`_ - - -Supported Features -================== - -The Zephyr stm32l476g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig`` - - -Connections and IOs -=================== - -STM32L476G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L476G Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2_TX : PD5 -- UART_2_RX : PD6 -- LD4 : PB2 -- LD5 : PE8 - -System Clock ------------- - -STM32L476G Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -STM32L476G Discovery board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -STM32L476G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. -This interface is supported by the openocd version included in Zephyr SDK. - -Flashing an application to STM32L476G Discovery ------------------------------------------------ - -Connect the STM32L476G Discovery to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l476g_disco - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l476g_disco - :maybe-skip-config: - :goals: debug - -.. _STM32L476G Discovery website: - https://www.st.com/en/evaluation-tools/32l476gdiscovery.html - -.. _STM32L476G Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00172179.pdf - -.. _STM32L476VG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l476vg.html - -.. _STM32L476 reference manual: - https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l496g_disco/Kconfig.board b/boards/arm/stm32l496g_disco/Kconfig.board deleted file mode 100644 index 4d2e23204a81a5..00000000000000 --- a/boards/arm/stm32l496g_disco/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# STM32L496G Discovery board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# Copyright (c) 2019 Centaur Analytics, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L496G_DISCO - bool "STM32L496G Discovery Development Board" - depends on SOC_STM32L496XX diff --git a/boards/arm/stm32l496g_disco/Kconfig.defconfig b/boards/arm/stm32l496g_disco/Kconfig.defconfig deleted file mode 100644 index 114aacf680d937..00000000000000 --- a/boards/arm/stm32l496g_disco/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# STM32L476G Nucleo board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L496G_DISCO - -config BOARD - default "stm32l496g_disco" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_STM32L496G_DISCO diff --git a/boards/arm/stm32l496g_disco/doc/index.rst b/boards/arm/stm32l496g_disco/doc/index.rst deleted file mode 100644 index e8bc81f092b9e8..00000000000000 --- a/boards/arm/stm32l496g_disco/doc/index.rst +++ /dev/null @@ -1,259 +0,0 @@ -.. _stm32l496g_disco_board: - -ST STM32L496G Discovery -####################### - -Overview -******** - -The STM32L496G Discovery board features an ARM Cortex-M4 based STM32L496AG MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the STM32L496G Discovery board: - - -- STM32L496AGI6 microcontroller featuring 1 Mbyte of Flash memory and 320 Kbytes of RAM in an UFBGA169 package -- 1.54 inch 240 x 240 pixel-TFT color LCD with parallel interface -- SAI Audio CODEC, with a stereo headset jack, including analog microphone input -- Stereo digital MEMS microphones -- microSD card connector (card included) -- Camera 8 bit-connector -- 8 Mbit-PSRAM -- IDD measurement -- 64 Mbit-Quad-SPI Flash -- USB OTG FS with Micro-AB connector -- Two types of extension resources: - - - STMod+ and PMOD connectors - - Compatible Arduino* Uno V3 connectors - -- On-board ST-LINK/V2-1 debugger/programmer with SWD connector -- 5 source options for power supply - - - ST-LINK/V2-1 USB connector - - User USB FS connector - - VIN from Arduino connector - - 5 V from Arduino connector - - USB charger - - USB VBUS or external source(3.3V, 5V, 7 - 12V) - - Power management access point - -- 8 LEDs -- Reset push button -- 4 direction-joystick with selection - -.. image:: img/stm32l496g_disco.jpg - :align: center - :alt: STM32L496G Discovery - -More information about the board can be found at the `STM32L496G Discovery website`_. - -Hardware -******** - -The STM32L496AG SoC provides the following hardware capabilities: - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 - |micro| A/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, - 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) -- Clock Sources: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - Internal 48 MHz with clock recovery - - 3 PLLs for system clock, USB, audio, ADC - -- RTC with HW calendar, alarms and calibration -- LCD 8 x 40 or 4 x 44 with step-up converter -- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- 16x timers: - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 2x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - SysTick timer - -- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Memories - - - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection - - 320 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR, and NAND memories - - Quad SPI memory interface - -- 4x digital filters for sigma delta modulator -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 - |micro| A/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - -- 20x communication interfaces - - - USB OTG 2.0 full-speed, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 5x USARTs (ISO 7816, LIN, IrDA, modem) - - 1x LPUART - - 3x SPIs (4x SPIs with the Quad SPI) - - 2x CAN (2.0B Active) and SDMMC interface - - SWPMI single wire protocol master I/F - - IRTIM (Infrared interface) - -- 14-channel DMA controller -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* - - -More information about STM32L496AG can be found in: - -- `STM32L496AG on www.st.com`_ -- `STM32L496 reference manual`_ - -Supported Features -================== - -The Zephyr stm32l496g_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | disk access | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| QSPI NOR | on-chip | off-chip flash | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb_device | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig`` - - -Connections and IOs -=================== - -STM32L496G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L496G Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_1 TX/RX : PB6/PG10 -- UART_2 TX/RX : PA2/PD6 (ST-Link Virtual Port Com) -- LPUART_1 TX/RX : PG7/PG8 (Arduino Serial) -- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) -- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 -- SPI1 NSS/SCK/MISO/MOSI : PA15/PA5/PB4/PB5 (Arduino SPI) -- USB DM/DP/ID : PA11/PA12/PA10 -- I2C_1_SCL : PB8 -- I2C_1_SDA : PB7 -- PWM_2_CH1 : PA0 -- LD2 : PB13 - -System Clock ------------- - -STM32L496G Discovery System Clock could be driven by an internal or external oscillator, -as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, -driven by 16MHz high speed internal oscillator. - -Serial Port ------------ - -STM32L496G Discovery board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. -Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug -tool interface. This interface is supported by openocd version -v0.10.0, which has been available since Zephyr SDK v0.9.2. - -Applications for the ``stm32l496g_disco`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - -Flashing an application to STM32L496G Discovery ------------------------------------------------ - -Connect the STM32L496G Discovery to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l496g_disco - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l496g_disco - :maybe-skip-config: - :goals: debug - -.. _STM32L496G Discovery website: - https://www.st.com/en/evaluation-tools/32l496gdiscovery.html - -.. _STM32L496G Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00353127.pdf - -.. _STM32L496AG on www.st.com: - https://www.st.com/en/microcontrollers/stm32l496ag.html - -.. _STM32L496 reference manual: - https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l4r9i_disco/Kconfig.board b/boards/arm/stm32l4r9i_disco/Kconfig.board deleted file mode 100644 index 57da0f65fdfa8c..00000000000000 --- a/boards/arm/stm32l4r9i_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L4R9I Discovery board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L4R9I_DISCO - bool "STM32L4R9I Discovery Development Board" - depends on SOC_STM32L4R9XX diff --git a/boards/arm/stm32l4r9i_disco/Kconfig.defconfig b/boards/arm/stm32l4r9i_disco/Kconfig.defconfig deleted file mode 100644 index 82eafa62744388..00000000000000 --- a/boards/arm/stm32l4r9i_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32L4R9I Discovery board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L4R9I_DISCO - -config BOARD - default "stm32l4r9i_disco" - -endif # BOARD_STM32L4R9I_DISCO diff --git a/boards/arm/stm32l4r9i_disco/doc/index.rst b/boards/arm/stm32l4r9i_disco/doc/index.rst deleted file mode 100644 index 0f651e2b9ffc25..00000000000000 --- a/boards/arm/stm32l4r9i_disco/doc/index.rst +++ /dev/null @@ -1,150 +0,0 @@ -.. _stm32l4r9i_disco_board: - -ST STM32L4R9I Discovery -####################### - -Overview -******** - -The 32L4R9IDISCOVERY Discovery kit is a complete demonstration and development platform -for STMicroelectronics Arm® Cortex®-M4 core-based STM32L4R9AI microcontroller. - -Leveraging the innovative ultra-low-power oriented features, 640 Kbytes of embedded RAM, -graphics performance (Chrom-ART Accelerator), and DSI controller offered by the STM32L4R9AI, -the 32L4R9IDISCOVERY Discovery kit enables users to easily prototype applications with -state-of-the-art energy efficiency, as well as stunning audio and graphics rendering with direct -support for AMOLED DSI round LCD display. - -For even more user-friendliness, the on-board ST-LINK/V2-1 debugger provides out-of-the-box -programming and debugging capabilities. - -.. image:: img/stm32l4r9i_disco.jpg - :align: center - :alt: STM32L4R9I-DISCO - -More information about the board can be found at the `STM32L4R9I-DISCOVERY website`_. -More information about STM32L4R9 can be found here: - -- `STM32L4R9/S9 on www.st.com`_ -- `STM32L4+ Series reference manual`_ -- `STM32L4R5xx/R7xx/R9xx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32l4r9i_disco board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | on-chip flash memory; | -| | | external OctoSPI memory | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | Real Time Clock | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | sd/mmc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on Zephyr porting. - -The default configuration can be found in the defconfig file: - - ``boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig`` - - -Pin Mapping -=========== - -For more details, please refer to `STM32L4R9I-DISCOVERY website`_. - -System Clock -============ - -The STM32L4R9AI System Clock can be driven by an internal or external oscillator, -as well as by the main PLL clock. By default, the System clock is driven by -the PLL clock at 120MHz. PLL clock is driven by a 4MHz medium speed internal clock. - -Serial Port -=========== - -The STM32L4R9I Discovery board has up to 6 U(S)ARTs. -The Zephyr console output is assigned to UART2, which is connected to the onboard -ST-LINK Virtual COM port interface. Default communication settings are 115200 8N1. - - -Programming and Debugging -************************* - -Flashing -======== - -The STM32L4R9I Discovery board includes an ST-LINK/V2-1 debug tool. - -Applications for the ``stm32l4r9i_disco`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details). - - -Flashing an application to STM32L4R9I Discovery ------------------------------------------------ - -Connect the STM32L4R9I Discovery to your host computer using the ST-LINK -USB port, then run a serial host program to connect with the board. For example: - -.. code-block:: console - - $ minicom -b 115200 -D /dev/ttyACM0 - -You can then build and flash applications in the usual way. -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l4r9i_disco - :goals: build flash - -You should see the following message in the serial host program: - -.. code-block:: console - - $ Hello World! stm32l4r9i_disco - - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l4r9i_disco - :goals: debug - -.. _STM32L4R9I-DISCOVERY website: - https://www.st.com/en/evaluation-tools/32l4r9idiscovery.html - -.. _STM32L4R9/S9 on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32l4r9-s9.html - -.. _STM32L4+ Series reference manual: - https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32L4R5xx/R7xx/R9xx datasheet: - https://www.st.com/resource/en/datasheet/stm32l4r5vi.pdf diff --git a/boards/arm/stm32l562e_dk/Kconfig.board b/boards/arm/stm32l562e_dk/Kconfig.board deleted file mode 100644 index 44cabce93d3d5e..00000000000000 --- a/boards/arm/stm32l562e_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32L562E-DK Discovery board configuration - -# Copyright (c) 2020 Yestin Sun -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32L562E_DK - bool "STM32L562E-DK Discovery Development Board" - depends on SOC_STM32L562XX diff --git a/boards/arm/stm32l562e_dk/Kconfig.defconfig b/boards/arm/stm32l562e_dk/Kconfig.defconfig deleted file mode 100644 index 3a81889dc71c67..00000000000000 --- a/boards/arm/stm32l562e_dk/Kconfig.defconfig +++ /dev/null @@ -1,40 +0,0 @@ -# STM32L562E-DK Discovery board configuration - -# Copyright (c) 2020 Yestin Sun -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32L562E_DK - -config BOARD - default "stm32l562e_dk" - -if BT - -config SPI - default y - -choice BT_HCI_BUS_TYPE - default BT_SPI -endchoice - -config BT_BLUENRG_ACI - default y - -# Disable Flow control -config BT_HCI_ACL_FLOW_CONTROL - default n - -config BT_HCI_VS_EXT - default n - -endif # BT - -if TRUSTED_EXECUTION_NONSECURE - -# Get flash configuration for NS image from dts flash partition -config USE_DT_CODE_PARTITION - default y - -endif # TRUSTED_EXECUTION_NONSECURE - -endif # BOARD_STM32L562E_DK diff --git a/boards/arm/stm32l562e_dk/doc/index.rst b/boards/arm/stm32l562e_dk/doc/index.rst deleted file mode 100644 index 16af6cb242b6fe..00000000000000 --- a/boards/arm/stm32l562e_dk/doc/index.rst +++ /dev/null @@ -1,387 +0,0 @@ -.. _stm32l562e_dk_board: - -ST STM32L562E-DK Discovery -########################## - -Overview -******** - -The STM32L562E-DK Discovery kit is designed as a complete demonstration and -development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based -STM32L562QEI6QU microcontroller with TrustZone |reg|. Here are some highlights of -the STM32L562E-DK Discovery board: - - -- STM32L562QEI6QU microcontroller featuring 512 Kbytes of Flash memory and 256 Kbytes of SRAM in BGA132 package -- 1.54" 240 x 240 pixel-262K color TFT LCD module with parallel interface and touch-control panel -- USB Type-C |trade| Sink device FS -- On-board energy meter: 300 nA to 150 mA measurement range with a dedicated USB interface -- SAI Audio CODEC -- MEMS digital microphones -- 512-Mbit Octal-SPI Flash memory -- Bluetooth |reg| V4.1 Low Energy module -- iNEMO 3D accelerometer and 3D gyroscope -- Board connectors - - - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors - - Pmod |trade| expansion connector - - Audio MEMS daughterboard expansion connector - - ARDUINO |reg| Uno V3 expansion connector - -- Flexible power-supply options - - - ST-LINK - - USB VBUS - - external sources - -- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: - - - mass storage - - Virtual COM port - - debug port - -- 2 user LEDs -- User and reset push-buttons - -.. image:: img/stm32l562e_dk.jpg - :align: center - :alt: STM32L562E-DK Discovery - -More information about the board can be found at the `STM32L562E-DK Discovery website`_. - -Hardware -******** - -The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5 -Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. -They operate at a frequency of up to 110 MHz. - -- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. -- Performance benchmark: - - - 1.5 DMPIS/MHz (Drystone 2.1) - - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ) - -- Security - - - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals - - Flexible life cycle scheme with RDP (readout protection) - - Root of trust thanks to unique boot entry and hide protection area (HDP) - - Secure Firmware Installation thanks to embedded Root Secure Services - - Secure Firmware Update support with TF-M - - AES coprocessor - - Public key accelerator - - On-the-fly decryption of Octo-SPI external memories - - HASH hardware accelerator - - Active tamper and protection temperature, voltage and frequency attacks - - True Random Number Generator NIST SP800-90B compliant - - 96-bit unique ID - - 512-byte One-Time Programmable for user data - -- Clock management: - - - 4 to 48 MHz crystal oscillator - - 32 kHz crystal oscillator for RTC (LSE) - - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) - - Internal low-power 32 kHz RC ( |plusminus| 5%) - - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by - LSE (better than |plusminus| 0.25 % accuracy) - - 3 PLLs for system clock, USB, audio, ADC - -- Power management - - - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry - - Embedded SMPS step-down converter - - External SMPS support - -- RTC with HW calendar, alarms and calibration -- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V -- Up to 22 capacitive sensing channels: support touchkey, linear and rotary touch sensors -- Up to 16 timers and 2 watchdogs - - - 2x 16-bit advanced motor-control - - 2x 32-bit and 5x 16-bit general purpose - - 2x 16-bit basic - - 3x low-power 16-bit timers (available in Stop mode) - - 2x watchdogs - - 2x SysTick timer - -- Memories - - - Up to 512 MB Flash, 2 banks read-while-write - - 512 KB of SRAM including 64 KB with hardware parity check - - External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories - - OCTOSPI memory interface - -- Rich analog peripherals (independent supply) - - - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS - - 2x 12-bit DAC, low-power sample and hold - - 2x operational amplifiers with built-in PGA - - 2x ultra-low-power comparators - - 4x digital filters for sigma delta modulator - -- 19x communication interfaces - - - USB Type-C / USB power delivery controller - - 2.0 full-speed crystal less solution, LPM and BCD - - 2x SAIs (serial audio interface) - - 4x I2C FM+(1 Mbit/s), SMBus/PMBus - - 6x USARTs (ISO 7816, LIN, IrDA, modem) - - 3x SPIs (7x SPIs with USART and OCTOSPI in SPI mode) - - 1xFDCAN - - 1xSDMMC interface - - 2x 14 channel DMA controllers - -- CRC calculation unit -- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| - - -More information about STM32L562QE can be found here: - -- `STM32L562QE on www.st.com`_ -- `STM32L562 reference manual`_ - -Supported Features -================== - -The Zephyr stm32l562e_dk board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| ADC | on-chip | ADC Controller | -+-----------+------------+-------------------------------------+ -| AES | on-chip | crypto | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | DAC Controller | -+-----------+------------+-------------------------------------+ -| DMA | on-chip | Direct Memory Access | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | PWM | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | sd/mmc | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| TrustZone | on-chip | Trusted Firmware-M | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig and dts files: - -- Common: - - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi` - -- Secure target: - - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig` - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk.dts` - -- Non-Secure target: - - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig` - - :zephyr_file:`boards/arm/stm32l562e_dk/stm32l562e_dk_ns.dts` - -Zephyr board options -==================== - -The STM32L562e is an SoC with Cortex-M33 architecture. Zephyr provides support -for building for both Secure and Non-Secure firmware. - -The BOARD options are summarized below: - -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| stm32l562e_dk | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| stm32l562e_dk_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ - -Here are the instructions to build Zephyr with a non-secure configuration, -using `tfm_ipc_` sample: - - .. code-block:: bash - - $ west build -b stm32l562e_dk_ns samples/tfm_integration/tfm_ipc/ - -Once done, before flashing, you need to first run a generated script that -will set platform option bytes config and erase platform (among others, -option bit TZEN will be set). - - .. code-block:: bash - - $ ./build/tfm/regression.sh - $ west flash - -Please note that, after having run a TFM sample on the board, you will need to -run `./build/tfm/regression.sh` once more to clean up the board from secure -options and get back the platform back to a "normal" state and be able to run -usual, non-TFM, binaries. -Also note that, even then, TZEN will remain set, and you will need to use -STM32CubeProgrammer_ to disable it fully, if required. - -Connections and IOs -=================== - -STM32L562E-DK Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, -input/output, pull-up, etc. - -For more details please refer to `STM32L562E-DK Discovery board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX/RX : PA9/PA10 -- USART_3 TX/RX : PC10/PC11 -- I2C_1 SCL/SDA : PB6/PB7 -- SPI_1 SCK/MISO/MOSI : PG2/PG3/PG4 (BT SPI bus) -- SPI_3 NSS/SCK/MISO/MOSI : PE0/PG9/PB4/PB5 (Arduino SPI) -- USER_PB : PC13 -- LD10 : PG12 -- PWM_2_CH1 : PA0 -- DAC1 : PA4 -- ADC1 : PC4 - -System Clock ------------- - -STM32L562E-DK System Clock could be driven by internal or external oscillator, -as well as main PLL clock. By default System clock is driven by PLL clock at -110MHz, driven by 4MHz medium speed internal oscillator. - -Serial Port ------------ - -STM32L562E-DK Discovery board has 6 U(S)ARTs. The Zephyr console output is -assigned to USART1. Default settings are 115200 8N1. - - -Programming and Debugging -************************* - -Applications for the ``stm32l562e_dk`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool -interface. Support can be enabled on pyocd by adding "pack" support with the -following pyocd command: - -.. code-block:: console - - $ pyocd pack --update - $ pyocd pack --install stm32l562qe - -Alternatively, this interface is supported by the openocd version -included in the Zephyr SDK since v0.13.1. - -Flashing an application to STM32L562E-DK Discovery --------------------------------------------------- - -Connect the STM32L562E-DK Discovery to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Nucleo board: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l562e_dk - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32l562e_dk - -Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| ------------------------------------------------------------------------------ - -The TF-M integration sample :ref:`tfm_ipc` can be run on a ST STM32L562E-DK Discovery. -In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``stm32l562e_dk_ns`` as build target. - -.. code-block:: bash - - $ west build -b stm32l562e_dk_ns path/to/source/directory - -Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script -is run automatically in a post-build step to make some required flash layout changes. - -Once the build is completed, run the following script to initialize the option bytes. - -.. code-block:: bash - - $ build/tfm/regression.sh - -Finally, to flash the board, run: - -.. code-block:: bash - - $ west flash --hex-file build/tfm_merged.hex - -Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts -(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` -(which is used for initialization) is available in the PATH. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32l562e_dk - :maybe-skip-config: - :goals: debug - -.. _STM32L562E-DK Discovery website: - https://www.st.com/en/evaluation-tools/stm32l562e-dk.html - -.. _STM32L562E-DK Discovery board User Manual: - https://www.st.com/resource/en/user_manual/dm00635554.pdf - -.. _STM32L562QE on www.st.com: - https://www.st.com/en/microcontrollers/stm32l562qe.html - -.. _STM32L562 reference manual: - https://www.st.com/resource/en/reference_manual/DM00346336.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.yaml b/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.yaml deleted file mode 100644 index 8d743536e74d86..00000000000000 --- a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: stm32l562e_dk_ns -name: ST STM32L562E-DK Discovery non secure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb -supported: - - counter - - gpio - - i2c - - lptim - - dac - - spi - - arduino_spi - - sdhc - - usb - - usb_device -ram: 192 -flash: 512 -vendor: st diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig b/boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig deleted file mode 100644 index c28424d306a05a..00000000000000 --- a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns_defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L562XX=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable GPIO -CONFIG_GPIO=y - -# Enable Clocks -CONFIG_CLOCK_CONTROL=y - -# console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/arm/stm32mp157c_dk2/Kconfig.board b/boards/arm/stm32mp157c_dk2/Kconfig.board deleted file mode 100644 index b020b97dd881ac..00000000000000 --- a/boards/arm/stm32mp157c_dk2/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32MP157C Discovery board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32MP157C_DK2 - bool "STM32MP157C Discovery Development 2 Board" - depends on SOC_STM32MP15_M4 diff --git a/boards/arm/stm32mp157c_dk2/Kconfig.defconfig b/boards/arm/stm32mp157c_dk2/Kconfig.defconfig deleted file mode 100644 index 277a98e6de6643..00000000000000 --- a/boards/arm/stm32mp157c_dk2/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# STM32MP157 discovery board configuration - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32MP157C_DK2 - -config BOARD - default "stm32mp157c_dk2" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -config CLOCK_STM32_HSE_CLOCK - default 24000000 - -endif # BOARD_STM32MP157_Dk2 diff --git a/boards/arm/stm32u5a9j_dk/Kconfig.board b/boards/arm/stm32u5a9j_dk/Kconfig.board deleted file mode 100644 index 8482aa58f0447a..00000000000000 --- a/boards/arm/stm32u5a9j_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32U5A9J Discovery Kit board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32U5A9J_DK - bool "STM32U5A9J Discovery Kit Development Board" - depends on SOC_STM32U5A9XX diff --git a/boards/arm/stm32u5a9j_dk/Kconfig.defconfig b/boards/arm/stm32u5a9j_dk/Kconfig.defconfig deleted file mode 100644 index 8124e0227409ab..00000000000000 --- a/boards/arm/stm32u5a9j_dk/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# STM32U5A9J DISCOVERY KIT board configuration - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32U5A9J_DK - -config BOARD - default "stm32u5a9j_dk" - -endif # BOARD_STM32U5A9J_DK diff --git a/boards/arm/stm32u5a9j_dk/doc/index.rst b/boards/arm/stm32u5a9j_dk/doc/index.rst deleted file mode 100644 index 23859666df7abc..00000000000000 --- a/boards/arm/stm32u5a9j_dk/doc/index.rst +++ /dev/null @@ -1,198 +0,0 @@ -.. _stm32u5a9j_dk_board: - -ST STM32U5A9J Discovery Kit -########################### - -Overview -******** - -The STM32U5A9J-DK Discovery kit is a complete demonstration and development -platform for the STM32U5A9NJH6Q microcontroller, featuring an Arm® Cortex®-M33 -core with Arm® TrustZone®. - -Leveraging the innovative ultra-low-power oriented features, 2.5 Mbytes of -embedded SRAM, 4 Mbytes of embedded flash memory, and rich graphics features, -the STM32U5A9J-DK Discovery kit enables users to easily prototype applications -with state-of-the-art energy efficiency, as well as providing stunning and -optimized graphics rendering with the support of the 2.5D NeoChrom Accelerator, -Chrom-ART Accelerator, and Chrom-GRC™ MMU. - -The full range of hardware features available on the board helps users to -enhance their application development by an evaluation of all the peripherals -such as a 2.47-inch RGB 480x480 pixels TFT round LCD module with MIPI DSI® -interface and capacitive touch panel, USB Type-C® HS, Octo-SPI flash memory -device, Hexadeca-SPI PSRAM memory device, eMMC flash memory device, -Time-of-Flight and gesture detection sensor, temperature sensor, and two 2.54 mm -pitch double-row flexible expansion connectors for easy prototyping with -daughterboards for specific applications (USART, LPUART, two SPIs, SAI, three -I2C, SDMMC, ADCs, timers, and GPIOs). - -The STM32U5A9J-DK Discovery kit integrates an STLINK-V3E embedded in-circuit -debugger and programmer for the STM32 microcontroller with a USB Virtual COM -port bridge and comes with the STM32CubeU5 MCU Package, which provides an STM32 -comprehensive software HAL library as well as various software examples. - -.. image:: img/top_view.jpg - :align: center - :alt: STM32U5A9J-DK Top View - -.. image:: img/bottom_view.jpg - :align: center - :alt: STM32U5A9J-DK Bottom View - -More information about the board can be found at the `STM32U5A9J-DK website`_. -More information about STM32U5A9NJH6Q can be found here: - -- `STM32U5A9NJ on www.st.com`_ -- `STM32U5 Series reference manual`_ -- `STM32U5Axxx datasheet`_ - -Supported Features -================== - -The current Zephyr stm32u5a9j_dk board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| LPUART | on-chip | low power uart | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| RNG | on-chip | True Random number generator | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| SDMMC | on-chip | flash memory | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration per core can be found in the defconfig file: -``boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig`` - -Pin Mapping -=========== - -For more details please refer to `STM32U5A9J-DK board User Manual`_. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- USART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) -- LD3 : PE0 -- LD4 : PE1 -- User Button: PC13 -- USART_3 TX/RX : PB10/PB11 -- LPUART_1 TX/RX : PG7/PG8 -- I2C1 SCL/SDA : PG14/PG13 -- I2C2 SCL/SDA : PF1/PF0 -- I2C6 SCL/SDA : PD1/PD0 -- SPI2 SCK/MISO/MOSI/CS : PB13/PD3/PD4/PB12 -- SPI3 SCK/MISO/MOSI/CS : PG9/PG10/PG11/PG15 -- ADC1 : channel5 PA0, channel14 PC5 -- ADC2 : channel9 PA4 -- ADC4 : channel5 PF14 - -System Clock -============ - -The STM32U5A9J-DK Discovery kit relies on an HSE oscillator (16 MHz crystal) -and an LSE oscillator (32.768 kHz crystal) as clock references. -Using the HSE (instead of HSI) is mandatory to manage the DSI interface for -the LCD module and the USB high‑speed interface. - -Serial Port -=========== - -The STM32U5A9J Discovery kit has up to 4 USARTs, 2 UARTs, and 1 LPUART. -The Zephyr console output is assigned to USART1 which connected to the onboard -ST-LINK/V3.0. Virtual COM port interface. Default communication settings are -115200 8N1. - - -Programming and Debugging -************************* - -STM32U5A9J Discovery kit includes an ST-LINK/V3 embedded debug tool interface. -This probe allows to flash and debug the board using various tools. - -Flashing -======== - -Board is configured to be flashed using west STM32CubeProgrammer runner. -Installation of `STM32CubeProgrammer`_ is then required to flash the board., - -Connect the STM32U5A9J Discovery board to your host computer using the USB -port, then run a serial host program to connect with your Discovery -board. For example: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 -b 115200 - -Then, build and flash in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stm32u5a9j_dk - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! stm32u5a9j_dk - -Debugging -========= - -Default debugger for this board is openocd. It could be used in the usual way -with "west debug" command. -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32u5a9j_dk - :goals: debug - - -.. _STM32U5A9J-DK website: - https://www.st.com/en/evaluation-tools/stm32u5a9j-dk.html - -.. _STM32U5A9J-DK board User Manual: - https://www.st.com/resource/en/user_manual/um2967-discovery-kit-with-stm32u5a9nj-mcu-stmicroelectronics.pdf - -.. _STM32U5A9NJ on www.st.com: - https://www.st.com/en/microcontrollers-microprocessors/stm32u5a9nj.html - -.. _STM32U5 Series reference manual: - https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf - -.. _STM32U5Axxx datasheet: - https://www.st.com/resource/en/datasheet/stm32u5a9nj.pdf - -.. _STM32CubeProgrammer: - https://www.st.com/en/development-tools/stm32cubeprog.html - -.. _STM32U5A9J_DK board schematics: - https://www.st.com/resource/en/schematic_pack/mb1829-u5a9njq-b01-schematic.pdf diff --git a/boards/arm/stm32vl_disco/Kconfig.board b/boards/arm/stm32vl_disco/Kconfig.board deleted file mode 100644 index 57a0e43e68e9fd..00000000000000 --- a/boards/arm/stm32vl_disco/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Board configuration - -# Copyright (c) 2020 Jonas Eriksson, Up to Code AB -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32VL_DISCO - bool "STM32VLDISCOVERY Development Board" - depends on SOC_STM32F100XB diff --git a/boards/arm/stm32vl_disco/Kconfig.defconfig b/boards/arm/stm32vl_disco/Kconfig.defconfig deleted file mode 100644 index 1bdcdc36a0dbe8..00000000000000 --- a/boards/arm/stm32vl_disco/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Board configuration - -# Copyright (c) 2020 Jonas Eriksson, Up to Code AB -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32VL_DISCO - -config BOARD - default "stm32vl_disco" - -endif # BOARD_STM32VL_DISCO diff --git a/boards/arm/stm32vl_disco/doc/index.rst b/boards/arm/stm32vl_disco/doc/index.rst deleted file mode 100644 index 7819200bafb30e..00000000000000 --- a/boards/arm/stm32vl_disco/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. _stm32vl_disco_board: - -ST STM32VL Discovery -#################### - -Overview -******** - -The STM32 Discovery series comes in many varieties, in this case the "Value -Line" STM32F100x SoC series is showcased. Like other Discovery board, an -integrated ST-LINK debugger and programmer is included (V1), but the only -included I/O devices are two user LEDs and one user button. - -.. image:: img/stm32vl_disco.jpg - :align: center - :alt: STM32VLDISCOVERY - -More information about the board can be found at the `STM32VLDISCOVERY website`_. - -Hardware -******** - -The STM32 Discovery board features: - -- On-board ST-LINK/V1 with selection mode switch to use the kit as a standalone - ST-LINK/V1 (with SWD connector for programming and debugging) -- Board power supply: through USB bus or from an external 5 V supply voltage -- External application power supply: 3 V and 5 V -- Four LEDs: - - - LD1 (red) for 3.3 V power on - - LD2 (red/green) for USB communication - - LD3 (green) for PC9 output - - LD4 (blue) for PC8 output -- Two push buttons (user and reset) -- Extension header for all LQFP64 I/Os for quick connection to prototyping board - and easy probing - -More information about the STM32F100x can be found in the -`STM32F100x reference manual`_ and the `STM32F100x data sheet`_. - -Supported Features -================== - -The Zephyr stm32vl_disco board configuration supports the following hardware features: - -.. list-table:: Supported hardware - :header-rows: 1 - - * - Interface - - Controller - - Driver/component - * - NVIC - - on-chip - - nested vector interrupt controller - * - UART - - on-chip - - serial port-polling - serial port-interrupt - * - PINMUX - - on-chip - - pinmux - * - GPIO - - on-chip - - gpio - * - CLOCK - - on-chip - - reset and clock control - * - FLASH - - on-chip - - flash memory - * - WATCHDOG - - on-chip - - window watchdog - * - I2C - - on-chip - - i2c - * - SPI - - on-chip - - spi - * - ADC - - on-chip - - adc - -Other hardware features are not yet supported in this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/stm32vl_disco/stm32vl_disco_defconfig`` - -Connections and IOs -=================== - -Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as -input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the -GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current -capable except for analog inputs. - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PA3 -- UART_3_TX : PB10 -- UART_3_RX : PB11 -- SPI1_NSS : PA4 -- SPI1_SCK : PA5 -- SPI1_MISO : PA6 -- SPI1_MOSI : PA7 -- SPI2_NSS : PB12 -- SPI2_SCK : PB13 -- SPI2_MISO : PB14 -- SPI2_MOSI : PB15 -- I2C1_SCL : PB6 -- I2C1_SDA : PB7 -- I2C2_SCL : PB10 -- I2C2_SDA : PB11 - -For more details please refer to `STM32VLDISCOVERY board User Manual`_. - -Programming and Debugging -************************* - -Applications for the ``stm32vl_disco`` board configuration can be built and -flashed in the usual way (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Flashing -======== - -STM32VLDISCOVERY board includes an ST-LINK/V1 embedded debug tool interface. -This interface is supported by the openocd version included in the Zephyr SDK. - -Flashing an application ------------------------ - -Here is an example for the :zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32vl_disco - :goals: build flash - -You will see the LED blinking every second. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:zephyr:code-sample:`blinky` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: stm32vl_disco - :maybe-skip-config: - :goals: debug - -USB mass storage issues -======================= - -The ST-LINK/V1 includes a buggy USB mass storage gadget. To connect to the -ST-LINK from Linux, you might need to ignore the device using modprobe -configuration parameters: - -.. code-block:: shell - - $ echo "options usb-storage quirks=483:3744:i" | sudo tee /etc/modprobe.d/local.conf - $ sudo modprobe -r usb-storage - -References -********** - -.. target-notes:: - -.. _STM32VLDISCOVERY website: - https://www.st.com/en/evaluation-tools/stm32vldiscovery.html - -.. _STM32F100x reference manual: - https://www.st.com/resource/en/reference_manual/cd00246267.pdf - -.. _STM32F100x data sheet: - https://www.st.com/resource/en/datasheet/stm32f100cb.pdf - -.. _STM32VLDISCOVERY board User Manual: - https://www.st.com/resource/en/user_manual/cd00267113.pdf diff --git a/boards/arm/stm32wb5mm_dk/Kconfig.board b/boards/arm/stm32wb5mm_dk/Kconfig.board deleted file mode 100644 index 28ca74d81a9508..00000000000000 --- a/boards/arm/stm32wb5mm_dk/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WB5MM-DK Discovery Development board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32WB5MM_DK - bool "stm32wb5mm-dk Discovery Development Board" - depends on SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mm_dk/Kconfig.defconfig b/boards/arm/stm32wb5mm_dk/Kconfig.defconfig deleted file mode 100644 index 5ce31881bd079a..00000000000000 --- a/boards/arm/stm32wb5mm_dk/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WB5MM-DK Discovery Development board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32WB5MM_DK - -config BOARD - default "stm32wb5mm_dk" - -choice BT_HCI_BUS_TYPE - default BT_STM32_IPM - depends on BT -endchoice - -endif # BOARD_STM32WB5MM_DK diff --git a/boards/arm/stm32wb5mmg/Kconfig.board b/boards/arm/stm32wb5mmg/Kconfig.board deleted file mode 100644 index 4fe8c22fd7cfa2..00000000000000 --- a/boards/arm/stm32wb5mmg/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# STM32WB5MMG Bluetooth module board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STM32WB5MMG - bool "stm32wb5mmg ultra low power Bluetooth module" - depends on SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mmg/Kconfig.defconfig b/boards/arm/stm32wb5mmg/Kconfig.defconfig deleted file mode 100644 index cedb62395be139..00000000000000 --- a/boards/arm/stm32wb5mmg/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# STM32WB5MMG Bluetooth module board configuration - -# Copyright (c) 2024 Javad Rahimipetroudi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_STM32WB5MMG - -config BOARD - default "stm32wb5mmg" - -choice BT_HCI_BUS_TYPE - default BT_STM32_IPM - depends on BT -endchoice - -endif # BOARD_STM32WB5MMG diff --git a/boards/arm/swan_r5/CMakeLists.txt b/boards/arm/swan_r5/CMakeLists.txt deleted file mode 100644 index 218a0602483ab4..00000000000000 --- a/boards/arm/swan_r5/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_sources(board.c) diff --git a/boards/arm/swan_r5/Kconfig.board b/boards/arm/swan_r5/Kconfig.board deleted file mode 100644 index f1f15cb8bd72ab..00000000000000 --- a/boards/arm/swan_r5/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Blues Wireless Swan board configuration - -# Copyright (c) 2022 Blues Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SWAN_R5 - bool "Blues Wireless Swan Development Board" - depends on SOC_STM32L4R5XX diff --git a/boards/arm/swan_r5/Kconfig.defconfig b/boards/arm/swan_r5/Kconfig.defconfig deleted file mode 100644 index 0ab4dbfb0d0f26..00000000000000 --- a/boards/arm/swan_r5/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Blues Wireless Swan board configuration - -# Copyright (c) 2022 Blues Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SWAN_R5 - -config BOARD - default "swan_r5" - -config SPI_STM32_INTERRUPT - default y - depends on SPI - -if NETWORKING - -config USB_DEVICE_STACK - default y - -config USB_DEVICE_NETWORK_EEM - default y - -endif # NETWORKING - -endif # BOARD_SWAN_R5 diff --git a/boards/arm/swan_r5/doc/index.rst b/boards/arm/swan_r5/doc/index.rst deleted file mode 100644 index 8a70207bf5887b..00000000000000 --- a/boards/arm/swan_r5/doc/index.rst +++ /dev/null @@ -1,232 +0,0 @@ -.. _swan_r5_board: - -Blues Wireless Swan -################### - -Overview -******** - -Swan is a low-cost embeddable STM32L4-based microcontroller designed to -accelerate the development and deployment of battery-powered solutions. -It is especially useful for applications requiring large memory or a high -degree of I/O expandability at an affordable cost, such as edge inferencing -and remote monitoring. - -Uniquely for Feather-compatible boards, Swan is designed to satisfy -developers' needs that span from early prototyping through high-volume -deployment. Developers may begin to use Swan in conjunction with -Adafruit's myriad sensors and FeatherWing-compatible carriers. -Due to its novel design, for high-volume deployment the low-cost Swan -can also be soldered directly to a parent PCB integrating those sensors, -utilizing the full range of Swan's I/O capabilities. - -The board has three independent power options-USB, Battery, or Line power- -and provides a software-switchable 2 Amp regulator for powering external -sensors. When operating in its low-power operating mode, the entire Swan -board commonly draws only about 8uA while retaining all of its memory, -making it quite suitable for battery-powered devices. - -The Swan board features an ARM Cortex-M4 based STM32L4R5ZI MCU -with a wide range of connectivity support and configurations. Here are -some highlights of the board: - -- STM32 microcontroller in WLCSP144 package -- 2MB of flash and 640KB of RAM -- Two types of extension resources: - - - Adafruit Feather-compatible connectivity - - Access to 36 additional STM32 pins (beyond the Feather pins) via 0.05" castellated edge headers - -- On-board ST-LINKV3 debugger/programmer with SWD connector - -- One Red User LED (LD1) -- Two push-buttons: USER and RESET - -- Castellated-edge access to 55 GPIO ports including: - - - 8 analog - - 16 digital - - 4x I2C, 3x SPI - - USB OTG full speed - - 1x 14-channel DMA - - tRNG - - 12-bit ADC, 2 x 12-bit DAC - - low-power RTC, and CRC calculation peripherals - -.. image:: img/swan.jpg - :align: center - :alt: Blues Wireless Swan - -More information about the board can be found at the `Swan Product Page`_. - -Hardware -******** - -The STM32L4R5ZI SoC provides the following hardware IPs: - -- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode - and 100 uA/MHz run mode) -- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive - real-time accelerator (ART Accelerator) allowing 0-wait-state - execution from Flash memory, frequency up to 120 MHz, MPU, 150 - DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions - -- Memories - - - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection - - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check - - External memory interface for static memories supporting SRAM, - PSRAM, NOR, NAND and FRAM memories - - 2 x OctoSPI memory interface - -- True random number generator -- CRC calculation unit, 96-bit unique ID -- Development support: serial wire debug (SWD), JTAG, Embedded Trace - Macrocell (ETM) - -More information about Swan can be found here: - -- `Swan Quickstart Guide`_ -- `Swan Datasheet`_ - -Supported Features -================== - -The Zephyr Swan board configuration supports the following -hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| USB | on-chip | usb | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -Other hardware features are not yet supported on this Zephyr port. - -The default configuration can be found in the defconfig file: -``boards/arm/swan_r5/swan_r5_defconfig`` - - -Connections and IOs -=================== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -.. rst-class:: rst-columns - -- A0 : PA3 -- A1 : PA1 -- A2 : PC3 -- A3 : PC1 -- A4 : PC4 -- A5 : PC5 -- D4 : PE3 -- D5 : PE11 -- D6 : PE9 -- D9 : PD15 -- D10 : PA4 -- D11 : PA7 -- D12 : PA6 -- D13 : PA5 -- UART_1_TX : PA9 -- UART_1_RX : PA10 -- UART_2_TX : PA2 -- UART_2_RX : PD6 -- UART_3_TX : PB10 -- UART_3_RX : PB11 -- LPUART_TX : PG7 -- LPUART_RX : PG8 -- I2C_1_SCL : PB6 -- I2C_1_SDA : PB7 -- I2C_2_SCL : PF1 -- I2C_2_SDA : PF0 -- I2C_3_SCL : PC0 -- I2C_3_SDA : PC9 -- SPI_1_NSS : PA4 -- SPI_1_SCK : PA5 -- SPI_1_MISO : PA6 -- SPI_1_MOSI : PA7 -- SPI_2_NSS : PD0 -- SPI_2_SCK : PD1 -- SPI_2_MISO : PB14 -- SPI_2_MOSI : PB15 -- SPI_3_NSS : PA15 -- SPI_3_SCK : PC10 -- SPI_3_MISO : PC11 -- SPI_3_MOSI : PC12 -- PWM_2_CH1 : PA0 -- USER_PB : PC13 -- LD1 : PE2 -- USB DM : PA11 -- USB DP : PA12 -- ADC1 : PA1 - -System Clock ------------- - -Swan System Clock could be driven by internal or external -oscillator, as well as main PLL clock. By default, the System clock is -driven by the PLL clock at 80MHz, driven by a 16MHz high speed -internal oscillator. - -Serial Port ------------ - -Swan has 4 U(S)ARTs. The Zephyr console output is -assigned to LPUART. Default settings are 115200 8N1. - -Programming and Debugging -************************* - -Connect Swan to your host computer using the USB port. -Then build and flash an application. Here is an example for the -:ref:`hello_world` application. - -Run a serial host program to connect with your Swan: - -.. code-block:: console - - $ minicom -D /dev/ttyACM0 - -Then build and flash the application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: swan_r5 - :goals: build flash - -You should see the following message on the console: - -.. code-block:: console - - Hello World! arm - -References -********** - -.. _Swan Product Page: - https://blues.io/products/swan - -.. _Swan Quickstart Guide: - https://dev.blues.io/start/swan/swan-quickstart - -.. _Swan Datasheet: - https://dev.blues.io/hardware/swan-datasheet/ diff --git a/boards/arm/tdk_robokit1/Kconfig.board b/boards/arm/tdk_robokit1/Kconfig.board deleted file mode 100644 index 16ea951fc203c7..00000000000000 --- a/boards/arm/tdk_robokit1/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# TDK RoboKit 1 Board Options - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TDK_ROBOKIT1 - bool "TDK RoboKit1 Board" - depends on SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70Q21B diff --git a/boards/arm/tdk_robokit1/Kconfig.defconfig b/boards/arm/tdk_robokit1/Kconfig.defconfig deleted file mode 100644 index eab856c9089abd..00000000000000 --- a/boards/arm/tdk_robokit1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# TDK RoboKit1 Configuration - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TDK_ROBOKIT1 - -config BOARD - default "tdk_robotkit1" - -endif # BOARD_TDK_ROBOKIT1 diff --git a/boards/arm/tdk_robokit1/board.cmake b/boards/arm/tdk_robokit1/board.cmake deleted file mode 100644 index 975b58dbcb1154..00000000000000 --- a/boards/arm/tdk_robokit1/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_runner_args(jlink "--device=ATSAME70Q21") -board_runner_args(openocd --cmd-post-verify "atsamv gpnvm set 1") -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/tdk_robokit1/doc/index.rst b/boards/arm/tdk_robokit1/doc/index.rst deleted file mode 100644 index a34408c3baff6d..00000000000000 --- a/boards/arm/tdk_robokit1/doc/index.rst +++ /dev/null @@ -1,184 +0,0 @@ -.. _tdk_robokit1: - -TDK RoboKit 1 -############# - -Overview -******** - -The TDK RoboKit1 is a development board for use primarily with ROS2 and provides a large -number of small ground robotics useful sensors including chirp sensors for time of flight -(e.g. ultrasonic obstacle detection). - -It pairs a 300MHz Cortex-M7 ATSAME70Q21 with an array of TDK sensors and pin headers useful for robotics. - -.. image:: img/tdk_robokit1.jpg - :align: center - :alt: TDK RoboKit1 - -Hardware -******** - -- ATSAME70Q21 ARM Cortex-M7 Processor -- 12 MHz crystal oscillator (Pres) -- 32.768 kHz crystal oscillator -- Micro-AB USB device -- Micro-AB USB debug (Microchip EDBG) interface supporting CMSIS-DAP, Virtual COM Port and Data -- JTAG interface connector -- One reset pushbutton -- One red user LED -- TDK ICM 42688-P 6-Axis 32KHz IMU -- TDK ICP-10111 Pressure Sensor -- TDK NTC Thermistor for Temperature -- AKM AK09918C Magnetometer -- 2 TDK HVCi-4223 Cortex-M3 Dedicated Motor Controller -- 3 TDK ICS-43434 Stereo Microphones -- Connector for Industrial Dual IMU (TDK IIM-46230) -- TDK CH101 Ultrasonic Range Sensor Array (9 Connectors, comes with 3) - -Supported Features -================== - -The TDK RoboKit1 board supports the following hardware -features: - -.. list-table:: - : header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - GPIO - - :kconfig:option:`CONFIG_GPIO_SAM` - - :dtcompatible:`atmel,sam-gpio` - * - USART - - :kconfig:option:`CONFIG_USART_SAM` - - :dtcompatible:`atmel,sam-usart` - * - UART - - :kconfig:option:`CONFIG_UART_SAM` - - :dtcompatible:`atmel,sam-uart` - * - SPI - - :kconfig:option:`CONFIG_SPI_SAM` - - :dtcompatible:`atmel,sam-spi` - * - I2C - - :kconfig:option:`CONFIG_I2C_SAM_TWIHS` - - :dtcompatible:`atmel,sam-i2c-twihs` - * - I2S - - :kconfig:option:`CONFIG_I2S_SAM_SSC` - - :dtcompatible:`atmel,sam-ssc` - * - ADC - - :kconfig:option:`CONFIG_ADC_SAM_AFEC` - - :dtcompatible:`atmel,sam-afec` - * - DAC - - :kconfig:option:`CONFIG_DAC_SAM` - - :dtcompatible:`atmel,sam-dac` - * - PWM - - :kconfig:option:`CONFIG_PWM_SAM` - - :dtcompatible:`atmel,sam-pwm` - * - CAN - - :kconfig:option:`CONFIG_CAN_SAM` - - :dtcompatible:`atmel,sam-can` - * - USB - - :kconfig:option:`CONFIG_USB_DC_SAM_USBHS` - - :dtcompatible:`atmel,sam-usbhs` - * - WATCHDOG - - :kconfig:option:`CONFIG_WDT_SAM` - - :dtcompatible:`atmel,sam-watchdog` - * - NVIC - - N/A - - :dtcompatible:`arm,v7m-nvic` - * - SYSTICK - - N/A - - N/A - * - COUNTER - - :kconfig:option:`CONFIG_COUNTER_SAM_TC` - - :dtcompatible:`atmel,sam-tc` - * - DMA - - :kconfig:option:`CONFIG_DMA_SAM_XDMAC` - - :dtcompatible:`atmel,sam-xdmac` - * - ENTROPY - - :kconfig:option:`CONFIG_ENTROPY_SAM_RNG` - - :dtcompatible:`atmel,sam-trng` - * - HWINFO (reset cause) - - :kconfig:option:`CONFIG_HWINFO_SAM_RSTC` - - :dtcompatible:`atmel,sam-rstc` - * - HWINFO (device id) - - :kconfig:option:`CONFIG_HWINFO_SAM` - - N/A - -The default configuration can be found in the Kconfig -:zephyr_file:`boards/arm/tdk_robokit1/tdk_robokit1_defconfig`. - -Connections and IOs -=================== - -The TDK RoboKit Hardware Guide has detailed information about board connections. - -System Clock -============ - -The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board -with the on-chip PLL to generate a 300 MHz system clock. - -Serial Port -=========== - -The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the UARTs is -configured for the console and is available as a Virtual COM Port via the USB2 connector. - -Programming and Debugging -************************* - -Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. -Both west flash and west debug commands should correctly work with both USB0 and USB1 -connected and the board powered. - -Flashing -======== - -#. Run your favorite terminal program to listen for output. Under Linux the - terminal should be :code:`/dev/ttyACM0`. For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -o - - The -o option tells minicom not to send the modem initialization - string. Connection should be configured as follows: - - - Speed: 115200 - - Data: 8 bits - - Parity: None - - Stop bits: 1 - -#. Connect the TDK RoboKit1 board to your host computer using the - USB debug port (USB1), USB2 for a serial console, and remaining micro USB for - power. Then build and flash the :ref:`hello_world` application. - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: tdk_robokit1 - :goals: build flash - - You should see "Hello World! tdk_robokit1" in your terminal. - -Debugging -========= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: tdk_robokit1 - :maybe-skip-config: - :goals: debug - -References -********** - -TDK RoboKit1 Product Page: - https://invensense.tdk.com/products/robokit1-dk/ - -.. _OpenOCD tool: - http://openocd.org/ diff --git a/boards/arm/tdk_robokit1/tdk_robokit1-common.dtsi b/boards/arm/tdk_robokit1/tdk_robokit1-common.dtsi deleted file mode 100644 index 5fc1bf4cb9f5f9..00000000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1-common.dtsi +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "tdk_robokit1-pinctrl.dtsi" - -/ { - aliases { - led0 = &led_0; - magn0 = &akm09918c; - accel0 = &icm42688; - die-temp0 = &icm42688; - ambient-temp0 = &temp_sensor; - }; - - chosen { - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - zephyr,sram = &sram0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - led_0: led_0 { - gpios = <&pioa 11 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - led_1: led_1 { - gpios = <&pioa 12 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - led_2: led_2 { - gpios = <&pioa 13 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - led_3: led_3 { - gpios = <&pioa 14 GPIO_ACTIVE_HIGH>; - label = "User LED"; - }; - }; - - temp_sensor: ambient_temp_sensor { - compatible = "epcos,b57861s0103a039"; - io-channels = <&spi_adc 0>; - pullup-uv = <3300000>; - pullup-ohm = <0>; - pulldown-ohm = <10000>; - connected-positive; - }; -}; - -&cpu0 { - clock-frequency = <300000000>; -}; - -&afec0 { - pinctrl-0 = <&afec0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&dacc { - status = "okay"; -}; - -&twihs0 { - pinctrl-0 = <&twihs0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&twihs1 { - pinctrl-0 = <&twihs1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&twihs2 { - pinctrl-0 = <&twihs2_default>; - pinctrl-names = "default"; - status = "okay"; - akm09918c: akm09918c@c { - compatible = "asahi-kasei,akm09918c"; - reg = <0xc>; - }; -}; - -&spi0 { - pinctrl-0 = <&spi0_default>; - pinctrl-names = "default"; - dmas = <&xdmac 0 DMA_PERID_SPI0_TX>, <&xdmac 1 DMA_PERID_SPI0_RX>; - dma-names = "tx", "rx"; - cs-gpios =<&pioa 31 GPIO_ACTIVE_LOW>, - <&pioc 31 GPIO_ACTIVE_LOW>; - status = "okay"; - - icm42688: icm42688p@0 { - compatible = "invensense,icm42688"; - reg = <0>; - int-gpios = <&pioc 5 GPIO_ACTIVE_HIGH>; - spi-max-frequency = <24000000>; - accel-hz = <32000>; - accel-fs = <16>; - gyro-hz = <32000>; - gyro-fs = <2000>; - }; - spi_adc: adc@1 { - compatible = "ti,ads7052"; - reg = <1>; - #io-channel-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - spi-max-frequency = <24000000>; - channel@0 { - reg = <0>; - zephyr,gain = "ADC_GAIN_1"; - zephyr,reference = "ADC_REF_VDD_1"; - zephyr,vref-mv = <3300>; - zephyr,acquisition-time = ; - zephyr,resolution = <14>; - }; - }; -}; - -&spi1 { - pinctrl-0 = <&spi1_default>; - pinctrl-names = "default"; - cs-gpios = <&pioc 25 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&uart0 { - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&usart2 { - current-speed = <115200>; - pinctrl-0 = <&usart2_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&wdt { - status = "okay"; -}; - -zephyr_udc0: &usbhs { - status = "okay"; -}; - -&mdio { - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - status = "okay"; -}; - -&pwm0 { - pinctrl-0 = <&pwm_default>; - pinctrl-names = "default"; - status = "okay"; -}; - - -&xdmac { - status = "okay"; -}; - -&flash0 { - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* - * The first half of sector 0 (64 kbytes) - * is reserved for the bootloader - */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x0 0x00010000>; - read-only; - }; - - /* From sector 1 to sector 7 (included): slot0 (896 kbytes) */ - slot0_partition: partition@20000 { - label = "image-0"; - reg = <0x00020000 0x000e0000>; - }; - - /* From sector 8 to sector 14 (included): slot1 (896 kbytes) */ - slot1_partition: partition@100000 { - label = "image-1"; - reg = <0x00100000 0x000e0000>; - }; - - /* Sector 15: scratch (128 kbytes) */ - scratch_partition: partition@1e0000 { - label = "image-scratch"; - reg = <0x001e0000 0x00020000>; - }; - }; -}; diff --git a/boards/arm/tdk_robokit1/tdk_robokit1.dts b/boards/arm/tdk_robokit1/tdk_robokit1.dts deleted file mode 100644 index a8763609e9b814..00000000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1.dts +++ /dev/null @@ -1,16 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -#include "tdk_robokit1-common.dtsi" - -/ { - model = "TDK RoboKit1"; - compatible = "tdk,robokit1", "atmel,same70q21", "atmel,same70"; -}; diff --git a/boards/arm/tdk_robokit1/tdk_robokit1.yaml b/boards/arm/tdk_robokit1/tdk_robokit1.yaml deleted file mode 100644 index 4c4d8b19e13c2a..00000000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: tdk_robokit1 -name: TDK RoboKit1 -type: mcu -arch: arm -ram: 384 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - dma - - i2c - - gpio - - spi - - watchdog - - usb_device - - pwm - - can - - hwinfo -vendor: tdk diff --git a/boards/arm/tdk_robokit1/tdk_robokit1_defconfig b/boards/arm/tdk_robokit1/tdk_robokit1_defconfig deleted file mode 100644 index f5df64df2a5267..00000000000000 --- a/boards/arm/tdk_robokit1/tdk_robokit1_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SAME70=y -CONFIG_SOC_PART_NUMBER_SAME70Q21B=y -CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK=y -CONFIG_SOC_ATMEL_SAME70_PLLA_MULA=24 -CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA=1 -CONFIG_ARM_MPU=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_BOARD_TDK_ROBOKIT1=y -CONFIG_WDT_DISABLE_AT_BOOT=y -CONFIG_BUILD_OUTPUT_HEX=y - -# Enable HW stack protection -CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/teensy4/CMakeLists.txt b/boards/arm/teensy4/CMakeLists.txt deleted file mode 100644 index 56f5eb005ab3f0..00000000000000 --- a/boards/arm/teensy4/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_library() -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(flexspi_nor_config.c) - zephyr_library_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA teensy4_sdram_ini_dcd.c) -endif() diff --git a/boards/arm/teensy4/Kconfig.board b/boards/arm/teensy4/Kconfig.board deleted file mode 100644 index f0f5f55a8e0e73..00000000000000 --- a/boards/arm/teensy4/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_TEENSY40 - bool "PJRC TEENSY40" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVL6A - -config BOARD_TEENSY41 - bool "PJRC TEENSY41" - depends on SOC_SERIES_IMX_RT - select SOC_PART_NUMBER_MIMXRT1062DVJ6A diff --git a/boards/arm/teensy4/Kconfig.defconfig b/boards/arm/teensy4/Kconfig.defconfig deleted file mode 100644 index 5e8eac0d0f0f78..00000000000000 --- a/boards/arm/teensy4/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2020, Bernhard Kraemer -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_TEENSY40 || BOARD_TEENSY41 - -config BUILD_OUTPUT_HEX - bool - default y - -config BOARD - default "teensy40" if BOARD_TEENSY40 - default "teensy41" if BOARD_TEENSY41 - -choice CODE_LOCATION - default CODE_FLEXSPI -endchoice - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_TEENSY40 || BOARD_TEENSY41 diff --git a/boards/arm/teensy4/flexspi_nor_config.c b/boards/arm/teensy4/flexspi_nor_config.c deleted file mode 100644 index 6420e446bd9f74..00000000000000 --- a/boards/arm/teensy4/flexspi_nor_config.c +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * Copyright (c) 2021, Bernhard Kraemer - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackFromDqsPad, - .csHoldTime = 3u, - .csSetupTime = 3u, - .sflashPadType = kSerialFlash_4Pads, - .serialClkFreq = kFlexSpiSerialClk_100MHz, - .sflashA1Size = 8u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0xEB, RADDR_SDR, - FLEXSPI_4PAD, 0x18), - FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, - 0x06, READ_SDR, - FLEXSPI_4PAD, 0x04), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 256u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ diff --git a/boards/arm/thingy52_nrf52832/CMakeLists.txt b/boards/arm/thingy52_nrf52832/CMakeLists.txt deleted file mode 100644 index 8faced7143824d..00000000000000 --- a/boards/arm/thingy52_nrf52832/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_CCS811) -zephyr_library() -zephyr_library_sources(board.c) -endif() diff --git a/boards/arm/thingy52_nrf52832/Kconfig b/boards/arm/thingy52_nrf52832/Kconfig deleted file mode 100644 index 318d486efefe2d..00000000000000 --- a/boards/arm/thingy52_nrf52832/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Thingy52 NRF52832 board configuration - -# Copyright (c) 2018 Aapo Vienamo -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_THINGY52_NRF52832 - -config BOARD_CCS_VDD_PWR_CTRL_INIT_PRIORITY - int "CCS_VDD power rail init priority" - default 85 - depends on GPIO_SX1509B - help - Initialization priority for the CCS_VDD power rail. This powers the - CCS811 gas sensor. The value has to be greater than - BOARD_VDD_PWR_CTRL_INIT_PRIORITY, but smaller than SENSOR_INIT_PRIORITY. - -endif # BOARD_THINGY52_NRF52832 diff --git a/boards/arm/thingy52_nrf52832/Kconfig.board b/boards/arm/thingy52_nrf52832/Kconfig.board deleted file mode 100644 index c369b95554bfbb..00000000000000 --- a/boards/arm/thingy52_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Thingy52 NRF52832 board configuration - -# Copyright (c) 2018 Aapo Vienamo -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_THINGY52_NRF52832 - bool "Thingy52 NRF52832" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/thingy52_nrf52832/Kconfig.defconfig b/boards/arm/thingy52_nrf52832/Kconfig.defconfig deleted file mode 100644 index d0002ec5e91c4b..00000000000000 --- a/boards/arm/thingy52_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Thingy52 NRF52832 board configuration - -# Copyright (c) 2018 Aapo Vienamo -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_THINGY52_NRF52832 - -config BOARD - default "thingy52_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_THINGY52_NRF52832 diff --git a/boards/arm/thingy52_nrf52832/doc/index.rst b/boards/arm/thingy52_nrf52832/doc/index.rst deleted file mode 100644 index f90d38a399aeb9..00000000000000 --- a/boards/arm/thingy52_nrf52832/doc/index.rst +++ /dev/null @@ -1,388 +0,0 @@ -.. _thingy52_nrf52832: - -Thingy:52 -######### - -Overview -******** - -Zephyr uses the thingy52_nrf52832 (PCA20020) board configuration for building -for the Thingy:52 board. The board has the nRF52832 MCU with ARM Cortex-M4F -processor, a set of environmental sensors, a pushbutton, and two RGB LEDs. - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* Gas sensor -* :abbr:`GPIO (General Purpose Input Output)` -* GPIO Expander -* Humidity and temperature sensor -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* Pressure sensor -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* RGB LEDs -* :abbr:`RTC (nRF RTC System Clock)` -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/thingy52_nrf52832.jpg - :align: center - :alt: nRF52 Thingy:52 - - nRF52 Thingy:52 (Credit: Nordic Semiconductor) - -More information about the board can be found at the `nRF52 DK website`_. The -`Nordic Semiconductor Infocenter`_ contains the processor's information and the -datasheet. - - -Hardware -******** - -Thingy:52 has the following features: - -* Two RGB LEDs -* CO2 and TVOC sensor -* Humidity and temperature sensor -* Color sensor -* I2C GPIO expander -* Provisions for a pin header and I2C and serial connectors -* Bluetooth radio - -Supported Features -================== - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| Gas | on-board | ccs811 | -| Sensor | | | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| GPIO Exp | on-board | sx1509b | -+-----------+------------+----------------------+ -| Humidity | on-board | hts221 | -| and Temp | | | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| Pressure | on-board | lps22hb_press | -| and Temp | | | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Connections and IOs -=================== - -Lightwell RGB LED ------------------ -The LED is driven by the SX1509B GPIO expander chip (device name GPIO_P0). - -+-------------------+-------------+ -| GPIO Expander Pin | LED Channel | -+===================+=============+ -| 5 | Green | -+-------------------+-------------+ -| 6 | Blue | -+-------------------+-------------+ -| 7 | Red | -+-------------------+-------------+ - -Button ------- - -Thingy:52 has a pushbutton, connected to the P0.11 SOC GPIO pin. - -Serial ------- - -By default the system UART has the following pin configuration: - -+---------+--------+ -| SOC Pin | Signal | -+=========+========+ -| P0.02 | TX | -+---------+--------+ -| P0.03 | RX | -+---------+--------+ - -The pins can be found on the P4 and P6 connectors. The system UART console -uses these pins by default. - -Internal I2C Bus ----------------- - -The internal I2C bus (I2C_0) is not routed to any of the external connectors, -but most of the on-board devices are accessed through it. The following pins -have been assigned to the bus: - -+---------+---------+ -| SOC Pin | Signal | -+=========+=========+ -| P0.07 | SDA | -+---------+---------+ -| P0.08 | SCL | -+---------+---------+ - -The following devices are attached to the bus. - -+----------+---------+ -| Device | Address | -+==========+=========+ -| SX1509B | 0x3e | -+----------+---------+ -| LPS22HB | 0x5c | -+----------+---------+ -| HTS221 | 0x5f | -+----------+---------+ -| CCS811 | 0x5a | -+----------+---------+ - -External I2C Bus ----------------- - -The external I2C bus (I2C_1) can be found on the P4 header and the P5 and P7 -connectors. - -+---------+---------+ -| SOC Pin | Signal | -+=========+=========+ -| P0.14 | SDA_EXT | -+---------+---------+ -| P0.15 | SCL_EXT | -+---------+---------+ - -Pin Header ----------- - -This is the pinout of the P4 pin header. Some of the SOC GPIO pins and I2C GPIO -expander pins are accessible through it. It also allows attaching external -devices to the four on-board N-channel MOSFET transistors. - -+-----+---------------+-----------------------+ -| Pin | Device | Signal / Device Pin | -+=====+===============+=======================+ -| 1 | SOC | SCL_EXT / P0.15 | -+-----+---------------+-----------------------+ -| 2 | SOC | SDA_EXT / P0.14 | -+-----+---------------+-----------------------+ -| 3 | SOC | ANA/DIG0 / P0.02 | -+-----+---------------+-----------------------+ -| 4 | SOC | ANA/DIG1 / P0.03 | -+-----+---------------+-----------------------+ -| 5 | SOC | ANA/DIG2 / P0.04 | -+-----+---------------+-----------------------+ -| 6 | | GND | -+-----+---------------+-----------------------+ -| 7 | GPIO Expander | Pin 0 | -+-----+---------------+-----------------------+ -| 8 | GPIO Expander | Pin 1 | -+-----+---------------+-----------------------+ -| 9 | GPIO Expander | Pin 2 | -+-----+---------------+-----------------------+ -| 10 | GPIO Expander | Pin 3 | -+-----+---------------+-----------------------+ -| 11 | MOSFET 1 | Drain | -+-----+---------------+-----------------------+ -| 12 | MOSFET 1 | Source | -+-----+---------------+-----------------------+ -| 13 | MOSFET 2 | Drain | -+-----+---------------+-----------------------+ -| 14 | MOSFET 2 | Source | -+-----+---------------+-----------------------+ -| 15 | MOSFET 3 | Drain | -+-----+---------------+-----------------------+ -| 16 | MOSFET 3 | Source | -+-----+---------------+-----------------------+ -| 17 | MOSFET 4 | Drain | -+-----+---------------+-----------------------+ -| 18 | MOSFET 4 | Source | -+-----+---------------+-----------------------+ -| 19 | | VDD | -+-----+---------------+-----------------------+ -| 20 | | GND | -+-----+---------------+-----------------------+ - -MOSFETs -~~~~~~~ - -The MOSFETs are attached to the following SOC GPIO pins: - -+----------+----------+ -| Device | Gate Pin | -+==========+==========+ -| MOSFET 1 | P0.18 | -+----------+----------+ -| MOSFET 2 | P0.19 | -+----------+----------+ -| MOSFET 3 | P0.20 | -+----------+----------+ -| MOSFET 4 | P0.21 | -+----------+----------+ - -Power Rails ------------ - -Thing:52 has multiple power rails. The necessary rails for the currently -supported devices are listed here. - -+---------+--------------+----------------------+ -| Name | Derived from | Controlled by | -+=========+==============+======================+ -| VREG | The battery | Always on | -+---------+--------------+----------------------+ -| VDD_nRF | VREG | Always on | -+---------+--------------+----------------------+ -| VDD | VREG | SOC pin P0.30 | -+---------+--------------+----------------------+ -| VDD_CCS | VDD | GPIO expander pin 10 | -+---------+--------------+----------------------+ - -Due to the dependencies of the power rails, multiple rails may need to be -powered for a given device to turn on. The correct order of powering up the -rails is the order of the rails down the dependency chain. For example, in order -to power the CCS811 gas sensor, VDD has to be turned on first and VDD_CCS after -it. Here's a list of the devices and their power rails: - -+----------+---------+ -| Device | Rail | -+==========+=========+ -| nRF52832 | VDD_nRF | -+----------+---------+ -| SX1509B | VDD | -+----------+---------+ -| LPS22HB | VDD | -+----------+---------+ -| HTS221 | VDD | -+----------+---------+ -| CCS811 | VDD_CCS | -+----------+---------+ - -Sensors -------- - -+----------+---------------------------------+-------+-------------+------------+ -| Device | Function | Bus | I2C Address | Power Rail | -+==========+=================================+=======+=============+============+ -| LPS22HB | Pressure and Temperature sensor | I2C_0 | 0x5c | VDD | -+----------+---------------------------------+-------+-------------+------------+ -| HTS221 | Humidity and Temperature sensor | I2C_0 | 0x5f | VDD | -+----------+---------------------------------+-------+-------------+------------+ -| CCS811 | Gas sensor | I2C_0 | 0x5a | VDD_CCS | -+----------+---------------------------------+-------+-------------+------------+ - -Misc. Device Pins ------------------ - -SX1509B -~~~~~~~ - -+---------------+-------------------+ -| Device Signal | SOC Pin | -+===============+===================+ -| SX_OSCIO | P0.05 | -+---------------+-------------------+ -| SX_RESET | P0.16 | -+---------------+-------------------+ - -LPS22HB -~~~~~~~ - -+---------------+-------------------+ -| Sensor Signal | SOC Pin | -+===============+===================+ -| LPS_INT | P0.23 | -+---------------+-------------------+ - -HTS221 -~~~~~~ - -+---------------+-------------------+ -| Sensor Signal | SOC Pin | -+===============+===================+ -| HTS_INT | P0.24 | -+---------------+-------------------+ - -CCS811 -~~~~~~ - -+---------------+-------------------+ -| Sensor Signal | GPIO Expander Pin | -+===============+===================+ -| CCS_RESET | 11 | -+---------------+-------------------+ -| CCS_WAKE | 12 | -+---------------+-------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Zephyr onto Thingy:52 requires an external J-Link programmer. The -programmer is attached to the P9 programming header. - - -Debugging -========= - -Thingy:52 does not have an on-board J-Link debug IC as some other nRF5 -development boards, however, instructions from the :ref:`nordic_segger` page -also apply to this board, with the additional step of connecting an external -debugger. A development board with a Debug out connector such as the -:ref:`nrf52dk_nrf52832` can be used as a debugger with Thingy:52. - -Testing board features -********************** - -The green lightwell LED can be tested with the :zephyr:code-sample:`blinky` example. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: thingy52_nrf52832 - :goals: build flash - - - -Also the temperature and humidity sensor can be tested with the :ref:`hts221` -sample. - -.. zephyr-app-commands:: - :zephyr-app: samples/sensor/hts221 - :board: thingy52_nrf52832 - :goals: build flash - -References -********** - -.. target-notes:: - -.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/Nordic-Thingy-52 -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832_defconfig b/boards/arm/thingy52_nrf52832/thingy52_nrf52832_defconfig deleted file mode 100644 index 2bdadf855de84b..00000000000000 --- a/boards/arm/thingy52_nrf52832/thingy52_nrf52832_defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_THINGY52_NRF52832=y - -# Enable regulators -CONFIG_REGULATOR=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable RTT -CONFIG_USE_SEGGER_RTT=y - -# enable regulators (init priority adjusted so that they -# are turned before I2C GPIO expander) -CONFIG_REGULATOR=y -CONFIG_REGULATOR_FIXED_INIT_PRIORITY=45 - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm/thingy53_nrf5340/CMakeLists.txt b/boards/arm/thingy53_nrf5340/CMakeLists.txt deleted file mode 100644 index 6a52022fad75e6..00000000000000 --- a/boards/arm/thingy53_nrf5340/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if (CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) - zephyr_library() - zephyr_library_sources(board.c) -endif() diff --git a/boards/arm/thingy53_nrf5340/Kconfig b/boards/arm/thingy53_nrf5340/Kconfig deleted file mode 100644 index 116fd1c8edb312..00000000000000 --- a/boards/arm/thingy53_nrf5340/Kconfig +++ /dev/null @@ -1,74 +0,0 @@ -# Thingy53 NRF5340 board configuration - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config THINGY53_INIT_PRIORITY - int "Init priority" - default 79 - help - Initialization priority of the Thingy:53. - -config MBOX_NRFX_IPC - default MBOX - -if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -config BOARD_ENABLE_DCDC_APP - bool "Application MCU DCDC converter" - select SOC_DCDC_NRF53X_APP - default y - -config BOARD_ENABLE_DCDC_NET - bool "Network MCU DCDC converter" - select SOC_DCDC_NRF53X_NET - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF53X_HV - default y - -config BOARD_SERIAL_BACKEND_CDC_ACM - bool "USB CDC" - default y - -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ - $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) - help - This option enables releasing the Network 'force off' signal, which - as a consequence will power up the Network MCU during system boot. - Additionally, the option allocates GPIO pins that will be used by UARTE - of the Network MCU. - Note: GPIO pin allocation can only be configured by the secure Application - MCU firmware, so when this option is used with the non-secure version of - the board, the application needs to take into consideration, that the - secure firmware image must already have configured GPIO allocation for the - Network MCU. - default y if (BT || NRF_802154_SER_HOST) - -config DOMAIN_CPUNET_BOARD - string - default "thingy53_nrf5340_cpunet" - depends on BOARD_ENABLE_CPUNET - help - The board which will be used for CPUNET domain when creating a multi - image application where one or more images should be located on - another board. For example hci_ipc on the nRF5340_cpunet for - Bluetooth applications. - -endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -if BOARD_THINGY53_NRF5340_CPUNET - -config DOMAIN_CPUAPP_BOARD - string - default "thingy53_nrf5340_cpuapp" - help - The board which will be used for CPUAPP domain when creating a multi - image application where one or more images should be located on - another board. - -endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/arm/thingy53_nrf5340/Kconfig.board b/boards/arm/thingy53_nrf5340/Kconfig.board deleted file mode 100644 index 0e472778a32a58..00000000000000 --- a/boards/arm/thingy53_nrf5340/Kconfig.board +++ /dev/null @@ -1,21 +0,0 @@ -# Thingy53 NRF5340 board configuration - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF5340_CPUAPP_QKAA - -config BOARD_THINGY53_NRF5340_CPUAPP - bool "Thingy53 nRF5340 Application MCU" - -config BOARD_THINGY53_NRF5340_CPUAPP_NS - bool "Thingy53 nRF5340 Application MCU non-secure" - -endif # SOC_NRF5340_CPUAPP_QKAA - -if SOC_NRF5340_CPUNET_QKAA - -config BOARD_THINGY53_NRF5340_CPUNET - bool "Thingy53 nRF5340 Network MCU" - -endif # SOC_NRF5340_CPUNET_QKAA diff --git a/boards/arm/thingy53_nrf5340/Kconfig.defconfig b/boards/arm/thingy53_nrf5340/Kconfig.defconfig deleted file mode 100644 index 12f1e5bbdc9b13..00000000000000 --- a/boards/arm/thingy53_nrf5340/Kconfig.defconfig +++ /dev/null @@ -1,152 +0,0 @@ -# Thingy53 NRF5340 board configuration - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -config BOARD - default "thingy53_nrf5340_cpuapp" - -# Code Partition: -# -# For the secure version of the board the firmware is linked at the beginning -# of the flash, or into the code-partition defined in DT if it is intended to -# be loaded by MCUboot. If the secure firmware is to be combined with a non- -# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always -# be restricted to the size of its code partition. -# -# For the non-secure version of the board, the firmware -# must be linked into the code-partition (non-secure) defined in DT, regardless. -# Apply this configuration below by setting the Kconfig symbols used by -# the linker according to the information extracted from DT partitions. - -# SRAM Partition: -# -# If the secure firmware is to be combined with a non-secure image -# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always -# be restricted to the secure image SRAM partition (sram-secure-partition). -# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram -# may be used by the image. -# -# For the non-secure version of the board, the firmware image SRAM is -# always restricted to the allocated non-secure SRAM partition. -# -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition -DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition - -if BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config SRAM_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) - -endif # BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE - -if BOARD_THINGY53_NRF5340_CPUAPP_NS - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -config FLASH_LOAD_SIZE - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) - -endif # BOARD_THINGY53_NRF5340_CPUAPP_NS - -if !TRUSTED_EXECUTION_SECURE - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC if BT -endchoice - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - -config BT_HAS_HCI_VS - default BT - -config USB_NRFX_ATTACHED_EVENT_DELAY - default 700 if USB_DEVICE_DRIVER - -config I2C - default y - -config SPI - default y - -config REGULATOR - default y - -endif # !TRUSTED_EXECUTION_SECURE - -if BOARD_SERIAL_BACKEND_CDC_ACM - -config USB_DEVICE_PRODUCT - default "Thingy:53 Application" - -config USB_DEVICE_VID - default 0x1915 - -config USB_DEVICE_PID - default 0x530C - -config USB_DEVICE_STACK - default y - -config USB_CDC_ACM - default y - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y if !MCUBOOT - -config SHELL_BACKEND_SERIAL_CHECK_DTR - default SHELL - depends on UART_LINE_CTRL - -config UART_LINE_CTRL - default SHELL - -config USB_DEVICE_REMOTE_WAKEUP - default n - -if LOG - -# Logger cannot use itself to log -choice USB_CDC_ACM_LOG_LEVEL_CHOICE - default USB_CDC_ACM_LOG_LEVEL_OFF -endchoice - -# Set USB log level to error only -choice USB_DEVICE_LOG_LEVEL_CHOICE - default USB_DEVICE_LOG_LEVEL_ERR -endchoice - -# Wait 4000ms at startup for logging -config LOG_PROCESS_THREAD_STARTUP_DELAY_MS - default 4000 - -endif # LOG - -endif # BOARD_SERIAL_BACKEND_CDC_ACM - -endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS - -if BOARD_THINGY53_NRF5340_CPUNET - -config BOARD - default "thingy53_nrf5340_cpunet" - -config BT_CTLR - default BT - -config BT_ECC - default BT - -endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/arm/thingy53_nrf5340/board.cmake b/boards/arm/thingy53_nrf5340/board.cmake deleted file mode 100644 index 75edf877f1043d..00000000000000 --- a/boards/arm/thingy53_nrf5340/board.cmake +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) -board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") -endif() - -if(CONFIG_BOARD_THINGY53_NRF5340_CPUNET) -board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") -endif() - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) -include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/thingy53_nrf5340/doc/index.rst b/boards/arm/thingy53_nrf5340/doc/index.rst deleted file mode 100644 index 4544ea7ed795d4..00000000000000 --- a/boards/arm/thingy53_nrf5340/doc/index.rst +++ /dev/null @@ -1,51 +0,0 @@ -.. _thingy53_nrf5340: - -Thingy:53 -######### - -Overview -******** - -Zephyr uses the thingy53_nrf5340 board configuration for building -for the Thingy:53 board. The board has the nRF5340 MCU processor, a set of -environmental sensors, a pushbutton, and RGB LED. - -The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: - -* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and - Armv8-M Security Extension, running at up to 128 MHz, referred to as - the **application core** -* a secondary Arm Cortex-M33 core, with a reduced feature set, running at - a fixed 64 MHz, referred to as the **network core**. - -The nrf5340dk_nrf5340_cpuapp build target provides support for the application -core on the nRF5340 SoC. The nrf5340dk_nrf5340_cpunet build target provides -support for the network core on the nRF5340 SoC. - -The `Nordic Semiconductor Infocenter`_ contains the processor's information and -the datasheet. - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Zephyr onto Thingy:53 requires an external J-Link programmer. The -programmer is attached to the P9 programming header. - -Debugging -========= - -Thingy:53 does not have an on-board J-Link debug IC as some other nRF5 -development boards, however, instructions from the :ref:`nordic_segger` page -also apply to this board, with the additional step of connecting an external -debugger. A development board with a Debug out connector such as the -:ref:`nrf5340dk_nrf5340` can be used as a debugger with Thingy:53. - -References -********** - -.. target-notes:: - -.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig b/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig deleted file mode 100644 index 33dc6fbdeddd86..00000000000000 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUNET_QKAA=y -CONFIG_BOARD_THINGY53_NRF5340_CPUNET=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# Enable GPIO -CONFIG_GPIO=y diff --git a/boards/arm/twr_ke18f/Kconfig.board b/boards/arm/twr_ke18f/Kconfig.board deleted file mode 100644 index 42713ad2c5f425..00000000000000 --- a/boards/arm/twr_ke18f/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# TWR-KE18F board configuration - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TWR_KE18F - bool "NXP TWR-KE18F" - depends on SOC_SERIES_KINETIS_KE1XF - select SOC_PART_NUMBER_MKE18F512VLL16 diff --git a/boards/arm/twr_ke18f/Kconfig.defconfig b/boards/arm/twr_ke18f/Kconfig.defconfig deleted file mode 100644 index ddf4f9274ebdeb..00000000000000 --- a/boards/arm/twr_ke18f/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# TWR-KE18F board - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TWR_KE18F - -config BOARD - default "twr_ke18f" - -config I2C_MCUX_LPI2C_BUS_RECOVERY - default y - depends on I2C_MCUX_LPI2C && PINCTRL - -# The KE1xF has 8 MPU regions, which is not enough for both HW stack protection -# and userspace. Only enable HW stack protection if userspace is not enabled. -config HW_STACK_PROTECTION - default y if !USERSPACE - -endif # BOARD_TWR_KE18F diff --git a/boards/arm/twr_ke18f/doc/index.rst b/boards/arm/twr_ke18f/doc/index.rst deleted file mode 100644 index 04aa94f0dfe73d..00000000000000 --- a/boards/arm/twr_ke18f/doc/index.rst +++ /dev/null @@ -1,254 +0,0 @@ -.. _twr_ke18f: - -NXP TWR-KE18F -############# - -Overview -******** - -The TWR-KE18F is a development board for NXP Kinetis KE1xF 32-bit -MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, -running an open source bootloader, offers options for serial -communication, flash programming, and run-control debugging. - -.. figure:: TWR-KE18F-DEVICE.jpg - :align: center - :alt: TWR-KE18F - - TWR-KE18F (Credit: NXP) - -Hardware -******** - -- MKE18F512VLL16 MCU (up to 168 MHz, 512 KB flash memory, 64 KB RAM, - and 100 Low profile Quad Flat Package (LQFP)) -- 3.3 V or 5 V MCU operation -- 6-axis FXOS8700CQ digital accelerometer and magnetometer -- RGB LED -- Four user LEDs -- Two user push-buttons -- Potentiometer -- Thermistor -- Infrared port (IrDA) -- CAN pin header -- Flex I/O pin header - -For more information about the KE1xF SoC and the TWR-KE18F board, see -these NXP reference documents: - -- `KE1xF Website`_ -- `KE1xF Datasheet`_ -- `KE1xF Reference Manual`_ -- `TWR-KE18F Website`_ -- `TWR-KE18F User Guide`_ -- `TWR-KE18F Schematics`_ - -Supported Features -================== - -The twr_ke18f board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| RTC | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | trigger supported with H/W mods | -| | | explained below; | -+-----------+------------+-------------------------------------+ -| SPI(M) | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| CAN | on-chip | can | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| ACMP | on-chip | analog comparator | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/twr_ke18f/twr_ke18f_defconfig``. - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The KE18 SoC is configured to use the 8 MHz external oscillator on the -board with the on-chip PLL to generate a 120 MHz system clock. - -Serial Port -=========== - -The KE18 SoC has three UARTs. UART0 is configured for the console. The -remaining UARTs are not used. - -Accelerometer and magnetometer -============================== - -The TWR-KE18F board by default only supports polling the FXOS8700 -accelerometer and magnetometer for sensor values -(``CONFIG_FXOS8700_TRIGGER_NONE=y``). - -In order to support FXOS8700 triggers (interrupts) the 0 ohm resistors -``R47`` and ``R57`` must be mounted on the TWR-KE18F board. The -devicetree must also be modified to describe the FXOS8700 interrupt -GPIOs: - -.. code-block:: devicetree - - /dts-v1/; - - &fxos8700 { - int1-gpios = <&gpioa 14 0>; - int2-gpios = <&gpioc 17 0>; - }; - -Finally, a trigger option must be enabled in Kconfig (either -``FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or -``FXOS8700_TRIGGER_OWN_THREAD=y``). - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. - -Early versions of this board have an outdated version of the OpenSDA bootloader -and require an update. Please see the `DAPLink Bootloader Update`_ page for -instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. - -Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) ------------------------------------------------------------------- - -Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program -the `OpenSDA DAPLink TWR-KE18F Firmware`_. - -Option 2: :ref:`opensda-jlink-onboard-debug-probe` --------------------------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program -the `OpenSDA J-Link Firmware for TWR-KE18F`_. - -Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and -``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the -default runner from pyOCD to J-Link: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_ke18f - :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink - :goals: build - -Configuring a Console -===================== - -Regardless of your choice in debug probe, we will use the OpenSDA -microcontroller as a usb-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J2. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_ke18f - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_ke18f - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_ke18f - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_ke18f - -.. _TWR-KE18F Website: - https://www.nxp.com/TWR-KE18F - -.. _TWR-KE18F User Guide: - https://www.nxp.com/docs/en/user-guide/TWRKE18FUG.pdf - -.. _TWR-KE18F Schematics: - https://www.nxp.com/webapp/Download?colCode=TWR-KE18F-SCH-DESIGNFILES - -.. _KE1xF Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/e-series5v-robustm0-plus-m4/kinetis-ke1xf-168mhz-performance-with-can-5v-microcontrollers-based-on-arm-cortex-m4:KE1xF - -.. _KE1xF Datasheet: - https://www.nxp.com/docs/en/data-sheet/KE1xFP100M168SF0.pdf - -.. _KE1xF Reference Manual: - https://www.nxp.com/docs/en/reference-manual/KE1xFP100M168SF0RM.pdf - -.. _DAPLink Bootloader Update: - https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ - -.. _OpenSDA DAPLink TWR-KE18F Firmware: - https://www.nxp.com/support/developer-resources/run-time-software/kinetis-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#TWR-KE18F - -.. _OpenSDA J-Link Firmware for TWR-KE18F: - https://www.segger.com/downloads/jlink/OpenSDA_TWR-KE18F diff --git a/boards/arm/twr_ke18f/twr_ke18f_defconfig b/boards/arm/twr_ke18f/twr_ke18f_defconfig deleted file mode 100644 index 05247818cabebd..00000000000000 --- a/boards/arm/twr_ke18f/twr_ke18f_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_KINETIS_KE1XF=y -CONFIG_SOC_MKE18F16=y -CONFIG_BOARD_TWR_KE18F=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y - -# Enable MPU -CONFIG_ARM_MPU=y diff --git a/boards/arm/twr_kv58f220m/Kconfig.board b/boards/arm/twr_kv58f220m/Kconfig.board deleted file mode 100644 index a5ee3947f3fcd8..00000000000000 --- a/boards/arm/twr_kv58f220m/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# TWR-KV58F220M board configuration - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TWR_KV58F220M - bool "NXP TWR-KV58F220M" - depends on SOC_SERIES_KINETIS_KV5X - select SOC_PART_NUMBER_MKV58F1M0VLQ24 diff --git a/boards/arm/twr_kv58f220m/Kconfig.defconfig b/boards/arm/twr_kv58f220m/Kconfig.defconfig deleted file mode 100644 index d9545c8762da5b..00000000000000 --- a/boards/arm/twr_kv58f220m/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# TWR-KV58F220M board - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TWR_KV58F220M - -config BOARD - default "twr_kv58f220m" - -config OSC_XTAL0_FREQ - default 50000000 - -config MCG_PRDIV0 - default 0x3 - -config MCG_VDIV0 - default 0x16 - -config MCG_FCRDIV - default 1 - -endif # BOARD_TWR_KV58F220M diff --git a/boards/arm/twr_kv58f220m/doc/index.rst b/boards/arm/twr_kv58f220m/doc/index.rst deleted file mode 100644 index f29129ecd76b78..00000000000000 --- a/boards/arm/twr_kv58f220m/doc/index.rst +++ /dev/null @@ -1,200 +0,0 @@ -.. _twr_kv58f220m: - -NXP TWR-KV58F220M -################# - -Overview -******** - -The TWR-KV58F220M is a development board for NXP Kinetis KV5x 32-bit -MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, -running an open source bootloader, offers options for serial -communication, flash programming, and run-control debugging. - -.. figure:: twr_kv58f220m.jpg - :align: center - :alt: TWR-KV58F220M - - TWR-KV58F220M (Credit: NXP) - -Hardware -******** - -- MKV58F1M0VLQ24 MCU (up to 240 MHz, 1 MB flash memory, 256 KB RAM, - and 144 Low profile Quad Flat Package (LQFP)) -- 1.8 V or 3.3 V MCU operation -- 6-axis FXOS8700CQ digital accelerometer and magnetometer -- Four user LEDs -- Four user push-buttons -- Potentiometer -- Two general purpose TWRPI headers -- Motor pin header - -For more information about the KV5x SoC and the TWR-KV58F220M board, see -these NXP reference documents: - -- `KV5x Website`_ -- `KV5x Datasheet`_ -- `KV5x Reference Manual`_ -- `TWR-KV58F220M Website`_ -- `TWR-KV58F220M User Guide`_ -- `TWR-KV58F220M Schematics`_ - -Supported Features -================== - -The twr_kv58f220m board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig``. - -Other hardware features are not currently supported by the port. - -System Clock -============ - -The KV58 SoC is configured to use the 50 MHz external oscillator on the -board with the on-chip PLL to generate a 237.5 MHz system clock. - -Serial Port -=========== - -The KV58 SoC has six UARTs. UART0 is configured for the console. The -remaining UARTs are not used. - -Accelerometer and magnetometer -============================== - -The TWR-KV58F220M board by default only supports polling the FXOS8700 -accelerometer and magnetometer for sensor values -(``CONFIG_FXOS8700_TRIGGER_NONE=y``). - -In order to support FXOS8700 triggers (interrupts), shunts must be placed on -the jumpers ``J2`` and ``J9``. A trigger option also must be enabled in Kconfig -(either ``CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or -``CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y``). - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -This board integrates an OpenSDA debug probe. However, it can currently only be -used for flashing the KV58 SoC by copying the compiled firmware to the USB Mass -Storage Device. The board cannot be debugged using the OpenSDA probe, since -pyOCD does not support the target. The OpenSDA J-Link firmware (as of release -2019-06-03) also cannot be used, since the flash algorithm for the KV58 seems to -be broken at the time of writing. - -An external J-Link debug probe connected to the JTAG header J13 is used to debug -the target. - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :tool: all - :board: twr_kv58f220m - :goals: build - -Configuring a Console -===================== - -Even though the OpenSDA probe cannot be used for debugging, we will use it as a -USB-to-serial adapter for the serial console. - -Connect a USB cable from your PC to J22. - -Use the following settings with your serial terminal of choice (minicom, putty, -etc.): - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_kv58f220m - :goals: flash - -Open a serial terminal, reset the board (press the SW1 button), and you should -see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_kv58f220m - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: twr_kv58f220m - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** - Hello World! twr_kv58f220m - -.. _TWR-KV58F220M Website: - https://www.nxp.com/TWR-KV58F220M - -.. _TWR-KV58F220M User Guide: - https://www.nxp.com/webapp/Download?colCode=TWRKV58F220MUG - -.. _TWR-KV58F220M Schematics: - https://www.nxp.com/webapp/Download?colCode=TWR-KV58F220M-SCH - -.. _KV5x Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/general-purpose-mcus/kv-series-cortex-m4-m0-plus-m7/kinetis-kv5x-240-mhz-motor-control-and-power-conversion-ethernet-mcus-based-on-arm-cortex-m7:KV5x - -.. _KV5x Datasheet: - https://www.nxp.com/docs/en/data-sheet/KV5XP144M240.pdf - -.. _KV5x Reference Manual: - https://www.nxp.com/webapp/Download?colCode=KV5XP144M240RM diff --git a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig b/boards/arm/ubx_bmd300eval_nrf52832/Kconfig deleted file mode 100644 index 5794811ba643e1..00000000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD300EVAL_NRF52832 diff --git a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.board b/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.board deleted file mode 100644 index cc5c009623b262..00000000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD300EVAL_NRF52832 - bool "u-blox BMD-300-EVAL" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.defconfig b/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.defconfig deleted file mode 100644 index 29b0576f3e1db2..00000000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD300EVAL_NRF52832 - -config BOARD - default "ubx_bmd300eval_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD300EVAL_NRF52832 diff --git a/boards/arm/ubx_bmd300eval_nrf52832/doc/index.rst b/boards/arm/ubx_bmd300eval_nrf52832/doc/index.rst deleted file mode 100644 index 4cf272153c05f4..00000000000000 --- a/boards/arm/ubx_bmd300eval_nrf52832/doc/index.rst +++ /dev/null @@ -1,397 +0,0 @@ -.. _ubx_bmd300eval_nrf52832: - -u-blox EVK-BMD-30/35: BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL -################################################################## - -Overview -******** - -The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL hardware provides -support for the u-blox BMD-300, BMD-301, and BMD-350 Bluetooth 5 -modules, based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F -CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-30-33-35-36-EVAL.jpg - :align: center - :alt: BMD-300-EVAL - - BMD-300-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share the same - pin headers and assignments. The boards are different only in - the module used on the board. The BMD-300 and BMD-301 modules - share the same footprint and differ only in the antenna. The - BMD-350 module utilizes the nRF52832 CIAA WLCSP package. - -More information about the BMD-300-EVAL, BMD-301-EVAL, and -BMD-350-EVAL and the respective modules can be found at the -`u-blox website`_. All of the Nordic Semiconductor examples for -the nRF52 DK (nrf52dk_nrf52832) may be used without modification. - -Hardware -******** - -The BMD-300/301/350 module on the board contains an internal -high-frequency oscillator at 32MHz. There is also a low frequency -(slow) oscillator of 32.768kHz. The module itself does not include -the slow crystal; however, the EVAL boards do. - -.. note:: - When targeting a custom design without a slow crystal, - be sure to modify code to utilize the internal RC - oscillator for the slow clock. - -Supported Features -================== - -The BMD-300/301/350-EVAL configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of -BMD-300/301/350-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.17 -* LED2 (red) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-300-eval_pin_out.jpg - :align: center - :alt: BMD-300-EVAL pin-out - - BMD-300-EVAL pin-out (Credit: u-blox AG) - -.. note:: - The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share - the same pin headers and assignments. - The BMD-300-EVAL is shown here. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-300/301/350-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 | -+-------+----------------+ -| 2 | P0.09 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.21 / RESET | -+-------+----------------+ -| 8 | P0.01 / XL2 | -+-------+----------------+ -| 9 | P0.00 / XL1 | -+-------+----------------+ -| 10 | GND | -+-------+----------------+ - - -Arduino Headers ---------------- - - -Power (J5) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | VSHLD | N/A | -+-------+--------------+---------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+---------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+---------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+---------------------------+ -| 5 | V5V | N/A | -+-------+--------------+---------------------------+ -| 6 | GND | N/A | -+-------+--------------+---------------------------+ -| 7 | GND | N/A | -+-------+--------------+---------------------------+ -| 8 | N/C | N/A | -+-------+--------------+---------------------------+ - - -Analog in (J8) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+---------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+---------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+---------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+---------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+---------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+---------------------------+ - - -Digital I/O (J7) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | D7 | P0.18/TRACEDATA[0]/SWO | -+-------+--------------+---------------------------+ -| 2 | D6 | P0.17 | -+-------+--------------+---------------------------+ -| 3 | D5 | P0.16/TRACEDATA[1] | -+-------+--------------+---------------------------+ -| 4 | D4 | P0.15/TRACEDATA[2] | -+-------+--------------+---------------------------+ -| 5 | D3 | P0.14/TRACEDATA[3] | -+-------+--------------+---------------------------+ -| 6 | D2 | P0.13 | -+-------+--------------+---------------------------+ -| 7 | D1 (TX) | P0.12 | -+-------+--------------+---------------------------+ -| 8 | D0 (RX) | P0.11 | -+-------+--------------+---------------------------+ - - -Digital I/O (J6) - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | SCL | P0.27 | -+-------+--------------+---------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+---------------------------+ -| 3 | AREF | P0.02/AIN0 | -+-------+--------------+---------------------------+ -| 4 | GND | N/A | -+-------+--------------+---------------------------+ -| 5 | D13 (SCK) | P0.25 | -+-------+--------------+---------------------------+ -| 6 | D12 (MISO) | P0.24 | -+-------+--------------+---------------------------+ -| 7 | D11 (MOSI) | P0.23 | -+-------+--------------+---------------------------+ -| 8 | D10 (SS) | P0.22 | -+-------+--------------+---------------------------+ -| 9 | D9 | P0.20/TRACECLK | -+-------+--------------+---------------------------+ -| 10 | D8 | P0.19 | -+-------+--------------+---------------------------+ - - -J11 - -+-------+--------------+---------------------------+ -| PIN # | Signal Name | BMD-300/301/350 Functions | -+=======+==============+===========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+---------------------------+ -| 2 | V5V | N/A | -+-------+--------------+---------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+---------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+---------------------------+ -| 5 | RESET | N/A | -+-------+--------------+---------------------------+ -| 6 | N/A | N/A | -+-------+--------------+---------------------------+ - - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the -BMD-300/301/350-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd300eval_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-330-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is -running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-3035-series-open-cpu diff --git a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig b/boards/arm/ubx_bmd330eval_nrf52810/Kconfig deleted file mode 100644 index cb7241f9b71cfc..00000000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# BMD-330-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD330EVAL_NRF52810 - -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT diff --git a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.board b/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.board deleted file mode 100644 index fa39a7e9bff2cd..00000000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-330-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD330EVAL_NRF52810 - bool "u-blox BMD-330-EVAL" - depends on SOC_NRF52810_QFAA diff --git a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.defconfig b/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.defconfig deleted file mode 100644 index 7168f408f393d7..00000000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# BMD-330-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD330EVAL_NRF52810 - -config BOARD - default "ubx_bmd330eval_nrf52810" - -endif # BOARD_UBX_BMD330EVAL_NRF52810 diff --git a/boards/arm/ubx_bmd330eval_nrf52810/doc/index.rst b/boards/arm/ubx_bmd330eval_nrf52810/doc/index.rst deleted file mode 100644 index 56ede10d98bcdb..00000000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/doc/index.rst +++ /dev/null @@ -1,388 +0,0 @@ -.. _ubx_bmd330eval_nrf52810: - -u-blox EVK-BMD-330: BMD-330-EVAL -################################ - -Overview -******** - -The BMD-330-EVAL hardware provides support for the -u-blox BMD-330 Bluetooth 5 module, based on The -Nordic Semiconductor nRF52810 ARM Cortex-M4 CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-30-33-35-36-EVAL.jpg - :align: center - :alt: BMD-300-EVAL - - BMD-300-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-330-EVAL shares the same pin headers and assignments as the - BMD-300-EVAL. The BMD-300-EVAL is shown here. - -More information about the BMD-330-EVAL and the BMD-330 module -can be found at the `u-blox website`_. All of the Nordic -Semiconductor examples for the nRF52 DK (nrf52dk_nrf52810) -may be used without modification. - -Hardware -******** - -The BMD-330 on the BMD-330-EVAL contains an internal -high-frequency oscillator at 32MHz. There is also a low frequency -(slow) oscillator of 32.768kHz. The BMD-330 itself does not include -the slow crystal; however, the BMD-330-EVAL does. - -.. note:: - When targeting a custom design without a slow crystal, - be sure to modify code to utilize the internal RC - oscillator for the slow clock. - -Supported Features -================== - -The BMD-330-EVAL configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of -BMD-330-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.17 -* LED2 (red) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-300-eval_pin_out.jpg - :align: center - :alt: BMD-300-EVAL pin-out - - BMD-300-EVAL pin-out (Credit: u-blox AG) - -.. note:: - The BMD-330-EVAL shares the same pin headers and assignments - as the BMD-300-EVAL. The BMD-300-EVAL is shown here. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-330-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 | -+-------+----------------+ -| 2 | P0.09 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.21 / RESET | -+-------+----------------+ -| 8 | P0.01 / XL2 | -+-------+----------------+ -| 9 | P0.00 / XL1 | -+-------+----------------+ -| 10 | GND | -+-------+----------------+ - - -Arduino Headers ---------------- - - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+----------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+============================+ -| 1 | D7 | P0.18 | -+-------+--------------+----------------------------+ -| 2 | D6 | P0.17 | -+-------+--------------+----------------------------+ -| 3 | D5 | P0.16 | -+-------+--------------+----------------------------+ -| 4 | D4 | P0.15 | -+-------+--------------+----------------------------+ -| 5 | D3 | P0.14 | -+-------+--------------+----------------------------+ -| 6 | D2 | P0.13 | -+-------+--------------+----------------------------+ -| 7 | D1 (TX) | P0.12 | -+-------+--------------+----------------------------+ -| 8 | D0 (RX) | P0.11 | -+-------+--------------+----------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P0.22 | -+-------+--------------+-------------------------+ -| 9 | D9 | P0.20 | -+-------+--------------+-------------------------+ -| 10 | D8 | P0.19 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-330 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the -BMD-330-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd330eval_nrf52810 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-330-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is -running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.dts`. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-330-open-cpu diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.yaml b/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.yaml deleted file mode 100644 index 3554db7451ff04..00000000000000 --- a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: ubx_bmd330eval_nrf52810 -name: UBX_BMD330EVAL_NRF52810 -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 24 -flash: 192 -supported: - - adc - - arduino_gpio - - arduino_i2c - - arduino_spi - - gpio - - counter - - nvs - - i2c - - pwm - - spi - - watchdog -vendor: u-blox diff --git a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig deleted file mode 100644 index 10df4b0cc46e22..00000000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD340EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.board b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.board deleted file mode 100644 index 538bd40ed3d06b..00000000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD340EVAL_NRF52840 - bool "u-blox BMD-340-EVAL" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig deleted file mode 100644 index f3113a62b3a6ea..00000000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD340EVAL_NRF52840 - -config BOARD - default "ubx_bmd340eval_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD340EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd340eval_nrf52840/doc/index.rst b/boards/arm/ubx_bmd340eval_nrf52840/doc/index.rst deleted file mode 100644 index 513f7dbdc8a637..00000000000000 --- a/boards/arm/ubx_bmd340eval_nrf52840/doc/index.rst +++ /dev/null @@ -1,521 +0,0 @@ -.. _ubx_bmd340eval_nrf52840: - -u-blox EVK-BMD-34/38: BMD-340-EVAL and BMD-341-EVAL -################################################### - -Overview -******** - -The BMD-340-EVAL and BMD-341-EVAL hardware provides support for the -u-blox BMD-340 and BMD-341 Bluetooth 5.0 modules, based on the -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. the BMD-340 and -BMD-341 are identical in operation except for the antenna. The -BMD-340 has a PCB antenna while the BMD-341 has a U.FL connector. -Both support the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-34-38-EVAL.jpg - :align: center - :alt: BMD-340-EVAL - - BMD-340-EVAL (Credit: u-blox AG) - -More information about the BMD-340-EVAL, BMD-340 module, BMD-341-EVAL, -and BMD-341 module can be found at the `u-blox website`_. -All of the Nordic Semiconductor examples for the nRF52840 DK -(nrf52840dk_nrf52840) may be used without modification. - -..note:: - The BMD-340 and BMD-341 are identical except for the antenna. - Throughout this board support package, the filenames utilize - the ubx_bmd340eval_nrf52840. - -Hardware -******** - -The BMD-340 on the BMD-340-EVAL (or BMD-341 on the BMD-341-EVAL) -contains an internal high-frequency oscillator at 32MHz. -There is also a low frequency (slow) oscillator of 32.768kHz. -The BMD-340 and BMD-341 do not include the slow crystal; -however, the BMD-340-EVAL and BMD-341-EVAL do. - -.. note:: - - When targeting a custom design without a slow crystal, be sure - to modify code to utilize the internal RC oscillator for the - slow clock. - -Supported Features -================== - -The BMD-340-EVAL and BMD-341-EVAL board configuration supports -the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of BMD-340-EVAL -and BMD-341-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.13 -* LED2 (red) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-340-eval_pin_out.jpg - :align: center - :alt: BMD-340-EVAL pin-out - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-340-EVAL or - BMD-341-EVAL for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Debug IN (J26) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | BMD-340_VCC | -+-------+----------------+ -| 2 | BMD-340_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | BMD-340_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | BMD-340_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | GND | -+-------+----------------+ -| 10 | BMD-340_RESET | -+-------+----------------+ - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 / NFC2 | -+-------+----------------+ -| 2 | P0.09 / NFC1 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.01 / XL2 | -+-------+----------------+ -| 8 | P0.00 / XL1 | -+-------+----------------+ - -Auxiliary (J10) - -+-------+-------------------+ -| PIN # | Signal Name | -+=======+===================+ -| 1 | P0.11 / TRACED[2] | -+-------+-------------------+ -| 2 | P0.12 / TRACED[1] | -+-------+-------------------+ -| 3 | P0.13 | -+-------+-------------------+ -| 4 | P0.14 | -+-------+-------------------+ -| 5 | P0.15 | -+-------+-------------------+ -| 6 | P0.16 | -+-------+-------------------+ -| 7 | P0.17 / QSPI_CS | -+-------+-------------------+ -| 8 | P0.18 / RESET | -+-------+-------------------+ -| 9 | P0.19 / QSPI_CLK | -+-------+-------------------+ -| 10 | P0.20 / QSPI_D0 | -+-------+-------------------+ -| 11 | P0.21 / QSPI_D1 | -+-------+-------------------+ -| 12 | P0.22 / QSPI_D2 | -+-------+-------------------+ -| 13 | P0.23 / QSPI_D3 | -+-------+-------------------+ -| 14 | P0.24 | -+-------+-------------------+ -| 15 | P0.25 | -+-------+-------------------+ -| 16 | P1.00 / TRACED[0] | -+-------+-------------------+ -| 17 | P1.09 / TRACED[3] | -+-------+-------------------+ -| 18 | No connection | -+-------+-------------------+ - -Arduino Headers ---------------- - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | D7 | P1.08 | -+-------+--------------+-------------------------+ -| 2 | D6 | P1.07 | -+-------+--------------+-------------------------+ -| 3 | D5 | P1.06 | -+-------+--------------+-------------------------+ -| 4 | D4 | P1.05 | -+-------+--------------+-------------------------+ -| 5 | D3 | P1.04 | -+-------+--------------+-------------------------+ -| 6 | D2 | P1.03 | -+-------+--------------+-------------------------+ -| 7 | D1 (TX) | P1.02 | -+-------+--------------+-------------------------+ -| 8 | D0 (RX) | P1.01 | -+-------+--------------+-------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P1.15 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P1.14 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P1.13 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P1.12 | -+-------+--------------+-------------------------+ -| 9 | D9 | P1.11 | -+-------+--------------+-------------------------+ -| 10 | D8 | P1.10 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-34x Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.15 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.13 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Applications for the BMD-340-EVAL and BMD-341-EVAL board -configurations can be built and flashed in the usual way -(see :ref:`build_an_application` and :ref:`application_run` -for more details); however, the standard debugging targets -are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BMD-340-EVAL -or BMD-341-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd340eval_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-340-EVAL and BMD-341-EVAL -***************************************************************** - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in -:zephyr_file:`boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your - application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is - used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app -main directory to be picked up automatically by the device tree -compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the BMD-340 at the `u-blox website`_, Section 2 -'Pin definition'. In the table 3 select the pins marked 'GPIO'. -Note that pins marked as 'Standard drive, low frequency I/O only -(<10 kH' can only be used in under-10KHz applications. -They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module - pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/docs/UBX-19033353 diff --git a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig deleted file mode 100644 index 5888e99eac4f2f..00000000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-345-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# Copyright (c) 2021 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -# No special configuration is required. -# The BMD-345 does not include DCDC components diff --git a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.board b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.board deleted file mode 100644 index 9f6b6acc0ebba7..00000000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# BMD-340-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# Copyright (c) 2021 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD345EVAL_NRF52840 - bool "u-blox BMD-345-EVAL" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig deleted file mode 100644 index e66bae50d86543..00000000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# BMD-345-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# Copyright (c) 2021 Linumiz -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD345EVAL_NRF52840 - -config BOARD - default "ubx_bmd345eval_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD345EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd345eval_nrf52840/doc/index.rst b/boards/arm/ubx_bmd345eval_nrf52840/doc/index.rst deleted file mode 100644 index 7404ebd9053594..00000000000000 --- a/boards/arm/ubx_bmd345eval_nrf52840/doc/index.rst +++ /dev/null @@ -1,533 +0,0 @@ -.. _ubx_bmd345eval_nrf52840: - -u-blox EVK-BMD-34/38: BMD-345-EVAL -################################## - -Overview -******** - -The BMD-345-EVALhardware provides support for the u-blox BMD-345 -Bluetooth 5.0 modules, based on the Nordic Semiconductor nRF52840 -ARM Cortex-M4F CPU and Skyworks RFX2411 Front End Module (FEM), -also known as a Power Amplifier / Low Noise Amplifier (PA/LNA). -Both support the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/bmd-345-eval_features.jpg - :align: center - :alt: BMD 345 EVAL - - BMD-345-EVAL (Credit: ublox AG) - -More information about the BMD-345-EVAL and BMD-345 module can be -found at the `u-blox website`_. - - -Hardware -******** - -The BMD-345 on the BMD-345-EVAL contains an internal high-frequency -oscillator at 32MHz. There is also a low frequency (slow) -oscillator of 32.768kHz. The BMD-345 does not include the slow -crystal; however, the BMD-345-EVAL does. - -.. note:: - - When targeting a custom design without a slow crystal, be sure - to modify code to utilize the internal RC oscillator for the - slow clock. - -Front End Module -================ - -BMD-345 utilizes the Skyworks RFX2411 front end module (FEM). -The FEM provides higher output power and better sensitivity. - -FEM pin assignments -------------------- - -+-------------+--------------+----------+--------+----------+---------+ -| GPIO Number | Signal Name | Shutdown | Bypass | Transmit | Receive | -+=============+==============+==========+========+==========+=========+ -| P1.05 | TX_EN | Low | Low | High | Low | -+-------------+--------------+----------+--------+----------+---------+ -| P1.06 | RX_EN | Low | Low | Low | High | -+-------------+--------------+----------+--------+----------+---------+ -| P1.04 | MODE | Low | High | Low | Low | -+-------------+--------------+----------+--------+----------+---------+ -| P1.02 | A_SEL | Low | Low | Low | Low | -+-------------+--------------+----------+--------+----------+---------+ - -Supported Features -================== - -The BMD-345-EVAL board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of BMD-345-EVAL -hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.13 -* LED2 (red) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-345-eval_pin_out.jpg - :align: center - :alt: BMD-345-EVAL pin-out - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-340-EVAL or - BMD-341-EVAL for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Debug IN (J26) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | BMD-340_VCC | -+-------+----------------+ -| 2 | BMD-340_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | BMD-340_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | BMD-340_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | GND | -+-------+----------------+ -| 10 | BMD-340_RESET | -+-------+----------------+ - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 / NFC2 | -+-------+----------------+ -| 2 | P0.09 / NFC1 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.01 / XL2 | -+-------+----------------+ -| 8 | P0.00 / XL1 | -+-------+----------------+ - -Auxiliary (J10) - -+-------+-------------------+ -| PIN # | Signal Name | -+=======+===================+ -| 1 | P0.11 / TRACED[2] | -+-------+-------------------+ -| 2 | P0.12 / TRACED[1] | -+-------+-------------------+ -| 3 | P0.13 | -+-------+-------------------+ -| 4 | P0.14 | -+-------+-------------------+ -| 5 | P0.15 | -+-------+-------------------+ -| 6 | P0.16 | -+-------+-------------------+ -| 7 | P0.17 / QSPI_CS | -+-------+-------------------+ -| 8 | P0.18 / RESET | -+-------+-------------------+ -| 9 | P0.19 / QSPI_CLK | -+-------+-------------------+ -| 10 | P0.20 / QSPI_D0 | -+-------+-------------------+ -| 11 | P0.21 / QSPI_D1 | -+-------+-------------------+ -| 12 | P0.22 / QSPI_D2 | -+-------+-------------------+ -| 13 | P0.23 / QSPI_D3 | -+-------+-------------------+ -| 14 | P0.24 | -+-------+-------------------+ -| 15 | P0.25 | -+-------+-------------------+ -| 16 | P1.00 / TRACED[0] | -+-------+-------------------+ -| 17 | P1.09 / TRACED[3] | -+-------+-------------------+ -| 18 | No connection | -+-------+-------------------+ - -Arduino Headers ---------------- - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | D7 | P1.08 | -+-------+--------------+-------------------------+ -| 2 | D6 | P1.07 | -+-------+--------------+-------------------------+ -| 3 | N/C | N/A | -+-------+--------------+-------------------------+ -| 4 | N/C | N/A | -+-------+--------------+-------------------------+ -| 5 | N/C | N/A | -+-------+--------------+-------------------------+ -| 6 | D2 | P1.03 | -+-------+--------------+-------------------------+ -| 7 | N/C | N/A | -+-------+--------------+-------------------------+ -| 8 | D0 (RX) | P1.01 | -+-------+--------------+-------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P1.15 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P1.14 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P1.13 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P1.12 | -+-------+--------------+-------------------------+ -| 9 | D9 | P1.11 | -+-------+--------------+-------------------------+ -| 10 | D8 | P1.10 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-345 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.15 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.13 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Applications for the BMD-345-EVAL board -configurations can be built and flashed in the usual way -(see :ref:`build_an_application` and :ref:`application_run` -for more details); however, the standard debugging targets -are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BMD-345-EVAL -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd345eval_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-345-EVAL -***************************************************************** - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in -:zephyr_file:`boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd345eval_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your - application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is - used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app -main directory to be picked up automatically by the device tree -compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the BMD-345 at the `u-blox website`_, Section 2 -'Pin definition'. In the table 3 select the pins marked 'GPIO'. -Note that pins marked as 'Standard drive, low frequency I/O only -(<10 kH' can only be used in under-10KHz applications. -They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module - pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-34-series-open-cpu diff --git a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig b/boards/arm/ubx_bmd360eval_nrf52811/Kconfig deleted file mode 100644 index 53882dd3930da6..00000000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-360-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_BMD360EVAL_NRF52811 -# BT_CTLR depends on BT. When BT is enabled we should default to also -# enabling the controller. -config BT_CTLR - default y if BT diff --git a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.board b/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.board deleted file mode 100644 index b041fc6a2c77d6..00000000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# BMD-360-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD360EVAL_NRF52811 - bool "u-blox BMD-360-EVAL" - depends on SOC_NRF52811_QFAA diff --git a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.defconfig b/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.defconfig deleted file mode 100644 index a604bf98cd4932..00000000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# BMD-360-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD360EVAL_NRF52811 - -config BOARD - default "ubx_bmd360eval_nrf52811" - -endif # BOARD_UBX_BMD360EVAL_NRF52811 diff --git a/boards/arm/ubx_bmd360eval_nrf52811/doc/index.rst b/boards/arm/ubx_bmd360eval_nrf52811/doc/index.rst deleted file mode 100644 index c81d8b4ab7ebe2..00000000000000 --- a/boards/arm/ubx_bmd360eval_nrf52811/doc/index.rst +++ /dev/null @@ -1,386 +0,0 @@ -.. _ubx_bmd360eval_nrf52811: - -u-blox EVK-BMD-360: BMD-360-EVAL -################################ - -Overview -******** - -The BMD-360-EVAL hardware provides support for the -u-blox BMD-360 Bluetooth 5 module, based on The -Nordic Semiconductor nRF52811 ARM Cortex-M4 CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-30-33-35-36-EVAL.jpg - :align: center - :alt: BMD-300-EVAL - - BMD-300-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-360-EVAL shares the same pin headers and assignments as the - BMD-300-EVAL. The BMD-300-EVAL is shown here. - -More information about the BMD-360-EVAL and the BMD-360 module -can be found at the `u-blox website`_. - -Hardware -******** - -The BMD-360 on the BMD-360-EVAL contains an internal -high-frequency oscillator at 32MHz. There is also a low frequency -(slow) oscillator of 32.768kHz. The BMD-360 itself does not include -the slow crystal; however, the BMD-360-EVAL does. - -.. note:: - When targeting a custom design without a slow crystal, - be sure to modify code to utilize the internal RC - oscillator for the slow clock. - -Supported Features -================== - -The BMD-360-EVAL configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of -BMD-360-EVAL hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.17 -* LED2 (red) = P0.18 -* LED3 (green) = P0.19 -* LED4 (green) = P0.20 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.13 -* BUTTON2 = SW2 = P0.14 -* BUTTON3 = SW3 = P0.15 -* BUTTON4 = SW4 = P0.16 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-300-eval_pin_out.jpg - :align: center - :alt: BMD-300-EVAL pin-out - - BMD-300-EVAL pin-out (Credit: u-blox AG) - -.. note:: - The BMD-360-EVAL shares the same pin headers and assignments - as the BMD-300-EVAL. The BMD-300-EVAL is shown here. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-360-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 | -+-------+----------------+ -| 2 | P0.09 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.21 / RESET | -+-------+----------------+ -| 8 | P0.01 / XL2 | -+-------+----------------+ -| 9 | P0.00 / XL1 | -+-------+----------------+ -| 10 | GND | -+-------+----------------+ - - -Arduino Headers ---------------- - - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.21 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+----------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+============================+ -| 1 | D7 | P0.18 | -+-------+--------------+----------------------------+ -| 2 | D6 | P0.17 | -+-------+--------------+----------------------------+ -| 3 | D5 | P0.16 | -+-------+--------------+----------------------------+ -| 4 | D4 | P0.15 | -+-------+--------------+----------------------------+ -| 5 | D3 | P0.14 | -+-------+--------------+----------------------------+ -| 6 | D2 | P0.13 | -+-------+--------------+----------------------------+ -| 7 | D1 (TX) | P0.12 | -+-------+--------------+----------------------------+ -| 8 | D0 (RX) | P0.11 | -+-------+--------------+----------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P0.22 | -+-------+--------------+-------------------------+ -| 9 | D9 | P0.20 | -+-------+--------------+-------------------------+ -| 10 | D8 | P0.19 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-360 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.24 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.25 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.23 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the -BMD-360-EVAL can be found. For example, under Linux, -:code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd360eval_nrf52811 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-360-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is -running correctly on your board. The button and LED definitions -can be found in :zephyr_file:`boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.dts`. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/bmd-360-open-cpu diff --git a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig deleted file mode 100644 index 2620c816acb8dd..00000000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# BMD-380-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC -bool "DCDC mode" -select SOC_DCDC_NRF52X -default y -depends on BOARD_UBX_BMD380EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.board b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.board deleted file mode 100644 index e930b4d4ac4334..00000000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.board +++ /dev/null @@ -1,11 +0,0 @@ -# BMD-380-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_BMD380EVAL_NRF52840 - bool "u-blox BMD-380-EVAL" - depends on SOC_NRF52840_QIAA - -# should be CKAA, -# but SOC file not yet available from Nordic Semiconductor diff --git a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig b/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig deleted file mode 100644 index b77590a1fdd8ff..00000000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# BMD-380-EVAL board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_BMD380EVAL_NRF52840 - -config BOARD - default "ubx_bmd380eval_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_BMD380EVAL_NRF52840 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/doc/index.rst b/boards/arm/ubx_bmd380eval_nrf52840/doc/index.rst deleted file mode 100644 index e76334dd96a753..00000000000000 --- a/boards/arm/ubx_bmd380eval_nrf52840/doc/index.rst +++ /dev/null @@ -1,519 +0,0 @@ -.. _ubx_bmd380eval_nrf52840: - -u-blox EVK-BMD-34/48: BMD-380-EVAL -################################## - -Overview -******** - -The BMD-380-EVAL hardware provides support for the -u-blox BMD-380 Bluetooth 5.0 module, based on The -Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/BMD-34-38-EVAL.jpg - :align: center - :alt: BMD-340-EVAL - - BMD-340-EVAL (Credit: u-blox AG) - -.. note:: - The BMD-380-EVAL shares the same pin headers and assignments as the - BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. - See the pin tables below for the exceptions. - -More information about the BMD-340-EVAL and the BMD-340 module -can be found at the `u-blox website`_. All of the Nordic Semiconductor -examples for the nRF52840 DK (nrf52840dk_nrf52840) may be used without -modification. - -Hardware -******** - -The BMD-380 on the BMD-380-EVAL contains an internal high-frequency -oscillator at 32MHz. There is also a low frequency (slow) oscillator -of 32.768kHz. The BMD-380 itself does not include the slow crystal; -however, the BMD-380-eval does. - -.. note:: - - When targeting a custom design without a slow crystal, be sure - to modify code to utilize the internal RC oscillator for the - slow clock. - -Supported Features -================== - -The BMD-380-EVAL board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of BMD-380-EVAL -hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED1 (red) = P0.13 -* LED2 (red) = P0.14 -* LED3 (green) = P0.15 -* LED4 (green) = P0.16 -* D5 (red) = OB LED 1 -* D6 (green) = OB LED 2 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.11 -* BUTTON2 = SW2 = P0.12 -* BUTTON3 = SW3 = P0.24 -* BUTTON4 = SW4 = P0.25 -* BOOT = SW5 = boot/reset - -External Connectors -------------------- - -.. figure:: img/bmd-340-eval_pin_out.jpg - :align: center - :alt: BMD-340-EVAL pin-out - -.. note:: - The BMD-380-EVAL shares the same pin headers and assignments as the - BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. - See the pin tables below for the exceptions. - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the BMD-380-EVAL - for each header - -J-Link Prog Connector (J2) - -+-------+--------------+ -| PIN # | Signal Name | -+=======+==============+ -| 1 | VDD | -+-------+--------------+ -| 2 | IMCU_TMSS | -+-------+--------------+ -| 3 | GND | -+-------+--------------+ -| 4 | IMCU_TCKS | -+-------+--------------+ -| 5 | V5V | -+-------+--------------+ -| 6 | IMCU_TDOS | -+-------+--------------+ -| 7 | Cut off | -+-------+--------------+ -| 8 | IMCU_TDIS | -+-------+--------------+ -| 9 | Cut off | -+-------+--------------+ -| 10 | IMCU_RESET | -+-------+--------------+ - -Debug OUT (J3) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | EXT_VTG | -+-------+----------------+ -| 2 | EXT_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | EXT_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | EXT_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | EXT_GND_DETECT | -+-------+----------------+ -| 10 | EXT_RESET | -+-------+----------------+ - -Debug IN (J26) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | BMD-340_VCC | -+-------+----------------+ -| 2 | BMD-340_SWDIO | -+-------+----------------+ -| 3 | GND | -+-------+----------------+ -| 4 | BMD-340_SWDCLK | -+-------+----------------+ -| 5 | GND | -+-------+----------------+ -| 6 | BMD-340_SWO | -+-------+----------------+ -| 7 | N/C | -+-------+----------------+ -| 8 | N/C | -+-------+----------------+ -| 9 | GND | -+-------+----------------+ -| 10 | BMD-340_RESET | -+-------+----------------+ - -Auxiliary (J9) - -+-------+----------------+ -| PIN # | Signal Name | -+=======+================+ -| 1 | P0.10 / NFC2 | -+-------+----------------+ -| 2 | P0.09 / NFC1 | -+-------+----------------+ -| 3 | P0.08 | -+-------+----------------+ -| 4 | P0.07 | -+-------+----------------+ -| 5 | P0.06 | -+-------+----------------+ -| 6 | P0.05 / AIN3 | -+-------+----------------+ -| 7 | P0.01 / XL2 | -+-------+----------------+ -| 8 | P0.00 / XL1 | -+-------+----------------+ - -Auxiliary (J10) - -+-------+-------------------+ -| PIN # | Signal Name | -+=======+===================+ -| 1 | P0.11 / TRACED[2] | -+-------+-------------------+ -| 2 | P0.12 / TRACED[1] | -+-------+-------------------+ -| 3 | P0.13 | -+-------+-------------------+ -| 4 | P0.14 | -+-------+-------------------+ -| 5 | P0.15 | -+-------+-------------------+ -| 6 | P0.16 | -+-------+-------------------+ -| 7 | P0.17 / QSPI_CS | -+-------+-------------------+ -| 8 | P0.18 / RESET | -+-------+-------------------+ -| 9 | P0.19 / QSPI_CLK | -+-------+-------------------+ -| 10 | P0.20 / QSPI_D0 | -+-------+-------------------+ -| 11 | P0.21 / QSPI_D1 | -+-------+-------------------+ -| 12 | P0.22 / QSPI_D2 | -+-------+-------------------+ -| 13 | P0.23 / QSPI_D3 | -+-------+-------------------+ -| 14 | P0.24 | -+-------+-------------------+ -| 15 | P0.25 | -+-------+-------------------+ -| 16 | P1.00 / TRACED[0] | -+-------+-------------------+ -| 17 | P1.09 / TRACED[3] | -+-------+-------------------+ -| 18 | No connection | -+-------+-------------------+ - -Power (J5) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 2 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | VSHLD | N/A | -+-------+--------------+-------------------------+ -| 5 | V5V | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ - -Analog in (J8) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.29 / AIN5 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.31 / AIN7 | -+-------+--------------+-------------------------+ - -Digital I/O (J7) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | D7 | P1.08 | -+-------+--------------+-------------------------+ -| 2 | - | No connection | -+-------+--------------+-------------------------+ -| 3 | D5 | P1.06 | -+-------+--------------+-------------------------+ -| 4 | D4 | No connection | -+-------+--------------+-------------------------+ -| 5 | - | No connection | -+-------+--------------+-------------------------+ -| 6 | - | No connection | -+-------+--------------+-------------------------+ -| 7 | D1 (TX) | P1.02 | -+-------+--------------+-------------------------+ -| 8 | - | No connection | -+-------+--------------+-------------------------+ - -Digital I/O (J6) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | SCL | P0.27 | -+-------+--------------+-------------------------+ -| 2 | SDA | P0.26 | -+-------+--------------+-------------------------+ -| 3 | AREF | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 4 | GND | N/A | -+-------+--------------+-------------------------+ -| 5 | D13 (SCK) | P1.15 | -+-------+--------------+-------------------------+ -| 6 | D12 (MISO) | P1.14 | -+-------+--------------+-------------------------+ -| 7 | D11 (MOSI) | P1.13 | -+-------+--------------+-------------------------+ -| 8 | D10 (SS) | P1.12 | -+-------+--------------+-------------------------+ -| 9 | D9 | P1.11 | -+-------+--------------+-------------------------+ -| 10 | D8 | P1.10 | -+-------+--------------+-------------------------+ - -J11 - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | BMD-380 Functions | -+=======+==============+=========================+ -| 1 | D12 (MISO) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | V5V | N/A | -+-------+--------------+-------------------------+ -| 3 | D13 (SCK) | P0.15 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.13 | -+-------+--------------+-------------------------+ -| 5 | RESET | N/A | -+-------+--------------+-------------------------+ -| 6 | N/A | N/A | -+-------+--------------+-------------------------+ - -Programming and Debugging -************************* - -Applications for the BMD-380-EVAL board configurations can -be built and flashed in the usual way -(see :ref:`build_an_application` and :ref:`application_run` -for more details); however, the standard debugging targets -are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the BMD-380-EVAL -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_bmd380eval_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the BMD-380-EVAL -************************************************ - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found -in -:zephyr_file:`boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your - application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is - used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app -main directory to be picked up automatically by the device tree -compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the BMD-380 at the `u-blox website`_, Section 2 -'Pin definition'. In the table 3 select the pins marked 'GPIO'. -Note that pins marked as 'Standard drive, low frequency I/O only -(<10 kH' can only be used in under-10KHz applications. -They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module - pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/docs/UBX-19039467 diff --git a/boards/arm/ubx_evkannab1_nrf52832/Kconfig b/boards/arm/ubx_evkannab1_nrf52832/Kconfig deleted file mode 100644 index 3effcbce4e4180..00000000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# u-blox EVK-ANNA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKANNAB1_NRF52832 diff --git a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.board b/boards/arm/ubx_evkannab1_nrf52832/Kconfig.board deleted file mode 100644 index 81a8fb291ba77e..00000000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# u-blox EVK-ANNA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKANNAB1_NRF52832 - bool "u-blox EVK-ANNA-B1" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.defconfig b/boards/arm/ubx_evkannab1_nrf52832/Kconfig.defconfig deleted file mode 100644 index eaac8eb95d998c..00000000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# u-blox EVK-ANNA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKANNAB1_NRF52832 - -config BOARD - default "ubx_evkannab1_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKANNAB1_NRF52832 diff --git a/boards/arm/ubx_evkannab1_nrf52832/doc/index.rst b/boards/arm/ubx_evkannab1_nrf52832/doc/index.rst deleted file mode 100644 index 8a4702f331c174..00000000000000 --- a/boards/arm/ubx_evkannab1_nrf52832/doc/index.rst +++ /dev/null @@ -1,169 +0,0 @@ -.. _ubx_evkannab1_nrf52832: - -u-blox EVK-ANNA-B11x -#################### - -Overview -******** - -The u-blox ANNA-B1 Evaluation Kit hardware is a Bluetooth low energy -module based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU -and has support for the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-ANNA-B112.jpg - - EVK ANNA-B1 - -More information about the ANNA-B1 module and the EVK-ANNA-B1 -can be found at `ANNA-B1 product page`_ and -`EVK-ANNA-B1 product page`_. - -Supported Features -================== - -The ubx_evkannab1_nrf52832 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth Low Energy | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `EVK-ANNA-B1 product page`_ and `ANNA-B1 Data Sheet`_ -for a complete list of EVK ANNA-B1 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.27 -* LED1 (green) = P0.25 -* LED2 (blue) = P0.26 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.25 -* BUTTON2 = SW2 = P0.24 - -General information on module pin numbering -------------------------------------------- - -The numbering of the pins on the module and EVK do not follow the GPIO -numbering on the nRF52832 SoC. Please see the `ANNA-B1 Data Sheet`_ for -information on how to map ANNA-B1 pins to the pin numbering on the -nRF52832 SoC. - -The reason for this is the u-blox module family concept where different -modules share the same pinout and can be interchanged. - -Programming and Debugging -************************* - -Applications for the ``ubx_evkannab1_nrf52832`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Build and flash applications as usual (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Open a terminal program to the USB Serial Port installed when connecting -the board and listen for output. - -Settings: 115200, 8N1, no flow control. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evkannab1_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging boards -containing a Nordic Semiconductor chip with a Segger IC. - - -Testing the LEDs and buttons in the EVK NINA-B11x -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) -and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.dts`. - -Note that the buttons on the EVK-ANNA-B1 are marked SW1 and SW2, which -are named sw0 and sw1 in the dts file. -Also note that the SW1 button and the green LED are connected on HW level. - - -References -********** - -.. target-notes:: - -.. _ANNA-B1 product page: https://www.u-blox.com/en/product/anna-b112-open-cpu -.. _EVK-ANNA-B1 product page: https://www.u-blox.com/en/product/evk-anna-b112 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _ANNA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-18011707 diff --git a/boards/arm/ubx_evkninab1_nrf52832/Kconfig b/boards/arm/ubx_evkninab1_nrf52832/Kconfig deleted file mode 100644 index a55e5f969341eb..00000000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# u-blox EVK NINA-B1 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB1_NRF52832 diff --git a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.board b/boards/arm/ubx_evkninab1_nrf52832/Kconfig.board deleted file mode 100644 index e97367f358c3a9..00000000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# u-blox EVK-NINA-B1 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKNINAB1_NRF52832 - bool "u-blox EVK-NINA-B1" - depends on SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.defconfig b/boards/arm/ubx_evkninab1_nrf52832/Kconfig.defconfig deleted file mode 100644 index 408147057d14da..00000000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# u-blox EVK-NINA-B1 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKNINAB1_NRF52832 - -config BOARD - default "ubx_evkninab1_nrf52832" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKNINAB1_NRF52832 diff --git a/boards/arm/ubx_evkninab1_nrf52832/doc/index.rst b/boards/arm/ubx_evkninab1_nrf52832/doc/index.rst deleted file mode 100644 index 666fdce7e5c442..00000000000000 --- a/boards/arm/ubx_evkninab1_nrf52832/doc/index.rst +++ /dev/null @@ -1,178 +0,0 @@ -.. _ubx_evkninab1_nrf52832: - -u-blox EVK NINA-B11x -#################### - -Overview -******** - -The u-blox NINA-B1 Evaluation Kit hardware is a Bluetooth -low energy module based on the Nordic Semiconductor nRF52832 -ARM Cortex-M4F CPU and has support for the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-NINA-B1.jpg - - EVK NINA-B1 - -More information about the NINA-B1 module and the EVK NINA-B1 -can be found at `NINA-B1 product page`_ and -`EVK-NINA-B1 product page`_. - -Supported Features -================== - -The ubx_evkninab1_nrf52832 board configuration supports the -following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth Low Energy | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -.. note:: - Most Arduino interfaces are supported. Arduino pins - D5 and D8 are not available, so arduino_gpio is - disabled. On the EVK-NINA-B1, these pins are - assigned to SWDIO and SWDCLK, respectively. - -Other hardware features have not been enabled yet for this board. -See `EVK-NINA-B1 product page`_ and `NINA-B1 Data Sheet`_ -for a complete list of EVK NINA-B1 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.08 -* LED1 (green) = P0.16 -* LED2 (blue) = P0.18 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.16 -* BUTTON2 = SW2 = P0.30 - - -General information on module pin numbering -------------------------------------------- - -The numbering of the pins on the module and EVK do not follow the GPIO -numbering on the nRF52832 SoC. Please see the `NINA-B1 Data Sheet`_ for -information on how to map NINA-B1 pins to the pin numbering on the -nRF52832 SoC. - -The reason for this is the u-blox module family concept where different -modules share the same pinout and can be interchanged, see -`NINA module family Nested design`_. - -Programming and Debugging -************************* - -Applications for the ``ubx_evkninab1_nrf52832`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Build and flash applications as usual (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -Open a terminal program to the USB Serial Port installed when connecting -the board and listen for output. - -Settings: 115200, 8N1, no flow control. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evkninab1_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging boards -containing a Nordic Semiconductor chip with a Segger IC. - - -Testing the LEDs and buttons in the EVK NINA-B11x -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) -and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.dts`. - -Note that the buttons on the EVK-NINA-B1 are marked SW1 and SW2, which -are named sw0 and sw1 in the dts file. -Also note that the SW1 button and the green LED are connected on HW level. - - -References -********** - -.. target-notes:: - -.. _NINA-B1 product page: https://www.u-blox.com/en/product/nina-b1-series-open-cpu -.. _EVK-NINA-B1 product page: https://www.u-blox.com/en/product/evk-nina-b1 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _NINA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-15019243 -.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ubx_evkninab3_nrf52840/Kconfig b/boards/arm/ubx_evkninab3_nrf52840/Kconfig deleted file mode 100644 index ca405a90b695cd..00000000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# EVK-NINA-B3 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB3_NRF52840 diff --git a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.board b/boards/arm/ubx_evkninab3_nrf52840/Kconfig.board deleted file mode 100644 index ee5b2dc98b992c..00000000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# EVK-NINA-B3 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKNINAB3_NRF52840 - bool "u-blox EVK-NINA-B3" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig b/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig deleted file mode 100644 index e28e100e9fc2f6..00000000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# EVK-NINA-B3 board configuration - -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKNINAB3_NRF52840 - -config BOARD - default "ubx_evkninab3_nrf52840" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKNINAB3_NRF52840 diff --git a/boards/arm/ubx_evkninab3_nrf52840/doc/index.rst b/boards/arm/ubx_evkninab3_nrf52840/doc/index.rst deleted file mode 100644 index 6fc01e40a976ea..00000000000000 --- a/boards/arm/ubx_evkninab3_nrf52840/doc/index.rst +++ /dev/null @@ -1,328 +0,0 @@ -.. _ubx_ninab3_nrf52840: - -u-blox EVK-NINA-B3 -################## - -Overview -******** - -The u-blox EVK-NINA-B30 Development Kit hardware provides support for the -u-blox NINA-B30x Bluetooth 5.0 module, based on the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-NINA-B3.jpg - :align: center - :alt: EVK-NINA-B3 - - EVK-NINA-B3 (Credit: u-blox AG) - -More information about the EVK-NINA-B3 and the NINA-B30x modules -can be found at the `u-blox website`_. - -Hardware -******** - -The NINA-B30x on the EVK-NINA-B30x contains an internal high-frequency -oscillator at 32MHz as well as a low frequency (slow) oscillator -of 32.768kHz. - - -Supported Features -================== - -The ubx_evkninab3_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | IEEE 802.15.4 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See the `u-blox website`_ for a complete list of EVK-NINA-B30x -hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.13 -* LED1 (green) = P0.25 -* LED2 (blue) = P1.00 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.25 -* BUTTON2 = SW2 = P0.2 -* BOOT = SW0 = boot/reset - -External Connectors -------------------- - -.. note:: - The pin numbers noted below are referenced to - the pin 1 markings on the EVK-NINA-B30x - for each header - - -Arduino Headers ---------------- - -Power (J1) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 1 | N/C | N/A | -+-------+--------------+-------------------------+ -| 2 | VDD_IO | N/A | -+-------+--------------+-------------------------+ -| 3 | RESET | P0.18 / RESET | -+-------+--------------+-------------------------+ -| 4 | 3V3 | N/A | -+-------+--------------+-------------------------+ -| 5 | 5V0 | N/A | -+-------+--------------+-------------------------+ -| 6 | GND | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 8 | VIN | N/A | -+-------+--------------+-------------------------+ - -Analog in (J2) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 1 | A0 | P0.04 / AIN2 | -+-------+--------------+-------------------------+ -| 2 | A1 | P0.30 / AIN6 | -+-------+--------------+-------------------------+ -| 3 | A2 | P0.05 / AIN3 | -+-------+--------------+-------------------------+ -| 4 | A3 | P0.02 / AIN0 | -+-------+--------------+-------------------------+ -| 5 | A4 | P0.28 / AIN4 | -+-------+--------------+-------------------------+ -| 6 | A5 | P0.03 / AIN1 | -+-------+--------------+-------------------------+ - -Digital I/O (J3) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 8 | D7 | P0.10 | -+-------+--------------+-------------------------+ -| 7 | D6 | P0.09 | -+-------+--------------+-------------------------+ -| 6 | D5 | P0.11 | -+-------+--------------+-------------------------+ -| 5 | D4 | P0.13 | -+-------+--------------+-------------------------+ -| 4 | D3 | P0.31 | -+-------+--------------+-------------------------+ -| 3 | D2 | P1.12 | -+-------+--------------+-------------------------+ -| 2 | D1 (TX) | P1.13 | -+-------+--------------+-------------------------+ -| 1 | D0 (RX) | P0.29 | -+-------+--------------+-------------------------+ - -Digital I/O (J4) - -+-------+--------------+-------------------------+ -| PIN # | Signal Name | NINA-B30x Functions | -+=======+==============+=========================+ -| 10 | SCL | P0.24 | -+-------+--------------+-------------------------+ -| 9 | SDA | P0.16 | -+-------+--------------+-------------------------+ -| 8 | N/C | N/A | -+-------+--------------+-------------------------+ -| 7 | GND | N/A | -+-------+--------------+-------------------------+ -| 6 | D13 (SCK) | P0.07 | -+-------+--------------+-------------------------+ -| 5 | D12 (MISO) | P1.00 | -+-------+--------------+-------------------------+ -| 4 | D11 (MOSI) | P0.15 | -+-------+--------------+-------------------------+ -| 3 | D10 (SS) | P0.14 | -+-------+--------------+-------------------------+ -| 2 | D9 | P0.12 | -+-------+--------------+-------------------------+ -| 1 | D8 | P1.09 | -+-------+--------------+-------------------------+ - - -Programming and Debugging -************************* - -Applications for the ``ubx_evkninab3_nrf52840`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the EVK-NINA-B30x -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evkninab3_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging -u-blox boards with a Segger J-LINK-OB IC. - - -Testing the LEDs and buttons in the EVK-NINA-B30x -************************************************* - -There are 2 samples that allow you to test that the buttons -(switches) and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkninab3_nrf52840/ubx_ninab3_nrf52840.dts`. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app main directory to be -picked up automatically by the device tree compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the NINA-B3 at `u-blox website`_, Section 3 'Pin definition'. -In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' -can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module pad number. - -References -********** - -.. target-notes:: - -.. _u-blox website: https://www.u-blox.com/en/product/nina-b3-series-open-cpu diff --git a/boards/arm/ubx_evkninab4_nrf52833/Kconfig b/boards/arm/ubx_evkninab4_nrf52833/Kconfig deleted file mode 100644 index 1b346d578f34ef..00000000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# NINA-B4 EVK board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_UBX_EVKNINAB4_NRF52833 diff --git a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.board b/boards/arm/ubx_evkninab4_nrf52833/Kconfig.board deleted file mode 100644 index 0eb3268ba9e1f1..00000000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# NINA-B4 EVK board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UBX_EVKNINAB4_NRF52833 - bool "u-blox EVK-NINA-B4" - depends on SOC_NRF52833_QIAA diff --git a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig b/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig deleted file mode 100644 index 0e6ffbcfc5a219..00000000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# EVK-NINA-B4 board configuration -# -# Copyright (c) 2021 u-blox AG -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UBX_EVKNINAB4_NRF52833 - -config BOARD - default "ubx_evkninab4_nrf52833" - -config BT_CTLR - default BT - -endif # BOARD_UBX_EVKNINAB4_NRF52833 diff --git a/boards/arm/ubx_evkninab4_nrf52833/doc/index.rst b/boards/arm/ubx_evkninab4_nrf52833/doc/index.rst deleted file mode 100644 index abdb7754a9d1b1..00000000000000 --- a/boards/arm/ubx_evkninab4_nrf52833/doc/index.rst +++ /dev/null @@ -1,230 +0,0 @@ -.. _ubx_ninab4_nrf52833: - -u-blox EVK NINA-B40x -#################### - -Overview -******** - -The u-blox NINA-B4 Evaluation Kit hardware is a Bluetooth low energy -module based on the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU -and has support for the following features: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`USB (Universal Serial Bus)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/EVK-NINA-B406_Top_web.jpg - - EVK NINA-B4 - -More information about the NINA-B4 module and the EVK-NINA-B4 can be -found at `NINA-B40 product page`_ and `EVK-NINA-B4 product page`_. - -Supported Features -================== - -The ubx_evkninab4_nrf52833 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth low energy | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. -See `EVK-NINA-B4 product page`_ and `NINA-B40 Data Sheet`_ -for a complete list of EVK NINA-B4 hardware features. - -Connections and IOs -=================== - -LED ---- - -* LED0 (red) = P0.13 -* LED1 (green) = P1.01 -* LED2 (blue) = P1.00 - -Push buttons ------------- - -* BUTTON1 = SW1 = P1.01 (Shared with green LED) -* BUTTON2 = SW2 = P0.02 - -General information on module pin numbering -------------------------------------------- - -The numbering of the pins on the module and EVK do not follow the GPIO -numbering on the nRF52833 SoC. Please see the `NINA-B40 Data Sheet`_ for -information on how to map NINA-B40 pins to the pin numbering on the -nRF52833 SoC. - -The reason for this is the u-blox module family concept where different -modules share the same pinout and can be interchanged, see -`NINA module family Nested design`_. - -Programming and Debugging -************************* - -Applications for the ``ubx_evkninab4_nrf52833`` board configuration can be -built and flashed in the usual way (see :ref:`build_an_application` -and :ref:`application_run` for more details); however, the standard -debugging targets are not currently available. - -Flashing -======== - -Build and flash applications as usual (see -:ref:`build_an_application` and :ref:`application_run` for more details) - -Here is an example for the :ref:`hello_world` application. - -Open a terminal program to the USB Serial Port installed when connecting -the board and listen for output. - -Settings: 115200, 8N1, no flow control. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: ubx_evknina4_nrf52833 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging boards -containing a Nordic Semiconductor chip with a Segger IC. - - -Testing the LEDs and buttons in the EVK NINA-B40x -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) -and LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running -correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts`. - -Note that the buttons on the EVK-NINA-B4 are marked SW1 and SW2, which -are named sw0 and sw1 in the dts file. -Also note that the SW1 button and the green LED are connected on HW level. - -Using UART1 -*********** - -The following approach can be used when an application needs to use -more than one UART for connecting peripheral devices: - -1. Add device tree overlay file to the main directory of your application: - - .. code-block:: devicetree - - &pinctrl { - uart1_default: uart1_default { - group1 { - psels = , - ; - }; - }; - /* required if CONFIG_PM_DEVICE=y */ - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - }; - - &uart1 { - compatible = "nordic,nrf-uarte"; - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; - }; - - In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX - -2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` - -Overlay file naming -=================== - -The file has to be named ``.overlay`` and placed in the app main directory to be -picked up automatically by the device tree compiler. - -Selecting the pins -================== - -Pins can be configured in the board pinctrl file. To see the available mappings, -open the data sheet for the NINA-B4 at `NINA-B40 Data Sheet`_, Section 3 'Pin definition'. -In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' -can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. - -.. note: - Pins are defined according to the "nRF52" pin number, not the module pad number. - - -References -********** - -.. target-notes:: - -.. _NINA-B40 product page: https://www.u-blox.com/en/product/nina-b40-series-open-cpu -.. _EVK-NINA-B4 product page: https://www.u-blox.com/en/product/evk-nina-b4 -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _NINA-B40 Data Sheet: https://www.u-blox.com/en/docs/UBX-19049405 -.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ucans32k1sic/Kconfig.board b/boards/arm/ucans32k1sic/Kconfig.board deleted file mode 100644 index 314c7f98d5e80a..00000000000000 --- a/boards/arm/ucans32k1sic/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UCANS32K1SIC - bool "ucans32k1sic" - depends on SOC_SERIES_S32K1XX - select SOC_PART_NUMBER_FS32K146UAT0VLHT diff --git a/boards/arm/ucans32k1sic/Kconfig.defconfig b/boards/arm/ucans32k1sic/Kconfig.defconfig deleted file mode 100644 index 044df50c0c592f..00000000000000 --- a/boards/arm/ucans32k1sic/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UCANS32K1SIC - -config BOARD - default "ucans32k1sic" - -if SERIAL - -config UART_CONSOLE - default y - -endif # SERIAL - -if CAN - -config GPIO - default y - -endif # CAN - -endif # BOARD_UCANS32K1SIC diff --git a/boards/arm/ucans32k1sic/doc/index.rst b/boards/arm/ucans32k1sic/doc/index.rst deleted file mode 100644 index 66138b44a008b8..00000000000000 --- a/boards/arm/ucans32k1sic/doc/index.rst +++ /dev/null @@ -1,197 +0,0 @@ -.. _ucans32k1sic: - -NXP UCANS32K1SIC -################ - -Overview -******** - -`NXP UCANS32K1SIC`_ is a CAN signal improvement capability (SIC) evaluation -board designed for both automotive and industrial applications. The UCANS32K1SIC -provides two CAN SIC interfaces and is based on the 32-bit Arm Cortex-M4F -`NXP S32K146`_ microcontroller. - -.. image:: img/ucans32k1sic_top.webp - :align: center - :alt: NXP UCANS32K1SIC (TOP) - -Hardware -******** - -- NXP S32K146 - - Arm Cortex-M4F @ up to 112 Mhz - - 1 MB Flash - - 128 KB SRAM - - up to 127 I/Os - - 3x FlexCAN with 2x FD - - eDMA, 12-bit ADC, MPU, ECC and more. - -- Interfaces: - - DCD-LZ debug interface with SWD + Console / UART - - Dual CAN FD PHYs with dual connectors for daisy chain operation - - JST-GH DroneCode compliant standard connectors and I/O headers - - user RGB LED and button. - -More information about the hardware and design resources can be found at -`NXP UCANS32K1SIC`_ website. - -Supported Features -================== - -The ``ucans32k1sic`` board configuration supports the following hardware features: - -============ ========== ================================ -Interface Controller Driver/Component -============ ========== ================================ -SYSMPU on-chip mpu -PORT on-chip pinctrl -GPIO on-chip gpio -LPUART on-chip serial -LPI2C on-chip i2c -LPSPI on-chip spi -FTM on-chip pwm -FlexCAN on-chip can -Watchdog on-chip watchdog -RTC on-chip counter -============ ========== ================================ - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/ucans32k1sic/ucans32k1sic_defconfig`. - -Connections and IOs -=================== - -This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``. - -Pin control can be further configured from your application overlay by adding -children nodes with the desired pinmux configuration to the singleton node -``pinctrl``. Supported properties are described in -:zephyr_file:`dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml`. - -LEDs ----- - -The UCANS32K1SIC board has one user RGB LED that can be used either as a GPIO -LED or as a PWM LED. - -.. table:: RGB LED as GPIO LED - :widths: auto - - =============== ================ =============== ===== - Devicetree node Devicetree alias Label Pin - =============== ================ =============== ===== - led1_red led0 LED1_RGB_RED PTD15 - led1_green led1 LED1_RGB_GREEN PTD16 - led1_blue led2 LED1_RGB_BLUE PTD0 - =============== ================ =============== ===== - -.. table:: RGB LED as PWM LED - :widths: auto - - =============== ======================== ================== ================ - Devicetree node Devicetree alias Label Pin - =============== ======================== ================== ================ - led1_red_pwm pwm-led0 / red-pwm-led LED1_RGB_RED_PWM PTD15 / FTM0_CH0 - led1_green_pwm pwm-led1 / green-pwm-led LED1_RGB_GREEN_PWM PTD16 / FTM0_CH1 - led1_blue_pwm pwm-led2 / blue-pwm-led LED1_RGB_BLUE_PWM PTD0 / FTM0_CH2 - =============== ======================== ================== ================ - -The user can control the LEDs in any way. An output of ``0`` illuminates the LED. - -Buttons -------- - -The UCANS32K1SIC board has one user button: - -======================= ============== ===== -Devicetree node Label Pin -======================= ============== ===== -sw0 / button_3 SW3 PTD15 -======================= ============== ===== - -Serial Console -============== - -The serial console is provided via ``lpuart1`` on the 7-pin DCD-LZ debug -connector ``P6``. - -========= ===== ============ -Connector Pin Pin Function -========= ===== ============ -P6.2 PTC7 LPUART1_TX -P6.3 PTC6 LPUART1_RX -========= ===== ============ - -System Clock -============ - -The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode). - -Programming and Debugging -************************* - -Applications for the ``ucans32k1sic`` board can be built in the usual way as -documented in :ref:`build_an_application`. - -This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ -West runners for flashing and debugging applications. Follow the steps described -in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, -to setup the flash and debug host tools for these runners, respectively. The -default runner is J-Link. - -Flashing -======== - -Run the ``west flash`` command to flash the application using SEGGER J-Link. -Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. - -The Lauterbach TRACE32 runner supports additional options that can be passed -through command line: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile= loadTo= - eraseFlash= verifyFlash= - -Where: - -- ```` is the path to the Zephyr application ELF in the output - directory -- ``loadTo=flash`` loads the application to the SoC internal program flash - (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the - application to SRAM. The default is ``flash``. -- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the - application is downloaded to either Flash or SRAM. This routine takes time to - execute. The default is ``no``. -- ``verifyFlash=yes`` verify the SoC internal flash content after programming - (use together with ``loadTo=flash``). The default is ``no``. - -For example, to erase and verify flash content: - -.. code-block:: console - - west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes - -Debugging -========= - -Run the ``west debug`` command to start a GDB session using SEGGER J-Link. -Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 -software debugging interface. - -References -********** - -.. target-notes:: - -.. _NXP UCANS32K1SIC: - https://www.nxp.com/design/development-boards/analog-toolbox/can-sic-evaluation-board:UCANS32K1SIC - -.. _NXP S32K146: - https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k1-microcontrollers-for-automotive-general-purpose:S32K1 - -.. _Lauterbach TRACE32: - https://www.lauterbach.com - -.. _SEGGER J-Link: - https://wiki.segger.com/S32Kxxx diff --git a/boards/arm/ucans32k1sic/ucans32k1sic_defconfig b/boards/arm/ucans32k1sic/ucans32k1sic_defconfig deleted file mode 100644 index 8580c7155cb12f..00000000000000 --- a/boards/arm/ucans32k1sic/ucans32k1sic_defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_UCANS32K1SIC=y -CONFIG_SOC_SERIES_S32K1XX=y -CONFIG_SOC_S32K146=y -CONFIG_BUILD_OUTPUT_HEX=y - -# Use Systick as system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000 - -# Run from internal program flash -CONFIG_XIP=y - -# Enable MPU -CONFIG_ARM_MPU=y - -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y diff --git a/boards/arm/udoo_neo_full_m4/Kconfig.board b/boards/arm/udoo_neo_full_m4/Kconfig.board deleted file mode 100644 index f9f67b923ed3dc..00000000000000 --- a/boards/arm/udoo_neo_full_m4/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UDOO_NEO_FULL_M4 - bool "UDOO Neo Full" - depends on SOC_SERIES_IMX_6X_M4 - select SOC_PART_NUMBER_MCIMX6X4EVM10AB diff --git a/boards/arm/udoo_neo_full_m4/Kconfig.defconfig b/boards/arm/udoo_neo_full_m4/Kconfig.defconfig deleted file mode 100644 index 62636188a78da9..00000000000000 --- a/boards/arm/udoo_neo_full_m4/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# UDOO Neo Full board - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UDOO_NEO_FULL_M4 - -config BOARD - default "udoo_neo_full_m4" - -endif # BOARD_UDOO_NEO_FULL_M4 diff --git a/boards/arm/udoo_neo_full_m4/doc/index.rst b/boards/arm/udoo_neo_full_m4/doc/index.rst deleted file mode 100644 index f3c11e3dd31668..00000000000000 --- a/boards/arm/udoo_neo_full_m4/doc/index.rst +++ /dev/null @@ -1,368 +0,0 @@ -.. _udoo_neo_full_m4: - -UDOO Neo Full -############# - -Overview -******** - -UDOO Neo Full is an open source Arduino Uno compatible single board computer. -It is equipped with an NXP |reg| i.MX 6SoloX hybrid multicore processor -composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4 -core running up to 227 MHz for high CPU performance and real-time response. -Zephyr was ported to run on the Cortex-M4 core only. In a future release, it -will also communicate with the Cortex-A9 core (running Linux) via OpenAMP. - -.. figure:: udoo_neo_full_m4.jpg - :align: center - :alt: UDOO-Neo-Full - - UDOO Neo Full (Credit: udoo.org) - -Hardware -******** - -- MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core - -- Memory - - - 1 GB RAM - - 128 KB OCRAM - - 256 KB L2 cache (can be switched into OCRAM instead) - - 16 KB OCRAM_S - - 32 KB TCML - - 32 KB TCMU - - 32 KB CAAM (secure RAM) - -- A9 Boot Devices - - - NOR flash - - NAND flash - - OneNAND flash - - SD/MMC - - Serial (I2C/SPI) NOR flash and EEPROM - - QuadSPI (QSPI) flash - -- Display - - - Micro HDMI connector - - LVDS display connector - - Touch (I2C signals) - -- Multimedia - - - Integrated 2d/3d graphics controller - - 8-bit parallel interface for analog camera supporting NTSC and PAL - - HDMI audio transmitter - - S/PDIF - - I2S - -- Connectivity - - - USB 2.0 Type A port - - USB OTG (micro-AB connector) - - 10/100 Mbit/s Ethernet PHY - - Wi-Fi 802.11 b/g/n - - Bluetooth 4.0 Low Energy - - 3x UART ports - - 2x CAN Bus interfaces - - 8x PWM signals - - 3x I2C interface - - 1x SPI interface - - 6x multiplexable signals - - 32x GPIO (A9) - - 22x GPIO (M4) - -- Other - - - MicroSD card slot (8-bit SDIO interface) - - Power status LED (green) - - 2x user LED (red and orange) - -- Power - - - 5 V DC Micro USB - - 6-15 V DC jack - - RTC battery connector - -- Debug - - - pads for soldering of JTAG 14-pin connector - -- Sensor - - - 3-Axis Accelerometer - - 3-Axis Magnetometer - - 3-Axis Digital Gyroscope - - 1x Sensor Snap-In I2C connector - -- Expansion port - - - Arduino interface - -For more information about the MCIMX6X SoC and UDOO Neo Full board, -see these references: - -- `NXP i.MX 6SoloX Website`_ -- `NXP i.MX 6SoloX Datasheet`_ -- `NXP i.MX 6SoloX Reference Manual`_ -- `UDOO Neo Website`_ -- `UDOO Neo Getting Started`_ -- `UDOO Neo Documentation`_ -- `UDOO Neo Datasheet`_ -- `UDOO Neo Schematics`_ - -Supported Features -================== - -The UDOO Neo Full board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | general purpose input/output | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | counter | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The UDOO Neo Full board was tested with the following pinmux -controller configuration. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| J4 RX | UART5_RX_DATA | UART Console | -+---------------+-----------------+---------------------------+ -| J4 TX | UART5_TX_DATA | UART Console | -+---------------+-----------------+---------------------------+ - -System Clock -============ - -The MCIMX6X SoC is configured to use the 24 MHz external oscillator -on the board with the on-chip PLL to generate core clock. -PLL settings for M4 core are set via code running on the A9 core. - -Serial Port -=========== - -The MCIMX6X SoC has six UARTs. UART5 is configured for the M4 core and the -remaining are used by the A9 core or not used. - -Programming and Debugging -************************* - -The M4 core does not have a flash memory and is not provided a clock -at power-on-reset. Therefore it needs to be started by the A9 core. -The A9 core is responsible to load the M4 binary application into the RAM, -put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get -the M4 out of reset. The A9 can perform these steps at the bootloader level -or after the Linux system has booted. - -The M4 core can use up to 5 different RAMs (some other types of memory like -a secure RAM are not currently implemented in Zephyr). -These are the memory mappings for A9 and M4: - -+------------+-----------------------+-----------------------+-----------------------+ -| Region | Cortex-A9 | Cortex-M4 | Size | -+============+=======================+=======================+=======================+ -| TCML | 0x007F8000-0x007FFFFF | 0x1FFF8000-0x1FFFFFFF | 32 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | 32 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| OCRAM_S | 0x008F8000-0x008FBFFF | 0x208F8000-0x208FBFFF | 16 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20900000-0x2091FFFF | 128 KB | -+------------+-----------------------+-----------------------+-----------------------+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 2048 MB (1536 for M4) | -+------------+-----------------------+-----------------------+-----------------------+ - -References -========== - -- `NXP i.MX 6SoloX Reference Manual`_ Chapter 2 - Memory Maps - -You have to choose which RAM will be used at compilation time. This configuration -is done in the file ``boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts``. - -If you want to have the code placed in the subregion of a memory, which will -likely be the case when using DDR, select "zephyr,flash=&flash" and set the -DT_FLASH_SIZE macro to determine the region size and DT_FLASH_ADDR to determine -the address where the region begins. - -If you want to have the data placed in the subregion of a memory, which will -likely be the case when using DDR, select "zephyr,sram = &sram", which sets the -CONFIG_SRAM_SIZE macro to determine the region size and -CONFIG_SRAM_BASE_ADDRESS to determine the address where the region begins. - -Otherwise set "zephyr,flash" and/or "zephyr,sram" to one of the predefined -regions: - -.. code-block:: none - - "zephyr,flash" - - &tcml - - &ocram_s - - &ocram - - &ddr - - "zephyr,sram" - - &tcmu - - &ocram_s - - &ocram - - &ddr - -Below you will find the instructions how a Linux user space application running -on the A9 core can be used to load and run Zephyr application on the M4 core. - -The UDOOBuntu Linux distribution contains a `udooneo-m4uploader`_ utility, -but its purpose is to load UDOO Neo "Arduino-like" sketches, so it doesn't -work with Zephyr applications in most cases. The reason is that there is -an exchange of information between this utility and the program running on the -M4 core using hardcoded shared memory locations. The utility writes a flag which -is read by the program running on the M4 core. The program is then supposed to -end safely and write the status to the shared memory location for the main core. -The utility then loads the new application and reads its status from the shared -memory location to determine if it has successfully launched. Since this -functionality is specific for the UDOO Neo "Arduino-like" sketches, it is not -implemented in Zephyr. However Zephyr applications can support it on their own -if planned to be used along with the UDOOBuntu Linux running on the A9 core. -The udooneo-uploader utility calls another executable named -mqx_upload_on_m4SoloX which can be called directly to load Zephyr applications. -Copy the Zephyr binary image into the Linux filesystem and invoke the utility -as a root user: - -.. code-block:: console - - mqx_upload_on_m4SoloX zephyr.bin - -If the output looks like below, the mqx_upload_on_m4SoloX could not read -the status of the stopped application. This is expected if the previously -loaded application is not a UDOO Neo "Arduino-like" sketch and ignores the -shared memory communication: - -.. code-block:: console - - UDOONeo - mqx_upload_on_m4SoloX 1.1.0 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 - UDOONeo - Failed to Stop M4 sketch: reboot system ! - -In such situation, the mqx_upload_on_m4SoloX utility has reset the trace flags, -so it will succeed when called again. Then it can have this output below: - -.. code-block:: console - - UDOONeo - mqx_upload_on_m4SoloX 1.1.0 - UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 - UDOONeo - start - end (0x84000000 - 0x84080000) - UDOONeo - Waiting M4 Run, m4TraceFlags: 000001E0 - UDOONeo - M4 sketch is running - -Or the one below, if the utility cannot read the status flag that the M4 core -applications has started. It can be ignored as the application should be -running, the utility just doesn't know it: - -.. code-block:: console - - UDOONeo - mqx_upload_on_m4SoloX 1.1.0 - UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 - UDOONeo - start - end (0x84000000 - 0x84080000) - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 - UDOONeo - Failed to Start M4 sketch: reboot system ! - -The stack pointer and the program counter values are read from the binary. -The memory address where binary will be placed is calculated from the program -counter as its value aligned to 64 KB down, or it can be provided as a second -command line argument: - -.. code-block:: console - - mqx_upload_on_m4SoloX zephyr.bin 0x84000000 - -It is necessary to provide the address if the binary is copied into a memory -region which has different mapping between the A9 and the M4 core. The address -calculated from the stack pointer value in the binary file would be wrong. - -It is possible to modify the mqx_upload_on_m4SoloX utility source code -to not exchange the information with the M4 core application using shared -memory. - -It is also possible to use the `imx-m4fwloader`_ utility to load the M4 core -application. - -One option applicable in UDOOBuntu Linux is to copy the binary file into the -file /var/opt/m4/m4last.fw in the Linux filesystem. The next time the system is -booted, Das U-Boot will load it from there. - -Another option is to directly use Das U-Boot to load the code. - -Debugging -========= - -The UDOO Neo Full board includes pads for soldering the 14-pin JTAG -connector. Zephyr applications running on the M4 core have only been -tested by observing UART console output. - -References -========== - -.. target-notes:: - -.. _UDOO Neo Website: - https://www.udoo.org/udoo-neo/ - -.. _UDOO Neo Getting Started: - https://www.udoo.org/get-started-neo/ - -.. _UDOO Neo Documentation: - https://www.udoo.org/docs-neo - -.. _UDOO Neo Datasheet: - https://www.udoo.org/download/files/datasheets/datasheet_udoo_neo.pdf - -.. _UDOO Neo Schematics: - https://www.udoo.org/download/files/schematics/UDOO_NEO_schematics.pdf - -.. _Udoo Neo Linux or Android Images for the A9 Core: - https://www.udoo.org/downloads/ - -.. _udooneo-m4uploader: - https://github.com/ektor5/udooneo-m4uploader - -.. _imx-m4fwloader: - https://github.com/codeauroraforum/imx-m4fwloader - -.. _NXP i.MX 6SoloX Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX - -.. _NXP i.MX 6SoloX Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX6SXCEC.pdf - -.. _NXP i.MX 6SoloX Reference Manual: - https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts b/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts deleted file mode 100644 index 6e7ee0bfb63464..00000000000000 --- a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.dts +++ /dev/null @@ -1,84 +0,0 @@ -/* - * Copyright (c) 2018, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/* - * Determines the address and size for code memory which will be applied - * when "zephyr,flash = &flash". Use this to select a custom region, - * usually within DDR. - */ -#define DT_FLASH_SIZE DT_SIZE_K(512) -#define DT_FLASH_ADDR 84000000 /* DT_ADDR will add leading 0x where needed */ - -/* - * Determines the address and size for data memory which will be applied - * when "zephyr,sram = &sram". Use this to select a custom region, - * usually within DDR. - */ -#define DT_SRAM_SIZE DT_SIZE_K(128) -#define DT_SRAM_ADDR 84080000 /* DT_ADDR will add leading 0x where needed */ - -#include -#include "udoo_neo_full_m4-pinctrl.dtsi" - -/ { - model = "UDOO Neo Full board"; - compatible = "nxp,mcimx6x_m4"; - - aliases { - led0 = &red_led; - }; - - chosen { - zephyr,flash = &flash; - zephyr,sram = &tcmu; - zephyr,console = &uart5; - zephyr,shell-uart = &uart5; - }; - - leds { - compatible = "gpio-leds"; - red_led: led_0 { - gpios = <&gpio4 6 0>; - label = "User LD1"; - }; - }; -}; - -&uart5 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart5_default>; - pinctrl-names = "default"; -}; - -&gpio4 { - status = "okay"; -}; - -&gpio5 { - status = "okay"; -}; - -&gpio6 { - status = "okay"; -}; - -&mub { - status = "okay"; -}; - -&epit1 { - status = "okay"; -}; - -&epit2 { - status = "okay"; -}; diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.yaml b/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.yaml deleted file mode 100644 index 8e2876ca5ab5ad..00000000000000 --- a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4.yaml +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: udoo_neo_full_m4 -name: UDOO Neo Full -type: mcu -arch: arm -ram: 32 -flash: 512 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - counter - - gpio - - uart -vendor: nxp diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig b/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig deleted file mode 100644 index c03d8770a7d13c..00000000000000 --- a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_MCIMX6X_M4=y -CONFIG_SOC_SERIES_IMX_6X_M4=y -CONFIG_BOARD_UDOO_NEO_FULL_M4=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=227000000 -CONFIG_PINCTRL=y diff --git a/boards/arm/usb_kw24d512/Kconfig.board b/boards/arm/usb_kw24d512/Kconfig.board deleted file mode 100644 index f76553fe19d59c..00000000000000 --- a/boards/arm/usb_kw24d512/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# USB-KW24D512 board - -# Copyright (c) 2017, Phytec Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_USB_KW24D512 - bool "NXP USB-KW24D512" - depends on SOC_SERIES_KINETIS_KWX - select SOC_PART_NUMBER_MKW24D512VHA5 diff --git a/boards/arm/usb_kw24d512/Kconfig.defconfig b/boards/arm/usb_kw24d512/Kconfig.defconfig deleted file mode 100644 index 373eae6292abc6..00000000000000 --- a/boards/arm/usb_kw24d512/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# USB-KW24D512 board - -# Copyright (c) 2017, Phytec Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_USB_KW24D512 - -config BOARD - default "usb_kw24d512" - -config OSC_XTAL0_FREQ - # The MCU is configured to use 4 MHz external - # clock from the transceiver provided at the CLK_OUT output. - # CLK_OUT is internally connected to the input pin EXTAL0 - # of the MCU. - default 4000000 - -config MCG_PRDIV0 - default 0x1 - -config MCG_VDIV0 - default 0x0 - -config MCG_FCRDIV - default 2 - -config MCR20A_IS_PART_OF_KW2XD_SIP - default y - depends on IEEE802154_MCR20A - -endif # BOARD_USB_KW24D512 diff --git a/boards/arm/usb_kw24d512/doc/index.rst b/boards/arm/usb_kw24d512/doc/index.rst deleted file mode 100644 index 41b0d956c93502..00000000000000 --- a/boards/arm/usb_kw24d512/doc/index.rst +++ /dev/null @@ -1,231 +0,0 @@ -.. _usb_kw24d512: - -NXP USB-KW24D512 -################ - -Overview -******** - -The USB-KW24D512 is an evaluation board in a convenient USB dongle -form factor based on the NXP MKW24D512 System-in-Package (SiP) device -(KW2xD wireless MCU series). -MKW24D512 wireless MCU provides a low-power, compact device with -integrated IEEE 802.15.4 radio. The board can be used as a packet sniffer, -network node, border router or as a development board. - -Hardware -******** - -- Kinetis KW2xD-2.4 GHz 802.15.4 Wireless Radio Microcontroller - (50 MHz, 512 KB flash memory, 64 KB RAM, low-power, crystal-less USB) -- USB Type A Connector -- Two blue LEDs -- One user push button -- One reset button -- Integrated PCB Folded F-type antenna -- 10-pin (0.05”) JTAG debug port for target MCU - -For more information about the KW2xD SiP and USB-KW24D512 board: - -- `KW2xD Website`_ -- `KW2xD Datasheet`_ -- `KW2xD Reference Manual`_ -- `USB-KW24D512 Website`_ -- `USB-KW24D512 Hardware Reference Manual`_ - -Supported Features -================== - -The USB-KW24D512 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| FLASH | on-chip | soc flash | -+-----------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+-----------+------------+-------------------------------------+ -| RNGA | on-chip | entropy; | -| | | random | -+-----------+------------+-------------------------------------+ -| FTFL | on-chip | flash programming | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/usb_kw24d512/usb_kw24d512_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The KW2xD SoC has five pairs of pinmux/gpio controllers. - -+-------+-----------------+--------------------------------------+ -| Name | Function | Usage | -+=======+=================+======================================+ -| PTA1 | UART0_RX | UART Console | -+-------+-----------------+--------------------------------------+ -| PTA2 | UART0_TX | UART Console | -+-------+-----------------+--------------------------------------+ -| PTC4 | GPIO | SW1 | -+-------+-----------------+--------------------------------------+ -| PTD4 | GPIO | Blue LED (D2) | -+-------+-----------------+--------------------------------------+ -| PTD5 | GPIO | Blue LED (D3) | -+-------+-----------------+--------------------------------------+ -| PTB10 | SPI1_PCS0 | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB11 | SPI1_SCK | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB16 | SPI1_SOUT | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB17 | SPI1_SIN | internal connected to MCR20A | -+-------+-----------------+--------------------------------------+ -| PTB19 | GPIO | internal connected to MCR20A (Reset) | -+-------+-----------------+--------------------------------------+ -| PTB3 | GPIO | internal connected to MCR20A (IRQ_B) | -+-------+-----------------+--------------------------------------+ -| PTC0 | GPIO | internal connected to MCR20A (GPIO5) | -+-------+-----------------+--------------------------------------+ - -System Clock -============ - -USB-KW24D512 contains 32 MHz oscillator crystal, which is connected to the -clock pins of the radio transceiver. The MCU is configured to -use the 4 MHz external clock from the transceiver with the on-chip PLL -to generate a 48 MHz system clock. - -Serial Port -=========== - -The KW2xD SoC has three UARTs. One is configured and can be used for the -console, but it uses the same pins as the JTAG interface and is only -accessible via the JTAG SWD connector. - -USB -=== - -The KW2xD SoC has a USB OTG (USBOTG) controller that supports both -device and host functions. Only USB device function is supported in Zephyr -at the moment. The USB-KW24D512 board has a USB Type A connector and -can only be used in device mode. - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Configuring a Debug Probe -========================= - -A debug probe is used for both flashing and debugging the board. This board is -configured by default to use the :ref:`jlink-external-debug-probe`. - -:ref:`jlink-external-debug-probe` ---------------------------------- - -Install the :ref:`jlink-debug-host-tools` and make sure they are in your search -path. - -Attach a J-Link 10-pin connector to J1. - -Configuring a Console -===================== - -The console is available using `Segger RTT`_. - -Connect a USB cable from your PC to J5. - -Once you have started a debug session, run telnet: - -.. code-block:: console - - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - SEGGER J-Link V6.44 - Real time terminal output - SEGGER J-Link ARM V10.1, SN=600111924 - Process: JLinkGDBServerCLExe - -Flashing -======== - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: usb_kw24d512 - :goals: flash - -The Segger RTT console is only available during a debug session. Use ``attach`` -to start one: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: usb_kw24d512 - :goals: attach - -Run telnet as shown earlier, and you should see the following message in the -terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! usb_kw24d512 - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: usb_kw24d512 - :goals: debug - -Run telnet as shown earlier, step through the application in your debugger, and -you should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v1.14.0-rc1 ***** - Hello World! usb_kw24d512 - -.. _USB-KW24D512 Website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/ieee-802.15.4-packet-sniffer-usb-dongle-form-factor:USB-KW24D512 - -.. _USB-KW24D512 Hardware Reference Manual: - https://www.nxp.com/webapp/Download?colCode=USB-KW2XHWRM - -.. _KW2xD Website: - https://www.nxp.com/products/wireless/thread/kinetis-kw2xd-2.4-ghz-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m4-core:KW2xD - -.. _KW2xD Datasheet: - https://www.nxp.com/docs/en/data-sheet/MKW2xDxxx.pdf - -.. _KW2xD Reference Manual: - https://www.nxp.com/webapp/Download?colCode=MKW2XDXXXRM - -.. _Segger RTT: - https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ diff --git a/boards/arm/usb_kw24d512/usb_kw24d512_defconfig b/boards/arm/usb_kw24d512/usb_kw24d512_defconfig deleted file mode 100644 index 1d9dbb04067809..00000000000000 --- a/boards/arm/usb_kw24d512/usb_kw24d512_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_MKW24D5=y -CONFIG_SOC_SERIES_KINETIS_KWX=y -CONFIG_BOARD_USB_KW24D512=y -CONFIG_CONSOLE=y -CONFIG_RTT_CONSOLE=y -CONFIG_USE_SEGGER_RTT=y -CONFIG_SERIAL=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 -CONFIG_OSC_EXTERNAL=y diff --git a/boards/arm/v2m_beetle/Kconfig.board b/boards/arm/v2m_beetle/Kconfig.board deleted file mode 100644 index 6c0d883865dbe7..00000000000000 --- a/boards/arm/v2m_beetle/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# ARM V2M Beetle Board configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# V2M (V2 = Versatile Express, M = Motherboard) -config BOARD_V2M_BEETLE - bool "ARM V2M Beetle Board" - depends on SOC_BEETLE_R0 diff --git a/boards/arm/v2m_beetle/Kconfig.defconfig b/boards/arm/v2m_beetle/Kconfig.defconfig index 2c88eebef3906f..3e04387a2337e4 100644 --- a/boards/arm/v2m_beetle/Kconfig.defconfig +++ b/boards/arm/v2m_beetle/Kconfig.defconfig @@ -5,9 +5,6 @@ if BOARD_V2M_BEETLE -config BOARD - default "v2m_beetle" - if SERIAL config UART_INTERRUPT_DRIVEN diff --git a/boards/arm/v2m_beetle/Kconfig.v2m_beetle b/boards/arm/v2m_beetle/Kconfig.v2m_beetle new file mode 100644 index 00000000000000..574be8a942b0f1 --- /dev/null +++ b/boards/arm/v2m_beetle/Kconfig.v2m_beetle @@ -0,0 +1,8 @@ +# ARM V2M Beetle Board configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# V2M (V2 = Versatile Express, M = Motherboard) +config BOARD_V2M_BEETLE + select SOC_BEETLE_R0 diff --git a/boards/arm/v2m_beetle/board.yml b/boards/arm/v2m_beetle/board.yml new file mode 100644 index 00000000000000..b19e9bfec75b7f --- /dev/null +++ b/boards/arm/v2m_beetle/board.yml @@ -0,0 +1,5 @@ +board: + name: v2m_beetle + vendor: arm + socs: + - name: beetle_r0 diff --git a/boards/arm/v2m_beetle/v2m_beetle_defconfig b/boards/arm/v2m_beetle/v2m_beetle_defconfig index 7301a8a27328af..175c3072e9fe90 100644 --- a/boards/arm/v2m_beetle/v2m_beetle_defconfig +++ b/boards/arm/v2m_beetle/v2m_beetle_defconfig @@ -6,11 +6,9 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_BEETLE_R0=y -CONFIG_SOC_SERIES_BEETLE=y -CONFIG_BOARD_V2M_BEETLE=y CONFIG_RUNTIME_NMI=y CONFIG_CLOCK_CONTROL=y + # 24MHz system clock CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000 diff --git a/boards/arm/v2m_musca_b1/Kconfig.board b/boards/arm/v2m_musca_b1/Kconfig.board deleted file mode 100644 index 6fc98094cfd807..00000000000000 --- a/boards/arm/v2m_musca_b1/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MUSCA_B1 - bool "ARM Cortex-M33 SMM on V2M-MUSCA" - depends on SOC_SERIES_MUSCA_B1 diff --git a/boards/arm/v2m_musca_b1/Kconfig.defconfig b/boards/arm/v2m_musca_b1/Kconfig.defconfig index 77dc7e9ad364bb..24b1c90fe77a14 100644 --- a/boards/arm/v2m_musca_b1/Kconfig.defconfig +++ b/boards/arm/v2m_musca_b1/Kconfig.defconfig @@ -1,11 +1,7 @@ # Copyright (c) 2019 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -if BOARD_MUSCA_B1 - -config BOARD - default "musca_b1" if TRUSTED_EXECUTION_SECURE || !TRUSTED_EXECUTION_NONSECURE - default "musca_b1_ns" +if BOARD_V2M_MUSCA_B1 if SERIAL @@ -14,4 +10,4 @@ config UART_INTERRUPT_DRIVEN endif # SERIAL -endif +endif # BOARD_V2M_MUSCA_B1 diff --git a/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 b/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 new file mode 100644 index 00000000000000..3171dc5033efd5 --- /dev/null +++ b/boards/arm/v2m_musca_b1/Kconfig.v2m_musca_b1 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_V2M_MUSCA_B1 + select SOC_V2M_MUSCA_B1 diff --git a/boards/arm/v2m_musca_b1/board.yml b/boards/arm/v2m_musca_b1/board.yml new file mode 100644 index 00000000000000..47cebc33bb14d6 --- /dev/null +++ b/boards/arm/v2m_musca_b1/board.yml @@ -0,0 +1,7 @@ +board: + name: v2m_musca_b1 + vendor: arm + socs: + - name: musca_b1 + variants: + - name: 'ns' diff --git a/boards/arm/v2m_musca_b1/doc/index.rst b/boards/arm/v2m_musca_b1/doc/index.rst index 0f0c261460a100..0a7d41ac883c1d 100644 --- a/boards/arm/v2m_musca_b1/doc/index.rst +++ b/boards/arm/v2m_musca_b1/doc/index.rst @@ -98,7 +98,7 @@ See the `V2M Musca B1 Website`_ for a complete list of V2M Musca board hardware features. The default configuration can be found in the defconfig file: -``boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig``. +:zephyr_file:`boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig`. Interrupt Controller ==================== diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml index 76ddda994682ea..72be434271db60 100644 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml @@ -1,4 +1,4 @@ -identifier: v2m_musca_b1 +identifier: v2m_musca_b1/musca_b1 name: ARM V2M MUSCA B1 type: mcu arch: arm diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig b/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig index d6f7a3876d1931..b04afd5915d38a 100644 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MUSCA_B1=y -CONFIG_SOC_V2M_MUSCA_B1=y CONFIG_RUNTIME_NMI=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_ARM_MPU=y diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.dts b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts similarity index 100% rename from boards/arm/v2m_musca_b1/v2m_musca_b1_ns.dts rename to boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.dts diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml new file mode 100644 index 00000000000000..8f8700b08853c2 --- /dev/null +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml @@ -0,0 +1,11 @@ +identifier: v2m_musca_b1/musca_b1/ns +name: ARM V2M MUSCA B1 NonSecure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 64 +flash: 1663 +vendor: arm diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig new file mode 100644 index 00000000000000..925071fbdf4e17 --- /dev/null +++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns_defconfig @@ -0,0 +1,7 @@ +# +# Copyright (c) 2019 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.yaml deleted file mode 100644 index f116e1e52b9850..00000000000000 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: v2m_musca_b1_ns -name: ARM V2M MUSCA B1 NonSecure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 64 -flash: 1663 -vendor: arm diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns_defconfig b/boards/arm/v2m_musca_b1/v2m_musca_b1_ns_defconfig deleted file mode 100644 index b782032beffe64..00000000000000 --- a/boards/arm/v2m_musca_b1/v2m_musca_b1_ns_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2019 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MUSCA_B1=y -CONFIG_SOC_V2M_MUSCA_B1=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_ARM_MPU=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/v2m_musca_s1/Kconfig.board b/boards/arm/v2m_musca_s1/Kconfig.board deleted file mode 100644 index 81261ba47bf18e..00000000000000 --- a/boards/arm/v2m_musca_s1/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MUSCA_S1 - bool "ARM Cortex-M33 SMM on V2M-MUSCA-S1" - depends on SOC_SERIES_MUSCA_S1 diff --git a/boards/arm/v2m_musca_s1/Kconfig.defconfig b/boards/arm/v2m_musca_s1/Kconfig.defconfig index 532970a8b6bf2f..f450de9f4760c1 100644 --- a/boards/arm/v2m_musca_s1/Kconfig.defconfig +++ b/boards/arm/v2m_musca_s1/Kconfig.defconfig @@ -1,11 +1,7 @@ # Copyright (c) 2019-2020 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -if BOARD_MUSCA_S1 - -config BOARD - default "musca_s1" if TRUSTED_EXECUTION_SECURE || !TRUSTED_EXECUTION_NONSECURE - default "musca_s1_ns" +if BOARD_V2M_MUSCA_S1 if SERIAL @@ -14,4 +10,4 @@ config UART_INTERRUPT_DRIVEN endif # SERIAL -endif +endif # BOARD_V2M_MUSCA_S1 diff --git a/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 b/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 new file mode 100644 index 00000000000000..fd5ab86f341ce5 --- /dev/null +++ b/boards/arm/v2m_musca_s1/Kconfig.v2m_musca_s1 @@ -0,0 +1,5 @@ +# Copyright (c) 2019-2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_V2M_MUSCA_S1 + select SOC_V2M_MUSCA_S1 diff --git a/boards/arm/v2m_musca_s1/board.yml b/boards/arm/v2m_musca_s1/board.yml new file mode 100644 index 00000000000000..a7a3e18358d7cf --- /dev/null +++ b/boards/arm/v2m_musca_s1/board.yml @@ -0,0 +1,7 @@ +board: + name: v2m_musca_s1 + vendor: arm + socs: + - name: musca_s1 + variants: + - name: 'ns' diff --git a/boards/arm/v2m_musca_s1/doc/index.rst b/boards/arm/v2m_musca_s1/doc/index.rst index 8a1c4b221bd495..7072ef7e219132 100644 --- a/boards/arm/v2m_musca_s1/doc/index.rst +++ b/boards/arm/v2m_musca_s1/doc/index.rst @@ -95,7 +95,7 @@ See the `V2M Musca-S1 Website`_ for a complete list of V2M Musca-S1 board hardware features. The default configuration can be found in the defconfig file: -``boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig``. +:zephyr_file:`boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig`. Interrupt Controller ==================== @@ -384,13 +384,13 @@ folder after TF-M built. Building the TF-M integration sample for Musca-S1 ------------------------------------------------- -The TF-M integration samples can be run using the ``v2m_musca_s1_ns`` +The TF-M integration samples can be run using the ``v2m_musca_s1/musca_s1/ns`` target. Please make sure all the requirements listed in the sample's description are met before building. .. zephyr-app-commands:: :zephyr-app: samples/tfm_integration/psa_crypto - :board: v2m_musca_s1_ns + :board: v2m_musca_s1/musca_s1/ns :goals: build To upload the build artifact to the board, first connect the Musca-S1 to your diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml index 194666cba50d30..7e99e0fc4eb47b 100644 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml @@ -1,4 +1,4 @@ -identifier: v2m_musca_s1 +identifier: v2m_musca_s1/musca_s1 name: ARM V2M MUSCA-S1 type: mcu arch: arm diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig b/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig index dd2b349173649e..59601296cfae30 100644 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_MUSCA_S1=y -CONFIG_SOC_V2M_MUSCA_S1=y CONFIG_RUNTIME_NMI=y CONFIG_ARM_TRUSTZONE_M=y CONFIG_ARM_MPU=y diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.dts b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts similarity index 100% rename from boards/arm/v2m_musca_s1/v2m_musca_s1_ns.dts rename to boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.dts diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml new file mode 100644 index 00000000000000..090f6996c580b2 --- /dev/null +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml @@ -0,0 +1,11 @@ +identifier: v2m_musca_s1/musca_s1/ns +name: ARM V2M MUSCA-S1 NonSecure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 511 +vendor: arm diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig new file mode 100644 index 00000000000000..d5c8f4180ac806 --- /dev/null +++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns_defconfig @@ -0,0 +1,7 @@ +# +# Copyright (c) 2019-2020 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.yaml deleted file mode 100644 index 7494e2aff38103..00000000000000 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: v2m_musca_s1_ns -name: ARM V2M MUSCA-S1 NonSecure -type: mcu -arch: arm -toolchain: - - zephyr - - gnuarmemb - - xtools -ram: 256 -flash: 511 -vendor: arm diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns_defconfig b/boards/arm/v2m_musca_s1/v2m_musca_s1_ns_defconfig deleted file mode 100644 index 146db80b6f8f93..00000000000000 --- a/boards/arm/v2m_musca_s1/v2m_musca_s1_ns_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2019-2020 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_MUSCA_S1=y -CONFIG_SOC_V2M_MUSCA_S1=y -CONFIG_ARM_TRUSTZONE_M=y -CONFIG_RUNTIME_NMI=y -CONFIG_TRUSTED_EXECUTION_NONSECURE=y -CONFIG_ARM_MPU=y - -# Serial -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/arm/verdin_imx8mp_m7/Kconfig.board b/boards/arm/verdin_imx8mp_m7/Kconfig.board deleted file mode 100644 index fb86601179c667..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# VERDIN_IMX8MP_M7 board - -# Copyright (c) 2023 Toradex -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_VERDIN_IMX8MP_M7 - bool "Toradex iMX8M Plus M7" - depends on SOC_SERIES_IMX8ML_M7 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/verdin_imx8mp_m7/Kconfig.defconfig b/boards/arm/verdin_imx8mp_m7/Kconfig.defconfig deleted file mode 100644 index 3c3ab2db770b28..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# VERDIN_IMX8MP_M7 board defconfig - -# Copyright (c) 2023 Toradex -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_VERDIN_IMX8MP_M7 - -config BOARD - default "verdin_imx8mp_m7" - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_VERDIN_IMX8MP_M7 diff --git a/boards/arm/verdin_imx8mp_m7/doc/index.rst b/boards/arm/verdin_imx8mp_m7/doc/index.rst deleted file mode 100644 index 455acb8c290aaa..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/doc/index.rst +++ /dev/null @@ -1,304 +0,0 @@ -.. _verdin_imx8mp_m7: - -Toradex Verdin iMX8M Plus SoM -############################# - -Overview -******** - -The Verdin iMX8M Plus is a Computer on Module (CoM) developed by Toradex. It is based on the NXP® -i.MX 8M Plus family of processors (or System on Chips - SoCs). - -The Verdin iMX8M Plus family consists of: - -+-------------------------------------------------+-----------------------+ -| CoM | SoC | -+=================================================+=======================+ -| Verdin iMX8M Plus Quad 8GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus Quad 4GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus Quad 4GB IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus Quad 2GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | -+-------------------------------------------------+-----------------------+ -| Verdin iMX8M Plus QuadLite 1GB IT | i.MX 8M Plus QuadLite | -+-------------------------------------------------+-----------------------+ - -Quoting NXP: - - The i.MX 8M Plus family focuses on machine learning and vision, advanced multimedia, and - industrial automation with high reliability. It is built to meet the needs of Smart Home, - Building, City and Industry 4.0 applications. - -The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside -a single Arm Cortex™-M7F microcontroller operating at 800 MHz. - -.. figure:: verdin_imx8mp_front.jpg - :align: center - :alt: Toradex Verdin iMX8M Plus - - Toradex Verdin iMX8M Plus (Credit: Toradex) - -Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and -energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1 -memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary -functions. This cache is housed within a single APR region. Facilitating debugging processes, the -cores support both real-time trace through the ETM system and static debugging via JTAG. -Furthermore, the platform features support for real-time trace capabilities, achieved through ARM's -CoreSight ETM modules, and also enables cross-triggering by utilizing CTI and CTM modules. - -The Arm® Cortex®-M7 microcontroller is indicated for Real-time control, combining high-performance -with a minimal interrupt latency. It stands out for its compatibility with existing Cortex-M profile -processors. The microcontroller employs an efficient in-order super-scalar pipeline, allowing -dual-issued instructions such as load/load and load/store pairs, thanks to its multiple memory -interfaces. These interfaces encompass Tightly-Coupled Memory (TCM), Harvard caches, and an AXI -master interface. The Arm Cortex-M7 Platform boasts features like a 32 KB L1 Instruction Cache, 32 -KB L1 Data Cache, Floating Point Unit (FPU) with FPv5 architecture support, and an Internal Trace -(TRC) mechanism. Furthermore, the chip supports 160 IRQs, and integrates crucial Arm CoreSight -components including ETM and CTI, dedicated to facilitating debug and trace functions. - -Hardware -******** - -- SoC name: NXP® i.MX 8M Plus -- CPU Type: 4x Arm Cortex™-A53 (1.6 GHz) -- Microcontroller: 1x Arm Cortex™-M7F (800 MHz) - -- Memory: - - - RAM -> A53: 1GB, 2GB, 4GB or 8GB - - RAM -> M7: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A53: Up to 32GB eMMC - -- Connectivity: - - - USB 3.1: 1x Host / 1x OTG (Gen 1) - - USB 2.0: 1x Host / 1x OTG - - Ethernet Gigabit with TSN (+2nd RGMII) - - Wi-Fi Dual-band 802.11ac 2x2 MU-MIMO - - Bluetooth 5 - - 5x I2C - - 3x SPI - - 1 QSPI - - 4x UART - - Up to 92 GPIO - - 4x Analog Input - - 2x CAN (FlexCAN) - -- Multimedia: - - - Neural Processing Unit (NPU) - - Image Signal Processor (ISP) - - 2D and 3D acceleration - - HDMI, MIPI-DSI and MIPI-CSI interface - -For more information about the Verdin iMX8M Plus and the i.MX 8M Plus SoC refer to these links: - -- `i.MX 8M Plus Applications Processor page`_ -- `Verdin iMX8M Plus homepage`_ -- `Verdin iMX8M Plus developer page`_ -- `Verdin Development Board developer page`_ -- `Verdin iMX8M Plus Datasheet`_ -- `Verdin Development Board Datasheet`_ - -Supported Features -================== - -The Zephyr verdin_imx8mp_m7 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | GPIO output | -| | | GPIO input | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - -- :zephyr_file:`boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig`, if you choose to use - the ITCM memory. - -- :zephyr_file:`boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig`, if you choose to use - the DDR memory. - -It is recommended to disable peripherals used by the M7 core on the Linux host. - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -UART ----- - -Zephyr is configured to use the UART4 by default, which is connected to the FTDI USB converter on -most Toradex carrier boards. - -This is also the UART connected to WiFi/BT chip in modules that have the WiFi/BT chip. Therefore, if -UART4 is used, WiFI/BT will not work properly. - -If the WiFi/BT is needed, then another UART should be used for Zephyr (UART1 for example). You can -change the UART by changing the ``zephyr,console`` and ``zephyr,shell-uart`` in the -:zephyr_file:`boards/arm/verdin_imx8mp_m7_itcm.dts` or -:zephyr_file:`boards/arm/verdin_imx8mp_m7_ddr.dts` file. - -+---------------+-----------------+---------------------------+ -| Board Name | SoC Name | Usage | -+===============+=================+===========================+ -| UART_1 | UART1 | General purpose UART | -+---------------+-----------------+---------------------------+ -| UART_4 | UART4 | Cortex-M4 debug UART | -+---------------+-----------------+---------------------------+ - -GPIO ----- - -All the GPIO banks available are enabled in the :zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. - -System Clock -============ - -The M7 Core is configured to run at a 800 MHz clock speed. - -Serial Port -=========== - -The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and the remaining are not -used/tested. - -Programming and Debugging -************************* - -The Verdin iMX8M Plus board doesn't have QSPI flash for the M7, and it needs to be started by the -A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in -reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can -perform these steps at bootloader level or after the Linux system has booted. - -The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and -DDR). These are the memory mapping for A53 and M7: - -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | -+============+=========================+========================+=======================+======================+ -| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ -| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | -+------------+-------------------------+------------------------+-----------------------+----------------------+ - -For more information about memory mapping see the `i.MX 8M Plus Applications Processor Reference -Manual`_ (section 2.1 to 2.3) - -At compilation time you have to choose which RAM will be used. To facilitate this process, there are -two targets available: - -- ``verdin_imx8mp_m7_itcm``, which uses the ITCM configuration. -- ``verdin_imx8mp_m7_ddr``, which uses the DDR configuration. - - -Starting the Cortex-M7 via U-Boot -================================= - -Load and run Zephyr on M7 from A53 using u-boot by copying the compiled ``zephyr.bin`` to the first -FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot -execution at prompt. - -Load the M7 binary onto the desired memory and start its execution using: - -ITCM -==== - -Loading the binary from an EXT4 partition: - -.. code-block:: shell - - ext4load mmc 2:2 ${loadaddr} //zephyr.bin - cp.b ${loadaddr} 0x7e0000 - bootaux 0x7e0000 - -DDR -=== - -Loading the binary from an EXT4 partition: - -.. code-block:: shell - - ext4load mmc 2:2 ${loadaddr} //zephyr.bin - cp.b ${loadaddr} 0x80000000 - bootaux 0x80000000 - -Debugging -========= - -Toradex Verdin iMX8M Plus SoM can be debugged by connecting an external JLink JTAG debugger to the -X56 debug connector and to the PC, or simply connecting a USB-C to X66 on the Verdin Development -Board. Then, the application can be debugged using the usual way. - -Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: verdin_imx8mp_m7_ddr - :goals: debug - -Open a serial terminal, step through the application in your debugger, and you -should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.4.0-2300-g03905f7e55d2 *** - Hello World! verdin_imx8mp_m7_ddr - -References -========== - -- `How to Load Compiled Binaries into Cortex-M`_ -- `Cortex-M JTAG Debugging`_ -- `NXP website`_ - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK - -.. _i.MX 8M Plus Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MPRM - -.. _How to Load Compiled Binaries into Cortex-M: - https://developer.toradex.com/software/real-time/cortex-m/how-to-load-binaries - -.. _Cortex-M JTAG Debugging: - https://developer.toradex.com/software/real-time/cortex-m/cortexm-jtag-debugging/ - -.. _i.MX 8M Plus Applications Processor page: - https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-plus-arm-cortex-a53-machine-learning-vision-multimedia-and-industrial-iot:IMX8MPLUS - -.. _Verdin iMX8M Plus homepage: - https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus - -.. _Verdin iMX8M Plus developer page: - https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-imx8m-plus - -.. _Verdin Development Board developer page: - https://developer.toradex.com/hardware/verdin-som-family/carrier-boards/verdin-development-board/ - -.. _Verdin iMX8M Plus Datasheet: - https://docs.toradex.com/110977-verdin_imx8m_plus_v1.1_datasheet.pdf - -.. _Verdin Development Board Datasheet: - https://docs.toradex.com/109463-verdin_development_board_datasheet_v1.1.pdf diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.dts b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.dts deleted file mode 100644 index 861077246fd04d..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2023 Toradex - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "verdin_imx8mp_m7-pinctrl.dtsi" -#include - -/ { - model = "Toradex Verdin iMX8M Plus M7"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* DDR */ - zephyr,flash = &ddr_code; - zephyr,sram = &ddr_sys; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.yaml b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.yaml deleted file mode 100644 index fc64d8c3db8859..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: verdin_imx8mp_m7_ddr -name: Toradex Verdin iMX8M Plus (DDR) -type: mcu -arch: arm -ram: 2048 -flash: 2048 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - uart diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig deleted file mode 100644 index 7c0d4073679355..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_ddr_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_VERDIN_IMX8MP_M7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_DDR=y -CONFIG_PINCTRL=y diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.dts b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.dts deleted file mode 100644 index 5744928f8a7f9d..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2023 Toradex - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "verdin_imx8mp_m7-pinctrl.dtsi" -#include - -/ { - model = "Toradex Verdin iMX8M Plus M7"; - compatible = "nxp,mimx8mp_evk"; - - chosen { - /* TCM */ - zephyr,flash = &itcm; - zephyr,sram = &dtcm; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&gpio3 { - status = "okay"; -}; - -&mailbox0 { - status = "okay"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.yaml b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.yaml deleted file mode 100644 index 8db4c170c5de93..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm.yaml +++ /dev/null @@ -1,18 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: verdin_imx8mp_m7_itcm -name: Toradex Verdin iMX8M Plus (ITCM) -type: mcu -arch: arm -ram: 128 -flash: 128 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - uart diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig b/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig deleted file mode 100644 index 52c354abc1f95a..00000000000000 --- a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7_itcm_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2023 Toradex -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX8ML_M7=y -CONFIG_SOC_MIMX8ML8=y -CONFIG_BOARD_VERDIN_IMX8MP_M7=y -CONFIG_CLOCK_CONTROL=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_CODE_ITCM=y -CONFIG_PINCTRL=y diff --git a/boards/arm/vmu_rt1170/CMakeLists.txt b/boards/arm/vmu_rt1170/CMakeLists.txt deleted file mode 100644 index 9e03e6cb024725..00000000000000 --- a/boards/arm/vmu_rt1170/CMakeLists.txt +++ /dev/null @@ -1,26 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if(CONFIG_NXP_IMX_RT_BOOT_HEADER) - zephyr_library() - set(RT1170_BOARD_DIR - "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1170") - if(CONFIG_BOOT_FLEXSPI_NOR) - # Include flash configuration block for RT1170 EVK from NXP's HAL. - # This configuration block may need modification if another flash chip is - # used on your custom board. See NXP AN12238 for more information. - zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) - zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) - zephyr_library_sources(flexspi_nor_config.c) - zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) - endif() -endif() - -if(CONFIG_MCUX_GPT_TIMER) - message(WARNING "You appear to be using the GPT hardware timer. " - "This timer will enable lower power modes, but at the cost of reduced " - "hardware timer resolution") -endif() diff --git a/boards/arm/vmu_rt1170/Kconfig.board b/boards/arm/vmu_rt1170/Kconfig.board deleted file mode 100644 index 53aa20f680077c..00000000000000 --- a/boards/arm/vmu_rt1170/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_VMU_RT1170 - bool "NXP VMU_RT1170" - depends on SOC_MIMXRT1176_CM7 - select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/arm/vmu_rt1170/Kconfig.defconfig b/boards/arm/vmu_rt1170/Kconfig.defconfig deleted file mode 100644 index 1c27b74b23e569..00000000000000 --- a/boards/arm/vmu_rt1170/Kconfig.defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# VMU_RT1170 board - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_VMU_RT1170 - -config BOARD - default "vmu_rt1170" if BOARD_VMU_RT1170 - -choice CODE_LOCATION - default CODE_FLEXSPI if BOARD_VMU_RT1170 -endchoice - -if DISK_DRIVERS - -config IMX_USDHC_DAT3_PWR_TOGGLE - default y - -endif # DISK_DRIVERS - -if FLASH - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 - default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 -endchoice - -endif #FLASH - -if NETWORKING - -config NET_L2_ETHERNET - default y if CPU_CORTEX_M7 # No cache memory support is required for driver - -config ETH_MCUX_PHY_RESET - default n - -config ETH_MCUX_RMII_EXT_CLK - default y - -endif # NETWORKING - - -endif # BOARD_VMU_RT1170 diff --git a/boards/arm/vmu_rt1170/flexspi_nor_config.c b/boards/arm/vmu_rt1170/flexspi_nor_config.c deleted file mode 100644 index 21523fc29d0d22..00000000000000 --- a/boards/arm/vmu_rt1170/flexspi_nor_config.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2019, MADMACHINE LIMITED - * - * refer to hal_nxp board file - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -/*! - * @brief ROM API init - * - * Get the bootloader api entry address. - */ -void ROM_API_Init(void); - -/*! - * @brief Initialize Serial NOR devices via FLEXSPI - * - * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. - * - * @param instance storage the instance of FLEXSPI. - * @param config A pointer to the storage for the driver runtime state. - * - * @retval kStatus_Success Api was executed successfully. - * @retval kStatus_InvalidArgument A invalid argument is provided. - * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. - * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. - * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout - */ -status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, struct flexspi_nor_config_t *config); - - - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) -__attribute__((section(".boot_hdr.conf"))) -#elif defined(__ICCARM__) -#pragma location = ".boot_hdr.conf" -#endif - -/* Config used for booting */ - -const struct flexspi_nor_config_t Qspiflash_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = - kFlexSPIReadSampleClk_LoopbackInternally, - .csHoldTime = 1u, - .csSetupTime = 1u, - .sflashPadType = kSerialFlash_1Pad, - .serialClkFreq = kFlexSpiSerialClk_80MHz, - .sflashA1Size = 64u * 1024u * 1024u, - .lookupTable = { - FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x03, RADDR_SDR, - FLEXSPI_1PAD, 0x18), - FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, - 0x04, STOP, - FLEXSPI_1PAD, 0), - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, -}; -#endif /* CONFIG_NXP_IMX_RT_BOOT_HEADER */ - -/* Config used for code execution */ -const struct flexspi_nor_config_t g_flash_fast_config = { - .memConfig = { - .tag = FLEXSPI_CFG_BLK_TAG, - .version = FLEXSPI_CFG_BLK_VERSION, - .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, - .csHoldTime = 1, - .csSetupTime = 1, - .deviceModeCfgEnable = 1, - .deviceModeType = kDeviceConfigCmdType_Spi2Xpi, - .waitTimeCfgCommands = 1, - .deviceModeSeq = { - .seqNum = 1, - .seqId = 6, /* See Lookup table for more details */ - .reserved = 0, - }, - .deviceModeArg = 2, /* Enable OPI DDR mode */ - .controllerMiscOption = - (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) - | (1u << kFlexSpiMiscOffset_DdrModeEnable), - .deviceType = kFlexSpiDeviceType_SerialNOR, - .sflashPadType = kSerialFlash_8Pads, - .serialClkFreq = kFlexSpiSerialClk_200MHz, - .sflashA1Size = 64ul * 1024u * 1024u, - .busyOffset = 0u, - .busyBitPolarity = 0u, - .lookupTable = { - /* Read */ - [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, - 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), - [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, - 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04), - [0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, - 0x04, STOP, FLEXSPI_1PAD, 0x00), - - /* Write enable SPI */ - [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x06, STOP, FLEXSPI_1PAD, 0x00), - - /*Write Configuration Register 2 =01, Enable OPI DDR mode*/ - [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00), - [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00), - [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, - 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01), - - }, - }, - .pageSize = 256u, - .sectorSize = 4u * 1024u, - .blockSize = 64u * 1024u, - .isUniformBlockSize = false, - .ipcmdSerialClkFreq = 1, - .serialNorType = 2, - .reserve2[0] = 0x7008200, -}; - - -__ramfunc int imxrt_reclock_initialize(void) -{ - const uint32_t instance = 1; - - volatile struct flexspi_nor_config_t bootConfig; - - memcpy((struct flexspi_nor_config_t *)&bootConfig, &g_flash_fast_config, - sizeof(struct flexspi_nor_config_t)); - bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG; - - ROM_API_Init(); - - ROM_FLEXSPI_NorFlash_Init(instance, (struct flexspi_nor_config_t *)&bootConfig); - - return 0; -} - -SYS_INIT(imxrt_reclock_initialize, PRE_KERNEL_1, 0); diff --git a/boards/arm/w5500_evb_pico/Kconfig.board b/boards/arm/w5500_evb_pico/Kconfig.board deleted file mode 100644 index 9c863d899dc2dc..00000000000000 --- a/boards/arm/w5500_evb_pico/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# Copyright (c) 2023 Ian Wakely -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_W5500_EVB_PICO - bool "Wiznet W5500 Evaluation Board" - depends on SOC_RP2040 diff --git a/boards/arm/w5500_evb_pico/Kconfig.defconfig b/boards/arm/w5500_evb_pico/Kconfig.defconfig deleted file mode 100644 index 5e569b40cc9e41..00000000000000 --- a/boards/arm/w5500_evb_pico/Kconfig.defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# Copyright (c) 2023 Ian Wakely -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_W5500_EVB_PICO - -config BOARD - default "w5500_evb_pico" if BOARD_W5500_EVB_PICO - -config RP2_FLASH_W25Q080 - default y - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -if I2C_DW - -config I2C_DW_CLOCK_SPEED - default 125 - -endif #I2C_DW - -config USB_SELF_POWERED - default n - -endif # BOARD_W5500_EVB_PICO diff --git a/boards/arm/warp7_m4/Kconfig.board b/boards/arm/warp7_m4/Kconfig.board deleted file mode 100644 index 14ab7c1023f88a..00000000000000 --- a/boards/arm/warp7_m4/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# WaRP7 iMX7S M4 board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WARP7_M4 - bool "WaRP7 iMX7 Solo" - depends on SOC_SERIES_IMX7_M4 - select SOC_PART_NUMBER_MCIMX7S3DVK08SA diff --git a/boards/arm/warp7_m4/Kconfig.defconfig b/boards/arm/warp7_m4/Kconfig.defconfig deleted file mode 100644 index 6086acb474b834..00000000000000 --- a/boards/arm/warp7_m4/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# WaRP7 iMX7S M4 board - -# Copyright (c) 2018, Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WARP7_M4 - -config BOARD - default "warp7_m4" - -config FXOS8700_DRDY_INT1 - default y - depends on FXOS8700_TRIGGER - -config FXAS21002_DRDY_INT1 - default y - depends on FXAS21002_TRIGGER - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -endif # BOARD_WARP7_M4 diff --git a/boards/arm/warp7_m4/doc/index.rst b/boards/arm/warp7_m4/doc/index.rst deleted file mode 100644 index dc863e99d5ac6a..00000000000000 --- a/boards/arm/warp7_m4/doc/index.rst +++ /dev/null @@ -1,345 +0,0 @@ -.. _warp7_m4: - -WaRP7 - Next Generation IoT and Wearable Development Platform -############################################################# - -Overview -******** - -The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7 -core and Single Cortex M4 core. -Zephyr was ported to run on the M4 core. In a later release, it will also -communicate with the A7 core (running Linux) via RPmsg. - - -.. image:: warp7_m4.jpg - :align: center - :alt: WaRP7-iMX7S - -Hardware -******** - -The WaRP7 Platform is composed of a CPU and IO board. - -WaRP7 IO Board -============== - -- 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface) -- 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface) -- Altimeter: NXP MPL3115A2 (I2C4 interface) -- NXP NTAG NT3H1101 (I2C2 interface) -- Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces) -- S1 - Reset Button (POR_B signal) -- S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal) -- S3 - On/Off (MX7_ONOFF signal) -- Board to board connector (34 configurable pins) -- mikroBUS expansion connector -- 10-pin needle JTAG Connector -- Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4) -- MIPI DSI 1 lane Connector -- LCD Touch Connector (I2C2 interface) -- Audio Jack: Mic and Stereo Headphone - -WaRP7 CPU Board -=============== - -- CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and - Single Cortex M4 (200MHz) core -- Memory - - - RAM -> A7: 4GB (Kingston 08EMCP04) - - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) - - Flash -> A7: 8GB eMMC (Kingston 08EMCP04) -- Multimedia - - - MIPI CSI 1 lane connector with 5MP OV5640 camera module (I2C2 interface) -- Connectivity - - - Board to board connector (34 configurable pins) - - Micro USB 2.0 OTG connector (USB_OTG1 interface) - - Murata Type 1DX Wi-Fi IEEE 802.11b/g/n and Bluetooth 4.1 plus EDR - (SD1, UART3 SAI2 interfaces) -- Li-ion/Li-polymer Battery Charger: NXP BC3770 (I2C1 interface) -- Power management integrated circuit (PMIC): NXP PF3000 (I2C1 interface) - - -For more information about the i.MX7 SoC and WaRP7, see these references: - -- `i.MX 7 Series Website`_ -- `i.MX 7 Solo Datasheet`_ -- `i.MX 7 Solo Reference Manual`_ -- `WaRP7 Site`_ -- `WaRP7 Quick Start Guide`_ -- `WaRP7 User Guide`_ -- `WaRP7 GitHub repository`_ - -Supported Features -================== - -The WaRP7 configuration supports the following hardware features on the -Cortex M4 Core: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| SYSTICK | on-chip | systick | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -| | | fxas21002 polling; | -| | | fxas21002 trigger; | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/warp7_m4/warp7_m4_defconfig`` - -Other hardware features are not currently supported by the port. - -Connections and IOs -=================== - -The WaRP7 board Board was tested with the following pinmux controller -configuration. - -+---------------+---------------------+--------------------------------+ -| Board Name | SoC Name | Usage | -+===============+=====================+================================+ -| FT_TX2 | UART2_TXD | UART Console | -+---------------+---------------------+--------------------------------+ -| FT_RX2 | UART2_RXD | UART Console | -+---------------+---------------------+--------------------------------+ -| MKBUS_TX | UART6_TXD | UART | -+---------------+---------------------+--------------------------------+ -| MKBUS_RX | UART6_RXD | UART | -+---------------+---------------------+--------------------------------+ -| S2 | ENET1_RD1/GPIO7_IO1 | SW0 | -+---------------+---------------------+--------------------------------+ -| I2C4_SDA | I2C4_SDA | I2C / FXOS8700 / FXAS21002 | -+---------------+---------------------+--------------------------------+ -| I2C4_SCL | I2C4_SCL | I2C / FXOS8700 / FXAS21002 | -+---------------+---------------------+--------------------------------+ -| SENSOR_INT_B | ENET1_RD0/GPIO7_IO0 | FXOS8700 INT1 / FXAS21002 INT1 | -+---------------+---------------------+--------------------------------+ - -System Clock -============ - -The M4 Core is configured to run at a 200 MHz clock speed. - -Serial Port -=========== - -The iMX7S SoC has seven UARTs. The number 2 is configured for the console and -the number 6 is used in the mikroBUS connector. - -Programming and Debugging -************************* - -The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by -the A7 core. The A7 core is responsible to load the M4 binary application into -the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and -get the M4 out of reset. -The A7 can perform these steps at bootloader level or after the Linux system -has booted. - -The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and -M4: - -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | -+============+=======================+========================+=======================+======================+ -| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ -| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | -+------------+-----------------------+------------------------+-----------------------+----------------------+ - - -References -========== - -- `i.MX 7 Solo Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) -- `Toradex Wiki`_ - - -At compilation time you have to choose which RAM will be used. This -configuration is done in the file ``boards/arm/warp7_m4/warp7_m4.dts`` with -"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available -configurations are: - -.. code-block:: none - - "zephyr,flash" - - &ddr_code - - &tcml_code - - &ocram_code - - &ocram_s_code - - &ocram_pxp_code - - &ocram_epdc_code - - "zephyr,sram" - - &ddr_sys - - &tcmu_sys - - &ocram_sys - - &ocram_s_sys - - &ocram_pxp_sys - - &ocram_epdc_sys - - -Below you will find the instructions to load and run Zephyr on M4 from A7 using -u-boot. - -Connect both micro USB interfaces into the PC. In one USB interface you will -have 2 USB serial ports, the first one is the A7 console and the second is the -M4 console for Zephyr with both configured to work at 115200 8N1. -The other USB interface is used to power the CPU and IO boards and is connected -to the USB OTG interface of the i.MX7S. - -After powering up the platform stop the u-boot execution on the A7 core and -expose the eMMC as mass storage with the following command in the u-boot -prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT -partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the -u-boot prompt. -Set the u-boot environment variables and run the zephyr.bin from the -appropriated memory configured in the Zephyr compilation: - -.. code-block:: console - - setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' - # TCML - setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' - setenv bootm4tcml 'run m4tcml && run bootm4' - run bootm4tcml - # TCMU - setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' - setenv bootm4tcmu 'run m4tcmu && run bootm4' - run bootm4tcmu - # OCRAM - setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' - setenv bootm4ocram 'run m4ocram && run bootm4' - run bootm4ocram - # OCRAM_S - setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' - setenv bootm4ocrams 'run m4ocrams && run bootm4' - run bootm4ocrams - # DDR - setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' - setenv bootm4ddr 'run m4ddr && run bootm4' - run bootm4ddr - - -Debugging -========= - -Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. - -To run Zephyr Binary using J-Link, create the following script to get the -Program Counter and Stack Pointer from ``zephyr.bin``. - -get-pc-sp.sh: -.. code-block:: console - - #!/bin/sh - - firmware=$1 - - pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') - sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') - - echo pc=$pc - echo sp=$sp - - -Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` -.. code-block:: console - - pc=00900f01 - sp=00905020 - -Plug in the J-Link into the board and PC and run the J-Link command line tool: - -.. code-block:: console - - /usr/bin/JLinkExe -device Cortex-M4 -if JTAG \ - -speed 4000 -autoconnect 1 -jtagconf -1,-1 \ - -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript - -The following steps are necessary to run the zephyr.bin: - -1. Put the M4 core in reset -2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) -3. Set PC (Program Counter) -4. Set SP (Stack Pointer) -5. Get the M4 core out of reset - -Issue the following commands inside J-Link commander: - -.. code-block:: console - - w4 0x3039000C 0xAC - loadfile zephyr.bin,0x00900000 - w4 0x00180000 00900f01 - w4 0x00180004 00905020 - w4 0x3039000C 0xAA - -With these mechanisms, applications for the ``warp7_m4`` board -configuration can be built and debugged in the usual way (see -:ref:`build_an_application` and :ref:`application_run` for more details). - -References -========== - -- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ -- `J-Link iMX7D Instructions`_ - -.. _WaRP7 Site: - https://www.element14.com/warp7 - -.. _WaRP7 User Guide: - https://github.com/WaRP7/WaRP7-User-Guide/releases/download/v1.3/User_Guide_Manual_v1-3.pdf - -.. _WaRP7 Quick Start Guide: - https://www.nxp.com/docs/en/supporting-information/WARP7-LEAFLET-QSG.pdf - -.. _WaRP7 GitHub repository: - https://github.com/WaRP7 - -.. _i.MX 7 Series Website: - https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 - -.. _i.MX 7 Solo Datasheet: - https://www.nxp.com/docs/en/data-sheet/IMX7SCEC.pdf - -.. _i.MX 7 Solo Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX7SRM - -.. _J-Link Tools: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack - -.. _NXP iMX7D Connect CortexM4.JLinkScript: - https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript - -.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: - https://www.nxp.com/docs/en/application-note/AN5317.pdf - -.. _J-Link iMX7D Instructions: - https://wiki.segger.com/IMX7D - -.. _Toradex Wiki: - https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/warp7_m4/warp7_m4.dts b/boards/arm/warp7_m4/warp7_m4.dts deleted file mode 100644 index 44f8153d749b13..00000000000000 --- a/boards/arm/warp7_m4/warp7_m4.dts +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (c) 2018, Diego Sueiro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "warp7_m4-pinctrl.dtsi" -#include - -/ { - model = "WaRP7 IMX7S board"; - compatible = "nxp,mcimx7d_m4"; - - aliases { - sw0 = &user_switch_1; - magn0 = &fxos8700; - accel0 = &fxos8700; - }; - - chosen { - zephyr,flash = &tcml_code; - zephyr,sram = &tcmu_sys; - zephyr,console = &uart2; - zephyr,shell-uart = &uart2; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_switch_1: user_sw_1 { - gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; - label = "User SW1"; - zephyr,code = ; - }; - }; -}; - -&uart2 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&uart6 { - status = "okay"; - current-speed = <115200>; - modem-mode = <0>; - pinctrl-0 = <&uart6_default>; - pinctrl-names = "default"; -}; - -&gpio7 { - status = "okay"; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&i2c2 { - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&i2c3 { - pinctrl-0 = <&i2c3_default>; - pinctrl-names = "default"; -}; - -&i2c4 { - status = "okay"; - pinctrl-0 = <&i2c4_default>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - }; - - fxas21002@20 { - compatible = "nxp,fxas21002"; - reg = <0x20>; - int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; - }; - -}; - -&mub { - status = "okay"; -}; diff --git a/boards/arm/warp7_m4/warp7_m4.yaml b/boards/arm/warp7_m4/warp7_m4.yaml deleted file mode 100644 index 67ed8dc274578c..00000000000000 --- a/boards/arm/warp7_m4/warp7_m4.yaml +++ /dev/null @@ -1,24 +0,0 @@ -# -# Copyright (c) 2018, Diego Sueiro -# -# SPDX-License-Identifier: Apache-2.0 -# - -identifier: warp7_m4 -name: WaRP7 IMX7S -type: mcu -arch: arm -ram: 32 -flash: 32 -toolchain: - - zephyr - - gnuarmemb - - xtools -testing: - ignore_tags: - - net - - bluetooth -supported: - - gpio - - i2c -vendor: nxp diff --git a/boards/arm/warp7_m4/warp7_m4_defconfig b/boards/arm/warp7_m4/warp7_m4_defconfig deleted file mode 100644 index 25281eb93ac27c..00000000000000 --- a/boards/arm/warp7_m4/warp7_m4_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2018, Diego Sueiro -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_SERIES_IMX7_M4=y -CONFIG_SOC_MCIMX7_M4=y -CONFIG_BOARD_WARP7_M4=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_CONSOLE=y -CONFIG_XIP=y -CONFIG_PINCTRL=y diff --git a/boards/arm/waveshare_open103z/Kconfig.board b/boards/arm/waveshare_open103z/Kconfig.board deleted file mode 100644 index ea48f05c767ae3..00000000000000 --- a/boards/arm/waveshare_open103z/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Waveshare Open103Z board configuration - -# Copyright (c) 2020 Stefano Manni -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WAVESHARE_OPEN103Z - bool "Waveshare OPEN103Z Development Board" - depends on SOC_STM32F103XE diff --git a/boards/arm/waveshare_open103z/Kconfig.defconfig b/boards/arm/waveshare_open103z/Kconfig.defconfig deleted file mode 100644 index 4a2b56b826ae24..00000000000000 --- a/boards/arm/waveshare_open103z/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Waveshare Open103Z board configuration - -# Copyright (c) 2020 Stefano Manni -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WAVESHARE_OPEN103Z - -config BOARD - default "waveshare_open103z" - -endif # BOARD_WAVESHARE_OPEN103Z diff --git a/boards/arm/we_ophelia1ev_nrf52805/Kconfig b/boards/arm/we_ophelia1ev_nrf52805/Kconfig deleted file mode 100644 index 5c6bc44014fa2d..00000000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Ophelia-I EV nRF52805 board configuration - -# Copyright (c) 2020 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - depends on BOARD_WE_OPHELIA1EV_NRF52805 diff --git a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.board b/boards/arm/we_ophelia1ev_nrf52805/Kconfig.board deleted file mode 100644 index c2709b066bb5c4..00000000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WE_OPHELIA1EV_NRF52805 - bool "we_ophelia1ev_nrf52805" - depends on SOC_NRF52805_CAAA diff --git a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.defconfig b/boards/arm/we_ophelia1ev_nrf52805/Kconfig.defconfig deleted file mode 100644 index b0a71cc39493cc..00000000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_OPHELIA1EV_NRF52805 - -config BOARD - default "we_ophelia1ev_nrf52805" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/we_ophelia1ev_nrf52805/doc/index.rst b/boards/arm/we_ophelia1ev_nrf52805/doc/index.rst deleted file mode 100644 index ea523c2fcf26c2..00000000000000 --- a/boards/arm/we_ophelia1ev_nrf52805/doc/index.rst +++ /dev/null @@ -1,115 +0,0 @@ -.. _we_ophelia1ev_nrf52805: - -Ophelia-I EV NRF52805 -##################### - -Overview -******** - -The we_ophelia1ev_nrf52805 board is an evaluation board of the Ophelia-I radio module. -It provides support for the Nordic Semiconductor nRF52805 ARM CPU and -the following devices: - -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/we_ophelia1ev_nrf52805.jpg - :align: center - :alt: Ophelia-I EV - - Ophelia-I EV (Credit: Würth Elektronik) - -Hardware -******** - -The Ophelia-I uses the internal low frequency RC oscillator -and provides the so called smart antenna connection, that allows -to choose between the module's integrated PCB antenna and an external -antenna that can be connected to the available SMA connector. - -Supported Features -================== - -The we_ophelia1ev_nrf52805 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Programming and Debugging -************************* - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board nRF52 DK -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: nrf52dk_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - -References -********** - -.. target-notes:: - -.. _Ophelia-I radio module website: https://www.we-online.com/katalog/de/OPHELIA-I -.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 diff --git a/boards/arm/we_proteus2ev_nrf52832/Kconfig.board b/boards/arm/we_proteus2ev_nrf52832/Kconfig.board deleted file mode 100644 index 98f30de1fee7b8..00000000000000 --- a/boards/arm/we_proteus2ev_nrf52832/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WE_PROTEUS2EV_NRF52832 - bool "we_proteus2ev_nrf52832" - depends on SOC_NRF52832_CIAA diff --git a/boards/arm/we_proteus2ev_nrf52832/Kconfig.defconfig b/boards/arm/we_proteus2ev_nrf52832/Kconfig.defconfig deleted file mode 100644 index 52437ae72dbd1b..00000000000000 --- a/boards/arm/we_proteus2ev_nrf52832/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS2EV_NRF52832 - -config BOARD - default "we_proteus2ev_nrf52832" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/we_proteus2ev_nrf52832/doc/index.rst b/boards/arm/we_proteus2ev_nrf52832/doc/index.rst deleted file mode 100644 index 316d961c647403..00000000000000 --- a/boards/arm/we_proteus2ev_nrf52832/doc/index.rst +++ /dev/null @@ -1,162 +0,0 @@ -.. _we_proteus2ev_nrf52832: - -Würth Elektronik Proteus-II-EV -############################## - -Overview -******** - -The Proteus-II-EV hardware provides -support for the Proteus-II radio module that uses the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and -the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/we_proteus2ev_nrf52832.jpg - :align: center - :alt: Proteus-II EV - - Proteus-II-EV (Credit: Würth Elektronik) - -More information about the radio module can be found the Würth Elektronik web page https://www.we-online.com/katalog/de/PROTEUS-II . - - -Hardware -******** - -Proteus-II radio module provides only the internal oscillators. The frequency of the slow clock -is 32.768 kHz. The frequency of the main clock is 32 MHz. - -Supported Features -================== - -The we_proteus2ev_nrf52832 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not supported by the Zephyr kernel. - -Connections and IOs -=================== - -LED ---- - -* LED1 = P0.00 -* LED2 = P0.01 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.29 - - -Programming and Debugging -************************* - -Applications for the ``we_proteus2ev_nrf52832`` board configuration can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board Proteus-II-EV -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: we_proteus2ev_nrf52832 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a -Segger IC. - - -Testing the LEDs and buttons in the Proteus-II-EV -************************************************* - -There are 2 samples that allow you to test that the buttons (switches) and LEDs on -the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts`. - -References -********** - -.. target-notes:: - -.. _Proteus-II radio module website: https://www.we-online.com/katalog/de/PROTEUS-II -.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/we_proteus3ev_nrf52840/Kconfig b/boards/arm/we_proteus3ev_nrf52840/Kconfig deleted file mode 100644 index 415c14238bf270..00000000000000 --- a/boards/arm/we_proteus3ev_nrf52840/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Proteus-III-EV board configuration - -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS3EV_NRF52840 - -config BOARD_ENABLE_DCDC - bool "DCDC mode" - select SOC_DCDC_NRF52X - default y - -config BOARD_ENABLE_DCDC_HV - bool "High Voltage DCDC converter" - select SOC_DCDC_NRF52X_HV - default y - -endif # BOARD_WE_PROTEUS3EV_NRF52840 diff --git a/boards/arm/we_proteus3ev_nrf52840/Kconfig.board b/boards/arm/we_proteus3ev_nrf52840/Kconfig.board deleted file mode 100644 index e59eb93e9c2398..00000000000000 --- a/boards/arm/we_proteus3ev_nrf52840/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WE_PROTEUS3EV_NRF52840 - bool "we_proteus3ev_nrf52840" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/we_proteus3ev_nrf52840/Kconfig.defconfig b/boards/arm/we_proteus3ev_nrf52840/Kconfig.defconfig deleted file mode 100644 index 8e1fa9443b4ba0..00000000000000 --- a/boards/arm/we_proteus3ev_nrf52840/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_WE_PROTEUS3EV_NRF52840 - -config BOARD - default "we_proteus3ev_nrf52840" - -config BT_CTLR - default BT - -endif diff --git a/boards/arm/we_proteus3ev_nrf52840/doc/index.rst b/boards/arm/we_proteus3ev_nrf52840/doc/index.rst deleted file mode 100644 index 608f366716adef..00000000000000 --- a/boards/arm/we_proteus3ev_nrf52840/doc/index.rst +++ /dev/null @@ -1,164 +0,0 @@ -.. _we_proteus3ev_nrf52840: - -Würth Elektronik Proteus-III-EV -############################### - -Overview -******** - -The Proteus-III-EV (evaluation board) hardware provides support -for the Proteus-III radio module that uses the Nordic Semiconductor -nRF52840 ARM Cortex-M4F CPU and the following devices: - -* :abbr:`ADC (Analog to Digital Converter)` -* CLOCK -* FLASH -* :abbr:`GPIO (General Purpose Input Output)` -* :abbr:`I2C (Inter-Integrated Circuit)` -* :abbr:`MPU (Memory Protection Unit)` -* :abbr:`NVIC (Nested Vectored Interrupt Controller)` -* :abbr:`PWM (Pulse Width Modulation)` -* RADIO (Bluetooth Low Energy and 802.15.4) -* :abbr:`RTC (nRF RTC System Clock)` -* Segger RTT (RTT Console) -* :abbr:`SPI (Serial Peripheral Interface)` -* :abbr:`UART (Universal asynchronous receiver-transmitter)` -* :abbr:`WDT (Watchdog Timer)` - -.. figure:: img/we_proteus3ev_nrf52840.jpg - :align: center - :alt: Proteus-III EV - - Proteus-III EV (Credit: Würth Elektronik) - -More information about the radio module can be found the Würth Elektronik -web page https://www.we-online.com/katalog/de/PROTEUS-III . - - -Hardware -******** - -Proteus-III radio module provides only the internal oscillators. The -frequency of the slow clock is 32.768 kHz. The frequency of the main -clock is 32 MHz. - -Supported Features -================== - -The we_proteus3ev_nrf52840 board configuration supports the following -hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| RTT | Segger | console | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features are not supported by the Zephyr kernel. - -Connections and IOs -=================== - -LED ---- - -* LED1 = P0.00 -* LED2 = P0.01 - -Push buttons ------------- - -* BUTTON1 = SW1 = P0.03 - -Programming and Debugging -************************* - -Applications for the ``we_proteus3ev_nrf52840`` board configuration can be -built, flashed, and debugged in the usual way. See -:ref:`build_an_application` and :ref:`application_run` for more details on -building and running. - -Flashing -======== - -Follow the instructions in the :ref:`nordic_segger` page to install -and configure all the necessary software. Further information can be -found in :ref:`nordic_segger_flashing`. Then build and flash -applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board Proteus-III-EV -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: we_proteus3ev_nrf52840 - :goals: build flash - -Debugging -========= - -Refer to the :ref:`nordic_segger` page to learn about debugging Nordic -boards with a Segger IC. - -Testing the LEDs and buttons in the Proteus-III-EV -************************************************** - -There are 2 samples that allow you to test that the buttons (switches) and -LEDs on the board are working properly with Zephyr: - -.. code-block:: console - - samples/basic/blinky - samples/basic/button - -You can build and flash the examples to make sure Zephyr is running correctly -on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.dts`. - -References -********** - -.. target-notes:: - -.. _Proteus-III radio module website: https://www.we-online.com/katalog/de/PROTEUS-III -.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com -.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html -.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/arm/weact_stm32g431_core/Kconfig.board b/boards/arm/weact_stm32g431_core/Kconfig.board deleted file mode 100644 index 9886fd64702779..00000000000000 --- a/boards/arm/weact_stm32g431_core/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2023 Andreas Sandberg -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_WEACT_STM32G431_CORE - bool "WeAct Studio STM32G431 Core Board" - depends on SOC_STM32G431XX diff --git a/boards/arm/weact_stm32g431_core/Kconfig.defconfig b/boards/arm/weact_stm32g431_core/Kconfig.defconfig deleted file mode 100644 index 25d65455013564..00000000000000 --- a/boards/arm/weact_stm32g431_core/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2023 Andreas Sandberg -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_WEACT_STM32G431_CORE - -config BOARD - default "weact_stm32g431_core" - -endif diff --git a/boards/arm/weact_stm32g431_core/doc/index.rst b/boards/arm/weact_stm32g431_core/doc/index.rst deleted file mode 100644 index 2d367ba280827e..00000000000000 --- a/boards/arm/weact_stm32g431_core/doc/index.rst +++ /dev/null @@ -1,147 +0,0 @@ -.. _weact_stm32g431_core: - -WeAct Studio STM32G431 Core Board -################################# - -The WeAct STM32G431 Core Board is a low-cost bare-bones STM32G431-based development -board. See the `STM32G431CB website`_ for more information about the MCU. More information -about the board, including schematics, is available from the `WeAct GitHub`_. - -Modifications USB-C Power Delivery -********************************** - -The board does not support USB-C PD in its standard configuration. To enable USB-C PD, CC1 -and CC2 need to be disconnected from their pull-down resistors and be connected to PB6 and -PB4 respectively. Dead battery support requires PA9 and PA10 to be routed to CC1 and -CC2. VBUS also needs to be connected to the MCU through a voltage divider. - -The pull-downs are disconnected by removing the zero-Ohm resistors on SB8 and SB9 next to -the USB-C connector. SB3, SB5, SB6, and SB7 then need to be closed to connect the CCx -lines to the MCU. The voltage divider is connected to PB2 by closing SB4. - -After these modifications have been made, PA9, PA10, PB2, PB4, and PB6 should be -considered reserved for USB-C and not available for other applications. - -.. warning:: - The internal USB DFU boot loader may not work correctly with machines that respect USB - PD signaling unless dead battery support has been enabled. A USB-C to USB-A adapter or - programming using the SWD port can be used as a workaround. - - -Supported Features -================== - -The Zephyr weact_stm32g431_core board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| ADC | on-chip | ADC Controller | -+------------+------------+-------------------------------------+ -| USB | on-chip | USB device | -+------------+------------+-------------------------------------+ -| UCPD | on-chip | ucpd | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: - - ``boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig`` - -Pin Mapping -=========== - -Default Zephyr Peripheral Mapping: ----------------------------------- - -- UART_2 TX/RX : PA2/PA3 -- UCPD1 CCx : PB6/PB4 (not connected by default) -- UCPD1 DBCCx : PA9/PA10 (not connected by default) -- BUTTON (User) : PC13 -- BUTTON (BOOT0) : PB8 -- LED0 : PC6 -- ADC (VBUS) : PB2 - -The ADC is disabled by default since the VBUS voltage divider is not connected in the -board's standard configuration. - - -Hardware Configuration ----------------------- -+---------------+---------+-----------------------------------------------+ -| Solder bridge | Default | Description | -+===============+=========+===============================================+ -| SB1/SB2 | Open | Route PC14/PC15 (LSE) to header | -+---------------+---------+-----------------------------------------------+ -| SB6/SB7 | Open | Connect PB4/PB6 (UCPD1_CCx) to USB-C CCx pins | -+---------------+---------+-----------------------------------------------+ -| SB3/SB5 | Open | Connect PA9/PA10 (UCPD1_DBCCx) to to PB6/PB4 | -+---------------+---------+-----------------------------------------------+ -| SB4 | Open | Connect PB2 to VBUS voltage divider | -+---------------+---------+-----------------------------------------------+ -| SB8/SB9 | Closed | Connect USB-CCx to pull-down resistors | -+---------------+---------+-----------------------------------------------+ -| SB10 | Open | VBUS protection diode bypass | -+---------------+---------+-----------------------------------------------+ - - -Clock Sources -------------- - -The board has two external oscillators. The frequency of the slow clock (LSE) is 32.768 -kHz. The frequency of the main clock (HSE) is 8 MHz. - -The default configuration sources the system clock from the PLL, which is derived from -HSE, and is set at 144 MHz. The 48 MHz clock used by the USB interface is derived from the -PLL instead of the internal 48 MHz oscillator. - -Programming and Debugging -************************* - -The MCU is normally programmed using the ROM bootloader or the exposed SWD port. - -Please note that some laptops may not detect the ROM bootloader correctly if the CCx -pull-downs have been disconnected by opening SB8 and SB9 unless dead battery support has -been enabled by closing SB3 and SB5. A USB-C to USB-A adapter can be used as a workaround -if this is a problem. - -Flashing an Application -======================= - -Connect a USB-C cable and the board should power ON. Force the board into DFU mode by -keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. - -The dfu-util runner is supported on this board and so a sample can be built and tested -easily. - -.. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: weact_stm32g431_core - :goals: build flash - -Debugging -========= - -The board can be debugged by installing the included 100 mil (0.1 inch) header, and -attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO pins on that header. - - -References -********** - -.. target-notes:: - -.. _WeAct GitHub: - https://github.com/WeActStudio/WeActStudio.STM32G431CoreBoard - -.. _STM32G431CB website: - https://www.st.com/en/microcontrollers-microprocessors/stm32g431cb.html - -.. _STM32F401x reference manual: - https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/wio_terminal/Kconfig.board b/boards/arm/wio_terminal/Kconfig.board deleted file mode 100644 index cec329c248f40c..00000000000000 --- a/boards/arm/wio_terminal/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Joel Guittet -# Wio Terminal board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_WIO_TERMINAL - bool "Wio Terminal" - depends on SOC_PART_NUMBER_SAMD51P19A diff --git a/boards/arm/wio_terminal/Kconfig.defconfig b/boards/arm/wio_terminal/Kconfig.defconfig deleted file mode 100644 index cca0d78a232cfa..00000000000000 --- a/boards/arm/wio_terminal/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 Joel Guittet -# Wio Terminal board configuration - -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "wio_terminal" - depends on BOARD_WIO_TERMINAL - -config LV_COLOR_16_SWAP - default y if LVGL diff --git a/boards/arm/wio_terminal/doc/index.rst b/boards/arm/wio_terminal/doc/index.rst deleted file mode 100644 index 4b11a461323eab..00000000000000 --- a/boards/arm/wio_terminal/doc/index.rst +++ /dev/null @@ -1,213 +0,0 @@ -.. _wio_terminal: - -Wio Terminal -############ - -Overview -******** - -The Wio Terminal is a small (72 mm x 57 mm x 12 mm) and powerful ARM board with -wireless connectivity (2.4G/5G dual-band Wi-Fi and BLE 5.0), LCD display, -USB C port, FPC connector, microSD card slot, Raspberry Pi compatible 40-pins -header and 2 Grove connectors. - -.. image:: img/wio_terminal.png - :width: 500px - :align: center - :alt: Seeed Studio Wio Terminal - -Hardware -******** - -- ATSAMD51P19 ARM Cortex-M4F processor at 120 MHz -- 512 KiB flash memory and 192 KiB of RAM -- 4 MiB external flash -- MicroSD card slot -- RTL8720DN 2.4G/5G Dual Bands Wireless and BLE5.0 Combo Module -- 2.4inch LCD display -- LIS3DH accelerometer -- Microphone 1.0V-10V -42dB -- Speaker ≥78dB @10cm 4000Hz -- Light Sensor 400-1050nm -- Infrared Emitter 940nm -- GPIO 40 pin (Raspberry Pi compatible) -- 2x Grove connectors -- 1x user LED -- 3x user buttons -- 5-way user button -- Power/Reset/Boot mode switch -- Native USB port - -Supported Features -================== - -The wio_terminal board configuration supports the following hardware features: - -.. list-table:: - :header-rows: 1 - - * - Interface - - Controller - - Driver / Component - * - NVIC - - on-chip - - Nested vector interrupt controller - * - Flash - - on-chip - - Can be used with LittleFS to store files - * - SYSTICK - - on-chip - - Systick - * - WDT - - on-chip - - Watchdog - * - GPIO - - on-chip - - I/O ports - * - USART - - on-chip - - Serial port - * - I2C - - on-chip - - Inter-Integrated Circuit - * - SPI - - on-chip - - Serial Peripheral Interface port - * - TRNG - - on-chip - - True Random Number Generator - * - HWINFO - - on-chip - - Unique 128 bit serial number - * - RTC - - on-chip - - Real-Time Counter - * - USB - - on-chip - - USB device - * - PWM - - on-chip - - PWM - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the Kconfig file -:zephyr_file:`boards/arm/wio_terminal/wio_terminal_defconfig`. - -Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. -To use the RTC, set :kconfig:option:`CONFIG_CORTEX_M_SYSTICK=n` and set -:kconfig:option:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided -by 7, i.e. no more than 4500. - -Connections and IOs -=================== - -The `Wio Terminal Getting started guide`_ has detailed information about the -board including `pinouts`_ and its `schematics`_. - -System Clock -============ - -The SAMD51 MCU is configured to use the 32.768 kHz internal oscillator with the -on-chip PLL generating the 120 MHz system clock. - -Serial Port -=========== - -Zephyr console output is available using the USB connector, which is used to -make the console available on PC as USB CDC class. - -USB Device Port -=============== - -The SAMD51 MCU has a USB device port that can be used to communicate with a -host PC. See the :ref:`usb-samples` sample applications for more, such as the -:zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual serial port that echos -characters back to the host PC. - -Programming and Debugging -************************* - -The Wio Terminal ships with an UF2 bootloader that is BOSSA compatible. The -bootloader can be entered by quickly tapping the reset button twice. - -The UF2 file is generated when building the application, and it is possible to -use it to flash the target. Enter the bootloader by quickly sliding the power -button twice, and copy the UF2 file to the USB mass storage device. The device -reboots on the new firmware after the UF2 file has finished transferring. - -Flashing -======== - -#. Build the Zephyr kernel and the :code:`button` sample application: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: build - :compact: - -#. Swipe the reset/power button down twice quickly to enter bootloader mode - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: flash - :compact: - - You should see the blue (user) LED flashing whenever you press the third - (counting from the top left) user button at the top of the Wio Terminal. - -Debugging -========= - -In addition to the built-in bootloader, the Wio Terminal can be flashed and -debugged using an SWD probe such as the Segger J-Link. - -#. Solder cables to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, - :code:`GND`, and :code:`3V3` pins. See `Test with SWD`_ for more - information. - -#. Connect the board to the probe by connecting the :code:`SWCLK`, - :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the - Wio Terminal to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, - :code:`GND`, and :code:`VTref` pins on the `J-Link`_. - -#. Flash the image: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: flash - :flash-args: -r openocd - :compact: - -#. Start debugging: - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/button - :board: wio_terminal - :goals: debug - :compact: - -References -********** - -.. target-notes:: - -.. _Wio Terminal Getting started guide: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/ - -.. _pinouts: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#pinout-diagram - -.. _schematics: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#resources - -.. _Test with SWD: - https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#test-with-swd - -.. _J-Link: - https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/xiao_ble/Kconfig.board b/boards/arm/xiao_ble/Kconfig.board deleted file mode 100644 index ca317fd24510ed..00000000000000 --- a/boards/arm/xiao_ble/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# XIAO BLE board configuration - -# Copyright (c) 2022 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XIAO_BLE - bool "XIAO BLE" - depends on SOC_NRF52840_QIAA diff --git a/boards/arm/xiao_ble/Kconfig.defconfig b/boards/arm/xiao_ble/Kconfig.defconfig deleted file mode 100644 index e0e6dbc28e89cf..00000000000000 --- a/boards/arm/xiao_ble/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# XIAO BLE board configuration - -# Copyright (c) 2022 Marcin Niestroj -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XIAO_BLE - -config BOARD - default "xiao_ble" - -config BT_CTLR - default BT - -endif # BOARD_XIAO_BLE - -if USB_DEVICE_STACK - -config UART_CONSOLE - default CONSOLE - -config USB_DEVICE_INITIALIZE_AT_BOOT - default y - -endif # USB_DEVICE_STACK diff --git a/boards/arm/xiao_ble/doc/index.rst b/boards/arm/xiao_ble/doc/index.rst deleted file mode 100644 index d4d4266311baee..00000000000000 --- a/boards/arm/xiao_ble/doc/index.rst +++ /dev/null @@ -1,219 +0,0 @@ -.. _xiao_ble: - -XIAO BLE (Sense) -################ - -Overview -******** - -The Seeed XIAO BLE (Sense) is a tiny (21 mm x 17.5 mm) Nordic Semiconductor -nRF52840 ARM Cortex-M4F development board with onboard LEDs, USB port, QSPI -flash, battery charger, and range of I/O broken out into 14 pins. - -.. figure:: img/xiao_ble.jpg - :align: center - :alt: XIAO BLE - -Hardware -******** - -- Nordic nRF52840 Cortex-M4F processor at 64MHz -- 2MB QSPI Flash -- RGB LED -- USB Type-C Connector, nRF52840 acting as USB device -- Battery charger BQ25101 -- Reset button -- Bluetooth antenna -- LSM6DS3TR-C 6D IMU (3D accelerometer and 3D gyroscope) (XIAO BLE Sense only) -- PDM microphone (XIAO BLE Sense only) - -Supported Features -================== - -The xiao_ble board configuration supports the following hardware features: - -+-----------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================+ -| ADC | on-chip | adc | -+-----------+------------+----------------------+ -| CLOCK | on-chip | clock_control | -+-----------+------------+----------------------+ -| FLASH | on-chip | flash, QSPI flash | -+-----------+------------+----------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+----------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+----------------------+ -| MPU | on-chip | arch/arm | -+-----------+------------+----------------------+ -| NVIC | on-chip | arch/arm | -+-----------+------------+----------------------+ -| PWM | on-chip | pwm | -+-----------+------------+----------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154 | -+-----------+------------+----------------------+ -| RTC | on-chip | system clock | -+-----------+------------+----------------------+ -| SPI(M/S) | on-chip | spi | -+-----------+------------+----------------------+ -| UART | on-chip | serial | -+-----------+------------+----------------------+ -| USB | on-chip | usb | -+-----------+------------+----------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+----------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The `XIAO BLE wiki`_ has detailed information about the board including -`pinouts`_ and the `schematic`_. - -LED ---- - -* LED1 (red) = P0.26 -* LED2 (green) = P0.30 -* LED3 (blue) = P0.06 - -Programming and Debugging -************************* - -The XIAO BLE ships with the `Adafruit nRF52 Bootloader`_ which supports flashing -using `UF2`_. Doing so allows easy flashing of new images, but does not support -debugging the device. For debugging please use `External Debugger`_. - -UF2 Flashing -============ - -To enter the bootloader, connect the USB port of the XIAO BLE to your host, and -double tap the reset botton to the left of the USB connector. A mass storage -device named `XIAO BLE` should appear on the host. Using the command line, or -your file manager copy the `zephyr/zephyr.uf2` file from your build to the base -of the `XIAO BLE` mass storage device. The XIAO BLE will automatically reset -and launch the newly flashed application. - -External Debugger -================= - -In order to support debugging the device, instead of using the bootloader, you -can use an :ref:`External Debug Probe `. To flash and debug Zephyr -applications you need to use `Seeeduino XIAO Expansion Board`_ or solder an SWD -header onto the back side of the board. - -For Segger J-Link debug probes, follow the instructions in the -:ref:`jlink-external-debug-probe` page to install and configure all the -necessary software. - -Flashing --------- - -Setup and connect a supported debug probe (JLink, instructions at :ref:`jlink-external-debug-probe` or -BlackMagic Probe). Then build and flash applications as -usual (see :ref:`build_an_application` and :ref:`application_run` for more -details). - -Here is an example for the :ref:`hello_world` application. - -First, run your favorite terminal program to listen for output. - -.. code-block:: console - - $ minicom -D -b 115200 - -Replace :code:`` with the port where the board XIAO BLE -can be found. For example, under Linux, :code:`/dev/ttyACM0`. - -Then build and flash the application in the usual way. Just add -``CONFIG_BOOT_DELAY=5000`` to the configuration, so that USB CDC ACM is -initialized before any text is printed, as below: - -.. tabs:: - - .. group-tab:: XIAO BLE - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_ble - :goals: build flash - :gen-args: -DCONFIG_BOOT_DELAY=5000 - - .. group-tab:: XIAO BLE Sense - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_ble_sense - :goals: build flash - :gen-args: -DCONFIG_BOOT_DELAY=5000 - -Debugging ---------- - -Refer to the :ref:`jlink-external-debug-probe` page to learn about debugging -boards with a Segger IC. - -Debugging using a BlackMagic Probe is also supported. - -Testing the LEDs in the XIAO BLE (Sense) -**************************************** - -There is a sample that allows to test that LEDs on the board are working -properly with Zephyr: - -.. tabs:: - - .. group-tab:: XIAO BLE - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: xiao_ble - :goals: build flash - - .. group-tab:: XIAO BLE Sense - - .. zephyr-app-commands:: - :zephyr-app: samples/basic/blinky - :board: xiao_ble_sense - :goals: build flash - -You can build and flash the examples to make sure Zephyr is running correctly on -your board. The LED definitions can be found in -:zephyr_file:`boards/arm/xiao_ble/xiao_ble_common.dtsi`. - -Testing shell over USB in the XIAO BLE (Sense) -********************************************** - -There is a sample that allows to test shell interface over USB CDC ACM interface -with Zephyr: - -.. tabs:: - - .. group-tab:: XIAO BLE - - .. zephyr-app-commands:: - :zephyr-app: samples/subsys/shell/shell_module - :board: xiao_ble - :goals: build flash - - .. group-tab:: XIAO BLE Sense - - .. zephyr-app-commands:: - :zephyr-app: samples/subsys/shell/shell_module - :board: xiao_ble_sense - :goals: build flash - -References -********** - -.. target-notes:: - -.. _XIAO BLE wiki: https://wiki.seeedstudio.com/XIAO_BLE/ -.. _pinouts: https://wiki.seeedstudio.com/XIAO_BLE/#hardware-overview -.. _schematic: https://wiki.seeedstudio.com/XIAO_BLE/#resources -.. _Seeeduino XIAO Expansion Board: https://wiki.seeedstudio.com/Seeeduino-XIAO-Expansion-Board/ -.. _Adafruit nRF52 Bootloader: https://github.com/adafruit/Adafruit_nRF52_Bootloader -.. _UF2: https://github.com/microsoft/uf2 diff --git a/boards/arm/xiao_ble/pre_dt_board.cmake b/boards/arm/xiao_ble/pre_dt_board.cmake deleted file mode 100644 index 3369c21d3af5ba..00000000000000 --- a/boards/arm/xiao_ble/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - power@40000000 & clock@40000000 & bprot@40000000 -# - acl@4001e000 & flash-controller@4001e000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/xiao_ble/xiao_ble_defconfig b/boards/arm/xiao_ble/xiao_ble_defconfig deleted file mode 100644 index 59471d3d22a034..00000000000000 --- a/boards/arm/xiao_ble/xiao_ble_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_XIAO_BLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y - -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# enable USB -CONFIG_USB_DEVICE_STACK=y - -# Build UF2 by default, supported by the Adafruit nRF52 Bootloader -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/xiao_ble/xiao_ble_sense.yaml b/boards/arm/xiao_ble/xiao_ble_sense.yaml deleted file mode 100644 index 7d11907651a299..00000000000000 --- a/boards/arm/xiao_ble/xiao_ble_sense.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: xiao_ble_sense -name: XIAO BLE Sense -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - ble - - counter - - gpio - - i2c - - i2s - - pwm - - spi - - usb_cdc - - usb_device - - watchdog - - netif:openthread -vendor: seeed diff --git a/boards/arm/xiao_ble/xiao_ble_sense_defconfig b/boards/arm/xiao_ble/xiao_ble_sense_defconfig deleted file mode 100644 index 73878352edd6f5..00000000000000 --- a/boards/arm/xiao_ble/xiao_ble_sense_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_XIAO_BLE=y - -# Enable MPU -CONFIG_ARM_MPU=y - -# Enable hardware stack protection -CONFIG_HW_STACK_PROTECTION=y - -# enable GPIO -CONFIG_GPIO=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y - -# Logger cannot use itself to log -CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y - -# enable USB -CONFIG_USB_DEVICE_STACK=y - -# Build UF2 by default, supported by the Adafruit nRF52 Bootloader -CONFIG_BUILD_OUTPUT_UF2=y -CONFIG_USE_DT_CODE_PARTITION=y - -# required to enable LSM6DS3TR-C power -CONFIG_REGULATOR=y diff --git a/boards/arm/xmc45_relax_kit/Kconfig.board b/boards/arm/xmc45_relax_kit/Kconfig.board deleted file mode 100644 index 6be8d36685926b..00000000000000 --- a/boards/arm/xmc45_relax_kit/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -config BOARD_XMC45_RELAX_KIT - bool "Infineon Relax Kit" - depends on SOC_SERIES_XMC_4XXX - select SOC_PART_NUMBER_F100X1024 diff --git a/boards/arm/xmc45_relax_kit/Kconfig.defconfig b/boards/arm/xmc45_relax_kit/Kconfig.defconfig deleted file mode 100644 index 0296bc64ff79c5..00000000000000 --- a/boards/arm/xmc45_relax_kit/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -if BOARD_XMC45_RELAX_KIT - -config BOARD - default "xmc45_relax_kit" - -if NETWORKING - -config NET_L2_ETHERNET - default y -config MDIO - default y -config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif # BOARD_XMC45_RELAX_KIT diff --git a/boards/arm/xmc47_relax_kit/Kconfig.board b/boards/arm/xmc47_relax_kit/Kconfig.board deleted file mode 100644 index 7c60e2a03e89cf..00000000000000 --- a/boards/arm/xmc47_relax_kit/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Schlumberger - -config BOARD_XMC47_RELAX_KIT - bool "Infineon XMC4700 Relax Kit" - depends on SOC_SERIES_XMC_4XXX - select SOC_PART_NUMBER_F144X2048 diff --git a/boards/arm/xmc47_relax_kit/Kconfig.defconfig b/boards/arm/xmc47_relax_kit/Kconfig.defconfig deleted file mode 100644 index 98978ffd5409df..00000000000000 --- a/boards/arm/xmc47_relax_kit/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Schlumberger - -if BOARD_XMC47_RELAX_KIT - -config BOARD - default "xmc47_relax_kit" - -if NETWORKING - -config NET_L2_ETHERNET - default y -config MDIO - default y -config TEST_RANDOM_GENERATOR - default y - -endif # NETWORKING - -endif diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit_defconfig b/boards/arm/xmc47_relax_kit/xmc47_relax_kit_defconfig deleted file mode 100644 index 85522ce92bd90a..00000000000000 --- a/boards/arm/xmc47_relax_kit/xmc47_relax_kit_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Schlumberger - -CONFIG_BOARD_XMC47_RELAX_KIT=y -CONFIG_SOC_SERIES_XMC_4XXX=y -CONFIG_SOC_XMC4700=y - -# enable uart driver -CONFIG_SERIAL=y - -# enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/zybo/Kconfig.board b/boards/arm/zybo/Kconfig.board deleted file mode 100644 index 30dfd50f3da384..00000000000000 --- a/boards/arm/zybo/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Digilent Zybo board configuration - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ZYBO - bool "Digilent Zybo" - depends on SOC_XILINX_XC7Z010 diff --git a/boards/arm/zybo/Kconfig.defconfig b/boards/arm/zybo/Kconfig.defconfig deleted file mode 100644 index ea8ddb6a62a459..00000000000000 --- a/boards/arm/zybo/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Digilent Zybo board - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ZYBO - -config BOARD - default "zybo" - -endif # BOARD_ZYBO diff --git a/boards/arm/zybo/doc/index.rst b/boards/arm/zybo/doc/index.rst deleted file mode 100644 index 44810e666ce313..00000000000000 --- a/boards/arm/zybo/doc/index.rst +++ /dev/null @@ -1,147 +0,0 @@ -.. _zybo: - -Digilent Zybo -############# - -Overview -******** - -The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital -circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the -Xilinx All Programmable System-on-Chip (AP SoC) architecture. This architecture tightly integrates a -dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. - -.. figure:: zybo-0.jpg - :align: center - :alt: Digilent Zybo - - Digilent (Credit: Digilent) - -Hardware -******** - -Supported Features -================== - -The zybo board configuration supports the following hardware features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| GICv1 | on-chip | ARM generic interrupt controller v1 | -+------------+------------+-------------------------------------+ -| ARCH TIMER | on-chip | ARM architected timer | -+------------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+------------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/arm/zybo/zybo_defconfig``. - -Other hardware features are not currently supported by the port. - -Programming and Debugging -************************* - -The Zynq-7000 series SoC needs to be initialized prior to running a Zephyr application. This can be -achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx -Vivado generated ``ps_init.tcl`` JTAG script, Das U-Boot Secondary Program Loader (SPL), ...). - -The instructions here use the U-Boot SPL. For further details and instructions for using Das U-Boot -with Xilinx Zynq-7000 series SoCs, see the following documentation: - -- `Das U-Boot Website`_ -- `Using Distro Boot With Xilinx U-Boot`_ - -Building Das U-Boot -=================== - -Clone and build Das U-Boot for the Digilent Zybo: - -.. code-block:: console - - git clone -b v2022.04 https://source.denx.de/u-boot/u-boot.git - cd u-boot - make distclean - make xilinx_zynq_virt_defconfig - export PATH=/path/to/zephyr-sdk/arm-zephyr-eabi/bin/:$PATH - export CROSS_COMPILE=arm-zephyr-eabi- - export DEVICE_TREE="zynq-zybo" - make - -Flashing -======== - -Here is an example for running the :ref:`hello_world` application via JTAG. - -Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press -the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot -SPL via JTAG. - -Next, upload and run the Zephyr application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: zybo - :goals: flash - -You should see the following message in the terminal: - -.. code-block:: console - - *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** - Hello World! zybo - -Another option is to load and run the :ref:`hello_world` application via U-Boot. Copy -``u-boot/spl/boot.bin``, ``u-boot/u-boot.img``, and ``zephyr/zephyr.bin`` to a FAT32 formatted -microSD card, insert the card in the ``SD MICRO`` slot on the Zybo board, ensure the board is -configured for ``SD`` boot, and turn on the board. - -Once U-boot is done initializing, load an run the Zephyr application: - -.. code-block:: console - - Zynq> fatload mmc 0 0x0 zephyr.bin - 817120 bytes read in 56 ms (13.9 MiB/s) - Zynq> go 0x0 - ## Starting application at 0x00000000 ... - *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** - Hello World! zybo - -Debugging -========= - -Here is an example for the :ref:`hello_world` application. - -Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press -the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot -SPL via JTAG. - -Next, upload and debug the Zephyr application: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: zybo - :goals: debug - -Step through the application in your debugger, and you should see the following message in the -terminal: - -.. code-block:: console - - *** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *** - Hello World! zybo - -.. _Digilent Zybo: - https://digilent.com/reference/programmable-logic/zybo/start - -.. _Das U-Boot Website: - https://www.denx.de/wiki/U-Boot - -.. _Using Distro Boot With Xilinx U-Boot: - https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/749142017/Using+Distro+Boot+With+Xilinx+U-Boot diff --git a/boards/arm/zybo/zybo_defconfig b/boards/arm/zybo/zybo_defconfig deleted file mode 100644 index ad4d88eaee3584..00000000000000 --- a/boards/arm/zybo/zybo_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_XILINX_XC7ZXXX=y -CONFIG_SOC_XILINX_XC7Z010=y -CONFIG_BOARD_ZYBO=y - -# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) -CONFIG_ARM_ARCH_TIMER=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=325000000 - -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/bcm958402m2_a72/Kconfig.board b/boards/arm64/bcm958402m2_a72/Kconfig.board deleted file mode 100644 index 655d894e4d5a70..00000000000000 --- a/boards/arm64/bcm958402m2_a72/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BCM958402M2_A72 - bool "Broadcom Viper BCM958402M2_A72" - depends on SOC_BCM58402_A72 diff --git a/boards/arm64/bcm958402m2_a72/Kconfig.defconfig b/boards/arm64/bcm958402m2_a72/Kconfig.defconfig deleted file mode 100644 index 8f7714ab9f30b4..00000000000000 --- a/boards/arm64/bcm958402m2_a72/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "bcm958402m2_a72" - depends on BOARD_BCM958402M2_A72 diff --git a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml b/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml deleted file mode 100644 index d59dd34439c948..00000000000000 --- a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.yaml +++ /dev/null @@ -1,8 +0,0 @@ -identifier: bcm958402m2_a72 -name: Broadcom BCM958402M2_A72 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -vendor: brcm diff --git a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72_defconfig b/boards/arm64/bcm958402m2_a72/bcm958402m2_a72_defconfig deleted file mode 100644 index 6f758f867d9d9d..00000000000000 --- a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72_defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_VIPER=y -CONFIG_SOC_BCM58402_A72=y -CONFIG_BOARD_BCM958402M2_A72=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_FLASH_SIZE=0 -CONFIG_FLASH_BASE_ADDRESS=0x0 - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable PCIe EP -CONFIG_PCIE_ENDPOINT=y -CONFIG_PCIE_EP_IPROC=y -CONFIG_PCIE_EP_IPROC_V2=y - -# Enable DMA -CONFIG_DMA=y -CONFIG_DMA_64BIT=y diff --git a/boards/arm64/bcm958402m2_a72/doc/index.rst b/boards/arm64/bcm958402m2_a72/doc/index.rst deleted file mode 100644 index 8c8737f7e52bcd..00000000000000 --- a/boards/arm64/bcm958402m2_a72/doc/index.rst +++ /dev/null @@ -1,51 +0,0 @@ -.. _bcm958402m2_a72: - -Broadcom BCM958402M2 (Cortex-A72) -################################# - -Overview -******** -The Broadcom bcm958402m2_a72 board utilizes the Viper BCM58402_A72 SoC -to provide support for PCIe offload engine functionality. - -Hardware -******** -The bcm958402m2_a72 is a PCIe card with the following physical features: - -* PCIe Gen4 interface -* RS232 UART (optionally populated) -* JTAG (optionally populated) - -Supported Features -================== -The Broadcom bcm958402m2_a72 board configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-500 | on-chip | GICv3 interrupt controller | -+-----------+------------+--------------------------------------+ -| UART | on-chip | NS16550 compatible serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm/bcm958402m2_a72/bcm958402m2_a72_defconfig`` - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. -Board is booted over PCIe interface. - -Debugging -========= -The bcm958402m2_a72 board includes pads for soldering a JTAG connector. -Zephyr applications running on the Cortex-A72 core can also be tested -by observing UART console output. diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.board b/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.board deleted file mode 100644 index dbc0bf5ac7db51..00000000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FVP_BASE_REVC_2XAEMV8A - bool "FVP Base RevC AEMv8A simulation board" - depends on SOC_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.defconfig b/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.defconfig deleted file mode 100644 index bfbb54fb049c85..00000000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FVP_BASE_REVC_2XAEMV8A - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "fvp_base_revc_2xaemv8a" - -endif # BOARD_FVP_BASE_REVC_2XAEMV8A diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.yaml b/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.yaml deleted file mode 100644 index b6e39f0dab3550..00000000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_base_revc_2xaemv8a_smp_ns -name: FVP Emulation FVP_Base_RevC-2xAEMvA (SMP) -arch: arm64 -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -vendor: arm diff --git a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns_defconfig b/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns_defconfig deleted file mode 100644 index 235444bcab5c78..00000000000000 --- a/boards/arm64/fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a_smp_ns_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2022 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8A=y -CONFIG_SOC_FVP_BASE_REVC_2XAEMV8A=y -CONFIG_BOARD_FVP_BASE_REVC_2XAEMV8A=y - -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable TFA -CONFIG_ARMV8_A_NS=y -CONFIG_BUILD_WITH_TFA=y - -# Enable SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 -CONFIG_CACHE_MANAGEMENT=y -CONFIG_TIMEOUT_64BIT=y -CONFIG_ARM64_SET_VMPIDR_EL2=y -CONFIG_MAX_THREAD_BYTES=3 - -# PSCI is supported -CONFIG_PM_CPU_OPS=y diff --git a/boards/arm64/fvp_baser_aemv8r/Kconfig.board b/boards/arm64/fvp_baser_aemv8r/Kconfig.board deleted file mode 100644 index 3b0c7ba7081975..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_FVP_BASER_AEMV8R - bool "FVP BaseR AEMv8R simulation board" - depends on SOC_FVP_AEMV8R_AARCH64 diff --git a/boards/arm64/fvp_baser_aemv8r/Kconfig.defconfig b/boards/arm64/fvp_baser_aemv8r/Kconfig.defconfig deleted file mode 100644 index 89a9b37380385d..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_FVP_BASER_AEMV8R - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "fvp_baser_aemv8r" - -endif # BOARD_FVP_BASER_AEMV8R diff --git a/boards/arm64/fvp_baser_aemv8r/board.cmake b/boards/arm64/fvp_baser_aemv8r/board.cmake deleted file mode 100644 index 410431bdcbfa86..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/board.cmake +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS armfvp) -set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R) -set(ARMFVP_MIN_VERSION 11.16.16) - -set(ARMFVP_FLAGS - -C cluster0.has_aarch64=1 - -C cluster0.VMSA_supported=0 - -C cluster0.NUM_CORES=${CONFIG_MP_MAX_NUM_CPUS} - -C cluster0.gicv3.cpuintf-mmap-access-level=2 - -C cluster0.gicv3.SRE-enable-action-on-mmap=2 - -C cluster0.gicv3.SRE-EL2-enable-RAO=1 - -C cluster0.gicv3.extended-interrupt-range-support=1 - -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1 - -C gic_distributor.has-two-security-states=0 - -C bp.refcounter.non_arch_start_at_default=1 - # UART0 config - -C bp.pl011_uart0.out_file=- - -C bp.pl011_uart0.unbuffered_output=1 - -C bp.terminal_0.start_telnet=0 - # UART1 config - -C bp.pl011_uart1.out_file=- - -C bp.pl011_uart1.unbuffered_output=1 - -C bp.terminal_1.start_telnet=0 - # UART2 config - -C bp.pl011_uart2.out_file=- - -C bp.pl011_uart2.unbuffered_output=1 - -C bp.terminal_2.start_telnet=0 - # UART3 config - -C bp.pl011_uart3.out_file=- - -C bp.pl011_uart3.unbuffered_output=1 - -C bp.terminal_3.start_telnet=0 - - -C bp.vis.disable_visualisation=1 - -C bp.vis.rate_limit-enable=0 - -C cache_state_modelled=1 - ) diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml deleted file mode 100644 index 840fa70e5c91ec..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r.yaml +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r -name: FVP Emulation FVP_BaseR_AEMv8R -arch: arm64 -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -testing: - timeout_multiplier: 8 -vendor: arm diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig deleted file mode 100644 index 7876a7453279f6..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R=y -CONFIG_SOC_FVP_AEMV8R_AARCH64=y -CONFIG_BOARD_FVP_BASER_AEMV8R=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.dts b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.dts deleted file mode 100644 index 13c39522ca1185..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.dts +++ /dev/null @@ -1,6 +0,0 @@ -/* - * Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "fvp_baser_aemv8r.dts" diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.yaml b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.yaml deleted file mode 100644 index ed63f35d1012fa..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp.yaml +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -identifier: fvp_baser_aemv8r_smp -name: FVP Emulation FVP_BaseR_AEMv8R (SMP) -arch: arm64 -type: sim -toolchain: - - zephyr - - cross-compile -ram: 2048 -flash: 64 -supported: - - smp -testing: - timeout_multiplier: 20 -vendor: arm diff --git a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp_defconfig b/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp_defconfig deleted file mode 100644 index 9a96f0b3d4fdf8..00000000000000 --- a/boards/arm64/fvp_baser_aemv8r/fvp_baser_aemv8r_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_FVP_AEMV8R=y -CONFIG_SOC_FVP_AEMV8R_AARCH64=y -CONFIG_BOARD_FVP_BASER_AEMV8R=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -CONFIG_THREAD_STACK_INFO=y - -# Enable Timer and Sys clock -CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 -CONFIG_ARM_ARCH_TIMER=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable simulate cpu power management -CONFIG_SOC_FVP_AEMV8R_SIMULATE_CPU_PM=y -CONFIG_PM_CPU_OPS=y -CONFIG_PM_CPU_OPS_PSCI=n -CONFIG_ARM64_SET_VMPIDR_EL2=y - -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 - -CONFIG_MAX_THREAD_BYTES=3 diff --git a/boards/arm64/index.rst b/boards/arm64/index.rst deleted file mode 100644 index e7dbb2d68426bd..00000000000000 --- a/boards/arm64/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-arm64: - -ARM64 Boards -############ - -.. toctree:: - :maxdepth: 1 - :glob: - - **/index diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.board b/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.board deleted file mode 100644 index a23f8c5d1e09aa..00000000000000 --- a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK - bool "Intel SoC FPGA Development Kit (Agilex5)" - select HAS_COVERAGE_SUPPORT - depends on SOC_AGILEX5 diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.defconfig b/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.defconfig deleted file mode 100644 index 5b832b29c002cb..00000000000000 --- a/boards/arm64/intel_socfpga_agilex5_socdk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "intel_socfpga_agilex5_socdk" - depends on BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK - -config MAX_THREAD_BYTES - default 5 diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/doc/index.rst b/boards/arm64/intel_socfpga_agilex5_socdk/doc/index.rst deleted file mode 100644 index 537b1628cde84a..00000000000000 --- a/boards/arm64/intel_socfpga_agilex5_socdk/doc/index.rst +++ /dev/null @@ -1,80 +0,0 @@ -.. _intel_socfpga_agilex5_socdk: - -Intel® Agilex™ 5 SoC FPGA Development Kit -######################################### - -Overview -******** - -The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design -environment that includes both hardware and software for developing -Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for -developing custom ARM* processor-based SoC designs and ideal for intelligent -applications at the edge, embedded and more. - -Hardware -******** - -The Intel® Agilex™ 5 Development Kit supports the following physical features: - -- Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with - multi-core ARM processors of Dual-core A55 and Dual-core A76 -- On-board 8 GB DDR5 memory -- On-board JTAG Intel FPGA Download Cable II -- QSPI flash daughtercard - -Supported Features -================== -The Intel® Agilex™ 5 SoC Development Kit configuration supports the following -hardware features: - -+-----------+------------+---------------------------------------------+ -| Interface | Controller | Hardware Subsystem Vendor | -+===========+============+=============================================+ -| GIC-600 | on-chip | ARM GICv3 interrupt controller | -+-----------+------------+---------------------------------------------+ -| UART | on-chip | Synopsys Designware,NS16550 compatible | -+-----------+------------+---------------------------------------------+ -| ARM TIMER | on-chip | ARM system timer | -+-----------+------------+---------------------------------------------+ -| Reset | on-chip | Intel Corporation, SoCFPGA Reset controller | -+-----------+------------+---------------------------------------------+ -| Clock | on-chip | Intel Corporation, SoCFPGA Clock controller | -+-----------+------------+---------------------------------------------+ - -NOTE: TODO, more details on dev kit will be updated as and when available. - -The default configuration can be found in the defconfig file: - `boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig` - -Programming and Debugging -************************* - -Zephyr Boot Flow -**************** -Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). -ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which -provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface). - -Boot flow: - ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1) - -Intel Arm Trusted Firmware (ATF) can be downloaded from github: - `altera-opensource/arm-trusted-firmware `_ - -Flashing -======== -Zephyr image can be loaded in DDR memory at address 0x80000000 from -SD Card or QSPI Flash or NAND in ATF BL2. - -Debugging -========= -The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on -board, connect it to Intel USB blaster download cables for debugging. - -Zephyr applications running on the Cortex-A55/A76 core can be tested by -observing UART console output. - -References -========== -`Intel® Agilex™ 5 FPGA and SoC FPGA `_ diff --git a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board deleted file mode 100644 index 7dcc7b1e7a52c1..00000000000000 --- a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_SOCFPGA_AGILEX_SOCDK - bool "Intel SoC FPGA Development Kit (Agilex)" - depends on SOC_AGILEX diff --git a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig b/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig deleted file mode 100644 index 58c3bddb5a198f..00000000000000 --- a/boards/arm64/intel_socfpga_agilex_socdk/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "intel_socfpga_agilex_socdk" - depends on BOARD_INTEL_SOCFPGA_AGILEX_SOCDK diff --git a/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst b/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst deleted file mode 100644 index fdf60262b15127..00000000000000 --- a/boards/arm64/intel_socfpga_agilex_socdk/doc/index.rst +++ /dev/null @@ -1,79 +0,0 @@ -.. _intel_socfpga_agilex_socdk: - -Intel Agilex SoC Development Kit -################################# - -Overview -******** - -The Intel Agilex SoC Development Kit offers a complete design environment -that includes both hardware and software for developing Intel Agilex -F-Series FPGA designs. This kit is recommended for developing custom -Arm* processor-based SoC designs and evaluating transceiver performance. - -Hardware -******** - -The Intel Agilex SoC Development Kit supports the following physical features: - -- Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the - quad-core Arm Cortex-A53 processor -- On-board 8 GB DDR4 memory -- On-board JTAG Intel FPGA Download Cable II -- QSPI flash daughtercard -- HPS OOBE daughtercard with UART and SD Card support - -Supported Features -================== -The Intel Agilex SoC Development Kit configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-400 | on-chip | GICv2 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | NS16550 compatible serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig`` - -Programming and Debugging -************************* - -Boot Flow -========= -Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). -ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage -boot loader (SSBL). - -Zephyr boot flow: - - ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1) - -Intel Arm Trusted Firmware (ATF) can be downloaded from github: - - `altera-opensource/arm-trusted-firmware `_ - -Flashing -======== -Zephyr image can be loaded in DDR memory at address 0x10000000 from -SD Card or QSPI Flash in ATF BL2. - -Debugging -========= -The Intel Agilex SoC Development Kit includes one JTAG connector on -board, connect it to Intel USB blaster download cables for debugging. - -Zephyr applications running on the Cortex-A53 core can be tested by -observing UART console output. - -References -========== -`Intel Agilex Transceiver-SoC Development Kit `_ diff --git a/boards/arm64/khadas_edgev/Kconfig.board b/boards/arm64/khadas_edgev/Kconfig.board deleted file mode 100644 index 201df41a38bf8a..00000000000000 --- a/boards/arm64/khadas_edgev/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_KHADAS_EDGEV - bool "Khadas Edge-V" - depends on SOC_SERIES_RK3399 diff --git a/boards/arm64/khadas_edgev/Kconfig.defconfig b/boards/arm64/khadas_edgev/Kconfig.defconfig deleted file mode 100644 index ac8a0a4dadaf5f..00000000000000 --- a/boards/arm64/khadas_edgev/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD - default "khadas_edgev" - depends on BOARD_KHADAS_EDGEV diff --git a/boards/arm64/khadas_edgev/doc/index.rst b/boards/arm64/khadas_edgev/doc/index.rst deleted file mode 100644 index 35128a04106c29..00000000000000 --- a/boards/arm64/khadas_edgev/doc/index.rst +++ /dev/null @@ -1,85 +0,0 @@ -.. _khadas_edgev: - -Khadas Edge-V -################################# - -Overview -******** - -See - -Hardware -******** - -See - -Supported Features -================== - -Khadas Edge-V board default configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-500 | on-chip | GICv3 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | Synopsys DesignWare 8250 serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file for NON-SMP: - - ``boards/arm64/khadas_edgev/khadas_edgev_defconfig`` - -There are multiple serial ports on the board: Zephyr is using -uart2 as serial console. - -Programming and Debugging -************************* - -Use the following configuration to run basic Zephyr applications and -kernel tests on Khadas Edge-V board. For example, with the :ref:`hello_world`: - -1. Non-SMP mode - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :host-os: unix - :board: khadas_edgev - :goals: build - -This will build an image with the synchronization sample app. - -Build the zephyr image: - -.. code-block:: console - - mkimage -C none -A arm64 -O linux -a 0x10000000 -e 0x10000000 -d build/zephyr/zephyr.bin build/zephyr/zephyr.img - -Use u-boot to load and kick Zephyr.bin to CPU Core0: - -.. code-block:: console - - tftpboot ${pxefile_addr_r} zephyr.img; bootm start ${pxefile_addr_r}; bootm loados; bootm go - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build XXXXXXXXXXXX *** - Hello World! khadas_edgev - -Flashing -======== - -Zephyr image can be loaded in DDR memory at address 0x10000000 from SD Card, -EMMC, QSPI Flash or downloaded from network in uboot. - -References -========== - -`Documentation: `_ diff --git a/boards/arm64/mimx8mm_evk/Kconfig.board b/boards/arm64/mimx8mm_evk/Kconfig.board deleted file mode 100644 index c84e506adb7ed2..00000000000000 --- a/boards/arm64/mimx8mm_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MM_EVK_A53 - bool "NXP i.MX8M Mini EVK A53" - depends on SOC_SERIES_MIMX8M_A53 - select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/arm64/mimx8mm_evk/Kconfig.defconfig b/boards/arm64/mimx8mm_evk/Kconfig.defconfig deleted file mode 100644 index 9f4d9e9490f364..00000000000000 --- a/boards/arm64/mimx8mm_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MM_EVK_A53 - -config BOARD - default "mimx8mm_evk_a53" - -endif # BOARD_MIMX8MM_EVK_A53 diff --git a/boards/arm64/mimx8mm_evk/doc/index.rst b/boards/arm64/mimx8mm_evk/doc/index.rst deleted file mode 100644 index 947abd2ba2a4be..00000000000000 --- a/boards/arm64/mimx8mm_evk/doc/index.rst +++ /dev/null @@ -1,131 +0,0 @@ -.. _imx8mm_evk: - -NXP i.MX8MM EVK (Cortex-A53) -############################ - -Overview -******** - -i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mm_evk_a53 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 - -Or kick SMP zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 - - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx8mm_evk_a53 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: - -.. code-block:: console - - #jailhouse enable imx8mm.cell - #jailhouse cell create imx8mm-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0x93c00000 - #jailhouse cell start 1 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MMRM diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.dts b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.dts deleted file mode 100644 index 942e5eae9a55a9..00000000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2020-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mm_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MM A53"; - compatible = "fsl,mimx8mm"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - cpu@2 { - status = "disabled"; - }; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.yaml b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.yaml deleted file mode 100644 index 72295bdb7eb4e2..00000000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx8mm_evk_a53 -name: NXP i.MX8M Mini EVK A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_defconfig b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_defconfig deleted file mode 100644 index d8c66f1754a10f..00000000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MM_A53=y -CONFIG_BOARD_MIMX8MM_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.dts b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.dts deleted file mode 100644 index 02b5ca010d1bd0..00000000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2021-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mm_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MM A53"; - compatible = "fsl,mimx8mm"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.yaml b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.yaml deleted file mode 100644 index b6a23c923e05b3..00000000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: mimx8mm_evk_a53_smp -name: NXP i.MX8M Mini EVK A53 with SMP kernel -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp_defconfig b/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp_defconfig deleted file mode 100644 index 3c06082bb592fc..00000000000000 --- a/boards/arm64/mimx8mm_evk/mimx8mm_evk_a53_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MM_A53=y -CONFIG_BOARD_MIMX8MM_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mn_evk/Kconfig.board b/boards/arm64/mimx8mn_evk/Kconfig.board deleted file mode 100644 index 04506a42ed83af..00000000000000 --- a/boards/arm64/mimx8mn_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MN_EVK_A53 - bool "NXP i.MX8M Nano EVK A53" - depends on SOC_SERIES_MIMX8M_A53 - select SOC_PART_NUMBER_MIMX8MN6DVTJZ diff --git a/boards/arm64/mimx8mn_evk/Kconfig.defconfig b/boards/arm64/mimx8mn_evk/Kconfig.defconfig deleted file mode 100644 index 21f6caecd9bb51..00000000000000 --- a/boards/arm64/mimx8mn_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MN_EVK_A53 - -config BOARD - default "mimx8mn_evk_a53" - -endif # BOARD_MIMX8MN_EVK_A53 diff --git a/boards/arm64/mimx8mn_evk/doc/index.rst b/boards/arm64/mimx8mn_evk/doc/index.rst deleted file mode 100644 index b9620176b6eb1d..00000000000000 --- a/boards/arm64/mimx8mn_evk/doc/index.rst +++ /dev/null @@ -1,131 +0,0 @@ -.. _imx8mn_evk: - -NXP i.MX8MN EVK (Cortex-A53) -############################ - -Overview -******** - -i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M7 - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mn_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 - -Or kick SMP zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 - - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx8mn_evk_a53 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: - -.. code-block:: console - - #jailhouse enable imx8mn.cell - #jailhouse cell create imx8mn-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0x93c00000 - #jailhouse cell start 1 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-nano-applications-processor:8MNANOD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/webapp/Download?colCode=IMX8MNRM diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.dts b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.dts deleted file mode 100644 index a38bb21184c18f..00000000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.dts +++ /dev/null @@ -1,44 +0,0 @@ -/* - * Copyright 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mn_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MN A53"; - compatible = "fsl,mimx8mn"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - cpu@2 { - status = "disabled"; - }; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.yaml b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.yaml deleted file mode 100644 index 4b6bd284846765..00000000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx8mn_evk_a53 -name: NXP i.MX8M Nano EVK A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_defconfig b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_defconfig deleted file mode 100644 index 79da4a06d8fcf7..00000000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MN_A53=y -CONFIG_BOARD_MIMX8MN_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.dts b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.dts deleted file mode 100644 index 53af33520dba63..00000000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.dts +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mn_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MN A53"; - compatible = "fsl,mimx8mn"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sram0: memory@93c00000 { - reg = <0x93c00000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.yaml b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.yaml deleted file mode 100644 index 487c1bb8d3a360..00000000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: mimx8mn_evk_a53_smp -name: NXP i.MX8M Nano EVK A53 with SMP kernel -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp_defconfig b/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp_defconfig deleted file mode 100644 index 111083ae550436..00000000000000 --- a/boards/arm64/mimx8mn_evk/mimx8mn_evk_a53_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MN_A53=y -CONFIG_BOARD_MIMX8MN_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mp_evk/Kconfig.board b/boards/arm64/mimx8mp_evk/Kconfig.board deleted file mode 100644 index c37a3a6d1f2a5d..00000000000000 --- a/boards/arm64/mimx8mp_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2021-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX8MP_EVK_A53 - bool "NXP i.MX8M Plus EVK A53" - depends on SOC_SERIES_MIMX8M_A53 - select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm64/mimx8mp_evk/Kconfig.defconfig b/boards/arm64/mimx8mp_evk/Kconfig.defconfig deleted file mode 100644 index e43bd17cae858c..00000000000000 --- a/boards/arm64/mimx8mp_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2021-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX8MP_EVK_A53 - -config BOARD - default "mimx8mp_evk_a53" - -endif # BOARD_MIMX8MP_EVK_A53 diff --git a/boards/arm64/mimx8mp_evk/doc/index.rst b/boards/arm64/mimx8mp_evk/doc/index.rst deleted file mode 100644 index e59f94189a002d..00000000000000 --- a/boards/arm64/mimx8mp_evk/doc/index.rst +++ /dev/null @@ -1,130 +0,0 @@ -.. _imx8mp_evk: - -NXP i.MX8MP EVK (Cortex-A53) -################################# - -Overview -******** - -i.MX8M Plus LPDDR4 EVK board is based on NXP i.MX8M Plus applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - Micron 32MB QSPI NOR - - microSD Socket - - Wireless: - - - WiFi: 2.4/5GHz IEEE 802.11b/g/n - - Bluetooth: v4.1 - - USB: - - - OTG - 2x type C - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 1x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A53 and M4 - -More information about the board can be found at the -`NXP website`_. - -Supported Features -================== - -The Zephyr mimx8mp_evk_a53 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8 MHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick non-smp zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000 - -Or kick SMP zephyr.bin: - -.. code-block:: console - - mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000 - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx8mp_evk_a53 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! - thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! - -Use Jailhouse hypervisor, after root cell linux is up: - -.. code-block:: console - - #jailhouse enable imx8mp.cell - #jailhouse cell create imx8mp-zephyr.cell - #jailhouse cell load 1 zephyr.bin -a 0xc0000000 - #jailhouse cell start 1 - -References -========== - -.. _NXP website: - https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK - -.. _i.MX 8M Applications Processor Reference Manual: - https://www.nxp.com/docs/en/reference-manual/IMX8MPRM.pdf diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.dts b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.dts deleted file mode 100644 index b0ffede31dbf94..00000000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.dts +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright 2021-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MP A53"; - compatible = "fsl,mimx8mp"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - cpu@2 { - status = "disabled"; - }; - }; - - sram0: memory@c0000000 { - reg = <0xc0000000 DT_SIZE_M(1)>; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.yaml b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.yaml deleted file mode 100644 index dbee1a28ef2add..00000000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx8mp_evk_a53 -name: NXP i.MX8M Plus EVK A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_defconfig b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_defconfig deleted file mode 100644 index 215166ba08042a..00000000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MP_A53=y -CONFIG_BOARD_MIMX8MP_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.dts b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.dts deleted file mode 100644 index 456fd5ea6e2466..00000000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.dts +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright 2021-2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx8mp_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX8MP A53"; - compatible = "fsl,mimx8mp"; - - chosen { - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - cpu@1 { - status = "disabled"; - }; - }; - - psci { - compatible = "arm,psci-0.2"; - method = "smc"; - }; - - sram0: memory@c0000000 { - reg = <0xc0000000 DT_SIZE_M(1)>; - }; - -}; - -&uart4 { - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.yaml b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.yaml deleted file mode 100644 index c44defa6a5b3f4..00000000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: mimx8mp_evk_a53_smp -name: NXP i.MX8M Plus EVK A53 with SMP kernel -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp_defconfig b/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp_defconfig deleted file mode 100644 index 3e135ef3e309f3..00000000000000 --- a/boards/arm64/mimx8mp_evk/mimx8mp_evk_a53_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX8M_A53=y -CONFIG_SOC_MIMX8MP_A53=y -CONFIG_BOARD_MIMX8MP_EVK_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# SMP -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx93_evk/Kconfig.board b/boards/arm64/mimx93_evk/Kconfig.board deleted file mode 100644 index 59ecb516cde51f..00000000000000 --- a/boards/arm64/mimx93_evk/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MIMX93_EVK_A55 - bool "NXP i.MX93 EVK A55" - depends on SOC_SERIES_MIMX9_A55 - select SOC_PART_NUMBER_MIMX9352CVUXK diff --git a/boards/arm64/mimx93_evk/Kconfig.defconfig b/boards/arm64/mimx93_evk/Kconfig.defconfig deleted file mode 100644 index 2e9cc7599ed367..00000000000000 --- a/boards/arm64/mimx93_evk/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_MIMX93_EVK_A55 - -config BOARD - default "mimx93_evk_a55" - -endif # BOARD_MIMX8MP_EVK_A55 diff --git a/boards/arm64/mimx93_evk/doc/index.rst b/boards/arm64/mimx93_evk/doc/index.rst deleted file mode 100644 index 50792491c95fc9..00000000000000 --- a/boards/arm64/mimx93_evk/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _imx93_evk: - -NXP i.MX93 EVK (Cortex-A55) -############################ - -Overview -******** - -The i.MX93 Evaluation Kit (MCIMX93-EVK board) is a platform designed to show -the most commonly used features of the i.MX 93 Applications Processor in a -small and low cost package. The MCIMX93-EVK board is an entry-level development -board, which helps developers to get familiar with the processor before -investing a large amount of resources in more specific designs. - -i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single -Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core. - -- Board features: - - - RAM: 2GB LPDDR4 - - Storage: - - - SanDisk 16GB eMMC5.1 - - microSD Socket - - Wireless: - - - Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, - which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, - and 802.15.4 - - USB: - - - Two USB 2.0 Type C connectors - - Ethernet - - PCI-E M.2 - - Connectors: - - - 40-Pin Dual Row Header - - LEDs: - - - 1x Power status LED - - 2x UART LED - - Debug - - - JTAG 20-pin connector - - MicroUSB for UART debug, two COM ports for A55 and M33 - - -Supported Features -================== - -The Zephyr mimx93_evk board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v4 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 24 MHz. -Cortex-A55 Core runs up to 1.7 GHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART4. - -Programming and Debugging -************************* - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: - -.. code-block:: console - - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xd0000000 - - -Or use the following command to kick zephyr.bin to Cortex-A55 Core0: - -.. code-block:: console - - fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000 - - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: mimx93_evk_a55 - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v3.2.0-8-g1613870534a0 *** - thread_a: Hello World from cpu 0 on mimx93_evk_a55! - thread_b: Hello World from cpu 0 on mimx93_evk_a55! - thread_a: Hello World from cpu 0 on mimx93_evk_a55! - thread_b: Hello World from cpu 0 on mimx93_evk_a55! - -References -========== - -More information can refer to NXP official website: -`NXP website`_. - -.. _NXP website: - https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-93-applications-processor-family-arm-cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93 - - -Using the SOF-specific variant -****************************** - -Purpose -======= - -Since this board doesn't have a DSP, an alternative for people who might be interested -in running SOF on this board had to be found. The alternative consists of running SOF -on an A55 core using Jailhouse as a way to "take away" one A55 core from Linux and -assign it to Zephyr with `SOF`_. - -.. _SOF: - https://github.com/thesofproject/sof - -What is Jailhouse? -================== - -Jailhouse is a light-weight hypervisor that allows the partitioning of hardware resources. -For more details on how this is done and, generally, about Jailhouse, please see: `1`_, -`2`_ and `3`_. The GitHub repo can be found `here`_. - -.. _1: - https://lwn.net/Articles/578295/ - -.. _2: - https://lwn.net/Articles/578852/ - -.. _3: - http://events17.linuxfoundation.org/sites/events/files/slides/ELCE2016-Jailhouse-Tutorial.pdf - -.. _here: - https://github.com/siemens/jailhouse - - -How does it work? -================= -Firstly, we need to explain a few Jailhouse concepts that will be referred to later on: - -* **Cell**: refers to a set of hardware resources that the OS assigned to this - cell can utilize. - -* **Root cell**: refers to the cell in which Linux is running. This is the main cell which - will contain all the hardware resources that Linux will utilize and will be used to assign - resources to the inmates. The inmates CANNOT use resources such as the CPU that haven't been - assigned to the root cell. - -* **Inmate**: refers to any other OS that runs alongside Linux. The resources an inmate will - use are taken from the root cell (the cell Linux is running in). - -SOF+Zephyr will run as an inmate, alongside Linux, on core 1 of the board. This means that -said core will be taken away from Linux and will only be utilized by Zephyr. - -The hypervisor restricts inmate's/root's access to certain hardware resources using -the second-stage translation table which is based on the memory regions described in the -configuration files. Please consider the following scenario: - - Root cell wants to use the **UART** which let's say has its registers mapped in - the **[0x0 - 0x42000000]** region. If the inmate wants to use the same **UART** for - some reason then we'd need to also add this region to inmate's configuration - file and add the **JAILHOUSE_MEM_ROOTSHARED** flag. This flag means that the inmate - is allowed to share this region with the root. If this region is not set in - the inmate's configuration file and Zephyr (running as an inmate here) tries - to access this region this will result in a second stage translation fault. - -Notes: - -* Linux and Zephyr are not aware that they are running alongside each other. - They will only be aware of the cores they have been assigned through the config - files (there's a config file for the root and one for each inmate). - -Architecture overview -===================== - -The architecture overview can be found at this `location`_. (latest status update as of now -and the only one containing diagrams). - -.. _location: - https://github.com/thesofproject/sof/issues/7192 - - -How to use this board? -====================== - -This board has been designed for SOF so it's only intended to be used with SOF. - -TODO: document the SOF build process for this board. For now, the support for -i.MX93 is still in review and has yet to merged on SOF side. diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55.dts b/boards/arm64/mimx93_evk/mimx93_evk_a55.dts deleted file mode 100644 index 03b14cf9bc7d09..00000000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55.dts +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright 2022,2024 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx93_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX93 A55"; - compatible = "fsl,mimx93"; - - chosen { - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - }; - - sram0: memory@d0000000 { - reg = <0xd0000000 DT_SIZE_M(1)>; - }; - - aliases { - led0 = &led_r; - sw0 = &btn_1; - }; - - leds { - compatible = "gpio-leds"; - led_r: led_r { - label = "LED_R"; - gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; - }; - led_g: led_g { - label = "LED_G"; - gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; - }; - led_b: led_b { - label = "LED_B"; - gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; - }; - }; - - keys { - compatible = "gpio-keys"; - - btn_1: btn_1{ - label = "BTN1"; - gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; - }; - - btn_2: btn_2{ - label = "BTN2"; - gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - }; - }; -}; - -&lpuart1 { - status = "disabled"; - current-speed = <115200>; - /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - - -&lpi2c1{ - status = "disabled"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&lpi2c2{ - status = "disabled"; - clock-frequency = ; - pinctrl-0 = <&i2c2_default>; - pinctrl-names = "default"; -}; - -&lpspi3 { - status = "disabled"; - clock-frequency = <1000000>; - pinctrl-0 = <&spi3_default>; - pinctrl-names = "default"; -}; - -&gpio1{ - status = "okay"; -}; - -&gpio2{ - status = "okay"; -}; - -&gpio3{ - status = "okay"; -}; - -&gpio4{ - status = "okay"; -}; diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55.yaml b/boards/arm64/mimx93_evk/mimx93_evk_a55.yaml deleted file mode 100644 index d4fc0bc7ae61bc..00000000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: mimx93_evk_a55 -name: NXP i.MX93 Plus EVK A55 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - gpio - - uart - - i2c - - spi -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig b/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig deleted file mode 100644 index fb60fdfd9bb7f6..00000000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# -# Copyright 2022 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y - -# MMU Options -CONFIG_MAX_XLAT_TABLES=64 - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX9_A55=y -CONFIG_SOC_MIMX93_A55=y -CONFIG_BOARD_MIMX93_EVK_A55=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_KERNEL_DIRECT_MAP=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.dts b/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.dts deleted file mode 100644 index 2d1c03e3f9f4ca..00000000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "mimx93_evk-pinctrl.dtsi" - -/ { - model = "NXP i.MX93 A55"; - compatible = "fsl,mimx93"; - - chosen { - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - zephyr,sram = &sram0; - }; - - cpus { - cpu@0 { - status = "disabled"; - }; - }; - - /* Inmate memory, reserved through "mem=1248MB" boot argument, - * starts at 0xce000000. - */ - sram0: memory@ce000000 { - reg = <0xce000000 DT_SIZE_M(1)>; - }; - - /* TODO: all of the nodes below are needed by SOF and should - * be removed once all drivers used by SOF have been moved - * to Zephyr. - * - * They are added in the DTS for the sake of not using hardcoded - * values in mmu_regions.c - */ - mu2_a: memory@42430000 { - reg = <0x42430000 DT_SIZE_K(64)>; - }; - - sai3: memory@42660000 { - reg = <0x42660000 DT_SIZE_K(64)>; - }; - - edma2_ch0: memory@42010000 { - reg = <0x42010000 DT_SIZE_K(32)>; - }; - - edma2_ch1: memory@42018000 { - reg = <0x42018000 DT_SIZE_K(32)>; - }; - - outbox: memory@ce100000 { - reg = <0xce100000 DT_SIZE_K(4)>; - }; - - inbox: memory@ce101000 { - reg = <0xce101000 DT_SIZE_K(4)>; - }; - - stream: memory@ce102000 { - reg = <0xce102000 DT_SIZE_K(4)>; - }; - - /* TODO: this is extremely bad and it's needed here because of - * the fact that the DMA buffer shared by host and FW is situated - * in this region. For now, it's easier to create a mapping for the - * whole region but in the future a mapping should only be created - * for the physical address of the buffer sent to the FW through an - * IPC. - */ - host_ram: memory@80000000 { - reg = <0x80000000 DT_SIZE_M(1024)>; - }; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.yaml b/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.yaml deleted file mode 100644 index 7fffa3f990e71f..00000000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: mimx93_evk_a55_sof -name: NXP i.MX93 Plus EVK A55 for SOF module -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -testing: - ignore_tags: - - net - - bluetooth -vendor: fsl diff --git a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof_defconfig b/boards/arm64/mimx93_evk/mimx93_evk_a55_sof_defconfig deleted file mode 100644 index 6d0bc02b113475..00000000000000 --- a/boards/arm64/mimx93_evk/mimx93_evk_a55_sof_defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# -# Copyright 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y - -# The number of bits used for PAs and VAs -# from Zephyr needs to match the number of -# bits used for said address used by Jailhouse. -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y -# SOF doesn't currently support the usage of -# run-time data cache line size detection. -# Because of this, CONFIG_DCACHE_LINE_SIZE_DETECT -# (which defaults to n) can't be set to 'y'. -# The size of data cache line will have to be -# set manually to 64 (value taken from A55 TRM). -CONFIG_DCACHE_LINE_SIZE=64 - -# Platform Configuration -CONFIG_SOC_SERIES_MIMX9_A55=y -CONFIG_SOC_MIMX93_A55=y -CONFIG_BOARD_MIMX93_EVK_A55=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_CLOCK_CONTROL=y -CONFIG_PINCTRL=y - -# Enable dynamic interrupts -CONFIG_DYNAMIC_INTERRUPTS=y diff --git a/boards/arm64/nxp_ls1046ardb/Kconfig.board b/boards/arm64/nxp_ls1046ardb/Kconfig.board deleted file mode 100644 index 5986971533e401..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2021 NXP -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_NXP_LS1046ARDB - bool "NXP Layerscape ls1046ardb" - depends on SOC_SERIES_LS1046A diff --git a/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig b/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig deleted file mode 100644 index 1896c014d5cf1e..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2021 NXP -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD - default "nxp_ls1046ardb" - depends on BOARD_NXP_LS1046ARDB diff --git a/boards/arm64/nxp_ls1046ardb/doc/index.rst b/boards/arm64/nxp_ls1046ardb/doc/index.rst deleted file mode 100644 index 98e52f941bc40a..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _nxp_ls1046ardb: - -NXP LS1046A RDB -################################# - -Overview -******** - -The LS1046A reference design board (RDB) is a high-performance computing, -evaluation, and development platform that supports the Layerscape LS1046A -architecture processor. The LS1046ARDB board supports the Layerscape LS1046A -processor and is optimized to support the DDR4 memory and a full complement -of high-speed SerDes ports. - -The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72 -cores with packet processing acceleration and high-speed peripherals. The -impressive performance of more than 32,000 CoreMarks, paired with 10 Gb -Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an -excellent combination for a range of enterprise and service provider -networking, storage, security and industrial applications. - -Hardware -******** - -LS1046A RDB boards supports the following features: - - -- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed -- Supports 8 GB DDR4 SDRAM memory -- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi - memory device -- One 512 MB SLC NAND flash with ECC support (1.8 V) -- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections -- Support two 64 MB onboard QSPI NOR flash memories -- USB: - - Two USB 3.0 controllers with integrated PHYs. - - One USB1 3.0 port is connected to a Type A host connector. - - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector. - - One USB2.0 is connected to miniPCIe connector . -- Ethernet: - - Supports SGMII 1G PHYs at Lane 2 and Lane 3 - - Supports SFP+module with XFI retimers - - Supports AQR106/107 10G PHY with XFI/2.5G SGMII -- PCIe and SATA: - - Mini PCIe express x1 (Gen1/2/3)card - - Standard PCIe x1 (Gen1/2/3) card - - Standard PCIe x1 (Gen1/2/3) card - - One SATA 3.0 connector - -Supported Features -================== - -NXP LS1046A RDB board default configuration supports the following -hardware features: - -+-----------+------------+--------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+======================================+ -| GIC-400 | on-chip | GICv2 interrupt controller | -+-----------+------------+--------------------------------------+ -| ARM TIMER | on-chip | System Clock | -+-----------+------------+--------------------------------------+ -| UART | on-chip | NS16550 compatible serial port | -+-----------+------------+--------------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file for NON-SMP: - - ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig`` - -Or for SMP running on all four CPU Cores: - - ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig`` - -Or for SMP running on 2 CPU Cores (Core2 and Core3): - - ``boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig`` - -There are two serial port on the board: uart1 and uart2, Zephyr is using -uart2 as serial console. - -Programming and Debugging -************************* - -Use the following configuration to run basic Zephyr applications and -kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample: - -1. Non-SMP mode - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nxp_ls1046ardb - :goals: build - -This will build an image with the synchronization sample app. - -Use u-boot to load and kick Zephyr.bin to CPU Core0: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; - -Or kick Zephyr.bin to any other CPU Cores, for example run Zephyr on Core3: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 3 release 0xc0000000; - - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - thread_b: Hello World from cpu 0 on nxp_ls1046ardb! - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - -2. SMP mode running on 4 CPU Cores - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nxp_ls1046ardb_smp_4cores - :goals: build - -This will build an image with the synchronization sample app. - -Use u-boot to load and kick Zephyr.bin to CPU Core0: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** - Secondary CPU core 1 (MPID:0x1) is up - Secondary CPU core 2 (MPID:0x2) is up - Secondary CPU core 3 (MPID:0x3) is up - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - thread_b: Hello World from cpu 1 on nxp_ls1046ardb! - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - -3. SMP mode running on 2 CPU Cores: Core2 and Core3 - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: nxp_ls1046ardb_smp_2cores - :goals: build - -This will build an image with the synchronization sample app. - -Use u-boot to load and kick Zephyr.bin to CPU Core2: - -.. code-block:: console - - tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 2 release 0xc0000000; - -It will display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** - Secondary CPU core 1 (MPID:0x3) is up - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - thread_b: Hello World from cpu 1 on nxp_ls1046ardb! - thread_a: Hello World from cpu 0 on nxp_ls1046ardb! - -4. Running Zephyr on Jailhouse inmate Cell - -Use the following to run Zephyr in Jailhouse inmate, need to configure Jailhouse -inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3 -for Zephyr SMP 2cores image. - -1) Use root Cell dts to boot root Cell Linux. - -2) Install Jailhouse module: - -.. code-block:: console - - modprobe jailhouse - -3) Run Zephyr demo in inmate Cell: - -.. code-block:: console - - jailhouse enable ls1046a-rdb.cell - jailhouse cell create ls1046a-rdb-inmate-demo.cell - jailhouse cell load 1 zephyr.bin --address 0xc0000000 - jailhouse cell start 1 - -Flashing -======== - -Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card, -EMMC, QSPI Flash or downloaded from network in uboot. - -Debugging -========= - -LS1046A RDB board includes one JTAG connector on board, connect it to -CodeWarrior TAP for debugging. - -References -========== - -`Layerscape LS1046A Reference Design Board `_ - -`LS1046A Reference Manual `_ diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml deleted file mode 100644 index e00a5475b1bd07..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: nxp_ls1046ardb -name: NXP LS1046ARDB on single CPU Core (NON-SMP) -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig deleted file mode 100644 index c8bb699fd1c934..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_LS1046A=y -CONFIG_SOC_LS1046A=y -CONFIG_BOARD_NXP_LS1046ARDB=y -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y -# 25 MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_AARCH64_IMAGE_HEADER=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.yaml deleted file mode 100644 index 93e56887e22538..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: nxp_ls1046ardb_smp_2cores -name: NXP LS1046ARDB SMP on CPU Core2 and Core3 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig deleted file mode 100644 index 8339f5e897c471..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_LS1046A=y -CONFIG_SOC_LS1046A=y -CONFIG_BOARD_NXP_LS1046ARDB=y -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y -# 25 MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_MAX_THREAD_BYTES=5 -CONFIG_MAX_XLAT_TABLES=10 - -# SMP support -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_CACHE_MANAGEMENT=y -CONFIG_ARMV8_A_NS=y - -# PSCI is supported -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.yaml b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.yaml deleted file mode 100644 index c74af99c1be70a..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: nxp_ls1046ardb_smp_4cores -name: NXP LS1046ARDB SMP on four CPU Cores -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig b/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig deleted file mode 100644 index 2ed89853987804..00000000000000 --- a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores_defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_LS1046A=y -CONFIG_SOC_LS1046A=y -CONFIG_BOARD_NXP_LS1046ARDB=y -CONFIG_ARM64_VA_BITS_40=y -CONFIG_ARM64_PA_BITS_40=y -# 25 MHz system clock -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 - -# Zephyr Kernel Configuration -CONFIG_XIP=n -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_MAX_THREAD_BYTES=5 -CONFIG_MAX_XLAT_TABLES=10 - -# SMP support -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 -CONFIG_CACHE_MANAGEMENT=y -CONFIG_ARMV8_A_NS=y - -# PSCI is supported -CONFIG_PM_CPU_OPS=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/phycore_am62x_a53/Kconfig.board b/boards/arm64/phycore_am62x_a53/Kconfig.board deleted file mode 100644 index 1a8e9d08363de6..00000000000000 --- a/boards/arm64/phycore_am62x_a53/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PHYCORE_AM62X_A53 - bool "PHYTEC phyCORE-AM62x A53" - depends on SOC_SERIES_AM6X_A53 diff --git a/boards/arm64/phycore_am62x_a53/Kconfig.defconfig b/boards/arm64/phycore_am62x_a53/Kconfig.defconfig deleted file mode 100644 index 51dd70ebc3c75f..00000000000000 --- a/boards/arm64/phycore_am62x_a53/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_PHYCORE_AM62X_A53 - -config BOARD - default "phycore_am62x_a53" - -endif # BOARD_PHYCORE_AM62X_A53 diff --git a/boards/arm64/phycore_am62x_a53/doc/index.rst b/boards/arm64/phycore_am62x_a53/doc/index.rst deleted file mode 100644 index 0fb1c6063b1482..00000000000000 --- a/boards/arm64/phycore_am62x_a53/doc/index.rst +++ /dev/null @@ -1,109 +0,0 @@ -.. _phycore_am62x_a53: - -PHYTEC phyCORE-AM62x (Cortex-A53) -################################# - -Overview -******** - -PHYTEC phyCORE-AM62x board is based on TI Sitara applications -processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. -Zephyr OS is ported to run on the Cortex®-A53 core. - -- Board features: - - - RAM: 2GB DDR4 - - Storage: - - - 16GB eMMC - - 64MB OSPI NOR - - 4KB EEPROM - - Ethernet - -More information about the board can be found at the -`PHYTEC website`_. - -Supported Features -================== - -The Zephyr phycore_am62x_a53 board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| PINCTRL | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 200 MHz. - -DDR RAM -------- - -The board has 2GB of DDR RAM available. This board configuration -allocates Zephyr 1MB of RAM (0x82000000 to 0x82100000). - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART0. - -SD Card -******* - -Download PHYTEC's official `WIC`_ and `bmap`_ files and flash the WIC file with -bmap-tools on a SD-card. - -.. code-block:: console - - bmaptool copy phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz /dev/sdX - -Building -******** - -You can build an application in the usual way. Refer to -:ref:`build_an_application` for more details. Here is an example for -:ref:`hello_world`. - -.. zephyr-app-commands:: - :board: phycore_am62x_a53 - :zephyr-app: samples/hello_world - :goals: build - -Programming -*********** - -Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and -plug the SD card into the board. Power it up and stop the u-boot execution at -prompt. - -Use U-Boot to load and kick zephyr.bin: - -.. code-block:: console - - fatload mmc 1:1 0x82000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x82000000 - - -.. - References - -.. _PHYTEC website: - https://www.phytec.com/product/phycore-am62x/ - -.. _WIC: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz - -.. _Bmap: - https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap diff --git a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.yaml b/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.yaml deleted file mode 100644 index fe65e6b4a3671a..00000000000000 --- a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: phycore_am62x_a53 -name: PHYTEC phyCORE-AM62x A53 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -testing: - ignore_tags: - - net - - bluetooth -vendor: ti diff --git a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53_defconfig b/boards/arm64/phycore_am62x_a53/phycore_am62x_a53_defconfig deleted file mode 100644 index 3f5893f6747e9d..00000000000000 --- a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53_defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# ARM Options -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_ARMV8_A_NS=y -CONFIG_ARM64_VA_BITS_36=y -CONFIG_ARM64_PA_BITS_36=y - -# Cache Options -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE_LINE_SIZE_DETECT=y -CONFIG_ICACHE_LINE_SIZE_DETECT=y - -# Platform Configuration -CONFIG_SOC_SERIES_AM6X_A53=y -CONFIG_SOC_AM6234_A53=y -CONFIG_BOARD_PHYCORE_AM62X_A53=y - -# Zephyr Kernel Configuration -CONFIG_XIP=n - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable Console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/qemu_cortex_a53/Kconfig.board b/boards/arm64/qemu_cortex_a53/Kconfig.board deleted file mode 100644 index c14d70c2b72638..00000000000000 --- a/boards/arm64/qemu_cortex_a53/Kconfig.board +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_CORTEX_A53 - bool "Cortex-A53 Emulation (QEMU)" - depends on SOC_QEMU_CORTEX_A53 - select ARM64 - select QEMU_TARGET - -config QEMU_CORTEX_A53_ETH_E1000 - bool "Use Intel e1000 Ethernet driver for networking" - default y if !NET_TEST - depends on BOARD_QEMU_CORTEX_A53 && NETWORKING && DT_HAS_INTEL_E1000_ENABLED - select ETH_E1000 - select NET_L2_ETHERNET - select PCIE - select PCIE_CONTROLLER - select PCIE_ECAM diff --git a/boards/arm64/qemu_cortex_a53/Kconfig.defconfig b/boards/arm64/qemu_cortex_a53/Kconfig.defconfig deleted file mode 100644 index 8f10806f7baa27..00000000000000 --- a/boards/arm64/qemu_cortex_a53/Kconfig.defconfig +++ /dev/null @@ -1,39 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_CORTEX_A53 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "qemu_cortex_a53" - -config MAX_THREAD_BYTES - default 3 - -if NETWORKING - -choice NET_QEMU_NETWORKING - default NET_QEMU_ETHERNET if QEMU_CORTEX_A53_ETH_E1000 -endchoice - -config NET_DRIVERS - default n if QEMU_CORTEX_A53_ETH_E1000 - -endif # NETWORKING - -# QEMU PCI requires at least 256M of virtual space -config KERNEL_VM_SIZE - default 0x80000000 if PCIE - -# QEMU PCI requires physical addresses with more than 32 bits -choice ARM64_VA_BITS - default ARM64_VA_BITS_40 if PCIE -endchoice - -choice ARM64_PA_BITS - default ARM64_PA_BITS_40 if PCIE -endchoice - -endif # BOARD_QEMU_CORTEX_A53 diff --git a/boards/arm64/qemu_cortex_a53/board.cmake b/boards/arm64/qemu_cortex_a53/board.cmake deleted file mode 100644 index 4935438e4b7733..00000000000000 --- a/boards/arm64/qemu_cortex_a53/board.cmake +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) -set(QEMU_ARCH aarch64) - -set(QEMU_CPU_TYPE_${ARCH} cortex-a53) - -if(CONFIG_ARMV8_A_NS) -set(QEMU_MACH virt,gic-version=3) -else() -set(QEMU_MACH virt,secure=on,gic-version=3) -endif() - -set(QEMU_FLAGS_${ARCH} - -cpu ${QEMU_CPU_TYPE_${ARCH}} - -nographic - -machine ${QEMU_MACH} - ) - -if(CONFIG_XIP) - # This should be equivalent to - # ... -drive if=pflash,file=build/zephyr/zephyr.bin,format=raw - # without having to pad the binary file to the FLASH size - set(QEMU_KERNEL_OPTION - -bios ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - ) -endif() - -board_set_debugger_ifnset(qemu) diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig deleted file mode 100644 index e697012a690b16..00000000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_defconfig +++ /dev/null @@ -1,21 +0,0 @@ -CONFIG_SOC_QEMU_CORTEX_A53=y -CONFIG_BOARD_QEMU_CORTEX_A53=y -CONFIG_ARM_ARCH_TIMER=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Avoid timing skew in tests -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=4 -CONFIG_QEMU_ICOUNT_SLEEP=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.yaml b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.yaml deleted file mode 100644 index 9a6e87c0a70ce7..00000000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: qemu_cortex_a53_smp -name: QEMU Emulation for Cortex-A53 SMP -type: qemu -simulation: qemu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -supported: - - smp -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: qemu diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp_defconfig b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp_defconfig deleted file mode 100644 index ad9011aa3b760c..00000000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp_defconfig +++ /dev/null @@ -1,31 +0,0 @@ -CONFIG_SOC_QEMU_CORTEX_A53=y -CONFIG_BOARD_QEMU_CORTEX_A53=y -CONFIG_ARM_ARCH_TIMER=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# icount does not work well with SMP -CONFIG_QEMU_ICOUNT=n - -# We have multiple QEMU-A53 boards, so let us exercise ARMV8_A_NS on this one -# (plus it is needed for SMP) -CONFIG_ARMV8_A_NS=y - -# PSCI is supported with NS -CONFIG_PM_CPU_OPS=y - -# SMP-related -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_TIMEOUT_64BIT=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.yaml b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.yaml deleted file mode 100644 index 5654908d3d2fe3..00000000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_cortex_a53_xip -name: QEMU Emulation for Cortex-A53 (XIP) -type: qemu -simulation: qemu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 128 -testing: - default: true - only_tags: - - xip -vendor: qemu diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip_defconfig b/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip_defconfig deleted file mode 100644 index d2dbdc1fc51c46..00000000000000 --- a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -CONFIG_SOC_QEMU_CORTEX_A53=y -CONFIG_BOARD_QEMU_CORTEX_A53=y -CONFIG_ARM_ARCH_TIMER=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable serial port -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Avoid timing skew in tests -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=4 -CONFIG_QEMU_ICOUNT_SLEEP=y - -# Enable XIP -CONFIG_XIP=y diff --git a/boards/arm64/qemu_kvm_arm64/Kconfig.board b/boards/arm64/qemu_kvm_arm64/Kconfig.board deleted file mode 100644 index 6542a5383e5bfa..00000000000000 --- a/boards/arm64/qemu_kvm_arm64/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_KVM_ARM64 - bool "Cortex AArch64 KVM Virt Emulation (QEMU)" - depends on SOC_QEMU_VIRT_ARM64 - select ARM64 - select QEMU_TARGET diff --git a/boards/arm64/qemu_kvm_arm64/Kconfig.defconfig b/boards/arm64/qemu_kvm_arm64/Kconfig.defconfig deleted file mode 100644 index 0156bce7e2e9cc..00000000000000 --- a/boards/arm64/qemu_kvm_arm64/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SASU -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_KVM_ARM64 - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "qemu_kvm_arm64" - -endif # BOARD_QEMU_KVM_ARM64 diff --git a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.board b/boards/arm64/rcar_h3ulcb_ca57/Kconfig.board deleted file mode 100644 index 7367501632bc50..00000000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_H3ULCB_CA57 - bool "Renesas H3ULCB" - depends on SOC_ARM64_R8A77951 diff --git a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.defconfig b/boards/arm64/rcar_h3ulcb_ca57/Kconfig.defconfig deleted file mode 100644 index fefd6e1259d368..00000000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_H3ULCB_CA57 - -config BOARD - default "rcar_h3ulcb_ca57" - -config BUILD_OUTPUT_BIN - default y - -endif # BOARD_RCAR_H3ULCB_CA57 diff --git a/boards/arm64/rcar_h3ulcb_ca57/doc/index.rst b/boards/arm64/rcar_h3ulcb_ca57/doc/index.rst deleted file mode 100644 index a22d948be2a0d8..00000000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/doc/index.rst +++ /dev/null @@ -1,86 +0,0 @@ -.. _rcar_h3ulcb_ca57: - -R-CAR H3 ARM CA57 (ARMv8) -######################### - -Overview -******** -The R-Car H3 is an SOC that features the basic functions for next-generation -car navigation systems. - -Hardware -******** -The R-Car H3 includes: - -* four 1.5-GHz ARM Cortex-A57 MPCore cores; -* four 1.2-GHz ARM Cortex-A53 MPCore cores; -* memory controller for LPDDR4-3200 with 32 bits x 4 channels; -* 2 channels for HDMI1.4b output and 1channel for RGB888 output and 1channel for LVDS; -* 4 channels MIPI-CSI2 Video Input, 2channels digital Video Input; -* serial ATA interface; -* USB3.0 x 2ch and USB2.0 x 3ch interfaces; -* 800-MHz ARM Cortex-R7 core; -* two- and three-dimensional graphics engines; -* video processing units; -* sound processing units; -* MediaLB interface; -* SD card host interface; -* USB3.0 and USB2.0 interfaces; -* PCI Express interface; -* CAN interface; -* EtherAVB. - -Connections and IOs -=================== - -H3ULCB Board ------------- - -Here are official IOs figures from eLinux for H3ULCB board: - -.. figure:: img/rcar_h3ulcb_top.jpg - :align: center - -.. figure:: img/rcar_h3ulcb_bottom.jpg - :align: center - -Supported Features -================== -The Renesas rcar_h3ulcb_ca57 board configuration supports the following -hardware features: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+-----------+------------------------------+--------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig`` - -Programming and Debugging -************************* - -Flashing -======== - -The flash on board is not supported by Zephyr at this time. - -References -********** - -- `Renesas R-Car Development Support website`_ -- `eLinux R-Car Starter Kit page`_ - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux R-Car Starter Kit page: - https://elinux.org/R-Car/Boards/H3SK diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.dts b/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.dts deleted file mode 100644 index 7c1f153325de69..00000000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2023 EPAM Systems - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include -#include "rcar_h3ulcb_ca57-pinctrl.dtsi" - -/ { - model = "H3ULCB CA57"; - - chosen { - zephyr,sram = &ram; - zephyr,console = &scif2; - zephyr,shell-uart = &scif2; - }; - - ram: memory@48000000 { - device_type = "mmio-sram"; - reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.yaml b/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.yaml deleted file mode 100644 index e34235c2d43f60..00000000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: rcar_h3ulcb_ca57 -name: Renesas H3ULCB based on r8a77951 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 512 -supported: - - clock_control - - uart -testing: - ignore_tags: - - net - - bluetooth - - isotp -vendor: renesas diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig b/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig deleted file mode 100644 index 3995ececf442ac..00000000000000 --- a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -CONFIG_SOC_ARM64_R8A77951=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_H3ULCB_CA57=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 -CONFIG_XIP=n - -CONFIG_MAX_XLAT_TABLES=24 -CONFIG_ARMV8_A_NS=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable clock control -CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm64/rcar_salvator_xs_m3/Kconfig.board b/boards/arm64/rcar_salvator_xs_m3/Kconfig.board deleted file mode 100644 index 032514dac7a410..00000000000000 --- a/boards/arm64/rcar_salvator_xs_m3/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RCAR_SALVATOR_XS_M3 - bool "Renesas Salvator XS M3" - depends on SOC_R8A77961 diff --git a/boards/arm64/rcar_salvator_xs_m3/Kconfig.defconfig b/boards/arm64/rcar_salvator_xs_m3/Kconfig.defconfig deleted file mode 100644 index 7230474a1d7f0b..00000000000000 --- a/boards/arm64/rcar_salvator_xs_m3/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RCAR_SALVATOR_XS_M3 - -config BOARD - default "rcar_salvator_xs_m3" - -config BUILD_OUTPUT_BIN - default y - -endif # BOARD_RCAR_SALVATOR_XS_M3 diff --git a/boards/arm64/rcar_salvator_xs_m3/doc/index.rst b/boards/arm64/rcar_salvator_xs_m3/doc/index.rst deleted file mode 100644 index b89c71d4ecd8dc..00000000000000 --- a/boards/arm64/rcar_salvator_xs_m3/doc/index.rst +++ /dev/null @@ -1,69 +0,0 @@ -.. _rcar_salvator_xs_m3: - -R-CAR Salvator XS M3 ARM CA57 (ARMv8) -##################################### - -Overview -******** -The R-Car M3-W is an SOC that features the basic functions for next-generation -car navigation systems. - -Hardware -******** -The R-Car M3-W includes: - -* two 1.5-GHz ARM Cortex-A57 MPCore cores; -* four 1.3-GHz ARM Cortex-A53 MPCore cores, -* memory controller for LPDDR4-3200 with 32 bits x 2 channels; -* 1 channels for HDMI1.4b output and 1 channel for RGB888 output and 1channel for LVDS; -* 2 channels MIPI-CSI2 Video Input, 2 channels digital Video Input; -* USB3.0 x 1ch and USB2.0 x 2ch interfaces; -* 800-MHz ARM Cortex-R7 core; -* two- and three-dimensional graphics engines; -* video processing units; -* sound processing units; -* MediaLB interface; -* SD card host interface; -* USB3.0 and USB2.0 interfaces; -* PCI Express interface; -* CAN interface; -* EtherAVB. - -Supported Features -================== -The Renesas rcar_salvator_xs_m3 board configuration supports the following -hardware features: - -+-----------+------------------------------+--------------------------------+ -| Interface | Driver/components | Support level | -+===========+==============================+================================+ -| PINCTRL | pinctrl | | -+-----------+------------------------------+--------------------------------+ -| CLOCK | clock_control | | -+-----------+------------------------------+--------------------------------+ -| UART | uart | serial port-polling | -+-----------+------------------------------+--------------------------------+ - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig`` - -Programming and Debugging -************************* - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -References -********** - -- `Renesas R-Car Development Support website`_ -- `eLinux Salvator-XS page`_ - -.. _Renesas R-Car Development Support website: - https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support - -.. _eLinux Salvator-XS page: - https://elinux.org/R-Car/Boards/Salvator-XS diff --git a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.dts b/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.dts deleted file mode 100644 index 15fae0ca965694..00000000000000 --- a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.dts +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2023 EPAM Systems - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -/dts-v1/; -#include -#include -#include "salvator_xs_m3-pinctrl.dtsi" - -/ { - model = "Salvator XS M3"; - - chosen { - zephyr,sram = &ram; - zephyr,console = &scif2; - zephyr,shell-uart = &scif2; - }; - - ram: memory@48000000 { - device_type = "mmio-sram"; - reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; - }; -}; - -&scif2 { - pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.yaml b/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.yaml deleted file mode 100644 index 84d4a864a352f8..00000000000000 --- a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: rcar_salvator_xs_m3 -name: Renesas Salvator XS M3 based on r8a77961 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 512 -supported: - - clock_control - - uart -testing: - ignore_tags: - - net - - bluetooth - - isotp -vendor: renesas diff --git a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig b/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig deleted file mode 100644 index a6eb4060d39ab8..00000000000000 --- a/boards/arm64/rcar_salvator_xs_m3/rcar_salvator_xs_m3_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -CONFIG_SOC_R8A77961=y -CONFIG_SOC_SERIES_RCAR_GEN3=y -CONFIG_BOARD_RCAR_SALVATOR_XS_M3=y - -# Cache management -CONFIG_CACHE_MANAGEMENT=y - -# Enable UART driver -CONFIG_SERIAL=y -CONFIG_AARCH64_IMAGE_HEADER=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 -CONFIG_XIP=n - -CONFIG_MAX_XLAT_TABLES=24 -CONFIG_ARMV8_A_NS=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable clock control -CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm64/roc_rk3568_pc/Kconfig.board b/boards/arm64/roc_rk3568_pc/Kconfig.board deleted file mode 100644 index 97844de31fd447..00000000000000 --- a/boards/arm64/roc_rk3568_pc/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ROC_RK3568_PC - bool "Rockchip ROC-RK3568-PC" - depends on SOC_SERIES_RK3568 - select ARM64 diff --git a/boards/arm64/roc_rk3568_pc/Kconfig.defconfig b/boards/arm64/roc_rk3568_pc/Kconfig.defconfig deleted file mode 100644 index 9ad4f73bd2b02c..00000000000000 --- a/boards/arm64/roc_rk3568_pc/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ROC_RK3568_PC - -config BOARD - default "roc_rk3568_pc" - -endif # BOARD_ROC_RK3568_PC diff --git a/boards/arm64/roc_rk3568_pc/doc/index.rst b/boards/arm64/roc_rk3568_pc/doc/index.rst deleted file mode 100644 index ae999409545d76..00000000000000 --- a/boards/arm64/roc_rk3568_pc/doc/index.rst +++ /dev/null @@ -1,142 +0,0 @@ -.. _roc_rk3568_pc: - -Firefly ROC-RK3568-PC (Quad-core Cortex-A55) -############################################ - -Overview -******** - -The ROC-RK3568-PC is a Quad-Core 64-Bit Mini Computer, which supports 4G large RAM. M.2 -and SATA3.0 interfaces enables expansion with large hard drives. -Providing dual Gigabit Ethernet ports, it supports WiFi 6 wireless transmission. -Control Port can be connected with RS485/RS232 devices. - -RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture, -has frequency up to 2.0GHz. Zephyr OS is ported to run on it. - - -- Board features: - - - RAM: 4GB LPDDR4 - - Storage: - - - 32GB eMMC - - M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD) - - TF-Card Slot - - Wireless: - - - Supports WiFi 6 (802.11 AX) - - Supports BT5.0 - - USB: - - - One USB 3.0 - - Two USB 2.0 - - One Type-C - - Ethernet - - M.2 PCIe3.0 (Expand with NVMe SSD) - - LEDs: - - - 1x Power status LED - - Debug - - - UART debug ports for board - - -Supported Features -================== - -The Zephyr roc_rk3568_pc board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| GIC-v3 | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| ARM TIMER | on-chip | system clock | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+-----------+------------+-------------------------------------+ - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 24 MHz. -Cortex-A55 Core runs up to 2.0 GHz. - -Serial Port ------------ - -This board configuration uses a single serial communication channel with the -CPU's UART2. - -Programming and Debugging -************************* - -Use U-Boot to load the zephyr.bin to the memory and kick it: - -.. code-block:: console - - tftp 0x40000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x40000000 - -Use this configuration to run basic Zephyr applications and kernel tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: roc_rk3568_pc - :goals: run - -This will build an image with the synchronization sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build bc695c6df5eb *** - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 0 on roc_rk3568_pc! - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 0 on roc_rk3568_pc! - - -roc_rk3568_pc_smp support, use this configuration to run Zephyr smp applications and subsys tests, -for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: roc_rk3568_pc_smp - :goals: run - -This will build an image with the shell_module sample app, boot it and -display the following ram console output: - -.. code-block:: console - - *** Booting Zephyr OS build bc695c6df5eb *** - I/TC: Secondary CPU 1 initializing - I/TC: Secondary CPU 1 switching to normal world boot - I/TC: Secondary CPU 2 initializing - I/TC: Secondary CPU 2 switching to normal world boot - I/TC: Secondary CPU 3 initializing - I/TC: Secondary CPU 3 switching to normal world boot - Secondary CPU core 1 (MPID:0x100) is up - Secondary CPU core 2 (MPID:0x200) is up - Secondary CPU core 3 (MPID:0x300) is up - - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 1 on roc_rk3568_pc! - thread_a: Hello World from cpu 0 on roc_rk3568_pc! - thread_b: Hello World from cpu 1 on roc_rk3568_pc! - -References -========== - -More information can refer to Firefly official website: -`Firefly website`_. - -.. _Firefly website: - https://en.t-firefly.com/product/industry/rocrk3568pc.html?theme=pc diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml deleted file mode 100644 index 07120b871fa581..00000000000000 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: roc_rk3568_pc_smp -name: Rockchip ROC RK3568 PC SMP -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 1024 -supported: - - smp -testing: - ignore_tags: - - net - - bluetooth diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig b/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig deleted file mode 100644 index 3ffc3f25b416e8..00000000000000 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp_defconfig +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -# Platform Configuration -CONFIG_SOC_SERIES_RK3568=y -CONFIG_SOC_RK3568=y -CONFIG_BOARD_ROC_RK3568_PC=y -CONFIG_ARM_ARCH_TIMER=y - -# Serial Drivers -CONFIG_SERIAL=y -CONFIG_UART_NS16550=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# SMP support -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=4 -CONFIG_MAX_THREAD_BYTES=4 - -# ARMv8 NS world with cache management -CONFIG_ARMV8_A_NS=y -CONFIG_CACHE_MANAGEMENT=y -CONFIG_DCACHE=y - -# PSCI support -CONFIG_PM_CPU_OPS=y -CONFIG_PM_CPU_OPS_PSCI=y - -# Clock support -CONFIG_CLOCK_CONTROL=y -CONFIG_TICKLESS_KERNEL=y diff --git a/boards/arm64/rpi_4b/Kconfig.board b/boards/arm64/rpi_4b/Kconfig.board deleted file mode 100644 index 9b0e9c80985d36..00000000000000 --- a/boards/arm64/rpi_4b/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RPI_4B - bool "Broadcom BCM2711" - depends on SOC_BCM2711 diff --git a/boards/arm64/rpi_4b/Kconfig.defconfig b/boards/arm64/rpi_4b/Kconfig.defconfig deleted file mode 100644 index c04170c57515b7..00000000000000 --- a/boards/arm64/rpi_4b/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "Raspberry Pi 4 Model B" - depends on BOARD_RPI_4B diff --git a/boards/arm64/rpi_4b/doc/index.rst b/boards/arm64/rpi_4b/doc/index.rst deleted file mode 100644 index a3222f368b75d5..00000000000000 --- a/boards/arm64/rpi_4b/doc/index.rst +++ /dev/null @@ -1,71 +0,0 @@ -.. rpi_4b: - -Raspberry Pi 4 Model B (Cortex-A72) -################################### - -Overview -******** -see - -Hardware -******** -see - -Supported Features -================== -The Raspberry Pi 4 Model B board configuration supports the following -hardware features: - -.. list-table:: - :header-rows: 1 - - * - Peripheral - - Kconfig option - - Devicetree compatible - * - GIC-400 - - N/A - - :dtcompatible:`arm,gic-v2` - * - GPIO - - :kconfig:option:`CONFIG_GPIO` - - :dtcompatible:`brcm,bcm2711-gpio` - * - UART (Mini UART) - - :kconfig:option:`CONFIG_SERIAL` - - :dtcompatible:`brcm,bcm2711-aux-uart` - -Other hardware features have not been enabled yet for this board. - -The default configuration can be found in the defconfig file: - - ``boards/arm64/rpi_4b/rpi_4b_defconfig`` - -Programming and Debugging -************************* - -TF Card -======= - -Prepare a TF card with MBR and FAT32. In the root directory of the TF card: - -1. Download and place these firmware files: - - * `bcm2711-rpi-4-b.dtb `_ - * `bootcode.bin `_ - * `start4.elf `_ - -2. Copy ``build/zephyr/zephyr.bin`` -3. Create a ``config.txt``: - - .. code-block:: text - - kernel=zephyr.bin - arm_64bit=1 - enable_uart=1 - uart_2ndstage=1 - -Insert the card and power on the board. You should see the following output on -the serial console (GPIO 14/15): - -.. code-block:: text - - *** Booting Zephyr OS build XXXXXXXXXXXX *** - Hello World! Raspberry Pi 4 Model B! diff --git a/boards/arm64/xenvm/Kconfig.board b/boards/arm64/xenvm/Kconfig.board deleted file mode 100644 index a967e98216aa2e..00000000000000 --- a/boards/arm64/xenvm/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XENVM - bool "Xen Virtual Machine" - depends on SOC_XENVM - select ARM64 diff --git a/boards/arm64/xenvm/Kconfig.defconfig b/boards/arm64/xenvm/Kconfig.defconfig deleted file mode 100644 index 2e8d48bc8f65df..00000000000000 --- a/boards/arm64/xenvm/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_XENVM - -config BUILD_OUTPUT_BIN - default y - -config BOARD - default "xenvm" - -endif # BOARD_XENVM diff --git a/boards/arm64/xenvm/doc/index.rst b/boards/arm64/xenvm/doc/index.rst deleted file mode 100644 index bfeb319aaae6cf..00000000000000 --- a/boards/arm64/xenvm/doc/index.rst +++ /dev/null @@ -1,188 +0,0 @@ -.. xenvm: - -ARMv8 Xen Virtual Machine Example -################################# - -Overview -******** - -This board allows to run Zephyr as Xen guest on any ARMv8 board that supports -ARM Virtualization Extensions. This is example configuration, as almost any VM -configuration is unique in many aspects. - -It provides minimal set of devices: - -* ARM Generic timer -* GICv2/GICv3 - -Hardware -******** -Supported Features -================== - -The following hardware features are supported: - -+--------------+-------------+----------------------+ -| Interface | Controller | Driver/Component | -+==============+=============+======================+ -| GIC | virtualized | interrupt controller | -+--------------+-------------+----------------------+ -| ARM TIMER | virtualized | system clock | -+--------------+-------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -The default configuration using GICv2 can be found in the defconfig file: - ``boards/arm64/xenvm/xenvm_defconfig`` - -The default configuration using GICv3 can be found in the defconfig file: - ``boards/arm64/xenvm/xenvm_gicv3_defconfig`` - -Devices -======== -System Clock ------------- - -This board configuration uses a system clock frequency of 8.32 MHz. This is the -default value, which should be corrected for user's actual hardware. - -You can determine clock frequency of your ARM Generic Timer by inspecting Xen -boot log: - -:: - - (XEN) [ 0.147541] Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 8320 KHz - -Interrupt Controller --------------------- - -Depending on the version of the GIC on your hardware, you may choose one of the -following board configurations: - -- ``xenvm_defconfig`` selects GICv2 -- ``xenvm_gicv3_defconfig`` selects GICv3 - -CPU Core type -------------- - -Default core in this configuration is Cortex A72. Depending on yours actual -hardware you might want to change this option in the same way as Interrupt -Controller configuration. - -Known Problems or Limitations -============================== - -Xen configures guests in runtime by providing device tree that describes guest -environment. On other hand, Zephyr uses static configuration that should be know -at build time. So there are chances, that Zephyr image created with default -configuration would not boot on your hardware. In this case you need to update -configuration by altering device tree and Kconfig options. This will be covered -in detail in next section. - -Most of Xen-specific features are not supported at the moment. This includes: -* XenBus (under development) -* Xen PV drivers - -Now only following features are supported: -* Xen Enlighten memory page -* Xen event channels -* Xen PV console (2 versions: regular ring buffer based for DomU and consoleio for Dom0) -* Xen early console_io interface (mainly for debug purposes - requires debug version of Xen) -* Xen grant tables (granting access for own grants and map/unmap foreign grants) - -Building and Running -******************** - -Use this configuration to run basic Zephyr applications and kernel tests as Xen -guest, for example, with the :zephyr:code-sample:`synchronization` sample: - -- if your hardware is based on GICv2: - -.. code-block:: - - $ west build -b xenvm samples/synchronization - -- if your hardware is based on GICv3: - -.. code-block:: - - $ west build -b xenvm_gicv3 samples/synchronization - -This will build an image with the synchronization sample app. Next, you need to -create guest configuration file :code:`zephyr.conf`. There is example: - -.. code-block:: - - kernel="zephyr.bin" - name="zephyr" - vcpus=1 - memory=16 - gic_version="v2" - on_crash="preserve" - -When using ``xenvm_gicv3`` configuration, you need to remove the ``gic_version`` -parameter or set it to ``"v3"``. - -You need to upload both :code:`zephyr.bin` and :code:`zephyr.conf` to your Dom0 -and then you can run Zephyr by issuing - -.. code-block:: - - $ xl create zephyr.conf - -Next you need to attach to PV console: - -.. code-block:: - - $ xl console zephyr - -Also this can be performed via single command: - -.. code-block:: - - $ xl create -c zephyr.conf - -You will see Zephyr output: - -.. code-block:: console - - *** Booting Zephyr OS build zephyr-v2.4.0-1137-g5803ee1e8183 *** - thread_a: Hello World from cpu 0 on xenvm! - thread_b: Hello World from cpu 0 on xenvm! - thread_a: Hello World from cpu 0 on xenvm! - thread_b: Hello World from cpu 0 on xenvm! - thread_a: Hello World from cpu 0 on xenvm! - -Exit xen virtual console by pressing :kbd:`CTRL+]` - -Updating configuration -********************** - -As was said earlier, Xen describes hardware using device tree and expects that -guest will parse device tree in runtime. On other hand, Zephyr supports only -static, build time configuration. While provided configuration should work on -almost any ARMv8 host running in aarch64 mode, there is no guarantee, that Xen -will not change some values (like RAM base address) in the future. - -Also, frequency of system timer is board specific and should be updated when running -Zephyr xenvm image on new hardware. - -One can make Xen to dump generated DTB by using :code:`LIBXL_DEBUG_DUMP_DTB` -environment variable, like so: - -.. code-block:: - - $ LIBXL_DEBUG_DUMP_DTB=domu-libxl.dtb xl create zephyr.conf - -Then, generated "domu-libxl.dtb" file can be de-compiled using "dtc" tool. - -Use information from de-compiled DTB file to update all related entries in -provided "xenvm.dts" file. If memory layout is also changed, you may need to -update :code:`CONFIG_SRAM_BASE_ADDRESS` as well. - -References -********** - -`Xen ARM with Virtualization Extensions `_ - -`xl.conf (guest configuration file) manual `_ diff --git a/boards/arm64/xenvm/xenvm_gicv3.yaml b/boards/arm64/xenvm/xenvm_gicv3.yaml deleted file mode 100644 index 91026d183d259b..00000000000000 --- a/boards/arm64/xenvm/xenvm_gicv3.yaml +++ /dev/null @@ -1,9 +0,0 @@ -identifier: xenvm_gicv3 -name: ARMv8 Xen Virtual Machine With GICv3 -type: mcu -arch: arm64 -toolchain: - - zephyr - - cross-compile -ram: 16384 -vendor: xen diff --git a/boards/arm64/xenvm/xenvm_gicv3_defconfig b/boards/arm64/xenvm/xenvm_gicv3_defconfig deleted file mode 100644 index 7b6b9afa888e1a..00000000000000 --- a/boards/arm64/xenvm/xenvm_gicv3_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -CONFIG_SOC_XENVM=y -CONFIG_BOARD_XENVM=y - -# Enable UART driver -CONFIG_SERIAL=y - -CONFIG_MAX_XLAT_TABLES=24 - -# Enable console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -# Enable logging subsys -CONFIG_LOG=y -CONFIG_LOG_MODE_MINIMAL=n - -CONFIG_USERSPACE=n - -CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y diff --git a/boards/arturo182/index.rst b/boards/arturo182/index.rst new file mode 100644 index 00000000000000..d9093d36c102e7 --- /dev/null +++ b/boards/arturo182/index.rst @@ -0,0 +1,10 @@ +.. _boards-arturo182: + +Arturo182 +######### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arturo182/serpente/Kconfig.serpente b/boards/arturo182/serpente/Kconfig.serpente new file mode 100644 index 00000000000000..3c22b1b359bc02 --- /dev/null +++ b/boards/arturo182/serpente/Kconfig.serpente @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Alexander Falb +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SERPENTE + select SOC_SAMD21E18A diff --git a/boards/arm/serpente/board.cmake b/boards/arturo182/serpente/board.cmake similarity index 100% rename from boards/arm/serpente/board.cmake rename to boards/arturo182/serpente/board.cmake diff --git a/boards/arturo182/serpente/board.yml b/boards/arturo182/serpente/board.yml new file mode 100644 index 00000000000000..e5775329a06e33 --- /dev/null +++ b/boards/arturo182/serpente/board.yml @@ -0,0 +1,5 @@ +board: + name: serpente + vendor: solderparty + socs: + - name: samd21e18a diff --git a/boards/arm/serpente/doc/img/serpente.jpg b/boards/arturo182/serpente/doc/img/serpente.jpg similarity index 100% rename from boards/arm/serpente/doc/img/serpente.jpg rename to boards/arturo182/serpente/doc/img/serpente.jpg diff --git a/boards/arturo182/serpente/doc/index.rst b/boards/arturo182/serpente/doc/index.rst new file mode 100644 index 00000000000000..4b6bf5e7390c31 --- /dev/null +++ b/boards/arturo182/serpente/doc/index.rst @@ -0,0 +1,125 @@ +.. _serpente: + +Arturo182 Serpente +################## + +Overview +******** + +The Serpente is a very small low-cost development and prototyping +board equipped with 4MiB flash storage, a PWM enabled RGB led and 6 I/O pins. +The board comes with 3 different USB connector options: USB Type-C plug, +USB Type-C socket and USB Type-A plug. + +.. image:: img/serpente.jpg + :align: center + :alt: Serpente Boards + +Hardware +******** + +- ATSAMD21E18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- Extra 4MiB SPI flash memory +- RGB User LED +- Reset button +- Native USB port + +Supported Features +================== + +The Serpente board configuration supports the +following hardware features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/arturo182/serpente/serpente_defconfig`. + +Connections and IOs +=================== + +The `Serpente documentation`_ has detailed information about the board +including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 8MHz internal oscillator +with the on-chip PLL generating the 48 MHz system clock. + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which prints "Hello World!" +to the host PC. + +Programming and Debugging +========================= + +The Serpente ships the BOSSA compatible UF2 bootloader. The bootloader +can be entered by quickly tapping the reset button twice. + +Flashing +======== + +#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: serpente + :goals: build + :compact: + +#. Connect the Serpente to your host computer using USB + + +#. Tap the reset button twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: serpente + :goals: flash + :compact: + + You should see the User LED blink. + +References +********** + +.. target-notes:: + +.. _Serpente documentation: + https://www.solder.party/docs/serpente/r2/ + +.. _pinouts: + https://www.solder.party/docs/serpente/r2/pinout/ + +.. _schematic: + https://www.solder.party/docs/serpente/r2/downloads/ diff --git a/boards/arm/atsamc21n_xpro/pre_dt_board.cmake b/boards/arturo182/serpente/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamc21n_xpro/pre_dt_board.cmake rename to boards/arturo182/serpente/pre_dt_board.cmake diff --git a/boards/arm/serpente/serpente-pinctrl.dtsi b/boards/arturo182/serpente/serpente-pinctrl.dtsi similarity index 100% rename from boards/arm/serpente/serpente-pinctrl.dtsi rename to boards/arturo182/serpente/serpente-pinctrl.dtsi diff --git a/boards/arm/serpente/serpente.dts b/boards/arturo182/serpente/serpente.dts similarity index 100% rename from boards/arm/serpente/serpente.dts rename to boards/arturo182/serpente/serpente.dts diff --git a/boards/arm/serpente/serpente.yaml b/boards/arturo182/serpente/serpente.yaml similarity index 96% rename from boards/arm/serpente/serpente.yaml rename to boards/arturo182/serpente/serpente.yaml index e93d19f463aaae..df7cff28db10cb 100644 --- a/boards/arm/serpente/serpente.yaml +++ b/boards/arturo182/serpente/serpente.yaml @@ -2,12 +2,12 @@ identifier: serpente name: SERPENTE type: mcu arch: arm -ram: 32 -flash: 256 toolchain: - zephyr - gnuarmemb - xtools +flash: 256 +ram: 32 supported: - adc - counter @@ -17,5 +17,6 @@ supported: - pwm - spi - uart + - usb - usb_device - watchdog diff --git a/boards/arturo182/serpente/serpente_defconfig b/boards/arturo182/serpente/serpente_defconfig new file mode 100644 index 00000000000000..5690d6c73cdb5f --- /dev/null +++ b/boards/arturo182/serpente/serpente_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/aspeed/ast1030_evb/Kconfig.ast1030_evb b/boards/aspeed/ast1030_evb/Kconfig.ast1030_evb new file mode 100644 index 00000000000000..ecae95bcd449f6 --- /dev/null +++ b/boards/aspeed/ast1030_evb/Kconfig.ast1030_evb @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Aspeed AST1030 evaluation board configuration +# +# Copyright (c) 2021 Aspeed Technology Inc. + +config BOARD_AST1030_EVB + select SOC_AST1030 diff --git a/boards/arm/ast1030_evb/ast1030_evb.dts b/boards/aspeed/ast1030_evb/ast1030_evb.dts similarity index 100% rename from boards/arm/ast1030_evb/ast1030_evb.dts rename to boards/aspeed/ast1030_evb/ast1030_evb.dts diff --git a/boards/arm/ast1030_evb/ast1030_evb.yaml b/boards/aspeed/ast1030_evb/ast1030_evb.yaml similarity index 100% rename from boards/arm/ast1030_evb/ast1030_evb.yaml rename to boards/aspeed/ast1030_evb/ast1030_evb.yaml diff --git a/boards/arm/ast1030_evb/ast1030_evb_defconfig b/boards/aspeed/ast1030_evb/ast1030_evb_defconfig similarity index 92% rename from boards/arm/ast1030_evb/ast1030_evb_defconfig rename to boards/aspeed/ast1030_evb/ast1030_evb_defconfig index 62278d4421327d..aa48ee095f7eb4 100644 --- a/boards/arm/ast1030_evb/ast1030_evb_defconfig +++ b/boards/aspeed/ast1030_evb/ast1030_evb_defconfig @@ -2,7 +2,7 @@ # # Copyright (c) 2021 Aspeed Technology Inc. # -CONFIG_SOC_SERIES_AST10X0=y + CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 CONFIG_MAIN_STACK_SIZE=4096 CONFIG_FLASH_SIZE=0 diff --git a/boards/aspeed/ast1030_evb/board.yml b/boards/aspeed/ast1030_evb/board.yml new file mode 100644 index 00000000000000..e129a899425da1 --- /dev/null +++ b/boards/aspeed/ast1030_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: ast1030_evb + vendor: aspeed + socs: + - name: ast1030 diff --git a/boards/arm/ast1030_evb/doc/ast1030_evb.jpg b/boards/aspeed/ast1030_evb/doc/ast1030_evb.jpg similarity index 100% rename from boards/arm/ast1030_evb/doc/ast1030_evb.jpg rename to boards/aspeed/ast1030_evb/doc/ast1030_evb.jpg diff --git a/boards/aspeed/ast1030_evb/doc/index.rst b/boards/aspeed/ast1030_evb/doc/index.rst new file mode 100644 index 00000000000000..fb7d83d074bd29 --- /dev/null +++ b/boards/aspeed/ast1030_evb/doc/index.rst @@ -0,0 +1,93 @@ +.. _ast1030_evb: + +AST1030_EVB +################### + +Overview +******** + +The AST1030_EVB kit is a development platform to evaluate the +Aspeed AST10x0 series SOCs. This board needs to be mated with +part number AST1030. + +.. image:: ast1030_evb.jpg + :align: center + :alt: AST1030 Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 768 KB on-chip SRAM for instruction and data memory +- 1 MB on-chip Flash memory for boot ROM and data storage +- SPI interface +- UART interface +- I2C/I3C interface +- FAN PWM interface +- ADC interface +- JTAG interface +- USB interface +- LPC interface +- eSPI interface + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in +:zephyr_file:`boards/aspeed/ast1030_evb/ast1030_evb_defconfig` + + +Connections and IOs +=================== + +Aspeed to provide the schematic for this board. + +System Clock +============ + +The AST1030 SOC is configured to use external 25MHz clock input to generate 200Mhz system clock by +the on-chip PLL. + +Serial Port +=========== + +UART5 is configured for serial logs. The default serial setup is 115200 8N1. + + +Programming and Debugging +************************* + +This board comes with a JTAG port which facilitates debugging using a single physical connection. + +Flashing +======== + +Build application as usual for the ``ast1030_evb`` board, and flash +using SF100 SPI Flash programmer. See the +`Aspeed Zephyr SDK User Guide`_ for more information. + + +Debugging +========= + +Use JTAG or SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Aspeed Zephyr SDK User Guide: + https://github.com/AspeedTech-BMC/zephyr/releases/download/v00.01.03/Aspeed_Zephy_SDK_User_Guide_v00.01.03.pdf diff --git a/boards/aspeed/index.rst b/boards/aspeed/index.rst new file mode 100644 index 00000000000000..3647c2f2101110 --- /dev/null +++ b/boards/aspeed/index.rst @@ -0,0 +1,10 @@ +.. _boards-aspeed: + +ASPEED Technology Inc. +###################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/degu_evk/Kconfig b/boards/atmark_techno/degu_evk/Kconfig similarity index 100% rename from boards/arm/degu_evk/Kconfig rename to boards/atmark_techno/degu_evk/Kconfig diff --git a/boards/atmark_techno/degu_evk/Kconfig.defconfig b/boards/atmark_techno/degu_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..286008a36ab97d --- /dev/null +++ b/boards/atmark_techno/degu_evk/Kconfig.defconfig @@ -0,0 +1,33 @@ +# Degu Evaluation Kit configuration + +# Copyright (c) 2019 Atmark Techno, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DEGU_EVK + +if USB_DEVICE_STACK + +config USB_DEVICE_PRODUCT + default "Degu Evaluation Kit" + +config UART_INTERRUPT_DRIVEN + default y + +config UART_LINE_CTRL + default y + +endif # USB_DEVICE_STACK + +if LOG + +# Logger cannot use itself to log +config USB_CDC_ACM_LOG_LEVEL + default 0 + +# Set USB log level to error only +config USB_DEVICE_LOG_LEVEL + default 1 + +endif # LOG + +endif # BOARD_DEGU_EVK diff --git a/boards/atmark_techno/degu_evk/Kconfig.degu_evk b/boards/atmark_techno/degu_evk/Kconfig.degu_evk new file mode 100644 index 00000000000000..b9cea5477f58b6 --- /dev/null +++ b/boards/atmark_techno/degu_evk/Kconfig.degu_evk @@ -0,0 +1,7 @@ +# Degu Evaluation Kit configuration + +# Copyright (c) 2019 Atmark Techno, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DEGU_EVK + select SOC_NRF52840_QIAA diff --git a/boards/arm/degu_evk/board.cmake b/boards/atmark_techno/degu_evk/board.cmake similarity index 100% rename from boards/arm/degu_evk/board.cmake rename to boards/atmark_techno/degu_evk/board.cmake diff --git a/boards/atmark_techno/degu_evk/board.yml b/boards/atmark_techno/degu_evk/board.yml new file mode 100644 index 00000000000000..19859fc1e7de4f --- /dev/null +++ b/boards/atmark_techno/degu_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: degu_evk + vendor: atmarktechno + socs: + - name: nrf52840 diff --git a/boards/arm/degu_evk/degu_evk-pinctrl.dtsi b/boards/atmark_techno/degu_evk/degu_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/degu_evk/degu_evk-pinctrl.dtsi rename to boards/atmark_techno/degu_evk/degu_evk-pinctrl.dtsi diff --git a/boards/arm/degu_evk/degu_evk.dts b/boards/atmark_techno/degu_evk/degu_evk.dts similarity index 100% rename from boards/arm/degu_evk/degu_evk.dts rename to boards/atmark_techno/degu_evk/degu_evk.dts diff --git a/boards/arm/degu_evk/degu_evk.yaml b/boards/atmark_techno/degu_evk/degu_evk.yaml similarity index 100% rename from boards/arm/degu_evk/degu_evk.yaml rename to boards/atmark_techno/degu_evk/degu_evk.yaml diff --git a/boards/atmark_techno/degu_evk/degu_evk_defconfig b/boards/atmark_techno/degu_evk/degu_evk_defconfig new file mode 100644 index 00000000000000..ceed266a40205d --- /dev/null +++ b/boards/atmark_techno/degu_evk/degu_evk_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable USB (for CDC ACM console) +CONFIG_USB_DEVICE_STACK=y + +# Additional board options +CONFIG_GPIO=y + +# Required to enable 3V3 power rail and Vin1 monitor +CONFIG_REGULATOR=y diff --git a/boards/arm/degu_evk/doc/img/degu_evk.jpg b/boards/atmark_techno/degu_evk/doc/img/degu_evk.jpg similarity index 100% rename from boards/arm/degu_evk/doc/img/degu_evk.jpg rename to boards/atmark_techno/degu_evk/doc/img/degu_evk.jpg diff --git a/boards/arm/degu_evk/doc/index.rst b/boards/atmark_techno/degu_evk/doc/index.rst similarity index 100% rename from boards/arm/degu_evk/doc/index.rst rename to boards/atmark_techno/degu_evk/doc/index.rst diff --git a/boards/arm/bl652_dvk/pre_dt_board.cmake b/boards/atmark_techno/degu_evk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl652_dvk/pre_dt_board.cmake rename to boards/atmark_techno/degu_evk/pre_dt_board.cmake diff --git a/boards/atmark_techno/index.rst b/boards/atmark_techno/index.rst new file mode 100644 index 00000000000000..f49e927fdabb7d --- /dev/null +++ b/boards/atmark_techno/index.rst @@ -0,0 +1,10 @@ +.. _boards-atmark-techno: + +Atmark Techno +############# + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/atmel/index.rst b/boards/atmel/index.rst new file mode 100644 index 00000000000000..94d1cafb403e15 --- /dev/null +++ b/boards/atmel/index.rst @@ -0,0 +1,10 @@ +.. _boards-atmel: + +Atmel Corporation +################# + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/atmel/sam/sam4e_xpro/Kconfig.defconfig b/boards/atmel/sam/sam4e_xpro/Kconfig.defconfig new file mode 100644 index 00000000000000..f5e3a93e0c0e8a --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam/sam4e_xpro/Kconfig.sam4e_xpro b/boards/atmel/sam/sam4e_xpro/Kconfig.sam4e_xpro new file mode 100644 index 00000000000000..d545050aa9053f --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/Kconfig.sam4e_xpro @@ -0,0 +1,5 @@ +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM4E_XPRO + select SOC_SAM4E16E diff --git a/boards/arm/sam4e_xpro/board.cmake b/boards/atmel/sam/sam4e_xpro/board.cmake similarity index 100% rename from boards/arm/sam4e_xpro/board.cmake rename to boards/atmel/sam/sam4e_xpro/board.cmake diff --git a/boards/atmel/sam/sam4e_xpro/board.yml b/boards/atmel/sam/sam4e_xpro/board.yml new file mode 100644 index 00000000000000..017a22d62cdc5c --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: sam4e_xpro + vendor: atmel + socs: + - name: sam4e16e diff --git a/boards/arm/sam4e_xpro/doc/img/sam4e_xpro.jpg b/boards/atmel/sam/sam4e_xpro/doc/img/sam4e_xpro.jpg similarity index 100% rename from boards/arm/sam4e_xpro/doc/img/sam4e_xpro.jpg rename to boards/atmel/sam/sam4e_xpro/doc/img/sam4e_xpro.jpg diff --git a/boards/atmel/sam/sam4e_xpro/doc/index.rst b/boards/atmel/sam/sam4e_xpro/doc/index.rst new file mode 100644 index 00000000000000..18d0836c6d6ff0 --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/doc/index.rst @@ -0,0 +1,201 @@ +.. _sam4e_xpro: + +SAM4E Xplained Pro +################### + +Overview +******** + +The SAM4E Xplained Pro evaluation kit is a development platform to evaluate the +Atmel SAM4E series microcontrollers. + +.. image:: img/sam4e_xpro.jpg + :align: center + :alt: SAM4E Xplained Pro + +Hardware +******** + +- ATSAM4E16E ARM Cortex-M4F Processor +- 12 MHz crystal oscillator +- internal 32.768 kHz crystal oscillator +- 2 x IS61WV5128BLL 4Mb SRAM +- MT29F2G08ABAEAWP 2Gb NAND +- SD card connector +- CAN-bus (TLE7250GVIOXUMA1 CAN Transceiver) +- Ethernet port (KSZ8081MNXIA phy) +- Micro-AB USB device +- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data + Gateway Interface (DGI) +- One reset and one user pushbutton +- 1 yellow user LEDs + + +Supported Features +================== + +The sam4e_xpro board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| AFEC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | hwinfo | ++-----------+------------+-------------------------------------+ +| HSMCI | on-chip | sdhc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig`. + +Connections and IOs +=================== + +The `SAM4E Xplained Pro User Guide`_ has detailed information about board +connections. Download the `SAM4E Xplained Pro documentation`_ for more detail. + +System Clock +============ + +The SAM4E MCU is configured to use the 12 MHz internal oscillator on the board +with the on-chip PLL to generate an 120 MHz system clock. + +Serial Port +=========== + +The ATSAM4E16E MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is +configured for the console and is available as a Virtual COM Port by EDBG USB +chip. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM4E MCU requires the `OpenOCD tool`_. +By default a factory new SAM4E chip will boot SAM-BA boot loader located in +the ROM, not the flashed image. This is determined by the value of GPNVM1 +(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is +set to 1 changing the default behavior to boot from Flash. + +If your chip has a security bit GPNVM0 set you will be unable to program flash +memory or connect to it via a debug interface. The only way to clear GPNVM0 +is to perform a chip erase procedure that will erase all GPNVM bits and the full +contents of the SAM4E flash memory: + +- With the board power off, set a jumper on the J304 header. +- Turn the board power on. The jumper can be removed soon after the power is on + (flash erasing procedure is started when the erase line is asserted for at + least 230ms) + +Flashing +======== + +For flash the board Zephyr provides two paths. One uses the default OpenOCD +tool and the second one uses :ref:`atmel_sam_ba_bootloader`. + +Using OpenOCD +------------- + +#. Connect the SAM4E Xplained Pro board to your host computer using the USB + debug port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4e_xpro + :goals: build flash + +Using SAM-BA bootloader +----------------------- + +#. Close the ``ERASE`` jumper on the SAM4E Xplained Pro board. Power on the + board for 10s. + +#. Open the ``ERASE`` jumper. + +#. Connect the SAM4E Xplained Pro board to your host computer using the SoC + USB port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4e_xpro + :goals: build + + .. code-block:: console + + $ west flash -r bossac + +Visualizing the message +----------------------- + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Press reset button + + You should see "Hello World! sam4e_xpro" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4e_xpro + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _SAM4E Xplained Pro User Guide: + http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42216-SAM4E-Xplained-Pro_User-Guide.pdf + +.. _SAM4E Xplained Pro documentation: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4E-Xplained-Pro_Design-Documentation.zip + +.. _OpenOCD tool: + http://openocd.org/ + +.. _SAM-BA: + https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/arm/sam4e_xpro/sam4e_xpro-pinctrl.dtsi b/boards/atmel/sam/sam4e_xpro/sam4e_xpro-pinctrl.dtsi similarity index 96% rename from boards/arm/sam4e_xpro/sam4e_xpro-pinctrl.dtsi rename to boards/atmel/sam/sam4e_xpro/sam4e_xpro-pinctrl.dtsi index fb19be497ca6a3..29f51f1e13cf61 100644 --- a/boards/arm/sam4e_xpro/sam4e_xpro-pinctrl.dtsi +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro-pinctrl.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2022-2023, Gerson Fernando Budke + * Copyright (c) 2022-2024, Gerson Fernando Budke * SPDX-License-Identifier: Apache-2.0 */ @@ -105,5 +105,4 @@ ; }; }; - }; diff --git a/boards/arm/sam4e_xpro/sam4e_xpro.dts b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts similarity index 100% rename from boards/arm/sam4e_xpro/sam4e_xpro.dts rename to boards/atmel/sam/sam4e_xpro/sam4e_xpro.dts diff --git a/boards/arm/sam4e_xpro/sam4e_xpro.yaml b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml similarity index 76% rename from boards/arm/sam4e_xpro/sam4e_xpro.yaml rename to boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml index 76ca997b1a0c90..561b06b8afe42d 100644 --- a/boards/arm/sam4e_xpro/sam4e_xpro.yaml +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml @@ -6,11 +6,19 @@ toolchain: - zephyr - gnuarmemb - xtools +flash: 1024 +ram: 128 supported: - - netif:eth + - adc + - counter - gpio - - spi + - hwinfo + - i2c + - netif:eth + - pwm - sdhc + - spi + - uart - watchdog - xpro_gpio - xpro_i2c diff --git a/boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig b/boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig new file mode 100644 index 00000000000000..cf189ca136bdee --- /dev/null +++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam4e_xpro/support/openocd.cfg b/boards/atmel/sam/sam4e_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/sam4e_xpro/support/openocd.cfg rename to boards/atmel/sam/sam4e_xpro/support/openocd.cfg diff --git a/boards/atmel/sam/sam4l_ek/Kconfig.sam4l_ek b/boards/atmel/sam/sam4l_ek/Kconfig.sam4l_ek new file mode 100644 index 00000000000000..be93be83111161 --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/Kconfig.sam4l_ek @@ -0,0 +1,5 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM4L_EK + select SOC_SAM4LC4C diff --git a/boards/arm/sam4l_ek/board.cmake b/boards/atmel/sam/sam4l_ek/board.cmake similarity index 100% rename from boards/arm/sam4l_ek/board.cmake rename to boards/atmel/sam/sam4l_ek/board.cmake diff --git a/boards/atmel/sam/sam4l_ek/board.yml b/boards/atmel/sam/sam4l_ek/board.yml new file mode 100644 index 00000000000000..7045ba351ce083 --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/board.yml @@ -0,0 +1,5 @@ +board: + name: sam4l_ek + vendor: atmel + socs: + - name: sam4lc4c diff --git a/boards/arm/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg b/boards/atmel/sam/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg similarity index 100% rename from boards/arm/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg rename to boards/atmel/sam/sam4l_ek/doc/img/atmel-sam4l-ek-callouts.jpg diff --git a/boards/atmel/sam/sam4l_ek/doc/index.rst b/boards/atmel/sam/sam4l_ek/doc/index.rst new file mode 100644 index 00000000000000..a28b0728836ea6 --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/doc/index.rst @@ -0,0 +1,176 @@ +.. _sam4l_ek: + +SAM4L-EK +######## + +Overview +******** + +The SAM4L series embeds picoPower technology for ultra-low power consumption. +Combined power control techniques are used to bring active current consumption +down to 90μA/MHz. The device allows a wide range of configurations giving the +user the ability to balance between the lowest possible power consumption and +the feature set selected for the application. The WAIT and RETENTION modes +provide full logic and RAM retention, associated with fast wake-up capability +(<1.5μs) and a very low consumption of, respectively, 3 μA and 1.5 μA. In +addition, WAIT mode supports SleepWalking features. In BACKUP mode, CPU, +peripherals and RAM are powered off consuming less than 0.9μA with external +interrupt wake-up support. + +The SAM4L-EK is a full featured design to develop for Atmel SAM4L SoC series. +The kit is equipped with a rich set of peripherals that make the ATSAM4L-EK a +perfect evaluation platform. Download the `SAM4L-EK Online User Guide`_ for +more details. + +.. image:: img/atmel-sam4l-ek-callouts.jpg + :align: center + :alt: SAM4L-EK + +Hardware +******** + +- ATSAM4LC4C ARM Cortex-M4 Processor +- 12 MHz crystal oscillator +- 32.768 kHz crystal oscillator +- 1 Micro-AB USB OTG host/device +- 1 AT86RF2xx IEEE 802.15.4 transceiver connector +- 1 RS-485 full duplex interface +- 1 Sensor Xplained board connector +- 1 Audio Jack connector 3.5mm +- 1 Dedicated Board Monitor MCU + + - Power measurement (VDDIN, VDDIO, VDDANA) + - 1 OLED Display (128x64) + - 5 LEDs + - 1 Joystick + - 1 USART + - 1 TWI +- 1 40x4 LCD Segment Display +- 1 user touch button and One user pushbutton +- 1 user LED +- 1 QTouch Slider +- 1 QTouch Button +- 1 TEMT6000 Light Sensor +- 1 AT25DF641A Serial NOR Flash + +Supported Features +================== + +The sam4l_ek board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique 120 bit serial number | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| TWIM | on-chip | i2c master port-interrupt | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb device | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig`. + +Connections and IOs +=================== + +The `SAM4L-EK Design Documentation`_ has detailed information about board +connections. Download the `SAM4L-EK Design Documentation`_ for more details. + +System Clock +============ + +The SAM4L MCU is configured to use the 12 MHz internal oscillator on the board +with the on-chip PLL to generate an 48 MHz system clock. + +Serial Port +=========== + +The ATSAM4LC4C MCU has 4 USARTs. One of the USARTs (USART2) is connected on +the embedded debug unit and can works as a console. The USART0 is shared +between all others headers and RS-485 port. + +Programming and Debugging +************************* + +The SAM4L-EK board have a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the SAM4LC4C chip. You can use Ozone or JLink to communicate with +the SAM4LC4C. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the SAM4L-EK board to your host computer using the USB debug port. + Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4l_ek + :goals: build flash + + You should see "Hello World! sam4l_ek" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4l_ek + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _SAM4L-EK Online User Guide: + http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42026-ATSAM4L-EK-User-Guide_ApplicationNote_AVR32850.pdf + +.. _SAM4L-EK Design Documentation: + http://ww1.microchip.com/downloads/en/DeviceDoc/doc42027_SAM4L-EK_Design_Documentation.PDF + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/sam4l_ek/sam4l_ek-pinctrl.dtsi b/boards/atmel/sam/sam4l_ek/sam4l_ek-pinctrl.dtsi similarity index 100% rename from boards/arm/sam4l_ek/sam4l_ek-pinctrl.dtsi rename to boards/atmel/sam/sam4l_ek/sam4l_ek-pinctrl.dtsi diff --git a/boards/arm/sam4l_ek/sam4l_ek.dts b/boards/atmel/sam/sam4l_ek/sam4l_ek.dts similarity index 100% rename from boards/arm/sam4l_ek/sam4l_ek.dts rename to boards/atmel/sam/sam4l_ek/sam4l_ek.dts diff --git a/boards/arm/sam4l_ek/sam4l_ek.yaml b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml similarity index 78% rename from boards/arm/sam4l_ek/sam4l_ek.yaml rename to boards/atmel/sam/sam4l_ek/sam4l_ek.yaml index cdadbee508a2fc..f33959c7805951 100644 --- a/boards/arm/sam4l_ek/sam4l_ek.yaml +++ b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml @@ -2,16 +2,20 @@ identifier: sam4l_ek name: SAM4L-EK type: mcu arch: arm -flash: 256 -ram: 32 toolchain: - zephyr - gnuarmemb - xtools +flash: 256 +ram: 32 supported: + - counter - gpio + - entropy + - hwinfo - i2c - spi - - usart + - uart + - usb - usb_device vendor: atmel diff --git a/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig b/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig new file mode 100644 index 00000000000000..6c902f537d7c2b --- /dev/null +++ b/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/atmel/sam/sam4s_xplained/Kconfig.sam4s_xplained b/boards/atmel/sam/sam4s_xplained/Kconfig.sam4s_xplained new file mode 100644 index 00000000000000..08f005f16d0c5e --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/Kconfig.sam4s_xplained @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM4S_XPLAINED + select SOC_SAM4S16C diff --git a/boards/arm/sam4s_xplained/board.cmake b/boards/atmel/sam/sam4s_xplained/board.cmake similarity index 100% rename from boards/arm/sam4s_xplained/board.cmake rename to boards/atmel/sam/sam4s_xplained/board.cmake diff --git a/boards/atmel/sam/sam4s_xplained/board.yml b/boards/atmel/sam/sam4s_xplained/board.yml new file mode 100644 index 00000000000000..c406301245ba1b --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/board.yml @@ -0,0 +1,5 @@ +board: + name: sam4s_xplained + vendor: atmel + socs: + - name: sam4s16c diff --git a/boards/arm/sam4s_xplained/doc/img/sam4s_xplained.jpg b/boards/atmel/sam/sam4s_xplained/doc/img/sam4s_xplained.jpg similarity index 100% rename from boards/arm/sam4s_xplained/doc/img/sam4s_xplained.jpg rename to boards/atmel/sam/sam4s_xplained/doc/img/sam4s_xplained.jpg diff --git a/boards/atmel/sam/sam4s_xplained/doc/index.rst b/boards/atmel/sam/sam4s_xplained/doc/index.rst new file mode 100644 index 00000000000000..9c1b999eca91fe --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/doc/index.rst @@ -0,0 +1,190 @@ +.. _sam4s_xplained: + +SAM4S Xplained +############## + +Overview +******** + +The SAM4S Xplained evaluation kit is a development platform to evaluate the +Atmel SAM4S series microcontrollers. + +.. image:: img/sam4s_xplained.jpg + :align: center + :alt: SAM4S Xplained + +Hardware +******** + +- ATSAM4S16C ARM Cortex-M4 Processor +- 12 MHz crystal oscillator +- internal 32.768 kHz crystal oscillator +- IS66WV51216DALL 8 Mb SRAM +- Micro-AB USB device +- Micro-AB USB debug interface supporting SEGGER OB and Virtual COM Port and + Data +- One reset and one user pushbutton +- 2 yellow user LEDs +- IC pads for external flash chip + +Supported Features +================== + +The sam4s_xplained board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| SMC | on-chip | memc (PSRAM) | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig`. + +Connections and IOs +=================== + +Download the `SAM4S Xplained Design Files`_ for more information. It has +full schematic and gerbers files. + +System Clock +============ + +The SAM4S MCU is configured to use the 12 MHz internal oscillator on the board +with the on-chip PLL to generate an 84 MHz system clock. + +Serial Port +=========== + +The ATSAM4S16C MCU has 2 UARTs and 2 USARTs. One of the UARTs (UART0) is +connected to the Segger J-Link OB chip (the AT91SAM3U4 is programmed to be +Segger J-Link OB). Segger J-Link OB brings the UART out as a virtual COM port. +The section flashing uses the UART from the Segger USB debug connection. + +Programming and Debugging +************************* + +The SAM4S Xplained board comes with Segger +`J-Link OB `_. This provides a debug +interface to the SAM4S16C chip. You can use Ozone or JLink to communicate with +the SAM4S16C. + +Flashing +======== + +For flash the board Zephyr provides two paths. One uses the default JLink +tool and the second one uses :ref:`atmel_sam_ba_bootloader`. + +Using JLink +------------- + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Connect the SAM4S Xplained board to your host computer using the USB debug + port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4s_xplained + :goals: build flash + + +Using SAM-BA bootloader +----------------------- + +#. Close the ``J25`` jumper on the SAM4S Xplained board. Power on the board + for 10s. + +#. Open the ``J25`` jumper. + +#. Connect the SAM4S Xplained board to your host computer using the SoC USB + port. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4s_xplained + :goals: build + + .. code-block:: console + + $ west flash -r bossac + + +Visualizing the message +----------------------- + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Press reset button + + You should see "Hello World! sam4s_xplained" in your terminal. + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam4s_xplained + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _SAM4S Xplained Online User Guide: + http://ww1.microchip.com/downloads/en/devicedoc/atmel-42075-sam4s-xplained-pro_user-guide.pdf + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink + +.. _SAM4S Xplained Design Files: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAM4S-XPLD__KitsFiles.zip diff --git a/boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi b/boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi similarity index 100% rename from boards/arm/sam4s_xplained/sam4s_xplained-pinctrl.dtsi rename to boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi diff --git a/boards/arm/sam4s_xplained/sam4s_xplained.dts b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts similarity index 100% rename from boards/arm/sam4s_xplained/sam4s_xplained.dts rename to boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts diff --git a/boards/arm/sam4s_xplained/sam4s_xplained.yaml b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml similarity index 89% rename from boards/arm/sam4s_xplained/sam4s_xplained.yaml rename to boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml index 20e5949b0feab3..0cc1a4f9debe02 100644 --- a/boards/arm/sam4s_xplained/sam4s_xplained.yaml +++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml @@ -6,9 +6,13 @@ toolchain: - zephyr - gnuarmemb - xtools +flash: 1024 +ram: 128 supported: - adc + - counter - gpio + - hwinfo - memc - pwm - spi @@ -17,5 +21,4 @@ supported: - xplained_i2c - xplained_serial - xplained_spi - - hwinfo vendor: atmel diff --git a/boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig b/boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig new file mode 100644 index 00000000000000..91293d9a64121c --- /dev/null +++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_MEMC=y diff --git a/boards/atmel/sam/sam_e70_xplained/Kconfig.defconfig b/boards/atmel/sam/sam_e70_xplained/Kconfig.defconfig new file mode 100644 index 00000000000000..59f0676d06b57b --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Atmel SMART SAM E70 Xplained Board configuration + +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if ETH_SAM_GMAC + +# Read MAC address from AT24MAC402 EEPROM + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS + default 0x9A + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE + default 1 + +config ETH_SAM_GMAC_MAC_I2C_EEPROM + default y + select I2C + +endif # ETH_SAM_GMAC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam/sam_e70_xplained/Kconfig.sam_e70_xplained b/boards/atmel/sam/sam_e70_xplained/Kconfig.sam_e70_xplained new file mode 100644 index 00000000000000..8cff5c27738422 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/Kconfig.sam_e70_xplained @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM_E70_XPLAINED + select SOC_SAME70Q21 if BOARD_SAM_E70_XPLAINED_SAME70Q21 + select SOC_SAME70Q21B if BOARD_SAM_E70_XPLAINED_SAME70Q21B diff --git a/boards/arm/sam_e70_xplained/board.cmake b/boards/atmel/sam/sam_e70_xplained/board.cmake similarity index 100% rename from boards/arm/sam_e70_xplained/board.cmake rename to boards/atmel/sam/sam_e70_xplained/board.cmake diff --git a/boards/atmel/sam/sam_e70_xplained/board.yml b/boards/atmel/sam/sam_e70_xplained/board.yml new file mode 100644 index 00000000000000..1308363814ac12 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/board.yml @@ -0,0 +1,6 @@ +board: + name: sam_e70_xplained + vendor: atmel + socs: + - name: same70q21 + - name: same70q21b diff --git a/boards/arm/sam_e70_xplained/doc/img/sam_e70_xplained.jpg b/boards/atmel/sam/sam_e70_xplained/doc/img/sam_e70_xplained.jpg similarity index 100% rename from boards/arm/sam_e70_xplained/doc/img/sam_e70_xplained.jpg rename to boards/atmel/sam/sam_e70_xplained/doc/img/sam_e70_xplained.jpg diff --git a/boards/atmel/sam/sam_e70_xplained/doc/index.rst b/boards/atmel/sam/sam_e70_xplained/doc/index.rst new file mode 100644 index 00000000000000..bab33f538c461c --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/doc/index.rst @@ -0,0 +1,195 @@ +.. _sam_e70_xplained: + +SAM E70(B) Xplained +################### + +Overview +******** + +The SAM E70 Xplained evaluation kit is a development platform to evaluate the +Atmel SAM E70 series microcontrollers. The current version allows to use both +IC variations ATSAME70Q21A(B). + +.. image:: img/sam_e70_xplained.jpg + :align: center + :alt: SAM E70 Xplained + +Hardware +******** + +- ATSAME70Q21A(B) ARM Cortex-M7 Processor +- 12 MHz crystal oscillator +- 32.768 kHz crystal oscillator (not populated) +- AT24MAC402 EEPROM +- IS42S16100E 16 Mb SDRAM +- SD card connector +- Ethernet port +- Micro-AB USB device +- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data + Gateway Interface (DGI) +- JTAG interface connector +- One reset and one user pushbutton +- One green user LED + +Supported Features +================== + +The sam_e70_xplained board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| AFEC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN FD | on-chip | can | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| XDMAC | on-chip | dma | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig`. + +Connections and IOs +=================== + +The `SAME70-XPLD User Guide`_ has detailed information about board connections. + +System Clock +============ + +The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 300 MHz system clock. + +Serial Port +=========== + +The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the USARTs is +configured for the console and is available as a Virtual COM Port via EDBG USB +chip. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. +Support for Atmel SAM E microcontroller series was added in OpenOCD release +0.10.0, which was added in Zephyr SDK 0.9.2. + +By default a factory new SAM E70 chip will boot SAM-BA boot loader located in +the ROM, not the flashed image. This is determined by the value of GPNVM1 +(General-Purpose NVM bit 1). The flash procedure will ensure that GPNVM1 is +set to 1 changing the default behavior to boot from Flash. + +If your chip has a security bit GPNVM0 set you will be unable to program flash +memory or connect to it via a debug interface. The only way to clear GPNVM0 +is to perform a chip erase procedure that will erase all GPNVM bits and the full +contents of the SAM E70 flash memory: + +- With the board power off, set a jumper on the J200 header. +- Turn the board power on. The jumper can be removed soon after the power is on + (flash erasing procedure is started when the erase line is asserted for at + least 230ms) + +Flashing +======== + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the SAM E70 Xplained board to your host computer using the + USB debug port. Then build and flash the :ref:`hello_world` + application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_e70_xplained/same70q21 + :goals: build flash + + You should see "Hello World! sam_e70_xplained" in your terminal. + +#. To use the SoC variation B IC, you need type "sam_e70_xplained/same70q21b". + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_e70_xplained/same70q21b + :goals: build flash + + You should see "Hello World! sam_e70_xplained" in your terminal. + +You can flash the image using an external debug adapter such as J-Link +or ULINK, connected to the 20-pin JTAG header. Supply the name of the +debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment +variable. OpenOCD will look for the appropriate interface +configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its +internal search path. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_e70_xplained/same70q21 + :maybe-skip-config: + :goals: debug + +References +********** + +SAM E70 Product Page: + http://www.atmel.com/products/microcontrollers/arm/sam-e.aspx + +.. _SAME70-XPLD User Guide: + http://www.atmel.com/Images/Atmel-44050-Cortex-M7-Microcontroller-SAM-E70-XPLD-Xplained_User-guide.pdf + +.. _OpenOCD tool: + http://openocd.org/ + +.. _SAM-BA: + http://www.atmel.com/tools/ATMELSAM-BAIN-SYSTEMPROGRAMMER.aspx diff --git a/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake b/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake new file mode 100644 index 00000000000000..3b32c9ca518166 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/ethernet@40050000 & /soc/mdio@40050000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi similarity index 100% rename from boards/arm/sam_e70_xplained/sam_e70_xplained-common.dtsi rename to boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-common.dtsi diff --git a/boards/arm/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi similarity index 100% rename from boards/arm/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi rename to boards/atmel/sam/sam_e70_xplained/sam_e70_xplained-pinctrl.dtsi diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts new file mode 100644 index 00000000000000..64a26cecc88b0a --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.dts @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2017 Piotr Mienkowski + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_e70_xplained-common.dtsi" + +/ { + model = "Atmel SAM E70 Xplained board"; + compatible = "atmel,sam_e70_xplained", "atmel,same70q21", "atmel,same70"; +}; + +&tc0 { + status = "okay"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc0_qdec_default>; + pinctrl-names = "default"; +}; + +&tc1 { + status = "disabled"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc1_qdec_default>; + pinctrl-names = "default"; +}; + +&tc2 { + status = "disabled"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc2_qdec_default>; + pinctrl-names = "default"; +}; + +&tc3 { + status = "disabled"; + compatible = "atmel,sam-tc-qdec"; + + pinctrl-0 = <&tc3_qdec_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml new file mode 100644 index 00000000000000..e6da0170989a60 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml @@ -0,0 +1,26 @@ +identifier: sam_e70_xplained/same70q21 +name: SAM E70 Xplained +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - can + - counter + - dac + - dma + - gpio + - hwinfo + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig new file mode 100644 index 00000000000000..f5404f816bee14 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts new file mode 100644 index 00000000000000..e65d9da3325494 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_e70_xplained-common.dtsi" + +/ { + model = "Atmel SAM E70B Xplained board"; + compatible = "atmel,sam_e70b_xplained", "atmel,same70q21b", "atmel,same70b"; +}; diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml new file mode 100644 index 00000000000000..8d15c3ae088e22 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml @@ -0,0 +1,26 @@ +identifier: sam_e70_xplained/same70q21b +name: SAM E70 Xplained (Revision B) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - can + - counter + - dac + - dma + - gpio + - hwinfo + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b_defconfig b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b_defconfig new file mode 100644 index 00000000000000..f5404f816bee14 --- /dev/null +++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam_e70_xplained/support/openocd.cfg b/boards/atmel/sam/sam_e70_xplained/support/openocd.cfg similarity index 100% rename from boards/arm/sam_e70_xplained/support/openocd.cfg rename to boards/atmel/sam/sam_e70_xplained/support/openocd.cfg diff --git a/boards/atmel/sam/sam_v71_xult/Kconfig.defconfig b/boards/atmel/sam/sam_v71_xult/Kconfig.defconfig new file mode 100644 index 00000000000000..5c860149dc8b9d --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Atmel SMART SAM V71 Xplained Board configuration + +# Copyright (c) 2019 Gerson Fernando Budke +# Copyright (c) 2016 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if ETH_SAM_GMAC + +# Read MAC address from AT24MAC402 EEPROM + +config ETH_SAM_GMAC_MAC_I2C_EEPROM + default y + select I2C + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS + default 0x9A + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE + default 1 + +endif # ETH_SAM_GMAC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam/sam_v71_xult/Kconfig.sam_v71_xult b/boards/atmel/sam/sam_v71_xult/Kconfig.sam_v71_xult new file mode 100644 index 00000000000000..e84ae3fc535f7a --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/Kconfig.sam_v71_xult @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAM_V71_XULT + select SOC_SAMV71Q21 if BOARD_SAM_V71_XULT_SAMV71Q21 + select SOC_SAMV71Q21B if BOARD_SAM_V71_XULT_SAMV71Q21B diff --git a/boards/arm/sam_v71_xult/board.cmake b/boards/atmel/sam/sam_v71_xult/board.cmake similarity index 100% rename from boards/arm/sam_v71_xult/board.cmake rename to boards/atmel/sam/sam_v71_xult/board.cmake diff --git a/boards/atmel/sam/sam_v71_xult/board.yml b/boards/atmel/sam/sam_v71_xult/board.yml new file mode 100644 index 00000000000000..68996e0648586c --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/board.yml @@ -0,0 +1,6 @@ +board: + name: sam_v71_xult + vendor: atmel + socs: + - name: samv71q21 + - name: samv71q21b diff --git a/boards/arm/sam_v71_xult/doc/img/sam_v71_xult.jpg b/boards/atmel/sam/sam_v71_xult/doc/img/sam_v71_xult.jpg similarity index 100% rename from boards/arm/sam_v71_xult/doc/img/sam_v71_xult.jpg rename to boards/atmel/sam/sam_v71_xult/doc/img/sam_v71_xult.jpg diff --git a/boards/atmel/sam/sam_v71_xult/doc/index.rst b/boards/atmel/sam/sam_v71_xult/doc/index.rst new file mode 100644 index 00000000000000..e0b5fce6c04d32 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/doc/index.rst @@ -0,0 +1,198 @@ +.. _sam_v71_xplained_ultra: + +SAM V71(B) Xplained Ultra +######################### + +Overview +******** + +The SAM V71 Xplained Ultra evaluation kit is a development platform to +evaluate the Atmel SAM V71 series microcontrollers. The current version +allows to use both IC variations ATSAMV71Q21A(B). + +.. image:: img/sam_v71_xult.jpg + :align: center + :alt: SAM V71 Xplained Ultra + +Hardware +******** + +- ATSAMV71Q21A(B) ARM Cortex-M7 Processor +- 12 MHz crystal oscillator +- 32.768 kHz crystal oscillator +- Supercap backup +- AT24MAC402 EEPROM +- IS42S16100E 16 Mb SDRAM +- S25FL116K 16 Mb QSPI +- WM8904 low power stereo audio codec +- ATA6561 CAN Transceiver +- SD card connector with SDIO support +- Camera interface connector +- MediaLB connector +- Ethernet port +- Micro-AB USB device +- Micro-AB USB debug interface supporting CMSIS-DAP, Virtual COM Port and Data + Gateway Interface (DGI) +- JTAG interface connector +- One reset and two user pushbuttons +- Two yellow user LEDs + +Supported Features +================== + +The sam_v71_xplained_ultra board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| AFEC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN FD | on-chip | can | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| XDMAC | on-chip | dma | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig`. + +Connections and IOs +=================== + +The `SAMV71-XULT User Guide`_ has detailed information about board +connections. + +System Clock +============ + +The SAM V71 MCU is configured to use the 12 MHz external oscillator on the +board with the on-chip PLL to generate a 300 MHz system clock. + +Serial Port +=========== + +The ATSAMV71Q21 MCU has five UARTs and three USARTs. USART1 is configured +for the console and is available as a Virtual COM Port via EDBG USB chip. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM V71 MCU requires the `OpenOCD tool`_. +By default a factory new SAM V71 chip will boot the `SAM-BA`_ boot loader +located in the ROM, not the flashed image. This is determined by the value +of GPNVM1 (General-Purpose NVM bit 1). The flash procedure will ensure that +GPNVM1 is set to 1 changing the default behavior to boot from Flash. + +If your chip has a security bit GPNVM0 set you will be unable to program flash +memory or connect to it via a debug interface. The only way to clear GPNVM0 +is to perform a chip erase procedure that will erase all GPNVM bits and the +full contents of the SAM V71 flash memory: + +- With the board power off, set a jumper on the J200 header. +- Turn the board power on. The jumper can be removed soon after the power is + on (flash erasing procedure is started when the erase line is asserted for + at least 230ms) + +Flashing +======== + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the SAM V71 Xplained Ultra board to your host computer using the + USB debug port. Then build and flash the :ref:`hello_world` + application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_v71_xult/samv71q21 + :goals: build flash + + You should see "Hello World! sam_v71_xult" in your terminal. + +#. To use the SoC variation B IC, you need type "sam_v71_xult/samv71q21b". + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_v71_xult/samv71q21b + :goals: build flash + + You should see "Hello World! sam_v71_xult" in your terminal. + +You can flash the image using an external debug adapter such as J-Link +or ULINK, connected to the 20-pin JTAG header. Supply the name of the +debug adapter (e.g., ``jlink``) via an OPENOCD_INTERFACE environment +variable. OpenOCD will look for the appropriate interface +configuration in an ``interface/$(OPENOCD_INTERFACE).cfg`` file on its +internal search path. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sam_v71_xult/samv71q21 + :maybe-skip-config: + :goals: debug + +References +********** + +SAM V71 Product Page: + https://www.microchip.com/design-centers/32-bit/sam-32-bit-mcus/sam-v-mcus + +.. _SAMV71-XULT User Guide: + http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42408-SAMV71-Xplained-Ultra_User-Guide.pdf + +.. _OpenOCD tool: + http://openocd.org/ + +.. _SAM-BA: + https://www.microchip.com/developmenttools/ProductDetails/PartNO/SAM-BA%20In-system%20Programmer diff --git a/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake b/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake new file mode 100644 index 00000000000000..3b32c9ca518166 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/pre_dt_board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/ethernet@40050000 & /soc/mdio@40050000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi similarity index 100% rename from boards/arm/sam_v71_xult/sam_v71_xult-common.dtsi rename to boards/atmel/sam/sam_v71_xult/sam_v71_xult-common.dtsi diff --git a/boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi b/boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi similarity index 100% rename from boards/arm/sam_v71_xult/sam_v71_xult-pinctrl.dtsi rename to boards/atmel/sam/sam_v71_xult/sam_v71_xult-pinctrl.dtsi diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts new file mode 100644 index 00000000000000..9bdcadc7946317 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2017 Piotr Mienkowski + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_v71_xult-common.dtsi" + +/ { + model = "Atmel SAM V71 Xplained Ultra board"; + compatible = "atmel,sam_v71_xult", "atmel,samv71q21", "atmel,samv71"; +}; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml new file mode 100644 index 00000000000000..e8b433685d0107 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml @@ -0,0 +1,33 @@ +identifier: sam_v71_xult/samv71q21 +name: SAM V71 Xplained Ultra +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - can + - counter + - dac + - dma + - hwinfo + - gpio + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi +vendor: atmel diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig new file mode 100644 index 00000000000000..f5404f816bee14 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts new file mode 100644 index 00000000000000..f6f7f5a03ebfdd --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2020 Stephanos Ioannidis + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "sam_v71_xult-common.dtsi" + +/ { + model = "Atmel SAM V71B Xplained Ultra board"; + compatible = "atmel,sam_v71_xult", "atmel,samv71q21b", "atmel,samv71b"; +}; diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml new file mode 100644 index 00000000000000..578359edbbe011 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml @@ -0,0 +1,33 @@ +identifier: sam_v71_xult/samv71q21b +name: SAM V71 Xplained Ultra (Revision B) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 2048 +ram: 384 +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - can + - counter + - dac + - dma + - hwinfo + - gpio + - i2s + - pwm + - netif:eth + - spi + - usb + - usb_device + - watchdog + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi +vendor: atmel diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b_defconfig b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b_defconfig new file mode 100644 index 00000000000000..f5404f816bee14 --- /dev/null +++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_CACHE_MANAGEMENT=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/sam_v71_xult/support/openocd.cfg b/boards/atmel/sam/sam_v71_xult/support/openocd.cfg similarity index 100% rename from boards/arm/sam_v71_xult/support/openocd.cfg rename to boards/atmel/sam/sam_v71_xult/support/openocd.cfg diff --git a/boards/atmel/sam0/samc21n_xpro/Kconfig.samc21n_xpro b/boards/atmel/sam0/samc21n_xpro/Kconfig.samc21n_xpro new file mode 100644 index 00000000000000..5041081eb3dfa1 --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/Kconfig.samc21n_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMC21N_XPRO + select SOC_SAMC21N18A diff --git a/boards/arm/atsamc21n_xpro/board.cmake b/boards/atmel/sam0/samc21n_xpro/board.cmake similarity index 100% rename from boards/arm/atsamc21n_xpro/board.cmake rename to boards/atmel/sam0/samc21n_xpro/board.cmake diff --git a/boards/atmel/sam0/samc21n_xpro/board.yml b/boards/atmel/sam0/samc21n_xpro/board.yml new file mode 100644 index 00000000000000..2037cde2398a2f --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samc21n_xpro + vendor: atmel + socs: + - name: samc21n18a diff --git a/boards/arm/atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg b/boards/atmel/sam0/samc21n_xpro/doc/img/atsamc21n_xpro.jpg similarity index 100% rename from boards/arm/atsamc21n_xpro/doc/img/atsamc21n_xpro.jpg rename to boards/atmel/sam0/samc21n_xpro/doc/img/atsamc21n_xpro.jpg diff --git a/boards/atmel/sam0/samc21n_xpro/doc/index.rst b/boards/atmel/sam0/samc21n_xpro/doc/index.rst new file mode 100644 index 00000000000000..600163a00c9589 --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/doc/index.rst @@ -0,0 +1,194 @@ +.. _samc21n_xpro: + +SAM C21N Xplained Pro Evaluation Kit +#################################### + +Overview +******** + +The SAM C21N Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM C21N Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsamc21n_xpro.jpg + :align: center + :alt: SAMC21N-XPRO + +Hardware +******** + +- SAMC21N18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of RAM, 8KB RRW flash +- One yellow user LED +- One mechanical user push button +- One reset button +- One QTouch® button +- On-board USB based EDBG unit with serial console +- Two CAN transceivers + +Supported Features +================== + +The samc21n_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - CAN + - on-chip + - CAN ports + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM C21N Xplained Pro evaluation kit has 4 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM C21 Family Datasheet`_ and the `SAM C21N +Xplained Pro Schematic`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- ADC0 : PB09 +- ADC1 : PA08 +- CAN0 TX : PA24 +- CAN0 RX : PA25 +- CAN1 TX : PB14 +- CAN1 RX : PB15 +- SERCOM0 USART TX : PB24 +- SERCOM0 USART RX : PB25 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM2 USART TX : PA12 +- SERCOM2 USART RX : PA13 +- SERCOM4 USART TX : PB10 +- SERCOM4 USART RX : PB11 +- SERCOM5 SPI MISO : PB00 +- SERCOM5 SPI MOSI : PB02 +- SERCOM5 SPI SCK : PB01 +- GPIO/PWM LED0 : PC05 + +System Clock +============ + +The SAMC21 MCU is configured to use the 32.768 kHz internal oscillator +with the on-chip internal oscillator generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMC21 MCU has eight SERCOM based USARTs with three configured as USARTs in +this BSP. SERCOM4 is the default Zephyr console. + +- SERCOM0 9600 8n1 +- SERCOM2 115200 8n1 +- SERCOM4 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMC21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC2 instead of by GPIO. + +Programming and Debugging +************************* + +The SAM C21N Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMC21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samc21n_xpro + :goals: build + :compact: + +#. Connect the SAM C21N Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samc21n_xpro + :goals: flash + :compact: + + You should see "Hello World! samc21n_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/ATSAMC21N-XPRO + +.. _SAM C21 Family Datasheet: + https://ww1.microchip.com/downloads/aemDocuments/documents/MCU32/ProductDocuments/DataSheets/SAM-C20-C21-Family-Data-Sheet-DS60001479J.pdf + +.. _SAM C21N Xplained Pro Schematic: + https://ww1.microchip.com/downloads/en/DeviceDoc/ATSAMC21N_Xplained_Pro_Design_Files.zip diff --git a/boards/arm/atsamd20_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samc21n_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamd20_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/samc21n_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamc21n_xpro/atsamc21n_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samc21n_xpro/samc21n_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts new file mode 100644 index 00000000000000..79ff5b90ecfd76 --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "samc21n_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM C21N Xplained Pro"; + compatible = "samc21n,xpro", "atmel,samc21n18a", "atmel,samc21"; + + chosen { + zephyr,console = &sercom4; + zephyr,shell-uart = &sercom4; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,canbus = &can0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + i2c-0 = &sercom1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portc 05 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc2 1 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&portb 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "User Button"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&adc1 { + pinctrl-0 = <&adc1_default>; + pinctrl-names = "default"; +}; + +&tcc2 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + prescaler = <256>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <9600>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom2_uart_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <1>; + + pinctrl-0 = <&sercom4_uart_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_spi_default>; + pinctrl-names = "default"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 0x00004000>; + }; + }; +}; + +&can0 { + status = "okay"; + + pinctrl-0 = <&can0_default>; + pinctrl-names = "default"; + + bus-speed = <125000>; + bus-speed-data = <1000000>; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + pinctrl-0 = <&can1_default>; + pinctrl-names = "default"; + + bus-speed = <125000>; + bus-speed-data = <1000000>; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml new file mode 100644 index 00000000000000..428d79e1110643 --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml @@ -0,0 +1,23 @@ +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samc21n_xpro +name: SAM C21N Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - can + - dma + - gpio + - i2c + - pwm + - spi + - uart +vendor: atmel diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig new file mode 100644 index 00000000000000..73259566dbf4ae --- /dev/null +++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamc21n_xpro/support/openocd.cfg b/boards/atmel/sam0/samc21n_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamc21n_xpro/support/openocd.cfg rename to boards/atmel/sam0/samc21n_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samd20_xpro/Kconfig.samd20_xpro b/boards/atmel/sam0/samd20_xpro/Kconfig.samd20_xpro new file mode 100644 index 00000000000000..be7865252c7489 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/Kconfig.samd20_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMD20_XPRO + select SOC_SAMD20J18 diff --git a/boards/arm/atsamd20_xpro/board.cmake b/boards/atmel/sam0/samd20_xpro/board.cmake similarity index 100% rename from boards/arm/atsamd20_xpro/board.cmake rename to boards/atmel/sam0/samd20_xpro/board.cmake diff --git a/boards/atmel/sam0/samd20_xpro/board.yml b/boards/atmel/sam0/samd20_xpro/board.yml new file mode 100644 index 00000000000000..c6c44e378302b6 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samd20_xpro + vendor: atmel + socs: + - name: samd20j18 diff --git a/boards/arm/atsamd20_xpro/doc/img/atsamd20_xpro.jpg b/boards/atmel/sam0/samd20_xpro/doc/img/atsamd20_xpro.jpg similarity index 100% rename from boards/arm/atsamd20_xpro/doc/img/atsamd20_xpro.jpg rename to boards/atmel/sam0/samd20_xpro/doc/img/atsamd20_xpro.jpg diff --git a/boards/atmel/sam0/samd20_xpro/doc/index.rst b/boards/atmel/sam0/samd20_xpro/doc/index.rst new file mode 100644 index 00000000000000..b0dbff2822941e --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/doc/index.rst @@ -0,0 +1,161 @@ +.. _samd20_xpro: + +SAM D20 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM D20 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM D20 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. figure:: img/atsamd20_xpro.jpg + :width: 500px + :align: center + :alt: SAMD20-XPRO + + SAMD20-XPRO (Credit: `Microchip Technology`_) + +Hardware +******** + +- SAMD20J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samd20_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig`. + +Connections and IOs +=================== + +The `Microchip website`_ has detailed information about board +connections. Download the `SAM D20 Xplained Pro Schematic`_ for more detail. + +System Clock +============ + +The SAMD20 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs +(SERCOM3) is connected to the onboard Atmel Embedded Debugger (EDBG). +SERCOM4 is available on the EXT1 connector. + +SPI Port +======== + +The SAMD20 MCU has 6 SERCOM based SPIs. On the SAM D20 Xplained Pro, +SERCOM0 is available on the EXT1 connector. + +Programming and Debugging +************************* + +The SAM D20 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMD20 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd20_xpro + :goals: build + :compact: + +#. Connect the SAM D20 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd20_xpro + :goals: flash + :compact: + + You should see "Hello World! samd20_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip Technology: + https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO + +.. _Microchip website: + https://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD20-XPRO + +.. _SAM D20 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD20-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamd21_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samd20_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamd21_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/samd20_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsamd20_xpro/atsamd20_xpro-pinctrl.dtsi b/boards/atmel/sam0/samd20_xpro/samd20_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamd20_xpro/atsamd20_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samd20_xpro/samd20_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts b/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts new file mode 100644 index 00000000000000..83f5df99c05a2e --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2018 Sean Nyekjaer + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "samd20_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM D20 Xplained Pro"; + compatible = "samd20,xpro", "atmel,samd20j18", "atmel,samd20"; + + chosen { + zephyr,console = &sercom3; + zephyr,shell-uart = &sercom3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &yellow_led; + sw0 = &user_button; + i2c-0 = &sercom2; + }; + + leds { + compatible = "gpio-leds"; + yellow_led: led_0 { + gpios = <&porta 14 GPIO_ACTIVE_LOW>; + label = "LED0"; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&porta 5 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sercom0_spi_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom3 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <1>; + + pinctrl-0 = <&sercom3_uart_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom4_uart_default>; + pinctrl-names = "default"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 0x00004000>; + }; + }; +}; diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml new file mode 100644 index 00000000000000..548bd6c462a885 --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml @@ -0,0 +1,19 @@ +identifier: samd20_xpro +name: SAM D20 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - flash + - gpio + - i2c + - spi + - uart + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig b/boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig new file mode 100644 index 00000000000000..c7f66b36c3647d --- /dev/null +++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd20_xpro/support/openocd.cfg b/boards/atmel/sam0/samd20_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamd20_xpro/support/openocd.cfg rename to boards/atmel/sam0/samd20_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samd21_xpro/Kconfig.samd21_xpro b/boards/atmel/sam0/samd21_xpro/Kconfig.samd21_xpro new file mode 100644 index 00000000000000..3c1926b956e04d --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/Kconfig.samd21_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2018 Bryan O'Donoghue +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMD21_XPRO + select SOC_SAMD21J18A diff --git a/boards/arm/atsamd21_xpro/board.cmake b/boards/atmel/sam0/samd21_xpro/board.cmake similarity index 100% rename from boards/arm/atsamd21_xpro/board.cmake rename to boards/atmel/sam0/samd21_xpro/board.cmake diff --git a/boards/atmel/sam0/samd21_xpro/board.yml b/boards/atmel/sam0/samd21_xpro/board.yml new file mode 100644 index 00000000000000..d4fd578dd3564e --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samd21_xpro + vendor: atmel + socs: + - name: samd21j18a diff --git a/boards/arm/atsamd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg b/boards/atmel/sam0/samd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg similarity index 100% rename from boards/arm/atsamd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg rename to boards/atmel/sam0/samd21_xpro/doc/img/ATSAMD21-XPRO-pinout.jpg diff --git a/boards/arm/atsamd21_xpro/doc/img/atsamd21_xpro.jpg b/boards/atmel/sam0/samd21_xpro/doc/img/atsamd21_xpro.jpg similarity index 100% rename from boards/arm/atsamd21_xpro/doc/img/atsamd21_xpro.jpg rename to boards/atmel/sam0/samd21_xpro/doc/img/atsamd21_xpro.jpg diff --git a/boards/atmel/sam0/samd21_xpro/doc/index.rst b/boards/atmel/sam0/samd21_xpro/doc/index.rst new file mode 100644 index 00000000000000..f4f5bd3391de93 --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/doc/index.rst @@ -0,0 +1,202 @@ +.. _samd21_xpro: + +SAM D21 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM D21 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM D21 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel's Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. figure:: img/atsamd21_xpro.jpg + :width: 500px + :align: center + :alt: SAMD21-XPRO + + SAMD21-XPRO (Credit: `Microchip Technology`_) + +Hardware +******** + +- SAMD21J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samd21_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - USB + - on-chip + - Universal Serial Bus device ports + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM D21 Xplained Pro evaluation kit has 3 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM D21 Family Datasheet`_ and the `SAM D21 +Xplained Pro Schematic`_. + +.. image:: img/ATSAMD21-XPRO-pinout.jpg + :align: center + :alt: SAMD21-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 USART TX : PA10 +- SERCOM0 USART RX : PA11 +- SERCOM1 USART TX : PA16 +- SERCOM1 USART RX : PA19 +- SERCOM2 I2C SDA : PA08 +- SERCOM2 I2C SCL : PA09 +- SERCOM3 USART TX : PA22 +- SERCOM3 USART RX : PA23 +- SERCOM5 SPI MISO : PB16 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- USB DP : PA25 +- USB DM : PA24 +- GPIO SPI CS : PB17 +- GPIO/PWM LED0 : PB30 + +System Clock +============ + +The SAMD21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMD21 MCU has six SERCOM based USARTs with three configured as USARTs in +this BSP. SERCOM3 is the default Zephyr console. + +- SERCOM0 9600 8n1 +- SERCOM1 115200 8n1 +- SERCOM3 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMD21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the SAM D21 Xplained Pro, +SERCOM5 is connected to an 8 megabit SPI flash. + +Programming and Debugging +************************* + +The SAM D21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMD21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd21_xpro + :goals: build + :compact: + +#. Connect the SAM D21 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samd21_xpro + :goals: flash + :compact: + + You should see "Hello World! samd21_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip Technology: + http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMD21-XPRO + +.. _SAM D21 Family Datasheet: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAM-D21-Family-Datasheet-DS40001882C.pdf + +.. _SAM D21 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAMD21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsamr21_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samd21_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsamr21_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/samd21_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsamd21_xpro/atsamd21_xpro-pinctrl.dtsi b/boards/atmel/sam0/samd21_xpro/samd21_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamd21_xpro/atsamd21_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samd21_xpro/samd21_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts b/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts new file mode 100644 index 00000000000000..f390bc106de9a9 --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2018 Bryan O'Donoghue + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include +#include "samd21_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM D21 Xplained Pro"; + compatible = "samd21,xpro", "atmel,samd21j18a", "atmel,samd21"; + + chosen { + zephyr,console = &sercom3; + zephyr,shell-uart = &sercom3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + i2c-0 = &sercom2; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portb 30 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 0 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <9600>; + rxpo = <3>; + txpo = <1>; + + pinctrl-0 = <&sercom0_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <0>; + + pinctrl-0 = <&sercom1_uart_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom3 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom3_uart_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_spi_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb_dc_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml new file mode 100644 index 00000000000000..d5e6a725003b55 --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2018 Bryan O'Donoghue +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samd21_xpro +name: SAM D21 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig b/boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig new file mode 100644 index 00000000000000..656d7033aa16d2 --- /dev/null +++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2018 Bryan O'Donoghue +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamd21_xpro/support/openocd.cfg b/boards/atmel/sam0/samd21_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamd21_xpro/support/openocd.cfg rename to boards/atmel/sam0/samd21_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/same54_xpro/Kconfig.defconfig b/boards/atmel/sam0/same54_xpro/Kconfig.defconfig new file mode 100644 index 00000000000000..17f73bc5ce43fa --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/Kconfig.defconfig @@ -0,0 +1,28 @@ +# SAM E54 Xplained Pro board configuration +# +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if ETH_SAM_GMAC + +# Read MAC address from AT24MAC402 EEPROM + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS + default 0x9A + +config ETH_SAM_GMAC_MAC_I2C_INT_ADDRESS_SIZE + default 1 + +config ETH_SAM_GMAC_MAC_I2C_EEPROM + default y + select I2C + +endif # ETH_SAM_GMAC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING diff --git a/boards/atmel/sam0/same54_xpro/Kconfig.same54_xpro b/boards/atmel/sam0/same54_xpro/Kconfig.same54_xpro new file mode 100644 index 00000000000000..c6d072763f82f1 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/Kconfig.same54_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAME54_XPRO + select SOC_SAME54P20A diff --git a/boards/arm/atsame54_xpro/board.cmake b/boards/atmel/sam0/same54_xpro/board.cmake similarity index 100% rename from boards/arm/atsame54_xpro/board.cmake rename to boards/atmel/sam0/same54_xpro/board.cmake diff --git a/boards/atmel/sam0/same54_xpro/board.yml b/boards/atmel/sam0/same54_xpro/board.yml new file mode 100644 index 00000000000000..d10fef7e7b7d9c --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: same54_xpro + vendor: atmel + socs: + - name: same54p20a diff --git a/boards/arm/atsame54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg b/boards/atmel/sam0/same54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg similarity index 100% rename from boards/arm/atsame54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg rename to boards/atmel/sam0/same54_xpro/doc/img/ATSAME54-XPRO-pinout.jpg diff --git a/boards/arm/atsame54_xpro/doc/img/atsame54_xpro.jpg b/boards/atmel/sam0/same54_xpro/doc/img/atsame54_xpro.jpg similarity index 100% rename from boards/arm/atsame54_xpro/doc/img/atsame54_xpro.jpg rename to boards/atmel/sam0/same54_xpro/doc/img/atsame54_xpro.jpg diff --git a/boards/atmel/sam0/same54_xpro/doc/index.rst b/boards/atmel/sam0/same54_xpro/doc/index.rst new file mode 100644 index 00000000000000..5fa1eb49e37888 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/doc/index.rst @@ -0,0 +1,230 @@ +.. _same54_xpro: + +SAM E54 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM E54 Cortex®-M4F processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsame54_xpro.jpg + :align: center + :alt: SAME54-XPRO + +Hardware +******** + +- SAME54P20A ARM Cortex-M4F processor at 120 MHz +- 32.768 kHz crystal oscillator +- 12 MHz crystal oscillator +- 1024 KiB flash memory and 256 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console +- One QTouch® PTC button +- 32 MiB QSPI Flash +- ATECC508 CryptoAuthentication™ device +- AT24MAC402 serial EEPROM with EUI-48™ MAC address +- Ethernet + + - RJ45 connector with built-in magnetics + - KSZ8091RNA PHY + - 10Base-T/100Base-TX IEE 802.3 compliant Ethernet transceiver + +- USB interface, host, and device +- SD/SDIO card connector + +Supported Features +================== + +The same54_xpro board configuration supports the following hardware +features: + ++---------------+------------+----------------------------+ +| Interface | Controller | Driver/Component | ++===============+============+============================+ +| ADC | on-chip | adc | ++---------------+------------+----------------------------+ +| DAC | on-chip | dac | ++---------------+------------+----------------------------+ +| DMAC | on-chip | dma | ++---------------+------------+----------------------------+ +| EEPROM | i2c | eeprom, EUI-48 MAC Address | ++---------------+------------+----------------------------+ +| EIC | on-chip | interrupt_controller | ++---------------+------------+----------------------------+ +| GMAC | on-chip | ethernet, mdio | ++---------------+------------+----------------------------+ +| GPIO | on-chip | gpio | ++---------------+------------+----------------------------+ +| MPU | on-chip | arch/arm | ++---------------+------------+----------------------------+ +| NVIC | on-chip | arch/arm | ++---------------+------------+----------------------------+ +| NVMCTRL | on-chip | flash | ++---------------+------------+----------------------------+ +| PORT | on-chip | pinctrl | ++---------------+------------+----------------------------+ +| RTC | on-chip | timer | ++---------------+------------+----------------------------+ +| SERCOM I2C | on-chip | i2c | ++---------------+------------+----------------------------+ +| SERCOM SPI | on-chip | spi | ++---------------+------------+----------------------------+ +| SERCOM USART | on-chip | serial, console | ++---------------+------------+----------------------------+ +| Serial Number | on-chip | hwinfo | ++---------------+------------+----------------------------+ +| SYSTICK | on-chip | timer | ++---------------+------------+----------------------------+ +| TC | on-chip | counter | ++---------------+------------+----------------------------+ +| TCC | on-chip | counter, pwm | ++---------------+------------+----------------------------+ +| TRNG | on-chip | entropy | ++---------------+------------+----------------------------+ +| USB | on-chip | usb | ++---------------+------------+----------------------------+ +| WDT | on-chip | watchdog | ++---------------+------------+----------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/same54_xpro/same54_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM E54 Xplained Pro evaluation kit has 4 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM D5x/E5x Family Datasheet`_ and the `SAM E54 +Xplained Pro Schematic`_. + +.. image:: img/ATSAME54-XPRO-pinout.jpg + :align: center + :alt: SAME54-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM2 USART TX : PB24 +- SERCOM2 USART RX : PB25 +- GPIO/PWM LED0 : PC18 +- GPIO SW0 : PB31 +- GMAC RMII REFCK : PA14 +- GMAC RMII TXEN : PA17 +- GMAC RMII TXD0 : PA18 +- GMAC RMII TXD1 : PA19 +- GMAC RMII CRSDV : PC20 +- GMAC RMII RXD0 : PA13 +- GMAC RMII RXD1 : PA12 +- GMAC RMII RXER : PA15 +- GMAC MDIO MDC : PC11 +- GMAC MDIO MDIO : PC12 +- SERCOM4 SPI SCK : PB26 +- SERCOM4 SPI MOSI : PB27 +- SERCOM4 SPI MISO : PB29 +- SERCOM7 I2C SDA : PD08 +- SERCOM7 I2C SCL : PD09 +- USB DP : PA25 +- USB DM : PA24 + +System Clock +============ + +The SAME54 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAME54 MCU has 8 SERCOM based USARTs with one configured as USARTs in +this BSP. SERCOM2 is the default Zephyr console. + +- SERCOM2 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAME54 MCU has 5 TCC based PWM units with up to 6 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAME54 MCU has 8 SERCOM based SPIs. + +I2C Port +======== + +The SAME54 MCU has 8 SERCOM based I2Cs. On the SAM E54 Xplained Pro, +SERCOM7 is connected to a AT24MAC402 EEPROM and a ATECC508A Crypto +Authentication device. + +Programming and Debugging +************************* + +The SAM E54 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAME54 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: same54_xpro + :goals: build + :compact: + +#. Connect the SAM E54 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: same54_xpro + :goals: flash + :compact: + + You should see "Hello World! same54_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAME54-XPRO + +.. _SAM D5x/E5x Family Datasheet: + http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf + +.. _SAM E54 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAME54-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsame54_xpro/pre_dt_board.cmake b/boards/atmel/sam0/same54_xpro/pre_dt_board.cmake similarity index 100% rename from boards/arm/atsame54_xpro/pre_dt_board.cmake rename to boards/atmel/sam0/same54_xpro/pre_dt_board.cmake diff --git a/boards/arm/atsame54_xpro/atsame54_xpro-pinctrl.dtsi b/boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsame54_xpro/atsame54_xpro-pinctrl.dtsi rename to boards/atmel/sam0/same54_xpro/same54_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.dts b/boards/atmel/sam0/same54_xpro/same54_xpro.dts new file mode 100644 index 00000000000000..f8d957727cd4d5 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.dts @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2019 Benjamin Valentin + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "same54_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM E54 Xplained Pro"; + compatible = "same54,xpro", "atmel,same54p20a", "atmel,same54"; + + chosen { + zephyr,console = &sercom2; + zephyr,shell-uart = &sercom2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &button0; + i2c-0 = &sercom7; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portc 18 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 2 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&portb 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <120000000>; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.1s for 120MHz main clock */ + prescaler = <8>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_uart_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <3>; + dopo = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom4_spi_default>; + pinctrl-names = "default"; +}; + +&sercom7 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom7_i2c_default>; + pinctrl-names = "default"; + + eeprom: eeprom@5e { + compatible = "atmel,24mac402"; + reg = <0x5e>; + }; +}; + +&adc0 { + status = "okay"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb_dc_default>; + pinctrl-names = "default"; +}; + +&gmac { + status = "okay"; + + pinctrl-0 = <&gmac_rmii>; + pinctrl-names = "default"; + + mac-eeprom = <&eeprom>; + phy-handle = <&phy>; +}; + +&mdio { + status = "okay"; + + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + status = "okay"; + reg = <0>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + }; +}; diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml new file mode 100644 index 00000000000000..1cddeeaf7ad9d5 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml @@ -0,0 +1,24 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: same54_xpro +name: SAM E54 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 1024 +ram: 256 +supported: + - adc + - flash + - gpio + - i2c + - netif:eth + - pwm + - spi + - uart + - usb_device +vendor: atmel diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro_defconfig b/boards/atmel/sam0/same54_xpro/same54_xpro_defconfig new file mode 100644 index 00000000000000..33a48629acdb57 --- /dev/null +++ b/boards/atmel/sam0/same54_xpro/same54_xpro_defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsame54_xpro/support/openocd.cfg b/boards/atmel/sam0/same54_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsame54_xpro/support/openocd.cfg rename to boards/atmel/sam0/same54_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/saml21_xpro/Kconfig.saml21_xpro b/boards/atmel/sam0/saml21_xpro/Kconfig.saml21_xpro new file mode 100644 index 00000000000000..465269f2d8d891 --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/Kconfig.saml21_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAML21_XPRO + select SOC_SAML21J18B diff --git a/boards/arm/atsaml21_xpro/board.cmake b/boards/atmel/sam0/saml21_xpro/board.cmake similarity index 100% rename from boards/arm/atsaml21_xpro/board.cmake rename to boards/atmel/sam0/saml21_xpro/board.cmake diff --git a/boards/atmel/sam0/saml21_xpro/board.yml b/boards/atmel/sam0/saml21_xpro/board.yml new file mode 100644 index 00000000000000..10e2284d58bdf9 --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: saml21_xpro + vendor: atmel + socs: + - name: saml21j18b diff --git a/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro-pinout.jpg b/boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro-pinout.jpg similarity index 100% rename from boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro-pinout.jpg rename to boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro-pinout.jpg diff --git a/boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro.jpg b/boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro.jpg similarity index 100% rename from boards/arm/atsaml21_xpro/doc/img/atsaml21-xpro.jpg rename to boards/atmel/sam0/saml21_xpro/doc/img/atsaml21-xpro.jpg diff --git a/boards/atmel/sam0/saml21_xpro/doc/index.rst b/boards/atmel/sam0/saml21_xpro/doc/index.rst new file mode 100644 index 00000000000000..172fa1f0826c2f --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/doc/index.rst @@ -0,0 +1,198 @@ + .. _saml21_xpro: + +SAM L21 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM L21 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM L21 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +.. image:: img/atsaml21-xpro.jpg + :align: center + :alt: SAML21-XPRO + +Hardware +******** + +- SAML21J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The saml21_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - TRNG + - on-chip + - True Random Number Generator + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM L21 Xplained Pro evaluation kit has 2 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM L21 Family Datasheet`_ and the `SAM L21 +Xplained Pro Schematic`_. + +.. image:: img/atsaml21-xpro-pinout.jpg + :align: center + :alt: SAML21-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 SPI MISO : PA04 +- SERCOM0 SPI MOSI : PA06 +- SERCOM0 SPI SCK : PA07 +- SERCOM1 USART TX : PA18 +- SERCOM1 USART RX : PA19 +- SERCOM2 I2C SDA : PA08 +- SERCOM2 I2C SCL : PA09 +- SERCOM3 USART TX : PA22 +- SERCOM3 USART RX : PA23 +- SERCOM4 USART TX : PB08 +- SERCOM4 USART RX : PB09 +- SERCOM5 SPI MISO : PB16 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- USB DP : PA25 +- USB DM : PA24 +- GPIO SPI CS : PB17 +- GPIO/PWM LED0 : PB10 + +System Clock +============ + +The SAML21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAML21 MCU has six SERCOM based USARTs with two configured as USARTs in +this BSP. SERCOM3 is the default Zephyr console. + +- SERCOM1 115200 8n1 - connected to EXT2 and EXT3 +- SERCOM3 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) +- SERCOM4 115200 8n1 - connected to EXT1 + +PWM +=== + +The SAML21 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAML21 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. + +- SERCOM0 - connected to EXT1 +- SERCOM5 - connected to EXT2 and EXT3 + +Programming and Debugging +************************* + +The SAM L21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAML21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: saml21_xpro + :goals: build + :compact: + +#. Connect the SAM L21 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ picocom -b 115200 /dev/ttyACM0 + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: saml21_xpro + :goals: flash + :compact: + + You should see "Hello World! saml21_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b + +.. _SAM L21 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf + +.. _SAM L21 Xplained Pro Schematic: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAML21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/arm/atsaml21_xpro/atsaml21_xpro-pinctrl.dtsi b/boards/atmel/sam0/saml21_xpro/saml21_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsaml21_xpro/atsaml21_xpro-pinctrl.dtsi rename to boards/atmel/sam0/saml21_xpro/saml21_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts b/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts new file mode 100644 index 00000000000000..c0e0e43d666ba3 --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "saml21_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM L21 Xplained Pro"; + compatible = "saml21,xpro", "atmel,saml21j18b", "atmel,saml21"; + + chosen { + zephyr,console = &sercom3; + zephyr,shell-uart = &sercom3; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&portb 10 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 0 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc { + status = "okay"; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&tcc0_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom0_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <3>; + txpo = <0>; + + pinctrl-0 = <&sercom1_default>; + pinctrl-names = "default"; +}; + +&sercom2 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom2_default>; + pinctrl-names = "default"; +}; + +&sercom3 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom3_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom4_default>; + pinctrl-names = "default"; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml new file mode 100644 index 00000000000000..3d531f6628718b --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: saml21_xpro +name: SAM L21 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig b/boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig new file mode 100644 index 00000000000000..50125e5510d6f9 --- /dev/null +++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAML_XOSC32K=y +CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsaml21_xpro/support/openocd.cfg b/boards/atmel/sam0/saml21_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsaml21_xpro/support/openocd.cfg rename to boards/atmel/sam0/saml21_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samr21_xpro/Kconfig.samr21_xpro b/boards/atmel/sam0/samr21_xpro/Kconfig.samr21_xpro new file mode 100644 index 00000000000000..3f83d7d1adc656 --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/Kconfig.samr21_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMR21_XPRO + select SOC_SAMR21G18A diff --git a/boards/arm/atsamr21_xpro/board.cmake b/boards/atmel/sam0/samr21_xpro/board.cmake similarity index 100% rename from boards/arm/atsamr21_xpro/board.cmake rename to boards/atmel/sam0/samr21_xpro/board.cmake diff --git a/boards/atmel/sam0/samr21_xpro/board.yml b/boards/atmel/sam0/samr21_xpro/board.yml new file mode 100644 index 00000000000000..c56b60ffc6f458 --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samr21_xpro + vendor: atmel + socs: + - name: samr21g18a diff --git a/boards/arm/atsamr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg b/boards/atmel/sam0/samr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg similarity index 100% rename from boards/arm/atsamr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg rename to boards/atmel/sam0/samr21_xpro/doc/img/ATSAMR21-XPRO-pinout.jpg diff --git a/boards/arm/atsamr21_xpro/doc/img/atsamr21_xpro.jpg b/boards/atmel/sam0/samr21_xpro/doc/img/atsamr21_xpro.jpg similarity index 100% rename from boards/arm/atsamr21_xpro/doc/img/atsamr21_xpro.jpg rename to boards/atmel/sam0/samr21_xpro/doc/img/atsamr21_xpro.jpg diff --git a/boards/atmel/sam0/samr21_xpro/doc/index.rst b/boards/atmel/sam0/samr21_xpro/doc/index.rst new file mode 100644 index 00000000000000..1172f8a3f98241 --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/doc/index.rst @@ -0,0 +1,225 @@ +.. _samr21_xpro: + +SAM R21 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM R21 Xplained Pro is a compact evaluation board by Atmel featuring a +SAMR21G18A SoC. The SoC includes a SAMR21 ARM Cortex-M0+ micro-controller +bundled with Atmel's AT86RF233, a 2.4GHz IEEE802.15.4 compatible radio. +The kit includes Atmel’s Embedded Debugger (EDBG), which provides a full +debug interface without the need for additional hardware. + +.. image:: img/atsamr21_xpro.jpg + :align: center + :alt: SAMR21-XPRO + +Hardware +******** + +- SAMR21G18A ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory and 32 KiB of RAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samr21_xpro board configuration supports the following hardware +features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+--------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+--------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+--------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+--------------------------------------+ +| PWM | on-chip | Pulse Width Modulation | ++-----------+------------+--------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+--------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+--------------------------------------+ +| I2C | on-chip | I2C Peripheral Interface ports | ++-----------+------------+--------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM R21 Xplained Pro evaluation kit has 3 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM R21 Family Datasheet`_ and the `SAM R21 +Xplained Pro Schematic`_. + +.. image:: img/ATSAMR21-XPRO-pinout.jpg + :align: center + :alt: SAMR21-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 USART TX : PA5 +- SERCOM0 USART RX : PA4 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM5 SPI MISO : PB02 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- GPIO SPI CS : PB03 +- GPIO/PWM LED0 : PA19 + +System Clock +============ + +The SAMR21 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMR21 MCU has six SERCOM based USARTs with two configured as USARTs in +this BSP. SERCOM0 is the default Zephyr console. + +- SERCOM0 115200 8n1 connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMR21 MCU has 3 TCC based PWM units with up to 4 outputs each and a +period of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then +LED0 is driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMR21 MCU has 6 SERCOM based SPIs. + +- SERCOM5 is exposed via Xplained Pro Standard Extension Header + +I2C Port +======== + +When connecting an I2C device and a logic analyzer to an I2C port at the same +time, the internal pull-up resistors are not sufficient for stable bus +operation. You probably have to connect external pull-ups to both bus lines. 10K +is a good value to start with. + +- SERCOM1 is exposed via Xplained Pro Standard Extension Header + +Radio +===== + +The SAMR21 SoC includes an on-chip AT86RF233 radio. It is internally +connected via SPI and some GPIO pins and behaves the same way as +externally connected SPI devices. + ++-------------+------------------------------------------------------------------------------------------+ +| Sensor | AT86RF233 | ++=============+==========================================================================================+ +| Type | 2.4GHz IEEE802.15.4 radio | ++-------------+------------------------------------------------------------------------------------------+ +| Vendor | Atmel | ++-------------+------------------------------------------------------------------------------------------+ +| Datasheet |`Datasheet `_| ++-------------+------------------------------------------------------------------------------------------+ +| connected to| SPI_0 | ++-------------+------------------------------------------------------------------------------------------+ +| Pin Config: | ++-------------+------------------------------------------------------------------------------------------+ +| Device | SERCOM4 | ++-------------+------------------------------------------------------------------------------------------+ +| MOSI | PB30 (OUT, SPI MOSI) | ++-------------+------------------------------------------------------------------------------------------+ +| MISO | PC19 (IN, SPI MISO) | ++-------------+------------------------------------------------------------------------------------------+ +| SCLK | PC18 (OUT, SPI SCLK) | ++-------------+------------------------------------------------------------------------------------------+ +| CS | PB31 (OUT, GPIO output) | ++-------------+------------------------------------------------------------------------------------------+ +| IRQ | PB00 (IN, GPIO external interrupt) | ++-------------+------------------------------------------------------------------------------------------+ +| RSTN | PB15 (OUT, GPIO output) | ++-------------+------------------------------------------------------------------------------------------+ +| SLP_TR | PA20 (OUT, GPIO output) | ++-------------+------------------------------------------------------------------------------------------+ + +Zephyr provide several samples that can use this technology. You can check +:zephyr:code-sample:`wpan-usb` and :zephyr:code-sample:`wpan-serial` examples as starting +points. Another good test can be done with IPv6 by using the server/client +echo demo. More information at :zephyr:code-sample:`sockets-echo-server` and +:zephyr:code-sample:`sockets-echo-client`. + +Programming and Debugging +************************* + +The SAM R21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMR21 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr21_xpro + :goals: build + :compact: + +#. Connect the SAM R21 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr21_xpro + :goals: flash + :compact: + + You should see "Hello World! samr21_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAMR21-XPRO + +.. _SAM R21 Family Datasheet: + http://ww1.microchip.com/downloads/en/devicedoc/sam-r21_datasheet.pdf + +.. _SAM R21 Xplained Pro Schematic: + http://ww1.microchip.com/downloads/en/DeviceDoc/SAMR21-Xplained-Pro_Design-Documentation.zip diff --git a/boards/atmel/sam0/samr21_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samr21_xpro/pre_dt_board.cmake new file mode 100644 index 00000000000000..62686b6896c45d --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/pre_dt_board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# SPI is implemented via sercom so node name isn't spi@... +list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge") + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - /soc/pinmux@41004400 & /soc/gpio@41004400 +# - /soc/pinmux@41004480 & /soc/gpio@41004480 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/arm/atsamr21_xpro/atsamr21_xpro-pinctrl.dtsi b/boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamr21_xpro/atsamr21_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samr21_xpro/samr21_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts new file mode 100644 index 00000000000000..01ed0e8826ce38 --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2019 Benjamin Valentin + * Copyright (c) 2019-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "samr21_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM R21 Xplained Pro"; + compatible = "samr21,xpro", "atmel,samr21g18a", "atmel,samr21"; + + chosen { + zephyr,console = &sercom0; + zephyr,shell-uart = &sercom0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,ieee802154 = &ieee802154; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + i2c-0 = &sercom1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&porta 19 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 3 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; + + ext1_header: xplained-pro-connector1 { + compatible = "atmel-xplained-pro-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* Shared */ + gpio-map = <0 0 &porta 6 0>, /* ADC6 */ + <1 0 &porta 7 0>, /* ADC7 */ + <2 0 &porta 13 0>, /* GPIO */ + <3 0 &porta 28 0>, /* GPIO */ + <4 0 &porta 18 0>, /* PWM_T0_W2 */ + <5 0 &porta 19 0>, /* PWM_T0_W3 */ + <6 0 &porta 22 0>, /* GPIO */ + <7 0 &porta 23 0>, /* GPIO */ + <8 0 &porta 16 0>, /* TWD1 EXT2 */ + <9 0 &porta 17 0>, /* TWCK1 EXT2 */ + <10 0 &porta 5 0>, /* RXD0 */ + <11 0 &porta 4 0>, /* TXD0 */ + <12 0 &portb 3 0>, /* SPI5(SS) */ + <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ + <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ + <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + }; + + ext2_header: xplained-pro-connector2 { + compatible = "atmel-xplained-pro-header"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; /* Shared */ + gpio-map = /*<0 0 - - 0>, - */ + /*<1 0 - - 0>, - */ + <2 0 &porta 15 0>, /* GPIO */ + /*<3 0 - - 0>, - */ + /*<4 0 - - 0>, - */ + /*<5 0 - - 0>, - */ + /*<6 0 - - 0>, - */ + <7 0 &porta 8 0>, /* GPIO */ + <8 0 &porta 16 0>, /* TWD1 EXT1 */ + <9 0 &porta 17 0>, /* TWCK1 EXT1 */ + /*<11 0 - - 0>, - */ + /*<12 0 - - 0>, - */ + <12 0 &porta 14 0>, /* GPIO */ + <13 0 &portb 22 0>, /* SPI5(MOSI) EXTx */ + <14 0 &portb 2 0>, /* SPI5(MISO) EXTx */ + <15 0 &portb 23 0>; /* SPI5(SCK) EXTx */ + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_uart_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_i2c_default>; + pinctrl-names = "default"; +}; + +&sercom4 { + status = "okay"; + compatible = "atmel,sam0-spi"; + /* + * CS-PB31; MOSI-PB30; MISO-PC19; SCLK-PC18 + * PAD[1]; PAD[2]; PAD[0]; PAD[3] + */ + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom4_spi_default>; + pinctrl-names = "default"; + + cs-gpios = <&portb 31 GPIO_ACTIVE_LOW>; + + ieee802154: rf2xx@0 { + compatible = "atmel,rf2xx"; + reg = <0x0>; + spi-max-frequency = <6000000>; + irq-gpios = <&portb 0 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + reset-gpios = <&portb 15 GPIO_ACTIVE_LOW>; + slptr-gpios = <&porta 20 GPIO_ACTIVE_HIGH>; + dig2-gpios = <&portb 17 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; + status = "okay"; + tx-pwr-min = [01 11]; /* -17.0 dBm */ + tx-pwr-max = [00 04]; /* 4.0 dBm */ + tx-pwr-table = [00 01 03 04 05 05 06 06 + 07 07 07 08 08 09 09 0a + 0a 0a 0b 0b 0b 0b 0c 0c + 0c 0c 0d 0d 0d 0d 0d 0d + 0d 0d 0e 0e 0e 0e 0e 0e + 0e 0e 0e 0e 0e 0e 0f 0f]; + }; +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <2>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_spi_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb_dc_default>; + pinctrl-names = "default"; +}; + +ext1_spi: &sercom5 { +}; + +ext1_i2c: &sercom1 { +}; + +ext1_serial: &sercom0 { +}; + +ext2_spi: &sercom5 { +}; + +ext2_i2c: &sercom1 { +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The final 16 KiB is reserved for the application. + * Storage partition will be used by FCB/LittleFS/NVS + * if enabled. + */ + storage_partition: partition@3c000 { + label = "storage"; + reg = <0x0003c000 0x00004000>; + }; + }; +}; diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml new file mode 100644 index 00000000000000..25ce756d667c9c --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml @@ -0,0 +1,28 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samr21_xpro +name: SAM R21 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - flash + - gpio + - i2c + - netif + - pwm + - spi + - uart + - usb_device + - xpro_gpio + - xpro_i2c + - xpro_serial + - xpro_spi +vendor: atmel diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig b/boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig new file mode 100644 index 00000000000000..15f71b9d5eda74 --- /dev/null +++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2019 Benjamin Valentin +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_XOSC32K=y +CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr21_xpro/support/openocd.cfg b/boards/atmel/sam0/samr21_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamr21_xpro/support/openocd.cfg rename to boards/atmel/sam0/samr21_xpro/support/openocd.cfg diff --git a/boards/atmel/sam0/samr34_xpro/Kconfig.samr34_xpro b/boards/atmel/sam0/samr34_xpro/Kconfig.samr34_xpro new file mode 100644 index 00000000000000..b5141577e59b30 --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/Kconfig.samr34_xpro @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SAMR34_XPRO + select SOC_SAMR34J18B diff --git a/boards/arm/atsamr34_xpro/board.cmake b/boards/atmel/sam0/samr34_xpro/board.cmake similarity index 100% rename from boards/arm/atsamr34_xpro/board.cmake rename to boards/atmel/sam0/samr34_xpro/board.cmake diff --git a/boards/atmel/sam0/samr34_xpro/board.yml b/boards/atmel/sam0/samr34_xpro/board.yml new file mode 100644 index 00000000000000..39df0e0451b64e --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/board.yml @@ -0,0 +1,5 @@ +board: + name: samr34_xpro + vendor: atmel + socs: + - name: samr34j18b diff --git a/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro-pinout.jpg b/boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro-pinout.jpg similarity index 100% rename from boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro-pinout.jpg rename to boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro-pinout.jpg diff --git a/boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro.jpg b/boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro.jpg similarity index 100% rename from boards/arm/atsamr34_xpro/doc/img/atsamr34-xpro.jpg rename to boards/atmel/sam0/samr34_xpro/doc/img/atsamr34-xpro.jpg diff --git a/boards/atmel/sam0/samr34_xpro/doc/index.rst b/boards/atmel/sam0/samr34_xpro/doc/index.rst new file mode 100644 index 00000000000000..aa8849d2cb3d41 --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/doc/index.rst @@ -0,0 +1,218 @@ + .. _samr34_xpro: + +SAM R34 Xplained Pro Evaluation Kit +################################### + +Overview +******** + +The SAM R34 Xplained Pro evaluation kit is ideal for evaluation and +prototyping with the SAM R34 Cortex®-M0+ processor-based +microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG), +which provides a full debug interface without the need for additional +hardware. + +The SAMR34 and SAMR35 parts are produced as a System-in-Package (SiP), +including both a SAML21 die, and a Semtech SX1276 LoRa radio die. + +This board is also referred to as DM320111. + +.. image:: img/atsamr34-xpro.jpg + :align: center + :alt: SAMR34-XPRO + +Hardware +******** + +- SAMR34J18 ARM Cortex-M0+ processor at 48 MHz +- 32.768 kHz crystal oscillator +- 256 KiB flash memory, 32 KiB of SRAM, 8KB Low Power SRAM +- One yellow user LED +- One mechanical user push button +- One reset button +- On-board USB based EDBG unit with serial console + +Supported Features +================== + +The samr34_xpro board configuration supports the following hardware +features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - PWM + - on-chip + - Pulse Width Modulation + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + * - TRNG + - on-chip + - True Random Number Generator + +The following hardware features are supported by Zephyr, but not yet fully +supported by the SOC: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - LoRa Radio + - on-chip + - Internal SX1276 LoRa Radio + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig`. + +Pin Mapping +=========== + +The SAM R34 Xplained Pro evaluation kit has 3 GPIO controllers. These +controllers are responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `SAM R34 Family Datasheet`_ and the `SAM R34 +Xplained Pro Schematic`_. + +.. image:: img/atsamr34-xpro-pinout.jpg + :align: center + :alt: SAMR34-XPRO-pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- +- SERCOM0 UART TX : PA04 +- SERCOM0 UART RX : PA05 +- SERCOM1 I2C SDA : PA16 +- SERCOM1 I2C SCL : PA17 +- SERCOM4 SPI MISO : PC19 +- SERCOM4 SPI MOSI : PB30 +- SERCOM4 SPI SCK : PC18 +- SERCOM4 GPIO CS : PB31 +- SERCOM5 SPI MISO : PB02 +- SERCOM5 SPI MOSI : PB22 +- SERCOM5 SPI SCK : PB23 +- SERCOM5 GPIO CS0 : PA23 +- SERCOM5 GPIO CS1 : PA14 +- USB DP : PA25 +- USB DM : PA24 +- GPIO/PWM LED0 : PA19 + +System Clock +============ + +The SAMR34 MCU is configured to use the 32.768 kHz external oscillator +with the on-chip PLL generating the 48 MHz system clock. + +Serial Port +=========== + +The SAMR34 MCU has six SERCOM based USARTs with one configured as USART in +this BSP. SERCOM0 is the default Zephyr console. + +- SERCOM0 115200 8n1 - connected to the onboard Atmel Embedded Debugger (EDBG) + +PWM +=== + +The SAMR34 MCU has 3 TCC based PWM units with up to 4 outputs each and a period +of 24 bits or 16 bits. If :code:`CONFIG_PWM_SAM0_TCC` is enabled then LED0 is +driven by TCC0 instead of by GPIO. + +SPI Port +======== + +The SAMR34 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP. + +- SERCOM4 - connected to the internal LoRa radio +- SERCOM5 - connected to EXT1 and EXT3 + +Programming and Debugging +************************* + +The SAM R34 Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This +provides a debug interface to the SAMR34 chip and is supported by +OpenOCD. + +Flashing +======== + +#. Build the Zephyr kernel and the ``hello_world`` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr34_xpro + :goals: build + :compact: + +#. Connect the SAM R34 Xplained Pro to your host computer using the USB debug + port. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ picocom -b 115200 /dev/ttyACM0 + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: samr34_xpro + :goals: flash + :compact: + + You should see "Hello World! samr34_xpro" in your terminal. + +References +********** + +.. target-notes:: + +.. _Microchip website: + https://www.microchip.com/en-us/development-tool/dm320111 + +.. _SAM L21 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM_L21_Family_DataSheet_DS60001477C.pdf + +.. _SAM R34 Family Datasheet: + https://ww1.microchip.com/downloads/en/DeviceDoc/SAM-R34-R35-Low-Power-LoRa-Sub-GHz-SiP-Data-Sheet-DS70005356C.pdf + +.. _SAM R34 Xplained Pro Schematic: + https://ww1.microchip.com/downloads/Secure/en/DeviceDoc/SAMR34_SiP_Reference_Design_Package_V3.0.exe + +.. _Semtech SX1276: + https://www.semtech.com/products/wireless-rf/lora-transceivers/sx1276 diff --git a/boards/arm/atsamr34_xpro/atsamr34_xpro-pinctrl.dtsi b/boards/atmel/sam0/samr34_xpro/samr34_xpro-pinctrl.dtsi similarity index 100% rename from boards/arm/atsamr34_xpro/atsamr34_xpro-pinctrl.dtsi rename to boards/atmel/sam0/samr34_xpro/samr34_xpro-pinctrl.dtsi diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts b/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts new file mode 100644 index 00000000000000..964cd8af4dfc9f --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "samr34_xpro-pinctrl.dtsi" +#include + +/ { + model = "SAM R34 Xplained Pro"; + compatible = "samr34,xpro", "atmel,samr34j18b", "atmel,samr34"; + + chosen { + zephyr,console = &sercom0; + zephyr,shell-uart = &sercom0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + pwm-led0 = &pwm_led0; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&porta 19 GPIO_ACTIVE_LOW>; + label = "Yellow LED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&tcc0 3 PWM_MSEC(20)>; + }; + }; + + buttons { + compatible = "gpio-keys"; + user_button: button_0 { + gpios = <&porta 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW0"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = <48000000>; +}; + +&adc { + status = "okay"; +}; + +&tcc0 { + status = "okay"; + compatible = "atmel,sam0-tcc-pwm"; + /* Gives a maximum period of 1.4s */ + prescaler = <4>; + #pwm-cells = <2>; + + pinctrl-0 = <&tcc0_default>; + pinctrl-names = "default"; +}; + +&sercom0 { + status = "okay"; + compatible = "atmel,sam0-uart"; + current-speed = <115200>; + rxpo = <1>; + txpo = <0>; + + pinctrl-0 = <&sercom0_default>; + pinctrl-names = "default"; +}; + +&sercom1 { + status = "okay"; + compatible = "atmel,sam0-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom1_default>; + pinctrl-names = "default"; +}; + +/* SERCOM4 is used for the internal LoRa radio */ +&sercom4 { + status = "okay"; +}; + +&lora { + status = "okay"; + + tcxo-power-gpios = <&porta 9 GPIO_ACTIVE_HIGH>; /* TCXO_PWR */ + tcxo-power-startup-delay-ms = <5>; + rfi-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ + rfo-enable-gpios = <&porta 13 GPIO_ACTIVE_HIGH>; /* BAND_SEL */ +}; + +&sercom5 { + status = "okay"; + compatible = "atmel,sam0-spi"; + dipo = <0>; + dopo = <1>; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-0 = <&sercom5_default>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usb0 { + status = "okay"; + + pinctrl-0 = <&usb0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml new file mode 100644 index 00000000000000..be66ff6cde536c --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +identifier: samr34_xpro +name: SAM R34 Xplained Pro +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +flash: 256 +ram: 32 +supported: + - adc + - counter + - dma + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: atmel diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig b/boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig new file mode 100644 index 00000000000000..50125e5510d6f9 --- /dev/null +++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAML_XOSC32K=y +CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/atsamr34_xpro/support/openocd.cfg b/boards/atmel/sam0/samr34_xpro/support/openocd.cfg similarity index 100% rename from boards/arm/atsamr34_xpro/support/openocd.cfg rename to boards/atmel/sam0/samr34_xpro/support/openocd.cfg diff --git a/boards/bbc/index.rst b/boards/bbc/index.rst new file mode 100644 index 00000000000000..e86cac8937be4d --- /dev/null +++ b/boards/bbc/index.rst @@ -0,0 +1,10 @@ +.. _boards-bbc: + +BBC +### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/bbc/microbit/Kconfig.bbc_microbit b/boards/bbc/microbit/Kconfig.bbc_microbit new file mode 100644 index 00000000000000..37fc2a5e24fee6 --- /dev/null +++ b/boards/bbc/microbit/Kconfig.bbc_microbit @@ -0,0 +1,7 @@ +# nRF51 BBC_MICROBIT board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BBC_MICROBIT + select SOC_NRF51822_QFAA diff --git a/boards/bbc/microbit/Kconfig.defconfig b/boards/bbc/microbit/Kconfig.defconfig new file mode 100644 index 00000000000000..1f8bf5b8bc7452 --- /dev/null +++ b/boards/bbc/microbit/Kconfig.defconfig @@ -0,0 +1,19 @@ +# nRF51 BBC_MICROBIT board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BBC_MICROBIT + +config BT_CTLR + default BT + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +endif # FXOS8700 + +endif # BOARD_BBC_MICROBIT diff --git a/boards/arm/bbc_microbit/bbc_microbit-pinctrl.dtsi b/boards/bbc/microbit/bbc_microbit-pinctrl.dtsi similarity index 100% rename from boards/arm/bbc_microbit/bbc_microbit-pinctrl.dtsi rename to boards/bbc/microbit/bbc_microbit-pinctrl.dtsi diff --git a/boards/arm/bbc_microbit/bbc_microbit.dts b/boards/bbc/microbit/bbc_microbit.dts similarity index 100% rename from boards/arm/bbc_microbit/bbc_microbit.dts rename to boards/bbc/microbit/bbc_microbit.dts diff --git a/boards/arm/bbc_microbit/bbc_microbit.yaml b/boards/bbc/microbit/bbc_microbit.yaml similarity index 100% rename from boards/arm/bbc_microbit/bbc_microbit.yaml rename to boards/bbc/microbit/bbc_microbit.yaml diff --git a/boards/bbc/microbit/bbc_microbit_defconfig b/boards/bbc/microbit/bbc_microbit_defconfig new file mode 100644 index 00000000000000..6bff8b91228cd7 --- /dev/null +++ b/boards/bbc/microbit/bbc_microbit_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock control +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bbc_microbit/board.cmake b/boards/bbc/microbit/board.cmake similarity index 100% rename from boards/arm/bbc_microbit/board.cmake rename to boards/bbc/microbit/board.cmake diff --git a/boards/arm/bbc_microbit/board.h b/boards/bbc/microbit/board.h similarity index 100% rename from boards/arm/bbc_microbit/board.h rename to boards/bbc/microbit/board.h diff --git a/boards/bbc/microbit/board.yml b/boards/bbc/microbit/board.yml new file mode 100644 index 00000000000000..3983adf061e37d --- /dev/null +++ b/boards/bbc/microbit/board.yml @@ -0,0 +1,5 @@ +board: + name: bbc_microbit + vendor: bbc + socs: + - name: nrf51822 diff --git a/boards/arm/bbc_microbit/doc/img/bbc_microbit.jpg b/boards/bbc/microbit/doc/img/bbc_microbit.jpg similarity index 100% rename from boards/arm/bbc_microbit/doc/img/bbc_microbit.jpg rename to boards/bbc/microbit/doc/img/bbc_microbit.jpg diff --git a/boards/arm/bbc_microbit/doc/index.rst b/boards/bbc/microbit/doc/index.rst similarity index 100% rename from boards/arm/bbc_microbit/doc/index.rst rename to boards/bbc/microbit/doc/index.rst diff --git a/boards/arm/96b_carbon_nrf51/pre_dt_board.cmake b/boards/bbc/microbit/pre_dt_board.cmake similarity index 100% rename from boards/arm/96b_carbon_nrf51/pre_dt_board.cmake rename to boards/bbc/microbit/pre_dt_board.cmake diff --git a/boards/bbc/microbit_v2/Kconfig.bbc_microbit_v2 b/boards/bbc/microbit_v2/Kconfig.bbc_microbit_v2 new file mode 100644 index 00000000000000..172aaf9e965555 --- /dev/null +++ b/boards/bbc/microbit_v2/Kconfig.bbc_microbit_v2 @@ -0,0 +1,7 @@ +# nRF52 BBC_MICROBIT_V2 board configuration + +# Copyright (c) 2020 Lingao Meng +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BBC_MICROBIT_V2 + select SOC_NRF52833_QIAA diff --git a/boards/bbc/microbit_v2/Kconfig.defconfig b/boards/bbc/microbit_v2/Kconfig.defconfig new file mode 100644 index 00000000000000..3139f2f24c5f7c --- /dev/null +++ b/boards/bbc/microbit_v2/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 BBC_MICROBIT_V2 board configuration + +# Copyright (c) 2020 Lingao Meng +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BBC_MICROBIT_V2 + +config BT_CTLR + default BT + +endif # BOARD_BBC_MICROBIT_V2 diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2-pinctrl.dtsi b/boards/bbc/microbit_v2/bbc_microbit_v2-pinctrl.dtsi similarity index 100% rename from boards/arm/bbc_microbit_v2/bbc_microbit_v2-pinctrl.dtsi rename to boards/bbc/microbit_v2/bbc_microbit_v2-pinctrl.dtsi diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts b/boards/bbc/microbit_v2/bbc_microbit_v2.dts similarity index 100% rename from boards/arm/bbc_microbit_v2/bbc_microbit_v2.dts rename to boards/bbc/microbit_v2/bbc_microbit_v2.dts diff --git a/boards/arm/bbc_microbit_v2/bbc_microbit_v2.yaml b/boards/bbc/microbit_v2/bbc_microbit_v2.yaml similarity index 100% rename from boards/arm/bbc_microbit_v2/bbc_microbit_v2.yaml rename to boards/bbc/microbit_v2/bbc_microbit_v2.yaml diff --git a/boards/bbc/microbit_v2/bbc_microbit_v2_defconfig b/boards/bbc/microbit_v2/bbc_microbit_v2_defconfig new file mode 100644 index 00000000000000..dddc2f924d0955 --- /dev/null +++ b/boards/bbc/microbit_v2/bbc_microbit_v2_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# clock control +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bbc_microbit_v2/board.cmake b/boards/bbc/microbit_v2/board.cmake similarity index 100% rename from boards/arm/bbc_microbit_v2/board.cmake rename to boards/bbc/microbit_v2/board.cmake diff --git a/boards/bbc/microbit_v2/board.yml b/boards/bbc/microbit_v2/board.yml new file mode 100644 index 00000000000000..1355002a7d1fbe --- /dev/null +++ b/boards/bbc/microbit_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: bbc_microbit_v2 + vendor: bbc + socs: + - name: nrf52833 diff --git a/boards/arm/bbc_microbit_v2/doc/img/bbc_microbit2.jpg b/boards/bbc/microbit_v2/doc/img/bbc_microbit2.jpg similarity index 100% rename from boards/arm/bbc_microbit_v2/doc/img/bbc_microbit2.jpg rename to boards/bbc/microbit_v2/doc/img/bbc_microbit2.jpg diff --git a/boards/arm/bbc_microbit_v2/doc/index.rst b/boards/bbc/microbit_v2/doc/index.rst similarity index 100% rename from boards/arm/bbc_microbit_v2/doc/index.rst rename to boards/bbc/microbit_v2/doc/index.rst diff --git a/boards/arm/bl653_dvk/pre_dt_board.cmake b/boards/bbc/microbit_v2/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl653_dvk/pre_dt_board.cmake rename to boards/bbc/microbit_v2/pre_dt_board.cmake diff --git a/boards/arm/beagle_bcf/CMakeLists.txt b/boards/beagle/beagleconnect_freedom/CMakeLists.txt similarity index 100% rename from boards/arm/beagle_bcf/CMakeLists.txt rename to boards/beagle/beagleconnect_freedom/CMakeLists.txt diff --git a/boards/beagle/beagleconnect_freedom/Kconfig b/boards/beagle/beagleconnect_freedom/Kconfig new file mode 100644 index 00000000000000..76a029c88606e6 --- /dev/null +++ b/boards/beagle/beagleconnect_freedom/Kconfig @@ -0,0 +1,17 @@ +# BeagleConnect Freedom board configuration + +# Copyright (c) 2020 Erik Larson +# Copyright (c) 2021 Jason Kridner, BeagleBoard.org Foundation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BEAGLECONNECT_FREEDOM + +config BOARD_ANTENNA_INIT_PRIO + int "Board antenna switch initialization priority" + default 70 + help + Set the priority for board init, must be greater than + KERNEL_INIT_PRIORITY_DEVICE but smaller than + IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. + +endif # BOARD_BEAGLECONNECT_FREEDOM diff --git a/boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom b/boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom new file mode 100644 index 00000000000000..28ddae96e897ad --- /dev/null +++ b/boards/beagle/beagleconnect_freedom/Kconfig.beagleconnect_freedom @@ -0,0 +1,8 @@ +# BeagleConnect Freedom board configuration + +# Copyright (c) 2020 Erik Larson +# Copyright (c) 2021 Jason Kridner, BeagleBoard.org Foundation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEAGLECONNECT_FREEDOM + select SOC_CC1352P7 diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom-pinctrl.dtsi b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi similarity index 100% rename from boards/arm/beagle_bcf/beagleconnect_freedom-pinctrl.dtsi rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom-pinctrl.dtsi diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts similarity index 100% rename from boards/arm/beagle_bcf/beagleconnect_freedom.dts rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom.yaml b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml similarity index 100% rename from boards/arm/beagle_bcf/beagleconnect_freedom.yaml rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml diff --git a/boards/arm/beagle_bcf/beagleconnect_freedom_defconfig b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig similarity index 87% rename from boards/arm/beagle_bcf/beagleconnect_freedom_defconfig rename to boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig index a2c05f40f32331..024c0463996e90 100644 --- a/boards/arm/beagle_bcf/beagleconnect_freedom_defconfig +++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom_defconfig @@ -8,9 +8,6 @@ CONFIG_GPIO=y CONFIG_PINCTRL=y -CONFIG_SOC_SERIES_CC13X2X7_CC26X2X7=y -CONFIG_SOC_CC1352P7=y -CONFIG_BOARD_BEAGLECONNECT_FREEDOM=y CONFIG_BUILD_OUTPUT_HEX=y # custom callback for the antenna switch CONFIG_CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS=y diff --git a/boards/arm/beagle_bcf/board.cmake b/boards/beagle/beagleconnect_freedom/board.cmake similarity index 100% rename from boards/arm/beagle_bcf/board.cmake rename to boards/beagle/beagleconnect_freedom/board.cmake diff --git a/boards/beagle/beagleconnect_freedom/board.yml b/boards/beagle/beagleconnect_freedom/board.yml new file mode 100644 index 00000000000000..a0d11fb2410fe2 --- /dev/null +++ b/boards/beagle/beagleconnect_freedom/board.yml @@ -0,0 +1,5 @@ +board: + name: beagleconnect_freedom + vendor: beagle + socs: + - name: cc1352p7 diff --git a/boards/arm/beagle_bcf/board_antenna.c b/boards/beagle/beagleconnect_freedom/board_antenna.c similarity index 100% rename from boards/arm/beagle_bcf/board_antenna.c rename to boards/beagle/beagleconnect_freedom/board_antenna.c diff --git a/boards/arm/beagle_bcf/doc/img/beagleconnect_freedom.webp b/boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom.webp similarity index 100% rename from boards/arm/beagle_bcf/doc/img/beagleconnect_freedom.webp rename to boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom.webp diff --git a/boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_back_annotated.webp b/boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_back_annotated.webp similarity index 100% rename from boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_back_annotated.webp rename to boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_back_annotated.webp diff --git a/boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_front_annotated.webp b/boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_front_annotated.webp similarity index 100% rename from boards/arm/beagle_bcf/doc/img/beagleconnect_freedom_front_annotated.webp rename to boards/beagle/beagleconnect_freedom/doc/img/beagleconnect_freedom_front_annotated.webp diff --git a/boards/arm/beagle_bcf/doc/index.rst b/boards/beagle/beagleconnect_freedom/doc/index.rst similarity index 100% rename from boards/arm/beagle_bcf/doc/index.rst rename to boards/beagle/beagleconnect_freedom/doc/index.rst diff --git a/boards/beagle/beaglev_fire/Kconfig b/boards/beagle/beaglev_fire/Kconfig new file mode 100644 index 00000000000000..a0ce11033e7d5a --- /dev/null +++ b/boards/beagle/beaglev_fire/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEAGLEV_FIRE + select 64BIT + select SCHED_IPI_SUPPORTED + select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/beagle/beaglev_fire/Kconfig.beaglev_fire b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire new file mode 100644 index 00000000000000..b4bf8b4b2d3dd7 --- /dev/null +++ b/boards/beagle/beaglev_fire/Kconfig.beaglev_fire @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BEAGLEV_FIRE + select SOC_POLARFIRE diff --git a/boards/riscv/beaglev_fire/beaglev_fire.dts b/boards/beagle/beaglev_fire/beaglev_fire.dts similarity index 100% rename from boards/riscv/beaglev_fire/beaglev_fire.dts rename to boards/beagle/beaglev_fire/beaglev_fire.dts diff --git a/boards/riscv/beaglev_fire/beaglev_fire.yaml b/boards/beagle/beaglev_fire/beaglev_fire.yaml similarity index 100% rename from boards/riscv/beaglev_fire/beaglev_fire.yaml rename to boards/beagle/beaglev_fire/beaglev_fire.yaml diff --git a/boards/riscv/beaglev_fire/beaglev_fire_defconfig b/boards/beagle/beaglev_fire/beaglev_fire_defconfig similarity index 77% rename from boards/riscv/beaglev_fire/beaglev_fire_defconfig rename to boards/beagle/beaglev_fire/beaglev_fire_defconfig index eaf7d9c6f15802..deb1db784f8bf3 100644 --- a/boards/riscv/beaglev_fire/beaglev_fire_defconfig +++ b/boards/beagle/beaglev_fire/beaglev_fire_defconfig @@ -1,12 +1,9 @@ # Copyright (c) 2023 Microchip Technology Inc # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_POLARFIRE=y -CONFIG_SOC_POLARFIRE=y CONFIG_MPFS_HAL=n CONFIG_BASE64=y CONFIG_INCLUDE_RESET_VECTOR=y -CONFIG_BOARD_BEAGLEV_FIRE=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/beagle/beaglev_fire/board.yml b/boards/beagle/beaglev_fire/board.yml new file mode 100644 index 00000000000000..89447e4b4ce319 --- /dev/null +++ b/boards/beagle/beaglev_fire/board.yml @@ -0,0 +1,5 @@ +board: + name: beaglev_fire + vendor: beagle + socs: + - name: polarfire diff --git a/boards/riscv/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp b/boards/beagle/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp similarity index 100% rename from boards/riscv/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp rename to boards/beagle/beaglev_fire/doc/img/BeagleV-Fire-Front-Annotated-768x432.webp diff --git a/boards/riscv/beaglev_fire/doc/img/board-booting.png b/boards/beagle/beaglev_fire/doc/img/board-booting.png similarity index 100% rename from boards/riscv/beaglev_fire/doc/img/board-booting.png rename to boards/beagle/beaglev_fire/doc/img/board-booting.png diff --git a/boards/riscv/beaglev_fire/doc/index.rst b/boards/beagle/beaglev_fire/doc/index.rst similarity index 100% rename from boards/riscv/beaglev_fire/doc/index.rst rename to boards/beagle/beaglev_fire/doc/index.rst diff --git a/boards/beagle/index.rst b/boards/beagle/index.rst new file mode 100644 index 00000000000000..e0afe34ad49f30 --- /dev/null +++ b/boards/beagle/index.rst @@ -0,0 +1,10 @@ +.. _boards-beagle: + +BeagleBoard.org Foundation +########################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/blue_clover/index.rst b/boards/blue_clover/index.rst new file mode 100644 index 00000000000000..b629a34e8eb1a8 --- /dev/null +++ b/boards/blue_clover/index.rst @@ -0,0 +1,10 @@ +.. _boards-blue-clover: + +Blue Clover Devices +################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig b/boards/blue_clover/plt_demo_v2/Kconfig similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/Kconfig rename to boards/blue_clover/plt_demo_v2/Kconfig diff --git a/boards/blue_clover/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 b/boards/blue_clover/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 new file mode 100644 index 00000000000000..2b69264a29cb75 --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/Kconfig.blueclover_plt_demo_v2 @@ -0,0 +1,7 @@ +# Blue Clover PLT Demo V2 Configuration + +# Copyright (c) 2021 Blue Clover +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 + select SOC_NRF52832_QFAA diff --git a/boards/blue_clover/plt_demo_v2/Kconfig.defconfig b/boards/blue_clover/plt_demo_v2/Kconfig.defconfig new file mode 100644 index 00000000000000..ce7c0c3891f64e --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Blue Clover PLT Demo V2 Configuration + +# Copyright (c) 2021 Blue Clover +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 + +config BT_CTLR + default BT + +config I2C + default SENSOR + +endif # BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832 diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832-pinctrl.dtsi diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.dts b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.dts rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.dts diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.yaml b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml similarity index 85% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.yaml rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml index f031e5105efb9f..6536b8a957f585 100644 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832.yaml +++ b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -identifier: blueclover_plt_demo_v2_nrf52832 +identifier: blueclover_plt_demo_v2/nrf52832 name: Blue Clover PLT Demo Board V2 type: mcu arch: arm diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832_defconfig b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832_defconfig similarity index 75% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832_defconfig rename to boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832_defconfig index d9999ba9516cc9..e953d30137e12a 100644 --- a/boards/arm/blueclover_plt_demo_v2_nrf52832/blueclover_plt_demo_v2_nrf52832_defconfig +++ b/boards/blue_clover/plt_demo_v2/blueclover_plt_demo_v2_nrf52832_defconfig @@ -4,10 +4,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_BLUECLOVER_PLT_DEMO_V2_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/board.cmake b/boards/blue_clover/plt_demo_v2/board.cmake similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/board.cmake rename to boards/blue_clover/plt_demo_v2/board.cmake diff --git a/boards/blue_clover/plt_demo_v2/board.yml b/boards/blue_clover/plt_demo_v2/board.yml new file mode 100644 index 00000000000000..2d0c58bf628342 --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: blueclover_plt_demo_v2 + vendor: bcdevices + socs: + - name: nrf52832 diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/doc/img/blueclover_plt_demo_v2.jpg b/boards/blue_clover/plt_demo_v2/doc/img/blueclover_plt_demo_v2.jpg similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/doc/img/blueclover_plt_demo_v2.jpg rename to boards/blue_clover/plt_demo_v2/doc/img/blueclover_plt_demo_v2.jpg diff --git a/boards/blue_clover/plt_demo_v2/doc/index.rst b/boards/blue_clover/plt_demo_v2/doc/index.rst new file mode 100644 index 00000000000000..ae3b5c158f77ca --- /dev/null +++ b/boards/blue_clover/plt_demo_v2/doc/index.rst @@ -0,0 +1,153 @@ +.. _blueclover_plt_demo_v2_nrf52832: + +Blue Clover PLT Demo V2 nRF52832 +################################ + +Overview +******** + +The Blue Clover PLT Demo V2 is an open source (OSWHA certified) hardware +product, featuring the Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU +and several useful external peripherals. + +The Nordic Semiconductor nRF52832 ARM Cortex-M4F MCU features the following: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/blueclover_plt_demo_v2.jpg + :align: center + :alt: Blue Clover PLT Demo V2 nRF52832 + +Hardware +******** + +- nRF52832 ARM Cortex-M4F processor at 64 MHz +- 512 KB flash memory and 64 KB of SRAM +- Bosch BMI270 IMU +- Sensiron SHT30 Humidity and Temperature sensor +- Murata PKLCS1212E4001R1 Piezo Buzzer +- Battery connector and charger for 3.7 V lithium polymer batteries +- 4 APA102C Addressable LEDs +- Reset button (can be configured as user button) +- 1 User button +- Tag-Connect TC2030-FP 6-pin Debug Connector + +Supported Features +================== + +The Blue Clover PLT Demo V2 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +Push buttons +------------ + +* RESET = P0.21 +* STATUS = P0.26 + +UART +---- + +* TXD = P0.06 +* RXD = P0.08 + +Power +----- + +* USB-C Connector +* JST-PH Battery Connector + +NFC +--- + +* U.FL Connector, on NFC1/P0.09, NFC2/P0.10 + +Programming and Debugging +************************* + +Applications for the ``blueclover_plt_demo_v2/nrf52832`` board configuration +can be built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing +======== + +Flashing Zephyr onto the ``blueclover_plt_demo_v2/nrf52832`` board requires +an external programmer. The programmer is attached to the SWD header. + +Build the Zephyr kernel and the :zephyr:code-sample:`led-apa102` sample application. + + .. zephyr-app-commands:: + :zephyr-app: samples/drivers/led_apa102 + :board: blueclover_plt_demo_v2/nrf52832 + :goals: build + :compact: + +Flash the image. + + .. zephyr-app-commands:: + :zephyr-app: samples/drivers/led_apa102 + :board: blueclover_plt_demo_v2/nrf52832 + :goals: flash + :compact: + +References +********** + +.. target-notes:: + +.. _Blue Clover PLT Demo V2 Product site: + https://bcdevices.com/products/plt-demo-board + +.. _Blue Clover PLT Demo V2 OSWHA Certification: + https://certification.oshwa.org/us002054.html + +.. _Schematic, layout, and gerbers: + https://github.com/bcdevices/plt-docs/tree/master/PLT-DEMOv2 diff --git a/boards/arm/bl654_dvk/pre_dt_board.cmake b/boards/blue_clover/plt_demo_v2/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl654_dvk/pre_dt_board.cmake rename to boards/blue_clover/plt_demo_v2/pre_dt_board.cmake diff --git a/boards/blues/index.rst b/boards/blues/index.rst new file mode 100644 index 00000000000000..a4f76b4c9fadd8 --- /dev/null +++ b/boards/blues/index.rst @@ -0,0 +1,10 @@ +.. _boards-blues: + +Blues +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/nrf52840dongle_nrf52840/CMakeLists.txt b/boards/blues/swan_r5/CMakeLists.txt similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/CMakeLists.txt rename to boards/blues/swan_r5/CMakeLists.txt diff --git a/boards/blues/swan_r5/Kconfig.defconfig b/boards/blues/swan_r5/Kconfig.defconfig new file mode 100644 index 00000000000000..a9d7a1e00b1a2e --- /dev/null +++ b/boards/blues/swan_r5/Kconfig.defconfig @@ -0,0 +1,22 @@ +# Blues Wireless Swan board configuration + +# Copyright (c) 2022 Blues Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SWAN_R5 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_EEM + default y + +endif # NETWORKING + +endif # BOARD_SWAN_R5 diff --git a/boards/blues/swan_r5/Kconfig.swan_r5 b/boards/blues/swan_r5/Kconfig.swan_r5 new file mode 100644 index 00000000000000..6b3b835c31f1e2 --- /dev/null +++ b/boards/blues/swan_r5/Kconfig.swan_r5 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Blues Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SWAN_R5 + select SOC_STM32L4R5XX diff --git a/boards/arm/swan_r5/board.c b/boards/blues/swan_r5/board.c similarity index 100% rename from boards/arm/swan_r5/board.c rename to boards/blues/swan_r5/board.c diff --git a/boards/arm/swan_r5/board.cmake b/boards/blues/swan_r5/board.cmake similarity index 100% rename from boards/arm/swan_r5/board.cmake rename to boards/blues/swan_r5/board.cmake diff --git a/boards/blues/swan_r5/board.yml b/boards/blues/swan_r5/board.yml new file mode 100644 index 00000000000000..d9d4096e352a47 --- /dev/null +++ b/boards/blues/swan_r5/board.yml @@ -0,0 +1,5 @@ +board: + name: swan_r5 + vendor: blues + socs: + - name: stm32l4r5xx diff --git a/boards/arm/swan_r5/doc/img/swan.jpg b/boards/blues/swan_r5/doc/img/swan.jpg similarity index 100% rename from boards/arm/swan_r5/doc/img/swan.jpg rename to boards/blues/swan_r5/doc/img/swan.jpg diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst new file mode 100644 index 00000000000000..644e82e86dd95c --- /dev/null +++ b/boards/blues/swan_r5/doc/index.rst @@ -0,0 +1,232 @@ +.. _swan_r5_board: + +Blues Wireless Swan +################### + +Overview +******** + +Swan is a low-cost embeddable STM32L4-based microcontroller designed to +accelerate the development and deployment of battery-powered solutions. +It is especially useful for applications requiring large memory or a high +degree of I/O expandability at an affordable cost, such as edge inferencing +and remote monitoring. + +Uniquely for Feather-compatible boards, Swan is designed to satisfy +developers' needs that span from early prototyping through high-volume +deployment. Developers may begin to use Swan in conjunction with +Adafruit's myriad sensors and FeatherWing-compatible carriers. +Due to its novel design, for high-volume deployment the low-cost Swan +can also be soldered directly to a parent PCB integrating those sensors, +utilizing the full range of Swan's I/O capabilities. + +The board has three independent power options-USB, Battery, or Line power- +and provides a software-switchable 2 Amp regulator for powering external +sensors. When operating in its low-power operating mode, the entire Swan +board commonly draws only about 8uA while retaining all of its memory, +making it quite suitable for battery-powered devices. + +The Swan board features an ARM Cortex-M4 based STM32L4R5ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the board: + +- STM32 microcontroller in WLCSP144 package +- 2MB of flash and 640KB of RAM +- Two types of extension resources: + + - Adafruit Feather-compatible connectivity + - Access to 36 additional STM32 pins (beyond the Feather pins) via 0.05" castellated edge headers + +- On-board ST-LINKV3 debugger/programmer with SWD connector + +- One Red User LED (LD1) +- Two push-buttons: USER and RESET + +- Castellated-edge access to 55 GPIO ports including: + + - 8 analog + - 16 digital + - 4x I2C, 3x SPI + - USB OTG full speed + - 1x 14-channel DMA + - tRNG + - 12-bit ADC, 2 x 12-bit DAC + - low-power RTC, and CRC calculation peripherals + +.. image:: img/swan.jpg + :align: center + :alt: Blues Wireless Swan + +More information about the board can be found at the `Swan Product Page`_. + +Hardware +******** + +The STM32L4R5ZI SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode + and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive + real-time accelerator (ART Accelerator) allowing 0-wait-state + execution from Flash memory, frequency up to 120 MHz, MPU, 150 + DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions + +- Memories + + - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection + - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check + - External memory interface for static memories supporting SRAM, + PSRAM, NOR, NAND and FRAM memories + - 2 x OctoSPI memory interface + +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace + Macrocell (ETM) + +More information about Swan can be found here: + +- `Swan Quickstart Guide`_ +- `Swan Datasheet`_ + +Supported Features +================== + +The Zephyr Swan board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/blues/swan_r5/swan_r5_defconfig` + + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- A0 : PA3 +- A1 : PA1 +- A2 : PC3 +- A3 : PC1 +- A4 : PC4 +- A5 : PC5 +- D4 : PE3 +- D5 : PE11 +- D6 : PE9 +- D9 : PD15 +- D10 : PA4 +- D11 : PA7 +- D12 : PA6 +- D13 : PA5 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PD6 +- UART_3_TX : PB10 +- UART_3_RX : PB11 +- LPUART_TX : PG7 +- LPUART_RX : PG8 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- I2C_2_SCL : PF1 +- I2C_2_SDA : PF0 +- I2C_3_SCL : PC0 +- I2C_3_SDA : PC9 +- SPI_1_NSS : PA4 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PD0 +- SPI_2_SCK : PD1 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PA15 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD1 : PE2 +- USB DM : PA11 +- USB DP : PA12 +- ADC1 : PA1 + +System Clock +------------ + +Swan System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default, the System clock is +driven by the PLL clock at 80MHz, driven by a 16MHz high speed +internal oscillator. + +Serial Port +----------- + +Swan has 4 U(S)ARTs. The Zephyr console output is +assigned to LPUART. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Connect Swan to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Swan: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: swan_r5 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +References +********** + +.. _Swan Product Page: + https://blues.io/products/swan + +.. _Swan Quickstart Guide: + https://dev.blues.io/start/swan/swan-quickstart + +.. _Swan Datasheet: + https://dev.blues.io/hardware/swan-datasheet/ diff --git a/boards/arm/swan_r5/feather_connector.dtsi b/boards/blues/swan_r5/feather_connector.dtsi similarity index 100% rename from boards/arm/swan_r5/feather_connector.dtsi rename to boards/blues/swan_r5/feather_connector.dtsi diff --git a/boards/arm/nucleo_l476rg/support/openocd.cfg b/boards/blues/swan_r5/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l476rg/support/openocd.cfg rename to boards/blues/swan_r5/support/openocd.cfg diff --git a/boards/arm/swan_r5/swan_r5.dts b/boards/blues/swan_r5/swan_r5.dts similarity index 100% rename from boards/arm/swan_r5/swan_r5.dts rename to boards/blues/swan_r5/swan_r5.dts diff --git a/boards/arm/swan_r5/swan_r5.yaml b/boards/blues/swan_r5/swan_r5.yaml similarity index 100% rename from boards/arm/swan_r5/swan_r5.yaml rename to boards/blues/swan_r5/swan_r5.yaml diff --git a/boards/arm/swan_r5/swan_r5_defconfig b/boards/blues/swan_r5/swan_r5_defconfig similarity index 86% rename from boards/arm/swan_r5/swan_r5_defconfig rename to boards/blues/swan_r5/swan_r5_defconfig index caaca50d8b881c..596cbc88cbdcd5 100644 --- a/boards/arm/swan_r5/swan_r5_defconfig +++ b/boards/blues/swan_r5/swan_r5_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/bcm958401m2/CMakeLists.txt b/boards/brcm/bcm958401m2/CMakeLists.txt similarity index 100% rename from boards/arm/bcm958401m2/CMakeLists.txt rename to boards/brcm/bcm958401m2/CMakeLists.txt diff --git a/boards/brcm/bcm958401m2/Kconfig.bcm958401m2 b/boards/brcm/bcm958401m2/Kconfig.bcm958401m2 new file mode 100644 index 00000000000000..38fd12a9ec5629 --- /dev/null +++ b/boards/brcm/bcm958401m2/Kconfig.bcm958401m2 @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config BOARD_BCM958401M2 + select SOC_BCM58400 diff --git a/boards/arm/bcm958401m2/bcm958401m2.dts b/boards/brcm/bcm958401m2/bcm958401m2.dts similarity index 100% rename from boards/arm/bcm958401m2/bcm958401m2.dts rename to boards/brcm/bcm958401m2/bcm958401m2.dts diff --git a/boards/arm/bcm958401m2/bcm958401m2.yaml b/boards/brcm/bcm958401m2/bcm958401m2.yaml similarity index 100% rename from boards/arm/bcm958401m2/bcm958401m2.yaml rename to boards/brcm/bcm958401m2/bcm958401m2.yaml diff --git a/boards/brcm/bcm958401m2/bcm958401m2_defconfig b/boards/brcm/bcm958401m2/bcm958401m2_defconfig new file mode 100644 index 00000000000000..cc0d8af5baac55 --- /dev/null +++ b/boards/brcm/bcm958401m2/bcm958401m2_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/bcm958401m2/board.cmake b/boards/brcm/bcm958401m2/board.cmake similarity index 100% rename from boards/arm/bcm958401m2/board.cmake rename to boards/brcm/bcm958401m2/board.cmake diff --git a/boards/brcm/bcm958401m2/board.yml b/boards/brcm/bcm958401m2/board.yml new file mode 100644 index 00000000000000..06c116fe825c65 --- /dev/null +++ b/boards/brcm/bcm958401m2/board.yml @@ -0,0 +1,5 @@ +board: + name: bcm958401m2 + vendor: brcm + socs: + - name: bcm58400 diff --git a/boards/brcm/bcm958401m2/doc/index.rst b/boards/brcm/bcm958401m2/doc/index.rst new file mode 100644 index 00000000000000..e053bc2ce054e7 --- /dev/null +++ b/boards/brcm/bcm958401m2/doc/index.rst @@ -0,0 +1,57 @@ +.. _bcm958401m2: + +Broadcom BCM958401M2 +#################### + +Overview +******** +The Broadcom BCM958401M2 board utilizes the Valkyrie BCM58400 SoC to +provide support for PCIe offload engine functionality. + +Hardware +******** +The BCM958401M2 is a PCIe card with the following physical features: + +* PCIe Gen3 interface +* RS232 UART (optionally populated) +* JTAG (optionally populated) + +Supported Features +================== +The Broadcom BCM958401M2 board configuration supports the following hardware +features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vectored interrupt controller | ++-----------+------------+--------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/broadcom/bcm958401m2/bcm958401m2_defconfig` + +Connections and IOs +=================== + + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. +Board is booted over PCIe interface. + +Debugging +========= +The bcm958401m2 board includes pads for soldering a JTAG connector. +Zephyr applications running on the M7 core can also be tested by observing UART console output. + + +References +********** diff --git a/boards/arm/bcm958402m2_m7/CMakeLists.txt b/boards/brcm/bcm958402m2/CMakeLists.txt similarity index 100% rename from boards/arm/bcm958402m2_m7/CMakeLists.txt rename to boards/brcm/bcm958402m2/CMakeLists.txt diff --git a/boards/brcm/bcm958402m2/Kconfig.bcm958402m2 b/boards/brcm/bcm958402m2/Kconfig.bcm958402m2 new file mode 100644 index 00000000000000..fb3fbf5a3bd921 --- /dev/null +++ b/boards/brcm/bcm958402m2/Kconfig.bcm958402m2 @@ -0,0 +1,6 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BCM958402M2 + select SOC_BCM58402_M7 if BOARD_BCM958402M2_BCM58402_M7 + select SOC_BCM58402_A72 if BOARD_BCM958402M2_BCM58402_A72 diff --git a/boards/arm64/bcm958402m2_a72/bcm958402m2_a72.dts b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.dts similarity index 100% rename from boards/arm64/bcm958402m2_a72/bcm958402m2_a72.dts rename to boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.dts diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.yaml b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.yaml new file mode 100644 index 00000000000000..cbade5c4497d8a --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72.yaml @@ -0,0 +1,8 @@ +identifier: bcm958402m2/bcm58402/a72 +name: Broadcom BCM958402M2_A72 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +vendor: brcm diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig new file mode 100644 index 00000000000000..e7b8f00265b77b --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable PCIe EP +CONFIG_PCIE_ENDPOINT=y +CONFIG_PCIE_EP_IPROC=y +CONFIG_PCIE_EP_IPROC_V2=y + +# Enable DMA +CONFIG_DMA=y +CONFIG_DMA_64BIT=y diff --git a/boards/arm/bcm958402m2_m7/bcm958402m2_m7.dts b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.dts similarity index 100% rename from boards/arm/bcm958402m2_m7/bcm958402m2_m7.dts rename to boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.dts diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.yaml b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.yaml new file mode 100644 index 00000000000000..c5c0c06996a13d --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7.yaml @@ -0,0 +1,8 @@ +identifier: bcm958402m2/bcm58402/m7 +name: Broadcom BCM958402M2_M7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +vendor: brcm diff --git a/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig new file mode 100644 index 00000000000000..5eb9b53fa6dd30 --- /dev/null +++ b/boards/brcm/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable PCIe EP +CONFIG_PCIE_ENDPOINT=y +CONFIG_PCIE_EP_IPROC=y +CONFIG_PCIE_EP_IPROC_V2=y + +# Enable DMA +CONFIG_DMA=y +CONFIG_DMA_64BIT=y diff --git a/boards/arm/bcm958402m2_m7/board.cmake b/boards/brcm/bcm958402m2/board.cmake similarity index 100% rename from boards/arm/bcm958402m2_m7/board.cmake rename to boards/brcm/bcm958402m2/board.cmake diff --git a/boards/brcm/bcm958402m2/board.yml b/boards/brcm/bcm958402m2/board.yml new file mode 100644 index 00000000000000..e9ad1770ed577a --- /dev/null +++ b/boards/brcm/bcm958402m2/board.yml @@ -0,0 +1,5 @@ +board: + name: bcm958402m2 + vendor: brcm + socs: + - name: bcm58402 diff --git a/boards/brcm/bcm958402m2/doc/a72.rst b/boards/brcm/bcm958402m2/doc/a72.rst new file mode 100644 index 00000000000000..80fdd0ea4e5cee --- /dev/null +++ b/boards/brcm/bcm958402m2/doc/a72.rst @@ -0,0 +1,50 @@ +.. _bcm958402m2_a72: + +Broadcom BCM958402M2 (Cortex-A72) +################################# + +Overview +******** +The Broadcom ``bcm958402m2/bcm58402/a72`` board utilizes the Viper BCM58402_A72 SoC +to provide support for PCIe offload engine functionality. + +Hardware +******** +The ``bcm958402m2/bcm58402/a72`` is a PCIe card with the following physical features: + +* PCIe Gen4 interface +* RS232 UART (optionally populated) +* JTAG (optionally populated) + +Supported Features +================== +The Broadcom ``bcm958402m2/bcm58402/a72`` board configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-500 | on-chip | GICv3 interrupt controller | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/broadcom/bcm958402m2/bcm958402m2_bcm58402_a72_defconfig` + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. +Board is booted over PCIe interface. + +Debugging +========= +The ``bcm958402m2/bcm58402/a72`` board includes pads for soldering a JTAG connector. +Zephyr applications running on the Cortex-A72 core can also be tested +by observing UART console output. diff --git a/boards/brcm/bcm958402m2/doc/m7.rst b/boards/brcm/bcm958402m2/doc/m7.rst new file mode 100644 index 00000000000000..6edf138796430d --- /dev/null +++ b/boards/brcm/bcm958402m2/doc/m7.rst @@ -0,0 +1,50 @@ +.. _bcm958402m2_m7: + +Broadcom BCM958402M2 (Cortex-M7) +################################ + +Overview +******** +The Broadcom ``bcm958402m2/bcm58402/m7`` board utilizes the Viper BCM58402_M7 SoC to +provide support for PCIe offload engine functionality. + +Hardware +******** +The ``bcm958402m2/bcm58402/m7`` is a PCIe card with the following physical features: + +* PCIe Gen4 interface +* RS232 UART (optionally populated) +* JTAG (optionally populated) + +Supported Features +================== +The Broadcom ``bcm958402m2/bcm58402/m7`` board configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| NVIC | on-chip | nested vectored interrupt controller | ++-----------+------------+--------------------------------------+ +| UART | on-chip | Compatible with UART NS16550 | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/broadcom/bcm958402m2/bcm958402m2_bcm58402_m7_defconfig` + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. +Board is booted over PCIe interface. + +Debugging +========= +The ``bcm958402m2/bcm58402/m7`` board includes pads for soldering a JTAG connector. +Zephyr applications running on the M7 core can also be tested +by observing UART console output. diff --git a/boards/brcm/index.rst b/boards/brcm/index.rst new file mode 100644 index 00000000000000..08223cb7fc73e2 --- /dev/null +++ b/boards/brcm/index.rst @@ -0,0 +1,10 @@ +.. _boards-brcm: + +Broadcom Corporation +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cdns/index.rst b/boards/cdns/index.rst new file mode 100644 index 00000000000000..108368522b7681 --- /dev/null +++ b/boards/cdns/index.rst @@ -0,0 +1,10 @@ +.. _boards-cdns: + +Cadence Design Systems Inc. +########################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cdns/xt-sim/Kconfig.defconfig b/boards/cdns/xt-sim/Kconfig.defconfig new file mode 100644 index 00000000000000..98be6f9e997fab --- /dev/null +++ b/boards/cdns/xt-sim/Kconfig.defconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Cadence Design Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config IPM_CONSOLE_STACK_SIZE + default 2048 if IPM_CONSOLE_RECEIVER diff --git a/boards/cdns/xt-sim/Kconfig.xt-sim b/boards/cdns/xt-sim/Kconfig.xt-sim new file mode 100644 index 00000000000000..317547710dba4c --- /dev/null +++ b/boards/cdns/xt-sim/Kconfig.xt-sim @@ -0,0 +1,7 @@ +# XTENSA board configuration + +# Copyright (c) 2016 Cadence Design Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XT_SIM + select SOC_XTENSA_SAMPLE_CONTROLLER diff --git a/boards/xtensa/xt-sim/board.cmake b/boards/cdns/xt-sim/board.cmake similarity index 100% rename from boards/xtensa/xt-sim/board.cmake rename to boards/cdns/xt-sim/board.cmake diff --git a/boards/cdns/xt-sim/board.yml b/boards/cdns/xt-sim/board.yml new file mode 100644 index 00000000000000..d162e416a3bc0b --- /dev/null +++ b/boards/cdns/xt-sim/board.yml @@ -0,0 +1,5 @@ +board: + name: xt-sim + vendor: cdns + socs: + - name: xtensa_sample_controller diff --git a/boards/xtensa/xt-sim/doc/img/xt-sim.jpg b/boards/cdns/xt-sim/doc/img/xt-sim.jpg similarity index 100% rename from boards/xtensa/xt-sim/doc/img/xt-sim.jpg rename to boards/cdns/xt-sim/doc/img/xt-sim.jpg diff --git a/boards/xtensa/xt-sim/doc/index.rst b/boards/cdns/xt-sim/doc/index.rst similarity index 100% rename from boards/xtensa/xt-sim/doc/index.rst rename to boards/cdns/xt-sim/doc/index.rst diff --git a/boards/xtensa/xt-sim/xt-sim.dts b/boards/cdns/xt-sim/xt-sim.dts similarity index 100% rename from boards/xtensa/xt-sim/xt-sim.dts rename to boards/cdns/xt-sim/xt-sim.dts diff --git a/boards/xtensa/xt-sim/xt-sim.yaml b/boards/cdns/xt-sim/xt-sim.yaml similarity index 100% rename from boards/xtensa/xt-sim/xt-sim.yaml rename to boards/cdns/xt-sim/xt-sim.yaml diff --git a/boards/xtensa/xt-sim/xt-sim_defconfig b/boards/cdns/xt-sim/xt-sim_defconfig similarity index 77% rename from boards/xtensa/xt-sim/xt-sim_defconfig rename to boards/cdns/xt-sim/xt-sim_defconfig index 73700f07275d9c..9a055db716ffac 100644 --- a/boards/xtensa/xt-sim/xt-sim_defconfig +++ b/boards/cdns/xt-sim/xt-sim_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER=y -CONFIG_BOARD_XT_SIM=y CONFIG_CONSOLE=y CONFIG_GEN_ISR_TABLES=y diff --git a/boards/circuit_dojo/feather/Kconfig.circuitdojo_feather b/boards/circuit_dojo/feather/Kconfig.circuitdojo_feather new file mode 100644 index 00000000000000..74ef4bd8e27339 --- /dev/null +++ b/boards/circuit_dojo/feather/Kconfig.circuitdojo_feather @@ -0,0 +1,8 @@ +# Circuit Dojo nRF9160 Feather configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CIRCUITDOJO_FEATHER + select SOC_NRF9160_SICA diff --git a/boards/circuit_dojo/feather/Kconfig.defconfig b/boards/circuit_dojo/feather/Kconfig.defconfig new file mode 100644 index 00000000000000..f093911dc477c0 --- /dev/null +++ b/boards/circuit_dojo/feather/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Circuit Dojo nRF9160 Feather configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CIRCUITDOJO_FEATHER + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_CIRCUITDOJO_FEATHER_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_CIRCUITDOJO_FEATHER_NRF9160_NS + +endif # BOARD_CIRCUITDOJO_FEATHER diff --git a/boards/arm/circuitdojo_feather_nrf9160/board.cmake b/boards/circuit_dojo/feather/board.cmake similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/board.cmake rename to boards/circuit_dojo/feather/board.cmake diff --git a/boards/circuit_dojo/feather/board.yml b/boards/circuit_dojo/feather/board.yml new file mode 100644 index 00000000000000..0eb6ff5c4c0ad5 --- /dev/null +++ b/boards/circuit_dojo/feather/board.yml @@ -0,0 +1,7 @@ +board: + name: circuitdojo_feather + vendor: circuitdojo + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.dts b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.dts similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.dts rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.dts diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.yaml b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.yaml similarity index 81% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.yaml rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.yaml index 05fd7a44189965..ee93576b4af58c 100644 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160.yaml +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160.yaml @@ -1,4 +1,4 @@ -identifier: circuitdojo_feather_nrf9160 +identifier: circuitdojo_feather/nrf9160 name: CircuitDojo-Feather-nRF9160 type: mcu arch: arm diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common-pinctrl.dtsi b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common-pinctrl.dtsi similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common-pinctrl.dtsi rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common-pinctrl.dtsi diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dtsi b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common.dtsi similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_common.dtsi rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common.dtsi diff --git a/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_defconfig b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_defconfig new file mode 100644 index 00000000000000..b5a9bfd1f881be --- /dev/null +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Required to enable 3V3 power rail +CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.dts b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.dts similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.dts rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.dts diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.yaml b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.yaml similarity index 80% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.yaml rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.yaml index 56905972e9f2c1..582e28dbfc9bd2 100644 --- a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_ns.yaml +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns.yaml @@ -1,4 +1,4 @@ -identifier: circuitdojo_feather_nrf9160_ns +identifier: circuitdojo_feather/nrf9160/ns name: CircuitDojo-Feather-nRF9160-Non-Secure type: mcu arch: arm diff --git a/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns_defconfig b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..e87033d490dd53 --- /dev/null +++ b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_ns_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Required to enable 3V3 power rail +CONFIG_REGULATOR=y diff --git a/boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_partition_conf.dtsi b/boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_partition_conf.dtsi similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/circuitdojo_feather_nrf9160_partition_conf.dtsi rename to boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_partition_conf.dtsi diff --git a/boards/arm/circuitdojo_feather_nrf9160/doc/img/circuitdojo_feather_nrf9160.jpg b/boards/circuit_dojo/feather/doc/img/circuitdojo_feather_nrf9160.jpg similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/doc/img/circuitdojo_feather_nrf9160.jpg rename to boards/circuit_dojo/feather/doc/img/circuitdojo_feather_nrf9160.jpg diff --git a/boards/arm/circuitdojo_feather_nrf9160/doc/img/nrf9160-feather-v31-features.jpg b/boards/circuit_dojo/feather/doc/img/nrf9160-feather-v31-features.jpg similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/doc/img/nrf9160-feather-v31-features.jpg rename to boards/circuit_dojo/feather/doc/img/nrf9160-feather-v31-features.jpg diff --git a/boards/circuit_dojo/feather/doc/index.rst b/boards/circuit_dojo/feather/doc/index.rst new file mode 100644 index 00000000000000..0dd9bac2edd9db --- /dev/null +++ b/boards/circuit_dojo/feather/doc/index.rst @@ -0,0 +1,161 @@ +.. _circuitdojo_feather_nrf9160: + +nRF9160 Feather +############### + +.. figure:: img/circuitdojo_feather_nrf9160.jpg + :align: center + :alt: Circuit Dojo nRF9160 Feather + + nRF9160 Feather (Credit: Circuit Dojo) + +Overview +******** + +The nRF9160 Feather by Circuit Dojo is a single-board development +for bringing your LTE-M and NB-IoT applications to life. The circuitdojo_feather_nrf9160 +board configuration leverages the pre-existing support for the Nordic Semiconductor +nRF9160. Supported nRF9160 peripherals include: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9160 Feather Documentation`_. + + +Hardware +******** + +.. figure:: img/nrf9160-feather-v31-features.jpg + :align: center + :alt: nRF9160 Feather Features + +Connections and IOs +=================== + +The nRF9160 Feather has everything you know and love about +the Feather platform. Here are some of the highlights: + +LED +--- + +* D7 (blue) = P0.03 + +Push buttons and Switches +------------------------- + +* MODE = P0.12 +* RESET + +USB +--- + +Contains a USB/UART connection for both debugging and loading new +code using a UART Enabled MCUBoot. + +Standard Battery Connection +---------------------------- + +The nRF9160 Feather has a 2 pin battery connector on board. Lithium Polymer batteries > +300mA required. + +Nano SIM Holder +--------------- + +The nRF9160 Feather has a built-in nano SIM (4FF) holder located +on the bottom side. + + +Programming and Debugging +************************* + +circuitdojo_feather_nrf9160 has a Tag Connect TC2030-CTX-NL. It can be used +by most programmers like: + +* J-Link (the nRF53-DK is recommended) +* CMSIS-DAP based programmers + +Check out `Getting Started`_ for more info. + +Building an application +======================= + +In most cases you'll want to use the ``ns`` target with any of the Zephyr +or Nordic based examples. + +.. note:: + Trusted Firmware-M (TF-M) and building the ``ns`` target is not supported for this board. + +Some of the examples do not use secure mode, so they do not require the +``ns`` suffix. A great example of this is the `hello_world` below. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ screen /dev/ 115200 + +Replace :code:`` with the port where the nRF9160 Feather +can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: circuitdojo_feather_nrf9160 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons on the nRF9160 Feather +*************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/circuit_dojo/feather/circuitdojo_feather_nrf9160_common.dtsi`. + +References +********** + +.. target-notes:: + +**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for +developing a great platform! + +.. _nRF9160 Feather Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html +.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/circuitdojo_feather_nrf9160/pre_dt_board.cmake b/boards/circuit_dojo/feather/pre_dt_board.cmake similarity index 100% rename from boards/arm/circuitdojo_feather_nrf9160/pre_dt_board.cmake rename to boards/circuit_dojo/feather/pre_dt_board.cmake diff --git a/boards/circuit_dojo/index.rst b/boards/circuit_dojo/index.rst new file mode 100644 index 00000000000000..63fe4f4a205c80 --- /dev/null +++ b/boards/circuit_dojo/index.rst @@ -0,0 +1,10 @@ +.. _boards-circuit-dojo: + +Circuit Dojo +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/common/openocd-nrf5.board.cmake b/boards/common/openocd-nrf5.board.cmake index 90ab5d32a4cf95..b87936288208d2 100644 --- a/boards/common/openocd-nrf5.board.cmake +++ b/boards/common/openocd-nrf5.board.cmake @@ -6,9 +6,14 @@ # # Boards which don't meet this convention can set this variable before # including this script. -if (NOT DEFINED OPENOCD_NRF5_SUBFAMILY) +if(NOT DEFINED OPENOCD_NRF5_SUBFAMILY) string(REGEX MATCH nrf5. OPENOCD_NRF5_SUBFAMILY "${BOARD}") + + if(HWMv2 AND "${OPENOCD_NRF5_SUBFAMILY}" STREQUAL "") + string(REGEX MATCH nrf5. OPENOCD_NRF5_SUBFAMILY "${BOARD_IDENTIFIER}") + endif() endif() + if("${OPENOCD_NRF5_SUBFAMILY}" STREQUAL "") message(FATAL_ERROR "Can't match nrf5 subfamily from BOARD name. " diff --git a/boards/contextual_electronics/abc/Kconfig b/boards/contextual_electronics/abc/Kconfig new file mode 100644 index 00000000000000..b6a9479723e7d9 --- /dev/null +++ b/boards/contextual_electronics/abc/Kconfig @@ -0,0 +1,10 @@ +# ABC board configuration + +# Copyright (c) 2020 Analog Life LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_CONTEXTUALELECTRONICS_ABC diff --git a/boards/contextual_electronics/abc/Kconfig.contextualelectronics_abc b/boards/contextual_electronics/abc/Kconfig.contextualelectronics_abc new file mode 100644 index 00000000000000..2dbfd946509b60 --- /dev/null +++ b/boards/contextual_electronics/abc/Kconfig.contextualelectronics_abc @@ -0,0 +1,7 @@ +# ABC board configuration + +# Copyright (c) 2020 Analog Life LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CONTEXTUALELECTRONICS_ABC + select SOC_NRF52840_QIAA diff --git a/boards/contextual_electronics/abc/Kconfig.defconfig b/boards/contextual_electronics/abc/Kconfig.defconfig new file mode 100644 index 00000000000000..8568f02c34bbe5 --- /dev/null +++ b/boards/contextual_electronics/abc/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52840 BLE Cell board configuration + +# Copyright (c) 2020 Bilal Wasim +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CONTEXTUALELECTRONICS_ABC + +config BT_CTLR + default BT + +endif # BOARD_CONTEXTUALELECTRONICS_ABC diff --git a/boards/contextual_electronics/abc/board.cmake b/boards/contextual_electronics/abc/board.cmake new file mode 100644 index 00000000000000..261663eef4e27a --- /dev/null +++ b/boards/contextual_electronics/abc/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(OPENOCD_NRF5_SUBFAMILY "nrf52") +board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +board_runner_args(pyocd "--target=nrf52840" "--frequency=4000000") +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/boards/contextual_electronics/abc/board.yml b/boards/contextual_electronics/abc/board.yml new file mode 100644 index 00000000000000..5c921f05256773 --- /dev/null +++ b/boards/contextual_electronics/abc/board.yml @@ -0,0 +1,5 @@ +board: + name: contextualelectronics_abc + vendor: contextualelectronics + socs: + - name: nrf52840 diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc-pinctrl.dtsi b/boards/contextual_electronics/abc/contextualelectronics_abc-pinctrl.dtsi similarity index 100% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc-pinctrl.dtsi rename to boards/contextual_electronics/abc/contextualelectronics_abc-pinctrl.dtsi diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc.dts b/boards/contextual_electronics/abc/contextualelectronics_abc.dts similarity index 100% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc.dts rename to boards/contextual_electronics/abc/contextualelectronics_abc.dts diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc.yaml b/boards/contextual_electronics/abc/contextualelectronics_abc.yaml similarity index 100% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc.yaml rename to boards/contextual_electronics/abc/contextualelectronics_abc.yaml diff --git a/boards/arm/contextualelectronics_abc/contextualelectronics_abc_defconfig b/boards/contextual_electronics/abc/contextualelectronics_abc_defconfig similarity index 75% rename from boards/arm/contextualelectronics_abc/contextualelectronics_abc_defconfig rename to boards/contextual_electronics/abc/contextualelectronics_abc_defconfig index fce1393698416b..2908364b9c5969 100644 --- a/boards/arm/contextualelectronics_abc/contextualelectronics_abc_defconfig +++ b/boards/contextual_electronics/abc/contextualelectronics_abc_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_CONTEXTELEC_ABC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/contextualelectronics_abc/doc/img/contextualelectronics_abc.jpg b/boards/contextual_electronics/abc/doc/img/contextualelectronics_abc.jpg similarity index 100% rename from boards/arm/contextualelectronics_abc/doc/img/contextualelectronics_abc.jpg rename to boards/contextual_electronics/abc/doc/img/contextualelectronics_abc.jpg diff --git a/boards/arm/contextualelectronics_abc/doc/index.rst b/boards/contextual_electronics/abc/doc/index.rst similarity index 100% rename from boards/arm/contextualelectronics_abc/doc/index.rst rename to boards/contextual_electronics/abc/doc/index.rst diff --git a/boards/arm/bl654_sensor_board/pre_dt_board.cmake b/boards/contextual_electronics/abc/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl654_sensor_board/pre_dt_board.cmake rename to boards/contextual_electronics/abc/pre_dt_board.cmake diff --git a/boards/contextual_electronics/index.rst b/boards/contextual_electronics/index.rst new file mode 100644 index 00000000000000..d8f51610c4a456 --- /dev/null +++ b/boards/contextual_electronics/index.rst @@ -0,0 +1,10 @@ +.. _boards-contextual-electronics: + +Contextual Electronics +###################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble b/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble new file mode 100644 index 00000000000000..450f6530657c97 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/Kconfig.cy8ckit_062_ble @@ -0,0 +1,10 @@ +# PSoC6 BLE Pioneer Kit configuration + +# Copyright (c) 2018 Cypress +# Copyright (c) 2020 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_062_BLE + select SOC_PART_NUMBER_CY8C6347BZI_BLD53 + select SOC_CY8C6347_M0 if BOARD_CY8CKIT_062_BLE_CY8C6347_M0 + select SOC_CY8C6347_M4 if BOARD_CY8CKIT_062_BLE_CY8C6347_M4 diff --git a/boards/cypress/cy8ckit_062_ble/board.cmake b/boards/cypress/cy8ckit_062_ble/board.cmake new file mode 100644 index 00000000000000..8a2483e4e8e755 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/board.cmake @@ -0,0 +1,15 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M0) + board_runner_args(jlink "--device=CY8C6xx7_CM0p" "--speed=2000") +elseif(CONFIG_BOARD_CY8CKIT_062_BLE_CY8C6347_M4) + board_runner_args(jlink "--device=CY8C6xx7_CM4" "--speed=2000") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/cypress/cy8ckit_062_ble/board.yml b/boards/cypress/cy8ckit_062_ble/board.yml new file mode 100644 index 00000000000000..f0b1325911a467 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/board.yml @@ -0,0 +1,11 @@ +board: + name: cy8ckit_062_ble + vendor: cypress + revision: + format: "major.minor.patch" + default: "0.0.0" + revisions: + - name: "0.0.0" + - name: "1.0.0" + socs: + - name: cy8c6347 diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_common.dtsi diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0.dts rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0.dts diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_0_0_0.overlay rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml new file mode 100644 index 00000000000000..311c88f58acbfa --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m0 +name: Cypress PSoC6 BLE Pioneer Kit (M0) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - arduino_spi + - gpio + - spi +vendor: cypress diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m0_1_0_0.overlay rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml new file mode 100644 index 00000000000000..c3bcfac49c5188 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m0 +name: Cypress PSoC6 BLE Pioneer Kit (M0) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - arduino_spi + - gpio + - spi +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig new file mode 100644 index 00000000000000..fefeed4980f7a6 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4.dts rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts diff --git a/boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay similarity index 100% rename from boards/arm/cy8ckit_062_ble/cy8ckit_062_ble_m4_0_0_0.overlay rename to boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml new file mode 100644 index 00000000000000..ba22e8aa624b3a --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@0.0.0/cy8c6347/m4 +name: Cypress PSoC6 BLE Pioneer Kit (M4) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml new file mode 100644 index 00000000000000..bd4a3affce9f29 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020-2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_ble@1.0.0/cy8c6347/m4 +name: Cypress PSoC6 BLE Pioneer Kit (M4) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_gpio + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig new file mode 100644 index 00000000000000..fefeed4980f7a6 --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg b/boards/cypress/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg similarity index 100% rename from boards/arm/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg rename to boards/cypress/cy8ckit_062_ble/doc/img/cy8ckit-062-ble.jpg diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst new file mode 100644 index 00000000000000..155f94f7b032fa --- /dev/null +++ b/boards/cypress/cy8ckit_062_ble/doc/index.rst @@ -0,0 +1,305 @@ +.. _cy8ckit_062_ble: + +INFINEON PSoC63 BLE Pioneer Kit +############################### + +Overview +******** + +The PSoC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that +enables design and debug of the Cypress PSoC 63 BLE MCU. + +The PSoC 6 BLE Pioneer Kit features the PSoC 63 MCU: a dual-core MCU, with a +150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm +Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM, +an integrated BLE 4.2 radio, 78 GPIO, 7 programmable analog blocks, 12 +programmable digital blocks, and capacitive-sensing with CapSense. + +The PSoC 6 BLE Pioneer board offers compatibility with Arduino shields, a +512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power +delivery system (EZ-PD™ CCG3), 5-segment CapSense slider, two CapSense +buttons, one CapSense proximity sensing header, an RGB LED, two user LEDs, +and one push button. + +The CY8CKIT-062-BLE package includes a CY8CKIT-028-EPD E-INK Display Shield +that contains a 2.7-inch E-INK display, a motion sensor, a thermistor, and a +PDM microphone. The kit package also contains a CY5677 CySmart BLE 4.2 USB +Dongle that is factory-programmed to emulate a BLE GAP Central device, +enabling you to emulate a BLE host on your computer. + +The Cortex-M0+ is a primary core on the board's SoC. It starts first and +enables the CM4 core. + +.. image:: img/cy8ckit-062-ble.jpg + :align: center + :alt: CY8CKIT_062_BLE + +1. Battery charging indicator (LED6) +2. USB PD output voltage availability indicator (LED7) +3. KitProg2 USB Type-C connector (J10) +4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) +5. KitProg2 programming mode selection button (SW3) +6. KitProg2 I/O header (J6)1 +7. KitProg2 programming/custom application header (J7)1 +8. External power supply connector (J9) +9. PSoC 6 BLE user button (SW2) +10. KitProg2 application selection button (SW4) +11. Digilent® Pmod™ compatible I/O header (J14)1 +12. Power LED (LED4) +13. KitProg2 status LEDs (LED1, LED2, and LED3) +14. PSoC 6 reset button (SW1) +15. PSoC 6 I/O header (J18, J19 and J20) +16. Arduino™ Uno R3 compatible power header (J1) +17. PSoC 6 debug and trace header (J12) +18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) +19. PSoC 6 program and debug header (J11) +20. KitProg2 programming target selection switch (SW6) +21. CapSense slider and buttons +22. CapSense proximity header (J13) +23. PSoC 6 BLE VDD selection switch (SW5) +24. PSoC 6 BLE power monitoring jumper (J8)2 +25. Arduino Uno R3 compatible ICSP header (J5)1 +26. PSoC 6 user LEDs (LED8 and LED9) +27. RGB LED (LED5) +28. Cypress 512-Mbit serial NOR Flash memory (S25FL512S, U4) +29. Cypress serial Ferroelectric RAM (U5)1 +30. VBACKUP and PMIC control selection switch (SW7)2 +31. Cypress PSoC 6 BLE (CY8C6347BZI-BLD53, U1) +32. BLE Antenna +33. U.FL connector for external antenna (J17)1 +34. Cypress main voltage regulator (MB39C022G, U6) +35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) +36. Battery connector (J15)1,2 +37. USB PD output voltage (9V/12V) connector (J16) + +Hardware +******** + +For more information about the PSoC 63 BLE MCU SoC and CY8CKIT-062-BLE board: + +- `PSoC 63 BLE MCU SoC Website`_ +- `PSoC 63 BLE MCU Datasheet`_ +- `PSoC 63 BLE MCU Architecture Reference Manual`_ +- `PSoC 63 BLE MCU Register Reference Manual`_ +- `CY8CKIT-062-BLE Website`_ +- `CY8CKIT-062-BLE User Guide`_ +- `CY8CKIT-062-BLE Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| SPI | on-chip | spi | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + + +The default configurations can be found in the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig` for +Cortex-M0+ and on the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig` for +Cortex-M4 + +System Clock +============ + +The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + +Serial Port +=========== + +The PSoC 63 BLE MCU SoC has 8 SCB blocks and each one can be configured as +UART/SPI/I2C interfaces for serial communication. At the moment UART5 on SCB5 +and UART6 on SCB6 are configured. SCB5 is connected to the onboard KitProg2's +USB-UART Bridge working as a serial console interface. SCB6 to P13_0, P13_1 +pins on the J3 of the Arduino Uno R3 compatible PSoC6 I/O header for general +purposes. + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + +Programming and Debugging +************************* + +The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. There are also PSoC 6 program and debug headers J11 +and J12 that can be used with Segger J-Link [default]. +A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and +Cy_WDT_Disable(). + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble/cy8c6347/m0 + :goals: build + :compact: + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble/cy8c6347/m0 + :goals: flash + :compact: + + You should see "Hello World! cy8ckit_062_ble" in your terminal. + +Running on Dual Core +******************** + +#. Build the Zephyr kernel and the :zephyr:code-sample:`button` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: cy8ckit_062_ble/cy8c6347/m4 + :goals: build + :compact: + +#. If you have a USB-Serial adapter, you can connect SBC[UART]-6 on Arduino + header. Schematic should be checked for connections. Run your favorite + terminal program again now listen for another output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. To flash an image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: cy8ckit_062_ble/cy8c6347/m4 + :goals: flash + :compact: + +#. Configure Cortex-M0+ to enable Cortex-M4: + + The last step flash the M4 image on the flash. However, Cortex-M0 by default + doesn't start the M4 and nothing will happen. To enable Cortex-M4 CPU, + repeat the steps on programming and debug and add the following parameter + when performing the build process. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble/cy8c6347/m0 + :goals: build flash + :gen-args: -DCONFIG_SOC_PSOC6_M0_ENABLES_M4=y + :compact: + + Now you can press button SW-2 and see LED-9 blink at same time you have the + "Hello World! cy8ckit_062_ble" in the your terminal. + +Board Revision +************** + +The CY8CKIT-062-BLE KitProg2 shares connections with Arduino-R3 header. This +connections may not allow the correct use of shields. The default board +revision (0.0.0) allows use of default connections. The use of Arduino headers +are only possible after rework the board and using the revision 1.0.0. + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application for + board revision 1.0.0: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cy8ckit_062_ble@1.0.0/cy8c6347/m0 + :goals: build + :compact: + +#. The differences from version 0.0.0 to 1.0.0: + ++-------------+------------+------------+ +| Connection | 0.0.0 | 1.0.0 | ++=============+============+============+ +| CDC-COM RX | P5_0 | P9_0 | ++-------------+------------+------------+ +| CDC-COM TX | P5_1 | P9_1 | ++-------------+------------+------------+ +| R77 | X | | ++-------------+------------+------------+ +| R78 | | X | ++-------------+------------+------------+ + + +The P9 pins are available at J2. Those signals should be routed to J6. + +J2-2 to J6-14 +J2-4 to J6-13 + +The most complex part is short circuit pins 14 and 15 from U13. That connect +UART_RTS with UART_CTS from KitProg2. + +References +********** + +.. _PSoC 63 BLE MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-cortex-m0-psoc-63-connectivity-line + +.. _PSoC 63 BLE MCU Datasheet: + https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-63-ble-datasheet-programmable-system-chip-psoc + +.. _PSoC 63 BLE MCU Architecture Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-63-ble-architecture-technical-reference + +.. _PSoC 63 BLE MCU Register Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-cy8c63x6-cy8c63x7-cy8c63x6-cy8c63x7-registers + +.. _CY8CKIT-062-BLE Website: + https://www.cypress.com/documentation/development-kitsboards/psoc-6-ble-pioneer-kit-cy8ckit-062-ble + +.. _CY8CKIT-062-BLE User Guide: + https://www.cypress.com/file/390496/download + +.. _CY8CKIT-062-BLE Schematics: + https://www.cypress.com/file/417021/download diff --git a/boards/arm/cy8ckit_062_ble/support/openocd.cfg b/boards/cypress/cy8ckit_062_ble/support/openocd.cfg similarity index 100% rename from boards/arm/cy8ckit_062_ble/support/openocd.cfg rename to boards/cypress/cy8ckit_062_ble/support/openocd.cfg diff --git a/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt b/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt new file mode 100644 index 00000000000000..e77e648b62a23b --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/Kconfig.cy8ckit_062_wifi_bt @@ -0,0 +1,10 @@ +# PSoC6 WiFi-BT Pioneer Kit configuration + +# Copyright (c) 2018 Cypress +# Copyright (c) 2020 ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_062_WIFI_BT + select SOC_PART_NUMBER_CY8C6247BZI_D54 + select SOC_CY8C6247_M0 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M0 + select SOC_CY8C6247_M4 if BOARD_CY8CKIT_062_WIFI_BT_CY8C6247_M4 diff --git a/boards/arm/cy8ckit_062_wifi_bt/board.cmake b/boards/cypress/cy8ckit_062_wifi_bt/board.cmake similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/board.cmake rename to boards/cypress/cy8ckit_062_wifi_bt/board.cmake diff --git a/boards/cypress/cy8ckit_062_wifi_bt/board.yml b/boards/cypress/cy8ckit_062_wifi_bt/board.yml new file mode 100644 index 00000000000000..f5113e41a55bf6 --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8ckit_062_wifi_bt + vendor: cypress + socs: + - name: cy8c6247 diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m0.dts rename to boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.dts diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml new file mode 100644 index 00000000000000..3b2372a04dca1d --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_wifi_bt/cy8c6247/m0 +name: Cypress PSoC6 WiFi-BT Pioneer Kit (M0) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig new file mode 100644 index 00000000000000..fd9d1d319abcfa --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.dts b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_m4.dts rename to boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.dts diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml new file mode 100644 index 00000000000000..df5c8c0b53b9d3 --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: cy8ckit_062_wifi_bt/cy8c6247/m4 +name: Cypress PSoC6 WiFi-BT Pioneer Kit (M4) +type: mcu +arch: arm +ram: 288 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig new file mode 100644 index 00000000000000..fd9d1d319abcfa --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, Cypress +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_HEX=y + +# UART driver +CONFIG_SERIAL=y diff --git a/boards/arm/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg b/boards/cypress/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg rename to boards/cypress/cy8ckit_062_wifi_bt/doc/img/cy8ckit_062_wifi_bt_m0.jpg diff --git a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst new file mode 100644 index 00000000000000..d7e20c9bcb0cec --- /dev/null +++ b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst @@ -0,0 +1,208 @@ +.. _cy8ckit_062_wifi_bt: + +INFINEON PSoC6 WiFi-BT Pioneer Kit +################################## + +Overview +******** + +The PSoC 6 WiFi-BT Pioneer Kit (CY8CKIT-062-WiFi-BT) is a low-cost hardware +platform that enables design and debug of the PSoC 62 MCU and the Murata +LBEE5KL1DX Module (CYW4343W WiFi + Bluetooth Combo Chip). + +The PSoC 6 WiFi-BT Pioneer Kit features the PSoC 62 MCU: a +dual-core MCU, with a 150-MHz Arm Cortex-M4 as the primary application +processor and a 100-MHz Arm Cortex-M0+ that supports low-power operations, +1MB of Flash, 288KB of SRAM, 104 GPIO, 7 programmable analog blocks, +56 programmable digital blocks, Full-Speed USB, a serial memory interface, +a PDM-PCM digital microphone interface, and industry-leading capacitive-sensing +with CapSense. + +The PSoC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields. + +The Cortex-M0+ is a primary core on the board's SoC. It starts first and +enables the CM4 core. + +.. image:: img/cy8ckit_062_wifi_bt_m0.jpg + :align: center + :alt: CY8CKIT_062_WIFI_BT + +1. USB PD output voltage availability indicator (LED7) +2. Battery charging indicator (LED6) +3. KitProg2 USB Type-C connector (J10) +4. Cypress EZ-PD™ CCG3 Type-C Port Controller with PD (CYPD3125-40LQXI, U3) +5. KitProg2 programming mode selection button (SW3) +6. KitProg2 I/O header (J6)1 +7. KitProg2 programming/custom application header (J7)1 +8. External power supply connector (J9) +9. PSoC 6 user button (SW2) +10. KitProg2 application selection button (SW4) +11. Digilent® Pmod™ compatible I/O header (J14)1 +12. Power LED (LED4) +13. KitProg2 status LEDs (LED1, LED2, and LED3) +14. PSoC 6 reset button (SW1) +15. PSoC 6 I/O header (J18, J19 and J20) +16. Arduino™ Uno R3 compatible power header (J1) +17. PSoC 6 debug and trace header (J12) +18. Arduino Uno R3 compatible PSoC 6 I/O header (J2, J3 and J4) +19. PSoC 6 program and debug header (J11) +20. CapSense proximity header (J13) +21. CapSense slider and buttons +22. PSoC 6 VDD selection switch (SW5) +23. Cypress 512-Mbit serial NOR Flash memory (S25-FL512S, U4) +24. PSoC 6 user LEDs (LED8 and LED9) +25. RGB LED (LED5) +26. WiFi/BT module (LBEE5KL 1DX, U6) +27. Cypress serial Ferroelectric RAM (U5)1 +28. WiFi-BT Antenna +29. VBACKUP and PMIC control selection switch (SW7)2 +30. PSoC 6 USB device Type-C connector (J28) +31. Cypress PSoC 6 (CY8C6247BZI-D54, U1) +32. PSoC 6 USB Host Type-A connector (J27) +33. Arduino Uno R3 compatible ICSP header (J5)1 +34. PSoC 6 power monitoring jumper (J8)2 +35. KitProg2 (PSoC 5LP) programmer and debugger(CY8C5868LTI-LP039, U2) +36. Battery connector (J15)1,2 +37. USB PD output voltage (9V/12V) connector (J16) + +Hardware +******** + +For more information about the PSoC 62 MCU SoC and CY8CKIT-062-WiFi-BT board: + +- `PSoC 62 MCU SoC Website`_ +- `PSoC 62 MCU Datasheet`_ +- `PSoC 62 MCU Architecture Reference Manual`_ +- `PSoC 62 MCU Register Reference Manual`_ +- `CY8CKIT-062-WiFi-BT Website`_ +- `CY8CKIT-062-WiFi-BT User Guide`_ +- `CY8CKIT-062-WiFi-BT Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig`. + + +System Clock +============ + +The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + +Serial Port +=========== + +The PSoC 62 MCU SoC has 9 SCB blocks 8 of each can be configured as UART +interfaces for serial communication. At the moment UART5 on SCB5 and UART6 on +SCB6 are configured. SCB5 is connected to the onboard KitProg2's USB-UART +Bridge, SCB6 to P12_0, P12_1 pins on the J3 of the Arduino Uno R3 compatible +PSoC6 I/O header. + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + + +Programming and Debugging +************************* + +The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. There are also PSoC 6 program and debug headers J11 +and J12 that can be used with Segger J-Link. +A watchdog timer is enabled by default. To disable it call Cy_WDT_Unlock() and +Cy_WDT_Disable(). + +Only the CM0+ core starts by default after the MCU reset. In order to have +CM4 core working FW for both cores should be written into Flash. CM0+ FW +should starts the CM4 core at one point using +Cy_SysEnableCM4(CM4_START_ADDRESS); call. CM4_START_ADDRESS is 0x10060000 in +the current configuration. The CM0+/CM4 Flash/SRAM areas are defined in +:zephyr_file:`dts/arm/cypress/psoc6.dtsi`. + +Build the project for CM0+ + +.. zephyr-app-commands:: + :board: cy8ckit_062_wifi_bt/cy8c6247/m0 + :goals: build + +Switch the DevKit into CMSIS-DAP mode using SW3 (LED2 should blink) and flash +the board: + +.. code-block:: console + + $\bin\openocd -c "source [find interface/cmsis-dap.cfg]" \ + -c "transport select swd" -c "source [find target/psoc6.cfg]" \ + -c "if [catch {program {\samples\hello_world\build\zephyr\zephyr.elf}} ] \ + { echo {** Program operation failed **} } \ + else { echo {** Program operation completed successfully **} }" \ + -c "reset_config srst_only;reset run;psoc6.dap dpreg 0x04 0x00;shutdown" + +Switch the DevKit back using SW3. Open a serial terminal (minicom, putty, +etc.) and connect to the board with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and the following message will appear on the corresponding +serial port: + +.. code-block:: console + + ***** Booting Zephyr OS zephyr-v1.13.0-1877-g9d14874db1 ***** + Hello World! cy8ckit_062_wifi_bt + + +References +********** + +.. _PSoC 62 MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 + +.. _PSoC 62 MCU Datasheet: + https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary + +.. _PSoC 62 MCU Architecture Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual + +.. _PSoC 62 MCU Register Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm + +.. _CY8CKIT-062-WiFi-BT Website: + https://www.cypress.com/documentation/development-kitsboards/psoc-6-wifi-bt-pioneer-kit + +.. _CY8CKIT-062-WiFi-BT User Guide: + https://www.cypress.com/file/407731/download + +.. _CY8CKIT-062-WiFi-BT Schematics: + https://www.cypress.com/file/420846/download diff --git a/boards/arm/cy8ckit_062_wifi_bt/support/openocd.cfg b/boards/cypress/cy8ckit_062_wifi_bt/support/openocd.cfg similarity index 100% rename from boards/arm/cy8ckit_062_wifi_bt/support/openocd.cfg rename to boards/cypress/cy8ckit_062_wifi_bt/support/openocd.cfg diff --git a/boards/cypress/cy8ckit_062s4/Kconfig.cy8ckit_062s4 b/boards/cypress/cy8ckit_062s4/Kconfig.cy8ckit_062s4 new file mode 100644 index 00000000000000..db5e8c37451804 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/Kconfig.cy8ckit_062s4 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CKIT_062S4 + select SOC_CY8C6244LQI_S4D92 diff --git a/boards/arm/cy8ckit_062s4/board.cmake b/boards/cypress/cy8ckit_062s4/board.cmake similarity index 100% rename from boards/arm/cy8ckit_062s4/board.cmake rename to boards/cypress/cy8ckit_062s4/board.cmake diff --git a/boards/cypress/cy8ckit_062s4/board.yml b/boards/cypress/cy8ckit_062s4/board.yml new file mode 100644 index 00000000000000..adb45b87c07951 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8ckit_062s4 + vendor: cypress + socs: + - name: cy8c6244lqi_s4d92 diff --git a/boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.dts b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.dts similarity index 100% rename from boards/arm/cy8ckit_062s4/cy8ckit_062s4_m4.dts rename to boards/cypress/cy8ckit_062s4/cy8ckit_062s4.dts diff --git a/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.yaml b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.yaml new file mode 100644 index 00000000000000..aaa7d0c8305517 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4.yaml @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 David Ullmann + +identifier: cy8ckit_062s4 +name: CY8CKIT-062S4 PSoC 62S4 +type: mcu +arch: arm +ram: 128 +flash: 256 +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio +vendor: cypress diff --git a/boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig new file mode 100644 index 00000000000000..04b8a04dda6466 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2023 David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_PINCTRL=y + +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_XIP=y + +CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y diff --git a/boards/arm/cy8ckit_062s4/doc/img/cy8ckit_062s4.png b/boards/cypress/cy8ckit_062s4/doc/img/cy8ckit_062s4.png similarity index 100% rename from boards/arm/cy8ckit_062s4/doc/img/cy8ckit_062s4.png rename to boards/cypress/cy8ckit_062s4/doc/img/cy8ckit_062s4.png diff --git a/boards/cypress/cy8ckit_062s4/doc/index.rst b/boards/cypress/cy8ckit_062s4/doc/index.rst new file mode 100644 index 00000000000000..f3a026b3b6bc87 --- /dev/null +++ b/boards/cypress/cy8ckit_062s4/doc/index.rst @@ -0,0 +1,115 @@ +.. _cy8ckit_062s4: + +[INFINEON PSoC 62S4 Pioneer Kit] +################################ + +Overview +******** +The PSOC 62S4 Pioneer kit has a CY8C62x4 MCU, which is an ultra-low-power PSoC device specifically designed for battery-operated analog +sensing applications. It includes a 150-MHz Arm® Cortex®-M4 CPU as the primary application processor, a 100-MHz Arm® Cortex®-M0+ CPU that +supports low-power operations, up to 256 KB Flash and 128 KB SRAM, programmable analog sensing, +CapSense™ touch-sensing, and programmable digital peripherals. + +The board features an onboard +programmer/debugger (KitProg3), a 512-Mbit Quad SPI NOR flash, a micro-B connector for USB device +interface, a thermistor, an ambient light sensor, a 5-segment CapSense™ slider, two CapSense™ buttons, two +user LEDs, and a push button. The board supports operating voltages from 1.8 V to 3.3 V for PSoC™ 6 MCU. + +.. figure::img/cy8ckit_062s4.png + :width: 800px + :align: center + :alt: Board Name + + Board Name (Credit: ) + +Hardware +******** + +`CY8CKIT 062S4 Pioneer Kit Website`_ +`CY8CKIT 062S4 Pioneer Kit Guide`_ +`CY8CKIT 062S4 Pioneer Kit Schematic`_ +`CY8CKIT 062S4 Pioneer Kit Technical Reference Manual`_ +`CY8CKIT 062S4 Pioneer Kit Datasheet`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | ++-----------+------------+-----------------------+ + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/cypress/cy8ckit_062s4/cy8ckit_062s4_defconfig`. + +Clock Configuration +=================== + ++-----------+------------+-----------------------+ +| Clock | Source | Output Frequency | ++===========+============+=======================+ +| FLL | IMO | 100.0 MHz | ++-----------+------------+-----------------------+ +| PLL | IMO | 48.0 MHz | ++-----------+------------+-----------------------+ +| CLK_HF0 | CLK_PATH0 | 100.0 MHz | ++-----------+------------+-----------------------+ + +Fetch Binary Blobs +================== + +.. code-block:: console + + west blobs fetch hal_infineon + + +Build and flash hello world sample +********************************** + + +.. code-block:: console + + cd zephyr/samples/hello_world + west build -p auto -b cy8ckit_062s4 --pristine + west flash + picocom /dev/ttyACM0 -b 115200 + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + +References +********** + +.. _CY8CKIT 062S4 Pioneer Kit Guide: + https://www.infineon.com/dgdl/Infineon-CY8CKIT_062S4_PSoC62S4_pioneer_kit_guide-UserManual-v01_00-EN.pdf?fileId=8ac78c8c7e7124d1017e962f98992207 + +.. _CY8CKIT 062S4 Pioneer Kit Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8ckit-062s4/?redirId=VL1508&utm_medium=referral&utm_source=cypress&utm_campaign=202110_globe_en_all_integration-dev_kit + +.. _CY8CKIT 062S4 Pioneer Kit Schematic: + https://www.infineon.com/dgdl/Infineon-CY8CKIT-062S4_PSoC_62S4_Pioneer_Kit_Schematic-PCBDesignData-v01_00-EN.pdf?fileId=8ac78c8c7d710014017d7153484d2081 + +.. _CY8CKIT 062S4 Pioneer Kit Technical Reference Manual: + https://www.infineon.com/dgdl/Infineon-PSOC_6_MCU_CY8C61X4CY8C62X4_REGISTERS_TECHNICAL_REFERENCE_MANUAL_(TRM)_PSOC_61_PSOC_62_MCU-AdditionalTechnicalInformation-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0fb34f0627a7 + +.. _CY8CKIT 062S4 Pioneer Kit Datasheet: + https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_CY8C62X4-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7ddc01d7017ddd026d585901 diff --git a/boards/cypress/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w b/boards/cypress/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w new file mode 100644 index 00000000000000..6af485a6bed6c0 --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/Kconfig.cy8cproto_062_4343w @@ -0,0 +1,7 @@ +# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit + +# Copyright (c) 2021 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CPROTO_062_4343W + select SOC_CY8C624ABZI_S2D44 diff --git a/boards/cypress/cy8cproto_062_4343w/Kconfig.defconfig b/boards/cypress/cy8cproto_062_4343w/Kconfig.defconfig new file mode 100644 index 00000000000000..270370c7660152 --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/Kconfig.defconfig @@ -0,0 +1,54 @@ +# CY8CPROTO-062-4343W PSoC™ 6 Wi-Fi BT Prototyping Kit configuration + +# Copyright (c) 2021 Cypress Semiconductor Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CY8CPROTO_062_4343W + +if WIFI || BT + +# Select AIROC part and module +choice AIROC_PART + default CYW4343W +endchoice + +choice CYW4343W_MODULE + default CYW4343W_MURATA_1DX +endchoice + +endif # WIFI || BT + +if WIFI + +config WIFI_AIROC + default y + +# Enable L2 Ethernet +config NET_L2_ETHERNET + default y + +endif # WIFI + +if BT + +# Select HCI components +config UART + bool + default y + +config BT_UART + default y + +choice BT_HCI_BUS_TYPE + default BT_H4 +endchoice + +endif # BT + +# Heap Pool Size +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 15000 if WIFI + default 4096 + +endif # BOARD_CY8CPROTO_062_4343W diff --git a/boards/arm/cy8cproto_062_4343w/board.cmake b/boards/cypress/cy8cproto_062_4343w/board.cmake similarity index 100% rename from boards/arm/cy8cproto_062_4343w/board.cmake rename to boards/cypress/cy8cproto_062_4343w/board.cmake diff --git a/boards/cypress/cy8cproto_062_4343w/board.yml b/boards/cypress/cy8cproto_062_4343w/board.yml new file mode 100644 index 00000000000000..575dbf83414871 --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8cproto_062_4343w + vendor: cypress + socs: + - name: cy8c624abzi_s2d44 diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-common.dtsi diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w-pinctrl.dtsi diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.dts b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.dts similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.dts rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.dts diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml similarity index 100% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml diff --git a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig similarity index 84% rename from boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig rename to boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig index 3dd8e0eac78a01..19975610f6008b 100644 --- a/boards/arm/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig +++ b/boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig @@ -3,10 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 # -# Choice PSoC 6 Series and MPN -CONFIG_SOC_SERIES_PSOC_62=y -CONFIG_SOC_CY8C624ABZI_S2D44=y - # General configuration CONFIG_CORTEX_M_SYSTICK=y CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/cy8cproto_062_4343w/doc/img/board.jpg b/boards/cypress/cy8cproto_062_4343w/doc/img/board.jpg similarity index 100% rename from boards/arm/cy8cproto_062_4343w/doc/img/board.jpg rename to boards/cypress/cy8cproto_062_4343w/doc/img/board.jpg diff --git a/boards/cypress/cy8cproto_062_4343w/doc/index.rst b/boards/cypress/cy8cproto_062_4343w/doc/index.rst new file mode 100644 index 00000000000000..e1be366086c4ed --- /dev/null +++ b/boards/cypress/cy8cproto_062_4343w/doc/index.rst @@ -0,0 +1,184 @@ +.. _cy8cproto_062_4343w: + +INFINEON CY8CPROTO-062-4343W +############################ + +Overview +******** + +The CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Prototyping Kit is a low-cost hardware +platform that enables design and debug of PSoC 6 MCUs. It comes with a Murata +LBEE5KL1DX module, based on the CYW4343W combo device, industry-leading CAPSENSE +for touch buttons and slider, on-board debugger/programmer with KitProg3, microSD +card interface, 512-Mb Quad-SPI NOR flash, PDM-PCM microphone, and a thermistor. + +This kit is designed with a snap-away form-factor, allowing the user to separate +the different components and features that come with this kit and use independently. +In addition, support for Digilent's Pmod interface is also provided with this kit. + +.. image:: img/board.jpg + :align: center + :alt: CY8CPROTO-062-4343W + +Hardware +******** + +For more information about the PSoC 62 MCU SoC and CY8CPROTO-062-4343W board: + +- `PSoC 62 MCU SoC Website`_ +- `PSoC 62 MCU Datasheet`_ +- `PSoC 62 MCU Architecture Reference Manual`_ +- `PSoC 62 MCU Register Reference Manual`_ +- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website`_ +- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide`_ +- `CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics`_ + +Kit Features: +============= + +- Support of up to 2MB Flash and 1MB SRAM +- Dedicated SDHC to interface with WICED wireless devices. +- Delivers dual-cores, with a 150-MHz Arm Cortex-M4 as the primary + application processor and a 100-MHz Arm Cortex-M0+ as the secondary + processor for low-power operations. +- Supports Full-Speed USB, capacitive-sensing with CAPSENSE, a PDM-PCM + digital microphone interface, a Quad-SPI interface, 13 serial communication + blocks, 7 programmable analog blocks, and 56 programmable digital blocks. + +Kit Contents: +============= + +- PSoC 6 Wi-Fi BT Prototyping Board +- USB Type-A to Micro-B cable +- Quick Start Guide + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | GPIO | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ + + +The default configuration can be found in the Kconfig + +:zephyr_file:`boards/cypress/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig` + + +System Clock +============ + +The PSoC 62 MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + + +Fetch Binary Blobs +****************** + +cy8cproto_062_4343w board optionally uses binary blobs for features +(e.g WIFI/Bluetooth chip firmware, CM0p prebuilt images, etc). + +To fetch Binary Blobs: + +.. code-block:: console + + west blobs fetch hal_infineon + + +Build blinking led sample +************************* + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. code-block:: console + + cd zephyr + west build -p auto -b cy8cproto_062_4343w samples/basic/blink + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + + +Programming and Debugging +************************* + +The CY8CPROTO-062-4343W includes an onboard programmer/debugger (KitProg2) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. Flash and debug commands must be pointed to the Cypress +OpenOCD you downloaded above. + +On Windows: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd.exe + west debug --openocd path/to/infineon/openocd/bin/openocd.exe + +On Linux: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd + west debug --openocd path/to/infineon/openocd/bin/openocd + +Once the gdb console starts after executing the west debug command, you may +now set breakpoints and perform other standard GDB debugging on the PSoC 6 CM4 core. + +Errata +====== + ++------------------------------------------------+----------------------------------------+ +| Problem | Solution | ++================================================+========================================+ +| The GPIO_INT_TRIG_BOTH interrupt is not raised | This will be fixed in a future release.| +| when the associated GPIO is asserted. | | ++------------------------------------------------+----------------------------------------+ +| GDB experiences a timeout error connecting to | This will be fixed in a future release.| +| a server instance started by west debugserver. | | ++------------------------------------------------+----------------------------------------+ + +.. _PSoC 62 MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 + +.. _PSoC 62 MCU Datasheet: + https://www.cypress.com/documentation/datasheets/psoc-6-mcu-psoc-62-datasheet-programmable-system-chip-psoc-preliminary + +.. _PSoC 62 MCU Architecture Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-architecture-technical-reference-manual + +.. _PSoC 62 MCU Register Reference Manual: + https://www.cypress.com/documentation/technical-reference-manuals/psoc-6-mcu-psoc-62-register-technical-reference-manual-trm + +.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/ + +.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT User Guide: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f0118571844 + +.. _CY8CPROTO-062-4343W PSoC 6 Wi-Fi BT Schematics: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-062-4343w/#!?fileId=8ac78c8c7d0d8da4017d0f01126b183f + +.. _Infineon OpenOCD: + https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cy8cproto_062_4343w/support/openocd.cfg b/boards/cypress/cy8cproto_062_4343w/support/openocd.cfg similarity index 100% rename from boards/arm/cy8cproto_062_4343w/support/openocd.cfg rename to boards/cypress/cy8cproto_062_4343w/support/openocd.cfg diff --git a/boards/cypress/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble b/boards/cypress/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble new file mode 100644 index 00000000000000..23763f500c3d21 --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/Kconfig.cy8cproto_063_ble @@ -0,0 +1,8 @@ +# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit +# +# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CY8CPROTO_063_BLE + select SOC_CYBLE_416045_02 diff --git a/boards/cypress/cy8cproto_063_ble/Kconfig.defconfig b/boards/cypress/cy8cproto_063_ble/Kconfig.defconfig new file mode 100644 index 00000000000000..2d079f63a6b485 --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/Kconfig.defconfig @@ -0,0 +1,13 @@ +# CY8CPROTO-063-BLE PSoC™ 6 BLE Prototyping Kit + +# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CY8CPROTO_063_BLE + +choice BT_HCI_BUS_TYPE + default BT_PSOC6_BLESS if BT +endchoice + +endif # BOARD_CY8CPROTO_063_BLE diff --git a/boards/arm/cy8cproto_063_ble/board.cmake b/boards/cypress/cy8cproto_063_ble/board.cmake similarity index 100% rename from boards/arm/cy8cproto_063_ble/board.cmake rename to boards/cypress/cy8cproto_063_ble/board.cmake diff --git a/boards/cypress/cy8cproto_063_ble/board.yml b/boards/cypress/cy8cproto_063_ble/board.yml new file mode 100644 index 00000000000000..b35cb08ec2fcf6 --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/board.yml @@ -0,0 +1,5 @@ +board: + name: cy8cproto_063_ble + vendor: cypress + socs: + - name: cyble_416045_02 diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi similarity index 100% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble-pinctrl.dtsi diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.dts b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.dts similarity index 100% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.dts rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.dts diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.yaml b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.yaml similarity index 100% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble.yaml rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble.yaml diff --git a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig similarity index 89% rename from boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig rename to boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig index a3d7e7beab3033..17d512d195d92a 100644 --- a/boards/arm/cy8cproto_063_ble/cy8cproto_063_ble_defconfig +++ b/boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig @@ -4,10 +4,6 @@ # SPDX-Licence-Identifier: Apache-2.0 #*************************************************************************** -# Choice PSoC 6 Series and MPN -CONFIG_SOC_SERIES_PSOC_63=y -CONFIG_SOC_CYBLE_416045_02=y - # General configuration CONFIG_CORTEX_M_SYSTICK=y CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg b/boards/cypress/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg similarity index 100% rename from boards/arm/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg rename to boards/cypress/cy8cproto_063_ble/doc/img/cy8cproto-063-ble.jpg diff --git a/boards/cypress/cy8cproto_063_ble/doc/index.rst b/boards/cypress/cy8cproto_063_ble/doc/index.rst new file mode 100644 index 00000000000000..8ef38711c8f8ee --- /dev/null +++ b/boards/cypress/cy8cproto_063_ble/doc/index.rst @@ -0,0 +1,144 @@ +.. _cy8cproto_063_ble: + +INFINEON CY8CPROTO-063-BLE +########################### + +Overview +******** + +The PSoC 6 BLE Proto Kit (CY8CPROTO-063-BLE) is a hardware platform that +enables design and debug of the Cypress PSoC 63 BLE MCU. + +.. image:: img/cy8cproto-063-ble.jpg + :align: center + :alt: CY8CPROTO-063-BLE + +Hardware +******** + +For more information about the PSoC 63 BLE MCU SoC and CY8CPROTO-063-BLE board: + +- `PSoC 63 BLE MCU SoC Website`_ +- `PSoC 63 BLE MCU Datasheet`_ +- `PSoC 63 BLE MCU Architecture Reference Manual`_ +- `PSoC 63 BLE MCU Register Reference Manual`_ +- `CY8CPROTO-063-BLE Website`_ +- `CY8CPROTO-063-BLE User Guide`_ +- `CY8CPROTO-063-BLE Schematics`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| PINCTRL | on-chip | pin control | ++-----------+------------+-----------------------+ +| SPI | on-chip | spi | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-----------------------+ +| I2C | on-chip | I2C | ++-----------+------------+-----------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-----------------------+ +| Counter | on-chip | Counter | ++-----------+------------+-----------------------+ +| Bluetooth | on-chip | Bluetooth | ++-----------+------------+-----------------------+ + + +The default configurations can be found in +:zephyr_file:`boards/cypress/cy8cproto_063_ble/cy8cproto_063_ble_defconfig` + +System Clock +============ + +The PSoC 63 BLE MCU SoC is configured to use the internal IMO+FLL as a source for +the system clock. CM0+ works at 50MHz, CM4 - at 100MHz. Other sources for the +system clock are provided in the SOC, depending on your system requirements. + + +OpenOCD Installation +==================== + +To get the OpenOCD package, it is required that you + +1. Download the software ModusToolbox 3.1. https://softwaretools.infineon.com/tools/com.ifx.tb.tool.modustoolbox +2. Once downloaded add the path to access the Scripts folder provided by ModusToolbox + export PATH=$PATH:/path/to/ModusToolbox/tools_3.1/openocd/scripts +3. Add the OpenOCD executable file's path to west flash/debug. +4. Flash using: west flash --openocd path/to/infineon/openocd/bin/openocd +5. Debug using: west debug --openocd path/to/infineon/openocd/bin/openocd + + +Fetch Binary Blobs +****************** + +cy8cproto_063_ble board requires fetch binary files +(e.g Bluetooth controller firmware, CM0p prebuilt images, etc). + +To fetch Binary Blobs: + +.. code-block:: console + + west blobs fetch hal_infineon + +Programming and Debugging +************************* + +The CY8CPROTO-063-BLE includes an onboard programmer/debugger (KitProg3) with +mass storage programming to provide debugging, flash programming, and serial +communication over USB. Flash and debug commands must be pointed to the Cypress +OpenOCD you downloaded above. + +On Windows: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd.exe + west debug --openocd path/to/infineon/openocd/bin/openocd.exe + +On Linux: + +.. code-block:: console + + west flash --openocd path/to/infineon/openocd/bin/openocd + west debug --openocd path/to/infineon/openocd/bin/openocd + +References +********** + +.. _PSoC 63 BLE MCU SoC Website: + https://www.cypress.com/products/32-bit-arm-cortex-m4-psoc-6 + +.. _PSoC 63 BLE MCU Datasheet: + https://www.infineon.com/dgdl/Infineon-PSoC_6_MCU_PSoC_63_with_BLE_Datasheet_Programmable_System-on-Chip_(PSoC)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee4efe46c37&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files + +.. _PSoC 63 BLE MCU Architecture Reference Manual: + https://documentation.infineon.com/html/psoc6/zrs1651212645947.html + +.. _PSoC 63 BLE MCU Register Reference Manual: + https://documentation.infineon.com/html/psoc6/bnm1651211483724.html + +.. _CY8CPROTO-063-BLE Website: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/ + +.. _CY8CPROTO-063-BLE User Guide: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00d7eb1812 + +.. _CY8CPROTO-063-BLE Schematics: + https://www.infineon.com/cms/en/product/evaluation-boards/cy8cproto-063-ble/#!?fileId=8ac78c8c7d0d8da4017d0f00ea3c1821 + +.. _Infineon OpenOCD: + https://github.com/infineon/openocd/releases/tag/release-v4.3.0 diff --git a/boards/arm/cy8cproto_063_ble/support/openocd.cfg b/boards/cypress/cy8cproto_063_ble/support/openocd.cfg similarity index 100% rename from boards/arm/cy8cproto_063_ble/support/openocd.cfg rename to boards/cypress/cy8cproto_063_ble/support/openocd.cfg diff --git a/boards/cypress/index.rst b/boards/cypress/index.rst new file mode 100644 index 00000000000000..571b8c69b684c6 --- /dev/null +++ b/boards/cypress/index.rst @@ -0,0 +1,10 @@ +.. _boards-cypress: + +Cypress +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake index 270d5f5e1a9273..43334da2a33366 100644 --- a/boards/deprecated.cmake +++ b/boards/deprecated.cmake @@ -8,4 +8,861 @@ # To add a board rename, add a line in following format: # set(_DEPRECATED ) -set(esp32_DEPRECATED esp32_devkitc_wrover) +set(96b_carbon_DEPRECATED + 96b_carbon/stm32f401xe +) +set(96b_carbon_nrf51_DEPRECATED + 96b_carbon/nrf51822 +) +set(96b_meerkat96_DEPRECATED + 96b_meerkat96/mcimx7d/m4 +) +set(actinius_icarus_bee_ns_DEPRECATED + actinius_icarus_bee/nrf9160/ns +) +set(actinius_icarus_ns_DEPRECATED + actinius_icarus/nrf9160/ns +) +set(actinius_icarus_som_dk_ns_DEPRECATED + actinius_icarus_som_dk/nrf9160/ns +) +set(actinius_icarus_som_ns_DEPRECATED + actinius_icarus_som/nrf9160/ns +) +set(adafruit_feather_nrf52840_DEPRECATED + adafruit_feather +) +set(adafruit_itsybitsy_nrf52840_DEPRECATED + adafruit_itsybitsy +) +set(adp_xc7k_ae350_DEPRECATED + adp_xc7k +) +set(am62x_m4_phyboard_lyra_DEPRECATED + phyboard_lyra_am62x/am6234/m4 +) +set(am62x_m4_sk_DEPRECATED + sk_am62/am6234/m4 +) +set(arduino_giga_r1_m4_DEPRECATED + arduino_giga_r1/stm32h747xx/m4 +) +set(arduino_giga_r1_m7_DEPRECATED + arduino_giga_r1/stm32h747xx/m7 +) +set(arduino_nano_33_ble_sense_DEPRECATED + arduino_nano_33_ble/nrf52840/sense +) +set(arduino_opta_m4_DEPRECATED + arduino_opta/stm32h747xx/m4 +) +set(arduino_portenta_h7_m4_DEPRECATED + arduino_portenta_h7/stm32h747xx/m4 +) +set(arduino_portenta_h7_m7_DEPRECATED + arduino_portenta_h7/stm32h747xx/m7 +) +set(arty_a7_arm_designstart_m1_DEPRECATED + arty_a7/designstart_fpga_cortex_m1 +) +set(arty_a7_arm_designstart_m3_DEPRECATED + arty_a7/designstart_fpga_cortex_m3 +) +set(atsamc21n_xpro_DEPRECATED + samc21n_xpro +) +set(atsamd20_xpro_DEPRECATED + samd20_xpro +) +set(atsamd21_xpro_DEPRECATED + samd21_xpro +) +set(atsame54_xpro_DEPRECATED + same54_xpro +) +set(atsaml21_xpro_DEPRECATED + saml21_xpro +) +set(atsamr21_xpro_DEPRECATED + samr21_xpro +) +set(atsamr34_xpro_DEPRECATED + samr34_xpro +) +set(b_u585i_iot02a_ns_DEPRECATED + b_u585i_iot02a/stm32u585xx/ns +) +set(bcm958402m2_a72_DEPRECATED + bcm958402m2/bcm58402/a72 +) +set(bcm958402m2_m7_DEPRECATED + bcm958402m2/bcm58402/m7 +) +set(bl5340_dvk_cpuapp_DEPRECATED + bl5340_dvk/nrf5340/cpuapp +) +set(bl5340_dvk_cpuapp_ns_DEPRECATED + bl5340_dvk/nrf5340/cpuapp/ns +) +set(bl5340_dvk_cpunet_DEPRECATED + bl5340_dvk/nrf5340/cpunet +) +set(blueclover_plt_demo_v2_nrf52832_DEPRECATED + blueclover_plt_demo_v2 +) +set(circuitdojo_feather_nrf9160_DEPRECATED + circuitdojo_feather +) +set(circuitdojo_feather_nrf9160_ns_DEPRECATED + circuitdojo_feather/nrf9160/ns +) +set(colibri_imx7d_m4_DEPRECATED + colibri_imx7d/mcimx7d/m4 +) +set(cy8ckit_062_ble_m0_DEPRECATED + cy8ckit_062_ble/cy8c6347/m0 +) +set(cy8ckit_062_ble_m4_DEPRECATED + cy8ckit_062_ble/cy8c6347/m4 +) +set(cy8ckit_062_wifi_bt_m0_DEPRECATED + cy8ckit_062_wifi_bt/cy8c6247/m0 +) +set(cy8ckit_062_wifi_bt_m4_DEPRECATED + cy8ckit_062_wifi_bt/cy8c6247/m4 +) +set(cy8ckit_062s4_m4_DEPRECATED + cy8ckit_062s4 +) +set(ebyte_e73_tbb_nrf52832_DEPRECATED + ebyte_e73_tbb +) +set(efm32pg_stk3402a_DEPRECATED + efm32pg_stk3402a/efm32pg12b500f1024gl125 +) +set(efm32pg_stk3402a_jg_DEPRECATED + efm32pg_stk3402a/efm32jg12b500f1024gl125 +) +set(efr32_radio_brd4104a_DEPRECATED + efr32_radio/efr32bg13p632f512gm48 +) +set(efr32_radio_brd4161a_DEPRECATED + efr32_radio/efr32mg12p432f1024gl125 +) +set(efr32_radio_brd4170a_DEPRECATED + efr32_radio/efr32mg12p433f1024gm68 +) +set(efr32_radio_brd4180a_DEPRECATED + efr32_radio/efr32mg21a020f1024im32 +) +set(efr32_radio_brd4187c_DEPRECATED + efr32_radio/efr32mg24b220f1536im48 +) +set(efr32_radio_brd4250b_DEPRECATED + efr32_radio/efr32fg1p133f256gm48 +) +set(efr32_radio_brd4255a_DEPRECATED + efr32_radio/efr32fg13p233f512gm48 +) +set(em_starterkit_DEPRECATED + em_starterkit/emsk_em9d +) +set(em_starterkit_em11d_DEPRECATED + em_starterkit@2.3/emsk_em11d +) +set(em_starterkit_em7d_DEPRECATED + em_starterkit@2.3/emsk_em7d +) +set(em_starterkit_em7d_v22_DEPRECATED + em_starterkit@2.2/emsk_em7d +) +set(emsdp_DEPRECATED + emsdp/emsdp_em11d +) +set(emsdp_em4_DEPRECATED + emsdp/emsdp_em4 +) +set(emsdp_em5d_DEPRECATED + emsdp/emsdp_em5d +) +set(emsdp_em6_DEPRECATED + emsdp/emsdp_em6 +) +set(emsdp_em7d_DEPRECATED + emsdp/emsdp_em7d +) +set(emsdp_em7d_esp_DEPRECATED + emsdp/emsdp_em7d_esp +) +set(emsdp_em9d_DEPRECATED + emsdp/emsdp_em9d +) +set(esp32_DEPRECATED + esp32_devkitc_wrover/esp32/procpu +) +set(esp32_devkitc_wroom_DEPRECATED + esp32_devkitc_wroom/esp32/procpu +) +set(esp32_devkitc_wroom_appcpu_DEPRECATED + esp32_devkitc_wroom/esp32/appcpu +) +set(esp32_devkitc_wrover_DEPRECATED + esp32_devkitc_wrover/esp32/procpu +) +set(esp32_devkitc_wrover_appcpu_DEPRECATED + esp32_devkitc_wrover/esp32/appcpu +) +set(esp32_ethernet_kit_DEPRECATED + esp32_ethernet_kit/esp32/procpu +) +set(esp32c3_luatos_core_usb_DEPRECATED + esp32c3_luatos_core/esp32c3/usb +) +set(esp32s3_devkitm_DEPRECATED + esp32s3_devkitm/esp32s3/procpu +) +set(esp32s3_devkitm_appcpu_DEPRECATED + esp32s3_devkitm/esp32s3/appcpu +) +set(esp32s3_luatos_core_DEPRECATED + esp32s3_luatos_core/esp32s3/procpu +) +set(esp32s3_luatos_core_usb_DEPRECATED + esp32s3_luatos_core/esp32s3/procpu/usb +) +set(esp_wrover_kit_DEPRECATED + esp_wrover_kit/esp32/procpu +) +set(fvp_base_revc_2xaemv8a_smp_ns_DEPRECATED + fvp_base_revc_2xaemv8a/fvp_base_revc_2xaemv8a/smp/ns +) +set(fvp_baser_aemv8r_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch64 +) +set(fvp_baser_aemv8r_aarch32_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch32 +) +set(fvp_baser_aemv8r_aarch32_smp_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch32/smp +) +set(fvp_baser_aemv8r_smp_DEPRECATED + fvp_baser_aemv8r/fvp_aemv8r_aarch64/smp +) +set(heltec_wifi_lora32_v2_DEPRECATED + heltec_wifi_lora32_v2/esp32/procpu +) +set(heltec_wireless_stick_lite_v3_DEPRECATED + heltec_wireless_stick_lite_v3/esp32s3/procpu +) +set(hexiwear_k64_DEPRECATED + hexiwear/mk64f12 +) +set(hexiwear_kw40z_DEPRECATED + hexiwear/mkw40z4 +) +set(hifive1_revb_DEPRECATED + hifive1@B +) +set(hsdk_2cores_DEPRECATED + hsdk/arc_hsdk/2cores +) +set(intel_adsp_ace15_mtpm_DEPRECATED + intel_adsp/ace15_mtpm +) +set(intel_adsp_ace20_lnl_DEPRECATED + intel_adsp/ace20_lnl +) +set(intel_adsp_cavs25_DEPRECATED + intel_adsp/cavs25 +) +set(intel_adsp_cavs25_tgph_DEPRECATED + intel_adsp/cavs25/tgph +) +set(intel_ehl_crb_sbl_DEPRECATED + intel_ehl_crb/elkhart_lake/sbl +) +set(kincony_kc868_a32_DEPRECATED + kincony_kc868_a32/esp32/procpu +) +set(longan_nano_lite_DEPRECATED + longan_nano/gd32vf103/lite +) +set(lpcxpresso54114_m0_DEPRECATED + lpcxpresso54114/lpc54114/m0 +) +set(lpcxpresso54114_m4_DEPRECATED + lpcxpresso54114/lpc54114/m4 +) +set(lpcxpresso55s69_cpu0_DEPRECATED + lpcxpresso55s69/lpc55s69/cpu0 +) +set(lpcxpresso55s69_cpu1_DEPRECATED + lpcxpresso55s69/lpc55s69/cpu1 +) +set(lpcxpresso55s69_ns_DEPRECATED + lpcxpresso55s69/lpc55s69/cpu0/ns +) +set(m5stack_atoms3_DEPRECATED + m5stack_atoms3/esp32s3/procpu +) +set(m5stack_atoms3_lite_DEPRECATED + m5stack_atoms3_lite/esp32s3/procpu +) +set(m5stack_core2_DEPRECATED + m5stack_core2/esp32/procpu +) +set(m5stack_stamps3_DEPRECATED + m5stack_stamps3/esp32s3/procpu +) +set(m5stickc_plus_DEPRECATED + m5stickc_plus/esp32/procpu +) +set(mimx8mm_evk_DEPRECATED + imx8mm_evk/mimx8mm6/m4 +) +set(mimx8mm_evk_a53_DEPRECATED + imx8mm_evk/mimx8mm6/a53 +) +set(mimx8mm_evk_a53_smp_DEPRECATED + imx8mm_evk/mimx8mm6/a53/smp +) +set(mimx8mm_phyboard_polis_DEPRECATED + mimx8mm_phyboard_polis/mimx8mm6/m4 +) +set(mimx8mn_evk_a53_DEPRECATED + imx8mn_evk/mimx8mn6/a53 +) +set(mimx8mn_evk_a53_smp_DEPRECATED + imx8mn_evk/mimx8mn6/a53/smp +) +set(mimx8mp_evk_a53_DEPRECATED + imx8mp_evk/mimx8ml8/a53 +) +set(mimx8mp_evk_a53_smp_DEPRECATED + imx8mp_evk/mimx8ml8/a53/smp +) +set(mimx8mp_evk_ddr_DEPRECATED + imx8mp_evk/mimx8ml8/m7/ddr +) +set(mimx8mp_evk_itcm_DEPRECATED + imx8mp_evk/mimx8ml8/m7 +) +set(mimx8mp_phyboard_pollux_DEPRECATED + mimx8mp_phyboard_pollux/mimx8ml8/m7 +) +set(mimx8mq_evk_cm4_DEPRECATED + imx8mq_evk/mimx8mq6/m4 +) +set(mimx93_evk_a55_DEPRECATED + imx93_evk/mimx9352/a55 +) +set(mimxrt1050_evk_qspi_DEPRECATED + mimxrt1050_evk@qspi +) +set(mimxrt1060_evk_hyperflash_DEPRECATED + mimxrt1060_evk@hyperflash +) +set(mimxrt1160_evk_cm4_DEPRECATED + mimxrt1160_evk/mimxrt1166/cm4 +) +set(mimxrt1160_evk_cm7_DEPRECATED + mimxrt1160_evk/mimxrt1166/cm7 +) +set(mimxrt1170_evk_cm4_DEPRECATED + mimxrt1170_evk@A/mimxrt1176/cm4 +) +set(mimxrt1170_evk_cm7_DEPRECATED + mimxrt1170_evk@A/mimxrt1176/cm7 +) +set(mimxrt1170_evkb_cm4_DEPRECATED + mimxrt1170_evk@B/mimxrt1176/cm4 +) +set(mimxrt1170_evkb_cm7_DEPRECATED + mimxrt1170_evk@B/mimxrt1176/cm7 +) +set(mimxrt595_evk_cm33_DEPRECATED + mimxrt595_evk/mimxrt595s/cm33 +) +set(mimxrt685_evk_cm33_DEPRECATED + mimxrt685_evk +) +set(mps2_an385_DEPRECATED + mps2/an385 +) +set(mps2_an521_DEPRECATED + mps2/an521/cpu0 +) +set(mps2_an521_ns_DEPRECATED + mps2/an521/cpu0/ns +) +set(mps2_an521_remote_DEPRECATED + mps2/an521/cpu1 +) +set(mps3_an547_DEPRECATED + mps3 +) +set(mps3_an547_ns_DEPRECATED + mps3/an547/ns +) +set(nrf21540dk_nrf52840_DEPRECATED + nrf21540dk +) +set(nrf51dk_nrf51422_DEPRECATED + nrf51dk +) +set(nrf51dongle_nrf51422_DEPRECATED + nrf51dongle +) +set(nrf52833dk_nrf52820_DEPRECATED + nrf52833dk/nrf52820 +) +set(nrf52833dk_nrf52833_DEPRECATED + nrf52833dk/nrf52833 +) +set(nrf52840dk_nrf52811_DEPRECATED + nrf52840dk/nrf52811 +) +set(nrf52840dk_nrf52840_DEPRECATED + nrf52840dk/nrf52840 +) +set(nrf52840dongle_nrf52840_DEPRECATED + nrf52840dongle +) +set(nrf52dk_nrf52805_DEPRECATED + nrf52dk/nrf52805 +) +set(nrf52dk_nrf52810_DEPRECATED + nrf52dk/nrf52810 +) +set(nrf52dk_nrf52832_DEPRECATED + nrf52dk/nrf52832 +) +set(nrf5340_audio_dk_nrf5340_cpuapp_DEPRECATED + nrf5340_audio_dk/nrf5340/cpuapp +) +set(nrf5340_audio_dk_nrf5340_cpuapp_ns_DEPRECATED + nrf5340_audio_dk/nrf5340/cpuapp/ns +) +set(nrf5340_audio_dk_nrf5340_cpunet_DEPRECATED + nrf5340_audio_dk/nrf5340/cpunet +) +set(nrf5340dk_nrf5340_cpuapp_DEPRECATED + nrf5340dk/nrf5340/cpuapp +) +set(nrf5340dk_nrf5340_cpuapp_ns_DEPRECATED + nrf5340dk/nrf5340/cpuapp/ns +) +set(nrf5340dk_nrf5340_cpunet_DEPRECATED + nrf5340dk/nrf5340/cpunet +) +set(nrf54h20pdk_nrf54h20_cpuapp_DEPRECATED + nrf54h20pdk/nrf54h20/cpuapp +) +set(nrf54h20pdk_nrf54h20_cpuppr_DEPRECATED + nrf54h20pdk/nrf54h20/cpuppr +) +set(nrf54h20pdk_nrf54h20_cpurad_DEPRECATED + nrf54h20pdk/nrf54h20/cpurad +) +set(nrf54l15pdk_nrf54l15_cpuapp_DEPRECATED + nrf54l15pdk/nrf54l15/cpuapp +) +set(nrf9131ek_nrf9131_DEPRECATED + nrf9131ek +) +set(nrf9131ek_nrf9131_ns_DEPRECATED + nrf9131ek/nrf9131/ns +) +set(nrf9151dk_nrf9151_DEPRECATED + nrf9151dk +) +set(nrf9151dk_nrf9151_ns_DEPRECATED + nrf9151dk/nrf9151/ns +) +set(nrf9160_innblue21_DEPRECATED + innblue21 +) +set(nrf9160_innblue21_ns_DEPRECATED + innblue21/nrf9160/ns +) +set(nrf9160_innblue22_DEPRECATED + innblue22 +) +set(nrf9160_innblue22_ns_DEPRECATED + innblue22/nrf9160/ns +) +set(nrf9160dk_nrf52840_DEPRECATED + nrf9160dk/nrf52840 +) +set(nrf9160dk_nrf9160_DEPRECATED + nrf9160dk/nrf9160 +) +set(nrf9160dk_nrf9160_ns_DEPRECATED + nrf9160dk/nrf9160/ns +) +set(nrf9161dk_nrf9161_DEPRECATED + nrf9161dk +) +set(nrf9161dk_nrf9161_ns_DEPRECATED + nrf9161dk/nrf9161/ns +) +set(nsim_em_DEPRECATED + nsim/nsim_em +) +set(nsim_em11d_DEPRECATED + nsim/nsim_em11d +) +set(nsim_em7d_v22_DEPRECATED + nsim/nsim_em7d_v22 +) +set(nsim_hs_DEPRECATED + nsim/nsim_hs +) +set(nsim_hs3x_hostlink_DEPRECATED + nsim/nsim_hs/hostlink +) +set(nsim_hs5x_DEPRECATED + nsim/nsim_hs5x +) +set(nsim_hs5x_smp_DEPRECATED + nsim/nsim_hs5x/smp +) +set(nsim_hs5x_smp_12cores_DEPRECATED + nsim/nsim_hs5x/smp/12cores +) +set(nsim_hs6x_DEPRECATED + nsim/nsim_hs6x +) +set(nsim_hs6x_smp_DEPRECATED + nsim/nsim_hs6x/smp +) +set(nsim_hs6x_smp_12cores_DEPRECATED + nsim/nsim_hs6x/smp/12cores +) +set(nsim_hs_flash_xip_DEPRECATED + nsim/nsim_hs/flash_xip +) +set(nsim_hs_mpuv6_DEPRECATED + nsim/nsim_hs/mpuv6 +) +set(nsim_hs_smp_DEPRECATED + nsim/nsim_hs/smp +) +set(nsim_hs_sram_DEPRECATED + nsim/nsim_hs/sram +) +set(nsim_sem_DEPRECATED + nsim/nsim_sem +) +set(nsim_sem_mpu_stack_guard_DEPRECATED + nsim/nsim_sem/mpu_stack_guard +) +set(nsim_vpx5_DEPRECATED + nsim/nsim_vpx5 +) +set(nucleo_h745zi_q_m4_DEPRECATED + nucleo_h745zi_q/stm32h745xx/m4 +) +set(nucleo_h745zi_q_m7_DEPRECATED + nucleo_h745zi_q/stm32h745xx/m7 +) +set(nucleo_l452re_p_DEPRECATED + nucleo_l452re/stm32l452xx/p +) +set(nucleo_l552ze_q_ns_DEPRECATED + nucleo_l552ze_q/stm32l552xx/ns +) +set(nuvoton_pfm_m487_DEPRECATED + numaker_pfm_m487 +) +set(nxp_adsp_imx8_DEPRECATED + imx8qm_mek/mimx8qm6/adsp +) +set(nxp_adsp_imx8m_DEPRECATED + imx8mp_evk/mimx8ml8/adsp +) +set(nxp_adsp_imx8ulp_DEPRECATED + imx8ulp_evk/imx8ulp/adsp +) +set(nxp_adsp_imx8x_DEPRECATED + imx8qxp_mek/mimx8qx6/adsp +) +set(nxp_adsp_rt595_DEPRECATED + mimxrt595_evk/mimxrt595s/f1 +) +set(nxp_ls1046ardb_DEPRECATED + ls1046ardb +) +set(nxp_ls1046ardb_smp_2cores_DEPRECATED + ls1046ardb/ls1046a/smp +) +set(nxp_ls1046ardb_smp_4cores_DEPRECATED + ls1046ardb/ls1046a/smp/4cores +) +set(odroid_go_DEPRECATED + odroid_go/esp32/procpu +) +set(olimex_esp32_evb_DEPRECATED + olimex_esp32_evb/esp32/procpu +) +set(pan1783_evb_cpuapp_DEPRECATED + pan1783_evb/nrf5340/cpuapp +) +set(pan1783_evb_cpunet_DEPRECATED + pan1783_evb/nrf5340/cpunet +) +set(pan1783a_evb_cpuapp_DEPRECATED + pan1783a_evb/nrf5340/cpuapp +) +set(pan1783a_evb_cpunet_DEPRECATED + pan1783a_evb/nrf5340/cpunet +) +set(pan1783a_pa_evb_cpuapp_DEPRECATED + pan1783a_pa_evb/nrf5340/cpuapp +) +set(pan1783a_pa_evb_cpunet_DEPRECATED + pan1783a_pa_evb/nrf5340/cpunet +) +set(phycore_am62x_a53_DEPRECATED + phycore_am62x/am6234/a53 +) +set(pico_pi_m4_DEPRECATED + pico_pi/mcimx7d/m4 +) +set(qemu_arc_em_DEPRECATED + qemu_arc/qemu_arc_em +) +set(qemu_arc_hs_DEPRECATED + qemu_arc/qemu_arc_hs +) +set(qemu_arc_hs5x_DEPRECATED + qemu_arc/qemu_arc_hs5x +) +set(qemu_arc_hs6x_DEPRECATED + qemu_arc/qemu_arc_hs6x +) +set(qemu_arc_hs_xip_DEPRECATED + qemu_arc/qemu_arc_hs/xip +) +set(qemu_cortex_a53_smp_DEPRECATED + qemu_cortex_a53/qemu_cortex_a53/smp +) +set(qemu_cortex_a53_xip_DEPRECATED + qemu_cortex_a53/qemu_cortex_a53/xip +) +set(qemu_malta_be_DEPRECATED + qemu_malta/qemu_malta/be +) +set(qemu_riscv32_smp_DEPRECATED + qemu_riscv32/qemu_virt_riscv32/smp +) +set(qemu_riscv64_smp_DEPRECATED + qemu_riscv64/qemu_virt_riscv64/smp +) +set(qemu_x86_64_nokpti_DEPRECATED + qemu_x86_64/atom/nokpti +) +set(qemu_x86_nokpti_DEPRECATED + qemu_x86/atom/nokpti +) +set(qemu_x86_nommu_DEPRECATED + qemu_x86/atom/nommu +) +set(qemu_x86_nopae_DEPRECATED + qemu_x86/atom/nopae +) +set(qemu_x86_virt_DEPRECATED + qemu_x86/atom/virt +) +set(qemu_x86_xip_DEPRECATED + qemu_x86/atom/xip +) +set(qemu_xtensa_mmu_DEPRECATED + qemu_xtensa/dc233c/mmu +) +set(rak4631_nrf52840_DEPRECATED + rak4631 +) +set(rak5010_nrf52840_DEPRECATED + rak5010 +) +set(raytac_mdbt50q_db_33_nrf52833_DEPRECATED + raytac_mdbt50q_db_33 +) +set(raytac_mdbt50q_db_40_nrf52840_DEPRECATED + raytac_mdbt50q_db_40 +) +set(raytac_mdbt53_db_40_nrf5340_cpuapp_DEPRECATED + raytac_mdbt53_db_40/nrf5340/cpuapp +) +set(raytac_mdbt53_db_40_nrf5340_cpuapp_ns_DEPRECATED + raytac_mdbt53_db_40/nrf5340/cpuapp/ns +) +set(raytac_mdbt53_db_40_nrf5340_cpunet_DEPRECATED + raytac_mdbt53_db_40/nrf5340/cpunet +) +set(raytac_mdbt53v_db_40_nrf5340_cpuapp_DEPRECATED + raytac_mdbt53v_db_40/nrf5340/cpuapp +) +set(raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_DEPRECATED + raytac_mdbt53v_db_40/nrf5340/cpuapp/ns +) +set(raytac_mdbt53v_db_40_nrf5340_cpunet_DEPRECATED + raytac_mdbt53v_db_40/nrf5340/cpunet +) +set(rcar_h3_salvatorx_cr7_DEPRECATED + rcar_salvator_x/r8a77951/r7 +) +set(rcar_h3ulcb_ca57_DEPRECATED + rcar_h3ulcb/r8a77951/a57 +) +set(rcar_h3ulcb_cr7_DEPRECATED + rcar_h3ulcb/r8a77951/r7 +) +set(rcar_salvator_xs_m3_DEPRECATED + rcar_salvator_xs +) +set(rcar_spider_cr52_DEPRECATED + rcar_spider_s4 +) +set(reel_board_v2_DEPRECATED + reel_board@2 +) +set(roc_rk3568_pc_smp_DEPRECATED + roc_rk3568_pc/rk3568/smp +) +set(rpi_pico_w_DEPRECATED + rpi_pico/rp2040/w +) +set(rv32m1_vega_ri5cy_DEPRECATED + rv32m1_vega/openisa_rv32m1/ri5cy +) +set(rv32m1_vega_zero_riscy_DEPRECATED + rv32m1_vega/openisa_rv32m1/zero_riscy +) +set(s32z270dc2_rtu0_r52_DEPRECATED + s32z2xxdc2/s32z270/rtu0 +) +set(s32z270dc2_rtu1_r52_DEPRECATED + s32z2xxdc2/s32z270/rtu1 +) +set(sam_e70_xplained_DEPRECATED + sam_e70_xplained/same70q21 +) +set(sam_e70b_xplained_DEPRECATED + sam_e70_xplained/same70q21b +) +set(sam_v71_xult_DEPRECATED + sam_v71_xult/samv71q21 +) +set(sam_v71b_xult_DEPRECATED + sam_v71_xult/samv71q21b +) +set(sparkfun_thing_plus_nrf9160_DEPRECATED + sparkfun_thing_plus +) +set(sparkfun_thing_plus_nrf9160_ns_DEPRECATED + sparkfun_thing_plus/nrf9160/ns +) +set(stm32_min_dev_black_DEPRECATED + stm32_min_dev@black +) +set(stm32_min_dev_blue_DEPRECATED + stm32_min_dev@blue +) +set(stm32h747i_disco_m4_DEPRECATED + stm32h747i_disco/stm32h747xx/m4 +) +set(stm32h747i_disco_m7_DEPRECATED + stm32h747i_disco/stm32h747xx/m7 +) +set(stm32l562e_dk_ns_DEPRECATED + stm32l562e_dk/stm32l562xx/ns +) +set(tdk_robokit1_DEPRECATED + robokit1 +) +set(thingy52_nrf52832_DEPRECATED + thingy52 +) +set(thingy53_nrf5340_cpuapp_DEPRECATED + thingy53/nrf5340/cpuapp +) +set(thingy53_nrf5340_cpuapp_ns_DEPRECATED + thingy53/nrf5340/cpuapp/ns +) +set(thingy53_nrf5340_cpunet_DEPRECATED + thingy53/nrf5340/cpunet +) +set(ubx_bmd300eval_nrf52832_DEPRECATED + ubx_bmd300eval +) +set(ubx_bmd330eval_nrf52810_DEPRECATED + ubx_bmd330eval +) +set(ubx_bmd340eval_nrf52840_DEPRECATED + ubx_bmd340eval +) +set(ubx_bmd345eval_nrf52840_DEPRECATED + ubx_bmd345eval +) +set(ubx_bmd360eval_nrf52811_DEPRECATED + ubx_bmd360eval +) +set(ubx_bmd380eval_nrf52840_DEPRECATED + ubx_bmd380eval +) +set(ubx_evkannab1_nrf52832_DEPRECATED + ubx_evkannab1 +) +set(ubx_evkninab1_nrf52832_DEPRECATED + ubx_evkninab1 +) +set(ubx_evkninab3_nrf52840_DEPRECATED + ubx_evkninab3 +) +set(ubx_evkninab4_nrf52833_DEPRECATED + ubx_evkninab4 +) +set(udoo_neo_full_m4_DEPRECATED + udoo_neo_full/mcimx6x/m4 +) +set(v2m_musca_b1_ns_DEPRECATED + v2m_musca_b1/musca_b1/ns +) +set(v2m_musca_s1_ns_DEPRECATED + v2m_musca_s1/musca_s1/ns +) +set(verdin_imx8mp_m7_ddr_DEPRECATED + verdin_imx8mp/mimx8ml8/m7/ddr +) +set(verdin_imx8mp_m7_itcm_DEPRECATED + verdin_imx8mp/mimx8ml8/m7 +) +set(vmu_rt1170_DEPRECATED + vmu_rt1170/mimxrt1176/cm7 +) +set(warp7_m4_DEPRECATED + warp7/mcimx7d/m4 +) +set(we_ophelia1ev_nrf52805_DEPRECATED + we_ophelia1ev +) +set(we_proteus2ev_nrf52832_DEPRECATED + we_proteus2ev +) +set(we_proteus3ev_nrf52840_DEPRECATED + we_proteus3ev +) +set(xenvm_gicv3_DEPRECATED + xenvm/xenvm/gicv3 +) +set(xiao_ble_sense_DEPRECATED + xiao_ble/nrf52840/sense +) +set(xiao_esp32s3_DEPRECATED + xiao_esp32s3/esp32s3/procpu +) +set(yd_esp32_DEPRECATED + yd_esp32/esp32/procpu +) diff --git a/boards/digilent/arty_a7/CMakeLists.txt b/boards/digilent/arty_a7/CMakeLists.txt new file mode 100644 index 00000000000000..5b036b02a7337e --- /dev/null +++ b/boards/digilent/arty_a7/CMakeLists.txt @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) + +if((CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1) AND (CONFIG_BUILD_OUTPUT_BIN)) + # Generate zephyr.mem verilog memory hex dump file for initialising ITCM in + # Xilinx Vivado. + # + # This ought to be done using the objcopy verilog bfd, but it contains a bug + # affecting endianness: https://sourceware.org/bugzilla/show_bug.cgi?id=25202 + # + # Instead we use bin2hex from the SiFive elf2hex package, if available. + # https://github.com/sifive/elf2hex + find_program(BIN2HEX ${CROSS_COMPILE_TARGET}-bin2hex) + + if(NOT ${BIN2HEX} STREQUAL BIN2HEX-NOTFOUND) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${BIN2HEX} + ARGS --bit-width 32 + ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} + ) + message(STATUS "Verilog memory hex dump will be written to: ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.mem") + else() + message(STATUS "The bin2hex (${CROSS_COMPILE_TARGET}-bin2hex) utility was not found, verilog memory hex dump file cannot be generated") + endif() +endif() diff --git a/boards/digilent/arty_a7/Kconfig b/boards/digilent/arty_a7/Kconfig new file mode 100644 index 00000000000000..19be35749f88a2 --- /dev/null +++ b/boards/digilent/arty_a7/Kconfig @@ -0,0 +1,13 @@ +# Digilent Arty board configuration + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 50 + depends on BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 + depends on "$(dt_nodelabel_enabled,daplink_qspi_mux)" + help + Board initialization priority. The board initialization must take + place after the GPIO driver is initialized. diff --git a/boards/digilent/arty_a7/Kconfig.arty_a7 b/boards/digilent/arty_a7/Kconfig.arty_a7 new file mode 100644 index 00000000000000..6e5ac7bb17999e --- /dev/null +++ b/boards/digilent/arty_a7/Kconfig.arty_a7 @@ -0,0 +1,8 @@ +# Digilent Arty board configuration + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ARTY_A7 + select SOC_DESIGNSTART_FPGA_CORTEX_M1 if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 + select SOC_DESIGNSTART_FPGA_CORTEX_M3 if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/digilent/arty_a7/Kconfig.defconfig b/boards/digilent/arty_a7/Kconfig.defconfig new file mode 100644 index 00000000000000..ecd93d6954a3df --- /dev/null +++ b/boards/digilent/arty_a7/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Digilent Arty board configuration + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 + +config CPU_CORTEX_M_HAS_SYSTICK + default y + +config CPU_HAS_ARM_MPU + default y if BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 + +config NUM_IRQS + default 7 + +config GPIO + default y if "$(dt_nodelabel_enabled,daplink_qspi_mux)" + +endif # BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1 || BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/arm/arty/arty_a7_arm_designstart_m1.dts b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.dts similarity index 100% rename from boards/arm/arty/arty_a7_arm_designstart_m1.dts rename to boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.dts diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml new file mode 100644 index 00000000000000..565ddbffdb88c0 --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml @@ -0,0 +1,14 @@ +identifier: arty_a7/designstart_fpga_cortex_m1 +name: Digilent Arty A7 ARM DesignStart Cortex-M1 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 64 +supported: + - flash + - spi + - gpio diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig new file mode 100644 index 00000000000000..ce3f3066fa07e8 --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000 + +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/arty_a7_arm_designstart_m3.dts b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.dts similarity index 100% rename from boards/arm/arty/arty_a7_arm_designstart_m3.dts rename to boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.dts diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml new file mode 100644 index 00000000000000..416365ff29140d --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml @@ -0,0 +1,14 @@ +identifier: arty_a7/designstart_fpga_cortex_m3 +name: Digilent Arty A7 ARM DesignStart Cortex-M3 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 32 +supported: + - flash + - spi + - gpio diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig new file mode 100644 index 00000000000000..7952bdf9f20bf2 --- /dev/null +++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/arty/board.c b/boards/digilent/arty_a7/board.c similarity index 100% rename from boards/arm/arty/board.c rename to boards/digilent/arty_a7/board.c diff --git a/boards/digilent/arty_a7/board.cmake b/boards/digilent/arty_a7/board.cmake new file mode 100644 index 00000000000000..0596bf31add8f1 --- /dev/null +++ b/boards/digilent/arty_a7/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M1) + board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m1.cfg") + board_runner_args(jlink "--device=Cortex-M1" "--reset-after-load") +elseif(CONFIG_BOARD_ARTY_A7_DESIGNSTART_FPGA_CORTEX_M3) + board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd_arty_a7_arm_designstart_m3.cfg") + board_runner_args(jlink "--device=Cortex-M3" "--reset-after-load") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/arty/board.h b/boards/digilent/arty_a7/board.h similarity index 100% rename from boards/arm/arty/board.h rename to boards/digilent/arty_a7/board.h diff --git a/boards/digilent/arty_a7/board.yml b/boards/digilent/arty_a7/board.yml new file mode 100644 index 00000000000000..14a2c9ef41882b --- /dev/null +++ b/boards/digilent/arty_a7/board.yml @@ -0,0 +1,6 @@ +board: + name: arty_a7 + vendor: digilent + socs: + - name: designstart_fpga_cortex_m1 + - name: designstart_fpga_cortex_m3 diff --git a/boards/arm/arty/doc/arty_a7-35.jpg b/boards/digilent/arty_a7/doc/arty_a7-35.jpg similarity index 100% rename from boards/arm/arty/doc/arty_a7-35.jpg rename to boards/digilent/arty_a7/doc/arty_a7-35.jpg diff --git a/boards/digilent/arty_a7/doc/index.rst b/boards/digilent/arty_a7/doc/index.rst new file mode 100644 index 00000000000000..4284320d6de452 --- /dev/null +++ b/boards/digilent/arty_a7/doc/index.rst @@ -0,0 +1,228 @@ +.. _arty: + +Digilent Arty +############# + +Overview +******** + +The `Digilent Arty`_ is a line of FPGA-based development boards aimed for makers +and hobbyists. The Arty is available in several configurations, each with a +different Xilinx FPGA (Spartan-7, Artix-7, or Zynq-7000 series). + +Each board is equipped with on-board JTAG for FPGA programming and debugging, +LEDs, switches, buttons, DDR3 RAM, and QSPI flash for storing the FPGA +bitstream. + +.. figure:: arty_a7-35.jpg + :align: center + :alt: Digilent Arty A7-35 + + Digilent Arty A7-35 (Credit: Digilent Inc) + +The Spartan-7 and Artix-7 based Arty board do not contain a CPU, but require a +so-called soft processor to be instantiated within the FPGA in order to run +Zephyr. The Zynq-7000 based Arty boards are not yet supported by Zephyr. + +ARM Cortex-M1/M3 DesignStart FPGA +********************************* + +One way of instantiating soft processors on the Arty is using the `ARM +DesignStart FPGA`_ Xilinx edition reference designs from ARM. Zephyr supports +both the Cortex-M1 and the Cortex-M3 reference designs. The Cortex-M1 design +targets either the Spartan-7 or Artix-7 based Arty boards, whereas the Cortex-M3 +design only targets the Artix-7 based boards. Zephyr only supports the Artix-7 +targeted designs for now. + +For more information about the ARM Cortex-M1/M3 DesignStart FPGA, see the +following websites: + +- `Technical Resources for DesignStart FPGA`_ +- `Technical Resources for DesignStart FPGA on Xilinx`_ +- `ARM DesignStart FPGA Xilinx FAQs`_ + +Supported Features +================== + +The ``arty_a7/designstart_fpga_cortex_m1`` board configuration supports the following +hardware features of the Cortex-M1 reference design: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio, non-interrupt | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| QSPI | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ + +The default configuration for the Cortex-M1 can be found in the defconfig file: +:file:`boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1_defconfig`. + +In addition to the above, the ``arty_a7/designstart_fpga_cortex_m3`` board configuration +supports the following hardware features of the Cortex-M3 reference design: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | Memory Protection Unit | ++-----------+------------+-------------------------------------+ + +The default configuration for the Cortex-M3 can be found in the defconfig file: +:file:`boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The Cortex-M1 reference design is configured to use the 100 MHz external +oscillator on the board as CPU system clock whereas the Cortex-M3 reference +design is configured for 50MHz CPU system clock. + +Serial Port +=========== + +The reference design contains one Xilinx UART Lite. This UART is configured as +console and is accessible through the on-board JTAG adapter via USB connector +``J10``. + +Connecting the Debug Probes +=========================== + +Two different debug probes are needed in order to program the board; the +on-board Digilent JTAG connected to the FPGA, and an external Serial Wire Debug +(SWD) capable debug probe connected to the ARM Cortex-M1 CPU. + +The on-board JTAG is used for configuring and debugging the Xilinx FPGA +itself. It is available on USB connector ``J10``. + +The external SWD debug probe can be connected to connector ``J4`` (``nSRST`` on +``IO39``, ``SWDIO`` on ``IO40``, and ``SWCLK`` on ``IO41``). Another option is +to use the dedicated :ref:`v2c_daplink_shield`. + +Programming and Debugging +************************* + +First, configure the FPGA with the selected reference design FPGA bitstream +using Xilinx Vivado as described in the ARM Cortex-M1/Cortex-M3 DesignStart FPGA +Xilinx edition user guide (available as part of the reference design download +from `Technical Resources for DesignStart FPGA on Xilinx`_). + +Another option for configuring the FPGA with the reference design bitstream is +to use the :ref:`openocd-debug-host-tools`: + +.. code-block:: console + + openocd -f board/arty_s7.cfg -c "init;\ + pld load 0 m1_for_arty_a7_reference.bit;\ + shutdown" + +or: + +.. code-block:: console + + openocd -f board/arty_s7.cfg -c "init;\ + pld load 0 m3_for_arty_a7_reference.bit;\ + shutdown" + +.. note:: + + The pre-built FPGA bitstream only works for Arty boards equipped with an + Artix-35T FPGA. For other Arty variants (e.g. the Arty A7-100) the bitstream + must be rebuilt. + +Next, build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Console +===================== + +The UART console is available via the on-board JTAG on USB connector +``J10``. The on-board JTAG will enumerate as two USB serial ports. The UART is +typically available on the second serial port. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for building and flashing the :ref:`hello_world` application +for the Cortex-M1 reference design: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arty_a7/designstart_fpga_cortex_m1 + :goals: flash + +After flashing, you should see message similar to the following in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.3.99 *** + Hello World! arty_a7 + +The same procedure can be used for the Cortex-M3 reference design. + +Note, however, that the application was not persisted in flash memory by the +above steps. It was merely written to internal block RAM in the FPGA. It will +revert to the application stored in the block RAM within the FPGA bitstream +the next time the FPGA is configured. + +The steps to persist the application within the FPGA bitstream are covered by +the ARM Cortex-M1/M3 DesignStart FPGA Xilinx edition user guide. If the +:kconfig:option:`CONFIG_BUILD_OUTPUT_BIN` is enabled and the `SiFive elf2hex`_ package +is available, the build system will automatically generate a Verilog memory hex +dump :file:`zephyr.mem` file suitable for initialising the block RAM using +`Xilinx Vivado`_. + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: arty_a7/designstart_fpga_cortex_m1 + :goals: debug + +Step through the application in your debugger, and you should see a message +similar to the following in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.3.99 *** + Hello World! arty_a7 + +.. _Digilent Arty: + https://store.digilentinc.com/arty + +.. _ARM DesignStart FPGA: + https://www.arm.com/resources/designstart/designstart-fpga + +.. _Technical Resources for DesignStart FPGA: + https://developer.arm.com/ip-products/designstart/fpga + +.. _Technical Resources for DesignStart FPGA on Xilinx: + https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx + +.. _ARM DesignStart FPGA Xilinx FAQs: + https://developer.arm.com/ip-products/designstart/fpga/fpga-xilinx-faqs + +.. _SiFive elf2hex: + https://github.com/sifive/elf2hex + +.. _Xilinx Vivado: + https://www.xilinx.com/products/design-tools/vivado.html diff --git a/boards/arm/arty/dts/arty_a7_arm_designstart.dtsi b/boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi similarity index 100% rename from boards/arm/arty/dts/arty_a7_arm_designstart.dtsi rename to boards/digilent/arty_a7/dts/arty_a7_arm_designstart.dtsi diff --git a/boards/arm/arty/dts/bindings/arm,daplink-qspi-mux.yaml b/boards/digilent/arty_a7/dts/bindings/arm,daplink-qspi-mux.yaml similarity index 100% rename from boards/arm/arty/dts/bindings/arm,daplink-qspi-mux.yaml rename to boards/digilent/arty_a7/dts/bindings/arm,daplink-qspi-mux.yaml diff --git a/boards/arm/arty/support/openocd_arty_a7_arm_designstart.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart.cfg similarity index 100% rename from boards/arm/arty/support/openocd_arty_a7_arm_designstart.cfg rename to boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart.cfg diff --git a/boards/arm/arty/support/openocd_arty_a7_arm_designstart_m1.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg similarity index 100% rename from boards/arm/arty/support/openocd_arty_a7_arm_designstart_m1.cfg rename to boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m1.cfg diff --git a/boards/arm/arty/support/openocd_arty_a7_arm_designstart_m3.cfg b/boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg similarity index 100% rename from boards/arm/arty/support/openocd_arty_a7_arm_designstart_m3.cfg rename to boards/digilent/arty_a7/support/openocd_arty_a7_arm_designstart_m3.cfg diff --git a/boards/digilent/index.rst b/boards/digilent/index.rst new file mode 100644 index 00000000000000..811282e59ae7a2 --- /dev/null +++ b/boards/digilent/index.rst @@ -0,0 +1,10 @@ +.. _boards-digilent: + +Digilent, Inc. +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/digilent/zybo/Kconfig.zybo b/boards/digilent/zybo/Kconfig.zybo new file mode 100644 index 00000000000000..fc1662ed6be22e --- /dev/null +++ b/boards/digilent/zybo/Kconfig.zybo @@ -0,0 +1,7 @@ +# Digilent Zybo board configuration + +# Copyright (c) 2022 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ZYBO + select SOC_XILINX_XC7Z010 diff --git a/boards/arm/zybo/board.cmake b/boards/digilent/zybo/board.cmake similarity index 100% rename from boards/arm/zybo/board.cmake rename to boards/digilent/zybo/board.cmake diff --git a/boards/digilent/zybo/board.yml b/boards/digilent/zybo/board.yml new file mode 100644 index 00000000000000..f9c9c98bea2aaa --- /dev/null +++ b/boards/digilent/zybo/board.yml @@ -0,0 +1,5 @@ +board: + name: zybo + vendor: digilent + socs: + - name: xc7z010 diff --git a/boards/digilent/zybo/doc/index.rst b/boards/digilent/zybo/doc/index.rst new file mode 100644 index 00000000000000..f8e3857227df04 --- /dev/null +++ b/boards/digilent/zybo/doc/index.rst @@ -0,0 +1,147 @@ +.. _zybo: + +Digilent Zybo +############# + +Overview +******** + +The `Digilent Zybo`_ (ZYnq BOard) is a feature-rich, ready-to-use embedded software and digital +circuit development board. It is built around the Xilinx Zynq-7000 family, which is based on the +Xilinx All Programmable System-on-Chip (AP SoC) architecture. This architecture tightly integrates a +dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. + +.. figure:: zybo-0.jpg + :align: center + :alt: Digilent Zybo + + Digilent (Credit: Digilent) + +Hardware +******** + +Supported Features +================== + +The zybo board configuration supports the following hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| GICv1 | on-chip | ARM generic interrupt controller v1 | ++------------+------------+-------------------------------------+ +| ARCH TIMER | on-chip | ARM architected timer | ++------------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/digilent/zybo/zybo_defconfig` + +Other hardware features are not currently supported by the port. + +Programming and Debugging +************************* + +The Zynq-7000 series SoC needs to be initialized prior to running a Zephyr application. This can be +achieved in a number of ways (e.g. using the Xilinx First Stage Boot Loader (FSBL), the Xilinx +Vivado generated ``ps_init.tcl`` JTAG script, Das U-Boot Secondary Program Loader (SPL), ...). + +The instructions here use the U-Boot SPL. For further details and instructions for using Das U-Boot +with Xilinx Zynq-7000 series SoCs, see the following documentation: + +- `Das U-Boot Website`_ +- `Using Distro Boot With Xilinx U-Boot`_ + +Building Das U-Boot +=================== + +Clone and build Das U-Boot for the Digilent Zybo: + +.. code-block:: console + + git clone -b v2022.04 https://source.denx.de/u-boot/u-boot.git + cd u-boot + make distclean + make xilinx_zynq_virt_defconfig + export PATH=/path/to/zephyr-sdk/arm-zephyr-eabi/bin/:$PATH + export CROSS_COMPILE=arm-zephyr-eabi- + export DEVICE_TREE="zynq-zybo" + make + +Flashing +======== + +Here is an example for running the :ref:`hello_world` application via JTAG. + +Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press +the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot +SPL via JTAG. + +Next, upload and run the Zephyr application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: zybo + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** + Hello World! zybo + +Another option is to load and run the :ref:`hello_world` application via U-Boot. Copy +``u-boot/spl/boot.bin``, ``u-boot/u-boot.img``, and ``zephyr/zephyr.bin`` to a FAT32 formatted +microSD card, insert the card in the ``SD MICRO`` slot on the Zybo board, ensure the board is +configured for ``SD`` boot, and turn on the board. + +Once U-boot is done initializing, load an run the Zephyr application: + +.. code-block:: console + + Zynq> fatload mmc 0 0x0 zephyr.bin + 817120 bytes read in 56 ms (13.9 MiB/s) + Zynq> go 0x0 + ## Starting application at 0x00000000 ... + *** Booting Zephyr OS vx.xx.x-xxx-gxxxxxxxxxxxx *** + Hello World! zybo + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +Ensure the board is configured for JTAG boot, open a serial terminal, turn on/reset the board (press +the ``PS-SRST`` button), and initialize the Zynq-7000 series SoC by uploading and running the U-Boot +SPL via JTAG. + +Next, upload and debug the Zephyr application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: zybo + :goals: debug + +Step through the application in your debugger, and you should see the following message in the +terminal: + +.. code-block:: console + + *** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *** + Hello World! zybo + +.. _Digilent Zybo: + https://digilent.com/reference/programmable-logic/zybo/start + +.. _Das U-Boot Website: + https://www.denx.de/wiki/U-Boot + +.. _Using Distro Boot With Xilinx U-Boot: + https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/749142017/Using+Distro+Boot+With+Xilinx+U-Boot diff --git a/boards/arm/zybo/doc/zybo-0.jpg b/boards/digilent/zybo/doc/zybo-0.jpg similarity index 100% rename from boards/arm/zybo/doc/zybo-0.jpg rename to boards/digilent/zybo/doc/zybo-0.jpg diff --git a/boards/arm/zybo/support/openocd.cfg b/boards/digilent/zybo/support/openocd.cfg similarity index 100% rename from boards/arm/zybo/support/openocd.cfg rename to boards/digilent/zybo/support/openocd.cfg diff --git a/boards/arm/zybo/zybo-pinctrl.dtsi b/boards/digilent/zybo/zybo-pinctrl.dtsi similarity index 100% rename from boards/arm/zybo/zybo-pinctrl.dtsi rename to boards/digilent/zybo/zybo-pinctrl.dtsi diff --git a/boards/arm/zybo/zybo.dts b/boards/digilent/zybo/zybo.dts similarity index 100% rename from boards/arm/zybo/zybo.dts rename to boards/digilent/zybo/zybo.dts diff --git a/boards/arm/zybo/zybo.yaml b/boards/digilent/zybo/zybo.yaml similarity index 100% rename from boards/arm/zybo/zybo.yaml rename to boards/digilent/zybo/zybo.yaml diff --git a/boards/digilent/zybo/zybo_defconfig b/boards/digilent/zybo/zybo_defconfig new file mode 100644 index 00000000000000..bf2bc2777e69d4 --- /dev/null +++ b/boards/digilent/zybo/zybo_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) +CONFIG_ARM_ARCH_TIMER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=325000000 + +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/dragino/index.rst b/boards/dragino/index.rst new file mode 100644 index 00000000000000..c9141395af8dc1 --- /dev/null +++ b/boards/dragino/index.rst @@ -0,0 +1,10 @@ +.. _boards-dragino: + +Dragino +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/dragino/lsn50/Kconfig.dragino_lsn50 b/boards/dragino/lsn50/Kconfig.dragino_lsn50 new file mode 100644 index 00000000000000..c8dd04dbd9e6a8 --- /dev/null +++ b/boards/dragino/lsn50/Kconfig.dragino_lsn50 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DRAGINO_LSN50 + select SOC_STM32L072XX diff --git a/boards/arm/b_l072z_lrwan1/board.cmake b/boards/dragino/lsn50/board.cmake similarity index 100% rename from boards/arm/b_l072z_lrwan1/board.cmake rename to boards/dragino/lsn50/board.cmake diff --git a/boards/dragino/lsn50/board.yml b/boards/dragino/lsn50/board.yml new file mode 100644 index 00000000000000..e7c09a9c7bd655 --- /dev/null +++ b/boards/dragino/lsn50/board.yml @@ -0,0 +1,5 @@ +board: + name: dragino_lsn50 + vendor: dragino + socs: + - name: stm32l072xx diff --git a/boards/arm/dragino_lsn50/doc/img/dragino_lsn50.jpg b/boards/dragino/lsn50/doc/img/dragino_lsn50.jpg similarity index 100% rename from boards/arm/dragino_lsn50/doc/img/dragino_lsn50.jpg rename to boards/dragino/lsn50/doc/img/dragino_lsn50.jpg diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst new file mode 100644 index 00000000000000..b3d14f928856f8 --- /dev/null +++ b/boards/dragino/lsn50/doc/index.rst @@ -0,0 +1,193 @@ +.. _dragino_lsn50_board: + +Dragino LSN50 LoRA Sensor Node +############################## + +Overview +******** + +The Dragino LSN50 LoRA Sensor Node for IoT allows users to develop +applications with LoraWAN connectivity via the HopeRF / SX1276/SX1278. +Dragino LSN50 enables a wide diversity of applications by exploiting +low-power communication, ARM |reg| Cortex |reg|-M0 core-based +STM32L0 Series features. + +This kit provides: + +- STM32L072CZ MCU +- SX1276/SX1278 LoRa Transceiver +- Expansion connectors: + + - PMOD +- Li/SOCI2 Unchargable Battery +- GPIOs exposed via screw terminals on the carrier board +- Housing + +.. image:: img/dragino_lsn50.jpg + :align: center + :alt: Dragino LSN50 + +More information about the board can be found at the `Dragino LSN50 website`_. + +Hardware +******** + +The STM32L072CZ SoC provides the following hardware IPs: + +- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz +- Clock Sources: + + - 1 to 32 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal multispeed low-power 65 kHz to 4.2 MHz RC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 2x 16-bit with up to 4 channels + - 2x 16-bit with up to 2 channels + - 1x 16-bit ultra-low-power timer + - 1x SysTick + - 1x RTC + - 2x 16-bit basic for DAC + - 2x watchdogs (independent/window) +- Up to 84 fast I/Os, most 5 V-tolerant. +- Memories + + - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 20 KB of SRAM + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 1.14 MSPS + - 2x 12-bit DAC + - 2x ultra-low-power comparators +- 11x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 6x SPIs (4x SPIs with the Quad SPI) +- 7-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L072CZ can be found here: + + - `STM32L072CZ on www.st.com`_ + - `STM32L0x2 reference manual`_ + +Supported Features +================== + +The Zephyr Dragino LSN50 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/dragino/lsn50/dragino_lsn50_defconfig` + + +Connections and IOs +=================== + +Dragino LSN50 Board has GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `Dragino LSN50 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +System Clock +------------ + +Dragino LSN50 System Clock is at 32MHz, + +Serial Port +----------- + +Dragino LSN50 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``dragino_lsn50`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Dragino LSN50 board requires an external debugger. + +Flashing an application to Dragino LSN50 +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the Dragino LSN50 to a STLinkV2 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_lsn50 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_lsn50 + :maybe-skip-config: + :goals: debug + +.. _Dragino LSN50 website: + https://www.dragino.com/products/lora-lorawan-end-node/item/128-lsn50.html + +.. _STM32L072CZ on www.st.com: + https://www.st.com/en/microcontrollers/stm32l072cz.html + +.. _STM32L0x2 reference manual: + https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_lsn50/dragino_lsn50.dts b/boards/dragino/lsn50/dragino_lsn50.dts similarity index 100% rename from boards/arm/dragino_lsn50/dragino_lsn50.dts rename to boards/dragino/lsn50/dragino_lsn50.dts diff --git a/boards/arm/dragino_lsn50/dragino_lsn50.yaml b/boards/dragino/lsn50/dragino_lsn50.yaml similarity index 100% rename from boards/arm/dragino_lsn50/dragino_lsn50.yaml rename to boards/dragino/lsn50/dragino_lsn50.yaml diff --git a/boards/dragino/lsn50/dragino_lsn50_defconfig b/boards/dragino/lsn50/dragino_lsn50_defconfig new file mode 100644 index 00000000000000..06e8a32bb1f031 --- /dev/null +++ b/boards/dragino/lsn50/dragino_lsn50_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_lsn50/support/openocd.cfg b/boards/dragino/lsn50/support/openocd.cfg similarity index 100% rename from boards/arm/dragino_lsn50/support/openocd.cfg rename to boards/dragino/lsn50/support/openocd.cfg diff --git a/boards/dragino/nbsn95/Kconfig.dragino_nbsn95 b/boards/dragino/nbsn95/Kconfig.dragino_nbsn95 new file mode 100644 index 00000000000000..21a6867793e486 --- /dev/null +++ b/boards/dragino/nbsn95/Kconfig.dragino_nbsn95 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Next Big Thing AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DRAGINO_NBSN95 + select SOC_STM32L072XX diff --git a/boards/arm/dragino_lsn50/board.cmake b/boards/dragino/nbsn95/board.cmake similarity index 100% rename from boards/arm/dragino_lsn50/board.cmake rename to boards/dragino/nbsn95/board.cmake diff --git a/boards/dragino/nbsn95/board.yml b/boards/dragino/nbsn95/board.yml new file mode 100644 index 00000000000000..66d568935ec904 --- /dev/null +++ b/boards/dragino/nbsn95/board.yml @@ -0,0 +1,5 @@ +board: + name: dragino_nbsn95 + vendor: dragino + socs: + - name: stm32l072xx diff --git a/boards/arm/dragino_nbsn95/doc/img/dragino_nbsn95.jpg b/boards/dragino/nbsn95/doc/img/dragino_nbsn95.jpg similarity index 100% rename from boards/arm/dragino_nbsn95/doc/img/dragino_nbsn95.jpg rename to boards/dragino/nbsn95/doc/img/dragino_nbsn95.jpg diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst new file mode 100644 index 00000000000000..09a8b91f6ceef1 --- /dev/null +++ b/boards/dragino/nbsn95/doc/index.rst @@ -0,0 +1,192 @@ +.. _dragino_nbsn95_board: + +Dragino NBSN95 NB-IoT Sensor Node +################################# + +Overview +******** + +The Dragino NBSN95 NB-IoT Sensor Node for IoT allows users to develop +applications with NB-IoT connectivity via the Quectel BC95-G. +Dragino NBSN95 enables a wide diversity of applications by exploiting +low-power communication, ARM |reg| Cortex |reg|-M0 core-based +STM32L0 Series features. + +This kit provides: + +- STM32L072CZ MCU +- Quectel BC95-G NB-IoT +- Expansion connectors: + - PMOD +- Li/SOCI2 Unchargable Battery +- GPIOs exposed via screw terminals on the carrier board +- Housing + +.. image:: img/dragino_nbsn95.jpg + :align: center + :alt: Dragino NBSN95 + +More information about the board can be found at the `Dragino NBSN95 website`_. + +Hardware +******** + +The STM32L072CZ SoC provides the following hardware IPs: + +- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M0+ CPU, frequency up to 32 MHz +- Clock Sources: + + - 1 to 32 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal multispeed low-power 65 kHz to 4.2 MHz RC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 2x 16-bit with up to 4 channels + - 2x 16-bit with up to 2 channels + - 1x 16-bit ultra-low-power timer + - 1x SysTick + - 1x RTC + - 2x 16-bit basic for DAC + - 2x watchdogs (independent/window) +- Up to 84 fast I/Os, most 5 V-tolerant. +- Memories + + - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 20 KB of SRAM + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 1.14 MSPS + - 2x 12-bit DAC + - 2x ultra-low-power comparators +- 11x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 6x SPIs (4x SPIs with the Quad SPI) +- 7-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L072CZ can be found here: + + - `STM32L072CZ on www.st.com`_ + - `STM32L0x2 reference manual`_ + +Supported Features +================== + +The Zephyr Dragino NBSN95 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/dragino/nbsn95/dragino_nbsn95_defconfig` + + +Connections and IOs +=================== + +Dragino NBSN95 Board has GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `Dragino NBSN95 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +System Clock +------------ + +Dragino NBSN95 System Clock is at 32MHz, + +Serial Port +----------- + +Dragino NBSN95 board has 2 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``dragino_nbsn95`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Dragino NBSN95 board requires an external debugger. + +Flashing an application to Dragino NBSN95 +----------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the Dragino NBSN95 to a STLinkV2 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_nbsn95 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! dragino_nbsn95 + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: dragino_nbsn95 + :maybe-skip-config: + :goals: debug + +.. _Dragino NBSN95 website: + https://www.dragino.com/products/nb-iot/item/163-nbsn95.html + +.. _STM32L072CZ on www.st.com: + https://www.st.com/en/microcontrollers/stm32l072cz.html + +.. _STM32L0x2 reference manual: + https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95.dts b/boards/dragino/nbsn95/dragino_nbsn95.dts similarity index 100% rename from boards/arm/dragino_nbsn95/dragino_nbsn95.dts rename to boards/dragino/nbsn95/dragino_nbsn95.dts diff --git a/boards/arm/dragino_nbsn95/dragino_nbsn95.yaml b/boards/dragino/nbsn95/dragino_nbsn95.yaml similarity index 100% rename from boards/arm/dragino_nbsn95/dragino_nbsn95.yaml rename to boards/dragino/nbsn95/dragino_nbsn95.yaml diff --git a/boards/dragino/nbsn95/dragino_nbsn95_defconfig b/boards/dragino/nbsn95/dragino_nbsn95_defconfig new file mode 100644 index 00000000000000..1a570d28d13212 --- /dev/null +++ b/boards/dragino/nbsn95/dragino_nbsn95_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_nbsn95/support/openocd.cfg b/boards/dragino/nbsn95/support/openocd.cfg similarity index 100% rename from boards/arm/dragino_nbsn95/support/openocd.cfg rename to boards/dragino/nbsn95/support/openocd.cfg diff --git a/boards/ebyte/e73_tbb/Kconfig.defconfig b/boards/ebyte/e73_tbb/Kconfig.defconfig new file mode 100644 index 00000000000000..d3434e975a2c06 --- /dev/null +++ b/boards/ebyte/e73_tbb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EBYTE E73-TBB NRF52832 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# Copyright (c) 2021 Michal Morsisko +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EBYTE_E73_TBB_NRF52832 + +config BT_CTLR + default BT + +endif # BOARD_EBYTE_E73_TBB_NRF52832 diff --git a/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb b/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb new file mode 100644 index 00000000000000..8a04ffd502dc82 --- /dev/null +++ b/boards/ebyte/e73_tbb/Kconfig.ebyte_e73_tbb @@ -0,0 +1,7 @@ +# EBYTE-TBB board configuration + +# Copyright (c) 2021 Michal Morsisko +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EBYTE_E73_TBB_NRF52832 + select SOC_NRF52832_QFAA diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/board.cmake b/boards/ebyte/e73_tbb/board.cmake similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/board.cmake rename to boards/ebyte/e73_tbb/board.cmake diff --git a/boards/ebyte/e73_tbb/board.yml b/boards/ebyte/e73_tbb/board.yml new file mode 100644 index 00000000000000..3ae94fab665e11 --- /dev/null +++ b/boards/ebyte/e73_tbb/board.yml @@ -0,0 +1,5 @@ +board: + name: ebyte_e73_tbb + vendor: ebyte + socs: + - name: nrf52832 diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/doc/img/ebyte_e73_tbb_nrf52832.jpg b/boards/ebyte/e73_tbb/doc/img/ebyte_e73_tbb_nrf52832.jpg similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/doc/img/ebyte_e73_tbb_nrf52832.jpg rename to boards/ebyte/e73_tbb/doc/img/ebyte_e73_tbb_nrf52832.jpg diff --git a/boards/ebyte/e73_tbb/doc/index.rst b/boards/ebyte/e73_tbb/doc/index.rst new file mode 100644 index 00000000000000..f05a3454b6e576 --- /dev/null +++ b/boards/ebyte/e73_tbb/doc/index.rst @@ -0,0 +1,222 @@ +.. _ebyte_e73_tbb_nrf52832: + +EBYTE E73-TBB +############# + +Overview +******** + +The EBYTE E73-TBB hardware provides +support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/ebyte_e73_tbb_nrf52832.jpg + :align: center + :alt: EBYTE E73-TBB + + EBYTE E73-TBB (Credit: EBYTE) + +More information about the board can be found at the +`E73-TBB website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +E73-TBB has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. Additionally the board features CH340 USB-UART converter. +It is possible to connect external BT antenna using U.FL socket +and solder NFC antenna using NFC_ANT connector. + +Supported Features +================== + +The ebyte_e73_tbb/nrf52832 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not supported by the Zephyr kernel. +See `E73-TBB website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52832 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.17 +* LED1 (red) = P0.18 + +Push buttons +------------ + +* BUTTON0 = SW1 = P0.14 +* BUTTON1 = SW2 = P0.13 + +External Connectors +------------------- + +P1 Header + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | GND | ++-------+--------------+ +| 2 | 3.3V | ++-------+--------------+ +| 3 | P0.04 | ++-------+--------------+ +| 4 | P0.03 | ++-------+--------------+ +| 5 | P0.02 | ++-------+--------------+ +| 6 | P0.31 | ++-------+--------------+ +| 7 | P0.30 | ++-------+--------------+ +| 8 | P0.29 | ++-------+--------------+ +| 9 | P0.28 | ++-------+--------------+ +| 10 | P0.27 | ++-------+--------------+ +| 11 | P0.26 | ++-------+--------------+ +| 12 | P0.25 | ++-------+--------------+ + +P2 Header + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | P0.24 | ++-------+--------------+ +| 2 | P0.23 | ++-------+--------------+ +| 3 | P0.22 | ++-------+--------------+ +| 4 | SWDIO | ++-------+--------------+ +| 5 | SWDCLK | ++-------+--------------+ +| 6 | P0.21/RST | ++-------+--------------+ +| 7 | P0.20 | ++-------+--------------+ +| 8 | P0.19 | ++-------+--------------+ +| 9 | P0.16 | ++-------+--------------+ +| 10 | P0.15 | ++-------+--------------+ +| 11 | P0.12 | ++-------+--------------+ +| 12 | P0.11 | ++-------+--------------+ + +NFC_ANT + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | P0.10 | ++-------+--------------+ +| 2 | P0.09 | ++-------+--------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. +To flash the board connect pins: SWDIO, SWDCLK, RST, GND from E73-TBB +to corresponding pins on your J-Link device, then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ebyte_e73_tbb/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic chips with a +Segger IC. + + +Testing the LEDs and buttons in the E73-TBB +******************************************* + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + :zephyr:code-sample:`blinky` + :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _E73-TBB website: https://www.ebyte.com/en/product-view-news.html?id=889 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832-pinctrl.dtsi b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832-pinctrl.dtsi rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.dts b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts similarity index 100% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.dts rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.dts diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.yaml b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml similarity index 85% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.yaml rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml index ba39fdbfc462be..9311e76cff1486 100644 --- a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832.yaml +++ b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ebyte_e73_tbb_nrf52832 +identifier: ebyte_e73_tbb/nrf52832 name: EBYTE-E73-TBB-NRF52832 type: mcu arch: arm diff --git a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832_defconfig b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832_defconfig similarity index 76% rename from boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832_defconfig rename to boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832_defconfig index 8b9a09a8e8df85..0ee25845f2e6a6 100644 --- a/boards/arm/ebyte_e73_tbb_nrf52832/ebyte_e73_tbb_nrf52832_defconfig +++ b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_EBYTE_E73_TBB_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/ebyte/index.rst b/boards/ebyte/index.rst new file mode 100644 index 00000000000000..b1a2b8ae327692 --- /dev/null +++ b/boards/ebyte/index.rst @@ -0,0 +1,10 @@ +.. _boards-ebyte: + +Chengdu Ebyte Electronic Technology +################################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/efinix/index.rst b/boards/efinix/index.rst new file mode 100644 index 00000000000000..901246a75a4b49 --- /dev/null +++ b/boards/efinix/index.rst @@ -0,0 +1,10 @@ +.. _boards-efinix: + +Efinix, Inc. +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 b/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 new file mode 100644 index 00000000000000..3b3f710bc79b7d --- /dev/null +++ b/boards/efinix/titanium_ti60_f225/Kconfig.titanium_ti60_f225 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TITANIUM_TI60_F225 + select SOC_EFINIX_SAPPHIRE diff --git a/boards/efinix/titanium_ti60_f225/board.yml b/boards/efinix/titanium_ti60_f225/board.yml new file mode 100644 index 00000000000000..7daa700f0b3895 --- /dev/null +++ b/boards/efinix/titanium_ti60_f225/board.yml @@ -0,0 +1,5 @@ +board: + name: titanium_ti60_f225 + vendor: efinix + socs: + - name: efinix_sapphire diff --git a/boards/riscv/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg b/boards/efinix/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg similarity index 100% rename from boards/riscv/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg rename to boards/efinix/titanium_ti60_f225/doc/img/Ti60-BGA225-board-block-diagram.jpg diff --git a/boards/riscv/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg b/boards/efinix/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg similarity index 100% rename from boards/riscv/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg rename to boards/efinix/titanium_ti60_f225/doc/img/ti60f225-board-top.jpg diff --git a/boards/riscv/titanium_ti60_f225/doc/index.rst b/boards/efinix/titanium_ti60_f225/doc/index.rst similarity index 100% rename from boards/riscv/titanium_ti60_f225/doc/index.rst rename to boards/efinix/titanium_ti60_f225/doc/index.rst diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.dts b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.dts similarity index 100% rename from boards/riscv/titanium_ti60_f225/titanium_ti60_f225.dts rename to boards/efinix/titanium_ti60_f225/titanium_ti60_f225.dts diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225.yaml b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225.yaml similarity index 100% rename from boards/riscv/titanium_ti60_f225/titanium_ti60_f225.yaml rename to boards/efinix/titanium_ti60_f225/titanium_ti60_f225.yaml diff --git a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig similarity index 78% rename from boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig rename to boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig index 0608a8e8953741..e540d6c5bac797 100644 --- a/boards/riscv/titanium_ti60_f225/titanium_ti60_f225_defconfig +++ b/boards/efinix/titanium_ti60_f225/titanium_ti60_f225_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2023 Efinix Inc. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_EFINIX_SAPPHIRE=y -CONFIG_BOARD_TITANIUM_TI60_F225=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/electronut_labs/index.rst b/boards/electronut_labs/index.rst new file mode 100644 index 00000000000000..065a52cc96cc68 --- /dev/null +++ b/boards/electronut_labs/index.rst @@ -0,0 +1,10 @@ +.. _boards-electronut-labs: + +Electronut Labs +############### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/nrf52840_blip/Kconfig b/boards/electronut_labs/nrf52840_blip/Kconfig similarity index 100% rename from boards/arm/nrf52840_blip/Kconfig rename to boards/electronut_labs/nrf52840_blip/Kconfig diff --git a/boards/electronut_labs/nrf52840_blip/Kconfig.defconfig b/boards/electronut_labs/nrf52840_blip/Kconfig.defconfig new file mode 100644 index 00000000000000..91ff6042e0cfe7 --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Electronut Labs Blip board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_BLIP + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_BLIP diff --git a/boards/electronut_labs/nrf52840_blip/Kconfig.nrf52840_blip b/boards/electronut_labs/nrf52840_blip/Kconfig.nrf52840_blip new file mode 100644 index 00000000000000..b28eaadba83dea --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/Kconfig.nrf52840_blip @@ -0,0 +1,7 @@ +# Electronut Labs Blip board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_BLIP + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_blip/board.cmake b/boards/electronut_labs/nrf52840_blip/board.cmake similarity index 100% rename from boards/arm/nrf52840_blip/board.cmake rename to boards/electronut_labs/nrf52840_blip/board.cmake diff --git a/boards/electronut_labs/nrf52840_blip/board.yml b/boards/electronut_labs/nrf52840_blip/board.yml new file mode 100644 index 00000000000000..3964f015c2fc91 --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_blip + vendor: electronut + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_blip/doc/img/nrf52840_blip.jpg b/boards/electronut_labs/nrf52840_blip/doc/img/nrf52840_blip.jpg similarity index 100% rename from boards/arm/nrf52840_blip/doc/img/nrf52840_blip.jpg rename to boards/electronut_labs/nrf52840_blip/doc/img/nrf52840_blip.jpg diff --git a/boards/electronut_labs/nrf52840_blip/doc/index.rst b/boards/electronut_labs/nrf52840_blip/doc/index.rst new file mode 100644 index 00000000000000..768168da60e3d5 --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/doc/index.rst @@ -0,0 +1,196 @@ +.. _nrf52840_blip: + +Electronut Labs Blip +#################### + +Overview +******** + +The Electronut Labs Blip hardware provides support for the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52840_blip.jpg + :align: center + :alt: Electronut Labs Blip + + Electronut Labs Blip (Credit: Electronut Labs) + +More information about the board is available at https://github.com/electronut/ElectronutLabs-blip. + +Hardware +******** + +Blip has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The nrf52840_blip board configuration supports the following +hardware features currently: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (red) = P0.14 +* LED3 (blue) = P0.15 + +Push buttons +------------ + +* BUTTON1 = SW1 = P1.07 +* Reset = SW5 = P0.18 (can be used as GPIO also) + +UART +---- + +BMP does not support hardware flow control, so only RX/TX pins are connected. + +* TX = P0.6 +* RX = P0.8 + +I2C +--- + +I2C pins connected to onboard sensors: + +* SDA = P0.12 +* SCL = P0.11 + +SPI +--- + +* SCK = P0.25 +* MOSI = P1.02 +* MISO = P0.24 + +MicroSD is connected to these pins, and CS pin is connected to P0.17. + +Programming and Debugging +************************* + +Applications for the ``nrf52840_blip`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); The onboard Black Magic +Probe debugger presents itself as two USB-serial ports. On Linux, +they may come up as ``/dev/ttyACM0`` and ``/dev/ttyACM1``. The first +one of these (``/dev/ttyACM0`` here) is the debugger port. +GDB can directly connect to this port without requiring a GDB server by specifying +``target external /dev/ttyACM0``. The second port acts as a +serial port, connected to the SoC. + +Flashing +======== + +Applications are flashed and run as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the serial port of Black Magic Probe. +For example, under Linux, :code:`/dev/ttyACM1`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52840_blip + :goals: build flash + +Debugging +========= + +Debug and attach configurations are available using Black Magic Probe, and +``ninja debug``, or ``ninja attach`` (or with ``make``) are available. + +NOTE: You may need to press the reset button once after using ``ninja flash`` +to start executing the code. (not required with ``debug`` or ``attach``) + + +Testing the LEDs and buttons in the nRF52840 PDK +************************************************ + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/electronut_labs/nrf52840_blip/nrf52840_blip.dts`. + + +References +********** + +.. target-notes:: + +.. _Electronut Labs website: https://electronut.in +.. _Store link: https://www.tindie.com/stores/ElectronutLabs/ +.. _Blip website: https://github.com/electronut/ElectronutLabs-blip +.. _Schematic: https://github.com/electronut/ElectronutLabs-blip/blob/master/blip_v0.3_schematic.pdf +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ +.. _Black Magic Probe website: https://github.com/blacksphere/blackmagic diff --git a/boards/arm/nrf52840_blip/nrf52840_blip-pinctrl.dtsi b/boards/electronut_labs/nrf52840_blip/nrf52840_blip-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_blip/nrf52840_blip-pinctrl.dtsi rename to boards/electronut_labs/nrf52840_blip/nrf52840_blip-pinctrl.dtsi diff --git a/boards/arm/nrf52840_blip/nrf52840_blip.dts b/boards/electronut_labs/nrf52840_blip/nrf52840_blip.dts similarity index 100% rename from boards/arm/nrf52840_blip/nrf52840_blip.dts rename to boards/electronut_labs/nrf52840_blip/nrf52840_blip.dts diff --git a/boards/arm/nrf52840_blip/nrf52840_blip.yaml b/boards/electronut_labs/nrf52840_blip/nrf52840_blip.yaml similarity index 100% rename from boards/arm/nrf52840_blip/nrf52840_blip.yaml rename to boards/electronut_labs/nrf52840_blip/nrf52840_blip.yaml diff --git a/boards/electronut_labs/nrf52840_blip/nrf52840_blip_defconfig b/boards/electronut_labs/nrf52840_blip/nrf52840_blip_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/electronut_labs/nrf52840_blip/nrf52840_blip_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl654_usb/pre_dt_board.cmake b/boards/electronut_labs/nrf52840_blip/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl654_usb/pre_dt_board.cmake rename to boards/electronut_labs/nrf52840_blip/pre_dt_board.cmake diff --git a/boards/arm/nrf52840_papyr/Kconfig b/boards/electronut_labs/nrf52840_papyr/Kconfig similarity index 100% rename from boards/arm/nrf52840_papyr/Kconfig rename to boards/electronut_labs/nrf52840_papyr/Kconfig diff --git a/boards/electronut_labs/nrf52840_papyr/Kconfig.defconfig b/boards/electronut_labs/nrf52840_papyr/Kconfig.defconfig new file mode 100644 index 00000000000000..94d55d43358105 --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Electronut Labs Papyr board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_PAPYR + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_PAPYR diff --git a/boards/electronut_labs/nrf52840_papyr/Kconfig.nrf52840_papyr b/boards/electronut_labs/nrf52840_papyr/Kconfig.nrf52840_papyr new file mode 100644 index 00000000000000..f0825d7825f9a2 --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/Kconfig.nrf52840_papyr @@ -0,0 +1,7 @@ +# Electronut Labs Papyr board configuration + +# Copyright (c) 2018 Electronut Labs +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_PAPYR + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_papyr/board.cmake b/boards/electronut_labs/nrf52840_papyr/board.cmake similarity index 100% rename from boards/arm/nrf52840_papyr/board.cmake rename to boards/electronut_labs/nrf52840_papyr/board.cmake diff --git a/boards/electronut_labs/nrf52840_papyr/board.yml b/boards/electronut_labs/nrf52840_papyr/board.yml new file mode 100644 index 00000000000000..fcb089ad625f27 --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_papyr + vendor: electronut + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_papyr/doc/img/nrf52840_papyr.jpg b/boards/electronut_labs/nrf52840_papyr/doc/img/nrf52840_papyr.jpg similarity index 100% rename from boards/arm/nrf52840_papyr/doc/img/nrf52840_papyr.jpg rename to boards/electronut_labs/nrf52840_papyr/doc/img/nrf52840_papyr.jpg diff --git a/boards/arm/nrf52840_papyr/doc/nrf52840_papyr.rst b/boards/electronut_labs/nrf52840_papyr/doc/nrf52840_papyr.rst similarity index 100% rename from boards/arm/nrf52840_papyr/doc/nrf52840_papyr.rst rename to boards/electronut_labs/nrf52840_papyr/doc/nrf52840_papyr.rst diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi rename to boards/electronut_labs/nrf52840_papyr/nrf52840_papyr-pinctrl.dtsi diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr.dts b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.dts similarity index 100% rename from boards/arm/nrf52840_papyr/nrf52840_papyr.dts rename to boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.dts diff --git a/boards/arm/nrf52840_papyr/nrf52840_papyr.yaml b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.yaml similarity index 100% rename from boards/arm/nrf52840_papyr/nrf52840_papyr.yaml rename to boards/electronut_labs/nrf52840_papyr/nrf52840_papyr.yaml diff --git a/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr_defconfig b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/electronut_labs/nrf52840_papyr/nrf52840_papyr_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/blueclover_plt_demo_v2_nrf52832/pre_dt_board.cmake b/boards/electronut_labs/nrf52840_papyr/pre_dt_board.cmake similarity index 100% rename from boards/arm/blueclover_plt_demo_v2_nrf52832/pre_dt_board.cmake rename to boards/electronut_labs/nrf52840_papyr/pre_dt_board.cmake diff --git a/boards/element14/index.rst b/boards/element14/index.rst new file mode 100644 index 00000000000000..fbd25a3c5a8a4e --- /dev/null +++ b/boards/element14/index.rst @@ -0,0 +1,10 @@ +.. _boards-element-14: + +Element 14 +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/element14/warp7/Kconfig.defconfig b/boards/element14/warp7/Kconfig.defconfig new file mode 100644 index 00000000000000..b73424093e074e --- /dev/null +++ b/boards/element14/warp7/Kconfig.defconfig @@ -0,0 +1,23 @@ +# WaRP7 iMX7S M4 board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WARP7 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +config FXAS21002_DRDY_INT1 + default y + depends on FXAS21002_TRIGGER + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_WARP7 diff --git a/boards/element14/warp7/Kconfig.warp7 b/boards/element14/warp7/Kconfig.warp7 new file mode 100644 index 00000000000000..438b4807d0710e --- /dev/null +++ b/boards/element14/warp7/Kconfig.warp7 @@ -0,0 +1,7 @@ +# Copyright (c) 2018, Diego Sueiro +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WARP7 + select SOC_PART_NUMBER_MCIMX7S3DVK08SA + select SOC_MCIMX7D_M4 if BOARD_WARP7_MCIMX7D_M4 diff --git a/boards/element14/warp7/board.yml b/boards/element14/warp7/board.yml new file mode 100644 index 00000000000000..99b037ded48b17 --- /dev/null +++ b/boards/element14/warp7/board.yml @@ -0,0 +1,5 @@ +board: + name: warp7 + vendor: element14 + socs: + - name: mcimx7d diff --git a/boards/element14/warp7/doc/index.rst b/boards/element14/warp7/doc/index.rst new file mode 100644 index 00000000000000..e55de8a80e3ed3 --- /dev/null +++ b/boards/element14/warp7/doc/index.rst @@ -0,0 +1,345 @@ +.. _warp7: + +WaRP7 - Next Generation IoT and Wearable Development Platform +############################################################# + +Overview +******** + +The i.MX7S SoC is a Hybrid multi-core processor composed of Single Cortex A7 +core and Single Cortex M4 core. +Zephyr was ported to run on the M4 core. In a later release, it will also +communicate with the A7 core (running Linux) via RPmsg. + + +.. image:: warp7.jpg + :align: center + :alt: WaRP7-iMX7S + +Hardware +******** + +The WaRP7 Platform is composed of a CPU and IO board. + +WaRP7 IO Board +============== + +- 6-axis Accelerometer Magnetometer: NXP FXOS8700CQ (I2C4 interface) +- 3-axis Gyroscope: NXP FXAS21002C (I2C4 interface) +- Altimeter: NXP MPL3115A2 (I2C4 interface) +- NXP NTAG NT3H1101 (I2C2 interface) +- Audio Codec: NXP SGTL5000 (I2C4 and SAI1 interfaces) +- S1 - Reset Button (POR_B signal) +- S2 - User Defined button (ENET1_RD1/GPIO7_IO1 signal) +- S3 - On/Off (MX7_ONOFF signal) +- Board to board connector (34 configurable pins) +- mikroBUS expansion connector +- 10-pin needle JTAG Connector +- Debug USB exposing two UARTs (UART1 for A7 and UART2 for M4) +- MIPI DSI 1 lane Connector +- LCD Touch Connector (I2C2 interface) +- Audio Jack: Mic and Stereo Headphone + +WaRP7 CPU Board +=============== + +- CPU i.MX7 Solo with a Single Cortex A7 (800MHz) core and + Single Cortex M4 (200MHz) core +- Memory + + - RAM -> A7: 4GB (Kingston 08EMCP04) + - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A7: 8GB eMMC (Kingston 08EMCP04) +- Multimedia + + - MIPI CSI 1 lane connector with 5MP OV5640 camera module (I2C2 interface) +- Connectivity + + - Board to board connector (34 configurable pins) + - Micro USB 2.0 OTG connector (USB_OTG1 interface) + - Murata Type 1DX Wi-Fi IEEE 802.11b/g/n and Bluetooth 4.1 plus EDR + (SD1, UART3 SAI2 interfaces) +- Li-ion/Li-polymer Battery Charger: NXP BC3770 (I2C1 interface) +- Power management integrated circuit (PMIC): NXP PF3000 (I2C1 interface) + + +For more information about the i.MX7 SoC and WaRP7, see these references: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Solo Datasheet`_ +- `i.MX 7 Solo Reference Manual`_ +- `WaRP7 Site`_ +- `WaRP7 Quick Start Guide`_ +- `WaRP7 User Guide`_ +- `WaRP7 GitHub repository`_ + +Supported Features +================== + +The WaRP7 configuration supports the following hardware features on the +Cortex M4 Core: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | +| | | fxas21002 polling; | +| | | fxas21002 trigger; | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The WaRP7 board Board was tested with the following pinmux controller +configuration. + ++---------------+---------------------+--------------------------------+ +| Board Name | SoC Name | Usage | ++===============+=====================+================================+ +| FT_TX2 | UART2_TXD | UART Console | ++---------------+---------------------+--------------------------------+ +| FT_RX2 | UART2_RXD | UART Console | ++---------------+---------------------+--------------------------------+ +| MKBUS_TX | UART6_TXD | UART | ++---------------+---------------------+--------------------------------+ +| MKBUS_RX | UART6_RXD | UART | ++---------------+---------------------+--------------------------------+ +| S2 | ENET1_RD1/GPIO7_IO1 | SW0 | ++---------------+---------------------+--------------------------------+ +| I2C4_SDA | I2C4_SDA | I2C / FXOS8700 / FXAS21002 | ++---------------+---------------------+--------------------------------+ +| I2C4_SCL | I2C4_SCL | I2C / FXOS8700 / FXAS21002 | ++---------------+---------------------+--------------------------------+ +| SENSOR_INT_B | ENET1_RD0/GPIO7_IO0 | FXOS8700 INT1 / FXAS21002 INT1 | ++---------------+---------------------+--------------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7S SoC has seven UARTs. The number 2 is configured for the console and +the number 6 is used in the mikroBUS connector. + +Programming and Debugging +************************* + +The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by +the A7 core. The A7 core is responsible to load the M4 binary application into +the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and +get the M4 out of reset. +The A7 can perform these steps at bootloader level or after the Linux system +has booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and +M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + + +References +========== + +- `i.MX 7 Solo Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) +- `Toradex Wiki`_ + + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4.dts` with +"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available +configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from A7 using +u-boot. + +Connect both micro USB interfaces into the PC. In one USB interface you will +have 2 USB serial ports, the first one is the A7 console and the second is the +M4 console for Zephyr with both configured to work at 115200 8N1. +The other USB interface is used to power the CPU and IO boards and is connected +to the USB OTG interface of the i.MX7S. + +After powering up the platform stop the u-boot execution on the A7 core and +expose the eMMC as mass storage with the following command in the u-boot +prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT +partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the +u-boot prompt. +Set the u-boot environment variables and run the zephyr.bin from the +appropriated memory configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + + +Debugging +========= + +Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. + +To run Zephyr Binary using J-Link, create the following script to get the +Program Counter and Stack Pointer from ``zephyr.bin``. + +get-pc-sp.sh: +.. code-block:: console + + #!/bin/sh + + firmware=$1 + + pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') + sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') + + echo pc=$pc + echo sp=$sp + + +Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` +.. code-block:: console + + pc=00900f01 + sp=00905020 + +Plug in the J-Link into the board and PC and run the J-Link command line tool: + +.. code-block:: console + + /usr/bin/JLinkExe -device Cortex-M4 -if JTAG \ + -speed 4000 -autoconnect 1 -jtagconf -1,-1 \ + -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript + +The following steps are necessary to run the zephyr.bin: + +1. Put the M4 core in reset +2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) +3. Set PC (Program Counter) +4. Set SP (Stack Pointer) +5. Get the M4 core out of reset + +Issue the following commands inside J-Link commander: + +.. code-block:: console + + w4 0x3039000C 0xAC + loadfile zephyr.bin,0x00900000 + w4 0x00180000 00900f01 + w4 0x00180004 00905020 + w4 0x3039000C 0xAA + +With these mechanisms, applications for the ``warp7`` board +configuration can be built and debugged in the usual way (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _WaRP7 Site: + https://www.element14.com/warp7 + +.. _WaRP7 User Guide: + https://github.com/WaRP7/WaRP7-User-Guide/releases/download/v1.3/User_Guide_Manual_v1-3.pdf + +.. _WaRP7 Quick Start Guide: + https://www.nxp.com/docs/en/supporting-information/WARP7-LEAFLET-QSG.pdf + +.. _WaRP7 GitHub repository: + https://github.com/WaRP7 + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Solo Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7SCEC.pdf + +.. _i.MX 7 Solo Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7SRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/warp7_m4/doc/warp7_m4.jpg b/boards/element14/warp7/doc/warp7.jpg similarity index 100% rename from boards/arm/warp7_m4/doc/warp7_m4.jpg rename to boards/element14/warp7/doc/warp7.jpg diff --git a/boards/arm/warp7_m4/warp7_m4-pinctrl.dtsi b/boards/element14/warp7/warp7-pinctrl.dtsi similarity index 100% rename from boards/arm/warp7_m4/warp7_m4-pinctrl.dtsi rename to boards/element14/warp7/warp7-pinctrl.dtsi diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.dts b/boards/element14/warp7/warp7_mcimx7d_m4.dts new file mode 100644 index 00000000000000..5947f86898a7e9 --- /dev/null +++ b/boards/element14/warp7/warp7_mcimx7d_m4.dts @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2018, Diego Sueiro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "warp7-pinctrl.dtsi" +#include + +/ { + model = "WaRP7 IMX7S board"; + compatible = "nxp,mcimx7d_m4"; + + aliases { + sw0 = &user_switch_1; + magn0 = &fxos8700; + accel0 = &fxos8700; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_switch_1: user_sw_1 { + gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; + label = "User SW1"; + zephyr,code = ; + }; + }; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&uart6 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart6_default>; + pinctrl-names = "default"; +}; + +&gpio7 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + status = "okay"; + pinctrl-0 = <&i2c4_default>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + }; + + fxas21002@20 { + compatible = "nxp,fxas21002"; + reg = <0x20>; + int1-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + }; + +}; + +&mub { + status = "okay"; +}; diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.yaml b/boards/element14/warp7/warp7_mcimx7d_m4.yaml new file mode 100644 index 00000000000000..96a7e7fbca84e9 --- /dev/null +++ b/boards/element14/warp7/warp7_mcimx7d_m4.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2018, Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: warp7/mcimx7d/m4 +name: WaRP7 IMX7S +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - gpio + - i2c +vendor: nxp diff --git a/boards/element14/warp7/warp7_mcimx7d_m4_defconfig b/boards/element14/warp7/warp7_mcimx7d_m4_defconfig new file mode 100644 index 00000000000000..b62210da43e09f --- /dev/null +++ b/boards/element14/warp7/warp7_mcimx7d_m4_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2018, Diego Sueiro +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/enclustra/mercury_xu/CMakeLists.txt b/boards/enclustra/mercury_xu/CMakeLists.txt new file mode 100644 index 00000000000000..f1877356e3ba6c --- /dev/null +++ b/boards/enclustra/mercury_xu/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board.c) diff --git a/boards/enclustra/mercury_xu/Kconfig.defconfig b/boards/enclustra/mercury_xu/Kconfig.defconfig new file mode 100644 index 00000000000000..3a6d5d2a524c79 --- /dev/null +++ b/boards/enclustra/mercury_xu/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2020, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MERCURY_XU + +config FLASH_SIZE + int + default 64 + +config FLASH_BASE_ADDRESS + default 0x08000000 + +endif diff --git a/boards/enclustra/mercury_xu/Kconfig.mercury_xu b/boards/enclustra/mercury_xu/Kconfig.mercury_xu new file mode 100644 index 00000000000000..0cc9368f54f697 --- /dev/null +++ b/boards/enclustra/mercury_xu/Kconfig.mercury_xu @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MERCURY_XU + select SOC_XILINX_ZYNQMP_RPU diff --git a/boards/arm/mercury_xu/board.c b/boards/enclustra/mercury_xu/board.c similarity index 100% rename from boards/arm/mercury_xu/board.c rename to boards/enclustra/mercury_xu/board.c diff --git a/boards/enclustra/mercury_xu/board.yml b/boards/enclustra/mercury_xu/board.yml new file mode 100644 index 00000000000000..739a5c9585766e --- /dev/null +++ b/boards/enclustra/mercury_xu/board.yml @@ -0,0 +1,5 @@ +board: + name: mercury_xu + vendor: enclustra + socs: + - name: zynqmp_rpu diff --git a/boards/arm/mercury_xu/mercury_xu-pinctrl.dtsi b/boards/enclustra/mercury_xu/mercury_xu-pinctrl.dtsi similarity index 100% rename from boards/arm/mercury_xu/mercury_xu-pinctrl.dtsi rename to boards/enclustra/mercury_xu/mercury_xu-pinctrl.dtsi diff --git a/boards/arm/mercury_xu/mercury_xu.dts b/boards/enclustra/mercury_xu/mercury_xu.dts similarity index 100% rename from boards/arm/mercury_xu/mercury_xu.dts rename to boards/enclustra/mercury_xu/mercury_xu.dts diff --git a/boards/arm/mercury_xu/mercury_xu.yaml b/boards/enclustra/mercury_xu/mercury_xu.yaml similarity index 100% rename from boards/arm/mercury_xu/mercury_xu.yaml rename to boards/enclustra/mercury_xu/mercury_xu.yaml diff --git a/boards/enclustra/mercury_xu/mercury_xu_defconfig b/boards/enclustra/mercury_xu/mercury_xu_defconfig new file mode 100644 index 00000000000000..10ed71b13c9eff --- /dev/null +++ b/boards/enclustra/mercury_xu/mercury_xu_defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2020, Antmicro + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable timer +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 + +CONFIG_PINCTRL=y diff --git a/boards/enjoy_digital/index.rst b/boards/enjoy_digital/index.rst new file mode 100644 index 00000000000000..aedf86d9ecde84 --- /dev/null +++ b/boards/enjoy_digital/index.rst @@ -0,0 +1,10 @@ +.. _boards-enjoydigital: + +EnjoyDigital +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/enjoy_digital/litex_vexriscv/Kconfig.defconfig b/boards/enjoy_digital/litex_vexriscv/Kconfig.defconfig new file mode 100644 index 00000000000000..f48e777e7a7405 --- /dev/null +++ b/boards/enjoy_digital/litex_vexriscv/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LITEX_VEXRISCV + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_LITEX_VEXRISCV diff --git a/boards/enjoy_digital/litex_vexriscv/Kconfig.litex_vexriscv b/boards/enjoy_digital/litex_vexriscv/Kconfig.litex_vexriscv new file mode 100644 index 00000000000000..ae3a15d36856d4 --- /dev/null +++ b/boards/enjoy_digital/litex_vexriscv/Kconfig.litex_vexriscv @@ -0,0 +1,5 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LITEX_VEXRISCV + select SOC_LITEX_VEXRISCV diff --git a/boards/enjoy_digital/litex_vexriscv/board.yml b/boards/enjoy_digital/litex_vexriscv/board.yml new file mode 100644 index 00000000000000..18ea360bb83649 --- /dev/null +++ b/boards/enjoy_digital/litex_vexriscv/board.yml @@ -0,0 +1,5 @@ +board: + name: litex_vexriscv + vendor: litex + socs: + - name: litex_vexriscv diff --git a/boards/riscv/litex_vexriscv/doc/img/litex_vexriscv.jpg b/boards/enjoy_digital/litex_vexriscv/doc/img/litex_vexriscv.jpg similarity index 100% rename from boards/riscv/litex_vexriscv/doc/img/litex_vexriscv.jpg rename to boards/enjoy_digital/litex_vexriscv/doc/img/litex_vexriscv.jpg diff --git a/boards/riscv/litex_vexriscv/doc/img/symbiflow.svg b/boards/enjoy_digital/litex_vexriscv/doc/img/symbiflow.svg similarity index 100% rename from boards/riscv/litex_vexriscv/doc/img/symbiflow.svg rename to boards/enjoy_digital/litex_vexriscv/doc/img/symbiflow.svg diff --git a/boards/riscv/litex_vexriscv/doc/index.rst b/boards/enjoy_digital/litex_vexriscv/doc/index.rst similarity index 100% rename from boards/riscv/litex_vexriscv/doc/index.rst rename to boards/enjoy_digital/litex_vexriscv/doc/index.rst diff --git a/boards/riscv/litex_vexriscv/litex_vexriscv.dts b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv.dts similarity index 100% rename from boards/riscv/litex_vexriscv/litex_vexriscv.dts rename to boards/enjoy_digital/litex_vexriscv/litex_vexriscv.dts diff --git a/boards/riscv/litex_vexriscv/litex_vexriscv.yaml b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv.yaml similarity index 100% rename from boards/riscv/litex_vexriscv/litex_vexriscv.yaml rename to boards/enjoy_digital/litex_vexriscv/litex_vexriscv.yaml diff --git a/boards/riscv/litex_vexriscv/litex_vexriscv_defconfig b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv_defconfig similarity index 77% rename from boards/riscv/litex_vexriscv/litex_vexriscv_defconfig rename to boards/enjoy_digital/litex_vexriscv/litex_vexriscv_defconfig index b8730d07d06fa6..d51a5923ff8f0e 100644 --- a/boards/riscv/litex_vexriscv/litex_vexriscv_defconfig +++ b/boards/enjoy_digital/litex_vexriscv/litex_vexriscv_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_RISCV32_LITEX_VEXRISCV=y -CONFIG_BOARD_LITEX_VEXRISCV=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig new file mode 100644 index 00000000000000..7bb2bb0d629fd2 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROOM + select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig new file mode 100644 index 00000000000000..6da35bf9735f03 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/Kconfig.defconfig @@ -0,0 +1,26 @@ +# ESP32 board configuration + +# Copyright (c) 2017 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU + +if BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom b/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom new file mode 100644 index 00000000000000..44cd4bcd7dd0db --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/Kconfig.esp32_devkitc_wroom @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROOM + select SOC_ESP32_WROOM_32UE_N4 diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.sysbuild b/boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild similarity index 100% rename from boards/riscv/esp32c3_devkitm/Kconfig.sysbuild rename to boards/espressif/esp32_devkitc_wroom/Kconfig.sysbuild diff --git a/boards/xtensa/esp32_devkitc_wroom/board.cmake b/boards/espressif/esp32_devkitc_wroom/board.cmake similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/board.cmake rename to boards/espressif/esp32_devkitc_wroom/board.cmake diff --git a/boards/espressif/esp32_devkitc_wroom/board.yml b/boards/espressif/esp32_devkitc_wroom/board.yml new file mode 100644 index 00000000000000..42d9d88dc23889 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32_devkitc_wroom + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg b/boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg rename to boards/espressif/esp32_devkitc_wroom/doc/img/esp32_devkitc_wroom.jpg diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst new file mode 100644 index 00000000000000..7b0d7d8964cff2 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/doc/index.rst @@ -0,0 +1,215 @@ +.. _esp32_devkitc_wroom: + +ESP32-DEVKITC-WROOM +################### + +Overview +******** + +ESP32-DEVKITC-WROOM is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32-WROOM is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. [1]_ + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +.. figure:: img/esp32_devkitc_wroom.jpg + :align: center + :alt: ESP32-DEVKITC-WROOM + + ESP32-DevKitC-WROOM-32D DK + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32-DEVKITC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. + +Supported Features +================== + +Current Zephyr's ESP32-WROOM board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_devkitc_wroom + +Debugging +--------- + +ESP32-DEVKITC-WROOM support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wroom/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. [1] https://en.wikipedia.org/wiki/ESP32 +.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi rename to boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.dts new file mode 100644 index 00000000000000..c52b029ea552a3 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-DevkitC APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.yaml new file mode 100644 index 00000000000000..26d4e67df3fd1e --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_devkitc_wroom/esp32/appcpu +name: ESP32 DEVKITC WROOM APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..6caadbd90ce687 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_appcpu_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y +CONFIG_CONSOLE=n +CONFIG_SERIAL=n +CONFIG_UART_CONSOLE=n +CONFIG_GPIO=n diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.dts new file mode 100644 index 00000000000000..1708a7badf9878 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.dts @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_devkitc_wroom-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32-DevkitC PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; + cpu-power-states = <&light_sleep &deep_sleep>; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&psram0 { + status = "disabled"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.yaml new file mode 100644 index 00000000000000..88e22e7b170e90 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu.yaml @@ -0,0 +1,25 @@ +identifier: esp32_devkitc_wroom/esp32/procpu +name: ESP32-DevkitC-WROOM-32D +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu_defconfig new file mode 100644 index 00000000000000..3be2d9e39d5588 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_devkitc_wroom/support/openocd.cfg b/boards/espressif/esp32_devkitc_wroom/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/support/openocd.cfg rename to boards/espressif/esp32_devkitc_wroom/support/openocd.cfg diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig new file mode 100644 index 00000000000000..8c64a77ca46deb --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROVER + select SOC_ESP32_PROCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig b/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig new file mode 100644 index 00000000000000..ba249b4a0a6afb --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32_DEVKITC_WROVER_ESP32_PROCPU + +if BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP32_DEVKITC_WROVER_ESP32_APPCPU diff --git a/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover b/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover new file mode 100644 index 00000000000000..06cebcd58552a4 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/Kconfig.esp32_devkitc_wrover @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_DEVKITC_WROVER + select SOC_ESP32_WROVER_E_N4R8 diff --git a/boards/riscv/esp32c3_luatos_core/Kconfig.sysbuild b/boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild similarity index 100% rename from boards/riscv/esp32c3_luatos_core/Kconfig.sysbuild rename to boards/espressif/esp32_devkitc_wrover/Kconfig.sysbuild diff --git a/boards/xtensa/esp32_devkitc_wrover/board.cmake b/boards/espressif/esp32_devkitc_wrover/board.cmake similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/board.cmake rename to boards/espressif/esp32_devkitc_wrover/board.cmake diff --git a/boards/espressif/esp32_devkitc_wrover/board.yml b/boards/espressif/esp32_devkitc_wrover/board.yml new file mode 100644 index 00000000000000..e0eae97f70f25e --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32_devkitc_wrover + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg b/boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg rename to boards/espressif/esp32_devkitc_wrover/doc/img/esp32_devkitc_wrover.jpg diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst new file mode 100644 index 00000000000000..26f3a82e0110b4 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/doc/index.rst @@ -0,0 +1,296 @@ +.. _esp32_devkitc_wrover: + +ESP32-DEVKITC-WROVER +#################### + +Overview +******** + +ESP32 is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32 is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. [1]_ + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +.. figure:: img/esp32_devkitc_wrover.jpg + :align: center + :alt: ESP32-DEVKITC-WROVER + + ESP32-DevKitC-WROVER-IE + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32-DEVKITC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. + +Supported Features +================== + +Current Zephyr's ESP32-devkitc board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32_devkitc_wrover + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_devkitc_wrover + +Debugging +********* + +ESP32 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_devkitc_wrover/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. [1] https://en.wikipedia.org/wiki/ESP32 +.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi rename to boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.dts new file mode 100644 index 00000000000000..7298148a2c34d2 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-DevkitC WROVER-E APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.yaml new file mode 100644 index 00000000000000..8c8e8ae15778e7 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_devkitc_wrover/esp32/appcpu +name: ESP32-DevkitC-WROVER-E +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.dts new file mode 100644 index 00000000000000..60a063bc87561a --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.dts @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_devkitc_wrover-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32-DevkitC WROVER-E PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.yaml new file mode 100644 index 00000000000000..bf130d7d3a8cd5 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu.yaml @@ -0,0 +1,25 @@ +identifier: esp32_devkitc_wrover/esp32/procpu +name: ESP32-DevkitC-WROVER-E +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu_defconfig new file mode 100644 index 00000000000000..3be2d9e39d5588 --- /dev/null +++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_devkitc_wrover/support/openocd.cfg b/boards/espressif/esp32_devkitc_wrover/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/support/openocd.cfg rename to boards/espressif/esp32_devkitc_wrover/support/openocd.cfg diff --git a/boards/xtensa/esp32_ethernet_kit/CMakeLists.txt b/boards/espressif/esp32_ethernet_kit/CMakeLists.txt similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/CMakeLists.txt rename to boards/espressif/esp32_ethernet_kit/CMakeLists.txt diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig b/boards/espressif/esp32_ethernet_kit/Kconfig new file mode 100644 index 00000000000000..0df985354ccfe6 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_ETHERNET_KIT + select SOC_ESP32_PROCPU if BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig new file mode 100644 index 00000000000000..e7f2edb7c059f5 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/Kconfig.defconfig @@ -0,0 +1,33 @@ +# ESP32-ETHERNET-KIT board configuration + +# Copyright (c) 2022 Grant Ramsay +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU + +config ESP_SPIRAM + default y + +choice SPIRAM_TYPE + default SPIRAM_TYPE_ESPPSRAM64 +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32_ETHERNET_KIT_ESP32_PROCPU + +if BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP32_ETHERNET_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp32_ethernet_kit/Kconfig.esp32_ethernet_kit b/boards/espressif/esp32_ethernet_kit/Kconfig.esp32_ethernet_kit new file mode 100644 index 00000000000000..746c7763fdae6a --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/Kconfig.esp32_ethernet_kit @@ -0,0 +1,7 @@ +# ESP32-ETHERNET-KIT board configuration + +# Copyright (c) 2022 Grant Ramsay +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32_ETHERNET_KIT + select SOC_ESP32_WROVER_E_N4R8 diff --git a/boards/riscv/icev_wireless/Kconfig.sysbuild b/boards/espressif/esp32_ethernet_kit/Kconfig.sysbuild similarity index 100% rename from boards/riscv/icev_wireless/Kconfig.sysbuild rename to boards/espressif/esp32_ethernet_kit/Kconfig.sysbuild diff --git a/boards/riscv/esp32c3_devkitm/board.cmake b/boards/espressif/esp32_ethernet_kit/board.cmake similarity index 100% rename from boards/riscv/esp32c3_devkitm/board.cmake rename to boards/espressif/esp32_ethernet_kit/board.cmake diff --git a/boards/espressif/esp32_ethernet_kit/board.yml b/boards/espressif/esp32_ethernet_kit/board.yml new file mode 100644 index 00000000000000..747690f38a69f1 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32_ethernet_kit + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp32_ethernet_kit/board_init.c b/boards/espressif/esp32_ethernet_kit/board_init.c similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/board_init.c rename to boards/espressif/esp32_ethernet_kit/board_init.c diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-a-v1.2-layout.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-b-v1.0-layout.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-from-phy.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-rmii-clk-to-phy.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.1-block-diagram.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2-overview.jpg diff --git a/boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg b/boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg rename to boards/espressif/esp32_ethernet_kit/doc/img/esp32-ethernet-kit-v1.2.jpg diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst new file mode 100644 index 00000000000000..fb0bd9aa425343 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst @@ -0,0 +1,623 @@ +.. _esp32_ethernet_kit: + +ESP32-ETHERNET-KIT +################## + +The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables +Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide +more flexible power supply options, the ESP32-Ethernet-Kit also supports power +over Ethernet (PoE). + +.. _get-started-esp32-ethernet-kit-v1.2-overview: + +.. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg + :align: center + :alt: ESP32-Ethernet-Kit V1.2 + :figclass: align-center + + ESP32-Ethernet-Kit V1.2 Overview + +Overview +******** + +ESP32-Ethernet-Kit is an ESP32-based development board produced by +`Espressif `_. + +It consists of two development boards, the Ethernet board A and the PoE +board B. The `Ethernet board (A)`_ contains Bluetooth/Wi-Fi dual-mode +ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet +Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet +functionality. The A board can work independently, without the board B +installed. + +.. _get-started-esp32-ethernet-kit-v1.2: + +.. figure:: img/esp32-ethernet-kit-v1.2.jpg + :align: center + :alt: ESP32-Ethernet-Kit V1.2 + :figclass: align-center + + ESP32-Ethernet-Kit V1.2 + +For the application loading and monitoring, the Ethernet board (A) also +features FTDI FT2232H chip - an advanced multi-interface USB bridge. +This chip enables to use JTAG for direct debugging of ESP32 through the +USB interface without a separate JTAG debugger. + + +Functionality Overview +====================== + +The block diagram below shows the main components of ESP32-Ethernet-Kit +and their interconnections. + +.. figure:: img/esp32-ethernet-kit-v1.1-block-diagram.jpg + :align: center + :alt: ESP32-Ethernet-Kit block diagram + :figclass: align-center + + ESP32-Ethernet-Kit block diagram + + +Functional Description +---------------------- + +The following figures and tables describe the key components, interfaces, +and controls of the ESP32-Ethernet-Kit. + +.. _get-started-esp32-ethernet-kit-a-v1.2-layout: + + +Ethernet Board (A) +^^^^^^^^^^^^^^^^^^ + +.. figure:: img/esp32-ethernet-kit-a-v1.2-layout.jpg + :align: center + :alt: ESP32-Ethernet-Kit V1.2 + :figclass: align-center + + ESP32-Ethernet-Kit - Ethernet board (A) layout + +The table below provides description starting from the picture's top right +corner and going clockwise. + +.. list-table:: Table 1 Component Description + :widths: 40 150 + :header-rows: 1 + + * - Key Component + - Description + * - ESP32-WROVER-E + - This ESP32 module features 64-Mbit PSRAM for flexible extended storage + and data processing capabilities. + * - GPIO Header 2 + - Five unpopulated through-hole solder pads to provide access to selected + GPIOs of ESP32. For details, see `GPIO Header 2`_. + * - Function Switch + - A 4-bit DIP switch used to configure the functionality of selected GPIOs + of ESP32. For details see `Function Switch`_. + * - Tx/Rx LEDs + - Two LEDs to show the status of UART transmission. + * - FT2232H + - The FT2232H chip serves as a multi-protocol USB-to-serial bridge which + can be programmed and controlled via USB to provide communication with + ESP32. FT2232H also features USB-to-JTAG interface which is available + on channel A of the chip, while USB-to-serial is on channel B. + The FT2232H chip enhances user-friendliness in terms of application + development and debugging. See + `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. + * - USB Port + - USB interface. Power supply for the board as well as the communication + interface between a computer and the board. + * - Power Switch + - Power On/Off Switch. Toggling the switch to **5V0** position powers the + board on, toggling to **GND** position powers the board off. + * - 5V Input + - The 5 V power supply interface can be more convenient when the board is + operating autonomously (not connected to a computer). + * - 5V Power On LED + - This red LED turns on when power is supplied to the board, either from + USB or 5 V Input. + * - DC/DC Converter + - Provided DC 5 V to 3.3 V conversion, output current up to 2 A. + * - Board B Connectors + - A pair male and female header pins for mounting the `PoE board (B)`_ + * - IP101GRI (PHY) + - The physical layer (PHY) connection to the Ethernet cable is + implemented using the + `IP101GRI `_ + chip. The connection between PHY and ESP32 is done through the reduced + media-independent interface (RMII), a variant of the media-independent + interface `(MII) `_ + standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100 + Mbps. + * - RJ45 Port + - Ethernet network data transmission port. + * - Magnetics Module + - The Magnetics are part of the Ethernet specification to protect against + faults and transients, including rejection of common mode signals + between the transceiver IC and the cable. The magnetics also provide + galvanic isolation between the transceiver and the Ethernet device. + * - Link/Activity LEDs + - Two LEDs (green and red) that respectively indicate the "Link" and + "Activity" statuses of the PHY. + * - BOOT Button + - Download button. Holding down **BOOT** and then pressing **EN** + initiates Firmware Download mode for downloading firmware through the + serial port. + * - EN Button + - Reset button. + * - GPIO Header 1 + - This header provides six unpopulated through-hole solder pads connected + to spare GPIOs of ESP32. For details, see `GPIO Header 1`_. + +PoE Board (B) +^^^^^^^^^^^^^ + +This board coverts power delivered over the Ethernet cable (PoE) to provide a +power supply for the Ethernet board (A). The main components of the PoE board +(B) are shown on the block diagram under `Functionality Overview`_. + +The PoE board (B) has the following features: + +* Support for IEEE 802.3at +* Power output: 5 V, 1.4 A + +To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet +board (A) should be connected with an Ethernet cable to a switch that supports +PoE. When the Ethernet board (A) detects 5 V power output from the PoE board +(B), the USB power will be automatically cut off. + +.. figure:: img/esp32-ethernet-kit-b-v1.0-layout.jpg + :align: center + :alt: ESP32-Ethernet-Kit - PoE board (B) + :figclass: align-center + + ESP32-Ethernet-Kit - PoE board (B) layout + +.. list-table:: Table PoE board (B) + :widths: 40 150 + :header-rows: 1 + + * - Key Component + - Description + * - Board A Connector + - Four female (left) and four male (right) header pins for connecting the + PoE board (B) to `Ethernet board (A)`_. The pins on the left accept + power coming from a PoE switch. The pins on the right deliver 5 V power + supply to the Ethernet board (A). + * - External Power Terminals + - Optional power supply (26.6 ~ 54 V) to the PoE board (B). + +.. _get-started-esp32-ethernet-kit-v1.2-setup-options: + + +Setup Options +============= + +This section describes options to configure the ESP32-Ethernet-Kit hardware. + + +Function Switch +--------------- + +When in On position, this DIP switch is routing listed GPIOs to FT2232H to +provide JTAG functionality. When in Off position, the GPIOs may be used for +other purposes. + +======= ================ +DIP SW GPIO Pin +======= ================ + 1 GPIO13 + 2 GPIO12 + 3 GPIO15 + 4 GPIO14 +======= ================ + + +RMII Clock Selection +-------------------- + +The ethernet MAC and PHY under RMII working mode need a common 50 MHz +reference clock (i.e. RMII clock) that can be provided either externally, +or generated from internal ESP32 APLL (not recommended). + +.. note:: + + For additional information on the RMII clock selection, please refer to + `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, + sheet 2, location D2. + + +RMII Clock Sourced Externally by PHY +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the +IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency +multiplication of 25 MHz crystal connected to the PHY. For details, please see +the figure below. + +.. figure:: img/esp32-ethernet-kit-rmii-clk-from-phy.jpg + :align: center + :alt: RMII Clock from IP101GRI PHY + :figclass: align-center + + RMII Clock from IP101GRI PHY + +Please note that the PHY is reset on power up by pulling the RESET_N signal +down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable +PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter +download mode (when the clock signal of REF_CLK_50M is at a high logic level +during the GPIO0 power-up sampling phase). + + +RMII Clock Sourced Internally from ESP32's APLL +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Another option is to source the RMII Clock from internal ESP32 APLL, see +figure below. The clock signal coming from GPIO0 is first inverted, to account +for transmission line delay, and then supplied to the PHY. + +.. figure:: img/esp32-ethernet-kit-rmii-clk-to-phy.jpg + :align: center + :alt: RMII Clock from ESP Internal APLL + :figclass: align-center + + RMII Clock from ESP Internal APLL + +To implement this option, users need to remove or add some RC components on +the board. For details please refer to +`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, +sheet 2, location D2. Please note that if the APLL is already used for other +purposes (e.g. I2S peripheral), then you have no choice but use an external +RMII clock. + + +GPIO Allocation +--------------- + +This section describes allocation of ESP32 GPIOs to specific interfaces or +functions of the ESP32-Ethernet-Kit. + + +IP101GRI (PHY) Interface +^^^^^^^^^^^^^^^^^^^^^^^^ + +The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table +below. Implementation of ESP32-Ethernet-Kit defaults to Reduced +Media-Independent Interface (RMII). + +==== ================ =============== +No. ESP32 Pin (MAC) IP101GRI (PHY) +==== ================ =============== +*RMII Interface* +--------------------------------------- + 1 GPIO21 TX_EN + 2 GPIO19 TXD[0] + 3 GPIO22 TXD[1] + 4 GPIO25 RXD[0] + 5 GPIO26 RXD[1] + 6 GPIO27 CRS_DV + 7 GPIO0 REF_CLK +---- ---------------- --------------- +*Serial Management Interface* +--------------------------------------- + 8 GPIO23 MDC + 9 GPIO18 MDIO +---- ---------------- --------------- +*PHY Reset* +--------------------------------------- +10 GPIO5 Reset_N +==== ================ =============== + +.. note:: + + The allocation of all pins under the ESP32's *RMII Interface* is fixed and + cannot be changed either through IO MUX or GPIO Matrix. REF_CLK can only + be selected from GPIO0, GPIO16 or GPIO17 and it can not be changed through + GPIO Matrix. + + +GPIO Header 1 +^^^^^^^^^^^^^ + +This header exposes some GPIOs that are not used elsewhere on the +ESP32-Ethernet-Kit. + +==== ================ +No. ESP32 Pin +==== ================ + 1 GPIO32 + 2 GPIO33 + 3 GPIO34 + 4 GPIO35 + 5 GPIO36 + 6 GPIO39 +==== ================ + + +GPIO Header 2 +^^^^^^^^^^^^^ + +This header contains GPIOs that may be used for other purposes depending on +scenarios described in column "Comments". + +==== ========== ==================== +No. ESP32 Pin Comments +==== ========== ==================== + 1 GPIO17 See note 1 + 2 GPIO16 See note 1 + 3 GPIO4 + 4 GPIO2 + 5 GPIO13 See note 2 + 6 GPIO12 See note 2 + 7 GPIO15 See note 2 + 8 GPIO14 See note 2 + 9 GND Ground +10 3V3 3.3 V power supply +==== ========== ==================== + +.. note:: + + 1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the + ESP32-WROVER-E module and therefore not available for use. If you need + to use these pins, please solder a module without PSRAM memory inside, + e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. + + 2. Functionality depends on the settings of the `Function Switch`_. + + +GPIO Allocation Summary +^^^^^^^^^^^^^^^^^^^^^^^ + +.. csv-table:: + :header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments + + S_VP,,,,IO36, + S_VN,,,,IO39, + IO34,,,,IO34, + IO35,,,,IO35, + IO32,,,,IO32, + IO33,,,,IO33, + IO25,RXD[0],,,, + IO26,RXD[1],,,, + IO27,CRS_DV,,,, + IO14,,,TMS,IO14, + IO12,,,TDI,IO12, + IO13,,,TCK,IO13, + IO15,,,TDO,IO15, + IO2,,,,IO2, + IO0,REF_CLK,,,,See note 1 + IO4,,,,IO4, + IO16,,,,IO16 (NC),See note 2 + IO17,,,,IO17 (NC),See note 2 + IO5,Reset_N,,,,See note 1 + IO18,MDIO,,,, + IO19,TXD[0],,,, + IO21,TX_EN,,,, + RXD0,,RXD,,, + TXD0,,TXD,,, + IO22,TXD[1],,,, + IO23,MDC,,,, + +.. note:: + + 1. To prevent the power-on state of the GPIO0 from being affected by the + clock output on the PHY side, the RESET_N signal to PHY defaults to + low, turning the clock output off. After power-on you can control + RESET_N with GPIO5 to turn the clock output on. See also + `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off + the clock output through RESET_N, it is recommended to use a crystal + module that can be disabled/enabled externally. Similarly like when + using RESET_N, the oscillator module should be disabled by default and + turned on by ESP32 after power-up. For a reference design please see + `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. + + 2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the + ESP32-WROVER-E module and therefore not available for use. If you need + to use these pins, please solder a module without PSRAM memory inside, + e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32_ethernet_kit + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32_ethernet_kit`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32_ethernet_kit + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32_ethernet_kit/esp32/procpu + :goals: debug + + +Enabling Ethernet +***************** + +Enable Ethernet MAC, PHY and MDIO; add these to your device tree overlay: + +.. code-block:: devicetree + + ð { + status = "okay"; + }; + + &phy { + status = "okay"; + }; + + &mdio { + status = "okay"; + }; + +Enable Ethernet in KConfig: + +.. code-block:: cfg + + CONFIG_ETH_ESP32=y + CONFIG_NETWORKING=y + CONFIG_NET_L2_ETHERNET=y + +Board Init +========== + +RESET_N (GPIO5) is automatically set high to enable the Ethernet PHY +during board initialization (board_init.c) + +Related Documents +***************** + +* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic `_ (PDF) +* `ESP32-Ethernet-Kit PoE Board (B) Schematic `_ (PDF) +* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) PCB Layout `_ (PDF) +* `ESP32-Ethernet-Kit PoE Board (B) PCB Layout `_ (PDF) +* `ESP32 Datasheet `_ (PDF) +* `ESP32-WROVER-E Datasheet `_ (PDF) +* `OpenOCD ESP32 `_ diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi rename to boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.dts new file mode 100644 index 00000000000000..c5e1217b25c561 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-Ethernet-Kit APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.yaml b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.yaml new file mode 100644 index 00000000000000..1984dea8da3c27 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32_ethernet_kit/esp32/appcpu +name: ESP32 ETHERNET KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.dts new file mode 100644 index 00000000000000..7e8310c9605b4a --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.dts @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2022 Grant Ramsay + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32_ethernet_kit-pinctrl.dtsi" + +/ { + model = "Espressif ESP32-Ethernet-Kit PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + + phy: ethernet-phy@1 { + compatible = "ethernet-phy"; + status = "disabled"; + reg = <1>; + }; +}; + +ð { + phy-handle = <&phy>; +}; diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.yaml b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.yaml new file mode 100644 index 00000000000000..d7d4958d2e73f7 --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu.yaml @@ -0,0 +1,17 @@ +identifier: esp32_ethernet_kit/esp32/procpu +name: ESP32 ETHERNET KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - watchdog + - uart + - nvs + - pwm +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu_defconfig b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu_defconfig new file mode 100644 index 00000000000000..f029cac9e9e77b --- /dev/null +++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_ethernet_kit/support/openocd.cfg b/boards/espressif/esp32_ethernet_kit/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/support/openocd.cfg rename to boards/espressif/esp32_ethernet_kit/support/openocd.cfg diff --git a/boards/espressif/esp32c3_devkitm/Kconfig.defconfig b/boards/espressif/esp32c3_devkitm/Kconfig.defconfig new file mode 100644 index 00000000000000..9944bb871951b5 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/Kconfig.defconfig @@ -0,0 +1,15 @@ +# ESP32C3 devkitm board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/espressif/esp32c3_devkitm/Kconfig.esp32c3_devkitm b/boards/espressif/esp32c3_devkitm/Kconfig.esp32c3_devkitm new file mode 100644 index 00000000000000..854b9944ef4440 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/Kconfig.esp32c3_devkitm @@ -0,0 +1,7 @@ +# ESP32C3 devkitm board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_DEVKITM + select SOC_ESP32C3_MINI_N4 diff --git a/boards/riscv/stamp_c3/Kconfig.sysbuild b/boards/espressif/esp32c3_devkitm/Kconfig.sysbuild similarity index 100% rename from boards/riscv/stamp_c3/Kconfig.sysbuild rename to boards/espressif/esp32c3_devkitm/Kconfig.sysbuild diff --git a/boards/riscv/icev_wireless/board.cmake b/boards/espressif/esp32c3_devkitm/board.cmake similarity index 100% rename from boards/riscv/icev_wireless/board.cmake rename to boards/espressif/esp32c3_devkitm/board.cmake diff --git a/boards/espressif/esp32c3_devkitm/board.yml b/boards/espressif/esp32c3_devkitm/board.yml new file mode 100644 index 00000000000000..649dce34a7d026 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32c3_devkitm + vendor: espressif + socs: + - name: esp32c3 diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst new file mode 100644 index 00000000000000..379d2c310659b1 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/doc/index.rst @@ -0,0 +1,241 @@ +.. _esp32c3_devkitm: + +ESP32-C3 +######## + +Overview +******** + +ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. It strikes the right balance of power, +I/O capabilities and security, thus offering the optimal cost-effective +solution for connected devices. +The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, +but it also facilitates a variety of use-cases based on dual connectivity. [1]_ + +The features include the following: + +- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz +- 400 KB of internal RAM +- 802.11b/g/n/e/i +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh +- Various peripherals: + + - 12-bit ADC with up to 6 channels + - TWAI compatible with CAN bus 2.0 + - Temperature sensor + - 3x SPI + - 1x I2S + - 1x I2C + - 2x UART + - LED PWM with up to 6 channels + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +Supported Features +================== + +Current Zephyr's ESP32-C3-Devkitm board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32c3_devkitm + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: build + +The usual ``flash`` target will work with the ``esp32c3_devkitm`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_devkitm + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_devkitm + :goals: debug + +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-c3 +.. _ESP32C3 Devkitm User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html +.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi similarity index 100% rename from boards/riscv/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi rename to boards/espressif/esp32c3_devkitm/esp32c3_devkitm-pinctrl.dtsi diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts similarity index 98% rename from boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts rename to boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts index 6c390956e4894a..e636089ba03e3d 100644 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.dts +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts @@ -11,7 +11,7 @@ #include / { - model = "esp32c3_devkitm"; + model = "Espressif ESP32-DevkitM"; compatible = "espressif,esp32c3"; chosen { diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm.yaml b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml similarity index 100% rename from boards/riscv/esp32c3_devkitm/esp32c3_devkitm.yaml rename to boards/espressif/esp32c3_devkitm/esp32c3_devkitm.yaml diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig new file mode 100644 index 00000000000000..ef633ce56a18e2 --- /dev/null +++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_devkitm/support/openocd.cfg b/boards/espressif/esp32c3_devkitm/support/openocd.cfg similarity index 100% rename from boards/riscv/esp32c3_devkitm/support/openocd.cfg rename to boards/espressif/esp32c3_devkitm/support/openocd.cfg diff --git a/boards/espressif/esp32s2_saola/Kconfig.defconfig b/boards/espressif/esp32s2_saola/Kconfig.defconfig new file mode 100644 index 00000000000000..5beaa3e15b1724 --- /dev/null +++ b/boards/espressif/esp32s2_saola/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ESP32S2 Saola board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 32768 if WIFI + default 4096 diff --git a/boards/espressif/esp32s2_saola/Kconfig.esp32s2_saola b/boards/espressif/esp32s2_saola/Kconfig.esp32s2_saola new file mode 100644 index 00000000000000..f02ec0a49a063a --- /dev/null +++ b/boards/espressif/esp32s2_saola/Kconfig.esp32s2_saola @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_SAOLA + select SOC_ESP32S2_WROVER_N4R2 diff --git a/boards/riscv/xiao_esp32c3/Kconfig.sysbuild b/boards/espressif/esp32s2_saola/Kconfig.sysbuild similarity index 100% rename from boards/riscv/xiao_esp32c3/Kconfig.sysbuild rename to boards/espressif/esp32s2_saola/Kconfig.sysbuild diff --git a/boards/riscv/stamp_c3/board.cmake b/boards/espressif/esp32s2_saola/board.cmake similarity index 100% rename from boards/riscv/stamp_c3/board.cmake rename to boards/espressif/esp32s2_saola/board.cmake diff --git a/boards/espressif/esp32s2_saola/board.yml b/boards/espressif/esp32s2_saola/board.yml new file mode 100644 index 00000000000000..aafb5f3ee1efec --- /dev/null +++ b/boards/espressif/esp32s2_saola/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s2_saola + vendor: espressif + socs: + - name: esp32s2 diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst new file mode 100644 index 00000000000000..b329b45f682ced --- /dev/null +++ b/boards/espressif/esp32s2_saola/doc/index.rst @@ -0,0 +1,249 @@ +.. _esp32s2_saola: + +ESP32-S2 +######## + +Overview +******** + +ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and +cost-effective, with a high performance and a rich set of IO capabilities. [1]_ + +The features include the following: + +- RSA-3072-based secure boot +- AES-XTS-256-based flash encryption +- Protected private key and device secrets from software access +- Cryptographic accelerators for enhanced performance +- Protection against physical fault injection attacks +- Various peripherals: + + - 43x programmable GPIOs + - 14x configurable capacitive touch GPIOs + - USB OTG + - LCD interface + - camera interface + - SPI + - I2S + - UART + - ADC + - DAC + - LED PWM with up to 8 channels + +Supported Features +================== + +Current Zephyr's ESP32-S2-saola board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s2_saola + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: build + +The usual ``flash`` target will work with the ``esp32s2_saola`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s2_saola + +Debugging +********* + +ESP32-S2 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +The following table shows the pin mapping between ESP32-S2 board and JTAG interface. + ++---------------+-----------+ +| ESP32 pin | JTAG pin | ++===============+===========+ +| MTDO / GPIO40 | TDO | ++---------------+-----------+ +| MTDI / GPIO41 | TDI | ++---------------+-----------+ +| MTCK / GPIO39 | TCK | ++---------------+-----------+ +| MTMS / GPIO42 | TMS | ++---------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_saola + :goals: debug + +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html + + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-s2 +.. _ESP32-S2 Saola User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html +.. _ESP32S2 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _ESP32S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola-pinctrl.dtsi b/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s2_saola/esp32s2_saola-pinctrl.dtsi rename to boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola.dts b/boards/espressif/esp32s2_saola/esp32s2_saola.dts similarity index 98% rename from boards/xtensa/esp32s2_saola/esp32s2_saola.dts rename to boards/espressif/esp32s2_saola/esp32s2_saola.dts index 781f4b758d67f0..f7e73bb8f27555 100644 --- a/boards/xtensa/esp32s2_saola/esp32s2_saola.dts +++ b/boards/espressif/esp32s2_saola/esp32s2_saola.dts @@ -12,7 +12,7 @@ #include / { - model = "esp32s2_saola"; + model = "Espressif ESP32S2-Saola"; compatible = "espressif,esp32s2"; aliases { diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola.yaml b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml similarity index 100% rename from boards/xtensa/esp32s2_saola/esp32s2_saola.yaml rename to boards/espressif/esp32s2_saola/esp32s2_saola.yaml diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig b/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig new file mode 100644 index 00000000000000..5476839e2ba638 --- /dev/null +++ b/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_franzininho/support/openocd.cfg b/boards/espressif/esp32s2_saola/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s2_franzininho/support/openocd.cfg rename to boards/espressif/esp32s2_saola/support/openocd.cfg diff --git a/boards/espressif/esp32s3_devkitm/Kconfig b/boards/espressif/esp32s3_devkitm/Kconfig new file mode 100644 index 00000000000000..b4ccc062155f56 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_DEVKITM + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.defconfig b/boards/espressif/esp32s3_devkitm/Kconfig.defconfig new file mode 100644 index 00000000000000..1905ae5f5515ba --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/Kconfig.defconfig @@ -0,0 +1,26 @@ +# ESP32S3 DevKitM board configuration + +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU + +if BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU diff --git a/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm b/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm new file mode 100644 index 00000000000000..7b9f2a7d043072 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/Kconfig.esp32s3_devkitm @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_DEVKITM + select SOC_ESP32S3_MINI_N8 diff --git a/boards/xtensa/esp32_devkitc_wroom/Kconfig.sysbuild b/boards/espressif/esp32s3_devkitm/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32_devkitc_wroom/Kconfig.sysbuild rename to boards/espressif/esp32s3_devkitm/Kconfig.sysbuild diff --git a/boards/riscv/xiao_esp32c3/board.cmake b/boards/espressif/esp32s3_devkitm/board.cmake similarity index 100% rename from boards/riscv/xiao_esp32c3/board.cmake rename to boards/espressif/esp32s3_devkitm/board.cmake diff --git a/boards/espressif/esp32s3_devkitm/board.yml b/boards/espressif/esp32s3_devkitm/board.yml new file mode 100644 index 00000000000000..2d0195fc27dcdd --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s3_devkitm + vendor: espressif + socs: + - name: esp32s3 diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst new file mode 100644 index 00000000000000..5405100f36450d --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/doc/index.rst @@ -0,0 +1,286 @@ +.. _esp32s3_devkitm: + +ESP32S3-DevKitM +############### + +Overview +******** + +The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1 +or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi +and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_ + +Hardware +******** + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +ESP32-S3 DevKitM includes the following features: + +- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz +- Additional vector instructions support for AI acceleration +- 512KB of SRAM +- 384KB of ROM +- Wi-Fi 802.11b/g/n +- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate + +Digital interfaces: + +- 45 programmable GPIOs +- 4x SPI +- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 +- 1x DVP 8-bit ~16-bit camera interface +- 3x UART +- 2x I2C +- 2x I2S +- 1x RMT (TX/RX) +- 1x pulse counter +- LED PWM controller, up to 8 channels +- 1x full-speed USB OTG +- 1x USB Serial/JTAG controller +- 2x MCPWM +- 1x SDIO host controller with 2 slots +- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- Addressable RGB LED, driven by GPIO48. + +Analog interfaces: + +- 2x 12-bit SAR ADCs, up to 20 channels +- 1x temperature sensor +- 14x touch sensing IOs + +Timers: + +- 4x 54-bit general-purpose timers +- 1x 52-bit system timer +- 3x watchdog timers + +Low Power: + +- Power Management Unit with five power modes +- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) + +Asymmetric Multiprocessing (AMP) +******************************** + +ESP32S3-DevKitM allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core +architecture, each core can be enabled to execute customized tasks in stand-alone mode +and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +Supported Features +================== + +Current Zephyr's ESP32-S3-DevKitM board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s3_devkitm + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_devkitm`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_devkitm + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_devkitm/esp32s3/procpu + :goals: debug + +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html + +References +********** + +.. _ESP32-S3 DevKitM User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html +.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi rename to boards/espressif/esp32s3_devkitm/esp32s3_devkitm-pinctrl.dtsi diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.dts new file mode 100644 index 00000000000000..3815ebdacf9b8c --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Espressif ESP32S3-DevkitM APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.yaml new file mode 100644 index 00000000000000..7af60717bd440b --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_devkitm/esp32s3/appcpu +name: ESP32-S3 DevKitM APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.dts new file mode 100644 index 00000000000000..e0d4461a33bc02 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu.dts @@ -0,0 +1,183 @@ +/* + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp32s3_devkitm-pinctrl.dtsi" +#include +#include + +/ { + model = "Espressif ESP32S3-DevkitM PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + uart-0 = &uart0; + sw0 = &button0; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&touch { + debounce-interval-ms = <30>; + href-microvolt = <2700000>; + lref-microvolt = <500000>; + href-atten-microvolt = <1000000>; + filter-mode = ; + filter-debounce-cnt = <1>; + filter-noise-thr = ; + filter-jitter-step = <4>; + filter-smooth-level = ; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&usb_serial { + status = "disabled"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml new file mode 100644 index 00000000000000..f9e577353a95d8 --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_.yaml @@ -0,0 +1,23 @@ +identifier: esp32s3_devkitm/esp32s3/procpu +name: ESP32-S3 DevKitM PROCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - input +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_defconfig new file mode 100644 index 00000000000000..d789bab1824a6f --- /dev/null +++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_devkitm/support/openocd.cfg b/boards/espressif/esp32s3_devkitm/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s3_devkitm/support/openocd.cfg rename to boards/espressif/esp32s3_devkitm/support/openocd.cfg diff --git a/boards/espressif/esp_wrover_kit/Kconfig b/boards/espressif/esp_wrover_kit/Kconfig new file mode 100644 index 00000000000000..df5e831dad1dd2 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP_WROVER_KIT + select SOC_ESP32_PROCPU if BOARD_ESP_WROVER_KIT_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ESP_WROVER_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp_wrover_kit/Kconfig.defconfig b/boards/espressif/esp_wrover_kit/Kconfig.defconfig new file mode 100644 index 00000000000000..a05a1684d6b14f --- /dev/null +++ b/boards/espressif/esp_wrover_kit/Kconfig.defconfig @@ -0,0 +1,29 @@ +# ESP-WROVER-KIT board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP_WROVER_KIT_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +config DISK_DRIVER_SDMMC + default y + +endif # BOARD_ESP_WROVER_KIT_ESP32_PROCPU + +if BOARD_ESP_WROVER_KIT_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ESP_WROVER_KIT_ESP32_APPCPU diff --git a/boards/espressif/esp_wrover_kit/Kconfig.esp_wrover_kit b/boards/espressif/esp_wrover_kit/Kconfig.esp_wrover_kit new file mode 100644 index 00000000000000..a8ae97799706e8 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/Kconfig.esp_wrover_kit @@ -0,0 +1,7 @@ +# ESP-WROVER-KIT board configuration + +# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP_WROVER_KIT + select SOC_ESP32_WROVER_E_N4R8 diff --git a/boards/xtensa/esp32_devkitc_wrover/Kconfig.sysbuild b/boards/espressif/esp_wrover_kit/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32_devkitc_wrover/Kconfig.sysbuild rename to boards/espressif/esp_wrover_kit/Kconfig.sysbuild diff --git a/boards/xtensa/esp32_ethernet_kit/board.cmake b/boards/espressif/esp_wrover_kit/board.cmake similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/board.cmake rename to boards/espressif/esp_wrover_kit/board.cmake diff --git a/boards/espressif/esp_wrover_kit/board.yml b/boards/espressif/esp_wrover_kit/board.yml new file mode 100644 index 00000000000000..edfaae90477001 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: esp_wrover_kit + vendor: espressif + socs: + - name: esp32 diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-block-diagram.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp14.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-jtag.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-back.jpg diff --git a/boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg b/boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg similarity index 100% rename from boards/xtensa/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg rename to boards/espressif/esp_wrover_kit/doc/img/esp-wrover-kit-v4.1-layout-front.jpg diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst new file mode 100644 index 00000000000000..062038635051cc --- /dev/null +++ b/boards/espressif/esp_wrover_kit/doc/index.rst @@ -0,0 +1,658 @@ +.. _esp_wrover_kit: + +ESP-WROVER-KIT +############## + +Overview +******** + +ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif `_. + +ESP-WROVER-KIT features the following integrated components: + +- ESP32-WROVER-E module +- LCD screen +- MicroSD card slot + +Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface +USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface +without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and +cost-effective. + +Most of the ESP32 I/O pins are broken out to the board's pin headers for easy access. + +.. note:: + + ESP32's GPIO16 and GPIO17 are used as chip select and clock signals for PSRAM. By default, the two + GPIOs are not broken out to the board's pin headers in order to ensure reliable performance. + +Functionality Overview +********************** + +The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections. + +.. image:: img/esp-wrover-kit-block-diagram.jpg + :align: center + :alt: ESP-WROVER-KIT + +Functional Description +********************** + +The following two figures and the table below describe the key components, interfaces, and controls +of the ESP-WROVER-KIT board. + +.. figure:: img/esp-wrover-kit-v4.1-layout-front.jpg + :align: center + :alt: esp wrover front + + ESP-WROVER-KIT board layout - front + +.. _esp wrover back: + +.. figure:: img/esp-wrover-kit-v4.1-layout-back.jpg + :align: center + :alt: esp wrover back + + ESP-WROVER-KIT board layout - back + +The table below provides description in the following manner: +- Starting from the first picture’s top right corner and going clockwise +- Then moving on to the second picture + ++------------------+-------------------------------------------------------------------------+ +| Key Component | Description | ++==================+=========================================================================+ +| FT2232 | The FT2232 chip serves as a multi-protocol USB-to-serial bridge | +| | which can be programmed and controlled via USB to provide | +| | communication with ESP32. FT2232 also features USB-to-JTAG | +| | interface which is available on channel A of the chip, while USB-to- | +| | serial is on channel B. The FT2232 chip enhances user-friendliness in | +| | terms of application development and debugging. See `ESP-WROVER-KIT | +| | V4.1 schematic | +| | `_. | ++------------------+-------------------------------------------------------------------------+ +| 32.768 kHz | External precision 32.768 kHz crystal oscillator serves as a clock with | +| | low-power consumption while the chip is in Deep-sleep mode. | ++------------------+-------------------------------------------------------------------------+ +| 0R | Zero-ohm resistor intended as a placeholder for a current shunt, can | +| | be desoldered or replaced with a current shunt to facilitate the | +| | measurement of ESP32’s current consumption in different modes. | ++------------------+-------------------------------------------------------------------------+ +| ESP32-WROVER-E | This ESP32 module features 64-Mbit PSRAM for flexible extended | +| module | storage and data processing capabilities. | ++------------------+-------------------------------------------------------------------------+ +| Diagnostic LEDs | Four red LEDs connected to the GPIO pins of FT2232. Intended for | +| | future use. | ++------------------+-------------------------------------------------------------------------+ +| UART | Serial port. The serial TX/RX signals of FT2232 and ESP32 are broken | +| | out to the inward and outward sides of JP2 respectively. By default, | +| | these pairs of pins are connected with jumpers. To use ESP32’s serial | +| | interface, remove the jumpers and connect another external serial | +| | device to the respective pins. | ++------------------+-------------------------------------------------------------------------+ +| SPI | By default, ESP32 uses its SPI interface to access flash and PSRAM | +| | memory inside the module. Use these pins to connect ESP32 to | +| | another SPI device. In this case, an extra chip select (CS) signal is | +| | needed. Please note that the voltage of this interface is 3.3 V. | ++------------------+-------------------------------------------------------------------------+ +| CTS/RTS | Serial port flow control signals: the pins are not connected to the | +| | circuitry by default. To enable them, short the respective pins of JP14 | +| | with jumpers. | ++------------------+-------------------------------------------------------------------------+ +| JTAG | JTAG interface. JTAG signals of FT2232 and ESP32 are broken out to | +| | the inward and outward sides of JP2 respectively. By default, these | +| | pairs of pins are disconnected. To enable JTAG, short the respective | +| | pins with jumpers as shown in Section | +| | :ref:`Setup Options` | ++------------------+-------------------------------------------------------------------------+ +| USB Port | USB interface. Power supply for the board as well as the | +| | communication interface between a computer and the board. | ++------------------+-------------------------------------------------------------------------+ +| EN Button | Reset button. | ++------------------+-------------------------------------------------------------------------+ +| BOOT Button | Download button. Holding down Boot and then pressing EN initiates | +| | Firmware Download mode for downloading firmware through the | ++------------------+-------------------------------------------------------------------------+ +| Power Switch | Power On/Off Switch. Toggling toward the Boot button powers the | +| | board on, toggling away from Boot powers the board off. | ++------------------+-------------------------------------------------------------------------+ +| Power Selector | Power supply selector interface. The board can be powered either via | +| | USB or via the 5V Input interface. Select the power source with a | +| | jumper. For more details, see Section Setup Options, jumper header | +| | JP7. | ++------------------+-------------------------------------------------------------------------+ +| 5V input | 5V power supply interface for a standard coaxial power connector, | +| | 5.5 x 2.1 mm, center positive. This interface can be more convenient | +| | when the board is operating autonomously (not connected to a | +| | computer). | ++------------------+-------------------------------------------------------------------------+ +| 5V Power On LED | This red LED turns on when power is supplied to the board, either | +| | from USB or 5V Input. | ++------------------+-------------------------------------------------------------------------+ +| LDO | NCP1117(1A). 5V-to-3.3V LDO. NCP1117 can provide a maximum | +| | current of 1A. The LDO on the board has a fixed output voltage. | +| | Although, the user can install an LDO with adjustable output voltage. | +| | For details, please refer to `ESP-WROVER-KIT V4.1 schematic | +| | `_. | ++------------------+-------------------------------------------------------------------------+ +| Camera Connector | Camera interface, a standard OV7670 camera module. | ++------------------+-------------------------------------------------------------------------+ +| RGB LED | Red, green and blue (RGB) light emitting diodes (LEDs), can be | +| | controlled by pulse width modulation (PWM). | ++------------------+-------------------------------------------------------------------------+ +| I/O Connector | All the pins on the ESP32 module are broken out to pin headers. You | +| | can program ESP32 to enable multiple functions, such as PWM, ADC, | +| | DAC, I2C, I2S, SPI, etc. | ++------------------+-------------------------------------------------------------------------+ +| MicroSD Card | Useful for developing applications that access MicroSD card for data | +| Slot | storage and retrieval. | ++------------------+-------------------------------------------------------------------------+ +| LCD | Support for mounting and interfacing a 3.2” SPI (standard 4-wire | +| | Serial Peripheral Interface) LCD, as shown on figure | +| | :ref:`ESP-WROVER-KIT board layout - back` | ++------------------+-------------------------------------------------------------------------+ + +.. _setup options: + +Setup Options +************* + +There are three jumper blocks available to set up the board functionality. The most frequently +required options are listed in the table below. + +.. |jmpextpwr| image:: img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg + +.. |jmpusbpwr| image:: img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg + +.. |jmpjtag| image:: img/esp-wrover-kit-v4.1-jp2-jtag.jpg + +.. |jmpuart| image:: img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg + +.. |jmpctrl| image:: img/esp-wrover-kit-v4.1-jp14.jpg + ++------------------+--------------------------------------------------------------+ +| Header | Jumper Setting | Description of Functionality | ++========+================+=======================================================+ +| JP7 | |jmpextpwr| | Power ESP-WROVER-KIT via an external power supply | ++--------+----------------+-------------------------------------------------------+ +| JP7 | |jmpusbpwr| | Power ESP-WROVER-KIT via USB | ++--------+----------------+-------------------------------------------------------+ +| JP2 | |jmpjtag| | Enable JTAG functionality | ++--------+----------------+-------------------------------------------------------+ +| JP2 | |jmpuart| | Enable UART communication | ++--------+----------------+-------------------------------------------------------+ +| JP14 | |jmpctrl| | Enable RTS/CTS flow control for serial communication | ++--------+----------------+-------------------------------------------------------+ + +Allocation of ESP32 Pins +************************ + +Some pins / terminals of ESP32 are allocated for use with the onboard or external hardware. If +that hardware is not used, e.g., nothing is plugged into the Camera (JP4) header, then these +GPIOs can be used for other purposes. + +Some of the pins, such as GPIO0 or GPIO2, have multiple functions and some of them are shared +among onboard and external peripheral devices. Certain combinations of peripherals cannot work +together. For example, it is not possible to do JTAG debugging of an application that is using +SD card, because several pins are shared by JTAG and the SD card slot. + +In other cases, peripherals can coexist under certain conditions. This is applicable to, for +example, LCD screen and SD card that share only a single pin GPIO21. This pin is used to provide +D/C (Data / Control) signal for the LCD as well as the Card Detect signal read from the SD card +slot. If the card detect functionality is not essential, then it may be disabled by removing R167, +so both LCD and SD may operate together. + +For more details on which pins are shared among which peripherals, please refer to the table in +the next section. + +Main I/O Connector / JP1 +************************ + +The JP1 connector consists of 14x2 male pins whose functions are shown in the middle two “I/O” +columns of the table below. The two “Shared With” columns on both sides describe where else on +the board a certain GPIO is used. + ++-------------------+------+------+----------------------+ +| Shared With | I/O | I/O | Shared With | ++===================+======+======+======================+ +| n/a | 3.3V | GND | n/a | ++-------------------+------+------+----------------------+ +| NC/XTAL | IO32 | IO33 | NC/XTAL | ++-------------------+------+------+----------------------+ +| JTAG, MicroSD | IO12 | IO13 | JTAG, MicroSD | ++-------------------+------+------+----------------------+ +| JTAG, MicroSD | IO14 | IO27 | Camera | ++-------------------+------+------+----------------------+ +| Camera | IO26 | IO25 | Camera, LCD | ++-------------------+------+------+----------------------+ +| Camera | IO35 | IO34 | Camera | ++-------------------+------+------+----------------------+ +| Camera | IO39 | IO36 | Camera | ++-------------------+------+------+----------------------+ +| JTAG | EN | IO23 | Camera, LCD | ++-------------------+------+------+----------------------+ +| Camera, LCD | IO22 | IO21 | Camera, LCD, MicroSD | ++-------------------+------+------+----------------------+ +| Camera, LCD | IO19 | IO18 | Camera, LCD | ++-------------------+------+------+----------------------+ +| Camera, LCD | IO5 | IO17 | PSRAM | ++-------------------+------+------+----------------------+ +| PSRAM | IO16 | IO4 | LED, Camera, MicroSD | ++-------------------+------+------+----------------------+ +| Camera, LED, Boot | IO0 | IO2 | LED, MicroSD | ++-------------------+------+------+----------------------+ +| JTAG, MicroSD | IO15 | 5V | | ++-------------------+------+------+----------------------+ + +Legend: + + - NC/XTAL - 32.768 kHz Oscillator + - JTAG - JTAG / JP2 + - Boot - Boot button / SW2 + - Camera - Camera / JP4 + - LED - RGB LED + - MicroSD - MicroSD Card / J4 + - LCD - LCD / U5 + - PSRAM - ESP32-WROVER-E’s PSRAM + +32.768 kHz Oscillator +********************* + ++---+-----------+ +| . | ESP32 Pin | ++===+===========+ +| 1 | GPIO32 | ++---+-----------+ +| 2 | GPIO33 | ++---+-----------+ + +.. note:: + + Since GPIO32 and GPIO33 are connected to the oscillator by default, they are not connected to + the JP1 I/O connector to maintain signal integrity. This allocation may be changed from the + oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re- + soldering them to positions R12 / R24. + +SPI Flash / JP2 +*************** + ++---+--------------+ +| . | ESP32 Pin | ++===+==============+ +| 1 | CLK / GPIO6 | ++---+--------------+ +| 2 | SD0 / GPIO7 | ++---+--------------+ +| 3 | SD1 / GPIO8 | ++---+--------------+ +| 4 | SD2 / GPIO9 | ++---+--------------+ +| 5 | SD3 / GPIO10 | ++---+--------------+ +| 6 | CDM / GPIO11 | ++---+--------------+ + +.. important:: + The module’s flash bus is connected to the jumper block JP2 through zero-ohm resistors R140 ~ + R145. If the flash memory needs to operate at the frequency of 80 MHz, for reasons such as + improving the integrity of bus signals, you can desolder these resistors to disconnect the + module’s flash bus from the pin header JP2. + +JTAG / JP2 +********** + ++---+---------------+-------------+ +| . | ESP32 Pin | JTAG Signal | ++===+===============+=============+ +| 1 | EN | TRST_N | ++---+---------------+-------------+ +| 2 | MTMS / GPIO14 | TMS | ++---+---------------+-------------+ +| 3 | MTDO / GPIO15 | TDO | ++---+---------------+-------------+ +| 4 | MTDI / GPIO12 | TDI | ++---+---------------+-------------+ +| 5 | MTCK / GPIO13 | TCK | ++---+---------------+-------------+ + +Camera / JP4 +************ + ++----+-----------+-----------------------------+ +| . | ESP32 Pin | Camera Signal | ++====+===========+=============================+ +| 1 | n/a | 3.3V | ++----+-----------+-----------------------------+ +| 2 | n/a | Ground | ++----+-----------+-----------------------------+ +| 3 | GPIO27 | SIO_C / SCCB Clock | ++----+-----------+-----------------------------+ +| 4 | GPIO26 | SIO_D / SCCB Data | ++----+-----------+-----------------------------+ +| 5 | GPIO25 | VSYNC / Vertical Sync | ++----+-----------+-----------------------------+ +| 6 | GPIO23 | HREF / Horizontal Reference | ++----+-----------+-----------------------------+ +| 7 | GPIO22 | PCLK / Pixel Clock | ++----+-----------+-----------------------------+ +| 8 | GPIO21 | XCLK / System Clock | ++----+-----------+-----------------------------+ +| 9 | GPIO35 | D7 / Pixel Data Bit 7 | ++----+-----------+-----------------------------+ +| 10 | GPIO34 | D6 / Pixel Data Bit 6 | ++----+-----------+-----------------------------+ +| 11 | GPIO39 | D5 / Pixel Data Bit 5 | ++----+-----------+-----------------------------+ +| 12 | GPIO36 | D4 / Pixel Data Bit 4 | ++----+-----------+-----------------------------+ +| 13 | GPIO19 | D3 / Pixel Data Bit 3 | ++----+-----------+-----------------------------+ +| 14 | GPIO18 | D2 / Pixel Data Bit 2 | ++----+-----------+-----------------------------+ +| 15 | GPIO5 | D1 / Pixel Data Bit 1 | ++----+-----------+-----------------------------+ +| 16 | GPIO4 | D0 / Pixel Data Bit 0 | ++----+-----------+-----------------------------+ +| 17 | GPIO0 | RESET / Camera Reset | ++----+-----------+-----------------------------+ +| 18 | n/a | PWDN / Camera Power Down | ++----+-----------+-----------------------------+ + +- Signals D0 .. D7 denote camera data bus + +RGB LED +******* + ++----+-----------+---------+ +| . | ESP32 Pin | RGB LED | ++====+===========+=========+ +| 1 | GPIO0 | Red | ++----+-----------+---------+ +| 2 | GPIO2 | Green | ++----+-----------+---------+ +| 3 | GPIO4 | Blue | ++----+-----------+---------+ + +MicroSD Card +************ + ++---+---------------+----------------+ +| . | ESP32 Pin | MicroSD Signal | ++===+===============+================+ +| 1 | MTDI / GPIO12 | DATA2 | ++---+---------------+----------------+ +| 2 | MTCK / GPIO13 | CD / DATA3 | ++---+---------------+----------------+ +| 3 | MTDO / GPIO15 | CMD | ++---+---------------+----------------+ +| 4 | MTMS / GPIO14 | CLK | ++---+---------------+----------------+ +| 5 | GPIO2 | DATA0 | ++---+---------------+----------------+ +| 6 | GPIO4 | DATA1 | ++---+---------------+----------------+ +| 7 | GPIO21 | Card Detect | ++---+---------------+----------------+ + +LCD / U5 +******** + ++---+-----------+------------+ +| . | ESP32 Pin | LCD Signal | ++===+===========+============+ +| 1 | GPIO18 | RESET | ++---+-----------+------------+ +| 2 | GPIO19 | SCL | ++---+-----------+------------+ +| 3 | GPIO21 | D/C | ++---+-----------+------------+ +| 4 | GPIO22 | CS | ++---+-----------+------------+ +| 5 | GPIO23 | SDA | ++---+-----------+------------+ +| 6 | GPIO25 | SDO | ++---+-----------+------------+ +| 7 | GPIO5 | Backlight | ++---+-----------+------------+ + +Start Application Development +***************************** + +Before powering up your ESP-WROVER-KIT, please make sure that the board is in good +condition with no obvious signs of damage. + +Initial Setup +************* + +Please set only the following jumpers shown in the pictures below: + +- Select USB as the power source using the jumper block JP7. +- Enable UART communication using the jumper block JP2. + ++------------------------+---------------------------+ +| Power up from USB port | Enable UART communication | ++========+===============+===========================+ +| |jmpusbpwr| | |jmpuart| | ++------------------------+---------------------------+ + +Do not install any other jumpers. + +Turn the Power Switch to ON, the 5V Power On LED should light up. + +Supported Features +================== + +Current Zephyr's ESP32-Wrover-Kit board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp_wrover_kit + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp_wrover_kit`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp_wrover_kit + +Debugging +********* + +ESP32 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the ESP-WROVER-KIT board, the JTAG pins are connected internally to +a USB serial port on the same device as the console. These boards +require no external hardware and are debuggable as-is. The JTAG +signals, however, must be jumpered closed to connect the internal +controller (the default is to leave them disconnected). The jumper +headers are on the right side of the board as viewed from the power +switch, next to similar headers for SPI and UART. See +`ESP-WROVER-32 V3 Getting Started Guide`_ for details. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp_wrover_kit/esp32/procpu + :goals: debug + +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP-WROVER-32 V3 Getting Started Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-wrover-kit.html + +Related Documents +***************** + +.. _ESP-WROVER-KIT V4.1 schematics: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4_1.pdf (PDF) +.. _ESP-WROVER-KIT V4.1 layout: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4.1.dxf (DXF) +.. _ESP32 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf (PDF) +.. _ESP32-WROVER-E Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf (PDF) +.. _ESP32 Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi b/boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi rename to boards/espressif/esp_wrover_kit/esp_wrover_kit-pinctrl.dtsi diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.dts new file mode 100644 index 00000000000000..f0a046705ee005 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-Wrover-Kit APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.yaml b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.yaml new file mode 100644 index 00000000000000..64f7ef2124f651 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp_wrover_kit/esp32/appcpu +name: ESP WROVER KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.dts new file mode 100644 index 00000000000000..3709a13b475be2 --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.dts @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "esp_wrover_kit-pinctrl.dtsi" + +/ { + model = "Espressif ESP32-Wrover-Kit PROCPU"; + compatible = "espressif,esp32"; + + aliases { + led0 = &blue_led; + led1 = &green_led; + led2 = &red_led; + pwm-led0 = &pwm_led_red; + pwm-led1 = &pwm_led_green; + pwm-led2 = &pwm_led_blue; + red-pwm-led = &pwm_led_red; + green-pwm-led = &pwm_led_green; + blue-pwm-led = &pwm_led_blue; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ili9341; + }; + + leds { + compatible = "gpio-leds"; + + blue_led: led_0 { + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + label = "Blue - LED0"; + }; + + green_led: led_1 { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Green - LED1"; + }; + + red_led: led_2 { + gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; + label = "Red - LED2"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led_red: pwm_led_0 { + label = "Red PWM LED"; + pwms = <&ledc0 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; + pwm_led_green: pwm_led_1 { + label = "Green PWM LED"; + pwms = <&ledc0 1 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; + pwm_led_blue: pwm_led_2 { + label = "Blue PWM LED"; + pwms = <&ledc0 2 PWM_HZ(100) PWM_POLARITY_NORMAL>; + }; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9341: ili9341@0 { + compatible = "ilitek,ili9341"; + mipi-max-frequency = <25000000>; + reg = <0>; + pixel-format = <0>; + rotation = <0>; + width = <240>; + height = <320>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; + + /* FIXME: should be part of the display node */ + lcd-backlight { + gpio-hog; + gpios = <5 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + channel0@0 { + reg = <0x0>; + timer = <0>; + }; + channel1@1 { + reg = <0x1>; + timer = <1>; + }; + channel2@2 { + reg = <0x2>; + timer = <2>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.yaml b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.yaml new file mode 100644 index 00000000000000..80c6a5d398302f --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu.yaml @@ -0,0 +1,23 @@ +identifier: esp_wrover_kit/esp32/procpu +name: ESP WROVER KIT +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu_defconfig b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu_defconfig new file mode 100644 index 00000000000000..f029cac9e9e77b --- /dev/null +++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp_wrover_kit/support/openocd.cfg b/boards/espressif/esp_wrover_kit/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp_wrover_kit/support/openocd.cfg rename to boards/espressif/esp_wrover_kit/support/openocd.cfg diff --git a/boards/espressif/index.rst b/boards/espressif/index.rst new file mode 100644 index 00000000000000..b1b7dfbeede266 --- /dev/null +++ b/boards/espressif/index.rst @@ -0,0 +1,10 @@ +.. _boards-espressif: + +Espressif +######### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 b/boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 new file mode 100644 index 00000000000000..3f87d2714634cf --- /dev/null +++ b/boards/fanke/fk7b0m1_vbt6/Kconfig.fk7b0m1_vbt6 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FK7B0M1_VBT6 + select SOC_STM32H7B0XX diff --git a/boards/arm/fk7b0m1_vbt6/board.cmake b/boards/fanke/fk7b0m1_vbt6/board.cmake similarity index 100% rename from boards/arm/fk7b0m1_vbt6/board.cmake rename to boards/fanke/fk7b0m1_vbt6/board.cmake diff --git a/boards/fanke/fk7b0m1_vbt6/board.yml b/boards/fanke/fk7b0m1_vbt6/board.yml new file mode 100644 index 00000000000000..204e3538a93115 --- /dev/null +++ b/boards/fanke/fk7b0m1_vbt6/board.yml @@ -0,0 +1,5 @@ +board: + name: fk7b0m1_vbt6 + vendor: fanke + socs: + - name: stm32h7b0xx diff --git a/boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp b/boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp similarity index 100% rename from boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp rename to boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6.webp diff --git a/boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp b/boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp similarity index 100% rename from boards/arm/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp rename to boards/fanke/fk7b0m1_vbt6/doc/img/fk7b0m1_vbt6_pins.webp diff --git a/boards/fanke/fk7b0m1_vbt6/doc/index.rst b/boards/fanke/fk7b0m1_vbt6/doc/index.rst new file mode 100644 index 00000000000000..220fc514d4c852 --- /dev/null +++ b/boards/fanke/fk7b0m1_vbt6/doc/index.rst @@ -0,0 +1,179 @@ +.. _fk7b0m1_vbt6: + +FANKE FK7B0M1-VBT6 +################## + +Overview +******** + +The FK7B0M1-VBT6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller +platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H7B0VBT6 microcontroller. +This board is an ideal solution for developers looking to create high-performance +applications, especially in the field of Human-Machine Interface (HMI), leveraging its +robust capabilities and support for sophisticated display and touch technologies. + +The FK7B0M1-VBT6 is designed as a reference design for user application development before +transitioning to the final product, significantly simplifying the development process. +Its wide range of hardware features, including advanced display and touch capabilities, +make it exceptionally suitable for HMI applications, allowing for comprehensive evaluation +and testing of peripherals and functionalities. + +.. figure:: img/fk7b0m1_vbt6.webp + :width: 600px + :align: center + :alt: FK7B0M1-VBT6 + + FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) + +Hardware +******** + +FK7B0M1-VBT6 provides the following hardware components: + +- STM32H7B6VB in LQFP100 package +- ARM 32-bit Cortex-M7 CPU with FPU +- 280 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 128 KB Flash +- ~1.4 MB SRAM max (1.18 Mbytes user SRAM + 64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM + 4 Kbytes SRAM in Backup domain) +- Main clock: External 25MHz crystal oscillator. +- RTC: 32.768kHz crystal oscillator. +- 32-bit timers(2) +- 16-bit timers(12) +- 1 reset button, 1 user button, and 1 BOOT button +- 1 user LED +- External 64-Mbit QSPI (W25Q64) NOR Flash memory. +- External 64-Mbit SPI (W25Q64) NOR Flash memory. +- USB OTG Full Speed and High Speed(1) +- 1 micro SD card +- 1 RGB LCD interface +- SWD and serial port accessibility through a pin header +- Bring out 39 IO ports + +More information about STM32H7B0VB can be found here: + +- `STM32H7B0VB on www.st.com`_ + +Supported Features +================== + +The Zephyr nucleo_h723zg board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration per core can be found in +:zephyr_file:`boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig` + +Connections and IOs +=================== + +Available pins: +--------------- + +Nucleo FK7B0M1-VBT6 board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +.. figure:: img/fk7b0m1_vbt6_pins.webp + :width: 600px + :align: center + :alt: FK7B0M1-VBT6 + + FK7B0M1-VBT6 (Credit: FANKE Technology Co., Ltd) + +LED +--- + +- User LED (blue) = PC1 + +Push buttons +------------------------- + +- BOOT = SW1 = BOOT0 +- RESET = SW2 = NRST +- User button = SW3 = PC13 + +UART +----- + +- TX device = USART1 PA9 +- RX device = USART1 PA10 + +USB +--- + +- USB D- = PA11 +- USB D+ = PA12 + +System Clock +============ + +The FK7B0M1-VBT6 System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 280MHz, +driven by an 25MHz external crystal oscillator. + +Serial Port +=========== + +The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1. + +Programming and Debugging +************************* + +The FK7B0M1-VBT6 board does not include an on-board debugger. As a result, it requires +an external debugger, such as ST-Link, for programming and debugging purposes. + +The board provides header pins for the Serial Wire Debug (SWD) interface. + +Flashing +======== + +To begin, connect the ST-Link Debug Programmer to the FK7B0M1-VBT6 board using the SWD +interface. Next, connect the ST-Link to your host computer via a USB port. +Once this setup is complete, you can proceed to build and flash your application to the board + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: fk7b0m1_vbt6 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 -b 115200 + +Then, press the RESET button, you should see the following message: + +.. code-block:: console + + Hello World! fk7b0m1_vbt6 + +Debugging +========= + +This current Zephyr port does not support debugging. + +References +********** + +.. target-notes:: +.. _STM32H7B0VB on www.st.com: https://www.st.com/en/microcontrollers/stm32h7b0vb.html diff --git a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.dts b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts similarity index 100% rename from boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.dts rename to boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.dts diff --git a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml similarity index 100% rename from boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml rename to boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml diff --git a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig similarity index 87% rename from boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig rename to boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig index 72587a3a897a8d..dd4c5e18475e2e 100644 --- a/boards/arm/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig +++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6_defconfig @@ -1,9 +1,6 @@ # Copyright (c) Charles Dias # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H7B0XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/fk7b0m1_vbt6/support/openocd.cfg b/boards/fanke/fk7b0m1_vbt6/support/openocd.cfg similarity index 100% rename from boards/arm/fk7b0m1_vbt6/support/openocd.cfg rename to boards/fanke/fk7b0m1_vbt6/support/openocd.cfg diff --git a/boards/fanke/index.rst b/boards/fanke/index.rst new file mode 100644 index 00000000000000..2c9434547ae890 --- /dev/null +++ b/boards/fanke/index.rst @@ -0,0 +1,10 @@ +.. _boards-fanke: + +Fanke +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/firefly/index.rst b/boards/firefly/index.rst new file mode 100644 index 00000000000000..3ba363b1d9f7a0 --- /dev/null +++ b/boards/firefly/index.rst @@ -0,0 +1,10 @@ +.. _boards-firefly: + +Firefly +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/frdm_k64f/CMakeLists.txt b/boards/firefly/roc_rk3568_pc/CMakeLists.txt similarity index 100% rename from boards/arm/frdm_k64f/CMakeLists.txt rename to boards/firefly/roc_rk3568_pc/CMakeLists.txt diff --git a/boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc b/boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc new file mode 100644 index 00000000000000..eda2cdb36b6468 --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/Kconfig.roc_rk3568_pc @@ -0,0 +1,6 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ROC_RK3568_PC + select SOC_RK3568 diff --git a/boards/arm/google_kukui/board.cmake b/boards/firefly/roc_rk3568_pc/board.cmake similarity index 100% rename from boards/arm/google_kukui/board.cmake rename to boards/firefly/roc_rk3568_pc/board.cmake diff --git a/boards/firefly/roc_rk3568_pc/board.yml b/boards/firefly/roc_rk3568_pc/board.yml new file mode 100644 index 00000000000000..8a60a165dc43f6 --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/board.yml @@ -0,0 +1,7 @@ +board: + name: roc_rk3568_pc + vendor: firefly + socs: + - name: rk3568 + variants: + - name: smp diff --git a/boards/firefly/roc_rk3568_pc/doc/index.rst b/boards/firefly/roc_rk3568_pc/doc/index.rst new file mode 100644 index 00000000000000..4da6df1023aedf --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/doc/index.rst @@ -0,0 +1,142 @@ +.. _roc_rk3568_pc: + +Firefly ROC-RK3568-PC (Quad-core Cortex-A55) +############################################ + +Overview +******** + +The ROC-RK3568-PC is a Quad-Core 64-Bit Mini Computer, which supports 4G large RAM. M.2 +and SATA3.0 interfaces enables expansion with large hard drives. +Providing dual Gigabit Ethernet ports, it supports WiFi 6 wireless transmission. +Control Port can be connected with RS485/RS232 devices. + +RK3568 quad-core 64-bit Cortex-A55 processor, with brand new ARM v8.2-A architecture, +has frequency up to 2.0GHz. Zephyr OS is ported to run on it. + + +- Board features: + + - RAM: 4GB LPDDR4 + - Storage: + + - 32GB eMMC + - M.2 PCIe 3.0 x 1 (Expand with 2242 / 2280 NVMe SSD) + - TF-Card Slot + - Wireless: + + - Supports WiFi 6 (802.11 AX) + - Supports BT5.0 + - USB: + + - One USB 3.0 + - Two USB 2.0 + - One Type-C + - Ethernet + - M.2 PCIe3.0 (Expand with NVMe SSD) + - LEDs: + + - 1x Power status LED + - Debug + + - UART debug ports for board + + +Supported Features +================== + +The Zephyr roc_rk3568_pc board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A55 Core runs up to 2.0 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART2. + +Programming and Debugging +************************* + +Use U-Boot to load the zephyr.bin to the memory and kick it: + +.. code-block:: console + + tftp 0x40000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x40000000 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3568_pc + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build bc695c6df5eb *** + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 0 on roc_rk3568_pc! + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 0 on roc_rk3568_pc! + + +``roc_rk3568_pc//smp`` support, use this configuration to run Zephyr smp applications and subsys tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: roc_rk3568_pc//smp + :goals: run + +This will build an image with the shell_module sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build bc695c6df5eb *** + I/TC: Secondary CPU 1 initializing + I/TC: Secondary CPU 1 switching to normal world boot + I/TC: Secondary CPU 2 initializing + I/TC: Secondary CPU 2 switching to normal world boot + I/TC: Secondary CPU 3 initializing + I/TC: Secondary CPU 3 switching to normal world boot + Secondary CPU core 1 (MPID:0x100) is up + Secondary CPU core 2 (MPID:0x200) is up + Secondary CPU core 3 (MPID:0x300) is up + + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 1 on roc_rk3568_pc! + thread_a: Hello World from cpu 0 on roc_rk3568_pc! + thread_b: Hello World from cpu 1 on roc_rk3568_pc! + +References +========== + +More information can refer to Firefly official website: +`Firefly website`_. + +.. _Firefly website: + https://en.t-firefly.com/product/industry/rocrk3568pc.html?theme=pc diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc.dts similarity index 100% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc.dts rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc.dts diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc.yaml similarity index 100% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc.yaml rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc.yaml diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_defconfig similarity index 85% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc_defconfig index d85c08d24e7119..e9d051b573a98b 100644 --- a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_defconfig +++ b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_defconfig @@ -3,9 +3,6 @@ # SPDX-License-Identifier: Apache-2.0 # Platform Configuration -CONFIG_SOC_SERIES_RK3568=y -CONFIG_SOC_RK3568=y -CONFIG_BOARD_ROC_RK3568_PC=y CONFIG_ARM_ARCH_TIMER=y # Serial Drivers diff --git a/boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.dts similarity index 100% rename from boards/arm64/roc_rk3568_pc/roc_rk3568_pc_smp.dts rename to boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.dts diff --git a/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml new file mode 100644 index 00000000000000..fdf59e56fca5eb --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp.yaml @@ -0,0 +1,14 @@ +identifier: roc_rk3568_pc/rk3568/smp +name: Rockchip ROC RK3568 PC SMP +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth diff --git a/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig new file mode 100644 index 00000000000000..5d5b627f5491ae --- /dev/null +++ b/boards/firefly/roc_rk3568_pc/roc_rk3568_pc_rk3568_smp_defconfig @@ -0,0 +1,15 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +# SMP support +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=4 +CONFIG_MAX_THREAD_BYTES=4 + +# ARMv8 NS world with cache management +CONFIG_DCACHE=y + +# PSCI support +CONFIG_PM_CPU_OPS=y +CONFIG_PM_CPU_OPS_PSCI=y diff --git a/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig b/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig new file mode 100644 index 00000000000000..7bf6f84463b1e9 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ESP32S2 Franzininho board configuration + +# Copyright (c) 2022 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 32768 if WIFI + default 4096 diff --git a/boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho b/boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho new file mode 100644 index 00000000000000..61c438408b5013 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/Kconfig.esp32s2_franzininho @@ -0,0 +1,7 @@ +# ESP32S2 Franzininho board configuration + +# Copyright (c) 2022 Felipe Neves +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_FRANZININHO + select SOC_ESP32S2_WROOM diff --git a/boards/xtensa/esp32_ethernet_kit/Kconfig.sysbuild b/boards/franzininho/esp32s2_franzininho/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32_ethernet_kit/Kconfig.sysbuild rename to boards/franzininho/esp32s2_franzininho/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s2_franzininho/board.cmake b/boards/franzininho/esp32s2_franzininho/board.cmake similarity index 100% rename from boards/xtensa/esp32s2_franzininho/board.cmake rename to boards/franzininho/esp32s2_franzininho/board.cmake diff --git a/boards/franzininho/esp32s2_franzininho/board.yml b/boards/franzininho/esp32s2_franzininho/board.yml new file mode 100644 index 00000000000000..913c4d4232faa4 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s2_franzininho + vendor: espressif + socs: + - name: esp32s2 diff --git a/boards/xtensa/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg b/boards/franzininho/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg similarity index 100% rename from boards/xtensa/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg rename to boards/franzininho/esp32s2_franzininho/doc/img/esp32_s2_franzininho.jpg diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst new file mode 100644 index 00000000000000..de0b2c8b1b7252 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst @@ -0,0 +1,174 @@ +.. _esp32s2_franzininho: + +ESP32-S2 Franzininho +#################### + +Overview +******** + +Franzininho is an educational development board based on ESP32-S2 which is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, +designed to be secure and cost-effective, with a high performance and a rich set of IO capabilities. [1]_ + +The features include the following: + +- RSA-3072-based secure boot +- AES-XTS-256-based flash encryption +- Protected private key and device secrets from software access +- Cryptographic accelerators for enhanced performance +- Protection against physical fault injection attacks +- Various peripherals: + + - 43x programmable GPIOs + - 14x configurable capacitive touch GPIOs + - USB OTG + - LCD interface + - camera interface + - SPI + - I2S + - UART + - ADC + - DAC + - LED PWM with up to 8 channels + +.. figure:: img/esp32_s2_franzininho.jpg + :align: center + :alt: ESP32-S2 FRANZININHO + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s2_franzininho + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_franzininho + :goals: build + +The usual ``flash`` target will work with the ``esp32s2_franzininho`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s2_franzininho + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s2_franzininho + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-s2 +.. _`ESP32S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf +.. _`ESP32S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi rename to boards/franzininho/esp32s2_franzininho/esp32s2_franzininho-pinctrl.dtsi diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.dts b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts similarity index 98% rename from boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.dts rename to boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts index 2ce35ee5534283..d8a6f1c70706b2 100644 --- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.dts +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts @@ -10,7 +10,7 @@ #include "esp32s2_franzininho-pinctrl.dtsi" / { - model = "esp32s2_franzininho"; + model = "ESP32S2 Franzininho"; compatible = "espressif,esp32s2"; aliases { diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.yaml b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml similarity index 92% rename from boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.yaml rename to boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml index 9cc2a2603423fb..0a227dc60212f2 100644 --- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho.yaml +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml @@ -16,4 +16,4 @@ testing: - heap - net - bluetooth -vendor: espressif +vendor: franzininho diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig new file mode 100644 index 00000000000000..f566acd9340219 --- /dev/null +++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + + + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_lolin_mini/support/openocd.cfg b/boards/franzininho/esp32s2_franzininho/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/support/openocd.cfg rename to boards/franzininho/esp32s2_franzininho/support/openocd.cfg diff --git a/boards/franzininho/index.rst b/boards/franzininho/index.rst new file mode 100644 index 00000000000000..e7222d6d4a1389 --- /dev/null +++ b/boards/franzininho/index.rst @@ -0,0 +1,10 @@ +.. _boards-franzininho: + +Franzininho +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/gaisler/generic_leon3/Kconfig.defconfig b/boards/gaisler/generic_leon3/Kconfig.defconfig new file mode 100644 index 00000000000000..0294060baa5f52 --- /dev/null +++ b/boards/gaisler/generic_leon3/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GENERIC_LEON3 + +config SPARC_CASA + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +config UART_INTERRUPT_DRIVEN + default y + +endif diff --git a/boards/gaisler/generic_leon3/Kconfig.generic_leon3 b/boards/gaisler/generic_leon3/Kconfig.generic_leon3 new file mode 100644 index 00000000000000..88240708cf07df --- /dev/null +++ b/boards/gaisler/generic_leon3/Kconfig.generic_leon3 @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GENERIC_LEON3 + select SOC_LEON3 diff --git a/boards/sparc/generic_leon3/board.cmake b/boards/gaisler/generic_leon3/board.cmake similarity index 100% rename from boards/sparc/generic_leon3/board.cmake rename to boards/gaisler/generic_leon3/board.cmake diff --git a/boards/gaisler/generic_leon3/board.yml b/boards/gaisler/generic_leon3/board.yml new file mode 100644 index 00000000000000..33c4d806adde7e --- /dev/null +++ b/boards/gaisler/generic_leon3/board.yml @@ -0,0 +1,5 @@ +board: + name: generic_leon3 + vendor: gaisler + socs: + - name: leon3 diff --git a/boards/sparc/generic_leon3/doc/index.rst b/boards/gaisler/generic_leon3/doc/index.rst similarity index 100% rename from boards/sparc/generic_leon3/doc/index.rst rename to boards/gaisler/generic_leon3/doc/index.rst diff --git a/boards/sparc/generic_leon3/generic_leon3.dts b/boards/gaisler/generic_leon3/generic_leon3.dts similarity index 100% rename from boards/sparc/generic_leon3/generic_leon3.dts rename to boards/gaisler/generic_leon3/generic_leon3.dts diff --git a/boards/sparc/generic_leon3/generic_leon3.yaml b/boards/gaisler/generic_leon3/generic_leon3.yaml similarity index 100% rename from boards/sparc/generic_leon3/generic_leon3.yaml rename to boards/gaisler/generic_leon3/generic_leon3.yaml diff --git a/boards/gaisler/generic_leon3/generic_leon3_defconfig b/boards/gaisler/generic_leon3/generic_leon3_defconfig new file mode 100644 index 00000000000000..d7eb0842fa7ec8 --- /dev/null +++ b/boards/gaisler/generic_leon3/generic_leon3_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_EXTRA_EXCEPTION_INFO=y diff --git a/boards/gaisler/gr716a_mini/Kconfig.defconfig b/boards/gaisler/gr716a_mini/Kconfig.defconfig new file mode 100644 index 00000000000000..5617c96a6dd43a --- /dev/null +++ b/boards/gaisler/gr716a_mini/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_GR716A_MINI + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 20000000 + +config UART_INTERRUPT_DRIVEN + default y + +endif diff --git a/boards/gaisler/gr716a_mini/Kconfig.gr716a_mini b/boards/gaisler/gr716a_mini/Kconfig.gr716a_mini new file mode 100644 index 00000000000000..11b033a54d82a2 --- /dev/null +++ b/boards/gaisler/gr716a_mini/Kconfig.gr716a_mini @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GR716A_MINI + select SOC_GR716A diff --git a/boards/sparc/gr716a_mini/board.cmake b/boards/gaisler/gr716a_mini/board.cmake similarity index 100% rename from boards/sparc/gr716a_mini/board.cmake rename to boards/gaisler/gr716a_mini/board.cmake diff --git a/boards/gaisler/gr716a_mini/board.yml b/boards/gaisler/gr716a_mini/board.yml new file mode 100644 index 00000000000000..0de80629b404a7 --- /dev/null +++ b/boards/gaisler/gr716a_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: gr716a_mini + vendor: gaisler + socs: + - name: gr716a diff --git a/boards/sparc/gr716a_mini/doc/gr716a_mini.jpg b/boards/gaisler/gr716a_mini/doc/gr716a_mini.jpg similarity index 100% rename from boards/sparc/gr716a_mini/doc/gr716a_mini.jpg rename to boards/gaisler/gr716a_mini/doc/gr716a_mini.jpg diff --git a/boards/sparc/gr716a_mini/doc/index.rst b/boards/gaisler/gr716a_mini/doc/index.rst similarity index 100% rename from boards/sparc/gr716a_mini/doc/index.rst rename to boards/gaisler/gr716a_mini/doc/index.rst diff --git a/boards/sparc/gr716a_mini/gr716a_mini.dts b/boards/gaisler/gr716a_mini/gr716a_mini.dts similarity index 100% rename from boards/sparc/gr716a_mini/gr716a_mini.dts rename to boards/gaisler/gr716a_mini/gr716a_mini.dts diff --git a/boards/sparc/gr716a_mini/gr716a_mini.yaml b/boards/gaisler/gr716a_mini/gr716a_mini.yaml similarity index 100% rename from boards/sparc/gr716a_mini/gr716a_mini.yaml rename to boards/gaisler/gr716a_mini/gr716a_mini.yaml diff --git a/boards/gaisler/gr716a_mini/gr716a_mini_defconfig b/boards/gaisler/gr716a_mini/gr716a_mini_defconfig new file mode 100644 index 00000000000000..101f819969b275 --- /dev/null +++ b/boards/gaisler/gr716a_mini/gr716a_mini_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/gaisler/index.rst b/boards/gaisler/index.rst new file mode 100644 index 00000000000000..ece74721dcd002 --- /dev/null +++ b/boards/gaisler/index.rst @@ -0,0 +1,10 @@ +.. _boards-gaisler: + +Gaisler +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/gd/gd32a503v_eval/Kconfig.gd32a503v_eval b/boards/gd/gd32a503v_eval/Kconfig.gd32a503v_eval new file mode 100644 index 00000000000000..c1e49432cb6d5f --- /dev/null +++ b/boards/gd/gd32a503v_eval/Kconfig.gd32a503v_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32A503V_EVAL + select SOC_GD32A503 diff --git a/boards/arm/gd32a503v_eval/board.cmake b/boards/gd/gd32a503v_eval/board.cmake similarity index 100% rename from boards/arm/gd32a503v_eval/board.cmake rename to boards/gd/gd32a503v_eval/board.cmake diff --git a/boards/gd/gd32a503v_eval/board.yml b/boards/gd/gd32a503v_eval/board.yml new file mode 100644 index 00000000000000..129cf4b0b50d85 --- /dev/null +++ b/boards/gd/gd32a503v_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32a503v_eval + vendor: gd + socs: + - name: gd32a503 diff --git a/boards/arm/gd32a503v_eval/doc/img/gd32a503v_eval.jpg b/boards/gd/gd32a503v_eval/doc/img/gd32a503v_eval.jpg similarity index 100% rename from boards/arm/gd32a503v_eval/doc/img/gd32a503v_eval.jpg rename to boards/gd/gd32a503v_eval/doc/img/gd32a503v_eval.jpg diff --git a/boards/arm/gd32a503v_eval/doc/index.rst b/boards/gd/gd32a503v_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32a503v_eval/doc/index.rst rename to boards/gd/gd32a503v_eval/doc/index.rst diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi b/boards/gd/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi rename to boards/gd/gd32a503v_eval/gd32a503v_eval-pinctrl.dtsi diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval.dts b/boards/gd/gd32a503v_eval/gd32a503v_eval.dts similarity index 100% rename from boards/arm/gd32a503v_eval/gd32a503v_eval.dts rename to boards/gd/gd32a503v_eval/gd32a503v_eval.dts diff --git a/boards/arm/gd32a503v_eval/gd32a503v_eval.yaml b/boards/gd/gd32a503v_eval/gd32a503v_eval.yaml similarity index 100% rename from boards/arm/gd32a503v_eval/gd32a503v_eval.yaml rename to boards/gd/gd32a503v_eval/gd32a503v_eval.yaml diff --git a/boards/gd/gd32a503v_eval/gd32a503v_eval_defconfig b/boards/gd/gd32a503v_eval/gd32a503v_eval_defconfig new file mode 100644 index 00000000000000..5d4c4159b6c097 --- /dev/null +++ b/boards/gd/gd32a503v_eval/gd32a503v_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32e103v_eval/Kconfig.gd32e103v_eval b/boards/gd/gd32e103v_eval/Kconfig.gd32e103v_eval new file mode 100644 index 00000000000000..f4fb38d69e5c6c --- /dev/null +++ b/boards/gd/gd32e103v_eval/Kconfig.gd32e103v_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32E103V_EVAL + select SOC_GD32E103 diff --git a/boards/arm/gd32e103v_eval/board.cmake b/boards/gd/gd32e103v_eval/board.cmake similarity index 100% rename from boards/arm/gd32e103v_eval/board.cmake rename to boards/gd/gd32e103v_eval/board.cmake diff --git a/boards/gd/gd32e103v_eval/board.yml b/boards/gd/gd32e103v_eval/board.yml new file mode 100644 index 00000000000000..1c4896977835a6 --- /dev/null +++ b/boards/gd/gd32e103v_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32e103v_eval + vendor: gd + socs: + - name: gd32e103 diff --git a/boards/arm/gd32e103v_eval/doc/img/gd32e103v_eval.jpg b/boards/gd/gd32e103v_eval/doc/img/gd32e103v_eval.jpg similarity index 100% rename from boards/arm/gd32e103v_eval/doc/img/gd32e103v_eval.jpg rename to boards/gd/gd32e103v_eval/doc/img/gd32e103v_eval.jpg diff --git a/boards/arm/gd32e103v_eval/doc/index.rst b/boards/gd/gd32e103v_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32e103v_eval/doc/index.rst rename to boards/gd/gd32e103v_eval/doc/index.rst diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi b/boards/gd/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi rename to boards/gd/gd32e103v_eval/gd32e103v_eval-pinctrl.dtsi diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.dts b/boards/gd/gd32e103v_eval/gd32e103v_eval.dts similarity index 100% rename from boards/arm/gd32e103v_eval/gd32e103v_eval.dts rename to boards/gd/gd32e103v_eval/gd32e103v_eval.dts diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.yaml b/boards/gd/gd32e103v_eval/gd32e103v_eval.yaml similarity index 100% rename from boards/arm/gd32e103v_eval/gd32e103v_eval.yaml rename to boards/gd/gd32e103v_eval/gd32e103v_eval.yaml diff --git a/boards/gd/gd32e103v_eval/gd32e103v_eval_defconfig b/boards/gd/gd32e103v_eval/gd32e103v_eval_defconfig new file mode 100644 index 00000000000000..35ac235333c743 --- /dev/null +++ b/boards/gd/gd32e103v_eval/gd32e103v_eval_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021, YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GD32_HXTAL_8MHZ=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32e103v_eval/support/openocd.cfg b/boards/gd/gd32e103v_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32e103v_eval/support/openocd.cfg rename to boards/gd/gd32e103v_eval/support/openocd.cfg diff --git a/boards/gd/gd32e507v_start/Kconfig.gd32e507v_start b/boards/gd/gd32e507v_start/Kconfig.gd32e507v_start new file mode 100644 index 00000000000000..be09310ad58f32 --- /dev/null +++ b/boards/gd/gd32e507v_start/Kconfig.gd32e507v_start @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32E507V_START + select SOC_GD32E507 diff --git a/boards/arm/gd32e507v_start/board.cmake b/boards/gd/gd32e507v_start/board.cmake similarity index 100% rename from boards/arm/gd32e507v_start/board.cmake rename to boards/gd/gd32e507v_start/board.cmake diff --git a/boards/gd/gd32e507v_start/board.yml b/boards/gd/gd32e507v_start/board.yml new file mode 100644 index 00000000000000..b364620f61a844 --- /dev/null +++ b/boards/gd/gd32e507v_start/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32e507v_start + vendor: gd + socs: + - name: gd32e507 diff --git a/boards/arm/gd32e507v_start/doc/img/gd32e507v_start.jpg b/boards/gd/gd32e507v_start/doc/img/gd32e507v_start.jpg similarity index 100% rename from boards/arm/gd32e507v_start/doc/img/gd32e507v_start.jpg rename to boards/gd/gd32e507v_start/doc/img/gd32e507v_start.jpg diff --git a/boards/arm/gd32e507v_start/doc/index.rst b/boards/gd/gd32e507v_start/doc/index.rst similarity index 100% rename from boards/arm/gd32e507v_start/doc/index.rst rename to boards/gd/gd32e507v_start/doc/index.rst diff --git a/boards/arm/gd32e507v_start/gd32e507v_start-pinctrl.dtsi b/boards/gd/gd32e507v_start/gd32e507v_start-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32e507v_start/gd32e507v_start-pinctrl.dtsi rename to boards/gd/gd32e507v_start/gd32e507v_start-pinctrl.dtsi diff --git a/boards/arm/gd32e507v_start/gd32e507v_start.dts b/boards/gd/gd32e507v_start/gd32e507v_start.dts similarity index 100% rename from boards/arm/gd32e507v_start/gd32e507v_start.dts rename to boards/gd/gd32e507v_start/gd32e507v_start.dts diff --git a/boards/arm/gd32e507v_start/gd32e507v_start.yaml b/boards/gd/gd32e507v_start/gd32e507v_start.yaml similarity index 100% rename from boards/arm/gd32e507v_start/gd32e507v_start.yaml rename to boards/gd/gd32e507v_start/gd32e507v_start.yaml diff --git a/boards/gd/gd32e507v_start/gd32e507v_start_defconfig b/boards/gd/gd32e507v_start/gd32e507v_start_defconfig new file mode 100644 index 00000000000000..51f83a8ccd6624 --- /dev/null +++ b/boards/gd/gd32e507v_start/gd32e507v_start_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32e507z_eval/Kconfig.gd32e507z_eval b/boards/gd/gd32e507z_eval/Kconfig.gd32e507z_eval new file mode 100644 index 00000000000000..bd40810385cfbc --- /dev/null +++ b/boards/gd/gd32e507z_eval/Kconfig.gd32e507z_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32E507Z_EVAL + select SOC_GD32E507 diff --git a/boards/arm/gd32e507z_eval/board.cmake b/boards/gd/gd32e507z_eval/board.cmake similarity index 100% rename from boards/arm/gd32e507z_eval/board.cmake rename to boards/gd/gd32e507z_eval/board.cmake diff --git a/boards/gd/gd32e507z_eval/board.yml b/boards/gd/gd32e507z_eval/board.yml new file mode 100644 index 00000000000000..2325550db5d3f3 --- /dev/null +++ b/boards/gd/gd32e507z_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32e507z_eval + vendor: gd + socs: + - name: gd32e507 diff --git a/boards/arm/gd32e507z_eval/doc/img/gd32e507z_eval.webp b/boards/gd/gd32e507z_eval/doc/img/gd32e507z_eval.webp similarity index 100% rename from boards/arm/gd32e507z_eval/doc/img/gd32e507z_eval.webp rename to boards/gd/gd32e507z_eval/doc/img/gd32e507z_eval.webp diff --git a/boards/arm/gd32e507z_eval/doc/index.rst b/boards/gd/gd32e507z_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32e507z_eval/doc/index.rst rename to boards/gd/gd32e507z_eval/doc/index.rst diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi b/boards/gd/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi rename to boards/gd/gd32e507z_eval/gd32e507z_eval-pinctrl.dtsi diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval.dts b/boards/gd/gd32e507z_eval/gd32e507z_eval.dts similarity index 100% rename from boards/arm/gd32e507z_eval/gd32e507z_eval.dts rename to boards/gd/gd32e507z_eval/gd32e507z_eval.dts diff --git a/boards/arm/gd32e507z_eval/gd32e507z_eval.yaml b/boards/gd/gd32e507z_eval/gd32e507z_eval.yaml similarity index 100% rename from boards/arm/gd32e507z_eval/gd32e507z_eval.yaml rename to boards/gd/gd32e507z_eval/gd32e507z_eval.yaml diff --git a/boards/gd/gd32e507z_eval/gd32e507z_eval_defconfig b/boards/gd/gd32e507z_eval/gd32e507z_eval_defconfig new file mode 100644 index 00000000000000..51f83a8ccd6624 --- /dev/null +++ b/boards/gd/gd32e507z_eval/gd32e507z_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32f350r_eval/Kconfig.gd32f350r_eval b/boards/gd/gd32f350r_eval/Kconfig.gd32f350r_eval new file mode 100644 index 00000000000000..ae610061d8d635 --- /dev/null +++ b/boards/gd/gd32f350r_eval/Kconfig.gd32f350r_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F350R_EVAL + select SOC_GD32F350 diff --git a/boards/arm/gd32f350r_eval/board.cmake b/boards/gd/gd32f350r_eval/board.cmake similarity index 100% rename from boards/arm/gd32f350r_eval/board.cmake rename to boards/gd/gd32f350r_eval/board.cmake diff --git a/boards/gd/gd32f350r_eval/board.yml b/boards/gd/gd32f350r_eval/board.yml new file mode 100644 index 00000000000000..ee486b1798354c --- /dev/null +++ b/boards/gd/gd32f350r_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f350r_eval + vendor: gd + socs: + - name: gd32f350 diff --git a/boards/arm/gd32f350r_eval/doc/img/gd32f350r_eval.webp b/boards/gd/gd32f350r_eval/doc/img/gd32f350r_eval.webp similarity index 100% rename from boards/arm/gd32f350r_eval/doc/img/gd32f350r_eval.webp rename to boards/gd/gd32f350r_eval/doc/img/gd32f350r_eval.webp diff --git a/boards/arm/gd32f350r_eval/doc/index.rst b/boards/gd/gd32f350r_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f350r_eval/doc/index.rst rename to boards/gd/gd32f350r_eval/doc/index.rst diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi b/boards/gd/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi rename to boards/gd/gd32f350r_eval/gd32f350r_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval.dts b/boards/gd/gd32f350r_eval/gd32f350r_eval.dts similarity index 100% rename from boards/arm/gd32f350r_eval/gd32f350r_eval.dts rename to boards/gd/gd32f350r_eval/gd32f350r_eval.dts diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval.yaml b/boards/gd/gd32f350r_eval/gd32f350r_eval.yaml similarity index 100% rename from boards/arm/gd32f350r_eval/gd32f350r_eval.yaml rename to boards/gd/gd32f350r_eval/gd32f350r_eval.yaml diff --git a/boards/gd/gd32f350r_eval/gd32f350r_eval_defconfig b/boards/gd/gd32f350r_eval/gd32f350r_eval_defconfig new file mode 100644 index 00000000000000..6df7f7edc24057 --- /dev/null +++ b/boards/gd/gd32f350r_eval/gd32f350r_eval_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/gd32f350r_eval/support/openocd.cfg b/boards/gd/gd32f350r_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f350r_eval/support/openocd.cfg rename to boards/gd/gd32f350r_eval/support/openocd.cfg diff --git a/boards/gd/gd32f403z_eval/Kconfig.gd32f403z_eval b/boards/gd/gd32f403z_eval/Kconfig.gd32f403z_eval new file mode 100644 index 00000000000000..e9fa7237053827 --- /dev/null +++ b/boards/gd/gd32f403z_eval/Kconfig.gd32f403z_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F403Z_EVAL + select SOC_GD32F403 diff --git a/boards/arm/gd32f403z_eval/board.cmake b/boards/gd/gd32f403z_eval/board.cmake similarity index 100% rename from boards/arm/gd32f403z_eval/board.cmake rename to boards/gd/gd32f403z_eval/board.cmake diff --git a/boards/gd/gd32f403z_eval/board.yml b/boards/gd/gd32f403z_eval/board.yml new file mode 100644 index 00000000000000..222ba863858447 --- /dev/null +++ b/boards/gd/gd32f403z_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f403z_eval + vendor: gd + socs: + - name: gd32f403 diff --git a/boards/arm/gd32f403z_eval/doc/img/gd32f403z_eval.jpg b/boards/gd/gd32f403z_eval/doc/img/gd32f403z_eval.jpg similarity index 100% rename from boards/arm/gd32f403z_eval/doc/img/gd32f403z_eval.jpg rename to boards/gd/gd32f403z_eval/doc/img/gd32f403z_eval.jpg diff --git a/boards/arm/gd32f403z_eval/doc/index.rst b/boards/gd/gd32f403z_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f403z_eval/doc/index.rst rename to boards/gd/gd32f403z_eval/doc/index.rst diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi b/boards/gd/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi rename to boards/gd/gd32f403z_eval/gd32f403z_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.dts b/boards/gd/gd32f403z_eval/gd32f403z_eval.dts similarity index 100% rename from boards/arm/gd32f403z_eval/gd32f403z_eval.dts rename to boards/gd/gd32f403z_eval/gd32f403z_eval.dts diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.yaml b/boards/gd/gd32f403z_eval/gd32f403z_eval.yaml similarity index 100% rename from boards/arm/gd32f403z_eval/gd32f403z_eval.yaml rename to boards/gd/gd32f403z_eval/gd32f403z_eval.yaml diff --git a/boards/gd/gd32f403z_eval/gd32f403z_eval_defconfig b/boards/gd/gd32f403z_eval/gd32f403z_eval_defconfig new file mode 100644 index 00000000000000..1c7051a83fb4ff --- /dev/null +++ b/boards/gd/gd32f403z_eval/gd32f403z_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f403z_eval/support/openocd.cfg b/boards/gd/gd32f403z_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f403z_eval/support/openocd.cfg rename to boards/gd/gd32f403z_eval/support/openocd.cfg diff --git a/boards/gd/gd32f407v_start/Kconfig.gd32f407v_start b/boards/gd/gd32f407v_start/Kconfig.gd32f407v_start new file mode 100644 index 00000000000000..6624205d86b7a1 --- /dev/null +++ b/boards/gd/gd32f407v_start/Kconfig.gd32f407v_start @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F407V_START + select SOC_GD32F407 diff --git a/boards/arm/gd32f407v_start/board.cmake b/boards/gd/gd32f407v_start/board.cmake similarity index 100% rename from boards/arm/gd32f407v_start/board.cmake rename to boards/gd/gd32f407v_start/board.cmake diff --git a/boards/gd/gd32f407v_start/board.yml b/boards/gd/gd32f407v_start/board.yml new file mode 100644 index 00000000000000..c4a99ab566e72d --- /dev/null +++ b/boards/gd/gd32f407v_start/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f407v_start + vendor: gd + socs: + - name: gd32f407 diff --git a/boards/arm/gd32f407v_start/doc/img/gd32f407v_start.webp b/boards/gd/gd32f407v_start/doc/img/gd32f407v_start.webp similarity index 100% rename from boards/arm/gd32f407v_start/doc/img/gd32f407v_start.webp rename to boards/gd/gd32f407v_start/doc/img/gd32f407v_start.webp diff --git a/boards/arm/gd32f407v_start/doc/index.rst b/boards/gd/gd32f407v_start/doc/index.rst similarity index 100% rename from boards/arm/gd32f407v_start/doc/index.rst rename to boards/gd/gd32f407v_start/doc/index.rst diff --git a/boards/arm/gd32f407v_start/gd32f407v_start-pinctrl.dtsi b/boards/gd/gd32f407v_start/gd32f407v_start-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f407v_start/gd32f407v_start-pinctrl.dtsi rename to boards/gd/gd32f407v_start/gd32f407v_start-pinctrl.dtsi diff --git a/boards/arm/gd32f407v_start/gd32f407v_start.dts b/boards/gd/gd32f407v_start/gd32f407v_start.dts similarity index 100% rename from boards/arm/gd32f407v_start/gd32f407v_start.dts rename to boards/gd/gd32f407v_start/gd32f407v_start.dts diff --git a/boards/arm/gd32f407v_start/gd32f407v_start.yaml b/boards/gd/gd32f407v_start/gd32f407v_start.yaml similarity index 100% rename from boards/arm/gd32f407v_start/gd32f407v_start.yaml rename to boards/gd/gd32f407v_start/gd32f407v_start.yaml diff --git a/boards/gd/gd32f407v_start/gd32f407v_start_defconfig b/boards/gd/gd32f407v_start/gd32f407v_start_defconfig new file mode 100644 index 00000000000000..b037de8dd841a9 --- /dev/null +++ b/boards/gd/gd32f407v_start/gd32f407v_start_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/gd/gd32f450i_eval/Kconfig.gd32f450i_eval b/boards/gd/gd32f450i_eval/Kconfig.gd32f450i_eval new file mode 100644 index 00000000000000..04574e6b6dfbba --- /dev/null +++ b/boards/gd/gd32f450i_eval/Kconfig.gd32f450i_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F450I_EVAL + select SOC_GD32F450 diff --git a/boards/arm/gd32f450i_eval/board.cmake b/boards/gd/gd32f450i_eval/board.cmake similarity index 100% rename from boards/arm/gd32f450i_eval/board.cmake rename to boards/gd/gd32f450i_eval/board.cmake diff --git a/boards/gd/gd32f450i_eval/board.yml b/boards/gd/gd32f450i_eval/board.yml new file mode 100644 index 00000000000000..a5da3b33c36a59 --- /dev/null +++ b/boards/gd/gd32f450i_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f450i_eval + vendor: gd + socs: + - name: gd32f450 diff --git a/boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.webp b/boards/gd/gd32f450i_eval/doc/img/gd32f450i_eval.webp similarity index 100% rename from boards/arm/gd32f450i_eval/doc/img/gd32f450i_eval.webp rename to boards/gd/gd32f450i_eval/doc/img/gd32f450i_eval.webp diff --git a/boards/arm/gd32f450i_eval/doc/index.rst b/boards/gd/gd32f450i_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f450i_eval/doc/index.rst rename to boards/gd/gd32f450i_eval/doc/index.rst diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi b/boards/gd/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi rename to boards/gd/gd32f450i_eval/gd32f450i_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.dts b/boards/gd/gd32f450i_eval/gd32f450i_eval.dts similarity index 100% rename from boards/arm/gd32f450i_eval/gd32f450i_eval.dts rename to boards/gd/gd32f450i_eval/gd32f450i_eval.dts diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml b/boards/gd/gd32f450i_eval/gd32f450i_eval.yaml similarity index 100% rename from boards/arm/gd32f450i_eval/gd32f450i_eval.yaml rename to boards/gd/gd32f450i_eval/gd32f450i_eval.yaml diff --git a/boards/gd/gd32f450i_eval/gd32f450i_eval_defconfig b/boards/gd/gd32f450i_eval/gd32f450i_eval_defconfig new file mode 100644 index 00000000000000..07ba35284c335b --- /dev/null +++ b/boards/gd/gd32f450i_eval/gd32f450i_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f450i_eval/support/openocd.cfg b/boards/gd/gd32f450i_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f450i_eval/support/openocd.cfg rename to boards/gd/gd32f450i_eval/support/openocd.cfg diff --git a/boards/gd/gd32f450v_start/Kconfig.gd32f450v_start b/boards/gd/gd32f450v_start/Kconfig.gd32f450v_start new file mode 100644 index 00000000000000..a666d7912652e7 --- /dev/null +++ b/boards/gd/gd32f450v_start/Kconfig.gd32f450v_start @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F450V_START + select SOC_GD32F450 diff --git a/boards/arm/gd32f450v_start/board.cmake b/boards/gd/gd32f450v_start/board.cmake similarity index 100% rename from boards/arm/gd32f450v_start/board.cmake rename to boards/gd/gd32f450v_start/board.cmake diff --git a/boards/gd/gd32f450v_start/board.yml b/boards/gd/gd32f450v_start/board.yml new file mode 100644 index 00000000000000..96e00536946112 --- /dev/null +++ b/boards/gd/gd32f450v_start/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f450v_start + vendor: gd + socs: + - name: gd32f450 diff --git a/boards/arm/gd32f450v_start/doc/img/gd32f450v_start.webp b/boards/gd/gd32f450v_start/doc/img/gd32f450v_start.webp similarity index 100% rename from boards/arm/gd32f450v_start/doc/img/gd32f450v_start.webp rename to boards/gd/gd32f450v_start/doc/img/gd32f450v_start.webp diff --git a/boards/arm/gd32f450v_start/doc/index.rst b/boards/gd/gd32f450v_start/doc/index.rst similarity index 100% rename from boards/arm/gd32f450v_start/doc/index.rst rename to boards/gd/gd32f450v_start/doc/index.rst diff --git a/boards/arm/gd32f450v_start/gd32f450v_start-pinctrl.dtsi b/boards/gd/gd32f450v_start/gd32f450v_start-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f450v_start/gd32f450v_start-pinctrl.dtsi rename to boards/gd/gd32f450v_start/gd32f450v_start-pinctrl.dtsi diff --git a/boards/arm/gd32f450v_start/gd32f450v_start.dts b/boards/gd/gd32f450v_start/gd32f450v_start.dts similarity index 100% rename from boards/arm/gd32f450v_start/gd32f450v_start.dts rename to boards/gd/gd32f450v_start/gd32f450v_start.dts diff --git a/boards/arm/gd32f450v_start/gd32f450v_start.yaml b/boards/gd/gd32f450v_start/gd32f450v_start.yaml similarity index 100% rename from boards/arm/gd32f450v_start/gd32f450v_start.yaml rename to boards/gd/gd32f450v_start/gd32f450v_start.yaml diff --git a/boards/gd/gd32f450v_start/gd32f450v_start_defconfig b/boards/gd/gd32f450v_start/gd32f450v_start_defconfig new file mode 100644 index 00000000000000..51f83a8ccd6624 --- /dev/null +++ b/boards/gd/gd32f450v_start/gd32f450v_start_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f450v_start/support/openocd.cfg b/boards/gd/gd32f450v_start/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f450v_start/support/openocd.cfg rename to boards/gd/gd32f450v_start/support/openocd.cfg diff --git a/boards/gd/gd32f450z_eval/Kconfig.gd32f450z_eval b/boards/gd/gd32f450z_eval/Kconfig.gd32f450z_eval new file mode 100644 index 00000000000000..3126837aaa2877 --- /dev/null +++ b/boards/gd/gd32f450z_eval/Kconfig.gd32f450z_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F450Z_EVAL + select SOC_GD32F450 diff --git a/boards/arm/gd32f450z_eval/board.cmake b/boards/gd/gd32f450z_eval/board.cmake similarity index 100% rename from boards/arm/gd32f450z_eval/board.cmake rename to boards/gd/gd32f450z_eval/board.cmake diff --git a/boards/gd/gd32f450z_eval/board.yml b/boards/gd/gd32f450z_eval/board.yml new file mode 100644 index 00000000000000..53e30794b6a9bb --- /dev/null +++ b/boards/gd/gd32f450z_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f450z_eval + vendor: gd + socs: + - name: gd32f450 diff --git a/boards/arm/gd32f450z_eval/doc/img/gd32f450z_eval.webp b/boards/gd/gd32f450z_eval/doc/img/gd32f450z_eval.webp similarity index 100% rename from boards/arm/gd32f450z_eval/doc/img/gd32f450z_eval.webp rename to boards/gd/gd32f450z_eval/doc/img/gd32f450z_eval.webp diff --git a/boards/arm/gd32f450z_eval/doc/index.rst b/boards/gd/gd32f450z_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f450z_eval/doc/index.rst rename to boards/gd/gd32f450z_eval/doc/index.rst diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi b/boards/gd/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi rename to boards/gd/gd32f450z_eval/gd32f450z_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval.dts b/boards/gd/gd32f450z_eval/gd32f450z_eval.dts similarity index 100% rename from boards/arm/gd32f450z_eval/gd32f450z_eval.dts rename to boards/gd/gd32f450z_eval/gd32f450z_eval.dts diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval.yaml b/boards/gd/gd32f450z_eval/gd32f450z_eval.yaml similarity index 100% rename from boards/arm/gd32f450z_eval/gd32f450z_eval.yaml rename to boards/gd/gd32f450z_eval/gd32f450z_eval.yaml diff --git a/boards/gd/gd32f450z_eval/gd32f450z_eval_defconfig b/boards/gd/gd32f450z_eval/gd32f450z_eval_defconfig new file mode 100644 index 00000000000000..4b47334704de17 --- /dev/null +++ b/boards/gd/gd32f450z_eval/gd32f450z_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f450z_eval/support/openocd.cfg b/boards/gd/gd32f450z_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f450z_eval/support/openocd.cfg rename to boards/gd/gd32f450z_eval/support/openocd.cfg diff --git a/boards/gd/gd32f470i_eval/Kconfig.gd32f470i_eval b/boards/gd/gd32f470i_eval/Kconfig.gd32f470i_eval new file mode 100644 index 00000000000000..09ef416cb798b6 --- /dev/null +++ b/boards/gd/gd32f470i_eval/Kconfig.gd32f470i_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32F470I_EVAL + select SOC_GD32F470 diff --git a/boards/arm/gd32f470i_eval/board.cmake b/boards/gd/gd32f470i_eval/board.cmake similarity index 100% rename from boards/arm/gd32f470i_eval/board.cmake rename to boards/gd/gd32f470i_eval/board.cmake diff --git a/boards/gd/gd32f470i_eval/board.yml b/boards/gd/gd32f470i_eval/board.yml new file mode 100644 index 00000000000000..a4205dc69d2600 --- /dev/null +++ b/boards/gd/gd32f470i_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32f470i_eval + vendor: gd + socs: + - name: gd32f470 diff --git a/boards/arm/gd32f470i_eval/doc/img/gd32f470i_eval.jpg b/boards/gd/gd32f470i_eval/doc/img/gd32f470i_eval.jpg similarity index 100% rename from boards/arm/gd32f470i_eval/doc/img/gd32f470i_eval.jpg rename to boards/gd/gd32f470i_eval/doc/img/gd32f470i_eval.jpg diff --git a/boards/arm/gd32f470i_eval/doc/index.rst b/boards/gd/gd32f470i_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32f470i_eval/doc/index.rst rename to boards/gd/gd32f470i_eval/doc/index.rst diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi b/boards/gd/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi rename to boards/gd/gd32f470i_eval/gd32f470i_eval-pinctrl.dtsi diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval.dts b/boards/gd/gd32f470i_eval/gd32f470i_eval.dts similarity index 100% rename from boards/arm/gd32f470i_eval/gd32f470i_eval.dts rename to boards/gd/gd32f470i_eval/gd32f470i_eval.dts diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval.yaml b/boards/gd/gd32f470i_eval/gd32f470i_eval.yaml similarity index 100% rename from boards/arm/gd32f470i_eval/gd32f470i_eval.yaml rename to boards/gd/gd32f470i_eval/gd32f470i_eval.yaml diff --git a/boards/gd/gd32f470i_eval/gd32f470i_eval_defconfig b/boards/gd/gd32f470i_eval/gd32f470i_eval_defconfig new file mode 100644 index 00000000000000..4b47334704de17 --- /dev/null +++ b/boards/gd/gd32f470i_eval/gd32f470i_eval_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_GPIO=y diff --git a/boards/arm/gd32f470i_eval/support/openocd.cfg b/boards/gd/gd32f470i_eval/support/openocd.cfg similarity index 100% rename from boards/arm/gd32f470i_eval/support/openocd.cfg rename to boards/gd/gd32f470i_eval/support/openocd.cfg diff --git a/boards/gd/gd32l233r_eval/Kconfig.gd32l233r_eval b/boards/gd/gd32l233r_eval/Kconfig.gd32l233r_eval new file mode 100644 index 00000000000000..ee489163d9a1af --- /dev/null +++ b/boards/gd/gd32l233r_eval/Kconfig.gd32l233r_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32L233R_EVAL + select SOC_GD32L233 diff --git a/boards/arm/gd32l233r_eval/board.cmake b/boards/gd/gd32l233r_eval/board.cmake similarity index 100% rename from boards/arm/gd32l233r_eval/board.cmake rename to boards/gd/gd32l233r_eval/board.cmake diff --git a/boards/gd/gd32l233r_eval/board.yml b/boards/gd/gd32l233r_eval/board.yml new file mode 100644 index 00000000000000..847def4fe2cc2f --- /dev/null +++ b/boards/gd/gd32l233r_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32l233r_eval + vendor: gd + socs: + - name: gd32l233 diff --git a/boards/arm/gd32l233r_eval/doc/img/gd32l233r_eval.jpg b/boards/gd/gd32l233r_eval/doc/img/gd32l233r_eval.jpg similarity index 100% rename from boards/arm/gd32l233r_eval/doc/img/gd32l233r_eval.jpg rename to boards/gd/gd32l233r_eval/doc/img/gd32l233r_eval.jpg diff --git a/boards/arm/gd32l233r_eval/doc/index.rst b/boards/gd/gd32l233r_eval/doc/index.rst similarity index 100% rename from boards/arm/gd32l233r_eval/doc/index.rst rename to boards/gd/gd32l233r_eval/doc/index.rst diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi b/boards/gd/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi similarity index 100% rename from boards/arm/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi rename to boards/gd/gd32l233r_eval/gd32l233r_eval-pinctrl.dtsi diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval.dts b/boards/gd/gd32l233r_eval/gd32l233r_eval.dts similarity index 100% rename from boards/arm/gd32l233r_eval/gd32l233r_eval.dts rename to boards/gd/gd32l233r_eval/gd32l233r_eval.dts diff --git a/boards/arm/gd32l233r_eval/gd32l233r_eval.yaml b/boards/gd/gd32l233r_eval/gd32l233r_eval.yaml similarity index 100% rename from boards/arm/gd32l233r_eval/gd32l233r_eval.yaml rename to boards/gd/gd32l233r_eval/gd32l233r_eval.yaml diff --git a/boards/gd/gd32l233r_eval/gd32l233r_eval_defconfig b/boards/gd/gd32l233r_eval/gd32l233r_eval_defconfig new file mode 100644 index 00000000000000..32b8efcc716584 --- /dev/null +++ b/boards/gd/gd32l233r_eval/gd32l233r_eval_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/gd/gd32vf103c_starter/Kconfig.gd32vf103c_starter b/boards/gd/gd32vf103c_starter/Kconfig.gd32vf103c_starter new file mode 100644 index 00000000000000..2671a8a98dd725 --- /dev/null +++ b/boards/gd/gd32vf103c_starter/Kconfig.gd32vf103c_starter @@ -0,0 +1,5 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32VF103C_STARTER + select SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103c_starter/board.cmake b/boards/gd/gd32vf103c_starter/board.cmake similarity index 100% rename from boards/riscv/gd32vf103c_starter/board.cmake rename to boards/gd/gd32vf103c_starter/board.cmake diff --git a/boards/gd/gd32vf103c_starter/board.yml b/boards/gd/gd32vf103c_starter/board.yml new file mode 100644 index 00000000000000..e91c7178af81af --- /dev/null +++ b/boards/gd/gd32vf103c_starter/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32vf103c_starter + vendor: gd + socs: + - name: gd32vf103 diff --git a/boards/riscv/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg b/boards/gd/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg similarity index 100% rename from boards/riscv/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg rename to boards/gd/gd32vf103c_starter/doc/img/gd32vf103c_starter.jpg diff --git a/boards/riscv/gd32vf103c_starter/doc/index.rst b/boards/gd/gd32vf103c_starter/doc/index.rst similarity index 100% rename from boards/riscv/gd32vf103c_starter/doc/index.rst rename to boards/gd/gd32vf103c_starter/doc/index.rst diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi b/boards/gd/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi similarity index 100% rename from boards/riscv/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi rename to boards/gd/gd32vf103c_starter/gd32vf103c_starter-pinctrl.dtsi diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter.dts b/boards/gd/gd32vf103c_starter/gd32vf103c_starter.dts similarity index 100% rename from boards/riscv/gd32vf103c_starter/gd32vf103c_starter.dts rename to boards/gd/gd32vf103c_starter/gd32vf103c_starter.dts diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter.yaml b/boards/gd/gd32vf103c_starter/gd32vf103c_starter.yaml similarity index 100% rename from boards/riscv/gd32vf103c_starter/gd32vf103c_starter.yaml rename to boards/gd/gd32vf103c_starter/gd32vf103c_starter.yaml diff --git a/boards/gd/gd32vf103c_starter/gd32vf103c_starter_defconfig b/boards/gd/gd32vf103c_starter/gd32vf103c_starter_defconfig new file mode 100644 index 00000000000000..1a94284e1b728e --- /dev/null +++ b/boards/gd/gd32vf103c_starter/gd32vf103c_starter_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GD32_HXTAL_8MHZ=y diff --git a/boards/riscv/gd32vf103c_starter/support/openocd.cfg b/boards/gd/gd32vf103c_starter/support/openocd.cfg similarity index 100% rename from boards/riscv/gd32vf103c_starter/support/openocd.cfg rename to boards/gd/gd32vf103c_starter/support/openocd.cfg diff --git a/boards/gd/gd32vf103v_eval/Kconfig.gd32vf103v_eval b/boards/gd/gd32vf103v_eval/Kconfig.gd32vf103v_eval new file mode 100644 index 00000000000000..77de39c9612d25 --- /dev/null +++ b/boards/gd/gd32vf103v_eval/Kconfig.gd32vf103v_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GD32VF103V_EVAL + select SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103v_eval/board.cmake b/boards/gd/gd32vf103v_eval/board.cmake similarity index 100% rename from boards/riscv/gd32vf103v_eval/board.cmake rename to boards/gd/gd32vf103v_eval/board.cmake diff --git a/boards/gd/gd32vf103v_eval/board.yml b/boards/gd/gd32vf103v_eval/board.yml new file mode 100644 index 00000000000000..3d12d916d384ff --- /dev/null +++ b/boards/gd/gd32vf103v_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: gd32vf103v_eval + vendor: gd + socs: + - name: gd32vf103 diff --git a/boards/riscv/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg b/boards/gd/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg similarity index 100% rename from boards/riscv/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg rename to boards/gd/gd32vf103v_eval/doc/img/gd32vf103v_eval.jpg diff --git a/boards/riscv/gd32vf103v_eval/doc/index.rst b/boards/gd/gd32vf103v_eval/doc/index.rst similarity index 100% rename from boards/riscv/gd32vf103v_eval/doc/index.rst rename to boards/gd/gd32vf103v_eval/doc/index.rst diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi b/boards/gd/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi similarity index 100% rename from boards/riscv/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi rename to boards/gd/gd32vf103v_eval/gd32vf103v_eval-pinctrl.dtsi diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval.dts b/boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts similarity index 100% rename from boards/riscv/gd32vf103v_eval/gd32vf103v_eval.dts rename to boards/gd/gd32vf103v_eval/gd32vf103v_eval.dts diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval.yaml b/boards/gd/gd32vf103v_eval/gd32vf103v_eval.yaml similarity index 100% rename from boards/riscv/gd32vf103v_eval/gd32vf103v_eval.yaml rename to boards/gd/gd32vf103v_eval/gd32vf103v_eval.yaml diff --git a/boards/gd/gd32vf103v_eval/gd32vf103v_eval_defconfig b/boards/gd/gd32vf103v_eval/gd32vf103v_eval_defconfig new file mode 100644 index 00000000000000..e34c644b2646cc --- /dev/null +++ b/boards/gd/gd32vf103v_eval/gd32vf103v_eval_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GD32_HXTAL_8MHZ=y + +CONFIG_GPIO=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/riscv/gd32vf103v_eval/support/openocd.cfg b/boards/gd/gd32vf103v_eval/support/openocd.cfg similarity index 100% rename from boards/riscv/gd32vf103v_eval/support/openocd.cfg rename to boards/gd/gd32vf103v_eval/support/openocd.cfg diff --git a/boards/gd/index.rst b/boards/gd/index.rst new file mode 100644 index 00000000000000..79f0a161ca837f --- /dev/null +++ b/boards/gd/index.rst @@ -0,0 +1,10 @@ +.. _boards-gd: + +GigaDevice Semiconductor +######################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/google/dragonclaw/Kconfig.google_dragonclaw b/boards/google/dragonclaw/Kconfig.google_dragonclaw new file mode 100644 index 00000000000000..37570bfc0e084e --- /dev/null +++ b/boards/google/dragonclaw/Kconfig.google_dragonclaw @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GOOGLE_DRAGONCLAW + select SOC_STM32F412CX diff --git a/boards/arm/google_dragonclaw/board.cmake b/boards/google/dragonclaw/board.cmake similarity index 100% rename from boards/arm/google_dragonclaw/board.cmake rename to boards/google/dragonclaw/board.cmake diff --git a/boards/google/dragonclaw/board.yml b/boards/google/dragonclaw/board.yml new file mode 100644 index 00000000000000..28e8b84ab4fedc --- /dev/null +++ b/boards/google/dragonclaw/board.yml @@ -0,0 +1,5 @@ +board: + name: google_dragonclaw + vendor: google + socs: + - name: stm32f412zx diff --git a/boards/arm/google_dragonclaw/doc/index.rst b/boards/google/dragonclaw/doc/index.rst similarity index 100% rename from boards/arm/google_dragonclaw/doc/index.rst rename to boards/google/dragonclaw/doc/index.rst diff --git a/boards/arm/google_dragonclaw/google_dragonclaw.dts b/boards/google/dragonclaw/google_dragonclaw.dts similarity index 100% rename from boards/arm/google_dragonclaw/google_dragonclaw.dts rename to boards/google/dragonclaw/google_dragonclaw.dts diff --git a/boards/arm/google_dragonclaw/google_dragonclaw.yaml b/boards/google/dragonclaw/google_dragonclaw.yaml similarity index 100% rename from boards/arm/google_dragonclaw/google_dragonclaw.yaml rename to boards/google/dragonclaw/google_dragonclaw.yaml diff --git a/boards/arm/google_dragonclaw/google_dragonclaw_defconfig b/boards/google/dragonclaw/google_dragonclaw_defconfig similarity index 81% rename from boards/arm/google_dragonclaw/google_dragonclaw_defconfig rename to boards/google/dragonclaw/google_dragonclaw_defconfig index c39f9c6a269fe1..3247707e4e4533 100644 --- a/boards/arm/google_dragonclaw/google_dragonclaw_defconfig +++ b/boards/google/dragonclaw/google_dragonclaw_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Google Inc # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412CX=y -CONFIG_BOARD_GOOGLE_DRAGONCLAW=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/google/index.rst b/boards/google/index.rst new file mode 100644 index 00000000000000..207a008b91c084 --- /dev/null +++ b/boards/google/index.rst @@ -0,0 +1,10 @@ +.. _boards-google: + +Google, Inc. +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/google/kukui/Kconfig.google_kukui b/boards/google/kukui/Kconfig.google_kukui new file mode 100644 index 00000000000000..51b960645eecf4 --- /dev/null +++ b/boards/google/kukui/Kconfig.google_kukui @@ -0,0 +1,5 @@ +# Copyright 2019 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GOOGLE_KUKUI + select SOC_STM32F098XX diff --git a/boards/arm64/bcm958402m2_a72/board.cmake b/boards/google/kukui/board.cmake similarity index 100% rename from boards/arm64/bcm958402m2_a72/board.cmake rename to boards/google/kukui/board.cmake diff --git a/boards/google/kukui/board.yml b/boards/google/kukui/board.yml new file mode 100644 index 00000000000000..699218ade22ae4 --- /dev/null +++ b/boards/google/kukui/board.yml @@ -0,0 +1,5 @@ +board: + name: google_kukui + vendor: google + socs: + - name: stm32f098xx diff --git a/boards/google/kukui/doc/index.rst b/boards/google/kukui/doc/index.rst new file mode 100644 index 00000000000000..a68586f311f228 --- /dev/null +++ b/boards/google/kukui/doc/index.rst @@ -0,0 +1,88 @@ +.. _google_kukui_board: + +Google Kukui EC +############### + +Overview +******** + +Kukui is a reference board for Chromium OS-based devices Krane and +Kodama. These are known as the Lenovo Chromebook Duet and 10e Chromebook +Tablet, respectively. + +Zephyr has support for the STM32-based embedded controller (EC) on-board. + +Hardware +******** + +- STM32F098RCH6 +- MT6370 battery charger +- BMM150 compass +- BMM160 gyroscope +- Connections to the MediaTek AP + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other features (such as I2C) are not available in Zephyr. + +The default configuration can be found in +:zephyr_file:`boards/google/kukui/google_kukui_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output +(push-pull or open-drain), as input (with or without pull-up or +pull-down), or as peripheral alternate function. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA10/PA9 +- I2C_1 SCL/SDA : PB8/PB9 +- I2C_2 SCL/SDA : PA11/PA12 +- Volume down : GPIOB pin 11 +- Volume up : GPIOB pin 10 +- Power : GPIOA pin 0 + +Programming and Debugging +************************* + +Build application as usual for the ``google_kukui`` board, and flash +using Servo V2, μServo, or Servo V4 (CCD). See the +`Chromium EC Flashing Documentation`_ for more information. + +Debugging +========= + +Use SWD with a J-Link or ST-Link. + +References +********** + +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/google_kukui/google_kukui.dts b/boards/google/kukui/google_kukui.dts similarity index 100% rename from boards/arm/google_kukui/google_kukui.dts rename to boards/google/kukui/google_kukui.dts diff --git a/boards/arm/google_kukui/google_kukui.yaml b/boards/google/kukui/google_kukui.yaml similarity index 100% rename from boards/arm/google_kukui/google_kukui.yaml rename to boards/google/kukui/google_kukui.yaml diff --git a/boards/google/kukui/google_kukui_defconfig b/boards/google/kukui/google_kukui_defconfig new file mode 100644 index 00000000000000..0196b219b8fca6 --- /dev/null +++ b/boards/google/kukui/google_kukui_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/google/twinkie_v2/Kconfig.google_twinkie_v2 b/boards/google/twinkie_v2/Kconfig.google_twinkie_v2 new file mode 100644 index 00000000000000..52f0de57ebb533 --- /dev/null +++ b/boards/google/twinkie_v2/Kconfig.google_twinkie_v2 @@ -0,0 +1,5 @@ +# Copyright 2023 The ChromiumOS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_GOOGLE_TWINKIE_V2 + select SOC_STM32G0B1XX diff --git a/boards/arm/google_twinkie_v2/board.cmake b/boards/google/twinkie_v2/board.cmake similarity index 100% rename from boards/arm/google_twinkie_v2/board.cmake rename to boards/google/twinkie_v2/board.cmake diff --git a/boards/google/twinkie_v2/board.yml b/boards/google/twinkie_v2/board.yml new file mode 100644 index 00000000000000..b77d79328f71a3 --- /dev/null +++ b/boards/google/twinkie_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: google_twinkie_v2 + vendor: google + socs: + - name: stm32g0b1xx diff --git a/boards/google/twinkie_v2/doc/index.rst b/boards/google/twinkie_v2/doc/index.rst new file mode 100644 index 00000000000000..42be6aa2958e21 --- /dev/null +++ b/boards/google/twinkie_v2/doc/index.rst @@ -0,0 +1,57 @@ +.. _google_twinkie_v2_board: + +Google Twinkie V2 +################# + +Overview +******** + +Google Twinkie V2 is a reference board for the google power delivery analyzer +(PDA) Twinkie V2. + +Hardware +******** + +- STM32G0B1REI6 + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/google/twinkie_v2/google_twinkie_v2_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- +- CC1_BUF : PA1 +- CC2_BUF : PA3 +- VBUS_READ_BUF : PB11 +- CSA_VBUS : PC4 +- CSA_CC2 : PC5 + +Programming and Debugging +************************* + +Build application as usual for the ``google_twinkie_v2`` board, and flash +using dfu-util or J-Link. + +Debugging +========= + +Use SWD with a J-Link or ST-Link. diff --git a/boards/arm/google_twinkie_v2/google_twinkie_v2.dts b/boards/google/twinkie_v2/google_twinkie_v2.dts similarity index 100% rename from boards/arm/google_twinkie_v2/google_twinkie_v2.dts rename to boards/google/twinkie_v2/google_twinkie_v2.dts diff --git a/boards/arm/google_twinkie_v2/google_twinkie_v2.yaml b/boards/google/twinkie_v2/google_twinkie_v2.yaml similarity index 100% rename from boards/arm/google_twinkie_v2/google_twinkie_v2.yaml rename to boards/google/twinkie_v2/google_twinkie_v2.yaml diff --git a/boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig b/boards/google/twinkie_v2/google_twinkie_v2_defconfig similarity index 80% rename from boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig rename to boards/google/twinkie_v2/google_twinkie_v2_defconfig index 040be2d3672562..3262a345bd28e5 100644 --- a/boards/arm/google_twinkie_v2/google_twinkie_v2_defconfig +++ b/boards/google/twinkie_v2/google_twinkie_v2_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G0B1XX=y - # GPIO Controller CONFIG_GPIO=y diff --git a/boards/hardkernel/index.rst b/boards/hardkernel/index.rst new file mode 100644 index 00000000000000..b37651add3c876 --- /dev/null +++ b/boards/hardkernel/index.rst @@ -0,0 +1,10 @@ +.. _boards-hardkernel: + +HardKernel +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/hardkernel/odroid_go/Kconfig b/boards/hardkernel/odroid_go/Kconfig new file mode 100644 index 00000000000000..b35c68b5a0e0e0 --- /dev/null +++ b/boards/hardkernel/odroid_go/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ODROID_GO + select SOC_ESP32_PROCPU if BOARD_ODROID_GO_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_ODROID_GO_ESP32_APPCPU diff --git a/boards/hardkernel/odroid_go/Kconfig.defconfig b/boards/hardkernel/odroid_go/Kconfig.defconfig new file mode 100644 index 00000000000000..345a0f4f64ee63 --- /dev/null +++ b/boards/hardkernel/odroid_go/Kconfig.defconfig @@ -0,0 +1,39 @@ +# ODROID-GO Game Kit configuration + +# Copyright (c) 2019 Yannis Damigos +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ODROID_GO_ESP32_PROCPU + +config DISK_DRIVER_SDMMC + default y if DISK_ACCESS + +config SPI + default y if DISK_DRIVER_SDMMC + +config ESP_SPIRAM + default y + +choice SPIRAM_TYPE + default SPIRAM_TYPE_ESPPSRAM64 +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ODROID_GO_ESP32_PROCPU + +if BOARD_ODROID_GO_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 4096 + +endif # BOARD_ODROID_GO_ESP32_APPCPU diff --git a/boards/hardkernel/odroid_go/Kconfig.odroid_go b/boards/hardkernel/odroid_go/Kconfig.odroid_go new file mode 100644 index 00000000000000..88d56badd919b3 --- /dev/null +++ b/boards/hardkernel/odroid_go/Kconfig.odroid_go @@ -0,0 +1,7 @@ +# ODROID-GO Game Kit configuration + +# Copyright (c) 2019 Yannis Damigos +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ODROID_GO + select SOC_ESP32_WROVER_E_N16R2 diff --git a/boards/xtensa/esp32s2_franzininho/Kconfig.sysbuild b/boards/hardkernel/odroid_go/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s2_franzininho/Kconfig.sysbuild rename to boards/hardkernel/odroid_go/Kconfig.sysbuild diff --git a/boards/xtensa/heltec_wifi_lora32_v2/board.cmake b/boards/hardkernel/odroid_go/board.cmake similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/board.cmake rename to boards/hardkernel/odroid_go/board.cmake diff --git a/boards/hardkernel/odroid_go/board.yml b/boards/hardkernel/odroid_go/board.yml new file mode 100644 index 00000000000000..fad513c5ee9f58 --- /dev/null +++ b/boards/hardkernel/odroid_go/board.yml @@ -0,0 +1,5 @@ +board: + name: odroid_go + vendor: hardkernel + socs: + - name: esp32 diff --git a/boards/xtensa/odroid_go/doc/img/odroid_go.jpg b/boards/hardkernel/odroid_go/doc/img/odroid_go.jpg similarity index 100% rename from boards/xtensa/odroid_go/doc/img/odroid_go.jpg rename to boards/hardkernel/odroid_go/doc/img/odroid_go.jpg diff --git a/boards/hardkernel/odroid_go/doc/index.rst b/boards/hardkernel/odroid_go/doc/index.rst new file mode 100644 index 00000000000000..9fa4d107b1398b --- /dev/null +++ b/boards/hardkernel/odroid_go/doc/index.rst @@ -0,0 +1,245 @@ +.. _odroid_go: + +ODROID-GO +######### + +Overview +******** + +ODROID-GO Game Kit is a "Do it yourself" ("DIY") portable game console by +HardKernel. It features a custom ESP32-WROVER with 16 MB flash and it operates +from 80 MHz - 240 MHz [1]_. + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 80 - 240MHz +- 4 MB of PSRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- 2.4 inch 320x240 TFT LCD +- Speaker +- Micro SD card slot +- Micro USB port (battery charging and USB_UART data communication +- Input Buttons (Menu, Volume, Select, Start, A, B, Direction Pad) +- Expansion port (I2C, GPIO, SPI) +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +.. figure:: img/odroid_go.jpg + :align: center + :alt: ODROID-GO + + ODROID-Go Game Kit + +External Connector +================== + ++-------+------------------+-------------------------+ +| PIN # | Signal Name | ESP32-WROVER Functions | ++=======+==================+=========================+ +| 1 | GND | GND | ++-------+------------------+-------------------------+ +| 2 | VSPI.SCK (IO18) | GPIO18, VSPICLK | ++-------+------------------+-------------------------+ +| 3 | IO12 | GPIO12 | ++-------+------------------+-------------------------+ +| 4 | IO15 | GPIO15, ADC2_CH3 | ++-------+------------------+-------------------------+ +| 5 | IO4 | GPIO4, ADC2_CH0 | ++-------+------------------+-------------------------+ +| 6 | P3V3 | 3.3 V | ++-------+------------------+-------------------------+ +| 7 | VSPI.MISO (IO19) | GPIO19, VSPIQ | ++-------+------------------+-------------------------+ +| 8 | VSPI.MOSI (IO23) | GPIO23, VSPID | ++-------+------------------+-------------------------+ +| 9 | N.C | N/A | ++-------+------------------+-------------------------+ +| 10 | VBUS | USB VBUS (5V) | ++-------+------------------+-------------------------+ + +Supported Features +================== + +The Zephyr odroid_go board configuration supports the following hardware +features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ + + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: odroid_go + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``odroid_go`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! odroid_go + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: odroid_go/esp32/procpu + :goals: debug + +References +********** + +.. target-notes:: + +.. [1] https://wiki.odroid.com/odroid_go/odroid_go +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/odroid_go/odroid_go-pinctrl.dtsi b/boards/hardkernel/odroid_go/odroid_go-pinctrl.dtsi similarity index 100% rename from boards/xtensa/odroid_go/odroid_go-pinctrl.dtsi rename to boards/hardkernel/odroid_go/odroid_go-pinctrl.dtsi diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.dts b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.dts new file mode 100644 index 00000000000000..6b59353de6d788 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "ODROID-GO Game Kit APPCPU"; + compatible = "hardkernel,odroid_go", "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.yaml b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.yaml new file mode 100644 index 00000000000000..a5a1c003ef35ca --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: odroid_go/esp32/appcpu +name: ODROID-GO +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: hardkernel diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.dts new file mode 100644 index 00000000000000..caf722d8cc9893 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.dts @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2019 Yannis Damigos + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "odroid_go-pinctrl.dtsi" +#include + +/ { + model = "ODROID-GO Game Kit PROCPU"; + compatible = "hardkernel,odroid_go", "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ili9341; + }; + + leds { + compatible = "gpio-leds"; + blue_led: led { + gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; + label = "Status Led"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + menu_button: menu_button { + label = "Menu"; + gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + volume_button: volume_button { + label = "Volume"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + select_button: select_button { + label = "Select"; + gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + a_button: a_button { + label = "A"; + gpios = <&gpio1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + b_button: b_button { + label = "B"; + gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + start_button: start_button { + label = "Start"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + lcd_backlight_en { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_enable"; + enable-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + aliases { + uart-0 = &uart0; + led0 = &blue_led; + sw0 = &menu_button; + watchdog0 = &wdt0; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9341: ili9341@0 { + compatible = "ilitek,ili9341"; + mipi-max-frequency = <25000000>; + pixel-format = <0>; + reg = <0>; + rotation = <270>; + width = <320>; + height = <240>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; + + blue-led-disable { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + + sdhc0: sdhc@1 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <1>; + status = "okay"; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + spi-max-frequency = <20000000>; + }; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.yaml b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.yaml new file mode 100644 index 00000000000000..59363bb4ee92e4 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu.yaml @@ -0,0 +1,18 @@ +identifier: odroid_go/esp32/procpu +name: ODROID-GO +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: hardkernel diff --git a/boards/hardkernel/odroid_go/odroid_go_esp32_procpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu_defconfig new file mode 100644 index 00000000000000..5de7f124113557 --- /dev/null +++ b/boards/hardkernel/odroid_go/odroid_go_esp32_procpu_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y + +# required to enable LCD backlight +CONFIG_REGULATOR=y diff --git a/boards/xtensa/heltec_wifi_lora32_v2/CMakeLists.txt b/boards/heltec/heltec_wifi_lora32_v2/CMakeLists.txt similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/CMakeLists.txt rename to boards/heltec/heltec_wifi_lora32_v2/CMakeLists.txt diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig b/boards/heltec/heltec_wifi_lora32_v2/Kconfig new file mode 100644 index 00000000000000..bfffbcb956375c --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIFI_LORA32_V2 + select SOC_ESP32_PROCPU if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_APPCPU diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig new file mode 100644 index 00000000000000..4f459aa0ca4250 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.defconfig @@ -0,0 +1,26 @@ +# HELTEC board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_HELTEC_WIFI_LORA32_V2_ESP32_PROCPU + +if BOARD_HELTEC_WIFI_LORA32_V2_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_HELTEC_WIFI_LORA_V2_ESP32_APPCPU diff --git a/boards/heltec/heltec_wifi_lora32_v2/Kconfig.heltec_wifi_lora32_v2 b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.heltec_wifi_lora32_v2 new file mode 100644 index 00000000000000..0e5d5c62da61cc --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.heltec_wifi_lora32_v2 @@ -0,0 +1,7 @@ +# HELTEC ESP32 board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIFI_LORA32_V2 + select SOC_ESP32_D0WD_V3 diff --git a/boards/xtensa/esp32s2_saola/Kconfig.sysbuild b/boards/heltec/heltec_wifi_lora32_v2/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s2_saola/Kconfig.sysbuild rename to boards/heltec/heltec_wifi_lora32_v2/Kconfig.sysbuild diff --git a/boards/xtensa/odroid_go/board.cmake b/boards/heltec/heltec_wifi_lora32_v2/board.cmake similarity index 100% rename from boards/xtensa/odroid_go/board.cmake rename to boards/heltec/heltec_wifi_lora32_v2/board.cmake diff --git a/boards/heltec/heltec_wifi_lora32_v2/board.yml b/boards/heltec/heltec_wifi_lora32_v2/board.yml new file mode 100644 index 00000000000000..e87344a9766696 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/board.yml @@ -0,0 +1,5 @@ +board: + name: heltec_wifi_lora32_v2 + vendor: heltec + socs: + - name: esp32 diff --git a/boards/xtensa/heltec_wifi_lora32_v2/board_init.c b/boards/heltec/heltec_wifi_lora32_v2/board_init.c similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/board_init.c rename to boards/heltec/heltec_wifi_lora32_v2/board_init.c diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst new file mode 100644 index 00000000000000..07355a6d70b22d --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst @@ -0,0 +1,208 @@ +.. _heltec_wifi_lora32_v2: + +Heltec WiFi LoRa 32 (V2) +######################## + +Overview +******** + +Heltec WiFi LoRa 32 is a classic IoT dev-board designed & produced by Heltec Automation(TM), it's a highly +integrated product based on ESP32 + SX127x, it has Wi-Fi, BLE, LoRa functions, also Li-Po battery management +system, 0.96" OLED are also included. [1]_ + +The features include the following: + +- Microprocessor: ESP32 (dual-core 32-bit MCU + ULP core) +- LoRa node chip SX1276/SX1278 +- Micro USB interface with a complete voltage regulator, ESD protection, short circuit protection, + RF shielding, and other protection measures +- Onboard SH1.25-2 battery interface, integrated lithium battery management system +- Integrated WiFi, LoRa, Bluetooth three network connections, onboard Wi-Fi, Bluetooth dedicated 2.4GHz + metal 3D antenna, reserved IPEX (U.FL) interface for LoRa use +- Onboard 0.96-inch 128*64 dot matrix OLED display +- Integrated CP2102 USB to serial port chip + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: heltec_wifi_lora32_v2 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``heltec_wifi_lora32_v2`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! heltec_wifi_lora32_v2 + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wifi_lora32_v2/esp32/procpu + :goals: debug + +Utilizing Hardware Features +*************************** + +Onboard OLED display +==================== + +The onboard OLED display is of type ``ssd1306``, has 128*64 pixels and is +connected via I2C. It can therefore be used by enabling the +:ref:`ssd1306_128_shield` as shown in the following for the :zephyr:code-sample:`lvgl` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/subsys/display/lvgl + :board: heltec_wifi_lora32_v2/esp32/procpu + :shield: ssd1306_128x64 + :goals: flash + +References +********** + +- `Heltec WiFi LoRa (v2) Pinout Diagram `_ +- `Heltec WiFi LoRa (v2) Schematic Diagrams `_ +- `ESP32 Toolchain `_ +- `esptool documentation `_ +- `OpenOCD ESP32 `_ + +.. [1] https://heltec.org/project/wifi-lora-32/ diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi rename to boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2-pinctrl.dtsi diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.dts new file mode 100644 index 00000000000000..4cf9e26b89d45c --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Heltec Wi-Fi Lora32 V2 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.yaml b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.yaml new file mode 100644 index 00000000000000..373c6b0eae9949 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: heltec_wifi_lora32_v2/esp32/appcpu +name: ESP32 DEVKITC WROVER APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.dts new file mode 100644 index 00000000000000..5e1c8c6c6ff122 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.dts @@ -0,0 +1,161 @@ +/* + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "heltec_wifi_lora32_v2-pinctrl.dtsi" +#include + +/ { + model = "Heltec Wi-Fi Lora32 V2 PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + led0 = &led0; + sw0 = &button0; + watchdog0 = &wdt0; + lora0 = &lora0; + }; + + leds { + compatible = "gpio-leds"; + led0: led { + gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; + label = "White LED"; + }; + + vext: vext { + gpios = <&gpio0 21 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "External VCC"; + }; + + oledrst: oledrst { + gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>; + label = "OLED Reset"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "PRG Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + lora0: lora@0 { + compatible = "semtech,sx1276"; + reg = <0>; + reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + dio-gpios = + /* SX1276 D0 -> GPIO26 */ + <&gpio0 26 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 -> GPIO35 */ + <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, + /* SX1276 D1 -> GPIO34 */ + <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; + spi-max-frequency = <1000000>; + power-amplifier-output = "pa-boost"; + }; +}; + +&flash0 { + /* the board is using plain d0wd SoC part without the flash + * so any additional flash size should be defined at the board level + */ + reg = <0x0 DT_SIZE_M(8)>; + + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; + +/* Required by the ssd1306_128x64 shield which enables the OLED display */ +arduino_i2c: &i2c0 {}; diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.yaml b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.yaml new file mode 100644 index 00000000000000..f8571589d7a123 --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu.yaml @@ -0,0 +1,17 @@ +identifier: heltec_wifi_lora32_v2/esp32/procpu +name: HELTEC WiFi LoRa 32 (V2) Board +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - watchdog + - uart + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: espressif diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu_defconfig b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu_defconfig new file mode 100644 index 00000000000000..f029cac9e9e77b --- /dev/null +++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/CMakeLists.txt b/boards/heltec/heltec_wireless_stick_lite_v3/CMakeLists.txt similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/CMakeLists.txt rename to boards/heltec/heltec_wireless_stick_lite_v3/CMakeLists.txt diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig new file mode 100644 index 00000000000000..fc8b7634c1df42 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIRELESS_STICK_LITE_V3 + select SOC_ESP32S3_PROCPU if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig new file mode 100644 index 00000000000000..82915e44b949b0 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Heltec Wireless Stick Lite (V3) board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# Copyright (c) 2023 The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_PROCPU + +if BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_HELTEC_WIRELESS_STICK_LITE_V3_ESP32S3_APPCPU diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.heltec_wireless_stick_lite_v3 b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.heltec_wireless_stick_lite_v3 new file mode 100644 index 00000000000000..d868ea29de2ad9 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.heltec_wireless_stick_lite_v3 @@ -0,0 +1,8 @@ +# Heltec Wireless Stick Lite (V3) board configuration + +# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) +# Copyright (c) 2023 The Zephyr Project Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HELTEC_WIRELESS_STICK_LITE_V3 + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.sysbuild b/boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s3_devkitm/Kconfig.sysbuild rename to boards/heltec/heltec_wireless_stick_lite_v3/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s2_lolin_mini/board.cmake b/boards/heltec/heltec_wireless_stick_lite_v3/board.cmake similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/board.cmake rename to boards/heltec/heltec_wireless_stick_lite_v3/board.cmake diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/board.yml b/boards/heltec/heltec_wireless_stick_lite_v3/board.yml new file mode 100644 index 00000000000000..12cb133cb4fb4d --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/board.yml @@ -0,0 +1,5 @@ +board: + name: heltec_wireless_stick_lite_v3 + vendor: heltec + socs: + - name: esp32s3 diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/board_init.c b/boards/heltec/heltec_wireless_stick_lite_v3/board_init.c similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/board_init.c rename to boards/heltec/heltec_wireless_stick_lite_v3/board_init.c diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp b/boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp rename to boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3.webp diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp b/boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp rename to boards/heltec/heltec_wireless_stick_lite_v3/doc/heltec_wireless_stick_lite_v3_pinout.webp diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst new file mode 100644 index 00000000000000..987eeb9f0f1ee6 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst @@ -0,0 +1,306 @@ +.. heltec_wireless_stick_lite_v3: + +HelTec Wireless Stick Lite (V3) +############################### + +Overview +******** + +HelTec Wireless Stick Lite (V3) is a development board with Wi-Fi, Bluetooth and LoRa support. It is designed and produced by HelTec Automation(TM). [1]_ + +.. figure:: heltec_wireless_stick_lite_v3.webp + :width: 400px + :align: center + :alt: HelTec Wireless Stick Lite (V3) + + HelTec Wireless Stick Lite (V3) (Credit: Chengdu HelTec Automation Technology Co., Ltd.) + +Hardware +******** + +The main hardware features are: + +- ESP32-S3FN8 low-power MCU-based SoC (dual-core Xtensa® 32-bit LX7 microprocessor, five stage pipeline rack Structure, main frequency up to 240 MHz). +- Semtech SX1262 LoRa node chip +- Type-C USB interface with a complete voltage regulator, ESD protection, short circuit protection, RF shielding, and other protection measures (note: you need an USB-A to USB-C cable if you want to power-up the board from USB). +- Onboard SH1.25-2 battery interface, integrated lithium battery management system (charge and discharge management, overcharge protection, battery power detection, USB / battery power automatic switching). +- Integrated WiFi and Bluetooth interfaces with 2.4GHz metal spring antenna and reserved IPEX (U.FL) interface for LoRa use. +- Integrated CP2102 USB to serial port chip, convenient for program downloading, debugging information printing. +- Good RF circuit design and low-power design. + +Supported Features +================== +- LoRa via SPI +- UART0 (USB Serial via CP2102) +- UART1 +- I2C +- CAN (optional, need to enable) +- PWM LED +- User Switch / Button + +Connections and IOs +=================== + +.. figure:: heltec_wireless_stick_lite_v3_pinout.webp + :width: 600px + :align: center + :alt: HelTec Wireless Stick Lite (V3) Pinout + + Pinout (Credit: Chengdu HelTec Automation Technology Co., Ltd.) + +.. table:: HelTec Wireless Stick Lite (V3) Pinout + :widths: auto + + +--------+---------+-----------------------------+ + | Header | Function| Description | + +========+=========+=============================+ + | J2.1 | Ve | | + +--------+---------+-----------------------------+ + | J2.2 | GND | | + +--------+---------+-----------------------------+ + | J2.3 | | | + +--------+---------+-----------------------------+ + | J2.4 | U0RXD | Zephyr Console+Shell | + +--------+---------+-----------------------------+ + | J2.5 | U0TXD | Zephyr Console+Shell | + +--------+---------+-----------------------------+ + | J2.6 | | | + +--------+---------+-----------------------------+ + | J2.7 | | | + +--------+---------+-----------------------------+ + | J2.8 | GPIO35 | PWM LED Control | + +--------+---------+-----------------------------+ + | J2.9 | GPIO36 | Vext Control | + +--------+---------+-----------------------------+ + | J2.10 | GPIO37 | ADC Control | + +--------+---------+-----------------------------+ + | J2.11 | | | + +--------+---------+-----------------------------+ + | J2.12 | GPIO39 | | + +--------+---------+-----------------------------+ + | J2.13 | GPIO40 | | + +--------+---------+-----------------------------+ + | J2.14 | GPIO41 | | + +--------+---------+-----------------------------+ + | J2.15 | GPIO42 | | + +--------+---------+-----------------------------+ + | J2.16 | GPIO45 | | + +--------+---------+-----------------------------+ + | J2.17 | GPIO46 | | + +--------+---------+-----------------------------+ + | J2.18 | ADC1_CH0| Battery Voltage Measurement | + +--------+---------+-----------------------------+ + | J2.19 | | | + +--------+---------+-----------------------------+ + | J2.20 | | | + +--------+---------+-----------------------------+ + | J3.1 | 5V | | + +--------+---------+-----------------------------+ + | J3.2 | 3V3 | | + +--------+---------+-----------------------------+ + | J3.3 | GND | | + +--------+---------+-----------------------------+ + | J3.4 | GPIO47 | | + +--------+---------+-----------------------------+ + | J3.5 | GPIO48 | | + +--------+---------+-----------------------------+ + | J3.6 | GPIO0 | User Switch | + +--------+---------+-----------------------------+ + | J3.7 | | | + +--------+---------+-----------------------------+ + | J3.8 | | | + +--------+---------+-----------------------------+ + | J3.9 | U1RXD | UART 1 | + +--------+---------+-----------------------------+ + | J3.10 | GPIO21 | | + +--------+---------+-----------------------------+ + | J3.11 | | | + +--------+---------+-----------------------------+ + | J3.12 | U1TXD | UART 1 | + +--------+---------+-----------------------------+ + | J3.13 | | | + +--------+---------+-----------------------------+ + | J3.14 | NC | Reset Switch | + +--------+---------+-----------------------------+ + | J3.15 | | | + +--------+---------+-----------------------------+ + | J3.16 | | | + +--------+---------+-----------------------------+ + | J3.17 | | | + +--------+---------+-----------------------------+ + | J3.18 | | | + +--------+---------+-----------------------------+ + | J3.19 | TWAI_TX | CAN (optional) | + +--------+---------+-----------------------------+ + | J3.20 | TWAI_RX | CAN (optional) | + +--------+---------+-----------------------------+ + + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Programming and Debugging +************************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the EPS32-S3 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: heltec_wireless_stick_lite_v3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32S3 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``heltec_wireless_stick_lite_v3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! heltec_wireless_stick_lite_v3 + +Debugging +========= + +As with much custom hardware, the ESP32S3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: heltec_wireless_stick_lite_v3/esp32s3/procpu + :goals: debug + +References +********** + +- `Heltec Wireless Stick Lite (v3) Pinout Diagram `_ +- `Heltec Wireless Stick Lite (v3) Schematic Diagrams `_ +- `ESP-IDF Programming Guide `_ +- `esptool documentation `_ +- `OpenOCD ESP32 `_ + +.. [1] https://heltec.org/project/wireless-stick-lite-v2/ diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi rename to boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3-pinctrl.dtsi diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.dts new file mode 100644 index 00000000000000..6c49e64e8d1c90 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Heltec Wireless Stick Lite V3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.yaml b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000000..a465da8f94dc97 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: heltec_wireless_stick_lite_v3/esp32s3/appcpu +name: ESP32-S3 DevKitM APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: heltec diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.dts new file mode 100644 index 00000000000000..38d870a6fbb260 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.dts @@ -0,0 +1,216 @@ +/* + * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) + * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. + * Copyright (c) 2023 The Zephyr Project Contributors + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "heltec_wireless_stick_lite_v3-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Heltec Wireless Stick Lite V3 PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + pwm-0 = &ledc0; + pwm-led0 = &pwm_led_white; + uart-0 = &uart0; + uart-1 = &uart1; + i2c-0 = &i2c0; + lora0 = &lora0; + sw0 = &button0; + watchdog0 = &wdt0; + }; + + leds { + compatible = "gpio-leds"; + + vext: vext { + gpios = <&gpio0 36 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Vext Control"; + }; + + adc: adc { + gpios = <&gpio0 37 GPIO_ACTIVE_LOW>; + label = "ADC Control"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led_white: pwm_led_gpio0_35 { + label = "White PWM LED"; + pwms = <&ledc0 0 PWM_MSEC(10) PWM_POLARITY_NORMAL>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "USER SW"; + zephyr,code = ; + }; + }; + + vbatt { + compatible = "voltage-divider"; + io-channels = <&adc1 0>; + output-ohms = <100000>; + full-ohms = <(100000 + 390000)>; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&adc1 { + status ="okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + channel0@0 { + reg = <0x0>; + timer = <0>; + }; +}; + +&i2c0 { + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + lora0: lora@0 { + compatible = "semtech,sx1262"; + reg = <0>; + reset-gpios = <&gpio0 12 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + busy-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; + dio1-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + dio2-tx-enable; + dio3-tcxo-voltage = ; + tcxo-power-startup-delay-ms = <5>; + spi-max-frequency = <16000000>; + }; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.yaml b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.yaml new file mode 100644 index 00000000000000..91221f8616b160 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu.yaml @@ -0,0 +1,23 @@ +identifier: heltec_wireless_stick_lite_v3/esp32s3/procpu +name: Heltec Wireless Stick Lite (V3) +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma + - lora +testing: + ignore_tags: + - net + - bluetooth +vendor: heltec diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu_defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000000..2dfe1853d5cc90 --- /dev/null +++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_esp32s3_procpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CLOCK_CONTROL=y +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_PWM=y +CONFIG_SERIAL=y +CONFIG_SPI=y +CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/esp32s3_luatos_core/support/openocd.cfg b/boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/support/openocd.cfg rename to boards/heltec/heltec_wireless_stick_lite_v3/support/openocd.cfg diff --git a/boards/heltec/index.rst b/boards/heltec/index.rst new file mode 100644 index 00000000000000..5e8fb67eea2071 --- /dev/null +++ b/boards/heltec/index.rst @@ -0,0 +1,10 @@ +.. _boards-heltec: + +Heltec +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/holyiot/index.rst b/boards/holyiot/index.rst new file mode 100644 index 00000000000000..9fb2705a252446 --- /dev/null +++ b/boards/holyiot/index.rst @@ -0,0 +1,10 @@ +.. _boards-holyiot: + +Shenzhen Holyiot Technology Co. +############################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/holyiot/yj16019/Kconfig.defconfig b/boards/holyiot/yj16019/Kconfig.defconfig new file mode 100644 index 00000000000000..c4298c49d6e671 --- /dev/null +++ b/boards/holyiot/yj16019/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Holyiot YJ-16019 board configuration + +# Copyright (c) 2019 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HOLYIOT_YJ16019 + +config BT_CTLR + default BT + +endif # BOARD_HOLYIOT_YJ16019 diff --git a/boards/holyiot/yj16019/Kconfig.holyiot_yj16019 b/boards/holyiot/yj16019/Kconfig.holyiot_yj16019 new file mode 100644 index 00000000000000..6db73feb4059a5 --- /dev/null +++ b/boards/holyiot/yj16019/Kconfig.holyiot_yj16019 @@ -0,0 +1,7 @@ +# Holyiot YJ-16019 board configuration + +# Copyright (c) 2019 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HOLYIOT_YJ16019 + select SOC_NRF52832_QFAA diff --git a/boards/arm/holyiot_yj16019/board.cmake b/boards/holyiot/yj16019/board.cmake similarity index 100% rename from boards/arm/holyiot_yj16019/board.cmake rename to boards/holyiot/yj16019/board.cmake diff --git a/boards/holyiot/yj16019/board.yml b/boards/holyiot/yj16019/board.yml new file mode 100644 index 00000000000000..e8ab16bc427d5e --- /dev/null +++ b/boards/holyiot/yj16019/board.yml @@ -0,0 +1,5 @@ +board: + name: holyiot_yj16019 + vendor: holyiot + socs: + - name: nrf52832 diff --git a/boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_front.jpg b/boards/holyiot/yj16019/doc/img/holyiot_yj16019_front.jpg similarity index 100% rename from boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_front.jpg rename to boards/holyiot/yj16019/doc/img/holyiot_yj16019_front.jpg diff --git a/boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_pcb.jpg b/boards/holyiot/yj16019/doc/img/holyiot_yj16019_pcb.jpg similarity index 100% rename from boards/arm/holyiot_yj16019/doc/img/holyiot_yj16019_pcb.jpg rename to boards/holyiot/yj16019/doc/img/holyiot_yj16019_pcb.jpg diff --git a/boards/holyiot/yj16019/doc/index.rst b/boards/holyiot/yj16019/doc/index.rst new file mode 100644 index 00000000000000..7ecbf5b0931aca --- /dev/null +++ b/boards/holyiot/yj16019/doc/index.rst @@ -0,0 +1,147 @@ +.. _holyiot_yj16019: + +Holyiot YJ-16019 +################ + +Overview +******** + +The `Holyiot`_ YJ-16019 hardware provides support for the Nordic +Semiconductor nRF52832 ARM Cortex-M4 CPU and the following devices: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/holyiot_yj16019_front.jpg + :align: center + :alt: Holyiot YJ-16019 + + Holyiot YJ-16019 (Credit: Holyiot) + +The board is equipped with one LED, one push button, and is powered by +a CR2032 coin cell. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +The nRF52832 of the Holyiot YJ-16019 is clocked by an external crystal with a frequency of 32 MHz +(Y1). The 32.768 kHz crystal (Y2) shown on the board schematics is not mounted. + +Supported Features +================== + +The holyiot_yj16019 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LED and push button +------------------- + +* Push button = P0.28 +* LED = P0.29 + +Programming and Debugging +************************* + +Applications for the ``holyiot_yj16019`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, an external +Segger J-Link is required since the board does not have any on-board +debug IC. + +The following pins of the Segger J-Link must be connected to the following test +pads on the PCB (see image): + +* VTref = VCC +* GND = GND +* SWDIO = SDO +* SWCLK = SCK + +.. figure:: img/holyiot_yj16019_pcb.jpg + :align: center + :alt: Holyiot YJ-16019 PCB + + Holyiot YJ-16019 PCB (Credit: Holyiot) + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: holyiot_yj16019 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +nRF52x-based boards with a Segger debugger. + + +Testing the LED and button on the Holyiot YJ-16019 +************************************************** + +There are 2 samples that allow you to test that the button and LED on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found +in :zephyr_file:`boards/holyiot/yj16019/holyiot_yj16019.dts`. + +References +********** + +.. target-notes:: + +.. _Holyiot: http://www.holyiot.com +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019-pinctrl.dtsi b/boards/holyiot/yj16019/holyiot_yj16019-pinctrl.dtsi similarity index 100% rename from boards/arm/holyiot_yj16019/holyiot_yj16019-pinctrl.dtsi rename to boards/holyiot/yj16019/holyiot_yj16019-pinctrl.dtsi diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019.dts b/boards/holyiot/yj16019/holyiot_yj16019.dts similarity index 100% rename from boards/arm/holyiot_yj16019/holyiot_yj16019.dts rename to boards/holyiot/yj16019/holyiot_yj16019.dts diff --git a/boards/arm/holyiot_yj16019/holyiot_yj16019.yaml b/boards/holyiot/yj16019/holyiot_yj16019.yaml similarity index 100% rename from boards/arm/holyiot_yj16019/holyiot_yj16019.yaml rename to boards/holyiot/yj16019/holyiot_yj16019.yaml diff --git a/boards/holyiot/yj16019/holyiot_yj16019_defconfig b/boards/holyiot/yj16019/holyiot_yj16019_defconfig new file mode 100644 index 00000000000000..cee867613f063e --- /dev/null +++ b/boards/holyiot/yj16019/holyiot_yj16019_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +# 32kHz clock source +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/arm/bt510/pre_dt_board.cmake b/boards/holyiot/yj16019/pre_dt_board.cmake similarity index 100% rename from boards/arm/bt510/pre_dt_board.cmake rename to boards/holyiot/yj16019/pre_dt_board.cmake diff --git a/boards/index.rst b/boards/index.rst index 9c843c9e95ba09..77814350d9ed23 100644 --- a/boards/index.rst +++ b/boards/index.rst @@ -15,15 +15,17 @@ available under :zephyr_file:`doc/templates/board.tmpl`. .. toctree:: :maxdepth: 2 + :glob: - arc/index.rst - arm/index.rst - arm64/index.rst - mips/index.rst - nios2/index.rst - posix/index.rst - riscv/index.rst - sparc/index.rst - x86/index.rst - xtensa/index.rst - shields/index.rst + */index + +.. _boards-shields: + +Shields +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + shields/**/* diff --git a/boards/infineon/index.rst b/boards/infineon/index.rst new file mode 100644 index 00000000000000..729b67d60a6b2d --- /dev/null +++ b/boards/infineon/index.rst @@ -0,0 +1,10 @@ +.. _boards-cypress: + +Infineon Technologies +##################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/infineon/xmc45_relax_kit/Kconfig.defconfig b/boards/infineon/xmc45_relax_kit/Kconfig.defconfig new file mode 100644 index 00000000000000..b47f54cf8abdb0 --- /dev/null +++ b/boards/infineon/xmc45_relax_kit/Kconfig.defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +if BOARD_XMC45_RELAX_KIT + +if NETWORKING + +config NET_L2_ETHERNET + default y +config MDIO + default y +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +endif # BOARD_XMC45_RELAX_KIT diff --git a/boards/infineon/xmc45_relax_kit/Kconfig.xmc45_relax_kit b/boards/infineon/xmc45_relax_kit/Kconfig.xmc45_relax_kit new file mode 100644 index 00000000000000..e88549aa49c0ea --- /dev/null +++ b/boards/infineon/xmc45_relax_kit/Kconfig.xmc45_relax_kit @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +config BOARD_XMC45_RELAX_KIT + select SOC_XMC4500 + select SOC_PART_NUMBER_F100X1024 diff --git a/boards/arm/xmc45_relax_kit/board.cmake b/boards/infineon/xmc45_relax_kit/board.cmake similarity index 100% rename from boards/arm/xmc45_relax_kit/board.cmake rename to boards/infineon/xmc45_relax_kit/board.cmake diff --git a/boards/infineon/xmc45_relax_kit/board.yml b/boards/infineon/xmc45_relax_kit/board.yml new file mode 100644 index 00000000000000..9622337aa30619 --- /dev/null +++ b/boards/infineon/xmc45_relax_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: xmc45_relax_kit + vendor: infineon + socs: + - name: xmc4500 diff --git a/boards/arm/xmc45_relax_kit/doc/index.rst b/boards/infineon/xmc45_relax_kit/doc/index.rst similarity index 100% rename from boards/arm/xmc45_relax_kit/doc/index.rst rename to boards/infineon/xmc45_relax_kit/doc/index.rst diff --git a/boards/arm/xmc45_relax_kit/doc/xmc45_relax_kit.jpg b/boards/infineon/xmc45_relax_kit/doc/xmc45_relax_kit.jpg similarity index 100% rename from boards/arm/xmc45_relax_kit/doc/xmc45_relax_kit.jpg rename to boards/infineon/xmc45_relax_kit/doc/xmc45_relax_kit.jpg diff --git a/boards/arm/xmc45_relax_kit/support/openocd.cfg b/boards/infineon/xmc45_relax_kit/support/openocd.cfg similarity index 100% rename from boards/arm/xmc45_relax_kit/support/openocd.cfg rename to boards/infineon/xmc45_relax_kit/support/openocd.cfg diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi similarity index 100% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit-pinctrl.dtsi diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit.dts b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts similarity index 100% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit.dts rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit.dts diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit.yaml b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml similarity index 100% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit.yaml rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml diff --git a/boards/arm/xmc45_relax_kit/xmc45_relax_kit_defconfig b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig similarity index 76% rename from boards/arm/xmc45_relax_kit/xmc45_relax_kit_defconfig rename to boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig index 97c44446dafc1f..db059d2bd55563 100644 --- a/boards/arm/xmc45_relax_kit/xmc45_relax_kit_defconfig +++ b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig @@ -3,9 +3,6 @@ # Copyright (c) 2020 Linumiz # Author: Parthiban Nallathambi -CONFIG_BOARD_XMC45_RELAX_KIT=y -CONFIG_SOC_SERIES_XMC_4XXX=y -CONFIG_SOC_XMC4500=y CONFIG_ARM_MPU=y # enable uart driver diff --git a/boards/infineon/xmc47_relax_kit/Kconfig.defconfig b/boards/infineon/xmc47_relax_kit/Kconfig.defconfig new file mode 100644 index 00000000000000..aa8b936f764c1f --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/Kconfig.defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Schlumberger + +if BOARD_XMC47_RELAX_KIT + +if NETWORKING + +config NET_L2_ETHERNET + default y +config MDIO + default y +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +endif diff --git a/boards/infineon/xmc47_relax_kit/Kconfig.xmc47_relax_kit b/boards/infineon/xmc47_relax_kit/Kconfig.xmc47_relax_kit new file mode 100644 index 00000000000000..c70d84c174669f --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/Kconfig.xmc47_relax_kit @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Schlumberger + +config BOARD_XMC47_RELAX_KIT + select SOC_XMC4700 + select SOC_PART_NUMBER_F144X2048 diff --git a/boards/arm/xmc47_relax_kit/arduino_r3_connector.dtsi b/boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/xmc47_relax_kit/arduino_r3_connector.dtsi rename to boards/infineon/xmc47_relax_kit/arduino_r3_connector.dtsi diff --git a/boards/arm/xmc47_relax_kit/board.cmake b/boards/infineon/xmc47_relax_kit/board.cmake similarity index 100% rename from boards/arm/xmc47_relax_kit/board.cmake rename to boards/infineon/xmc47_relax_kit/board.cmake diff --git a/boards/infineon/xmc47_relax_kit/board.yml b/boards/infineon/xmc47_relax_kit/board.yml new file mode 100644 index 00000000000000..e0077321e3a98e --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/board.yml @@ -0,0 +1,5 @@ +board: + name: xmc47_relax_kit + vendor: infineon + socs: + - name: xmc4700 diff --git a/boards/arm/xmc47_relax_kit/doc/index.rst b/boards/infineon/xmc47_relax_kit/doc/index.rst similarity index 100% rename from boards/arm/xmc47_relax_kit/doc/index.rst rename to boards/infineon/xmc47_relax_kit/doc/index.rst diff --git a/boards/arm/xmc47_relax_kit/doc/xmc47_relax_kit.jpg b/boards/infineon/xmc47_relax_kit/doc/xmc47_relax_kit.jpg similarity index 100% rename from boards/arm/xmc47_relax_kit/doc/xmc47_relax_kit.jpg rename to boards/infineon/xmc47_relax_kit/doc/xmc47_relax_kit.jpg diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi similarity index 100% rename from boards/arm/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi rename to boards/infineon/xmc47_relax_kit/xmc47_relax_kit-pinctrl.dtsi diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit.dts b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts similarity index 100% rename from boards/arm/xmc47_relax_kit/xmc47_relax_kit.dts rename to boards/infineon/xmc47_relax_kit/xmc47_relax_kit.dts diff --git a/boards/arm/xmc47_relax_kit/xmc47_relax_kit.yaml b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml similarity index 100% rename from boards/arm/xmc47_relax_kit/xmc47_relax_kit.yaml rename to boards/infineon/xmc47_relax_kit/xmc47_relax_kit.yaml diff --git a/boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig new file mode 100644 index 00000000000000..ce881b0d426302 --- /dev/null +++ b/boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Schlumberger + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/innblue/index.rst b/boards/innblue/index.rst new file mode 100644 index 00000000000000..c5491ac8f80702 --- /dev/null +++ b/boards/innblue/index.rst @@ -0,0 +1,10 @@ +.. _boards-innblue: + +innblue +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/innblue/innblue21/Kconfig.defconfig b/boards/innblue/innblue21/Kconfig.defconfig new file mode 100644 index 00000000000000..abf57a46a11be6 --- /dev/null +++ b/boards/innblue/innblue21/Kconfig.defconfig @@ -0,0 +1,45 @@ +# nRF9160 innblue V2.1 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_INNBLUE21 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +if BOARD_INNBLUE21_NRF9160 && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE21_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_INNBLUE21_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE21_NRF9160_NS + +config BT_HCI_VS + default y if BT + +config REGULATOR + default y if SENSOR + +endif # BOARD_INNBLUE21 diff --git a/boards/innblue/innblue21/Kconfig.innblue21 b/boards/innblue/innblue21/Kconfig.innblue21 new file mode 100644 index 00000000000000..718e3753087d75 --- /dev/null +++ b/boards/innblue/innblue21/Kconfig.innblue21 @@ -0,0 +1,7 @@ +# nRF9160 innblue V2.1 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INNBLUE21 + select SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue21/board.cmake b/boards/innblue/innblue21/board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue21/board.cmake rename to boards/innblue/innblue21/board.cmake diff --git a/boards/innblue/innblue21/board.yml b/boards/innblue/innblue21/board.yml new file mode 100644 index 00000000000000..8d62be567905ce --- /dev/null +++ b/boards/innblue/innblue21/board.yml @@ -0,0 +1,7 @@ +board: + name: innblue21 + vendor: innblue + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/nrf9160_innblue21/doc/img/nrf9160_innblue21.jpg b/boards/innblue/innblue21/doc/img/nrf9160_innblue21.jpg similarity index 100% rename from boards/arm/nrf9160_innblue21/doc/img/nrf9160_innblue21.jpg rename to boards/innblue/innblue21/doc/img/nrf9160_innblue21.jpg diff --git a/boards/innblue/innblue21/doc/index.rst b/boards/innblue/innblue21/doc/index.rst new file mode 100644 index 00000000000000..333db42bfd9255 --- /dev/null +++ b/boards/innblue/innblue21/doc/index.rst @@ -0,0 +1,144 @@ +.. _nrf9160_innblue21: + +nRF9160 INNBLUE21 +################# + +Overview +******** + +The nRF9160 innblue21 is a cellular IoT sensor development board, which +is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. + +.. figure:: img/nrf9160_innblue21.jpg + :align: center + :alt: nRF9160 innblue21 + + nRF9160 innblue21 (Credit: innblue) + +Hardware +******** + +The following parts are built into the board: + +* Accelerometer: ST LIS2DH12 +* CryptoElement: Atmel ATECC608a +* Humidity Sensor: ST HTS221 +* Qi charger: TI BQ51013 +* Battery fuel gauge: TI BQ27421 + +Supported Features +================== + +The innblue21 board configuration supports the following +hardware (as of nRF9160) features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED1 ( red ) = P0.7 +* LED2 (green) = P0.6 +* LED3 ( blue) = P0.5 +* LED4 ( red ) = P0.4 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.31 + +Security components +=================== + +- Implementation Defined Attribution Unit. The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +innblue21 supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=innblue21`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=innblue21/nrf9160/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=innblue21``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9160 innblue21 +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: innblue21 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_common-pinctrl.dtsi b/boards/innblue/innblue21/innblue21_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue21/nrf9160_innblue21_common-pinctrl.dtsi rename to boards/innblue/innblue21/innblue21_common-pinctrl.dtsi diff --git a/boards/innblue/innblue21/innblue21_common.dtsi b/boards/innblue/innblue21/innblue21_common.dtsi new file mode 100644 index 00000000000000..53160a680c66ec --- /dev/null +++ b/boards/innblue/innblue21/innblue21_common.dtsi @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "innblue21_common-pinctrl.dtsi" +#include + +/ { + model = "innblue v21 Dev Kit"; + compatible = "innblue,innblue21"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_1 { + gpios = <&gpio0 7 0>; + label = "RGB red channel"; + }; + green_led: led_2 { + gpios = <&gpio0 6 0>; + label = "RGB green channel"; + }; + blue_led: led_3 { + gpios = <&gpio0 5 0>; + label = "RGB blue channel"; + }; + + mode_led: led_4 { + gpios = <&gpio0 4 0>; + label = "mode red channel"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 31 GPIO_PULL_UP>; + label = "Button 0"; + zephyr,code = ; + }; + }; + + en_3v3_sensor: enable-3v3-sensor { + compatible = "regulator-fixed"; + regulator-name = "en_3v3_sensor"; + enable-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10000>; + regulator-boot-on; + }; + + en_5v0_boost: enable-5v0-boost { + compatible = "regulator-fixed"; + regulator-name = "en_5v0_boost"; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10000>; + regulator-boot-on; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + led3 = &mode_led; + sw0 = &button0; + rgb-pwm = &pwm0; + mode-pwm = &pwm1; + watchdog0 = &wdt0; + accel0 = &lis2dh12_accel; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-1 = <&uart2_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c2 { + compatible = "nordic,nrf-twim"; + status = "okay"; + + clock-frequency = ; + + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + pinctrl-names = "default", "sleep"; + lis2dh12_accel: lis2dh12-accel@19 { + compatible = "st,lis2dh"; + reg = <0x19>; + irq-gpios = <&gpio0 0 0>, <&gpio0 1 0>; + }; + + hts221@5f { + compatible = "st,hts221"; + reg = <0x5f>; + drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + lps22hb-press@5c { + compatible = "st,lps22hb-press"; + reg = <0x5c>; + }; + + ccs811: ccs811@5a { + compatible = "ams,ccs811"; + reg = <0x5a>; + }; + + bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-1 = <&pwm1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x10000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + }; + slot0_ns_partition: partition@50000 { + label = "image-0-nonsecure"; + }; + slot1_partition: partition@80000 { + label = "image-1"; + }; + slot1_ns_partition: partition@c0000 { + label = "image-1-nonsecure"; + }; + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +/ { + /* SRAM allocated and used by the BSD library */ + sram0_bsd: memory@20010000 { + compatible = "mmio-sram"; + }; + + /* SRAM allocated to the Non-Secure image */ + sram0_ns: memory@20020000 { + compatible = "mmio-sram"; + }; +}; + +/* Include partition configuration file */ +#include "innblue21_partition_conf.dtsi" diff --git a/boards/innblue/innblue21/innblue21_nrf9160.dts b/boards/innblue/innblue21/innblue21_nrf9160.dts new file mode 100644 index 00000000000000..f13c5c9036ad2d --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue21_common.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/innblue/innblue21/innblue21_nrf9160.yaml b/boards/innblue/innblue21/innblue21_nrf9160.yaml new file mode 100644 index 00000000000000..5722ebcd8c9e07 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160.yaml @@ -0,0 +1,14 @@ +identifier: innblue21/nrf9160 +name: nRF9160-INNBLUE21 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue21/innblue21_nrf9160_defconfig b/boards/innblue/innblue21/innblue21_nrf9160_defconfig new file mode 100644 index 00000000000000..75e6bba71319a1 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.dts b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts new file mode 100644 index 00000000000000..2ca97a7b16254a --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue21_common.dtsi" + +/ { + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0_ns; + zephyr,code-partition = &slot0_ns_partition; + }; +}; diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml b/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml new file mode 100644 index 00000000000000..17faee49190ecf --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml @@ -0,0 +1,14 @@ +identifier: innblue21/nrf9160/ns +name: nRF9160-INNBLUE21-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns_defconfig b/boards/innblue/innblue21/innblue21_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..e27861efc3c757 --- /dev/null +++ b/boards/innblue/innblue21/innblue21_nrf9160_ns_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue21/nrf9160_innblue21_partition_conf.dtsi b/boards/innblue/innblue21/innblue21_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue21/nrf9160_innblue21_partition_conf.dtsi rename to boards/innblue/innblue21/innblue21_partition_conf.dtsi diff --git a/boards/arm/nrf9131ek_nrf9131/pre_dt_board.cmake b/boards/innblue/innblue21/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/pre_dt_board.cmake rename to boards/innblue/innblue21/pre_dt_board.cmake diff --git a/boards/innblue/innblue22/Kconfig.defconfig b/boards/innblue/innblue22/Kconfig.defconfig new file mode 100644 index 00000000000000..540a784ec975e8 --- /dev/null +++ b/boards/innblue/innblue22/Kconfig.defconfig @@ -0,0 +1,45 @@ +# nRF9160 innblue V2.2 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_INNBLUE22 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +if BOARD_INNBLUE22_NRF9160 && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE22_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_INNBLUE22_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_INNBLUE22_NRF9160_NS + +config BT_HCI_VS + default y if BT + +config REGULATOR + default y if SENSOR + +endif # BOARD_INNBLUE22 diff --git a/boards/innblue/innblue22/Kconfig.innblue22 b/boards/innblue/innblue22/Kconfig.innblue22 new file mode 100644 index 00000000000000..53c5d7dd86109f --- /dev/null +++ b/boards/innblue/innblue22/Kconfig.innblue22 @@ -0,0 +1,7 @@ +# nRF9160 innblue V2.2 board configuration + +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INNBLUE22 + select SOC_NRF9160_SICA diff --git a/boards/arm/nrf9160_innblue22/board.cmake b/boards/innblue/innblue22/board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue22/board.cmake rename to boards/innblue/innblue22/board.cmake diff --git a/boards/innblue/innblue22/board.yml b/boards/innblue/innblue22/board.yml new file mode 100644 index 00000000000000..eeb4f946ffbe86 --- /dev/null +++ b/boards/innblue/innblue22/board.yml @@ -0,0 +1,7 @@ +board: + name: innblue22 + vendor: innblue + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/nrf9160_innblue22/doc/img/nrf9160_innblue22.jpg b/boards/innblue/innblue22/doc/img/nrf9160_innblue22.jpg similarity index 100% rename from boards/arm/nrf9160_innblue22/doc/img/nrf9160_innblue22.jpg rename to boards/innblue/innblue22/doc/img/nrf9160_innblue22.jpg diff --git a/boards/innblue/innblue22/doc/index.rst b/boards/innblue/innblue22/doc/index.rst new file mode 100644 index 00000000000000..862c42cdd22c44 --- /dev/null +++ b/boards/innblue/innblue22/doc/index.rst @@ -0,0 +1,144 @@ +.. _nrf9160_innblue22: + +nRF9160 INNBLUE22 +################# + +Overview +******** + +The nRF9160 innblue22 is a cellular IoT sensor development board, which +is based on the nRF9160 SiP, and features NB-IoT and LTE-M connectivity. + +.. figure:: img/nrf9160_innblue22.jpg + :align: center + :alt: nRF9160 innblue22 + + nRF9160 innblue22 (Credit: innblue) + +Hardware +******** + +The following parts are built into the board: + +* Accelerometer: ST LIS2DH12 +* CryptoElement: Atmel ATECC608a +* Humidity Sensor: ST HTS221 +* Qi charger: TI BQ51013 +* Battery fuel gauge: TI BQ27421 + +Supported Features +================== + +The innblue22 board configuration supports the following +hardware (as of nRF9160) features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED1 ( red ) = P0.7 +* LED2 (green) = P0.6 +* LED3 ( blue) = P0.5 +* LED4 ( red ) = P0.4 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.31 + +Security components +=================== + +- Implementation Defined Attribution Unit. The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +innblue22 supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications +============================================== + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=innblue22`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=innblue22/nrf9160/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=innblue22``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9160 innblue22 +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: innblue22 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_common-pinctrl.dtsi b/boards/innblue/innblue22/innblue22_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue22/nrf9160_innblue22_common-pinctrl.dtsi rename to boards/innblue/innblue22/innblue22_common-pinctrl.dtsi diff --git a/boards/innblue/innblue22/innblue22_common.dtsi b/boards/innblue/innblue22/innblue22_common.dtsi new file mode 100644 index 00000000000000..de57fa1ced454c --- /dev/null +++ b/boards/innblue/innblue22/innblue22_common.dtsi @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "innblue22_common-pinctrl.dtsi" +#include + +/ { + model = "innblue v22 Dev Kit"; + compatible = "innblue,innblue22"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_1 { + gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + label = "RGB red channel"; + }; + green_led: led_2 { + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + label = "RGB green channel"; + }; + blue_led: led_3 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "RGB blue channel"; + }; + + mode_led: led_4 { + gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; + label = "mode red channel"; + }; + }; + + buttons { + compatible = "gpio-keys"; + + button0: button_0 { + gpios = <&gpio0 31 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Button 0"; + zephyr,code = ; + }; + }; + + en_5v0_boost: enable-5v0-boost { + compatible = "regulator-fixed"; + regulator-name = "en_5v0_boost"; + enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + startup-delay-us = <10000>; + regulator-boot-on; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &red_led; + led1 = &green_led; + led2 = &blue_led; + led3 = &mode_led; + sw0 = &button0; + rgb-pwm = &pwm0; + mode-pwm = &pwm1; + watchdog0 = &wdt0; + accel0 = &lis2dh12_accel; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-1 = <&uart2_sleep>; + pinctrl-names = "default", "sleep"; +}; + + +&i2c2 { + compatible = "nordic,nrf-twim"; + status = "okay"; + + clock-frequency = ; + + pinctrl-0 = <&i2c2_default>; + pinctrl-1 = <&i2c2_sleep>; + pinctrl-names = "default", "sleep"; + bq27421@55 { + compatible = "ti,bq274xx"; + reg = <0x55>; + design-voltage = <3700>; + design-capacity = <1800>; + taper-current = <45>; + terminate-voltage = <3000>; + }; + + lis2dh12_accel: lis2dh12-accel@19 { + compatible = "st,lis2dh"; + reg = <0x19>; + irq-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>, <&gpio0 1 GPIO_ACTIVE_HIGH>; + }; + + hts221@5f { + compatible = "st,hts221"; + reg = <0x5f>; + drdy-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; + }; + + lps22hb-press@5c { + compatible = "st,lps22hb-press"; + reg = <0x5c>; + }; + + ccs811: ccs811@5a { + compatible = "ams,ccs811"; + reg = <0x5a>; + }; + + bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + }; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm1 { + status = "okay"; + pinctrl-0 = <&pwm1_default>; + pinctrl-1 = <&pwm1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x10000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + }; + slot0_ns_partition: partition@50000 { + label = "image-0-nonsecure"; + }; + slot1_partition: partition@80000 { + label = "image-1"; + }; + slot1_ns_partition: partition@c0000 { + label = "image-1-nonsecure"; + }; + /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +/ { + /* SRAM allocated and used by the BSD library */ + sram0_bsd: memory@20010000 { + compatible = "mmio-sram"; + }; + + /* SRAM allocated to the Non-Secure image */ + sram0_ns: memory@20020000 { + compatible = "mmio-sram"; + }; +}; + +/* Include partition configuration file */ +#include "innblue22_partition_conf.dtsi" diff --git a/boards/innblue/innblue22/innblue22_nrf9160.dts b/boards/innblue/innblue22/innblue22_nrf9160.dts new file mode 100644 index 00000000000000..c9c24c1090c35b --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue22_common.dtsi" + +/ { + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/innblue/innblue22/innblue22_nrf9160.yaml b/boards/innblue/innblue22/innblue22_nrf9160.yaml new file mode 100644 index 00000000000000..9bad5763319f6f --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160.yaml @@ -0,0 +1,14 @@ +identifier: innblue22/nrf9160 +name: nRF9160-INNBLUE22 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue22/innblue22_nrf9160_defconfig b/boards/innblue/innblue22/innblue22_nrf9160_defconfig new file mode 100644 index 00000000000000..75e6bba71319a1 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns.dts b/boards/innblue/innblue22/innblue22_nrf9160_ns.dts new file mode 100644 index 00000000000000..93fa33ba334c6a --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_ns.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2020 InnBlue + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "innblue22_common.dtsi" + +/ { + chosen { + zephyr,flash = &flash0; + zephyr,sram = &sram0_ns; + zephyr,code-partition = &slot0_ns_partition; + }; +}; diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml b/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml new file mode 100644 index 00000000000000..4542d90bad0383 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml @@ -0,0 +1,14 @@ +identifier: innblue22/nrf9160/ns +name: nRF9160-INNBLUE22-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - i2c + - pwm + - watchdog diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns_defconfig b/boards/innblue/innblue22/innblue22_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..e27861efc3c757 --- /dev/null +++ b/boards/innblue/innblue22/innblue22_nrf9160_ns_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2020 InnBlue +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160_innblue22/nrf9160_innblue22_partition_conf.dtsi b/boards/innblue/innblue22/innblue22_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9160_innblue22/nrf9160_innblue22_partition_conf.dtsi rename to boards/innblue/innblue22/innblue22_partition_conf.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/pre_dt_board.cmake b/boards/innblue/innblue22/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/pre_dt_board.cmake rename to boards/innblue/innblue22/pre_dt_board.cmake diff --git a/boards/intel/adl/CMakeLists.txt b/boards/intel/adl/CMakeLists.txt new file mode 100644 index 00000000000000..36ddcdf9d1392b --- /dev/null +++ b/boards/intel/adl/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/intel/adl/Kconfig.defconfig b/boards/intel/adl/Kconfig.defconfig new file mode 100644 index 00000000000000..518f0c01ee2dc0 --- /dev/null +++ b/boards/intel/adl/Kconfig.defconfig @@ -0,0 +1,53 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +config ACPI + default y + +if ACPI +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 +config MAIN_STACK_SIZE + default 320000 + +if SHELL +config SHELL_STACK_SIZE + default 320000 +endif # SHELL +endif # ACPI + +if DMA +config DMA_64BIT + default y +config DMA_DW_HW_LLI + default n +config DMA_DW_CHANNEL_COUNT + default 2 +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y + +config HAS_COVERAGE_SUPPORT + default y diff --git a/boards/intel/adl/Kconfig.intel_adl_crb b/boards/intel/adl/Kconfig.intel_adl_crb new file mode 100644 index 00000000000000..81b9bd972b5d39 --- /dev/null +++ b/boards/intel/adl/Kconfig.intel_adl_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ADL_CRB + select SOC_ALDER_LAKE diff --git a/boards/intel/adl/Kconfig.intel_adl_rvp b/boards/intel/adl/Kconfig.intel_adl_rvp new file mode 100644 index 00000000000000..01eca2f55f407f --- /dev/null +++ b/boards/intel/adl/Kconfig.intel_adl_rvp @@ -0,0 +1,5 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ADL_RVP + select SOC_ALDER_LAKE diff --git a/boards/x86/intel_adl/board.cmake b/boards/intel/adl/board.cmake similarity index 100% rename from boards/x86/intel_adl/board.cmake rename to boards/intel/adl/board.cmake diff --git a/boards/intel/adl/board.yml b/boards/intel/adl/board.yml new file mode 100644 index 00000000000000..fe51b63f813868 --- /dev/null +++ b/boards/intel/adl/board.yml @@ -0,0 +1,9 @@ +boards: + - name: intel_adl_crb + vendor: intel + socs: + - name: alder_lake + - name: intel_adl_rvp + vendor: intel + socs: + - name: alder_lake diff --git a/boards/intel/adl/doc/index.rst b/boards/intel/adl/doc/index.rst new file mode 100644 index 00000000000000..ac3a4c03076e87 --- /dev/null +++ b/boards/intel/adl/doc/index.rst @@ -0,0 +1,65 @@ +.. _intel_adl_n: + +Alder Lake N +############ + +Overview +******** +Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer +technology process. + +Currently supported is N-processor line, Single Chip Platform that consists of +the Processor Die and Alder Lake N Platform Controller Hub (ADL-N PCH) Die on +the same package as Multi-Chip Package (MCP). + +Proposed branding for Adler Lake N is Intel Processor (N100,N200) and +Intel Core i3 (N300, N305). + +Alder Lake N Customer Reference Board (ADL-N CRB) and Alder Lake Reference +Validation Platform (ADL-N RVP) are example implementations of compact single +board computer with high performance for IoT edge devices. + +This board configuration enables kernel support for the Alder Lake N boards. + +Hardware +******** + +General information about the board can be found at the `INTEL_ADL`_ website. + +Connections and IOs +=================== + +Refer to the `INTEL_ADL`_ website for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image for an Alder Lake N CRB board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application for Alder Lake N CRB: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_adl_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the Alder Lake N CRB Board using UEFI +============================================= + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core-i3-n-series-datasheet-volume-1-of-2/ diff --git a/boards/x86/intel_adl/intel_adl.dts b/boards/intel/adl/intel_adl.dts similarity index 100% rename from boards/x86/intel_adl/intel_adl.dts rename to boards/intel/adl/intel_adl.dts diff --git a/boards/x86/intel_adl/intel_adl_crb.dts b/boards/intel/adl/intel_adl_crb.dts similarity index 100% rename from boards/x86/intel_adl/intel_adl_crb.dts rename to boards/intel/adl/intel_adl_crb.dts diff --git a/boards/x86/intel_adl/intel_adl_crb.yaml b/boards/intel/adl/intel_adl_crb.yaml similarity index 100% rename from boards/x86/intel_adl/intel_adl_crb.yaml rename to boards/intel/adl/intel_adl_crb.yaml diff --git a/boards/x86/intel_adl/intel_adl_crb_defconfig b/boards/intel/adl/intel_adl_crb_defconfig similarity index 81% rename from boards/x86/intel_adl/intel_adl_crb_defconfig rename to boards/intel/adl/intel_adl_crb_defconfig index 5287bfcacc08a3..fb9be2a4994a30 100644 --- a/boards/x86/intel_adl/intel_adl_crb_defconfig +++ b/boards/intel/adl/intel_adl_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ALDER_LAKE=y -CONFIG_BOARD_INTEL_ADL_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/intel_adl/intel_adl_rvp.dts b/boards/intel/adl/intel_adl_rvp.dts similarity index 100% rename from boards/x86/intel_adl/intel_adl_rvp.dts rename to boards/intel/adl/intel_adl_rvp.dts diff --git a/boards/x86/intel_adl/intel_adl_rvp.yaml b/boards/intel/adl/intel_adl_rvp.yaml similarity index 100% rename from boards/x86/intel_adl/intel_adl_rvp.yaml rename to boards/intel/adl/intel_adl_rvp.yaml diff --git a/boards/x86/intel_adl/intel_adl_rvp_defconfig b/boards/intel/adl/intel_adl_rvp_defconfig similarity index 81% rename from boards/x86/intel_adl/intel_adl_rvp_defconfig rename to boards/intel/adl/intel_adl_rvp_defconfig index 0f6ed718268ef3..fb9be2a4994a30 100644 --- a/boards/x86/intel_adl/intel_adl_rvp_defconfig +++ b/boards/intel/adl/intel_adl_rvp_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ALDER_LAKE=y -CONFIG_BOARD_INTEL_ADL_RVP=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/intel/adsp/Kconfig.defconfig b/boards/intel/adsp/Kconfig.defconfig new file mode 100644 index 00000000000000..eafedb0c550e66 --- /dev/null +++ b/boards/intel/adsp/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if DAI_INTEL_SSP + +config DAI_SSP_HAS_POWER_CONTROL + def_bool y + +endif diff --git a/boards/intel/adsp/Kconfig.intel_adsp b/boards/intel/adsp/Kconfig.intel_adsp new file mode 100644 index 00000000000000..2e4c98447203b2 --- /dev/null +++ b/boards/intel/adsp/Kconfig.intel_adsp @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ADSP + select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25 + select SOC_INTEL_CAVS_V25 if BOARD_INTEL_ADSP_CAVS25_TGPH + select SOC_INTEL_ACE15_MTPM if BOARD_INTEL_ADSP_ACE15_MTPM + select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL diff --git a/boards/intel/adsp/board.cmake b/boards/intel/adsp/board.cmake new file mode 100644 index 00000000000000..bcdfc3286467c8 --- /dev/null +++ b/boards/intel/adsp/board.cmake @@ -0,0 +1,42 @@ +# Copyright (c) 2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_INTEL_ADSP_CAVS25 OR CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) + + if($ENV{CAVS_OLD_FLASHER}) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + endif() + + board_set_flasher_ifnset(intel_adsp) + + set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in cavs25/board.cmake") + + if(CONFIG_BOARD_INTEL_ADSP_CAVS25) + board_set_rimage_target(tgl) + endif() + + if(CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) + board_set_rimage_target(tgl-h) + endif() + + board_finalize_runner_args(intel_adsp) + +elseif(CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM) + + board_set_rimage_target(mtl) + + set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace15_mtpm/board.cmake") + + board_finalize_runner_args(intel_adsp) + +elseif(CONFIG_BOARD_INTEL_ADSP_ACE20_LNL) + + set(SUPPORTED_EMU_PLATFORMS acesim) + + board_set_rimage_target(lnl) + + set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake") + +endif() diff --git a/boards/intel/adsp/board.yml b/boards/intel/adsp/board.yml new file mode 100644 index 00000000000000..9295ae0c3eb2fd --- /dev/null +++ b/boards/intel/adsp/board.yml @@ -0,0 +1,9 @@ +boards: + - name: intel_adsp + vendor: intel + socs: + - name: cavs25 + variants: + - name: 'tgph' + - name: ace15_mtpm + - name: ace20_lnl diff --git a/boards/xtensa/intel_adsp_cavs25/doc/chromebooks_adsp.rst b/boards/intel/adsp/doc/chromebooks_adsp.rst similarity index 98% rename from boards/xtensa/intel_adsp_cavs25/doc/chromebooks_adsp.rst rename to boards/intel/adsp/doc/chromebooks_adsp.rst index 867df7b838979d..a89d2b75881199 100644 --- a/boards/xtensa/intel_adsp_cavs25/doc/chromebooks_adsp.rst +++ b/boards/intel/adsp/doc/chromebooks_adsp.rst @@ -1,5 +1,3 @@ -:orphan: - .. _zephyr-audio-dsp-development-on-chromebooks: Zephyr Audio DSP Development on Chromebooks @@ -366,7 +364,7 @@ the Crouton environment installed above. Copy them: .. code-block:: console - dev$ scp soc/xtensa/intel_adsp/tools/cavstool.py user@crouton: + dev$ scp soc/intel/intel_adsp/tools/cavstool.py user@crouton: Then start the service in the Crouton environment: @@ -386,7 +384,7 @@ a "zephyr.ri" file to be copied to the device. .. code-block:: console - dev$ west build -b intel_adsp_cavs25 samples/hello_world + dev$ west build -b intel_adsp/cavs25 samples/hello_world dev$ west sign --tool-data=~/rimage/config -t ~/rimage/rimage -- \ -k $ZEPHYR_BASE/../modules/audio/sof/keys/otc_private_key_3k.pem @@ -401,7 +399,7 @@ the logging script. .. code-block:: console dev$ west flash --remote-host crouton - Hello World! intel_adsp_cavs25 + Hello World! intel_adsp Misc References *************** diff --git a/boards/intel/adsp/doc/index.rst b/boards/intel/adsp/doc/index.rst new file mode 100644 index 00000000000000..3145b7637cd195 --- /dev/null +++ b/boards/intel/adsp/doc/index.rst @@ -0,0 +1,11 @@ +.. _boards-intel-adsp: + +Intel ADSP +########## + +.. toctree:: + + intel_adsp_generic + chromebooks_adsp + intel_adsp_cavs25 + intel_adsp_ace15_mtpm diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/doc/index.rst b/boards/intel/adsp/doc/intel_adsp_ace15_mtpm.rst similarity index 100% rename from boards/xtensa/intel_adsp_ace15_mtpm/doc/index.rst rename to boards/intel/adsp/doc/intel_adsp_ace15_mtpm.rst diff --git a/boards/xtensa/intel_adsp_cavs25/doc/index.rst b/boards/intel/adsp/doc/intel_adsp_cavs25.rst similarity index 100% rename from boards/xtensa/intel_adsp_cavs25/doc/index.rst rename to boards/intel/adsp/doc/intel_adsp_cavs25.rst diff --git a/boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst b/boards/intel/adsp/doc/intel_adsp_generic.rst similarity index 90% rename from boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst rename to boards/intel/adsp/doc/intel_adsp_generic.rst index 6b0a4526fe4009..e0a8edf1ba263b 100644 --- a/boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst +++ b/boards/intel/adsp/doc/intel_adsp_generic.rst @@ -1,5 +1,3 @@ -:orphan: - .. _intel_adsp_generic: Intel ADSP cAVS and ACE @@ -115,7 +113,7 @@ Build as usual. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: intel_adsp_cavs25 + :board: intel_adsp/cavs25 :goals: build Signing @@ -141,7 +139,7 @@ undocumented rimage precedence rules it's best to use only one way at a time. - For board-specific needs you can define WEST_SIGN_OPTS in ``boards/my/board/board.cmake``, see example in - ``soc/xtensa/intel_adsp/common/CMakeLists.txt`` + ``soc/intel/adsp/common/CMakeLists.txt`` Starting with Zephyr 3.6.0, ``west flash`` does not invoke ``west sign`` anymore and you cannot pass rimage parameters to ``west flash`` anymore. To @@ -162,16 +160,16 @@ this point onward, we will refer to the board as the "remote host" and your development machine as the "local host". Copy the below scripts to the cAVS board. -:zephyr_file:`soc/xtensa/intel_adsp/tools/remote-fw-service.py` will receive +:zephyr_file:`soc/intel/intel_adsp/tools/remote-fw-service.py` will receive the binary sent over the network by West and invoke -:zephyr_file:`soc/xtensa/intel_adsp/tools/cavstool.py` (referred to as the +:zephyr_file:`soc/intel/intel_adsp/tools/cavstool.py` (referred to as the "cAVS tool"), which performs the flash and captures the log. Start :file:`remote-fw-service.py`. .. code-block:: console - scp -r $ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool.py username@remotehostname - scp -r $ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/remote-fw-service.py username@remotehostname + scp -r $ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool.py username@remotehostname + scp -r $ZEPHYR_BASE/soc/intel/intel_adsp/tools/remote-fw-service.py username@remotehostname ssh username@remotehostname sudo ./remote-fw-service.py @@ -179,7 +177,7 @@ the binary sent over the network by West and invoke communicate. It forwards logs collected by :file:`cavstool.py` on port 9999 (referred to as its "log port") and services requests on port 10000 (its "requests port"). When you run West or Twister on your local host, -it sends requests using the :zephyr_file:`soc/xtensa/intel_adsp/tools/cavstool_client.py` +it sends requests using the :zephyr_file:`soc/intel/intel_adsp/tools/cavstool_client.py` script (referred to as "cAVS tool client"). It also uses ports 9999 and 10000 on your local host, so be sure those ports are free. @@ -193,7 +191,7 @@ Running tests with Twister is slightly more complicated. .. code-block:: console - twister -p intel_adsp_cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool_client.py,-s,remotehostname,-l" --west-flash="--remote-host=remotehostname" -T samples/hello_world + twister -p intel_adsp/cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool_client.py,-s,remotehostname,-l" --west-flash="--remote-host=remotehostname" -T samples/hello_world If your network is set up such that the TCP connection from :file:`cavstool_client.py` to :file:`remote-fw-service.py` is forwarded through @@ -204,14 +202,14 @@ the port numbers to the intermediate host name. .. code-block:: console west flash --remote-host intermediatehost:reqport --pty remotehostname:logport - twister -p intel_adsp_cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" --west-flash="--remote-host=remotehostname:reqport" -T samples/hello_world + twister -p intel_adsp/cavs25 --device-testing --device-serial-pty="$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" --west-flash="--remote-host=remotehostname:reqport" -T samples/hello_world You can also save this information to a hardware map file and pass that to Twister. .. code-block:: console - twister -p intel_adsp_cavs25 --hardware-map cavs.map --device-testing -T samples/hello_world + twister -p intel_adsp/cavs25 --hardware-map cavs.map --device-testing -T samples/hello_world Here's a sample ``cavs.map``: @@ -219,10 +217,10 @@ Here's a sample ``cavs.map``: - connected: true id: None - platform: intel_adsp_cavs25 + platform: intel_adsp/cavs25 product: None runner: intel_adsp - serial_pty: "/home/zephyrus/zephyrproject/zephyr/soc/xtensa/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" + serial_pty: "/home/zephyrus/zephyrproject/zephyr/soc/intel/intel_adsp/tools/cavstool_client.py,-s,remotehostname:logport,-l" runner_params: - --remote-host=remotehostname:reqport @@ -247,7 +245,7 @@ You should see the following at the end of the log if you are successful: .. code-block:: console ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! intel_adsp_cavs25 + Hello World! intel_adsp Flashing to ACE-based ADSP -------------------------- diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.dts b/boards/intel/adsp/intel_adsp_ace15_mtpm.dts similarity index 100% rename from boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.dts rename to boards/intel/adsp/intel_adsp_ace15_mtpm.dts diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.yaml b/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml similarity index 84% rename from boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.yaml rename to boards/intel/adsp/intel_adsp_ace15_mtpm.yaml index 9493e4c08da8b5..3449cda35f7bfd 100644 --- a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm.yaml +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_ace15_mtpm +identifier: intel_adsp/ace15_mtpm name: ACE 1.5 MTL M Audio DSP type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig new file mode 100644 index 00000000000000..2237dfb963a20e --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_MM_DRV=y +CONFIG_CRYPTO=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts b/boards/intel/adsp/intel_adsp_ace20_lnl.dts similarity index 100% rename from boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts rename to boards/intel/adsp/intel_adsp_ace20_lnl.dts diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml b/boards/intel/adsp/intel_adsp_ace20_lnl.yaml similarity index 85% rename from boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml rename to boards/intel/adsp/intel_adsp_ace20_lnl.yaml index 693f3ad2ce6319..47a025636544e1 100644 --- a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml +++ b/boards/intel/adsp/intel_adsp_ace20_lnl.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_ace20_lnl +identifier: intel_adsp/ace20_lnl name: ACE 2.0 LNL Audio DSP type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig new file mode 100644 index 00000000000000..3d897eb967321c --- /dev/null +++ b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n + +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_MM_DRV=y +CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y + +CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts b/boards/intel/adsp/intel_adsp_cavs25.dts similarity index 100% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.dts rename to boards/intel/adsp/intel_adsp_cavs25.dts diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml b/boards/intel/adsp/intel_adsp_cavs25.yaml similarity index 87% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml rename to boards/intel/adsp/intel_adsp_cavs25.yaml index 8d175cbc621643..79982b426e7dd5 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25.yaml +++ b/boards/intel/adsp/intel_adsp_cavs25.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_cavs25 +identifier: intel_adsp/cavs25 name: cAVS 2.5 Audio DSP (converged Audio Voice and Speech) type: mcu arch: xtensa diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.dts b/boards/intel/adsp/intel_adsp_cavs25_cavs25_tgph.dts similarity index 100% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.dts rename to boards/intel/adsp/intel_adsp_cavs25_cavs25_tgph.dts diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig b/boards/intel/adsp/intel_adsp_cavs25_defconfig similarity index 76% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig rename to boards/intel/adsp/intel_adsp_cavs25_defconfig index 18a58706176747..24443bce131fbd 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_defconfig +++ b/boards/intel/adsp/intel_adsp_cavs25_defconfig @@ -1,11 +1,9 @@ +# Copyright (c) 2020-2024 Intel Corporation +# # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y -CONFIG_SOC_INTEL_CAVS_V25=y -CONFIG_BOARD_INTEL_ADSP_CAVS25=y - CONFIG_GEN_ISR_TABLES=y CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.yaml b/boards/intel/adsp/intel_adsp_cavs25_tgph.yaml similarity index 86% rename from boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.yaml rename to boards/intel/adsp/intel_adsp_cavs25_tgph.yaml index f11256de9bf2ed..db3d32fad8fac0 100644 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph.yaml +++ b/boards/intel/adsp/intel_adsp_cavs25_tgph.yaml @@ -1,4 +1,4 @@ -identifier: intel_adsp_cavs25_tgph +identifier: intel_adsp/cavs25/tgph name: cAVS 2.5 Audio DSP for Tiger Lake H PCH (Converged Audio Voice and Speech) type: mcu arch: xtensa diff --git a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig new file mode 100644 index 00000000000000..a0b72230091152 --- /dev/null +++ b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_DAI_SSP_HAS_POWER_CONTROL=y + +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_CORE_COUNT=2 diff --git a/boards/intel/adsp/pre_dt_board.cmake b/boards/intel/adsp/pre_dt_board.cmake new file mode 100644 index 00000000000000..9a917df707b054 --- /dev/null +++ b/boards/intel/adsp/pre_dt_board.cmake @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if(NOT CONFIG_BOARD_INTEL_ADSP_ACE20_LNL) + +# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: +# - dmic0: dmic0@10000 & dmic1: dmic1@10000 +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") + +endif() diff --git a/boards/x86/common/efi_boot.rst b/boards/intel/common/efi_boot.rst similarity index 100% rename from boards/x86/common/efi_boot.rst rename to boards/intel/common/efi_boot.rst diff --git a/boards/x86/common/net_boot.rst b/boards/intel/common/net_boot.rst similarity index 100% rename from boards/x86/common/net_boot.rst rename to boards/intel/common/net_boot.rst diff --git a/boards/x86/common/scripts/build_grub.sh b/boards/intel/common/scripts/build_grub.sh similarity index 100% rename from boards/x86/common/scripts/build_grub.sh rename to boards/intel/common/scripts/build_grub.sh diff --git a/boards/intel/ehl/CMakeLists.txt b/boards/intel/ehl/CMakeLists.txt new file mode 100644 index 00000000000000..36ddcdf9d1392b --- /dev/null +++ b/boards/intel/ehl/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/intel/ehl/Kconfig.defconfig b/boards/intel/ehl/Kconfig.defconfig new file mode 100644 index 00000000000000..9e7dcf48a0458f --- /dev/null +++ b/boards/intel/ehl/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +if BOARD_INTEL_EHL_CRB_ELKHART_LAKE_SBL +config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN + depends on SHELL_BACKEND_SERIAL + default n +endif + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 2097152 + depends on ACPI + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +if BOARD_INTEL_EHL_CRB_ELKHART_LAKE + config HAS_COVERAGE_SUPPORT + default y +endif diff --git a/boards/intel/ehl/Kconfig.intel_ehl_crb b/boards/intel/ehl/Kconfig.intel_ehl_crb new file mode 100644 index 00000000000000..1d99891fe5872e --- /dev/null +++ b/boards/intel/ehl/Kconfig.intel_ehl_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_EHL_CRB + select SOC_ELKHART_LAKE diff --git a/boards/x86/intel_ehl/board.cmake b/boards/intel/ehl/board.cmake similarity index 100% rename from boards/x86/intel_ehl/board.cmake rename to boards/intel/ehl/board.cmake diff --git a/boards/intel/ehl/board.yml b/boards/intel/ehl/board.yml new file mode 100644 index 00000000000000..5f8d3cafa1b899 --- /dev/null +++ b/boards/intel/ehl/board.yml @@ -0,0 +1,7 @@ +board: + name: intel_ehl_crb + vendor: intel + socs: + - name: elkhart_lake + variants: + - name: 'sbl' diff --git a/boards/intel/ehl/doc/index.rst b/boards/intel/ehl/doc/index.rst new file mode 100644 index 00000000000000..16bf6c2bd22643 --- /dev/null +++ b/boards/intel/ehl/doc/index.rst @@ -0,0 +1,89 @@ +.. _intel_ehl_crb: + +Elkhart Lake CRB +################ + +Overview +******** +Elkhart Lake Reference Board (EHL CRB) is an example implementation of a +compact single board computer with high performance for IoT edge devices. + +This board configuration enables kernel support for the `EHL`_ board. + +.. note:: + This board configuration works on the variant of `EHL`_ + boards containing Intel |reg| Atom |trade| SoC. + +Hardware +******** + +General information about the board can be found at the `EHL`_ website. + +.. include:: ../../../../soc/intel/elkhart_lake/doc/supported_features.txt + + +Connections and IOs +=================== + +Refer to the `EHL`_ website for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image on a EHL CRB board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application on Elkhart Lake CRB: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_ehl_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the Elkhart Lake CRB Board using UEFI +============================================= + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +Booting the Elkhart Lake CRB Board over network +=============================================== + +.. include:: ../../../intel/common/net_boot.rst + :start-after: start_include_here + +.. note:: + To enable PXE boot for Elkhart Lake CRB board do the following: + + #. Enable boot from PXE. Go to EFI shell and make sure that the first boot + option is ``UEFI PXEv4``. + + .. code-block:: console + + Shell> bcfg boot dump + Option: 00. Variable: Boot0007 + Desc - UEFI PXEv4 (MAC:6805CABC1997) + DevPath - PciRoot(0x0)/Pci(0x1C,0x0)/Pci(0x0,0x0)/MAC(6805CABC1997,0x0)/IPv4(0.0.0.0) + Optional- Y + ... + + #. If UEFI PXEv4 is not the first boot option use ``bcfg boot mv`` command to + change boot order + + .. code-block:: console + + Shell> bcfg boot mv 7 0 + +.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/x86/intel_ehl/intel_ehl_crb.dts b/boards/intel/ehl/intel_ehl_crb.dts similarity index 100% rename from boards/x86/intel_ehl/intel_ehl_crb.dts rename to boards/intel/ehl/intel_ehl_crb.dts diff --git a/boards/x86/intel_ehl/intel_ehl_crb.yaml b/boards/intel/ehl/intel_ehl_crb.yaml similarity index 100% rename from boards/x86/intel_ehl/intel_ehl_crb.yaml rename to boards/intel/ehl/intel_ehl_crb.yaml diff --git a/boards/x86/intel_ehl/intel_ehl_crb_defconfig b/boards/intel/ehl/intel_ehl_crb_defconfig similarity index 80% rename from boards/x86/intel_ehl/intel_ehl_crb_defconfig rename to boards/intel/ehl/intel_ehl_crb_defconfig index e25760a5a05d3f..ba1c681c4cf9de 100644 --- a/boards/x86/intel_ehl/intel_ehl_crb_defconfig +++ b/boards/intel/ehl/intel_ehl_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ELKHART_LAKE=y -CONFIG_BOARD_INTEL_EHL_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/intel_ehl/intel_ehl_crb_sbl.dts b/boards/intel/ehl/intel_ehl_crb_sbl.dts similarity index 100% rename from boards/x86/intel_ehl/intel_ehl_crb_sbl.dts rename to boards/intel/ehl/intel_ehl_crb_sbl.dts diff --git a/boards/x86/intel_ehl/intel_ehl_crb_sbl.yaml b/boards/intel/ehl/intel_ehl_crb_sbl.yaml similarity index 78% rename from boards/x86/intel_ehl/intel_ehl_crb_sbl.yaml rename to boards/intel/ehl/intel_ehl_crb_sbl.yaml index 52cfa670ae6bfe..3493ed0611dd40 100644 --- a/boards/x86/intel_ehl/intel_ehl_crb_sbl.yaml +++ b/boards/intel/ehl/intel_ehl_crb_sbl.yaml @@ -1,4 +1,4 @@ -identifier: intel_ehl_crb_sbl +identifier: intel_ehl_crb/elkhart_lake/sbl name: Elkhart Lake CRB with Slim Bootloader type: mcu arch: x86 diff --git a/boards/x86/intel_ehl/intel_ehl_crb_sbl_defconfig b/boards/intel/ehl/intel_ehl_crb_sbl_defconfig similarity index 75% rename from boards/x86/intel_ehl/intel_ehl_crb_sbl_defconfig rename to boards/intel/ehl/intel_ehl_crb_sbl_defconfig index 1ccff387dc120a..29055f28717b41 100644 --- a/boards/x86/intel_ehl/intel_ehl_crb_sbl_defconfig +++ b/boards/intel/ehl/intel_ehl_crb_sbl_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ELKHART_LAKE=y -CONFIG_BOARD_INTEL_EHL_CRB_SBL=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/intel/index.rst b/boards/intel/index.rst new file mode 100644 index 00000000000000..800c4e5bd51746 --- /dev/null +++ b/boards/intel/index.rst @@ -0,0 +1,10 @@ +.. _boards-intel: + +Intel Corporation +################# + +.. toctree:: + :maxdepth: 1 + :glob: + + */**/index diff --git a/boards/intel/ish/Kconfig.defconfig b/boards/intel/ish/Kconfig.defconfig new file mode 100644 index 00000000000000..fdedc70fd29b52 --- /dev/null +++ b/boards/intel/ish/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +if TEST +config TEST_EXTRA_STACK_SIZE + default 1024 +endif # TEST + +config SYS_CLOCK_TICKS_PER_SEC + default 2048 if HPET_TIMER # HPET is 32768 HZ diff --git a/boards/intel/ish/Kconfig.intel_ish_5_4_1 b/boards/intel/ish/Kconfig.intel_ish_5_4_1 new file mode 100644 index 00000000000000..62ef1213675836 --- /dev/null +++ b/boards/intel/ish/Kconfig.intel_ish_5_4_1 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ISH_5_4_1 + select SOC_INTEL_ISH_5_4_1 diff --git a/boards/intel/ish/Kconfig.intel_ish_5_6_0 b/boards/intel/ish/Kconfig.intel_ish_5_6_0 new file mode 100644 index 00000000000000..4c8fe37972cca3 --- /dev/null +++ b/boards/intel/ish/Kconfig.intel_ish_5_6_0 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ISH_5_6_0 + select SOC_INTEL_ISH_5_6_0 diff --git a/boards/intel/ish/Kconfig.intel_ish_5_8_0 b/boards/intel/ish/Kconfig.intel_ish_5_8_0 new file mode 100644 index 00000000000000..122fc3b30ba84a --- /dev/null +++ b/boards/intel/ish/Kconfig.intel_ish_5_8_0 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_ISH_5_8_0 + select SOC_INTEL_ISH_5_8_0 diff --git a/boards/intel/ish/board.yml b/boards/intel/ish/board.yml new file mode 100644 index 00000000000000..ee7c4661800701 --- /dev/null +++ b/boards/intel/ish/board.yml @@ -0,0 +1,16 @@ +boards: + + - name: intel_ish_5_4_1 + vendor: intel + socs: + - name: intel_ish_5_4_1 + + - name: intel_ish_5_6_0 + vendor: intel + socs: + - name: intel_ish_5_6_0 + + - name: intel_ish_5_8_0 + vendor: intel + socs: + - name: intel_ish_5_8_0 diff --git a/boards/intel/ish/doc/index.rst b/boards/intel/ish/doc/index.rst new file mode 100644 index 00000000000000..d9c3c179b23768 --- /dev/null +++ b/boards/intel/ish/doc/index.rst @@ -0,0 +1,79 @@ +.. _intel_ish: + +Intel Integrated Sensor Hub (ISH) +################################# + +Overview +******** +Intel Integrated Sensor Hub (ISH) is a lower-power/always-on co-processor +inside many Intel Processors. It helps offload sensor processing tasks from +the core processor for better power saving. + +Hardware +******** + +- LMT MinuteIA Core: + + - 16KB instruction cache and 16KB data cache. + - 640KB SRAM space for code and data - implemented as L2 SRAM. + - 8KB AON RF space for code resident during deep D0i2/3 PG states. + +- Interface-to-Sensor peripherals (I2C, SPI, UART, I3C, GPIO, DMA). +- Inter Process Communications (IPC) to core processor and other IP processors. + +.. include:: ../../../../soc/intel/intel_ish/doc/supported_features.txt + +Programming and Debugging +************************* +Use the following procedures for booting an ISH image on a ADL RVP board +for Chrome. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application for ISH 5.4.1 on Intel ADL Processor: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_ish_5_4_1 + :goals: build + + .. note:: + + A Zephyr image file named :file:`ish_fw.bin` is automatically + created in the build directory after the application is built. + +Run ish_fw.bin on ADL RVP board for Chrome +========================================== + +- Power on the ADL RVP board. +- Log in Chrome OS. (Note: the user must have root access right, see `Developer Mode`_) +- Re-mount the root filesystem as read-write: + +.. code-block:: console + + $ mount -o remount,rw / + +- If re-mount fails, execute below commands to Remove rootfs verification: + +.. code-block:: console + + $ /usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --partitions + $ reboot + +- Go to the ISH firmware direcoty: + +.. code-block:: console + + $ cd /lib/firmware/intel + +- Relace the file adlrvp_ish.bin with zephyr image built out, ish_fw.bin. +- Reboot, then observe Zephyr log output via ISH UART0. + +.. _Developer Mode: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md diff --git a/boards/x86/intel_ish/intel_ish_5_4_1.dts b/boards/intel/ish/intel_ish_5_4_1.dts similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_4_1.dts rename to boards/intel/ish/intel_ish_5_4_1.dts diff --git a/boards/x86/intel_ish/intel_ish_5_4_1.yaml b/boards/intel/ish/intel_ish_5_4_1.yaml similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_4_1.yaml rename to boards/intel/ish/intel_ish_5_4_1.yaml diff --git a/boards/intel/ish/intel_ish_5_4_1_defconfig b/boards/intel/ish/intel_ish_5_4_1_defconfig new file mode 100644 index 00000000000000..de4d5660e15b1d --- /dev/null +++ b/boards/intel/ish/intel_ish_5_4_1_defconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +# uart & console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_6_0.dts b/boards/intel/ish/intel_ish_5_6_0.dts similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_6_0.dts rename to boards/intel/ish/intel_ish_5_6_0.dts diff --git a/boards/x86/intel_ish/intel_ish_5_6_0.yaml b/boards/intel/ish/intel_ish_5_6_0.yaml similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_6_0.yaml rename to boards/intel/ish/intel_ish_5_6_0.yaml diff --git a/boards/intel/ish/intel_ish_5_6_0_defconfig b/boards/intel/ish/intel_ish_5_6_0_defconfig new file mode 100644 index 00000000000000..de4d5660e15b1d --- /dev/null +++ b/boards/intel/ish/intel_ish_5_6_0_defconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +# uart & console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_8_0.dts b/boards/intel/ish/intel_ish_5_8_0.dts similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_8_0.dts rename to boards/intel/ish/intel_ish_5_8_0.dts diff --git a/boards/x86/intel_ish/intel_ish_5_8_0.yaml b/boards/intel/ish/intel_ish_5_8_0.yaml similarity index 100% rename from boards/x86/intel_ish/intel_ish_5_8_0.yaml rename to boards/intel/ish/intel_ish_5_8_0.yaml diff --git a/boards/intel/ish/intel_ish_5_8_0_defconfig b/boards/intel/ish/intel_ish_5_8_0_defconfig new file mode 100644 index 00000000000000..de4d5660e15b1d --- /dev/null +++ b/boards/intel/ish/intel_ish_5_8_0_defconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +# uart & console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/intel/niosv_g/Kconfig.niosv_g b/boards/intel/niosv_g/Kconfig.niosv_g new file mode 100644 index 00000000000000..2d07c1b5e15201 --- /dev/null +++ b/boards/intel/niosv_g/Kconfig.niosv_g @@ -0,0 +1,8 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NIOSV_G + select SOC_NIOSV_G + help + Intel FPGA Nios V/g General Purpose Processor diff --git a/boards/intel/niosv_g/board.yml b/boards/intel/niosv_g/board.yml new file mode 100644 index 00000000000000..7f6cc30ce62a02 --- /dev/null +++ b/boards/intel/niosv_g/board.yml @@ -0,0 +1,4 @@ +board: + name: niosv_g + socs: + - name: niosv_g diff --git a/boards/riscv/niosv_g/doc/index.rst b/boards/intel/niosv_g/doc/index.rst similarity index 100% rename from boards/riscv/niosv_g/doc/index.rst rename to boards/intel/niosv_g/doc/index.rst diff --git a/boards/riscv/niosv_g/niosv_g.dts b/boards/intel/niosv_g/niosv_g.dts similarity index 100% rename from boards/riscv/niosv_g/niosv_g.dts rename to boards/intel/niosv_g/niosv_g.dts diff --git a/boards/riscv/niosv_g/niosv_g.yaml b/boards/intel/niosv_g/niosv_g.yaml similarity index 100% rename from boards/riscv/niosv_g/niosv_g.yaml rename to boards/intel/niosv_g/niosv_g.yaml diff --git a/boards/intel/niosv_g/niosv_g_defconfig b/boards/intel/niosv_g/niosv_g_defconfig new file mode 100644 index 00000000000000..27dd451aaf576e --- /dev/null +++ b/boards/intel/niosv_g/niosv_g_defconfig @@ -0,0 +1,9 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n diff --git a/boards/intel/niosv_m/Kconfig.niosv_m b/boards/intel/niosv_m/Kconfig.niosv_m new file mode 100644 index 00000000000000..c7474b4b926ed4 --- /dev/null +++ b/boards/intel/niosv_m/Kconfig.niosv_m @@ -0,0 +1,8 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NIOSV_M + select SOC_NIOSV_M + help + Intel FPGA NIOSV Microcontroller Core Processor diff --git a/boards/intel/niosv_m/board.yml b/boards/intel/niosv_m/board.yml new file mode 100644 index 00000000000000..a77efa39ff186c --- /dev/null +++ b/boards/intel/niosv_m/board.yml @@ -0,0 +1,4 @@ +board: + name: niosv_m + socs: + - name: niosv_m diff --git a/boards/riscv/niosv_m/doc/index.rst b/boards/intel/niosv_m/doc/index.rst similarity index 100% rename from boards/riscv/niosv_m/doc/index.rst rename to boards/intel/niosv_m/doc/index.rst diff --git a/boards/riscv/niosv_m/niosv_m.dts b/boards/intel/niosv_m/niosv_m.dts similarity index 100% rename from boards/riscv/niosv_m/niosv_m.dts rename to boards/intel/niosv_m/niosv_m.dts diff --git a/boards/riscv/niosv_m/niosv_m.yaml b/boards/intel/niosv_m/niosv_m.yaml similarity index 100% rename from boards/riscv/niosv_m/niosv_m.yaml rename to boards/intel/niosv_m/niosv_m.yaml diff --git a/boards/intel/niosv_m/niosv_m_defconfig b/boards/intel/niosv_m/niosv_m_defconfig new file mode 100644 index 00000000000000..9ac86fe8e526ba --- /dev/null +++ b/boards/intel/niosv_m/niosv_m_defconfig @@ -0,0 +1,10 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_PRINTK=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_ALTERA_JTAG=y +CONFIG_XIP=n diff --git a/boards/intel/rpl/CMakeLists.txt b/boards/intel/rpl/CMakeLists.txt new file mode 100644 index 00000000000000..36ddcdf9d1392b --- /dev/null +++ b/boards/intel/rpl/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/intel/rpl/Kconfig.defconfig b/boards/intel/rpl/Kconfig.defconfig new file mode 100644 index 00000000000000..ca8a77426881b0 --- /dev/null +++ b/boards/intel/rpl/Kconfig.defconfig @@ -0,0 +1,59 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +config ACPI + default y + +if ACPI +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 +config MAIN_STACK_SIZE + default 320000 + +if SHELL +config SHELL_STACK_SIZE + default 320000 +endif # SHELL +endif # ACPI + +if DMA +config DMA_64BIT + default y +config DMA_DW_HW_LLI + default n +config DMA_DW_CHANNEL_COUNT + default 2 +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y if BOARD_INTEL_RPL_S_CRB + +if SHELL +config SHELL_STACK_SIZE + default 320000 +endif + +config HAS_COVERAGE_SUPPORT + default y diff --git a/boards/intel/rpl/Kconfig.intel_rpl_p_crb b/boards/intel/rpl/Kconfig.intel_rpl_p_crb new file mode 100644 index 00000000000000..91449a9d2b7e2c --- /dev/null +++ b/boards/intel/rpl/Kconfig.intel_rpl_p_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_RPL_P_CRB + select SOC_RAPTOR_LAKE diff --git a/boards/intel/rpl/Kconfig.intel_rpl_s_crb b/boards/intel/rpl/Kconfig.intel_rpl_s_crb new file mode 100644 index 00000000000000..79dc093dfe6cbd --- /dev/null +++ b/boards/intel/rpl/Kconfig.intel_rpl_s_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_RPL_S_CRB + select SOC_RAPTOR_LAKE diff --git a/boards/x86/intel_rpl/board.cmake b/boards/intel/rpl/board.cmake similarity index 100% rename from boards/x86/intel_rpl/board.cmake rename to boards/intel/rpl/board.cmake diff --git a/boards/intel/rpl/board.yml b/boards/intel/rpl/board.yml new file mode 100644 index 00000000000000..cc3969adcede0f --- /dev/null +++ b/boards/intel/rpl/board.yml @@ -0,0 +1,9 @@ +boards: + - name: intel_rpl_p_crb + vendor: intel + socs: + - name: raptor_lake + - name: intel_rpl_s_crb + vendor: intel + socs: + - name: raptor_lake diff --git a/boards/intel/rpl/doc/index.rst b/boards/intel/rpl/doc/index.rst new file mode 100644 index 00000000000000..4c078ab765ec01 --- /dev/null +++ b/boards/intel/rpl/doc/index.rst @@ -0,0 +1,75 @@ +.. _intel_rpl_crb: + +Raptor Lake CRB +############### + +Overview +******** +Raptor Lake processor is a 13th generation 64-bit multi-core processor built +on a 10-nanometer technology process. Raptor Lake is based on a Hybrid +architecture, utilizing P-cores for performance and E-Cores for efficiency. + +Raptor Lake S and Raptor Lake P processor lines are supported. + +The S-Processor line is a 2-Chip Platform that includes the Processor Die and +Platform Controller Hub (PCH-S) Die in the Package. + +The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the +Processor Die and Platform Controller Hub (PCH-P) Die on the same package as +the Processor Die. + +For more information about Raptor Lake Processor lines, P-cores, and E-cores +please refer to `RPL`_. + +Raptor Lake Customer Reference Board (RPL CRB) is an example implementation of a +compact single board computer with high performance for IoT edge devices. The +supported boards are `intel_rpl_s_crb` and `intel_rpl_p_crb`. + +These board configurations enable kernel support for the supported Raptor Lake +boards. + +Hardware +******** + +General information about the board can be found at the `RPL`_. + +.. include:: ../../../../soc/intel/raptor_lake/doc/supported_features.txt + + +Connections and IOs +=================== + +Refer to the `RPL`_ for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image on an RPL CRB board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application on Raptor Lake S CRB: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_rpl_s_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the Raptor Lake S CRB Board using UEFI +============================================== + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. _RPL: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/ diff --git a/boards/x86/intel_rpl/intel_rpl_p_crb.dts b/boards/intel/rpl/intel_rpl_p_crb.dts similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_p_crb.dts rename to boards/intel/rpl/intel_rpl_p_crb.dts diff --git a/boards/x86/intel_rpl/intel_rpl_p_crb.yaml b/boards/intel/rpl/intel_rpl_p_crb.yaml similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_p_crb.yaml rename to boards/intel/rpl/intel_rpl_p_crb.yaml diff --git a/boards/x86/intel_rpl/intel_rpl_p_crb_defconfig b/boards/intel/rpl/intel_rpl_p_crb_defconfig similarity index 82% rename from boards/x86/intel_rpl/intel_rpl_p_crb_defconfig rename to boards/intel/rpl/intel_rpl_p_crb_defconfig index 09fd65cf261599..c94efc744f68c4 100644 --- a/boards/x86/intel_rpl/intel_rpl_p_crb_defconfig +++ b/boards/intel/rpl/intel_rpl_p_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RAPTOR_LAKE=y -CONFIG_BOARD_INTEL_RPL_P_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/intel_rpl/intel_rpl_s_crb.dts b/boards/intel/rpl/intel_rpl_s_crb.dts similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_s_crb.dts rename to boards/intel/rpl/intel_rpl_s_crb.dts diff --git a/boards/x86/intel_rpl/intel_rpl_s_crb.yaml b/boards/intel/rpl/intel_rpl_s_crb.yaml similarity index 100% rename from boards/x86/intel_rpl/intel_rpl_s_crb.yaml rename to boards/intel/rpl/intel_rpl_s_crb.yaml diff --git a/boards/x86/intel_rpl/intel_rpl_s_crb_defconfig b/boards/intel/rpl/intel_rpl_s_crb_defconfig similarity index 82% rename from boards/x86/intel_rpl/intel_rpl_s_crb_defconfig rename to boards/intel/rpl/intel_rpl_s_crb_defconfig index 1d8570bdeb7498..c94efc744f68c4 100644 --- a/boards/x86/intel_rpl/intel_rpl_s_crb_defconfig +++ b/boards/intel/rpl/intel_rpl_s_crb_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RAPTOR_LAKE=y -CONFIG_BOARD_INTEL_RPL_S_CRB=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig b/boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig new file mode 100644 index 00000000000000..549795110a543b --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config HAS_COVERAGE_SUPPORT + default y + +config MAX_THREAD_BYTES + default 5 diff --git a/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk b/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk new file mode 100644 index 00000000000000..603cdb55a6720b --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/Kconfig.intel_socfpga_agilex5_socdk @@ -0,0 +1,7 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK + select SOC_AGILEX5 + help + Intel SoC FPGA Development Kit (Agilex5) diff --git a/boards/intel/socfpga/agilex5_socdk/board.yml b/boards/intel/socfpga/agilex5_socdk/board.yml new file mode 100644 index 00000000000000..fd4f5c91d66746 --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/board.yml @@ -0,0 +1,4 @@ +board: + name: intel_socfpga_agilex5_socdk + socs: + - name: agilex5 diff --git a/boards/intel/socfpga/agilex5_socdk/doc/index.rst b/boards/intel/socfpga/agilex5_socdk/doc/index.rst new file mode 100644 index 00000000000000..006ca06625167d --- /dev/null +++ b/boards/intel/socfpga/agilex5_socdk/doc/index.rst @@ -0,0 +1,80 @@ +.. _intel_socfpga_agilex5_socdk: + +Intel® Agilex™ 5 SoC FPGA Development Kit +######################################### + +Overview +******** + +The Intel® Agilex™ 5 SoC FPGA Development Kit offers a complete design +environment that includes both hardware and software for developing +Intel® Agilex™ 5 E-Series based FPGA designs. This kit is recommended for +developing custom ARM* processor-based SoC designs and ideal for intelligent +applications at the edge, embedded and more. + +Hardware +******** + +The Intel® Agilex™ 5 Development Kit supports the following physical features: + +- Intel® Agilex™ 5 E-Series FPGA, 50K-656K LEs integrated with + multi-core ARM processors of Dual-core A55 and Dual-core A76 +- On-board 8 GB DDR5 memory +- On-board JTAG Intel FPGA Download Cable II +- QSPI flash daughtercard + +Supported Features +================== +The Intel® Agilex™ 5 SoC Development Kit configuration supports the following +hardware features: + ++-----------+------------+---------------------------------------------+ +| Interface | Controller | Hardware Subsystem Vendor | ++===========+============+=============================================+ +| GIC-600 | on-chip | ARM GICv3 interrupt controller | ++-----------+------------+---------------------------------------------+ +| UART | on-chip | Synopsys Designware,NS16550 compatible | ++-----------+------------+---------------------------------------------+ +| ARM TIMER | on-chip | ARM system timer | ++-----------+------------+---------------------------------------------+ +| Reset | on-chip | Intel Corporation, SoCFPGA Reset controller | ++-----------+------------+---------------------------------------------+ +| Clock | on-chip | Intel Corporation, SoCFPGA Clock controller | ++-----------+------------+---------------------------------------------+ + +NOTE: TODO, more details on dev kit will be updated as and when available. + +The default configuration can be found in the defconfig file: + `boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig` + +Programming and Debugging +************************* + +Zephyr Boot Flow +**************** +Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). +ATF BL2 is the First Stage Boot Loader (FSBL) and ATF BL31 is the Run time resident firmware which +provides services like SMC (Secure monitor calls) and PSCI (Power state coordination interface). + +Boot flow: + ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL1) + +Intel Arm Trusted Firmware (ATF) can be downloaded from github: + `altera-opensource/arm-trusted-firmware `_ + +Flashing +======== +Zephyr image can be loaded in DDR memory at address 0x80000000 from +SD Card or QSPI Flash or NAND in ATF BL2. + +Debugging +========= +The Intel® Agilex™ 5 SoC Development Kit includes one JTAG connector on +board, connect it to Intel USB blaster download cables for debugging. + +Zephyr applications running on the Cortex-A55/A76 core can be tested by +observing UART console output. + +References +========== +`Intel® Agilex™ 5 FPGA and SoC FPGA `_ diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.dts b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts similarity index 100% rename from boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.dts rename to boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.dts diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.yaml b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.yaml similarity index 100% rename from boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk.yaml rename to boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk.yaml diff --git a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig similarity index 84% rename from boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig rename to boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig index 0985f470c74841..2ac56d65d379be 100644 --- a/boards/arm64/intel_socfpga_agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig +++ b/boards/intel/socfpga/agilex5_socdk/intel_socfpga_agilex5_socdk_defconfig @@ -1,14 +1,10 @@ -# Copyright (c) 2023 Intel Corporation +# Copyright (c) 2023-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 # The Zephyr build from this defconfig is expected to boot from # Intel Arm Trusted Firmware (ATF). # Boot Flow is: ATF BL21 -> ATF BL31 -> Zephyr -CONFIG_SOC_SERIES_AGILEX5=y -CONFIG_SOC_AGILEX5=y -CONFIG_BOARD_INTEL_SOCFPGA_AGILEX5_SOCDK=y - # Compiler Options CONFIG_FORTIFY_SOURCE_RUN_TIME=y diff --git a/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk b/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk new file mode 100644 index 00000000000000..18fcd9d69e85ee --- /dev/null +++ b/boards/intel/socfpga/agilex_socdk/Kconfig.intel_socfpga_agilex_socdk @@ -0,0 +1,7 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_SOCFPGA_AGILEX_SOCDK + select SOC_AGILEX + help + Intel SoC FPGA Development Kit (Agilex) diff --git a/boards/intel/socfpga/agilex_socdk/board.yml b/boards/intel/socfpga/agilex_socdk/board.yml new file mode 100644 index 00000000000000..1c09cba049170c --- /dev/null +++ b/boards/intel/socfpga/agilex_socdk/board.yml @@ -0,0 +1,4 @@ +board: + name: intel_socfpga_agilex_socdk + socs: + - name: agilex diff --git a/boards/intel/socfpga/agilex_socdk/doc/index.rst b/boards/intel/socfpga/agilex_socdk/doc/index.rst new file mode 100644 index 00000000000000..92db2c9830050b --- /dev/null +++ b/boards/intel/socfpga/agilex_socdk/doc/index.rst @@ -0,0 +1,78 @@ +.. _intel_socfpga_agilex_socdk: + +Intel Agilex SoC Development Kit +################################# + +Overview +******** + +The Intel Agilex SoC Development Kit offers a complete design environment +that includes both hardware and software for developing Intel Agilex +F-Series FPGA designs. This kit is recommended for developing custom +Arm* processor-based SoC designs and evaluating transceiver performance. + +Hardware +******** + +The Intel Agilex SoC Development Kit supports the following physical features: + +- Intel Agilex F-Series FPGA, 1400 KLE, 2486A package integrate the + quad-core Arm Cortex-A53 processor +- On-board 8 GB DDR4 memory +- On-board JTAG Intel FPGA Download Cable II +- QSPI flash daughtercard +- HPS OOBE daughtercard with UART and SD Card support + +Supported Features +================== +The Intel Agilex SoC Development Kit configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-400 | on-chip | GICv2 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig` + +Programming and Debugging +************************* + +Boot Flow +========= +Zephyr image will need to be loaded by Intel Arm Trusted Firmware (ATF). +ATF BL2 is first stage boot loader (FSBL) and ATF BL31 is second stage +boot loader (SSBL). + +Zephyr boot flow: + + ATF BL2 (EL3) -> ATF BL31 (EL3) -> Zephyr (EL2->EL1) + +Intel Arm Trusted Firmware (ATF) can be downloaded from github: + + `altera-opensource/arm-trusted-firmware `_ + +Flashing +======== +Zephyr image can be loaded in DDR memory at address 0x10000000 from +SD Card or QSPI Flash in ATF BL2. + +Debugging +========= +The Intel Agilex SoC Development Kit includes one JTAG connector on +board, connect it to Intel USB blaster download cables for debugging. + +Zephyr applications running on the Cortex-A53 core can be tested by +observing UART console output. + +References +========== +`Intel Agilex Transceiver-SoC Development Kit `_ diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.dts b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.dts similarity index 100% rename from boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.dts rename to boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.dts diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.yaml b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.yaml similarity index 100% rename from boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk.yaml rename to boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk.yaml diff --git a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig similarity index 77% rename from boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig rename to boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig index b2ffb0602d3c91..6b5cf5c9cb7e51 100644 --- a/boards/arm64/intel_socfpga_agilex_socdk/intel_socfpga_agilex_socdk_defconfig +++ b/boards/intel/socfpga/agilex_socdk/intel_socfpga_agilex_socdk_defconfig @@ -1,13 +1,10 @@ -# Copyright (c) 2021 Intel Corporation +# Copyright (c) 2021-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 # The Zephyr build from this defconfig is expected to boot from # Intel Arm Trusted Firmware (ATF) # Boot Flow: BL21 -> BL31 -> Zephyr -CONFIG_SOC_SERIES_AGILEX=y -CONFIG_SOC_AGILEX=y -CONFIG_BOARD_INTEL_SOCFPGA_AGILEX_SOCDK=y CONFIG_ARM_ARCH_TIMER=y # Serial Drivers diff --git a/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk new file mode 100644 index 00000000000000..cb62866b339f9d --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.cyclonev_socdk @@ -0,0 +1,7 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CYCLONEV_SOCDK + select SOC_CYCLONEV + help + Intel Cyclone V Development Kit diff --git a/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.defconfig b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.defconfig new file mode 100644 index 00000000000000..8afe506078be0f --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if I2C_DW +config I2C_DW_CLOCK_SPEED + default 200 +endif # I2C_DW + +if USB_DEVICE_STACK +config USB_DW_USB_2_0 + default y +config USB_DEVICE_DRIVER + default y +endif # USB_DEVICE_STACK + +if NETWORKING + +config NET_L2_ETHERNET + default y +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING diff --git a/boards/intel/socfpga_std/cyclonev_socdk/board.cmake b/boards/intel/socfpga_std/cyclonev_socdk/board.cmake new file mode 100644 index 00000000000000..adc44a8125a0d7 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/board.cmake @@ -0,0 +1,19 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(intel_cyclonev) +board_set_debugger_ifnset(intel_cyclonev) + +if(OPENOCD_USE_LOAD_IMAGE) + set_ifndef(OPENOCD_FLASH load_image) +else() + set_ifndef(OPENOCD_FLASH "flash write_image erase") +endif() + +set(OPENOCD_CMD_LOAD_DEFAULT "${OPENOCD_FLASH}") +set(OPENOCD_CMD_VERIFY_DEFAULT "verify_image") + +board_finalize_runner_args(intel_cyclonev + --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}" + --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}" + ) diff --git a/boards/intel/socfpga_std/cyclonev_socdk/board.yml b/boards/intel/socfpga_std/cyclonev_socdk/board.yml new file mode 100644 index 00000000000000..420762dda3f104 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/board.yml @@ -0,0 +1,4 @@ +board: + name: cyclonev_socdk + socs: + - name: cyclonev diff --git a/boards/arm/cyclonev_socdk/cyclonev_socdk.dts b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts similarity index 92% rename from boards/arm/cyclonev_socdk/cyclonev_socdk.dts rename to boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts index 79753b3d53f00d..5218c62f2c7bd5 100644 --- a/boards/arm/cyclonev_socdk/cyclonev_socdk.dts +++ b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.dts @@ -6,12 +6,12 @@ * this file is based on the GSRD DTS for Linux */ -#include "intel_socfpga_std/socfpga_cyclone5.dtsi" +#include "intel_socfpga_std/socfpga_cyclonev.dtsi" #include / { model = "Altera SOCFPGA Cyclone V SoC Development Kit"; - compatible = "altr,socfpga-cyclone5-socdk", "altr,socfpga-cyclone5", "altr,socfpga"; + compatible = "altr,socfpga-cyclonev-socdk", "altr,socfpga-cyclonev", "altr,socfpga"; ddr0: memory@0 { name = "memory"; diff --git a/boards/arm/cyclonev_socdk/cyclonev_socdk.yaml b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.yaml similarity index 100% rename from boards/arm/cyclonev_socdk/cyclonev_socdk.yaml rename to boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk.yaml diff --git a/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk_defconfig b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk_defconfig new file mode 100644 index 00000000000000..32f784e44c8324 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/cyclonev_socdk_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_ARCH_TIMER=y + +CONFIG_SYSCON=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_NS16550_VARIANT_NS16950=y + +#Config Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +#Flash not used. +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 + +# GPIOs +CONFIG_GPIO=y diff --git a/boards/arm/cyclonev_socdk/doc/img/cv_soc_board.jpg b/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cv_soc_board.jpg similarity index 100% rename from boards/arm/cyclonev_socdk/doc/img/cv_soc_board.jpg rename to boards/intel/socfpga_std/cyclonev_socdk/doc/img/cv_soc_board.jpg diff --git a/boards/arm/cyclonev_socdk/doc/img/cyclonev_blinky.jpg b/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_blinky.jpg similarity index 100% rename from boards/arm/cyclonev_socdk/doc/img/cyclonev_blinky.jpg rename to boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_blinky.jpg diff --git a/boards/arm/cyclonev_socdk/doc/img/cyclonev_westflash.jpg b/boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_westflash.jpg similarity index 100% rename from boards/arm/cyclonev_socdk/doc/img/cyclonev_westflash.jpg rename to boards/intel/socfpga_std/cyclonev_socdk/doc/img/cyclonev_westflash.jpg diff --git a/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst new file mode 100644 index 00000000000000..752284a63b9c79 --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/doc/index.rst @@ -0,0 +1,359 @@ +.. _cyclonev_socdk: + +Intel® Cyclone® V SoC Development Kit +##################################### + +Overview +******** + + +The Zephyr kernel is supported on the Intel® Cyclone® V SoC Development Kit, +using its Hard Processor System (HPS) CPU. + +.. figure:: img/cv_soc_board.jpg + :align: center + :alt: Intel's Cyclone® V SoC FPGA DevKit + + Intel®'s Cyclone® V SoC FPGA DevKit (Credit: Intel®) + +Hardware +******** + +Jumpers and DIP Switch settings +=============================== + +Recommended board settings are the same as the GSRD for Cyclone® V +SoC Development Board. + +There are two sets of switches on the back of the board. Of particular +importance is SW2. First, the board jumpers need to be configured as follows: + +* J5 : Open +* J6 : Short +* J7 : Short +* J9 : Open +* J13: Short +* J16: Open +* J26: Short pins 1-2 +* J27: Short pins 2-3 +* J28: Short pins 1-2 +* J29: Short pins 2-3 +* J30: Short pins 1-2 +* J31: Open + +Then, the board switches need to be configured as follows: + +* SW1: All OFF +* SW2: All OFF +* SW3: ON-OFF-ON-OFF-ON-ON +* SW4: OFF-OFF-ON-ON + +Other switches are user switches, their position is application-specific. +Refer to the development kit user manual for specifics about jumpers and switches + +Necessary Software +================== + +You will need the Intel® Quartus® Prime SDK in order to work with this device. The +`Intel® Quartus® Prime Lite Edition `_ +for Linux may be obtained without charge. + +For your convenience using the SDK tools (such as ``quartus_pgm``), +you should put the binaries provided by the SDK +in your path. Below is an example, adjust ALTERA_BASE to where you installed the +SDK: + +.. code-block:: console + + export QUARTUS_ROOTDIR=/opt/intelFPGA_lite/21.1 + export PATH=$PATH:$QUARTUS_ROOTDIR/quartus/bin:$QUARTUS_ROOTDIR/programmer/bin + +You may need to adjust your udev rules so that you can talk to the USB Blaster +II peripheral, which is the built-in JTAG interface for this device. + +The following works for Ubuntu: + +.. code-block:: console + + # For Altera USB-Blaster permissions. + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6010",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + SUBSYSTEM=="usb",\ + ENV{DEVTYPE}=="usb_device",\ + ATTR{idVendor}=="09fb",\ + ATTR{idProduct}=="6810",\ + MODE="0666",\ + NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ + RUN+="/bin/chmod 0666 %c" + +You can test connectivity with the SDK jtagconfig tool, you should see something +like: + +.. code-block:: console + + $ jtagconfig + 1) USB-BlasterII [1-5] + 4ba00477 SOCVHPS + 02D020DD 5ZSEBA6(.|ES)/5CSEMA6/.. + + +Golden Reference Design +======================= + +The Golden System Reference Design (GSRD) provides a set of essential hardware +and software system componets that can be used as a starting point for various +custom user designs. + +The Zephyr support for Cyclone® V SoC Development Kit is based on GSRD hardware. +Please refer to `Intel® Cyclone® V SoC GSRD `_ + +The hardware use for this release is based on Intel® Quartus® version 21.1 +the hardware files can be found `here `_ + +The directory "cv_soc_devkit_ghrd" contains the necessary files to create +a Intel® Quartus® project: + +* ghrd_top.v : top level Verilog (HDL) file for the GSRD +* soc_system.qpf : Quartus® Prime Project File +* soc_system.qsf : Quartus® Prime Settings File +* soc_system.qsys : Platform Designer file (contains the SoC system) +* soc_system.sopcinfo : SOPC Information file contains details about modules instantiated in the project, parameter names and values. +* soc_system_timing.sdc : Synopsys Desing Constraint FILE. +* output_files/soc_system.sof : FPGA configuration file. + + +Flash this FPGA file (.sof) using the ``quartus_pgm`` SDK tool with the FPGA +configuration file soc_system.sof: + +.. code-block:: console + + $ quartus_pgm -m jtag -o "p;path/to/soc_system.sof" + +This system is composed by the HPS, ARM Cortex-A9. In this example the UART, timer, +USB, I2C, DDR memory are exposed. Please double check the peripheral you intend to +use have its corresponding driver support. +You can find more information of the Cyclone® V SoC Devkit GSRD in RocketBoards +or consult the "Cyclone® V Hard Processor System Technical Reference Manual" + + +Console Output +============== + +16550 UART +---------- + +By default, the kernel is configured to send console output to the 16550 UART. +You can monitor this on your workstation by connecting to the top right mini USB +port on the board (J8/UART) (it will show up in /dev as a ttyUSB node), and then running +minicom/PuTTy with flow control disabled, 115200-8N1 settings. + + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Kernel into the board +------------------------------ + +The usual ``flash`` target will work with the ``cyclonev_socdk`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +``Important!!!`` : Before flashing the board a ``preloader`` is required, +you can download `cv_soc_devkit_ghrd.tar.gz `_, +extract the file and copy ``cv_soc_devkit_ghrd/software/preloader/uboot-socfpga/spl/u-boot-spl`` +to :zephyr_file:`boards/intel/socfpga_std/cyclonev_socdk/support/` + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cyclonev_socdk + :goals: flash + +Refer to :ref:`build_an_application` and :ref:`application_run` for +more details. + +This provisions the Zephyr kernel and the CPU configuration onto the board, +using the customized OpenOCD runner script :zephyr_file:`scripts/west_commands/runners/intel_cyclonev.py` +After it completes the kernel will immediately boot using the GSRD preloader. +Notice that there a lot of helper files to ``flash`` the application with +OpenOCD and GDB Debbuger (Zephyr SDK must be installed in your machine). +This files should be located in :zephyr_file:`boards/intel/socfpga_std/cyclonev_socdk/support/` including: + +* blaster_6810.hex : USB-BlasterII firmware +* tmp_preloader_dl_cmd.txt : GDB helper file to load the preloader +* tmp_appli_dl_cmd.gdb : GDB helper file to load the zephyr.elf file +* tmp_appli_debug_cmd.gdb : GDB helper file to load the zephyr.elf file while debugging +* openocd.cfg : sources configuration files for OpenOCD +* download_all.gdb : GDB helper file to load the preloader +* u-boot-spl : Cyclone® V SoC DevKit GSRD preloader (copied from GSRD: cv_soc_devkit_ghrd.tar.gz) + +The following image shows the expected output (UART) after executing "west flash" using +the "hello world" sample design: + +.. figure:: img/cyclonev_westflash.jpg + :align: center + :alt: UART output after "west flash" example + + UART output after "west flash" example (Credit: Intel®) + +Debugging +========= + +The Zephyr SDK includes a GDB server which can be used to debug a Cyclone® V +SoC Development Kit board. +You can either debug a running image that was flashed onto the device in User +Flash Memory (UFM), or load an image over the JTAG using GDB. + +Debugging With Flashed Image +---------------------------- + +You can debug an application in the usual way. Here is an example. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: cyclonev_socdk + :goals: debug + +You will see output similar to the following: + +.. code-block:: console + + -- west debug: rebuilding + ninja: no work to do. + -- west debug: using runner intel_cyclonev + -- runners.intel_cyclonev: OpenOCD GDB server running on port 3333; no thread info available + Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) + Licensed under GNU GPL v2 + For bug reports, read http://openocd.org/doc/doxygen/bugs.html + Info : only one transport option; autoselect 'jtag' + cycv_dbginit + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : Altera USB-Blaster II (uninitialized) found + Info : Loading firmware... + Info : Waiting for reenumerate... + Info : Waiting for reenumerate... + Info : Altera USB-Blaster II found (Firm. rev. = 1.39) + Info : This adapter doesn't support configurable speed + Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) + Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) + Info : DAP transaction stalled (WAIT) - slowing down + Info : DAP transaction stalled (WAIT) - slowing down + Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints + Info : starting gdb server for fpgasoc.cpu.0 on 3333 + Info : Listening on port 3333 for gdb connections + Info : accepting 'gdb' connection on tcp/3333 + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT + target halted in ARM state due to debug-request, current mode: Supervisor + cpsr: 0x600001d3 pc: 0x00002fa4 + MMU: disabled, D-Cache: disabled, I-Cache: enabled + warning: No executable has been specified and target does not support + determining executable automatically. Try using the "file" command. + 0x00002fa4 in ?? () + Restoring section .text (0xffff0000 to 0xffff6f84) + Info : DAP transaction stalled (WAIT) - slowing down + Warn : keep_alive() was not invoked in the 1000 ms timelimit. GDB alive packet not sent! (1469 ms). Workaround: increase "set remotetimeout" in GDB + Restoring section .rodata (0xffff6f84 to 0xffff8af9) + Restoring section .data (0xffff8b00 to 0xffff99d4) + Info : DAP transaction stalled (WAIT) - slowing down + Hardware assisted breakpoint 1 at 0xffff147e + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + + Temporary breakpoint 1, 0xffff147e in spl_boot_device () + [Inferior 1 (Remote target) detached] + Info : dropped 'gdb' connection + shutdown command invoked + Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) + Licensed under GNU GPL v2 + For bug reports, read http://openocd.org/doc/doxygen/bugs.html + Info : only one transport option; autoselect 'jtag' + cycv_dbginit + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : Altera USB-Blaster II found (Firm. rev. = 1.39) + Info : This adapter doesn't support configurable speed + Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) + Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) + Info : DAP transaction stalled (WAIT) - slowing down + Info : DAP transaction stalled (WAIT) - slowing down + Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT + Info : starting gdb server for fpgasoc.cpu.0 on 3333 + Info : Listening on port 3333 for gdb connections + Info : accepting 'gdb' connection on tcp/3333 + warning: No executable has been specified and target does not support + determining executable automatically. Try using the "file" command. + 0xffff147c in ?? () + warning: /home/demo/zephyrproject/zephyr/boards/intel/socfpga_std/cyclonev_socdk/support/tmp_appli_debug_cmd.gdb: No such file or directory + [Inferior 1 (Remote target) detached] + Info : dropped 'gdb' connection + shutdown command invoked + Open On-Chip Debugger 0.11.0+dev-00244-g7e3dbbbe2 (2021-11-18-07:14) + Licensed under GNU GPL v2 + For bug reports, read http://openocd.org/doc/doxygen/bugs.html + Info : only one transport option; autoselect 'jtag' + cycv_dbginit + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + Info : Altera USB-Blaster II found (Firm. rev. = 1.39) + Info : This adapter doesn't support configurable speed + Info : JTAG tap: fpgasoc.fpga.tap tap/device found: 0x02d020dd (mfg: 0x06e (Altera), part: 0x2d02, ver: 0x0) + Info : JTAG tap: fpgasoc.cpu tap/device found: 0x4ba00477 (mfg: 0x23b (ARM Ltd), part: 0xba00, ver: 0x4) + Info : DAP transaction stalled (WAIT) - slowing down + Info : DAP transaction stalled (WAIT) - slowing down + Info : fpgasoc.cpu.0: hardware has 6 breakpoints, 4 watchpoints + Reading symbols from /home/demo/zephyrproject/zephyr/build/zephyr/zephyr.elf... + Info : fpgasoc.cpu.0 rev 0, partnum c09, arch f, variant 3, implementor 41 + Info : fpgasoc.cpu.0: MPIDR level2 0, cluster 0, core 0, multi core, no SMT + Info : starting gdb server for fpgasoc.cpu.0 on 3333 + Info : Listening on port 3333 for gdb connections + Remote debugging using :3333 + Info : accepting 'gdb' connection on tcp/3333 + main () at /home/demo/zephyrproject/zephyr/samples/hello_world/src/main.c:11 + 11 printk("Hello World! %s\n", CONFIG_BOARD); + (gdb) + + +Try other examples +================== +There are varios examples that can be downloaded to the Cyclone® V SoC FPGA +Development Kit Board. Try to ``blink`` an LED from the HPS side of the chip: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: cyclonev_socdk + :goals: flash + +.. figure:: img/cyclonev_blinky.jpg + :align: center + :alt: HPS LED0 blinking example + + HPS LED0 blinking example (Credit: Intel®) + +Try writing characters to the LCD display connected to the i2c bus: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/lcd_cyclonev_socdk + :board: cyclonev_socdk + :goals: flash + + +References +********** + +* `Cyclone® V Hard Processor System Technical Reference Manual `_ +* `Cyclone® V SoC Development Kit and Intel® SoC FPGA Embedded Development Suite `_ +* `Cyclone® V SoC GSRD in RocketBoards.org `_ +* `Intel® FPGA Software Download Center `_ +* `Embedded Peripherals IP User Guide `_ +* `Quartus II Scripting Reference Manual `_ diff --git a/boards/arm/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg b/boards/intel/socfpga_std/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg similarity index 100% rename from boards/arm/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg rename to boards/intel/socfpga_std/cyclonev_socdk/support/altera-usb-blaster2-cyclonev.cfg diff --git a/boards/arm/cyclonev_socdk/support/appli_debug_cmd.gdb b/boards/intel/socfpga_std/cyclonev_socdk/support/appli_debug_cmd.gdb similarity index 100% rename from boards/arm/cyclonev_socdk/support/appli_debug_cmd.gdb rename to boards/intel/socfpga_std/cyclonev_socdk/support/appli_debug_cmd.gdb diff --git a/boards/arm/cyclonev_socdk/support/appli_dl_cmd.gdb b/boards/intel/socfpga_std/cyclonev_socdk/support/appli_dl_cmd.gdb similarity index 100% rename from boards/arm/cyclonev_socdk/support/appli_dl_cmd.gdb rename to boards/intel/socfpga_std/cyclonev_socdk/support/appli_dl_cmd.gdb diff --git a/boards/arm/cyclonev_socdk/support/blaster_6810.hex b/boards/intel/socfpga_std/cyclonev_socdk/support/blaster_6810.hex similarity index 100% rename from boards/arm/cyclonev_socdk/support/blaster_6810.hex rename to boards/intel/socfpga_std/cyclonev_socdk/support/blaster_6810.hex diff --git a/boards/intel/socfpga_std/cyclonev_socdk/support/download_all.gdb b/boards/intel/socfpga_std/cyclonev_socdk/support/download_all.gdb new file mode 100644 index 00000000000000..9770043891030b --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/support/download_all.gdb @@ -0,0 +1,18 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 +# Description: +# Download preloader and .elf using GDB commands + +set confirm off +set pagination off + +#Download and Run preloader +source boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt + +#Stop watchdog timer +#permodrst Reg , reset watch dog timer +set $permodrst = (int *)0xffd05014 +set *$permodrst = (*$permodrst) | (1<<6) +set *$permodrst = (*$permodrst) & ~(1<<6) + +quit diff --git a/boards/arm/cyclonev_socdk/support/openocd.cfg b/boards/intel/socfpga_std/cyclonev_socdk/support/openocd.cfg similarity index 100% rename from boards/arm/cyclonev_socdk/support/openocd.cfg rename to boards/intel/socfpga_std/cyclonev_socdk/support/openocd.cfg diff --git a/boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt b/boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt new file mode 100644 index 00000000000000..f349b2ec6db87a --- /dev/null +++ b/boards/intel/socfpga_std/cyclonev_socdk/support/preloader_dl_cmd.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 +# Description: +# Helper file to download the GSRD preloader to the board before the application + +restore boards/intel/socfpga_std/cyclonev_socdk/support/u-boot-spl +symbol-file -readnow boards/intel/socfpga_std/cyclonev_socdk/support/u-boot-spl +thbreak spl_boot_device +jump _start diff --git a/boards/ite/index.rst b/boards/ite/index.rst new file mode 100644 index 00000000000000..e603fcd44c17f8 --- /dev/null +++ b/boards/ite/index.rst @@ -0,0 +1,10 @@ +.. _boards-ite: + +ITE Tech. Inc. +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ite/it82xx2_evb/Kconfig.defconfig b/boards/ite/it82xx2_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..a106a9d61514ca --- /dev/null +++ b/boards/ite/it82xx2_evb/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IT82XX2_EVB + +config INPUT + default y if KSCAN + +endif diff --git a/boards/ite/it82xx2_evb/Kconfig.it82xx2_evb b/boards/ite/it82xx2_evb/Kconfig.it82xx2_evb new file mode 100644 index 00000000000000..94025707fa4867 --- /dev/null +++ b/boards/ite/it82xx2_evb/Kconfig.it82xx2_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IT82XX2_EVB + select SOC_IT82202_AX diff --git a/boards/ite/it82xx2_evb/board.yml b/boards/ite/it82xx2_evb/board.yml new file mode 100644 index 00000000000000..f986050cad3d7b --- /dev/null +++ b/boards/ite/it82xx2_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: it82xx2_evb + vendor: ite + socs: + - name: it82202ax diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P1.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P1.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P1.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P1.jpg diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P2.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P2.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P2.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P2.jpg diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P3.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P3.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P3.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P3.jpg diff --git a/boards/riscv/it82xx2_evb/doc/WinFlashTool_P4.jpg b/boards/ite/it82xx2_evb/doc/WinFlashTool_P4.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/WinFlashTool_P4.jpg rename to boards/ite/it82xx2_evb/doc/WinFlashTool_P4.jpg diff --git a/boards/ite/it82xx2_evb/doc/index.rst b/boards/ite/it82xx2_evb/doc/index.rst new file mode 100644 index 00000000000000..e969114180e11b --- /dev/null +++ b/boards/ite/it82xx2_evb/doc/index.rst @@ -0,0 +1,247 @@ +.. _it82xx2_evb: + +ITE IT82XX2 series +###################### + +Overview +******** + +The IT82XX2 is a 32-bit RISC-V microcontroller. +And a highly integrated embedded controller with system functions. +It is suitable for mobile system applications. The picture below is +the IT82202 development board (also known as it82xx2_evb) and its debug card. + +.. figure:: it82xx2_evb_and_debug_card.jpg + :align: center + :alt: IT82202 EVB + +To find out more about ITE, visit our World Wide Web at:`ITE's website`_ + +Hardware +******** +The IT82XX2 series contains different chip types(ex, it82202, it82302), +and they support different hardware features. +Listing the IT82202 hardware features as following: + +- RISC-V RV32IMAFC instruction set +- 4KB instruction cache size +- 256KB SRAM in total +- Built-in 32.768 kHz clock generator +- Embedded Flash, 512K/1024K-byte e-flash +- eSPI, SSPI, SPI slave, BRAM, KBC, PECI, UART +- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG +- Support 6 Voltage Comparator +- Support Cryptographic Engine +- 6 SMBus channels, with 6 DMA controller, compatible with I2C +- USB 2.0 Full-speed Controller +- USB Type-c CC Logic +- USB Power Delivery + + +Supported Features +================== +currently supports the following hardware features: + +.. list-table:: Supported Features + :header-rows: 1 + :widths: auto + + * - Interface + - Controller + - Driver/Component + * - NVIC + - on-chip + - interrupt controller + * - FLASH + - on-chip + - flash controller + * - PINCTRL + - on-chip + - pin controller + * - ESPI + - on-chip + - espi + * - PECI + - on-chip + - peci + * - UART + - on-chip + - serial + * - GPIO + - on-chip + - gpio + * - PWM + - on-chip + - pwm + * - ADC + - on-chip + - adc + * - TIMER + - on-chip + - timer + * - WATCHDOG + - on-chip + - watchdog + * - KSCAN + - on-chip + - kscan + * - SENSOR + - on-chip + - voltage comparator + * - I2C + - on-chip + - i2c + + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the +:zephyr_file:`boards/ite/it82xx2_evb/it82xx2_evb_defconfig` Kconfig file. + +Programming and debugging on it82202 +************************************ + +In order to upload the application to the device, +you'll need our flash tool and Download board. +You can get them at: `ITE's website`_. + +Wiring +======= +#. Connect the Download Board to your host computer using the USB cable. + +#. Connect the it82xx2_evb to the evolution motherboard. + +#. Connect the Download Board J5 to J41 on the evolution motherboard. + +#. Connect the USB to UART wire to J33 on the evolution motherboard. + + .. image:: it82xx2_evb_wiring.jpg + :align: center + :alt: it82xx2_evb wiring + + .. note:: Be careful during connection! + Use separate wires to connect I2C pins with pins on the it82xx2_evb board. + Wiring connection is described in the table below. + + +-------------+---------------+ + | J5 | it82xx2_evb | + | Connector | J41 Connector | + +=============+===============+ + | 2 | E0 | + +-------------+---------------+ + | 3 | E7 | + +-------------+---------------+ + | 4 | GND | + +-------------+---------------+ + + For USB to UART cable, connect the evolution motherboard as below: + + +-------------+---------------+ + | USB to UART | Evolution | + | cable | motherboard | + | | J33 Connector | + +=============+===============+ + | RX | B0 | + +-------------+---------------+ + | TX | B1 | + +-------------+---------------+ + | GND | GND | + +-------------+---------------+ + +Building +======== + +#. Build :ref:`hello_world` application as you would normally do + (see :`Zephyr Getting Started Guide`_):. + + .. zephyr-app-commands:: + :board: it82xx2_evb + :zephyr-app: samples/hello_world + :goals: build + +#. The file :file:`zephyr.bin` will be created by west. + +Flashing +======== + +Windows +-------- + +Use the winflash tool to program a zephyr application +to the it82xx2 board flash. + +#. Open the winflash tool and make sure the order you open the switch is right. + First, turn on the Download board switch. + Second, turn on the it82xx2_evb board switch. + Then, configure your winflash tool like below. + + .. figure:: WinFlashTool_P2.jpg + :align: center + + .. figure:: WinFlashTool_P4.jpg + +#. Using the winflash tool flash ``zephyr.bin`` into your ITE board. + First, click the ``Load`` button and select your ``zephyr.bin`` file. + Second, click ``run`` to flash the image into board. + + .. figure:: WinFlashTool_P3.jpg + :align: center + +#. At this point, you have flashed your image into ITE board and + it will work if you turn on the ITE board. You can use a terminal program + to verify flashing worked correctly. + + For example, open device manager to find the USB Serial Port(COM4) and use your + terminal program to connect it(Speed: 115200). + + .. figure:: WinFlashTool_P1.jpg + :align: center + +#. Turn on the it82xx2_evb board switch, you should see ``"Hello World! it82xx2_evb"`` + sent by the board. If you don't see this message, press the Reset button and the + message should appear. + +Ubuntu +-------- + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -b 115200 + +#. Open a second terminal window and use the Linux flash tool to flash your board. + + .. code-block:: console + + $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin + + .. note:: The source code of ITE tool can be downloaded here: + https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 + +#. Split first and second terminal windows to view both of them. + You should see ``"Hello World! it82xx2_evb"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +it82xx2_evb board can be debugged by connecting USB to UART. We can write commands and +read messages through minicom in the Ubuntu terminal. + +Troubleshooting +=============== + +#. If the flash tool reports a failure, re-plug the 8390 Download board or + power cycle the it82xx2_evb board and try again. + +References +========== + +.. target-notes:: + +.. _ITE's website: https://www.ite.com.tw/zh-tw/product/view?mid=169 +.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg b/boards/ite/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg rename to boards/ite/it82xx2_evb/doc/it82xx2_evb_and_debug_card.jpg diff --git a/boards/riscv/it82xx2_evb/doc/it82xx2_evb_wiring.jpg b/boards/ite/it82xx2_evb/doc/it82xx2_evb_wiring.jpg similarity index 100% rename from boards/riscv/it82xx2_evb/doc/it82xx2_evb_wiring.jpg rename to boards/ite/it82xx2_evb/doc/it82xx2_evb_wiring.jpg diff --git a/boards/riscv/it82xx2_evb/it82xx2_evb.dts b/boards/ite/it82xx2_evb/it82xx2_evb.dts similarity index 100% rename from boards/riscv/it82xx2_evb/it82xx2_evb.dts rename to boards/ite/it82xx2_evb/it82xx2_evb.dts diff --git a/boards/riscv/it82xx2_evb/it82xx2_evb.yaml b/boards/ite/it82xx2_evb/it82xx2_evb.yaml similarity index 100% rename from boards/riscv/it82xx2_evb/it82xx2_evb.yaml rename to boards/ite/it82xx2_evb/it82xx2_evb.yaml diff --git a/boards/riscv/it82xx2_evb/it82xx2_evb_defconfig b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig similarity index 81% rename from boards/riscv/it82xx2_evb/it82xx2_evb_defconfig rename to boards/ite/it82xx2_evb/it82xx2_evb_defconfig index 6866e3f633b948..2b174670d48368 100644 --- a/boards/riscv/it82xx2_evb/it82xx2_evb_defconfig +++ b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig @@ -1,11 +1,6 @@ # Copyright (c) 2023 ITE Corporation. All Rights Reserved. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_ITE_IT8XXX2=y -CONFIG_SOC_IT8XXX2=y -CONFIG_SOC_IT82202_AX=y -CONFIG_BOARD_IT82XX2_EVB=y - CONFIG_GEN_IRQ_VECTOR_TABLE=n # General Kernel Options diff --git a/boards/ite/it8xxx2_evb/Kconfig.defconfig b/boards/ite/it8xxx2_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..57fc0404475f49 --- /dev/null +++ b/boards/ite/it8xxx2_evb/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IT8XXX2_EVB + +if PM + +config PM_DEVICE + default y + +choice PM_POLICY + default PM_POLICY_CUSTOM +endchoice + +endif # PM + +config INPUT + default y if KSCAN + +endif # BOARD_IT8XXX2_EVB diff --git a/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb b/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb new file mode 100644 index 00000000000000..9eed36bcacdc8f --- /dev/null +++ b/boards/ite/it8xxx2_evb/Kconfig.it8xxx2_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IT8XXX2_EVB + select SOC_IT82202_AX diff --git a/boards/riscv/it8xxx2_evb/board.cmake b/boards/ite/it8xxx2_evb/board.cmake similarity index 100% rename from boards/riscv/it8xxx2_evb/board.cmake rename to boards/ite/it8xxx2_evb/board.cmake diff --git a/boards/ite/it8xxx2_evb/board.yml b/boards/ite/it8xxx2_evb/board.yml new file mode 100644 index 00000000000000..ff2f8ca7776cd8 --- /dev/null +++ b/boards/ite/it8xxx2_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: it8xxx2_evb + vendor: ite + socs: + - name: it82202ax diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P1.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P1.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P1.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P1.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P2.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P2.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P2.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P2.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P3.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P3.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P3.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P3.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/WinFlashTool_P4.jpg b/boards/ite/it8xxx2_evb/doc/WinFlashTool_P4.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/WinFlashTool_P4.jpg rename to boards/ite/it8xxx2_evb/doc/WinFlashTool_P4.jpg diff --git a/boards/ite/it8xxx2_evb/doc/index.rst b/boards/ite/it8xxx2_evb/doc/index.rst new file mode 100644 index 00000000000000..9f345639c4849f --- /dev/null +++ b/boards/ite/it8xxx2_evb/doc/index.rst @@ -0,0 +1,228 @@ +.. _it8xxx2_evb: + +ITE IT8XXX2 series +###################### + +Overview +******** + +The IT8XXX2 is a 32-bit RISC-V Micro-controller. +And a highly integrated embedded controller with system functions. +It is suitable for mobile system applications. The picture below is +the IT81302 MECC board (also known as it8xxx2_evb) and its debug card. + +.. figure:: it8xxx2_evb_and_debug_card.jpg + :align: center + :alt: IT81302 EVB + +To find out more about ITE, visit our World Wide Web at:`ITE's website`_ + +Hardware +******** +The IT8XXX2 series contains different chip types(ex, it81302, it83202), +and they support different hardware features. +Listing the IT81302 hardware features as following: + +- RISC-V RV32IMAFC instruction set +- 4KB instruction cache size +- 60KB SDRAM in total +- Built-in 32.768 kHz clock generator +- PWM, eSPI, LPC, FLASH, UART, GPIO, Timer, Watchdog, ADC, JTAG +- 6 SMBus channels, with 3 DMA controllers, compatible with I2C +- SPI master/slave +- USB Type-c CC Logic +- USB Power Delivery +- Support KB scan + + +Supported Features +================== +currently supports the following hardware features: + +.. list-table:: Supported Features + :header-rows: 1 + :widths: auto + + * - Interface + - Controller + - Driver/Component + * - NVIC + - on-chip + - interrupt controller + * - TIMER + - on-chip + - timer + * - UART + - on-chip + - serial + * - GPIO + - on-chip + - gpio + * - ADC + - on-chip + - adc + * - I2C + - on-chip + - i2c + * - KSCAN + - on-chip + - kscan + + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the +:zephyr_file:`boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig` Kconfig file. + +Hardware reworks +**************** + +Before using the it8xxx2_evb, some hardware rework is needed. The HW rework +guide can be found in ITE's website. +https://www.ite.com.tw/uploads/product_download/IT81302_MECC_Rework_Guide_0927.pdf + +Programming and debugging on it83202 +************************************ + +In order to upload the application to the device, +you'll need our flash tool and Download board. +You can get them at: `ITE's website`_. + +Wiring +======= +#. Connect the Download Board to your host computer using the USB cable. + +#. Connect the it8xxx2_evb to your host computer or a 5V1A USB power supply. + +#. Connect the Download Board J5 to J8 on the it8xxx2_evb board. + +#. Connect the USB to UART wire to it8xxx2_evb. + + .. image:: it8xxx2_evb_wiring.jpg + :align: center + :alt: it8xxx2_evb wiring + + .. note:: Be careful during connection! + Use separate wires to connect I2C pins with pins on the it8xxx2_evb board. + Wiring connection is described in the table below. + + +-------------+---------------+ + | J5 | it8xxx2_evb | + | Connector | J8 Connector | + +=============+===============+ + | 2 | 1 | + +-------------+---------------+ + | 3 | 3 | + +-------------+---------------+ + | 4 | 5 | + +-------------+---------------+ + + For USB to UART cable, connect the it8xxx2_evb as below: + + +-------------+---------------+ + | USB to UART | it8xxx2_evb | + | cable | J5 Connector | + +=============+===============+ + | RX | J5.3 | + +-------------+---------------+ + | TX | J5.4 | + +-------------+---------------+ + | GND | eSPI Debug.10 | + +-------------+---------------+ + +Building +======== + +#. Build :ref:`hello_world` application as you would normally do + (see :`Zephyr Getting Started Guide`_):. + + .. zephyr-app-commands:: + :board: it8xxx2_evb + :zephyr-app: samples/hello_world + :goals: build + +#. The file :file:`zephyr.bin` will be created by west. + +Flashing +======== + +Windows +-------- + +Use the winflash tool to program a zephyr application +to the it8xxx2 board flash. + +#. Open winflash tool and make sure the order you open the switch is right. + Fisrt, turn on the Download board switch. + Second, turn on the it8xxx2_evb board switch. + Then, configure your winflash tool like below. + + .. figure:: WinFlashTool_P2.jpg + :align: center + + .. figure:: WinFlashTool_P4.jpg + +#. Using winflash tool flash zephyr.bin into your ITE board. + First, click ``Load`` button and select your zephyr.bin file. + Second, click ``run`` to flash the iamge into board. + + .. figure:: WinFlashTool_P3.jpg + :align: center + +#. At this point, you have flashed your image into ITE board and + it will work if you turn on ITE board. You can use a terminal program + to verify flashing worked correctly. + + For example, open device manager to find the USB Serial Port(COM4) and use your + terminal program to connect it(Speed: 115200). + + .. figure:: WinFlashTool_P1.jpg + :align: center + +#. Turn on the it8xxx2_evb board switch, you should see ``"Hello World! it8xxx2_evb"`` + sent by the board. If you don't see this message, press the Reset button and the + message should appear. + +Ubuntu +-------- + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -b 115200 + +#. Open a second terminal window and use linux flash tool to flash your board. + + .. code-block:: console + + $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin + + .. note:: The source code of ITE tool can be downloaded here: + https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 + +#. Split first and second terminal windows to view both of them. + You should see ``"Hello World! it8xxx2_evb"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +Supporting uart debug, currently. + +Troubleshooting +=============== + +#. If the flash tool reports a failure, re-plug the 8390 Download board or + power cycle the it8xxx2_evb board and try again. + +References +========== + +.. target-notes:: + +.. _ITE's website: http://www.ite.com.tw/en/product/view?mid=149 +.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg b/boards/ite/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg rename to boards/ite/it8xxx2_evb/doc/it8xxx2_evb_and_debug_card.jpg diff --git a/boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg b/boards/ite/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg similarity index 100% rename from boards/riscv/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg rename to boards/ite/it8xxx2_evb/doc/it8xxx2_evb_wiring.jpg diff --git a/boards/riscv/it8xxx2_evb/it8xxx2_evb.dts b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts similarity index 100% rename from boards/riscv/it8xxx2_evb/it8xxx2_evb.dts rename to boards/ite/it8xxx2_evb/it8xxx2_evb.dts diff --git a/boards/riscv/it8xxx2_evb/it8xxx2_evb.yaml b/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml similarity index 100% rename from boards/riscv/it8xxx2_evb/it8xxx2_evb.yaml rename to boards/ite/it8xxx2_evb/it8xxx2_evb.yaml diff --git a/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig b/boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig similarity index 83% rename from boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig rename to boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig index 38a44d6f8f3d35..a73b3068d1eba2 100644 --- a/boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig +++ b/boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2020 ITE Corporation. All Rights Reserved. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_ITE_IT8XXX2=y -CONFIG_SOC_IT8XXX2=y -CONFIG_BOARD_IT8XXX2_EVB=y CONFIG_BOOT_DELAY=1 CONFIG_GEN_IRQ_VECTOR_TABLE=n diff --git a/boards/riscv/it8xxx2_evb/support/it8xxx2_evb.resc b/boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc similarity index 100% rename from boards/riscv/it8xxx2_evb/support/it8xxx2_evb.resc rename to boards/ite/it8xxx2_evb/support/it8xxx2_evb.resc diff --git a/boards/arm/frdm_k82f/CMakeLists.txt b/boards/khadas/edgev/CMakeLists.txt similarity index 100% rename from boards/arm/frdm_k82f/CMakeLists.txt rename to boards/khadas/edgev/CMakeLists.txt diff --git a/boards/khadas/edgev/Kconfig.khadas_edgev b/boards/khadas/edgev/Kconfig.khadas_edgev new file mode 100644 index 00000000000000..324629cbc7f865 --- /dev/null +++ b/boards/khadas/edgev/Kconfig.khadas_edgev @@ -0,0 +1,7 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_KHADAS_EDGEV + select SOC_RK3399 diff --git a/boards/arm64/khadas_edgev/board.cmake b/boards/khadas/edgev/board.cmake similarity index 100% rename from boards/arm64/khadas_edgev/board.cmake rename to boards/khadas/edgev/board.cmake diff --git a/boards/khadas/edgev/board.yml b/boards/khadas/edgev/board.yml new file mode 100644 index 00000000000000..fc70dcf0a44da0 --- /dev/null +++ b/boards/khadas/edgev/board.yml @@ -0,0 +1,5 @@ +board: + name: khadas_edgev + vendor: khadas + socs: + - name: rk3399 diff --git a/boards/khadas/edgev/doc/index.rst b/boards/khadas/edgev/doc/index.rst new file mode 100644 index 00000000000000..2c73d109b09cae --- /dev/null +++ b/boards/khadas/edgev/doc/index.rst @@ -0,0 +1,84 @@ +.. _khadas_edgev: + +Khadas Edge-V +################################# + +Overview +******** + +See + +Hardware +******** + +See + +Supported Features +================== + +Khadas Edge-V board default configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-500 | on-chip | GICv3 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | Synopsys DesignWare 8250 serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in (NON-SMP) +:zephyr_file:`boards/khadas/edgev/khadas_edgev_defconfig` + +There are multiple serial ports on the board: Zephyr is using +uart2 as serial console. + +Programming and Debugging +************************* + +Use the following configuration to run basic Zephyr applications and +kernel tests on Khadas Edge-V board. For example, with the :ref:`hello_world`: + +1. Non-SMP mode + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :host-os: unix + :board: khadas_edgev + :goals: build + +This will build an image with the synchronization sample app. + +Build the zephyr image: + +.. code-block:: console + + mkimage -C none -A arm64 -O linux -a 0x10000000 -e 0x10000000 -d build/zephyr/zephyr.bin build/zephyr/zephyr.img + +Use u-boot to load and kick Zephyr.bin to CPU Core0: + +.. code-block:: console + + tftpboot ${pxefile_addr_r} zephyr.img; bootm start ${pxefile_addr_r}; bootm loados; bootm go + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build XXXXXXXXXXXX *** + Hello World! khadas_edgev + +Flashing +======== + +Zephyr image can be loaded in DDR memory at address 0x10000000 from SD Card, +EMMC, QSPI Flash or downloaded from network in uboot. + +References +========== + +`Documentation: `_ diff --git a/boards/arm64/khadas_edgev/khadas_edgev.dts b/boards/khadas/edgev/khadas_edgev.dts similarity index 100% rename from boards/arm64/khadas_edgev/khadas_edgev.dts rename to boards/khadas/edgev/khadas_edgev.dts diff --git a/boards/arm64/khadas_edgev/khadas_edgev.yaml b/boards/khadas/edgev/khadas_edgev.yaml similarity index 100% rename from boards/arm64/khadas_edgev/khadas_edgev.yaml rename to boards/khadas/edgev/khadas_edgev.yaml diff --git a/boards/arm64/khadas_edgev/khadas_edgev_defconfig b/boards/khadas/edgev/khadas_edgev_defconfig similarity index 81% rename from boards/arm64/khadas_edgev/khadas_edgev_defconfig rename to boards/khadas/edgev/khadas_edgev_defconfig index 6573521640f63b..44e7ed446c4f0d 100644 --- a/boards/arm64/khadas_edgev/khadas_edgev_defconfig +++ b/boards/khadas/edgev/khadas_edgev_defconfig @@ -1,9 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # Platform Configuration -CONFIG_SOC_SERIES_RK3399=y -CONFIG_SOC_RK3399=y -CONFIG_BOARD_KHADAS_EDGEV=y CONFIG_ARM64_VA_BITS_40=y CONFIG_ARM64_PA_BITS_40=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000 diff --git a/boards/khadas/index.rst b/boards/khadas/index.rst new file mode 100644 index 00000000000000..357dfc3543c239 --- /dev/null +++ b/boards/khadas/index.rst @@ -0,0 +1,10 @@ +.. _boards-khadas: + +Khadas +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/kincony/index.rst b/boards/kincony/index.rst new file mode 100644 index 00000000000000..afa86ed08958ed --- /dev/null +++ b/boards/kincony/index.rst @@ -0,0 +1,10 @@ +.. _boards-kincony: + +Kincony +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/kincony/kincony_kc868_a32/Kconfig b/boards/kincony/kincony_kc868_a32/Kconfig new file mode 100644 index 00000000000000..446d0a838bd59c --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KINCONY_KC868_A32 + select SOC_ESP32_PROCPU if BOARD_KINCONY_KC868_A32_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_KINCONY_KC868_A32_ESP32_APPCPU diff --git a/boards/kincony/kincony_kc868_a32/Kconfig.defconfig b/boards/kincony/kincony_kc868_a32/Kconfig.defconfig new file mode 100644 index 00000000000000..e8705a11f98507 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Bartosz Bilas +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_KINCONY_KC868_A32_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_KINCONY_KC868_A32_ESP32_PROCPU + +if BOARD_KINCONY_KC868_A32_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_KINCONY_KC868_A32_ESP32_APPCPU diff --git a/boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 b/boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 new file mode 100644 index 00000000000000..ad38ee9ab7644c --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/Kconfig.kincony_kc868_a32 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Bartosz Bilas +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_KINCONY_KC868_A32 + select SOC_ESP32_WROOM_32UE_N4 diff --git a/boards/xtensa/kincony_kc868_a32/Kconfig.sysbuild b/boards/kincony/kincony_kc868_a32/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/kincony_kc868_a32/Kconfig.sysbuild rename to boards/kincony/kincony_kc868_a32/Kconfig.sysbuild diff --git a/boards/xtensa/kincony_kc868_a32/board.cmake b/boards/kincony/kincony_kc868_a32/board.cmake similarity index 100% rename from boards/xtensa/kincony_kc868_a32/board.cmake rename to boards/kincony/kincony_kc868_a32/board.cmake diff --git a/boards/kincony/kincony_kc868_a32/board.yml b/boards/kincony/kincony_kc868_a32/board.yml new file mode 100644 index 00000000000000..99bf4fa715b71f --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/board.yml @@ -0,0 +1,5 @@ +board: + name: kincony_kc868_a32 + vendor: kincony + socs: + - name: esp32 diff --git a/boards/xtensa/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg b/boards/kincony/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg similarity index 100% rename from boards/xtensa/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg rename to boards/kincony/kincony_kc868_a32/doc/img/kincony_kc868_a32.jpg diff --git a/boards/kincony/kincony_kc868_a32/doc/index.rst b/boards/kincony/kincony_kc868_a32/doc/index.rst new file mode 100644 index 00000000000000..a6117bec55e9f1 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/doc/index.rst @@ -0,0 +1,97 @@ +.. _kincony_kc868_a32: + +KINCONY KC868-A32 +################# + +Overview +******** + +Kincony KC868-A32 is a home automation relay module based on the +Espressif ESP-WROOM-32 module with all its inherent capabilities +(Wi-Fi, Bluetooth, etc.) + +The features include the following: + +- 32 digital optoisolated inputs “dry contact” +- 4 analog inputs 0-5 V +- 32 relays 220 V, 10 A (COM, NO, NC) +- RS485 interface +- I2C connector +- Connector GSM/HMI +- Ethernet LAN8270A +- USB Type-B connector for programming and filling firmware +- RESET and DOWNLOAD buttons +- Powered by 12V DC + +.. figure:: img/kincony_kc868_a32.jpg + :align: center + :alt: KINCONCY-KC868-A32 + + KINCONCY-KC868-A32 + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: kincony_kc868_a32/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``kincony_kc868_a32`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: kincony_kc868_a32/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! kincony_kc868_a32 + +Enabling Ethernet +***************** + +Enable Ethernet in KConfig: + +.. code-block:: cfg + + CONFIG_NETWORKING=y + CONFIG_NET_L2_ETHERNET=y + CONFIG_MDIO=y + +References +********** + +.. _KINCONY KC868-A32 User Guide: https://www.kincony.com/arduino-esp32-32-channel-relay-module-kc868-a32.html diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi similarity index 100% rename from boards/xtensa/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi rename to boards/kincony/kincony_kc868_a32/kincony_kc868_a32-pinctrl.dtsi diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.dts new file mode 100644 index 00000000000000..7940256ff2969b --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Kincony KC868_A32 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.yaml b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.yaml new file mode 100644 index 00000000000000..af75ec0edbcf86 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: kincony_kc868_a32/esp32/appcpu +name: ESP32 DEVKITC WROVER APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.dts b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.dts new file mode 100644 index 00000000000000..0f459d7f7c5c53 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.dts @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2023 Bartosz Bilas + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "kincony_kc868_a32-pinctrl.dtsi" + +/ { + model = "Kincony KC868_A32 PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&cpu0 { + clock-frequency = ; + cpu-power-states = <&light_sleep &deep_sleep>; +}; + +&cpu1 { + clock-frequency = ; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 13 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + i2c0_pcf8574@21 { + compatible = "nxp,pcf857x"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c0_pcf8574@22 { + compatible = "nxp,pcf857x"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c0_pcf8574@24 { + compatible = "nxp,pcf857x"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c0_pcf8574@25 { + compatible = "nxp,pcf857x"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 5 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + + i2c1_pcf8574@21 { + compatible = "nxp,pcf857x"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c1_pcf8574@22 { + compatible = "nxp,pcf857x"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c1_pcf8574@24 { + compatible = "nxp,pcf857x"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + + i2c1_pcf8574@25 { + compatible = "nxp,pcf857x"; + reg = <0x25>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; +}; + +&mdio { + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy: ethernet-phy@0 { + compatible = "ethernet-phy"; + status = "okay"; + reg = <0>; + }; +}; + +ð { + status = "okay"; + phy-handle = <&phy>; + ref-clk-output-gpios = <&gpio0 17 0>; +}; + +&psram0 { + status = "disabled"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.yaml b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.yaml new file mode 100644 index 00000000000000..51ac12191f6dd4 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu.yaml @@ -0,0 +1,19 @@ +identifier: kincony_kc868_a32/esp32/procpu +name: KINCONY-KC868-A32 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - watchdog + - uart + - nvs + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: kincony diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu_defconfig b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu_defconfig new file mode 100644 index 00000000000000..071024ac98dba0 --- /dev/null +++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_esp32_procpu_defconfig @@ -0,0 +1,11 @@ +# Copyright (c) Bartosz Bilas +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/xtensa/kincony_kc868_a32/support/openocd.cfg b/boards/kincony/kincony_kc868_a32/support/openocd.cfg similarity index 100% rename from boards/xtensa/kincony_kc868_a32/support/openocd.cfg rename to boards/kincony/kincony_kc868_a32/support/openocd.cfg diff --git a/boards/lairdconnect/bl5340_dvk/CMakeLists.txt b/boards/lairdconnect/bl5340_dvk/CMakeLists.txt new file mode 100644 index 00000000000000..ab8867f56a4c29 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA. +# Copyright (c) 2021-2023 Laird Connectivity. +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(bl5340_dvk_cpunet_reset.c) + + if(CONFIG_BUILD_WITH_TFM) + zephyr_library_include_directories( + $/api_ns/interface/include + ) + endif() +endif() diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig b/boards/lairdconnect/bl5340_dvk/Kconfig new file mode 100644 index 00000000000000..da61ea66547dde --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/Kconfig @@ -0,0 +1,62 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2021 Nordic Semiconductor ASA +# Copyright (c) 2021-2023 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "bl5340_dvk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the bl5340_dvk_cpunet for + Bluetooth applications. + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +if BOARD_BL5340_DVK_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "bl5340_dvk/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk b/boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk new file mode 100644 index 00000000000000..7451d37b908ca6 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/Kconfig.bl5340_dvk @@ -0,0 +1,9 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL5340_DVK + select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig b/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig new file mode 100644 index 00000000000000..65c005ee286054 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/Kconfig.defconfig @@ -0,0 +1,119 @@ +# BL5340-DVK board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# Copyright (c) 2021-2023 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config I2C + default GPIO || DAC + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +config BT_HCI_VS + default y if BT + +# 2.8" TFT Touch Shield for Arduino w/Capacitive Touch Screen Module +# is mounted to the DVK using standoffs. +# https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module +if DISPLAY + +config INPUT_FT5336_INTERRUPT + default y + +if LVGL + +config LV_Z_VDB_SIZE + default 64 + +config LV_Z_BITS_PER_PIXEL + default 16 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +config LV_COLOR_16_SWAP + default y + +config INPUT + default y + +endif # LVGL + +endif # DISPLAY + +endif # BOARD_BL5340_DVK_NRF5340_CPUAPP || BOARD_BL5340_DVK_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_BL5340_DVK_NRF5340_CPUNET + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT + +config BT_ECC + default y if BT + +endif # BOARD_BL5340_DVK_NRF5340_CPUNET diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts new file mode 100644 index 00000000000000..7640e86e4aad15 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.dts @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Laird Connectivity BL5340 (nRF5340) Application"; + compatible = "lairdconnect,bl5340-dvk-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + zephyr,sram-non-secure-partition = &sram0_ns; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000000..1b23d5f23ecb60 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml @@ -0,0 +1,22 @@ +identifier: bl5340_dvk/nrf5340/cpuapp +name: BL5340-DVK-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - counter + - gpio + - i2c + - pwm + - qspi + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: lairdconnect diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common-pinctrl.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_cpuapp_common-pinctrl.dtsi rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi new file mode 100644 index 00000000000000..ff29e1f176ea2e --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_common.dtsi @@ -0,0 +1,381 @@ +/* + * Copyright (c) 2019-2023 Nordic Semiconductor ASA + * Copyright (c) 2021-2023 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bl5340_dvk_nrf5340_cpuapp_common-pinctrl.dtsi" +#include + +/ { + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,display = &ili9340; + zephyr,bt-hci-ipc = &ipc0; + }; + + /* Main LEDs and buttons are on an I2C TCA9538 GPIO port expander */ + /* Note TCA9538 does not have configurable internal pull ups/ downs */ + buttons { + compatible = "gpio-keys"; + boot_button0: boot_button { + gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + label = "Bootloader button (S4)"; + zephyr,code = ; + }; + + button1: button_1 { + gpios = <&gpio_exp0 0 GPIO_ACTIVE_LOW>; + label = "Push button switch 1 (S1)"; + zephyr,code = ; + }; + + button2: button_2 { + gpios = <&gpio_exp0 1 GPIO_ACTIVE_LOW>; + label = "Push button switch 2 (S2)"; + zephyr,code = ; + }; + + button3: button_3 { + gpios = <&gpio_exp0 2 GPIO_ACTIVE_LOW>; + label = "Push button switch 3 (S9)"; + zephyr,code = ; + }; + + button4: button_4 { + gpios = <&gpio_exp0 3 GPIO_ACTIVE_LOW>; + label = "Push button switch 4 (S10)"; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + led1: led_1 { + gpios = <&gpio_exp0 4 GPIO_ACTIVE_LOW>; + label = "Blue LED 1"; + }; + led2: led_2 { + gpios = <&gpio_exp0 5 GPIO_ACTIVE_LOW>; + label = "Blue LED 2"; + }; + led3: led_3 { + gpios = <&gpio_exp0 6 GPIO_ACTIVE_LOW>; + label = "Blue LED 3"; + }; + led4: led_4 { + gpios = <&gpio_exp0 7 GPIO_ACTIVE_LOW>; + label = "Blue LED 4"; + }; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336>; + swap-xy; + invert-x; + invert-y; + }; + + gpio_fwd: nrf-gpio-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + status = "okay"; + uart { + gpios = <&gpio1 8 0>, <&gpio1 10 0>, <&gpio1 7 0>, <&gpio1 9 0>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led1; + led1 = &led2; + led2 = &led3; + led3 = &led4; + sw0 = &button1; + sw1 = &button2; + sw2 = &button3; + sw3 = &button4; + mcuboot-button0 = &button1; + mcuboot-led0 = &led1; + sdhc0 = &sdhc0; + watchdog0 = &wdt0; + accel0 = &lis3dh; + bbram0 = &extrtc0; + spi-flash0 = &mx25r64; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + spi-dev = <&spi2>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9340: ili9340@0 { + compatible = "ilitek,ili9340"; + reg = <0>; + mipi-max-frequency = <32000000>; + rotation = <270>; + width = <320>; + height = <240>; + }; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; + at24c256@50 { + compatible = "atmel,at24"; + reg = <0x50>; + size = <32768>; + pagesize = <64>; + address-width = <16>; + timeout = <10>; + }; + + lis3dh: lis3dh@18 { + compatible = "st,lis2dh"; + reg = <0x18>; + irq-gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>, <&gpio0 24 GPIO_ACTIVE_HIGH>; + }; + + ft5336: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + }; + + bme680@76 { + compatible = "bosch,bme680"; + reg = <0x76>; + }; + + dac0: mcp4725@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + #io-channel-cells = <1>; + }; + + extrtc0: mcp7940n@6f { + compatible = "microchip,mcp7940n"; + reg = <0x6f>; + status = "okay"; + }; + + gpio_exp0: tca9538@70 { + compatible = "ti,tca9538"; + reg = <0x70>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + nint-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; +}; + +&spi2 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; + enc424j600@0 { + compatible = "microchip,enc424j600"; + reg = <0>; + spi-max-frequency = <8000000>; + int-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; + }; +}; + +&spi3 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; + sdhc0: sdhc@0 { + reg = <0>; + compatible = "zephyr,sdhc-spi-slot"; + status = "okay"; + spi-max-frequency = <8000000>; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + }; +}; + +&spi4 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { + compatible = "nordic,qspi-nor"; + reg = <0>; + /* MX25R64 supports only pp and pp4io */ + writeoc = "pp4io"; + /* MX25R64 supports all readoc options */ + readoc = "read4io"; + sck-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 64K */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + }; + /* 640K */ + slot0_partition: partition@10000 { + label = "image-0"; + }; + /* 256K */ + slot0_ns_partition: partition@b0000 { + label = "image-0-nonsecure"; + }; + + /* + * The flash starting at 0x000f8000 and ending at + * 0x000fffff is reserved for use by the application. + */ + + /* + * Storage partition will be used by FCB/NVS + * if enabled. 32K + */ + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +&mx25r64 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 640K */ + slot1_partition: partition@0 { + label = "image-1"; + }; + /* 256K */ + slot1_ns_partition: partition@A0000 { + label = "image-1-nonsecure"; + }; + /* 128K */ + scratch_partition: partition@e0000 { + label = "image-scratch"; + reg = <0x000e0000 0x00020000>; + }; + /* 7MB */ + lfs_partition: partition@100000 { + label = "lfs_storage"; + reg = <0x00100000 0x00700000>; + }; + }; +}; + +/ { + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_image: image@20000000 { + /* Zephyr image(s) memory */ + }; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + }; + + sram0_ns: image_ns@20040000 { + /* Non-Secure image memory */ + }; + }; +}; + +/* Include partition configuration file */ +#include "bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi" diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..b60faf810bbeec --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Setup clocks +CONFIG_CLOCK_CONTROL_NRF_K32SRC_250PPM=y +CONFIG_SOC_LFXO_CAP_INT_7PF=y +CONFIG_SOC_HFXO_CAP_INTERNAL=y +CONFIG_SOC_HFXO_CAP_INT_VALUE_X2=27 diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts new file mode 100644 index 00000000000000..d159b8c4afe1b7 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340_dvk_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Laird Connectivity BL5340 (nRF5340) Application"; + compatible = "lairdconnect,bl5340-dvk-cpuapp"; + + chosen { + zephyr,sram = &sram0_ns; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_ns_partition; + }; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml new file mode 100644 index 00000000000000..087975c8d0da70 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml @@ -0,0 +1,21 @@ +identifier: bl5340_dvk/nrf5340/cpuapp/ns +name: BL5340-DVK-application-MCU-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 192 +flash: 192 +supported: + - counter + - gpio + - i2c + - pwm + - spi + - uart + - usb_cdc + - usb_device + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000000..2a74dd56f4144a --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi new file mode 100644 index 00000000000000..b85e3d03dc2d73 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_partition_conf.dtsi @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2019-2020 Nordic Semiconductor ASA + * Copyright (c) 2021 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Default Flash planning for bl5340_dvk CPUAPP (Application MCU). + * + * Zephyr build for BL5340 with ARM TrustZone-M support + * implies building Secure and Non-Secure Zephyr images. + * + * Secure image will be placed, by default, in flash0 + * (or in slot0, if MCUboot is present). + * Secure image will use sram0 for system memory. + * + * Non-Secure image will be placed in slot0_ns, and use + * sram0_ns for system memory. + * + * Note that the Secure image only requires knowledge of + * the beginning of the Non-Secure image (not its size). + */ + +&slot0_partition { + reg = <0x00010000 0xa0000>; +}; + +&slot0_ns_partition { + reg = <0x000b0000 0x40000>; +}; + +&slot1_partition { + reg = <0x00000000 0xa0000>; +}; + +&slot1_ns_partition { + reg = <0x000a0000 0x40000>; +}; + +/* Default SRAM planning when building for nRF5340 with + * ARM TrustZone-M support + * - Lowest 256 kB SRAM allocated to Secure image (sram0_s) + * - Middle 192 kB allocated to Non-Secure image (sram0_ns) + * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) + * (see bl5340_dvk_shared_sram_planning_conf.dtsi) + */ +&sram0_image { + reg = <0x20000000 DT_SIZE_K(448)>; +}; + +&sram0_s { + reg = <0x20000000 0x40000>; +}; + +&sram0_ns { + reg = <0x20040000 0x30000>; +}; + +/* Include shared RAM configuration file */ +#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet-pinctrl.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_cpunet-pinctrl.dtsi rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts new file mode 100644 index 00000000000000..4df761d04879ae --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.dts @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021-2023 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "bl5340_dvk_nrf5340_cpunet-pinctrl.dtsi" +#include "bl5340_dvk_nrf5340_cpunet_common.dtsi" + +/ { + model = "Laird Connectivity BL5340 (nRF5340) Network"; + compatible = "lairdconnect,bl5340-dvk-cpunet"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + zephyr,bt-hci-ipc = &ipc0; + }; + + aliases { + watchdog0 = &wdt0; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml new file mode 100644 index 00000000000000..d9727296714594 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml @@ -0,0 +1,18 @@ +identifier: bl5340_dvk/nrf5340/cpunet +name: BL5340-DVK-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - counter + - gpio + - i2c + - spi + - uart + - watchdog +vendor: lairdconnect diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi new file mode 100644 index 00000000000000..ce2e145d58753c --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_common.dtsi @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2021-2023 Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&flash1 { + /* + * For more information, see: + * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* 48K */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + /* 88K */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x16000>; + }; + /* 88K */ + slot1_partition: partition@22000 { + label = "image-1"; + reg = <0x00022000 0x16000>; + }; + /* 32K */ + storage_partition: partition@38000 { + label = "storage"; + reg = <0x00038000 0x8000>; + }; + }; +}; + +/* Include shared RAM configuration file */ +#include "bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..56940c43a096e0 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_cpunet_reset.c b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_cpunet_reset.c rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_cpunet_reset.c diff --git a/boards/arm/frdm_kl25z/CMakeLists.txt b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig similarity index 100% rename from boards/arm/frdm_kl25z/CMakeLists.txt rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_defconfig diff --git a/boards/arm/bl5340_dvk/bl5340_dvk_shared_sram_planning_conf.dtsi b/boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/bl5340_dvk/bl5340_dvk_shared_sram_planning_conf.dtsi rename to boards/lairdconnect/bl5340_dvk/bl5340_dvk_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/lairdconnect/bl5340_dvk/board.cmake b/boards/lairdconnect/bl5340_dvk/board.cmake new file mode 100644 index 00000000000000..15aec8e6a36dfa --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/board.cmake @@ -0,0 +1,21 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP OR CONFIG_BOARD_BL5340_DVK_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(BOARD_BL5340_DVK_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/lairdconnect/bl5340_dvk/board.yml b/boards/lairdconnect/bl5340_dvk/board.yml new file mode 100644 index 00000000000000..71343692f4cb13 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/board.yml @@ -0,0 +1,8 @@ +board: + name: bl5340_dvk + vendor: lairdconnect + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/bl5340_dvk/doc/img/bl5340_dvk_top.jpg b/boards/lairdconnect/bl5340_dvk/doc/img/bl5340_dvk_top.jpg similarity index 100% rename from boards/arm/bl5340_dvk/doc/img/bl5340_dvk_top.jpg rename to boards/lairdconnect/bl5340_dvk/doc/img/bl5340_dvk_top.jpg diff --git a/boards/lairdconnect/bl5340_dvk/doc/index.rst b/boards/lairdconnect/bl5340_dvk/doc/index.rst new file mode 100644 index 00000000000000..4148b639a6d3a6 --- /dev/null +++ b/boards/lairdconnect/bl5340_dvk/doc/index.rst @@ -0,0 +1,436 @@ +.. _bl5340_dvk: + +Laird Connectivity BL5340 DVK +############################# + +Overview +******** +The BL5340 Development Kit provides support for the Laird Connectivity +BL5340 module which is powered by a dual-core Nordic Semiconductor +nRF5340 ARM Cortex-M33F CPU. The nRF5340 inside the BL5340 module is a +dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running + at a fixed 64 MHz, referred to as the **network core**. + +The ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the application +core on the BL5340 module. The ``bl5340_dvk/nrf5340/cpunet`` build target provides +support for the network core on the BL5340 module. If ARM TrustZone is +used then the ``bl5340_dvk/nrf5340/cpuapp`` build target provides support for the +non-secure partition of the application core on the BL5340 module. + +This development kit has the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`I2S (Inter-Integrated Sound)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/bl5340_dvk_top.jpg + :align: center + :alt: BL5340 DVK + + BL5340 DVK (Credit: Laird Connectivity) + +More information about the module can be found on the +`BL5340 homepage`_. + +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +Hardware +******** + +The BL5340 DVK has two external oscillators. The frequency of +the slow clock is 32.768KHz. The frequency of the main clock +is 32MHz. + +Supported Features +================== + +The ``bl5340_dvk/nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``bl5340_dvk/nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ +for a complete list of hardware features. + +Connections and IOs +=================== + +An eight-pin GPIO port expander is used to provide additional inputs +and outputs to the BL5340 module. + +Refer to the `TI TCA9538 datasheet`_ for further details. + +LEDs +---- + +* LED1 (blue) = via TCA9538 port expander channel P4 (active low) +* LED2 (blue) = via TCA9538 port expander channel P5 (active low) +* LED3 (blue) = via TCA9538 port expander channel P6 (active low) +* LED4 (blue) = via TCA9538 port expander channel P7 (active low) + +Push buttons +------------ + +* BUTTON1 = SW1 = via TCA9538 port expander channel P0 (active low) +* BUTTON2 = SW2 = via TCA9538 port expander channel P1 (active low) +* BUTTON3 = SW3 = via TCA9538 port expander channel P2 (active low) +* BUTTON4 = SW4 = via TCA9538 port expander channel P3 (active low) +* BOOT = boot (active low) + +External Memory +=============== + +Several external memory sources are available for the BL5340 DVK. These +are described as follows. + +Flash Memory +------------ + +A Macronix MX25R6435FZNIL0 8MB external QSPI Flash memory part is +incorporated for application image storage and large datasets. + +Refer to the `Macronix MX25R6435FZNIL0 datasheet`_ for further details. + +EEPROM Memory +------------- + +A 32KB Giantec GT24C256C-2GLI-TR EEPROM is available via I2C for +storage of infrequently updated data and small datasets. + +Refer to the `Giantec GT24C256C-2GLI-TR datasheet`_ for further details. + +External Memory +--------------- + +An on-board micro SD card slot is available for use with micro SD cards. + +Sensors +======= + +The BL5340 DVK incorporates two sensors for user application testing. +These are described as follows. + +Temperature, Pressure, Humidity & Air Quality Sensor +---------------------------------------------------- + +A Bosch BME680 Temperature, Pressure, Humidity & Air Quality sensor is +available via I2C for environmental measurement applications. + +Refer to the `Bosch BME680 datasheet`_ for further details. + +3-Axis Accelerometer +-------------------- + +An ST Microelectronics LIS3DH 3-Axis Accelerometer is available via I2C +for vibration and motion detection applications. + +Refer to the `ST Microelectronics LIS3DH datasheet`_ for further details. + +Ethernet +======== + +Cabled 10/100 Base-T Ethernet Connectivity is available via a Microchip +ENC424J600 Ethernet controller. + +Refer to the `Microchip ENC424J600 datasheet`_ for further details. + +TFT Display & Capacitive Touch Screen Controller +================================================ + +A 2.8 inch, 240 x 320 pixel TFT display with capacitive touch +controller is included with the BL5340 DVK for user interface +application features. + +Refer to the `ER_TFTM028_4 datasheet`_ for a high level overview of the +display. + +An ILI9341 TFT controller is incorporated in the TFT module and +acts as the main controller, controlled via SPI. + +Refer to the `ILI9341 datasheet`_ for further details. + +An FT6206 Capacitive Touch Controller, controlled via I2C is +also incorporated in the TFT module. + +Refer to the `FT6206 datasheet`_ for further details. + +Real-Time Clock +=============== + +A real-time clock is available for accurate time data availability. + +Refer to the `Microchip MCP7940N datasheet`_ for further details. + +DAC +=== + +A 10-bit Digital to Analog Converter is incorporated for generation of +variable voltages. + +Refer to the `Microchip MCP4725 datasheet`_ for further details. + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application + core. The IDAU is implemented with the System Protection Unit and is + used to define secure and non-secure memory maps. By default, all of + the memory space (Flash, SRAM, and peripheral address space) is + defined to be secure accessible only. +- Secure boot. + +Programming and Debugging +************************* + +The BL5340's application core supports the Armv8-M Security Extension. +Applications built for the ``bl5340_dvk/nrf5340/cpuapp`` board by default +boot in the Secure state. + +The BL5340's network core does not support the Armv8-M Security +Extension. The IDAU may configure bus accesses by the network core to +have Secure attribute set; the latter allows to build and run Secure +only applications on the BL5340 module. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the BL5340 module may contain a Secure and a Non-Secure +firmware image for the application core. The Secure image can be built +using either Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure +firmware images are always built using Zephyr. The two alternatives are +described below. + +.. note:: + + By default the Secure image for BL5340's application core is + built using TF-M. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the +Non-Secure firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may + be required, to adjust the Non-Secure image Flash and SRAM starting + address and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=bl5340_dvk/nrf5340/cpunet``. + +When building a Secure/Non-Secure application for the BL5340's +application core, the Secure application will have to set the IDAU +(SPU) configuration to allow Non-Secure access to all CPU resources +utilized by the Non-Secure application firmware. SPU configuration +shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=bl5340_dvk/nrf5340/cpuapp`` for +the firmware running on the BL5340's application core, and using +``-DBOARD=bl5340_dvk/nrf5340/cpunet`` for the firmware running +on the BL5340's network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The BL5340 has a flash read-back protection feature. When flash + read-back protection is active, you will need to recover the chip + before reflashing. If you are flashing with + :ref:`west `, run this command for more + details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the BL5340 DVK requires + upgrading the nRF Command Line Tools to version 10.12.0 or newer. + Further information on how to install the nRF Command Line Tools can + be found in :ref:`nordic_segger_flashing`. + +Here is an example for the :ref:`hello_world` application running on the +BL5340's application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BL5340 DVK board +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: bl5340_dvk/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +boards with a Segger IC. + +Testing Bluetooth on the BL5340 DVK +*********************************** +Many of the Bluetooth examples will work on the BL5340 DVK. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _BL5340 homepage: https://www.lairdconnect.com/wireless-modules/bluetooth-modules/bluetooth-5-modules/bl5340-series-multi-core-bluetooth-52-802154-nfc-modules +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _TI TCA9538 datasheet: https://www.ti.com/lit/gpn/TCA9538 +.. _Macronix MX25R6435FZNIL0 datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf +.. _Giantec GT24C256C-2GLI-TR datasheet: https://www.giantec-semi.com/juchen1123/uploads/pdf/GT24C256C_DS_Cu.pdf +.. _Bosch BME680 datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bme680-ds001.pdf +.. _ST Microelectronics LIS3DH datasheet: https://www.st.com/resource/en/datasheet/lis3dh.pdf +.. _Microchip ENC424J600 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/39935c.pdf +.. _ER_TFTM028_4 datasheet: https://www.buydisplay.com/download/manual/ER-TFTM028-4_Datasheet.pdf +.. _ILI9341 datasheet: https://www.buydisplay.com/download/ic/ILI9341.pdf +.. _FT6206 datasheet: https://www.buydisplay.com/download/ic/FT6206.pdf +.. _Microchip MCP7940N datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/20005010H.pdf +.. _Microchip MCP4725 datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22039d.pdf +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/bl5340_dvk/pre_dt_board.cmake b/boards/lairdconnect/bl5340_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bl5340_dvk/pre_dt_board.cmake rename to boards/lairdconnect/bl5340_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl652_dvk/Kconfig b/boards/lairdconnect/bl652_dvk/Kconfig similarity index 100% rename from boards/arm/bl652_dvk/Kconfig rename to boards/lairdconnect/bl652_dvk/Kconfig diff --git a/boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk b/boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk new file mode 100644 index 00000000000000..0a6881d76fdb11 --- /dev/null +++ b/boards/lairdconnect/bl652_dvk/Kconfig.bl652_dvk @@ -0,0 +1,7 @@ +# BL652 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL652_DVK + select SOC_NRF52832_QFAA diff --git a/boards/lairdconnect/bl652_dvk/Kconfig.defconfig b/boards/lairdconnect/bl652_dvk/Kconfig.defconfig new file mode 100644 index 00000000000000..62fac3e6c21d51 --- /dev/null +++ b/boards/lairdconnect/bl652_dvk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# BL652 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL652_DVK + +config BT_CTLR + default BT + +if DAC + +config I2C + default y + +endif # DAC + +endif # BOARD_BL652_DVK diff --git a/boards/arm/bl652_dvk/bl652_dvk-pinctrl.dtsi b/boards/lairdconnect/bl652_dvk/bl652_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/bl652_dvk/bl652_dvk-pinctrl.dtsi rename to boards/lairdconnect/bl652_dvk/bl652_dvk-pinctrl.dtsi diff --git a/boards/arm/bl652_dvk/bl652_dvk.dts b/boards/lairdconnect/bl652_dvk/bl652_dvk.dts similarity index 100% rename from boards/arm/bl652_dvk/bl652_dvk.dts rename to boards/lairdconnect/bl652_dvk/bl652_dvk.dts diff --git a/boards/arm/bl652_dvk/bl652_dvk.yaml b/boards/lairdconnect/bl652_dvk/bl652_dvk.yaml similarity index 100% rename from boards/arm/bl652_dvk/bl652_dvk.yaml rename to boards/lairdconnect/bl652_dvk/bl652_dvk.yaml diff --git a/boards/arm/bl652_dvk/bl652_dvk_defconfig b/boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig similarity index 81% rename from boards/arm/bl652_dvk/bl652_dvk_defconfig rename to boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig index def931d42fcb09..a108273c64ce58 100644 --- a/boards/arm/bl652_dvk/bl652_dvk_defconfig +++ b/boards/lairdconnect/bl652_dvk/bl652_dvk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_BL652_DVK=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl652_dvk/board.cmake b/boards/lairdconnect/bl652_dvk/board.cmake similarity index 100% rename from boards/arm/bl652_dvk/board.cmake rename to boards/lairdconnect/bl652_dvk/board.cmake diff --git a/boards/lairdconnect/bl652_dvk/board.yml b/boards/lairdconnect/bl652_dvk/board.yml new file mode 100644 index 00000000000000..2c2e672ec80aca --- /dev/null +++ b/boards/lairdconnect/bl652_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl652_dvk + vendor: lairdconnect + socs: + - name: nrf52832 diff --git a/boards/arm/bl652_dvk/doc/bl652_dvk.rst b/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst similarity index 99% rename from boards/arm/bl652_dvk/doc/bl652_dvk.rst rename to boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst index 9d14b847fb9cdf..a0d6657d4c1772 100644 --- a/boards/arm/bl652_dvk/doc/bl652_dvk.rst +++ b/boards/lairdconnect/bl652_dvk/doc/bl652_dvk.rst @@ -260,7 +260,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl652_dvk/bl652_dvk.dts`. +:zephyr_file:`boards/laird_connect/bl652_dvk/bl652_dvk.dts`. References ********** diff --git a/boards/arm/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg b/boards/lairdconnect/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg similarity index 100% rename from boards/arm/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg rename to boards/lairdconnect/bl652_dvk/doc/img/BL652-SA_DVK_BoxContents.jpg diff --git a/boards/arm/bl652_dvk/doc/img/bl652_dvk.jpg b/boards/lairdconnect/bl652_dvk/doc/img/bl652_dvk.jpg similarity index 100% rename from boards/arm/bl652_dvk/doc/img/bl652_dvk.jpg rename to boards/lairdconnect/bl652_dvk/doc/img/bl652_dvk.jpg diff --git a/boards/arm/bt610/pre_dt_board.cmake b/boards/lairdconnect/bl652_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bt610/pre_dt_board.cmake rename to boards/lairdconnect/bl652_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl653_dvk/Kconfig b/boards/lairdconnect/bl653_dvk/Kconfig similarity index 100% rename from boards/arm/bl653_dvk/Kconfig rename to boards/lairdconnect/bl653_dvk/Kconfig diff --git a/boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk b/boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk new file mode 100644 index 00000000000000..65fd5c9a277969 --- /dev/null +++ b/boards/lairdconnect/bl653_dvk/Kconfig.bl653_dvk @@ -0,0 +1,7 @@ +# BL653 DVK board configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL653_DVK + select SOC_NRF52833_QIAA diff --git a/boards/lairdconnect/bl653_dvk/Kconfig.defconfig b/boards/lairdconnect/bl653_dvk/Kconfig.defconfig new file mode 100644 index 00000000000000..43f19f65a6d6e7 --- /dev/null +++ b/boards/lairdconnect/bl653_dvk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# BL653 DVK board configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL653_DVK + +config BT_CTLR + default BT + +if DAC + +config I2C + default y + +endif # DAC + +endif # BOARD_BL653_DVK diff --git a/boards/arm/bl653_dvk/bl653_dvk-pinctrl.dtsi b/boards/lairdconnect/bl653_dvk/bl653_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/bl653_dvk/bl653_dvk-pinctrl.dtsi rename to boards/lairdconnect/bl653_dvk/bl653_dvk-pinctrl.dtsi diff --git a/boards/arm/bl653_dvk/bl653_dvk.dts b/boards/lairdconnect/bl653_dvk/bl653_dvk.dts similarity index 100% rename from boards/arm/bl653_dvk/bl653_dvk.dts rename to boards/lairdconnect/bl653_dvk/bl653_dvk.dts diff --git a/boards/arm/bl653_dvk/bl653_dvk.yaml b/boards/lairdconnect/bl653_dvk/bl653_dvk.yaml similarity index 100% rename from boards/arm/bl653_dvk/bl653_dvk.yaml rename to boards/lairdconnect/bl653_dvk/bl653_dvk.yaml diff --git a/boards/arm/bl653_dvk/bl653_dvk_defconfig b/boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig similarity index 80% rename from boards/arm/bl653_dvk/bl653_dvk_defconfig rename to boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig index b1abe06089c33a..e61d78a6a18a34 100644 --- a/boards/arm/bl653_dvk/bl653_dvk_defconfig +++ b/boards/lairdconnect/bl653_dvk/bl653_dvk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_BL653_DVK=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl653_dvk/board.cmake b/boards/lairdconnect/bl653_dvk/board.cmake similarity index 100% rename from boards/arm/bl653_dvk/board.cmake rename to boards/lairdconnect/bl653_dvk/board.cmake diff --git a/boards/lairdconnect/bl653_dvk/board.yml b/boards/lairdconnect/bl653_dvk/board.yml new file mode 100644 index 00000000000000..c898247f1f3838 --- /dev/null +++ b/boards/lairdconnect/bl653_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl653_dvk + vendor: lairdconnect + socs: + - name: nrf52833 diff --git a/boards/arm/bl653_dvk/doc/bl653_dvk.rst b/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst similarity index 99% rename from boards/arm/bl653_dvk/doc/bl653_dvk.rst rename to boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst index ee5996e81aeefb..8e4c76b4d09f01 100644 --- a/boards/arm/bl653_dvk/doc/bl653_dvk.rst +++ b/boards/lairdconnect/bl653_dvk/doc/bl653_dvk.rst @@ -167,7 +167,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl653_dvk/bl653_dvk.dts`. +:zephyr_file:`boards/laird_connect/bl653_dvk/bl653_dvk.dts`. Using UART1 *********** diff --git a/boards/arm/bl653_dvk/doc/img/bl653_dvk.jpg b/boards/lairdconnect/bl653_dvk/doc/img/bl653_dvk.jpg similarity index 100% rename from boards/arm/bl653_dvk/doc/img/bl653_dvk.jpg rename to boards/lairdconnect/bl653_dvk/doc/img/bl653_dvk.jpg diff --git a/boards/arm/contextualelectronics_abc/pre_dt_board.cmake b/boards/lairdconnect/bl653_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/contextualelectronics_abc/pre_dt_board.cmake rename to boards/lairdconnect/bl653_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl654_dvk/Kconfig b/boards/lairdconnect/bl654_dvk/Kconfig similarity index 100% rename from boards/arm/bl654_dvk/Kconfig rename to boards/lairdconnect/bl654_dvk/Kconfig diff --git a/boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk b/boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk new file mode 100644 index 00000000000000..ec8ac37b241c04 --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/Kconfig.bl654_dvk @@ -0,0 +1,7 @@ +# BL654 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_DVK + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bl654_dvk/Kconfig.defconfig b/boards/lairdconnect/bl654_dvk/Kconfig.defconfig new file mode 100644 index 00000000000000..facb6117693de1 --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/Kconfig.defconfig @@ -0,0 +1,18 @@ +# BL654 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL654_DVK + +config BT_CTLR + default BT + +if DAC + +config I2C + default y + +endif # DAC + +endif # BOARD_BL654_DVK diff --git a/boards/arm/bl654_dvk/bl654_dvk-pinctrl.dtsi b/boards/lairdconnect/bl654_dvk/bl654_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/bl654_dvk/bl654_dvk-pinctrl.dtsi rename to boards/lairdconnect/bl654_dvk/bl654_dvk-pinctrl.dtsi diff --git a/boards/arm/bl654_dvk/bl654_dvk.dts b/boards/lairdconnect/bl654_dvk/bl654_dvk.dts similarity index 100% rename from boards/arm/bl654_dvk/bl654_dvk.dts rename to boards/lairdconnect/bl654_dvk/bl654_dvk.dts diff --git a/boards/arm/bl654_dvk/bl654_dvk.yaml b/boards/lairdconnect/bl654_dvk/bl654_dvk.yaml similarity index 100% rename from boards/arm/bl654_dvk/bl654_dvk.yaml rename to boards/lairdconnect/bl654_dvk/bl654_dvk.yaml diff --git a/boards/arm/bl654_dvk/bl654_dvk_defconfig b/boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig similarity index 81% rename from boards/arm/bl654_dvk/bl654_dvk_defconfig rename to boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig index 7d5b17577b282a..a108273c64ce58 100644 --- a/boards/arm/bl654_dvk/bl654_dvk_defconfig +++ b/boards/lairdconnect/bl654_dvk/bl654_dvk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BL654_DVK=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl654_dvk/board.cmake b/boards/lairdconnect/bl654_dvk/board.cmake similarity index 100% rename from boards/arm/bl654_dvk/board.cmake rename to boards/lairdconnect/bl654_dvk/board.cmake diff --git a/boards/lairdconnect/bl654_dvk/board.yml b/boards/lairdconnect/bl654_dvk/board.yml new file mode 100644 index 00000000000000..26fbd0e33bd450 --- /dev/null +++ b/boards/lairdconnect/bl654_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_dvk + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bl654_dvk/doc/bl654_dvk.rst b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst similarity index 98% rename from boards/arm/bl654_dvk/doc/bl654_dvk.rst rename to boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst index c70afb78729972..f4cbc11e332d2a 100644 --- a/boards/arm/bl654_dvk/doc/bl654_dvk.rst +++ b/boards/lairdconnect/bl654_dvk/doc/bl654_dvk.rst @@ -173,7 +173,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl654_dvk/bl654_dvk.dts`. +:zephyr_file:`boards/laird_connect/bl654_dvk/bl654_dvk.dts`. References diff --git a/boards/arm/bl654_dvk/doc/img/455-00001_BoxContents.jpg b/boards/lairdconnect/bl654_dvk/doc/img/455-00001_BoxContents.jpg similarity index 100% rename from boards/arm/bl654_dvk/doc/img/455-00001_BoxContents.jpg rename to boards/lairdconnect/bl654_dvk/doc/img/455-00001_BoxContents.jpg diff --git a/boards/arm/bl654_dvk/doc/img/bl654_dvk.jpg b/boards/lairdconnect/bl654_dvk/doc/img/bl654_dvk.jpg similarity index 100% rename from boards/arm/bl654_dvk/doc/img/bl654_dvk.jpg rename to boards/lairdconnect/bl654_dvk/doc/img/bl654_dvk.jpg diff --git a/boards/arm/decawave_dwm1001_dev/pre_dt_board.cmake b/boards/lairdconnect/bl654_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/decawave_dwm1001_dev/pre_dt_board.cmake rename to boards/lairdconnect/bl654_dvk/pre_dt_board.cmake diff --git a/boards/arm/bl654_sensor_board/Kconfig b/boards/lairdconnect/bl654_sensor_board/Kconfig similarity index 100% rename from boards/arm/bl654_sensor_board/Kconfig rename to boards/lairdconnect/bl654_sensor_board/Kconfig diff --git a/boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board b/boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board new file mode 100644 index 00000000000000..71ff5ad2f6f040 --- /dev/null +++ b/boards/lairdconnect/bl654_sensor_board/Kconfig.bl654_sensor_board @@ -0,0 +1,7 @@ +# BL654 Sensor Board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_SENSOR_BOARD + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig b/boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig new file mode 100644 index 00000000000000..3ac458bcec99e2 --- /dev/null +++ b/boards/lairdconnect/bl654_sensor_board/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BL654 Sensor Board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL654_SENSOR_BOARD + +config BT_CTLR + default BT + +endif # BOARD_BL654_SENSOR_BOARD diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi similarity index 100% rename from boards/arm/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board-pinctrl.dtsi diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board.dts b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts similarity index 100% rename from boards/arm/bl654_sensor_board/bl654_sensor_board.dts rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.dts diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board.yaml b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.yaml similarity index 100% rename from boards/arm/bl654_sensor_board/bl654_sensor_board.yaml rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board.yaml diff --git a/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig similarity index 77% rename from boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig rename to boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig index f8352265d3fcca..fedbabc08379c0 100644 --- a/boards/arm/bl654_sensor_board/bl654_sensor_board_defconfig +++ b/boards/lairdconnect/bl654_sensor_board/bl654_sensor_board_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BL654_SENSOR_BOARD=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bl654_sensor_board/board.cmake b/boards/lairdconnect/bl654_sensor_board/board.cmake similarity index 100% rename from boards/arm/bl654_sensor_board/board.cmake rename to boards/lairdconnect/bl654_sensor_board/board.cmake diff --git a/boards/lairdconnect/bl654_sensor_board/board.yml b/boards/lairdconnect/bl654_sensor_board/board.yml new file mode 100644 index 00000000000000..ebe40b44601f3a --- /dev/null +++ b/boards/lairdconnect/bl654_sensor_board/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_sensor_board + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst similarity index 99% rename from boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst rename to boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst index 673eed4eefb0ec..b3114b2948fdc5 100644 --- a/boards/arm/bl654_sensor_board/doc/bl654_sensor_board.rst +++ b/boards/lairdconnect/bl654_sensor_board/doc/bl654_sensor_board.rst @@ -238,7 +238,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button and LED definitions can be found in -:zephyr_file:`boards/arm/bl654_sensor_board/bl654_sensor_board.dts`. +:zephyr_file:`boards/laird_connect/bl654_sensor_board/bl654_sensor_board.dts`. References diff --git a/boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board.jpg b/boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board.jpg similarity index 100% rename from boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board.jpg rename to boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board.jpg diff --git a/boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg b/boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg similarity index 100% rename from boards/arm/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg rename to boards/lairdconnect/bl654_sensor_board/doc/img/bl654_sensor_board_usb_swd_programmer.jpg diff --git a/boards/arm/degu_evk/pre_dt_board.cmake b/boards/lairdconnect/bl654_sensor_board/pre_dt_board.cmake similarity index 100% rename from boards/arm/degu_evk/pre_dt_board.cmake rename to boards/lairdconnect/bl654_sensor_board/pre_dt_board.cmake diff --git a/boards/arm/bl654_usb/Kconfig b/boards/lairdconnect/bl654_usb/Kconfig similarity index 100% rename from boards/arm/bl654_usb/Kconfig rename to boards/lairdconnect/bl654_usb/Kconfig diff --git a/boards/lairdconnect/bl654_usb/Kconfig.bl654_usb b/boards/lairdconnect/bl654_usb/Kconfig.bl654_usb new file mode 100644 index 00000000000000..0dba254491ac52 --- /dev/null +++ b/boards/lairdconnect/bl654_usb/Kconfig.bl654_usb @@ -0,0 +1,7 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BL654_USB + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bl654_usb/Kconfig.defconfig b/boards/lairdconnect/bl654_usb/Kconfig.defconfig new file mode 100644 index 00000000000000..baf624a0c5a460 --- /dev/null +++ b/boards/lairdconnect/bl654_usb/Kconfig.defconfig @@ -0,0 +1,59 @@ +# BL654 USB adapter board configuration + +# Copyright (c) 2021-2022 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BL654_USB + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR, and limit the maximum size to not protude into +# the bootloader at the end of flash. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# so no override or limit is necessary. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on !USE_DT_CODE_PARTITION + +config FLASH_LOAD_SIZE + default 0xdf000 + depends on !USE_DT_CODE_PARTITION + +config USB_CDC_ACM + default n if USB_DEVICE_BLUETOOTH + +if BL654_USB_SERIAL_BACKEND_CDCACM + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +# Logger cannot use itself to log +config USB_CDC_ACM_LOG_LEVEL + default 0 + +# Set USB log level to error only +config USB_DEVICE_LOG_LEVEL + default 1 + +endif #BL654_USB_SERIAL_BACKEND_CDCACM + +config BT_CTLR + default BT + +endif # BOARD_BL654_USB diff --git a/boards/arm/bl654_usb/bl654_usb-pinctrl.dtsi b/boards/lairdconnect/bl654_usb/bl654_usb-pinctrl.dtsi similarity index 100% rename from boards/arm/bl654_usb/bl654_usb-pinctrl.dtsi rename to boards/lairdconnect/bl654_usb/bl654_usb-pinctrl.dtsi diff --git a/boards/arm/bl654_usb/bl654_usb.dts b/boards/lairdconnect/bl654_usb/bl654_usb.dts similarity index 100% rename from boards/arm/bl654_usb/bl654_usb.dts rename to boards/lairdconnect/bl654_usb/bl654_usb.dts diff --git a/boards/arm/bl654_usb/bl654_usb.yaml b/boards/lairdconnect/bl654_usb/bl654_usb.yaml similarity index 100% rename from boards/arm/bl654_usb/bl654_usb.yaml rename to boards/lairdconnect/bl654_usb/bl654_usb.yaml diff --git a/boards/arm/bl654_usb/bl654_usb_defconfig b/boards/lairdconnect/bl654_usb/bl654_usb_defconfig similarity index 79% rename from boards/arm/bl654_usb/bl654_usb_defconfig rename to boards/lairdconnect/bl654_usb/bl654_usb_defconfig index b51d0c1d99edde..ba7d61d55be66b 100644 --- a/boards/arm/bl654_usb/bl654_usb_defconfig +++ b/boards/lairdconnect/bl654_usb/bl654_usb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BL654_USB=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/lairdconnect/bl654_usb/board.yml b/boards/lairdconnect/bl654_usb/board.yml new file mode 100644 index 00000000000000..dc616554605c4a --- /dev/null +++ b/boards/lairdconnect/bl654_usb/board.yml @@ -0,0 +1,5 @@ +board: + name: bl654_usb + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bl654_usb/doc/bl654_usb.rst b/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst similarity index 95% rename from boards/arm/bl654_usb/doc/bl654_usb.rst rename to boards/lairdconnect/bl654_usb/doc/bl654_usb.rst index 5d4fdc774dec73..d2fd722f504887 100644 --- a/boards/arm/bl654_usb/doc/bl654_usb.rst +++ b/boards/lairdconnect/bl654_usb/doc/bl654_usb.rst @@ -103,9 +103,9 @@ Programming and Debugging Applications for the ``bl654_usb`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). The -``bl654_usb`` board cannot be used for debugging. The compatible BL654_DVK -board can be used for development. Documentation can be found at the `BL654_DVK -Zephyr site`_ and :zephyr_file:`boards/arm/bl654_dvk/doc/bl654_dvk.rst` +``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK +board can be used for development. Documentation can be found at the :ref:`bl654_dvk` +site and :zephyr_file:`boards/laird_connect/bl654_dvk/doc/bl654_dvk.rst` Flashing ======== @@ -175,7 +175,7 @@ the board is working properly with Zephyr: You can build and flash the example to make sure Zephyr is running correctly on your board. The LED definitions can be found in -:zephyr_file:`boards/arm/bl654_usb/bl654_usb.dts`. +:zephyr_file:`boards/laird_connect/bl654_usb/bl654_usb.dts`. References @@ -188,4 +188,3 @@ References .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html .. _Creating a secure bootloader image: https://www.lairdconnect.com/documentation/application-note-creating-secure-bootloader-image-bl654-usb .. _nrfutil: https://github.com/NordicSemiconductor/pc-nrfutil -.. _BL654_DVK Zephyr site: https://docs.zephyrproject.org/latest/boards/arm/bl654_dvk/doc/bl654_dvk.html diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb.jpg b/boards/lairdconnect/bl654_usb/doc/img/bl654_usb.jpg similarity index 100% rename from boards/arm/bl654_usb/doc/img/bl654_usb.jpg rename to boards/lairdconnect/bl654_usb/doc/img/bl654_usb.jpg diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb_pcb.jpg b/boards/lairdconnect/bl654_usb/doc/img/bl654_usb_pcb.jpg similarity index 100% rename from boards/arm/bl654_usb/doc/img/bl654_usb_pcb.jpg rename to boards/lairdconnect/bl654_usb/doc/img/bl654_usb_pcb.jpg diff --git a/boards/arm/bl654_usb/doc/img/bl654_usb_reset.jpg b/boards/lairdconnect/bl654_usb/doc/img/bl654_usb_reset.jpg similarity index 100% rename from boards/arm/bl654_usb/doc/img/bl654_usb_reset.jpg rename to boards/lairdconnect/bl654_usb/doc/img/bl654_usb_reset.jpg diff --git a/boards/arm/holyiot_yj16019/pre_dt_board.cmake b/boards/lairdconnect/bl654_usb/pre_dt_board.cmake similarity index 100% rename from boards/arm/holyiot_yj16019/pre_dt_board.cmake rename to boards/lairdconnect/bl654_usb/pre_dt_board.cmake diff --git a/boards/arm/bt510/Kconfig b/boards/lairdconnect/bt510/Kconfig similarity index 100% rename from boards/arm/bt510/Kconfig rename to boards/lairdconnect/bt510/Kconfig diff --git a/boards/lairdconnect/bt510/Kconfig.bt510 b/boards/lairdconnect/bt510/Kconfig.bt510 new file mode 100644 index 00000000000000..20a34044970aa0 --- /dev/null +++ b/boards/lairdconnect/bt510/Kconfig.bt510 @@ -0,0 +1,7 @@ +# BT510 DVK board configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BT510 + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bt510/Kconfig.defconfig b/boards/lairdconnect/bt510/Kconfig.defconfig new file mode 100644 index 00000000000000..70cb87fa1f776f --- /dev/null +++ b/boards/lairdconnect/bt510/Kconfig.defconfig @@ -0,0 +1,14 @@ +# BT510 Sensor configuration + +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BT510 + +config BT_CTLR + default BT + +config I2C + default SENSOR + +endif # BOARD_BT510 diff --git a/boards/arm/bt510/board.cmake b/boards/lairdconnect/bt510/board.cmake similarity index 100% rename from boards/arm/bt510/board.cmake rename to boards/lairdconnect/bt510/board.cmake diff --git a/boards/lairdconnect/bt510/board.yml b/boards/lairdconnect/bt510/board.yml new file mode 100644 index 00000000000000..1a9760895ecf19 --- /dev/null +++ b/boards/lairdconnect/bt510/board.yml @@ -0,0 +1,5 @@ +board: + name: bt510 + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bt510/bt510-pinctrl.dtsi b/boards/lairdconnect/bt510/bt510-pinctrl.dtsi similarity index 100% rename from boards/arm/bt510/bt510-pinctrl.dtsi rename to boards/lairdconnect/bt510/bt510-pinctrl.dtsi diff --git a/boards/arm/bt510/bt510.dts b/boards/lairdconnect/bt510/bt510.dts similarity index 100% rename from boards/arm/bt510/bt510.dts rename to boards/lairdconnect/bt510/bt510.dts diff --git a/boards/arm/bt510/bt510.yaml b/boards/lairdconnect/bt510/bt510.yaml similarity index 100% rename from boards/arm/bt510/bt510.yaml rename to boards/lairdconnect/bt510/bt510.yaml diff --git a/boards/arm/bt510/bt510_defconfig b/boards/lairdconnect/bt510/bt510_defconfig similarity index 79% rename from boards/arm/bt510/bt510_defconfig rename to boards/lairdconnect/bt510/bt510_defconfig index cd897918fe1602..c4cc98bc3b7ecd 100644 --- a/boards/arm/bt510/bt510_defconfig +++ b/boards/lairdconnect/bt510/bt510_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BT510=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bt510/doc/bt510.rst b/boards/lairdconnect/bt510/doc/bt510.rst similarity index 99% rename from boards/arm/bt510/doc/bt510.rst rename to boards/lairdconnect/bt510/doc/bt510.rst index 841c27b85d66f5..cbee5deabb8b0b 100644 --- a/boards/arm/bt510/doc/bt510.rst +++ b/boards/lairdconnect/bt510/doc/bt510.rst @@ -244,7 +244,7 @@ the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/arm/bt510/bt510.dts`. +:zephyr_file:`boards/laird_connect/bt510/bt510.dts`. References diff --git a/boards/arm/bt510/doc/img/bt510.jpg b/boards/lairdconnect/bt510/doc/img/bt510.jpg similarity index 100% rename from boards/arm/bt510/doc/img/bt510.jpg rename to boards/lairdconnect/bt510/doc/img/bt510.jpg diff --git a/boards/arm/bt510/doc/img/bt510_back.jpg b/boards/lairdconnect/bt510/doc/img/bt510_back.jpg similarity index 100% rename from boards/arm/bt510/doc/img/bt510_back.jpg rename to boards/lairdconnect/bt510/doc/img/bt510_back.jpg diff --git a/boards/arm/bt510/doc/img/bt510_prog.jpg b/boards/lairdconnect/bt510/doc/img/bt510_prog.jpg similarity index 100% rename from boards/arm/bt510/doc/img/bt510_prog.jpg rename to boards/lairdconnect/bt510/doc/img/bt510_prog.jpg diff --git a/boards/arm/mg100/pre_dt_board.cmake b/boards/lairdconnect/bt510/pre_dt_board.cmake similarity index 100% rename from boards/arm/mg100/pre_dt_board.cmake rename to boards/lairdconnect/bt510/pre_dt_board.cmake diff --git a/boards/arm/bt610/Kconfig b/boards/lairdconnect/bt610/Kconfig similarity index 100% rename from boards/arm/bt610/Kconfig rename to boards/lairdconnect/bt610/Kconfig diff --git a/boards/lairdconnect/bt610/Kconfig.bt610 b/boards/lairdconnect/bt610/Kconfig.bt610 new file mode 100644 index 00000000000000..c87453d32a9283 --- /dev/null +++ b/boards/lairdconnect/bt610/Kconfig.bt610 @@ -0,0 +1,7 @@ +# BT610 board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BT610 + select SOC_NRF52840_QIAA diff --git a/boards/lairdconnect/bt610/Kconfig.defconfig b/boards/lairdconnect/bt610/Kconfig.defconfig new file mode 100644 index 00000000000000..9a82770655ef07 --- /dev/null +++ b/boards/lairdconnect/bt610/Kconfig.defconfig @@ -0,0 +1,14 @@ +# BT6X0 Sensor configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BT610 + +config BT_CTLR + default BT + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_TI_TCA9538),i2c) + +endif # BOARD_BT610 diff --git a/boards/arm/bt610/board.cmake b/boards/lairdconnect/bt610/board.cmake similarity index 100% rename from boards/arm/bt610/board.cmake rename to boards/lairdconnect/bt610/board.cmake diff --git a/boards/lairdconnect/bt610/board.yml b/boards/lairdconnect/bt610/board.yml new file mode 100644 index 00000000000000..c5a846a0d8d4ae --- /dev/null +++ b/boards/lairdconnect/bt610/board.yml @@ -0,0 +1,5 @@ +board: + name: bt610 + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/bt610/bt610-pinctrl.dtsi b/boards/lairdconnect/bt610/bt610-pinctrl.dtsi similarity index 100% rename from boards/arm/bt610/bt610-pinctrl.dtsi rename to boards/lairdconnect/bt610/bt610-pinctrl.dtsi diff --git a/boards/arm/bt610/bt610.dts b/boards/lairdconnect/bt610/bt610.dts similarity index 100% rename from boards/arm/bt610/bt610.dts rename to boards/lairdconnect/bt610/bt610.dts diff --git a/boards/arm/bt610/bt610.yaml b/boards/lairdconnect/bt610/bt610.yaml similarity index 100% rename from boards/arm/bt610/bt610.yaml rename to boards/lairdconnect/bt610/bt610.yaml diff --git a/boards/arm/bt610/bt610_defconfig b/boards/lairdconnect/bt610/bt610_defconfig similarity index 82% rename from boards/arm/bt610/bt610_defconfig rename to boards/lairdconnect/bt610/bt610_defconfig index 531ba015b1efca..3bff5fbaeb5793 100644 --- a/boards/arm/bt610/bt610_defconfig +++ b/boards/lairdconnect/bt610/bt610_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_BT610=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/bt610/doc/bt610.rst b/boards/lairdconnect/bt610/doc/bt610.rst similarity index 99% rename from boards/arm/bt610/doc/bt610.rst rename to boards/lairdconnect/bt610/doc/bt610.rst index 2fe7d7ad93129c..25798b1281024f 100644 --- a/boards/arm/bt610/doc/bt610.rst +++ b/boards/lairdconnect/bt610/doc/bt610.rst @@ -598,7 +598,7 @@ on the board are working properly with Zephyr: You can build and flash the examples to make sure Zephyr is running correctly on your board. The button, LED and sensor device definitions can be found in -:zephyr_file:`boards/arm/bt610/bt610.dts`. +:zephyr_file:`boards/laird_connect/bt610/bt610.dts`. References diff --git a/boards/arm/bt610/doc/img/bt610_back.jpg b/boards/lairdconnect/bt610/doc/img/bt610_back.jpg similarity index 100% rename from boards/arm/bt610/doc/img/bt610_back.jpg rename to boards/lairdconnect/bt610/doc/img/bt610_back.jpg diff --git a/boards/arm/bt610/doc/img/bt610_board.jpg b/boards/lairdconnect/bt610/doc/img/bt610_board.jpg similarity index 100% rename from boards/arm/bt610/doc/img/bt610_board.jpg rename to boards/lairdconnect/bt610/doc/img/bt610_board.jpg diff --git a/boards/arm/bt610/doc/img/bt610_front.jpg b/boards/lairdconnect/bt610/doc/img/bt610_front.jpg similarity index 100% rename from boards/arm/bt610/doc/img/bt610_front.jpg rename to boards/lairdconnect/bt610/doc/img/bt610_front.jpg diff --git a/boards/arm/nrf21540dk_nrf52840/pre_dt_board.cmake b/boards/lairdconnect/bt610/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/pre_dt_board.cmake rename to boards/lairdconnect/bt610/pre_dt_board.cmake diff --git a/boards/lairdconnect/index.rst b/boards/lairdconnect/index.rst new file mode 100644 index 00000000000000..5c3a6d6621a2a9 --- /dev/null +++ b/boards/lairdconnect/index.rst @@ -0,0 +1,10 @@ +.. _boards-lairdconnect: + +Laird Connectivity +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/mg100/Kconfig b/boards/lairdconnect/mg100/Kconfig similarity index 100% rename from boards/arm/mg100/Kconfig rename to boards/lairdconnect/mg100/Kconfig diff --git a/boards/lairdconnect/mg100/Kconfig.defconfig b/boards/lairdconnect/mg100/Kconfig.defconfig new file mode 100644 index 00000000000000..7c08d74f8c5a46 --- /dev/null +++ b/boards/lairdconnect/mg100/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2022 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MG100 + +config MODEM + default NETWORKING + +config MODEM_HL7800 + default NETWORKING + +config NORDIC_QSPI_NOR + default BOOTLOADER_MCUBOOT + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if NORDIC_QSPI_NOR + +config REGULATOR + default DISK_DRIVER_SDMMC + +config BT_CTLR + default BT + +endif # BOARD_MG100 diff --git a/boards/lairdconnect/mg100/Kconfig.mg100 b/boards/lairdconnect/mg100/Kconfig.mg100 new file mode 100644 index 00000000000000..9129b13291128e --- /dev/null +++ b/boards/lairdconnect/mg100/Kconfig.mg100 @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MG100 + bool + default y + select SOC_NRF52840_QIAA diff --git a/boards/arm/mg100/board.cmake b/boards/lairdconnect/mg100/board.cmake similarity index 100% rename from boards/arm/mg100/board.cmake rename to boards/lairdconnect/mg100/board.cmake diff --git a/boards/lairdconnect/mg100/board.yml b/boards/lairdconnect/mg100/board.yml new file mode 100644 index 00000000000000..25a3ace314f714 --- /dev/null +++ b/boards/lairdconnect/mg100/board.yml @@ -0,0 +1,5 @@ +board: + name: mg100 + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/mg100/doc/img/mg100.jpg b/boards/lairdconnect/mg100/doc/img/mg100.jpg similarity index 100% rename from boards/arm/mg100/doc/img/mg100.jpg rename to boards/lairdconnect/mg100/doc/img/mg100.jpg diff --git a/boards/lairdconnect/mg100/doc/index.rst b/boards/lairdconnect/mg100/doc/index.rst new file mode 100644 index 00000000000000..e89fb09cf0a8fd --- /dev/null +++ b/boards/lairdconnect/mg100/doc/index.rst @@ -0,0 +1,249 @@ +.. _mg100: + +Laird Connectivity Sentrius™ MG100 Gateway +########################################## + +Overview +******** +The Sentrius™ MG100 Gateway offers a compact, out of box Bluetooth to low power cellular gateway +solution. + +Based on the Pinnacle 100 socket modem, the Sentrius™ MG100 gateway captures data from any +Bluetooth 5 modules or devices and sends it to the cloud via a global low power cellular +(LTE-M/NB-IoT) connection. The MG100 seamlessly incorporates a powerful Cortex M4F controller, +full Bluetooth 5 connectivity, and dual-mode LTE-M/NB-IoT capabilities. The MG100 has full regulatory +and network certifications and End Device carrier approvals. + +Develop your application directly on the integrated Cortex M4F microcontroller using Zephyr RTOS, +enabling your application development with a secure, open source RTOS with more than just kernel +services. Remotely debug your fleet of devices with the `Memfault Platform`_. Take advantage of the +Zephyr community and Laird Connectivity’s multi featured Out of Box (OOB) sample source code +covering all aspects of the product's capabilities and hardware interfaces. The MG100 also delivers +complete antenna flexibility with internal or external antenna options available, and the optional +battery backup provides uninterrupted reporting of remote Bluetooth sensor data. + +More information about the board can be found at the `MG100 website`_. + +The MG100 hardware provides support for the Nordic Semiconductor `nRF52840`_ ARM Cortex-M4F CPU, +`Sierra Wireless HL7800`_ +and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* :abbr:`LIS3DH (ST Micro 3-axis MEMS accelerometer)` +* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` +* :abbr:`SD Card` + +.. figure:: img/mg100.jpg + :align: center + :alt: MG100 + + MG100 (450-00054-K1) + +Hardware +******** + +Supported Features +================== + +The MG100 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| QSPI | on-chip | qspi/MX25R64(8MB) | ++-----------+------------+----------------------+ +| LIS3DH | I2C(M) | sensor/lis3dh | ++-----------+------------+----------------------+ +| HL7800 | UART | HL7800 modem driver | ++-----------+------------+----------------------+ +| SDMMC | SPI(M) | SD Card via SPI | ++-----------+------------+----------------------+ + +See `MG100 website`_ for a complete list +of MG100 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P1.7 +* LED2 (blue) = P1.6 +* LED3 (green) = P1.5 + +Push buttons +------------ + +* BUTTON1 = P0.3 + +External flash memory +--------------------- + +A 64Mbit external flash memory part is available for storage of application +images and data. Refer to the `Macronix MX25R6435F datasheet`_ for further +details. + +The flash memory is connected to the on-board QSPI device controller. + +* MX25R64 = QSPI + +SCK = P0.19 +IO0 = P0.20 +IO1 = P0.21 +IO2 = P0.22 +IO3 = P0.23 +CSN = P0.17 + +LIS3DH Motion Sensor +-------------------- + +Motion sensor to detect if the gateway moves. + +IRQ IO = P0.28 +I2C SDA = P0.26 +I2C SCL = P0.27 + +SD Card +------- + +SD card used to store large amounts of data. + +SPI CS = P0.29 +SPI SCK = P1.09 +SPI MOSI = P0.11 +SPI MISO = P0.12 + +Programming and Debugging +************************* + +Applications for the ``mg100`` board configuration can be +built and flashed in the usual way. (see :ref:`build_an_application` +and :ref:`application_run` for more details) + +The `Laird Connectivity USB-SWD Programming Kit`_ contains all the necessary +hardware to enable programming and debugging an MG100. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. note:: On the MG100, + the USB connector should be used to access the UART console. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board MG100 +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mg100 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Software +******** + +MG100 Out-of-Box Demo Software +============================== +The MG100 ships with an out of the box software demo. +Check out the `BLE Gateway OOB Demo`_ source code and documentation. + +Testing Bluetooth on the MG100 +============================== +Many of the Bluetooth examples will work on the MG100. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + +Testing the LEDs and buttons in the MG100 +==================================================== + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/laird_connect/mg100/mg100.dts`. + +References +********** + +.. target-notes:: + +.. _MG100 website: https://www.lairdconnect.com/iot-devices/iot-gateways/sentrius-mg100-gateway-lte-mnb-iot-and-bluetooth-5 +.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf +.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _BLE Gateway OOB Demo: https://github.com/LairdCP/Pinnacle-100-Firmware-Manifest +.. _Macronix MX25R6435F datasheet: https://www.macronix.com/Lists/Datasheet/Attachments/7913/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.5.pdf +.. _Laird Connectivity USB-SWD Programming Kit: https://www.lairdconnect.com/wireless-modules/programming-kits/usb-swd-programming-kit +.. _Memfault Platform: https://docs.memfault.com/docs/mcu/pinnacle-100-guide +.. _nRF52840: https://www.nordicsemi.com/products/nrf52840 diff --git a/boards/arm/mg100/mg100-pinctrl.dtsi b/boards/lairdconnect/mg100/mg100-pinctrl.dtsi similarity index 100% rename from boards/arm/mg100/mg100-pinctrl.dtsi rename to boards/lairdconnect/mg100/mg100-pinctrl.dtsi diff --git a/boards/arm/mg100/mg100.dts b/boards/lairdconnect/mg100/mg100.dts similarity index 100% rename from boards/arm/mg100/mg100.dts rename to boards/lairdconnect/mg100/mg100.dts diff --git a/boards/arm/mg100/mg100.yaml b/boards/lairdconnect/mg100/mg100.yaml similarity index 100% rename from boards/arm/mg100/mg100.yaml rename to boards/lairdconnect/mg100/mg100.yaml diff --git a/boards/arm/mg100/mg100_defconfig b/boards/lairdconnect/mg100/mg100_defconfig similarity index 81% rename from boards/arm/mg100/mg100_defconfig rename to boards/lairdconnect/mg100/mg100_defconfig index e2af3973938d0c..f40691b7952939 100644 --- a/boards/arm/mg100/mg100_defconfig +++ b/boards/lairdconnect/mg100/mg100_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Laird Connectivity # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_MG100=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52832_mdk/pre_dt_board.cmake b/boards/lairdconnect/mg100/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52832_mdk/pre_dt_board.cmake rename to boards/lairdconnect/mg100/pre_dt_board.cmake diff --git a/boards/arm/pinnacle_100_dvk/Kconfig b/boards/lairdconnect/pinnacle_100_dvk/Kconfig similarity index 100% rename from boards/arm/pinnacle_100_dvk/Kconfig rename to boards/lairdconnect/pinnacle_100_dvk/Kconfig diff --git a/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig new file mode 100644 index 00000000000000..181dc76a04ebab --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Pinnacle(TM) 100 DVK board configuration + +# Copyright (c) 2019 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PINNACLE_100_DVK + +config MODEM + default NETWORKING + +config MODEM_HL7800 + default NETWORKING + +config NORDIC_QSPI_NOR + default BOOTLOADER_MCUBOOT + +config NORDIC_QSPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 if NORDIC_QSPI_NOR + +config BT_CTLR + default BT + +endif # BOARD_PINNACLE_100_DVK diff --git a/boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk new file mode 100644 index 00000000000000..fa018b9ab03974 --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/Kconfig.pinnacle_100_dvk @@ -0,0 +1,9 @@ +# Pinnacle(TM) 100 DVK board configuration +# +# Copyright (c) 2020 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PINNACLE_100_DVK + bool + default y + select SOC_NRF52840_QIAA diff --git a/boards/arm/pinnacle_100_dvk/board.cmake b/boards/lairdconnect/pinnacle_100_dvk/board.cmake similarity index 100% rename from boards/arm/pinnacle_100_dvk/board.cmake rename to boards/lairdconnect/pinnacle_100_dvk/board.cmake diff --git a/boards/lairdconnect/pinnacle_100_dvk/board.yml b/boards/lairdconnect/pinnacle_100_dvk/board.yml new file mode 100644 index 00000000000000..1741e687ace1ba --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: pinnacle_100_dvk + vendor: lairdconnect + socs: + - name: nrf52840 diff --git a/boards/arm/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg b/boards/lairdconnect/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg similarity index 100% rename from boards/arm/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg rename to boards/lairdconnect/pinnacle_100_dvk/doc/img/pinnacle_100_dvk.jpg diff --git a/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst b/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst new file mode 100644 index 00000000000000..483fff9dd8e51c --- /dev/null +++ b/boards/lairdconnect/pinnacle_100_dvk/doc/index.rst @@ -0,0 +1,220 @@ +.. _pinnacle_100_dvk: + +Laird Connectivity Pinnacle 100 DVK +################################### + +Overview +******** +The Pinnacle™ 100 cellular modem seamlessly incorporates a powerful Cortex M4F +controller, full Bluetooth 5 and LTE-M/NB-IoT capabilities – all with full +regulatory certifications and LTE carrier approvals. The Pinnacle 100 also +delivers complete antenna flexibility, with pre-integrated internal or external +antenna options such as the Revie Flex family of LTE and NB-IoT +internal antennas. + +Develop your application directly on the M4F controller using Zephyr RTOS to +cut BOM costs and power consumption. Take advantage of the Zephyr community, +Laird Connectivity’s sample code (cellular, Bluetooth) and hardware interfaces, +or use our hosted mode AT commands set firmware. + +Extremely power conscious, the Pinnacle 100 is ideal for battery-powered +devices operating at the edge of your IoT networks, seamlessly bridging the +cellular WAN to BLE. It’s never been easier to bridge wireless +Bluetooth 5 sensor data to cloud services like AWS IoT over a +low-power LTE connection. + +More information about the board can be found at the `Pinnacle 100 website`_. + +The Pinnacle 100 Development Kit (453-00010-K1 or 453-00011-K1) hardware +provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU, `Sierra Wireless HL7800`_ (Altair ALT1250) +and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* :abbr:`BME680 (Bosch Sensortec BME680 environmental sensor)` +* :abbr:`HL7800 (Sierra Wireless HL7800 LTE-M1/NB-IoT modem)` + +.. figure:: img/pinnacle_100_dvk.jpg + :align: center + :alt: Pinnacle 100 DVK + + Pinnacle 100 DVK (453-00010-K1) + +Hardware +******** + +Supported Features +================== + +The Pinnacle 100 development board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| QSPI | on-chip | qspi/MX25R64(8MB) | ++-----------+------------+----------------------+ +| BME680 | I2C(M) | sensor/bme680 | ++-----------+------------+----------------------+ +| HL7800 | UART | HL7800 modem driver | ++-----------+------------+----------------------+ + +See `Pinnacle 100 website`_ for a complete list +of Pinnacle 100 Development Kit hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (blue) = P1.4 +* LED2 (green) = P1.5 +* LED3 (red) = P1.6 +* LED4 (green) = P1.7 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.31 +* BUTTON2 = SW2 = P0.3 +* BUTTON3 = SW3 = P0.4 +* BUTTON4 = SW4 = P0.2 +* NRF RESET = SW5 = reset + +Programming and Debugging +************************* + +Applications for the ``pinnacle_100_dvk`` board configuration can be +built and flashed in the usual way. (see :ref:`build_an_application` +and :ref:`application_run` for more details) + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. note:: On the Pinnacle 100 development board, + the FTDI USB should be used to access the UART console. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board Pinnacle 100 DVK +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: pinnacle_100_dvk + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Software +******** + +Pinnacle 100 Out-of-Box Demo Software +===================================== +The Pinnacle 100 development kit ships with an out of the box software demo. +Check out the `Pinnacle 100 OOB Demo`_ source code and documentation. + +Sample Applications +=================== +`Pinnacle 100 Sample Applications`_ are available. + +Testing Bluetooth on the Pinnacle 100 DVK +========================================= +Many of the Bluetooth examples will work on the Pinnacle 100 DVK. +Try them out: + +* :ref:`ble_peripheral` +* :ref:`bluetooth-eddystone-sample` +* :ref:`bluetooth-ibeacon-sample` + +Testing the LEDs and buttons in the Pinnacle 100 DVK +==================================================== + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/laird_connect/pinnacle_100_dvk/pinnacle_100_dvk.dts`. + +References +********** + +.. target-notes:: + +.. _Pinnacle 100 website: https://www.lairdconnect.com/wireless-modules/cellular-solutions/pinnacle-100-cellular-modem +.. _nRF52840 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.1.pdf +.. _Sierra Wireless HL7800: https://source.sierrawireless.com/devices/hl-series/hl7800/#sthash.641qTTwA.dpbs +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _Pinnacle 100 OOB Demo: https://github.com/LairdCP/Pinnacle_100_oob_demo +.. _Pinnacle 100 Sample Applications: https://github.com/LairdCP/Pinnacle_100_Sample_Applications diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk-pinctrl.dtsi diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts similarity index 100% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.dts rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.dts diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.yaml b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.yaml similarity index 100% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk.yaml rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk.yaml diff --git a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig similarity index 81% rename from boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig rename to boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig index 0e6c950ae36966..06f53140c430d6 100644 --- a/boards/arm/pinnacle_100_dvk/pinnacle_100_dvk_defconfig +++ b/boards/lairdconnect/pinnacle_100_dvk/pinnacle_100_dvk_defconfig @@ -2,10 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PINNACLE_100_DVK=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52833dk_nrf52820/pre_dt_board.cmake b/boards/lairdconnect/pinnacle_100_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52833dk_nrf52820/pre_dt_board.cmake rename to boards/lairdconnect/pinnacle_100_dvk/pre_dt_board.cmake diff --git a/boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig b/boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig new file mode 100644 index 00000000000000..01cbc05ee78930 --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# rm1xx_dvk board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RM1XX_DVK + +config BT_CTLR + default BT + +endif # BOARD_RM1XX_DVK diff --git a/boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk b/boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk new file mode 100644 index 00000000000000..ead49ede862c4e --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/Kconfig.rm1xx_dvk @@ -0,0 +1,7 @@ +# rm1xx_dvk board configuration + +# Copyright (c) 2021 Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RM1XX_DVK + select SOC_NRF51822_QFAC diff --git a/boards/arm/rm1xx_dvk/board.cmake b/boards/lairdconnect/rm1xx_dvk/board.cmake similarity index 100% rename from boards/arm/rm1xx_dvk/board.cmake rename to boards/lairdconnect/rm1xx_dvk/board.cmake diff --git a/boards/lairdconnect/rm1xx_dvk/board.yml b/boards/lairdconnect/rm1xx_dvk/board.yml new file mode 100644 index 00000000000000..1e7ddd8f806789 --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/board.yml @@ -0,0 +1,5 @@ +board: + name: rm1xx_dvk + vendor: lairdconnect + socs: + - name: nrf51822 diff --git a/boards/arm/rm1xx_dvk/doc/img/RM186-DVK.jpg b/boards/lairdconnect/rm1xx_dvk/doc/img/RM186-DVK.jpg similarity index 100% rename from boards/arm/rm1xx_dvk/doc/img/RM186-DVK.jpg rename to boards/lairdconnect/rm1xx_dvk/doc/img/RM186-DVK.jpg diff --git a/boards/arm/rm1xx_dvk/doc/img/RM186-SM.jpg b/boards/lairdconnect/rm1xx_dvk/doc/img/RM186-SM.jpg similarity index 100% rename from boards/arm/rm1xx_dvk/doc/img/RM186-SM.jpg rename to boards/lairdconnect/rm1xx_dvk/doc/img/RM186-SM.jpg diff --git a/boards/arm/rm1xx_dvk/doc/index.rst b/boards/lairdconnect/rm1xx_dvk/doc/index.rst similarity index 100% rename from boards/arm/rm1xx_dvk/doc/index.rst rename to boards/lairdconnect/rm1xx_dvk/doc/index.rst diff --git a/boards/arm/bbc_microbit/pre_dt_board.cmake b/boards/lairdconnect/rm1xx_dvk/pre_dt_board.cmake similarity index 100% rename from boards/arm/bbc_microbit/pre_dt_board.cmake rename to boards/lairdconnect/rm1xx_dvk/pre_dt_board.cmake diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi similarity index 100% rename from boards/arm/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi rename to boards/lairdconnect/rm1xx_dvk/rm1xx_dvk-pinctrl.dtsi diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk.dts b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.dts similarity index 100% rename from boards/arm/rm1xx_dvk/rm1xx_dvk.dts rename to boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.dts diff --git a/boards/arm/rm1xx_dvk/rm1xx_dvk.yaml b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.yaml similarity index 100% rename from boards/arm/rm1xx_dvk/rm1xx_dvk.yaml rename to boards/lairdconnect/rm1xx_dvk/rm1xx_dvk.yaml diff --git a/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig new file mode 100644 index 00000000000000..46dc69d74cde7d --- /dev/null +++ b/boards/lairdconnect/rm1xx_dvk/rm1xx_dvk_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_PINCTRL=y diff --git a/boards/lowrisc/index.rst b/boards/lowrisc/index.rst new file mode 100644 index 00000000000000..cc96e30f5018d3 --- /dev/null +++ b/boards/lowrisc/index.rst @@ -0,0 +1,10 @@ +.. _boards-lowrisc: + +lowRISC +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey b/boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey new file mode 100644 index 00000000000000..b7ba3bd9f71c6c --- /dev/null +++ b/boards/lowrisc/opentitan_earlgrey/Kconfig.opentitan_earlgrey @@ -0,0 +1,5 @@ +# Copyright (c) 2023 by Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OPENTITAN_EARLGREY + select SOC_OPENTITAN diff --git a/boards/lowrisc/opentitan_earlgrey/board.yml b/boards/lowrisc/opentitan_earlgrey/board.yml new file mode 100644 index 00000000000000..d7e8a24879c281 --- /dev/null +++ b/boards/lowrisc/opentitan_earlgrey/board.yml @@ -0,0 +1,5 @@ +board: + name: opentitan_earlgrey + vendor: lowrisc + socs: + - name: opentitan diff --git a/boards/riscv/opentitan_earlgrey/doc/index.rst b/boards/lowrisc/opentitan_earlgrey/doc/index.rst similarity index 100% rename from boards/riscv/opentitan_earlgrey/doc/index.rst rename to boards/lowrisc/opentitan_earlgrey/doc/index.rst diff --git a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey.dts b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.dts similarity index 100% rename from boards/riscv/opentitan_earlgrey/opentitan_earlgrey.dts rename to boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.dts diff --git a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey.yaml b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.yaml similarity index 100% rename from boards/riscv/opentitan_earlgrey/opentitan_earlgrey.yaml rename to boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey.yaml diff --git a/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig new file mode 100644 index 00000000000000..f9c0c4a356a775 --- /dev/null +++ b/boards/lowrisc/opentitan_earlgrey/opentitan_earlgrey_defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 by Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig new file mode 100644 index 00000000000000..054ac2567296e2 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/Kconfig.defconfig @@ -0,0 +1,15 @@ +# ESP32C3 core board configuration + +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core b/boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core new file mode 100644 index 00000000000000..e7eb73ed384ee5 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/Kconfig.esp32c3_luatos_core @@ -0,0 +1,5 @@ +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32C3_LUATOS_CORE + select SOC_ESP32C3_MINI_N4 diff --git a/boards/xtensa/esp32s3_luatos_core/Kconfig.sysbuild b/boards/luatos/esp32c3_luatos_core/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/Kconfig.sysbuild rename to boards/luatos/esp32c3_luatos_core/Kconfig.sysbuild diff --git a/boards/riscv/esp32c3_luatos_core/board.cmake b/boards/luatos/esp32c3_luatos_core/board.cmake similarity index 100% rename from boards/riscv/esp32c3_luatos_core/board.cmake rename to boards/luatos/esp32c3_luatos_core/board.cmake diff --git a/boards/luatos/esp32c3_luatos_core/board.yml b/boards/luatos/esp32c3_luatos_core/board.yml new file mode 100644 index 00000000000000..e1a5ed42046171 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/board.yml @@ -0,0 +1,7 @@ +board: + name: esp32c3_luatos_core + vendor: luatos + socs: + - name: esp32c3 + variants: + - name: usb diff --git a/boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg b/boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg rename to boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core.jpg diff --git a/boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg b/boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg rename to boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_pinfunc.jpg diff --git a/boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg b/boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg rename to boards/luatos/esp32c3_luatos_core/doc/img/esp32c3_luatos_core_usb.jpg diff --git a/boards/luatos/esp32c3_luatos_core/doc/index.rst b/boards/luatos/esp32c3_luatos_core/doc/index.rst new file mode 100644 index 00000000000000..beaf0d1e85bfad --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/doc/index.rst @@ -0,0 +1,259 @@ +.. _esp32c3_luatos_core: + +ESP32C3_LUATOS_CORE +################### + +Overview +******** + +ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, +based on the open-source RISC-V architecture. It strikes the right balance of power, +I/O capabilities and security, thus offering the optimal cost-effective +solution for connected devices. +The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, +but it also facilitates a variety of use-cases based on dual connectivity. [1]_ + +The features include the following: + +- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz +- 400 KB of internal RAM +- 802.11b/g/n/e/i +- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh +- Various peripherals: + + - 12-bit ADC with up to 6 channels + - TWAI compatible with CAN bus 2.0 + - Temperature sensor + - 3x SPI + - 1x I2S + - 1x I2C + - 2x UART + - LED PWM with up to 6 channels + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) + +There are two version hardware of this board. The difference between them is the ch343 chip. + +1. USB-C connect to UART over CH343 chip(esp32c3_luatos_core) + +.. image:: img/esp32c3_luatos_core.jpg + :align: center + :alt: esp32c3_luatos_core + +2. USB-C connect to esp32 chip directly(esp32c3_luatos_core/esp32c3/usb) + +.. image:: img/esp32c3_luatos_core_usb.jpg + :align: center + :alt: esp32c3_luatos_core/esp32c3/usb + +Supported Features +================== + +Current Zephyr's ESP32C3_LUATOS_CORE board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +.. image:: img/esp32c3_luatos_core_pinfunc.jpg + :align: center + :alt: esp32c3_luatos_core_pinfunc + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32c3_luatos_core + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: build + +The usual ``flash`` target will work with the ``esp32c3_luatos_core`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32c3_luatos_core + +Debugging +********* + +As with much custom hardware, the ESP32-C3 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32c3_luatos_core + :goals: debug + +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases + +References +********** + +.. [1] https://www.espressif.com/en/products/socs/esp32-c3 +.. _ESP32C3 Core Website: https://wiki.luatos.com/chips/esp32c3/board.html +.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi similarity index 100% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core-pinctrl.dtsi diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dts b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts similarity index 100% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dts rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dts diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi similarity index 98% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dtsi rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi index 2a1a74996c5c70..2972e4725f1d2e 100644 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.dtsi +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi @@ -9,7 +9,7 @@ #include / { - model = "esp32c3_luatos_core"; + model = "ESP32C3 Luatos Core"; compatible = "espressif,esp32c3"; aliases { diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.yaml b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml similarity index 80% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.yaml rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml index 21f96ad6c9eab1..5baefb918a28d7 100644 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core.yaml +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.yaml @@ -1,4 +1,4 @@ -identifier: esp32c3_luatos_core +identifier: esp32c3_luatos_core/esp32c3 name: ESP32C3 LuatOS Core type: mcu arch: riscv @@ -19,4 +19,4 @@ testing: ignore_tags: - net - bluetooth -vendor: espressif +vendor: luatos diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig new file mode 100644 index 00000000000000..ef633ce56a18e2 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.dts b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts similarity index 100% rename from boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.dts rename to boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.dts diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml new file mode 100644 index 00000000000000..7910c6ac8eedad --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb.yaml @@ -0,0 +1,22 @@ +identifier: esp32c3_luatos_core/esp32c3/usb +name: ESP32C3 LuatOS Core USB +type: mcu +arch: riscv +toolchain: + - zephyr +supported: + - adc + - gpio + - i2c + - watchdog + - uart + - dma + - pwm + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: luatos diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig new file mode 100644 index 00000000000000..ef633ce56a18e2 --- /dev/null +++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/support/openocd.cfg b/boards/luatos/esp32c3_luatos_core/support/openocd.cfg similarity index 100% rename from boards/riscv/esp32c3_luatos_core/support/openocd.cfg rename to boards/luatos/esp32c3_luatos_core/support/openocd.cfg diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig b/boards/luatos/esp32s3_luatos_core/Kconfig new file mode 100644 index 00000000000000..96c55ea054dcc6 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_LUATOS_CORE + select SOC_ESP32S3_PROCPU if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB + select SOC_ESP32S3_APPCPU if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig b/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig new file mode 100644 index 00000000000000..093805f235b016 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/Kconfig.defconfig @@ -0,0 +1,26 @@ +# ESP32S3 Core board configuration + +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_PROCPU_USB + +if BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU || BOARD_ESP32S3_LUATOS_CORE_ESP32S3_APPCPU_USB diff --git a/boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core b/boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core new file mode 100644 index 00000000000000..98ca53fefcadd4 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/Kconfig.esp32s3_luatos_core @@ -0,0 +1,5 @@ +# Copyright (c) 2023 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S3_LUATOS_CORE + select SOC_ESP32S3_MINI_N8 diff --git a/boards/xtensa/esp_wrover_kit/Kconfig.sysbuild b/boards/luatos/esp32s3_luatos_core/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/esp_wrover_kit/Kconfig.sysbuild rename to boards/luatos/esp32s3_luatos_core/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s2_saola/board.cmake b/boards/luatos/esp32s3_luatos_core/board.cmake similarity index 100% rename from boards/xtensa/esp32s2_saola/board.cmake rename to boards/luatos/esp32s3_luatos_core/board.cmake diff --git a/boards/luatos/esp32s3_luatos_core/board.yml b/boards/luatos/esp32s3_luatos_core/board.yml new file mode 100644 index 00000000000000..cd29886c969a44 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/board.yml @@ -0,0 +1,10 @@ +board: + name: esp32s3_luatos_core + vendor: luatos + socs: + - name: esp32s3 + variants: + - name: usb + cpucluster: procpu + - name: usb + cpucluster: appcpu diff --git a/boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg b/boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg rename to boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core.jpg diff --git a/boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg b/boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg rename to boards/luatos/esp32s3_luatos_core/doc/img/esp32s3_luatos_core_pinout.jpg diff --git a/boards/luatos/esp32s3_luatos_core/doc/index.rst b/boards/luatos/esp32s3_luatos_core/doc/index.rst new file mode 100644 index 00000000000000..4921e11e915328 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/doc/index.rst @@ -0,0 +1,292 @@ +.. _esp32s3_luatos_core: + +ESP32S3-Luatos-Core +################### + +Overview +******** + +The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3. +The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalities. +For more information, check `ESP32S3-LUATOS-CORE`_ (chinese) + +.. image:: img/esp32s3_luatos_core.jpg + :align: center + :alt: esp32s3_luatos_core + +Hardware +******** + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +ESP32S3-LUATOS-CORE includes the following features: + +- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz +- Additional vector instructions support for AI acceleration +- 512KB of SRAM +- 384KB of ROM +- 8MB of PSRAM +- 16MB of FLASH +- Wi-Fi 802.11b/g/n +- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate + +Digital interfaces: + +- 4x SPI +- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 +- 1x DVP 8-bit ~16-bit camera interface +- 3x UART +- 2x I2C +- 2x I2S +- 1x RMT (TX/RX) +- 1x pulse counter +- LED PWM controller, up to 8 channels +- 1x USB Port with USB switcher, supporting following modes: + - 1x full-speed USB OTG or 1x USB Serial/JTAG controller + - USB to serial chip CH343 +- 2x MCPWM +- 1x SDIO host controller with 2 slots +- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels +- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) +- 2x Blue LED + +Analog interfaces: + +- 2x 12-bit SAR ADCs, up to 20 channels + +Timers: + +- 4x 54-bit general-purpose timers +- 1x 52-bit system timer +- 3x watchdog timers + +Low Power: + +- Power Management Unit with five power modes +- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM + +Security: + +- Secure boot +- Flash encryption +- 4-Kbit OTP, up to 1792 bits for users +- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) + +For more information, check the datasheet at `ESP32-S3 Datasheet`_. + +.. image:: img/esp32s3_luatos_core_pinout.jpg + :align: center + :alt: esp32s3_luatos_core_pinout + +Supported Features +================== + +Current Zephyr's ESP32S3-LUATOS-Core board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ +| USB-CDC | on-chip | serial | ++------------+------------+-------------------------------------+ + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: esp32s3_luatos_core + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: build + +If CH343 chip is disabled, You need use the following command to build: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core_usb/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``esp32s3_luatos_core`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! esp32s3_luatos_core + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: esp32s3_luatos_core/esp32s3/procpu + :goals: debug + +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd +.. _`ESP32S3-LUATOS-CORE`: https://wiki.luatos.com/chips/esp32s3/board.html + +References +********** + +.. _ESP32S3-LUATOS-CORE User Guide: https://wiki.luatos.com/chips/esp32s3/board.html +.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf +.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi rename to boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core-pinctrl.dtsi diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dtsi rename to boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.dts new file mode 100644 index 00000000000000..e33c7f43401af0 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "ESP32S3 Luatos Core APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.yaml new file mode 100644 index 00000000000000..05aac04c00fb8a --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_luatos_core/esp32s3/appcpu +name: ESP32-S3 LuatOS Core +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.dts new file mode 100644 index 00000000000000..7a251b40e04f16 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "ESP32S3 Luatos Core USB APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.yaml new file mode 100644 index 00000000000000..cb2ac02717b5fc --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb.yaml @@ -0,0 +1,27 @@ +identifier: esp32s3_luatos_core/esp32s3/appcpu/usb +name: ESP32-S3 LuatOS Core USB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_appcpu_usb_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.dts new file mode 100644 index 00000000000000..8c44d0cebd7943 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "esp32s3_luatos_core.dtsi" + +/ { + model = "ESP32S3 Luatos Core PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + led0 = &led0; + led1 = &led1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + uart-0 = &uart0; + sw0 = &button0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.yaml new file mode 100644 index 00000000000000..2a1bb02cc2f2c9 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu.yaml @@ -0,0 +1,22 @@ +identifier: esp32s3_luatos_core/esp32s3/procpu +name: ESP32-S3 LuatOS Core +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_defconfig new file mode 100644 index 00000000000000..d789bab1824a6f --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.dts b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.dts new file mode 100644 index 00000000000000..0a707724f9f0a5 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.dts @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2023 YuLong Yao + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include "esp32s3_luatos_core.dtsi" + +/ { + model = "ESP32S3 Luatos Core USB PROCPU"; + compatible = "espressif,esp32s3"; + + aliases { + led0 = &led0; + led1 = &led1; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + uart-0 = &usb_serial; + sw0 = &button0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + }; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "disabled"; +}; diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.yaml b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.yaml new file mode 100644 index 00000000000000..f1cd4d19d5a6b2 --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb.yaml @@ -0,0 +1,22 @@ +identifier: esp32s3_luatos_core/esp32s3/procpu/usb +name: ESP32-S3 LuatOS Core USB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: luatos diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb_defconfig new file mode 100644 index 00000000000000..d789bab1824a6f --- /dev/null +++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_esp32s3_procpu_usb_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/support/openocd.cfg b/boards/luatos/esp32s3_luatos_core/support/openocd.cfg similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/support/openocd.cfg rename to boards/luatos/esp32s3_luatos_core/support/openocd.cfg diff --git a/boards/luatos/index.rst b/boards/luatos/index.rst new file mode 100644 index 00000000000000..3a9934889e477d --- /dev/null +++ b/boards/luatos/index.rst @@ -0,0 +1,10 @@ +.. _boards-luatos: + +Luatos +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/m5stack/index.rst b/boards/m5stack/index.rst new file mode 100644 index 00000000000000..e4d1a57d992859 --- /dev/null +++ b/boards/m5stack/index.rst @@ -0,0 +1,10 @@ +.. _boards-m5stack: + +M5Stack +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/m5stack/m5stack_atoms3/Kconfig b/boards/m5stack/m5stack_atoms3/Kconfig new file mode 100644 index 00000000000000..651e5528b9463b --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3 + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig new file mode 100644 index 00000000000000..c0dadaceeb4d1f --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/Kconfig.defconfig @@ -0,0 +1,28 @@ +# M5Stack AtomS3 board configuration +# Copyright (c) 2023 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU + +config LV_COLOR_16_SWAP + default y if LVGL + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STACK_ATOMS3_ESP32S3_PROCPU + +if BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_ATOMS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3/Kconfig.m5stack_atoms3 b/boards/m5stack/m5stack_atoms3/Kconfig.m5stack_atoms3 new file mode 100644 index 00000000000000..e858deba10db3d --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/Kconfig.m5stack_atoms3 @@ -0,0 +1,7 @@ +# M5Stack AtomS3 board configuration + +# Copyright (c) 2023 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3 + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.sysbuild b/boards/m5stack/m5stack_atoms3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/heltec_wifi_lora32_v2/Kconfig.sysbuild rename to boards/m5stack/m5stack_atoms3/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s3_devkitm/board.cmake b/boards/m5stack/m5stack_atoms3/board.cmake similarity index 100% rename from boards/xtensa/esp32s3_devkitm/board.cmake rename to boards/m5stack/m5stack_atoms3/board.cmake diff --git a/boards/m5stack/m5stack_atoms3/board.yml b/boards/m5stack/m5stack_atoms3/board.yml new file mode 100644 index 00000000000000..4126aa17d2e19e --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_atoms3 + vendor: m5stack + socs: + - name: esp32s3 diff --git a/boards/xtensa/m5stack_atoms3/doc/img/m5stack_atoms3.webp b/boards/m5stack/m5stack_atoms3/doc/img/m5stack_atoms3.webp similarity index 100% rename from boards/xtensa/m5stack_atoms3/doc/img/m5stack_atoms3.webp rename to boards/m5stack/m5stack_atoms3/doc/img/m5stack_atoms3.webp diff --git a/boards/m5stack/m5stack_atoms3/doc/index.rst b/boards/m5stack/m5stack_atoms3/doc/index.rst new file mode 100644 index 00000000000000..c053f73c101773 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/doc/index.rst @@ -0,0 +1,136 @@ +.. _m5stack_atoms3: + +M5Stack AtomS3 +############## + +Overview +******** + +M5Stack AtomS3 is an ESP32-based development board from M5Stack. + +It features the following integrated components: + +- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) +- 512KB of SRAM +- 384KB of ROM +- 8MB of Flash +- LCD IPS TFT 0.85", 128x128 px screen (ST7789 compatible) +- 6-axis IMU MPU6886 +- Infrared emitter + + +.. figure:: img/m5stack_atoms3.webp + :align: center + :alt: M5Stack AtomS3 + + M5Stack AtomS3 + + +Supported Features +================== + +The Zephyr m5stack_atoms3 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5Stack AtomS3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: shell + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_atoms3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3/esp32s3/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_atoms3 + +Debugging +--------- + +M5Stack AtomS3 debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5Stack AtomS3 schematic `_ +- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3/grove_connectors.dtsi b/boards/m5stack/m5stack_atoms3/grove_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3/grove_connectors.dtsi rename to boards/m5stack/m5stack_atoms3/grove_connectors.dtsi diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi b/boards/m5stack/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi rename to boards/m5stack/m5stack_atoms3/m5stack_atoms3-pinctrl.dtsi diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.dts new file mode 100644 index 00000000000000..91bcff6c0079db --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "M5Stack AtomS3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.yaml b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000000..a8efc9aad007d9 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_atoms3/esp32s3/appcpu +name: M5Stack AtomS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.dts new file mode 100644 index 00000000000000..1b5a5da32da108 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.dts @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2023 Benjamin Cabé + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_atoms3-pinctrl.dtsi" +#include "grove_connectors.dtsi" +#include + +/ { + model = "M5Stack AtomS3 PROCPU"; + compatible = "m5stack,atoms3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &st7789v; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + accel0 = &mpu6886; + }; + + gpio_keys { + compatible = "gpio-keys"; + + /* This is the button that's underneath the LCD display */ + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // G42 + zephyr,code = ; + }; + }; + + /* Regulators */ + lcd_backlight_en { + compatible = "regulator-fixed"; + regulator-name = "lcd_backlight_enable"; + enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + mpu6886: mpu6886@68 { + compatible = "invensense,mpu6050"; + reg = <0x68>; + status = "okay"; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + + st7789v: st7789v@0 { + compatible = "sitronix,st7789v"; + reg = <0>; + spi-max-frequency = <27000000>; + cmd-data-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; /* G33 */ + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* G34 */ + + width = <128>; + height = <128>; + x-offset = <2>; + y-offset = <1>; + + vcom = <0x28>; + gctrl = <0x35>; + vrhs = <0x10>; + vdvs = <0x20>; + mdac = <0x00>; + gamma = <0x01>; + colmod = <0x55>; + lcm = <0x0c>; + porch-param = [0c 0c 00 33 33]; + cmd2en-param = [5a 69 02 00]; + pwctrl1-param = [a4 a1]; + pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; + nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; + ram-param = [00 E0]; + rgb-param = [40 02 14]; + }; + +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.yaml b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.yaml new file mode 100644 index 00000000000000..4be28b02f83eb4 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu.yaml @@ -0,0 +1,21 @@ +identifier: m5stack_atoms3/esp32s3/procpu +name: M5Stack AtomS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - regulator + - uart + - pinmux + - nvs + - display +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu_defconfig b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000000..88c69e52e8c2e0 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_esp32s3_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GPIO=y +CONFIG_REGULATOR=y # for LCD backlight + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig b/boards/m5stack/m5stack_atoms3_lite/Kconfig new file mode 100644 index 00000000000000..bcf86cfa018443 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3_LITE + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig new file mode 100644 index 00000000000000..8039b4762cde2a --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig.defconfig @@ -0,0 +1,28 @@ +# M5Stack AtomS3 Lite board configuration +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +config KERNEL_MEM_POOL + default y + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STACK_ATOMS3_LITE_ESP32S3_PROCPU + +if BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_ATOMS3_LITE_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_atoms3_lite/Kconfig.m5stack_atoms3_lite b/boards/m5stack/m5stack_atoms3_lite/Kconfig.m5stack_atoms3_lite new file mode 100644 index 00000000000000..0d21265e495add --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/Kconfig.m5stack_atoms3_lite @@ -0,0 +1,6 @@ +# M5Stack AtomS3 Lite board configuration +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_ATOMS3_LITE + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.sysbuild b/boards/m5stack/m5stack_atoms3_lite/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.sysbuild rename to boards/m5stack/m5stack_atoms3_lite/Kconfig.sysbuild diff --git a/boards/xtensa/esp32s3_luatos_core/board.cmake b/boards/m5stack/m5stack_atoms3_lite/board.cmake similarity index 100% rename from boards/xtensa/esp32s3_luatos_core/board.cmake rename to boards/m5stack/m5stack_atoms3_lite/board.cmake diff --git a/boards/m5stack/m5stack_atoms3_lite/board.yml b/boards/m5stack/m5stack_atoms3_lite/board.yml new file mode 100644 index 00000000000000..c9204d5159c9db --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_atoms3_lite + vendor: m5stack + socs: + - name: esp32s3 diff --git a/boards/xtensa/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp b/boards/m5stack/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp rename to boards/m5stack/m5stack_atoms3_lite/doc/img/m5stack_atoms3_lite.webp diff --git a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst new file mode 100644 index 00000000000000..204d8e5bbec506 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst @@ -0,0 +1,134 @@ +.. _m5stack_atoms3_lite: + +M5Stack AtomS3 Lite +################### + +Overview +******** + +M5Stack AtomS3 Lite is an ESP32-based development board from M5Stack. + +It features the following integrated components: + +- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) +- 512KB of SRAM +- 384KB of ROM +- 8MB of Flash +- RGB Status-LED + + +.. figure:: img/m5stack_atoms3_lite.webp + :align: center + :alt: M5Stack AtomS3 Lite + + M5Stack AtomS3 Lite + + +Supported Features +================== + +The Zephyr m5stack_atoms3_lite board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5Stack AtomS3 Lite, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: shell + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3_lite/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_atoms3_lite`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_atoms3_lite/esp32s3/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_atoms3_lite + +Debugging +--------- + +M5Stack AtomS3 Lite debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5Stack AtomS3 Lite schematic `_ +- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3_lite/grove_connectors.dtsi b/boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/grove_connectors.dtsi rename to boards/m5stack/m5stack_atoms3_lite/grove_connectors.dtsi diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi rename to boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite-pinctrl.dtsi diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.dts new file mode 100644 index 00000000000000..994c9b9a3b2b26 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "M5Stack AtomS3 Lite APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.yaml b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.yaml new file mode 100644 index 00000000000000..0a641e9ef12755 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_atoms3_lite/esp32s3/appcpu +name: M5Stack AtomS3-Lite +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.dts new file mode 100644 index 00000000000000..430de46a5548c6 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.dts @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2023 Benjamin Cabé + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_atoms3_lite-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "M5Stack AtomS3 Lite PROCPU"; + compatible = "m5stack,atoms3_lite"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + i2c-0 = &i2c0; + led-strip = &status_rgb_led; + }; + + buttons { + compatible = "gpio-keys"; + debounce-interval-ms = <100>; + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + line-idle-low; + pinctrl-0 = <&spim3_ws2812_led>; + pinctrl-names = "default"; + + status_rgb_led: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + reg = <0>; + spi-max-frequency = ; + + chain-length = <1>; + color-mapping = , + , + ; + spi-one-frame = ; + spi-zero-frame = ; + }; +}; +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.yaml b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.yaml new file mode 100644 index 00000000000000..3012207d36de95 --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu.yaml @@ -0,0 +1,23 @@ +identifier: m5stack_atoms3_lite/esp32s3/procpu +name: M5Stack AtomS3-Lite +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - counter + - watchdog + - entropy + - pwm + - pinmux + - nvs + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu_defconfig b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu_defconfig new file mode 100644 index 00000000000000..d789bab1824a6f --- /dev/null +++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_esp32s3_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/m5stack/m5stack_core2/Kconfig b/boards/m5stack/m5stack_core2/Kconfig new file mode 100644 index 00000000000000..abe38faa5ec1d7 --- /dev/null +++ b/boards/m5stack/m5stack_core2/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_CORE2 + select SOC_ESP32_PROCPU if BOARD_M5STACK_CORE2_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_M5STACK_CORE2_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_core2/Kconfig.defconfig b/boards/m5stack/m5stack_core2/Kconfig.defconfig new file mode 100644 index 00000000000000..6057cf0a0f512e --- /dev/null +++ b/boards/m5stack/m5stack_core2/Kconfig.defconfig @@ -0,0 +1,53 @@ +# M5Stack Core2 board configuration +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_CORE2_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 65536 if BT + default 4096 + +config KERNEL_MEM_POOL + default y + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +config REGULATOR_AXP192_INIT_PRIORITY + default 81 + +config GPIO_HOGS_INIT_PRIORITY + default 82 + +config INPUT_FT5336_INTERRUPT + default y if INPUT + +config INPUT + default y + +config LV_COLOR_16_SWAP + default y if LVGL + +# Increase initialization priority of MIPI DBI device, so that it initializes +# after the GPIO controller +if MIPI_DBI + +config MIPI_DBI_INIT_PRIORITY + default 82 + +endif # MIPI_DBI + +endif # BOARD_M5STACK_CORE2_ESP32_PROCPU + +if BOARD_M5STACK_CORE2_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_CORE2_ESP32_APPCPU diff --git a/boards/m5stack/m5stack_core2/Kconfig.m5stack_core2 b/boards/m5stack/m5stack_core2/Kconfig.m5stack_core2 new file mode 100644 index 00000000000000..f6858d5a928518 --- /dev/null +++ b/boards/m5stack/m5stack_core2/Kconfig.m5stack_core2 @@ -0,0 +1,7 @@ +# M5Stack Core2 board configuration + +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_CORE2 + select SOC_ESP32_D0WD_V3 diff --git a/boards/xtensa/esp_wrover_kit/board.cmake b/boards/m5stack/m5stack_core2/board.cmake similarity index 100% rename from boards/xtensa/esp_wrover_kit/board.cmake rename to boards/m5stack/m5stack_core2/board.cmake diff --git a/boards/m5stack/m5stack_core2/board.yml b/boards/m5stack/m5stack_core2/board.yml new file mode 100644 index 00000000000000..1ff253f820177b --- /dev/null +++ b/boards/m5stack/m5stack_core2/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_core2 + vendor: m5stack + socs: + - name: esp32 diff --git a/boards/xtensa/m5stack_core2/doc/img/m5stack_core2.webp b/boards/m5stack/m5stack_core2/doc/img/m5stack_core2.webp similarity index 100% rename from boards/xtensa/m5stack_core2/doc/img/m5stack_core2.webp rename to boards/m5stack/m5stack_core2/doc/img/m5stack_core2.webp diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst new file mode 100644 index 00000000000000..9dc66f5c9bae74 --- /dev/null +++ b/boards/m5stack/m5stack_core2/doc/index.rst @@ -0,0 +1,197 @@ +.. _m5stack_core2: + +M5Stack Core2 +############# + +Overview +******** + +M5Stack Core2 is an ESP32-based development board from M5Stack. It is the successor for the Core module. + +M5Stack Core2 features the following integrated components: + +- ESP32-D0WDQ6-V3 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) +- PSRAM 8MB +- Flash 16MB +- LCD IPS TFT 2", 320x240 px screen (ILI9342C) +- Touch screen (FT6336U) +- PMU AXP192 +- Audio NS4168 amplifier (1W-092 speaker) +- Vibration motor +- RTC BM8563 +- USB CP2104 +- SD-Card slot +- IMO 6-axis IMU MPU6886 +- MIC SPM1423 +- Battery 390mAh 3,7V + +.. figure:: img/m5stack_core2.webp + :align: center + :alt: M5Stack-Core2 + :width: 400 px + + M5Stack-Core2 module + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the M5Stack Core2 board. + +.. _M5Core2 Schematic: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/schematic/Core/CORE2_V1.0_SCH.pdf +.. _MPU-ESP32: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32_datasheet_en_v3.9.pdf +.. _TOUCH-FT6336U: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/Ft6336GU_Firmware%20外部寄存器_20151112-%20EN.xlsx +.. _SND-NS4168: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/NS4168_CN_datasheet.pdf +.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf +.. _LCD-ILI9342C: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ILI9342C-ILITEK.pdf +.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf +.. _RTC-BM8563: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/BM8563_V1.1_cn.pdf +.. _SY7088: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SY7088-Silergy.pdf +.. _PMU-AXP192: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/AXP192_datasheet_en.pdf +.. _VIB-1072_RFN01: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/1027RFN01-33d.pdf + ++------------------+--------------------------------------------------------------------------+------------+ +| Key Component | Description | Status | ++==================+==========================================================================+============+ +|| ESP32-D0WDQ6-V2 || This `MPU-ESP32`_ module provides complete Wi-Fi and Bluetooth || supported | +|| module || functionalities and integrates a 16-MB SPI flash. || | ++------------------+--------------------------------------------------------------------------+------------+ +|| 32.768 kHz RTC || External precision 32.768 kHz crystal oscillator serves as a clock with || supported | +|| || low-power consumption while the chip is in Deep-sleep mode. || | ++------------------+--------------------------------------------------------------------------+------------+ +| Status LED | One user LED connected to the GPIO pin. | supported | ++------------------+--------------------------------------------------------------------------+------------+ +|| USB Port || USB interface. Power supply for the board as well as the || supported | +|| || communication interface between a computer and the board. || | +|| || Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 || | ++------------------+--------------------------------------------------------------------------+------------+ +| Reset button | Reset button | supported | ++------------------+--------------------------------------------------------------------------+------------+ +| Power Switch | Power on/off button. | supported | ++------------------+--------------------------------------------------------------------------+------------+ +|| LCD screen || Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) || supported | +|| || controlled via SPI interface || | ++------------------+--------------------------------------------------------------------------+------------+ +| SD-Card slot | SD-Card connection via SPI-mode. | supported | ++------------------+--------------------------------------------------------------------------+------------+ +|| 6-axis IMU || The `MPU-6886`_ is a 6-axis motion tracker (6DOF IMU) device that || todo | +|| MPU6886 || combines a 3-axis gyroscope and a 3-axis accelerometer. || | +|| || For details please refer to :ref:`m5stack_core2_ext` || | ++------------------+--------------------------------------------------------------------------+------------+ +|| Built-in || The `SPM-1423`_ I2S driven microphone. || todo | +|| microphone || || | ++------------------+--------------------------------------------------------------------------+------------+ +| Built-in speaker | 1W speaker for audio output via I2S interface. | todo | ++------------------+--------------------------------------------------------------------------+------------+ + +Supported Features +================== + +The Zephyr m5stack_core2 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5Stack Core2, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_core2/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_core2`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_core2/esp32/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_core2 + +Debugging +--------- + +M5Stack Core2 debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5StickC PLUS schematic `_ (WEBP) +- `ESP32-PICO-D4 Datasheet `_ (PDF) +- `M5StickC PLUS docs `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_core2/grove_connectors.dtsi b/boards/m5stack/m5stack_core2/grove_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_core2/grove_connectors.dtsi rename to boards/m5stack/m5stack_core2/grove_connectors.dtsi diff --git a/boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi b/boards/m5stack/m5stack_core2/m5stack_core2-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_core2/m5stack_core2-pinctrl.dtsi rename to boards/m5stack/m5stack_core2/m5stack_core2-pinctrl.dtsi diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.dts new file mode 100644 index 00000000000000..cd5cf5d0bf228c --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "M5Stack Core2 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.yaml b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.yaml new file mode 100644 index 00000000000000..8e5a51d07c7f0e --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_core2/esp32/appcpu +name: M5Stack Core2 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts new file mode 100644 index 00000000000000..0ca3efab6cdc77 --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.dts @@ -0,0 +1,285 @@ +/* + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_core2-pinctrl.dtsi" +#include "grove_connectors.dtsi" +#include "m5stack_mbus_connectors.dtsi" +#include +#include + +/ { + model = "M5Stack Core2 PROCPU"; + compatible = "m5stack,core2"; + + aliases { + pwr-led = &pwr_led; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + rtc = &pfc8563_rtc; + led0 = &led_pwr; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,display = &ili9342c; + zephyr,code-partition = &slot0_partition; + zephyr,rtc = &pfc8563_rtc; + }; + + leds { + compatible = "gpio-leds"; + led_pwr: led_pwr { + gpios = <&axp192_gpio 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + label = "Power LED"; + }; + }; + + lvgl_pointer { + compatible = "zephyr,lvgl-pointer-input"; + input = <&ft5336_touch>; + swap-xy; + }; + + mipi_dbi { + compatible = "zephyr,mipi-dbi-spi"; + dc-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; + reset-gpios = <&axp192_gpio 4 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + spi-dev = <&spi3>; + write-only; + #address-cells = <1>; + #size-cells = <0>; + + ili9342c: ili9342c@0 { + compatible = "ilitek,ili9342c"; + mipi-max-frequency = <30000000>; + reg = <0>; + vin-supply = <&lcd_bg>; + pixel-format = ; + display-inversion; + width = <320>; + height = <240>; + rotation = <0>; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&psram0 { + reg = <0x3f800000 DT_SIZE_M(8)>; + status = "disabled"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; + pinctrl-names = "default"; +}; + +&uart1 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + scl-timeout-us = <0>; + pinctrl-names = "default"; + + pfc8563_rtc: pfc8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; + + axp192_pmic: axp192@34 { + compatible = "x-powers,axp192"; + reg = <0x34>; + status = "okay"; + + axp192_regulator: axp192_regulator { + compatible = "x-powers,axp192-regulator"; + status = "okay"; + + vdd_mcu: DCDC1 { + regulator-init-microvolt = <3350000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3400000>; + regulator-initial-mode = ; + regulator-boot-on; + regulator-always-on; + }; + + lcd_bg: DCDC3 { + regulator-init-microvolt = <2800000>; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + v_peri: LDO2 { + regulator-init-microvolt = <3300000>; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + vib_motor: LDO3 { + regulator-init-microvolt = <2800000>; + }; + }; + + axp192_gpio: axp192_gpio { + compatible = "x-powers,axp192-gpio"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <5>; + status = "okay"; + + pwr_led: axp192_gpio1 { + gpio-hog; + gpios = <1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; + output-high; + line-name = "pwr-led"; + }; + + bus_pwr_en: axp192_gpio0 { + gpio-hog; + gpios = <0 0>; + input; + }; + }; + }; + + ft5336_touch: ft5336@38 { + compatible = "focaltech,ft5336"; + reg = <0x38>; + int-gpios = <&gpio1 7 0>; + }; +}; + +&i2c1 { + status = "disabled"; + clock-frequency = ; + sda-gpios = <&gpio1 0 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio1 1 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + dma-enabled; + clock-frequency = <20000000>; + cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>, + <&gpio0 4 GPIO_ACTIVE_LOW>; + + sdhc0: sdhc@1 { + compatible = "zephyr,sdhc-spi-slot"; + reg = <1>; + status = "okay"; + spi-max-frequency = <20000000>; + mmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + + }; +}; + + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + reg = <0 DT_SIZE_M(16)>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + /* 14MB storage */ + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00db0000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.yaml b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.yaml new file mode 100644 index 00000000000000..b5f7a37910dde1 --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu.yaml @@ -0,0 +1,20 @@ +identifier: m5stack_core2/esp32/procpu +name: M5Stack Core2 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - regulator + - uart + - pinmux + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu_defconfig new file mode 100644 index 00000000000000..008eb0afc9e3b9 --- /dev/null +++ b/boards/m5stack/m5stack_core2/m5stack_core2_esp32_procpu_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0 + +CONFIG_GPIO=y + +CONFIG_REGULATOR=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +# for debugging +CONFIG_SHELL=y diff --git a/boards/xtensa/m5stack_core2/m5stack_mbus_connectors.dtsi b/boards/m5stack/m5stack_core2/m5stack_mbus_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_core2/m5stack_mbus_connectors.dtsi rename to boards/m5stack/m5stack_core2/m5stack_mbus_connectors.dtsi diff --git a/boards/xtensa/m5stack_core2/support/openocd.cfg b/boards/m5stack/m5stack_core2/support/openocd.cfg similarity index 100% rename from boards/xtensa/m5stack_core2/support/openocd.cfg rename to boards/m5stack/m5stack_core2/support/openocd.cfg diff --git a/boards/m5stack/m5stack_stamps3/Kconfig b/boards/m5stack/m5stack_stamps3/Kconfig new file mode 100644 index 00000000000000..3bc66a42ed475a --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_STAMPS3 + select SOC_ESP32S3_PROCPU if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_stamps3/Kconfig.defconfig b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig new file mode 100644 index 00000000000000..70493b8d4751db --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/Kconfig.defconfig @@ -0,0 +1,28 @@ +# M5Stack StampS3 board configuration +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +config KERNEL_MEM_POOL + default y + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STACK_STAMPS3_ESP32S3_PROCPU + +if BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STACK_STAMPS3_ESP32S3_APPCPU diff --git a/boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 b/boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 new file mode 100644 index 00000000000000..a48130faf89c0c --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/Kconfig.m5stack_stamps3 @@ -0,0 +1,7 @@ +# M5Stack StampS3 board configuration + +# Copyright (c) 2023 Martin Kiepfer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STACK_STAMPS3 + select SOC_ESP32S3_FN8 diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/board.cmake b/boards/m5stack/m5stack_stamps3/board.cmake similarity index 100% rename from boards/xtensa/heltec_wireless_stick_lite_v3/board.cmake rename to boards/m5stack/m5stack_stamps3/board.cmake diff --git a/boards/m5stack/m5stack_stamps3/board.yml b/boards/m5stack/m5stack_stamps3/board.yml new file mode 100644 index 00000000000000..e723d91c19a0ed --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stack_stamps3 + vendor: m5stack + socs: + - name: esp32s3 diff --git a/boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3.webp b/boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3.webp similarity index 100% rename from boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3.webp rename to boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3.webp diff --git a/boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp b/boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp similarity index 100% rename from boards/xtensa/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp rename to boards/m5stack/m5stack_stamps3/doc/img/m5stack_stamps3_header.webp diff --git a/boards/m5stack/m5stack_stamps3/doc/index.rst b/boards/m5stack/m5stack_stamps3/doc/index.rst new file mode 100644 index 00000000000000..59e1d5145aab54 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/doc/index.rst @@ -0,0 +1,199 @@ +.. _m5stack_stamps3: + +M5Stack StampS3 +############### + +Overview +******** + +M5Stack StampS3 is an ESP32-based development board from M5Stack. +It features the following integrated components: + +- ESP32-S3FN8 chip (240MHz dual core) +- 512KB SRAM +- 384KB ROM +- 8MB Flash +- Wi-Fi +- Bluetooth +- User-Button + +.. figure:: img/m5stack_stamps3.webp + :align: center + :alt: M5Stack StampS3 + :width: 400 px + + M5Stack StampS3 module + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the M5Stack StampS3 module. + ++---------------+-----------------------------------------------------------------+-----------+ +| Key Component | Description | Status | ++===============+=================================================================+===========+ +| ESP32-S3FN8 | This MPU-ESP32S3 module provides complete Wi-Fi and Bluetooth | supported | +| module | functionalities and integrates a 8MB flash. | | ++---------------+-----------------------------------------------------------------+-----------+ +| Status LED | One user LED connected via :dtcompatible:`worldsemi,ws2812-spi` | supported | +| | interface (``led-strip``). | | ++---------------+-----------------------------------------------------------------+-----------+ +| USB Port | USB interface. Power supply for the board as well as the | supported | +| | communication interface between a computer and the board. | | ++---------------+-----------------------------------------------------------------+-----------+ +| User button | User button (``sw0``) | supported | ++---------------+-----------------------------------------------------------------+-----------+ + +Main connector header +===================== + +The Zephyr m5stack_stamps3 board can be used on various applications. It +therefore publishes a header definition to be used in different shields: +:dtcompatible:`m5stack,stamps3-header`. + +.. figure:: img/m5stack_stamps3_header.webp + :align: center + :alt: M5Stack StampS3 Header + :width: 400 px + + M5Stack StampS3 connector header + +Following interfaces are being exported for this header: + +- ``m5stack_stamps3_clkout0``: PWM output with 2 channels (0 and 2). +- ``m5stack_stamps3_spilcd``: SPI interface for interfacing LCDs. Consists of a + CLK, MOSI and CS signal. +- ``m5stack_stamps3_i2c0`` and ``m5stack_stamps3_i2c1``: I2C interfaces (SDA, SCL). +- ``m5stack_stamps3_uart0``: UART interface (RXD, TXD). +- ``m5stack_stamps3_header``: All GPIOs are of course accessible via main header + definition. + ++-----+-----------------------------------------+-----+---------------------------------+ +| Pin | Functions | Pin | Functions | ++=====+=========================================+=====+=================================+ +| 1 | | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 2 | | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 3 | ``m5stack_stamps3_clkout0`` - Channel 0 | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 4 | | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 5 | ``m5stack_stamps3_spilcd`` - MOSI | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 6 | ``m5stack_stamps3_spilcd`` - CLK | | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 7 | ``m5stack_stamps3_spilcd`` - CS | 28 | **3V3** | ++-----+-----------------------------------------+-----+---------------------------------+ +| 8 | | 27 | ``m5stack_stamps3_uart0`` - TXD | ++-----+-----------------------------------------+-----+---------------------------------+ +| 9 | ``m5stack_stamps3_clkout0`` - Channel 2 | 26 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 10 | | 25 | ``m5stack_stamps3_uart0`` - RXD | ++-----+-----------------------------------------+-----+---------------------------------+ +| 11 | **GND** | 24 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 12 | ``m5stack_stamps3_i2c1`` - SDA | 23 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 13 | **5V** | 22 | **EN** | ++-----+-----------------------------------------+-----+---------------------------------+ +| 14 | ``m5stack_stamps3_i2c1`` - SCL | 21 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 15 | ``m5stack_stamps3_i2c0`` - SDA | 20 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 16 | | 19 | | ++-----+-----------------------------------------+-----+---------------------------------+ +| 17 | ``m5stack_stamps3_i2c0`` - SCL | 18 | **GND** | ++-----+-----------------------------------------+-----+---------------------------------+ + +Power supply +============ + +M5Stack StampS3 requires a single 5V input power supply. The module internally +features a DCDC (MUN3CAD01-SC) to generate the 3.3V needed for the MCU. + +The **EN** signal (Pin 22) is an active low signal to enable the **3V3** power +supply. If this pin is pulled low this main 3.3V power supply for the MCU will be +deactivated. It is internally equipped with a pull-up and can hence be left open +if unused. + +Start Application Development +***************************** + +Before powering up your M5Stack StampS3, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +------------------- + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_stamps3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stack_stamps3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stack_stamps3/esp32s3/procpu + :goals: flash + +The baud rate of 921600bps is set by default. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stack_stamps3 + +Debugging +--------- + +M5Stack StampS3 exports a JTAG-interface via Pins 19 (MTCK), 21 (MTDO), 23 +(MTDI), 25 (MTMS). + +.. note:: + + Please note that additional JTAG equipment is needed to utilize JTAG. Refer to + the ESP32S3 datasheet and the M5Stack StampS3 documentation for details. + +Related Documents +***************** + +- `M5Stack StampS3 schematic `_ +- `M5Stack StampS3 `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi b/boards/m5stack/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi rename to boards/m5stack/m5stack_stamps3/m5stack_stamps3-pinctrl.dtsi diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3_connectors.dtsi b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_connectors.dtsi similarity index 100% rename from boards/xtensa/m5stack_stamps3/m5stack_stamps3_connectors.dtsi rename to boards/m5stack/m5stack_stamps3/m5stack_stamps3_connectors.dtsi diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.dts new file mode 100644 index 00000000000000..a9e590b9bbf8b0 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "M5Stack StampS3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.yaml b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000000..eb4fcfcd02809c --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stack_stamps3/esp32s3/appcpu +name: M5Stack StampS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.dts new file mode 100644 index 00000000000000..f832f4618ba4bf --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.dts @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2023 Martin Kiepfer + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stack_stamps3-pinctrl.dtsi" +#include "m5stack_stamps3_connectors.dtsi" +#include +#include +#include +#include + +/ { + model = "M5Stack StampS3 PROCPU"; + compatible = "m5stack,stamps3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + sw0 = &user_button_0; + watchdog0 = &wdt0; + //pwm-0 = &ledc0; + i2c-0 = &i2c0; + led-strip = &status_rgb_led; + }; + + gpio_keys { + compatible = "gpio-keys"; + + /* This is the button that's underneath the LCD display */ + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&mcpwm0 { + status = "okay"; + pinctrl-0 = <&mcpwm0_default>; + pinctrl-names = "default"; + prescale = <255>; + prescale-timer0 = <100>; + prescale-timer1 = <100>; +}; + +&ledc0 { + pinctrl-0 = <&ledc0_default>; + pinctrl-names = "default"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + channel0@0 { + reg = <0x0>; + timer = <0>; + }; + channel0@1 { + reg = <0x1>; + timer = <0>; + }; +}; + + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + line-idle-low; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; + + status_rgb_led: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + reg = <0x0>; + spi-max-frequency = ; + + chain-length = <1>; + color-mapping = , + , + ; + spi-one-frame = ; + spi-zero-frame = ; + reset-delay = <250>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.yaml b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.yaml new file mode 100644 index 00000000000000..99e14f59b19762 --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu.yaml @@ -0,0 +1,20 @@ +identifier: m5stack_stamps3/esp32s3/procpu +name: M5Stack StampS3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pwm + - pinmux + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu_defconfig b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000000..466f9999601c4e --- /dev/null +++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_esp32s3_procpu_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_GPIO=y + +CONFIG_CONSOLE=y +CONFIG_PWM=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/m5stack/m5stickc_plus/Kconfig b/boards/m5stack/m5stickc_plus/Kconfig new file mode 100644 index 00000000000000..0befa89fc68b15 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STICKC_PLUS + select SOC_ESP32_PROCPU if BOARD_M5STICKC_PLUS_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_M5STICKC_PLUS_ESP32_APPCPU diff --git a/boards/m5stack/m5stickc_plus/Kconfig.defconfig b/boards/m5stack/m5stickc_plus/Kconfig.defconfig new file mode 100644 index 00000000000000..638a054bec13b5 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/Kconfig.defconfig @@ -0,0 +1,26 @@ +# M5StickC PLUS board configuration + +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_M5STICKC_PLUS_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_M5STICKC_PLUS_ESP32_PROCPU + +if BOARD_M5STICKC_PLUS_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_M5STICKC_PLUS_ESP32_APPCPU diff --git a/boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus b/boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus new file mode 100644 index 00000000000000..9ab1db5c121855 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/Kconfig.m5stickc_plus @@ -0,0 +1,7 @@ +# M5StickC PLUS board configuration + +# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M5STICKC_PLUS + select SOC_ESP32_PICO_D4 diff --git a/boards/xtensa/m5stack_atoms3_lite/Kconfig.sysbuild b/boards/m5stack/m5stickc_plus/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/Kconfig.sysbuild rename to boards/m5stack/m5stickc_plus/Kconfig.sysbuild diff --git a/boards/xtensa/m5stickc_plus/board.cmake b/boards/m5stack/m5stickc_plus/board.cmake similarity index 100% rename from boards/xtensa/m5stickc_plus/board.cmake rename to boards/m5stack/m5stickc_plus/board.cmake diff --git a/boards/m5stack/m5stickc_plus/board.yml b/boards/m5stack/m5stickc_plus/board.yml new file mode 100644 index 00000000000000..3a604266d079c3 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/board.yml @@ -0,0 +1,5 @@ +board: + name: m5stickc_plus + vendor: m5stack + socs: + - name: esp32 diff --git a/boards/m5stack/m5stickc_plus/doc/index.rst b/boards/m5stack/m5stickc_plus/doc/index.rst new file mode 100644 index 00000000000000..1e5907d50cd673 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/doc/index.rst @@ -0,0 +1,218 @@ +.. _m5stickc_plus: + +M5StickC PLUS +############# + +Overview +******** + +M5StickC PLUS, one of the core devices in M5Stacks product series, is an ESP32-based development board. + +M5StickC PLUS features the following integrated components: + +- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) +- ST7789v2, LCD TFT 1.14", 135x240 px screen +- IMU MPU-6886 +- SPM-1423 microphone +- RTC BM8563 +- PMU AXP192 +- 120 mAh 3,7 V battery + +Some of the ESP32 I/O pins are broken out to the board's pin headers for easy access. + +Functional Description +********************** + +The following table below describes the key components, interfaces, and controls +of the M5StickC PLUS board. + +.. _ST7789v2: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ST7789V.pdf +.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf +.. _ESP32-PICO-D4: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32-pico-d4_datasheet_en.pdf +.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf + ++------------------+-------------------------------------------------------------------------+ +| Key Component | Description | ++==================+=========================================================================+ +| 32.768 kHz RTC | External precision 32.768 kHz crystal oscillator serves as a clock with | +| | low-power consumption while the chip is in Deep-sleep mode. | ++------------------+-------------------------------------------------------------------------+ +| ESP32-PICO-D4 | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth | +| module | functionalities and integrates a 4-MB SPI flash. | ++------------------+-------------------------------------------------------------------------+ +| Diagnostic LED | One user LED connected to the GPIO pin. | ++------------------+-------------------------------------------------------------------------+ +| USB Port | USB interface. Power supply for the board as well as the | +| | communication interface between a computer and the board. | +| | Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 | ++------------------+-------------------------------------------------------------------------+ +| Power Switch | Power on/off button. | ++------------------+-------------------------------------------------------------------------+ +| A/B user buttons | Two push buttons intended for any user use. | ++------------------+-------------------------------------------------------------------------+ +| LCD screen | Built-in LCD TFT display \(`ST7789v2`_, 1.14", 135x240 px\) controlled | +| | by the SPI interface | ++------------------+-------------------------------------------------------------------------+ +| MPU-6886 | The `MPU-6886`_ is a 6-axis MotionTracking device that combines a | +| | 3-axis gyroscope and a 3-axis accelerometer. | ++------------------+-------------------------------------------------------------------------+ +| Built-in | The `SPM-1423`_ I2S driven microphone. | +| microphone | | ++------------------+-------------------------------------------------------------------------+ + + +Start Application Development +***************************** + +Before powering up your M5StickC PLUS, please make sure that the board is in good +condition with no obvious signs of damage. + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: m5stickc_plus + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stickc_plus/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``m5stickc_plus`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: m5stickc_plus/esp32/procpu + :goals: flash + +The default baud rate for the M5StickC PLUS is set to 1500000bps. If experiencing issues when flashing, +try using different values by using ``--esp-baud-rate `` option during +``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). + +You can also open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! m5stickc_plus + +Debugging +********* + +M5StickC PLUS debugging is not supported due to pinout limitations. + +Related Documents +***************** + +- `M5StickC PLUS schematic `_ (WEBP) +- `ESP32-PICO-D4 Datasheet `_ (PDF) +- `M5StickC PLUS docs `_ +- `ESP32 Datasheet `_ (PDF) +- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus-pinctrl.dtsi b/boards/m5stack/m5stickc_plus/m5stickc_plus-pinctrl.dtsi similarity index 100% rename from boards/xtensa/m5stickc_plus/m5stickc_plus-pinctrl.dtsi rename to boards/m5stack/m5stickc_plus/m5stickc_plus-pinctrl.dtsi diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.dts new file mode 100644 index 00000000000000..8b7e74fdd988ca --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "M5StickC Plus APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.yaml b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.yaml new file mode 100644 index 00000000000000..e436849ced4d1a --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: m5stickc_plus/esp32/appcpu +name: M5StickC PLUS +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: m5stack diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.dts new file mode 100644 index 00000000000000..2f0f6975bbaad4 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.dts @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include "m5stickc_plus-pinctrl.dtsi" +#include + +/ { + model = "M5StickC Plus PROCPU"; + compatible = "m5stack,m5stickc-plus"; + + aliases { + led0 = &red_led; + sw0 = &user_button_0; + sw1 = &user_button_1; + uart-0 = &uart0; + i2c-0 = &i2c0; + watchdog0 = &wdt0; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + + red_led: led_0 { + gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; + label = "Red - LED0"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + user_button_0: button_0 { + label = "User button 0"; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_1: button_1 { + label = "User button 1"; + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +/* IMU MPU-6886, RTC BM8563, PMU AXP192 */ +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_sda_gpio21 &i2c0_scl_gpio22>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_miso_gpio12 &spim2_mosi_gpio11 + &spim2_sclk_gpio14 &spim2_csel_gpio16>; + pinctrl-names = "default"; +}; + +/* LCD TFT 1.14", 135x240 px, ST7789v2 */ +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_miso_gpio25 &spim3_mosi_gpio15 + &spim3_sclk_gpio13 &spim3_csel_gpio5>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&timer2 { + status = "okay"; +}; + +&timer3 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.yaml b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.yaml new file mode 100644 index 00000000000000..24499601d4a475 --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu.yaml @@ -0,0 +1,19 @@ +identifier: m5stickc_plus/esp32/procpu +name: M5StickC PLUS +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - i2c + - spi + - watchdog + - uart + - pinmux + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: m5stack diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu_defconfig b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu_defconfig new file mode 100644 index 00000000000000..ee9920cda6870e --- /dev/null +++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y +CONFIG_I2C=y diff --git a/boards/xtensa/m5stickc_plus/support/openocd.cfg b/boards/m5stack/m5stickc_plus/support/openocd.cfg similarity index 100% rename from boards/xtensa/m5stickc_plus/support/openocd.cfg rename to boards/m5stack/m5stickc_plus/support/openocd.cfg diff --git a/boards/m5stack/stamp_c3/Kconfig.defconfig b/boards/m5stack/stamp_c3/Kconfig.defconfig new file mode 100644 index 00000000000000..4ce7fe02e12004 --- /dev/null +++ b/boards/m5stack/stamp_c3/Kconfig.defconfig @@ -0,0 +1,19 @@ +# M5Stack STAMP-C3 board configuration + +# Copyright 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +if BT + +choice BT_HCI_BUS_TYPE + default BT_ESP32 +endchoice + +endif # BT diff --git a/boards/m5stack/stamp_c3/Kconfig.stamp_c3 b/boards/m5stack/stamp_c3/Kconfig.stamp_c3 new file mode 100644 index 00000000000000..dd126de3dfd81f --- /dev/null +++ b/boards/m5stack/stamp_c3/Kconfig.stamp_c3 @@ -0,0 +1,7 @@ +# M5Stack STAMP-C3 board configuration + +# Copyright 2022 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STAMP_C3 + select SOC_ESP32C3_FX4 diff --git a/boards/xtensa/m5stickc_plus/Kconfig.sysbuild b/boards/m5stack/stamp_c3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/m5stickc_plus/Kconfig.sysbuild rename to boards/m5stack/stamp_c3/Kconfig.sysbuild diff --git a/boards/xtensa/m5stack_atoms3/board.cmake b/boards/m5stack/stamp_c3/board.cmake similarity index 100% rename from boards/xtensa/m5stack_atoms3/board.cmake rename to boards/m5stack/stamp_c3/board.cmake diff --git a/boards/m5stack/stamp_c3/board.yml b/boards/m5stack/stamp_c3/board.yml new file mode 100644 index 00000000000000..aa24963edd6549 --- /dev/null +++ b/boards/m5stack/stamp_c3/board.yml @@ -0,0 +1,5 @@ +board: + name: stamp_c3 + vendor: m5stack + socs: + - name: esp32c3 diff --git a/boards/m5stack/stamp_c3/doc/index.rst b/boards/m5stack/stamp_c3/doc/index.rst new file mode 100644 index 00000000000000..9ac2a05b7ec987 --- /dev/null +++ b/boards/m5stack/stamp_c3/doc/index.rst @@ -0,0 +1,205 @@ +.. _stamp_c3: + +M5Stack STAMP-C3 +################## + +Overview +******** + +STAMP-C3 featuring ESPRESSIF ESP32-C3 RISC-V MCU with Wi-Fi connectivity +for IoT edge devices such as home appliances and Industrial Automation. + +For more details see the `M5Stack STAMP-C3`_ page. + +Supported Features +================== + +The STAMP-C3 board configuration supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| TWAI | on-chip | can_esp32_twai | ++-----------+------------+------------------+ + + +Prerequisites +************* + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: stamp_c3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: build + +The usual ``flash`` target will work with the ``stamp_c3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! stamp_c3 + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stamp_c3 + :goals: debug + +References +********** + +.. target-notes:: + +.. _`M5Stack STAMP-C3`: https://docs.m5stack.com/en/core/stamp_c3 +.. _`ESP32C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf +.. _`ESP32C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi b/boards/m5stack/stamp_c3/stamp_c3-pinctrl.dtsi similarity index 100% rename from boards/riscv/stamp_c3/stamp_c3-pinctrl.dtsi rename to boards/m5stack/stamp_c3/stamp_c3-pinctrl.dtsi diff --git a/boards/riscv/stamp_c3/stamp_c3.dts b/boards/m5stack/stamp_c3/stamp_c3.dts similarity index 100% rename from boards/riscv/stamp_c3/stamp_c3.dts rename to boards/m5stack/stamp_c3/stamp_c3.dts diff --git a/boards/riscv/stamp_c3/stamp_c3.yaml b/boards/m5stack/stamp_c3/stamp_c3.yaml similarity index 100% rename from boards/riscv/stamp_c3/stamp_c3.yaml rename to boards/m5stack/stamp_c3/stamp_c3.yaml diff --git a/boards/m5stack/stamp_c3/stamp_c3_defconfig b/boards/m5stack/stamp_c3/stamp_c3_defconfig new file mode 100644 index 00000000000000..ef633ce56a18e2 --- /dev/null +++ b/boards/m5stack/stamp_c3/stamp_c3_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/stamp_c3/support/openocd.cfg b/boards/m5stack/stamp_c3/support/openocd.cfg similarity index 100% rename from boards/riscv/stamp_c3/support/openocd.cfg rename to boards/m5stack/stamp_c3/support/openocd.cfg diff --git a/boards/madmachine/index.rst b/boards/madmachine/index.rst new file mode 100644 index 00000000000000..a43bebd08ad4c6 --- /dev/null +++ b/boards/madmachine/index.rst @@ -0,0 +1,10 @@ +.. _boards-mad-machine: + +Mad Machine +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/madmachine/mm_feather/CMakeLists.txt b/boards/madmachine/mm_feather/CMakeLists.txt new file mode 100644 index 00000000000000..623a4b901ac154 --- /dev/null +++ b/boards/madmachine/mm_feather/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 2021 MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) + zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmfeather_sdram_ini_dcd.c) +endif() diff --git a/boards/madmachine/mm_feather/Kconfig.defconfig b/boards/madmachine/mm_feather/Kconfig.defconfig new file mode 100644 index 00000000000000..a2503d832b4fa9 --- /dev/null +++ b/boards/madmachine/mm_feather/Kconfig.defconfig @@ -0,0 +1,18 @@ +# MM-FEATHER board + +# Copyright (c) 2021, MADMACHINE LIMITED +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MM_FEATHER + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_MM_FEATHER diff --git a/boards/madmachine/mm_feather/Kconfig.mm_feather b/boards/madmachine/mm_feather/Kconfig.mm_feather new file mode 100644 index 00000000000000..33a0180483d3a2 --- /dev/null +++ b/boards/madmachine/mm_feather/Kconfig.mm_feather @@ -0,0 +1,7 @@ +# Copyright (c) 2021, MADMACHINE LIMITED +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MM_FEATHER + select SOC_PART_NUMBER_MIMXRT1062DVL6A + select SOC_MIMXRT1062 diff --git a/boards/arm/mm_feather/board.cmake b/boards/madmachine/mm_feather/board.cmake similarity index 100% rename from boards/arm/mm_feather/board.cmake rename to boards/madmachine/mm_feather/board.cmake diff --git a/boards/madmachine/mm_feather/board.yml b/boards/madmachine/mm_feather/board.yml new file mode 100644 index 00000000000000..1b9ca3f2c7c10a --- /dev/null +++ b/boards/madmachine/mm_feather/board.yml @@ -0,0 +1,5 @@ +board: + name: mm_feather + vendor: madmachine + socs: + - name: mimxrt1062 diff --git a/boards/arm/mm_feather/doc/index.rst b/boards/madmachine/mm_feather/doc/index.rst similarity index 100% rename from boards/arm/mm_feather/doc/index.rst rename to boards/madmachine/mm_feather/doc/index.rst diff --git a/boards/arm/mm_feather/doc/mm_feather.jpg b/boards/madmachine/mm_feather/doc/mm_feather.jpg similarity index 100% rename from boards/arm/mm_feather/doc/mm_feather.jpg rename to boards/madmachine/mm_feather/doc/mm_feather.jpg diff --git a/boards/madmachine/mm_feather/flexspi_nor_config.c b/boards/madmachine/mm_feather/flexspi_nor_config.c new file mode 100644 index 00000000000000..c229eda7d99585 --- /dev/null +++ b/boards/madmachine/mm_feather/flexspi_nor_config.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ diff --git a/boards/arm/mm_feather/mm_feather-pinctrl.dtsi b/boards/madmachine/mm_feather/mm_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/mm_feather/mm_feather-pinctrl.dtsi rename to boards/madmachine/mm_feather/mm_feather-pinctrl.dtsi diff --git a/boards/arm/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts similarity index 100% rename from boards/arm/mm_feather/mm_feather.dts rename to boards/madmachine/mm_feather/mm_feather.dts diff --git a/boards/arm/mm_feather/mm_feather.yaml b/boards/madmachine/mm_feather/mm_feather.yaml similarity index 100% rename from boards/arm/mm_feather/mm_feather.yaml rename to boards/madmachine/mm_feather/mm_feather.yaml diff --git a/boards/arm/mm_feather/mm_feather_defconfig b/boards/madmachine/mm_feather/mm_feather_defconfig similarity index 83% rename from boards/arm/mm_feather/mm_feather_defconfig rename to boards/madmachine/mm_feather/mm_feather_defconfig index 1ec155fc2fedd8..65cb3610d48c32 100644 --- a/boards/arm/mm_feather/mm_feather_defconfig +++ b/boards/madmachine/mm_feather/mm_feather_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/mm_feather/mmfeather_sdram_ini_dcd.c b/boards/madmachine/mm_feather/mmfeather_sdram_ini_dcd.c similarity index 100% rename from boards/arm/mm_feather/mmfeather_sdram_ini_dcd.c rename to boards/madmachine/mm_feather/mmfeather_sdram_ini_dcd.c diff --git a/boards/madmachine/mm_swiftio/CMakeLists.txt b/boards/madmachine/mm_swiftio/CMakeLists.txt new file mode 100644 index 00000000000000..c3084a6b71b923 --- /dev/null +++ b/boards/madmachine/mm_swiftio/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 20179 MADMACHINE LIMITED +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR flexspi_nor_config.c) + zephyr_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA mmswiftio_sdram_ini_dcd.c) +endif() diff --git a/boards/madmachine/mm_swiftio/Kconfig.defconfig b/boards/madmachine/mm_swiftio/Kconfig.defconfig new file mode 100644 index 00000000000000..207e95b6757001 --- /dev/null +++ b/boards/madmachine/mm_swiftio/Kconfig.defconfig @@ -0,0 +1,18 @@ +# MM-SWIFTIO board + +# Copyright (c) 2019, MADMACHINE LIMITED +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MM_SWIFTIO + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_MM_SWIFTIO diff --git a/boards/madmachine/mm_swiftio/Kconfig.mm_swiftio b/boards/madmachine/mm_swiftio/Kconfig.mm_swiftio new file mode 100644 index 00000000000000..11ed8ddafd5e08 --- /dev/null +++ b/boards/madmachine/mm_swiftio/Kconfig.mm_swiftio @@ -0,0 +1,6 @@ +# Copyright (c) 2019, MADMACHINE LIMITED +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MM_SWIFTIO + select SOC_PART_NUMBER_MIMXRT1052DVL6B diff --git a/boards/arm/mm_swiftio/board.cmake b/boards/madmachine/mm_swiftio/board.cmake similarity index 100% rename from boards/arm/mm_swiftio/board.cmake rename to boards/madmachine/mm_swiftio/board.cmake diff --git a/boards/madmachine/mm_swiftio/board.yml b/boards/madmachine/mm_swiftio/board.yml new file mode 100644 index 00000000000000..784e79c52adf4d --- /dev/null +++ b/boards/madmachine/mm_swiftio/board.yml @@ -0,0 +1,5 @@ +board: + name: mm_swiftio + vendor: madmachine + socs: + - name: mimxrt1052 diff --git a/boards/arm/mm_swiftio/doc/index.rst b/boards/madmachine/mm_swiftio/doc/index.rst similarity index 100% rename from boards/arm/mm_swiftio/doc/index.rst rename to boards/madmachine/mm_swiftio/doc/index.rst diff --git a/boards/arm/mm_swiftio/doc/mm_swiftio.jpg b/boards/madmachine/mm_swiftio/doc/mm_swiftio.jpg similarity index 100% rename from boards/arm/mm_swiftio/doc/mm_swiftio.jpg rename to boards/madmachine/mm_swiftio/doc/mm_swiftio.jpg diff --git a/boards/madmachine/mm_swiftio/flexspi_nor_config.c b/boards/madmachine/mm_swiftio/flexspi_nor_config.c new file mode 100644 index 00000000000000..c229eda7d99585 --- /dev/null +++ b/boards/madmachine/mm_swiftio/flexspi_nor_config.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ diff --git a/boards/arm/mm_swiftio/mm_swiftio-pinctrl.dtsi b/boards/madmachine/mm_swiftio/mm_swiftio-pinctrl.dtsi similarity index 100% rename from boards/arm/mm_swiftio/mm_swiftio-pinctrl.dtsi rename to boards/madmachine/mm_swiftio/mm_swiftio-pinctrl.dtsi diff --git a/boards/arm/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts similarity index 100% rename from boards/arm/mm_swiftio/mm_swiftio.dts rename to boards/madmachine/mm_swiftio/mm_swiftio.dts diff --git a/boards/arm/mm_swiftio/mm_swiftio.yaml b/boards/madmachine/mm_swiftio/mm_swiftio.yaml similarity index 100% rename from boards/arm/mm_swiftio/mm_swiftio.yaml rename to boards/madmachine/mm_swiftio/mm_swiftio.yaml diff --git a/boards/arm/mm_swiftio/mm_swiftio_defconfig b/boards/madmachine/mm_swiftio/mm_swiftio_defconfig similarity index 83% rename from boards/arm/mm_swiftio/mm_swiftio_defconfig rename to boards/madmachine/mm_swiftio/mm_swiftio_defconfig index d09c986b33ad4c..0aee57c3625b40 100644 --- a/boards/arm/mm_swiftio/mm_swiftio_defconfig +++ b/boards/madmachine/mm_swiftio/mm_swiftio_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1052=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/mm_swiftio/mmswiftio_sdram_ini_dcd.c b/boards/madmachine/mm_swiftio/mmswiftio_sdram_ini_dcd.c similarity index 100% rename from boards/arm/mm_swiftio/mmswiftio_sdram_ini_dcd.c rename to boards/madmachine/mm_swiftio/mmswiftio_sdram_ini_dcd.c diff --git a/boards/maker_diary/index.rst b/boards/maker_diary/index.rst new file mode 100644 index 00000000000000..eee9613df01dd3 --- /dev/null +++ b/boards/maker_diary/index.rst @@ -0,0 +1,10 @@ +.. _boards-maker-diary: + +Maker Diary +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/nrf52832_mdk/Kconfig b/boards/maker_diary/nrf52832_mdk/Kconfig similarity index 100% rename from boards/arm/nrf52832_mdk/Kconfig rename to boards/maker_diary/nrf52832_mdk/Kconfig diff --git a/boards/maker_diary/nrf52832_mdk/Kconfig.defconfig b/boards/maker_diary/nrf52832_mdk/Kconfig.defconfig new file mode 100644 index 00000000000000..13d65f68be1935 --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52832-MDK board configuration + +# Copyright (c) 2018 makerdiary.com. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52832_MDK + +config BT_CTLR + default BT + +endif # BOARD_NRF52832_MDK diff --git a/boards/maker_diary/nrf52832_mdk/Kconfig.nrf52832_mdk b/boards/maker_diary/nrf52832_mdk/Kconfig.nrf52832_mdk new file mode 100644 index 00000000000000..87fc85bda302a4 --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/Kconfig.nrf52832_mdk @@ -0,0 +1,7 @@ +# nRF52832-MDK board configuration + +# Copyright (c) 2018 makerdiary.com. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52832_MDK + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52832_mdk/board.cmake b/boards/maker_diary/nrf52832_mdk/board.cmake similarity index 100% rename from boards/arm/nrf52832_mdk/board.cmake rename to boards/maker_diary/nrf52832_mdk/board.cmake diff --git a/boards/maker_diary/nrf52832_mdk/board.yml b/boards/maker_diary/nrf52832_mdk/board.yml new file mode 100644 index 00000000000000..70028809dc37f3 --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52832_mdk + vendor: makerdiary + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52832_mdk/doc/index.rst b/boards/maker_diary/nrf52832_mdk/doc/index.rst similarity index 100% rename from boards/arm/nrf52832_mdk/doc/index.rst rename to boards/maker_diary/nrf52832_mdk/doc/index.rst diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi rename to boards/maker_diary/nrf52832_mdk/nrf52832_mdk-pinctrl.dtsi diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk.dts b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk.dts similarity index 100% rename from boards/arm/nrf52832_mdk/nrf52832_mdk.dts rename to boards/maker_diary/nrf52832_mdk/nrf52832_mdk.dts diff --git a/boards/arm/nrf52832_mdk/nrf52832_mdk.yaml b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk.yaml similarity index 100% rename from boards/arm/nrf52832_mdk/nrf52832_mdk.yaml rename to boards/maker_diary/nrf52832_mdk/nrf52832_mdk.yaml diff --git a/boards/maker_diary/nrf52832_mdk/nrf52832_mdk_defconfig b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/maker_diary/nrf52832_mdk/nrf52832_mdk_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52833dk_nrf52833/pre_dt_board.cmake b/boards/maker_diary/nrf52832_mdk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/pre_dt_board.cmake rename to boards/maker_diary/nrf52832_mdk/pre_dt_board.cmake diff --git a/boards/arm/nrf52840_mdk/Kconfig b/boards/maker_diary/nrf52840_mdk/Kconfig similarity index 100% rename from boards/arm/nrf52840_mdk/Kconfig rename to boards/maker_diary/nrf52840_mdk/Kconfig diff --git a/boards/maker_diary/nrf52840_mdk/Kconfig.defconfig b/boards/maker_diary/nrf52840_mdk/Kconfig.defconfig new file mode 100644 index 00000000000000..4ffd9e4ea08d36 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52840-MDK board configuration + +# Copyright (c) 2018 makerdiary.com +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_MDK + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_MDK diff --git a/boards/maker_diary/nrf52840_mdk/Kconfig.nrf52840_mdk b/boards/maker_diary/nrf52840_mdk/Kconfig.nrf52840_mdk new file mode 100644 index 00000000000000..a32c79ad741f3e --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/Kconfig.nrf52840_mdk @@ -0,0 +1,7 @@ +# nRF52840-MDK board configuration + +# Copyright (c) 2018 makerdiary.com +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_MDK + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk/board.cmake b/boards/maker_diary/nrf52840_mdk/board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk/board.cmake rename to boards/maker_diary/nrf52840_mdk/board.cmake diff --git a/boards/maker_diary/nrf52840_mdk/board.yml b/boards/maker_diary/nrf52840_mdk/board.yml new file mode 100644 index 00000000000000..09e13811fc307a --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_mdk + vendor: makerdiary + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_mdk/doc/index.rst b/boards/maker_diary/nrf52840_mdk/doc/index.rst similarity index 100% rename from boards/arm/nrf52840_mdk/doc/index.rst rename to boards/maker_diary/nrf52840_mdk/doc/index.rst diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi rename to boards/maker_diary/nrf52840_mdk/nrf52840_mdk-pinctrl.dtsi diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk.dts b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk.dts similarity index 100% rename from boards/arm/nrf52840_mdk/nrf52840_mdk.dts rename to boards/maker_diary/nrf52840_mdk/nrf52840_mdk.dts diff --git a/boards/arm/nrf52840_mdk/nrf52840_mdk.yaml b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk.yaml similarity index 100% rename from boards/arm/nrf52840_mdk/nrf52840_mdk.yaml rename to boards/maker_diary/nrf52840_mdk/nrf52840_mdk.yaml diff --git a/boards/maker_diary/nrf52840_mdk/nrf52840_mdk_defconfig b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk/nrf52840_mdk_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf52840_blip/pre_dt_board.cmake b/boards/maker_diary/nrf52840_mdk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_blip/pre_dt_board.cmake rename to boards/maker_diary/nrf52840_mdk/pre_dt_board.cmake diff --git a/boards/arm/nrf52840_mdk_usb_dongle/Kconfig b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/Kconfig rename to boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.defconfig b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.defconfig new file mode 100644 index 00000000000000..eb2cfed745d41f --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.defconfig @@ -0,0 +1,37 @@ +# nRF52840 MDK USB Dongle board configuration +# +# Copyright (c) 2018 Nordic Semiconductor ASA +# +# Copyright (c) 2022 Nikola Trifunovic +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840_MDK_USB_DONGLE + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# so no override is necessary. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on BOARD_HAS_NRF5_BOOTLOADER && !USE_DT_CODE_PARTITION + +if USB_DEVICE_STACK + +# Enable UART driver, needed for CDC ACM +config SERIAL + default y + +endif # USB_DEVICE_STACK + +config BT_CTLR + default BT + +endif # BOARD_NRF52840_MDK_USB_DONGLE diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.nrf52840_mdk_usb_dongle b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.nrf52840_mdk_usb_dongle new file mode 100644 index 00000000000000..7f71811f3f22ee --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/Kconfig.nrf52840_mdk_usb_dongle @@ -0,0 +1,8 @@ +# nRF52840 MDK USB Dongle board configuration + +# Copyright (c) 2022 Nikola Trifunovic +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840_MDK_USB_DONGLE + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840_mdk_usb_dongle/board.cmake b/boards/maker_diary/nrf52840_mdk_usb_dongle/board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/board.cmake rename to boards/maker_diary/nrf52840_mdk_usb_dongle/board.cmake diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/board.yml b/boards/maker_diary/nrf52840_mdk_usb_dongle/board.yml new file mode 100644 index 00000000000000..1c3020c52b5978 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840_mdk_usb_dongle + vendor: makerdiary + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840_mdk_usb_dongle/doc/index.rst b/boards/maker_diary/nrf52840_mdk_usb_dongle/doc/index.rst similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/doc/index.rst rename to boards/maker_diary/nrf52840_mdk_usb_dongle/doc/index.rst diff --git a/boards/arm/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg b/boards/maker_diary/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg rename to boards/maker_diary/nrf52840_mdk_usb_dongle/doc/nrf52840-mdk-usb-dongle-pinout.jpg diff --git a/boards/arm/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi b/boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi rename to boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-debugger.dtsi diff --git a/boards/arm/nrf52840_mdk_usb_dongle/fstab-stock.dtsi b/boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-stock.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/fstab-stock.dtsi rename to boards/maker_diary/nrf52840_mdk_usb_dongle/fstab-stock.dtsi diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi rename to boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle-pinctrl.dtsi diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts rename to boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.dts diff --git a/boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml rename to boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml diff --git a/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig new file mode 100644 index 00000000000000..86ff0f6c71f461 --- /dev/null +++ b/boards/maker_diary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle_defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Console +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y diff --git a/boards/arm/nrf52840_mdk/pre_dt_board.cmake b/boards/maker_diary/nrf52840_mdk_usb_dongle/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk/pre_dt_board.cmake rename to boards/maker_diary/nrf52840_mdk_usb_dongle/pre_dt_board.cmake diff --git a/boards/microchip/ev11l78a/Kconfig.defconfig b/boards/microchip/ev11l78a/Kconfig.defconfig new file mode 100644 index 00000000000000..9fe8fda5d7483a --- /dev/null +++ b/boards/microchip/ev11l78a/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if USBC_STACK + +# Kernel Options due to Low Memory (4k) +CONFIG_LOG_BUFFER_SIZE=256 +CONFIG_MAIN_STACK_SIZE=640 +CONFIG_IDLE_STACK_SIZE=200 +CONFIG_ISR_STACK_SIZE=512 +CONFIG_USBC_STACK_SIZE=512 +# Prevent Interrupt Vector Table in RAM +CONFIG_SRAM_VECTOR_TABLE=n + +# This board only supports the sink role, so +# no need to ever implement source for it. +CONFIG_USBC_CSM_SINK_ONLY=y + +endif # USBC_STACK diff --git a/boards/microchip/ev11l78a/Kconfig.ev11l78a b/boards/microchip/ev11l78a/Kconfig.ev11l78a new file mode 100644 index 00000000000000..2e4080c0e17ed1 --- /dev/null +++ b/boards/microchip/ev11l78a/Kconfig.ev11l78a @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Meta Platforms, Inc. and its affiliates. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EV11L78A + select SOC_SAMD20E16 diff --git a/boards/arm/ev11l78a/board.cmake b/boards/microchip/ev11l78a/board.cmake similarity index 100% rename from boards/arm/ev11l78a/board.cmake rename to boards/microchip/ev11l78a/board.cmake diff --git a/boards/microchip/ev11l78a/board.yml b/boards/microchip/ev11l78a/board.yml new file mode 100644 index 00000000000000..abaabec67abd82 --- /dev/null +++ b/boards/microchip/ev11l78a/board.yml @@ -0,0 +1,5 @@ +board: + name: ev11l78a + vendor: microchip + socs: + - name: samd20e16 diff --git a/boards/arm/ev11l78a/doc/img/ev11l78a.jpg b/boards/microchip/ev11l78a/doc/img/ev11l78a.jpg similarity index 100% rename from boards/arm/ev11l78a/doc/img/ev11l78a.jpg rename to boards/microchip/ev11l78a/doc/img/ev11l78a.jpg diff --git a/boards/microchip/ev11l78a/doc/index.rst b/boards/microchip/ev11l78a/doc/index.rst new file mode 100644 index 00000000000000..2197ede6331ad7 --- /dev/null +++ b/boards/microchip/ev11l78a/doc/index.rst @@ -0,0 +1,105 @@ +.. _ev11l78a: + +UPD301C Basic Sink Application Example +###################################### + +Overview +******** + +The UPD301C Basic Sink Application Example Evaluation Kit (EV11L78A) +is a low-cost evaluation platform for Microchip's UPD301C Standalone +Programmable USB Power Delivery (PD) Controller. This RoHS-compliant +evaluation platform comes in a small form factor and adheres to the +USB Type-C™ Connector Specification and USB PD 3.0 specification. + +.. figure:: img/ev11l78a.jpg + :width: 500px + :align: center + :alt: EV11L78A + + UPD301C Basic Sink Application Example (Credit: `Microchip Technology`_) + +Hardware +******** + +- ATSAMD20E16 ARM Cortex-M0+ processor at 48 MHz +- UPD301C combines a SAMD20 core and a UPD350 USB-PD controller +- Sink PDO Selector Switch +- Onboard LED Voltmeter + +Supported Features +================== + +The ev11l78a board configuration supports the following hardware +features: + + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - systick + * - WDT + - on-chip + - Watchdog + * - ADC + - on-chip + - Analog to Digital Converter + * - GPIO + - on-chip + - I/O ports + * - USART + - on-chip + - Serial ports + * - I2C + - on-chip + - I2C ports + * - SPI + - on-chip + - Serial Peripheral Interface ports + +Other hardware features are not currently supported by Zephyr. + +Refer to the `EV11L78A Schematics`_ for a detailed hardware diagram. + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/microchip/ev11l78a/ev11l78a_defconfig`. + +Serial Port +=========== + +The SAMD20 MCU has 6 SERCOM based USARTs. One of the USARTs +(SERCOM1) is available on the Debug/Status header. + +SPI Port +======== + +The SAMD20 MCU has 6 SERCOM based SPIs. One of the SPIs (SERCOM0) +is internally connected between the SAMD20 core and the UPD350. + +I²C Port +======== + +The SAMD20 MCU has 6 SERCOM based I2Cs. One of the I2Cs (SERCOM3) +is available on the Debug/Status header. + +References +********** + +.. target-notes:: + +.. _Microchip Technology: + https://www.microchip.com/en-us/development-tool/ev11l78a + +.. _EV11L78A Schematics: + https://ww1.microchip.com/downloads/aemDocuments/documents/UNG/ProductDocuments/SupportingCollateral/03-00056-R1.0.PDF diff --git a/boards/arm/ev11l78a/ev11l78a-pinctrl.dtsi b/boards/microchip/ev11l78a/ev11l78a-pinctrl.dtsi similarity index 100% rename from boards/arm/ev11l78a/ev11l78a-pinctrl.dtsi rename to boards/microchip/ev11l78a/ev11l78a-pinctrl.dtsi diff --git a/boards/arm/ev11l78a/ev11l78a.dts b/boards/microchip/ev11l78a/ev11l78a.dts similarity index 100% rename from boards/arm/ev11l78a/ev11l78a.dts rename to boards/microchip/ev11l78a/ev11l78a.dts diff --git a/boards/arm/ev11l78a/ev11l78a.yaml b/boards/microchip/ev11l78a/ev11l78a.yaml similarity index 100% rename from boards/arm/ev11l78a/ev11l78a.yaml rename to boards/microchip/ev11l78a/ev11l78a.yaml diff --git a/boards/microchip/ev11l78a/ev11l78a_defconfig b/boards/microchip/ev11l78a/ev11l78a_defconfig new file mode 100644 index 00000000000000..481d0cf53601cb --- /dev/null +++ b/boards/microchip/ev11l78a/ev11l78a_defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SOC_ATMEL_SAMD_OSC8M=y +CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/ev11l78a/pre_dt_board.cmake b/boards/microchip/ev11l78a/pre_dt_board.cmake similarity index 100% rename from boards/arm/ev11l78a/pre_dt_board.cmake rename to boards/microchip/ev11l78a/pre_dt_board.cmake diff --git a/boards/arm/ev11l78a/support/openocd.cfg b/boards/microchip/ev11l78a/support/openocd.cfg similarity index 100% rename from boards/arm/ev11l78a/support/openocd.cfg rename to boards/microchip/ev11l78a/support/openocd.cfg diff --git a/boards/microchip/index.rst b/boards/microchip/index.rst new file mode 100644 index 00000000000000..1610cf6a7c2f24 --- /dev/null +++ b/boards/microchip/index.rst @@ -0,0 +1,10 @@ +.. _boards-microchip-technology-inc: + +Microchip Technology Inc. +######################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/microchip/m2gl025_miv/Kconfig.m2gl025_miv b/boards/microchip/m2gl025_miv/Kconfig.m2gl025_miv new file mode 100644 index 00000000000000..62484218132735 --- /dev/null +++ b/boards/microchip/m2gl025_miv/Kconfig.m2gl025_miv @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_M2GL025_MIV + select SOC_MIV diff --git a/boards/riscv/m2gl025_miv/board.cmake b/boards/microchip/m2gl025_miv/board.cmake similarity index 100% rename from boards/riscv/m2gl025_miv/board.cmake rename to boards/microchip/m2gl025_miv/board.cmake diff --git a/boards/microchip/m2gl025_miv/board.yml b/boards/microchip/m2gl025_miv/board.yml new file mode 100644 index 00000000000000..84e61821f35adc --- /dev/null +++ b/boards/microchip/m2gl025_miv/board.yml @@ -0,0 +1,5 @@ +board: + name: m2gl025_miv + vendor: microchip + socs: + - name: miv diff --git a/boards/riscv/m2gl025_miv/doc/index.rst b/boards/microchip/m2gl025_miv/doc/index.rst similarity index 100% rename from boards/riscv/m2gl025_miv/doc/index.rst rename to boards/microchip/m2gl025_miv/doc/index.rst diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv.dts b/boards/microchip/m2gl025_miv/m2gl025_miv.dts similarity index 100% rename from boards/riscv/m2gl025_miv/m2gl025_miv.dts rename to boards/microchip/m2gl025_miv/m2gl025_miv.dts diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv.yaml b/boards/microchip/m2gl025_miv/m2gl025_miv.yaml similarity index 100% rename from boards/riscv/m2gl025_miv/m2gl025_miv.yaml rename to boards/microchip/m2gl025_miv/m2gl025_miv.yaml diff --git a/boards/riscv/m2gl025_miv/m2gl025_miv_defconfig b/boards/microchip/m2gl025_miv/m2gl025_miv_defconfig similarity index 75% rename from boards/riscv/m2gl025_miv/m2gl025_miv_defconfig rename to boards/microchip/m2gl025_miv/m2gl025_miv_defconfig index e33765680d5441..a00960e8ca0747 100644 --- a/boards/riscv/m2gl025_miv/m2gl025_miv_defconfig +++ b/boards/microchip/m2gl025_miv/m2gl025_miv_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_MIV=y -CONFIG_SOC_MIV=y -CONFIG_BOARD_M2GL025_MIV=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/m2gl025_miv/support/m2gl025_miv.repl b/boards/microchip/m2gl025_miv/support/m2gl025_miv.repl similarity index 100% rename from boards/riscv/m2gl025_miv/support/m2gl025_miv.repl rename to boards/microchip/m2gl025_miv/support/m2gl025_miv.repl diff --git a/boards/riscv/m2gl025_miv/support/m2gl025_miv.resc b/boards/microchip/m2gl025_miv/support/m2gl025_miv.resc similarity index 100% rename from boards/riscv/m2gl025_miv/support/m2gl025_miv.resc rename to boards/microchip/m2gl025_miv/support/m2gl025_miv.resc diff --git a/boards/arm/mec1501modular_assy6885/CMakeLists.txt b/boards/microchip/mec1501modular_assy6885/CMakeLists.txt similarity index 100% rename from boards/arm/mec1501modular_assy6885/CMakeLists.txt rename to boards/microchip/mec1501modular_assy6885/CMakeLists.txt diff --git a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig new file mode 100644 index 00000000000000..1f5c692b90fb1a --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2019 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC1501MODULAR_ASSY6885 + +#PS/2 driver is compiled in terms of this flag. +config ESPI_PERIPHERAL_8042_KBC + default y + depends on ESPI_XEC + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 +# The driver requires tickless mode and ticks per +# second to be 32768 for accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 48MHz divided by +# SOC_MEC1501_PROC_CLK_DIV. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 48000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +if ESPI + +config ESPI_PERIPHERAL_UART_SOC_MAPPING + default 1 + +endif # ESPI + +endif # RTOS_TIMER + +endif # BOARD_MEC1501MODULAR_ASSY6885 diff --git a/boards/microchip/mec1501modular_assy6885/Kconfig.mec1501modular_assy6885 b/boards/microchip/mec1501modular_assy6885/Kconfig.mec1501modular_assy6885 new file mode 100644 index 00000000000000..721f2a0da9665a --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/Kconfig.mec1501modular_assy6885 @@ -0,0 +1,5 @@ +# Copyright (c) 2019, Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC1501MODULAR_ASSY6885 + select SOC_MEC1501_HSZ diff --git a/boards/arm/mec1501modular_assy6885/board.cmake b/boards/microchip/mec1501modular_assy6885/board.cmake similarity index 100% rename from boards/arm/mec1501modular_assy6885/board.cmake rename to boards/microchip/mec1501modular_assy6885/board.cmake diff --git a/boards/microchip/mec1501modular_assy6885/board.yml b/boards/microchip/mec1501modular_assy6885/board.yml new file mode 100644 index 00000000000000..d45ec4217f798e --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/board.yml @@ -0,0 +1,5 @@ +board: + name: mec1501modular_assy6885 + vendor: microchip + socs: + - name: mec1501_hsz diff --git a/boards/microchip/mec1501modular_assy6885/doc/index.rst b/boards/microchip/mec1501modular_assy6885/doc/index.rst new file mode 100644 index 00000000000000..a74f48163fb6d5 --- /dev/null +++ b/boards/microchip/mec1501modular_assy6885/doc/index.rst @@ -0,0 +1,321 @@ +.. _mec1501modular_assy6885: + +Microchip MEC1501 Modular card ASSY6885 +####################################### + +Overview +******** + +The MEC1501 Modular card ASSY6885 is a development board to evaluate the Microchip +MEC152X series microcontrollers. This board can work standalone or be mated with +any platform that complies with MECC specification. + +.. image:: mec1501modular_assy6885.jpg + :align: center + :alt: MEC1501 Modular ASSY 6885 + +Hardware +******** + +- MEC1521HA0SZ ARM Cortex-M4 Processor +- 256 KB RAM and 64 KB boot ROM +- GPIO headers +- UART1 using microUSB +- PECI interface 3.0 +- 10 SMBUS instances +- FAN, PMW and TACHO pins +- VCI interface +- Independent Hardware Driven PS/2 Ports + +At difference from MEC15xx evaluation board, modular MEC1521 exposes the pins +in 2 different ways: + +1) Standalone mode via headers + + - GPIOs + - PWM5 + - JTAG/SWD, ETM and MCHP Trace ports + - eSPI bus + - SMB0 + +2) Mated mode with another platform that has a high density MECC connector. + + - FAN0, PWM0, SMB0, SMB1, SMB4 and SMB5 + - eSPI bus + - Breathing/Blinking LEDs + +The board is powered through the +5V USB Micro A connector or from the MECC connector. + + +For more information about the SOC please see the `MEC152x Reference Manual`_ + +Supported Features +================== + +The mec1501modular_assy6885 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ESPI | on-chip | espi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RTOS | on-chip | timer | ++-----------+------------+-------------------------------------+ +| TIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PS2 | on-chip | ps2 | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the +:zephyr_file:`boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig` +Kconfig file. + +Connections and IOs +=================== + +This evaluation board kit is comprised of the following HW blocks: + +- MEC1501 Modular Card ASSY 6885 Rev A0 `MEC1501 Modular EC Card - Assy_6885 Rev A0p1`_ + +System Clock +============ + +The MEC1501 MCU is configured to use the 48Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== +UART1 is configured for serial logs. + +Jumper settings +*************** + +Please follow the jumper settings below to properly demo this +board. Advanced users may deviate from this recommendation. + +Jumper setting for MEC1501 Modular Assy 6885 Rev A1p0 +===================================================== + +Power-related jumpers +--------------------- + +If you wish to power from type A/B connector ``P10`` set the jumper ``JP35 1-2``. + +If you wish to power through MECC connector ``P1`` and mate to external platform, +set the jumper to ``JP35 3-4``. + +.. note:: A single jumper is required in JP35. + ++------+---------+---------+------+------+------+----------+ +| JP30 | JP31 | JP32 | JP33 | JP34 | JP40 | JP21 | +| VTR3 | VTR_PLL | VTR_REG | VTR1 | VTR2 | 3.3V | VREF_ADC | ++======+=========+=========+======+======+======+==========+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+---------+---------+------+------+------+----------+ + + ++------+------------+------+----------+ +| JP6 | JP36 | JP27 | JP4 | +| VBAT | VTR_ANALOG | PECI | VREF_VTT | ++======+============+======+==========+ +| 2-3 | 1-2 | 2-3 | open | ++------+------------+------+----------+ + +These jumpers configure nRESETI and JTAG_STRAP respectively. + ++-----------+---------------+ +| JP22 | JP29 | +| (nRESETI) | (JTAG_STRAP) | ++===========+===============+ +| 11-12 | 1-2 | ++-----------+---------------+ + +Boot-ROM Straps +--------------- + +These jumpers configure MEC1501 Boot-ROM straps. + ++-------------+------------+--------------+-------------+ +| JP37 | J6 | JP41 | JP23 | +| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | ++=============+============+==============+=============+ +| 1-2 | 1-2 | 1-2 | 3-4 | ++-------------+------------+--------------+-------------+ + + +``JP23 3-4`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples +SHD SPI CS0# and if high, it loads code from SHD SPI. +This is the recommended setup. + ++-------------+------------+----------------------------+ +| CR_STRAP | BSS_STRAP | SOURCE | ++-------------+------------+----------------------------+ +| 0 | X | Use 3.3V Private SPI | ++-------------+------------+----------------------------+ +| 1 | 0 | Use eSPI Flash channel | ++-------------+------------+----------------------------+ +| | 1 | Use 3.3V Shared channel(R)| ++-------------+------------+----------------------------+ + +Power management +---------------- +``JP20 2-3`` is required so all GPIOs powered by VTR3 rail worked at 1.8V. + +.. note:: External 1.8V needs to be connected to JP13.1 + ++-------------------+-----------------+ +| JP20 | JP13 | +| (VTR3 selection) | (1.8V source) | ++===================+=================+ +| 2-3 | 1.8V to pin 1 | ++-------------------+-----------------+ + + +Jumper location map +------------------- + +.. code-block:: none + + +--------------------------------------------------------------------------------------+ + | |------------| +----------+ J10 || | + | [BT1] + +------------+ J50 ++ ++ || | + | | JP38 JP43 ++ || || | + | + + + +-+ JP4 + + JP26 || || | + | JP6 + + + + + + + + || || | + | JP31 ++ JP32 JP36 +-+ JP27 + + + + J6 || | + | JP18 JP37 JP41 JP42 ++ | + | ++ + + +--------+ J48 | + | || JP21 + + +--------+ JP22 +----------+ | + | J2 || + JP34 JP30 J11 ++ | + | ++ + J44 || | + | ++ +----------------+ || | + | +---------------+ || + JP24 |----------------| ++ | + | |---------------| ++ + +----------+ +----------------+ J47 | + | JP20 +---------------+ JP23 JP40 +----------+ ++ | + | + ++ JP29 || | + | + + +----------+ + || | + | J52+---------------+ + + +----------+ J5 +-------------+ ++ | + | J45+---------------+ JP33 TP57 JP25 +-------------+ J4 J49 | + | | + | ++ TP4 +----------+ ++ | + | ++ + + + + + + TP61 +----------+ ++ | + | JP28 + + + + + TP65 + TP60 J51 JP35 | + | TP58 JP16 JP11 JP13 JP15 JP10 | + | TP5 | + | TP6 TP1 | + +--------------------------------------------------------------------------------------+ + + +Programming and Debugging +************************* + +Setup +===== + +#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within + that directory. For the pre-production MEC150x use the `MEC150x SPI Image Gen`_ + repository. + +#. Make the image generation available for Zephyr, by making the tool + searchable by path, or by setting an environment variable + ``EVERGLADES_SPI_GEN``, for example: + + .. code-block:: console + + export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE + + Note that the tools for Linux and Windows have different file names. + For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. + +#. If needed, a custom SPI image configuration file can be specified + to override the default one. + + .. code-block:: console + + export EVERGLADES_SPI_CFG=custom_spi_cfg.txt + + +Building +========== +#. Build :ref:`hello_world` application as you would normally do. + +#. Once you have ``zephyr.bin``, use the `MEC152x SPI Image Gen`_ microchip tool + to create the final binary. You need the output from this tool to flash + in the SHD SPI memory. + +Flashing +======== + +#. Connect Dediprog into header ``J2``. + +#. Flash the SPI NOR ``U3`` at offset 0x0 using Dediprog SF100 + or a similar tool for flashing SPI chips. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the MEC1501MODULAR_ASSY6885 board to your host computer using the + UART1 port and apply power. + + You should see ``"Hello World! mec1501modular_assy6885"`` in your terminal. + +Debugging +========= +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +HW Issues +========= +In case you don't see your application running, please make sure ``LED1`` is lit. +If is off, then check the power related jumpers again. + +References +********** +.. target-notes:: + +.. _MEC152x Preliminary Data Sheet: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC152x Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC1501 Modular EC Card - Assy_6885 Rev A0p1: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Modular%20EC%20Card%20-%20Assy_6885%20Rev%20A0p1%20-%20SCH.pdf +.. _MEC152x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen +.. _MEC150x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen diff --git a/boards/arm/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg b/boards/microchip/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg similarity index 100% rename from boards/arm/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg rename to boards/microchip/mec1501modular_assy6885/doc/mec1501modular_assy6885.jpg diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi similarity index 100% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885-pinctrl.dtsi diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts similarity index 100% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.yaml b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml similarity index 100% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.yaml rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml diff --git a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig similarity index 80% rename from boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig rename to boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig index 7ab9a08fba2fb8..1f9a9f937c5814 100644 --- a/boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig +++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig @@ -4,12 +4,9 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MEC1501_HSZ=y -CONFIG_SOC_SERIES_MEC1501X=y # Make sure external power management setup is as indicated in documentation CONFIG_SOC_MEC1501_VTR3_1_8V=y CONFIG_SOC_MEC1501_VCI_PINS_AS_GPIOS=n -CONFIG_BOARD_MEC1501MODULAR_ASSY6885=y CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/mec1501modular_assy6885/support/spi_cfg.txt b/boards/microchip/mec1501modular_assy6885/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec1501modular_assy6885/support/spi_cfg.txt rename to boards/microchip/mec1501modular_assy6885/support/spi_cfg.txt diff --git a/boards/arm/mec15xxevb_assy6853/CMakeLists.txt b/boards/microchip/mec15xxevb_assy6853/CMakeLists.txt similarity index 100% rename from boards/arm/mec15xxevb_assy6853/CMakeLists.txt rename to boards/microchip/mec15xxevb_assy6853/CMakeLists.txt diff --git a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig new file mode 100644 index 00000000000000..c4dae2ad32ee52 --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2019 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC15XXEVB_ASSY6853 + +config ESPI_XEC + default y + depends on ESPI + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 +# The driver requires tickless mode and ticks per +# second to be 32768 for accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 48MHz divided by +# SOC_MEC1501_PROC_CLK_DIV. +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 48000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + +endif # BOARD_MEC15XXEVB_ASSY6853 diff --git a/boards/microchip/mec15xxevb_assy6853/Kconfig.mec15xxevb_assy6853 b/boards/microchip/mec15xxevb_assy6853/Kconfig.mec15xxevb_assy6853 new file mode 100644 index 00000000000000..b5397e26932455 --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/Kconfig.mec15xxevb_assy6853 @@ -0,0 +1,5 @@ +# Copyright (c) 2019, Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC15XXEVB_ASSY6853 + select SOC_MEC1501_HSZ diff --git a/boards/arm/mec15xxevb_assy6853/board.cmake b/boards/microchip/mec15xxevb_assy6853/board.cmake similarity index 100% rename from boards/arm/mec15xxevb_assy6853/board.cmake rename to boards/microchip/mec15xxevb_assy6853/board.cmake diff --git a/boards/arm/mec15xxevb_assy6853/board.h b/boards/microchip/mec15xxevb_assy6853/board.h similarity index 100% rename from boards/arm/mec15xxevb_assy6853/board.h rename to boards/microchip/mec15xxevb_assy6853/board.h diff --git a/boards/microchip/mec15xxevb_assy6853/board.yml b/boards/microchip/mec15xxevb_assy6853/board.yml new file mode 100644 index 00000000000000..ae55848943856d --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/board.yml @@ -0,0 +1,5 @@ +board: + name: mec15xxevb_assy6853 + vendor: microchip + socs: + - name: mec1501_hsz diff --git a/boards/arm/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg b/boards/microchip/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg similarity index 100% rename from boards/arm/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg rename to boards/microchip/mec15xxevb_assy6853/doc/dediprog_connector_2.jpg diff --git a/boards/microchip/mec15xxevb_assy6853/doc/index.rst b/boards/microchip/mec15xxevb_assy6853/doc/index.rst new file mode 100644 index 00000000000000..e3b29e99212a5f --- /dev/null +++ b/boards/microchip/mec15xxevb_assy6853/doc/index.rst @@ -0,0 +1,467 @@ +.. _mec15xxevb_assy6853: + +Microchip MEC15xxEVB ASSY6853 +############################# + +Overview +******** + +The MEC15xxEVB_ASSY6853 kit is a future development platform to evaluate the +Microchip MEC15XX series microcontrollers. This board needs to be mated with +part number MEC1501 144WFBA SOLDER DC ASSY 6860(cpu board) in order to operate. +The MEC152x has superseded the MEC1501 in production. MEC152x is identical to +MEC150x except for an enhanced Boot-ROM SPI loader. The SPI image format has +been updated requiring a new SPI image tool. MEC1501 and MEC152x SPI image +formats are not compatible with each other. Evaluation and cpu boards are +compatible. + +.. image:: mec15xxevb_assy6853.jpg + :align: center + :alt: MEC15XX EVB ASSY 6853 + +Hardware +******** + +- MEC1521HA0SZ ARM Cortex-M4 Processor +- 256 KB RAM and 64 KB boot ROM +- Keyboard interface +- ADC & GPIO headers +- UART0, UART1, and UART2 +- FAN0, FAN1, FAN2 headers +- FAN PWM interface +- JTAG/SWD, ETM and MCHP Trace ports +- PECI interface 3.0 +- I2C voltage translator +- 10 SMBUS headers +- 4 SGPIO headers +- VCI interface +- 5 independent Hardware Driven PS/2 Ports +- eSPI header +- 3 Breathing/Blinking LEDs +- 2 Sockets for SPI NOR chips +- One reset and VCC_PWRDGD pushbuttons +- One external PCA9555 I/O port with jumper selectable I2C address. +- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. +- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. + +For more information about the SOC's please see `MEC152x Reference Manual`_ + +Supported Features +================== + +The mec15xxevb_assy6853 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PS/2 | on-chip | ps2 | ++-----------+------------+-------------------------------------+ +| KSCAN | on-chip | kscan | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer | ++-----------+------------+-------------------------------------+ + + + + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the +:zephyr_file:`boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig` Kconfig file. + +Connections and IOs +=================== + +This evaluation board kit is comprised of the following HW blocks: + +- MEC15xx EVB ASSY 6853 Rev A `MEC15xx EVB Schematic`_ +- MEC1501 144WFBA SOLDER DC ASSY 6883 with MEC152x silicon `MEC1501 Daughter Card Schematic`_ +- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ + +System Clock +============ + +The MEC1521 MCU is configured to use the 48Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== + +UART2 is configured for serial logs. + +Jumper settings +*************** + +Please follow the jumper settings below to properly demo this +board. Advanced users may deviate from this recommendation. + +Jumper setting for MEC15xx EVB Assy 6853 Rev A1p0 +================================================= + +Power-related jumpers +--------------------- + +If you wish to power from +5V power brick, then connect to barrel connector ``P11`` +(5.5mm OD, 2.1mm ID) and move the jumper to ``JP88 5-6``. + +If you wish to power from micro-USB type A/B connector ``P12``, move the +jumper to ``JP88 7-8``. + + +.. note:: A single jumper is required in JP88. + ++-------+------+------+------+------+------+------+------+------+------+------+ +| JP22 | JP32 | JP33 | JP37 | JP43 | JP47 | JP54 | JP56 | JP58 | JP64 | JP65 | ++=======+======+======+======+======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++-------+------+------+------+------+------+------+------+------+------+------+ + ++------+------+------+------+------+------+------+------+------+------+ +| JP72 | JP73 | JP76 | JP79 | JP80 | JP81 | JP82 | JP84 | JP87 | JP89 | ++======+======+======+======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+------+------+------+ + ++------+------+-------+-------+-------+ +| JP90 | JP91 | JP100 | JP101 | JP118 | ++======+======+=======+=======+=======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 2-3 | ++------+------+-------+-------+-------+ + +These jumpers configure VCC Power good, nRESETI and JTAG_STRAP respectively. + ++------------------+-----------+--------------+ +| JP5 | JP4 | JP45 | +| (VCC Power good) | (nRESETI) | (JTAG_STRAP) | ++==================+===========+==============+ +| 1-2 | 1-2 | 2-3 | ++------------------+-----------+--------------+ + +Boot-ROM Straps. +---------------- + +These jumpers configure MEC1501 Boot-ROM straps. + ++-------------+------------+--------------+-------------+ +| JP93 | JP11 | JP46 | JP96 | +| (CMP_STRAP) | (CR_STRAP) | (VTR2_STRAP) | (BSS_STRAP) | ++=============+============+==============+=============+ +| 2-3 | 1-2 | 2-3 | 1-2 | ++-------------+------------+--------------+-------------+ + +``JP96 1-2`` pulls SHD SPI CS0# up to VTR2. MEC1501 Boot-ROM samples +SHD SPI CS0# and if high, it loads code from SHD SPI. + +Peripheral Routing Jumpers +-------------------------- + +Each column of the following table illustrates how to enable UART2, SWD, +PVT SPI, SHD SPI and LED0-2 respectively. + ++----------+----------+--------+-----------+----------+---------+ +| JP48 | JP9 | JP9 | JP38 | JP98 | JP41 | +| (UART2) | (UART2) | (SWD) | (PVT SPI) | (SHD SPI)| (LED0-2)| ++==========+==========+========+===========+==========+=========+ +| 1-2 | | 2-3 | 2-3 | 2-3 | 1-2 | ++----------+----------+--------+-----------+----------+---------+ +| 4-5 | 4-5 | | 5-6 | 5-6 | 3-4 | ++----------+----------+--------+-----------+----------+---------+ +| 7-8 | | 8-9 | 8-9 | 8-9 | 5-6 | ++----------+----------+--------+-----------+----------+---------+ +| 10-11 | 10-11 | | 11-12 | 11-12 | | ++----------+----------+--------+-----------+----------+---------+ +| | | | 14-15 | 14-15 | | ++----------+----------+--------+-----------+----------+---------+ +| | | | 17-18 | 20-21 | | ++----------+----------+--------+-----------+----------+---------+ + +.. note:: For UART2 make sure JP39 have jumpers connected 1-2, 3-4. + +To receive UART2 serial output, please refer to the picture below +to make sure that JP9 configured for UART2 output. + +.. image:: mec15xxevb_assy6853_jp9_1.jpg + :align: center + :alt: JP9 header Assy6853 + +Jumper settings for MEC1501 144WFBGA Socket DC Assy 6883 Rev B1p0 +================================================================= + +The jumper configuration explained above covers the base board. The ASSY +6883 MEC1501 CPU board provides capability for an optional, external 32KHz +clock source. The card includes a 32KHz crystal oscillator. The card can +also be configured to use an external 50% duty cycle 32KHz source on the +XTAL2/32KHZ_IN pin. Note, firmware must set the MEC15xx clock enable +register to select the external source matching the jumper settings. If +using the MEC15xx internal silicon oscillator then the 32K jumper settings +are don't cares. ``JP1`` is for scoping test clock outputs. Please refer to +the schematic in reference section below. + +Parallel 32KHz crystal configuration +------------------------------------ ++-------+-------+ +| JP2 | JP3 | ++=======+=======+ +| 1-2 | 2-3 | ++-------+-------+ + +External 32KHz 50% duty cycle configuration +------------------------------------------- ++-------+-------+ +| JP2 | JP3 | ++=======+=======+ +| NC | 1-2 | ++-------+-------+ + + +Jumper settings for MEC1503 144WFBGA Socket DC Assy 6856 Rev B1p0 +================================================================= + +The MEC1503 ASSY 6856 CPU card does not include an onboard external +32K crystal or oscillator. The one jumper block ``JP1`` is for scoping +test clock outputs not for configuration. Please refer to schematic +in reference section below. + +Programming and Debugging +************************* + +Setup +===== +#. If you use Dediprog SF100 programmer, then setup it. + + Windows version can be found at the `SF100 Product page`_. + + Linux version source code can be found at `SF100 Linux GitHub`_. + Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. + For Linux please make sure that you copied ``60-dediprog.rules`` + from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) + then restart service using: + + .. code-block:: console + + $ udevadm control --reload + + Add directory with program ``dpcmd`` (on Linux) + or ``dpcmd.exe`` (on Windows) to your ``PATH``. + +#. Clone the `MEC152x SPI Image Gen`_ repository or download the files within + that directory. For the pre-production MEC150x use `MEC150x SPI Image Gen`_ + repository. + +#. Make the image generation available for Zephyr, by making the tool + searchable by path, or by setting an environment variable + ``EVERGLADES_SPI_GEN``, for example: + + .. code-block:: console + + export EVERGLADES_SPI_GEN=/everglades_spi_gen_RomE + + Note that the tools for Linux and Windows have different file names. + For the pre-production MEC1501 SOC use everglades_spi_gen_lin64. + +#. If needed, a custom SPI image configuration file can be specified + to override the default one. + + .. code-block:: console + + export EVERGLADES_SPI_CFG=custom_spi_cfg.txt + +Wiring +======== +#. Connect the SPI Dongle ASSY 6791 to ``J44`` in the EVB. + + .. image:: spidongle_assy6791_view1.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip ``U3`` + Make sure that your programmer's offset is 0x0. + For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. + + .. list-table:: Microchip board wiring + :align: center + + * - + .. image:: spidongle_assy6791.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 + + - + .. image:: spidongle_assy6791_view2.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 view 2 + + | + + .. image:: dediprog_connector_2.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + + + .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! + Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. + Wiring connection is described in the table below. + + +------------+---------------+ + | Dediprog | Assy6791 | + | Connector | J6 Connector | + +============+===============+ + | VCC | 1 | + +------------+---------------+ + | GND | 2 | + +------------+---------------+ + | CS | 3 | + +------------+---------------+ + | CLK | 4 | + +------------+---------------+ + | MISO | 6 | + +------------+---------------+ + | MOSI | 5 | + +------------+---------------+ + +#. Connect UART2 port of the MEC15xxEVB_ASSY_6853 board + to your host computer using the RS232 cable. + +#. Apply power to the board via a micro-USB cable. + Configure this option by using a jumper between ``JP88 7-8``. + + .. image:: jp88_power_options.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +#. Final wiring for the board should look like this: + + .. image:: mec_board_setup.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +Building +======== +#. Build :ref:`hello_world` application as you would normally do. + +#. The file :file:`spi_image.bin` will be created if the build system + can find the image generation tool. This binary image can be used + to flash the SPI chip. + +Flashing +======== +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Flash your board using ``west`` from the second terminal window. + Split first and second terminal windows to view both of them. + + .. code-block:: console + + $ west flash + + .. note:: When west process started press Reset button and do not release it + till the whole west process will not be finished successfully. + + .. image:: reset_button_1.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + + + .. note:: If you don't want to press Reset button every time, you can disconnect + SPI Dongle ASSY 6791 from the EVB during the west flash programming. + Then connect it back to the ``J44`` header and apply power to the EVB. + Result will be the same. + + +#. You should see ``"Hello World! mec15xxevb_assy6853"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Troubleshooting +=============== +#. In case you don't see your application running, please make sure ``LED7``, ``LED8``, and ``LED1`` + are lit. If one of these is off, then check the power-related jumpers again. + +#. If you can't program the board using Dediprog, disconnect the Assy6791 + from the main board Assy6853 and try again. + +#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. + +Notes +===== +#. To enable PCA9555PW and test the I2C on mec15xxevb_assy6853, additional works are needed: + + As the I2C slave device NXP pca95xx on mec15xxevb_assy6853 is connected to I2C00 port, + however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, + so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use + I2C01 port by making some jumpers setting as below: + + * JP99 1-2 Connected Connect I2C01_SDA from CPU to header J5 + * JP99 13-14 Connected Connect I2C01_SCL from CPU to header J5 + * JP25 21-22 Connected External pull-up for I2C01_SDA + * JP25 23-24 Connected External pull-up for I2C01_SCL + * + * JP44.1 J5.1 Connected Connect NXP PCA95xx to I2C01 + * JP44.3 J5.3 Connected Connect NXP PCA95xx to I2C01 + + +References +********** +.. target-notes:: + +.. _MEC1501 Preliminary Data Sheet: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf +.. _MEC1501 Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf +.. _MEC152x Preliminary Data Sheet: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC152x Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC152x/MEC152x_Datasheet.pdf +.. _MEC15xx EVB Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/Everglades%20EVB%20-%20Assy_6853%20Rev%20A1p1%20-%20SCH.pdf +.. _MEC1501 Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6883%20Rev%20A0p1%20-%20SCH.pdf +.. _MEC1503 Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1503%20Socket%20DC%20for%20EVERGLADES%20EVB%20-%20Assy_6856%20Rev%20A1p0%20-%20SCH.pdf +.. _SPI Dongle Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf +.. _MEC152x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC152x/SPI_image_gen +.. _MEC150x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC1501/SPI_image_gen +.. _SF100 Linux GitHub: + https://github.com/DediProgSW/SF100Linux +.. _SF100 Product page: + https://www.dediprog.com/product/SF100 +.. _SF100 Linux manual: + https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec15xxevb_assy6853/doc/jp88_power_options.jpg b/boards/microchip/mec15xxevb_assy6853/doc/jp88_power_options.jpg similarity index 100% rename from boards/arm/mec15xxevb_assy6853/doc/jp88_power_options.jpg rename to boards/microchip/mec15xxevb_assy6853/doc/jp88_power_options.jpg diff --git a/boards/arm/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg b/boards/microchip/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg similarity index 100% rename from boards/arm/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg rename to boards/microchip/mec15xxevb_assy6853/doc/mec15xxevb_assy6853.jpg diff --git a/boards/arm/mec15xxevb_assy6853/doc/mec15xxevb_assy6853_jp9_1.jpg b/boards/microchip/mec15xxevb_assy6853/doc/mec15xxevb_assy6853_jp9_1.jpg similarity index 100% rename from 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84b5a80a778470..ca03d9409cf15f 100644 --- a/boards/arm/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig +++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig @@ -4,10 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MEC1501_HSZ=y -CONFIG_SOC_SERIES_MEC1501X=y CONFIG_SOC_MEC1501_VTR3_1_8V=y -CONFIG_BOARD_MEC15XXEVB_ASSY6853=y CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/mec15xxevb_assy6853/support/spi_cfg.txt b/boards/microchip/mec15xxevb_assy6853/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec15xxevb_assy6853/support/spi_cfg.txt rename to boards/microchip/mec15xxevb_assy6853/support/spi_cfg.txt diff --git a/boards/arm/mec172xevb_assy6906/CMakeLists.txt b/boards/microchip/mec172xevb_assy6906/CMakeLists.txt similarity index 100% rename from boards/arm/mec172xevb_assy6906/CMakeLists.txt rename to boards/microchip/mec172xevb_assy6906/CMakeLists.txt diff --git a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig new file mode 100644 index 00000000000000..c31952ed76635d --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC172XEVB_ASSY6906 + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 Hz. +# The driver requires tickless mode and ticks per second to be 32768 for +# accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR +# processor clock divider register. We assume PCR processor clock divider +# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 96000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + +endif # BOARD_MEC172XEVB_ASSY6906 diff --git a/boards/microchip/mec172xevb_assy6906/Kconfig.mec172xevb_assy6906 b/boards/microchip/mec172xevb_assy6906/Kconfig.mec172xevb_assy6906 new file mode 100644 index 00000000000000..d11b63868115b9 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/Kconfig.mec172xevb_assy6906 @@ -0,0 +1,5 @@ +# Copyright (c) 2021, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC172XEVB_ASSY6906 + select SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xevb_assy6906/board.cmake b/boards/microchip/mec172xevb_assy6906/board.cmake similarity index 100% rename from boards/arm/mec172xevb_assy6906/board.cmake rename to boards/microchip/mec172xevb_assy6906/board.cmake diff --git a/boards/microchip/mec172xevb_assy6906/board.yml b/boards/microchip/mec172xevb_assy6906/board.yml new file mode 100644 index 00000000000000..5f3f57b29a7d23 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/board.yml @@ -0,0 +1,5 @@ +board: + name: mec172xevb_assy6906 + vendor: microchip + socs: + - name: mec172x_nsz diff --git a/boards/arm/mec172xevb_assy6906/doc/Reset_Button.jpg b/boards/microchip/mec172xevb_assy6906/doc/Reset_Button.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/Reset_Button.jpg rename to boards/microchip/mec172xevb_assy6906/doc/Reset_Button.jpg diff --git a/boards/arm/mec172xevb_assy6906/doc/dediprog_connector.jpg b/boards/microchip/mec172xevb_assy6906/doc/dediprog_connector.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/dediprog_connector.jpg rename to boards/microchip/mec172xevb_assy6906/doc/dediprog_connector.jpg diff --git a/boards/microchip/mec172xevb_assy6906/doc/index.rst b/boards/microchip/mec172xevb_assy6906/doc/index.rst new file mode 100644 index 00000000000000..a2100e5a2d6b00 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/doc/index.rst @@ -0,0 +1,479 @@ +.. _mec172xevb_assy6906: + +Microchip MEC172xEVB ASSY6906 +############################# + +Overview +******** + +The MEC172xEVB_ASSY6906 kit is a future development platform to evaluate the +Microchip MEC172X series microcontrollers. This board needs to be mated with +part number MEC172x 144WFBGA SOLDER DC ASSY 6914 (cpu board) in order to operate. +MEC172x and MEC152x SPI image formats are not compatible with each other. + +.. image:: mec172xevb_assy6906.jpg + :align: center + :alt: MEC172X EVB ASSY 6906 + +Hardware +******** + +- MEC172x ARM Cortex-M4 Processor +- 416 KB RAM and 128 KB boot ROM +- Keyboard interface +- ADC & GPIO headers +- UART0 and UART1 +- FAN0, FAN1, FAN2 headers +- FAN PWM interface +- JTAG/SWD, ETM and MCHP Trace ports +- PECI interface 3.0 +- I2C voltage translator +- 10 SMBUS headers +- VCI interface +- 1 Hardware Driven PS/2 Port +- eSPI header +- 2 Sockets for SPI NOR chips +- One reset and VCC_PWRDGD pushbuttons +- One external PCA9555 I/O port with jumper selectable I2C address. +- One external LTC2489 delta-sigma ADC with jumper selectable I2C address. +- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector. + +For more information about the SOC's please see `MEC172x Reference Manual`_ + +Supported Features +================== + +The mec172xevb_assy6906 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PS/2 | on-chip | ps2 | ++-----------+------------+-------------------------------------+ +| KSCAN | on-chip | kscan | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer | ++-----------+------------+-------------------------------------+ +| RPMFAN | on-chip | Fan speed controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the +:zephyr_file:`boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file. + +Connections and IOs +=================== + +This evaluation board kit is comprised of the following HW blocks: + +- MEC172x EVB ASSY 6906 Rev A `MEC172x EVB Schematic`_ +- MEC172x 144WFBGA SOLDER DC ASSY 6914 with MEC172x silicon `MEC172x Daughter Card Schematic`_ +- SPI DONGLE ASSY 6791 `SPI Dongle Schematic`_ + +System Clock +============ + +The MEC1723 MCU is configured to use the 96Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 12 MHz. See Processor clock +control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in +the references at the end of this document. + +Serial Port +=========== + +UART1 is configured for serial logs. + +Jumper settings +*************** + +Please follow the jumper settings below to properly demo this +board. Advanced users may deviate from this recommendation. + +Jumper setting for MEC172x EVB Assy 6906 Rev A1p0 +================================================= + +Power-related jumpers +--------------------- + +If you wish to power from +5V power brick, then connect to barrel connector ``P1`` +(5.5mm OD, 2.1mm ID) and move the jumper to ``JP30 5-6``. + +If you wish to power from micro-USB type A/B connector ``P2``, move the +jumper to ``JP30 7-8``. + + +.. note:: A single jumper is required in ``JP30``. + ++------+-------+-------+------+------+ +| JP31 | JP158 | JP159 | JP40 | JP42 | ++======+=======+=======+======+======+ +| 2-3 | 2-3 | 2-3 | 1-2 | 1-2 | ++------+-------+-------+------+------+ + ++------+------+------+------+------+------+------+ +| JP36 | JP37 | JP38 | JP39 | JP41 | JP43 | JP44 | ++======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+ + ++------+------+------+------+------+------+------+------+------+ +| JP45 | JP46 | JP47 | JP50 | JP51 | JP52 | JP55 | JP56 | JP57 | ++======+======+======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+------+------+ + ++------+------+------+------+------+------+------+ +| JP59 | JP60 | JP61 | JP62 | JP63 | JP65 | JP66 | ++======+======+======+======+======+======+======+ +| 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | 1-2 | ++------+------+------+------+------+------+------+ + +These jumpers configure VCC Power good and nRESET_IN. + ++------------------+-------------+ +| JP32 | JP33 | +| (VCC Power good) | (nRESET_IN) | ++==================+=============+ +| 1-2 | 1-2 | ++------------------+-------------+ + +Boot-ROM Straps +--------------- + +These jumpers configure MEC172x Boot-ROM straps. + ++------------+--------------+-------------+-------------+---------------+ +| JP1 | JP2 | JP3 | JP7 | JP160 | +| (CR_STRAP) | (JTAG_STRAP) | (CMP_STRAP) | (BSS_STRAP) | (UART_BSTRAP) | ++============+==============+=============+=============+===============+ +| 1-2 | 2-3 | 2-3 | 1-2 | 1-2 | ++------------+--------------+-------------+-------------+---------------+ + +``JP7 1-2`` pulls SHD SPI CS0# up to VTR2. MEC172x Boot-ROM samples +SHD SPI CS0# and if high, it loads code from SHD SPI. + +Peripheral Routing Jumpers +-------------------------- + +Each column of the following table illustrates how to enable UART0, UART1, SHD SPI +and SWD, respectively. + ++-------+-------+------+------+------+------+------+ +| UART0 (P11) | ++-------+-------+------+------+------+------+------+ +| JP13 | JP17 | JP19 | JP22 | JP88 | JP89 | JP93 | ++=======+=======+======+======+======+======+======+ +| 2-3 | 2-3 | 1-2 | 1-2 | 2-3 | 2-3 | 1-3 | ++-------+-------+------+------+------+------+------+ +| 5-6 | 5-6 | 4-5 | 4-5 | | | 2-4 | ++-------+-------+------+------+------+------+------+ +| 8-9 | 8-9 | | | | | | ++-------+-------+------+------+------+------+------+ +| 11-12 | 11-12 | | | | | | ++-------+-------+------+------+------+------+------+ +| 14-15 | 14-15 | | | | | | ++-------+-------+------+------+------+------+------+ +| 17-18 | 17-18 | | | | | | ++-------+-------+------+------+------+------+------+ +| | 20-21 | | | | | | ++-------+-------+------+------+------+------+------+ +| | 23-24 | | | | | | ++-------+-------+------+------+------+------+------+ + ++------+------+-------+-------+------+------+-------+-----+--------+------+------+------+-------+ +| UART1 | ++---------------------------------------------------+-------------------------------------------+ +| (P12) | (P2) | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| JP11 | JP14 | JP19 | JP24 | JP90 | JP94 | JP157 | JP11 | JP19 | JP24 | JP90 | JP94 | JP157 | ++======+======+=======+=======+======+======+=======+======+=======+======+======+======+=======+ +| 1-2 | 1-2 | 20-21 | 2-3 | 2-3 | 1-3 | 1-2 | 1-2 | 11-12 | 5-6 | 2-3 | 1-3 | 1-3 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| 4-5 | | | 5-6 | | 2-4 | 4-5 | 4-5 | | 8-9 | | 2-4 | 4-6 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| 8-9 | | | 8-9 | | | 7-8 | | |17-18 | | | 7-9 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| | | | 11-12 | | | 10-11 | | |23-24 | | | 10-12 | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| | | | 14-15 | | | | | | | | | | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ +| | | | 17-18 | | | | | | | | | | ++------+------+-------+-------+------+------+-------+------+-------+------+------+------+-------+ + +NOTE: The "Hello World" example outputs at ``UART1 P12`` . + ++----------------------+-------+--------+ +| SHD_SPI | SWD | LED4-5 | ++-------+------+-------+-------+--------+ +| JP23 | JP25 | JP156 | J18 | JP21 | ++=======+======+=======+=======+========+ +| 2-3 | 1-2 | 1-2 | 8-9 | 4-5 | ++-------+------+-------+-------+--------+ +| 8-9 | | | 11-12 | 16-17 | ++-------+------+-------+-------+--------+ +| 14-15 | | | | | ++-------+------+-------+-------+--------+ +| 17-18 | | | | | ++-------+------+-------+-------+--------+ + +Jumper settings for MEC172x 144WFBGA Socket DC Assy 6914 Rev A0p1 +================================================================= + +The jumper configuration explained above covers the base board. The ASSY +6914 MEC172x CPU board provides capability for an optional, external 32KHz +clock source. The card includes a 32KHz crystal oscillator. The card can +also be configured to use an external 50% duty cycle 32KHz source on the +XTAL2/32KHZ_IN pin. Note, firmware must set the MEC172x clock enable +register to select the external source matching the jumper settings. If +using the MEC172x internal silicon oscillator then the 32K jumper settings +are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please +refer to the schematic in reference section below. + +Parallel 32KHz crystal configuration +------------------------------------ + ++-------+-------+ +| JP1 | JP2 | ++=======+=======+ +| 1-2 | 2-3 | ++-------+-------+ + +External 32KHz 50% duty cycle configuration +------------------------------------------- + ++-------+-------+ +| JP2 | JP3 | ++=======+=======+ +| NC | 1-2 | ++-------+-------+ + +NOTE: ``JP121 3-4`` on base board also needs to be loaded. + + +Programming and Debugging +************************* + +Setup +===== + +#. If you use Dediprog SF100 programmer, then setup it. + + Windows version can be found at the `SF100 Product page`_. + + Linux version source code can be found at `SF100 Linux GitHub`_. + Follow the `SF100 Linux manual`_ to complete setup of the SF100 programmer. + For Linux please make sure that you copied ``60-dediprog.rules`` + from the ``SF100Linux`` folder to the :code:`/etc/udev/rules.s` (or rules.d) + then restart service using: + + .. code-block:: console + + $ udevadm control --reload + + Add directory with program ``dpcmd`` (on Linux) + or ``dpcmd.exe`` (on Windows) to your ``PATH``. + +#. Clone the `MEC172x SPI Image Gen`_ repository or download the files within + that directory. + +#. Make the image generation available for Zephyr, by making the tool + searchable by path, or by setting an environment variable + ``MEC172X_SPI_GEN``, for example: + + .. code-block:: console + + export MEC172X_SPI_GEN=/mec172x_spi_gen_lin_x86_64 + + Note that the tools for Linux and Windows have different file names. + +#. The default MEC172X_SPI_CFG file is spi_cfg.txt located in ${BOARD_DIR}/support. + If needed, a custom SPI image configuration file can be specified to override the + default one. + + .. code-block:: console + + export MEC172X_SPI_CFG=custom_spi_cfg.txt + +Wiring +======== + +#. Connect the SPI Dongle ASSY 6791 to ``J34`` in the EVB. + + .. image:: spidongle_assy6791.jpg + :align: center + :alt: SPI DONGLE ASSY 6791 Connected + +#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip + ``U3``. Make sure that your programmer's offset is 0x0. + For programming you can use Dediprog SF100 or a similar tool for flashing SPI chips. + + .. image:: dediprog_connector.jpg + :align: center + :alt: SF100 Connected + + + .. note:: Remember that SPI MISO/MOSI are swapped on Dediprog headers! + Use separate wires to connect Dediprog pins with pins on the Assy6791 SPI board. + Wiring connection is described in the table below. + + +------------+---------------+ + | Dediprog | Assy6791 | + | Connector | J6 Connector | + +============+===============+ + | VCC | 1 | + +------------+---------------+ + | GND | 2 | + +------------+---------------+ + | CS | 3 | + +------------+---------------+ + | CLK | 4 | + +------------+---------------+ + | MISO | 6 | + +------------+---------------+ + | MOSI | 5 | + +------------+---------------+ + +#. Connect UART1 port of the MEC17xxEVB_ASSY_6906 board + to your host computer using the RS232 cable. + +#. Apply power to the board via a micro-USB cable. + Configure this option by using a jumper between ``JP30 7-8``. + + .. image:: jp30_power_options.jpg + :align: center + :alt: Power Connection + +Building +======== + +#. Build :ref:`hello_world` application as you would normally do. + +#. The file :file:`spi_image.bin` will be created if the build system + can find the image generation tool. This binary image can be used + to flash the SPI chip. + +Flashing +======== + +#. Run your favorite terminal program to listen for output. + Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. + + For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Flash your board using ``west`` from the second terminal window. + Split first and second terminal windows to view both of them. + + .. code-block:: console + + $ west flash + + .. note:: When west process started press Reset button ``S2`` and do not release it + till the whole west process will not be finished successfully. + + .. image:: Reset_Button.jpg + :align: center + :alt: Reset Button + + .. note:: If you don't want to press Reset button every time, you can disconnect + SPI Dongle ASSY 6791 from the EVB during the west flash programming. + Then connect it back to the ``J34`` header and apply power to the EVB. + Result will be the same. + + +#. You should see ``"Hello World! mec172xevb_assy6906"`` in the first terminal window. + If you don't see this message, press the Reset button and the message should appear. + +Debugging +========= + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Troubleshooting +=============== + +#. In case you don't see your application running, please make sure ``LED1`` and ``LED2`` + are lit. If one of these is off, then check the power-related jumpers again. + +#. If you can't program the board using Dediprog, disconnect the Assy6791 + from the main board Assy6906 and try again. + +#. If Dediprog can't detect the onboard flash, press the board's Reset button and try again. + +PCA9555 Enabling +================ +#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed: + + As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port, + however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log, + so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use + I2C01 port by making some jumpers setting as below: + + +---------+---------+------------------------------------------+ + | Pin 1 | Pin 2 | Comment | + +=========+=========+==========================================+ + | JP49.1 | JP49.2 | Connect PCA9555 VCC to +3.3V_STBY | + +---------+---------+------------------------------------------+ + | JP53.1 | JP53.2 | Select address 0100b, which means 0x26 | + +---------+---------+------------------------------------------+ + | JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 | + +---------+---------+------------------------------------------+ + | JP12.4 | JP12.5 | Connect I2C01_SCL from CPU to header J20 | + +---------+---------+------------------------------------------+ + | JP77.7 | JP77.8 | External pull-up for I2C01_SDA | + +---------+---------+------------------------------------------+ + | JP77.9 | JP77.10 | External pull-up for I2C01_SCL | + +---------+---------+------------------------------------------+ + | JP58.1 | JP20.1 | Connect NXP PCA9555 SCL to I2C01 | + +---------+---------+------------------------------------------+ + | JP58.3 | JP20.3 | Connect NXP PCA9555 SDA to I2C01 | + +---------+---------+------------------------------------------+ + +References +********** + +.. target-notes:: + +.. _MEC172x Reference Manual: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172x-Data-Sheet.pdf +.. _MEC172x EVB Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-EVB-Assy_6906-A1p0-SCH.pdf +.. _MEC172x Daughter Card Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC172x/MEC172X-144WFBGA-Socket-DC-Assy6914-Rev-A-SCH.pdf +.. _SPI Dongle Schematic: + https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/SPI%20Dongles%20and%20Aardvark%20Interposer%20Assy%206791%20Rev%20A1p1%20-%20SCH.pdf +.. _MEC172x SPI Image Gen: + https://github.com/MicrochipTech/CPGZephyrDocs/tree/master/MEC172x/SPI_image_gen +.. _SF100 Linux GitHub: + https://github.com/DediProgSW/SF100Linux +.. _SF100 Product page: + https://www.dediprog.com/product/SF100 +.. _SF100 Linux manual: + https://www.dediprog.com/download/save/727.pdf diff --git a/boards/arm/mec172xevb_assy6906/doc/jp30_power_options.jpg b/boards/microchip/mec172xevb_assy6906/doc/jp30_power_options.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/jp30_power_options.jpg rename to boards/microchip/mec172xevb_assy6906/doc/jp30_power_options.jpg diff --git a/boards/arm/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg b/boards/microchip/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg rename to boards/microchip/mec172xevb_assy6906/doc/mec172xevb_assy6906.jpg diff --git a/boards/arm/mec172xevb_assy6906/doc/spidongle_assy6791.jpg b/boards/microchip/mec172xevb_assy6906/doc/spidongle_assy6791.jpg similarity index 100% rename from boards/arm/mec172xevb_assy6906/doc/spidongle_assy6791.jpg rename to boards/microchip/mec172xevb_assy6906/doc/spidongle_assy6791.jpg diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts similarity index 100% rename from boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.dts rename to boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts diff --git a/boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.yaml similarity index 100% rename from boards/arm/mec172xevb_assy6906/mec172xevb_assy6906.yaml rename to boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.yaml diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig new file mode 100644 index 00000000000000..a925bc7538db31 --- /dev/null +++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_RTOS_TIMER=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py b/boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py similarity index 98% rename from boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py rename to boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py index 14482fd093f1ee..38d4bc39d8815f 100755 --- a/boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py +++ b/boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py @@ -31,7 +31,7 @@ product: mec172xevb_assy6906 runner: misc-flasher runner_params: - - /boards/arm/mec172xevb_assy6906/support/mec172x_remote_flasher.py + - /boards/microchip/mec172xevb_assy6906/support/mec172x_remote_flasher.py - serial_pty: "nc,," diff --git a/boards/arm/mec172xevb_assy6906/support/spi_cfg.txt b/boards/microchip/mec172xevb_assy6906/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec172xevb_assy6906/support/spi_cfg.txt rename to boards/microchip/mec172xevb_assy6906/support/spi_cfg.txt diff --git a/boards/arm/mec172xmodular_assy6930/CMakeLists.txt b/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/CMakeLists.txt rename to boards/microchip/mec172xmodular_assy6930/CMakeLists.txt diff --git a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig new file mode 100644 index 00000000000000..c0ad2565043351 --- /dev/null +++ b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Copyright (c) 2022 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MEC172XMODULAR_ASSY6930 + +if RTOS_TIMER + +# XEC RTOS timer HW frequency is fixed at 32768 Hz. +# The driver requires tickless mode and ticks per second to be 32768 for +# accurate operation. + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +endif # RTOS_TIMER + +if !RTOS_TIMER + +# If RTOS timer is not enabled we use ARM Cortex-M +# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR +# processor clock divider register. We assume PCR processor clock divider +# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV +# + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 96000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +endif # RTOS_TIMER + +endif # BOARD_MEC172XMODULAR_ASSY6930 diff --git a/boards/microchip/mec172xmodular_assy6930/Kconfig.mec172xmodular_assy6930 b/boards/microchip/mec172xmodular_assy6930/Kconfig.mec172xmodular_assy6930 new file mode 100644 index 00000000000000..a9c6469db85525 --- /dev/null +++ b/boards/microchip/mec172xmodular_assy6930/Kconfig.mec172xmodular_assy6930 @@ -0,0 +1,5 @@ +# Copyright (c) 2022, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MEC172XMODULAR_ASSY6930 + select SOC_MEC172X_NSZ diff --git a/boards/arm/mec172xmodular_assy6930/board.cmake b/boards/microchip/mec172xmodular_assy6930/board.cmake similarity index 100% rename from boards/arm/mec172xmodular_assy6930/board.cmake rename to boards/microchip/mec172xmodular_assy6930/board.cmake diff --git a/boards/microchip/mec172xmodular_assy6930/board.yml b/boards/microchip/mec172xmodular_assy6930/board.yml new file mode 100644 index 00000000000000..1fe04eba6e8a56 --- /dev/null +++ b/boards/microchip/mec172xmodular_assy6930/board.yml @@ -0,0 +1,5 @@ +board: + name: mec172xmodular_assy6930 + vendor: microchip + socs: + - name: mec172x_nsz diff --git a/boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg similarity index 100% rename from boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg rename to boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.jpg diff --git a/boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst similarity index 98% rename from boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst rename to boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst index 457cb85edaa010..a3a854873426b0 100644 --- a/boards/arm/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst +++ b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst @@ -85,7 +85,7 @@ The mec172xmodular_assy6930 (Rev. B) board configuration supports the following Other hardware features are not currently supported by Zephyr (at the moment) The default configuration can be found in the -:zephyr_file:`boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig` Kconfig file. +:zephyr_file:`boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig` Kconfig file. Connections and IOs =================== @@ -205,7 +205,7 @@ Setup .. code-block:: console - west build -p auto -b mec172xmodular_assy6930 samples/hello_world -- -DMEC172X_SPI_GEN=$HOME/CPGZephyrDocs/MEC172x/SPI_image_gen/mec172x_spi_gen_lin_x86_64 -DMEC172X_SPI_CFG=$HOME/zephyrproject/zephyr/boards/arm/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt + west build -p auto -b mec172xmodular_assy6930 samples/hello_world -- -DMEC172X_SPI_GEN=$HOME/CPGZephyrDocs/MEC172x/SPI_image_gen/mec172x_spi_gen_lin_x86_64 -DMEC172X_SPI_CFG=$HOME/zephyrproject/zephyr/boards/microchip/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt Wiring diff --git a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts similarity index 100% rename from boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.dts rename to boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts diff --git a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml similarity index 100% rename from boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml rename to boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.yaml diff --git a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig similarity index 76% rename from boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig rename to boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig index 4ebe3b29bf87d9..0df404e408f87d 100644 --- a/boards/arm/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig +++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MEC172X_NSZ=y -CONFIG_SOC_SERIES_MEC172X=y -CONFIG_BOARD_MEC172XMODULAR_ASSY6930=y CONFIG_RTOS_TIMER=y CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/mec172xmodular_assy6930/support/spi_cfg.txt b/boards/microchip/mec172xmodular_assy6930/support/spi_cfg.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/support/spi_cfg.txt rename to boards/microchip/mec172xmodular_assy6930/support/spi_cfg.txt diff --git a/boards/arm/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt b/boards/microchip/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt rename to boards/microchip/mec172xmodular_assy6930/support/spi_cfg_128MBit.txt diff --git a/boards/arm/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt b/boards/microchip/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt similarity index 100% rename from boards/arm/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt rename to boards/microchip/mec172xmodular_assy6930/support/spi_cfg_4MBit.txt diff --git a/boards/microchip/mpfs_icicle/Kconfig b/boards/microchip/mpfs_icicle/Kconfig new file mode 100644 index 00000000000000..bbacc84d304f36 --- /dev/null +++ b/boards/microchip/mpfs_icicle/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2021-2022 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPFS_ICICLE + select 64BIT + select SCHED_IPI_SUPPORTED + select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle new file mode 100644 index 00000000000000..cc744a4f94064b --- /dev/null +++ b/boards/microchip/mpfs_icicle/Kconfig.mpfs_icicle @@ -0,0 +1,5 @@ +# Copyright (c) 2021-2022 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MPFS_ICICLE + select SOC_POLARFIRE diff --git a/boards/riscv/mpfs_icicle/board.cmake b/boards/microchip/mpfs_icicle/board.cmake similarity index 100% rename from boards/riscv/mpfs_icicle/board.cmake rename to boards/microchip/mpfs_icicle/board.cmake diff --git a/boards/microchip/mpfs_icicle/board.yml b/boards/microchip/mpfs_icicle/board.yml new file mode 100644 index 00000000000000..a4976aa909b429 --- /dev/null +++ b/boards/microchip/mpfs_icicle/board.yml @@ -0,0 +1,5 @@ +board: + name: mpfs_icicle + vendor: microchip + socs: + - name: polarfire diff --git a/boards/riscv/mpfs_icicle/doc/index.rst b/boards/microchip/mpfs_icicle/doc/index.rst similarity index 100% rename from boards/riscv/mpfs_icicle/doc/index.rst rename to boards/microchip/mpfs_icicle/doc/index.rst diff --git a/boards/riscv/mpfs_icicle/mpfs_icicle.dts b/boards/microchip/mpfs_icicle/mpfs_icicle.dts similarity index 100% rename from boards/riscv/mpfs_icicle/mpfs_icicle.dts rename to boards/microchip/mpfs_icicle/mpfs_icicle.dts diff --git a/boards/riscv/mpfs_icicle/mpfs_icicle.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle.yaml similarity index 100% rename from boards/riscv/mpfs_icicle/mpfs_icicle.yaml rename to boards/microchip/mpfs_icicle/mpfs_icicle.yaml diff --git a/boards/riscv/mpfs_icicle/mpfs_icicle_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_defconfig similarity index 80% rename from boards/riscv/mpfs_icicle/mpfs_icicle_defconfig rename to boards/microchip/mpfs_icicle/mpfs_icicle_defconfig index 60df70677e1232..0e3812d078df7b 100644 --- a/boards/riscv/mpfs_icicle/mpfs_icicle_defconfig +++ b/boards/microchip/mpfs_icicle/mpfs_icicle_defconfig @@ -1,12 +1,9 @@ # Copyright (c) 2020-2021 Microchip Technology Inc # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_POLARFIRE=y -CONFIG_SOC_POLARFIRE=y CONFIG_MPFS_HAL=n CONFIG_BASE64=y CONFIG_INCLUDE_RESET_VECTOR=y -CONFIG_BOARD_MPFS_ICICLE=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/mpfs_icicle/support/mpfs250t.resc b/boards/microchip/mpfs_icicle/support/mpfs250t.resc similarity index 100% rename from boards/riscv/mpfs_icicle/support/mpfs250t.resc rename to boards/microchip/mpfs_icicle/support/mpfs250t.resc diff --git a/boards/mikroe/clicker_2/Kconfig.defconfig b/boards/mikroe/clicker_2/Kconfig.defconfig new file mode 100644 index 00000000000000..0bec9d8d1b24af --- /dev/null +++ b/boards/mikroe/clicker_2/Kconfig.defconfig @@ -0,0 +1,12 @@ +# MikroE Clicker 2 board configuration + +# Copyright (c) 2020 Trifork +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIKROE_CLICKER_2 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif #BOARD_MIKROE_CLICKER_2 diff --git a/boards/mikroe/clicker_2/Kconfig.mikroe_clicker_2 b/boards/mikroe/clicker_2/Kconfig.mikroe_clicker_2 new file mode 100644 index 00000000000000..811134eef033d4 --- /dev/null +++ b/boards/mikroe/clicker_2/Kconfig.mikroe_clicker_2 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Trifork +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_CLICKER_2 + select SOC_STM32F407XG diff --git a/boards/arm/mikroe_clicker_2/board.cmake b/boards/mikroe/clicker_2/board.cmake similarity index 100% rename from boards/arm/mikroe_clicker_2/board.cmake rename to boards/mikroe/clicker_2/board.cmake diff --git a/boards/mikroe/clicker_2/board.yml b/boards/mikroe/clicker_2/board.yml new file mode 100644 index 00000000000000..8ffead86036def --- /dev/null +++ b/boards/mikroe/clicker_2/board.yml @@ -0,0 +1,5 @@ +board: + name: mikroe_clicker_2 + vendor: mikroe + socs: + - name: stm32f407xx diff --git a/boards/arm/mikroe_clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg b/boards/mikroe/clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg similarity index 100% rename from boards/arm/mikroe_clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg rename to boards/mikroe/clicker_2/doc/img/clicker-2-stm32f4-thickbox_default-2.jpg diff --git a/boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst similarity index 97% rename from boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst rename to boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst index 76ee5d81867e12..99cb9ce0c61aa5 100644 --- a/boards/arm/mikroe_clicker_2/doc/mikroe_clicker_2.rst +++ b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst @@ -54,9 +54,8 @@ The Zephyr MikroE Clicker 2 configuration supports the following hardware featur Other hardware features have not been enabled yet for this board. -The default configuration can be found in the defconfig file: - - ``boards/arm/mikroe_clicker_2/mikroe_clicker_2_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/mikroe/clicker_2/mikroe_clicker_2_defconfig` Connections and IOs =================== diff --git a/boards/arm/mikroe_clicker_2/mikroe_clicker_2.dts b/boards/mikroe/clicker_2/mikroe_clicker_2.dts similarity index 100% rename from boards/arm/mikroe_clicker_2/mikroe_clicker_2.dts rename to boards/mikroe/clicker_2/mikroe_clicker_2.dts diff --git a/boards/arm/mikroe_clicker_2/mikroe_clicker_2.yaml b/boards/mikroe/clicker_2/mikroe_clicker_2.yaml similarity index 100% rename from boards/arm/mikroe_clicker_2/mikroe_clicker_2.yaml rename to boards/mikroe/clicker_2/mikroe_clicker_2.yaml diff --git a/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig b/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig new file mode 100644 index 00000000000000..2c36e734c578ad --- /dev/null +++ b/boards/mikroe/clicker_2/mikroe_clicker_2_defconfig @@ -0,0 +1,17 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/mikroe/index.rst b/boards/mikroe/index.rst new file mode 100644 index 00000000000000..e1471b2139fb1b --- /dev/null +++ b/boards/mikroe/index.rst @@ -0,0 +1,10 @@ +.. _boards-mikroe: + +MikroElektronika d.o.o. +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/mikroe/mini_m4_for_stm32/Kconfig.defconfig b/boards/mikroe/mini_m4_for_stm32/Kconfig.defconfig new file mode 100644 index 00000000000000..c2f0b85f4c6b08 --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Mikroe MINI-M4 for STM32 board configuration + +# Copyright (c) 2019, Kwon Tae-young +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIKROE_MINI_M4_FOR_STM32 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_MIKROE_MINI_M4_FOR_STM32 diff --git a/boards/mikroe/mini_m4_for_stm32/Kconfig.mikroe_mini_m4_for_stm32 b/boards/mikroe/mini_m4_for_stm32/Kconfig.mikroe_mini_m4_for_stm32 new file mode 100644 index 00000000000000..0d55a5cd14d609 --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/Kconfig.mikroe_mini_m4_for_stm32 @@ -0,0 +1,5 @@ +# Copyright (c) 2019, Kwon Tae-young +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIKROE_MINI_M4_FOR_STM32 + select SOC_STM32F415XX diff --git a/boards/arm/mikroe_mini_m4_for_stm32/board.cmake b/boards/mikroe/mini_m4_for_stm32/board.cmake similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/board.cmake rename to boards/mikroe/mini_m4_for_stm32/board.cmake diff --git a/boards/mikroe/mini_m4_for_stm32/board.yml b/boards/mikroe/mini_m4_for_stm32/board.yml new file mode 100644 index 00000000000000..60dde764fe6fba --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/board.yml @@ -0,0 +1,5 @@ +board: + name: mikroe_mini_m4_for_stm32 + vendor: mikroe + socs: + - name: stm32f415xx diff --git a/boards/arm/mikroe_mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg b/boards/mikroe/mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg rename to boards/mikroe/mini_m4_for_stm32/doc/img/mikroe_mini_m4_for_stm32.jpg diff --git a/boards/arm/mikroe_mini_m4_for_stm32/doc/img/st-linkv2.jpg b/boards/mikroe/mini_m4_for_stm32/doc/img/st-linkv2.jpg similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/doc/img/st-linkv2.jpg rename to boards/mikroe/mini_m4_for_stm32/doc/img/st-linkv2.jpg diff --git a/boards/arm/mikroe_mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst similarity index 97% rename from boards/arm/mikroe_mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst rename to boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst index 4536296915ed5d..7198f2da36e8e3 100644 --- a/boards/arm/mikroe_mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst +++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst @@ -85,9 +85,8 @@ features: Other hardware features have not been enabled yet for this board. -The default configuration can be found in the defconfig file: - - ``boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig` Serial Port =========== diff --git a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts rename to boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.dts diff --git a/boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml rename to boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml diff --git a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig new file mode 100644 index 00000000000000..201c26b992aa37 --- /dev/null +++ b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig @@ -0,0 +1,20 @@ +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/mikroe_mini_m4_for_stm32/support/openocd.cfg b/boards/mikroe/mini_m4_for_stm32/support/openocd.cfg similarity index 100% rename from boards/arm/mikroe_mini_m4_for_stm32/support/openocd.cfg rename to boards/mikroe/mini_m4_for_stm32/support/openocd.cfg diff --git a/boards/mips/index.rst b/boards/mips/index.rst deleted file mode 100644 index 011f9d74cd4ea4..00000000000000 --- a/boards/mips/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-mips: - -MIPS Boards -########### - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/mips/qemu_malta/Kconfig.board b/boards/mips/qemu_malta/Kconfig.board deleted file mode 100644 index 4716bd6dbe51bc..00000000000000 --- a/boards/mips/qemu_malta/Kconfig.board +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_QEMU_MALTA - bool "QEMU emulation for little endian MIPS Malta" - depends on SOC_QEMU_MALTA - select QEMU_TARGET - -config BOARD_QEMU_MALTA_BE - bool "QEMU emulation for big endian MIPS Malta" - depends on SOC_QEMU_MALTA - select QEMU_TARGET - select BIG_ENDIAN diff --git a/boards/mips/qemu_malta/Kconfig.defconfig b/boards/mips/qemu_malta/Kconfig.defconfig deleted file mode 100644 index 4a583be0d9e444..00000000000000 --- a/boards/mips/qemu_malta/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_QEMU_MALTA || BOARD_QEMU_MALTA_BE - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_malta" if BOARD_QEMU_MALTA - default "qemu_malta_be" if BOARD_QEMU_MALTA_BE - -endif # BOARD_QEMU_MALTA || BOARD_QEMU_MALTA_BE diff --git a/boards/mips/qemu_malta/doc/index.rst b/boards/mips/qemu_malta/doc/index.rst deleted file mode 100644 index abca31380611e3..00000000000000 --- a/boards/mips/qemu_malta/doc/index.rst +++ /dev/null @@ -1,106 +0,0 @@ -.. _qemu_malta: - -MIPS Malta Emulation (QEMU) -########################### - -Overview -******** - -This board configuration will use QEMU to emulate the MIPS Malta platform. - -This configuration provides support for an MIPS 4Kc/24Kc CPU cores and these devices: - -* CP0 Interrupt Controller -* CP0 Core Timer -* NS16550 UART - - -.. note:: - This board configuration makes no claims about its suitability for use - with an actual MIPS Malta hardware system, or any other hardware system. - -Hardware -******** - -Supported Features -================== - -The following hardware features are supported: - -+----------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+================+============+======================+ -| CP0 IntC | on-chip | interrupt controller | -+----------------+------------+----------------------+ -| CP0 Core Timer | on-chip | system clock | -+----------------+------------+----------------------+ -| NS16550 | FPGA | serial port | -| UART | | | -+----------------+------------+----------------------+ - -The kernel currently does not support other hardware features on this platform. - -Devices -======== -System Clock ------------- - -Qemu CP0 timer uses a clock frequency of 200 MHz, -see target/mips/cp0_timer.c in Qemu source tree for details. - -Serial Port ------------ - -This board configuration uses a single serial communication channel -with the FPGA UART2. - -Programming and Debugging -************************* - -Use this configuration to run basic Zephyr applications and kernel tests in the QEMU -emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_malta - :goals: run - -This will build an image with the synchronization sample app, boot it using -QEMU, and display the following console output: - -.. code-block:: console - - *** Booting Zephyr OS build v2.7.99-1627-g9bea7790d620 *** - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - thread_a: Hello World from cpu 0 on qemu_malta! - thread_b: Hello World from cpu 0 on qemu_malta! - - -Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. - - -Big-Endian -========== - -Use this configuration to run :zephyr:code-sample:`synchronization` sample in big-endian mode: - -.. zephyr-app-commands:: - :zephyr-app: samples/synchronization - :host-os: unix - :board: qemu_malta_be - :goals: run - - -References -********** - -https://www.qemu.org/ -https://www.linux-mips.org/wiki/MIPS_Malta diff --git a/boards/mips/qemu_malta/qemu_malta_be.yaml b/boards/mips/qemu_malta/qemu_malta_be.yaml deleted file mode 100644 index 91a9444d00b24e..00000000000000 --- a/boards/mips/qemu_malta/qemu_malta_be.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_malta_be -name: QEMU emulation for MIPS (big endian) -type: qemu -simulation: qemu -arch: mips -toolchain: - - zephyr - - xtools -ram: 1024 -flash: 512 -testing: - default: true - ignore_tags: - - net - - bluetooth -vendor: qemu diff --git a/boards/mips/qemu_malta/qemu_malta_be_defconfig b/boards/mips/qemu_malta/qemu_malta_be_defconfig deleted file mode 100644 index cbdcfed736af03..00000000000000 --- a/boards/mips/qemu_malta/qemu_malta_be_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_SOC_QEMU_MALTA=y -CONFIG_BOARD_QEMU_MALTA_BE=y -CONFIG_MIPS_CP0_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/mips/qemu_malta/qemu_malta_defconfig b/boards/mips/qemu_malta/qemu_malta_defconfig deleted file mode 100644 index edf9e1478976a1..00000000000000 --- a/boards/mips/qemu_malta/qemu_malta_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_SOC_QEMU_MALTA=y -CONFIG_BOARD_QEMU_MALTA=y -CONFIG_MIPS_CP0_TIMER=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_QEMU_ICOUNT=y -CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/mxchip/az3166_iotdevkit/Kconfig.az3166_iotdevkit b/boards/mxchip/az3166_iotdevkit/Kconfig.az3166_iotdevkit new file mode 100644 index 00000000000000..6e28ac7185bd2f --- /dev/null +++ b/boards/mxchip/az3166_iotdevkit/Kconfig.az3166_iotdevkit @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Benjamin Cabé +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_AZ3166_IOTDEVKIT + select SOC_STM32F412RX diff --git a/boards/arm/az3166_iotdevkit/az3166_iotdevkit.dts b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts similarity index 100% rename from boards/arm/az3166_iotdevkit/az3166_iotdevkit.dts rename to boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.dts diff --git a/boards/arm/az3166_iotdevkit/az3166_iotdevkit.yaml b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml similarity index 100% rename from boards/arm/az3166_iotdevkit/az3166_iotdevkit.yaml rename to boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml diff --git a/boards/arm/az3166_iotdevkit/az3166_iotdevkit_defconfig b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig similarity index 85% rename from boards/arm/az3166_iotdevkit/az3166_iotdevkit_defconfig rename to boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig index 883b48c262280c..ee16a27c1e186f 100644 --- a/boards/arm/az3166_iotdevkit/az3166_iotdevkit_defconfig +++ b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412RX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/az3166_iotdevkit/board.cmake b/boards/mxchip/az3166_iotdevkit/board.cmake similarity index 100% rename from boards/arm/az3166_iotdevkit/board.cmake rename to boards/mxchip/az3166_iotdevkit/board.cmake diff --git a/boards/mxchip/az3166_iotdevkit/board.yml b/boards/mxchip/az3166_iotdevkit/board.yml new file mode 100644 index 00000000000000..4ac727ed1c243e --- /dev/null +++ b/boards/mxchip/az3166_iotdevkit/board.yml @@ -0,0 +1,5 @@ +board: + name: az3166_iotdevkit + vendor: mxchip + socs: + - name: stm32f412rx diff --git a/boards/arm/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp b/boards/mxchip/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp similarity index 100% rename from boards/arm/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp rename to boards/mxchip/az3166_iotdevkit/doc/img/az3166-iotdevkit.webp diff --git a/boards/arm/az3166_iotdevkit/doc/index.rst b/boards/mxchip/az3166_iotdevkit/doc/index.rst similarity index 100% rename from boards/arm/az3166_iotdevkit/doc/index.rst rename to boards/mxchip/az3166_iotdevkit/doc/index.rst diff --git a/boards/arm/az3166_iotdevkit/support/openocd.cfg b/boards/mxchip/az3166_iotdevkit/support/openocd.cfg similarity index 100% rename from boards/arm/az3166_iotdevkit/support/openocd.cfg rename to boards/mxchip/az3166_iotdevkit/support/openocd.cfg diff --git a/boards/mxchip/index.rst b/boards/mxchip/index.rst new file mode 100644 index 00000000000000..9cad4f437d899c --- /dev/null +++ b/boards/mxchip/index.rst @@ -0,0 +1,10 @@ +.. _boards-mxchip: + +MXCHIP +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/posix/common/extra_args/CMakeLists.txt b/boards/native/common/extra_args/CMakeLists.txt similarity index 100% rename from boards/posix/common/extra_args/CMakeLists.txt rename to boards/native/common/extra_args/CMakeLists.txt diff --git a/boards/posix/common/extra_args/Kconfig b/boards/native/common/extra_args/Kconfig similarity index 100% rename from boards/posix/common/extra_args/Kconfig rename to boards/native/common/extra_args/Kconfig diff --git a/boards/posix/common/extra_args/extra_args.c b/boards/native/common/extra_args/extra_args.c similarity index 100% rename from boards/posix/common/extra_args/extra_args.c rename to boards/native/common/extra_args/extra_args.c diff --git a/boards/posix/common/irq/board_irq.h b/boards/native/common/irq/board_irq.h similarity index 100% rename from boards/posix/common/irq/board_irq.h rename to boards/native/common/irq/board_irq.h diff --git a/boards/posix/common/natsim_config.cmake b/boards/native/common/natsim_config.cmake similarity index 95% rename from boards/posix/common/natsim_config.cmake rename to boards/native/common/natsim_config.cmake index 54e800cd327362..d9decf2cacd426 100644 --- a/boards/posix/common/natsim_config.cmake +++ b/boards/native/common/natsim_config.cmake @@ -5,7 +5,7 @@ set(zephyr_build_path ${APPLICATION_BINARY_DIR}/zephyr) get_property(CCACHE GLOBAL PROPERTY RULE_LAUNCH_COMPILE) target_link_options(native_simulator INTERFACE - "-T ${ZEPHYR_BASE}/boards/posix/common/natsim_linker_script.ld") + "-T ${ZEPHYR_BASE}/boards/native/common/natsim_linker_script.ld") set(nsi_config_content ${nsi_config_content} diff --git a/boards/posix/common/natsim_linker_script.ld b/boards/native/common/natsim_linker_script.ld similarity index 100% rename from boards/posix/common/natsim_linker_script.ld rename to boards/native/common/natsim_linker_script.ld diff --git a/boards/posix/common/sdl/CMakeLists.txt b/boards/native/common/sdl/CMakeLists.txt similarity index 100% rename from boards/posix/common/sdl/CMakeLists.txt rename to boards/native/common/sdl/CMakeLists.txt diff --git a/boards/posix/common/sdl/Kconfig b/boards/native/common/sdl/Kconfig similarity index 100% rename from boards/posix/common/sdl/Kconfig rename to boards/native/common/sdl/Kconfig diff --git a/boards/posix/common/sdl/sdl_events.c b/boards/native/common/sdl/sdl_events.c similarity index 100% rename from boards/posix/common/sdl/sdl_events.c rename to boards/native/common/sdl/sdl_events.c diff --git a/boards/posix/common/sdl/sdl_events_bottom.c b/boards/native/common/sdl/sdl_events_bottom.c similarity index 100% rename from boards/posix/common/sdl/sdl_events_bottom.c rename to boards/native/common/sdl/sdl_events_bottom.c diff --git a/boards/posix/common/sdl/sdl_events_bottom.h b/boards/native/common/sdl/sdl_events_bottom.h similarity index 100% rename from boards/posix/common/sdl/sdl_events_bottom.h rename to boards/native/common/sdl/sdl_events_bottom.h diff --git a/boards/posix/doc/Port_vs_QEMU_vs.svg b/boards/native/doc/Port_vs_QEMU_vs.svg similarity index 100% rename from boards/posix/doc/Port_vs_QEMU_vs.svg rename to boards/native/doc/Port_vs_QEMU_vs.svg diff --git a/boards/posix/doc/Zephyr_and_bsim.svg b/boards/native/doc/Zephyr_and_bsim.svg similarity index 100% rename from boards/posix/doc/Zephyr_and_bsim.svg rename to boards/native/doc/Zephyr_and_bsim.svg diff --git a/boards/posix/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst similarity index 100% rename from boards/posix/doc/arch_soc.rst rename to boards/native/doc/arch_soc.rst diff --git a/boards/posix/doc/bsim_boards_design.rst b/boards/native/doc/bsim_boards_design.rst similarity index 100% rename from boards/posix/doc/bsim_boards_design.rst rename to boards/native/doc/bsim_boards_design.rst diff --git a/boards/posix/doc/layering.svg b/boards/native/doc/layering.svg similarity index 100% rename from boards/posix/doc/layering.svg rename to boards/native/doc/layering.svg diff --git a/boards/posix/doc/layering_natsim.svg b/boards/native/doc/layering_natsim.svg similarity index 100% rename from boards/posix/doc/layering_natsim.svg rename to boards/native/doc/layering_natsim.svg diff --git a/boards/posix/index.rst b/boards/native/index.rst similarity index 100% rename from boards/posix/index.rst rename to boards/native/index.rst diff --git a/boards/native/native_posix/CMakeLists.txt b/boards/native/native_posix/CMakeLists.txt new file mode 100644 index 00000000000000..b86941cc854281 --- /dev/null +++ b/boards/native/native_posix/CMakeLists.txt @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Oticon A/S + +zephyr_library() + +zephyr_library_compile_definitions(NO_POSIX_CHEATS) +zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L _XOPEN_SOURCE=600 _XOPEN_SOURCE_EXTENDED) + +zephyr_library_sources( + hw_models_top.c + timer_model.c + native_rtc.c + irq_handler.c + irq_ctrl.c + main.c + tracing.c + cmdline_common.c + cmdline.c + cpu_wait.c + hw_counter.c + ) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include + ) + +if(CONFIG_HAS_SDL) + add_subdirectory(${ZEPHYR_BASE}/boards/native/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) +endif() + +zephyr_ld_options( + -lm +) diff --git a/boards/native/native_posix/Kconfig b/boards/native/native_posix/Kconfig new file mode 100644 index 00000000000000..eee6cd26b03571 --- /dev/null +++ b/boards/native/native_posix/Kconfig @@ -0,0 +1,47 @@ +# Copyright (c) 2017 Oticon A/S +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_POSIX + bool + imply NATIVE_POSIX_TIMER + select POSIX_ARCH_CONSOLE + select NATIVE_APPLICATION + select 64BIT if BOARD_NATIVE_POSIX_NATIVE_64 + help + Native POSIX + Will produce a console Linux process which can be executed natively. + It provides some minimal needed models: + An interrupt controller, timer (system tick), and redirects kernel prints to + stdout. + +config BOARD_NATIVE_POSIX_64 + bool + select BOARD_NATIVE_POSIX + select 64BIT + help + Native POSIX - 64 bit version + Will produce a console Linux process which can be executed natively + as a 64-bit executable. + It provides some minimal needed models: + An interrupt controller, timer (system tick), and redirects kernel prints to + stdout. + +if BOARD_NATIVE_POSIX + +comment "Native POSIX options" + +config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME + bool "Slow down execution to real time" + default n if ARCH_POSIX_LIBFUZZER + default y if BT_USERCHAN || !TEST + help + When selected the execution of the process will be slowed down to real time. + (if there is a lot of load it may be slower than real time) + If deselected, the process will run as fast as possible. + Note that this only decouples simulated time from real/wall time. In either + case the zephyr kernel and application cannot tell the difference unless they + interact with some other driver/device which runs at real time. + +source "boards/native/common/sdl/Kconfig" + +endif # BOARD_NATIVE_POSIX diff --git a/boards/native/native_posix/Kconfig.defconfig b/boards/native/native_posix/Kconfig.defconfig new file mode 100644 index 00000000000000..5fc24d50c62a79 --- /dev/null +++ b/boards/native/native_posix/Kconfig.defconfig @@ -0,0 +1,69 @@ +# Copyright (c) 2017 Oticon A/S +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NATIVE_POSIX + +config BUILD_OUTPUT_BIN + default n + +config BUILD_OUTPUT_EXE + default y + +config OUTPUT_PRINT_MEMORY_USAGE + default n + +if NETWORKING + +config NET_L2_ETHERNET + default y if !NET_LOOPBACK && !NET_TEST + +config ETH_NATIVE_POSIX + default y if NET_L2_ETHERNET && ETH_DRIVER + +endif # NETWORKING + +choice BT_HCI_BUS_TYPE + default BT_USERCHAN + depends on BT_HCI +endchoice + +if LOG + +# For native_posix we can log synchronously without any problem +# Doing so will be nicer for debugging +choice LOG_MODE + default LOG_MODE_IMMEDIATE +endchoice + +endif # LOG + +if CONSOLE + +config POSIX_ARCH_CONSOLE + default y if !SERIAL + +config UART_CONSOLE + default y if SERIAL + +endif # CONSOLE + +config FLASH_SIMULATOR + default y + depends on FLASH + +config USB_NATIVE_POSIX + default y + depends on USB_DEVICE_DRIVER + +config EEPROM_SIMULATOR + default y + depends on EEPROM + +if I2C + +config EMUL + default y + +endif # I2C + +endif # BOARD_NATIVE_POSIX diff --git a/boards/native/native_posix/Kconfig.native_posix b/boards/native/native_posix/Kconfig.native_posix new file mode 100644 index 00000000000000..cb7c03889c425e --- /dev/null +++ b/boards/native/native_posix/Kconfig.native_posix @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_POSIX + select SOC_POSIX diff --git a/boards/native/native_posix/Kconfig.native_posix_64 b/boards/native/native_posix/Kconfig.native_posix_64 new file mode 100644 index 00000000000000..8151a52091004e --- /dev/null +++ b/boards/native/native_posix/Kconfig.native_posix_64 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_POSIX_64 + select SOC_POSIX diff --git a/boards/native/native_posix/board.cmake b/boards/native/native_posix/board.cmake new file mode 100644 index 00000000000000..f8c2fd58f87b8c --- /dev/null +++ b/boards/native/native_posix/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Oticon A/S + +set(SUPPORTED_EMU_PLATFORMS native) + +board_set_debugger_ifnset(native_gdb) +board_finalize_runner_args(native_gdb) diff --git a/boards/native/native_posix/board.yml b/boards/native/native_posix/board.yml new file mode 100644 index 00000000000000..8ab212aa1f9ad1 --- /dev/null +++ b/boards/native/native_posix/board.yml @@ -0,0 +1,15 @@ +boards: +- name: native_posix + vendor: zephyr + socs: + - name: native + variants: + - name: "64" + +# This board definition below, together with its respective +# Kconfig.native_posix_64 exist for backwards compatibility with the hwmv1 board name +# Once all its usage in tree is removed, or an alias has been introduced they can be removed. +- name: native_posix_64 + vendor: zephyr + socs: + - name: native diff --git a/boards/posix/native_posix/board_irq.h b/boards/native/native_posix/board_irq.h similarity index 100% rename from boards/posix/native_posix/board_irq.h rename to boards/native/native_posix/board_irq.h diff --git a/boards/posix/native_posix/board_soc.h b/boards/native/native_posix/board_soc.h similarity index 100% rename from boards/posix/native_posix/board_soc.h rename to boards/native/native_posix/board_soc.h diff --git a/boards/posix/native_posix/cmdline.c b/boards/native/native_posix/cmdline.c similarity index 100% rename from boards/posix/native_posix/cmdline.c rename to boards/native/native_posix/cmdline.c diff --git a/boards/posix/native_posix/cmdline.h b/boards/native/native_posix/cmdline.h similarity index 100% rename from boards/posix/native_posix/cmdline.h rename to boards/native/native_posix/cmdline.h diff --git a/boards/posix/native_posix/cmdline_common.c b/boards/native/native_posix/cmdline_common.c similarity index 100% rename from boards/posix/native_posix/cmdline_common.c rename to boards/native/native_posix/cmdline_common.c diff --git a/boards/posix/native_posix/cmdline_common.h b/boards/native/native_posix/cmdline_common.h similarity index 100% rename from boards/posix/native_posix/cmdline_common.h rename to boards/native/native_posix/cmdline_common.h diff --git a/boards/posix/native_posix/cpu_wait.c b/boards/native/native_posix/cpu_wait.c similarity index 100% rename from boards/posix/native_posix/cpu_wait.c rename to boards/native/native_posix/cpu_wait.c diff --git a/boards/posix/native_posix/doc/index.rst b/boards/native/native_posix/doc/index.rst similarity index 100% rename from boards/posix/native_posix/doc/index.rst rename to boards/native/native_posix/doc/index.rst diff --git a/boards/posix/native_posix/hw_counter.c b/boards/native/native_posix/hw_counter.c similarity index 100% rename from boards/posix/native_posix/hw_counter.c rename to boards/native/native_posix/hw_counter.c diff --git a/boards/posix/native_posix/hw_counter.h b/boards/native/native_posix/hw_counter.h similarity index 100% rename from boards/posix/native_posix/hw_counter.h rename to boards/native/native_posix/hw_counter.h diff --git a/boards/posix/native_posix/hw_models_top.c b/boards/native/native_posix/hw_models_top.c similarity index 100% rename from boards/posix/native_posix/hw_models_top.c rename to boards/native/native_posix/hw_models_top.c diff --git a/boards/posix/native_posix/hw_models_top.h b/boards/native/native_posix/hw_models_top.h similarity index 100% rename from boards/posix/native_posix/hw_models_top.h rename to boards/native/native_posix/hw_models_top.h diff --git a/boards/posix/native_posix/irq_ctrl.c b/boards/native/native_posix/irq_ctrl.c similarity index 100% rename from boards/posix/native_posix/irq_ctrl.c rename to boards/native/native_posix/irq_ctrl.c diff --git a/boards/posix/native_posix/irq_ctrl.h b/boards/native/native_posix/irq_ctrl.h similarity index 100% rename from boards/posix/native_posix/irq_ctrl.h rename to boards/native/native_posix/irq_ctrl.h diff --git a/boards/posix/native_posix/irq_handler.c b/boards/native/native_posix/irq_handler.c similarity index 100% rename from boards/posix/native_posix/irq_handler.c rename to boards/native/native_posix/irq_handler.c diff --git a/boards/posix/native_posix/irq_handler.h b/boards/native/native_posix/irq_handler.h similarity index 100% rename from boards/posix/native_posix/irq_handler.h rename to boards/native/native_posix/irq_handler.h diff --git a/boards/posix/native_posix/main.c b/boards/native/native_posix/main.c similarity index 100% rename from boards/posix/native_posix/main.c rename to boards/native/native_posix/main.c diff --git a/boards/posix/native_posix/native_posix.dts b/boards/native/native_posix/native_posix.dts similarity index 100% rename from boards/posix/native_posix/native_posix.dts rename to boards/native/native_posix/native_posix.dts diff --git a/boards/posix/native_posix/native_posix.yaml b/boards/native/native_posix/native_posix.yaml similarity index 100% rename from boards/posix/native_posix/native_posix.yaml rename to boards/native/native_posix/native_posix.yaml diff --git a/boards/posix/native_posix/native_posix_64.dts b/boards/native/native_posix/native_posix_64.dts similarity index 100% rename from boards/posix/native_posix/native_posix_64.dts rename to boards/native/native_posix/native_posix_64.dts diff --git a/boards/posix/native_posix/native_posix_64.yaml b/boards/native/native_posix/native_posix_64.yaml similarity index 100% rename from boards/posix/native_posix/native_posix_64.yaml rename to boards/native/native_posix/native_posix_64.yaml diff --git a/boards/native/native_posix/native_posix_64_defconfig b/boards/native/native_posix/native_posix_64_defconfig new file mode 100644 index 00000000000000..b0033eda61f9b6 --- /dev/null +++ b/boards/native/native_posix/native_posix_64_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/native/native_posix/native_posix_defconfig b/boards/native/native_posix/native_posix_defconfig new file mode 100644 index 00000000000000..b0033eda61f9b6 --- /dev/null +++ b/boards/native/native_posix/native_posix_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_posix/native_rtc.c b/boards/native/native_posix/native_rtc.c similarity index 100% rename from boards/posix/native_posix/native_rtc.c rename to boards/native/native_posix/native_rtc.c diff --git a/boards/posix/native_posix/native_rtc.h b/boards/native/native_posix/native_rtc.h similarity index 100% rename from boards/posix/native_posix/native_rtc.h rename to boards/native/native_posix/native_rtc.h diff --git a/boards/posix/native_posix/native_tracing.h b/boards/native/native_posix/native_tracing.h similarity index 100% rename from boards/posix/native_posix/native_tracing.h rename to boards/native/native_posix/native_tracing.h diff --git a/boards/posix/native_posix/timer_model.c b/boards/native/native_posix/timer_model.c similarity index 100% rename from boards/posix/native_posix/timer_model.c rename to boards/native/native_posix/timer_model.c diff --git a/boards/posix/native_posix/timer_model.h b/boards/native/native_posix/timer_model.h similarity index 100% rename from boards/posix/native_posix/timer_model.h rename to boards/native/native_posix/timer_model.h diff --git a/boards/posix/native_posix/tracing.c b/boards/native/native_posix/tracing.c similarity index 100% rename from boards/posix/native_posix/tracing.c rename to boards/native/native_posix/tracing.c diff --git a/boards/native/native_sim/CMakeLists.txt b/boards/native/native_sim/CMakeLists.txt new file mode 100644 index 00000000000000..2bb964f49e86c3 --- /dev/null +++ b/boards/native/native_sim/CMakeLists.txt @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_compile_definitions(NO_POSIX_CHEATS) + +zephyr_library_sources( + cmdline.c + cpu_wait.c + nsi_if.c + irq_handler.c + misc.c + posix_arch_if.c + ) + +zephyr_include_directories( + ${NSI_DIR}/common/src/include + ${NSI_DIR}/native/src/include +) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include +) + +if(CONFIG_HAS_SDL) + add_subdirectory(${ZEPHYR_BASE}/boards/native/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) +endif() + +add_subdirectory(${ZEPHYR_BASE}/boards/native/common/extra_args/ + ${CMAKE_CURRENT_BINARY_DIR}/extra_args +) + +set(nsi_config_content + ${nsi_config_content} + "NSI_NATIVE=1" +) + +include(../common/natsim_config.cmake) diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig new file mode 100644 index 00000000000000..e61028cce074e0 --- /dev/null +++ b/boards/native/native_sim/Kconfig @@ -0,0 +1,63 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_SIM + bool + select POSIX_ARCH_CONSOLE + select NATIVE_LIBRARY + select NATIVE_POSIX_TIMER + select 64BIT if BOARD_NATIVE_SIM_NATIVE_64 + imply BOARD_NATIVE_POSIX if NATIVE_SIM_NATIVE_POSIX_COMPAT + help + Native simulator (Single Core) + Will produce a console Linux process which can be executed natively. + +config BOARD_NATIVE_SIM_64 + bool + select BOARD_NATIVE_SIM + select 64BIT + help + Native simulator (Single Core) - 64 bit version + Will produce a console Linux process which can be executed natively + as a 64-bit executable. + +if BOARD_NATIVE_SIM + +comment "Native Simular (Single Core) options" + +config NATIVE_SIM_NATIVE_POSIX_COMPAT + bool "Pretend to be a native_posix board" + default y + help + When this option is set the native_sim board will pretend to be + a native_posix board from kconfig point of view, to allow using it directly with + code which was meant for the native_posix board and checks for the macro + CONFIG_BOARD_NATIVE_POSIX, or requires other kconfig options which depend on it. + +config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME + bool "Slow down execution to real time" + default n if ARCH_POSIX_LIBFUZZER + default y if BT_USERCHAN || !TEST + help + When selected the execution of the process will be slowed down to real time. + (if there is a lot of load it may be slower than real time) + If deselected, the process will run as fast as possible. + Note that this only decouples simulated time from real/wall time. In either + case the zephyr kernel and application cannot tell the difference unless they + interact with some other driver/device which runs at real time. + +# This option definition exists only to enable NATIVE_SIM_NATIVE_POSIX_COMPAT +config BOARD_NATIVE_POSIX + bool + +config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME + bool "Slow down execution to real time (native_posix compat)" + select NATIVE_SIM_SLOWDOWN_TO_REAL_TIME + help + Transitional option which allows applications which targeted native_posix + to set the correct native_sim option (CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME) + +source "boards/native/common/sdl/Kconfig" +source "boards/native/common/extra_args/Kconfig" + +endif # BOARD_NATIVE_SIM diff --git a/boards/native/native_sim/Kconfig.defconfig b/boards/native/native_sim/Kconfig.defconfig new file mode 100644 index 00000000000000..64657779d7ab99 --- /dev/null +++ b/boards/native/native_sim/Kconfig.defconfig @@ -0,0 +1,69 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NATIVE_SIM + +config BUILD_OUTPUT_BIN + default n + +config BUILD_OUTPUT_EXE + default y + +config OUTPUT_PRINT_MEMORY_USAGE + default n + +if NETWORKING + +config NET_L2_ETHERNET + default y if !NET_LOOPBACK && !NET_TEST + +config ETH_NATIVE_POSIX + default y if NET_L2_ETHERNET && ETH_DRIVER + +endif # NETWORKING + +choice BT_HCI_BUS_TYPE + default BT_USERCHAN + depends on BT_HCI +endchoice + +if LOG + +# For native_sim we can log synchronously without any problem +# Doing so will be nicer for debugging +choice LOG_MODE + default LOG_MODE_IMMEDIATE +endchoice + +endif # LOG + +if CONSOLE + +config POSIX_ARCH_CONSOLE + default y if !SERIAL + +config UART_CONSOLE + default y if SERIAL + +endif # CONSOLE + +config FLASH_SIMULATOR + default y + depends on FLASH + +config USB_NATIVE_POSIX + default y + depends on USB_DEVICE_DRIVER + +config EEPROM_SIMULATOR + default y + depends on EEPROM + +if I2C + +config EMUL + default y + +endif # I2C + +endif # BOARD_NATIVE_SIM diff --git a/boards/native/native_sim/Kconfig.native_sim b/boards/native/native_sim/Kconfig.native_sim new file mode 100644 index 00000000000000..8d75397d4908e1 --- /dev/null +++ b/boards/native/native_sim/Kconfig.native_sim @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_SIM + select SOC_POSIX diff --git a/boards/native/native_sim/Kconfig.native_sim_64 b/boards/native/native_sim/Kconfig.native_sim_64 new file mode 100644 index 00000000000000..c03791abd3581e --- /dev/null +++ b/boards/native/native_sim/Kconfig.native_sim_64 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NATIVE_SIM_64 + select SOC_POSIX diff --git a/boards/posix/native_posix/board.cmake b/boards/native/native_sim/board.cmake similarity index 100% rename from boards/posix/native_posix/board.cmake rename to boards/native/native_sim/board.cmake diff --git a/boards/native/native_sim/board.yml b/boards/native/native_sim/board.yml new file mode 100644 index 00000000000000..31ee9fabc08c7a --- /dev/null +++ b/boards/native/native_sim/board.yml @@ -0,0 +1,15 @@ +boards: +- name: native_sim + vendor: zephyr + socs: + - name: native + variants: + - name: "64" + +# This board definition below, together with its respective +# Kconfig.native_sim_64 exist for backwards compatibility with the hwmv1 board name +# Once all its usage in tree is removed, or an alias has been introduced they can be removed. +- name: native_sim_64 + vendor: zephyr + socs: + - name: native diff --git a/boards/posix/native_sim/board_irq.h b/boards/native/native_sim/board_irq.h similarity index 100% rename from boards/posix/native_sim/board_irq.h rename to boards/native/native_sim/board_irq.h diff --git a/boards/posix/native_sim/board_soc.h b/boards/native/native_sim/board_soc.h similarity index 100% rename from boards/posix/native_sim/board_soc.h rename to boards/native/native_sim/board_soc.h diff --git a/boards/posix/native_sim/cmdline.c b/boards/native/native_sim/cmdline.c similarity index 100% rename from boards/posix/native_sim/cmdline.c rename to boards/native/native_sim/cmdline.c diff --git a/boards/posix/native_sim/cmdline.h b/boards/native/native_sim/cmdline.h similarity index 100% rename from boards/posix/native_sim/cmdline.h rename to boards/native/native_sim/cmdline.h diff --git a/boards/posix/native_sim/cmdline_common.h b/boards/native/native_sim/cmdline_common.h similarity index 100% rename from boards/posix/native_sim/cmdline_common.h rename to boards/native/native_sim/cmdline_common.h diff --git a/boards/posix/native_sim/cpu_wait.c b/boards/native/native_sim/cpu_wait.c similarity index 100% rename from boards/posix/native_sim/cpu_wait.c rename to boards/native/native_sim/cpu_wait.c diff --git a/boards/posix/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst similarity index 100% rename from boards/posix/native_sim/doc/index.rst rename to boards/native/native_sim/doc/index.rst diff --git a/boards/posix/native_sim/irq_handler.c b/boards/native/native_sim/irq_handler.c similarity index 100% rename from boards/posix/native_sim/irq_handler.c rename to boards/native/native_sim/irq_handler.c diff --git a/boards/posix/native_sim/irq_handler.h b/boards/native/native_sim/irq_handler.h similarity index 100% rename from boards/posix/native_sim/irq_handler.h rename to boards/native/native_sim/irq_handler.h diff --git a/boards/posix/native_sim/misc.c b/boards/native/native_sim/misc.c similarity index 100% rename from boards/posix/native_sim/misc.c rename to boards/native/native_sim/misc.c diff --git a/boards/posix/native_sim/native_posix_compat.h b/boards/native/native_sim/native_posix_compat.h similarity index 100% rename from boards/posix/native_sim/native_posix_compat.h rename to boards/native/native_sim/native_posix_compat.h diff --git a/boards/posix/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts similarity index 100% rename from boards/posix/native_sim/native_sim.dts rename to boards/native/native_sim/native_sim.dts diff --git a/boards/posix/native_sim/native_sim.yaml b/boards/native/native_sim/native_sim.yaml similarity index 100% rename from boards/posix/native_sim/native_sim.yaml rename to boards/native/native_sim/native_sim.yaml diff --git a/boards/posix/native_sim/native_sim_64.dts b/boards/native/native_sim/native_sim_64.dts similarity index 100% rename from boards/posix/native_sim/native_sim_64.dts rename to boards/native/native_sim/native_sim_64.dts diff --git a/boards/posix/native_sim/native_sim_64.yaml b/boards/native/native_sim/native_sim_64.yaml similarity index 100% rename from boards/posix/native_sim/native_sim_64.yaml rename to boards/native/native_sim/native_sim_64.yaml diff --git a/boards/native/native_sim/native_sim_64_defconfig b/boards/native/native_sim/native_sim_64_defconfig new file mode 100644 index 00000000000000..b0033eda61f9b6 --- /dev/null +++ b/boards/native/native_sim/native_sim_64_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/native/native_sim/native_sim_defconfig b/boards/native/native_sim/native_sim_defconfig new file mode 100644 index 00000000000000..b0033eda61f9b6 --- /dev/null +++ b/boards/native/native_sim/native_sim_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_sim/nsi_if.c b/boards/native/native_sim/nsi_if.c similarity index 100% rename from boards/posix/native_sim/nsi_if.c rename to boards/native/native_sim/nsi_if.c diff --git a/boards/posix/native_sim/posix_arch_if.c b/boards/native/native_sim/posix_arch_if.c similarity index 100% rename from boards/posix/native_sim/posix_arch_if.c rename to boards/native/native_sim/posix_arch_if.c diff --git a/boards/posix/native_sim/timer_model.h b/boards/native/native_sim/timer_model.h similarity index 100% rename from boards/posix/native_sim/timer_model.h rename to boards/native/native_sim/timer_model.h diff --git a/boards/native/nrf_bsim/CMakeLists.txt b/boards/native/nrf_bsim/CMakeLists.txt new file mode 100644 index 00000000000000..a4329cd888007d --- /dev/null +++ b/boards/native/nrf_bsim/CMakeLists.txt @@ -0,0 +1,80 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# Copyright (c) 2018 Oticon A/S +# SPDX-License-Identifier: Apache-2.0 + +find_package(BabbleSim) + +zephyr_library() + +# Due to the BLE controller assumption about enum size +zephyr_compile_options( + -fshort-enums +) +# Structures layouts needs to match in the interface between the runner and the embedded SW +# The nrfx HAL uses enums in its definitions,so they need to have the same size in both, +# as both the HW models and embedded SW use them. +target_compile_options(native_simulator INTERFACE -fshort-enums) + +zephyr_library_sources( + irq_handler.c + cpu_wait.c + argparse.c + nsi_if.c + soc/nrfx_coredep.c + common/bstests_entry.c + common/cmsis/cmsis.c + common/trace_hook.c +) + +# Include sync_rtc from real SOC code if enabled +zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC + ${ZEPHYR_BASE}/soc/nordic/nrf53/sync_rtc.c + ) + +target_sources(native_simulator INTERFACE + common/bsim_args_runner.c + common/bsim_extra_cpu_if_stubs.c + common/phy_sync_ctrl.c + common/runner_hooks.c + common/posix_arch_if.c + common/trace_hook.c +) + +if (CONFIG_IPC_SERVICE AND CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP) + zephyr_library_sources( + ipc_backend.c + ) +endif() + +zephyr_include_directories( + soc + common + common/cmsis + ${NSI_DIR}/common/src/include +) + +zephyr_library_include_directories( + ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ + ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ + ${BSIM_COMPONENTS_PATH}/libRandv2/src/ + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include + common/ +) + +set(libpath ${BSIM_OUT_PATH}/lib) +set_property(TARGET native_simulator APPEND PROPERTY RUNNER_LINK_LIBRARIES + ${libpath}/libUtilv1.32.a + ${libpath}/libPhyComv1.32.a + ${libpath}/lib2G4PhyComv1.32.a + ${libpath}/libRandv2.32.a +) + +target_compile_options(native_simulator INTERFACE + "-DNSI_PRIMARY_MCU_N=${CONFIG_NATIVE_SIMULATOR_PRIMARY_MCU_INDEX}") + +add_subdirectory(${ZEPHYR_BASE}/boards/native/common/extra_args/ + ${CMAKE_CURRENT_BINARY_DIR}/extra_args +) + +include(../common/natsim_config.cmake) diff --git a/boards/native/nrf_bsim/Kconfig b/boards/native/nrf_bsim/Kconfig new file mode 100644 index 00000000000000..caed5baf8b6a9b --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig @@ -0,0 +1,93 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_BSIM + bool + select SOC_SERIES_BSIM_NRF52X + select SOC_COMPATIBLE_NRF52833 + select NRF_RTC_TIMER + select CLOCK_CONTROL + help + NRF52 simulation model + Will produce a console Linux process which can be executed natively. + It needs the BabbleSim simulator both in compile time and to execute + +config BOARD_NRF5340BSIM_NRF5340_CPUNET + bool + select SOC_SERIES_BSIM_NRF53X + select SOC_COMPATIBLE_NRF5340_CPUNET + select NRF_RTC_TIMER + select CLOCK_CONTROL + help + Simulated NRF53 Network core + Will produce a console Linux process which can be executed natively. + It needs the BabbleSim simulator both in compile time and to execute + +config BOARD_NRF5340BSIM_NRF5340_CPUAPP + bool + select SOC_SERIES_BSIM_NRF53X + select SOC_COMPATIBLE_NRF5340_CPUAPP + select NRF_RTC_TIMER + select CLOCK_CONTROL + help + Simulated NRF53 Application core + Will produce a console Linux process which can be executed natively. + It needs the BabbleSim simulator both in compile time and to execute + + +if SOC_SERIES_BSIM_NRFXX + +# The following file is normally parsed only for the ARM architecture, which is +# used by Nordic SoCs, so to make the symbols defined in this file available for +# the simulated nrf5x_bsim boards, which use the POSIX architecture, the file +# must be read also from here. +source "soc/nordic/common/Kconfig.peripherals" + +source "boards/native/common/extra_args/Kconfig" + +endif # SOC_SERIES_BSIM_NRFXX + + +# This would eventually be shared by a possible family of simulated NRF boards +# which use BabbleSim. When that happens, we can move this to a common +# Kconfig file + +config SOC_SERIES_BSIM_NRFXX + bool + select NATIVE_LIBRARY + select SOC_COMPATIBLE_NRF + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select PINCTRL_DYNAMIC if PINCTRL + help + Any NRF simulated SOC with BabbleSim, based on the POSIX arch + +config SOC_SERIES_BSIM_NRF52X + bool + select SOC_SERIES_BSIM_NRFXX + select SOC_COMPATIBLE_NRF52X + help + Any NRF52 simulated SOC with BabbleSim, based on the POSIX arch + +config SOC_SERIES_BSIM_NRF53X + bool + select SOC_SERIES_BSIM_NRFXX + select SOC_COMPATIBLE_NRF53X + help + Any NRF53 simulated SOC with BabbleSim, based on the POSIX arch + +if BOARD_NRF5340BSIM_NRF5340_CPUAPP + +# Replica of the option provided by the BOARD_NRF5340DK_NRF5340_CPUAPP board so samples can be +# reused as is +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + +endif # BOARD_NRF5340BSIM_NRF5340_CPUNET + +if SOC_SERIES_BSIM_NRF53X + +# Let's reuse the RTC sync options so applications which use it can be reused as is +source "soc/nordic/nrf53/Kconfig.sync_rtc" + +endif # SOC_SERIES_BSIM_NRF53X diff --git a/boards/native/nrf_bsim/Kconfig.defconfig b/boards/native/nrf_bsim/Kconfig.defconfig new file mode 100644 index 00000000000000..639c5d47428b12 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.defconfig @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +if SOC_SERIES_BSIM_NRFXX + +config BUILD_OUTPUT_BIN + default n + +config BUILD_OUTPUT_EXE + # When the IPC service is used, the net core image requires the application core image, as it needs + # access to its IPC buffer. Without it, the executable cannot be built. + default y if !(BOARD_NRF5340BSIM_NRF5340_CPUNET && IPC_SERVICE && (NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS = "")) + +config OUTPUT_PRINT_MEMORY_USAGE + default n + +config NATIVE_SIMULATOR_NUMBER_MCUS + default 2 if BOARD_NRF5340BSIM_NRF5340_CPUNET || BOARD_NRF5340BSIM_NRF5340_CPUAPP + default 1 + +config NATIVE_SIMULATOR_MCU_N + default 1 if BOARD_NRF5340BSIM_NRF5340_CPUNET + default 0 + +config NATIVE_SIMULATOR_AUTOSTART_MCU + default y if BOARD_NRF5340BSIM_NRF5340_CPUNET + +config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX + default 1 if SOC_SERIES_BSIM_NRF53X + default 0 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 128 if !TICKLESS_KERNEL + default 32768 + +config BT_CTLR + default y if BOARD_NRF52_BSIM || BOARD_NRF5340BSIM_NRF5340_CPUNET + depends on BT + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP + default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET + +if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET + +config MBOX_NRFX_IPC + default MBOX + +endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET + +if BOARD_NRF5340BSIM_NRF5340_CPUAPP + +config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET + default y if IPC_SERVICE_BACKEND_RPMSG + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC +endchoice + +endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP + +# The 15.4 driver Tx encryption is currently not functional with this +# simulated board => we disable it by default. With this Openthread will normally +# default to encrypt packets on its own. +config NRF_802154_ENCRYPTION + default n + +if LOG + +# For this board we can log synchronously without any problem +# Doing so will be nicer for debugging +choice LOG_MODE + default LOG_MODE_IMMEDIATE +endchoice + +endif # LOG + +if CONSOLE + +config POSIX_ARCH_CONSOLE + default y + +endif # CONSOLE + +endif # SOC_SERIES_BSIM_NRFXX diff --git a/boards/native/nrf_bsim/Kconfig.nrf52_bsim b/boards/native/nrf_bsim/Kconfig.nrf52_bsim new file mode 100644 index 00000000000000..c4cc397af5bee5 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf52_bsim @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_BSIM + select SOC_POSIX diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim b/boards/native/nrf_bsim/Kconfig.nrf5340bsim new file mode 100644 index 00000000000000..7847a16ab76ab1 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf5340bsim @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340BSIM + select SOC_POSIX diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp new file mode 100644 index 00000000000000..8e342000c3e507 --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpuapp @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340BSIM_NRF5340_CPUAPP + select SOC_POSIX diff --git a/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet new file mode 100644 index 00000000000000..e6867244e773da --- /dev/null +++ b/boards/native/nrf_bsim/Kconfig.nrf5340bsim_nrf5340_cpunet @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340BSIM_NRF5340_CPUNET + select SOC_POSIX diff --git a/boards/posix/nrf_bsim/argparse.c b/boards/native/nrf_bsim/argparse.c similarity index 100% rename from boards/posix/nrf_bsim/argparse.c rename to boards/native/nrf_bsim/argparse.c diff --git a/boards/posix/nrf_bsim/argparse.h b/boards/native/nrf_bsim/argparse.h similarity index 100% rename from boards/posix/nrf_bsim/argparse.h rename to boards/native/nrf_bsim/argparse.h diff --git a/boards/native/nrf_bsim/board.cmake b/boards/native/nrf_bsim/board.cmake new file mode 100644 index 00000000000000..70a6c0f0f4ded5 --- /dev/null +++ b/boards/native/nrf_bsim/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +set(SUPPORTED_EMU_PLATFORMS native) + +board_set_debugger_ifnset(native_gdb) +board_finalize_runner_args(native_gdb) diff --git a/boards/native/nrf_bsim/board.yml b/boards/native/nrf_bsim/board.yml new file mode 100644 index 00000000000000..20c9137a233fb9 --- /dev/null +++ b/boards/native/nrf_bsim/board.yml @@ -0,0 +1,23 @@ +boards: +- name: nrf52_bsim + vendor: zephyr + socs: + - name: native +- name: nrf5340bsim + vendor: zephyr + socs: + # Note this is referring to the real SOC yaml, but we only use its name and cpu-cluster definition + # In practice this board uses the same native SOC (SOC_POSIX) as the nrf52_bsim + - name: nrf5340 + +# These two board definitions below, together with their respective +# Kconfig.nrf5340bsim_nrf5340_cpu[app,net] exist for backwards compatibility with hwmv1 usage +# Once all their usage in tree is removed, or aliases have been introduced they can be removed. +- name: nrf5340bsim_nrf5340_cpuapp + vendor: zephyr + socs: + - name: native +- name: nrf5340bsim_nrf5340_cpunet + vendor: zephyr + socs: + - name: native diff --git a/boards/posix/nrf_bsim/board_irq.h b/boards/native/nrf_bsim/board_irq.h similarity index 100% rename from boards/posix/nrf_bsim/board_irq.h rename to boards/native/nrf_bsim/board_irq.h diff --git a/boards/posix/nrf_bsim/board_soc.h b/boards/native/nrf_bsim/board_soc.h similarity index 100% rename from boards/posix/nrf_bsim/board_soc.h rename to boards/native/nrf_bsim/board_soc.h diff --git a/boards/posix/nrf_bsim/common/README.txt b/boards/native/nrf_bsim/common/README.txt similarity index 100% rename from boards/posix/nrf_bsim/common/README.txt rename to boards/native/nrf_bsim/common/README.txt diff --git a/boards/posix/nrf_bsim/common/bsim_args_runner.c b/boards/native/nrf_bsim/common/bsim_args_runner.c similarity index 100% rename from boards/posix/nrf_bsim/common/bsim_args_runner.c rename to boards/native/nrf_bsim/common/bsim_args_runner.c diff --git a/boards/posix/nrf_bsim/common/bsim_args_runner.h b/boards/native/nrf_bsim/common/bsim_args_runner.h similarity index 100% rename from boards/posix/nrf_bsim/common/bsim_args_runner.h rename to boards/native/nrf_bsim/common/bsim_args_runner.h diff --git a/boards/posix/nrf_bsim/common/bsim_extra_cpu_if_stubs.c b/boards/native/nrf_bsim/common/bsim_extra_cpu_if_stubs.c similarity index 100% rename from boards/posix/nrf_bsim/common/bsim_extra_cpu_if_stubs.c rename to boards/native/nrf_bsim/common/bsim_extra_cpu_if_stubs.c diff --git a/boards/posix/nrf_bsim/common/bstests.h b/boards/native/nrf_bsim/common/bstests.h similarity index 100% rename from boards/posix/nrf_bsim/common/bstests.h rename to boards/native/nrf_bsim/common/bstests.h diff --git a/boards/posix/nrf_bsim/common/bstests_entry.c b/boards/native/nrf_bsim/common/bstests_entry.c similarity index 100% rename from boards/posix/nrf_bsim/common/bstests_entry.c rename to boards/native/nrf_bsim/common/bstests_entry.c diff --git a/boards/posix/nrf_bsim/common/cmdline.h b/boards/native/nrf_bsim/common/cmdline.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmdline.h rename to boards/native/nrf_bsim/common/cmdline.h diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis.c b/boards/native/nrf_bsim/common/cmsis/cmsis.c similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis.c rename to boards/native/nrf_bsim/common/cmsis/cmsis.c diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis.h b/boards/native/nrf_bsim/common/cmsis/cmsis.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis.h rename to boards/native/nrf_bsim/common/cmsis/cmsis.h diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis_compiler.h b/boards/native/nrf_bsim/common/cmsis/cmsis_compiler.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis_compiler.h rename to boards/native/nrf_bsim/common/cmsis/cmsis_compiler.h diff --git a/boards/posix/nrf_bsim/common/cmsis/cmsis_instr.h b/boards/native/nrf_bsim/common/cmsis/cmsis_instr.h similarity index 100% rename from boards/posix/nrf_bsim/common/cmsis/cmsis_instr.h rename to boards/native/nrf_bsim/common/cmsis/cmsis_instr.h diff --git a/boards/posix/nrf_bsim/common/phy_sync_ctrl.c b/boards/native/nrf_bsim/common/phy_sync_ctrl.c similarity index 100% rename from boards/posix/nrf_bsim/common/phy_sync_ctrl.c rename to boards/native/nrf_bsim/common/phy_sync_ctrl.c diff --git a/boards/posix/nrf_bsim/common/phy_sync_ctrl.h b/boards/native/nrf_bsim/common/phy_sync_ctrl.h similarity index 100% rename from boards/posix/nrf_bsim/common/phy_sync_ctrl.h rename to boards/native/nrf_bsim/common/phy_sync_ctrl.h diff --git a/boards/posix/nrf_bsim/common/posix_arch_if.c b/boards/native/nrf_bsim/common/posix_arch_if.c similarity index 100% rename from boards/posix/nrf_bsim/common/posix_arch_if.c rename to boards/native/nrf_bsim/common/posix_arch_if.c diff --git a/boards/posix/nrf_bsim/common/runner_hooks.c b/boards/native/nrf_bsim/common/runner_hooks.c similarity index 100% rename from boards/posix/nrf_bsim/common/runner_hooks.c rename to boards/native/nrf_bsim/common/runner_hooks.c diff --git a/boards/posix/nrf_bsim/common/trace_hook.c b/boards/native/nrf_bsim/common/trace_hook.c similarity index 100% rename from boards/posix/nrf_bsim/common/trace_hook.c rename to boards/native/nrf_bsim/common/trace_hook.c diff --git a/boards/posix/nrf_bsim/cpu_wait.c b/boards/native/nrf_bsim/cpu_wait.c similarity index 100% rename from boards/posix/nrf_bsim/cpu_wait.c rename to boards/native/nrf_bsim/cpu_wait.c diff --git a/boards/posix/nrf_bsim/doc/nrf52_bsim.rst b/boards/native/nrf_bsim/doc/nrf52_bsim.rst similarity index 100% rename from boards/posix/nrf_bsim/doc/nrf52_bsim.rst rename to boards/native/nrf_bsim/doc/nrf52_bsim.rst diff --git a/boards/posix/nrf_bsim/doc/nrf5340bsim.rst b/boards/native/nrf_bsim/doc/nrf5340bsim.rst similarity index 100% rename from boards/posix/nrf_bsim/doc/nrf5340bsim.rst rename to boards/native/nrf_bsim/doc/nrf5340bsim.rst diff --git a/boards/posix/nrf_bsim/ipc_backend.c b/boards/native/nrf_bsim/ipc_backend.c similarity index 100% rename from boards/posix/nrf_bsim/ipc_backend.c rename to boards/native/nrf_bsim/ipc_backend.c diff --git a/boards/posix/nrf_bsim/irq_handler.c b/boards/native/nrf_bsim/irq_handler.c similarity index 100% rename from boards/posix/nrf_bsim/irq_handler.c rename to boards/native/nrf_bsim/irq_handler.c diff --git a/boards/posix/nrf_bsim/nrf52_bsim.dts b/boards/native/nrf_bsim/nrf52_bsim.dts similarity index 96% rename from boards/posix/nrf_bsim/nrf52_bsim.dts rename to boards/native/nrf_bsim/nrf52_bsim.dts index 8410c80fb74974..d591c7920c620a 100644 --- a/boards/posix/nrf_bsim/nrf52_bsim.dts +++ b/boards/native/nrf_bsim/nrf52_bsim.dts @@ -10,7 +10,7 @@ #include #include /* We resuse the pinctrl definitions directly from the real board : */ -#include <../boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833-pinctrl.dtsi> +#include <../boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi> / { model = "nrf52 bsim"; diff --git a/boards/posix/nrf_bsim/nrf52_bsim.yaml b/boards/native/nrf_bsim/nrf52_bsim.yaml similarity index 100% rename from boards/posix/nrf_bsim/nrf52_bsim.yaml rename to boards/native/nrf_bsim/nrf52_bsim.yaml diff --git a/boards/native/nrf_bsim/nrf52_bsim_defconfig b/boards/native/nrf_bsim/nrf52_bsim_defconfig new file mode 100644 index 00000000000000..0559b64671296e --- /dev/null +++ b/boards/native/nrf_bsim/nrf52_bsim_defconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_NO_OPTIMIZATIONS=y +CONFIG_LOG_BACKEND_UART=n diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts similarity index 97% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts index 72194f3b0e1b68..aa1f235e16e589 100644 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.dts @@ -115,4 +115,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ -#include <../boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi> +#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi> diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml similarity index 100% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp.yaml diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..83aba50dc572b4 --- /dev/null +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +CONFIG_CONSOLE=y +CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts similarity index 95% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts index 93e3ee271634e8..7553a2cfc55f11 100644 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.dts @@ -77,4 +77,4 @@ /* We re-use the IPC shared buffer definition from the real HW. But note the start address of the * buffer won't be used. */ -#include <../boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi> +#include <../boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi> diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml similarity index 100% rename from boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml rename to boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet.yaml diff --git a/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..83aba50dc572b4 --- /dev/null +++ b/boards/native/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +CONFIG_CONSOLE=y +CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/nsi_if.c b/boards/native/nrf_bsim/nsi_if.c similarity index 100% rename from boards/posix/nrf_bsim/nsi_if.c rename to boards/native/nrf_bsim/nsi_if.c diff --git a/boards/arm/nrf52840_mdk_usb_dongle/pre_dt_board.cmake b/boards/native/nrf_bsim/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_mdk_usb_dongle/pre_dt_board.cmake rename to boards/native/nrf_bsim/pre_dt_board.cmake diff --git a/boards/posix/nrf_bsim/soc/nrfx_coredep.c b/boards/native/nrf_bsim/soc/nrfx_coredep.c similarity index 100% rename from boards/posix/nrf_bsim/soc/nrfx_coredep.c rename to boards/native/nrf_bsim/soc/nrfx_coredep.c diff --git a/boards/native/nrf_bsim/soc/pinctrl_soc.h b/boards/native/nrf_bsim/soc/pinctrl_soc.h new file mode 100644 index 00000000000000..b5d9981a35e2e5 --- /dev/null +++ b/boards/native/nrf_bsim/soc/pinctrl_soc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H +#define BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H + +/* We reuse the real SOC's header: */ +#include "../soc/nordic/common/pinctrl_soc.h" + +#endif /* BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H */ diff --git a/boards/posix/nrf_bsim/soc/soc_nrf_common.h b/boards/native/nrf_bsim/soc/soc_nrf_common.h similarity index 83% rename from boards/posix/nrf_bsim/soc/soc_nrf_common.h rename to boards/native/nrf_bsim/soc/soc_nrf_common.h index a77778de6530b0..a835f2f2fc0092 100644 --- a/boards/posix/nrf_bsim/soc/soc_nrf_common.h +++ b/boards/native/nrf_bsim/soc/soc_nrf_common.h @@ -8,6 +8,6 @@ #define BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H /* We reuse the real SOC's header: */ -#include "../soc/arm/nordic_nrf/common/soc_nrf_common.h" +#include "../soc/nordic/common/soc_nrf_common.h" #endif /* BOARDS_POSIX_NRF_BSIM_SOC_SOC_NRF_COMMON_H */ diff --git a/boards/posix/nrf_bsim/soc/soc_secure.h b/boards/native/nrf_bsim/soc/soc_secure.h similarity index 87% rename from boards/posix/nrf_bsim/soc/soc_secure.h rename to boards/native/nrf_bsim/soc/soc_secure.h index 667823334d00ec..a39c02435a8d90 100644 --- a/boards/posix/nrf_bsim/soc/soc_secure.h +++ b/boards/native/nrf_bsim/soc/soc_secure.h @@ -5,7 +5,7 @@ */ /* - * Replacement for Nordic's nrf soc/arm/nordic_nrf/common/soc_secure.h + * Replacement for Nordic's nrf soc/nordic/common/soc_secure.h */ #ifndef BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H #define BOARDS_POSIX_NRF52_BSIM_SOC_SECURE_H diff --git a/boards/posix/nrf_bsim/time_machine.h b/boards/native/nrf_bsim/time_machine.h similarity index 100% rename from boards/posix/nrf_bsim/time_machine.h rename to boards/native/nrf_bsim/time_machine.h diff --git a/boards/nios2/altera_max10/Kconfig.board b/boards/nios2/altera_max10/Kconfig.board deleted file mode 100644 index 90f467915bdd9c..00000000000000 --- a/boards/nios2/altera_max10/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ALTERA_MAX10 - bool "Altera MAX10 Board" - depends on SOC_NIOS2F_ZEPHYR diff --git a/boards/nios2/altera_max10/Kconfig.defconfig b/boards/nios2/altera_max10/Kconfig.defconfig deleted file mode 100644 index a2ca4d47bf9cda..00000000000000 --- a/boards/nios2/altera_max10/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ALTERA_MAX10 - -config BOARD - default "altera_max10" - -if FLASH - -config SOC_FLASH_NIOS2_QSPI - default y - -if SOC_FLASH_NIOS2_QSPI - -if DISK_DRIVER_FLASH - -endif # DISK_DRIVER_FLASH - -endif # SOC_FLASH_NIOS2_QSPI - -endif # FLASH - -endif # BOARD_ALTERA_MAX10 diff --git a/boards/nios2/altera_max10/altera_max10_defconfig b/boards/nios2/altera_max10/altera_max10_defconfig deleted file mode 100644 index 925abcca34c487..00000000000000 --- a/boards/nios2/altera_max10/altera_max10_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NIOS2F_ZEPHYR=y -CONFIG_BOARD_ALTERA_MAX10=y -CONFIG_HAS_ALTERA_HAL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/nios2/altera_max10/doc/index.rst b/boards/nios2/altera_max10/doc/index.rst deleted file mode 100644 index db4daf5256ac5f..00000000000000 --- a/boards/nios2/altera_max10/doc/index.rst +++ /dev/null @@ -1,332 +0,0 @@ -.. _altera_max10: - -Altera MAX10 -############ - -Overview -******** - - -The Zephyr kernel is supported on the Altera MAX10 Rev C development kit, using -the Nios II Gen 2 soft CPU. - -.. figure:: img/altera_max10.jpg - :align: center - :alt: Altera's MAX* 10 - - Altera's MAX* 10 (Credit: Altera) - -Hardware -******** - -DIP Switch settings -=================== - -There are two sets of switches on the back of the board. Of particular -importance is SW2: - -* Switch 2 (CONFIG_SEL) should be in the OFF (up) position so that the first - boot image is CFM0 -* Switch 3 (VTAP_BYPASS) needs to be in the ON (down) position or the flashing - scripts won't work -* Switch 4 (HSMC_BYPASSN) should be OFF (up) - -.. image:: img/Altera_MAX10_switches.jpg - :align: center - :alt: Altera's MAX* 10 Switches - -Other switches are user switches, their position is application-specific. - -Necessary Software -================== - -You will need the Altera Quartus SDK in order to work with this device. The -`Altera Lite Distribution`_ of Quartus may be obtained without -charge. - -For your convenience using the SDK tools (such as ``nios2-configure-sof``), -you should put the binaries provided by the SDK -in your path. Below is an example, adjust ALTERA_BASE to where you installed the -SDK: - -.. code-block:: console - - export ALTERA_BASE=/opt/altera_lite/16.0 - export PATH=$PATH:$ALTERA_BASE/quartus/bin:$ALTERA_BASE/nios2eds/bin - -You may need to adjust your udev rules so that you can talk to the USB Blaster -II peripheral, which is the built-in JTAG interface for this device. - -The following works for Fedora 23: - -.. code-block:: console - - # For Altera USB-Blaster permissions. - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6010",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - SUBSYSTEM=="usb",\ - ENV{DEVTYPE}=="usb_device",\ - ATTR{idVendor}=="09fb",\ - ATTR{idProduct}=="6810",\ - MODE="0666",\ - NAME="bus/usb/$env{BUSNUM}/$env{DEVNUM}",\ - RUN+="/bin/chmod 0666 %c" - -You can test connectivity with the SDK jtagconfig tool, you should see something -like: - -.. code-block:: console - - $ jtagconfig - 1) USB-BlasterII [1-1.2] - 031050DD 10M50DA(.|ES)/10M50DC - 020D10DD VTAP10 - - -Reference CPU -============= - -A reference CPU design of a Nios II/f core is included in the Zephyr tree -in the :zephyr_file:`soc/nios2/nios2f-zephyr/cpu` directory. - -Flash this CPU using the ``nios2-configure-sof`` SDK tool with the FPGA -configuration file -:zephyr_file:`soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof`: - -.. code-block:: console - - $ nios2-configure-sof ghrd_10m50da.sof - -This CPU is a Nios II/F core with a 16550 UART, JTAG UART, and the Avalon Timer. -For any Nios II SOC definition, you can find out more details about the CPU -configuration by inspecting system.h in the SOC's include directory. - -Console Output -============== - -16550 UART ----------- - -By default, the kernel is configured to send console output to the 16550 UART. -You can monitor this on your workstation by connecting to the top right mini USB -port on the board (it will show up in /dev as a ttyUSB node), and then running -minicom with flow control disabled, 115200-8N1 settings. - -JTAG UART ---------- - -You can also have it send its console output to the JTAG UART. -Enable ``jtag_uart`` node in :file:`altera_max10.dts` or overlay file: - -.. code-block:: devicetree - - &jtag_uart { - status = "okay"; - current-speed = <115200>; - }; - -To view these messages on your local workstation, run the terminal application -in the SDK: - -.. code-block:: console - - $ nios2-terminal - -Programming and Debugging -************************* - -Flashing -======== - -Flashing Kernel into UFM ------------------------- - -The usual ``flash`` target will work with the ``altera_max10`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: flash - -Refer to :ref:`build_an_application` and :ref:`application_run` for -more details. - -This provisions the Zephyr kernel and the CPU configuration onto the board, -using the scripts/support/quartus-flash.py script. After it completes the kernel -will immediately boot. - - -Flashing Kernel directly into RAM over JTAG -------------------------------------------- - -The SDK included the nios2-download tool which will let you flash a kernel -directly into RAM and then boot it from the __start symbol. - -In order for this to work, your entire kernel must be located in RAM. Make sure -the following config options are disabled: - -.. code-block:: console - - CONFIG_XIP=n - CONFIG_INCLUDE_RESET_VECTOR=n - -Then, after building your kernel, push it into device's RAM by running -this from the build directory: - -.. code-block:: console - - $ nios2-download --go zephyr/zephyr.elf - -If you have a console session running (either minicom or nios2-terminal) you -should see the application's output. There are additional arguments you can pass -to nios2-download so that it spawns a GDB server that you can connect to, -although it's typically simpler to just use nios2-gdb-server as described below. - -Debugging -========= - -The Altera SDK includes a GDB server which can be used to debug a MAX10 board. -You can either debug a running image that was flashed onto the device in User -Flash Memory (UFM), or load an image over the JTAG using GDB. - -Debugging With UFM Flashed Image --------------------------------- - -You can debug an application in the usual way. Here is an example. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: altera_max10 - :goals: debug - -You will see output similar to the following: - -.. code-block:: console - - Nios II GDB server running on port 3335 - Ignoring --stop option because --tcpport also specified - GNU gdb (GDB) 7.11.0.20160511-git - Copyright (C) 2016 Free Software Foundation, Inc. - License GPLv3+: GNU GPL version 3 or later - This is free software: you are free to change and redistribute it. - There is NO WARRANTY, to the extent permitted by law. Type "show copying" - and "show warranty" for details. - This GDB was configured as "--host=x86_64-pokysdk-linux --target=nios2-zephyr-elf". - Type "show configuration" for configuration details. - For bug reporting instructions, please see: - . - Find the GDB manual and other documentation resources online at: - . - For help, type "help". - Type "apropos word" to search for commands related to "word"... - Reading symbols from /projects/zephyr/samples/hello_world/build/zephyr/zephyr.elf...done. - Remote debugging using :3335 - Using cable "USB-BlasterII [3-1.3]", device 1, instance 0x00 - Resetting and pausing target processor: OK - Listening on port 3335 for connection from GDB: accepted - isr_tables_syms () at /projects/zephyr/arch/common/isr_tables.c:63 - 63 GEN_ABSOLUTE_SYM(__ISR_LIST_SIZEOF, sizeof(struct _isr_list)); - (gdb) b z_prep_c - Breakpoint 1 at 0xdf0: file /projects/zephyr/arch/nios2/core/prep_c.c, line 36. - (gdb) b z_cstart - Breakpoint 2 at 0x1254: file /projects/zephyr/kernel/init.c, line 348. - (gdb) c - Continuing. - - Breakpoint 2, z_cstart () at /projects/zephyr/kernel/init.c:348 - 348 { - (gdb) - -To start debugging manually: - - -.. code-block:: console - - nios2-gdb-server --tcpport 1234 --stop --reset-target - -And then connect with GDB from the build directory: - - -.. code-block:: console - - nios2-poky-elf-gdb zephyr/zephyr.elf -ex "target remote :1234" - -Debugging With JTAG Flashed Image ---------------------------------- - -In order for this to work, execute-in-place must be disabled, since the GDB -'load' command can only put text and data in RAM. Ensure this is in your -configuration: - -.. code-block:: console - - CONFIG_XIP=n - -It is OK for this procedure to leave the reset vector enabled, unlike -nios2-download (which errors out if it finds sections outside of SRAM) it will -be ignored. - -In a terminal, launch the nios2 GDB server. It doesn't matter what kernel (if -any) is on the device, but you should have at least flashed a CPU using -nios2-configure-sof. You can leave this process running. - -.. code-block:: console - - $ nios2-gdb-server --tcpport 1234 --tcppersist --init-cache --reset-target - -Build your Zephyr kernel, and load it into a GDB built for Nios II (included in -the Zephyr SDK) from the build directory: - -.. code-block:: console - - $ nios2-poky-elf-gdb zephyr/zephyr.elf - -Then connect to the GDB server: - -.. code-block:: console - - (gdb) target remote :1234 - -And then load the kernel image over the wire. The CPU will not start from the -reset vector, instead it will boot from the __start symbol: - - -.. code-block:: console - - (gdb) load - Loading section reset, size 0xc lma 0x0 - Loading section exceptions, size 0x1b0 lma 0x400020 - Loading section text, size 0x8df0 lma 0x4001d0 - Loading section devconfig, size 0x30 lma 0x408fc0 - Loading section rodata, size 0x3f4 lma 0x408ff0 - Loading section datas, size 0x888 lma 0x4093e4 - Loading section initlevel, size 0x30 lma 0x409c6c - Loading section _k_task_list, size 0x58 lma 0x409c9c - Loading section _k_task_ptr, size 0x8 lma 0x409cf4 - Loading section _k_event_list, size 0x10 lma 0x409cfc - Start address 0x408f54, load size 40184 - Transfer rate: 417 KB/sec, 368 bytes/write. - After this is done you may set breakpoints and continue execution. If you ever want to reset the CPU, issue the 'load' command again. - - - -References -********** - -* `CPU Documentation `_ -* `Nios II Processor Booting Methods in MAX 10 FPGA Devices `_ -* `Embedded Peripherals IP User Guide `_ -* `MAX 10 FPGA Configuration User Guide `_ -* `MAX 10 FPGA Development Kit User Guide `_ -* `Nios II Command-Line Tools `_ -* `Quartus II Scripting Reference Manual `_ - - -.. _Altera Lite Distribution: https://www.intel.com/content/www/us/en/collections/products/fpga/software/downloads.html diff --git a/boards/nios2/index.rst b/boards/nios2/index.rst deleted file mode 100644 index 61c352619adb99..00000000000000 --- a/boards/nios2/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-nios2: - -Nios II Boards -############## - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/nios2/qemu_nios2/Kconfig.board b/boards/nios2/qemu_nios2/Kconfig.board deleted file mode 100644 index de59ab26b4abfe..00000000000000 --- a/boards/nios2/qemu_nios2/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_NIOS2 - bool "QEMU NIOS II target" - depends on SOC_NIOS2_QEMU - select QEMU_TARGET diff --git a/boards/nios2/qemu_nios2/Kconfig.defconfig b/boards/nios2/qemu_nios2/Kconfig.defconfig deleted file mode 100644 index b550e80e0f64ef..00000000000000 --- a/boards/nios2/qemu_nios2/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_NIOS2 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_nios2" - -endif diff --git a/boards/nios2/qemu_nios2/board.cmake b/boards/nios2/qemu_nios2/board.cmake deleted file mode 100644 index d4cd0427b36814..00000000000000 --- a/boards/nios2/qemu_nios2/board.cmake +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_CPU_TYPE_${ARCH} nios2) - -set(QEMU_FLAGS_${ARCH} - -machine altera_10m50_zephyr - -nographic - ) - -board_set_debugger_ifnset(qemu) diff --git a/boards/nordic/index.rst b/boards/nordic/index.rst new file mode 100644 index 00000000000000..69e38ab15ca40f --- /dev/null +++ b/boards/nordic/index.rst @@ -0,0 +1,10 @@ +.. _boards-nordic: + +Nordic Semiconductor +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/nordic/nrf21540dk/Kconfig b/boards/nordic/nrf21540dk/Kconfig new file mode 100644 index 00000000000000..522eb6e44dda70 --- /dev/null +++ b/boards/nordic/nrf21540dk/Kconfig @@ -0,0 +1,10 @@ +# nRF21540 DK NRF52840 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_NRF21540DK diff --git a/boards/nordic/nrf21540dk/Kconfig.defconfig b/boards/nordic/nrf21540dk/Kconfig.defconfig new file mode 100644 index 00000000000000..28a3f3e2c98d9d --- /dev/null +++ b/boards/nordic/nrf21540dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF21540 DK NRF52840 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF21540DK + +config BT_CTLR + default BT + +endif # BOARD_NRF21540DK diff --git a/boards/nordic/nrf21540dk/Kconfig.nrf21540dk b/boards/nordic/nrf21540dk/Kconfig.nrf21540dk new file mode 100644 index 00000000000000..858fc4605051c7 --- /dev/null +++ b/boards/nordic/nrf21540dk/Kconfig.nrf21540dk @@ -0,0 +1,7 @@ +# nRF21540 DK NRF52840 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF21540DK + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf21540dk_nrf52840/board.cmake b/boards/nordic/nrf21540dk/board.cmake similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/board.cmake rename to boards/nordic/nrf21540dk/board.cmake diff --git a/boards/nordic/nrf21540dk/board.yml b/boards/nordic/nrf21540dk/board.yml new file mode 100644 index 00000000000000..4c9cf5943fec38 --- /dev/null +++ b/boards/nordic/nrf21540dk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf21540dk + vendor: nordic + socs: + - name: nrf52840 diff --git a/boards/arm/nrf21540dk_nrf52840/doc/img/nrf21540dk_nrf52840.jpg b/boards/nordic/nrf21540dk/doc/img/nrf21540dk_nrf52840.jpg similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/doc/img/nrf21540dk_nrf52840.jpg rename to boards/nordic/nrf21540dk/doc/img/nrf21540dk_nrf52840.jpg diff --git a/boards/nordic/nrf21540dk/doc/index.rst b/boards/nordic/nrf21540dk/doc/index.rst new file mode 100644 index 00000000000000..fdc726056360dc --- /dev/null +++ b/boards/nordic/nrf21540dk/doc/index.rst @@ -0,0 +1,236 @@ +.. _nrf21540dk_nrf52840: + +nRF21540 DK +########### + +Overview +******** +The nRF21540 DK (PCA10112) shows possibility of the Nordic Semiconductor +nRF21540 Front End Module connected with nRF52840 ARM Cortex-M4F CPU. +The CPU provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf21540dk_nrf52840.jpg + :align: center + :alt: nRF21540 DK + + nRF21540 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the `nRF21540 website`_. +The `Nordic Semiconductor Infocenter`_ contains the processor's and front end +module's information and the datasheet. + +Hardware +******** + +The nRF52840 on the nRF21540 DK has two external oscillators. The frequency +of the slow clock is 32.768 kHz. The frequency of the main clock is 32 MHz. + +Supported Features +================== + +The nrf21540dk/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52840 Product Specification`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF21540 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (green) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +Front End Module +---------------- + +* MOSI = P1.13 +* MISO = P1.14 +* CLOCK = P1.15 +* CHIP SELECT = P0.21 +* PDN = P0.23 +* MODE = P0.17 +* RXEN = P0.19 +* ANTSEL = P0.20 +* TXEN = P0.22 + +Programming and Debugging +************************* + +Applications for the ``nrf21540dk/nrf52840`` board configuration can be built, +flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF21540 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf21540dk/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF21540 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts`. + +Changing UART1 pins +******************* + +The following approach can be used when an application needs to use another set +of pins for UART1: + +1. Add devicetree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep_alt: uart1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + pinctrl-0 = <&uart1_default_alt>; + /* if sleep state is not used, use /delete-property/ pinctrl-1; and + * skip the "sleep" entry. + */ + pinctrl-1 = <&uart1_sleep_alt>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +See :ref:`set-devicetree-overlays` for further details. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. +In the table 7.1.1 'aQFN73 ball assignments' select the pins marked +'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used +in under-10KHz applications. They are not suitable for 115200 speed of UART. + +References +********** + +.. target-notes:: + +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF21540 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF21540 +.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf +.. _nRF21540 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF21540_PS_v1.0.pdf diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts similarity index 100% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.dts rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840.dts diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.yaml b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml similarity index 90% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.yaml rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml index 985dba241e122b..a1bcc36e034d79 100644 --- a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840.yaml +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: nrf21540dk_nrf52840 +identifier: nrf21540dk/nrf52840 name: nRF21540-DK-NRF52840 type: mcu arch: arm diff --git a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840_defconfig b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig similarity index 76% rename from boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840_defconfig rename to boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig index fecb5052471863..8daa29dc47326f 100644 --- a/boards/arm/nrf21540dk_nrf52840/nrf21540dk_nrf52840_defconfig +++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF21540DK_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840_papyr/pre_dt_board.cmake b/boards/nordic/nrf21540dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840_papyr/pre_dt_board.cmake rename to boards/nordic/nrf21540dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf51dk/Kconfig.defconfig b/boards/nordic/nrf51dk/Kconfig.defconfig new file mode 100644 index 00000000000000..ae8e85130f3eb5 --- /dev/null +++ b/boards/nordic/nrf51dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 DK NRF51822 board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51DK_NRF51822 + +config BT_CTLR + default BT + +endif # BOARD_NRF51DK_NRF51822 diff --git a/boards/nordic/nrf51dk/Kconfig.nrf51dk b/boards/nordic/nrf51dk/Kconfig.nrf51dk new file mode 100644 index 00000000000000..51802271197c1d --- /dev/null +++ b/boards/nordic/nrf51dk/Kconfig.nrf51dk @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51DK + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dk_nrf51422/board.cmake b/boards/nordic/nrf51dk/board.cmake similarity index 100% rename from boards/arm/nrf51dk_nrf51422/board.cmake rename to boards/nordic/nrf51dk/board.cmake diff --git a/boards/nordic/nrf51dk/board.yml b/boards/nordic/nrf51dk/board.yml new file mode 100644 index 00000000000000..788be3d79bc857 --- /dev/null +++ b/boards/nordic/nrf51dk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51dk + vendor: nordic + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51dk_nrf51422/doc/img/nrf51dk_nrf51422.jpg b/boards/nordic/nrf51dk/doc/img/nrf51dk_nrf51822.jpg similarity index 100% rename from boards/arm/nrf51dk_nrf51422/doc/img/nrf51dk_nrf51422.jpg rename to boards/nordic/nrf51dk/doc/img/nrf51dk_nrf51822.jpg diff --git a/boards/nordic/nrf51dk/doc/index.rst b/boards/nordic/nrf51dk/doc/index.rst new file mode 100644 index 00000000000000..b97e70e9613195 --- /dev/null +++ b/boards/nordic/nrf51dk/doc/index.rst @@ -0,0 +1,159 @@ +.. _nrf51dk_nrf51422: + +nRF51 DK +######## + +Overview +******** + +The nRF51 Development Kit (PCA10028) hardware provides support for the Nordic +Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf51dk_nrf51822.jpg + :align: center + :alt: nRF51 DK + + nRF51 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF51 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF51 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 16 MHz. + +Supported Features +================== + +The nrf51dk/nrf51822 board configuration supports the following nRF51 +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF51 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF51 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.21 +* LED2 (green) = P0.22 +* LED3 (green) = P0.23 +* LED4 (green) = P0.24 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.17 +* BUTTON2 = SW2 = P0.18 +* BUTTON3 = SW3 = P0.19 +* BUTTON4 = SW4 = P0.20 +* BOOT = SW5 = boot/reset + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF51 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf51dk/nrf51822 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF51 DK +******************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf51dk/nrf51dk_nrf51822.dts`. + +References +********** + +.. target-notes:: + +.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422-pinctrl.dtsi b/boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51dk_nrf51422/nrf51dk_nrf51422-pinctrl.dtsi rename to boards/nordic/nrf51dk/nrf51dk_nrf51822-pinctrl.dtsi diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts new file mode 100644 index 00000000000000..15e74d15f40d0c --- /dev/null +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822.dts @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf51dk_nrf51822-pinctrl.dtsi" +#include + +/ { + model = "Nordic nRF51 DK NRF51822"; + compatible = "nordic,nrf51-dk-nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio0 18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio0 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 20 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 3"; + zephyr,code = ; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + bootloader-led0 = &led0; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + watchdog0 = &wdt0; + }; +}; + +&sw_pwm { + status ="okay"; + channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; + clock-prescaler = <8>; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&adc { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c1 { + /* Cannot be used together with spi1. */ + /* status = "okay"; */ + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi0 { + /* Cannot be used together with i2c0. */ + /* status = "okay"; */ + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi1 { + compatible = "nordic,nrf-spi"; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x8000>; + }; + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x1b000>; + }; + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x1b000>; + }; + storage_partition: partition@3e000 { + label = "storage"; + reg = <0x0003e000 0x00002000>; + }; + }; +}; diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml b/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml new file mode 100644 index 00000000000000..e3aab4cbf8545e --- /dev/null +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml @@ -0,0 +1,24 @@ +identifier: nrf51dk/nrf51822 +name: nRF51-DK-NRF51822 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 256 +supported: + - adc + - ble + - counter + - gpio + - i2c + - nvs + - pwm + - spi + - watchdog +testing: + ignore_tags: + - net +vendor: nordic diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822_defconfig b/boards/nordic/nrf51dk/nrf51dk_nrf51822_defconfig new file mode 100644 index 00000000000000..1289685e1e806e --- /dev/null +++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_ble400/pre_dt_board.cmake b/boards/nordic/nrf51dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51_ble400/pre_dt_board.cmake rename to boards/nordic/nrf51dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf51dongle/Kconfig.defconfig b/boards/nordic/nrf51dongle/Kconfig.defconfig new file mode 100644 index 00000000000000..fed53a7a316f7c --- /dev/null +++ b/boards/nordic/nrf51dongle/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 Dongle NRF51822 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51DONGLE + +config BT_CTLR + default BT + +endif # BOARD_NRF51DONGLE diff --git a/boards/nordic/nrf51dongle/Kconfig.nrf51dongle b/boards/nordic/nrf51dongle/Kconfig.nrf51dongle new file mode 100644 index 00000000000000..a13b3e208beba9 --- /dev/null +++ b/boards/nordic/nrf51dongle/Kconfig.nrf51dongle @@ -0,0 +1,7 @@ +# nRF51 Dongle NRF51822 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51DONGLE + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51dongle_nrf51422/board.cmake b/boards/nordic/nrf51dongle/board.cmake similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/board.cmake rename to boards/nordic/nrf51dongle/board.cmake diff --git a/boards/nordic/nrf51dongle/board.yml b/boards/nordic/nrf51dongle/board.yml new file mode 100644 index 00000000000000..4c89cac7fdcc2e --- /dev/null +++ b/boards/nordic/nrf51dongle/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51dongle + vendor: nordic + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51dongle_nrf51422/doc/img/nrf51dongle_nrf51422.jpg b/boards/nordic/nrf51dongle/doc/img/nrf51dongle_nrf51822.jpg similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/doc/img/nrf51dongle_nrf51422.jpg rename to boards/nordic/nrf51dongle/doc/img/nrf51dongle_nrf51822.jpg diff --git a/boards/nordic/nrf51dongle/doc/index.rst b/boards/nordic/nrf51dongle/doc/index.rst new file mode 100644 index 00000000000000..720ff3a59861d9 --- /dev/null +++ b/boards/nordic/nrf51dongle/doc/index.rst @@ -0,0 +1,144 @@ +.. _nrf51dongle_nrf51422: + +nRF51 Dongle +############ + +Overview +******** + +The nRF51 Dongle (PCA10031) hardware provides support for the Nordic +Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf51dongle_nrf51822.jpg + :align: center + :alt: nRF51 Dongle + + nRF51 Dongle (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF51 Dongle website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF51 Dongle has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 16 MHz. + +Supported Features +================== + +The nrf51dongle/nrf51822 board configuration supports the following nRF51 +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF51 Dongle website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF51 Dongle hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.21 +* LED1 (green) = P0.22 +* LED1 (blue) = P0.23 + +Push buttons +------------ + +* BOOT = SW1 = boot/reset + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF51 Dongle +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf51dongle/nrf51822 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Testing the LEDs on the nRF51 Dongle +************************************ + +Build and flash the :zephyr:code-sample:`blinky` sample to test that the onboard LED +is working properly with Zephyr. + +References +********** + +.. target-notes:: + +.. _nRF51 Dongle website: http://www.nordicsemi.com/eng/Products/nRF51-Dongle +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/nrf51_blenano/nrf51_blenano-pinctrl.dtsi b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51_blenano/nrf51_blenano-pinctrl.dtsi rename to boards/nordic/nrf51dongle/nrf51dongle_nrf51822-pinctrl.dtsi diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts new file mode 100644 index 00000000000000..746b2ca767cbdf --- /dev/null +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.dts @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2018 Nordic Semiconductor ASA. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "nrf51dongle_nrf51822-pinctrl.dtsi" + +/ { + model = "Nordic nRF51 Dongle NRF51822"; + compatible = "nordic,nrf51-dongle-nrf51822"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led0_red: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "Red LED 0"; + }; + led0_green: led_1 { + gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + led0_blue: led_2 { + gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; + label = "Blue LED 0"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&sw_pwm 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0_red; + led1 = &led0_green; + led2 = &led0_blue; + pwm-led0 = &pwm_led0; + watchdog0 = &wdt0; + }; +}; + +&sw_pwm { + status ="okay"; + channel-gpios = <&gpio0 21 PWM_POLARITY_INVERTED>; + clock-prescaler = <8>; +}; + +&gpiote { + status ="okay"; +}; + +&gpio0 { + status ="okay"; +}; + +&adc { + status ="okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x8000>; + }; + slot0_partition: partition@8000 { + label = "image-0"; + reg = <0x00008000 0x1b000>; + }; + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x1b000>; + }; + storage_partition: partition@3e000 { + label = "storage"; + reg = <0x0003e000 0x00002000>; + }; + }; +}; diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml new file mode 100644 index 00000000000000..8622e018ba3285 --- /dev/null +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml @@ -0,0 +1,14 @@ +identifier: nrf51dongle/nrf51822 +name: nRF51-Dongle-nRF51822 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32 +flash: 256 +supported: + - ble + - nvs +vendor: nordic diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822_defconfig b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822_defconfig new file mode 100644 index 00000000000000..1289685e1e806e --- /dev/null +++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_blenano/pre_dt_board.cmake b/boards/nordic/nrf51dongle/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51_blenano/pre_dt_board.cmake rename to boards/nordic/nrf51dongle/pre_dt_board.cmake diff --git a/boards/nordic/nrf52833dk/CMakeLists.txt b/boards/nordic/nrf52833dk/CMakeLists.txt new file mode 100644 index 00000000000000..f7df5c94a3b3a5 --- /dev/null +++ b/boards/nordic/nrf52833dk/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF52833DK_NRF52820) + # The nrf52833dk_nrf52820 board mirrors the nRF52833 DK hardware. This + # needs to be considered by certain system initialization functionality + # residing in system_nrf52820.c and SoC dependent routines in nrfx_coredep.h. + zephyr_compile_definitions(DEVELOP_IN_NRF52833) + zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) +endif() diff --git a/boards/nordic/nrf52833dk/Kconfig b/boards/nordic/nrf52833dk/Kconfig new file mode 100644 index 00000000000000..8b53d5bd73f047 --- /dev/null +++ b/boards/nordic/nrf52833dk/Kconfig @@ -0,0 +1,10 @@ +# nRF52833 DK NRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_NRF52833DK diff --git a/boards/nordic/nrf52833dk/Kconfig.defconfig b/boards/nordic/nrf52833dk/Kconfig.defconfig new file mode 100644 index 00000000000000..30c49fa7fb7cda --- /dev/null +++ b/boards/nordic/nrf52833dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52833 DK NRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52833DK + +config BT_CTLR + default BT + +endif # BOARD_NRF52833DK diff --git a/boards/nordic/nrf52833dk/Kconfig.nrf52833dk b/boards/nordic/nrf52833dk/Kconfig.nrf52833dk new file mode 100644 index 00000000000000..1705a59edec071 --- /dev/null +++ b/boards/nordic/nrf52833dk/Kconfig.nrf52833dk @@ -0,0 +1,8 @@ +# nRF52833 DK NRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52833DK + select SOC_NRF52820_QDAA if BOARD_NRF52833DK_NRF52820 + select SOC_NRF52833_QIAA if BOARD_NRF52833DK_NRF52833 diff --git a/boards/arm/nrf52833dk_nrf52833/board.cmake b/boards/nordic/nrf52833dk/board.cmake similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/board.cmake rename to boards/nordic/nrf52833dk/board.cmake diff --git a/boards/nordic/nrf52833dk/board.yml b/boards/nordic/nrf52833dk/board.yml new file mode 100644 index 00000000000000..2d6b6e5b12f210 --- /dev/null +++ b/boards/nordic/nrf52833dk/board.yml @@ -0,0 +1,6 @@ +board: + name: nrf52833dk + vendor: nordic + socs: + - name: nrf52820 + - name: nrf52833 diff --git a/boards/nordic/nrf52833dk/doc/index.rst b/boards/nordic/nrf52833dk/doc/index.rst new file mode 100644 index 00000000000000..d182053d506475 --- /dev/null +++ b/boards/nordic/nrf52833dk/doc/index.rst @@ -0,0 +1,241 @@ +.. _nrf52833dk_nrf52833: + +nRF52833 DK +########### + +Overview +******** + +The nRF52833 Development Kit (PCA10100) hardware provides +support for the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +More information about the board can be found at the +`nRF52833 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF52833 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf52833dk/nrf52833`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52833 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52833 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (green) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +Programming and Debugging +************************* + +Applications for the ``nrf52833dk/nrf52833`` board configuration can be built, +flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52833dk/nrf52833 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF52833 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts`. + +Changing UART1 pins +******************* + +The following approach can be used when an application needs to use another set +of pins for UART1: + +1. Add devicetree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep_alt: uart1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + pinctrl-0 = <&uart1_default_alt>; + /* if sleep state is not used, use /delete-property/ pinctrl-1; and + * skip the "sleep" entry. + */ + pinctrl-1 = <&uart1_sleep_alt>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +See :ref:`set-devicetree-overlays` for further details. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `nRF52833 Product Specification`_, chapter 7 'Hardware and Layout'. +In the table 7.1.1 'aQFN73 ball assignments' select the pins marked +'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used +in under-10KHz applications. They are not suitable for 115200 speed of UART. + +References +********** + +.. target-notes:: + +.. _nRF52833 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF52833 Product Specification: https://infocenter.nordicsemi.com/pdf/nRF52833_OPS_v0.7.pdf + +.. _nrf52833dk_nrf52820: + +nRF52820 emulation on nRF52833 DK +################################# + +Overview +******** + +The ``nrf52833dk/nrf52820`` board is a modified version of the +:ref:`nrf52833dk_nrf52833` that enforces the limitations imposed by the nRF52820 +IC, which is a variant of the original nRF52833. Since Nordic does not offer a +development kit for the nRF52820 you can use this board to develop for this IC +while using the nRF52833 Development Kit (PCA10100). + +See :ref:`nrf52833dk_nrf52833` for more information about the development board +and `nRF52820 website`_ for the official reference on the IC itself. + +References +********** + +.. target-notes:: + +.. _nRF52820 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52820 diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820-pinctrl.dtsi rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820-pinctrl.dtsi diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts similarity index 100% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.dts rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820.dts diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.yaml b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml similarity index 87% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.yaml rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml index 1e31da83439540..b2d59ed4e4157c 100644 --- a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820.yaml +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml @@ -1,4 +1,4 @@ -identifier: nrf52833dk_nrf52820 +identifier: nrf52833dk/nrf52820 name: nRF52833-DK-NRF52820 type: mcu arch: arm diff --git a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig similarity index 76% rename from boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820_defconfig rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig index f953cca65f1c21..8daa29dc47326f 100644 --- a/boards/arm/nrf52833dk_nrf52820/nrf52833dk_nrf52820_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52820_QDAA=y -CONFIG_BOARD_NRF52833DK_NRF52820=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833-pinctrl.dtsi b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833-pinctrl.dtsi rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833-pinctrl.dtsi diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts similarity index 100% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.dts rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833.dts diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.yaml b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml similarity index 89% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.yaml rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml index 24cacd6ffa39d9..cd3ed1b54d2349 100644 --- a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833.yaml +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml @@ -1,4 +1,4 @@ -identifier: nrf52833dk_nrf52833 +identifier: nrf52833dk/nrf52833 name: nRF52833-DK-NRF52833 type: mcu arch: arm diff --git a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833_defconfig b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig similarity index 76% rename from boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833_defconfig rename to boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig index d4d96e6e395535..8daa29dc47326f 100644 --- a/boards/arm/nrf52833dk_nrf52833/nrf52833dk_nrf52833_defconfig +++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_NRF52833DK_NRF52833=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dk_nrf52811/pre_dt_board.cmake b/boards/nordic/nrf52833dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840dk_nrf52811/pre_dt_board.cmake rename to boards/nordic/nrf52833dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf52840dk/CMakeLists.txt b/boards/nordic/nrf52840dk/CMakeLists.txt new file mode 100644 index 00000000000000..3f75c04696cef5 --- /dev/null +++ b/boards/nordic/nrf52840dk/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +# The nrf52840dk_nrf52811 board mirrors the nRF52840 DK hardware. This +# needs to be considered by certain system initialization functionality +# residing in system_nrf52811.c and SoC dependent routines in nrfx_coredep.h. +if(CONFIG_BOARD_NRF52840DK_NRF52811) + zephyr_compile_definitions(DEVELOP_IN_NRF52840) + zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) +endif() diff --git a/boards/nordic/nrf52840dk/Kconfig b/boards/nordic/nrf52840dk/Kconfig new file mode 100644 index 00000000000000..61d553e93c51ec --- /dev/null +++ b/boards/nordic/nrf52840dk/Kconfig @@ -0,0 +1,19 @@ +# nRF52840 DK NRF52840 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DK + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + depends on SOC_NRF52840_QIAA + +endif # BOARD_NRF52840DK diff --git a/boards/nordic/nrf52840dk/Kconfig.defconfig b/boards/nordic/nrf52840dk/Kconfig.defconfig new file mode 100644 index 00000000000000..7e932d27f7afa4 --- /dev/null +++ b/boards/nordic/nrf52840dk/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52840 DK NRF52840 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DK + +config BT_CTLR + default BT + +endif # BOARD_NRF52840DK diff --git a/boards/nordic/nrf52840dk/Kconfig.nrf52840dk b/boards/nordic/nrf52840dk/Kconfig.nrf52840dk new file mode 100644 index 00000000000000..63dc7a84ae8baa --- /dev/null +++ b/boards/nordic/nrf52840dk/Kconfig.nrf52840dk @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Zephyr Project members and individual contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840DK + select SOC_NRF52840_QIAA if BOARD_NRF52840DK_NRF52840 + select SOC_NRF52811_QFAA if BOARD_NRF52840DK_NRF52811 diff --git a/boards/arm/nrf52840dk_nrf52840/board.cmake b/boards/nordic/nrf52840dk/board.cmake similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/board.cmake rename to boards/nordic/nrf52840dk/board.cmake diff --git a/boards/nordic/nrf52840dk/board.yml b/boards/nordic/nrf52840dk/board.yml new file mode 100644 index 00000000000000..d15e1975027aeb --- /dev/null +++ b/boards/nordic/nrf52840dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf52840dk + vendor: nordic + socs: + # Physical nRF52840 SoC on PCA10056 + - name: nrf52840 + # nRF52840 SoC in nRF52811 emulation mode on PCA10056 + - name: nrf52811 diff --git a/boards/arm/nrf52840dk_nrf52840/doc/img/nrf52840dk_nrf52840.jpg b/boards/nordic/nrf52840dk/doc/img/nrf52840dk_nrf52840.jpg similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/doc/img/nrf52840dk_nrf52840.jpg rename to boards/nordic/nrf52840dk/doc/img/nrf52840dk_nrf52840.jpg diff --git a/boards/nordic/nrf52840dk/doc/index.rst b/boards/nordic/nrf52840dk/doc/index.rst new file mode 100644 index 00000000000000..953c86fd19022b --- /dev/null +++ b/boards/nordic/nrf52840dk/doc/index.rst @@ -0,0 +1,250 @@ +.. _nrf52840dk_nrf52840: + +nRF52840 DK +########### + +Overview +******** + +The nRF52840 Development Kit (PCA10056) hardware provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52840dk_nrf52840.jpg + :align: center + :alt: nRF52840 DK + + nRF52840 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the `nRF52840 DK website`_. +The `Nordic Semiconductor Infocenter`_ contains the processor's information +and the datasheet. + + +Hardware +******** + +nRF52840 DK has two external oscillators. The frequency of the slow clock +is 32.768 kHz. The frequency of the main clock is 32 MHz. + +Supported Features +================== + +The ``nrf52840dk/nrf52840`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52840 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52840 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (green) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +Programming and Debugging +************************* + +Applications for the ``nrf52840dk/nrf52840`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52840 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52840dk/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF52840 DK +*********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts`. + +Changing UART1 pins +******************* + +The following approach can be used when an application needs to use another set +of pins for UART1: + +1. Add devicetree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default_alt: uart1_default_alt { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep_alt: uart1_sleep_alt { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + pinctrl-0 = <&uart1_default_alt>; + /* if sleep state is not used, use /delete-property/ pinctrl-1; and + * skip the "sleep" entry. + */ + pinctrl-1 = <&uart1_sleep_alt>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +See :ref:`set-devicetree-overlays` for further details. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `nRF52840 Product Specification`_, chapter 7 'Hardware and Layout'. +In the table 7.1.1 'aQFN73 ball assignments' select the pins marked +'General purpose I/O'. Note that pins marked as 'low frequency I/O only' can only be used +in under-10KHz applications. They are not suitable for 115200 speed of UART. + +.. _nrf52840dk_nrf52811: + +nRF52811 emulation on nRF52840 DK +################################# + +Overview +******** + +The ``nrf52840dk/nrf52811`` board variant is a modified version of the +:ref:`nrf52840dk_nrf52840` that enforces the limitations imposed by the nRF52811 +IC, which is a variant of the original nRF52840. Since Nordic does not offer a +development kit for the nRF52811 you can use this board to develop for this IC +while using the nRF52840 Development Kit (PCA10056). + +See :ref:`nrf52840dk_nrf52840` for more information about the development board +and `nRF52811 website`_ for the official reference on the IC itself. + + +References +********** + +.. target-notes:: + +.. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811 + +References +********** + +.. target-notes:: + +.. _nRF52840 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf +.. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811 diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811-pinctrl.dtsi rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811-pinctrl.dtsi diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts similarity index 100% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.dts rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811.dts diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.yaml b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml similarity index 85% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.yaml rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml index 40d927db11671f..4c06984e3de389 100644 --- a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811.yaml +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml @@ -1,4 +1,4 @@ -identifier: nrf52840dk_nrf52811 +identifier: nrf52840dk/nrf52811 name: nRF52840-DK-NRF52811 type: mcu arch: arm diff --git a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811_defconfig b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811_defconfig similarity index 84% rename from boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811_defconfig rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52811_defconfig index 97eaa9232e5c55..c076e7d889754a 100644 --- a/boards/arm/nrf52840dk_nrf52811/nrf52840dk_nrf52811_defconfig +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811_defconfig @@ -2,10 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52811_QFAA=y -CONFIG_BOARD_NRF52840DK_NRF52811=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.dts rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml similarity index 91% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml index 00ee8701a977f1..30a96d563c9477 100644 --- a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840.yaml +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: nrf52840dk_nrf52840 +identifier: nrf52840dk/nrf52840 name: nRF52840-DK-NRF52840 type: mcu arch: arm diff --git a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840_defconfig b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig similarity index 76% rename from boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840_defconfig rename to boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig index 107f9e00d599c4..8daa29dc47326f 100644 --- a/boards/arm/nrf52840dk_nrf52840/nrf52840dk_nrf52840_defconfig +++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840DK_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dk_nrf52840/pre_dt_board.cmake b/boards/nordic/nrf52840dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840dk_nrf52840/pre_dt_board.cmake rename to boards/nordic/nrf52840dk/pre_dt_board.cmake diff --git a/boards/arm/nrf9160dk_nrf52840/CMakeLists.txt b/boards/nordic/nrf52840dongle/CMakeLists.txt similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/CMakeLists.txt rename to boards/nordic/nrf52840dongle/CMakeLists.txt diff --git a/boards/nordic/nrf52840dongle/Kconfig b/boards/nordic/nrf52840dongle/Kconfig new file mode 100644 index 00000000000000..c4e9b3097623a8 --- /dev/null +++ b/boards/nordic/nrf52840dongle/Kconfig @@ -0,0 +1,29 @@ +# nRF52840 Dongle NRF52840 board configuration + +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DONGLE + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + +config BOARD_HAS_NRF5_BOOTLOADER + bool "Board has nRF5 bootloader" + default y + help + If selected, applications are linked so that they can be loaded by Nordic + nRF5 bootloader. + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "USB CDC" + default y + +endif # BOARD_NRF52840DONGLE diff --git a/boards/nordic/nrf52840dongle/Kconfig.defconfig b/boards/nordic/nrf52840dongle/Kconfig.defconfig new file mode 100644 index 00000000000000..1288e33bcdb5d9 --- /dev/null +++ b/boards/nordic/nrf52840dongle/Kconfig.defconfig @@ -0,0 +1,83 @@ +# nRF52840 Dongle NRF52840 board configuration +# +# Copyright (c) 2018-2023 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52840DONGLE + +# To let the nRF5 bootloader load an application, the application +# must be linked after Nordic MBR, that is factory-programmed on the board. + +# Nordic nRF5 bootloader exists outside of the partitions specified in the +# DTS file, so we manually override FLASH_LOAD_OFFSET to link the application +# correctly, after Nordic MBR. + +# When building MCUBoot, MCUBoot itself will select USE_DT_CODE_PARTITION +# which will make it link into the correct partition specified in DTS file, +# the offset is applied here so that the full partition size can be used when +# the bootloader Kconfig option has been disabled. + +config FLASH_LOAD_OFFSET + default 0x1000 + depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION) + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default SERIAL + +config CONSOLE + default y + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT && CONSOLE + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +# Set USB log level to error only +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_ERR +endchoice + +# Wait 4000ms at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 4000 + +endif # LOG + +if USB_DEVICE_STACK + +# Enable UART driver, needed for CDC ACM +config SERIAL + default y + +endif # USB_DEVICE_STACK + +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +config BT_CTLR + default BT + +endif # BOARD_NRF52840DONGLE diff --git a/boards/nordic/nrf52840dongle/Kconfig.nrf52840dongle b/boards/nordic/nrf52840dongle/Kconfig.nrf52840dongle new file mode 100644 index 00000000000000..cd58d54c6888ca --- /dev/null +++ b/boards/nordic/nrf52840dongle/Kconfig.nrf52840dongle @@ -0,0 +1,7 @@ +# nRF52840 Dongle NRF52840 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52840DONGLE + select SOC_NRF52840_QIAA diff --git a/boards/arm/nrf52840dongle_nrf52840/board.c b/boards/nordic/nrf52840dongle/board.c similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/board.c rename to boards/nordic/nrf52840dongle/board.c diff --git a/boards/arm/nrf52840dongle_nrf52840/board.cmake b/boards/nordic/nrf52840dongle/board.cmake similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/board.cmake rename to boards/nordic/nrf52840dongle/board.cmake diff --git a/boards/nordic/nrf52840dongle/board.yml b/boards/nordic/nrf52840dongle/board.yml new file mode 100644 index 00000000000000..a22449e5519245 --- /dev/null +++ b/boards/nordic/nrf52840dongle/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52840dongle + vendor: nordic + socs: + - name: nrf52840 diff --git a/boards/arm/nrf52840dongle_nrf52840/doc/img/nRF52840_dongle_press_reset.svg b/boards/nordic/nrf52840dongle/doc/img/nRF52840_dongle_press_reset.svg similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/doc/img/nRF52840_dongle_press_reset.svg rename to boards/nordic/nrf52840dongle/doc/img/nRF52840_dongle_press_reset.svg diff --git a/boards/arm/nrf52840dongle_nrf52840/doc/img/nrf52840dongle_nrf52840.jpg b/boards/nordic/nrf52840dongle/doc/img/nrf52840dongle_nrf52840.jpg similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/doc/img/nrf52840dongle_nrf52840.jpg rename to boards/nordic/nrf52840dongle/doc/img/nrf52840dongle_nrf52840.jpg diff --git a/boards/nordic/nrf52840dongle/doc/index.rst b/boards/nordic/nrf52840dongle/doc/index.rst new file mode 100644 index 00000000000000..235b0ea4b35b4f --- /dev/null +++ b/boards/nordic/nrf52840dongle/doc/index.rst @@ -0,0 +1,348 @@ +.. _nrf52840dongle_nrf52840: + +nRF52840 Dongle +############### + +Overview +******** + +The nRF52840 Dongle (PCA10059) hardware provides support for the Nordic +Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52840dongle_nrf52840.jpg + :align: center + :alt: nRF52840 Dongle + + nRF52840 Dongle + +More information about the board can be found at the +`nRF52840 Dongle website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +The ``nrf52840dongle/nrf52840`` has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf52840dongle/nrf52840`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52840 Dongle website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52840 Dongle board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (green) = P0.6 +* LED1 (red) = P0.8 +* LED1 (green) = P1.9 +* LED1 (blue) = P0.12 + +Push buttons +------------ + +* BUTTON1 = SW1 = P1.6 +* RESET = SW2 = P0.18 + +Programming and Debugging +************************* + +Applications for the ``nrf52840dongle/nrf52840`` board configuration can be +built in the usual way (see :ref:`build_an_application` for more details). + +Flashing +======== + +The board supports the following programming options: + +1. Using the built-in bootloader only +2. Using MCUboot in serial recovery mode +3. Using an external :ref:`debug probe ` + +These instructions use the :ref:`west ` tool and assume you are in the +root directory of your :term:`west installation`. + +Option 1: Using the Built-In Bootloader Only +-------------------------------------------- + +The board is factory-programmed with Nordic's bootloader from Nordic's nRF5 +SDK. With this option, you'll use Nordic's `nrfutil`_ program to create +firmware packages supported by this bootloader and flash them to the +device. Make sure ``nrfutil`` is installed before proceeding. + +#. Reset the board into the Nordic bootloader by pressing the RESET button. + + The push button is on the far side of the board from the USB connector. Note + that the button does not face up. You will have to push it from the outside + in, towards the USB connector: + + .. image:: img/nRF52840_dongle_press_reset.svg + :alt: Location of RESET button and direction of push + + The red LED should start a fade pattern, signalling the bootloader is + running. + +#. Compile a Zephyr application; we'll use :zephyr:code-sample:`blinky`. + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: nrf52840dongle/nrf52840 + :goals: build + +#. Package the application for the bootloader using ``nrfutil``: + + .. code-block:: console + + nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ + --application build/zephyr/zephyr.hex \ + --application-version 1 blinky.zip + +#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be + something like ``COMx`` on Windows, and something else on macOS. + + .. code-block:: console + + nrfutil dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0 + + When this command exits, observe the green LED on the board blinking, + instead of the red LED used by the bootloader. + +For more information, see `Nordic Semiconductor USB DFU`_. + +Option 2: Using MCUboot in Serial Recovery Mode +----------------------------------------------- + +It is also possible to use the MCUboot bootloader with this board to flash +Zephyr applications. You need to do some one-time set-up to build and flash +MCUboot on your board. From that point on, you can build and flash other Zephyr +applications using MCUboot's serial recovery mode. This process does not +overwrite the built-in Nordic bootloader, so you can always go back to using +Option 1 later. + +Install `nrfutil`_ and `mcumgr`_ first, and make sure MCUboot's ``imgtool`` is +available for signing your binary for MCUboot as described on :ref:`west-sign`. + +Next, do the **one-time setup** to flash MCUboot. We'll assume you've cloned +the `MCUboot`_ repository into the directory ``mcuboot``, and that it is next +to the zephyr repository on your computer. + +#. Reset the board into the Nordic bootloader as described above. + +#. Compile MCUboot as a Zephyr application. + + .. zephyr-app-commands:: + :app: mcuboot/boot/zephyr + :board: nrf52840dongle/nrf52840 + :build-dir: mcuboot + :goals: build + +#. Package the application for the bootloader using ``nrfutil``: + + .. code-block:: console + + nrfutil pkg generate --hw-version 52 --sd-req=0x00 \ + --application build/mcuboot/zephyr/zephyr.hex \ + --application-version 1 mcuboot.zip + +#. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be + something like ``COMx`` on Windows, and something else on macOS. + + .. code-block:: console + + nrfutil dfu usb-serial -pkg mcuboot.zip -p /dev/ttyACM0 + +You can now flash a Zephyr application to the board using MCUboot's serial +recovery mode. We'll use the :zephyr:code-sample:`smp-svr` sample since it's ready to be +compiled for chain-loading by MCUboot (and itself supports firmware updates +over Bluetooth). + +#. Boot into MCUboot serial recovery mode by plugging the board in with the SW1 + button pressed down. See above for a picture showing where SW1 is. + + **Do not press RESET**; that will run the Nordic bootloader, which is + different than MCUboot. + + A serial port will enumerate on your board. On Windows, "MCUBOOT" should + appear under "Other Devices" in the Device Manager (in addition to the usual + ``COMx`` device). On Linux, something like + :file:`/dev/serial/by-id/usb-ZEPHYR_MCUBOOT_0.01-if00` should be created. + + If no serial port appears, try plugging it in again, making sure SW1 is + pressed. If it still doesn't appear, retry the one-time MCUboot setup. + +#. Compile ``smp_svr``. + + .. zephyr-app-commands:: + :app: zephyr/samples/subsys/mgmt/mcumgr/smp_svr + :board: nrf52840dongle/nrf52840 + :build-dir: smp_svr + :goals: build + +#. Sign ``smp_svr`` for chain-loading by MCUboot. + + .. code-block:: console + + west sign -t imgtool --bin --no-hex -d build/smp_svr \ + -B smp_svr.signed.bin -- --key mcuboot/root-rsa-2048.pem + +#. Flash the application to the MCUboot serial port using ``mcumgr``: + + .. code-block:: console + + mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' \ + image upload -e smp_svr.signed.bin + +#. Reset the device: + + .. code-block:: console + + mcumgr --conntype=serial --connstring='dev=/dev/ttyACM0,baud=115200' reset + +You should now be able to scan for Bluetooth devices using a smartphone or +computer. The device you just flashed will be listed with ``Zephyr`` in its +name. + +.. note:: + + This board supports building other Zephyr applications for flashing with + MCUboot in this way also. Just make sure :kconfig:option:`CONFIG_BOOTLOADER_MCUBOOT` + is set when building your application. For example, to compile blinky for + loading by MCUboot, use this: + + .. zephyr-app-commands:: + :app: zephyr/samples/basic/blinky + :board: nrf52840dongle/nrf52840 + :build-dir: blinky + :goals: build + :gen-args: -DCONFIG_BOOTLOADER_MCUBOOT=y + + You can then sign and flash it using the steps above. + +Option 3: Using an External Debug Probe +--------------------------------------- + +If you have one, you can also use an external :ref:`debug probe ` +to flash and debug Zephyr applications, but you need to solder an SWD header +onto the back side of the board. + +For Segger J-Link debug probes, follow the instructions in the +:ref:`nordic_segger` page to install and configure all the necessary +software. Further information can be found in :ref:`nordic_segger_flashing`. + +Locate the DTS file: :zephyr_file:`boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts`. +This file requires a small modification to use a different partition table. +Edit the include directive to include "fstab-debugger" instead of "fstab-stock". + +In addition, the Kconfig file in the same directory must be modified by setting +``BOARD_HAS_NRF5_BOOTLOADER`` to be default ``n``, otherwise the code will be +flashed with an offset. + +Then build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nrf52840dongle/nrf52840 + :goals: build flash + +Observe the LED on the board blinking. + +Debugging +========= + +The ``nrf52840dongle/nrf52840`` board does not have an on-board J-Link debug IC +as some nRF5x development boards, however, instructions from the +:ref:`nordic_segger` page also apply to this board, with the additional step +of connecting an external debugger. + +Testing the LEDs and buttons on the nRF52840 Dongle +*************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` + +You can build and program the examples to make sure Zephyr is running correctly +on your board. + + +References +********** + +.. target-notes:: + +.. _nRF52840 Dongle website: + https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle +.. _Nordic Semiconductor Infocenter: + https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html +.. _Nordic Semiconductor USB DFU: + https://infocenter.nordicsemi.com/index.jsp?topic=%2Fcom.nordic.infocenter.sdk5.v15.2.0%2Fsdk_app_serial_dfu_bootloader.html +.. _nrfutil: + https://github.com/NordicSemiconductor/pc-nrfutil +.. _MCUboot: + https://github.com/JuulLabs-OSS/mcuboot +.. _mcumgr: + https://github.com/apache/mynewt-mcumgr-cli diff --git a/boards/arm/nrf52840dongle_nrf52840/fstab-debugger.dtsi b/boards/nordic/nrf52840dongle/fstab-debugger.dtsi similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/fstab-debugger.dtsi rename to boards/nordic/nrf52840dongle/fstab-debugger.dtsi diff --git a/boards/arm/nrf52840dongle_nrf52840/fstab-stock.dtsi b/boards/nordic/nrf52840dongle/fstab-stock.dtsi similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/fstab-stock.dtsi rename to boards/nordic/nrf52840dongle/fstab-stock.dtsi diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840-pinctrl.dtsi b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.dts rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.dts diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.yaml b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml similarity index 87% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.yaml rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml index f0fb4cdafbff5e..1e61b0e71e478e 100644 --- a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840.yaml +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: nrf52840dongle_nrf52840 +identifier: nrf52840dongle/nrf52840 name: nRF52840-Dongle-NRF52840 type: mcu arch: arm diff --git a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_defconfig similarity index 82% rename from boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig rename to boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_defconfig index 36998fc79a1201..ffaccd75ea8bf9 100644 --- a/boards/arm/nrf52840dongle_nrf52840/nrf52840dongle_nrf52840_defconfig +++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_NRF52840DONGLE_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52840dongle_nrf52840/pre_dt_board.cmake b/boards/nordic/nrf52840dongle/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52840dongle_nrf52840/pre_dt_board.cmake rename to boards/nordic/nrf52840dongle/pre_dt_board.cmake diff --git a/boards/nordic/nrf52dk/CMakeLists.txt b/boards/nordic/nrf52dk/CMakeLists.txt new file mode 100644 index 00000000000000..9135ec34d6fbc1 --- /dev/null +++ b/boards/nordic/nrf52dk/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF52DK_NRF52805 OR CONFIG_BOARD_NRF52DK_NRF52810) + # The nrf52dk_nrf52805/nrf52dk_nrf52810 boards mirrors the nRF52832 DK hardware. This + # needs to be considered by certain system initialization functionality + # residing in system_nrf52810.c and SoC dependent routines in nrfx_coredep.h. + zephyr_compile_definitions(DEVELOP_IN_NRF52832) + zephyr_compile_definitions(NRFX_COREDEP_DELAY_US_LOOP_CYCLES=3) +endif() diff --git a/boards/nordic/nrf52dk/Kconfig b/boards/nordic/nrf52dk/Kconfig new file mode 100644 index 00000000000000..fb039240e0197b --- /dev/null +++ b/boards/nordic/nrf52dk/Kconfig @@ -0,0 +1,18 @@ +# nRF52 DK nRF52810 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52DK + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT + +endif # BOARD_NRF52DK diff --git a/boards/nordic/nrf52dk/Kconfig.nrf52dk b/boards/nordic/nrf52dk/Kconfig.nrf52dk new file mode 100644 index 00000000000000..d04465a513563a --- /dev/null +++ b/boards/nordic/nrf52dk/Kconfig.nrf52dk @@ -0,0 +1,9 @@ +# nRF52 DK nRF52810 board configuration + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52DK + select SOC_NRF52805_CAAA if BOARD_NRF52DK_NRF52805 + select SOC_NRF52810_QFAA if BOARD_NRF52DK_NRF52810 + select SOC_NRF52832_QFAA if BOARD_NRF52DK_NRF52832 diff --git a/boards/arm/nrf52dk_nrf52832/board.cmake b/boards/nordic/nrf52dk/board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52832/board.cmake rename to boards/nordic/nrf52dk/board.cmake diff --git a/boards/nordic/nrf52dk/board.yml b/boards/nordic/nrf52dk/board.yml new file mode 100644 index 00000000000000..1f21be9c60e4e2 --- /dev/null +++ b/boards/nordic/nrf52dk/board.yml @@ -0,0 +1,7 @@ +board: + name: nrf52dk + vendor: nordic + socs: + - name: nrf52805 + - name: nrf52810 + - name: nrf52832 diff --git a/boards/arm/nrf52dk_nrf52832/doc/img/nrf52dk_nrf52832.jpg b/boards/nordic/nrf52dk/doc/img/nrf52dk_nrf52832.jpg similarity index 100% rename from boards/arm/nrf52dk_nrf52832/doc/img/nrf52dk_nrf52832.jpg rename to boards/nordic/nrf52dk/doc/img/nrf52dk_nrf52832.jpg diff --git a/boards/nordic/nrf52dk/doc/index.rst b/boards/nordic/nrf52dk/doc/index.rst new file mode 100644 index 00000000000000..07f241eac1efed --- /dev/null +++ b/boards/nordic/nrf52dk/doc/index.rst @@ -0,0 +1,455 @@ +.. _nrf52dk_nrf52832: + +nRF52 DK +######## + +Overview +******** + +The nRF52 Development Kit (PCA10040) hardware provides +support for the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf52dk_nrf52832.jpg + :align: center + :alt: nRF52 DK + + nRF52 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF52 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF52 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf52dk/nrf52832`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `nRF52 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF52 Development Kit board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.17 +* LED2 (green) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* LD5 (red/green) = OB LED 1/2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +J-Link Prog Connector + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug IN + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | VDD | N/A | ++-------+--------------+-------------------------+ +| 2 | SWDIO | SWDIO | ++-------+--------------+-------------------------+ +| 3 | GND | N/A | ++-------+--------------+-------------------------+ +| 4 | SWDCLK | SWDCLK | ++-------+--------------+-------------------------+ +| 5 | GND | N/A | ++-------+--------------+-------------------------+ +| 6 | P0.18 | P0.18 / TRACEDATA[0] / | +| | | SWO | ++-------+--------------+-------------------------+ +| 7 | Cut off | N/A | ++-------+--------------+-------------------------+ +| 8 | Cut off | N/A | ++-------+--------------+-------------------------+ +| 9 | GND | N/A | ++-------+--------------+-------------------------+ +| 10 | P0.21 | P0.21 / RESET | ++-------+--------------+-------------------------+ + +Debug OUT + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | +| | | ++-------+----------------+ +| 7 | Cut off | ++-------+----------------+ +| 8 | Cut off | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Shield Debug and Current measurement + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | VDD_nRF | ++-------+----------------+ +| 2 | VDD | ++-------+----------------+ +| 3 | SH_VTG | ++-------+----------------+ +| 4 | SH_SWDIO | ++-------+----------------+ +| 5 | SH_SWDCLK | ++-------+----------------+ +| 6 | SH_SWO | ++-------+----------------+ +| 7 | SH_RESET | ++-------+----------------+ +| 8 | SH_GND_DETECT | ++-------+----------------+ + +Auxiliary + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | P0.00 | P0.00 / XL1 | ++-------+--------------+-------------------------+ +| 2 | P0.01 | P0.01 / XL2 | ++-------+--------------+-------------------------+ +| 3 | P0.21 | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | P0.05_C | P0.05 / AIN3 | ++-------+--------------+-------------------------+ +| 5 | P0.06_C | P0.06 | ++-------+--------------+-------------------------+ +| 6 | P0.07_C | P0.07 | ++-------+--------------+-------------------------+ +| 7 | P0.08_C | P0.08 | ++-------+--------------+-------------------------+ +| 8 | P0.09 | P0.09 / NFC1 | ++-------+--------------+-------------------------+ +| 9 | P0.10 | P0.10 / NFC2 | ++-------+--------------+-------------------------+ + +Arduino Headers +--------------- + +P1/P7 Power + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | VDD | N/A | ++-------+--------------+-------------------------+ +| 2 | VDD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | VDD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | VIN | N/A | ++-------+--------------+-------------------------+ + +P2/P8 Analog in + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +P3/P9 Digital I/O + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | D0 (RX) | P0.11 | ++-------+--------------+-------------------------+ +| 2 | D1 (TX) | P0.12 | ++-------+--------------+-------------------------+ +| 3 | D2 | P0.13 | ++-------+--------------+-------------------------+ +| 4 | D3 | P0.14 / TRACEDATA[3] | ++-------+--------------+-------------------------+ +| 5 | D4 | P0.15 / TRACEDATA[2] | ++-------+--------------+-------------------------+ +| 6 | D5 | P0.16 / TRACEDATA[1] | ++-------+--------------+-------------------------+ +| 7 | D6 | P0.17 | ++-------+--------------+-------------------------+ +| 8 | D7 | P0.18 / TRACEDATA[3] / | +| | | SWO | ++-------+--------------+-------------------------+ + +P4/P10 Digital I/O + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | D8 | P0.19 | ++-------+--------------+-------------------------+ +| 2 | D9 | P0.20 / TRACECLK | ++-------+--------------+-------------------------+ +| 3 | D10 (SS) | P0.22 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 6 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 9 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 10 | SCL | P0.27 | ++-------+--------------+-------------------------+ + +P5/P11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NRF52832 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf52dk/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF52 DK +******************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf52dk/nrf52dk_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com + +.. _nrf52dk_nrf52805: + +nRF52805 emulation on nRF52 DK +############################## + +Overview +******** + +The ``nrf52dk/nrf52805`` board is a modified version of the :ref:`nrf52dk_nrf52832` +that enforces the limitations imposed by the nRF52805 IC, which is a +cost-reduced variant of the original nRF52832. Since Nordic does not offer a +development kit for the nRF52805, you can use this board to develop for this +IC while using the nRF52 Development Kit (PCA10040). + +See :ref:`nrf52dk_nrf52832` for more information about the development board and +`nRF52805 website`_ for the official reference on the IC itself. + +References +********** + +.. target-notes:: + +.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 + +.. _nrf52dk_nrf52810: + +nRF52810 emulation on nRF52 DK +############################## + +Overview +******** + +The ``nrf52dk/nrf52810`` board is a modified version of the :ref:`nrf52dk_nrf52832` +that enforces the limitations imposed by the nRF52810 IC, which is a +cost-reduced variant of the original nRF52832. Since Nordic does not offer a +development kit for the nRF52810 you can use this board to develop for this +IC while using the nRF52 Development Kit (PCA10040). + +See :ref:`nrf52dk_nrf52832` for more information about the development board and +`nRF52810 website`_ for the official reference on the IC itself. + + +References +********** + +.. target-notes:: + +.. _nRF52810 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52810 diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805-pinctrl.dtsi rename to boards/nordic/nrf52dk/nrf52dk_nrf52805-pinctrl.dtsi diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52805.dts similarity index 100% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.dts rename to boards/nordic/nrf52dk/nrf52dk_nrf52805.dts diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml similarity index 84% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.yaml rename to boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml index 3ebff8db1a461c..86d3e44b8eff73 100644 --- a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805.yaml +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml @@ -1,4 +1,4 @@ -identifier: nrf52dk_nrf52805 +identifier: nrf52dk/nrf52805 name: nRF52-DK-NRF52805 type: mcu arch: arm diff --git a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52805_defconfig similarity index 81% rename from boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805_defconfig rename to boards/nordic/nrf52dk/nrf52dk_nrf52805_defconfig index d1c9da8186cf8e..a4b09719b93005 100644 --- a/boards/arm/nrf52dk_nrf52805/nrf52dk_nrf52805_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52805_CAAA=y -CONFIG_BOARD_NRF52DK_NRF52805=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810-pinctrl.dtsi rename to boards/nordic/nrf52dk/nrf52dk_nrf52810-pinctrl.dtsi diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52810.dts similarity index 100% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.dts rename to boards/nordic/nrf52dk/nrf52dk_nrf52810.dts diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml similarity index 84% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.yaml rename to boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml index 05e07eeba2a2f8..46cc9adbac6b44 100644 --- a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810.yaml +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml @@ -1,4 +1,4 @@ -identifier: nrf52dk_nrf52810 +identifier: nrf52dk/nrf52810 name: nRF52-DK-NRF52810 type: mcu arch: arm diff --git a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52810_defconfig similarity index 83% rename from boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810_defconfig rename to boards/nordic/nrf52dk/nrf52dk_nrf52810_defconfig index a90ea346ba08e5..a6749163af4194 100644 --- a/boards/arm/nrf52dk_nrf52810/nrf52dk_nrf52810_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52810_QFAA=y -CONFIG_BOARD_NRF52DK_NRF52810=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832-pinctrl.dtsi b/boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832-pinctrl.dtsi rename to boards/nordic/nrf52dk/nrf52dk_nrf52832-pinctrl.dtsi diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts b/boards/nordic/nrf52dk/nrf52dk_nrf52832.dts similarity index 100% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.dts rename to boards/nordic/nrf52dk/nrf52dk_nrf52832.dts diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml similarity index 89% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.yaml rename to boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml index 209069df379f38..f50bb91ba040e8 100644 --- a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832.yaml +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: nrf52dk_nrf52832 +identifier: nrf52dk/nrf52832 name: nRF52-DK-NRF52832 type: mcu arch: arm diff --git a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832_defconfig b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig similarity index 77% rename from boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832_defconfig rename to boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig index 1f1eccdbec22f1..8daa29dc47326f 100644 --- a/boards/arm/nrf52dk_nrf52832/nrf52dk_nrf52832_defconfig +++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_NRF52DK_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52_adafruit_feather/pre_dt_board.cmake b/boards/nordic/nrf52dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_adafruit_feather/pre_dt_board.cmake rename to boards/nordic/nrf52dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf5340_audio_dk/CMakeLists.txt b/boards/nordic/nrf5340_audio_dk/CMakeLists.txt new file mode 100644 index 00000000000000..63112d0d00bff1 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(nrf5340_audio_dk_cpunet_reset.c) + + if(CONFIG_BUILD_WITH_TFM) + zephyr_library_include_directories( + $/api_ns/interface/include + ) + endif() +endif() diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig b/boards/nordic/nrf5340_audio_dk/Kconfig new file mode 100644 index 00000000000000..e626c40acc77cc --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/Kconfig @@ -0,0 +1,61 @@ +# nRF5340 Audio DK board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "nRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "nrf5340_audio_dk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "nrf5340_audio_dk/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig new file mode 100644 index 00000000000000..c8d07e2adfab8c --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/Kconfig.defconfig @@ -0,0 +1,77 @@ +# nRF5340 Audio DK board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP || BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/Kconfig.nrf5340_audio_dk b/boards/nordic/nrf5340_audio_dk/Kconfig.nrf5340_audio_dk new file mode 100644 index 00000000000000..a04b8f85a6a679 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/Kconfig.nrf5340_audio_dk @@ -0,0 +1,9 @@ +# nRF5340 Audio DK board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340_AUDIO_DK + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340_audio_dk/board.cmake b/boards/nordic/nrf5340_audio_dk/board.cmake new file mode 100644 index 00000000000000..b44ece9b7e5c09 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/board.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") +endif() + +if(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP OR CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(CONFIG_BOARD_NRF5340_AUDIO_DK_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/nrf5340_audio_dk/board.yml b/boards/nordic/nrf5340_audio_dk/board.yml new file mode 100644 index 00000000000000..443381b9461a73 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf5340_audio_dk + vendor: nordic + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/doc/img/nrf5340_audio_dk.jpg b/boards/nordic/nrf5340_audio_dk/doc/img/nrf5340_audio_dk.jpg similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/doc/img/nrf5340_audio_dk.jpg rename to boards/nordic/nrf5340_audio_dk/doc/img/nrf5340_audio_dk.jpg diff --git a/boards/nordic/nrf5340_audio_dk/doc/index.rst b/boards/nordic/nrf5340_audio_dk/doc/index.rst new file mode 100644 index 00000000000000..558f995be66257 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/doc/index.rst @@ -0,0 +1,109 @@ +.. _nrf5340_audio_dk_nrf5340: + +nRF5340 Audio DK +################ + +Overview +******** + +The nRF5340 Audio DK (PCA10121) is designed for showcasing, developing and experimenting +with Bluetooth® LE Audio. + +You can use this board for developing LE-Audio-compatible applications that support Auracast™, +connected isochronous streams (CIS) and broadcast isochronous streams (BIS), +and offer support for acting as a audio source, audio sink and source + sink. + +Zephyr uses the ``nrf5340_audio_dk/nrf5340`` board configuration for building +for the nRF5340 Audio DK. + +Hardware +******** + +The nRF5340 Audio DK comes with the following hardware features: + +* nRF5340 dual-core SoC based on the Arm® Cortex®-M33 architecture +* CS47L63 Low-Power Audio DSP with mono differential headphone driver +* nPM1100 Ultra-small form-factor Power Management IC +* On-board digital microphone +* On-board power measurement +* SD card slot +* Built-in debugger +* Stereo analog input using 3.5 mm jack +* USB soundcard capability + +.. figure:: img/nrf5340_audio_dk.jpg + :align: center + :alt: nRF5340 DK + +More information about the board can be found at the `nRF5340 Audio DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + +nRF5340 SoC +=========== + +The nRF5340 Audio DK is built around the nRF5340 SoC, which has the following characteristics: + +* A full-featured Arm Cortex-M33F core with DSP instructions, + FPU, and Armv8-M Security Extension, running at up to 128 MHz, + referred to as the **application core**. +* A secondary Arm Cortex-M33 core, with a reduced feature set, + running at a fixed 64 MHz, referred to as the **network core**. + +The ``nrf5340_audio_dk/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``nrf5340_audio_dk/nrf5340/cpunet`` build target provides +support for the network core on the nRF5340 SoC. + +The `Nordic Semiconductor Infocenter`_ contains the processor's information and +the datasheet. + +Supported Features +================== + +See :ref:`nrf5340dk_nrf5340` and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF5340 Audio DK board hardware features. + + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the nRF5340 Audio DK requires + upgrading the nRF Command Line Tools to version 10.12.0. Further + information on how to install the nRF Command Line Tools can be + found in :ref:`nordic_segger_flashing`. + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + +References +********** + +.. target-notes:: + +.. _nRF5340 Audio DK website: + https://www.nordicsemi.com/Products/Development-hardware/nrf5340-audio-dk +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_cpunet_reset.c b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_cpunet_reset.c rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_cpunet_reset.c diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.dts rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.dts diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml similarity index 84% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.yaml rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml index d5598ed9efcb81..9c131a6c9d46be 100644 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340_audio_dk_nrf5340_cpuapp +identifier: nrf5340_audio_dk/nrf5340/cpuapp name: NRF5340-AUDIO-DK-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_common.dtsi diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..516f0cf7407af1 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_ARM_TRUSTZONE_M=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml similarity index 83% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml index 7b670992a87fa4..4194fc63574801 100644 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340_audio_dk_nrf5340_cpuapp_ns +identifier: nrf5340_audio_dk/nrf5340/cpuapp/ns name: NRF5340-AUDIO-DK-NRF5340-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000000..5883909a4f027d --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_partition_conf.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.dts rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.dts diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml similarity index 79% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.yaml rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml index 28ecb10a8b52c2..35e0ba7ca28759 100644 --- a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_cpunet.yaml +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340_audio_dk_nrf5340_cpunet +identifier: nrf5340_audio_dk/nrf5340/cpunet name: NRF5340-AUDIO-DK-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet_defconfig b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..56940c43a096e0 --- /dev/null +++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/frdm_kw41z/CMakeLists.txt b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig similarity index 100% rename from boards/arm/frdm_kw41z/CMakeLists.txt rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_defconfig diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi rename to boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/arm/nrf5340_audio_dk_nrf5340/pre_dt_board.cmake b/boards/nordic/nrf5340_audio_dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf5340_audio_dk_nrf5340/pre_dt_board.cmake rename to boards/nordic/nrf5340_audio_dk/pre_dt_board.cmake diff --git a/boards/arm/nrf5340dk_nrf5340/CMakeLists.txt b/boards/nordic/nrf5340dk/CMakeLists.txt similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/CMakeLists.txt rename to boards/nordic/nrf5340dk/CMakeLists.txt diff --git a/boards/nordic/nrf5340dk/Kconfig b/boards/nordic/nrf5340dk/Kconfig new file mode 100644 index 00000000000000..7513fab4277e01 --- /dev/null +++ b/boards/nordic/nrf5340dk/Kconfig @@ -0,0 +1,58 @@ +# nRF5340 DK board configuration + +# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "nrf5340dk/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config DOMAIN_CPUAPP_BOARD + string + default "nrf5340dk/nrf5340/cpuapp" + depends on BOARD_NRF5340DK_NRF5340_CPUNET + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. diff --git a/boards/nordic/nrf5340dk/Kconfig.defconfig b/boards/nordic/nrf5340dk/Kconfig.defconfig new file mode 100644 index 00000000000000..67d7c7db9d553e --- /dev/null +++ b/boards/nordic/nrf5340dk/Kconfig.defconfig @@ -0,0 +1,78 @@ +# nRF5340 DK nRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_NRF5340DK_NRF5340_CPUAPP_NS + +if BOARD_NRF5340DK_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_NRF5340DK_NRF5340_CPUNET diff --git a/boards/nordic/nrf5340dk/Kconfig.nrf5340dk b/boards/nordic/nrf5340dk/Kconfig.nrf5340dk new file mode 100644 index 00000000000000..6d9e11d7faa690 --- /dev/null +++ b/boards/nordic/nrf5340dk/Kconfig.nrf5340dk @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Zephyr Project members and individual contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF5340DK + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340DK_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_NRF5340DK_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_NRF5340DK_NRF5340_CPUNET diff --git a/boards/arm/nrf5340dk_nrf5340/board.cmake b/boards/nordic/nrf5340dk/board.cmake similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/board.cmake rename to boards/nordic/nrf5340dk/board.cmake diff --git a/boards/nordic/nrf5340dk/board.yml b/boards/nordic/nrf5340dk/board.yml new file mode 100644 index 00000000000000..fd90df34350c5d --- /dev/null +++ b/boards/nordic/nrf5340dk/board.yml @@ -0,0 +1,8 @@ +board: + name: nrf5340dk + vendor: nordic + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/nrf5340dk_nrf5340/doc/img/nrf5340dk.jpg b/boards/nordic/nrf5340dk/doc/img/nrf5340dk.jpg similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/doc/img/nrf5340dk.jpg rename to boards/nordic/nrf5340dk/doc/img/nrf5340dk.jpg diff --git a/boards/nordic/nrf5340dk/doc/index.rst b/boards/nordic/nrf5340dk/doc/index.rst new file mode 100644 index 00000000000000..f8ce8a2a84b8af --- /dev/null +++ b/boards/nordic/nrf5340dk/doc/index.rst @@ -0,0 +1,330 @@ +.. _nrf5340dk_nrf5340: + +nRF5340 DK +########## + +Overview +******** + +The nRF5340 DK (PCA10095) is a single-board development kit for evaluation +and development on the Nordic nRF5340 System-on-Chip (SoC). + +The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running at + a fixed 64 MHz, referred to as the **network core**. + +The ``nrf5340dk/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``nrf5340dk/nrf5340/cpunet`` build target provides +support for the network core on the nRF5340 SoC. + +nRF5340 SoC provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf5340dk.jpg + :align: center + :alt: nRF5340 DK + + nRF5340 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF5340 DK website`_. +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF5340 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf5340dk/nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``nrf5340dk/nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `Nordic Semiconductor Infocenter`_ +for a complete list of nRF5340 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.28 +* LED2 (green) = P0.29 +* LED3 (green) = P0.30 +* LED4 (green) = P0.31 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.23 +* BUTTON2 = SW2 = P0.24 +* BUTTON3 = SW3 = P0.8 +* BUTTON4 = SW4 = P0.9 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application core. + The IDAU is implemented with the System Protection Unit and is used to + define secure and non-secure memory maps. By default, all of the memory + space (Flash, SRAM, and peripheral address space) is defined to be secure + accessible only. +- Secure boot. + +Programming and Debugging +************************* + +nRF5340 application core supports the Armv8-M Security Extension. +Applications built for the ``nrf5340dk/nrf5340/cpuapp`` board by default +boot in the Secure state. + +nRF5340 network core does not support the Armv8-M Security Extension. +nRF5340 IDAU may configure bus accesses by the nRF5340 network core +to have Secure attribute set; the latter allows to build and run +Secure only applications on the nRF5340 SoC. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF5340 may contain a Secure and a Non-Secure firmware +image for the application core. The Secure image can be built using either +Zephyr or `Trusted Firmware M`_ (TF-M). Non-Secure firmware +images are always built using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for nRF5340 application core is built + using TF-M. + + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following steps: + +1. Build the Non-Secure Zephyr application + for the application core using ``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output image binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +2. Build the application firmware for the network core using + ``-DBOARD=nrf5340dk/nrf5340/cpunet``. + + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process to build the Secure and the Non-Secure firmware images +using Zephyr requires the following steps: + +1. Build the Secure Zephyr application for the application core + using ``-DBOARD=nrf5340dk/nrf5340/cpuapp`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` and ``CONFIG_BUILD_WITH_TFM=n`` + in the application project configuration file. +2. Build the Non-Secure Zephyr application for the application core + using ``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns``. +3. Merge the two binaries together. +4. Build the application firmware for the network core using + ``-DBOARD=nrf5340dk/nrf5340/cpunet``. + + +When building a Secure/Non-Secure application for the nRF5340 application core, +the Secure application will have to set the IDAU (SPU) configuration to allow +Non-Secure access to all CPU resources utilized by the Non-Secure application +firmware. SPU configuration shall take place before jumping to the Non-Secure +application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf5340dk/nrf5340/cpuapp`` for +the firmware running on the nRF5340 application core, and using +``-DBOARD=nrf5340dk/nrf5340/cpunet`` for the firmware running +on the nRF5340 network core. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then you can build and flash +applications as usual (:ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + + .. code-block:: console + + west flash -H -r nrfjprog --skip-rebuild + +.. note:: + + Flashing and debugging applications on the nRF5340 DK requires + upgrading the nRF Command Line Tools to version 10.12.0. Further + information on how to install the nRF Command Line Tools can be + found in :ref:`nordic_segger_flashing`. + +Here is an example for the :ref:`hello_world` application running on the +nRF5340 application core. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF5340 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf5340dk/nrf5340/cpuapp + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + + +Testing the LEDs and buttons in the nRF5340 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and +LEDs on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF5340 DK website: + https://www.nordicsemi.com/Software-and-tools/Development-Kits/nRF5340-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/nordic/nrf5340dk/nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_common.dtsi rename to boards/nordic/nrf5340dk/nrf5340_cpuapp_common.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_partition_conf.dtsi b/boards/nordic/nrf5340dk/nrf5340_cpuapp_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpuapp_partition_conf.dtsi rename to boards/nordic/nrf5340dk/nrf5340_cpuapp_partition_conf.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_cpunet_reset.c b/boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_cpunet_reset.c rename to boards/nordic/nrf5340dk/nrf5340_cpunet_reset.c diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340_shared_sram_planning_conf.dtsi rename to boards/nordic/nrf5340dk/nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.dts rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml similarity index 87% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml index 6ed15a5d7ef1e2..0a8bfabf5c4685 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340dk_nrf5340_cpuapp +identifier: nrf5340dk/nrf5340/cpuapp name: NRF5340-DK-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_defconfig similarity index 75% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_defconfig rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_defconfig index 22e8f52ff31cb5..db40370dad0159 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_defconfig +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.dts rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml similarity index 86% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.yaml rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml index 90abc04b11940e..4b311f76e25d68 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340dk_nrf5340_cpuapp_ns +identifier: nrf5340dk/nrf5340/cpuapp/ns name: NRF5340-DK-NRF5340-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns_defconfig b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns_defconfig similarity index 79% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns_defconfig rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns_defconfig index 0fe351e2780623..1886b926bfd5a2 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpuapp_ns_defconfig +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.dts rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.dts diff --git a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml similarity index 82% rename from boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.yaml rename to boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml index 2f92bb86440b2b..a55a7879fc015e 100644 --- a/boards/arm/nrf5340dk_nrf5340/nrf5340dk_nrf5340_cpunet.yaml +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml @@ -1,4 +1,4 @@ -identifier: nrf5340dk_nrf5340_cpunet +identifier: nrf5340dk/nrf5340/cpunet name: NRF5340-DK-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet_defconfig b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..39428726753984 --- /dev/null +++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf5340dk_nrf5340/pre_dt_board.cmake b/boards/nordic/nrf5340dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf5340dk_nrf5340/pre_dt_board.cmake rename to boards/nordic/nrf5340dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf54h20pdk/Kconfig.defconfig b/boards/nordic/nrf54h20pdk/Kconfig.defconfig new file mode 100644 index 00000000000000..5aa509ba12efe1 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54H20PDK + +# Data cache is disabled due to a HW issue in the EngA SoC revision. +config DCACHE + default n + +endif # BOARD_NRF54H20PDK diff --git a/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk b/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk new file mode 100644 index 00000000000000..4185c95ef2a916 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/Kconfig.nrf54h20pdk @@ -0,0 +1,7 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54H20PDK + select SOC_NRF54H20_ENGA_CPUAPP if BOARD_NRF54H20PDK_NRF54H20_CPUAPP + select SOC_NRF54H20_ENGA_CPURAD if BOARD_NRF54H20PDK_NRF54H20_CPURAD + select SOC_NRF54H20_ENGA_CPUPPR if BOARD_NRF54H20PDK_NRF54H20_CPUPPR diff --git a/boards/arm/nrf54h20pdk_nrf54h20/board.cmake b/boards/nordic/nrf54h20pdk/board.cmake similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/board.cmake rename to boards/nordic/nrf54h20pdk/board.cmake diff --git a/boards/nordic/nrf54h20pdk/board.yml b/boards/nordic/nrf54h20pdk/board.yml new file mode 100644 index 00000000000000..50e2945307f87d --- /dev/null +++ b/boards/nordic/nrf54h20pdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf54h20pdk + vendor: nordic + socs: + - name: nrf54h20 diff --git a/boards/arm/nrf54h20pdk_nrf54h20/doc/img/nrf54h20pdk_nrf54h20.webp b/boards/nordic/nrf54h20pdk/doc/img/nrf54h20pdk_nrf54h20.webp similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/doc/img/nrf54h20pdk_nrf54h20.webp rename to boards/nordic/nrf54h20pdk/doc/img/nrf54h20pdk_nrf54h20.webp diff --git a/boards/nordic/nrf54h20pdk/doc/index.rst b/boards/nordic/nrf54h20pdk/doc/index.rst new file mode 100644 index 00000000000000..dd30ff1d133f3b --- /dev/null +++ b/boards/nordic/nrf54h20pdk/doc/index.rst @@ -0,0 +1,153 @@ +.. _nrf54h20pdk_nrf54h20: + +nRF54H20 PDK +############ + +Overview +******** + +.. note:: + + All software for the nRF54H20 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54H20 PDK is a single-board preview development kit for evaluation +and development on the Nordic nRF54H20 System-on-Chip (SoC). + +The nRF54H20 is a multicore SoC with: + +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 320 MHz, referred to as the **application core** +* an Arm Cortex-M33 core with DSP instructions, FPU, and Armv8-M Security + Extensions, running at up to 256 MHz, referred to as the **radio core**. + +The ``nrf54h20pdk/nrf54h20/cpuapp`` build target provides support for +the application core on the nRF54H20 SoC. +The ``nrf54h20pdk/nrf54h20/cpurad`` build target provides support for +the radio core on the nRF54H20 SoC. + +nRF54H20 SoC provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`GPIOTE (General Purpose Input Output tasks and events)` +* :abbr:`GRTC (Global real-time counter)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* MRAM +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf54h20pdk_nrf54h20.webp + :align: center + :alt: nRF54H20 PDK + + nRF54H20 PDK (Credit: Nordic Semiconductor) + +Hardware +******** + +nRF54H20 PDK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +Supported Features +================== + +The ``nrf54h20pdk/nrf54h20/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIOTE | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ + +The ``nrf54h20pdk/nrf54h20/cpurad`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIOTE | on-chip | gpio | ++-----------+------------+----------------------+ +| GRTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LEDs +---- + +* LED1 (green) = P9.0 +* LED2 (green) = P9.1 +* LED3 (green) = P9.2 +* LED4 (green) = P9.3 + +Push buttons +------------ + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* BUTTON3 = P0.10 +* BUTTON4 = P0.11 +* RESET (SW1) + +Programming and Debugging +************************* + +Applications for both the ``nrf54h20pdk/nrf54h20/cpuapp`` and +``nrf54h20pdk/nrf54h20/cpurad`` targets can be built, flashed, +and debugged in the usual way. See :ref:`build_an_application` +and :ref:`application_run` for more details on building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54H20 PDK, complete the following steps: + +First, connect the nRF54H20 PDK to you computer using the IMCU USB port on the PDK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54h20pdk/nrf54h20/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54H20 PDK +************************************************ + +There are 2 samples that allow you to test that the buttons (switches) and LEDs +on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts`. diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_defconfig new file mode 100644 index 00000000000000..bad567cbd7445e --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-memory_map.dtsi rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-memory_map.dtsi diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20-pinctrl.dtsi rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20-pinctrl.dtsi diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.dts rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.dts diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml similarity index 85% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml index a364c2863d370d..3c2b266c530cbd 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuapp.yaml +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20pdk_nrf54h20_cpuapp +identifier: nrf54h20pdk/nrf54h20/cpuapp name: nRF54H20-PDK-nRF54H20-Application type: mcu arch: arm diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig new file mode 100644 index 00000000000000..b014eb7b03111a --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuapp_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts similarity index 100% rename from boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.dts rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.dts diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml similarity index 83% rename from boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml index 274be865c36e20..e3cdc3cd1c880a 100644 --- a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr.yaml +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20pdk_nrf54h20_cpuppr +identifier: nrf54h20pdk/nrf54h20/cpuppr name: nRF54H20-PDK-nRF54H20-PPR type: mcu arch: riscv diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig new file mode 100644 index 00000000000000..0e657c5081e7f8 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpuppr_defconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts similarity index 100% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.dts rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.dts diff --git a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml similarity index 84% rename from boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml rename to boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml index d1c8548d07d0ac..138adf12001310 100644 --- a/boards/arm/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpurad.yaml +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54h20pdk_nrf54h20_cpurad +identifier: nrf54h20pdk/nrf54h20/cpurad name: nRF54H20-PDK-nRF54H20-Radio type: mcu arch: arm diff --git a/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig new file mode 100644 index 00000000000000..1a62a205502172 --- /dev/null +++ b/boards/nordic/nrf54h20pdk/nrf54h20pdk_nrf54h20_cpurad_defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_USE_DT_CODE_PARTITION=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# MPU-based null-pointer dereferencing detection cannot be applied +# as the (0x0 - 0x400) region is unmapped for this target. +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +# Enable cache +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake b/boards/nordic/nrf54h20pdk/pre_dt_board.cmake similarity index 100% rename from boards/riscv/nrf54h20pdk_nrf54h20/pre_dt_board.cmake rename to boards/nordic/nrf54h20pdk/pre_dt_board.cmake diff --git a/boards/nordic/nrf54l15pdk/Kconfig.defconfig b/boards/nordic/nrf54l15pdk/Kconfig.defconfig new file mode 100644 index 00000000000000..bd9c723161695c --- /dev/null +++ b/boards/nordic/nrf54l15pdk/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF54L15PDK_NRF54L15_CPUAPP + +config BT_CTLR + default BT + +endif # BOARD_NRF54L15PDK_NRF54L15_CPUAPP diff --git a/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk new file mode 100644 index 00000000000000..4ec5b6ee62decb --- /dev/null +++ b/boards/nordic/nrf54l15pdk/Kconfig.nrf54l15pdk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF54L15PDK_NRF54L15_CPUAPP + select SOC_NRF54L15_ENGA_CPUAPP diff --git a/boards/arm/nrf54l15pdk_nrf54l15/board.cmake b/boards/nordic/nrf54l15pdk/board.cmake similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/board.cmake rename to boards/nordic/nrf54l15pdk/board.cmake diff --git a/boards/nordic/nrf54l15pdk/board.yml b/boards/nordic/nrf54l15pdk/board.yml new file mode 100644 index 00000000000000..b33ecf7c4f63a5 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf54l15pdk + vendor: nordic + socs: + - name: nrf54l15 diff --git a/boards/arm/nrf54l15pdk_nrf54l15/doc/img/nrf54l15pdk_nrf54l15.webp b/boards/nordic/nrf54l15pdk/doc/img/nrf54l15pdk_nrf54l15.webp similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/doc/img/nrf54l15pdk_nrf54l15.webp rename to boards/nordic/nrf54l15pdk/doc/img/nrf54l15pdk_nrf54l15.webp diff --git a/boards/nordic/nrf54l15pdk/doc/index.rst b/boards/nordic/nrf54l15pdk/doc/index.rst new file mode 100644 index 00000000000000..ccc6230dd7dff6 --- /dev/null +++ b/boards/nordic/nrf54l15pdk/doc/index.rst @@ -0,0 +1,139 @@ +.. _nrf54l15pdk_nrf54l15: + +nRF54L15 PDK +############ + +Overview +******** + +.. note:: + + All software for the nRF54L15 SoC is experimental and hardware availability + is restricted to the participants in the limited sampling program. + +The nRF54L15 Preview Development Kit hardware provides +support for the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU and +the following devices: + +* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)` +* CLOCK +* RRAM +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`GRTC (Global real-time counter)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/nrf54l15pdk_nrf54l15.webp + :align: center + :alt: nRF54L15 PDK + + nRF54L15 PDK (Credit: Nordic Semiconductor) + +Hardware +******** + +nRF54L15 PDK has two crystal oscillators: + +* High-frequency 32 MHz crystal oscillator (HFXO) +* Low-frequency 32.768 kHz crystal oscillator (LFXO) + +The crystal oscillators can be configured to use either +internal or external capacitors. + +Supported Features +================== + +The ``nrf54l15pdk/nrf54l15/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| SAADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| RRAM | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| TWIM | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| GRTC | on-chip | counter | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Programming and Debugging +************************* + +Applications for the ``nrf54l15pdk/nrf54l15/cpuapp`` board can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +As an example, this section shows how to build and flash the :ref:`hello_world` +application. + +.. warning:: + + When programming the device, you might get an error similar to the following message:: + + ERROR: The operation attempted is unavailable due to readback protection in + ERROR: your device. Please use --recover to unlock the device. + + This error occurs when readback protection is enabled. + To disable the readback protection, you must *recover* your device. + + Enter the following command to recover the core:: + + west flash --recover + + The ``--recover`` command erases the flash memory and then writes a small binary into + the recovered flash memory. + This binary prevents the readback protection from enabling itself again after a pin + reset or power cycle. + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. + +To build and program the sample to the nRF54L15 PDK, complete the following steps: + +First, connect the nRF54L15 PDK to you computer using the IMCU USB port on the PDK. +Next, build the sample by running the following command: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf54l15pdk/nrf54l15/cpuapp + :goals: build flash + +Testing the LEDs and buttons in the nRF54L15 PDK +************************************************ + +Test the nRF54L15 PDK with a :zephyr:code-sample:`blinky` sample. diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp-pinctrl.dtsi diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.dts rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.dts diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml similarity index 87% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml index de5ce29d162bc0..ddcd456fb4abd5 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp.yaml +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: nrf54l15pdk_nrf54l15_cpuapp +identifier: nrf54l15pdk/nrf54l15/cpuapp name: nRF54l15-PDK-nRF54l15-Application type: mcu arch: arm diff --git a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_defconfig b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig similarity index 85% rename from boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_defconfig rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig index bc74c3eeb336fc..0352761e0ce661 100644 --- a/boards/arm/nrf54l15pdk_nrf54l15/nrf54l15pdk_nrf54l15_cpuapp_defconfig +++ b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_cpuapp_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF54LX=y -CONFIG_SOC_NRF54L15_ENGA_CPUAPP=y -CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/hexiwear_kw40z/CMakeLists.txt b/boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig similarity index 100% rename from boards/arm/hexiwear_kw40z/CMakeLists.txt rename to boards/nordic/nrf54l15pdk/nrf54l15pdk_nrf54l15_defconfig diff --git a/boards/arm/nrf54l15pdk_nrf54l15/revision.cmake b/boards/nordic/nrf54l15pdk/revision.cmake similarity index 100% rename from boards/arm/nrf54l15pdk_nrf54l15/revision.cmake rename to boards/nordic/nrf54l15pdk/revision.cmake diff --git a/boards/nordic/nrf9131ek/Kconfig.defconfig b/boards/nordic/nrf9131ek/Kconfig.defconfig new file mode 100644 index 00000000000000..b63e7ef8d34c17 --- /dev/null +++ b/boards/nordic/nrf9131ek/Kconfig.defconfig @@ -0,0 +1,35 @@ +# nRF9131 EK NRF9131 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9131EK_NRF9131 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9131EK_NRF9131_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9131EK_NRF9131_NS + +endif # BOARD_NRF9131EK_NRF9131 || BOARD_NRF9131EK_NRF9131_NS diff --git a/boards/nordic/nrf9131ek/Kconfig.nrf9131ek b/boards/nordic/nrf9131ek/Kconfig.nrf9131ek new file mode 100644 index 00000000000000..447e4577a7d87b --- /dev/null +++ b/boards/nordic/nrf9131ek/Kconfig.nrf9131ek @@ -0,0 +1,7 @@ +# nRF9131-EK board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9131EK + select SOC_NRF9131_LACA diff --git a/boards/arm/nrf9131ek_nrf9131/board.cmake b/boards/nordic/nrf9131ek/board.cmake similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/board.cmake rename to boards/nordic/nrf9131ek/board.cmake diff --git a/boards/nordic/nrf9131ek/board.yml b/boards/nordic/nrf9131ek/board.yml new file mode 100644 index 00000000000000..246aef6f4e3a46 --- /dev/null +++ b/boards/nordic/nrf9131ek/board.yml @@ -0,0 +1,7 @@ +board: + name: nrf9131ek + vendor: nordic + socs: + - name: nrf9131 + variants: + - name: 'ns' diff --git a/boards/arm/nrf9131ek_nrf9131/doc/img/nrf9131ek_nrf9131.webp b/boards/nordic/nrf9131ek/doc/img/nrf9131ek_nrf9131.webp similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/doc/img/nrf9131ek_nrf9131.webp rename to boards/nordic/nrf9131ek/doc/img/nrf9131ek_nrf9131.webp diff --git a/boards/nordic/nrf9131ek/doc/index.rst b/boards/nordic/nrf9131ek/doc/index.rst new file mode 100644 index 00000000000000..4e328e0bb0ec81 --- /dev/null +++ b/boards/nordic/nrf9131ek/doc/index.rst @@ -0,0 +1,229 @@ +.. _nrf9131ek_nrf9131: + +nRF9131 EK +########## + +Overview +******** + +The nRF9131 EK (PCA10165) is a single-board evaluation kit for the nRF9131 SiP +for DECT NR+ and LTE-M/NB-IoT with GNSS. +The ``nrf9131ek/nrf9131`` board configuration provides support for the Nordic Semiconductor nRF9131 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/nrf9131ek_nrf9131.webp + :align: center + :alt: nRF9131 EK + + nRF9131 EK (Credit: Nordic Semiconductor) + +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9131 EK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf9131ek/nrf9131`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED (red) = P0.29 +* LED (green) = P0.30 +* LED (blue) = P0.31 + +Push buttons and Switches +------------------------- + +* BUTTON = P0.28 +* RESET + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +``nrf9131ek/nrf9131`` supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF9131 may contain a Secure and a Non-Secure firmware +image. The Secure image can be built using either Zephyr or +`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built +using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for nRF9131 is built using TF-M. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9131ek/nrf9131`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9131ek/nrf9131/ns``. +3. Merge the two binaries together. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following action: + +1. Build the Non-Secure Zephyr application + using ``-DBOARD=nrf9131ek/nrf9131/ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9131ek/nrf9131``. + + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9131 EK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9131ek/nrf9131 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9131 EK +********************************************** + +There are 2 samples that allow you to test that the button and LED on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.dts b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.dts similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.dts rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131.dts diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.yaml b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml similarity index 85% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.yaml rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml index d1b04054ce8914..8cb2adc385f0f4 100644 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131.yaml +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml @@ -1,4 +1,4 @@ -identifier: nrf9131ek_nrf9131 +identifier: nrf9131ek/nrf9131 name: nRF9131-EK-NRF9131 type: mcu arch: arm diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common-pinctrl.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common-pinctrl.dtsi rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common-pinctrl.dtsi diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_common.dtsi rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_common.dtsi diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig new file mode 100644 index 00000000000000..4936d06617fa1a --- /dev/null +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_PINCTRL=y diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.dts b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.dts rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.dts diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.yaml b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml similarity index 84% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.yaml rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml index cf33abd55da3c0..c6e312066bf48d 100644 --- a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_ns.yaml +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf9131ek_nrf9131_ns +identifier: nrf9131ek/nrf9131/ns name: nRF9131-EK-NRF9131-Non-Secure type: mcu arch: arm diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig new file mode 100644 index 00000000000000..4051bf70caa5a0 --- /dev/null +++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_PINCTRL=y + +# Enable PMIC +CONFIG_I2C=y +CONFIG_REGULATOR=y +CONFIG_SENSOR=y +CONFIG_NPM1300_CHARGER=y diff --git a/boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_partition_conf.dtsi b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9131ek_nrf9131/nrf9131ek_nrf9131_partition_conf.dtsi rename to boards/nordic/nrf9131ek/nrf9131ek_nrf9131_partition_conf.dtsi diff --git a/boards/arm/nrf9160_innblue21/pre_dt_board.cmake b/boards/nordic/nrf9131ek/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue21/pre_dt_board.cmake rename to boards/nordic/nrf9131ek/pre_dt_board.cmake diff --git a/boards/nordic/nrf9151dk/Kconfig.defconfig b/boards/nordic/nrf9151dk/Kconfig.defconfig new file mode 100644 index 00000000000000..21f036f7607917 --- /dev/null +++ b/boards/nordic/nrf9151dk/Kconfig.defconfig @@ -0,0 +1,44 @@ +# nRF9151 DK NRF9151 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9151DK_NRF9151 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9151DK_NRF9151_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9151DK_NRF9151_NS + +config BT_HCI_VS + default y if BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,nrf5340_reset) + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) + +endif # BOARD_NRF9151DK_NRF9151 || BOARD_NRF9151DK_NRF9151_NS diff --git a/boards/nordic/nrf9151dk/Kconfig.nrf9151dk b/boards/nordic/nrf9151dk/Kconfig.nrf9151dk new file mode 100644 index 00000000000000..3125926cd8c54d --- /dev/null +++ b/boards/nordic/nrf9151dk/Kconfig.nrf9151dk @@ -0,0 +1,7 @@ +# nRF9151 DK NRF9151 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9151DK + select SOC_NRF9151_LACA diff --git a/boards/arm/nrf9151dk_nrf9151/board.cmake b/boards/nordic/nrf9151dk/board.cmake similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/board.cmake rename to boards/nordic/nrf9151dk/board.cmake diff --git a/boards/nordic/nrf9151dk/board.yml b/boards/nordic/nrf9151dk/board.yml new file mode 100644 index 00000000000000..f765134a46042f --- /dev/null +++ b/boards/nordic/nrf9151dk/board.yml @@ -0,0 +1,7 @@ +board: + name: nrf9151dk + vendor: nordic + socs: + - name: nrf9151 + variants: + - name: 'ns' diff --git a/boards/nordic/nrf9151dk/doc/index.rst b/boards/nordic/nrf9151dk/doc/index.rst new file mode 100644 index 00000000000000..a3a56f632c6f5a --- /dev/null +++ b/boards/nordic/nrf9151dk/doc/index.rst @@ -0,0 +1,203 @@ +.. _nrf9151dk_nrf9151: + +nRF9151 DK +########## + +Overview +******** + +The nRF9151 DK (PCA10171) is a single-board development kit for evaluation and +development on the nRF9151 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The ``nrf9151dk/nrf9151`` +board configuration provides support for the Nordic Semiconductor nRF9151 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9151 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9151 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf9151dk/nrf9151`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| FLASH | external | spi | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIO | external | i2c | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | nRF53 | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + + +.. _nrf9151dk_additional_hardware: + +Other hardware features have not been enabled yet for this board. +See `nRF9151 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF9151 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.0 +* LED2 (green) = P0.1 +* LED3 (green) = P0.4 +* LED4 (green) = P0.5 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* SWITCH1 = P0.18 +* SWITCH2 = P0.19 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +``nrf9151dk/nrf9151`` supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9151dk/nrf9151`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9151dk/nrf9151/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9151dk/nrf9151``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9151 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9151dk/nrf9151 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9151 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF9151 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9151-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9151dk_nrf9151/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml b/boards/nordic/nrf9151dk/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml rename to boards/nordic/nrf9151dk/dts/bindings/nordic,nrf9151dk-nrf5340-reset.yaml diff --git a/boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9151dk/dts/nrf9151dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9151dk/dts/nrf9151dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9151dk/dts/nrf9151dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/dts/nrf9151dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9151dk/dts/nrf9151dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.dts b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.dts similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.dts rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151.dts diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.yaml b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml similarity index 89% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.yaml rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml index 3ad90fea76d9d6..aa4473d49ea361 100644 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151.yaml +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml @@ -1,4 +1,4 @@ -identifier: nrf9151dk_nrf9151 +identifier: nrf9151dk/nrf9151 name: nRF9151-DK-NRF9151 type: mcu arch: arm diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common-pinctrl.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common-pinctrl.dtsi rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common-pinctrl.dtsi diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_common.dtsi rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_common.dtsi diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_defconfig b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.dts b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.dts rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.dts diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.yaml b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml similarity index 88% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.yaml rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml index c5d4fe925415ea..97e78ff3736382 100644 --- a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_ns.yaml +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml @@ -1,4 +1,4 @@ -identifier: nrf9151dk_nrf9151_ns +identifier: nrf9151dk/nrf9151/ns name: nRF9151-DK-NRF9151-Non-Secure type: mcu arch: arm diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns_defconfig b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns_defconfig new file mode 100644 index 00000000000000..2a74dd56f4144a --- /dev/null +++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_partition_conf.dtsi b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9151dk_nrf9151/nrf9151dk_nrf9151_partition_conf.dtsi rename to boards/nordic/nrf9151dk/nrf9151dk_nrf9151_partition_conf.dtsi diff --git a/boards/arm/nrf9160_innblue22/pre_dt_board.cmake b/boards/nordic/nrf9151dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160_innblue22/pre_dt_board.cmake rename to boards/nordic/nrf9151dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf9160dk/CMakeLists.txt b/boards/nordic/nrf9160dk/CMakeLists.txt new file mode 100644 index 00000000000000..6b0e7e4ce64b1b --- /dev/null +++ b/boards/nordic/nrf9160dk/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2019 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF9160DK_NRF9160) + zephyr_library() + zephyr_library_sources(nrf52840_reset.c) +elseif(CONFIG_BOARD_NRF9160DK_NRF52840) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/nordic/nrf9160dk/Kconfig b/boards/nordic/nrf9160dk/Kconfig new file mode 100644 index 00000000000000..92b1b9a892abf8 --- /dev/null +++ b/boards/nordic/nrf9160dk/Kconfig @@ -0,0 +1,23 @@ +# nRF9160 DK NRF52840 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9160DK + # The GPIO driver is required by this board's initialization code + # (board.c), so it is forced here to be enabled always, not only + # enabled by default (in defconfig). + select GPIO if BOARD_NRF9160DK_NRF52840 + +if BOARD_NRF9160DK_NRF52840 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +module = BOARD_NRF9160DK +module-str = Board Control +source "subsys/logging/Kconfig.template.log_config" + +endif # BOARD_NRF9160DK_NRF52840 diff --git a/boards/nordic/nrf9160dk/Kconfig.defconfig b/boards/nordic/nrf9160dk/Kconfig.defconfig new file mode 100644 index 00000000000000..11880ae2a131a1 --- /dev/null +++ b/boards/nordic/nrf9160dk/Kconfig.defconfig @@ -0,0 +1,54 @@ +# nRF9160 DK NRF9160 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9160DK_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9160DK_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9160DK_NRF9160_NS + +config BT_HCI_VS + default y if BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,nrf52840_reset) + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) + +endif # BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS + +if BOARD_NRF9160DK_NRF52840 + +config BT_CTLR + default BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,reset_input) + +endif # BOARD_NRF9160DK_NRF52840 diff --git a/boards/nordic/nrf9160dk/Kconfig.nrf9160dk b/boards/nordic/nrf9160dk/Kconfig.nrf9160dk new file mode 100644 index 00000000000000..c4c42657c37fb4 --- /dev/null +++ b/boards/nordic/nrf9160dk/Kconfig.nrf9160dk @@ -0,0 +1,8 @@ +# nRF9160 DK NRF9160 board configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9160DK + select SOC_NRF9160_SICA if BOARD_NRF9160DK_NRF9160 || BOARD_NRF9160DK_NRF9160_NS + select SOC_NRF52840_QIAA if BOARD_NRF9160DK_NRF52840 diff --git a/boards/arm/nrf9160dk_nrf52840/board.c b/boards/nordic/nrf9160dk/board.c similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/board.c rename to boards/nordic/nrf9160dk/board.c diff --git a/boards/nordic/nrf9160dk/board.cmake b/boards/nordic/nrf9160dk/board.cmake new file mode 100644 index 00000000000000..8bb0e6881830a8 --- /dev/null +++ b/boards/nordic/nrf9160dk/board.cmake @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_NRF9160DK_NRF9160 OR CONFIG_BOARD_NRF9160DK_NRF9160_NS) + if(CONFIG_BOARD_NRF9160DK_NRF9160_NS) + set(TFM_PUBLIC_KEY_FORMAT "full") + endif() + + if(CONFIG_TFM_FLASH_MERGED_BINARY) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) + endif() + + board_runner_args(jlink "--device=nRF9160_xxAA" "--speed=4000") + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +elseif(CONFIG_BOARD_NRF9160DK_NRF52840) + board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") + include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) + include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) +endif() diff --git a/boards/nordic/nrf9160dk/board.yml b/boards/nordic/nrf9160dk/board.yml new file mode 100644 index 00000000000000..5e6dcfad89b3cf --- /dev/null +++ b/boards/nordic/nrf9160dk/board.yml @@ -0,0 +1,14 @@ +board: + name: nrf9160dk + vendor: nordic + socs: + - name: nrf9160 + variants: + - name: 'ns' + - name: nrf52840 + revision: + format: major.minor.patch + default: "0.14.0" + revisions: + - name: "0.7.0" + - name: "0.14.0" diff --git a/boards/arm/nrf9160dk_nrf9160/doc/img/nrf9160dk_nrf9160.jpg b/boards/nordic/nrf9160dk/doc/img/nrf9160dk_nrf9160.jpg similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/doc/img/nrf9160dk_nrf9160.jpg rename to boards/nordic/nrf9160dk/doc/img/nrf9160dk_nrf9160.jpg diff --git a/boards/nordic/nrf9160dk/doc/index.rst b/boards/nordic/nrf9160dk/doc/index.rst new file mode 100644 index 00000000000000..0e8a3171a223d8 --- /dev/null +++ b/boards/nordic/nrf9160dk/doc/index.rst @@ -0,0 +1,531 @@ +.. _nrf9160dk_nrf9160: + +nRF9160 DK +########## + +Overview +******** + +The nRF9160 DK (PCA10090) is a single-board development kit for evaluation and +development on the nRF9160 SiP for LTE-M and NB-IoT. The nrf9160dk/nrf9160 +board configuration provides support for the Nordic Semiconductor nRF9160 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +.. figure:: img/nrf9160dk_nrf9160.jpg + :align: center + :alt: nRF9160 DK + + nRF9160 DK (Credit: Nordic Semiconductor) + +More information about the board can be found at the +`nRF9160 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9160 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The nrf9160dk/nrf9160 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +.. _nrf9160dk_additional_hardware: + +Additional hardware in v0.14.0+ +------------------------------- + +Starting from v0.14.0, additional hardware is available on the DK: + +* External flash memory (MX25R6435F, 64 Mb) +* I/O expander (PCAL6408A) that can be used to interface LEDs, slide switches, + and buttons + +To use this additional hardware, specify the revision of the board that +should be used when building your application (for more information, see +:ref:`application_board_version`). For example, to build for nRF9160 DK v1.0.0: + +.. zephyr-app-commands:: + :tool: all + :cd-into: + :board: nrf9160dk/nrf9160@1.0.0 + :goals: build + :compact: + +Remember to also enable routing for this additional hardware in the firmware for +:ref:`nrf9160dk_nrf52840` (see :ref:`nrf9160dk_board_controller_firmware`). + +Other hardware features have not been enabled yet for this board. +See `nRF9160 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF9160 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.2 +* LED2 (green) = P0.3 +* LED3 (green) = P0.4 +* LED4 (green) = P0.5 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.6 +* BUTTON2 = P0.7 +* SWITCH1 = P0.8 +* SWITCH2 = P0.9 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +nrf9160dk/nrf9160 supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +Applications on the nRF9160 may contain a Secure and a Non-Secure firmware +image. The Secure image can be built using either Zephyr or +`Trusted Firmware M`_ (TF-M). Non-Secure firmware images are always built +using Zephyr. The two alternatives are described below. + +.. note:: + + By default the Secure image for nRF9160 is built using TF-M. + +Building the Secure firmware using Zephyr +----------------------------------------- + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9160dk/nrf9160`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9160dk/nrf9160/ns``. +3. Merge the two binaries together. + +Building the Secure firmware with TF-M +-------------------------------------- + +The process to build the Secure firmware image using TF-M and the Non-Secure +firmware image using Zephyr requires the following action: + +1. Build the Non-Secure Zephyr application + using ``-DBOARD=nrf9160dk_nrf9160_ns``. + To invoke the building of TF-M the Zephyr build system requires the + Kconfig option ``BUILD_WITH_TFM`` to be enabled, which is done by + default when building Zephyr as a Non-Secure application. + The Zephyr build system will perform the following steps automatically: + + * Build the Non-Secure firmware image as a regular Zephyr application + * Build a TF-M (secure) firmware image + * Merge the output binaries together + * Optionally build a bootloader image (MCUboot) + +.. note:: + + Depending on the TF-M configuration, an application DTS overlay may be + required, to adjust the Non-Secure image Flash and SRAM starting address + and sizes. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9160dk/nrf9160``. + + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9160 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9160dk/nrf9160 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9160 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic_nrf/nrf9160dk/nrf9160dk_nrf9160_common.dtsi`. + +.. _nrf9160dk_nrf52840: + +nRF9160 DK - nRF52840 +##################### + +Overview +******** + +The nRF52840 SoC on the nRF9160 DK (PCA10090) hardware provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +The nRF52840 SoC does not have any connection to the any of the LEDs, +buttons, switches, and Arduino pin headers on the nRF9160 DK board. It is, +however, possible to route some of the pins of the nRF52840 SoC to the nRF9160 +SiP. + +More information about the board can be found at +the `Nordic Low power cellular IoT`_ website. +The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +The nRF9160 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The nrf9160dk/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Programming and Debugging +************************* + +Applications for the ``nrf9160dk/nrf52840`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Make sure that the PROG/DEBUG switch on the DK is set to nRF52. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Remember to set the PROG/DEBUG switch on the DK to nRF52. + +See the following example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF52840 SoC is connected +to. Usually, under Linux it will be ``/dev/ttyACM1``. The ``/dev/ttyACM0`` +port is connected to the nRF9160 SiP on the board. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9160dk/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards +with a Segger IC. + +Remember to set the PROG/DEBUG switch on the DK to nRF52. + +.. _nrf9160dk_board_controller_firmware: + +Board controller firmware +************************* + +The board controller firmware is a small snippet of code that takes care of +routing specific pins of the nRF9160 SiP to different components on the DK, +such as LEDs and buttons, UART interfaces (VCOMx) of the interface MCU, and +specific nRF52840 SoC pins. + +.. note:: + In nRF9160 DK revisions earlier than v0.14.0, nRF9160 signals routed to + other components on the DK are not simultaneously available on the DK + connectors. + +When compiling a project for nrf9160dk/nrf52840, the board controller firmware +will be compiled and run automatically after the Kernel has been initialized. + +By default, the board controller firmware will route the following: + ++--------------------------------+----------------------------------+ +| nRF9160 pins | Routed to | ++================================+==================================+ +| P0.26, P0.27, P0.28, and P0.29 | VCOM0 | ++--------------------------------+----------------------------------+ +| P0.01, P0.00, P0.15, and P0.14 | VCOM2 | ++--------------------------------+----------------------------------+ +| P0.02 | LED1 | ++--------------------------------+----------------------------------+ +| P0.03 | LED2 | ++--------------------------------+----------------------------------+ +| P0.04 | LED3 | ++--------------------------------+----------------------------------+ +| P0.05 | LED4 | ++--------------------------------+----------------------------------+ +| P0.08 | Switch 1 | ++--------------------------------+----------------------------------+ +| P0.09 | Switch 2 | ++--------------------------------+----------------------------------+ +| P0.06 | Button 1 | ++--------------------------------+----------------------------------+ +| P0.07 | Button 2 | ++--------------------------------+----------------------------------+ +| P0.17, P0.18, and P0.19 | Arduino pin headers | ++--------------------------------+----------------------------------+ +| P0.21, P0.22, and P0.23 | Trace interface | ++--------------------------------+----------------------------------+ +| COEX0, COEX1, and COEX2 | COEX interface | ++--------------------------------+----------------------------------+ + +For a complete list of all the routing options available, +see the `nRF9160 DK board control section in the nRF9160 DK User Guide`_. + +If you want to route some of the above pins differently or enable any of the +other available routing options, enable or disable the devicetree node that +represents the analog switch that provides the given routing. + +The following devicetree nodes are defined for the analog switches present +on the nRF9160 DK: + ++------------------------------------+------------------------------+ +| Devicetree node label | Analog switch name | ++====================================+==============================+ +| ``vcom0_pins_routing`` | nRF91_UART1 (nRF91_APP1) | ++------------------------------------+------------------------------+ +| ``vcom2_pins_routing`` | nRF91_UART2 (nRF91_APP2) | ++------------------------------------+------------------------------+ +| ``led1_pin_routing`` | nRF91_LED1 | ++------------------------------------+------------------------------+ +| ``led2_pin_routing`` | nRF91_LED2 | ++------------------------------------+------------------------------+ +| ``led3_pin_routing`` | nRF91_LED3 | ++------------------------------------+------------------------------+ +| ``led4_pin_routing`` | nRF91_LED4 | ++------------------------------------+------------------------------+ +| ``switch1_pin_routing`` | nRF91_SWITCH1 | ++------------------------------------+------------------------------+ +| ``switch2_pin_routing`` | nRF91_SWITCH2 | ++------------------------------------+------------------------------+ +| ``button1_pin_routing`` | nRF91_BUTTON1 | ++------------------------------------+------------------------------+ +| ``button2_pin_routing`` | nRF91_BUTTON2 | ++------------------------------------+------------------------------+ +| ``nrf_interface_pins_0_2_routing`` | nRF_IF0-2_CTRL (nRF91_GPIO) | ++------------------------------------+------------------------------+ +| ``nrf_interface_pins_3_5_routing`` | nRF_IF3-5_CTRL (nRF91_TRACE) | ++------------------------------------+------------------------------+ +| ``nrf_interface_pins_6_8_routing`` | nRF_IF6-8_CTRL (nRF91_COEX) | ++------------------------------------+------------------------------+ + +When building for the DK revision 0.14.0 or later, you can use the following +additional nodes (see :ref:`application_board_version` for information how to +build for specific revisions of the board): + ++------------------------------------+------------------------------+ +| Devicetree node label | Analog switch name | ++====================================+==============================+ +| ``nrf_interface_pin_9_routing`` | nRF_IF9_CTRL | ++------------------------------------+------------------------------+ +| ``io_expander_pins_routing`` | IO_EXP_EN | ++------------------------------------+------------------------------+ +| ``external_flash_pins_routing`` | EXT_MEM_CTRL | ++------------------------------------+------------------------------+ + +For example, if you want to enable the optional routing for the nRF9160 pins +P0.17, P0.18, and P0.19 so that they are routed to nRF52840 pins P0.17, P0.20, +and P0.15, respectively, add the following in the devicetree overlay in your +application: + +.. code-block:: devicetree + + &nrf_interface_pins_0_2_routing { + status = "okay"; + }; + +And if you want to, for example, disable routing for the VCOM2 pins, add the +following: + +.. code-block:: devicetree + + &vcom2_pins_routing { + status = "disabled"; + }; + +A few helper .dtsi files are provided in the directories +:zephyr_file:`boards/nordic_nrf/nrf9160dk/dts/nrf52840` and +:zephyr_file:`boards/nordic_nrf/nrf9160dk/dts/nrf9160`. They can serve as examples of +how to configure and use the above routings. You can also include them from +respective devicetree overlay files in your applications to conveniently +configure the signal routing between nRF9160 and nRF52840 on the nRF9160 DK. +For example, to use ``uart1`` on both these chips for communication between +them, add the following line in the overlays for applications on both sides, nRF52840: + +.. code-block:: devicetree + + #include + +nRF9160: + +.. code-block:: devicetree + + #include + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF9160 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9160-DK +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ +.. _Nordic Low power cellular IoT: https://www.nordicsemi.com/Products/Low-power-cellular-IoT +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF9160 DK board control section in the nRF9160 DK User Guide: https://infocenter.nordicsemi.com/topic/ug_nrf91_dk/UG/nrf91_DK/board_controller.html diff --git a/boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml b/boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml rename to boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-interface.yaml diff --git a/boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml b/boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml rename to boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-nrf52840-reset.yaml diff --git a/boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-optional-routing.yaml b/boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-optional-routing.yaml similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/bindings/nordic,nrf9160dk-optional-routing.yaml rename to boards/nordic/nrf9160dk/dts/bindings/nordic,nrf9160dk-optional-routing.yaml diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if5.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if5.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if9.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_nrf52840_reset_on_if9.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_uart1_on_if0_3.dtsi b/boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_uart1_on_if0_3.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/dts/nrf9160dk_uart1_on_if0_3.dtsi rename to boards/nordic/nrf9160dk/dts/nrf52840/nrf9160dk_uart1_on_if0_3.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if5.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if5.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if5.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if9.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_nrf52840_reset_on_if9.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_nrf52840_reset_on_if9.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_uart1_on_if0_3.dtsi b/boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_uart1_on_if0_3.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/dts/nrf9160dk_uart1_on_if0_3.dtsi rename to boards/nordic/nrf9160dk/dts/nrf9160/nrf9160dk_uart1_on_if0_3.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/nrf52840_reset.c b/boards/nordic/nrf9160dk/nrf52840_reset.c similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf52840_reset.c rename to boards/nordic/nrf9160dk/nrf52840_reset.c diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840-pinctrl.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf52840-pinctrl.dtsi diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840.dts rename to boards/nordic/nrf9160dk/nrf9160dk_nrf52840.dts diff --git a/boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_0_14_0.overlay b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.overlay similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/nrf9160dk_nrf52840_0_14_0.overlay rename to boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.overlay diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.yaml new file mode 100644 index 00000000000000..2219fa3b3a4c85 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_14_0.yaml @@ -0,0 +1,14 @@ +identifier: nrf9160dk/nrf52840 +name: nRF9160-DK-NRF52840 +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - ble + - netif:openthread + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_7_0.yaml new file mode 100644 index 00000000000000..20b765232869e6 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_0_7_0.yaml @@ -0,0 +1,14 @@ +identifier: nrf9160dk@0.7.0/nrf52840 +name: nRF9160-DK-NRF52840 +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb +supported: + - ble + - netif:openthread + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_defconfig b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_defconfig new file mode 100644 index 00000000000000..cfe82dd26781c5 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf52840_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160.dts similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160.dts rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160.dts diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_0_14_0.overlay b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.overlay similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_0_14_0.overlay rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.overlay diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml new file mode 100644 index 00000000000000..71e5bc2d0b3988 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9160dk/nrf9160 +name: nRF9160-DK-NRF9160 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml new file mode 100644 index 00000000000000..d66078fde8bb59 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9160dk@0.7.0/nrf9160 +name: nRF9160-DK-NRF9160 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common-pinctrl.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common-pinctrl.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common-pinctrl.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common_0_14_0.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_common_0_14_0.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_common_0_14_0.dtsi diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_defconfig b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.dts b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns.dts rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns.dts diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_0_14_0.overlay b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.overlay similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_ns_0_14_0.overlay rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.overlay diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml new file mode 100644 index 00000000000000..d610095afafe9d --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml @@ -0,0 +1,21 @@ +identifier: nrf9160dk/nrf9160/ns +name: nRF9160-DK-NRF9160-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml new file mode 100644 index 00000000000000..1957bc3ad259ba --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml @@ -0,0 +1,21 @@ +identifier: nrf9160dk@0.7.0/nrf9160/ns +name: nRF9160-DK-NRF9160-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem + - gpio +vendor: nordic diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_defconfig b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..624f98b1da390c --- /dev/null +++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable uart driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_partition_conf.dtsi b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/nrf9160dk_nrf9160_partition_conf.dtsi rename to boards/nordic/nrf9160dk/nrf9160dk_nrf9160_partition_conf.dtsi diff --git a/boards/arm/nrf52_blenano2/pre_dt_board.cmake b/boards/nordic/nrf9160dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_blenano2/pre_dt_board.cmake rename to boards/nordic/nrf9160dk/pre_dt_board.cmake diff --git a/boards/nordic/nrf9161dk/Kconfig.defconfig b/boards/nordic/nrf9161dk/Kconfig.defconfig new file mode 100644 index 00000000000000..3790d580a2953f --- /dev/null +++ b/boards/nordic/nrf9161dk/Kconfig.defconfig @@ -0,0 +1,44 @@ +# nRF9161 DK NRF9161 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_NRF9161DK_NRF9161 && TRUSTED_EXECUTION_SECURE + +if BOARD_NRF9161DK_NRF9161_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_NRF9161DK_NRF9161_NS + +config BT_HCI_VS + default y if BT + +config BT_WAIT_NOP + default BT && $(dt_nodelabel_enabled,nrf5340_reset) + +config I2C + default $(dt_compat_on_bus,$(DT_COMPAT_NXP_PCAL6408A),i2c) + +endif # BOARD_NRF9161DK_NRF9161 || BOARD_NRF9161DK_NRF9161_NS diff --git a/boards/nordic/nrf9161dk/Kconfig.nrf9161dk b/boards/nordic/nrf9161dk/Kconfig.nrf9161dk new file mode 100644 index 00000000000000..ff03a9d421f723 --- /dev/null +++ b/boards/nordic/nrf9161dk/Kconfig.nrf9161dk @@ -0,0 +1,7 @@ +# nRF9161 DK NRF9161 board configuration + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF9161DK + select SOC_NRF9161_LACA diff --git a/boards/arm/nrf9161dk_nrf9161/board.cmake b/boards/nordic/nrf9161dk/board.cmake similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/board.cmake rename to boards/nordic/nrf9161dk/board.cmake diff --git a/boards/nordic/nrf9161dk/board.yml b/boards/nordic/nrf9161dk/board.yml new file mode 100644 index 00000000000000..9bffcec81a6fc2 --- /dev/null +++ b/boards/nordic/nrf9161dk/board.yml @@ -0,0 +1,13 @@ +board: + name: nrf9161dk + vendor: nordic + socs: + - name: nrf9161 + variants: + - name: 'ns' + revision: + format: major.minor.patch + default: "0.9.0" + revisions: + - name: "0.7.0" + - name: "0.9.0" diff --git a/boards/nordic/nrf9161dk/doc/index.rst b/boards/nordic/nrf9161dk/doc/index.rst new file mode 100644 index 00000000000000..8b3a7fb0236820 --- /dev/null +++ b/boards/nordic/nrf9161dk/doc/index.rst @@ -0,0 +1,203 @@ +.. _nrf9161dk_nrf9161: + +nRF9161 DK +########## + +Overview +******** + +The nRF9161 DK (PCA10153) is a single-board development kit for evaluation and +development on the nRF9161 SiP for DECT NR+ and LTE-M/NB-IoT with GNSS. The ``nrf9161dk/nrf9161`` +board configuration provides support for the Nordic Semiconductor nRF9161 ARM +Cortex-M33F CPU with ARMv8-M Security Extension and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9161 DK website`_. The `Nordic Semiconductor Infocenter`_ +contains the processor's information and the datasheet. + + +Hardware +******** + +nRF9161 DK has two external oscillators. The frequency of +the slow clock is 32.768 kHz. The frequency of the main clock +is 32 MHz. + +Supported Features +================== + +The ``nrf9161dk/nrf9161`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| FLASH | external | spi | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIO | external | i2c | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | nRF53 | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + + +.. _nrf9161dk_additional_hardware: + +Other hardware features have not been enabled yet for this board. +See `nRF9161 DK website`_ and `Nordic Semiconductor Infocenter`_ +for a complete list of nRF9161 DK board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.0 +* LED2 (green) = P0.1 +* LED3 (green) = P0.4 +* LED4 (green) = P0.5 + +Push buttons and Switches +------------------------- + +* BUTTON1 = P0.8 +* BUTTON2 = P0.9 +* SWITCH1 = P0.18 +* SWITCH2 = P0.19 +* BOOT = SW5 = boot/reset + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_). The IDAU is implemented + with the System Protection Unit and is used to define secure and non-secure + memory maps. By default, all of the memory space (Flash, SRAM, and + peripheral address space) is defined to be secure accessible only. +- Secure boot. + + +Programming and Debugging +************************* + +``nrf9161dk/nrf9161`` supports the Armv8m Security Extension, and by default boots +in the Secure state. + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +============================================================================= + +The process requires the following steps: + +1. Build the Secure Zephyr application using ``-DBOARD=nrf9161dk/nrf9161`` and + ``CONFIG_TRUSTED_EXECUTION_SECURE=y`` in the application project configuration file. +2. Build the Non-Secure Zephyr application using ``-DBOARD=nrf9161dk/nrf9161/ns``. +3. Merge the two binaries together. + +When building a Secure/Non-Secure application, the Secure application will +have to set the IDAU (SPU) configuration to allow Non-Secure access to all +CPU resources utilized by the Non-Secure application firmware. SPU +configuration shall take place before jumping to the Non-Secure application. + +Building a Secure only application +================================== + +Build the Zephyr app in the usual way (see :ref:`build_an_application` +and :ref:`application_run`), using ``-DBOARD=nrf9161dk/nrf9161``. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the nRF9161 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf9161dk/nrf9161 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF9161 DK +********************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi`. + +References +********** + +.. target-notes:: + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _nRF9161 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF9161-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Trusted Firmware M: https://www.trustedfirmware.org/projects/tf-m/ diff --git a/boards/arm/nrf9161dk_nrf9161/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml b/boards/nordic/nrf9161dk/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml rename to boards/nordic/nrf9161dk/dts/bindings/nordic,nrf9161dk-nrf5340-reset.yaml diff --git a/boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_buttons_on_io_expander.dtsi b/boards/nordic/nrf9161dk/dts/nrf9161dk_buttons_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_buttons_on_io_expander.dtsi rename to boards/nordic/nrf9161dk/dts/nrf9161dk_buttons_on_io_expander.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_leds_on_io_expander.dtsi b/boards/nordic/nrf9161dk/dts/nrf9161dk_leds_on_io_expander.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/dts/nrf9161dk_leds_on_io_expander.dtsi rename to boards/nordic/nrf9161dk/dts/nrf9161dk_leds_on_io_expander.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.dts b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161.dts similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161.dts rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161.dts diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_0_7_0.overlay b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.overlay similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_0_7_0.overlay rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.overlay diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml new file mode 100644 index 00000000000000..47842c49d46d87 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9161dk@0.7.0/nrf9161 +name: nRF9161-DK-NRF9161 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml new file mode 100644 index 00000000000000..55e021d3f681f7 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml @@ -0,0 +1,22 @@ +identifier: nrf9161dk/nrf9161 +name: nRF9161-DK-NRF9161 +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 88 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - gpio + - i2c + - pwm + - spi + - watchdog + - counter +vendor: nordic diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common-pinctrl.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common-pinctrl.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common-pinctrl.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common.dtsi diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common_0_7_0.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_common_0_7_0.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_common_0_7_0.dtsi diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_defconfig b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.dts b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns.dts rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns.dts diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_0_7_0.overlay b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.overlay similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_ns_0_7_0.overlay rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.overlay diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml new file mode 100644 index 00000000000000..fd95098a773452 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml @@ -0,0 +1,20 @@ +identifier: nrf9161dk@0.7.0/nrf9161/ns +name: nRF9161-DK-NRF9161-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem +vendor: nordic diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml new file mode 100644 index 00000000000000..13cf209bc2d067 --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml @@ -0,0 +1,20 @@ +identifier: nrf9161dk/nrf9161/ns +name: nRF9161-DK-NRF9161-Non-Secure +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 128 +flash: 192 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - i2c + - pwm + - watchdog + - netif:modem +vendor: nordic diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_defconfig b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_defconfig new file mode 100644 index 00000000000000..2a74dd56f4144a --- /dev/null +++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_partition_conf.dtsi b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_partition_conf.dtsi similarity index 100% rename from boards/arm/nrf9161dk_nrf9161/nrf9161dk_nrf9161_partition_conf.dtsi rename to boards/nordic/nrf9161dk/nrf9161dk_nrf9161_partition_conf.dtsi diff --git a/boards/arm/nrf9160dk_nrf9160/pre_dt_board.cmake b/boards/nordic/nrf9161dk/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160dk_nrf9160/pre_dt_board.cmake rename to boards/nordic/nrf9161dk/pre_dt_board.cmake diff --git a/boards/nordic/thingy52/CMakeLists.txt b/boards/nordic/thingy52/CMakeLists.txt new file mode 100644 index 00000000000000..94f5692b56a482 --- /dev/null +++ b/boards/nordic/thingy52/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_CCS811) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/nordic/thingy52/Kconfig b/boards/nordic/thingy52/Kconfig new file mode 100644 index 00000000000000..e9629096e28229 --- /dev/null +++ b/boards/nordic/thingy52/Kconfig @@ -0,0 +1,17 @@ +# Thingy52 NRF52832 board configuration + +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_THINGY52 + +config BOARD_CCS_VDD_PWR_CTRL_INIT_PRIORITY + int "CCS_VDD power rail init priority" + default 85 + depends on GPIO_SX1509B + help + Initialization priority for the CCS_VDD power rail. This powers the + CCS811 gas sensor. The value has to be greater than + BOARD_VDD_PWR_CTRL_INIT_PRIORITY, but smaller than SENSOR_INIT_PRIORITY. + +endif # BOARD_THINGY52 diff --git a/boards/nordic/thingy52/Kconfig.defconfig b/boards/nordic/thingy52/Kconfig.defconfig new file mode 100644 index 00000000000000..40bdd8c6cdf43e --- /dev/null +++ b/boards/nordic/thingy52/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Thingy52 NRF52832 board configuration + +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_THINGY52 + +config BT_CTLR + default BT + +endif # BOARD_THINGY52 diff --git a/boards/nordic/thingy52/Kconfig.thingy52 b/boards/nordic/thingy52/Kconfig.thingy52 new file mode 100644 index 00000000000000..433eb4a2a956cf --- /dev/null +++ b/boards/nordic/thingy52/Kconfig.thingy52 @@ -0,0 +1,7 @@ +# Thingy52 NRF52832 board configuration + +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_THINGY52 + select SOC_NRF52832_QFAA diff --git a/boards/arm/thingy52_nrf52832/board.c b/boards/nordic/thingy52/board.c similarity index 100% rename from boards/arm/thingy52_nrf52832/board.c rename to boards/nordic/thingy52/board.c diff --git a/boards/arm/thingy52_nrf52832/board.cmake b/boards/nordic/thingy52/board.cmake similarity index 100% rename from boards/arm/thingy52_nrf52832/board.cmake rename to boards/nordic/thingy52/board.cmake diff --git a/boards/nordic/thingy52/board.yml b/boards/nordic/thingy52/board.yml new file mode 100644 index 00000000000000..425e24fb5960a1 --- /dev/null +++ b/boards/nordic/thingy52/board.yml @@ -0,0 +1,5 @@ +board: + name: thingy52 + vendor: nordic + socs: + - name: nrf52832 diff --git a/boards/arm/thingy52_nrf52832/doc/img/thingy52_nrf52832.jpg b/boards/nordic/thingy52/doc/img/thingy52_nrf52832.jpg similarity index 100% rename from boards/arm/thingy52_nrf52832/doc/img/thingy52_nrf52832.jpg rename to boards/nordic/thingy52/doc/img/thingy52_nrf52832.jpg diff --git a/boards/nordic/thingy52/doc/index.rst b/boards/nordic/thingy52/doc/index.rst new file mode 100644 index 00000000000000..0dd8b6067b6083 --- /dev/null +++ b/boards/nordic/thingy52/doc/index.rst @@ -0,0 +1,388 @@ +.. _thingy52_nrf52832: + +Thingy:52 +######### + +Overview +******** + +Zephyr uses the thingy52/nrf52832 (PCA20020) board configuration for building +for the Thingy:52 board. The board has the nRF52832 MCU with ARM Cortex-M4F +processor, a set of environmental sensors, a pushbutton, and two RGB LEDs. + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* Gas sensor +* :abbr:`GPIO (General Purpose Input Output)` +* GPIO Expander +* Humidity and temperature sensor +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* Pressure sensor +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* RGB LEDs +* :abbr:`RTC (nRF RTC System Clock)` +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/thingy52_nrf52832.jpg + :align: center + :alt: nRF52 Thingy:52 + + nRF52 Thingy:52 (Credit: Nordic Semiconductor) + +More information about the board can be found at the `nRF52 DK website`_. The +`Nordic Semiconductor Infocenter`_ contains the processor's information and the +datasheet. + + +Hardware +******** + +Thingy:52 has the following features: + +* Two RGB LEDs +* CO2 and TVOC sensor +* Humidity and temperature sensor +* Color sensor +* I2C GPIO expander +* Provisions for a pin header and I2C and serial connectors +* Bluetooth radio + +Supported Features +================== + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| Gas | on-board | ccs811 | +| Sensor | | | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| GPIO Exp | on-board | sx1509b | ++-----------+------------+----------------------+ +| Humidity | on-board | hts221 | +| and Temp | | | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| Pressure | on-board | lps22hb_press | +| and Temp | | | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +Lightwell RGB LED +----------------- +The LED is driven by the SX1509B GPIO expander chip (device name GPIO_P0). + ++-------------------+-------------+ +| GPIO Expander Pin | LED Channel | ++===================+=============+ +| 5 | Green | ++-------------------+-------------+ +| 6 | Blue | ++-------------------+-------------+ +| 7 | Red | ++-------------------+-------------+ + +Button +------ + +Thingy:52 has a pushbutton, connected to the P0.11 SOC GPIO pin. + +Serial +------ + +By default the system UART has the following pin configuration: + ++---------+--------+ +| SOC Pin | Signal | ++=========+========+ +| P0.02 | TX | ++---------+--------+ +| P0.03 | RX | ++---------+--------+ + +The pins can be found on the P4 and P6 connectors. The system UART console +uses these pins by default. + +Internal I2C Bus +---------------- + +The internal I2C bus (I2C_0) is not routed to any of the external connectors, +but most of the on-board devices are accessed through it. The following pins +have been assigned to the bus: + ++---------+---------+ +| SOC Pin | Signal | ++=========+=========+ +| P0.07 | SDA | ++---------+---------+ +| P0.08 | SCL | ++---------+---------+ + +The following devices are attached to the bus. + ++----------+---------+ +| Device | Address | ++==========+=========+ +| SX1509B | 0x3e | ++----------+---------+ +| LPS22HB | 0x5c | ++----------+---------+ +| HTS221 | 0x5f | ++----------+---------+ +| CCS811 | 0x5a | ++----------+---------+ + +External I2C Bus +---------------- + +The external I2C bus (I2C_1) can be found on the P4 header and the P5 and P7 +connectors. + ++---------+---------+ +| SOC Pin | Signal | ++=========+=========+ +| P0.14 | SDA_EXT | ++---------+---------+ +| P0.15 | SCL_EXT | ++---------+---------+ + +Pin Header +---------- + +This is the pinout of the P4 pin header. Some of the SOC GPIO pins and I2C GPIO +expander pins are accessible through it. It also allows attaching external +devices to the four on-board N-channel MOSFET transistors. + ++-----+---------------+-----------------------+ +| Pin | Device | Signal / Device Pin | ++=====+===============+=======================+ +| 1 | SOC | SCL_EXT / P0.15 | ++-----+---------------+-----------------------+ +| 2 | SOC | SDA_EXT / P0.14 | ++-----+---------------+-----------------------+ +| 3 | SOC | ANA/DIG0 / P0.02 | ++-----+---------------+-----------------------+ +| 4 | SOC | ANA/DIG1 / P0.03 | ++-----+---------------+-----------------------+ +| 5 | SOC | ANA/DIG2 / P0.04 | ++-----+---------------+-----------------------+ +| 6 | | GND | ++-----+---------------+-----------------------+ +| 7 | GPIO Expander | Pin 0 | ++-----+---------------+-----------------------+ +| 8 | GPIO Expander | Pin 1 | ++-----+---------------+-----------------------+ +| 9 | GPIO Expander | Pin 2 | ++-----+---------------+-----------------------+ +| 10 | GPIO Expander | Pin 3 | ++-----+---------------+-----------------------+ +| 11 | MOSFET 1 | Drain | ++-----+---------------+-----------------------+ +| 12 | MOSFET 1 | Source | ++-----+---------------+-----------------------+ +| 13 | MOSFET 2 | Drain | ++-----+---------------+-----------------------+ +| 14 | MOSFET 2 | Source | ++-----+---------------+-----------------------+ +| 15 | MOSFET 3 | Drain | ++-----+---------------+-----------------------+ +| 16 | MOSFET 3 | Source | ++-----+---------------+-----------------------+ +| 17 | MOSFET 4 | Drain | ++-----+---------------+-----------------------+ +| 18 | MOSFET 4 | Source | ++-----+---------------+-----------------------+ +| 19 | | VDD | ++-----+---------------+-----------------------+ +| 20 | | GND | ++-----+---------------+-----------------------+ + +MOSFETs +~~~~~~~ + +The MOSFETs are attached to the following SOC GPIO pins: + ++----------+----------+ +| Device | Gate Pin | ++==========+==========+ +| MOSFET 1 | P0.18 | ++----------+----------+ +| MOSFET 2 | P0.19 | ++----------+----------+ +| MOSFET 3 | P0.20 | ++----------+----------+ +| MOSFET 4 | P0.21 | ++----------+----------+ + +Power Rails +----------- + +Thing:52 has multiple power rails. The necessary rails for the currently +supported devices are listed here. + ++---------+--------------+----------------------+ +| Name | Derived from | Controlled by | ++=========+==============+======================+ +| VREG | The battery | Always on | ++---------+--------------+----------------------+ +| VDD_nRF | VREG | Always on | ++---------+--------------+----------------------+ +| VDD | VREG | SOC pin P0.30 | ++---------+--------------+----------------------+ +| VDD_CCS | VDD | GPIO expander pin 10 | ++---------+--------------+----------------------+ + +Due to the dependencies of the power rails, multiple rails may need to be +powered for a given device to turn on. The correct order of powering up the +rails is the order of the rails down the dependency chain. For example, in order +to power the CCS811 gas sensor, VDD has to be turned on first and VDD_CCS after +it. Here's a list of the devices and their power rails: + ++----------+---------+ +| Device | Rail | ++==========+=========+ +| nRF52832 | VDD_nRF | ++----------+---------+ +| SX1509B | VDD | ++----------+---------+ +| LPS22HB | VDD | ++----------+---------+ +| HTS221 | VDD | ++----------+---------+ +| CCS811 | VDD_CCS | ++----------+---------+ + +Sensors +------- + ++----------+---------------------------------+-------+-------------+------------+ +| Device | Function | Bus | I2C Address | Power Rail | ++==========+=================================+=======+=============+============+ +| LPS22HB | Pressure and Temperature sensor | I2C_0 | 0x5c | VDD | ++----------+---------------------------------+-------+-------------+------------+ +| HTS221 | Humidity and Temperature sensor | I2C_0 | 0x5f | VDD | ++----------+---------------------------------+-------+-------------+------------+ +| CCS811 | Gas sensor | I2C_0 | 0x5a | VDD_CCS | ++----------+---------------------------------+-------+-------------+------------+ + +Misc. Device Pins +----------------- + +SX1509B +~~~~~~~ + ++---------------+-------------------+ +| Device Signal | SOC Pin | ++===============+===================+ +| SX_OSCIO | P0.05 | ++---------------+-------------------+ +| SX_RESET | P0.16 | ++---------------+-------------------+ + +LPS22HB +~~~~~~~ + ++---------------+-------------------+ +| Sensor Signal | SOC Pin | ++===============+===================+ +| LPS_INT | P0.23 | ++---------------+-------------------+ + +HTS221 +~~~~~~ + ++---------------+-------------------+ +| Sensor Signal | SOC Pin | ++===============+===================+ +| HTS_INT | P0.24 | ++---------------+-------------------+ + +CCS811 +~~~~~~ + ++---------------+-------------------+ +| Sensor Signal | GPIO Expander Pin | ++===============+===================+ +| CCS_RESET | 11 | ++---------------+-------------------+ +| CCS_WAKE | 12 | ++---------------+-------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Zephyr onto Thingy:52 requires an external J-Link programmer. The +programmer is attached to the P9 programming header. + + +Debugging +========= + +Thingy:52 does not have an on-board J-Link debug IC as some other nRF5 +development boards, however, instructions from the :ref:`nordic_segger` page +also apply to this board, with the additional step of connecting an external +debugger. A development board with a Debug out connector such as the +:ref:`nrf52dk_nrf52832` can be used as a debugger with Thingy:52. + +Testing board features +********************** + +The green lightwell LED can be tested with the :zephyr:code-sample:`blinky` example. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: thingy52/nrf52832 + :goals: build flash + + + +Also the temperature and humidity sensor can be tested with the :ref:`hts221` +sample. + +.. zephyr-app-commands:: + :zephyr-app: samples/sensor/hts221 + :board: thingy52/nrf52832 + :goals: build flash + +References +********** + +.. target-notes:: + +.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/Nordic-Thingy-52 +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/nrf52_sparkfun/pre_dt_board.cmake b/boards/nordic/thingy52/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_sparkfun/pre_dt_board.cmake rename to boards/nordic/thingy52/pre_dt_board.cmake diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832-pinctrl.dtsi b/boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/thingy52_nrf52832/thingy52_nrf52832-pinctrl.dtsi rename to boards/nordic/thingy52/thingy52_nrf52832-pinctrl.dtsi diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832.dts b/boards/nordic/thingy52/thingy52_nrf52832.dts similarity index 100% rename from boards/arm/thingy52_nrf52832/thingy52_nrf52832.dts rename to boards/nordic/thingy52/thingy52_nrf52832.dts diff --git a/boards/arm/thingy52_nrf52832/thingy52_nrf52832.yaml b/boards/nordic/thingy52/thingy52_nrf52832.yaml similarity index 84% rename from boards/arm/thingy52_nrf52832/thingy52_nrf52832.yaml rename to boards/nordic/thingy52/thingy52_nrf52832.yaml index c4aa66f67ceefe..a49aeaba6ce45b 100644 --- a/boards/arm/thingy52_nrf52832/thingy52_nrf52832.yaml +++ b/boards/nordic/thingy52/thingy52_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: thingy52_nrf52832 +identifier: thingy52/nrf52832 name: Thingy52-NRF52832 type: mcu arch: arm diff --git a/boards/nordic/thingy52/thingy52_nrf52832_defconfig b/boards/nordic/thingy52/thingy52_nrf52832_defconfig new file mode 100644 index 00000000000000..401a71ab47a5bc --- /dev/null +++ b/boards/nordic/thingy52/thingy52_nrf52832_defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2018 Aapo Vienamo +# SPDX-License-Identifier: Apache-2.0 + +# Enable regulators +CONFIG_REGULATOR=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# Enable regulators (init priority adjusted so that they +# are turned before I2C GPIO expander) +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_INIT_PRIORITY=45 + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nordic/thingy53/CMakeLists.txt b/boards/nordic/thingy53/CMakeLists.txt new file mode 100644 index 00000000000000..4cf3ec75526c49 --- /dev/null +++ b/boards/nordic/thingy53/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) + zephyr_library() + zephyr_library_sources(board.c) +endif() diff --git a/boards/nordic/thingy53/Kconfig b/boards/nordic/thingy53/Kconfig new file mode 100644 index 00000000000000..d7be16ff007a39 --- /dev/null +++ b/boards/nordic/thingy53/Kconfig @@ -0,0 +1,74 @@ +# Thingy53 NRF5340 board configuration + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config THINGY53_INIT_PRIORITY + int "Init priority" + default 79 + help + Initialization priority of the Thingy:53. + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_SERIAL_BACKEND_CDC_ACM + bool "USB CDC" + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "thingy53/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +if BOARD_THINGY53_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "thingy53/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/nordic/thingy53/Kconfig.defconfig b/boards/nordic/thingy53/Kconfig.defconfig new file mode 100644 index 00000000000000..701bd9be4e6fae --- /dev/null +++ b/boards/nordic/thingy53/Kconfig.defconfig @@ -0,0 +1,146 @@ +# Thingy53 NRF5340 board configuration + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_THINGY53_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_THINGY53_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_THINGY53_NRF5340_CPUAPP_NS + +if !TRUSTED_EXECUTION_SECURE + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +config BT_HAS_HCI_VS + default BT + +config USB_NRFX_ATTACHED_EVENT_DELAY + default 700 if USB_DEVICE_DRIVER + +config I2C + default y + +config SPI + default y + +config REGULATOR + default y + +endif # !TRUSTED_EXECUTION_SECURE + +if BOARD_SERIAL_BACKEND_CDC_ACM + +config USB_DEVICE_PRODUCT + default "Thingy:53 Application" + +config USB_DEVICE_VID + default 0x1915 + +config USB_DEVICE_PID + default 0x530C + +config USB_DEVICE_STACK + default y + +config USB_CDC_ACM + default y + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y if !MCUBOOT + +config SHELL_BACKEND_SERIAL_CHECK_DTR + default SHELL + depends on UART_LINE_CTRL + +config UART_LINE_CTRL + default SHELL + +config USB_DEVICE_REMOTE_WAKEUP + default n + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +# Set USB log level to error only +choice USB_DEVICE_LOG_LEVEL_CHOICE + default USB_DEVICE_LOG_LEVEL_ERR +endchoice + +# Wait 4000ms at startup for logging +config LOG_PROCESS_THREAD_STARTUP_DELAY_MS + default 4000 + +endif # LOG + +endif # BOARD_SERIAL_BACKEND_CDC_ACM + +endif # BOARD_THINGY53_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP_NS + +if BOARD_THINGY53_NRF5340_CPUNET + +config BT_CTLR + default BT + +config BT_ECC + default BT + +endif # BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/nordic/thingy53/Kconfig.thingy53 b/boards/nordic/thingy53/Kconfig.thingy53 new file mode 100644 index 00000000000000..e7b23191373124 --- /dev/null +++ b/boards/nordic/thingy53/Kconfig.thingy53 @@ -0,0 +1,9 @@ +# Thingy53 NRF5340 board configuration + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_THINGY53 + select SOC_NRF5340_CPUAPP_QKAA if BOARD_THINGY53_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_THINGY53_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_THINGY53_NRF5340_CPUNET diff --git a/boards/arm/thingy53_nrf5340/board.c b/boards/nordic/thingy53/board.c similarity index 100% rename from boards/arm/thingy53_nrf5340/board.c rename to boards/nordic/thingy53/board.c diff --git a/boards/nordic/thingy53/board.cmake b/boards/nordic/thingy53/board.cmake new file mode 100644 index 00000000000000..dc63ca31895096 --- /dev/null +++ b/boards/nordic/thingy53/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_THINGY53_NRF5340_CPUAPP OR CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(CONFIG_BOARD_THINGY53_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nordic/thingy53/board.yml b/boards/nordic/thingy53/board.yml new file mode 100644 index 00000000000000..4659222a346db0 --- /dev/null +++ b/boards/nordic/thingy53/board.yml @@ -0,0 +1,8 @@ +board: + name: thingy53 + vendor: nordic + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/nordic/thingy53/doc/index.rst b/boards/nordic/thingy53/doc/index.rst new file mode 100644 index 00000000000000..e2f8b000f17ab0 --- /dev/null +++ b/boards/nordic/thingy53/doc/index.rst @@ -0,0 +1,51 @@ +.. _thingy53_nrf5340: + +Thingy:53 +######### + +Overview +******** + +Zephyr uses the ``thingy53/nrf5340`` board configuration for building +for the Thingy:53 board. The board has the nRF5340 MCU processor, a set of +environmental sensors, a pushbutton, and RGB LED. + +The nRF5340 is a dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running at + a fixed 64 MHz, referred to as the **network core**. + +The ``thingy53/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``thingy53/nrf5340/cpunet`` build target provides +support for the network core on the nRF5340 SoC. + +The `Nordic Semiconductor Infocenter`_ contains the processor's information and +the datasheet. + +Programming and Debugging +************************* + +Flashing +======== + +Flashing Zephyr onto Thingy:53 requires an external J-Link programmer. The +programmer is attached to the P9 programming header. + +Debugging +========= + +Thingy:53 does not have an on-board J-Link debug IC as some other nRF5 +development boards, however, instructions from the :ref:`nordic_segger` page +also apply to this board, with the additional step of connecting an external +debugger. A development board with a Debug out connector such as the +:ref:`nrf5340dk_nrf5340` can be used as a debugger with Thingy:53. + +References +********** + +.. target-notes:: + +.. _Nordic Semiconductor Infocenter: http://infocenter.nordicsemi.com/ diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/pre_dt_board.cmake b/boards/nordic/thingy53/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/pre_dt_board.cmake rename to boards/nordic/thingy53/pre_dt_board.cmake diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_common-pinctrl.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_common-pinctrl.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_common.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_common.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_common.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.dts rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp.dts diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml similarity index 86% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.yaml rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml index b4651427a220eb..fbc4eb335798a1 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: thingy53_nrf5340_cpuapp +identifier: thingy53/nrf5340/cpuapp name: Thingy53-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_defconfig b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_defconfig similarity index 82% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_defconfig rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_defconfig index 5f3fd735660e0a..de1c1fd596431a 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_defconfig +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_THINGY53_NRF5340_CPUAPP=y - # Enable MPU CONFIG_ARM_MPU=y @@ -20,7 +16,7 @@ CONFIG_GPIO=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable uart driver +# Enable UART driver CONFIG_SERIAL=y # Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.dts rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml similarity index 86% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.yaml rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml index d8db4ae152030d..b534406ea0760b 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: thingy53_nrf5340_cpuapp_ns +identifier: thingy53/nrf5340/cpuapp/ns name: Thingy53-NRF5340-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns_defconfig b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns_defconfig similarity index 84% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns_defconfig rename to boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns_defconfig index 23d7e5ff6e0604..39dc91517e0760 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpuapp_ns_defconfig +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF53X=y -CONFIG_SOC_NRF5340_CPUAPP_QKAA=y -CONFIG_BOARD_THINGY53_NRF5340_CPUAPP_NS=y - # Enable MPU CONFIG_ARM_MPU=y @@ -23,7 +19,7 @@ CONFIG_GPIO=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# Enable uart driver +# Enable UART driver CONFIG_SERIAL=y # Board Kconfig.defconfig enables USB CDC ACM and should disable USB remote diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet-pinctrl.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet-pinctrl.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.dts b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.dts rename to boards/nordic/thingy53/thingy53_nrf5340_cpunet.dts diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml similarity index 82% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.yaml rename to boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml index a41d496937f84a..c039c5ad9f445c 100644 --- a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_cpunet.yaml +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml @@ -1,4 +1,4 @@ -identifier: thingy53_nrf5340_cpunet +identifier: thingy53/nrf5340/cpunet name: Thingy53-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet_defconfig b/boards/nordic/thingy53/thingy53_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..c115d16a9d0512 --- /dev/null +++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y diff --git a/boards/arm/rddrone_fmuk66/CMakeLists.txt b/boards/nordic/thingy53/thingy53_nrf5340_defconfig similarity index 100% rename from boards/arm/rddrone_fmuk66/CMakeLists.txt rename to boards/nordic/thingy53/thingy53_nrf5340_defconfig diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_partition_conf.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_partition_conf.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_partition_conf.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_partition_conf.dtsi diff --git a/boards/arm/thingy53_nrf5340/thingy53_nrf5340_shared_sram_planning_conf.dtsi b/boards/nordic/thingy53/thingy53_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/thingy53_nrf5340/thingy53_nrf5340_shared_sram_planning_conf.dtsi rename to boards/nordic/thingy53/thingy53_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/nuvoton/index.rst b/boards/nuvoton/index.rst new file mode 100644 index 00000000000000..eec26543a0bf46 --- /dev/null +++ b/boards/nuvoton/index.rst @@ -0,0 +1,10 @@ +.. _boards-nuvoton: + +Nuvoton Technology Corporation +############################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig b/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..4bd26c0d34858d --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config INPUT + default y if KSCAN diff --git a/boards/nuvoton/npcx4m8f_evb/Kconfig.npcx4m8f_evb b/boards/nuvoton/npcx4m8f_evb/Kconfig.npcx4m8f_evb new file mode 100644 index 00000000000000..4483d2ee0c2b88 --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/Kconfig.npcx4m8f_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCX4M8F_EVB + select SOC_NPCX4M8F diff --git a/boards/arm/npcx4m8f_evb/board.cmake b/boards/nuvoton/npcx4m8f_evb/board.cmake similarity index 100% rename from boards/arm/npcx4m8f_evb/board.cmake rename to boards/nuvoton/npcx4m8f_evb/board.cmake diff --git a/boards/nuvoton/npcx4m8f_evb/board.yml b/boards/nuvoton/npcx4m8f_evb/board.yml new file mode 100644 index 00000000000000..16f6190d195293 --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: npcx4m8f_evb + vendor: nuvoton + socs: + - name: npcx4m8f diff --git a/boards/nuvoton/npcx4m8f_evb/doc/index.rst b/boards/nuvoton/npcx4m8f_evb/doc/index.rst new file mode 100644 index 00000000000000..928c4f2ce8177e --- /dev/null +++ b/boards/nuvoton/npcx4m8f_evb/doc/index.rst @@ -0,0 +1,131 @@ +.. _npcx4m8f_evb: + +Nuvoton NPCX4M8F_EVB +#################### + +Overview +******** + +The NPCX4M8F_EVB kit is a development platform to evaluate the +Nuvoton NPCX4 series microcontrollers. This board needs to be mated with +part number NPCX498F. + +.. image:: npcx4m8f_evb.jpg + :align: center + :alt: NPCX4M8F Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 512 KB RAM and 64 KB boot ROM +- ADC & GPIO headers +- UART0 and UART1 +- FAN PWM interface +- Jtag interface +- Intel Modular Embedded Controller Card (MECC) headers + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port/controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PM | on-chip | power management | ++-----------+------------+-------------------------------------+ +| PSL | on-chip | power switch logic | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pulse width modulator | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer sensor | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig` + + +Connections and IOs +=================== + +Nuvoton to provide the schematic for this board. + +System Clock +============ + +The NPCX4M8F MCU is configured to use the 120Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + +Programming and Debugging +************************* + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG-only sessions. + +Flashing +======== + +If the correct headers are installed, this board supports both J-TAG and also +the ChromiumOS servo. + +To flash using Servo V2, μServo, or Servo V4 (CCD), see the +`Chromium EC Flashing Documentation`_ for more information. + +To flash with J-TAG, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +The openocd from Zephyr SDK 0.16.1 doesn't include npcx4 support, so build openocd from source.:: + + sudo apt-get install libftdi-dev libusb-1.0.0-dev + git clone https://git.code.sf.net/p/openocd/code ~/openocd + cd ~/openocd + ./bootstrap + ./configure --enable-jlink --enable-ftdi + make clean + make + sudo make install + +Build and flash the blinky sample.:: + + west build -t clean && \ + west build -c -p auto -b npcx4m8f_evb samples/basic/blinky && \ + west flash --openocd /usr/local/bin/openocd + +Debugging +========= + +Use JTAG/SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx4m8f_evb/doc/npcx4m8f_evb.jpg b/boards/nuvoton/npcx4m8f_evb/doc/npcx4m8f_evb.jpg similarity index 100% rename from boards/arm/npcx4m8f_evb/doc/npcx4m8f_evb.jpg rename to boards/nuvoton/npcx4m8f_evb/doc/npcx4m8f_evb.jpg diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb-pinctrl.dtsi diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb.dts b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts similarity index 100% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb.dts rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb.yaml b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.yaml similarity index 100% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb.yaml rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.yaml diff --git a/boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig similarity index 88% rename from boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig rename to boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig index 4ec779de482b94..05a91e020f348f 100644 --- a/boards/arm/npcx4m8f_evb/npcx4m8f_evb_defconfig +++ b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_NPCX4M8F=y -CONFIG_SOC_SERIES_NPCX4=y -CONFIG_BOARD_NPCX4M8F_EVB=y - # Enable NPCX firmware header CONFIG_NPCX_HEADER=y CONFIG_NPCX_IMAGE_OUTPUT_HEX=y diff --git a/boards/arm/npcx4m8f_evb/support/openocd.cfg b/boards/nuvoton/npcx4m8f_evb/support/openocd.cfg similarity index 100% rename from boards/arm/npcx4m8f_evb/support/openocd.cfg rename to boards/nuvoton/npcx4m8f_evb/support/openocd.cfg diff --git a/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig b/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..91a81edc3531a2 --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config INPUT + default y if KSCAN diff --git a/boards/nuvoton/npcx7m6fb_evb/Kconfig.npcx7m6fb_evb b/boards/nuvoton/npcx7m6fb_evb/Kconfig.npcx7m6fb_evb new file mode 100644 index 00000000000000..3c7ee46d993db1 --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/Kconfig.npcx7m6fb_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCX7M6FB_EVB + select SOC_NPCX7M6FB diff --git a/boards/arm/npcx7m6fb_evb/board.cmake b/boards/nuvoton/npcx7m6fb_evb/board.cmake similarity index 100% rename from boards/arm/npcx7m6fb_evb/board.cmake rename to boards/nuvoton/npcx7m6fb_evb/board.cmake diff --git a/boards/nuvoton/npcx7m6fb_evb/board.yml b/boards/nuvoton/npcx7m6fb_evb/board.yml new file mode 100644 index 00000000000000..33528cde3476f9 --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: npcx7m6fb_evb + vendor: nuvoton + socs: + - name: npcx7m6fb diff --git a/boards/nuvoton/npcx7m6fb_evb/doc/index.rst b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst new file mode 100644 index 00000000000000..3bcf013f84fe27 --- /dev/null +++ b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst @@ -0,0 +1,107 @@ +.. _npcx7m6fb_evb: + +Nuvoton NPCX7M6FB_EVB +##################### + +Overview +******** + +The NPCX7M6FB_EVB kit is a development platform to evaluate the +Nuvoton NPCX7 series microcontrollers. This board needs to be mated with +part number NPCX796FB. + +.. image:: npcx7m6fb_evb.jpg + :align: center + :alt: NPCX7M6FB Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 256 KB RAM and 64 KB boot ROM +- ADC & GPIO headers +- UART0 and UART1 +- FAN PWM interface +- Jtag interface +- Intel Modular Embedded Controller Card (MECC) headers + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig` + + +Connections and IOs +=================== + +Nuvoton to provide the schematic for this board. + +System Clock +============ + +The NPCX7M6FB MCU is configured to use the 90Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + + +Programming and Debugging +************************* + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG only sessions. + +Flashing +======== + +If the correct IDC headers are installed, this board supports both J-TAG and +also the ChromiumOS servo. + +To flash using Servo V2, μServo, or Servo V4 (CCD), see the +`Chromium EC Flashing Documentation`_ for more information. + +To flash with J-TAG, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: npcx7m6fb_evb + :maybe-skip-config: + :goals: build flash + +Debugging +========= + +Use JTAG/SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg b/boards/nuvoton/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg similarity index 100% rename from boards/arm/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg rename to boards/nuvoton/npcx7m6fb_evb/doc/npcx7m6fb_evb.jpg diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb-pinctrl.dtsi diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts similarity index 100% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.dts rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.yaml b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.yaml similarity index 100% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb.yaml rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.yaml diff --git a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig similarity index 88% rename from boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig rename to boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig index c1abbbb44f98fe..13dabc3f51c68c 100644 --- a/boards/arm/npcx7m6fb_evb/npcx7m6fb_evb_defconfig +++ b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_NPCX7M6FB=y -CONFIG_SOC_SERIES_NPCX7=y -CONFIG_BOARD_NPCX7M6FB_EVB=y - # Enable NPCX firmware header CONFIG_NPCX_HEADER=y CONFIG_NPCX_IMAGE_OUTPUT_HEX=y diff --git a/boards/arm/npcx7m6fb_evb/support/openocd.cfg b/boards/nuvoton/npcx7m6fb_evb/support/openocd.cfg similarity index 100% rename from boards/arm/npcx7m6fb_evb/support/openocd.cfg rename to boards/nuvoton/npcx7m6fb_evb/support/openocd.cfg diff --git a/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig b/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..3004ce803d4678 --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config INPUT + default y if KSCAN diff --git a/boards/nuvoton/npcx9m6f_evb/Kconfig.npcx9m6f_evb b/boards/nuvoton/npcx9m6f_evb/Kconfig.npcx9m6f_evb new file mode 100644 index 00000000000000..792ab76ad47772 --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/Kconfig.npcx9m6f_evb @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NPCX9M6F_EVB + select SOC_NPCX9M6F diff --git a/boards/arm/npcx9m6f_evb/board.cmake b/boards/nuvoton/npcx9m6f_evb/board.cmake similarity index 100% rename from boards/arm/npcx9m6f_evb/board.cmake rename to boards/nuvoton/npcx9m6f_evb/board.cmake diff --git a/boards/nuvoton/npcx9m6f_evb/board.yml b/boards/nuvoton/npcx9m6f_evb/board.yml new file mode 100644 index 00000000000000..7baeb00dfa3a1d --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: npcx9m6f_evb + vendor: nuvoton + socs: + - name: npcx9m6f diff --git a/boards/nuvoton/npcx9m6f_evb/doc/index.rst b/boards/nuvoton/npcx9m6f_evb/doc/index.rst new file mode 100644 index 00000000000000..e9ed19970c5c0f --- /dev/null +++ b/boards/nuvoton/npcx9m6f_evb/doc/index.rst @@ -0,0 +1,121 @@ +.. _npcx9m6f_evb: + +Nuvoton NPCX9M6F_EVB +#################### + +Overview +******** + +The NPCX9M6F_EVB kit is a development platform to evaluate the +Nuvoton NPCX9 series microcontrollers. This board needs to be mated with +part number NPCX996F. + +.. image:: npcx9m6f_evb.jpg + :align: center + :alt: NPCX9M6F Evaluation Board + +Hardware +******** + +- ARM Cortex-M4F Processor +- 256 KB RAM and 64 KB boot ROM +- ADC & GPIO headers +- UART0 and UART1 +- FAN PWM interface +- Jtag interface +- Intel Modular Embedded Controller Card (MECC) headers + +Supported Features +================== + +The following features are supported: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port/controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PM | on-chip | power management | ++-----------+------------+-------------------------------------+ +| PSL | on-chip | power switch logic | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pulse width modulator | ++-----------+------------+-------------------------------------+ +| TACH | on-chip | tachometer sensor | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by Zephyr (at the moment) + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig` + + +Connections and IOs +=================== + +Nuvoton to provide the schematic for this board. + +System Clock +============ + +The NPCX9M6F MCU is configured to use the 90Mhz internal oscillator with the +on-chip PLL to generate a resulting EC clock rate of 15 MHz. See Processor clock +control register (chapter 4 in user manual) + +Serial Port +=========== + +UART1 is configured for serial logs. + + +Programming and Debugging +************************* + +This board comes with a Cortex ETM port which facilitates tracing and debugging +using a single physical connection. In addition, it comes with sockets for +JTAG-only sessions. + +Flashing +======== + +If the correct IDC headers are installed, this board supports both J-TAG and +also the ChromiumOS servo. + +To flash using Servo V2, μServo, or Servo V4 (CCD), see the +`Chromium EC Flashing Documentation`_ for more information. + +To flash with J-TAG, install the drivers for your programmer, for example: +SEGGER J-link's drivers are at https://www.segger.com/downloads/jlink/ + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: npcx9m6f_evb + :maybe-skip-config: + :goals: build flash + +Debugging +========= + +Use JTAG/SWD with a J-Link + +References +********** +.. target-notes:: + +.. _Chromium EC Flashing Documentation: + https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board diff --git a/boards/arm/npcx9m6f_evb/doc/npcx9m6f_evb.jpg b/boards/nuvoton/npcx9m6f_evb/doc/npcx9m6f_evb.jpg similarity index 100% rename from boards/arm/npcx9m6f_evb/doc/npcx9m6f_evb.jpg rename to boards/nuvoton/npcx9m6f_evb/doc/npcx9m6f_evb.jpg diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb-pinctrl.dtsi diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts similarity index 100% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb.dts rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb.yaml b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.yaml similarity index 100% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb.yaml rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.yaml diff --git a/boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig similarity index 88% rename from boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig rename to boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig index ae8b83cf8eb44d..c076f906112247 100644 --- a/boards/arm/npcx9m6f_evb/npcx9m6f_evb_defconfig +++ b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_NPCX9M6F=y -CONFIG_SOC_SERIES_NPCX9=y -CONFIG_BOARD_NPCX9M6F_EVB=y - # Enable NPCX firmware header CONFIG_NPCX_HEADER=y CONFIG_NPCX_IMAGE_OUTPUT_HEX=y diff --git a/boards/arm/npcx9m6f_evb/support/openocd.cfg b/boards/nuvoton/npcx9m6f_evb/support/openocd.cfg similarity index 100% rename from boards/arm/npcx9m6f_evb/support/openocd.cfg rename to boards/nuvoton/npcx9m6f_evb/support/openocd.cfg diff --git a/boards/nuvoton/numaker_pfm_m467/Kconfig b/boards/nuvoton/numaker_pfm_m467/Kconfig new file mode 100644 index 00000000000000..c18a30cfc2d93e --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_PFM_M467 + select SOC_FLASH_NUMAKER diff --git a/boards/nuvoton/numaker_pfm_m467/Kconfig.defconfig b/boards/nuvoton/numaker_pfm_m467/Kconfig.defconfig new file mode 100644 index 00000000000000..2d476ffc5619da --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/Kconfig.defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +if BOARD_NUMAKER_PFM_M467 + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_NUMAKER_PFM_M467 diff --git a/boards/nuvoton/numaker_pfm_m467/Kconfig.numaker_pfm_m467 b/boards/nuvoton/numaker_pfm_m467/Kconfig.numaker_pfm_m467 new file mode 100644 index 00000000000000..0516c6bdb94746 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/Kconfig.numaker_pfm_m467 @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_PFM_M467 + select SOC_M467 diff --git a/boards/nuvoton/numaker_pfm_m467/board.cmake b/boards/nuvoton/numaker_pfm_m467/board.cmake new file mode 100644 index 00000000000000..58661cdae22be7 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(pyocd "--target=m467hjhae") +board_runner_args(nulink "-f") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nulink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/canopen.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nuvoton/numaker_pfm_m467/board.yml b/boards/nuvoton/numaker_pfm_m467/board.yml new file mode 100644 index 00000000000000..d9b195940ee36f --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m467/board.yml @@ -0,0 +1,5 @@ +board: + name: numaker_pfm_m467 + vendor: nuvoton + socs: + - name: m467 diff --git a/boards/arm/numaker_pfm_m467/doc/index.rst b/boards/nuvoton/numaker_pfm_m467/doc/index.rst similarity index 100% rename from boards/arm/numaker_pfm_m467/doc/index.rst rename to boards/nuvoton/numaker_pfm_m467/doc/index.rst diff --git a/boards/arm/numaker_pfm_m467/doc/pfm_m467.jpeg b/boards/nuvoton/numaker_pfm_m467/doc/pfm_m467.jpeg similarity index 100% rename from boards/arm/numaker_pfm_m467/doc/pfm_m467.jpeg rename to boards/nuvoton/numaker_pfm_m467/doc/pfm_m467.jpeg diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi similarity index 100% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467-pinctrl.dtsi diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467.dts b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts similarity index 100% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467.dts rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.dts diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467.yaml b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml similarity index 100% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467.yaml rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml diff --git a/boards/arm/numaker_pfm_m467/numaker_pfm_m467_defconfig b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig similarity index 78% rename from boards/arm/numaker_pfm_m467/numaker_pfm_m467_defconfig rename to boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig index abc0d144a94918..a5396d157c3cbf 100644 --- a/boards/arm/numaker_pfm_m467/numaker_pfm_m467_defconfig +++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_M46X=y -CONFIG_SOC_M467=y CONFIG_PINCTRL=y CONFIG_GPIO=y @@ -13,14 +11,13 @@ CONFIG_CLOCK_CONTROL_NUMAKER_SCC=y CONFIG_ARM_MPU=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000 -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# console +# Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y # Enable FMC CONFIG_FLASH=y -CONFIG_SOC_FLASH_NUMAKER=y diff --git a/boards/arm/numaker_pfm_m467/support/openocd.cfg b/boards/nuvoton/numaker_pfm_m467/support/openocd.cfg similarity index 100% rename from boards/arm/numaker_pfm_m467/support/openocd.cfg rename to boards/nuvoton/numaker_pfm_m467/support/openocd.cfg diff --git a/boards/nuvoton/numaker_pfm_m487/Kconfig.numaker_pfm_m487 b/boards/nuvoton/numaker_pfm_m487/Kconfig.numaker_pfm_m487 new file mode 100644 index 00000000000000..156feae907e0e4 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/Kconfig.numaker_pfm_m487 @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Nuvoton PFM M467 board configuration +# +# Copyright (c) 2023 Nuvoton Technology Corporation. + +config BOARD_NUMAKER_PFM_M487 + select SOC_M487 diff --git a/boards/arm/nuvoton_pfm_m487/board.cmake b/boards/nuvoton/numaker_pfm_m487/board.cmake similarity index 100% rename from boards/arm/nuvoton_pfm_m487/board.cmake rename to boards/nuvoton/numaker_pfm_m487/board.cmake diff --git a/boards/nuvoton/numaker_pfm_m487/board.yml b/boards/nuvoton/numaker_pfm_m487/board.yml new file mode 100644 index 00000000000000..cc9dc43fe6ad27 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/board.yml @@ -0,0 +1,5 @@ +board: + name: numaker_pfm_m487 + vendor: nuvoton + socs: + - name: m487 diff --git a/boards/nuvoton/numaker_pfm_m487/doc/index.rst b/boards/nuvoton/numaker_pfm_m487/doc/index.rst new file mode 100644 index 00000000000000..323be5f5923f6f --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/doc/index.rst @@ -0,0 +1,98 @@ +.. _nuvoton_pfm_m487: + +NUVOTON NUMAKER PFM M487 +######################## + +Overview +******** + +The NuMaker PFM M487 is an Internet of Things (IoT) application focused platform +specially developed by Nuvoton. The PFM-M487 is based on the NuMicro® M487 +Ethernet series MCU with ARM® -Cortex®-M4F core. + +.. image:: pfm_m487.jpg + :align: center + :alt: PFM-M487 + +Features: +========= +- 32-bit Arm Cortex®-M4 M487JIDAE MCU +- Core clock up to 192 MHz +- 512 KB embedded Dual Bank Flash and 160 KB SRAM +- Audio codec (NAU88L25) with Microphone In and Headphone Out +- Ethernet (IP101GR) for network application +- USB 2.0 High-Speed OTG / Host / Device +- USB 1.1 Full-Speed OTG / Host / Device +- External SPI Flash (Winbond W25Q20) which can be regarded as ROM module +- MicroSD Card slot for T-Flash +- M487 extended interface 4 connector with 36 pins each +- Arduino UNO compatible interface +- Three push-buttons: one is for reset and the other two are for user-defined +- Four LEDs: one is for power indication and the other three are for user-defined +- On-board NU-Link-Me ICE debugger/programmer with SWD connector + +More information about the board can be found at the `PFM M487 User Manual`_. + +Supported Features +================== + +* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 192MHz. + +The development board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port | ++-----------+------------+-----------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +More details about the supported peripherals are available in `M480 TRM`_ +Other hardware features are not currently supported by the Zephyr kernel. + +Building and Flashing +********************* +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +On board debugger Nu-link-Me can emulate UART0 as a virtual COM port over usb, +To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON. +Connect the PFM M487 IoT to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_pfm_m487 + :goals: flash + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: numaker_pfm_m487 + :goals: debug + +Step through the application in your debugger. + +References +********** + +.. _PFM M487 User Manual: + https://www.nuvoton.com/export/resource-files/UM_NuMaker-PFM-M487_User_Manual_EN_Rev1.01.pdf +.. _M480 TRM: + https://www.nuvoton.com/export/resource-files/TRM_M480_Series_EN_Rev2.02.pdf diff --git a/boards/arm/nuvoton_pfm_m487/doc/pfm_m487.jpg b/boards/nuvoton/numaker_pfm_m487/doc/pfm_m487.jpg similarity index 100% rename from boards/arm/nuvoton_pfm_m487/doc/pfm_m487.jpg rename to boards/nuvoton/numaker_pfm_m487/doc/pfm_m487.jpg diff --git a/boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487-pinctrl.dtsi b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487-pinctrl.dtsi similarity index 100% rename from boards/arm/nuvoton_pfm_m487/nuvoton_pfm_m487-pinctrl.dtsi rename to boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487-pinctrl.dtsi diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.dts b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.dts new file mode 100644 index 00000000000000..87f24bb13d2eb3 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.dts @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2020 Linumiz + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "numaker_pfm_m487-pinctrl.dtsi" +#include + +/ { + model = "Nuvoton PFM M487 board"; + compatible = "nuvoton,pfm-m487", "nuvoton,m487"; + + aliases { + led0 = &red_led; + led1 = &yellow_led; + led2 = &green_led; + sw0 = &sw2; + sw1 = &sw3; + }; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpioh 0 GPIO_ACTIVE_LOW>; + label = "User LED Red"; + }; + yellow_led: led_1 { + gpios = <&gpioh 1 GPIO_ACTIVE_LOW>; + label = "User LED Yellow"; + }; + green_led: led_2 { + gpios = <&gpioh 2 GPIO_ACTIVE_LOW>; + label = "User LED Green"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + sw2: button_0 { + gpios = <&gpiog 15 GPIO_ACTIVE_LOW>; + label = "User SW2"; + zephyr,code = ; + }; + sw3: button_1 { + gpios = <&gpiof 11 GPIO_ACTIVE_LOW>; + label = "User SW3"; + zephyr,code = ; + }; + }; +}; + +&flash0 { + reg = <0x0 DT_SIZE_K(512)>; +}; + +&sram0 { + reg = <0x20000000 DT_SIZE_K(160)>; +}; + +&gpiob { + status = "okay"; +}; + +&gpiof { + status = "okay"; +}; + +&gpiog { + status = "okay"; +}; + +&gpioh { + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml new file mode 100644 index 00000000000000..396f6780698e7e --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml @@ -0,0 +1,11 @@ +identifier: numaker_pfm_m487 +name: NUVOTON-PFM-M487 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 160 +flash: 512 +vendor: nuvoton diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig new file mode 100644 index 00000000000000..bd250a1e0605a5 --- /dev/null +++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=192000000 + +# Enable GPIO and pinctrl drivers +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nuvoton_pfm_m487/support/openocd.cfg b/boards/nuvoton/numaker_pfm_m487/support/openocd.cfg similarity index 100% rename from boards/arm/nuvoton_pfm_m487/support/openocd.cfg rename to boards/nuvoton/numaker_pfm_m487/support/openocd.cfg diff --git a/boards/arm/frdm_k22f/CMakeLists.txt b/boards/nxp/frdm_k22f/CMakeLists.txt similarity index 100% rename from boards/arm/frdm_k22f/CMakeLists.txt rename to boards/nxp/frdm_k22f/CMakeLists.txt diff --git a/boards/nxp/frdm_k22f/Kconfig.defconfig b/boards/nxp/frdm_k22f/Kconfig.defconfig new file mode 100644 index 00000000000000..8978b957c14946 --- /dev/null +++ b/boards/nxp/frdm_k22f/Kconfig.defconfig @@ -0,0 +1,20 @@ +# FRDM-K22F board + +# Copyright (c) 2018 Prevas A/S +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_K22F + +config OSC_XTAL0_FREQ + default 8000000 + +config MCG_PRDIV0 + default 0x3 + +config MCG_VDIV0 + default 0xc + +config MCG_FCRDIV + default 0 + +endif # BOARD_FRDM_K22F diff --git a/boards/nxp/frdm_k22f/Kconfig.frdm_k22f b/boards/nxp/frdm_k22f/Kconfig.frdm_k22f new file mode 100644 index 00000000000000..4ca1a2c0fa4d0a --- /dev/null +++ b/boards/nxp/frdm_k22f/Kconfig.frdm_k22f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_K22F + select SOC_MK22F51212 + select SOC_PART_NUMBER_MK22FN512VLH12 diff --git a/boards/arm/frdm_k22f/board.cmake b/boards/nxp/frdm_k22f/board.cmake similarity index 100% rename from boards/arm/frdm_k22f/board.cmake rename to boards/nxp/frdm_k22f/board.cmake diff --git a/boards/nxp/frdm_k22f/board.yml b/boards/nxp/frdm_k22f/board.yml new file mode 100644 index 00000000000000..0498d799129f46 --- /dev/null +++ b/boards/nxp/frdm_k22f/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_k22f + vendor: nxp + socs: + - name: mk22f51212 diff --git a/boards/arm/frdm_k22f/doc/frdm_k22f.jpg b/boards/nxp/frdm_k22f/doc/frdm_k22f.jpg similarity index 100% rename from boards/arm/frdm_k22f/doc/frdm_k22f.jpg rename to boards/nxp/frdm_k22f/doc/frdm_k22f.jpg diff --git a/boards/nxp/frdm_k22f/doc/index.rst b/boards/nxp/frdm_k22f/doc/index.rst new file mode 100644 index 00000000000000..f0f98048561c7e --- /dev/null +++ b/boards/nxp/frdm_k22f/doc/index.rst @@ -0,0 +1,298 @@ +.. _frdm_k22f: + +NXP FRDM-K22F +############## + +Overview +******** + +The Freedom-K22F is an ultra-low-cost development platform for Kinetis K22 +MCUs. + +- Form-factor compatible with the Arduino R3 pin layout +- Peripherals enable rapid prototyping, including a 6-axis digital + accelerometer and magnetometer to create full eCompass capabilities, a + tri-colored LED and 2 user push-buttons for direct interaction, a optional + microSD card slot, and headers for use with Bluetooth* and 2.4 GHz radio + add-on modules +- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter + running an open source bootloader, offers options for serial communication, + flash programming, and run-control debugging + +.. image:: frdm_k22f.jpg + :align: center + :alt: FRDM-K22F + +Hardware +******** + +- MK22FN512VLH12 (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 64 pin Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- Two user push buttons +- Flexible power supply option - OpenSDAv2 USB, Kinetis K22 USB, and external source +- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors +- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface + software that provides: + + - Mass storage device (MSD) flash programming interface + - CMSIS-DAP debug interface over a driver-less USB HID connection providing + run-control debugging and compatibility with IDE tools + - Virtual serial port interface + - Open source CMSIS-DAP software project + +- Optional SDHC + +For more information about the K22F SoC and FRDM-K22F board: + +- `K22F Website`_ +- `K22F Datasheet`_ +- `K22F Reference Manual`_ +- `FRDM-K22F Website`_ +- `FRDM-K22F User Guide`_ +- `FRDM-K22F Schematics`_ + +Supported Features +================== + +The frdm_k22f board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the frdm_k64f board may have additional features +already supported, which can also be re-used on this frdm_k22f board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| FTFE | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + +:zephyr_file:`boards/nxp/frdm_k22f/frdm_k22f_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The K22F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTA1 | GPIO | Red LED | ++-------+-----------------+---------------------------+ +| PTA2 | GPIO | Green LED | ++-------+-----------------+---------------------------+ +| PTD5 | GPIO | Blue LED | ++-------+-----------------+---------------------------+ +| PTC1 | GPIO | SW2 | ++-------+-----------------+---------------------------+ +| PTD0 | GPIO | FXOS8700 INT1 | ++-------+-----------------+---------------------------+ +| PTD1 | GPIO | FXOS8700 INT2 | ++-------+-----------------+---------------------------+ +| PTB17 | GPIO | SW3 | ++-------+-----------------+---------------------------+ +| PTE1 | UART1_RX | UART Console | ++-------+-----------------+---------------------------+ +| PTE0 | UART1_TX | UART Console | ++-------+-----------------+---------------------------+ +| PTD2 | UART2_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTD3 | UART2_TX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTC4 | SPI0_PCS0 | SPI | ++-------+-----------------+---------------------------+ +| PTD1 | SPI0_SCK | SPI | ++-------+-----------------+---------------------------+ +| PTD2 | SPI0_SOUT | SPI | ++-------+-----------------+---------------------------+ +| PTD3 | SPI0_SIN | SPI | ++-------+-----------------+---------------------------+ +| PTB2 | I2C0_SCL | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ +| PTB3 | I2C0_SDA | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ + +System Clock +============ + +The K22F SoC is configured to use the 8 MHz crystal oscillator on the board +with the on-chip PLL to generate a 72 MHz system clock in its RUN mode. This +clock was selected to allow for the maximum number of peripherals to be used +with the crystal and PLL clocks. Other clock configurations are possible +through NXP SDK currently. + +Serial Port +=========== + +The K22F SoC has three UARTs. One is configured for the console, another for BT +HCI, and the remaining are not used. + +USB +=== + +The K22F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (K22F USB). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink FRDM-K22F Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `Segger J-Link OpenSDA V2.1 Firmware`_. Note that Segger +does provide an OpenSDA J-Link Board-Specific Firmware for this board, however +it is not compatible with the DAPLink bootloader. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k22f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J26. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k22f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.0.0 ***** + Hello World! frdm_k22f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k22f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.0.0 ***** + Hello World! frdm_k22f + +.. _FRDM-K22F Website: + https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-kinetis-k22-mcus:FRDM-K22F + +.. _FRDM-K22F User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMK22FUG + +.. _FRDM-K22F Schematics: + https://www.nxp.com/webapp/Download?colCode=FRDM-K22F-SCH + +.. _K22F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k2x-usb/kinetis-k22-120-mhz-cost-effective-full-speed-usb-microcontrollers-mcus-based-on-arm-cortex-m4-core:K22_120 + +.. _K22F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K22P121M120SF7.pdf + +.. _K22F Reference Manual: + https://www.nxp.com/docs/en/reference-manual/K22P121M120SF7RM.pdf + +.. _OpenSDA DAPLink FRDM-K22F Firmware: + https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk22f_if_crc_legacy_0x8000.bin + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _Segger J-Link OpenSDA V2.1 Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1.bin diff --git a/boards/arm/frdm_k22f/frdm_k22f-pinctrl.dtsi b/boards/nxp/frdm_k22f/frdm_k22f-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_k22f/frdm_k22f-pinctrl.dtsi rename to boards/nxp/frdm_k22f/frdm_k22f-pinctrl.dtsi diff --git a/boards/arm/frdm_k22f/frdm_k22f.dts b/boards/nxp/frdm_k22f/frdm_k22f.dts similarity index 100% rename from boards/arm/frdm_k22f/frdm_k22f.dts rename to boards/nxp/frdm_k22f/frdm_k22f.dts diff --git a/boards/arm/frdm_k22f/frdm_k22f.yaml b/boards/nxp/frdm_k22f/frdm_k22f.yaml similarity index 100% rename from boards/arm/frdm_k22f/frdm_k22f.yaml rename to boards/nxp/frdm_k22f/frdm_k22f.yaml diff --git a/boards/arm/frdm_k22f/frdm_k22f_defconfig b/boards/nxp/frdm_k22f/frdm_k22f_defconfig similarity index 84% rename from boards/arm/frdm_k22f/frdm_k22f_defconfig rename to boards/nxp/frdm_k22f/frdm_k22f_defconfig index 4ee913104debfe..28e4f2b6ec356c 100644 --- a/boards/arm/frdm_k22f/frdm_k22f_defconfig +++ b/boards/nxp/frdm_k22f/frdm_k22f_defconfig @@ -6,8 +6,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MK22F51212=y -CONFIG_SOC_SERIES_KINETIS_K2X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/frdm_k22f/support/openocd.cfg b/boards/nxp/frdm_k22f/support/openocd.cfg similarity index 100% rename from boards/arm/frdm_k22f/support/openocd.cfg rename to boards/nxp/frdm_k22f/support/openocd.cfg diff --git a/boards/arm/segger_trb_stm32f407/CMakeLists.txt b/boards/nxp/frdm_k64f/CMakeLists.txt similarity index 100% rename from boards/arm/segger_trb_stm32f407/CMakeLists.txt rename to boards/nxp/frdm_k64f/CMakeLists.txt diff --git a/boards/nxp/frdm_k64f/Kconfig.defconfig b/boards/nxp/frdm_k64f/Kconfig.defconfig new file mode 100644 index 00000000000000..1faad7cad92aa8 --- /dev/null +++ b/boards/nxp/frdm_k64f/Kconfig.defconfig @@ -0,0 +1,30 @@ +# FRDM-K64F board + +# Copyright (c) 2016, Freescale Semiconductor, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_K64F + +config OSC_XTAL0_FREQ + default 50000000 + +config MCG_PRDIV0 + default 0x13 + +config MCG_VDIV0 + default 0x18 + +config MCG_FCRDIV + default 1 + +config TEST_EXTRA_STACK_SIZE + default 128 + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_FRDM_K64F diff --git a/boards/nxp/frdm_k64f/Kconfig.frdm_k64f b/boards/nxp/frdm_k64f/Kconfig.frdm_k64f new file mode 100644 index 00000000000000..31c7e706ce2fa9 --- /dev/null +++ b/boards/nxp/frdm_k64f/Kconfig.frdm_k64f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_K64F + select SOC_MK64F12 + select SOC_PART_NUMBER_MK64FN1M0VLL12 diff --git a/boards/arm/frdm_k64f/board.cmake b/boards/nxp/frdm_k64f/board.cmake similarity index 100% rename from boards/arm/frdm_k64f/board.cmake rename to boards/nxp/frdm_k64f/board.cmake diff --git a/boards/nxp/frdm_k64f/board.yml b/boards/nxp/frdm_k64f/board.yml new file mode 100644 index 00000000000000..a338af6b99ce5f --- /dev/null +++ b/boards/nxp/frdm_k64f/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_k64f + vendor: nxp + socs: + - name: mk64f12 diff --git a/boards/arm/frdm_k64f/doc/frdm_k64f.jpg b/boards/nxp/frdm_k64f/doc/frdm_k64f.jpg similarity index 100% rename from boards/arm/frdm_k64f/doc/frdm_k64f.jpg rename to boards/nxp/frdm_k64f/doc/frdm_k64f.jpg diff --git a/boards/nxp/frdm_k64f/doc/index.rst b/boards/nxp/frdm_k64f/doc/index.rst new file mode 100644 index 00000000000000..97c158804ee7ba --- /dev/null +++ b/boards/nxp/frdm_k64f/doc/index.rst @@ -0,0 +1,401 @@ +.. _frdm_k64f: + +NXP FRDM-K64F +############## + +Overview +******** + +The Freedom-K64F is an ultra-low-cost development platform for Kinetis K64, +K63, and K24 MCUs. + +- Form-factor compatible with the Arduino R3 pin layout +- Peripherals enable rapid prototyping, including a 6-axis digital + accelerometer and magnetometer to create full eCompass capabilities, a + tri-colored LED and 2 user push-buttons for direct interaction, a microSD + card slot, and connectivity using onboard Ethernet port and headers for use + with Bluetooth* and 2.4 GHz radio add-on modules +- OpenSDAv2, the NXP open source hardware embedded serial and debug adapter + running an open source bootloader, offers options for serial communication, + flash programming, and run-control debugging + +.. image:: frdm_k64f.jpg + :align: center + :alt: FRDM-K64F + +Hardware +******** + +- MK64FN1M0VLL12 MCU (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- Two user push buttons +- Flexible power supply option - OpenSDAv2 USB, Kinetis K64 USB, and external source +- Easy access to MCU input/output through Arduino* R3 compatible I/O connectors +- Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface + software that provides: + + - Mass storage device (MSD) flash programming interface + - CMSIS-DAP debug interface over a driver-less USB HID connection providing + run-control debugging and compatibility with IDE tools + - Virtual serial port interface + - Open source CMSIS-DAP software project + +- Ethernet +- SDHC + +For more information about the K64F SoC and FRDM-K64F board: + +- `K64F Website`_ +- `K64F Datasheet`_ +- `K64F Reference Manual`_ +- `FRDM-K64F Website`_ +- `FRDM-K64F User Guide`_ +- `FRDM-K64F Schematics`_ + +Supported Features +================== + +NXP considers the FRDM-K64F as the superset board for the Kinetis K +series of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire Kinetis K series. NXP prioritizes enabling +this board with new support for Zephyr features. The frdm_k64f board +configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| FTFE | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_k64f/frdm_k64f_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The K64F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTB22 | GPIO | Red LED | ++-------+-----------------+---------------------------+ +| PTE26 | GPIO | Green LED | ++-------+-----------------+---------------------------+ +| PTB21 | GPIO | Blue LED | ++-------+-----------------+---------------------------+ +| PTC6 | GPIO | SW2 / FXOS8700 INT1 | ++-------+-----------------+---------------------------+ +| PTC13 | GPIO | FXOS8700 INT2 | ++-------+-----------------+---------------------------+ +| PTA4 | GPIO | SW3 | ++-------+-----------------+---------------------------+ +| PTB10 | ADC | ADC1 channel 14 | ++-------+-----------------+---------------------------+ +| PTB16 | UART0_RX | UART Console | ++-------+-----------------+---------------------------+ +| PTB17 | UART0_TX | UART Console | ++-------+-----------------+---------------------------+ +| PTB18 | CAN0_TX | CAN TX | ++-------+-----------------+---------------------------+ +| PTB19 | CAN0_RX | CAN RX | ++-------+-----------------+---------------------------+ +| PTC8 | PWM | PWM_3 channel 4 | ++-------+-----------------+---------------------------+ +| PTC9 | PWM | PWM_3 channel 5 | ++-------+-----------------+---------------------------+ +| PTC16 | UART3_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTC17 | UART3_TX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTD0 | SPI0_PCS0 | SPI | ++-------+-----------------+---------------------------+ +| PTD1 | SPI0_SCK | SPI | ++-------+-----------------+---------------------------+ +| PTD2 | SPI0_SOUT | SPI | ++-------+-----------------+---------------------------+ +| PTD3 | SPI0_SIN | SPI | ++-------+-----------------+---------------------------+ +| PTE24 | I2C0_SCL | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ +| PTE25 | I2C0_SDA | I2C / FXOS8700 | ++-------+-----------------+---------------------------+ +| PTA5 | MII0_RXER | Ethernet | ++-------+-----------------+---------------------------+ +| PTA12 | MII0_RXD1 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA13 | MII0_RXD0 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA14 | MII0_RXDV | Ethernet | ++-------+-----------------+---------------------------+ +| PTA15 | MII0_TXEN | Ethernet | ++-------+-----------------+---------------------------+ +| PTA16 | MII0_TXD0 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA17 | MII0_TXD1 | Ethernet | ++-------+-----------------+---------------------------+ +| PTA28 | MII0_TXER | Ethernet | ++-------+-----------------+---------------------------+ +| PTB0 | MII0_MDIO | Ethernet | ++-------+-----------------+---------------------------+ +| PTB1 | MII0_MDC | Ethernet | ++-------+-----------------+---------------------------+ +| PTC16 | ENET0_1588_TMR0 | Ethernet | ++-------+-----------------+---------------------------+ +| PTC17 | ENET0_1588_TMR1 | Ethernet | ++-------+-----------------+---------------------------+ +| PTC18 | ENET0_1588_TMR2 | Ethernet | ++-------+-----------------+---------------------------+ +| PTC19 | ENET0_1588_TMR3 | Ethernet | ++-------+-----------------+---------------------------+ + +.. note:: + Do not enable Ethernet and UART BT HCI simultaneously because they conflict + on PTC16-17. + +System Clock +============ + +The K64F SoC is configured to use the 50 MHz external oscillator on the board +with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The K64F SoC has six UARTs. One is configured for the console, another for BT +HCI, and the remaining are not used. + +USB +=== + +The K64F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (K64F USB). +Only USB device function is supported in Zephyr at the moment. + +CAN +=== + +The FRDM-K64F board does not come with an onboard CAN transceiver. In order to +use the CAN bus, an external CAN bus transceiver must be connected to ``PTB18`` +(``CAN0_TX``) and ``PTB19`` (``CAN0_RX``). + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +.. tabs:: + + .. group-tab:: OpenSDA DAPLink Onboard (Recommended) + + Install the :ref:`linkserver-debug-host-tools` and make sure they are in your + search path. LinkServer works with the default CMSIS-DAP firmware included in + the on-board debugger. + + Linkserver is the default for this board, ``west flash`` and ``west debug`` will + call the linkserver runner. + + .. code-block:: console + + west flash + + Alternatively, pyOCD can be used to flash and debug the board by using the + ``-r pyocd`` option with West. pyOCD is installed when you complete the + :ref:`gs_python_deps` step in the Getting Started Guide. The runners supported + by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP + does not test or support the pyOCD runner. + + + .. group-tab:: OpenSDA JLink Onboard + + Install the :ref:`jlink-debug-host-tools` and make sure they are in your search + path. + + The version of J-Link firmware to program to the board depends on the version + of the DAPLink bootloader. Refer to `OpenSDA Serial and Debug Adapter`_ for + more details. On this page, change the pull-down menu for "Choose your board to + start" to FRDM-K64F, and review the section "To update your board with OpenSDA + applications". Note that Segger does provide an OpenSDA J-Link Board-Specific + Firmware for this board, however it is not compatible with the DAPLink + bootloader. After downloading the appropriate J-Link firmware, follow the + instructions in :ref:`opensda-jlink-onboard-debug-probe` to program to the + board. + + Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and + ``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the + default runner to J-Link: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k64f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J26. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k64f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_k64f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k64f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_k64f + +Troubleshooting +=============== + +If pyocd raises an uncaught ``DAPAccessIntf.TransferFaultError()`` exception +when you try to flash or debug, it's possible that the K64F flash may have been +locked by a corrupt application. You can unlock it with the following sequence +of pyocd commands: + +.. code-block:: console + + $ pyocd cmd + 0001915:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device + Connected to K64F [Halted]: 0240000026334e450028400d5e0e000e4eb1000097969900 + >>> unlock + 0016178:WARNING:target_kinetis:K64F secure state: unlocked successfully + >>> reinit + 0034584:WARNING:target_kinetis:Forcing halt on connect in order to gain control of device + >>> load build/zephyr/zephyr.bin + [====================] 100% + >>> reset + Resetting target + >>> quit + +.. _FRDM-K64F Website: + https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F + +.. _FRDM-K64F User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMK64FUG + +.. _FRDM-K64F Schematics: + https://www.nxp.com/webapp/Download?colCode=FRDM-K64F-SCH-E4 + +.. _K64F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 + +.. _K64F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf + +.. _K64F Reference Manual: + https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink FRDM-K64F Firmware: + https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk64f_if_crc_legacy_0x5000.bin + +.. _OpenSDA Serial and Debug Adapter: + https://www.nxp.com/design/microcontrollers-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#FRDM-K64F + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/frdm_k64f/dts/nxp,enet-experimental.overlay b/boards/nxp/frdm_k64f/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/frdm_k64f/dts/nxp,enet-experimental.overlay rename to boards/nxp/frdm_k64f/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/frdm_k64f/frdm_k64f-pinctrl.dtsi b/boards/nxp/frdm_k64f/frdm_k64f-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_k64f/frdm_k64f-pinctrl.dtsi rename to boards/nxp/frdm_k64f/frdm_k64f-pinctrl.dtsi diff --git a/boards/arm/frdm_k64f/frdm_k64f.dts b/boards/nxp/frdm_k64f/frdm_k64f.dts similarity index 100% rename from boards/arm/frdm_k64f/frdm_k64f.dts rename to boards/nxp/frdm_k64f/frdm_k64f.dts diff --git a/boards/arm/frdm_k64f/frdm_k64f.yaml b/boards/nxp/frdm_k64f/frdm_k64f.yaml similarity index 100% rename from boards/arm/frdm_k64f/frdm_k64f.yaml rename to boards/nxp/frdm_k64f/frdm_k64f.yaml diff --git a/boards/arm/frdm_k64f/frdm_k64f_defconfig b/boards/nxp/frdm_k64f/frdm_k64f_defconfig similarity index 82% rename from boards/arm/frdm_k64f/frdm_k64f_defconfig rename to boards/nxp/frdm_k64f/frdm_k64f_defconfig index 1f2df24a8666dd..74d8a115b892a9 100644 --- a/boards/arm/frdm_k64f/frdm_k64f_defconfig +++ b/boards/nxp/frdm_k64f/frdm_k64f_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MK64F12=y -CONFIG_SOC_SERIES_KINETIS_K6X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/frdm_k64f/support/openocd.cfg b/boards/nxp/frdm_k64f/support/openocd.cfg similarity index 100% rename from boards/arm/frdm_k64f/support/openocd.cfg rename to boards/nxp/frdm_k64f/support/openocd.cfg diff --git a/boards/arm/twr_kv58f220m/CMakeLists.txt b/boards/nxp/frdm_k82f/CMakeLists.txt similarity index 100% rename from boards/arm/twr_kv58f220m/CMakeLists.txt rename to boards/nxp/frdm_k82f/CMakeLists.txt diff --git a/boards/nxp/frdm_k82f/Kconfig.defconfig b/boards/nxp/frdm_k82f/Kconfig.defconfig new file mode 100644 index 00000000000000..310e6d3709dc09 --- /dev/null +++ b/boards/nxp/frdm_k82f/Kconfig.defconfig @@ -0,0 +1,24 @@ +# FRDM-K82F board + +# Copyright (c) 2019 SEAL AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_K82F + +config OSC_XTAL0_FREQ + default 12000000 + +config MCG_PRDIV0 + default 0x0 + +config MCG_VDIV0 + default 0x4 + +config MCG_FCRDIV + default 1 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # BOARD_FRDM_K82F diff --git a/boards/nxp/frdm_k82f/Kconfig.frdm_k82f b/boards/nxp/frdm_k82f/Kconfig.frdm_k82f new file mode 100644 index 00000000000000..b05d7b858b1321 --- /dev/null +++ b/boards/nxp/frdm_k82f/Kconfig.frdm_k82f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_K82F + select SOC_MK82F25615 + select SOC_PART_NUMBER_MK82FN256VLL15 diff --git a/boards/arm/frdm_k82f/board.cmake b/boards/nxp/frdm_k82f/board.cmake similarity index 100% rename from boards/arm/frdm_k82f/board.cmake rename to boards/nxp/frdm_k82f/board.cmake diff --git a/boards/nxp/frdm_k82f/board.yml b/boards/nxp/frdm_k82f/board.yml new file mode 100644 index 00000000000000..cf7bc47e121e41 --- /dev/null +++ b/boards/nxp/frdm_k82f/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_k82f + vendor: nxp + socs: + - name: mk82f25615 diff --git a/boards/arm/frdm_k82f/doc/frdm_k82f.jpg b/boards/nxp/frdm_k82f/doc/frdm_k82f.jpg similarity index 100% rename from boards/arm/frdm_k82f/doc/frdm_k82f.jpg rename to boards/nxp/frdm_k82f/doc/frdm_k82f.jpg diff --git a/boards/nxp/frdm_k82f/doc/index.rst b/boards/nxp/frdm_k82f/doc/index.rst new file mode 100644 index 00000000000000..71e6e5133fc7d9 --- /dev/null +++ b/boards/nxp/frdm_k82f/doc/index.rst @@ -0,0 +1,253 @@ +.. _frdm_k82f: + +NXP FRDM-K82F +############## + +Overview +******** + +The FRDM-K82F is a low-cost development platform for Kinetis K80, K81, +and K82 MCUs. + +- Form-factor compatible with the Arduino R3 pin layout +- Peripherals enable rapid prototyping, including a six-axis digital + accelerometer and magnetometer to create full eCompass capabilities, a + tri-colored LED and two user push-buttons for direct interaction, 2x32 Mb + QuadSPI external flash, FlexIO camera header, touchpads and headers for use + with Bluetooth and 2.4 GHz radio add-on modules +- OpenSDAv2.1, the NXP open source hardware embedded serial and debug adapter + running an open source bootloader, offers options for serial communication, + flash programming, and run-control debugging + +.. image:: frdm_k82f.jpg + :align: center + :alt: FRDM-K82F + +Hardware +******** + +- MK82FN256VLL15 MCU (150 MHz, 256 KB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 100 Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- Two user push buttons +- 2x 32 Mb QSPI flash +- Flexible power supply option - OpenSDAv2.1 USB, Kinetis K82 USB, and external source +- Easy access to MCU input/output through Arduino R3 compatible I/O connectors +- Programmable OpenSDAv2.1 debug circuit supporting the CMSIS-DAP Interface + software that provides: + + - Mass storage device (MSD) flash programming interface + - CMSIS-DAP debug interface over a driver-less USB HID connection providing + run-control debugging and compatibility with IDE tools + - Virtual serial port interface + - Open source CMSIS-DAP software project + +- FlexIO header + +For more information about the K82F SoC and FRDM-K82F board: + +- `K82F Website`_ +- `K82F Datasheet`_ +- `K82F Reference Manual`_ +- `FRDM-K82F Website`_ +- `FRDM-K82F User Guide`_ +- `FRDM-K82F Schematics`_ + +Supported Features +================== + +The frdm_k82f board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`frdm_k64f`, which is the superset board in NXP's Kinetis K series. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the frdm_k64f board may have additional features +already supported, which can also be re-used on this frdm_k82f board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| FLASH | off-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FTFA | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_k82f/frdm_k82f_defconfig` + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The K82F SoC is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The K82F SoC has five UARTs. One is configured for the console, the remaining +ones are not used. + +USB +=== + +The K82F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (J11). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink FRDM-K82F Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Firmware for FRDM-K82F`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k82f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J5. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k82f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! frdm_k82f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_k82f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! frdm_k82f + +.. _FRDM-K82F Website: + https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k82-k81-and-k80-mcus:FRDM-K82F + +.. _FRDM-K82F User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMK82FUG + +.. _FRDM-K82F Schematics: + https://www.nxp.com/downloads/en/schematics/FRDM-K82F-SCH.pdf + +.. _K82F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k8x-secure/kinetis-k82-150-mhz-hw-cryptographic-co-processor-quadspi-microcontrollers-mcus-based-on-arm-cortex-m4-core:K82_150 + +.. _K82F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K82P121M150SF5.pdf + +.. _K82F Reference Manual: + https://www.nxp.com/webapp/Download?colCode=K82P121M150SF5RM + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink FRDM-K82F Firmware: + https://www.nxp.com/downloads/en/snippets-boot-code-headers-monitors/k20dx_frdmk82f_if_crc_legacy_0x8000.bin + +.. _OpenSDA J-Link Firmware for FRDM-K82F: + https://www.segger.com/downloads/jlink/OpenSDA_FRDM-K82F diff --git a/boards/arm/frdm_k82f/frdm_k82f-pinctrl.dtsi b/boards/nxp/frdm_k82f/frdm_k82f-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_k82f/frdm_k82f-pinctrl.dtsi rename to boards/nxp/frdm_k82f/frdm_k82f-pinctrl.dtsi diff --git a/boards/arm/frdm_k82f/frdm_k82f.dts b/boards/nxp/frdm_k82f/frdm_k82f.dts similarity index 100% rename from boards/arm/frdm_k82f/frdm_k82f.dts rename to boards/nxp/frdm_k82f/frdm_k82f.dts diff --git a/boards/arm/frdm_k82f/frdm_k82f.yaml b/boards/nxp/frdm_k82f/frdm_k82f.yaml similarity index 100% rename from boards/arm/frdm_k82f/frdm_k82f.yaml rename to boards/nxp/frdm_k82f/frdm_k82f.yaml diff --git a/boards/arm/frdm_k82f/frdm_k82f_defconfig b/boards/nxp/frdm_k82f/frdm_k82f_defconfig similarity index 83% rename from boards/arm/frdm_k82f/frdm_k82f_defconfig rename to boards/nxp/frdm_k82f/frdm_k82f_defconfig index 8b8a4e33367ac7..752e5539cbb24f 100644 --- a/boards/arm/frdm_k82f/frdm_k82f_defconfig +++ b/boards/nxp/frdm_k82f/frdm_k82f_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_KINETIS_K8X=y -CONFIG_SOC_MK82F25615=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/usb_kw24d512/CMakeLists.txt b/boards/nxp/frdm_kl25z/CMakeLists.txt similarity index 100% rename from boards/arm/usb_kw24d512/CMakeLists.txt rename to boards/nxp/frdm_kl25z/CMakeLists.txt diff --git a/boards/nxp/frdm_kl25z/Kconfig.defconfig b/boards/nxp/frdm_kl25z/Kconfig.defconfig new file mode 100644 index 00000000000000..5f32a4528a7290 --- /dev/null +++ b/boards/nxp/frdm_kl25z/Kconfig.defconfig @@ -0,0 +1,31 @@ +# FRDM-KL25Z board + +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_KL25Z + +config OSC_XTAL0_FREQ + default 8000000 + +config MCG_PRDIV0 + default 0x01 + +config MCG_VDIV0 + default 0x00 + +config MCG_FRDIV + default 5 + +config MCG_FCRDIV + default 0 + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +endif # FXOS8700 + +endif # BOARD_FRDM_KL25Z diff --git a/boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z b/boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z new file mode 100644 index 00000000000000..20165db21804f0 --- /dev/null +++ b/boards/nxp/frdm_kl25z/Kconfig.frdm_kl25z @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_KL25Z + select SOC_MKL25Z4 + select SOC_PART_NUMBER_MKL25Z128VLK4 diff --git a/boards/arm/frdm_kl25z/board.cmake b/boards/nxp/frdm_kl25z/board.cmake similarity index 100% rename from boards/arm/frdm_kl25z/board.cmake rename to boards/nxp/frdm_kl25z/board.cmake diff --git a/boards/nxp/frdm_kl25z/board.yml b/boards/nxp/frdm_kl25z/board.yml new file mode 100644 index 00000000000000..0caf35c690e08e --- /dev/null +++ b/boards/nxp/frdm_kl25z/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_kl25z + vendor: nxp + socs: + - name: mkl25z4 diff --git a/boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg b/boards/nxp/frdm_kl25z/doc/frdm_kl25z.jpg similarity index 100% rename from boards/arm/frdm_kl25z/doc/frdm_kl25z.jpg rename to boards/nxp/frdm_kl25z/doc/frdm_kl25z.jpg diff --git a/boards/nxp/frdm_kl25z/doc/index.rst b/boards/nxp/frdm_kl25z/doc/index.rst new file mode 100644 index 00000000000000..6695974c29ebbf --- /dev/null +++ b/boards/nxp/frdm_kl25z/doc/index.rst @@ -0,0 +1,250 @@ +.. _frdm_kl25z: + +NXP FRDM-KL25Z +############## + +Overview +******** + +The Freedom KL25Z is an ultra-low-cost development platform for +Kinetis |reg| L Series KL1x (KL14/15) and KL2x (KL24/25) MCUs built +on ARM |reg| Cortex |reg|-M0+ processor. + +The FRDM-KL25Z features include easy access to MCU I/O, battery-ready, +low-power operation, a standard-based form factor with expansion board +options and a built-in debug interface for flash programming and run-control. + + +.. image:: frdm_kl25z.jpg + :align: center + :alt: FRDM-KL25Z + +Hardware +******** + +- MKL25Z128VLK4 MCU @ 48 MHz, 128 KB flash, 16 KB SRAM, USB OTG (FS), 80LQFP +- On board capacitive touch "slider", MMA8451Q accelerometer, and tri-color LED +- OpenSDA debug interface + +For more information about the KL25Z SoC and FRDM-KL25Z board: + +- `KL25Z Website`_ +- `KL25Z Datasheet`_ +- `KL25Z Reference Manual`_ +- `FRDM-KL25Z Website`_ +- `FRDM-KL25Z User Guide`_ +- `FRDM-KL25Z Schematics`_ + +Supported Features +================== + +The frdm_kl25z board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_kl25z/frdm_kl25z_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KL25Z SoC has five pairs of pinmux/gpio controllers, and all are currently enabled +(PORTA/GPIOA, PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-KL25Z board. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTB2 | ADC | ADC0 channel 12 | ++-------+-------------+---------------------------+ +| PTB18 | GPIO | Red LED | ++-------+-------------+---------------------------+ +| PTB19 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTD1 | GPIO | Blue LED | ++-------+-------------+---------------------------+ +| PTA1 | UART0_RX | UART Console | ++-------+-------------+---------------------------+ +| PTA2 | UART0_TX | UART Console | ++-------+-------------+---------------------------+ +| PTE24 | I2C0_SCL | I2C | ++-------+-------------+---------------------------+ +| PTE25 | I2C0_SDA | I2C | ++-------+-------------+---------------------------+ + + +System Clock +============ + +The KL25Z SoC is configured to use the 8 MHz external oscillator on the board +with the on-chip FLL to generate a 48 MHz system clock. + +Serial Port +=========== + +The KL25Z UART0 is used for the console. + +USB +=== + +The KL25Z SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its mini USB connector (USB KL25Z). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: Linkserver: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------------------ + + Install the :ref:`linkserver-debug-host-tools` and make sure they are in your + search path. LinkServer works with the CMSIS-DAP debug firmware. Please follow the + instructions on :ref:`opensda-daplink-onboard-debug-probe` and select the latest revision + of the firmware image. + + Linkserver is the default for this board, ``west flash`` and ``west debug`` will + call the linkserver runner. + + .. code-block:: console + + west flash + west debug + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link FRDM-KL25Z Firmware`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kl25z + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Note: +----- + +The runners supported by NXP are LinkServer and JLink. pyOCD is another potential option, +but NXP does not test or support the pyOCD runner. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J7. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kl25z + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kl25z + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kl25z + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kl25z + +.. _FRDM-KL25Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z + +.. _FRDM-KL25Z User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMKL25ZUM + +.. _FRDM-KL25Z Schematics: + https://www.nxp.com/downloads/en/schematics/FRDM-KL25Z_SCH_REV_E.pdf + +.. _KL25Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/kinetis-kl2x-72-96mhz-usb-ultra-low-power-microcontrollers-mcus-based-on-arm-cortex-m0-plus-core:KL2x?&l + +.. _KL25Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/KL25P80M48SF0.pdf + +.. _KL25Z Reference Manual: + https://www.nxp.com/webapp/Download?colCode=KL25P80M48SF0RM + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink FRDM-KL25Z Firmware: + https://www.nxp.com/downloads/en/ide-debug-compile-build-tools/OpenSDAv2.2_DAPLink_frdmkl25z_rev0242.zip + +.. _OpenSDA J-Link FRDM-KL25Z Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KL25Z diff --git a/boards/arm/frdm_kl25z/frdm_kl25z-pinctrl.dtsi b/boards/nxp/frdm_kl25z/frdm_kl25z-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_kl25z/frdm_kl25z-pinctrl.dtsi rename to boards/nxp/frdm_kl25z/frdm_kl25z-pinctrl.dtsi diff --git a/boards/arm/frdm_kl25z/frdm_kl25z.dts b/boards/nxp/frdm_kl25z/frdm_kl25z.dts similarity index 100% rename from boards/arm/frdm_kl25z/frdm_kl25z.dts rename to boards/nxp/frdm_kl25z/frdm_kl25z.dts diff --git a/boards/arm/frdm_kl25z/frdm_kl25z.yaml b/boards/nxp/frdm_kl25z/frdm_kl25z.yaml similarity index 100% rename from boards/arm/frdm_kl25z/frdm_kl25z.yaml rename to boards/nxp/frdm_kl25z/frdm_kl25z.yaml diff --git a/boards/arm/frdm_kl25z/frdm_kl25z_defconfig b/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig similarity index 85% rename from boards/arm/frdm_kl25z/frdm_kl25z_defconfig rename to boards/nxp/frdm_kl25z/frdm_kl25z_defconfig index 54f27a6c14e0a5..0645bba8800b94 100644 --- a/boards/arm/frdm_kl25z/frdm_kl25z_defconfig +++ b/boards/nxp/frdm_kl25z/frdm_kl25z_defconfig @@ -1,6 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_KINETIS_KL2X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm64/bcm958402m2_a72/CMakeLists.txt b/boards/nxp/frdm_kw41z/CMakeLists.txt similarity index 100% rename from boards/arm64/bcm958402m2_a72/CMakeLists.txt rename to boards/nxp/frdm_kw41z/CMakeLists.txt diff --git a/boards/nxp/frdm_kw41z/Kconfig.defconfig b/boards/nxp/frdm_kw41z/Kconfig.defconfig new file mode 100644 index 00000000000000..2f1d83f690eb5d --- /dev/null +++ b/boards/nxp/frdm_kw41z/Kconfig.defconfig @@ -0,0 +1,25 @@ +# FRDM-KW41Z board + +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_FRDM_KW41Z + +config OSC_XTAL0_FREQ + default 32000000 + +config MCG_FRDIV + default 5 + +config MCG_FCRDIV + default 0 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +choice ADC_MCUX_ADC16_VREF + default ADC_MCUX_ADC16_VREF_ALTERNATE +endchoice + +endif # BOARD_FRDM_KW41Z diff --git a/boards/nxp/frdm_kw41z/Kconfig.frdm_kw41z b/boards/nxp/frdm_kw41z/Kconfig.frdm_kw41z new file mode 100644 index 00000000000000..3044a899ed0253 --- /dev/null +++ b/boards/nxp/frdm_kw41z/Kconfig.frdm_kw41z @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FRDM_KW41Z + select SOC_MKW41Z4 + select SOC_PART_NUMBER_MKW41Z512VHT4 diff --git a/boards/arm/frdm_kw41z/board.cmake b/boards/nxp/frdm_kw41z/board.cmake similarity index 100% rename from boards/arm/frdm_kw41z/board.cmake rename to boards/nxp/frdm_kw41z/board.cmake diff --git a/boards/nxp/frdm_kw41z/board.yml b/boards/nxp/frdm_kw41z/board.yml new file mode 100644 index 00000000000000..b17c67beb3e49f --- /dev/null +++ b/boards/nxp/frdm_kw41z/board.yml @@ -0,0 +1,5 @@ +board: + name: frdm_kw41z + vendor: nxp + socs: + - name: mkw41z4 diff --git a/boards/arm/frdm_kw41z/doc/frdm_kw41z.jpg b/boards/nxp/frdm_kw41z/doc/frdm_kw41z.jpg similarity index 100% rename from boards/arm/frdm_kw41z/doc/frdm_kw41z.jpg rename to boards/nxp/frdm_kw41z/doc/frdm_kw41z.jpg diff --git a/boards/nxp/frdm_kw41z/doc/index.rst b/boards/nxp/frdm_kw41z/doc/index.rst new file mode 100644 index 00000000000000..4457b6d9b16b7b --- /dev/null +++ b/boards/nxp/frdm_kw41z/doc/index.rst @@ -0,0 +1,259 @@ +.. _frdm_kw41z: + +NXP FRDM-KW41Z +############## + +Overview +******** + +The FRDM-KW41Z is a development kit enabled by the Kinetis |reg| W series +KW41Z/31Z/21Z (KW41Z) family built on ARM |reg| Cortex |reg|-M0+ processor with +integrated 2.4 GHz transceiver supporting Bluetooth |reg| Smart/Bluetooth +|reg| Low Energy +(BLE) v4.2, Generic FSK, IEEE |reg| 802.15.4 and Thread. + +The FRDM-KW41Z kit contains two Freedom boards that can be used as a +development board or a shield to connect to a host processor. The FRDM-KW41Z is +form-factor compatible with the Arduino |trade| R3 pin layout for more expansion +options. + +The FRDM-KW41Z highly-sensitive, optimized 2.4 GHz radio features a PCB +F-antenna which can be bypassed to test via SMA connection, multiple power +supply options, push/capacitive touch buttons, switches, LEDs and integrated +sensors. + +.. image:: frdm_kw41z.jpg + :align: center + :alt: FRDM-KW41Z + +Hardware +******** + +- Can be configured as Host or Shield for connection to Host Processor +- Supports all DC-DC configurations (Buck, Boost, Bypass) +- PCB inverted F-type antenna +- SMA RF Connector +- RF regulatory certified +- Serial Flash for OTA firmware upgrades +- On board NXP FXOS8700CQ digital sensor, 3D Accelerometer ( |plusminus| 2g/ + |plusminus| 4g/ |plusminus| 8g) + 3D + Magnetometer +- OpenSDA and JTAG debug + +For more information about the KW41Z SoC and FRDM-KW41Z board: + +- `KW41Z Website`_ +- `KW41Z Datasheet`_ +- `KW41Z Reference Manual`_ +- `FRDM-KW41Z Website`_ +- `FRDM-KW41Z User Guide`_ +- `FRDM-KW41Z Schematics`_ + +Supported Features +================== + +The frdm_kw41z board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling: | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | tpm | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FTFA | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/frdm_kw41z/frdm_kw41z_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KW41Z SoC has three pairs of pinmux/gpio controllers, but only two are +currently enabled (PORTA/GPIOA and PORTC/GPIOC) for the FRDM-KW41Z board. + ++-------+-------------+---------------------------+ +| Name | Function | Usage | ++=======+=============+===========================+ +| PTC1 | GPIO | Red LED / FXOS8700 INT1 | ++-------+-------------+---------------------------+ +| PTA19 | GPIO | Green LED | ++-------+-------------+---------------------------+ +| PTA18 | GPIO | Blue LED | ++-------+-------------+---------------------------+ +| PTB2 | ADC | ADC0 channel 3 | ++-------+-------------+---------------------------+ +| PTC2 | I2C1_SCL | I2C / FXOS8700 | ++-------+-------------+---------------------------+ +| PTC3 | I2C1_SDA | I2C / FXOS8700 | ++-------+-------------+---------------------------+ +| PTC4 | GPIO | SW3 | ++-------+-------------+---------------------------+ +| PTC5 | GPIO | SW4 | ++-------+-------------+---------------------------+ +| PTC6 | LPUART0_RX | UART Console | ++-------+-------------+---------------------------+ +| PTC7 | LPUART0_TX | UART Console | ++-------+-------------+---------------------------+ +| PTC16 | SPI0_SCK | SPI | ++-------+-------------+---------------------------+ +| PTC17 | SPI0_SOUT | SPI | ++-------+-------------+---------------------------+ +| PTC18 | SPI0_SIN | SPI | ++-------+-------------+---------------------------+ +| PTC19 | SPI0_PCS0 | SPI | ++-------+-------------+---------------------------+ + +System Clock +============ + +The KW41Z SoC is configured to use the 32 MHz external oscillator on the board +with the on-chip FLL to generate a 40 MHz system clock. + +Serial Port +=========== + +The KW41Z SoC has one UART, which is used for the console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink FRDM-KW41Z Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link FRDM-KW41Z Firmware`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kw41z + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J6. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kw41z + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kw41z + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: frdm_kw41z + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! frdm_kw41z + +.. _FRDM-KW41Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/freedom-development-kit-for-kinetis-kw41z-31z-21z-mcus:FRDM-KW41Z + +.. _FRDM-KW41Z User Guide: + https://www.nxp.com/webapp/Download?colCode=FRDMKW41ZUG + +.. _FRDM-KW41Z Schematics: + https://www.nxp.com/webapp/Download?colCode=FRDM-KW41Z-SCH + +.. _KW41Z Website: + https://www.nxp.com/products/wireless/zigbee/kinetis-kw41z-2.4-ghz-dual-mode-bluetooth-low-energy-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW41Z + +.. _KW41Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/MKW41Z512.pdf + +.. _KW41Z Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MKW41Z512RM + +.. _OpenSDA DAPLink FRDM-KW41Z Firmware: + https://www.nxp.com/downloads/en/reference-applications/OpenSDAv2.2_DAPLink_frdmkw41z_rev0241.zip + +.. _OpenSDA J-Link FRDM-KW41Z Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_FRDM-KW41Z diff --git a/boards/arm/frdm_kw41z/frdm_kw41z-pinctrl.dtsi b/boards/nxp/frdm_kw41z/frdm_kw41z-pinctrl.dtsi similarity index 100% rename from boards/arm/frdm_kw41z/frdm_kw41z-pinctrl.dtsi rename to boards/nxp/frdm_kw41z/frdm_kw41z-pinctrl.dtsi diff --git a/boards/arm/frdm_kw41z/frdm_kw41z.dts b/boards/nxp/frdm_kw41z/frdm_kw41z.dts similarity index 100% rename from boards/arm/frdm_kw41z/frdm_kw41z.dts rename to boards/nxp/frdm_kw41z/frdm_kw41z.dts diff --git a/boards/arm/frdm_kw41z/frdm_kw41z.yaml b/boards/nxp/frdm_kw41z/frdm_kw41z.yaml similarity index 100% rename from boards/arm/frdm_kw41z/frdm_kw41z.yaml rename to boards/nxp/frdm_kw41z/frdm_kw41z.yaml diff --git a/boards/arm/frdm_kw41z/frdm_kw41z_defconfig b/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig similarity index 78% rename from boards/arm/frdm_kw41z/frdm_kw41z_defconfig rename to boards/nxp/frdm_kw41z/frdm_kw41z_defconfig index f72dbb5af6929f..ec5a311d8fe6fa 100644 --- a/boards/arm/frdm_kw41z/frdm_kw41z_defconfig +++ b/boards/nxp/frdm_kw41z/frdm_kw41z_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MKW41Z4=y -CONFIG_SOC_SERIES_KINETIS_KWX=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/hexiwear/Kconfig.defconfig b/boards/nxp/hexiwear/Kconfig.defconfig new file mode 100644 index 00000000000000..652e7dac804522 --- /dev/null +++ b/boards/nxp/hexiwear/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Hexiwear K64 board + +# Copyright (c) 2016, Freescale Semiconductor, Inc. +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HEXIWEAR_MK64F12 + +config OSC_XTAL0_FREQ + default 12000000 + +config MCG_PRDIV0 + default 0x02 + +config MCG_VDIV0 + default 0x06 + +config MCG_FCRDIV + default 1 + +config REGULATOR + default y if ADC || SENSOR + +endif # BOARD_HEXIWEAR_MK64F12 + +# Hexiwear KW40Z board + +if BOARD_HEXIWEAR_MKW40Z4 + +config OSC_XTAL0_FREQ + default 32000000 + +config MCG_FRDIV + default 5 + +config MCG_FCRDIV + default 0 + +endif # BOARD_HEXIWEAR_MKW40Z4 diff --git a/boards/nxp/hexiwear/Kconfig.hexiwear b/boards/nxp/hexiwear/Kconfig.hexiwear new file mode 100644 index 00000000000000..5acdde083f4379 --- /dev/null +++ b/boards/nxp/hexiwear/Kconfig.hexiwear @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HEXIWEAR + select SOC_MK64F12 if BOARD_HEXIWEAR_MK64F12 + select SOC_PART_NUMBER_MK64FN1M0VDC12 if BOARD_HEXIWEAR_MK64F12 + select SOC_MKW40Z4 if BOARD_HEXIWEAR_MKW40Z4 + select SOC_PART_NUMBER_MKW40Z160VHT4 if BOARD_HEXIWEAR_MKW40Z4 diff --git a/boards/nxp/hexiwear/board.cmake b/boards/nxp/hexiwear/board.cmake new file mode 100644 index 00000000000000..c56e7d5e138970 --- /dev/null +++ b/boards/nxp/hexiwear/board.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 + +if (CONFIG_BOARD_HEXIWEAR_MK64F12) + board_runner_args(pyocd "--target=k64f") + board_runner_args(jlink "--device=MK64FN1M0xxx12") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +else() + board_runner_args(jlink "--device=MKW40Z160xxx4") + board_runner_args(pyocd "--target=kw40z4") + + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +endif() diff --git a/boards/nxp/hexiwear/board.yml b/boards/nxp/hexiwear/board.yml new file mode 100644 index 00000000000000..c478fa02678579 --- /dev/null +++ b/boards/nxp/hexiwear/board.yml @@ -0,0 +1,6 @@ +board: + name: hexiwear + vendor: nxp + socs: + - name: mk64f12 + - name: mkw40z4 diff --git a/boards/arm/hexiwear_k64/doc/hexiwear_k64.jpg b/boards/nxp/hexiwear/doc/hexiwear_k64.jpg similarity index 100% rename from boards/arm/hexiwear_k64/doc/hexiwear_k64.jpg rename to boards/nxp/hexiwear/doc/hexiwear_k64.jpg diff --git a/boards/nxp/hexiwear/doc/index.rst b/boards/nxp/hexiwear/doc/index.rst new file mode 100644 index 00000000000000..bc4d58a70d4337 --- /dev/null +++ b/boards/nxp/hexiwear/doc/index.rst @@ -0,0 +1,517 @@ +.. _hexiwear: + +Hexiwear +######## + +Overview +******** + +Hexiwear is powered by a Kinetis K64 microcontroller based on the ARM Cortex-M4 +core. Another Kinetis wireless MCU, the KW40Z, provides Bluetooth Low Energy +connectivity. Hexiwear also integrates a wide variety of sensors, as well as a +user interface consisting of a 1.1" 96px x 96px full color OLED display and six +capacitive buttons with haptic feedback. + +- Eye-catching Smart Watch form factor with powerful, low power Kinetis K6x MCU + and 6 on-board sensors. +- Designed for wearable applications with the onboard rechargeable battery, + OLED screen and onboard sensors such as optical heart rate, accelerometer, + magnetometer and gyroscope. +- Designed for IoT end node applications with the onboard sensor's such as + temperature, pressure, humidity and ambient light. +- Flexibility to let you add the sensors of your choice nearly 200 additional + sensors through click boards. + +.. image:: hexiwear_k64.jpg + :align: center + :alt: Hexiwear + +Hardware +******** + +- Main MCU: NXP Kinetis K64x (ARM Cortex-M4, 120 MHz, 1M Flash, 256K SRAM) +- Wireless MCU: NXP Kinetis KW4x (ARM Cortex-M0+, Bluetooth Low Energy & + 802.15.4 radio) +- 6-axis combo Accelerometer and Magnetometer NXP FXOS8700 +- 3-Axis Gyroscope: NXP FXAS21002 +- Absolute Pressure sensor NXP MPL3115 +- Li-Ion/Li-Po Battery Charger NXP MC34671 +- Optical heart rate sensor Maxim MAX30101 +- Ambient Light sensor, Humidity and Temperature sensor +- 1.1" full color OLED display +- Haptic feedback engine +- 190 mAh 2C Li-Po battery +- Capacitive touch interface +- RGB LED + +For more information about the K64F SoC and Hexiwear board: + +- `K64F Website`_ +- `K64F Datasheet`_ +- `K64F Reference Manual`_ +- `Hexiwear Website`_ +- `Hexiwear Fact Sheet`_ +- `Hexiwear Schematics`_ + +Supported Features +================== + +The hexiwear/mk64f12 board variant supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | +| | | fxas21002 polling; | +| | | fxas21002 trigger; | +| | | max30101 polling | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/hexiwear/hexiwear_mk64f12_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The K64F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTA29 | GPIO | LDO_EN | ++-------+-----------------+---------------------------+ +| PTB0 | I2C0_SCL | I2C / MAX30101 | ++-------+-----------------+---------------------------+ +| PTB1 | I2C0_SDA | I2C / MAX30101 | ++-------+-----------------+---------------------------+ +| PTB12 | GPIO | 3V3B EN | ++-------+-----------------+---------------------------+ +| PTB16 | UART0_RX | UART Console | ++-------+-----------------+---------------------------+ +| PTB17 | UART0_TX | UART Console | ++-------+-----------------+---------------------------+ +| PTC8 | GPIO / PWM | Red LED | ++-------+-----------------+---------------------------+ +| PTC9 | GPIO / PWM | Green LED | ++-------+-----------------+---------------------------+ +| PTC10 | I2C1_SCL | I2C / FXOS8700 / FXAS21002| ++-------+-----------------+---------------------------+ +| PTC11 | I2C1_SDA | I2C / FXOS8700 / FXAS21002| ++-------+-----------------+---------------------------+ +| PTC14 | GPIO | Battery sense enable | ++-------+-----------------+---------------------------+ +| PTC18 | GPIO | FXAS21002 INT2 | ++-------+-----------------+---------------------------+ +| PTD0 | GPIO / PWM | Blue LED | ++-------+-----------------+---------------------------+ +| PTD13 | GPIO | FXOS8700 INT2 | ++-------+-----------------+---------------------------+ +| PTE24 | UART4_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTE25 | UART4_TX | UART BT HCI | ++-------+-----------------+---------------------------+ + +.. note:: + + To enable battery sensing, you will need to enable the ``en_bat_sens`` + regulator in Devicetree. Similarly, to enable devices connected to the 1V8 + or 3V3 power rails (sensors), you will need to enable the ``en_ldo`` + and ``en_3v3b`` regulators in Devicetree. + +System Clock +============ + +The K64F SoC is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The K64F SoC has six UARTs. One is configured for the console, another for BT +HCI, and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +but because Segger RTT is required for a console on KW40Z, we recommend that +you reconfigure the board for the :ref:`opensda-jlink-onboard-debug-probe`. + +.. note:: + OpenSDA is shared between the K64 and the KW40Z via switches, therefore only + one SoC can be flashed, debugged, or have an open console at a time. + +Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) +---------------------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches +SW1 and SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals +are connected to the OpenSDA microcontroller. + +Option 2: :ref:`opensda-daplink-onboard-debug-probe` +---------------------------------------------------- + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to +program the `OpenSDA DAPLink Hexiwear Firmware`_. Check that switches SW1 and +SW2 are **on**, and SW3 and SW4 are **off** to ensure K64F SWD signals are +connected to the OpenSDA microcontroller. + +Add the arguments ``-DBOARD_FLASH_RUNNER=pyocd`` and +``-DBOARD_DEBUG_RUNNER=pyocd`` when you invoke ``west build`` to override the +default runner from J-Link to pyOCD: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :gen-args: -DBOARD_FLASH_RUNNER=pyocd -DBOARD_DEBUG_RUNNER=pyocd + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to CN1. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :goals: flash + +Open a serial terminal, reset the board (press the T4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mk64f12 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Using Bluetooth +*************** + +Configure the KW40Z as a Bluetooth controller +============================================= + +The K64 can support Zephyr Bluetooth host applications when you configure the +KW40Z as a Bluetooth controller. + +#. Download and install the `KW40Z Connectivity Software`_. This package + contains Bluetooth controller application for the KW40Z. +#. Flash the file ``tools/binaries/BLE_HCI_Modem.bin`` to the KW40Z. + +Now you can build and run the sample Zephyr Bluetooth host applications on the +K64. You do not need to repeat this step each time you flash a new Bluetooth +host application to the K64. + +Peripheral Heart Rate Sensor +============================ + +Navigate to the Zephyr ``samples/bluetooth/peripheral_hr`` sample +application, then build and flash it to the Hexiwear K64. Make sure +the OpenSDA switches on the docking station are configured for the +K64. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/peripheral_hr + :board: hexiwear/mk64f12 + :goals: build flash + +Reset the KW40Z and the K64 using the push buttons on the docking station. + +Install the Kinetis BLE Toolbox on your smartphone: + +- `Kinetis BLE Toolbox for iOS`_ +- `Kinetis BLE Toolbox for Android`_ + +Open the app, tap the **Heart Rate** feature, and you should see a **Zephyr +Heartrate Sensor** device. Tap the **Zephyr Heartrate Sensor** device and you +will then see a plot of the heart rate data that updates once per second. + + +.. _Hexiwear Website: + https://www.mikroe.com/hexiwear + +.. _Hexiwear Fact Sheet: + https://www.nxp.com/docs/en/fact-sheet/HEXIWEAR-FS.pdf + +.. _Hexiwear Schematics: + http://cdn-docs.mikroe.com/images/c/c0/Sch_Hexiwear_MainBoard_v106c.pdf + +.. _K64F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/k-seriesperformancem4/k6x-ethernet/kinetis-k64-120-mhz-256kb-sram-microcontrollers-mcus-based-on-arm-cortex-m4-core:K64_120 + +.. _K64F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K64P144M120SF5.pdf + +.. _K64F Reference Manual: + https://www.nxp.com/docs/en/reference-manual/K64P144M120SF5RM.pdf + +.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1 + +.. _OpenSDA DAPLink Hexiwear Firmware: + https://github.com/MikroElektronika/HEXIWEAR/blob/master/HW/HEXIWEAR_DockingStation/HEXIWEAR_DockingStation_DAPLINK_FW.bin + +.. _KW40Z Connectivity Software: + https://www.nxp.com/webapp/Download?colCode=KW40Z-CONNECTIVITY-SOFTWARE&appType=license&location=null&fpsp=1&WT_TYPE=Protocol%20Stacks&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=exe&WT_ASSET=Downloads&fileExt=.exe&Parent_nodeId=1432854896956716810497&Parent_pageType=product + +.. _Kinetis BLE Toolbox for iOS: + https://itunes.apple.com/us/app/kinetis-ble-toolbox/id1049036961?mt=8 + +.. _Kinetis BLE Toolbox for Android: + https://play.google.com/store/apps/details?id=com.freescale.kinetisbletoolbox + + +Hexiwear KW40Z +############## + +Overview +******** + +The KW40Z is a secondary SoC on the board that provides wireless connectivity +with a multimode BLE and 802.15.4 radio. + +For more information about the KW40Z SoC: + +- `KW40Z Website`_ +- `KW40Z Datasheet`_ +- `KW40Z Reference Manual`_ + +Supported Features +================== + +The hexiwear/mkw40z4 board variant supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| RTT | on-chip | console | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KW40Z SoC has three pairs of pinmux/gpio controllers, but only one is +currently enabled (PORTC/GPIOC) for the hexiwear/mkw40z4 board. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTB1 | ADC | ADC0 channel 1 | ++-------+-----------------+---------------------------+ +| PTC6 | UART0_RX | UART BT HCI | ++-------+-----------------+---------------------------+ +| PTC7 | UART0_TX | UART BT HCI | ++-------+-----------------+---------------------------+ + +System Clock +============ + +The KW40Z SoC is configured to use the 32 MHz external oscillator on the board +with the on-chip FLL to generate a 40 MHz system clock. + +Serial Port +=========== + +The KW40Z SoC has one UART, which is used for BT HCI. There is no UART +available for a console. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +but because Segger RTT is required for a console, you must reconfigure the +board for one of the following debug probes instead. + +:ref:`opensda-jlink-onboard-debug-probe` +---------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V2.1 Bootloader`_. Check that switches +SW1 and SW2 are **off**, and SW3 and SW4 are **on** to ensure KW40Z SWD signals +are connected to the OpenSDA microcontroller. + +Configuring a Console +===================== + +The console is available using `Segger RTT`_. + +Connect a USB cable from your PC to CN1. + +Once you have started a debug session, run telnet: + +.. code-block:: console + + $ telnet localhost 19021 + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + SEGGER J-Link V6.44 - Real time terminal output + J-Link OpenSDA 2 compiled Feb 28 2017 19:27:57 V1.0, SN=621000000 + Process: JLinkGDBServerCLExe + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: flash + +The Segger RTT console is only available during a debug session. Use ``attach`` +to start one: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: attach + +Run telnet as shown earlier, and you should see the following message in the +terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: hexiwear/mkw40z4 + :goals: debug + +Run telnet as shown earlier, step through the application in your debugger, and +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! hexiwear + +.. _KW40Z Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/kinetis-kw40z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW40Z + +.. _KW40Z Datasheet: + https://www.nxp.com/docs/en/data-sheet/MKW40Z160.pdf + +.. _KW40Z Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MKW40Z160RM + +.. _Segger RTT: + https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ + +.. _OpenSDA J-Link Generic Firmware for V2.1 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V2_1 diff --git a/boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi b/boards/nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi similarity index 100% rename from boards/arm/hexiwear_k64/hexiwear_k64-pinctrl.dtsi rename to boards/nxp/hexiwear/hexiwear_mk64f12-pinctrl.dtsi diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.dts b/boards/nxp/hexiwear/hexiwear_mk64f12.dts new file mode 100644 index 00000000000000..bbd3b43051eb6b --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.dts @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include +#include +#include "hexiwear_mk64f12-pinctrl.dtsi" + +/ { + model = "Hexiwear K64 board"; + compatible = "nxp,hexiwear", "nxp,k64f", "nxp,k6x"; + + aliases { + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + pwm-led0 = &green_pwm_led; + red-pwm-led = &red_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; + magn0 = &fxos8700; + accel0 = &fxos8700; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,bt-uart = &uart4; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpioc 8 GPIO_ACTIVE_LOW>; + label = "User LD1"; + }; + green_led: led_1 { + gpios = <&gpiod 0 GPIO_ACTIVE_LOW>; + label = "User LD2"; + }; + blue_led: led_2 { + gpios = <&gpioc 9 GPIO_ACTIVE_LOW>; + label = "User LD3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + + red_pwm_led: red_pwm_led { + pwms = <&ftm3 4 15625000 PWM_POLARITY_INVERTED>; + }; + green_pwm_led: green_pwm_led { + pwms = <&ftm3 0 15625000 PWM_POLARITY_INVERTED>; + }; + blue_pwm_led: blue_pwm_led { + pwms = <&ftm3 5 15625000 PWM_POLARITY_INVERTED>; + }; + }; + + en_bat_sens: enable-battery-sense { + compatible = "regulator-fixed"; + regulator-name = "en_bat_sens"; + enable-gpios = <&gpioc 14 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; + + en_ldo: enable-ldo { + compatible = "regulator-fixed"; + regulator-name = "en_ldo"; + enable-gpios = <&gpioa 29 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; + + en_3v3b: enable-3v3b { + compatible = "regulator-fixed"; + regulator-name = "en_3v3b"; + enable-gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; +}; + +&sim { + pllfll-select = ; + er32k-select = ; +}; + +&cpu0 { + clock-frequency = <120000000>; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&ftm3 { + status = "okay"; + compatible = "nxp,kinetis-ftm-pwm"; + #pwm-cells = <3>; + pinctrl-0 = <&ftm3_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; + + max30101@57 { + status = "disabled"; + compatible = "maxim,max30101"; + reg = <0x57>; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>; + }; + + fxas21002@20 { + compatible = "nxp,fxas21002"; + reg = <0x20>; + int1-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpioc 18 GPIO_ACTIVE_LOW>; + }; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&gpioe { + status = "okay"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* + * The flash starting at 0x00010000 and ending at + * 0x0001ffff (sectors 16-31) is reserved for use + * by the application. + */ + + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x00060000>; + }; + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00060000>; + }; + scratch_partition: partition@e0000 { + label = "image-scratch"; + reg = <0x000e0000 0x00020000>; + }; + }; +}; diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml new file mode 100644 index 00000000000000..d8f165c71314e7 --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml @@ -0,0 +1,16 @@ +identifier: hexiwear/mk64f12 +name: Hexiwear +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - ble + - gpio + - i2c + - pwm + - watchdog +vendor: nxp diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig b/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig new file mode 100644 index 00000000000000..8609fa1f8da4b0 --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mk64f12_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 +CONFIG_OSC_LOW_POWER=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi b/boards/nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi similarity index 100% rename from boards/arm/hexiwear_kw40z/hexiwear_kw40z-pinctrl.dtsi rename to boards/nxp/hexiwear/hexiwear_mkw40z4-pinctrl.dtsi diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4.dts b/boards/nxp/hexiwear/hexiwear_mkw40z4.dts new file mode 100644 index 00000000000000..c75ca229d345fe --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mkw40z4.dts @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/dts-v1/; + +#include +#include "hexiwear_mkw40z4-pinctrl.dtsi" + +/ { + model = "Hexiwear KW40 board"; + compatible = "nxp,kw40z", "nxp,mkw40z4"; + + chosen { + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; +}; + +&sim { + pllfll-select = ; + er32k-select = ; +}; + +&adc0 { + status = "okay"; + pinctrl-0 = <&adc0_default>; + pinctrl-names = "default"; +}; + +&lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; +}; + +&gpioa { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml b/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml new file mode 100644 index 00000000000000..af4d8d5220d1f0 --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml @@ -0,0 +1,14 @@ +identifier: hexiwear/mkw40z4 +name: Hexiwear KW40Z +type: mcu +arch: arm +ram: 16 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net +vendor: nxp diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig b/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig new file mode 100644 index 00000000000000..4f25cadc1eee43 --- /dev/null +++ b/boards/nxp/hexiwear/hexiwear_mkw40z4_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_RTT_CONSOLE=y +CONFIG_USE_SEGGER_RTT=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 +CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/imx8mm_evk/Kconfig.defconfig b/boards/nxp/imx8mm_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..5cc30c81ed1979 --- /dev/null +++ b/boards/nxp/imx8mm_evk/Kconfig.defconfig @@ -0,0 +1,15 @@ +# MIMX8MM EVK board defconfig + +# Copyright (c) 2020, Manivannan Sadhasivam +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX8MM_EVK_MIMX8MM6_M4 + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_IMX8MM_EVK_MIMX8MM6_M4 diff --git a/boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk b/boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk new file mode 100644 index 00000000000000..390956d20961e6 --- /dev/null +++ b/boards/nxp/imx8mm_evk/Kconfig.imx8mm_evk @@ -0,0 +1,7 @@ +# Copyright 2021-2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MM_EVK + select SOC_MIMX8MM6_A53 if BOARD_IMX8MM_EVK_MIMX8MM6_A53 || BOARD_IMX8MM_EVK_MIMX8MM6_A53_SMP + select SOC_MIMX8MM6_M4 if BOARD_IMX8MM_EVK_MIMX8MM6_M4 + select SOC_PART_NUMBER_MIMX8MM6DVTLZ diff --git a/boards/nxp/imx8mm_evk/board.cmake b/boards/nxp/imx8mm_evk/board.cmake new file mode 100644 index 00000000000000..ddcd01410a383e --- /dev/null +++ b/boards/nxp/imx8mm_evk/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2024 NXP + +if(CONFIG_BOARD_IMX8MM_EVK_MIMX8MM6_M4) + board_set_debugger_ifnset(jlink) + board_set_flasher_ifnset(jlink) + + board_runner_args(jlink "--device=MIMX8MD6_M4") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mm_evk/board.yml b/boards/nxp/imx8mm_evk/board.yml new file mode 100644 index 00000000000000..0c46177f70bb65 --- /dev/null +++ b/boards/nxp/imx8mm_evk/board.yml @@ -0,0 +1,8 @@ +board: + name: imx8mm_evk + vendor: nxp + socs: + - name: mimx8mm6 + variants: + - name: smp + cpucluster: a53 diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst new file mode 100644 index 00000000000000..6483febdcbaaa5 --- /dev/null +++ b/boards/nxp/imx8mm_evk/doc/index.rst @@ -0,0 +1,237 @@ +.. _imx8mm_evk: + +NXP i.MX8MM EVK +############### + +Overview +******** + +i.MX8M Mini LPDDR4 EVK board is based on NXP i.MX8M Mini applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - Micron 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 + - USB: + + - OTG - 2x type C + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr imx8mm_evk board for Cortex-A53 configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig` + +It is recommended to disable peripherals used by the M4 core on the Linux host. + +Other hardware features are not currently supported by the port. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8 MHz. + +The M4 Core is configured to run at a 400 MHz clock speed. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. This is used for the M4 and A53 core targets. + +Programming and Debugging (A53) +******************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + +Or kick SMP zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx8mm_evk/mimx8mm6/a53 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** + thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mm_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mm_evk_a53! + +Use Jailhouse hypervisor, after root cell linux is up: + +.. code-block:: console + + #jailhouse enable imx8mm.cell + #jailhouse cell create imx8mm-zephyr.cell + #jailhouse cell load 1 zephyr.bin -a 0x93c00000 + #jailhouse cell start 1 + +Programming and Debugging (M4) +****************************** + +The MIMX8MM EVK board doesn't have QSPI flash for the M4 and it needs +to be started by the A53 core. The A53 core is responsible to load the M4 binary +application into the RAM, put the M4 in reset, set the M4 Program Counter and +Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at +bootloader level or after the Linux system has booted. + +The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file +:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + +Load and run Zephyr on M4 from A53 using u-boot by copying the compiled +``zephyr.bin`` to the first FAT partition of the SD card and plug the SD +card into the board. Power it up and stop the u-boot execution at prompt. + +Load the M4 binary onto the desired memory and start its execution using: + +.. code-block:: console + + fatload mmc 0:1 0x7e0000 zephyr.bin;bootaux 0x7e0000 + +Debugging +========= + +MIMX8MM EVK board can be debugged by connecting an external JLink +JTAG debugger to the J902 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mm_evk/mimx8mm6/m4 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 ***** + Hello World! imx8mm_evk + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MMRM diff --git a/boards/arm64/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi b/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx8mm_evk/mimx8mm_evk-pinctrl.dtsi rename to boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts new file mode 100644 index 00000000000000..0a2b5c666ea70c --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2020-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mm_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MM A53"; + compatible = "fsl,mimx8mm"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + cpu@2 { + status = "disabled"; + }; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml new file mode 100644 index 00000000000000..1ab75987c38141 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mm_evk/mimx8mm6/a53 +name: NXP i.MX8M Mini EVK A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig new file mode 100644 index 00000000000000..4e31bf4e946057 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts new file mode 100644 index 00000000000000..308094cfb200bb --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mm_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MM A53"; + compatible = "fsl,mimx8mm"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml new file mode 100644 index 00000000000000..1ff3cd7af45226 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mm_evk/mimx8mm6/a53/smp +name: NXP i.MX8M Mini EVK A53 with SMP kernel +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig new file mode 100644 index 00000000000000..845b48736a7f1e --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53_smp_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts new file mode 100644 index 00000000000000..e7680d1286f150 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.dts @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2020, Manivannan Sadhasivam + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#include "imx8mm_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8M Mini EVK board"; + compatible = "nxp,mimx8mm_evk"; + + aliases { + uart-4 = &uart4; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml new file mode 100644 index 00000000000000..9ae6cadff5ddb1 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml @@ -0,0 +1,22 @@ +# +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mm_evk/mimx8mm6/m4 +name: NXP i.MX8M Mini EVK +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig new file mode 100644 index 00000000000000..e0223e4f71fc88 --- /dev/null +++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk b/boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk new file mode 100644 index 00000000000000..f9142e55b0fba5 --- /dev/null +++ b/boards/nxp/imx8mn_evk/Kconfig.imx8mn_evk @@ -0,0 +1,6 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MN_EVK + select SOC_MIMX8MN6_A53 if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP + select SOC_PART_NUMBER_MIMX8MN6DVTJZ if BOARD_IMX8MN_EVK_MIMX8MN6_A53 || BOARD_IMX8MN_EVK_MIMX8MN6_A53_SMP diff --git a/boards/arm64/mimx8mm_evk/board.cmake b/boards/nxp/imx8mn_evk/board.cmake similarity index 100% rename from boards/arm64/mimx8mm_evk/board.cmake rename to boards/nxp/imx8mn_evk/board.cmake diff --git a/boards/nxp/imx8mn_evk/board.yml b/boards/nxp/imx8mn_evk/board.yml new file mode 100644 index 00000000000000..294060de50698f --- /dev/null +++ b/boards/nxp/imx8mn_evk/board.yml @@ -0,0 +1,8 @@ +board: + name: imx8mn_evk + vendor: nxp + socs: + - name: mimx8mn6 + variants: + - name: smp + cpucluster: a53 diff --git a/boards/nxp/imx8mn_evk/doc/index.rst b/boards/nxp/imx8mn_evk/doc/index.rst new file mode 100644 index 00000000000000..3e27bb233ba91b --- /dev/null +++ b/boards/nxp/imx8mn_evk/doc/index.rst @@ -0,0 +1,131 @@ +.. _imx8mn_evk: + +NXP i.MX8MN EVK (Cortex-A53) +############################ + +Overview +******** + +i.MX8M Nano LPDDR4 EVK board is based on NXP i.MX8M Nano applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - Micron 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 + - USB: + + - OTG - 2x type C + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M7 + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr mimx8mn_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. + +Programming and Debugging +************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x93c00000 + +Or kick SMP zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0x93c00000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0x93c00000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx8mn_evk/mimx8mn6/a53 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** + thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mn_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mn_evk_a53! + +Use Jailhouse hypervisor, after root cell linux is up: + +.. code-block:: console + + #jailhouse enable imx8mn.cell + #jailhouse cell create imx8mn-zephyr.cell + #jailhouse cell load 1 zephyr.bin -a 0x93c00000 + #jailhouse cell start 1 + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-nano-applications-processor:8MNANOD4-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MNRM diff --git a/boards/arm64/mimx8mn_evk/mimx8mn_evk-pinctrl.dtsi b/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx8mn_evk/mimx8mn_evk-pinctrl.dtsi rename to boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts new file mode 100644 index 00000000000000..2927ff9d1caea2 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts @@ -0,0 +1,44 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mn_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MN A53"; + compatible = "fsl,mimx8mn"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + cpu@2 { + status = "disabled"; + }; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml new file mode 100644 index 00000000000000..b75fb589d21b56 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mn_evk/mimx8mn6/a53 +name: NXP i.MX8M Nano EVK A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig new file mode 100644 index 00000000000000..4e31bf4e946057 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts new file mode 100644 index 00000000000000..3dbc8b593ae370 --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.dts @@ -0,0 +1,46 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mn_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MN A53"; + compatible = "fsl,mimx8mn"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + sram0: memory@93c00000 { + reg = <0x93c00000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml new file mode 100644 index 00000000000000..d82cced07a9bcc --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mn_evk/mimx8mn6/a53/smp +name: NXP i.MX8M Nano EVK A53 with SMP kernel +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig new file mode 100644 index 00000000000000..845b48736a7f1e --- /dev/null +++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53_smp_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/arm64/khadas_edgev/CMakeLists.txt b/boards/nxp/imx8mp_evk/CMakeLists.txt similarity index 100% rename from boards/arm64/khadas_edgev/CMakeLists.txt rename to boards/nxp/imx8mp_evk/CMakeLists.txt diff --git a/boards/nxp/imx8mp_evk/Kconfig.defconfig b/boards/nxp/imx8mp_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..3fdc7b3cd9c18c --- /dev/null +++ b/boards/nxp/imx8mp_evk/Kconfig.defconfig @@ -0,0 +1,15 @@ +# MIMX8MP EVK board defconfig + +# Copyright (c) 2021, Laird Connectivity +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR diff --git a/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk new file mode 100644 index 00000000000000..fbda0ccc10dbe5 --- /dev/null +++ b/boards/nxp/imx8mp_evk/Kconfig.imx8mp_evk @@ -0,0 +1,8 @@ +# Copyright 2021-2022, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MP_EVK + select SOC_MIMX8ML8_A53 if BOARD_IMX8MP_EVK_MIMX8ML8_A53 || BOARD_IMX8MP_EVK_MIMX8ML8_A53_SMP + select SOC_MIMX8MP_ADSP if BOARD_IMX8MP_EVK_MIMX8ML8_ADSP + select SOC_MIMX8MP_M7 if BOARD_IMX8MP_EVK_MIMX8ML8_M7 || BOARD_IMX8MP_EVK_MIMX8ML8_M7_DDR + select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/nxp/imx8mp_evk/board.cmake b/boards/nxp/imx8mp_evk/board.cmake new file mode 100644 index 00000000000000..55a52a15b19522 --- /dev/null +++ b/boards/nxp/imx8mp_evk/board.cmake @@ -0,0 +1,20 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8MP_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx8m) +endif() + +if(CONFIG_SOC_MIMX8MP_M7) + board_set_debugger_ifnset(jlink) + board_set_flasher_ifnset(jlink) + + board_runner_args(jlink "--device=MIMX8ML8_M7") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/nxp/imx8mp_evk/board.yml b/boards/nxp/imx8mp_evk/board.yml new file mode 100644 index 00000000000000..d810c27a596756 --- /dev/null +++ b/boards/nxp/imx8mp_evk/board.yml @@ -0,0 +1,10 @@ +board: + name: imx8mp_evk + vendor: nxp + socs: + - name: mimx8ml8 + variants: + - name: smp + cpucluster: a53 + - name: ddr + cpucluster: m7 diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst new file mode 100644 index 00000000000000..9952c7c90b52c2 --- /dev/null +++ b/boards/nxp/imx8mp_evk/doc/index.rst @@ -0,0 +1,229 @@ +.. _imx8mp_evk: + +NXP i.MX8MP EVK +############### + +Overview +******** + +i.MX8M Plus LPDDR4 EVK board is based on NXP i.MX8M Plus applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - Micron 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11b/g/n + - Bluetooth: v4.1 + - USB: + + - OTG - 2x type C + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr mimx8mp_evk_a53 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +The Zephyr mimx8mp_evk_m7 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8 MHz. + +The M7 Core is configured to run at a 800 MHz clock speed. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. + +Programming and Debugging (A53) +******************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick non-smp zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xc0000000 + +Or kick SMP zephyr.bin: + +.. code-block:: console + + mw 303d0518 f 1; fatload mmc 1:1 0xc0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 2 release 0xc0000000 + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: imx8mp_evk/mimx8ml8/a53 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.1.0-3575-g44dd713bd883 *** + thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_b: Hello World from cpu 0 on mimx8mp_evk_a53! + thread_a: Hello World from cpu 0 on mimx8mp_evk_a53! + +Use Jailhouse hypervisor, after root cell linux is up: + +.. code-block:: console + + #jailhouse enable imx8mp.cell + #jailhouse cell create imx8mp-zephyr.cell + #jailhouse cell load 1 zephyr.bin -a 0xc0000000 + #jailhouse cell start 1 + +Programming and Debugging (M7) +****************************** + +The MIMX8MP EVK board doesn't have QSPI flash for the M7, and it needs +to be started by the A53 core. The A53 core is responsible to load the M7 binary +application into the RAM, put the M7 in reset, set the M7 Program Counter and +Stack Pointer, and get the M7 out of reset. The A53 can perform these steps at +bootloader level or after the Linux system has booted. + +The M7 can use up to 3 different RAMs (currently, only two configurations are +supported: ITCM and DDR). These are the memory mapping for A53 and M7: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done based on board name (imx8mp_evk/mimx8ml8/m7 for ITCM and +imx8mp_evk/mimx8ml8/m7/ddr for DDR). + +Load and run Zephyr on M7 from A53 using u-boot by copying the compiled +``zephyr.bin`` to the first FAT partition of the SD card and plug the SD +card into the board. Power it up and stop the u-boot execution at prompt. + +Load the M7 binary onto the desired memory and start its execution using: + +ITCM +=== + +.. code-block:: console + + fatload mmc 0:1 0x48000000 zephyr.bin + cp.b 0x48000000 0x7e0000 20000 + bootaux 0x7e0000 + +DDR +=== + +.. code-block:: console + + fatload mmc 0:1 0x80000000 zephyr.bin + dcache flush + bootaux 0x80000000 + +Debugging +========= + +MIMX8MP EVK board can be debugged by connecting an external JLink +JTAG debugger to the J24 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mp_evk/mimx8ml8/m7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91 *** + Hello World! imx8mp_evk + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/docs/en/reference-manual/IMX8MPRM.pdf diff --git a/boards/arm64/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx8mp_evk/mimx8mp_evk-pinctrl.dtsi rename to boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts new file mode 100644 index 00000000000000..18cff6569d4938 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts @@ -0,0 +1,45 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MP A53"; + compatible = "fsl,mimx8mp"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + cpu@2 { + status = "disabled"; + }; + }; + + sram0: memory@c0000000 { + reg = <0xc0000000 DT_SIZE_M(1)>; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml new file mode 100644 index 00000000000000..f1c632d8298781 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/a53 +name: NXP i.MX8M Plus EVK A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig new file mode 100644 index 00000000000000..4e31bf4e946057 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts new file mode 100644 index 00000000000000..0137c60d611b85 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2021-2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MP A53"; + compatible = "fsl,mimx8mp"; + + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + cpu@1 { + status = "disabled"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + sram0: memory@c0000000 { + reg = <0xc0000000 DT_SIZE_M(1)>; + }; + +}; + +&uart4 { + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml new file mode 100644 index 00000000000000..c1b905052351df --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp.yaml @@ -0,0 +1,21 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/a53/smp +name: NXP i.MX8M Plus EVK A53 with SMP kernel +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig new file mode 100644 index 00000000000000..845b48736a7f1e --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53_smp_defconfig @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# SMP +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_PM_CPU_OPS=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts new file mode 100644 index 00000000000000..dc8c0ab48a5816 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts @@ -0,0 +1,41 @@ +/* + * Copyright 2021, 2023, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +/ { + model = "NXP i.MX 8MPLUS Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&pinctrl { + uart4_default: uart4_default { + group0 { + pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, + <&iomuxc_uart4_txd_uart_tx_uart4_tx>; + bias-pull-up; + slew-rate = "slow"; + drive-strength = "x1"; + }; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.yaml new file mode 100644 index 00000000000000..78668aa26f61e1 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.yaml @@ -0,0 +1,16 @@ +identifier: imx8mp_evk/mimx8ml8/adsp +name: NXP i.MX 8MPLUS Audio DSP +type: mcu +arch: xtensa +toolchain: + - xcc + - xt-clang + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - mcumgr +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig new file mode 100644 index 00000000000000..e2c64fa2e0dc07 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp_defconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 + +# size of stack for initialization and main thread +CONFIG_MAIN_STACK_SIZE=3072 + +# enable logger +CONFIG_LOG=y + +# no need for a "raw" binary zephyr/zephyr.bin in the build directory +CONFIG_BUILD_OUTPUT_BIN=n + +# enable uart driver +CONFIG_SERIAL=y + +# clock configuration +CONFIG_CLOCK_CONTROL=y + +# console (remote proc console by default) +CONFIG_CONSOLE=y + +# uart console (overrides remote proc console) +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts new file mode 100644 index 00000000000000..2b05cab20cecff --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.dts @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021, Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8M Plus EVK board"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml new file mode 100644 index 00000000000000..6ab73e3386a8c6 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/m7 +name: NXP i.MX8M Plus EVK +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts new file mode 100644 index 00000000000000..ba805ef7cbf97c --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.dts @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2021, Laird Connectivity + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mp_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8M Plus EVK board"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* DDR */ + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml new file mode 100644 index 00000000000000..e5ed32a1d381ae --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mp_evk/mimx8ml8/m7/ddr +name: NXP i.MX8M Plus EVK (DDR) +type: mcu +arch: arm +ram: 2048 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart +vendor: nxp diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig new file mode 100644 index 00000000000000..17542cb4eec07e --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_DDR=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig new file mode 100644 index 00000000000000..0f7d91f447e969 --- /dev/null +++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Laird Connectivity +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_ITCM=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8mq_evk/Kconfig.defconfig b/boards/nxp/imx8mq_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..054cfde7fb7fbf --- /dev/null +++ b/boards/nxp/imx8mq_evk/Kconfig.defconfig @@ -0,0 +1,16 @@ +# MIMX8MQ EVK board defconfig + +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IMX8MQ_EVK + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_IMX8MQ_EVK diff --git a/boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk b/boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk new file mode 100644 index 00000000000000..c34dcaa76957fe --- /dev/null +++ b/boards/nxp/imx8mq_evk/Kconfig.imx8mq_evk @@ -0,0 +1,9 @@ +# MIMX8MQ EVK board + +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8MQ_EVK + select SOC_PART_NUMBER_MIMX8MQ6DVAJZ + select SOC_MIMX8MQ6_M4 if BOARD_IMX8MQ_EVK_MIMX8MQ6_M4 diff --git a/boards/arm/mimx8mq_evk/board.cmake b/boards/nxp/imx8mq_evk/board.cmake similarity index 100% rename from boards/arm/mimx8mq_evk/board.cmake rename to boards/nxp/imx8mq_evk/board.cmake diff --git a/boards/nxp/imx8mq_evk/board.yml b/boards/nxp/imx8mq_evk/board.yml new file mode 100644 index 00000000000000..c599f0a7afdbd9 --- /dev/null +++ b/boards/nxp/imx8mq_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8mq_evk + vendor: nxp + socs: + - name: mimx8mq6 diff --git a/boards/arm/mimx8mq_evk/doc/img/mimx8mq_evk.jpg b/boards/nxp/imx8mq_evk/doc/img/mimx8mq_evk.jpg similarity index 100% rename from boards/arm/mimx8mq_evk/doc/img/mimx8mq_evk.jpg rename to boards/nxp/imx8mq_evk/doc/img/mimx8mq_evk.jpg diff --git a/boards/nxp/imx8mq_evk/doc/index.rst b/boards/nxp/imx8mq_evk/doc/index.rst new file mode 100644 index 00000000000000..40bd5ac5c5042a --- /dev/null +++ b/boards/nxp/imx8mq_evk/doc/index.rst @@ -0,0 +1,215 @@ +.. _mimx8mq_evk: + +NXP MIMX8MQ EVK +############### + +Overview +******** + +i.MX8MQ EVK board is based on NXP i.MX8MQ applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-M4 core. + +- Board features: + + - RAM: 3GB LPDDR4 + - Storage: + + - 16GB eMMC5.0 + - 32MB QSPI NOR + - microSD Socket + - Wireless: + + - WiFi: 2.4/5GHz IEEE 802.11 a/b/g/n/ac + - Bluetooth: v4.1 + - USB: + + - OTG - 1x type C + - HOST - 1x type A + - Ethernet + - PCI-E M.2 + - LEDs: + + - 1x Power status LED + - 1x UART LED + - Debug + + - JTAG 10-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +.. image:: img/mimx8mq_evk.jpg + :align: center + :alt: MIMX8MQ EVK + +More information about the board can be found at the +`NXP website`_. + +Supported Features +================== + +The Zephyr mimx8mq_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig`. + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +MIMX8MQ EVK board was tested with the following pinmux controller +configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART2 RXD | UART2_TXD | UART Console | ++---------------+-----------------+---------------------------+ +| UART2 TXD | UART2_RXD | UART Console | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 266 MHz clock speed. + +Serial Port +=========== + +The i.MX8MQ SoC has four UARTs. UART_2 is configured for the console and +the remaining are not used/tested. + +Programming and Debugging +************************* + +The MIMX8MQ EVK board doesn't have QSPI flash for the M4 and it needs +to be started by the A53 core. The A53 core is responsible to load the M4 binary +application into the RAM, put the M4 in reset, set the M4 Program Counter and +Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at +bootloader level or after the Linux system has booted. + +The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + +Load and run Zephyr on M4 from A53 using u-boot. + +.. tabs:: + + .. group-tab:: From an SD card + Copy the compiled ``zephyr.bin`` to the first FAT partition of the + SD card and plug the SD card into the board. Power it up and stop the u-boot + execution at prompt. + + Load the M4 binary onto the desired memory and start its execution using: + + .. code-block:: console + + fatload mmc 0:1 0x40480000 zephyr.bin + cp.b 0x40480000 0x7e0000 0x8000 + bootaux 0x7e0000 + + .. group-tab:: From serial + This procedure requires ``screen`` and ``lrzsz`` to be installed. + + Start ``screen``, power up the board, and stop the u-boot execution at prompt: + + .. code-block:: console + + screen 115200 + + Start ``loadx`` with offset ``7e0000``: + + .. code-block:: console + + loadx 7e0000 115200 + + Send the compiled ``zephyr.bin`` with ``sx`` by pressing :kbd:`Ctrl-a` followed by :kbd:`:` + and write: + + .. code-block:: console + + exec !! sx + + Start execution: + + .. code-block:: console + + bootaux 0x7e0000 + +Debugging +========= + +MIMX8MQ EVK board can be debugged by connecting an external JLink +JTAG debugger to the J401 debug connector and to the PC. Then +the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: imx8mq_evk/mimx8mq6/m4 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS build zephyr-v2.6.99-30942-g6ee70bd22058 ***** + Hello World! imx8mq_evk + +References +========== + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-applications-processor:MCIMX8M-EVK + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM diff --git a/boards/arm/mimx8mq_evk/mimx8mq_evk-pinctrl.dtsi b/boards/nxp/imx8mq_evk/imx8mq_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimx8mq_evk/mimx8mq_evk-pinctrl.dtsi rename to boards/nxp/imx8mq_evk/imx8mq_evk-pinctrl.dtsi diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts new file mode 100644 index 00000000000000..7809ce505f7c5c --- /dev/null +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.dts @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021, Kwon Tae-young + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8mq_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX8MQ EVK board"; + compatible = "nxp,mimx8mq_evk"; + + aliases { + uart-2 = &uart2; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml new file mode 100644 index 00000000000000..acb8e15d8a503d --- /dev/null +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2021, Kwon Tae-young +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx8mq_evk/mimx8mq6/m4 +name: NXP i.MX8MQ EVK CM4 +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig new file mode 100644 index 00000000000000..e169a060eab12a --- /dev/null +++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek b/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek new file mode 100644 index 00000000000000..f70580b800c0d2 --- /dev/null +++ b/boards/nxp/imx8qm_mek/Kconfig.imx8qm_mek @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8QM_MEK + select SOC_MIMX8QM_ADSP if BOARD_IMX8QM_MEK_MIMX8QM6_ADSP + select SOC_PART_NUMBER_MIMX8QM6AVUFF diff --git a/boards/nxp/imx8qm_mek/board.cmake b/boards/nxp/imx8qm_mek/board.cmake new file mode 100644 index 00000000000000..0924bf99eecf75 --- /dev/null +++ b/boards/nxp/imx8qm_mek/board.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8QM_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx) +endif() diff --git a/boards/nxp/imx8qm_mek/board.yml b/boards/nxp/imx8qm_mek/board.yml new file mode 100644 index 00000000000000..d044277a6220bf --- /dev/null +++ b/boards/nxp/imx8qm_mek/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8qm_mek + vendor: nxp + socs: + - name: mimx8qm6 diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8-pinctrl.dtsi b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi similarity index 100% rename from boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8-pinctrl.dtsi rename to boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts new file mode 100644 index 00000000000000..325e293851f156 --- /dev/null +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi" + +/ { + model = "NXP i.MX 8QM Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.yaml b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.yaml new file mode 100644 index 00000000000000..c2a70b2652d974 --- /dev/null +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.yaml @@ -0,0 +1,11 @@ +identifier: imx8qm_mek/mimx8qm6/adsp +name: NXP i.MX 8QM Audio DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel + - sof +vendor: nxp diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig new file mode 100644 index 00000000000000..325b05b84e90c5 --- /dev/null +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=3072 + +# board/soc-related configurations +CONFIG_LOG=y + +# TODO: maybe move this to SOF? +CONFIG_DYNAMIC_INTERRUPTS=y +CONFIG_BUILD_OUTPUT_BIN=n + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial-related configurations +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek b/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek new file mode 100644 index 00000000000000..fbd35d46b2f935 --- /dev/null +++ b/boards/nxp/imx8qxp_mek/Kconfig.imx8qxp_mek @@ -0,0 +1,8 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8QXP_MEK + select SOC_MIMX8QXP_ADSP if BOARD_IMX8QXP_MEK_MIMX8QX6_ADSP + select SOC_PART_NUMBER_MIMX8QX6AVLFZ diff --git a/boards/nxp/imx8qxp_mek/board.cmake b/boards/nxp/imx8qxp_mek/board.cmake new file mode 100644 index 00000000000000..699964c5e39aec --- /dev/null +++ b/boards/nxp/imx8qxp_mek/board.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8QXP_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx) +endif() diff --git a/boards/nxp/imx8qxp_mek/board.yml b/boards/nxp/imx8qxp_mek/board.yml new file mode 100644 index 00000000000000..e31754086d7362 --- /dev/null +++ b/boards/nxp/imx8qxp_mek/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8qxp_mek + vendor: nxp + socs: + - name: mimx8qx6 diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x-pinctrl.dtsi b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi similarity index 100% rename from boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x-pinctrl.dtsi rename to boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts new file mode 100644 index 00000000000000..24a9ee09d9e5ae --- /dev/null +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2021, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi" + +/ { + model = "NXP i.MX 8QXP Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + }; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&lpuart2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.yaml b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.yaml new file mode 100644 index 00000000000000..4f168ada93e566 --- /dev/null +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.yaml @@ -0,0 +1,11 @@ +identifier: imx8qxp_mek/mimx8qx6/adsp +name: NXP i.MX 8QXP Audio DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel + - sof +vendor: nxp diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig new file mode 100644 index 00000000000000..325b05b84e90c5 --- /dev/null +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=3072 + +# board/soc-related configurations +CONFIG_LOG=y + +# TODO: maybe move this to SOF? +CONFIG_DYNAMIC_INTERRUPTS=y +CONFIG_BUILD_OUTPUT_BIN=n + +# clock-related configurations +CONFIG_CLOCK_CONTROL=y + +# serial-related configurations +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk b/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk new file mode 100644 index 00000000000000..dbf611081ab7cf --- /dev/null +++ b/boards/nxp/imx8ulp_evk/Kconfig.imx8ulp_evk @@ -0,0 +1,7 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX8ULP_EVK + select SOC_MIMX8ULP_ADSP if BOARD_IMX8ULP_EVK_IMX8ULP_ADSP diff --git a/boards/nxp/imx8ulp_evk/board.cmake b/boards/nxp/imx8ulp_evk/board.cmake new file mode 100644 index 00000000000000..97e0a80ba04ca5 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/board.cmake @@ -0,0 +1,12 @@ +# +# Copyright (c) 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMX8ULP_ADSP) + board_set_flasher_ifnset(misc-flasher) + board_finalize_runner_args(misc-flasher) + + board_set_rimage_target(imx8ulp) +endif() diff --git a/boards/nxp/imx8ulp_evk/board.yml b/boards/nxp/imx8ulp_evk/board.yml new file mode 100644 index 00000000000000..b401615d7d7856 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: imx8ulp_evk + vendor: nxp + socs: + - name: imx8ulp diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts new file mode 100644 index 00000000000000..49ad098fb24477 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.dts @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2023-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "NXP i.MX 8ULP Audio DSP"; + compatible = "nxp"; + + chosen { + zephyr,sram = &sram0; + }; +}; diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml new file mode 100644 index 00000000000000..437d112ee58825 --- /dev/null +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp.yaml @@ -0,0 +1,10 @@ +identifier: imx8ulp_evk/imx8ulp/adsp +name: NXP i.MX 8ULP Audio DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel + - sof diff --git a/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig new file mode 100644 index 00000000000000..e8d594b3070dac --- /dev/null +++ b/boards/nxp/imx8ulp_evk/imx8ulp_evk_imx8ulp_adsp_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_BIN=n + +CONFIG_DYNAMIC_INTERRUPTS=y + +CONFIG_LOG=y diff --git a/boards/arm64/mimx8mp_evk/CMakeLists.txt b/boards/nxp/imx93_evk/CMakeLists.txt similarity index 100% rename from boards/arm64/mimx8mp_evk/CMakeLists.txt rename to boards/nxp/imx93_evk/CMakeLists.txt diff --git a/boards/nxp/imx93_evk/Kconfig.imx93_evk b/boards/nxp/imx93_evk/Kconfig.imx93_evk new file mode 100644 index 00000000000000..e3121418393c59 --- /dev/null +++ b/boards/nxp/imx93_evk/Kconfig.imx93_evk @@ -0,0 +1,6 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IMX93_EVK_MIMX9352_A55 + select SOC_MIMX9352_A55 + select SOC_PART_NUMBER_MIMX9352CVUXK diff --git a/boards/arm64/mimx8mn_evk/board.cmake b/boards/nxp/imx93_evk/board.cmake similarity index 100% rename from boards/arm64/mimx8mn_evk/board.cmake rename to boards/nxp/imx93_evk/board.cmake diff --git a/boards/nxp/imx93_evk/board.yml b/boards/nxp/imx93_evk/board.yml new file mode 100644 index 00000000000000..110334be5589b0 --- /dev/null +++ b/boards/nxp/imx93_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: imx93_evk + vendor: nxp + socs: + - name: mimx9352 diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst new file mode 100644 index 00000000000000..0fdeb237ec27c7 --- /dev/null +++ b/boards/nxp/imx93_evk/doc/index.rst @@ -0,0 +1,215 @@ +.. _imx93_evk: + +NXP i.MX93 EVK (Cortex-A55) +############################ + +Overview +******** + +The i.MX93 Evaluation Kit (MCIMX93-EVK board) is a platform designed to show +the most commonly used features of the i.MX 93 Applications Processor in a +small and low cost package. The MCIMX93-EVK board is an entry-level development +board, which helps developers to get familiar with the processor before +investing a large amount of resources in more specific designs. + +i.MX93 MPU is composed of one cluster of 2x Cortex-A55 cores and a single +Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core. + +- Board features: + + - RAM: 2GB LPDDR4 + - Storage: + + - SanDisk 16GB eMMC5.1 + - microSD Socket + - Wireless: + + - Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC, + which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2, + and 802.15.4 + - USB: + + - Two USB 2.0 Type C connectors + - Ethernet + - PCI-E M.2 + - Connectors: + + - 40-Pin Dual Row Header + - LEDs: + + - 1x Power status LED + - 2x UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A55 and M33 + + +Supported Features +================== + +The Zephyr mimx93_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v4 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 24 MHz. +Cortex-A55 Core runs up to 1.7 GHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART4. + +Programming and Debugging +************************* + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; cpu 1 release 0xd0000000 + + +Or use the following command to kick zephyr.bin to Cortex-A55 Core0: + +.. code-block:: console + + fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0xd0000000 + + +Use this configuration to run basic Zephyr applications and kernel tests, +for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: mimx93_evk/mimx9352/a55 + :goals: run + +This will build an image with the synchronization sample app, boot it and +display the following ram console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.2.0-8-g1613870534a0 *** + thread_a: Hello World from cpu 0 on mimx93_evk_a55! + thread_b: Hello World from cpu 0 on mimx93_evk_a55! + thread_a: Hello World from cpu 0 on mimx93_evk_a55! + thread_b: Hello World from cpu 0 on mimx93_evk_a55! + +References +========== + +More information can refer to NXP official website: +`NXP website`_. + +.. _NXP website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-93-applications-processor-family-arm-cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93 + + +Using the SOF-specific variant +****************************** + +Purpose +======= + +Since this board doesn't have a DSP, an alternative for people who might be interested +in running SOF on this board had to be found. The alternative consists of running SOF +on an A55 core using Jailhouse as a way to "take away" one A55 core from Linux and +assign it to Zephyr with `SOF`_. + +.. _SOF: + https://github.com/thesofproject/sof + +What is Jailhouse? +================== + +Jailhouse is a light-weight hypervisor that allows the partitioning of hardware resources. +For more details on how this is done and, generally, about Jailhouse, please see: `1`_, +`2`_ and `3`_. The GitHub repo can be found `here`_. + +.. _1: + https://lwn.net/Articles/578295/ + +.. _2: + https://lwn.net/Articles/578852/ + +.. _3: + http://events17.linuxfoundation.org/sites/events/files/slides/ELCE2016-Jailhouse-Tutorial.pdf + +.. _here: + https://github.com/siemens/jailhouse + + +How does it work? +================= +Firstly, we need to explain a few Jailhouse concepts that will be referred to later on: + +* **Cell**: refers to a set of hardware resources that the OS assigned to this + cell can utilize. + +* **Root cell**: refers to the cell in which Linux is running. This is the main cell which + will contain all the hardware resources that Linux will utilize and will be used to assign + resources to the inmates. The inmates CANNOT use resources such as the CPU that haven't been + assigned to the root cell. + +* **Inmate**: refers to any other OS that runs alongside Linux. The resources an inmate will + use are taken from the root cell (the cell Linux is running in). + +SOF+Zephyr will run as an inmate, alongside Linux, on core 1 of the board. This means that +said core will be taken away from Linux and will only be utilized by Zephyr. + +The hypervisor restricts inmate's/root's access to certain hardware resources using +the second-stage translation table which is based on the memory regions described in the +configuration files. Please consider the following scenario: + + Root cell wants to use the **UART** which let's say has its registers mapped in + the **[0x0 - 0x42000000]** region. If the inmate wants to use the same **UART** for + some reason then we'd need to also add this region to inmate's configuration + file and add the **JAILHOUSE_MEM_ROOTSHARED** flag. This flag means that the inmate + is allowed to share this region with the root. If this region is not set in + the inmate's configuration file and Zephyr (running as an inmate here) tries + to access this region this will result in a second stage translation fault. + +Notes: + +* Linux and Zephyr are not aware that they are running alongside each other. + They will only be aware of the cores they have been assigned through the config + files (there's a config file for the root and one for each inmate). + +Architecture overview +===================== + +The architecture overview can be found at this `location`_. (latest status update as of now +and the only one containing diagrams). + +.. _location: + https://github.com/thesofproject/sof/issues/7192 + + +How to use this board? +====================== + +This board has been designed for SOF so it's only intended to be used with SOF. + +TODO: document the SOF build process for this board. For now, the support for +i.MX93 is still in review and has yet to merged on SOF side. diff --git a/boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi b/boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi similarity index 100% rename from boards/arm64/mimx93_evk/mimx93_evk-pinctrl.dtsi rename to boards/nxp/imx93_evk/imx93_evk-pinctrl.dtsi diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts new file mode 100644 index 00000000000000..a519801e875881 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.dts @@ -0,0 +1,120 @@ +/* + * Copyright 2022,2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "imx93_evk-pinctrl.dtsi" + +/ { + model = "NXP i.MX93 A55"; + compatible = "fsl,mimx93"; + + chosen { + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,sram = &sram0; + }; + + cpus { + cpu@0 { + status = "disabled"; + }; + }; + + sram0: memory@d0000000 { + reg = <0xd0000000 DT_SIZE_M(1)>; + }; + + aliases { + led0 = &led_r; + sw0 = &btn_1; + }; + + leds { + compatible = "gpio-leds"; + led_r: led_r { + label = "LED_R"; + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; + }; + led_g: led_g { + label = "LED_G"; + gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; + }; + led_b: led_b { + label = "LED_B"; + gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; + }; + }; + + keys { + compatible = "gpio-keys"; + + btn_1: btn_1{ + label = "BTN1"; + gpios = <&gpio2 23 GPIO_ACTIVE_LOW>; + }; + + btn_2: btn_2{ + label = "BTN2"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&lpuart1 { + status = "disabled"; + current-speed = <115200>; + /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&lpuart2 { + status = "okay"; + current-speed = <115200>; + /* clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>; */ + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + + +&lpi2c1{ + status = "disabled"; + clock-frequency = ; + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&lpi2c2{ + status = "disabled"; + clock-frequency = ; + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&lpspi3 { + status = "disabled"; + clock-frequency = <1000000>; + pinctrl-0 = <&spi3_default>; + pinctrl-names = "default"; +}; + +&gpio1{ + status = "okay"; +}; + +&gpio2{ + status = "okay"; +}; + +&gpio3{ + status = "okay"; +}; + +&gpio4{ + status = "okay"; +}; diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml new file mode 100644 index 00000000000000..3a045828f8423e --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55.yaml @@ -0,0 +1,24 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: imx93_evk/mimx9352/a55 +name: NXP i.MX93 Plus EVK A55 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +supported: + - gpio + - uart + - i2c + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig new file mode 100644 index 00000000000000..6b4743c46430d3 --- /dev/null +++ b/boards/nxp/imx93_evk/imx93_evk_mimx9352_a55_defconfig @@ -0,0 +1,31 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y + +# MMU Options +CONFIG_MAX_XLAT_TABLES=64 + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_KERNEL_DIRECT_MAP=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_CLOCK_CONTROL=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/index.rst b/boards/nxp/index.rst new file mode 100644 index 00000000000000..4ccb239797b54d --- /dev/null +++ b/boards/nxp/index.rst @@ -0,0 +1,10 @@ +.. _boards-nxp: + +NXP Semiconductors +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/lpcxpresso11u68/CMakeLists.txt b/boards/nxp/lpcxpresso11u68/CMakeLists.txt similarity index 100% rename from boards/arm/lpcxpresso11u68/CMakeLists.txt rename to boards/nxp/lpcxpresso11u68/CMakeLists.txt diff --git a/boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 b/boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 new file mode 100644 index 00000000000000..37bf6133254889 --- /dev/null +++ b/boards/nxp/lpcxpresso11u68/Kconfig.lpcxpresso11u68 @@ -0,0 +1,8 @@ +# Copyright (c) 2020, Seagate +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO11U68 + select SOC_LPC11U68 + select SOC_PART_NUMBER_LPC11U68JBD100 diff --git a/boards/arm/lpcxpresso11u68/board.cmake b/boards/nxp/lpcxpresso11u68/board.cmake similarity index 100% rename from boards/arm/lpcxpresso11u68/board.cmake rename to boards/nxp/lpcxpresso11u68/board.cmake diff --git a/boards/nxp/lpcxpresso11u68/board.yml b/boards/nxp/lpcxpresso11u68/board.yml new file mode 100644 index 00000000000000..30712d42e690c1 --- /dev/null +++ b/boards/nxp/lpcxpresso11u68/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso11u68 + vendor: nxp + socs: + - name: lpc11u68 diff --git a/boards/arm/lpcxpresso11u68/doc/index.rst b/boards/nxp/lpcxpresso11u68/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso11u68/doc/index.rst rename to boards/nxp/lpcxpresso11u68/doc/index.rst diff --git a/boards/arm/lpcxpresso11u68/doc/lpcxpresso11u68.jpg b/boards/nxp/lpcxpresso11u68/doc/lpcxpresso11u68.jpg similarity index 100% rename from boards/arm/lpcxpresso11u68/doc/lpcxpresso11u68.jpg rename to boards/nxp/lpcxpresso11u68/doc/lpcxpresso11u68.jpg diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68.dts b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts similarity index 100% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68.dts rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68.dts diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68.yaml b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml similarity index 100% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68.yaml rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68.yaml diff --git a/boards/arm/lpcxpresso11u68/lpcxpresso11u68_defconfig b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68_defconfig similarity index 94% rename from boards/arm/lpcxpresso11u68/lpcxpresso11u68_defconfig rename to boards/nxp/lpcxpresso11u68/lpcxpresso11u68_defconfig index 45ee27f2f72491..523128641eaf8d 100644 --- a/boards/arm/lpcxpresso11u68/lpcxpresso11u68_defconfig +++ b/boards/nxp/lpcxpresso11u68/lpcxpresso11u68_defconfig @@ -2,7 +2,6 @@ CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_GPIO=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SOC_SERIES_LPC11U6X=y # Since the board has little memory (32k), stack sizes are lowered # so that the application has more RAM for itself. CONFIG_MAIN_STACK_SIZE=512 diff --git a/boards/arm/faze/pre_dt_board.cmake b/boards/nxp/lpcxpresso11u68/pre_dt_board.cmake similarity index 100% rename from boards/arm/faze/pre_dt_board.cmake rename to boards/nxp/lpcxpresso11u68/pre_dt_board.cmake diff --git a/boards/arm/lpcxpresso11u68/support/openocd.cfg b/boards/nxp/lpcxpresso11u68/support/openocd.cfg similarity index 100% rename from boards/arm/lpcxpresso11u68/support/openocd.cfg rename to boards/nxp/lpcxpresso11u68/support/openocd.cfg diff --git a/boards/nxp/lpcxpresso51u68/Kconfig.lpcxpresso51u68 b/boards/nxp/lpcxpresso51u68/Kconfig.lpcxpresso51u68 new file mode 100644 index 00000000000000..ff4e5e1d362cd2 --- /dev/null +++ b/boards/nxp/lpcxpresso51u68/Kconfig.lpcxpresso51u68 @@ -0,0 +1,8 @@ +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO51U68 + select SOC_LPC51U68 + select SOC_PART_NUMBER_LPC51U68JBD64 diff --git a/boards/arm/lpcxpresso51u68/board.cmake b/boards/nxp/lpcxpresso51u68/board.cmake similarity index 100% rename from boards/arm/lpcxpresso51u68/board.cmake rename to boards/nxp/lpcxpresso51u68/board.cmake diff --git a/boards/nxp/lpcxpresso51u68/board.yml b/boards/nxp/lpcxpresso51u68/board.yml new file mode 100644 index 00000000000000..7eb0f17095ee19 --- /dev/null +++ b/boards/nxp/lpcxpresso51u68/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso51u68 + vendor: nxp + socs: + - name: lpc51u68 diff --git a/boards/arm/lpcxpresso51u68/doc/index.rst b/boards/nxp/lpcxpresso51u68/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso51u68/doc/index.rst rename to boards/nxp/lpcxpresso51u68/doc/index.rst diff --git a/boards/arm/lpcxpresso51u68/doc/lpcxpresso51u68.jpg b/boards/nxp/lpcxpresso51u68/doc/lpcxpresso51u68.jpg similarity index 100% rename from boards/arm/lpcxpresso51u68/doc/lpcxpresso51u68.jpg rename to boards/nxp/lpcxpresso51u68/doc/lpcxpresso51u68.jpg diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi rename to boards/nxp/lpcxpresso51u68/lpcxpresso51u68-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68.dts b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts similarity index 100% rename from boards/arm/lpcxpresso51u68/lpcxpresso51u68.dts rename to boards/nxp/lpcxpresso51u68/lpcxpresso51u68.dts diff --git a/boards/arm/lpcxpresso51u68/lpcxpresso51u68.yaml b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml similarity index 100% rename from boards/arm/lpcxpresso51u68/lpcxpresso51u68.yaml rename to boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml diff --git a/boards/nxp/lpcxpresso51u68/lpcxpresso51u68_defconfig b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68_defconfig new file mode 100644 index 00000000000000..9cc3359a8902c9 --- /dev/null +++ b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68_defconfig @@ -0,0 +1,6 @@ +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 diff --git a/boards/arm/lpcxpresso51u68/pre_dt_board.cmake b/boards/nxp/lpcxpresso51u68/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso51u68/pre_dt_board.cmake rename to boards/nxp/lpcxpresso51u68/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso54114/Kconfig.defconfig b/boards/nxp/lpcxpresso54114/Kconfig.defconfig new file mode 100644 index 00000000000000..a7f124a048ed01 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/Kconfig.defconfig @@ -0,0 +1,15 @@ +# LPCXpresso54114 board +# +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Place size restrictions on first image if dual core is enabled +if SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_LPC54114_M4 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # SECOND_CORE_MCUX && BOARD_LPCXPRESSO54114_LPC54114_M4 diff --git a/boards/nxp/lpcxpresso54114/Kconfig.lpcxpresso54114 b/boards/nxp/lpcxpresso54114/Kconfig.lpcxpresso54114 new file mode 100644 index 00000000000000..8442760ccda0fd --- /dev/null +++ b/boards/nxp/lpcxpresso54114/Kconfig.lpcxpresso54114 @@ -0,0 +1,9 @@ +# LPCXpresso54114 board + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO54114 + select SOC_LPC54114_M4 if BOARD_LPCXPRESSO54114_LPC54114_M4 + select SOC_LPC54114_M0 if BOARD_LPCXPRESSO54114_LPC54114_M0 + select SOC_PART_NUMBER_LPC54114J256BD64 diff --git a/boards/nxp/lpcxpresso54114/board.cmake b/boards/nxp/lpcxpresso54114/board.cmake new file mode 100644 index 00000000000000..0a88f68d928309 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/board.cmake @@ -0,0 +1,13 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(BOARD_LPCXPRESSO54114_LPC54114_M4 OR CONFIG_SECOND_CORE_MCUX) + board_runner_args(jlink "--device=LPC54114J256_M4" "--reset-after-load") +elseif(BOARD_LPCXPRESSO54114_LPC54114_M0) + board_runner_args(jlink "--device=LPC54114J256_M0" "--reset-after-load") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/nxp/lpcxpresso54114/board.yml b/boards/nxp/lpcxpresso54114/board.yml new file mode 100644 index 00000000000000..64477bf2ac8ed6 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso54114 + vendor: nxp + socs: + - name: lpc54114 diff --git a/boards/nxp/lpcxpresso54114/doc/index.rst b/boards/nxp/lpcxpresso54114/doc/index.rst new file mode 100644 index 00000000000000..644de94e415fa0 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/doc/index.rst @@ -0,0 +1,218 @@ +.. _lpcxpresso54114: + +NXP LPCXPRESSO54114 +################### + +Overview +******** + +The LPCXpresso54114 board has been developed by NXP to enable evaluation of and +prototyping with the low-power LPC54110 family of MCUs. LPCXpresso* is a +low-cost development platform available from NXP supporting NXP's ARM-based +microcontrollers. LPCXpresso is an end-to-end solution enabling embedded +engineers to develop their applications from initial evaluation to final +production. + +.. image:: lpcxpresso54114_m4.jpg + :align: center + :alt: LPCXPRESSO54114 + +Hardware +******** + +- LPC54114 dual-core (M4F and dual M0) MCU running at up to 100 MHz +- On-board high-speed USB based debug probe with CMSIS-DAP and J-Link protocol + support, can debug the on-board LPC54114 or an external target +- External debug probe option +- Tri-color LED, target Reset, ISP & interrupt/user buttons for easy testing of + software functionality +- Expansion options based on Arduino UNO and Pmod™, plus additional expansion + port pins +- On-board 1.8 V and 3.3 V regulators plus external power supply option +- 8 Mb Macronix MX25R SPI flash +- Built-in MCU power consumption and supply voltage measurement +- UART, I²C and SPI port bridging from LPC54114 target to USB via the on-board + debug probe +- FTDI UART connector + +For more information about the LPC54114 SoC and LPCXPRESSO54114 board: + +- `LPC54114 SoC Website`_ +- `LPC54114 Datasheet`_ +- `LPC54114 Reference Manual`_ +- `LPCXPRESSO54114 Website`_ +- `LPCXPRESSO54114 User Guide`_ +- `LPCXPRESSO54114 Schematics`_ + +Supported Features +================== + +The lpcxpresso54114 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| IAP | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration for each core can be found in the defconfig files: + + `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig` + `boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The LPC54114 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_0 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_1 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_18 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO0_19 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO0_20 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO0_25 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO0_26 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO0_29 | GPIO | RED LED | ++---------+-----------------+----------------------------+ +| PIO1_1 | SPI | SPI SSEL2 | ++---------+-----------------+----------------------------+ +| PIO1_9 | GPIO | BLUE_LED | ++---------+-----------------+----------------------------+ +| PIO1_10 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ + +System Clock +============ + +The LPC54114 SoC is configured to use the internal FRO at 48MHz as a source for +the system clock. Other sources for the system clock are provided in the SOC, +depending on your system requirements. + +Serial Port +=========== + +The LPC54114 SoC has 8 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, +however the :ref:`pyocd-debug-host-tools` do not support this probe so you must +reconfigure the board for one of the following debug probes instead. + +:ref:`lpclink2-jlink-onboard-debug-probe` +----------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program +the J-Link firmware. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the LPC-Link2 +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J5 + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso54114/lpc54114/m4 + :goals: flash + +Open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! lpcxpresso54114_m4 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso54114/lpc54114/m4 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! lpcxpresso54114_m4 + +.. _LPC54114 SoC Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc54000-series-cortex-m4-mcus/low-power-microcontrollers-mcus-based-on-arm-cortex-m4-cores-with-optional-cortex-m0-plus-co-processor:LPC541XX + +.. _LPC54114 Datasheet: + https://www.nxp.com/docs/en/data-sheet/LPC5411X.pdf + +.. _LPC54114 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=UM10914 + +.. _LPCXPRESSO54114 Website: + https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/lpcxpresso-boards/lpcxpresso54114-board:OM13089 + +.. _LPCXPRESSO54114 User Guide: + https://www.nxp.com/webapp/Download?colCode=UM10973 + +.. _LPCXPRESSO54114 Schematics: + https://www.nxp.com/downloads/en/design-support/LPCX5411x_Schematic_Rev_A1.pdf diff --git a/boards/arm/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg b/boards/nxp/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg similarity index 100% rename from boards/arm/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg rename to boards/nxp/lpcxpresso54114/doc/lpcxpresso54114_m4.jpg diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi b/boards/nxp/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi rename to boards/nxp/lpcxpresso54114/lpcxpresso54114-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114.dtsi b/boards/nxp/lpcxpresso54114/lpcxpresso54114.dtsi similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114.dtsi rename to boards/nxp/lpcxpresso54114/lpcxpresso54114.dtsi diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m0.dts b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114_m0.dts rename to boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.dts diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml new file mode 100644 index 00000000000000..8f99d4bbd9db94 --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml @@ -0,0 +1,20 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso54114/lpc54114/m0 +name: NXP LPCXpresso54114 M0 +type: mcu +arch: arm +ram: 32 +flash: 64 +testing: + ignore_tags: + - net +toolchain: + - xtools + - zephyr + - gnuarmemb +vendor: nxp diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig new file mode 100644 index 00000000000000..9242d2359a0dab --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig @@ -0,0 +1,11 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_USE_SEGGER_RTT=y +CONFIG_SERIAL=n +CONFIG_GPIO=n +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_PINCTRL=y diff --git a/boards/arm/lpcxpresso54114/lpcxpresso54114_m4.dts b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts similarity index 100% rename from boards/arm/lpcxpresso54114/lpcxpresso54114_m4.dts rename to boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.dts diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml new file mode 100644 index 00000000000000..c539b58e4425dc --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso54114/lpc54114/m4 +name: NXP LPCXpresso54114 M4 +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - arduino_i2c + - arduino_spi + - gpio + - i2c + - spi +vendor: nxp diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig new file mode 100644 index 00000000000000..921c68d49ade9e --- /dev/null +++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig @@ -0,0 +1,15 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/lpcxpresso54114/pre_dt_board.cmake b/boards/nxp/lpcxpresso54114/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso54114/pre_dt_board.cmake rename to boards/nxp/lpcxpresso54114/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso55s06/Kconfig.defconfig b/boards/nxp/lpcxpresso55s06/Kconfig.defconfig new file mode 100644 index 00000000000000..9d9e527b56e443 --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/Kconfig.defconfig @@ -0,0 +1,16 @@ +# LPCXpresso55S06 board + +# Copyright (c) 2022 metraTec +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S06 + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S06 diff --git a/boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 b/boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 new file mode 100644 index 00000000000000..b810ca2a91fc95 --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/Kconfig.lpcxpresso55s06 @@ -0,0 +1,8 @@ +# Copyright (c) 2022 metraTec +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S06 + select SOC_LPC55S06 + select SOC_PART_NUMBER_LPC55S06JBD64 diff --git a/boards/arm/lpcxpresso55s06/board.cmake b/boards/nxp/lpcxpresso55s06/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s06/board.cmake rename to boards/nxp/lpcxpresso55s06/board.cmake diff --git a/boards/nxp/lpcxpresso55s06/board.yml b/boards/nxp/lpcxpresso55s06/board.yml new file mode 100644 index 00000000000000..a15c5a1da8522d --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s06 + vendor: nxp + socs: + - name: lpc55s06 diff --git a/boards/arm/lpcxpresso55s06/doc/index.rst b/boards/nxp/lpcxpresso55s06/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s06/doc/index.rst rename to boards/nxp/lpcxpresso55s06/doc/index.rst diff --git a/boards/arm/lpcxpresso55s06/doc/lpcxpress55s06.jpg b/boards/nxp/lpcxpresso55s06/doc/lpcxpress55s06.jpg similarity index 100% rename from boards/arm/lpcxpresso55s06/doc/lpcxpress55s06.jpg rename to boards/nxp/lpcxpresso55s06/doc/lpcxpress55s06.jpg diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06.dts b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06.dts rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06.dts diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06.yaml b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06.yaml rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml diff --git a/boards/arm/lpcxpresso55s06/lpcxpresso55s06_common.dtsi b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s06/lpcxpresso55s06_common.dtsi rename to boards/nxp/lpcxpresso55s06/lpcxpresso55s06_common.dtsi diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig new file mode 100644 index 00000000000000..6fcd01d4551ae3 --- /dev/null +++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06_defconfig @@ -0,0 +1,15 @@ +# +# Copyright (c) 2022 metraTec +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_ARM_MPU=y + +CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s06/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s06/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s06/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s06/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso55s16/Kconfig.defconfig b/boards/nxp/lpcxpresso55s16/Kconfig.defconfig new file mode 100644 index 00000000000000..5b29155063af14 --- /dev/null +++ b/boards/nxp/lpcxpresso55s16/Kconfig.defconfig @@ -0,0 +1,19 @@ +# LPCXpresso55S16 board + +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S16 + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S16 diff --git a/boards/nxp/lpcxpresso55s16/Kconfig.lpcxpresso55s16 b/boards/nxp/lpcxpresso55s16/Kconfig.lpcxpresso55s16 new file mode 100644 index 00000000000000..38928131a5e722 --- /dev/null +++ b/boards/nxp/lpcxpresso55s16/Kconfig.lpcxpresso55s16 @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Henrik Brix Andersen +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S16 + select SOC_LPC55S16 + select SOC_PART_NUMBER_LPC55S16JBD100 diff --git a/boards/arm/lpcxpresso55s16/board.cmake b/boards/nxp/lpcxpresso55s16/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s16/board.cmake rename to boards/nxp/lpcxpresso55s16/board.cmake diff --git a/boards/nxp/lpcxpresso55s16/board.yml b/boards/nxp/lpcxpresso55s16/board.yml new file mode 100644 index 00000000000000..5b4c627af1c4f5 --- /dev/null +++ b/boards/nxp/lpcxpresso55s16/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s16 + vendor: nxp + socs: + - name: lpc55s16 diff --git a/boards/arm/lpcxpresso55s16/doc/index.rst b/boards/nxp/lpcxpresso55s16/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s16/doc/index.rst rename to boards/nxp/lpcxpresso55s16/doc/index.rst diff --git a/boards/arm/lpcxpresso55s16/doc/lpcxpresso55S16.jpg b/boards/nxp/lpcxpresso55s16/doc/lpcxpresso55S16.jpg similarity index 100% rename from boards/arm/lpcxpresso55s16/doc/lpcxpresso55S16.jpg rename to boards/nxp/lpcxpresso55s16/doc/lpcxpresso55S16.jpg diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16.dts b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16.dts rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16.yaml rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16_common.dtsi rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16_common.dtsi diff --git a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_defconfig b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig similarity index 76% rename from boards/arm/lpcxpresso55s16/lpcxpresso55s16_defconfig rename to boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig index 44af7c468e1e2b..e327fa910d74e3 100644 --- a/boards/arm/lpcxpresso55s16/lpcxpresso55s16_defconfig +++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S16=y -CONFIG_BOARD_LPCXPRESSO55S16=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/lpcxpresso55s16/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s16/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s16/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s16/pre_dt_board.cmake diff --git a/boards/nxp/lpcxpresso55s28/Kconfig.defconfig b/boards/nxp/lpcxpresso55s28/Kconfig.defconfig new file mode 100644 index 00000000000000..5642f6b9a0f630 --- /dev/null +++ b/boards/nxp/lpcxpresso55s28/Kconfig.defconfig @@ -0,0 +1,44 @@ +# LPCXpresso55S28 board + +# Copyright (c) 2020 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S28 + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # FXOS8700 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_LPCXPRESSO55S28 && TRUSTED_EXECUTION_SECURE + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S28 diff --git a/boards/nxp/lpcxpresso55s28/Kconfig.lpcxpresso55s28 b/boards/nxp/lpcxpresso55s28/Kconfig.lpcxpresso55s28 new file mode 100644 index 00000000000000..7947180bdf4b77 --- /dev/null +++ b/boards/nxp/lpcxpresso55s28/Kconfig.lpcxpresso55s28 @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Lemonbeat GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S28 + select SOC_LPC55S28 + select SOC_PART_NUMBER_LPC55S28JBD100 diff --git a/boards/arm/lpcxpresso55s28/board.cmake b/boards/nxp/lpcxpresso55s28/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s28/board.cmake rename to boards/nxp/lpcxpresso55s28/board.cmake diff --git a/boards/nxp/lpcxpresso55s28/board.yml b/boards/nxp/lpcxpresso55s28/board.yml new file mode 100644 index 00000000000000..d4309c4e3df01d --- /dev/null +++ b/boards/nxp/lpcxpresso55s28/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s28 + vendor: nxp + socs: + - name: lpc55s28 diff --git a/boards/arm/lpcxpresso55s28/doc/LPC55S28-EVK.jpg b/boards/nxp/lpcxpresso55s28/doc/LPC55S28-EVK.jpg similarity index 100% rename from boards/arm/lpcxpresso55s28/doc/LPC55S28-EVK.jpg rename to boards/nxp/lpcxpresso55s28/doc/LPC55S28-EVK.jpg diff --git a/boards/arm/lpcxpresso55s28/doc/index.rst b/boards/nxp/lpcxpresso55s28/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s28/doc/index.rst rename to boards/nxp/lpcxpresso55s28/doc/index.rst diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28.dts b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28.dts rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28.dts diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28.yaml b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28.yaml rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_common.dtsi b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28_common.dtsi rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28_common.dtsi diff --git a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig similarity index 78% rename from boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig rename to boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig index 8ce8f718d7e527..1a23b7b3d78ff5 100644 --- a/boards/arm/lpcxpresso55s28/lpcxpresso55s28_defconfig +++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig @@ -1,12 +1,10 @@ # # Copyright (c) 2020 Lemonbeat GmbH +# Copyright 2024 NXP # # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_LPC55XXX=y -CONFIG_SOC_LPC55S28=y -CONFIG_BOARD_LPCXPRESSO55S28=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/lpcxpresso55s28/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s28/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s28/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s28/pre_dt_board.cmake diff --git a/boards/arm/lpcxpresso55s36/Kconfig.defconfig b/boards/nxp/lpcxpresso55s36/Kconfig.defconfig similarity index 100% rename from boards/arm/lpcxpresso55s36/Kconfig.defconfig rename to boards/nxp/lpcxpresso55s36/Kconfig.defconfig diff --git a/boards/nxp/lpcxpresso55s36/Kconfig.lpcxpresso55s36 b/boards/nxp/lpcxpresso55s36/Kconfig.lpcxpresso55s36 new file mode 100644 index 00000000000000..61e25cddbe828b --- /dev/null +++ b/boards/nxp/lpcxpresso55s36/Kconfig.lpcxpresso55s36 @@ -0,0 +1,6 @@ +# Copyright 2022, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S36 + select SOC_LPC55S36 + select SOC_PART_NUMBER_LPC55S36JBD100 diff --git a/boards/arm/lpcxpresso55s36/board.cmake b/boards/nxp/lpcxpresso55s36/board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s36/board.cmake rename to boards/nxp/lpcxpresso55s36/board.cmake diff --git a/boards/nxp/lpcxpresso55s36/board.yml b/boards/nxp/lpcxpresso55s36/board.yml new file mode 100644 index 00000000000000..e888d7688156d2 --- /dev/null +++ b/boards/nxp/lpcxpresso55s36/board.yml @@ -0,0 +1,5 @@ +board: + name: lpcxpresso55s36 + vendor: nxp + socs: + - name: lpc55s36 diff --git a/boards/arm/lpcxpresso55s36/doc/index.rst b/boards/nxp/lpcxpresso55s36/doc/index.rst similarity index 100% rename from boards/arm/lpcxpresso55s36/doc/index.rst rename to boards/nxp/lpcxpresso55s36/doc/index.rst diff --git a/boards/arm/lpcxpresso55s36/doc/lpcxpresso55S36.jpg b/boards/nxp/lpcxpresso55s36/doc/lpcxpresso55S36.jpg similarity index 100% rename from boards/arm/lpcxpresso55s36/doc/lpcxpresso55S36.jpg rename to boards/nxp/lpcxpresso55s36/doc/lpcxpresso55S36.jpg diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s36/lpcxpresso55s36-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36.dts b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts similarity index 100% rename from boards/arm/lpcxpresso55s36/lpcxpresso55s36.dts rename to boards/nxp/lpcxpresso55s36/lpcxpresso55s36.dts diff --git a/boards/arm/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml similarity index 100% rename from boards/arm/lpcxpresso55s36/lpcxpresso55s36.yaml rename to boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig new file mode 100644 index 00000000000000..9aaf3ff8452c4f --- /dev/null +++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36_defconfig @@ -0,0 +1,15 @@ +# +# Copyright 2022, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_ARM_MPU=y + +CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s36/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s36/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s36/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s36/pre_dt_board.cmake diff --git a/boards/arm/lpcxpresso55s69/CMakeLists.txt b/boards/nxp/lpcxpresso55s69/CMakeLists.txt similarity index 100% rename from boards/arm/lpcxpresso55s69/CMakeLists.txt rename to boards/nxp/lpcxpresso55s69/CMakeLists.txt diff --git a/boards/nxp/lpcxpresso55s69/Kconfig.defconfig b/boards/nxp/lpcxpresso55s69/Kconfig.defconfig new file mode 100644 index 00000000000000..5a48b7afe24029 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/Kconfig.defconfig @@ -0,0 +1,59 @@ +# Copyright 2019,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LPCXPRESSO55S69 + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # FXOS8700 + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 && TRUSTED_EXECUTION_SECURE + +if TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 + +config FLASH_LOAD_OFFSET + default 0x50000 if (!TFM_BL2 && BUILD_WITH_TFM) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default 0x40000 if (!TFM_BL2 && BUILD_WITH_TFM) + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # TRUSTED_EXECUTION_NONSECURE || BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 + +choice TFM_PROFILE_TYPE + depends on BUILD_WITH_TFM + default TFM_PROFILE_TYPE_MEDIUM +endchoice + +if BOOTLOADER_MCUBOOT +choice MCUBOOT_BOOTLOADER_MODE + # Board only supports MCUBoot via "upgrade only" method: + default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY +endchoice +endif #BOOTLOADER_MCUBOOT + +endif # BOARD_LPCXPRESSO55S69 diff --git a/boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 b/boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 new file mode 100644 index 00000000000000..c047500eca1a48 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/Kconfig.lpcxpresso55s69 @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LPCXPRESSO55S69 + select SOC_LPC55S69_CPU0 if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 || \ + BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS + select SOC_LPC55S69_CPU1 if BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 + select SOC_PART_NUMBER_LPC55S69JBD100 diff --git a/boards/nxp/lpcxpresso55s69/board.cmake b/boards/nxp/lpcxpresso55s69/board.cmake new file mode 100644 index 00000000000000..137b2e614f3aaf --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/board.cmake @@ -0,0 +1,30 @@ +# +# Copyright 2019, 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +## DAP Link implementation in pyocd is underway, +## until then jlink can be used or copy image to storage + +if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR + CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0_NS OR + CONFIG_SECOND_CORE_MCUX) + board_runner_args(jlink "--device=LPC55S69_M33_0") + board_runner_args(linkserver "--device=LPC55S69:LPCXpresso55S69") + board_runner_args(linkserver "--override=/device/memory/0/flash-driver=LPC55xx_S.cfx") + board_runner_args(linkserver "--override=/device/memory/0/location=0x10000000") +elseif(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1) + board_runner_args(jlink "--device=LPC55S69_M33_1") +endif() + +board_runner_args(pyocd "--target=lpc55s69") + +if(CONFIG_BUILD_WITH_TFM) + set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex) +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/lpcxpresso55s69/board.yml b/boards/nxp/lpcxpresso55s69/board.yml new file mode 100644 index 00000000000000..605ab7b3e9f509 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/board.yml @@ -0,0 +1,8 @@ +board: + name: lpcxpresso55s69 + vendor: nxp + socs: + - name: lpc55s69 + variants: + - name: "ns" + cpucluster: 'cpu0' diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst new file mode 100644 index 00000000000000..449d80b7af6766 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/doc/index.rst @@ -0,0 +1,413 @@ +.. _lpcxpresso55s69: + +NXP LPCXPRESSO55S69 +################### + +Overview +******** + +The LPCXpresso55S69 development board provides the ideal platform for evaluation +of and development with the LPC55S6x MCU based on the Arm® Cortex®-M33 +architecture. The board includes a high performance onboard debug probe, audio +subsystem, and accelerometer, with several options for adding off-the-shelf +add-on boards for networking, sensors, displays, and other interfaces. + +.. image:: lpcxpresso55s69.jpg + :align: center + :alt: LPCXPRESSO55S69 + +Hardware +******** + +- LPC55S69 dual core Arm Cortex-M33 microcontroller running at up to 100 MHz +- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP and SEGGER J-Link + protocol options +- UART and SPI port bridging from LPC55S69 target to USB via the onboard debug + probe +- Hardware support for external debug probe +- 3 x user LEDs, plus Reset, ISP (3) and user buttons +- Micro SD card slot (4-bit SDIO) +- NXP MMA8652FCR1 accelerometer +- Stereo audio codec with line in/out +- High and full speed USB ports with micro A/B connector for host or device + functionality +- MikroEletronika Click expansion option +- LPCXpresso-V3 expansion option compatible with Arduino UNO +- PMod compatible expansion / host connector + +For more information about the LPC55S69 SoC and LPCXPRESSO55S69 board, see: + +- `LPC55S69 SoC Website`_ +- `LPC55S69 Datasheet`_ +- `LPC55S69 Reference Manual`_ +- `LPCXPRESSO55S69 Website`_ +- `LPCXPRESSO55S69 User Guide`_ +- `LPCXPRESSO55S69 Schematics`_ +- `LPCXPRESSO55S69 Debug Firmware`_ + +Supported Features +================== + +NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx +series of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire LPC55xx series. NXP prioritizes enabling +this board with new support for Zephyr features. The lpcxpresso55s69 board +configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WWDT | on-chip | windowed watchdog timer | ++-----------+------------+-------------------------------------+ +| TrustZone | on-chip | Trusted Firmware-M | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| MAILBOX | on-chip | ipm | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| USB HS | on-chip | USB High Speed device | ++-----------+------------+-------------------------------------+ +| USB FS | on-chip | USB Full Speed device | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| IAP | on-chip | flash programming | ++-----------+------------+-------------------------------------+ +| SDIF | on-chip | sdhc | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma (on CPU0) | ++-----------+------------+-------------------------------------+ + +Targets available +================== + +The default configuration file +``boards/arm/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig`` +only enables the first core. +CPU0 is the only target that can run standalone. + +- *lpcxpresso55s69/lpc55s69/cpu0* secure (S) address space for CPU0 +- *lpcxpresso55s69/lpc55s69/cpu0/ns* non-secure (NS) address space for CPU0 +- *lpcxpresso55s69/lpc55s69/cpu1* CPU1 target, no security extensions + +NS target for CPU0 does not work correctly without a secure image to configure +the system, then hand execution over to the NS environment. To enable a secure +image, run any of the ``tfm_integration`` samples. When using the NS target +``CONFIG_BUILD_WITH_TFM`` is always enabled to ensure that a valid S image is +included during the build process. + +CPU1 does not work without CPU0 enabling it. +To enable it, run one of the following samples in ``subsys\ipc``: +- ``ipm_mcux`` +- ``openamp`` + +Connections and IOs +=================== + +The LPC55S69 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_26 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO0_27 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_29 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_30 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO1_1 | SPI | SPI SSEL | ++---------+-----------------+----------------------------+ +| PIO1_2 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO1_3 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO1_4 | GPIO | RED LED | ++---------+-----------------+----------------------------+ +| PIO1_6 | GPIO | BLUE_LED | ++---------+-----------------+----------------------------+ +| PIO1_7 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ +| PIO1_20 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO1_21 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO1_24 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_20 | I2S | I2S DATAOUT | ++---------+-----------------+----------------------------+ +| PIO0_19 | I2S | I2S TX WS | ++---------+-----------------+----------------------------+ +| PIO0_21 | I2S | I2S TX SCK | ++---------+-----------------+----------------------------+ +| PIO1_13 | I2S | I2S DATAIN | ++---------+-----------------+----------------------------+ +| PIO0_15 | SCT0_OUT2 | PWM | ++---------+-----------------+----------------------------+ +| PIO0_24 | SD0_D0 | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_25 | SD0_D1 | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_31 | SD0_D2 | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_7 | SD0_CLK | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_8 | SD0_CMD | SDHC | ++---------+-----------------+----------------------------+ +| PIO0_9 | SD0_POW_EN | SDHC | ++---------+-----------------+----------------------------+ +| PIO1_0 | SD0_D3 | SDHC | ++---------+-----------------+----------------------------+ + +Memory mappings +=============== + +There are multiple memory configurations, they all start from the +MCUboot partitioning which looks like the table below + ++----------+------------------+---------------------------------+ +| Name | Address[Size] | Comment | ++==========+==================+=================================+ +| boot | 0x00000000[32K] | Bootloader | ++----------+------------------+---------------------------------+ +| slot0 | 0x00008000[160k] | Image that runs after boot | ++----------+------------------+---------------------------------+ +| slot0_ns | 0x00030000[96k] | Second image, core 1 or NS | ++----------+------------------+---------------------------------+ +| slot1 | 0x00048000[160k] | Updates slot0 image | ++----------+------------------+---------------------------------+ +| slot1_ns | 0x00070000[96k] | Updates slot0_ns image | ++----------+------------------+---------------------------------+ +| storage | 0x00088000[50k] | File system, persistent storage | ++----------+------------------+---------------------------------+ + +See below examples of how this partitioning is used + +Trusted Execution +***************** + ++-----------+------------------+--------------------+ +| Memory | Address[Size] | Comment | ++===========+==================+====================+ +| MCUboot | 0x00000000[32K] | Secure bootloader | ++-----------+------------------+--------------------+ +| TFM_S | 0x00008000[160k] | Secure image | ++-----------+------------------+--------------------+ +| Zephyr_NS | 0x00030000[96k] | Non-Secure image | ++-----------+------------------+--------------------+ +| storage | 0x00088000[50k] | Persistent storage | ++-----------+------------------+--------------------+ + ++----------------+------------------+-------------------+ +| RAM | Address[Size] | Comment | ++================+==================+===================+ +| secure_ram | 0x20000000[136k] | Secure memory | ++----------------+------------------+-------------------+ +| non_secure_ram | 0x20022000[136k] | Non-Secure memory | ++----------------+------------------+-------------------+ + +Dual Core samples +***************** + ++--------+------------------+----------------------------+ +| Memory | Address[Size] | Comment | ++========+==================+============================+ +| CPU0 | 0x00000000[630K] | CPU0, can access all flash | ++--------+------------------+----------------------------+ +| CPU1 | 0x00030000[96k] | CPU1, has no MPU | ++--------+------------------+----------------------------+ + ++-------+------------------+-----------------------+ +| RAM | Address[Size] | Comment | ++=======+==================+=======================+ +| sram0 | 0x20000000[64k] | CPU0 memory | ++-------+------------------+-----------------------+ +| sram3 | 0x20030000[64k] | CPU1 memory | ++-------+------------------+-----------------------+ +| sram4 | 0x20040000[16k] | Mailbox/shared memory | ++-------+------------------+-----------------------+ + +System Clock +============ + +The LPC55S69 SoC is configured to use PLL1 clocked from the external 16MHz +crystal, running at 144MHz as a source for the system clock. When the flash +controller is enabled, the core clock will be reduced to 96MHz. The application +may reconfigure clocks after initialization, provided that the core clock is +always set to 96MHz when flash programming operations are performed. + +Serial Port +=========== + +The LPC55S69 SoC has 8 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe, +however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you +must reconfigure the board for one of the following debug probes instead. + +:ref:`lpclink2-jlink-onboard-debug-probe` +----------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program +the J-Link firmware. Please make sure you have the latest firmware for this +board. + +:ref:`lpclink2-cmsis-onboard-debug-probe` +----------------------------------------- + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware` + +:ref:`opensda-daplink-onboard-debug-probe` +------------------------------------------ + +PyOCD support for this board is ongoing and not yet available. +To use DAPLink's flash memory programming on this board, follow the instructions +for `updating LPCXpresso firmware`_. + +Configuring a Console +===================== + +Connect a USB cable from your PC to P6, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso55s69/lpc55s69/cpu0 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0 ***** + Hello World! lpcxpresso55s69_cpu0 + +Building and flashing secure/non-secure with Arm |reg| TrustZone |reg| +---------------------------------------------------------------------- +The TF-M integration samples can be run using the ``lpcxpresso55s69_ns`` target. +To run we need to manually flash the resulting image (``tfm_merged.hex``) with +a J-Link as follows (reset and erase are for recovering a locked core): + + .. code-block:: console + + JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 + J-Link>r + J-Link>erase + J-Link>loadfile build/zephyr/tfm_merged.hex + +We need to reset the board manually after flashing the image to run this code. + +Building a dual-core image +-------------------------- +The dual-core samples are run using ``lpcxpresso55s69_cpu0`` target, +``lpcxpresso55s69_cpu1`` will be automatically built and merged in a single +image when ``SECOND_CORE_MCUX`` is selected. +To run we need to manually flash the resulting image (``multicore.bin``) with a +J-Link as follows (reset and erase are for recovering a locked core): + + .. code-block:: console + + JLinkExe -device lpc55s69 -if swd -speed 2000 -autoconnect 1 + J-Link>r + J-Link>erase + J-Link>loadfile build/multicore.bin + +We need to reset the board manually after flashing the image to run this code. + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lpcxpresso55s69_cpu0 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS zephyr-v1.14.0 ***** + Hello World! lpcxpresso55s69_cpu0 + +.. _LPC55S69 SoC Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x + +.. _LPC55S69 Datasheet: + https://www.nxp.com/docs/en/nxp/data-sheets/LPC55S6x_DS.pdf + +.. _LPC55S69 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=UM11126 + +.. _LPCXPRESSO55S69 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/lpcxpresso55s69-development-board:LPC55S69-EVK + +.. _LPCXPRESSO55S69 User Guide: + https://www.nxp.com/webapp/Download?colCode=UM11158 + +.. _LPCXPRESSO55S69 Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _LPCXPRESSO55S69 Schematics: + https://www.nxp.com/webapp/Download?colCode=LPC55S69-SCH + +.. _updating LPCXpresso firmware: + https://os.mbed.com/teams/NXP/wiki/Updating-LPCXpresso-firmware diff --git a/boards/arm/lpcxpresso55s69/doc/lpcxpresso55s69.jpg b/boards/nxp/lpcxpresso55s69/doc/lpcxpresso55s69.jpg similarity index 100% rename from boards/arm/lpcxpresso55s69/doc/lpcxpresso55s69.jpg rename to boards/nxp/lpcxpresso55s69/doc/lpcxpresso55s69.jpg diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69-pinctrl.dtsi diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69.dtsi b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69.dtsi rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69.dtsi diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig new file mode 100644 index 00000000000000..32700cd4833b19 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_defconfig @@ -0,0 +1,12 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +# Common Kconfigs for all board targets +# + +CONFIG_GPIO=y +CONFIG_PINCTRL=y + +CONFIG_RUNTIME_NMI=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0.dts rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml new file mode 100644 index 00000000000000..ae375cdeb66989 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml @@ -0,0 +1,30 @@ +# +# Copyright 2019, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso55s69/lpc55s69/cpu0 +name: NXP LPCXpresso55S69 (CPU0) +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - arduino_i2c + - arduino_serial + - arduino_spi + - counter + - gpio + - i2c + - i2s + - spi + - sdhc + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig new file mode 100644 index 00000000000000..966a0228f10bdf --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_defconfig @@ -0,0 +1,16 @@ +# +# Copyright 2019,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_ARM_TRUSTZONE_M=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69_ns.dts rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.dts diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml new file mode 100644 index 00000000000000..5d76704ba7b546 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml @@ -0,0 +1,25 @@ +# +# Copyright 2019, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso55s69/lpc55s69/cpu0/ns +name: NXP LPCXpresso55S69 (Non-Secure) +type: mcu +arch: arm +ram: 136 +flash: 96 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - arduino_spi + - counter + - dma + - gpio + - spi + - watchdog +vendor: nxp diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig new file mode 100644 index 00000000000000..b93da92c709106 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns_defconfig @@ -0,0 +1,19 @@ +# +# Copyright 2019,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +CONFIG_ARM_MPU=n + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_NONSECURE=y +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_BUILD_WITH_TFM=y + +CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts similarity index 100% rename from boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.dts rename to boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.dts diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml new file mode 100644 index 00000000000000..4d6f1c70ab8e89 --- /dev/null +++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml @@ -0,0 +1,19 @@ +# +# Copyright 2019, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: lpcxpresso55s69/lpc55s69/cpu1 +name: NXP LPCXpresso55S69 (CPU1) +type: mcu +arch: arm +ram: 64 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio +vendor: nxp diff --git a/boards/arm/lpcxpresso55s69/pinmux.c b/boards/nxp/lpcxpresso55s69/pinmux.c similarity index 100% rename from boards/arm/lpcxpresso55s69/pinmux.c rename to boards/nxp/lpcxpresso55s69/pinmux.c diff --git a/boards/arm/lpcxpresso55s69/pre_dt_board.cmake b/boards/nxp/lpcxpresso55s69/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso55s69/pre_dt_board.cmake rename to boards/nxp/lpcxpresso55s69/pre_dt_board.cmake diff --git a/boards/arm64/mimx93_evk/CMakeLists.txt b/boards/nxp/ls1046ardb/CMakeLists.txt similarity index 100% rename from boards/arm64/mimx93_evk/CMakeLists.txt rename to boards/nxp/ls1046ardb/CMakeLists.txt diff --git a/boards/nxp/ls1046ardb/Kconfig.ls1046ardb b/boards/nxp/ls1046ardb/Kconfig.ls1046ardb new file mode 100644 index 00000000000000..4b671144be722a --- /dev/null +++ b/boards/nxp/ls1046ardb/Kconfig.ls1046ardb @@ -0,0 +1,8 @@ +# +# Copyright 2021,2024 NXP +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_LS1046ARDB + select SOC_LS1046A + select SOC_PART_NUMBER_LS1046A diff --git a/boards/arm64/mimx8mp_evk/board.cmake b/boards/nxp/ls1046ardb/board.cmake similarity index 100% rename from boards/arm64/mimx8mp_evk/board.cmake rename to boards/nxp/ls1046ardb/board.cmake diff --git a/boards/nxp/ls1046ardb/board.yml b/boards/nxp/ls1046ardb/board.yml new file mode 100644 index 00000000000000..9ad691704808a1 --- /dev/null +++ b/boards/nxp/ls1046ardb/board.yml @@ -0,0 +1,9 @@ +board: + name: ls1046ardb + vendor: nxp + socs: + - name: ls1046a + variants: + - name: smp + variants: + - name: 4cores diff --git a/boards/nxp/ls1046ardb/doc/index.rst b/boards/nxp/ls1046ardb/doc/index.rst new file mode 100644 index 00000000000000..c6065c4f312a5a --- /dev/null +++ b/boards/nxp/ls1046ardb/doc/index.rst @@ -0,0 +1,215 @@ +.. _nxp_ls1046ardb: + +NXP LS1046A RDB +################################# + +Overview +******** + +The LS1046A reference design board (RDB) is a high-performance computing, +evaluation, and development platform that supports the Layerscape LS1046A +architecture processor. The LS1046ARDB board supports the Layerscape LS1046A +processor and is optimized to support the DDR4 memory and a full complement +of high-speed SerDes ports. + +The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72 +cores with packet processing acceleration and high-speed peripherals. The +impressive performance of more than 32,000 CoreMarks, paired with 10 Gb +Ethernet, PCIe Gen. 3, SATA 3.0, USB 3.0 and QSPI interfaces provides an +excellent combination for a range of enterprise and service provider +networking, storage, security and industrial applications. + +Hardware +******** + +LS1046A RDB boards supports the following features: + + +- Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed +- Supports 8 GB DDR4 SDRAM memory +- SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi + memory device +- One 512 MB SLC NAND flash with ECC support (1.8 V) +- CPLD connection: 8-bit registers in CPLD to configure mux/demux selections +- Support two 64 MB onboard QSPI NOR flash memories +- USB: + - Two USB 3.0 controllers with integrated PHYs. + - One USB1 3.0 port is connected to a Type A host connector. + - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector. + - One USB2.0 is connected to miniPCIe connector . +- Ethernet: + - Supports SGMII 1G PHYs at Lane 2 and Lane 3 + - Supports SFP+module with XFI retimers + - Supports AQR106/107 10G PHY with XFI/2.5G SGMII +- PCIe and SATA: + - Mini PCIe express x1 (Gen1/2/3)card + - Standard PCIe x1 (Gen1/2/3) card + - Standard PCIe x1 (Gen1/2/3) card + - One SATA 3.0 connector + +Supported Features +================== + +NXP LS1046A RDB board default configuration supports the following +hardware features: + ++-----------+------------+--------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================================+ +| GIC-400 | on-chip | GICv2 interrupt controller | ++-----------+------------+--------------------------------------+ +| ARM TIMER | on-chip | System Clock | ++-----------+------------+--------------------------------------+ +| UART | on-chip | NS16550 compatible serial port | ++-----------+------------+--------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in the defconfig file for NON-SMP: + + :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig` + +Or for SMP running on all four CPU Cores: + + :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig` + +Or for SMP running on 2 CPU Cores (Core2 and Core3): + + :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig` + +There are two serial port on the board: uart1 and uart2, Zephyr is using +uart2 as serial console. + +Programming and Debugging +************************* + +Use the following configuration to run basic Zephyr applications and +kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample: + +1. Non-SMP mode + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: ls1046ardb + :goals: build + +This will build an image with the synchronization sample app. + +Use u-boot to load and kick Zephyr.bin to CPU Core0: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; + +Or kick Zephyr.bin to any other CPU Cores, for example run Zephyr on Core3: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 3 release 0xc0000000; + + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 0 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + +2. SMP mode running on 4 CPU Cores + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: ls1046ardb/ls1046a/smp/4cores + :goals: build + +This will build an image with the synchronization sample app. + +Use u-boot to load and kick Zephyr.bin to CPU Core0: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; go 0xc0000000; + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** + Secondary CPU core 1 (MPID:0x1) is up + Secondary CPU core 2 (MPID:0x2) is up + Secondary CPU core 3 (MPID:0x3) is up + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 1 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + +3. SMP mode running on 2 CPU Cores: Core2 and Core3 + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: ls1046ardb/ls1046a/smp + :goals: build + +This will build an image with the synchronization sample app. + +Use u-boot to load and kick Zephyr.bin to CPU Core2: + +.. code-block:: console + + tftp c0000000 zephyr.bin; dcache off; dcache flush; icache flush; icache off; cpu 2 release 0xc0000000; + +It will display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 *** + Secondary CPU core 1 (MPID:0x3) is up + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + thread_b: Hello World from cpu 1 on nxp_ls1046ardb! + thread_a: Hello World from cpu 0 on nxp_ls1046ardb! + +4. Running Zephyr on Jailhouse inmate Cell + +Use the following to run Zephyr in Jailhouse inmate, need to configure Jailhouse +inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3 +for Zephyr SMP 2cores image. + +1) Use root Cell dts to boot root Cell Linux. + +2) Install Jailhouse module: + +.. code-block:: console + + modprobe jailhouse + +3) Run Zephyr demo in inmate Cell: + +.. code-block:: console + + jailhouse enable ls1046a-rdb.cell + jailhouse cell create ls1046a-rdb-inmate-demo.cell + jailhouse cell load 1 zephyr.bin --address 0xc0000000 + jailhouse cell start 1 + +Flashing +======== + +Zephyr image can be loaded in DDR memory at address 0xc0000000 from SD Card, +EMMC, QSPI Flash or downloaded from network in uboot. + +Debugging +========= + +LS1046A RDB board includes one JTAG connector on board, connect it to +CodeWarrior TAP for debugging. + +References +========== + +`Layerscape LS1046A Reference Design Board `_ + +`LS1046A Reference Manual `_ diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.dts similarity index 100% rename from boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb.dts rename to boards/nxp/ls1046ardb/ls1046ardb_ls1046a.dts diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml new file mode 100644 index 00000000000000..bbf14171767908 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a.yaml @@ -0,0 +1,9 @@ +identifier: ls1046ardb +name: NXP LS1046ARDB on single CPU Core (NON-SMP) +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +vendor: nxp diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig new file mode 100644 index 00000000000000..f33d12913c84d8 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig @@ -0,0 +1,20 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_ARM64_VA_BITS_40=y +CONFIG_ARM64_PA_BITS_40=y +# 25 MHz system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 + +# Zephyr Kernel Configuration +CONFIG_XIP=n +CONFIG_AARCH64_IMAGE_HEADER=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.dts b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.dts similarity index 100% rename from boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_2cores.dts rename to boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.dts diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml new file mode 100644 index 00000000000000..50a321527b0861 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp.yaml @@ -0,0 +1,9 @@ +identifier: ls1046ardb/ls1046a/smp +name: NXP LS1046ARDB SMP on CPU Core2 and Core3 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +vendor: nxp diff --git a/boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.dts b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.dts similarity index 100% rename from boards/arm64/nxp_ls1046ardb/nxp_ls1046ardb_smp_4cores.dts rename to boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.dts diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml new file mode 100644 index 00000000000000..484e40bd0b4bd4 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores.yaml @@ -0,0 +1,9 @@ +identifier: ls1046ardb/ls1046a/smp/4cores +name: NXP LS1046ARDB SMP on four CPU Cores +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +vendor: nxp diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig new file mode 100644 index 00000000000000..2d2429f57d2f9d --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# SMP support +CONFIG_MP_MAX_NUM_CPUS=4 diff --git a/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig new file mode 100644 index 00000000000000..ace2e242267b63 --- /dev/null +++ b/boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Zephyr Kernel Configuration +CONFIG_MAX_THREAD_BYTES=5 +CONFIG_MAX_XLAT_TABLES=10 + +# SMP support +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_CACHE_MANAGEMENT=y +CONFIG_ARMV8_A_NS=y + +# PSCI is supported +CONFIG_PM_CPU_OPS=y diff --git a/boards/nxp/mimxrt1010_evk/CMakeLists.txt b/boards/nxp/mimxrt1010_evk/CMakeLists.txt new file mode 100644 index 00000000000000..260448d63c76ac --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/CMakeLists.txt @@ -0,0 +1,33 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(init.c) + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + if(NOT DEFINED CONFIG_BOARD_MIMXRT1010_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1010-EVK, but targeting a custom board. You may need to " + "update your flash configuration data blocks") + endif() + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1010 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT1010_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1010") + zephyr_library_sources(${RT1010_BOARD_DIR}/xip/evkmimxrt1010_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1010_BOARD_DIR}/xip) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1010_evk/Kconfig.mimxrt1010_evk b/boards/nxp/mimxrt1010_evk/Kconfig.mimxrt1010_evk new file mode 100644 index 00000000000000..faf3f0c884d30f --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/Kconfig.mimxrt1010_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2019, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1010_EVK + select SOC_PART_NUMBER_MIMXRT1011DAE5A diff --git a/boards/arm/mimxrt1010_evk/board.cmake b/boards/nxp/mimxrt1010_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1010_evk/board.cmake rename to boards/nxp/mimxrt1010_evk/board.cmake diff --git a/boards/nxp/mimxrt1010_evk/board.yml b/boards/nxp/mimxrt1010_evk/board.yml new file mode 100644 index 00000000000000..8c5dd6f1d75020 --- /dev/null +++ b/boards/nxp/mimxrt1010_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1010_evk + vendor: nxp + socs: + - name: mimxrt1011 diff --git a/boards/arm/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1010_evk/doc/index.rst rename to boards/nxp/mimxrt1010_evk/doc/index.rst diff --git a/boards/arm/mimxrt1010_evk/doc/mimxrt1010_evk.jpg b/boards/nxp/mimxrt1010_evk/doc/mimxrt1010_evk.jpg similarity index 100% rename from boards/arm/mimxrt1010_evk/doc/mimxrt1010_evk.jpg rename to boards/nxp/mimxrt1010_evk/doc/mimxrt1010_evk.jpg diff --git a/boards/arm/mimxrt1010_evk/init.c b/boards/nxp/mimxrt1010_evk/init.c similarity index 88% rename from boards/arm/mimxrt1010_evk/init.c rename to boards/nxp/mimxrt1010_evk/init.c index 1e62f4b5a6ba57..1fd4b67e457e85 100644 --- a/boards/arm/mimxrt1010_evk/init.c +++ b/boards/nxp/mimxrt1010_evk/init.c @@ -7,7 +7,7 @@ void SystemInitHook(void) { -#ifdef CONFIG_CODE_FLEXSPI +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) /* AT25SF128A SPI Flash on the RT1010-EVK requires special alignment * considerations, so set the READADDROPT bit in the FlexSPI so it * will fetch more data than each AHB burst requires to meet alignment @@ -18,5 +18,5 @@ void SystemInitHook(void) * the instruction cache in very early boot. */ FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK; -#endif /* CONFIG_CODE_FLEXSPI */ +#endif } diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts similarity index 100% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk.dts rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk.dts diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk.yaml b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml similarity index 100% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk.yaml rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml diff --git a/boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig rename to boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig index 2e6ad98a5e79b6..dc0fdc31f2ae43 100644 --- a/boards/arm/mimxrt1010_evk/mimxrt1010_evk_defconfig +++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1011=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1015_evk/CMakeLists.txt b/boards/nxp/mimxrt1015_evk/CMakeLists.txt new file mode 100644 index 00000000000000..115153b462b1df --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1015_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1015-EVK, but targeting a custom board. You may need to " + "update your flash configuration data blocks") + endif() + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1015 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT1015_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1015") + zephyr_library_sources(${RT1015_BOARD_DIR}/xip/evkmimxrt1015_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1015_BOARD_DIR}/xip) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1015_evk/Kconfig.mimxrt1015_evk b/boards/nxp/mimxrt1015_evk/Kconfig.mimxrt1015_evk new file mode 100644 index 00000000000000..3685fc618b555a --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/Kconfig.mimxrt1015_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2019, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1015_EVK + select SOC_PART_NUMBER_MIMXRT1015DAF5A diff --git a/boards/arm/mimxrt1015_evk/board.cmake b/boards/nxp/mimxrt1015_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1015_evk/board.cmake rename to boards/nxp/mimxrt1015_evk/board.cmake diff --git a/boards/nxp/mimxrt1015_evk/board.yml b/boards/nxp/mimxrt1015_evk/board.yml new file mode 100644 index 00000000000000..5f26dc3898b7e0 --- /dev/null +++ b/boards/nxp/mimxrt1015_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1015_evk + vendor: nxp + socs: + - name: mimxrt1015 diff --git a/boards/arm/mimxrt1015_evk/doc/index.rst b/boards/nxp/mimxrt1015_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1015_evk/doc/index.rst rename to boards/nxp/mimxrt1015_evk/doc/index.rst diff --git a/boards/arm/mimxrt1015_evk/doc/mimxrt1015_evk.jpg b/boards/nxp/mimxrt1015_evk/doc/mimxrt1015_evk.jpg similarity index 100% rename from boards/arm/mimxrt1015_evk/doc/mimxrt1015_evk.jpg rename to boards/nxp/mimxrt1015_evk/doc/mimxrt1015_evk.jpg diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts similarity index 100% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk.dts rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk.dts diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml similarity index 100% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk.yaml rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml diff --git a/boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig rename to boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig index 3268f61aebccfe..dc0fdc31f2ae43 100644 --- a/boards/arm/mimxrt1015_evk/mimxrt1015_evk_defconfig +++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1015=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1020_evk/CMakeLists.txt b/boards/nxp/mimxrt1020_evk/CMakeLists.txt new file mode 100644 index 00000000000000..63a6d289e6d936 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1020_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1020-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1020_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1020") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1020 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1020_BOARD_DIR}/xip/evkmimxrt1020_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1020_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1020 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1020_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1020_evk/Kconfig.defconfig b/boards/nxp/mimxrt1020_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..9c2251e2e609b7 --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/Kconfig.defconfig @@ -0,0 +1,24 @@ +# MIMXRT1020-EVK board + +# Copyright 2018,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1020_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config ETH_MCUX_PHY_RESET + default y + +endif # NETWORKING + +endif # BOARD_MIMXRT1020_EVK diff --git a/boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk b/boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk new file mode 100644 index 00000000000000..a616953d3447bb --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/Kconfig.mimxrt1020_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2018, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1020_EVK + select SOC_PART_NUMBER_MIMXRT1021DAG5A diff --git a/boards/arm/mimxrt1020_evk/board.cmake b/boards/nxp/mimxrt1020_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1020_evk/board.cmake rename to boards/nxp/mimxrt1020_evk/board.cmake diff --git a/boards/nxp/mimxrt1020_evk/board.yml b/boards/nxp/mimxrt1020_evk/board.yml new file mode 100644 index 00000000000000..4df4def13bc42e --- /dev/null +++ b/boards/nxp/mimxrt1020_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1020_evk + vendor: nxp + socs: + - name: mimxrt1021 diff --git a/boards/arm/mimxrt1020_evk/doc/index.rst b/boards/nxp/mimxrt1020_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1020_evk/doc/index.rst rename to boards/nxp/mimxrt1020_evk/doc/index.rst diff --git a/boards/arm/mimxrt1020_evk/doc/mimxrt1020_evk.jpg b/boards/nxp/mimxrt1020_evk/doc/mimxrt1020_evk.jpg similarity index 100% rename from boards/arm/mimxrt1020_evk/doc/mimxrt1020_evk.jpg rename to boards/nxp/mimxrt1020_evk/doc/mimxrt1020_evk.jpg diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts similarity index 100% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk.dts rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk.dts diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk.yaml b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml similarity index 100% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk.yaml rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml diff --git a/boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig rename to boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig index 3ca8b4d09f09c1..8af2d46280907d 100644 --- a/boards/arm/mimxrt1020_evk/mimxrt1020_evk_defconfig +++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1021=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1024_evk/CMakeLists.txt b/boards/nxp/mimxrt1024_evk/CMakeLists.txt new file mode 100644 index 00000000000000..229a396bcf6afe --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1024_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1024-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1024_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1024") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1024 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1024_BOARD_DIR}/xip/evkmimxrt1024_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1024_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1024 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1024_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1024_evk/Kconfig.defconfig b/boards/nxp/mimxrt1024_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..f9bc8cbfe608bf --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/Kconfig.defconfig @@ -0,0 +1,32 @@ +# MIMXRT1024-EVK board + +# Copyright 2020,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1024_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config I2C_MCUX_LPI2C_BUS_RECOVERY + default y + depends on I2C_MCUX_LPI2C && PINCTRL + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +endif # BOARD_MIMXRT1024_EVK diff --git a/boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk b/boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk new file mode 100644 index 00000000000000..e1e69dc4565f06 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/Kconfig.mimxrt1024_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2020, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1024_EVK + select SOC_PART_NUMBER_MIMXRT1024DAG5A diff --git a/boards/arm/mimxrt1024_evk/board.cmake b/boards/nxp/mimxrt1024_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1024_evk/board.cmake rename to boards/nxp/mimxrt1024_evk/board.cmake diff --git a/boards/nxp/mimxrt1024_evk/board.yml b/boards/nxp/mimxrt1024_evk/board.yml new file mode 100644 index 00000000000000..c9420ad2b75866 --- /dev/null +++ b/boards/nxp/mimxrt1024_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1024_evk + vendor: nxp + socs: + - name: mimxrt1024 diff --git a/boards/arm/mimxrt1024_evk/doc/index.rst b/boards/nxp/mimxrt1024_evk/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1024_evk/doc/index.rst rename to boards/nxp/mimxrt1024_evk/doc/index.rst diff --git a/boards/arm/mimxrt1024_evk/doc/mimxrt1024_evk.jpg b/boards/nxp/mimxrt1024_evk/doc/mimxrt1024_evk.jpg similarity index 100% rename from boards/arm/mimxrt1024_evk/doc/mimxrt1024_evk.jpg rename to boards/nxp/mimxrt1024_evk/doc/mimxrt1024_evk.jpg diff --git a/boards/arm/mimxrt1024_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1024_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1024_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1024_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts similarity index 100% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk.dts rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk.dts diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml similarity index 100% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk.yaml rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml diff --git a/boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig rename to boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig index c41a65e312d979..591d807155216c 100644 --- a/boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig +++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1024=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1040_evk/CMakeLists.txt b/boards/nxp/mimxrt1040_evk/CMakeLists.txt new file mode 100644 index 00000000000000..9fc000a98ab3ba --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1040_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1040-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1040_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1040") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1040 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1040_BOARD_DIR}/xip/evkmimxrt1040_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1040_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1040 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1040_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1040_evk/Kconfig.defconfig b/boards/nxp/mimxrt1040_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..87cdb61799a5fa --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright 2023, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1040_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +endif # BOARD_MIMXRT1040_EVK diff --git a/boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk b/boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk new file mode 100644 index 00000000000000..6cfd479dadc023 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/Kconfig.mimxrt1040_evk @@ -0,0 +1,5 @@ +# Copyright 2023, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1040_EVK + select SOC_PART_NUMBER_MIMXRT1042XJM5B diff --git a/boards/arm/mimxrt1040_evk/board.cmake b/boards/nxp/mimxrt1040_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1040_evk/board.cmake rename to boards/nxp/mimxrt1040_evk/board.cmake diff --git a/boards/nxp/mimxrt1040_evk/board.yml b/boards/nxp/mimxrt1040_evk/board.yml new file mode 100644 index 00000000000000..ded85cfce4af75 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1040_evk + vendor: nxp + socs: + - name: mimxrt1042 diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst new file mode 100644 index 00000000000000..c2f1e1561ce992 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/doc/index.rst @@ -0,0 +1,372 @@ +.. _mimxrt1040_evk: + +NXP MIMXRT1040-EVK +################## + +Overview +******** + +i.MX RT1040 crossover MCUs add additional flexibility with new packages and an +extended temperature range up to 125° C. The i.MX RT1040 MCU has a compact +9x9 mm package, as well as the 11x11 mm package that supports implementing a +2-layer PCB design. The i.MX RT1040 MCUs run on the Arm® Cortex®-M7 core at +600 MHz. + +.. image:: mimxrt1040_evk.jpg + :align: center + :alt: MIMXRT1040-EVK + +Hardware +******** + +- MIMXRT1042XJM5B MCU (600 MHz, 512 KB TCM) + +- Memory + + - 256 MBit SDRAM (Winbond W9825G6KH) + - 64 Mbit QSPI Flash (Winbond W25Q64JVSSIQ) + +- Display + + - LCD connector + - Touch connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1040 SoC and MIMXRT1040-EVK board, see +these references: + +- `i.MX RT1040 Website`_ +- `i.MX RT1040 Datasheet`_ +- `i.MX RT1040 Reference Manual`_ +- `MIMXRT1040-EVK Website`_ +- `MIMXRT1040-EVK User Guide`_ +- `MIMXRT1040-EVK Design Files`_ + +External Memory +=============== + +This platform has the following external memories: + ++----------------+------------+-------------------------------------+ +| Device | Controller | Status | ++================+============+=====================================+ +| W9825G6KH | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++----------------+------------+-------------------------------------+ +| W25Q64JVSSIQ | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. Supported for XIP only. | ++----------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1040_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1064_evk board may have additional features +already supported, which can also be re-used on this mimxrt1040_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/mimxrt1040_evk/mimxrt1040_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT1040 SoC has five pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_08 | GPIO | User LD1 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | FLEXPWM1 PWM3A | PWM Output | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_14 | ADC0 IN3 | ADC0 Input | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_15 | ADC0 IN4 | ADC0 Input | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | LPSPI1_SDO | SPI Output | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | LPSPI1_SDI | SPI Input | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | LPSPI1_SCK | SPI Clock | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_00 | LPI2C1_SCL | I2C Clock | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_01 | LPI2C1_SDA | I2C Data | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R350, R346, + and R360 must be populated with zero ohm resistors. + +System Clock +============ + +The MIMXRT1040 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1040 SoC has eight UARTs. ``LPUART1`` is configured for the console, +and the remaining UARTs are not used. + + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +Option 1: :ref:`opensda-jlink-onboard-debug-probe` (Recommended) +---------------------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Check that jumpers J9 and J10 are **on** to ensure SWD signals are connected to +the OpenSDA microcontroller. Then, follow the instructions in `NXP AN13206`_ to +program a JLink based firmware to the LPC4322 based debugger on this board. + +Once the JLink based firmware is present on this board, the SOC will no longer +be powered via the USB connection to J1. Move J40 to short pins 3 and 4 in +order to use J48 for USB power, and connect another USB cable to power the SoC. +LED D16 should illuminate to indicate the board is powered, and it should now be +possible to program the SoC. + +Option 2: :ref:`jlink-external-debug-probe` +------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +The board can be programmed using the :ref:`jlink-external-debug-probe`, +provided the onboard debug circuit's SWD signals are isolated from the MCU. +To do so, ensure that jumpers J9 and J10 are **off** (they are on by default +when the board ships from the factory). The external probe's 20 pin connector +can then be connected to J2 to program the SOC. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J11 and J13 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J1. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1040_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** + Hello World! mimxrt1040_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1040_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS Booting Zephyr OS build v3.3.0-rc3-66 ***** + Hello World! mimxrt1040_evk + +Troubleshooting +=============== + +USER_LED D8 +----------- +The MIMXRT1040-EVK board ships with the wireless module in the M.2 connector, +and with jumper J80 shorted. This causes a conflict with the USER_LED D8, +and the LED will not turn off. Samples and applications using USER_LED D8, +like blinky, require removal of J80 jumper. + +Boot Header +----------- + +If the debug probe fails to connect with the following error, it's possible +that the boot header in QSPI is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the QSPI with the following +steps: + +#. Set the SW4 DIP switches to OFF-OFF-OFF-ON to boot into the ROM bootloader. + +#. Reset by pressing SW1 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW4 DIP switches to OFF-OFF-ON-OFF to boot from QSPI. + +#. Reset by pressing SW1 + + +WiFi Module +----------- + +If the debugger fails to connect with the following error, it's possible +the M.2 WiFi module is interfering with the debug signals + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +To resolve this, you may remove the M.2 WiFi module from the board when +flashing or debugging it, or remove jumper J80. + + +.. _MIMXRT1040-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1040-evaluation-kit:MIMXRT1040-EVK + +.. _MIMXRT1040-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVKUM + +.. _MIMXRT1040-EVK Design Files: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1040-EVK-DESIGNFILES + +.. _i.MX RT1040 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1040-crossover-mcu-with-arm-cortex-m7-core:i.MX-RT1040 + +.. _i.MX RT1040 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1040CEC.pdf + +.. _i.MX RT1040 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1040RM + +.. _NXP AN13206: + https://www.nxp.com/docs/en/application-note/AN13206.pdf diff --git a/boards/arm/mimxrt1040_evk/doc/mimxrt1040_evk.jpg b/boards/nxp/mimxrt1040_evk/doc/mimxrt1040_evk.jpg similarity index 100% rename from boards/arm/mimxrt1040_evk/doc/mimxrt1040_evk.jpg rename to boards/nxp/mimxrt1040_evk/doc/mimxrt1040_evk.jpg diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1040_evk/mimxrt1040_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk.dts b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts similarity index 100% rename from boards/arm/mimxrt1040_evk/mimxrt1040_evk.dts rename to boards/nxp/mimxrt1040_evk/mimxrt1040_evk.dts diff --git a/boards/arm/mimxrt1040_evk/mimxrt1040_evk.yaml b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml similarity index 100% rename from boards/arm/mimxrt1040_evk/mimxrt1040_evk.yaml rename to boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig new file mode 100644 index 00000000000000..5d1b150c729fa9 --- /dev/null +++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1050_evk/CMakeLists.txt b/boards/nxp/mimxrt1050_evk/CMakeLists.txt new file mode 100644 index 00000000000000..597a64852cf0a8 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/CMakeLists.txt @@ -0,0 +1,55 @@ +# +# Copyright 2017-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if (CONFIG_DISPLAY) +message(WARNING " +CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board +") +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_HYPERFLASH_ENABLED) + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED) + set(FLASH_CONF evkbimxrt1050_flexspi_nor_qspi_config.c) + else() + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1050-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + # Default EVK configuration uses hyperflash, so use that file + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + endif() + set(RT1050_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkbimxrt1050") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1050_BOARD_DIR}/xip/${FLASH_CONF}) + zephyr_library_include_directories(${RT1050_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1050_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..bfb4a84e341b0f --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig @@ -0,0 +1,52 @@ +# MIMXRT1050-EVK board + +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1050_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +if LVGL + +config LV_Z_VDB_SIZE + default 16 + +config LV_DPI_DEF + default 128 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +endif # LVGL + +endif # BOARD_MIMXRT1050_EVK diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk b/boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk new file mode 100644 index 00000000000000..f146c00267204b --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/Kconfig.mimxrt1050_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2017, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1050_EVK + select SOC_PART_NUMBER_MIMXRT1052DVL6B diff --git a/boards/nxp/mimxrt1050_evk/board.cmake b/boards/nxp/mimxrt1050_evk/board.cmake new file mode 100644 index 00000000000000..3e42ddc78feaa5 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/board.cmake @@ -0,0 +1,18 @@ +# +# Copyright 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +board_runner_args(jlink "--device=MCIMXRT1052") + +if("${BOARD_REVISION}" STREQUAL "qspi") + board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") + board_runner_args(pyocd "--target=mimxrt1050_quadspi") +else() + board_runner_args(pyocd "--target=mimxrt1050_hyperflash") + board_runner_args(linkserver "--device=MIMXRT1052xxxxB:EVKB-IMXRT1050") + include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/nxp/mimxrt1050_evk/board.yml b/boards/nxp/mimxrt1050_evk/board.yml new file mode 100644 index 00000000000000..c1276214baafc4 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/board.yml @@ -0,0 +1,11 @@ +board: + name: mimxrt1050_evk + vendor: nxp + socs: + - name: mimxrt1052 + revision: + format: "custom" + default: "hyperflash" + revisions: + - name: "hyperflash" + - name: "qspi" diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst new file mode 100644 index 00000000000000..165f3491f2c72d --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/doc/index.rst @@ -0,0 +1,499 @@ +.. _mimxrt1050_evk: + +NXP MIMXRT1050-EVK +################## + +Overview +******** + +The i.MX RT1050 is a new processor family featuring NXP's advanced +implementation of the ARM Cortex-M7 Core. It provides high CPU performance and +real-time response. + +The i.MX RT1050 provides various memory interfaces, including SDRAM, Raw NAND +FLASH, NOR FLASH, SD/eMMC, Quad SPI, HyperBus and a wide range of other +interfaces for connecting peripherals, such as WLAN, Bluetooth™, GPS, displays, +and camera sensors. As with other i.MX processors, i.MX RT1050 also has rich +audio and video features, including LCD display, basic 2D graphics, camera +interface, SPDIF, and I2S audio interface. + +The following document refers to the discontinued MIMXRT1050-EVK board. For the +MIMXRT1050-EVKB board, refer to `Board Revisions`_ section. + +.. image:: mimxrt1050_evk.jpg + :align: center + :alt: MIMXRT1050-EVK + +Hardware +******** + +- MIMXRT1052DVL6A MCU (600 MHz, 512 KB TCM) + +- Memory + + - 256 KB SDRAM + - 64 Mbit QSPI Flash + - 512 Mbit Hyper Flash + +- Display + + - LCD connector + - Touch connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - CMOS camera sensor interface + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1050 SoC and MIMXRT1050-EVK board, see +these references: + +- `i.MX RT1050 Website`_ +- `i.MX RT1050 Datasheet`_ +- `i.MX RT1050 Reference Manual`_ +- `MIMXRT1050-EVK Website`_ +- `MIMXRT1050-EVK User Guide`_ +- `MIMXRT1050-EVK Schematics`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| IS42S16160J | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ +| S26KS512SDPBHI020 | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1050_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1064_evk board may have additional features +already supported, which can also be re-used on this mimxrt1050_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/mimxrt1050_evk/mimxrt1050_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT1050 SoC has five pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_05 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_11 | GPIO | Touch Interrupt | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_11 | ADC | ADC1 channel 0 | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_B0_00 | LCD_CLK | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_01 | LCD_ENABLE | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_02 | LCD_HSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_03 | LCD_VSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_04 | LCD_DATA00 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_05 | LCD_DATA01 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_06 | LCD_DATA02 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_07 | LCD_DATA03 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_08 | LCD_DATA04 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_09 | LCD_DATA05 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_10 | LCD_DATA06 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_11 | LCD_DATA07 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_12 | LCD_DATA08 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_13 | LCD_DATA09 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_14 | LCD_DATA10 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_15 | LCD_DATA11 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_00 | LCD_DATA12 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_01 | LCD_DATA13 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_02 | LCD_DATA14 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_03 | LCD_DATA15 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_06 | ENET_RX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_09 | ENET_TX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_10 | ENET_REF_CLK | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_11 | ENET_RX_ER | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_12 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_14 | USDHC1_VSELECT | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_40 | ENET_MDC | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_41 | ENET_MDIO | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | ENET_RST | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | ENET_INT | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R278, + R279, R280, and R281 must be populated with zero ohm resistors + +System Clock +============ + +The MIMXRT1050 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1050 SoC has eight UARTs. ``LPUART1`` is configured for the console, +``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the +remaining are not used. + +USB +=== + +The RT1050 SoC has two USB OTG (USBOTG) controllers that supports both +device and host functions through its micro USB connectors. +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +Using LinkServer +---------------- + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + +Linkserver is the default runner. You may also se the ``-r linkserver`` option +with West to use the LinkServer runner. + +.. code-block:: console + + west flash + west debug + +JLink (on-board): :ref:`opensda-jlink-onboard-debug-probe` +---------------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware`_. Check that jumpers +J32 and J33 are **on** (they are on by default when boards ship from the +factory) to ensure SWD signals are connected to the OpenSDA microcontroller. + +Follow the instructions in `Enable QSPI flash support in SEGGER JLink`_ +in order to support your EVK if you have modified it to boot from QSPI NOR +flash as specified by NXP AN12108. + +External JLink :ref:`jlink-external-debug-probe` +------------------------------------------------ + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Attach a J-Link 20-pin connector to J21. Check that jumpers J32 and J33 are +**off** (they are on by default when boards ship from the factory) to ensure +SWD signals are disconnected from the OpenSDA microcontroller. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J30 and J31 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J28. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1050_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1050_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1050_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1050_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the boot header in HyperFlash is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the HyperFlash with the following +steps: + +#. Set the SW7 DIP switches to ON-ON-ON-OFF to prevent booting from HyperFlash. + +#. Reset by pressing SW4 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW7 DIP switches to OFF-ON-ON-OFF to boot from HyperFlash. + +#. Reset by pressing SW4 + +Board Revisions +*************** + +The original MIMXRT1050-EVK (rev A0) board was updated with a newer +MIMXRT1050-EVKB (rev A1) board, with these major hardware differences: + +- SoC changed from MIMXRT1052DVL6\ **A** to MIMXRT1052DVL6\ **B** +- Hardware bug fixes for: power, interfaces, and memory +- Arduino headers included + +For more details, please see the following `NXP i.MXRT1050 A0 to A1 Migration Guide`_. + +Current Zephyr build supports the new MIMXRT1050-EVKB + +.. _MIMXRT1050-EVK Website: + https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK + +.. _MIMXRT1050-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=IMXRT1050EVKBHUG + +.. _MIMXRT1050-EVK Schematics: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1050-EVK-DESIGNFILES + +.. _i.MX RT1050 Website: + https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1050 + +.. _i.MX RT1050 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1050CEC.pdf + +.. _i.MX RT1050 Reference Manual: + https://www.nxp.com/docs/en/reference-manual/IMXRT1050RM.pdf + +.. _OpenSDA J-Link MIMXRT1050-EVK-Hyperflash Firmware: + https://www.segger.com/downloads/jlink/OpenSDA_MIMXRT1050-EVK-Hyperflash + +.. _NXP i.MXRT1050 A0 to A1 Migration Guide: + https://www.nxp.com/docs/en/nxp/application-notes/AN12146.pdf + +.. _Enable QSPI flash support in SEGGER JLink: + https://wiki.segger.com/i.MXRT1050#QSPI_flash + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.jpg b/boards/nxp/mimxrt1050_evk/doc/mimxrt1050_evk.jpg similarity index 100% rename from boards/arm/mimxrt1050_evk/doc/mimxrt1050_evk.jpg rename to boards/nxp/mimxrt1050_evk/doc/mimxrt1050_evk.jpg diff --git a/boards/arm/mimxrt1050_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1050_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1050_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1050_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1050_evk/mimxrt1050_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts similarity index 77% rename from boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts rename to boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts index d1e8da5834b795..e636fc207d580b 100644 --- a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.dts +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dts @@ -30,9 +30,6 @@ zephyr,dtcm = &dtcm; zephyr,console = &lpuart1; zephyr,shell-uart = &lpuart1; - zephyr,flash-controller = &s26ks512s0; - zephyr,flash = &s26ks512s0; - zephyr,code-partition = &slot0_partition; zephyr,display = &lcdif; }; @@ -115,64 +112,6 @@ arduino_serial: &lpuart3 { pinctrl-names = "default"; }; -&flexspi { - status = "okay"; - ahb-prefetch; - ahb-read-addr-opt; - pinctrl-0 = <&pinmux_flexspi1>; - pinctrl-names = "default"; - ahb-bufferable; - ahb-cacheable; - sck-differential-clock; - combination-mode; - rx-clock-source = <3>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; - s26ks512s0: s26ks512s@0 { - compatible = "nxp,imx-flexspi-hyperflash"; - size = ; - reg = <0>; - spi-max-frequency = <166000000>; - word-addressable; - cs-interval-unit = <1>; - cs-interval = <2>; - cs-hold-time = <0>; - cs-setup-time = <3>; - data-valid-time = <1>; - column-space = <3>; - ahb-write-wait-unit = <2>; - ahb-write-wait-interval = <20>; - status = "okay"; - erase-block-size = <4096>; - write-block-size = <16>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(256)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@40000 { - label = "image-0"; - reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@341000 { - label = "image-1"; - reg = <0x00341000 DT_SIZE_M(3)>; - }; - storage_partition: partition@641000 { - label = "storage"; - reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; - }; - }; - }; -}; - &lcdif { status = "okay"; width = <480>; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig new file mode 100644 index 00000000000000..e4f0cbedcc2615 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay new file mode 100644 index 00000000000000..ccce00a56287b0 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.overlay @@ -0,0 +1,71 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &s26ks512s0; + zephyr,flash = &s26ks512s0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; + ahb-bufferable; + ahb-cacheable; + sck-differential-clock; + combination-mode; + rx-clock-source = <3>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; + s26ks512s0: s26ks512s@0 { + compatible = "nxp,imx-flexspi-hyperflash"; + size = ; + reg = <0>; + spi-max-frequency = <166000000>; + word-addressable; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <0>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <3>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <20>; + status = "okay"; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@341000 { + label = "image-1"; + reg = <0x00341000 DT_SIZE_M(3)>; + }; + storage_partition: partition@641000 { + label = "storage"; + reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; + }; + }; + }; +}; diff --git a/boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml similarity index 100% rename from boards/arm/mimxrt1050_evk/mimxrt1050_evk.yaml rename to boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay new file mode 100644 index 00000000000000..1fd770ec6558a0 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.overlay @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &is25wp064; + zephyr,flash = &is25wp064; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + is25wp064: is25wp064@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <67108864>; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@311000 { + label = "image-1"; + reg = <0x00311000 DT_SIZE_M(3)>; + }; + storage_partition: partition@611000 { + label = "storage"; + reg = <0x00611000 DT_SIZE_K(1980)>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml new file mode 100644 index 00000000000000..6476d666984ff2 --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml @@ -0,0 +1,31 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1050_evk@qspi +name: NXP MIMXRT1050-EVK-QSPI +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32768 +flash: 8192 +supported: + - arduino_gpio + - arduino_serial + - counter + - display + - dma + - gpio + - i2c + - netif:eth + - sdhc + - spi + - usb_device + - watchdog + - adc +vendor: nxp diff --git a/boards/nxp/mimxrt1050_evk/revision.cmake b/boards/nxp/mimxrt1050_evk/revision.cmake new file mode 100644 index 00000000000000..3e6f006a735b5b --- /dev/null +++ b/boards/nxp/mimxrt1050_evk/revision.cmake @@ -0,0 +1,7 @@ +if (NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "hyperflash") +else () + if (NOT (BOARD_REVISION STREQUAL "hyperflash") AND NOT (BOARD_REVISION STREQUAL "qspi")) + message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: hyperflash, qspi") + endif() +endif() diff --git a/boards/nxp/mimxrt1060_evk/CMakeLists.txt b/boards/nxp/mimxrt1060_evk/CMakeLists.txt new file mode 100644 index 00000000000000..29c2d6f9068a62 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/CMakeLists.txt @@ -0,0 +1,64 @@ +# +# Copyright 2018-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if (CONFIG_DISPLAY) +message(WARNING " +CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board +") +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(CONFIG_BOARD_MIMXRT1060_EVKB) + set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) + set(BOARD_NAME evkbmimxrt1060) + elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED) + set(FLASH_CONF evkmimxrt1060_flexspi_nor_config.c) + set(BOARD_NAME evkmimxrt1060) + elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_HYPERFLASH_ENABLED) + # No flash configuration block exists for the RT1060 with HyperFlash in + # the SDK, but we can reuse the block for the RT1050 as both boards use + # the same HyperFlash chip + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + set(BOARD_NAME evkbimxrt1050) + else() + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1060-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + # Default EVK configuration uses qspi, so use that file + set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c) + set(BOARD_NAME evkbmimxrt1060) + endif() + set(RT1060_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1060 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1060_BOARD_DIR}/xip/${FLASH_CONF}) + zephyr_library_include_directories(${RT1060_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1060 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1060_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..37dc90279ddee6 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig @@ -0,0 +1,73 @@ +# MIMXRT1060-EVK board + +# Copyright 2018,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVKB + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +if LVGL + +# LVGL should allocate buffers equal to size of display +config LV_Z_VDB_SIZE + default 100 + +# Enable double buffering +config LV_Z_DOUBLE_VDB + default y + +# Force full refresh. This prevents memory copy associated with partial +# display refreshes, which is not necessary for the eLCDIF driver +config LV_Z_FULL_REFRESH + default y + +config LV_DPI_DEF + default 128 + +config LV_Z_BITS_PER_PIXEL + default 16 + +# Force display buffers to be aligned to cache line size (32 bytes) +config LV_Z_VDB_ALIGN + default 32 + +# Use offloaded render thread +config LV_Z_FLUSH_THREAD + default y + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +endif # LVGL + +endif # BOARD_MIMXRT1060_EVK || BOARD_MIMXRT1060_EVKB diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evk b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evk new file mode 100644 index 00000000000000..a636a49b251006 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2018, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1060_EVK + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb new file mode 100644 index 00000000000000..d2f59c8c9cfa90 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/Kconfig.mimxrt1060_evkb @@ -0,0 +1,5 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1060_EVKB + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/nxp/mimxrt1060_evk/board.cmake b/boards/nxp/mimxrt1060_evk/board.cmake new file mode 100644 index 00000000000000..722afd541f7120 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/board.cmake @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018, 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(pyocd "--target=mimxrt1060") +board_runner_args(jlink "--device=MIMXRT1062xxx6A") +board_runner_args(linkserver "--device=MIMXRT1062xxxxA:EVK-MIMXRT1060") + +if (("${BOARD_REVISION}" STREQUAL "qspi") OR CONFIG_BOARD_MIMXRT1060_EVKB) + board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI") +elseif ("${BOARD_REVISION}" STREQUAL "hyperflash") + board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1060_evk/board.yml b/boards/nxp/mimxrt1060_evk/board.yml new file mode 100644 index 00000000000000..6682fbd72283c4 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/board.yml @@ -0,0 +1,11 @@ +boards: + - name: mimxrt1060_evk + vendor: nxp + socs: + - name: mimxrt1062 + revision: + format: "custom" + - name: mimxrt1060_evkb + vendor: nxp + socs: + - name: mimxrt1062 diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst new file mode 100644 index 00000000000000..de0943ce83ca5e --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/doc/index.rst @@ -0,0 +1,484 @@ +.. _mimxrt1060_evk: + +NXP MIMXRT1060-EVK +################## + +Overview +******** + +The i.MX RT1060 adds to the industry's first crossover +processor series and expands the i.MX RT series to three scalable families. + +The i.MX RT1060 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin +compatibility with i.MX RT1050. This series introduces additional features +ideal for real-time applications such as High-Speed GPIO, CAN FD, and +synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1060 runs on the +Arm® Cortex-M7® core up to 600 MHz. + +.. image:: mimxrt1060_evk.jpg + :align: center + :alt: MIMXRT1060-EVK + +Hardware +******** + +- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory) + +- Memory + + - 256 Mbit SDRAM + - 64 Mbit QSPI Flash + - 512 Mbit Hyper Flash + - TF socket for SD card + +- Display + + - LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - CMOS camera sensor interface + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1060 SoC and MIMXRT1060-EVK board, see +these references: + +- `i.MX RT1060 Website`_ +- `i.MX RT1060 Datasheet`_ +- `i.MX RT1060 Reference Manual`_ +- `MIMXRT1060-EVK Website`_ +- `MIMXRT1060-EVK User Guide`_ +- `MIMXRT1060-EVK Schematics`_ +- `MIMXRT1060-EVK Debug Firmware`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| IS25WP064AJBLE | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ +| IS42S16160J | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1060_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1064_evk board may have additional features +already supported, which can also be re-used on this mimxrt1060_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| SAI | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/arm/mimxrt1060_evk/mimxrt1060_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and I/Os +==================== + +The MIMXRT1060 SoC has five pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_05 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | GPIO/ENET_RST | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_11 | GPIO | Touch Interrupt | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_00 | LPI2C1_SCL | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_01 | LPI2C1_SDA | I2C | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | LPUART3_TX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_07 | LPUART3_RX | UART BT HCI | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_B0_00 | LCD_CLK | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_01 | LCD_ENABLE | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_02 | LCD_HSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_03 | LCD_VSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_04 | LCD_DATA00 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_05 | LCD_DATA01 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_06 | LCD_DATA02 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_07 | LCD_DATA03 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_08 | LCD_DATA04 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_09 | LCD_DATA05 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_10 | LCD_DATA06 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_11 | LCD_DATA07 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_12 | LCD_DATA08 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_13 | LCD_DATA09 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_14 | LCD_DATA10 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_15 | LCD_DATA11 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_00 | LCD_DATA12 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_01 | LCD_DATA13 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_02 | LCD_DATA14 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_03 | LCD_DATA15 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_06 | ENET_RX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_09 | ENET_TX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_10 | ENET_REF_CLK | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_11 | ENET_RX_ER | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_12 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_14 | USDHC1_VSELECT | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_40 | ENET_MDC | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_41 | ENET_MDIO | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | ENET_RST | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | ENET_INT | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_10 | ADC | ADC1 Channel 15 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_09 | SAI1_MCLK | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_12 | SAI1_RX | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_13 | SAI1_TX | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_14 | SAI1_TX_BCLK | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_15 | SAI1_TX_SYNC | I2S | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_02 | 1588_EVENT2_OUT | 1588 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_03 | 1588_EVENT2_IN | 1588 | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R278, R279, + R280 and R281 must be populated with zero ohm resistors. + +System Clock +============ + +The MIMXRT1060 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + + +Serial Port +=========== + +The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console, +``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +.. _Using LinkServer: + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `MIMXRT1060-EVK Debug Firmware` + +.. _Using J-Link RT1060: + +Using J-Link +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ or +`Using J-Link with MIMXRT1060-EVKB`_ for more details. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J45 and J46 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J41. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Using SWO +--------- +SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. +Your SWO viewer should be configured with a CPU frequency of 132MHz, and +SWO frequency of 7500KHz. + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1060_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW9 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1060_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1060_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1060_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the boot header in QSPI flash is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the QSPI flash with the following +steps: + +#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. + +#. Reset by pressing SW9 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. + +#. Reset by pressing SW9 + +If the west flash or debug commands fail, and the command hangs while executing +runners.jlink, confirm the J-Link debug probe is configured, powered, and +connected to the EVK properly. See :ref:`Using J-Link RT1060` for more details. + +.. _MIMXRT1060-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1060-evaluation-kit:MIMXRT1060-EVKB + +.. _MIMXRT1060-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT10601064EKBHUG + +.. _MIMXRT1060-EVK Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _MIMXRT1060-EVK Schematics: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1060-EVK-DESIGNFILE-A3 + +.. _i.MX RT1060 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060 + +.. _i.MX RT1060 Datasheet: + https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf + +.. _i.MX RT1060 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM + +.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 + +.. _Using J-Link with MIMXRT1060-EVKB: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVKB/ta-p/1452717 + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.jpg b/boards/nxp/mimxrt1060_evk/doc/mimxrt1060_evk.jpg similarity index 100% rename from boards/arm/mimxrt1060_evk/doc/mimxrt1060_evk.jpg rename to boards/nxp/mimxrt1060_evk/doc/mimxrt1060_evk.jpg diff --git a/boards/arm/mimxrt1060_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1060_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1060_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1060_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts similarity index 82% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts index 42782b4045401f..6e90b87871729a 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts @@ -24,9 +24,6 @@ }; chosen { - zephyr,flash-controller = &is25wp064; - zephyr,flash = &is25wp064; - zephyr,code-partition = &slot0_partition; zephyr,sram = &sdram0; zephyr,itcm = &itcm; zephyr,dtcm = &dtcm; @@ -116,52 +113,6 @@ arduino_serial: &lpuart3 { pinctrl-names = "default", "sleep"; }; -&flexspi { - status = "okay"; - pinctrl-0 = <&pinmux_flexspi1>; - pinctrl-names = "default"; - ahb-prefetch; - ahb-read-addr-opt; - rx-clock-source = <1>; - reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; - is25wp064: is25wp064@0 { - compatible = "nxp,imx-flexspi-nor"; - size = <67108864>; - reg = <0>; - spi-max-frequency = <133000000>; - status = "okay"; - jedec-id = [9d 70 17]; - erase-block-size = <4096>; - write-block-size = <1>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 DT_SIZE_K(64)>; - }; - /* Note slot 0 has one additional sector, - * this is intended for use with the swap move algorithm - */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; - }; - slot1_partition: partition@311000 { - label = "image-1"; - reg = <0x00311000 DT_SIZE_M(3)>; - }; - storage_partition: partition@611000 { - label = "storage"; - reg = <0x00611000 DT_SIZE_K(1980)>; - }; - }; - }; -}; - &lcdif { status = "okay"; width = <480>; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig new file mode 100644 index 00000000000000..8af2d46280907d --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay new file mode 100644 index 00000000000000..4d94e82f6113f9 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.overlay @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2018, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &s26ks512s0; + zephyr,flash = &s26ks512s0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + ahb-prefetch; + ahb-read-addr-opt; + ahb-bufferable; + ahb-cacheable; + sck-differential-clock; + combination-mode; + rx-clock-source = <3>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(64)>; + s26ks512s0: s26ks512s@0 { + compatible = "nxp,imx-flexspi-hyperflash"; + size = ; + reg = <0>; + spi-max-frequency = <166000000>; + word-addressable; + cs-interval-unit = <1>; + cs-interval = <2>; + cs-hold-time = <0>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <3>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <20>; + status = "okay"; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@40000 { + label = "image-0"; + reg = <0x00040000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@341000 { + label = "image-1"; + reg = <0x00341000 DT_SIZE_M(3)>; + }; + storage_partition: partition@641000 { + label = "storage"; + reg = <0x00641000 (DT_SIZE_M(57) + DT_SIZE_K(764))>; + }; + }; + }; +}; diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml new file mode 100644 index 00000000000000..93a7915e6fd9c2 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml @@ -0,0 +1,32 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1060_evk@hyperflash +name: NXP MIMXRT1060-EVK-HYPERFLASH +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 32768 +flash: 65536 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - counter + - display + - dma + - gpio + - i2c + - netif:eth + - sdhc + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay new file mode 100644 index 00000000000000..9fddaea0c62935 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.overlay @@ -0,0 +1,59 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash-controller = &is25wp064; + zephyr,flash = &is25wp064; + zephyr,code-partition = &slot0_partition; + }; +}; + +&flexspi { + status = "okay"; + pinctrl-0 = <&pinmux_flexspi1>; + pinctrl-names = "default"; + ahb-prefetch; + ahb-read-addr-opt; + rx-clock-source = <1>; + reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>; + is25wp064: is25wp064@0 { + compatible = "nxp,imx-flexspi-nor"; + size = <67108864>; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [9d 70 17]; + erase-block-size = <4096>; + write-block-size = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(64)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 (DT_SIZE_M(3) + DT_SIZE_K(4))>; + }; + slot1_partition: partition@311000 { + label = "image-1"; + reg = <0x00311000 DT_SIZE_M(3)>; + }; + storage_partition: partition@611000 { + label = "storage"; + reg = <0x00611000 DT_SIZE_K(1980)>; + }; + }; + }; +}; diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml similarity index 100% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evk.yaml rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb.dts b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts similarity index 84% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evkb.dts rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts index 56104fe9432266..506f0d0d7a795b 100644 --- a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb.dts +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.dts @@ -5,6 +5,7 @@ */ #include "mimxrt1060_evk.dts" +#include "mimxrt1060_evk_mimxrt1062_qspi.overlay" /* FLEXPWM not routed to LED on this EVK */ &flexpwm2_pwm3 { diff --git a/boards/arm/mimxrt1060_evk/mimxrt1060_evkb.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.yaml similarity index 100% rename from boards/arm/mimxrt1060_evk/mimxrt1060_evkb.yaml rename to boards/nxp/mimxrt1060_evk/mimxrt1060_evkb.yaml diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig new file mode 100644 index 00000000000000..365bcc53c40dd5 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evkb_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2022, Whisper.ai +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1060_evk/revision.cmake b/boards/nxp/mimxrt1060_evk/revision.cmake new file mode 100644 index 00000000000000..97a3da96ea4905 --- /dev/null +++ b/boards/nxp/mimxrt1060_evk/revision.cmake @@ -0,0 +1,9 @@ +if (NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "qspi") +else () + if (NOT (BOARD_REVISION STREQUAL "hyperflash") AND NOT (BOARD_REVISION STREQUAL "qspi")) + message(FATAL_ERROR "Invalid board revision, ${BOARD_REVISION}, valid revisions are: hyperflash, qspi") + elseif (BOARD_REVISION STREQUAL "hyperflash" AND CONFIG_BOARD_MIMXRT1060_EVKB) + message(FATAL_ERROR "hyperflash not supported on RT1060 EVKB") + endif() +endif() diff --git a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt new file mode 100644 index 00000000000000..70f8df6e741ada --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt @@ -0,0 +1,40 @@ +# +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2023 NXP +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(CONFIG_BOARD_MIMXRT1062_FMURT6) + # No flash configuration block exists for the RT1060 with HyperFlash in + # the SDK, but we can reuse the block for the RT1050 as FMURT6 also uses + # the same HyperFlash chip + set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c) + set(BOARD_NAME evkbimxrt1050) + endif() + set(RT1062_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1062_BOARD_DIR}/xip/${FLASH_CONF}) + zephyr_library_include_directories(${RT1062_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1050 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1062_BOARD_DIR}/dcd.c) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig b/boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig new file mode 100644 index 00000000000000..073cd680ec07ab --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/Kconfig.defconfig @@ -0,0 +1,22 @@ +# MIMXRT1062-FMURT6 board + +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2023 NXP + +if BOARD_MIMXRT1062_FMURT6 + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + + +endif # BOARD_MIMXRT1062_FMURT6 diff --git a/boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 b/boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 new file mode 100644 index 00000000000000..852363cbbd0efa --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/Kconfig.mimxrt1062_fmurt6 @@ -0,0 +1,5 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1062_FMURT6 + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/arm/mimxrt1062_fmurt6/board.cmake b/boards/nxp/mimxrt1062_fmurt6/board.cmake similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/board.cmake rename to boards/nxp/mimxrt1062_fmurt6/board.cmake diff --git a/boards/nxp/mimxrt1062_fmurt6/board.yml b/boards/nxp/mimxrt1062_fmurt6/board.yml new file mode 100644 index 00000000000000..bebcb6c79541d3 --- /dev/null +++ b/boards/nxp/mimxrt1062_fmurt6/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1062_fmurt6 + vendor: nxp + socs: + - name: mimxrt1062 diff --git a/boards/arm/mimxrt1062_fmurt6/doc/index.rst b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/doc/index.rst rename to boards/nxp/mimxrt1062_fmurt6/doc/index.rst diff --git a/boards/arm/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg b/boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg rename to boards/nxp/mimxrt1062_fmurt6/doc/mimxrt1062_fmurt6.jpg diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6-pinctrl.dtsi diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.dts diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml similarity index 100% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml diff --git a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig similarity index 76% rename from boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig rename to boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig index 4efad5e51cb3a1..3db75b19e6d7b2 100644 --- a/boards/arm/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig +++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig @@ -4,9 +4,6 @@ # Copyright 2023 NXP # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y -CONFIG_BOARD_MIMXRT1062_FMURT6=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1064_evk/CMakeLists.txt b/boards/nxp/mimxrt1064_evk/CMakeLists.txt new file mode 100644 index 00000000000000..7d2f7effa10791 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/CMakeLists.txt @@ -0,0 +1,49 @@ +# +# Copyright 2018-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if (CONFIG_DISPLAY) +message(WARNING " +CONFIG_DISPLAY: Running this firmware on a board without a display may damage the board +") +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT DEFINED CONFIG_BOARD_MIMXRT1064_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1064-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1064_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1064") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1064 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1064_BOARD_DIR}/xip/evkmimxrt1064_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1064_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1064 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1064_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1064_evk/Kconfig.defconfig b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..4ec3c9ebe2f906 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig @@ -0,0 +1,52 @@ +# MIMXRT1064-EVK board + +# Copyright 2018,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1064_EVK + +config DEVICE_CONFIGURATION_DATA + default y + +config NXP_IMX_EXTERNAL_SDRAM + default y + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +if NETWORKING + +config NET_L2_ETHERNET + default y + +if ETH_MCUX + +config ETH_MCUX_PHY_RESET + default y + +endif # ETH_MCUX + +endif # NETWORKING + +if LVGL + +config LV_Z_VDB_SIZE + default 16 + +config LV_DPI_DEF + default 128 + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_16 +endchoice + +endif # LVGL + +endif # BOARD_MIMXRT1064_EVK diff --git a/boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk b/boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk new file mode 100644 index 00000000000000..719b542874001e --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/Kconfig.mimxrt1064_evk @@ -0,0 +1,5 @@ +# Copyright (c) 2018, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1064_EVK + select SOC_PART_NUMBER_MIMXRT1064DVL6A diff --git a/boards/arm/mimxrt1064_evk/board.cmake b/boards/nxp/mimxrt1064_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1064_evk/board.cmake rename to boards/nxp/mimxrt1064_evk/board.cmake diff --git a/boards/nxp/mimxrt1064_evk/board.yml b/boards/nxp/mimxrt1064_evk/board.yml new file mode 100644 index 00000000000000..b3116560663b44 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1064_evk + vendor: nxp + socs: + - name: mimxrt1064 diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst new file mode 100644 index 00000000000000..38d284f1c47991 --- /dev/null +++ b/boards/nxp/mimxrt1064_evk/doc/index.rst @@ -0,0 +1,477 @@ +.. _mimxrt1064_evk: + +NXP MIMXRT1064-EVK +################## + +Overview +******** + +The i.MX RT1064 adds to the industry's first crossover +processor series and expands the i.MX RT series to three scalable families. +The i.MX RT1064 doubles the On-Chip SRAM to 1MB while keeping pin-to-pin +compatibility with i.MX RT1050. This series introduces additional features +ideal for real-time applications such as High-Speed GPIO, CAN FD, and +synchronous parallel NAND/NOR/PSRAM controller. The i.MX RT1064 runs on the +Arm® Cortex-M7® core up to 600 MHz. + +.. image:: mimxrt1064_evk.jpg + :align: center + :alt: MIMXRT1064-EVK + +Hardware +******** + +- MIMXRT1064DVL6A MCU (600 MHz, 1024 KB on-chip memory, 4096KB on-chip QSPI + flash) + +- Memory + + - 256 Mbit SDRAM + - 64 Mbit QSPI Flash + - 512 Mbit Hyper Flash + - TF socket for SD card + +- Display + + - LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - CMOS camera sensor interface + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1064 SoC and MIMXRT1064-EVK board, see +these references: + +- `i.MX RT1064 Website`_ +- `i.MX RT1064 Datasheet`_ +- `i.MX RT1064 Reference Manual`_ +- `MIMXRT1064-EVK Website`_ +- `MIMXRT1064-EVK Quick Reference Guide`_ +- `MIMXRT1064-EVK User Guide`_ +- `MIMXRT1064-EVK Schematics`_ +- `MIMXRT1064-EVK Debug Firmware`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| MT48LC16M16A2 | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +NXP considers the MIMXRT1064-EVK as the superset board for the i.MX RT10xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT10xx family. NXP prioritizes enabling +this board with new support for Zephyr features. The mimxrt1064_evk board +configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | display | ++-----------+------------+-------------------------------------+ +| VIDEO | on-chip | video, using CSI | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | QSPI flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| ENET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and I/Os +==================== + +The MIMXRT1064 SoC has four pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| GPIO_AD_B0_00 | LPSPI1_SCK | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_01 | LPSPI1_SDO | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_02 | LPSPI3_SDI/LCD_RST| SPI/LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_03 | LPSPI3_PCS0 | SPI | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_05 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | GPIO/ENET_RST | LED/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | GPIO/ENET_INT | GPIO/Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_11 | GPIO | Touch Interrupt | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_12 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_13 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_06 | LPUART3_TX | UART Arduino | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_07 | LPUART3_RX | UART Arduino | ++---------------+-----------------+---------------------------+ +| WAKEUP | GPIO | SW0 | ++---------------+-----------------+---------------------------+ +| GPIO_B0_00 | LCD_CLK | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_01 | LCD_ENABLE | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_02 | LCD_HSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_03 | LCD_VSYNC | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_04 | LCD_DATA00 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_05 | LCD_DATA01 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_06 | LCD_DATA02 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_07 | LCD_DATA03 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_08 | LCD_DATA04 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_09 | LCD_DATA05 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_10 | LCD_DATA06 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_11 | LCD_DATA07 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_12 | LCD_DATA08 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_13 | LCD_DATA09 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_14 | LCD_DATA10 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B0_15 | LCD_DATA11 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_00 | LCD_DATA12 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_01 | LCD_DATA13 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_02 | LCD_DATA14 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_03 | LCD_DATA15 | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_B1_04 | ENET_RX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_05 | ENET_RX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_06 | ENET_RX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_07 | ENET_TX_DATA00 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_08 | ENET_TX_DATA01 | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_09 | ENET_TX_EN | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_10 | ENET_REF_CLK | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_11 | ENET_RX_ER | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_B1_12 | GPIO | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_14 | USDHC1_VSELECT | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_B1_15 | BACKLIGHT_CTL | LCD Display | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_40 | ENET_MDC | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_EMC_41 | ENET_MDIO | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_09 | ENET_RST | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B0_10 | ENET_INT | Ethernet | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_00 | USDHC1_CMD/LPSPI1_SCK | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_01 | USDHC1_CLK/LPSPI1_PCS0 | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_02 | USDHC1_DATA0/LPSPI1_SDO | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_03 | USDHC1_DATA1/LPSPI1_SDI | SD Card/SPI | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_04 | USDHC1_DATA2 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B0_05 | USDHC1_DATA3 | SD Card | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_05 | FLEXSPIA_DQS | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_06 | FLEXSPIA_SS0_B | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_07 | FLEXSPIA_SCLK | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_08 | FLEXSPIA_DATA00 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_09 | FLEXSPIA_DATA01 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_10 | FLEXSPIA_DATA02 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_SD_B1_11 | FLEXSPIA_DATA03 | QSPI Flash | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_11 | ADC | ADC1 Channel 0 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_B1_10 | ADC | ADC1 Channel 1 | ++---------------+-----------------+---------------------------+ + +.. note:: + In order to use the SPI peripheral on this board, resistors R278, R279, + R280 and R281 must be populated with zero ohm resistors + +System Clock +============ + +The MIMXRT1064 SoC is configured to use SysTick as the system clock source, +running at 600MHz. + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1064 SoC has eight UARTs. ``LPUART1`` is configured for the console +and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +.. note:: + When the device transitions into low power states, the debugger may be + unable to access the chip. Use caution when enabling ``CONFIG_PM``, and + if the debugger cannot flash the part, see :ref:`Troubleshooting RT1064` + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +.. _Using LinkServer: + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `MIMXRT1064-EVK Debug Firmware` + +.. _Using J-Link RT1064: + +Using J-Link +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK`_ for more +details. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J45 and J46 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J41. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Using SWO +--------- +SWO can be used as a logging backend, by setting ``CONFIG_LOG_BACKEND_SWO=y``. +Your SWO viewer should be configured with a CPU frequency of 132MHz, and +SWO frequency of 7500KHz. + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1064_evk + :goals: flash + +Open a serial terminal, reset the board (press the SW9 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1064_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1064_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! mimxrt1064_evk + + +.. _Troubleshooting RT1064: + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the boot header in QSPI flash is invalid or corrupted. The boot header is +configured by :kconfig:option:`CONFIG_NXP_IMXRT_BOOT_HEADER`. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the QSPI flash with the following +steps: + +#. Set the SW7 DIP switches to ON-OFF-ON-OFF to prevent booting from QSPI flash. + +#. Reset by pressing SW9 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application. + +#. Set the SW7 DIP switches to OFF-OFF-ON-OFF to boot from QSPI flash. + +#. Reset by pressing SW9 + +If the west flash or debug commands fail, and the command hangs while executing +runners.jlink, confirm the J-Link debug probe is configured, powered, and +connected to the EVK properly. See :ref:`Using J-Link RT1064` for more +details. + +.. _MIMXRT1064-EVK Website: + https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK + +.. _MIMXRT1064-EVK Quick Reference Guide: + https://www.nxp.com/webapp/Download?colCode=IMXRT1064QSG + +.. _MIMXRT1064-EVK User Guide: + https://www.nxp.com/docs/en/data-sheet/MIMXRT10601064EKBHUG.pdf + +.. _MIMXRT1064-EVK Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _MIMXRT1064-EVK Schematics: + https://www.nxp.com/webapp/Download?colCode=i.MXRT160EVKDS&Parent_nodeId=1537930933174731284155&Parent_pageType=product + +.. _i.MX RT1064 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1064-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1064 + +.. _i.MX RT1064 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1064CEC.pdf + +.. _i.MX RT1064 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1064RM + +.. _Using J-Link with MIMXRT1060-EVK or MIMXRT1064-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1060-EVK-or-MIMXRT1064-EVK/ta-p/1281149 diff --git a/boards/arm/mimxrt1064_evk/doc/mimxrt1064_evk.jpg b/boards/nxp/mimxrt1064_evk/doc/mimxrt1064_evk.jpg similarity index 100% rename from boards/arm/mimxrt1064_evk/doc/mimxrt1064_evk.jpg rename to boards/nxp/mimxrt1064_evk/doc/mimxrt1064_evk.jpg diff --git a/boards/arm/mimxrt1064_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1064_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1064_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1064_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts similarity index 100% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk.dts rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml similarity index 100% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk.yaml rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml diff --git a/boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig similarity index 79% rename from boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig rename to boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig index 22911d8b782b9b..8af2d46280907d 100644 --- a/boards/arm/mimxrt1064_evk/mimxrt1064_evk_defconfig +++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1064=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/mimxrt1160_evk/CMakeLists.txt b/boards/nxp/mimxrt1160_evk/CMakeLists.txt new file mode 100644 index 00000000000000..928a9693df79bc --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/CMakeLists.txt @@ -0,0 +1,44 @@ +# +# Copyright 2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7) + OR (DEFINED CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4))) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1160-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + set(RT1160_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1160") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1160 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1160_BOARD_DIR}/xip/evkmimxrt1160_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1160_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1160 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1160_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..340878191a031a --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig @@ -0,0 +1,53 @@ +# MIMXRT1160-EVK board + +# Copyright 2021,2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1160_EVK + +# Only use DCD when booting primary core (M7) +config DEVICE_CONFIGURATION_DATA + default y if CPU_CORTEX_M7 + +config NXP_IMX_EXTERNAL_SDRAM + default y if CPU_CORTEX_M7 + +if SECOND_CORE_MCUX && BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 + +config BUILD_OUTPUT_INFO_HEADER + default y + +DT_CHOSEN_IMAGE_M4 = nxp,m4-partition + +# Adjust the offset of the output image if building for RT11xx SOC +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ + $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ + $(dt_node_reg_addr_hex,/soc/ocram@20200000)" + +endif + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 240000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 && CORTEX_M_SYSTICK + default 600000000 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 && CORTEX_M_SYSTICK + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +if NETWORKING + +config NET_L2_ETHERNET + default y if CPU_CORTEX_M7 # No cache memory support is required for driver + +config ETH_MCUX_PHY_RESET + default y + +endif # NETWORKING + +endif # BOARD_MIMXRT1160_EVK diff --git a/boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk b/boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk new file mode 100644 index 00000000000000..7a58b49cbbc8bb --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/Kconfig.mimxrt1160_evk @@ -0,0 +1,10 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MIMXRT1160_EVK + select SOC_PART_NUMBER_MIMXRT1166DVM6A + select SOC_MIMXRT1166_CM7 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 + select SOC_MIMXRT1166_CM4 if BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 diff --git a/boards/arm/mimxrt1160_evk/board.cmake b/boards/nxp/mimxrt1160_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt1160_evk/board.cmake rename to boards/nxp/mimxrt1160_evk/board.cmake diff --git a/boards/nxp/mimxrt1160_evk/board.yml b/boards/nxp/mimxrt1160_evk/board.yml new file mode 100644 index 00000000000000..4fe56f8d256ebd --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt1160_evk + vendor: nxp + socs: + - name: mimxrt1166 diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst new file mode 100644 index 00000000000000..501182df322cb2 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/doc/index.rst @@ -0,0 +1,366 @@ +.. _mimxrt1160_evk: + +NXP MIMXRT1160-EVK +################## + +Overview +******** + +The dual core i.MX RT1160 runs on the Cortex-M7 core at 600 MHz and on the +Cortex-M4 at 240 MHz. The i.MX RT1160 MCU offers support over a wide +temperature range and is qualified for consumer, industrial and automotive +markets. + +.. image:: mimxrt1160_evk.jpg + :align: center + :alt: MIMXRT1160-EVK + +Hardware +******** + +- MIMXRT1166DVM6A MCU + + - 600MHz Cortex-M7 & 240Mhz Cortex-M4 + - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit Octal Flash + - TF socket for SD card + +- Display + + - MIPI LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + - 10/100/1000 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - MIPI camera sensor connector + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1160 SoC and MIMXRT1160-EVK board, see +these references: + +- `i.MX RT1160 Website`_ +- `i.MX RT1160 Datasheet`_ +- `i.MX RT1160 Reference Manual`_ +- `MIMXRT1160-EVK Website`_ +- `MIMXRT1160-EVK Board Hardware User's Guide`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| W9825G6KH | SEMC | Enabled via device configuration | +| | | data block, which sets up SEMC at | +| | | boot time | ++--------------------+------------+-------------------------------------+ +| IS25WP128 | FLEXSPI | Enabled via flash configurationn | +| | | block, which sets up FLEXSPI at | +| | | boot time. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +The mimxrt1160_evk board configuration supports the hardware features listed +below. For additional features not yet supported, please also refer to the +:ref:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family. +NXP prioritizes enabling the superset board with NXP's Full Platform Support for +Zephyr. Therefore, the mimxrt1170_evk board may have additional features +already supported, which can also be re-used on this mimxrt1160_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | flexcan | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ +| GPT | on-chip | gpt | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB Device | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| CAAM RNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig` + +Other hardware features are not currently supported by the port. + + +Connections and I/Os +==================== + +The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| WAKEUP | GPIO | SW7 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_04 | GPIO | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AD_24 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_25 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_00 | CAN3_TX | flexcan | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_01 | CAN3_RX | flexcan | ++---------------+-----------------+---------------------------+ +| GPIO_AD_29 | SPI1_CS0 | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_28 | SPI1_CLK | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_30 | SPI1_SDO | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_31 | SPI1_SDI | spi | ++---------------+-----------------+---------------------------+ +| GPIO_AD_08 | LPI2C1_SCL | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_AD_09 | LPI2C1_SDA | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_05 | LPI2C5_SCL | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_LPSR_04 | LPI2C5_SDA | i2c | ++---------------+-----------------+---------------------------+ +| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | ++---------------+-----------------+---------------------------+ + + +Dual Core samples +***************** + ++-----------+------------------+----------------------------+ +| Core | Boot Address | Comment | ++===========+==================+============================+ +| Cortex M7 | 0x30000000[630K] | primary core | ++-----------+------------------+----------------------------+ +| Cortex M4 | 0x20020000[96k] | boots from OCRAM | ++-----------+------------------+----------------------------+ + ++----------+------------------+-----------------------+ +| Memory | Address[Size] | Comment | ++==========+==================+=======================+ +| flexspi1 | 0x30000000[16M] | Cortex M7 flash | ++----------+------------------+-----------------------+ +| sdram0 | 0x80030000[64M] | Cortex M7 ram | ++----------+------------------+-----------------------+ +| ocram | 0x20020000[512K] | Cortex M4 "flash" | ++----------+------------------+-----------------------+ +| sram1 | 0x20000000[128K] | Cortex M4 ram | ++----------+------------------+-----------------------+ +| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | ++----------+------------------+-----------------------+ + +Only the first 16K of ocram2 has the correct MPU region attributes set to be +used as shared memory + +System Clock +============ + +The MIMXRT1160 SoC is configured to use SysTick as the system clock source, +running at 600MHz. When targeting the M4 core, SysTick will also be used, +running at 240MHz + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1160 SoC has 12 UARTs. One is configured for the console and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Building a Dual-Core Image +========================== +Dual core samples load the M4 core image from flash into the shared ``ocram`` +region. The M7 core then sets the M4 boot address to this region. The only +sample currently enabled for dual core builds is the ``openamp`` sample. +To flash a dual core sample, the M4 image must be flashed first, so that it is +written to flash. Then, the M7 image must be flashed. The openamp sysbuild +sample will do this automatically by setting the image order. + +The secondary core can be debugged normally in single core builds +(where the target is ``mimxrt1160_evk/mimxrt1166/cm4``). For dual core builds, the +secondary core should be placed into a loop, then a debugger can be attached +(see `AN13264`_, section 4.2.3 for more information) + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +.. _Using J-Link RT1160: + +Using J-Link +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J5 and J8 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J11. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +Before power on the board, make sure SW1 is set to 0001b + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1160_evk/mimxrt1166/cm7 + :goals: flash + +Power off the board, and change SW1 to 0010b. Then power on the board and +open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.6.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1160_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1160_evk/mimxrt1166/cm7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1160_evk + +.. _MIMXRT1160-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1160-evaluation-kit:MIMXRT1160-EVK + +.. _MIMXRT1160-EVK Board Hardware User's Guide: + https://www.nxp.com/webapp/Download?colCode=UM11617 + +.. _i.MX RT1160 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1160-crossover-mcu-family-high-performance-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1160 + +.. _i.MX RT1160 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1160CEC.pdf + +.. _i.MX RT1160 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1160RM + +.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 + +.. _AN13264: + https://www.nxp.com/docs/en/application-note/AN13264.pdf + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1160_evk/doc/mimxrt1160_evk.jpg b/boards/nxp/mimxrt1160_evk/doc/mimxrt1160_evk.jpg similarity index 100% rename from boards/arm/mimxrt1160_evk/doc/mimxrt1160_evk.jpg rename to boards/nxp/mimxrt1160_evk/doc/mimxrt1160_evk.jpg diff --git a/boards/arm/mimxrt1160_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1160_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1160_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1160_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk.dtsi diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.dts diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml new file mode 100644 index 00000000000000..400e501406f2b2 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml @@ -0,0 +1,23 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1160_evk/mimxrt1166/cm4 +name: NXP MIMXRT1160-EVK CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - dma + - i2c + - gpio + - pwm + - uart +vendor: nxp diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig new file mode 100644 index 00000000000000..5139427b850b5b --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts similarity index 100% rename from boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts rename to boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.dts diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml new file mode 100644 index 00000000000000..9ff9b57258d2e4 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml @@ -0,0 +1,29 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1160_evk/mimxrt1166/cm7 +name: NXP MIMXRT1160-EVK CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 16384 +supported: + - counter + - can + - dma + - gpio + - hwinfo + - i2c + - netif:eth + - pwm + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig new file mode 100644 index 00000000000000..78f5191a1545b0 --- /dev/null +++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig @@ -0,0 +1,14 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt1170_evk/CMakeLists.txt b/boards/nxp/mimxrt1170_evk/CMakeLists.txt new file mode 100644 index 00000000000000..c564e77e49273c --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/CMakeLists.txt @@ -0,0 +1,49 @@ +# +# Copyright 2022-2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + if(NOT ((DEFINED CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7) + OR (DEFINED CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4))) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT1170-EVK, but targeting a custom board. You may need to " + "update your flash configuration or device configuration data blocks") + endif() + if (${BOARD_REVISION} STREQUAL "A") + set(RT1170_BOARD_NAME "evkmimxrt1170") + elseif (${BOARD_REVISION} STREQUAL "B") + set(RT1170_BOARD_NAME "evkbmimxrt1170") + endif() + set(RT1170_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${RT1170_BOARD_NAME}") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(${RT1170_BOARD_DIR}/xip/${RT1170_BOARD_NAME}_flexspi_nor_config.c) + zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) + endif() + if(CONFIG_DEVICE_CONFIGURATION_DATA) + # Include device configuration data block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another SDRAM chip + # is used on your custom board. + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_library_sources(${RT1170_BOARD_DIR}/dcd.c) + else() + if(CONFIG_SRAM_BASE_ADDRESS EQUAL 0x80000000) + message(WARNING "You are using SDRAM as RAM but no device " + "configuration data (DCD) is included. This configuration may not boot") + endif() + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..395d8351794c16 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig @@ -0,0 +1,56 @@ +# MIMXRT1170-EVK board + +# Copyright 2021,2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1170_EVK + +# Only use DCD when booting primary core (M7) +config DEVICE_CONFIGURATION_DATA + default y if CPU_CORTEX_M7 + +config NXP_IMX_EXTERNAL_SDRAM + default y if CPU_CORTEX_M7 + +if SECOND_CORE_MCUX && CPU_CORTEX_M4 + +config BUILD_OUTPUT_INFO_HEADER + default y + +DT_CHOSEN_IMAGE_M4 = nxp,m4-partition + +# Adjust the offset of the output image if building for RT11xx SOC +config BUILD_OUTPUT_ADJUST_LMA + default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M4)) + \ + $(dt_node_reg_addr_hex,/soc/spi@400cc000,1)) - \ + $(dt_node_reg_addr_hex,/soc/ocram@20200000)" + +endif + +if DISK_DRIVERS + +config IMX_USDHC_DAT3_PWR_TOGGLE + default y + +endif # DISK_DRIVERS + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +if NETWORKING + +config NET_L2_ETHERNET + default y if CPU_CORTEX_M7 # No cache memory support is required for driver + +config ETH_MCUX_PHY_RESET + default y + +endif # NETWORKING + +endif diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.mimxrt1170_evk b/boards/nxp/mimxrt1170_evk/Kconfig.mimxrt1170_evk new file mode 100644 index 00000000000000..c17775510766e7 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/Kconfig.mimxrt1170_evk @@ -0,0 +1,9 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1170_EVK + select SOC_PART_NUMBER_MIMXRT1176DVMAA + select SOC_MIMXRT1176_CM7 if BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 + select SOC_MIMXRT1176_CM4 if BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 diff --git a/boards/nxp/mimxrt1170_evk/board.cmake b/boards/nxp/mimxrt1170_evk/board.cmake new file mode 100644 index 00000000000000..d1438e4a7b174a --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/board.cmake @@ -0,0 +1,32 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMXRT1176_CM7 OR CONFIG_SECOND_CORE_MCUX) + board_runner_args(pyocd "--target=mimxrt1170_cm7") + board_runner_args(jlink "--device=MIMXRT1176xxxA_M7" "--reset-after-load") + + if(${BOARD_REVISION} STREQUAL "A") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + elseif(${BOARD_REVISION} STREQUAL "B") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") + endif() + + board_runner_args(linkserver "--core=cm7") +elseif(CONFIG_SOC_MIMXRT1176_CM4) + board_runner_args(pyocd "--target=mimxrt1170_cm4") + # Note: Please use JLINK above V7.50 (Only support run cm4 image when debugging due to default boot core on board is cm7 core) + board_runner_args(jlink "--device=MIMXRT1176xxxA_M4") + if(${BOARD_REVISION} STREQUAL "A") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVK") + elseif(${BOARD_REVISION} STREQUAL "B") + board_runner_args(linkserver "--device=MIMXRT1176xxxxx:MIMXRT1170-EVKB") + endif() + board_runner_args(linkserver "--core=cm4") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt1170_evk/board.yml b/boards/nxp/mimxrt1170_evk/board.yml new file mode 100644 index 00000000000000..0b8e2b058e014a --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/board.yml @@ -0,0 +1,11 @@ +board: + name: mimxrt1170_evk + vendor: nxp + socs: + - name: mimxrt1176 + revision: + format: "letter" + default: "A" + revisions: + - name: "A" + - name: "B" diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst new file mode 100644 index 00000000000000..40dffaba765e65 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/doc/index.rst @@ -0,0 +1,454 @@ +.. _mimxrt1170_evk: + +NXP MIMXRT1170-EVK/EVKB +####################### + +Overview +******** + +The dual core i.MX RT1170 runs on the Cortex-M7 core at 1 GHz and on the Cortex-M4 +at 400 MHz. The i.MX RT1170 MCU offers support over a wide temperature range +and is qualified for consumer, industrial and automotive markets. Zephyr +supports the initial revision of this EVK, as well as rev EVKB. + +.. image:: mimxrt1170_evk.jpg + :align: center + :alt: MIMXRT1170-EVK + +Hardware +******** + +- MIMXRT1176DVMAA MCU + + - 1GHz Cortex-M7 & 400Mhz Cortex-M4 + - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit Octal Flash + - 2 Gbit raw NAND flash + - 64 Mbit LPSPI flash + - TF socket for SD card + +- Display + + - MIPI LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + - 10/100/1000 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - on-board debugger + +- Sensor + + - FXOS8700CQ 6-axis e-compass + - MIPI camera sensor connector + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1170 SoC and MIMXRT1170-EVK board, see +these references: + +- `i.MX RT1170 Website`_ +- `i.MX RT1170 Datasheet`_ +- `i.MX RT1170 Reference Manual`_ +- `MIMXRT1170-EVK Website`_ +- `MIMXRT1170-EVK Board Hardware User's Guide`_ + +External Memory +=============== + +This platform has the following external memories: + ++--------------------+------------+-------------------------------------+ +| Device | Controller | Status | ++====================+============+=====================================+ +| W9825G6KH | SEMC | Enabled via device configuration | +| SDRAM | | data (DCD) block, which sets up | +| | | the SEMC at boot time | ++--------------------+------------+-------------------------------------+ +| IS25WP128 | FLEXSPI | Enabled via flash configuration | +| QSPI flash | | block (FCB), which sets up the | +| (RT1170 EVK) | | FLEXSPI at boot time. | ++--------------------+------------+-------------------------------------+ +| W25Q512NWEIQ | FLEXSPI | Enabled via flash configuration | +| QSPI flash | | block (FCB), which sets up the | +| (RT1170 EVKB) | | FLEXSPI at boot time. Supported for | +| | | XIP only. | ++--------------------+------------+-------------------------------------+ + +Supported Features +================== + +NXP considers the MIMXRT1170-EVK as the superset board for the i.MX RT11xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT11xx family. NXP prioritizes enabling +this board with new support for Zephyr features. Note that this table +covers two boards: the RT1170 EVK (`mimxrt1170_evk//cm7/cm4`), and +RT1170 EVKB (`mimxrt1170_evk@B//cm7/cm4`) + ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| Interface | Controller | Driver/Component | RT1170 EVK | RT1170 EVKB | ++===========+============+=====================================+=================+=================+ +| NVIC | on-chip | nested vector interrupt controller | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SYSTICK | on-chip | systick | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| GPIO | on-chip | gpio | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| COUNTER | on-chip | gpt | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| TIMER | on-chip | gpt | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| CAN | on-chip | flexcan | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SPI | on-chip | spi | Supported (M7) | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| I2C | on-chip | i2c | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| PWM | on-chip | pwm | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| ADC | on-chip | adc | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| UART | on-chip | serial port-polling; | Supported | Supported | +| | | serial port-interrupt; | | | +| | | serial port-async | | | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| DMA | on-chip | dma | Supported | Supported | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| WATCHDOG | on-chip | watchdog | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| ENET | on-chip | ethernet - 10/100M (ENET_QOS or | Supported (M7) | No support | +| ENET1G | | GigE not supported yet) | | | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SAI | on-chip | i2s | Supported | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| USB | on-chip | USB Device | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| HWINFO | on-chip | Unique device serial number | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| DISPLAY | on-chip | eLCDIF; MIPI-DSI. Tested with | Supported (M7) | Supported (M7) | +| | | :ref:`rk055hdmipi4m`, | | | +| | | :ref:`rk055hdmipi4ma0`, | | | +| | | and :ref:`g1120b0mipi` shields | | | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| ACMP | on-chip | analog comparator | Supported | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| CAAM RNG | on-chip | entropy | Supported (M7) | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| FLEXSPI | on-chip | flash programming | Supported (M7) | No support | ++-----------+------------+-------------------------------------+-----------------+-----------------+ +| SDHC | on-chip | SD host controller | Supported (M7) | Supported (M7) | ++-----------+------------+-------------------------------------+-----------------+-----------------+ + +The default configuration can be found in the defconfig files: +:zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig` +:zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig` + +Connections and I/Os +==================== + +The MIMXRT1170 SoC has six pairs of pinmux/gpio controllers. + ++---------------------------+----------------+------------------+ +| Name | Function | Usage | ++---------------------------+----------------+------------------+ +| WAKEUP | GPIO | SW7 | ++---------------------------+----------------+------------------+ +| GPIO_AD_04 | GPIO | LED | ++---------------------------+----------------+------------------+ +| GPIO_AD_24 | LPUART1_TX | UART Console | ++---------------------------+----------------+------------------+ +| GPIO_AD_25 | LPUART1_RX | UART Console | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_00 | CAN3_TX | flexcan | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_01 | CAN3_RX | flexcan | ++---------------------------+----------------+------------------+ +| GPIO_AD_29 | SPI1_CS0 | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_28 | SPI1_CLK | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_30 | SPI1_SDO | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_31 | SPI1_SDI | spi | ++---------------------------+----------------+------------------+ +| GPIO_AD_08 | LPI2C1_SCL | i2c | ++---------------------------+----------------+------------------+ +| GPIO_AD_09 | LPI2C1_SDA | i2c | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_05 | LPI2C5_SCL | i2c | ++---------------------------+----------------+------------------+ +| GPIO_LPSR_04 | LPI2C5_SDA | i2c | ++---------------------------+----------------+------------------+ +| GPIO_AD_04 | FLEXPWM1_PWM2 | pwm | ++---------------------------+----------------+------------------+ +| GPIO_AD_32 | ENET_MDC | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_AD_33 | ENET_MDIO | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_02 | ENET_TX_DATA00 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_03 | ENET_TX_DATA01 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_04 | ENET_TX_EN | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_05 | ENET_REF_CLK | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_06 | ENET_RX_DATA00 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_07 | ENET_RX_DATA01 | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_08 | ENET_RX_EN | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_DISP_B2_09 | ENET_RX_ER | Ethernet | ++---------------------------+----------------+------------------+ +| GPIO_AD_17_SAI1_MCLK | SAI_MCLK | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_21_SAI1_TX_DATA00 | SAI1_TX_DATA | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_22_SAI1_TX_BCLK | SAI1_TX_BCLK | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_23_SAI1_TX_SYNC | SAI1_TX_SYNC | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_17_SAI1_MCLK | SAI1_MCLK | SAI | ++---------------------------+----------------+------------------+ +| GPIO_AD_20_SAI1_RX_DATA00 | SAI1_RX_DATA00 | SAI | ++---------------------------+----------------+------------------+ + +Dual Core samples +***************** + ++-----------+------------------+----------------------------+ +| Core | Boot Address | Comment | ++===========+==================+============================+ +| Cortex M7 | 0x30000000[630K] | primary core | ++-----------+------------------+----------------------------+ +| Cortex M4 | 0x20020000[96k] | boots from OCRAM | ++-----------+------------------+----------------------------+ + ++----------+------------------+-----------------------+ +| Memory | Address[Size] | Comment | ++==========+==================+=======================+ +| flexspi1 | 0x30000000[16M] | Cortex M7 flash | ++----------+------------------+-----------------------+ +| sdram0 | 0x80030000[64M] | Cortex M7 ram | ++----------+------------------+-----------------------+ +| ocram | 0x20020000[512K] | Cortex M4 "flash" | ++----------+------------------+-----------------------+ +| sram1 | 0x20000000[128K] | Cortex M4 ram | ++----------+------------------+-----------------------+ +| ocram2 | 0x200C0000[512K] | Mailbox/shared memory | ++----------+------------------+-----------------------+ + +Only the first 16K of ocram2 has the correct MPU region attributes set to be +used as shared memory + +System Clock +============ + +The MIMXRT1170 SoC is configured to use SysTick as the system clock source, +running at 996MHz. When targeting the M4 core, SysTick will also be used, +running at 400MHz + +When power management is enabled, the 32 KHz low frequency +oscillator on the board will be used as a source for the GPT timer to +generate a system clock. This clock enables lower power states, at the +cost of reduced resolution + +Serial Port +=========== + +The MIMXRT1170 SoC has 12 UARTs. One is configured for the console and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Building a Dual-Core Image +========================== +Dual core samples load the M4 core image from flash into the shared ``ocram`` +region. The M7 core then sets the M4 boot address to this region. The only +sample currently enabled for dual core builds is the ``openamp`` sample. +To flash a dual core sample, the M4 image must be flashed first, so that it is +written to flash. Then, the M7 image must be flashed. The openamp sysbuild +sample will do this automatically by setting the image order. + +The secondary core can be debugged normally in single core builds +(where the target is ``mimxrt1170_evk/mimxrt1176/cm4``). For dual core builds, the +secondary core should be placed into a loop, then a debugger can be attached +(see `AN13264`_, section 4.2.3 for more information) + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. The on-board +debugger listed below works with the LinkServer runner by default, or can be +reprogrammed with JLink firmware. +- MIMXRT1170-EVKB: :ref:`mcu-link-cmsis-onboard-debug-probe` +- MIMXRT1170-EVK: :ref:`opensda-daplink-onboard-debug-probe` + +Using J-Link +------------ + +JLink is the default runner for this board. Install the +:ref:`jlink-debug-host-tools` and make sure they are in your search path. + +There are two options: the onboard debug circuit can be updated with Segger +J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the +EVK. See `Using J-Link with MIMXRT1170-EVKB`_ or +`Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details. + +Using LinkServer +---------------- + +Known limitations with LinkServer and these boards include: +- ``west debug`` does not yet work correctly, and the application image is not +properly written to the memory. `NXP MCUXpresso for Visual Studio Code`_ +can be used to debug Zephyr applications with LinkServer. +- ``west flash`` will not write images to non-flash locations. The flash +command only works when all data in the image is written to flash memory +regions. + +Install the :ref:`linkserver-debug-host-tools` and make sure they are in your +search path. LinkServer works with the default CMSIS-DAP firmware included in +the on-board debugger. + +Use the ``-r linkserver`` option with West to use the LinkServer runner. + +.. code-block:: console + + west flash -r linkserver + +Alternatively, pyOCD can be used to flash and debug the board by using the +``-r pyocd`` option with West. pyOCD is installed when you complete the +:ref:`gs_python_deps` step in the Getting Started Guide. The runners supported +by NXP are LinkServer and JLink. pyOCD is another potential option, but NXP +does not test or support the pyOCD runner. + +Configuring a Console +===================== + +We will use the on-board debugger +microcontroller as a usb-to-serial adapter for the serial console. The following +jumper settings are default on these boards, and are required to connect the +UART signals to the USB bridge circuit: +- MIMXRT1170-EVKB: JP2 open (default) +- MIMXRT1170-EVK: J31 and J32 shorted (default) + +Connect a USB cable from your PC to the on-board debugger USB port: +- MIMXRT1170-EVKB: J86 +- MIMXRT1170-EVK: J11 + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +Before powering the board, make sure SW1 is set to 0001b + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1170_evk/mimxrt1176/cm7 + :goals: flash + +Power off the board, and change SW1 to 0010b. Then power on the board and +open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1170_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1170_evk/mimxrt1176/cm7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1170_evk + +.. _MIMXRT1170-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK + +.. _MIMXRT1170-EVK Board Hardware User's Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKHUG + +.. _i.MX RT1170 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170 + +.. _i.MX RT1170 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1170CEC.pdf + +.. _i.MX RT1170 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1170RM + +.. _Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1160-EVK-or-MIMXRT1170-EVK/ta-p/1529760 + +.. _Using J-Link with MIMXRT1170-EVKB: + https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-J-Link-with-MIMXRT1170-EVKB/ta-p/1715138 + +.. _AN13264: + https://www.nxp.com/docs/en/application-note/AN13264.pdf + +.. _NXP MCUXpresso for Visual Studio Code: + https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC + +Experimental ENET Driver +======================== + +Current default ethernet driver is eth_mcux, with binding `nxp,kinetis-ethernet`. There is a new +driver with binding `nxp,enet`, which is experimental and undergoing development, but will have +enhanced capability, such as not hardcoding code for only one phy in the driver like eth_mcux. + +To build for this EVK with the new driver, include the experimental overlay to west build with +the option `-DEXTRA_DTC_OVERLAY_FILE=nxp,enet-experimental.overlay`. diff --git a/boards/arm/mimxrt1170_evk/doc/mimxrt1170_evk.jpg b/boards/nxp/mimxrt1170_evk/doc/mimxrt1170_evk.jpg similarity index 100% rename from boards/arm/mimxrt1170_evk/doc/mimxrt1170_evk.jpg rename to boards/nxp/mimxrt1170_evk/doc/mimxrt1170_evk.jpg diff --git a/boards/arm/mimxrt1170_evk/dts/nxp,enet-experimental.overlay b/boards/nxp/mimxrt1170_evk/dts/nxp,enet-experimental.overlay similarity index 100% rename from boards/arm/mimxrt1170_evk/dts/nxp,enet-experimental.overlay rename to boards/nxp/mimxrt1170_evk/dts/nxp,enet-experimental.overlay diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk-pinctrl.dtsi diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk.dtsi b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk.dtsi rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk.dtsi diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm4.dts rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.dts diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml new file mode 100644 index 00000000000000..87788b3a0153dc --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml @@ -0,0 +1,22 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk/mimxrt1176/cm4 +name: NXP MIMXRT1170-EVK CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - dma + - gpio + - i2c + - pwm +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000000..c92d197f548dee --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,81 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /delete-property/ zephyr,flash-controller; + /delete-property/ zephyr,code-partition; + }; + + aliases { + /delete-property/ magn0; + /delete-property/ accel0; + }; +}; + +&flexspi { + /* RT1170 EVKB uses a different QSPI flash chip */ + /delete-node/ is25wp128@0; + status = "okay"; + reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; + w25q512nw:w25q512nw@0 { + /* IS25WP128 flash chip not currently enabled */ + compatible = "nxp,imx-flexspi-nor"; + size = ; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [ef 60 20]; + erase-block-size = <4096>; + write-block-size = <1>; + + /* + * Partitions are present to support dual core operation. + * as flash write is not supported, MCUBoot is not enabled. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x301000>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 0x300000>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_K(1984)>; + }; + }; + }; +}; + +&lpspi1 { + dmas = <&edma_lpsr0 0 36>, <&edma_lpsr0 1 37>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +&lpi2c5 { + /* FXOS accelerometer is not present in this board */ + /delete-node/ fxos8700@1f; +}; + +/* Disable ethernet, as PHY is not supported */ +&enet { + status = "disabled"; +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml new file mode 100644 index 00000000000000..da1f36a162c29c --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml @@ -0,0 +1,23 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk@B/mimxrt1176/cm4 +name: NXP MIMXRT1170-EVKB CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - dma + - gpio + - i2c + - spi + - pwm +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig new file mode 100644 index 00000000000000..822498def23bbf --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2021,2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts similarity index 100% rename from boards/arm/mimxrt1170_evk/mimxrt1170_evk_cm7.dts rename to boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml new file mode 100644 index 00000000000000..c7e846adf6ab30 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml @@ -0,0 +1,31 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk/mimxrt1176/cm7 +name: NXP MIMXRT1170-EVK CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 16384 +supported: + - adc + - counter + - can + - dma + - gpio + - hwinfo + - i2c + - mipi_dsi + - netif:eth + - pwm + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000000..4073b78a83e3e3 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,76 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &w25q512nw; + /delete-property/ zephyr,flash-controller; + /delete-property/ zephyr,code-partition; + }; + + aliases { + /delete-property/ magn0; + /delete-property/ accel0; + }; +}; + +&flexspi { + /* RT1170 EVKB uses a different QSPI flash chip */ + /delete-node/ is25wp128@0; + status = "okay"; + reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(64)>; + w25q512nw:w25q512nw@0 { + /* IS25WP128 flash chip not currently enabled */ + compatible = "nxp,imx-flexspi-nor"; + size = ; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [ef 60 20]; + erase-block-size = <4096>; + write-block-size = <1>; + + /* + * Partitions are present to support dual core operation. + * as flash write is not supported, MCUBoot is not enabled. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + /* Note slot 0 has one additional sector, + * this is intended for use with the swap move algorithm + */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x301000>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 0x300000>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_K(1984)>; + }; + }; + }; +}; + +&lpi2c5 { + /* FXOS accelerometer is not present in this board */ + /delete-node/ fxos8700@1f; +}; + +/* Disable ethernet, as PHY is not supported */ +&enet { + status = "disabled"; +}; diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml new file mode 100644 index 00000000000000..5cdfdf97c87571 --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml @@ -0,0 +1,29 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1170_evk@B/mimxrt1176/cm7 +name: NXP MIMXRT1170-EVKB CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 65536 +flash: 65536 +supported: + - adc + - counter + - can + - dma + - gpio + - hwinfo + - i2c + - mipi_dsi + - spi + - usb_device + - watchdog +vendor: nxp diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig new file mode 100644 index 00000000000000..822498def23bbf --- /dev/null +++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig @@ -0,0 +1,13 @@ +# +# Copyright 2021,2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_PINCTRL=y diff --git a/boards/nxp/mimxrt595_evk/CMakeLists.txt b/boards/nxp/mimxrt595_evk/CMakeLists.txt new file mode 100644 index 00000000000000..f7db55d9430ffb --- /dev/null +++ b/boards/nxp/mimxrt595_evk/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright 2022-2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_BOARD_MIMXRT595_EVK_MIMXRT595S_CM33) + zephyr_library() + zephyr_library_sources(board.c) + zephyr_library_include_directories(.) +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + if(NOT DEFINED CONFIG_BOARD_MIMXRT595_EVK_MIMXRT595S_CM33) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT595-EVK, but targeting a custom board. You may need to " + "update your flash configuration block data") + endif() + # Include flash configuration block for R595 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN13304 for more information. + zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT595_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt595") + zephyr_library_sources(${RT595_BOARD_DIR}/flash_config/flash_config.c) + zephyr_library_include_directories(${RT595_BOARD_DIR}/flash_config) +endif() + +# Add custom linker section to relocate framebuffers to PSRAM +zephyr_linker_sources_ifdef(CONFIG_LV_Z_VBD_CUSTOM_SECTION + SECTIONS dc_ram.ld) diff --git a/boards/nxp/mimxrt595_evk/Kconfig b/boards/nxp/mimxrt595_evk/Kconfig new file mode 100644 index 00000000000000..c97c859f16dd53 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/Kconfig @@ -0,0 +1,48 @@ +# Copyright 2022, NXP +# Copyright (c) 2023 Google LLC. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INIT_PRIORITY + int "Board initialization priority" + default 45 + help + Board initialization priority. + +DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset) +DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data) +DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text) + +if BOARD_MIMXRT595_EVK_MIMXRT595S_F1 + +config RT595_ADSP_STACK_SIZE + hex "Boot time stack size" + default 0x1000 + help + Stack space is reserved at the end of the RT595_ADSP_DATA_MEM + region, starting at RT595_ADSP_DATA_MEM_ADDR - RT595_ADSP_STACK_SIZE + +config RT595_ADSP_RESET_MEM_ADDR + hex + default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM)) + +config RT595_ADSP_RESET_MEM_SIZE + hex + default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM)) + +config RT595_ADSP_DATA_MEM_ADDR + hex + default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM)) + +config RT595_ADSP_DATA_MEM_SIZE + hex + default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM)) + +config RT595_ADSP_TEXT_MEM_ADDR + hex + default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM)) + +config RT595_ADSP_TEXT_MEM_SIZE + hex + default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM)) + +endif # BOARD_MIMXRT595_EVK_RT595_F1 diff --git a/boards/nxp/mimxrt595_evk/Kconfig.defconfig b/boards/nxp/mimxrt595_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..9813fb6bdf19d7 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/Kconfig.defconfig @@ -0,0 +1,39 @@ +# MIMXRT595-EVK board + +# Copyright 2022-2023, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33 + +config FLASH_MCUX_FLEXSPI_MX25UM51345G + default y if FLASH + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +if DMA_MCUX_LPC + +# Memory from the heap pool is used to allocate DMA descriptors for +# channels that use multiple blocks for a DMA transfer. +# Adjust HEAP_MEM_POOL_MIN_SIZE in case you need more memory. +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 + +endif # DMA_MCUX_LPC + +# Turn on Device Level Power Management as we wish +# to reconfigure the FlexSPI pins for power savings +# when transitioning the SoC to Deep Low Power modes. +config PM_DEVICE + default y if PM + +config REGULATOR + default y if PM || POWEROFF + +endif # BOARD_MIMXRT595_EVK_MIMXRT595S_CM33 diff --git a/boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk b/boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk new file mode 100644 index 00000000000000..eaf79c89a5dfc9 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/Kconfig.mimxrt595_evk @@ -0,0 +1,10 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_MIMXRT595_EVK + select SOC_PART_NUMBER_MIMXRT595SFFOC + select SOC_MIMXRT595S_CM33 if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33 + select SOC_MIMXRT595S_F1 if BOARD_MIMXRT595_EVK_MIMXRT595S_F1 diff --git a/boards/arm/mimxrt595_evk/board.c b/boards/nxp/mimxrt595_evk/board.c similarity index 100% rename from boards/arm/mimxrt595_evk/board.c rename to boards/nxp/mimxrt595_evk/board.c diff --git a/boards/arm/mimxrt595_evk/board.cmake b/boards/nxp/mimxrt595_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt595_evk/board.cmake rename to boards/nxp/mimxrt595_evk/board.cmake diff --git a/boards/arm/mimxrt595_evk/board.h b/boards/nxp/mimxrt595_evk/board.h similarity index 100% rename from boards/arm/mimxrt595_evk/board.h rename to boards/nxp/mimxrt595_evk/board.h diff --git a/boards/nxp/mimxrt595_evk/board.yml b/boards/nxp/mimxrt595_evk/board.yml new file mode 100644 index 00000000000000..5982f346712612 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt595_evk + vendor: nxp + socs: + - name: mimxrt595s diff --git a/boards/arm/mimxrt595_evk/dc_ram.ld b/boards/nxp/mimxrt595_evk/dc_ram.ld similarity index 100% rename from boards/arm/mimxrt595_evk/dc_ram.ld rename to boards/nxp/mimxrt595_evk/dc_ram.ld diff --git a/boards/nxp/mimxrt595_evk/doc/index.rst b/boards/nxp/mimxrt595_evk/doc/index.rst new file mode 100644 index 00000000000000..5be8e0da21c8dd --- /dev/null +++ b/boards/nxp/mimxrt595_evk/doc/index.rst @@ -0,0 +1,334 @@ +.. _mimxrt595_evk: + +NXP MIMXRT595-EVK +################## + +Overview +******** + +i.MX RT500 crossover MCUs are part of the edge computing family and are optimized +for low-power HMI applications by combining a graphics engine and a streamlined +Cadence Tensilica Fusion F1 DSP core with a next-generation Arm Cortex-M33 +core. These devices are designed to unlock the potential of display-based applications +with a secure, power-optimized embedded processor. + +i.MX RT500 MCUs provides up to 5MB of on-chip SRAM and several high-bandwidth interfaces +to access off-chip flash, including an Octal/Quad SPI interface with an on-the-fly +decryption engine. + +.. image:: mimxrt595_evk.jpg + :align: center + :alt: MIMXRT595-EVK + +Hardware +******** + +- MIMXRT595SFFOC Cortex-M33 (275 MHz) core processor with Cadence Tensilica Fusion F1 DSP +- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) +- USB2.0 high-speed host and device with micro USB connector and external crystal +- Octal/Quad/pSRAM external memories via FlexSPI +- 5 MB system SRAM +- Full size SD card slot (SDIO) +- On-board eMMC chip +- On-board 5 V inputs NXP PCA9420UK PMIC providing 1.2 V, 1.8 V, 3.3 V +- User LEDs +- Reset and User buttons +- MIPI-DSI connector +- Single row headers for ARDUINO signals and MikroBus connector +- FlexIO connector for MikroElektronica TFT Proto 5 inch capacitive touch display +- One motion sensor combo accelero-/magneto-meter NXP FXOS8700CQ +- Stereo audio codec with line-In/ line-Out/ and Microphone +- Pmod/host expansion connector +- NXP TFA9896 audio digital amplifier +- Support for up to eight off-board digital microphones via 12-pin header +- Two on-board digital microphones + +For more information about the MIMXRT595 SoC and MIMXRT595-EVK board, see +these references: + +- `i.MX RT595 Website`_ +- `i.MX RT595 Datasheet`_ +- `i.MX RT595 Reference Manual`_ +- `MIMXRT595-EVK Website`_ +- `MIMXRT595-EVK User Guide`_ +- `MIMXRT595-EVK Schematics`_ +- `MIMXRT595-EVK Debug Firmware`_ + +Supported Features +================== + +NXP considers the MIMXRT595-EVK as a superset board for the i.MX RT5xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT5xx family. NXP prioritizes enabling +this board with new support for Zephyr features. The mimxrt595_evk board +configuration supports the hardware features below. Another very similar +board is the :ref:`mimxrt685_evk`, and that board may have additional features +already supported, which can also be re-used on this mimxrt595_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| OS_TIMER | on-chip | os timer | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | OctalSPI Flash | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PM | on-chip | power management; uses SoC sleep, | +| | | deep sleep and deep-powerdown modes | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access (works with eMMC & SD) | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | LCDIF; MIPI-DSI. Tested with | +| | | :ref:`rk055hdmipi4m`, | +| | | :ref:`rk055hdmipi4ma0`, and | +| | | :ref:`g1120b0mipi` display shields | ++-----------+------------+-------------------------------------+ +| DMIC | on-chip | dmic | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT595 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_2 | USART0 | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_1 | USART0 | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_14 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ +| PIO0_25 | GPIO | SW0 | ++---------+-----------------+----------------------------+ +| PIO0_10 | GPIO | SW1 | ++---------+-----------------+----------------------------+ +| PIO4_30 | USART12 | USART TX | ++---------+-----------------+----------------------------+ +| PIO4_31 | USART12 | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_29 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO0_30 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO0_22 | GPIO | FXOS8700 TRIGGER | ++---------+-----------------+----------------------------+ +| PIO1_5 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO1_4 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO1_3 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO1_6 | SPI | SPI SSEL | ++---------+-----------------+----------------------------+ +| PIO0_5 | SCT0 | SCT0 GPI0 | ++---------+-----------------+----------------------------+ +| PIO0_6 | SCT0 | SCT0 GPI1 | ++---------+-----------------+----------------------------+ + +System Clock +============ + +The MIMXRT595 EVK is configured to use the OS Event timer +as a source for the system clock. + +Serial Port +=========== + +The MIMXRT595 SoC has 13 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Fusion F1 DSP Core +================== + +You can build a Zephyr application for the RT500 DSP core by targeting the F1 +SOC. Xtensa toolchain supporting RT500 DSP core is included in Zephyr SDK. +To build the hello_world sample for the RT500 DSP core: + +.. code-block:: shell + + $ west build -b mimxrt595_evk/mimxrt595s/f1 samples/hello_world + +For detailed instructions on how to debug DSP firmware, please refer to +this document: `Getting Started with Xplorer for EVK-MIMXRT595`_ + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2. + +.. tabs:: + + .. group-tab:: LPCLink2 JLink Onboard + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, + if not already done (these jumpers are installed by default). + 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the + J-Link firmware. Please make sure you have the latest firmware for this board. + + .. group-tab:: JLink External + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + + 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, + and J19 (these are installed by default). + + 3. Connect the J-Link probe to J2 10-pin header. + + See :ref:`jlink-external-debug-probe` for more information. + + .. group-tab:: Linkserver + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path. + 2. To update the debug firmware, please follow the instructions on `MIMXRT595-EVK Debug Firmware` + +Configuring a Console +===================== + +Connect a USB cable from your PC to J40, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt595_evk/mimxrt595s/cm33 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS v2.7 *** + Hello World! mimxrt595_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt595_evk/mimxrt595s/cm33 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS v2.7 *** + Hello World! mimxrt595_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the image in flash is interfering and causing this issue. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the flash with the following +steps: + +#. Set the SW7 DIP switches to ON-ON-ON to prevent booting from flash. + +#. Reset by pressing SW3 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application (example "Hello World"). + +#. Set the SW5 DIP switches to OFF-OFF-ON to boot from flash. + +#. Reset by pressing SW3 + +.. _MIMXRT595-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK + +.. _MIMXRT595-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=MIMXRT595EVKHUG + +.. _MIMXRT595-EVK Debug Firmware: + https://www.nxp.com/docs/en/application-note/AN13206.pdf + +.. _MIMXRT595-EVK Schematics: + https://www.nxp.com/downloads/en/schematics/MIMXRT595-EVK-DESIGN-FILES.zip + +.. _i.MX RT595 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt500-crossover-mcu-with-arm-cortex-m33-dsp-and-gpu-cores:i.MX-RT500 + +.. _i.MX RT595 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT500EC.pdf + +.. _i.MX RT595 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT500RM + +.. _Getting Started with Xplorer for EVK-MIMXRT595: + https://www.nxp.com/docs/en/supporting-information/GSXEVKMIMXRT595.pdf diff --git a/boards/arm/mimxrt595_evk/doc/mimxrt595_evk.jpg b/boards/nxp/mimxrt595_evk/doc/mimxrt595_evk.jpg similarity index 100% rename from boards/arm/mimxrt595_evk/doc/mimxrt595_evk.jpg rename to boards/nxp/mimxrt595_evk/doc/mimxrt595_evk.jpg diff --git a/boards/arm/mimxrt595_evk/mimxrt595_evk_cm33-pinctrl.dtsi b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt595_evk/mimxrt595_evk_cm33-pinctrl.dtsi rename to boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts new file mode 100644 index 00000000000000..eccf7d453653f3 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.dts @@ -0,0 +1,512 @@ +/* + * Copyright 2022-2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include + +#include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi" + + +/ { + model = "NXP MIMXRT595-EVK board"; + compatible = "nxp,mimxrt595"; + + aliases { + sw0 = &user_button_1; + sw1 = &user_button_2; + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + usart-0 = &flexcomm0; + watchdog0 = &wwdt0; + magn0 = &fxos8700; + accel0 = &fxos8700; + sdhc0 = &usdhc0; + pwm-0 = &sc_timer; + dmic-dev = &dmic0; + }; + + chosen { + zephyr,flash-controller = &mx25um51345g; + zephyr,flash = &mx25um51345g; + zephyr,code-partition = &slot0_partition; + zephyr,sram = &sram0; + zephyr,console = &flexcomm0; + zephyr,shell-uart = &flexcomm0; + zephyr,display = &lcdif; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "User SW1"; + gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_2: button_1 { + label = "User SW2"; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpio1 0 0>; + label = "User LED_GREEN"; + }; + blue_led: led_2 { + gpios = <&gpio3 17 0>; + label = "User LED_BLUE"; + }; + red_led: led_3 { + gpios = <&gpio0 14 0>; + label = "User LED_RED"; + }; + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 5 0>, /* A0 */ + <1 0 &gpio0 6 0>, /* A1 */ + <2 0 &gpio0 19 0>, /* A2 */ + <3 0 &gpio0 13 0>, /* A3 */ + <4 0 &gpio4 22 0>, /* A4 */ + <5 0 &gpio4 21 0>, /* A5 */ + <6 0 &gpio4 31 0>, /* D0 */ + <7 0 &gpio4 30 0>, /* D1 */ + <8 0 &gpio4 20 0>, /* D2 */ + <9 0 &gpio4 23 0>, /* D3 */ + <10 0 &gpio4 24 0>, /* D4 */ + <11 0 &gpio4 25 0>, /* D5 */ + <12 0 &gpio4 26 0>, /* D6 */ + <13 0 &gpio4 27 0>, /* D7 */ + <14 0 &gpio4 28 0>, /* D8 */ + <15 0 &gpio4 29 0>, /* D9 */ + <16 0 &gpio5 0 0>, /* D10 */ + <17 0 &gpio5 1 0>, /* D11 */ + <18 0 &gpio5 2 0>, /* D12 */ + <19 0 &gpio5 3 0>, /* D13 */ + <20 0 &gpio4 22 0>, /* D14 */ + <21 0 &gpio4 21 0>; /* D15 */ + }; + + /* + * This node describes the GPIO pins of the MIPI FPC interface, + * J44 on the EVK. This interface is standard to several + * NXP EVKs, and is used with several MIPI displays + * (available as zephyr shields) + */ + nxp_mipi_connector: mipi-connector { + compatible = "gpio-nexus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 12 0>, /* Pin 1, LEDK */ + <21 0 &gpio3 21 0>, /* Pin 21, RESET */ + <22 0 &gpio3 18 0>, /* Pin 22, LPTE */ + <26 0 &gpio0 30 0>, /* Pin 26, CTP_I2C SDA */ + <27 0 &gpio0 29 0>, /* Pin 27, CTP_I2C SCL */ + <28 0 &gpio4 4 0>, /* Pin 28, CTP_RST */ + <29 0 &gpio3 19 0>, /* Pin 29, CTP_INT */ + <32 0 &gpio3 15 0>, /* Pin 32, PWR_EN */ + <34 0 &gpio0 12 0>; /* Pin 34, BL_PWM */ + }; + + en_mipi_display: enable-mipi-display { + compatible = "regulator-fixed"; + regulator-name = "en_mipi_display"; + enable-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + }; +}; + +/* + * RT595 EVK board uses OS timer as the kernel timer + * In case we need to switch to SYSTICK timer, then + * replace &os_timer with &systick + */ +&os_timer { + status = "okay"; + wakeup-source; +}; + +&rtc { + status = "okay"; +}; + +&flexcomm0 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_usart>; + pinctrl-names = "default"; + dmas = <&dma0 0>, <&dma0 1>; + dma-names = "rx", "tx"; +}; + +arduino_i2c: &flexcomm4 { + compatible = "nxp,lpc-i2c"; + status = "okay"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_flexcomm4_i2c>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +nxp_mipi_i2c: &arduino_i2c {}; + +zephyr_mipi_dsi: &mipi_dsi {}; + +zephyr_lcdif: &lcdif {}; + + +hs_spi1: &hs_lspi1 { + compatible = "nxp,lpc-spi"; + pinctrl-0 = <&pinmux_flexcomm16_spi>; + pinctrl-names = "default"; + dmas = <&dma0 28>, <&dma0 29>; + dma-names = "rx", "tx"; + status = "okay"; +}; + +/* I2S RX */ +i2s0: &flexcomm1 { + compatible = "nxp,lpc-i2s"; + pinctrl-0 = <&pinmux_flexcomm1_i2s>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 2>; + dma-names = "rx"; + status = "disabled"; +}; + +/* I2S TX */ +i2s1: &flexcomm3 { + compatible = "nxp,lpc-i2s"; + pinctrl-0 = <&pinmux_flexcomm3_i2s>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 7>; + dma-names = "tx"; + status = "disabled"; +}; + +arduino_serial: &flexcomm12 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm12_usart>; + pinctrl-names = "default"; + dmas = <&dma0 34>, <&dma0 35>; + dma-names = "rx", "tx"; +}; + +/* PCA9420 PMIC */ +&pmic_i2c { + status = "okay"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_pmic_i2c>; + pinctrl-names = "default"; + + pca9420: pca9420@61 { + compatible = "nxp,pca9420"; + reg = <0x61>; + nxp,enable-modesel-pins; + + pca9420_sw1: BUCK1 { + regulator-boot-on; + nxp,mode0-microvolt = <1100000>; + nxp,mode1-microvolt = <600000>; + nxp,mode2-microvolt = <900000>; + nxp,mode3-microvolt = <800000>; + }; + + pca9420_sw2: BUCK2 { + regulator-boot-on; + nxp,mode0-microvolt = <1800000>; + nxp,mode1-microvolt = <1800000>; + nxp,mode2-microvolt = <1800000>; + nxp,mode3-microvolt = <1800000>; + }; + + pca9420_ldo1: LDO1 { + regulator-boot-on; + nxp,mode0-microvolt = <1800000>; + nxp,mode1-microvolt = <1800000>; + nxp,mode2-microvolt = <1800000>; + nxp,mode3-microvolt = <1800000>; + }; + + pca9420_ldo2: LDO2 { + regulator-boot-on; + nxp,mode0-microvolt = <3300000>; + nxp,mode1-microvolt = <3300000>; + nxp,mode2-microvolt = <3300000>; + nxp,mode3-microvolt = <3300000>; + }; + }; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +/* + * GPIO module interrupts are shared between all GPIO devices on this + * SOC, but Zephyr does not currently support sharing interrupts between + * devices. The user can select GPIO modules to support interrupts by + * setting the appropriate `int-source` and `interrupt` property for + * a given module. On this board, GPIO3 and GPIO4 are configured to support + * interrupts. + */ +&gpio3 { + status = "okay"; + int-source = "int-a"; + interrupts = <2 0>; +}; + +&gpio4 { + status = "okay"; + int-source = "int-b"; + interrupts = <3 0>; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&user_button_1 { + status = "okay"; +}; + +&user_button_2 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&blue_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; + +&usdhc0 { + status = "okay"; + pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + mmc { + compatible = "zephyr,mmc-disk"; + status = "okay"; + }; + pinctrl-0 = <&pinmux_usdhc>; + pinctrl-names = "default"; + mmc-hs200-1_8v; + mmc-hs400-1_8v; +}; + +&wwdt0 { + status = "okay"; +}; + +&flexspi { + status = "okay"; + pinctrl-0 = <&pinmux_flexspi>; + pinctrl-1 = <&pinmux_flexspi_sleep>; + pinctrl-names = "default", "sleep"; + + mx25um51345g: mx25um51345g@0 { + compatible = "nxp,imx-flexspi-mx25um51345g"; + /* MX25UM51245G is 64MB, 512MBit flash part */ + size = ; + reg = <0>; + spi-max-frequency = <200000000>; + status = "okay"; + jedec-id = [c2 81 3a]; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_K(3076)>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 DT_SIZE_K(3072)>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_M(57)>; + }; + }; + }; +}; + +&flexspi2 { + status = "okay"; + pinctrl-0 = <&pinmux_flexspi2>; + pinctrl-names = "default"; + rx-clock-source = <3>; + ahb-prefetch; + ahb-bufferable; + ahb-cacheable; + ahb-read-addr-opt; + aps6408l: aps6408l@0 { + compatible = "nxp,imx-flexspi-aps6408l"; + /* APS6408L is 8MB, 64MBit pSRAM */ + size = ; + reg = <0>; + spi-max-frequency = <198000000>; + status = "okay"; + cs-interval-unit = <1>; + cs-interval = <5>; + cs-hold-time = <3>; + cs-setup-time = <3>; + data-valid-time = <1>; + column-space = <0>; + ahb-write-wait-unit = <2>; + ahb-write-wait-interval = <0>; + }; +}; + +&sc_timer { + pinctrl-0 = <&pinmux_sctimer_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i3c0 { + pinctrl-0 = <&pinmux_i3c>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&mbox { + status = "okay"; +}; + +/* Disable this node if not using USB and need another MPU region */ +&sram1 { + status = "okay"; +}; + +/* Enable smartDMA controller */ +&smartdma { + status = "okay"; +}; + +/* Add smartDMA to mipi DSI */ +&mipi_dsi { + dmas = <&smartdma>; + dma-names = "smartdma"; +}; + +&dmic0 { + status = "okay"; + pinctrl-0 = <&pinmux_dmic0>; + pinctrl-names = "default"; + use2fs; +}; + +/* Configure pdm channels 0 and 1 with gain, and cutoff settings + * appropriate for the attached MEMS microphones. + */ +&pdmc0 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&pdmc1 { + status = "okay"; + gainshift = <3>; + dc-cutoff = "155hz"; + dc-gain = <1>; +}; + +&mrt_channel0 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml new file mode 100644 index 00000000000000..532fa9519ea7d4 --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml @@ -0,0 +1,32 @@ +# +# Copyright (c) 2022, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt595_evk/mimxrt595s/cm33 +name: NXP MIMXRT595-EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 4608 +flash: 65536 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - counter + - dma + - gpio + - i2c + - spi + - usb_device + - watchdog + - sdhc + - pwm + - i2s + - dmic +vendor: nxp diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig new file mode 100644 index 00000000000000..a25ec7156e7a7d --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig @@ -0,0 +1,16 @@ +# +# Copyright 2022,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_PINCTRL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.dts b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.dts similarity index 100% rename from boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.dts rename to boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.dts diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml new file mode 100644 index 00000000000000..48245feebc68bd --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1.yaml @@ -0,0 +1,10 @@ +identifier: mimxrt595_evk/mimxrt595s/f1 +name: i.MXRT595 Fusion F1 DSP +type: mcu +arch: xtensa +toolchain: + - zephyr +testing: + only_tags: + - kernel +vendor: nxp diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig new file mode 100644 index 00000000000000..0cb1f999e9201a --- /dev/null +++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_f1_defconfig @@ -0,0 +1,4 @@ +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y +CONFIG_NXP_IMXRT_BOOT_HEADER=n diff --git a/boards/arm/mimxrt595_evk/pre_dt_board.cmake b/boards/nxp/mimxrt595_evk/pre_dt_board.cmake similarity index 100% rename from boards/arm/mimxrt595_evk/pre_dt_board.cmake rename to boards/nxp/mimxrt595_evk/pre_dt_board.cmake diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt new file mode 100644 index 00000000000000..39c978f14cc695 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt @@ -0,0 +1,25 @@ +# +# Copyright 2020-2022 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(init.c) + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + if(NOT DEFINED CONFIG_BOARD_MIMXRT685_EVK) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT685-EVK, but targeting a custom board. You may need to " + "update your flash configuration block data") + endif() + # Include flash configuration block for R685 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN13386 for more information. + zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT685_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt685") + zephyr_library_sources(${RT685_BOARD_DIR}/flash_config/flash_config.c) + zephyr_library_include_directories(${RT685_BOARD_DIR}/flash_config) +endif() diff --git a/boards/arm/mimxrt685_evk/Kconfig b/boards/nxp/mimxrt685_evk/Kconfig similarity index 100% rename from boards/arm/mimxrt685_evk/Kconfig rename to boards/nxp/mimxrt685_evk/Kconfig diff --git a/boards/nxp/mimxrt685_evk/Kconfig.defconfig b/boards/nxp/mimxrt685_evk/Kconfig.defconfig new file mode 100644 index 00000000000000..8fbc681e0528b2 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/Kconfig.defconfig @@ -0,0 +1,29 @@ +# MIMXRT685-EVK board + +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT685_EVK + +config NXP_IMXRT_BOOT_HEADER + default y if !BOOTLOADER_MCUBOOT + +config XTAL_SYS_CLK_HZ + default 24000000 + +config SYSOSC_SETTLING_US + default 260 + +choice FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_MODE + default FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_STR +endchoice + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM +endchoice + +config FXOS8700_DRDY_INT1 + default y + depends on FXOS8700_TRIGGER + +endif # BOARD_MIMXRT685_EVK diff --git a/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk new file mode 100644 index 00000000000000..d87399aebd7f83 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/Kconfig.mimxrt685_evk @@ -0,0 +1,5 @@ +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT685_EVK + select SOC_PART_NUMBER_MIMXRT685SFVKB diff --git a/boards/arm/mimxrt685_evk/board.cmake b/boards/nxp/mimxrt685_evk/board.cmake similarity index 100% rename from boards/arm/mimxrt685_evk/board.cmake rename to boards/nxp/mimxrt685_evk/board.cmake diff --git a/boards/nxp/mimxrt685_evk/board.yml b/boards/nxp/mimxrt685_evk/board.yml new file mode 100644 index 00000000000000..41956acbb3146d --- /dev/null +++ b/boards/nxp/mimxrt685_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt685_evk + vendor: nxp + socs: + - name: mimxrt685s diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst new file mode 100644 index 00000000000000..3b0357ffb02180 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/doc/index.rst @@ -0,0 +1,370 @@ +.. _mimxrt685_evk: + +NXP MIMXRT685-EVK +################## + +Overview +******** + +The i.MX RT600 is a crossover MCU family optimized for 32-bit immersive audio +playback and voice user interface applications combining a high-performance +Cadence Tensilica HiFi 4 audio DSP core with a next-generation Cortex-M33 +core. The i.MX RT600 family of crossover MCUs is designed to unlock the +potential of voice-assisted end nodes with a secure, power-optimized embedded +processor. + +The i.MX RT600 family provides up to 4.5MB of on-chip SRAM and several +high-bandwidth interfaces to access off-chip flash, including an Octal/Quad SPI +interface with an on-the-fly decryption engine. + +.. image:: mimxrt685_evk.jpg + :align: center + :alt: MIMXRT685-EVK + +Hardware +******** + +- MIMXRT685SFVKB Cortex-M33 (300 MHz, 128 KB TCM) core processor with Cadence Xtensa HiFi4 DSP +- Onboard, high-speed USB, Link2 debug probe with CMSIS-DAP protocol (supporting Cortex M33 debug only) +- High speed USB port with micro A/B connector for the host or device functionality +- UART, I2C and SPI port bridging from i.MX RT685 target to USB via the on-board debug probe +- 512 MB Macronix Octal SPI Flash operating at 1.8 V +- 4.5 MB Apmemory PSRAM +- Full size SD card slot (SDIO) +- NXP PCA9420UK PMIC +- User LEDs +- Reset and User buttons +- Arduino and PMod/Host expansion connectors +- NXP FXOS8700CQ accelerometer +- Stereo audio codec with line in/out and electret microphone +- Stereo NXP TFA9894 digital amplifiers, with option for external +5V power for higher performance speakers +- Support for up to eight off-board digital microphones via 12-pin header +- Two on-board DMICS + +For more information about the MIMXRT685 SoC and MIMXRT685-EVK board, see +these references: + +- `i.MX RT685 Website`_ +- `i.MX RT685 Datasheet`_ +- `i.MX RT685 Reference Manual`_ +- `MIMXRT685-EVK Website`_ +- `MIMXRT685-EVK User Guide`_ +- `MIMXRT685-EVK Schematics`_ + +Supported Features +================== + +NXP considers the MIMXRT685-EVK as a superset board for the i.MX RT6xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT6xx family. NXP prioritizes enabling +this board with new support for Zephyr features. The mimxrt685_evk board +configuration supports the hardware features below. Another very similar +board is the :ref:`mimxrt595_evk`, and that board may have additional features +already supported, which can also be re-used on this mimxrt685_evk board: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| OS_TIMER | on-chip | os timer | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | OctalSPI Flash | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| HWINFO | on-chip | Unique device serial number | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| SDHC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CTIMER | on-chip | counter | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| FLEXSPI | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/mimxrt685_evk/mimxrt685_evk_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT685 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_2 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO0_1 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_14 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ +| PIO1_1 | GPIO | SW0 | ++---------+-----------------+----------------------------+ +| PIO0_17 | I2C | I2C SDA | ++---------+-----------------+----------------------------+ +| PIO0_18 | I2C | I2C SCL | ++---------+-----------------+----------------------------+ +| PIO1_5 | GPIO | FXOS8700 TRIGGER | ++---------+-----------------+----------------------------+ +| PIO1_5 | SPI | SPI MOSI | ++---------+-----------------+----------------------------+ +| PIO1_4 | SPI | SPI MISO | ++---------+-----------------+----------------------------+ +| PIO1_3 | SPI | SPI SCK | ++---------+-----------------+----------------------------+ +| PIO1_6 | SPI | SPI SSEL | ++---------+-----------------+----------------------------+ +| PIO0_23 | I2S | I2S DATAOUT | ++---------+-----------------+----------------------------+ +| PIO0_22 | I2S | I2S TX WS | ++---------+-----------------+----------------------------+ +| PIO0_21 | I2S | I2S TX SCK | ++---------+-----------------+----------------------------+ +| PIO0_9 | I2S | I2S DATAIN | ++---------+-----------------+----------------------------+ +| PIO0_29 | USART | USART TX | ++---------+-----------------+----------------------------+ +| PIO0_30 | USART | USART RX | ++---------+-----------------+----------------------------+ +| PIO1_11 | FLEXSPI0B_DATA0 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_12 | FLEXSPI0B_DATA1 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_13 | FLEXSPI0B_DATA2 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_14 | FLEXSPI0B_DATA3 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO1_29 | FLEXSPI0B_SCLK | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_12 | PIO2_12 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_17 | FLEXSPI0B_DATA4 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_18 | FLEXSPI0B_DATA5 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_19 | FLEXSPI0B_SS0_N | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_22 | FLEXSPI0B_DATA6 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO2_23 | FLEXSPI0B_DATA7 | OctalSPI Flash | ++---------+-----------------+----------------------------+ +| PIO0_27 | SCT0_OUT7 | PWM | ++---------+-----------------+----------------------------+ +| PIO1_30 | SD0_CLK | SD card | ++---------+-----------------+----------------------------+ +| PIO1_31 | SD0_CMD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_0 | SD0_D0 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_1 | SD0_D1 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_2 | SD0_D2 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_3 | SD0_D3 | SD card | ++---------+-----------------+----------------------------+ +| PIO2_4 | SD0_WR_PRT | SD card | ++---------+-----------------+----------------------------+ +| PIO2_9 | SD0_CD | SD card | ++---------+-----------------+----------------------------+ +| PIO2_10 | SD0_RST | SD card | ++---------+-----------------+----------------------------+ + +System Clock +============ + +The MIMXRT685 EVK is configured to use the OS Event timer +as a source for the system clock. + +Serial Port +=========== + +The MIMXRT685 SoC has 8 FLEXCOMM interfaces for serial communication. One is +configured as USART for the console and the remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the LPC-Link2. + +.. tabs:: + + .. group-tab:: LinkServer CMSIS-DAP + + 1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your + search path. LinkServer works with the default CMSIS-DAP firmware included in + the on-board debugger. + 2. Make sure the jumpers JP17, JP18 and JP19 are installed. + + linkserver is the default runner for this board + + .. code-block:: console + + west flash + west debug + + .. group-tab:: LPCLink2 JLink Onboard + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + 2. To connect the SWD signals to onboard debug circuit, install jumpers JP17, JP18 and JP19, + if not already done (these jumpers are installed by default). + 3. Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program the + J-Link firmware. Please make sure you have the latest firmware for this board. + + .. code-block:: console + + west flash -r jlink + west debug -r jlink + + .. group-tab:: JLink External + + + 1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path. + + 2. To disconnect the SWD signals from onboard debug circuit, **remove** jumpers J17, J18, + and J19 (these are installed by default). + + 3. Connect the J-Link probe to J2 10-pin header. + + See :ref:`jlink-external-debug-probe` for more information. + + .. code-block:: console + + west flash -r jlink + west debug -r jlink + +Configuring a Console +===================== + +Connect a USB cable from your PC to J16, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`linkserver-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt685_evk + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0 ***** + Hello World! mimxrt685_evk + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. This example uses the +:ref:`linkserver-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt685_evk + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS zephyr-v2.3.0 ***** + Hello World! mimxrt685_evk + +Troubleshooting +=============== + +If the debug probe fails to connect with the following error, it's possible +that the image in flash is interfering and causing this issue. + +.. code-block:: console + + Remote debugging using :2331 + Remote communication error. Target disconnected.: Connection reset by peer. + "monitor" command not supported by this target. + "monitor" command not supported by this target. + You can't do that when your target is `exec' + (gdb) Could not connect to target. + Please check power, connection and settings. + +You can fix it by erasing and reprogramming the flash with the following +steps: + +#. Set the SW5 DIP switches to ON-ON-ON to prevent booting from flash. + +#. Reset by pressing SW3 + +#. Run ``west debug`` or ``west flash`` again with a known working Zephyr + application (example "Hello World"). + +#. Set the SW5 DIP switches to ON-OFF-ON to boot from flash. + +#. Reset by pressing SW3 + +.. _MIMXRT685-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK + +.. _MIMXRT685-EVK User Guide: + https://www.nxp.com/webapp/Download?colCode=UM11159 + +.. _MIMXRT685-EVK Schematics: + https://www.nxp.com/downloads/en/design-support/RT685-DESIGNFILES.zip + +.. _i.MX RT685 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt600-crossover-mcu-with-arm-cortex-m33-and-dsp-cores:i.MX-RT600 + +.. _i.MX RT685 Datasheet: + https://www.nxp.com/docs/en/data-sheet/DS-RT600.pdf + +.. _i.MX RT685 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=UM11147 diff --git a/boards/arm/mimxrt685_evk/doc/mimxrt685_evk.jpg b/boards/nxp/mimxrt685_evk/doc/mimxrt685_evk.jpg similarity index 100% rename from boards/arm/mimxrt685_evk/doc/mimxrt685_evk.jpg rename to boards/nxp/mimxrt685_evk/doc/mimxrt685_evk.jpg diff --git a/boards/arm/mimxrt685_evk/init.c b/boards/nxp/mimxrt685_evk/init.c similarity index 100% rename from boards/arm/mimxrt685_evk/init.c rename to boards/nxp/mimxrt685_evk/init.c diff --git a/boards/arm/mimxrt685_evk/mimxrt685_evk_cm33-pinctrl.dtsi b/boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi similarity index 100% rename from boards/arm/mimxrt685_evk/mimxrt685_evk_cm33-pinctrl.dtsi rename to boards/nxp/mimxrt685_evk/mimxrt685_evk-pinctrl.dtsi diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk.dts new file mode 100644 index 00000000000000..a7df8a693efdd7 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk.dts @@ -0,0 +1,387 @@ +/* + * Copyright (c) 2020-2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include + +#include "mimxrt685_evk-pinctrl.dtsi" + +/ { + model = "NXP MIMXRT685-EVK board"; + compatible = "nxp,mimxrt685"; + + aliases { + sw0 = &user_button_1; + sw1 = &user_button_2; + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + usart-0 = &flexcomm0; + /* For pwm test suites */ + pwm-0 = &sc_timer; + pwm-led0 = &green_pwm_led; + green-pwm-led = &green_pwm_led; + blue-pwm-led = &blue_pwm_led; + red-pwm-led = &red_pwm_led; + watchdog0 = &wwdt0; + magn0 = &fxos8700; + accel0 = &fxos8700; + sdhc0 = &usdhc0; + }; + + chosen { + zephyr,flash-controller = &mx25um51345g; + zephyr,flash = &mx25um51345g; + zephyr,code-partition = &slot0_partition; + zephyr,sram = &sram0; + zephyr,console = &flexcomm0; + zephyr,shell-uart = &flexcomm0; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "User SW1"; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_2: button_1 { + label = "User SW2"; + gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + leds: leds { + compatible = "gpio-leds"; + green_led: led_1 { + gpios = <&gpio0 14 0>; + label = "User LED_GREEN"; + }; + blue_led: led_2 { + gpios = <&gpio0 26 0>; + label = "User LED_BLUE"; + }; + red_led: led_3 { + gpios = <&gpio0 31 0>; + label = "User LED_RED"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + green_pwm_led: green_pwm_led { + pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "Green PWM LED"; + status = "okay"; + }; + blue_pwm_led: blue_pwm_led { + pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "Blue PWM LED"; + status = "okay"; + }; + red_pwm_led: red_pwm_led { + pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "Red PWM LED"; + status = "disabled"; + }; + }; + + arduino_header: arduino-connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 5 0>, /* A0 */ + <1 0 &gpio0 6 0>, /* A1 */ + <2 0 &gpio0 19 0>, /* A2 */ + <3 0 &gpio0 20 0>, /* A3 */ + <4 0 &gpio0 17 0>, /* A4 */ + <5 0 &gpio0 18 0>, /* A5 */ + <6 0 &gpio0 30 0>, /* D0 */ + <7 0 &gpio0 29 0>, /* D1 */ + <8 0 &gpio0 28 0>, /* D2 */ + <9 0 &gpio0 27 0>, /* D3 */ + <10 0 &gpio1 0 0>, /* D4 */ + <11 0 &gpio1 10 0>, /* D5 */ + <12 0 &gpio1 2 0>, /* D6 */ + <13 0 &gpio1 8 0>, /* D7 */ + <14 0 &gpio1 9 0>, /* D8 */ + <15 0 &gpio1 7 0>, /* D9 */ + <16 0 &gpio1 6 0>, /* D10 */ + <17 0 &gpio1 5 0>, /* D11 */ + <18 0 &gpio1 4 0>, /* D12 */ + <19 0 &gpio1 3 0>, /* D13 */ + <20 0 &gpio0 17 0>, /* D14 */ + <21 0 &gpio0 18 0>; /* D15 */ + }; +}; + +/* + * RT600 EVK board uses OS timer as the kernel timer + * In case we need to switch to SYSTICK timer, then + * replace &os_timer with &systick + */ +&os_timer { + status = "okay"; + wakeup-source; +}; + +&rtc { + status = "okay"; +}; + +&flexcomm0 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_usart>; + pinctrl-names = "default"; + dmas = <&dma0 0>, <&dma0 1>; + dma-names = "rx", "tx"; +}; + +arduino_i2c: &flexcomm2 { + compatible = "nxp,lpc-i2c"; + status = "okay"; + pinctrl-0 = <&pinmux_flexcomm2_i2c>; + pinctrl-names = "default"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + int1-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + }; +}; + +arduino_serial: &flexcomm4 { + compatible = "nxp,lpc-usart"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm4_usart>; + pinctrl-names = "default"; + dmas = <&dma0 8>, <&dma0 9>; + dma-names = "rx", "tx"; +}; + +arduino_spi: &flexcomm5 { + compatible = "nxp,lpc-spi"; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 10>, <&dma0 11>; + dma-names = "rx", "tx"; + pinctrl-0 = <&pinmux_flexcomm5_spi>; + pinctrl-names = "default"; +}; + +/* I2S receive channel */ +i2s0: &flexcomm1 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 2>; + dma-names = "rx"; + pinctrl-0 = <&pinmux_flexcomm1_i2s>; + pinctrl-names = "default"; +}; + +/* I2S transmit channel */ +i2s1: &flexcomm3 { + status = "okay"; + compatible = "nxp,lpc-i2s"; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dma0 7>; + dma-names = "tx"; + pinctrl-0 = <&pinmux_flexcomm3_i2s>; + pinctrl-names = "default"; +}; + +/* PCA9420 PMIC */ +&pmic_i2c { + status = "okay"; + compatible = "nxp,lpc-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&pinmux_pmic_i2c>; + pinctrl-names = "default"; + + pca9420: pca9420@61 { + compatible = "nxp,pca9420"; + reg = <0x61>; + nxp,enable-modesel-pins; + + buck1: BUCK1 { + regulator-boot-on; + }; + + buck2: BUCK2 { + regulator-boot-on; + }; + + ldo1: LDO1 { + regulator-boot-on; + }; + + ldo2: LDO2 { + regulator-boot-on; + }; + + + }; +}; + +&flexspi { + pinctrl-0 = <&pinmux_flexspi>; + pinctrl-names = "default"; + status = "okay"; + mx25um51345g: mx25um51345g@2 { + compatible = "nxp,imx-flexspi-mx25um51345g"; + /* MX25UM51245G is 64MB, 512MBit flash part */ + size = ; + reg = <2>; + spi-max-frequency = <200000000>; + status = "okay"; + jedec-id = [c2 81 3a]; + erase-block-size = <4096>; + write-block-size = <16>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 DT_SIZE_K(128)>; + }; + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 DT_SIZE_K(3076)>; + }; + slot1_partition: partition@321000 { + label = "image-1"; + reg = <0x00321000 DT_SIZE_K(3072)>; + }; + storage_partition: partition@621000 { + label = "storage"; + reg = <0x00621000 DT_SIZE_M(57)>; + }; + }; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&dma0 { + status = "okay"; +}; + +&wwdt0 { + status = "okay"; +}; + +&user_button_1 { + status = "okay"; +}; + +&user_button_2 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&blue_led { + status = "okay"; +}; + +&red_led { + status = "okay"; +}; + +&sc_timer { + status = "okay"; + pinctrl-0 = <&pinmux_sctimer>; + pinctrl-names = "default"; +}; + +&usdhc0 { + status = "okay"; + /* Quick fix for 1.8V SD cards on RT600- disable 1.8V negotiation */ + no-1-8-v; + pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + sdmmc { + compatible = "zephyr,sdmmc-disk"; + status = "okay"; + }; + pinctrl-0 = <&pinmux_usdhc>; + pinctrl-names = "default"; +}; + +&lpadc0 { + status = "okay"; + pinctrl-0 = <&pinmux_lpadc0>; + pinctrl-names = "default"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&ctimer0 { + status = "okay"; +}; + +&ctimer1 { + status = "okay"; +}; + +&ctimer2 { + status = "okay"; +}; + +&ctimer3 { + status = "okay"; +}; + +&ctimer4 { + status = "okay"; +}; + +&i3c0 { + pinctrl-0 = <&pinmux_i3c>; + pinctrl-names = "default"; + + status = "okay"; +}; + +/* Disable this node if not using USB and need another MPU region */ +&sram1 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml new file mode 100644 index 00000000000000..53f260fc60e224 --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk.yaml @@ -0,0 +1,34 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt685_evk +name: NXP MIMXRT685-EVK +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 4608 +flash: 65536 +supported: + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - counter + - dma + - pwm + - gpio + - hwinfo + - i2c + - i3c + - i2s + - sdhc + - spi + - watchdog + - usb_device +vendor: nxp diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig b/boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig new file mode 100644 index 00000000000000..47128760e08edc --- /dev/null +++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_defconfig @@ -0,0 +1,17 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_PINCTRL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mimxrt685_evk/pre_dt_board.cmake b/boards/nxp/mimxrt685_evk/pre_dt_board.cmake similarity index 100% rename from boards/arm/mimxrt685_evk/pre_dt_board.cmake rename to boards/nxp/mimxrt685_evk/pre_dt_board.cmake diff --git a/boards/nxp/mr_canhubk3/Kconfig.defconfig b/boards/nxp/mr_canhubk3/Kconfig.defconfig new file mode 100644 index 00000000000000..02710328d68420 --- /dev/null +++ b/boards/nxp/mr_canhubk3/Kconfig.defconfig @@ -0,0 +1,43 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MR_CANHUBK3 + +if SERIAL + +config UART_CONSOLE + default y + +endif # SERIAL + +if SPI + +config SPI_INIT_PRIORITY + default 50 + +if WDT_NXP_FS26 + +config WDT_NXP_FS26_INIT_PRIORITY + default 51 + +endif # WDT_NXP_FS26 +endif # SPI + +if CAN + +config GPIO + default y + +endif # CAN + +if NETWORKING + +config NET_L2_ETHERNET + default y if !NET_LOOPBACK && !NET_TEST + +config MDIO + default y if NET_L2_ETHERNET + +endif # NETWORKING + +endif # BOARD_MR_CANHUBK3 diff --git a/boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 b/boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 new file mode 100644 index 00000000000000..447411b0b35b6b --- /dev/null +++ b/boards/nxp/mr_canhubk3/Kconfig.mr_canhubk3 @@ -0,0 +1,6 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MR_CANHUBK3 + select SOC_S32K344 + select SOC_PART_NUMBER_PS32K344EHVPBS diff --git a/boards/arm/mr_canhubk3/board.cmake b/boards/nxp/mr_canhubk3/board.cmake similarity index 100% rename from boards/arm/mr_canhubk3/board.cmake rename to boards/nxp/mr_canhubk3/board.cmake diff --git a/boards/nxp/mr_canhubk3/board.yml b/boards/nxp/mr_canhubk3/board.yml new file mode 100644 index 00000000000000..3840a8f3d30384 --- /dev/null +++ b/boards/nxp/mr_canhubk3/board.yml @@ -0,0 +1,5 @@ +board: + name: mr_canhubk3 + vendor: nxp + socs: + - name: s32k344 diff --git a/boards/arm/mr_canhubk3/doc/img/mr_canhubk3_top.jpg b/boards/nxp/mr_canhubk3/doc/img/mr_canhubk3_top.jpg similarity index 100% rename from boards/arm/mr_canhubk3/doc/img/mr_canhubk3_top.jpg rename to boards/nxp/mr_canhubk3/doc/img/mr_canhubk3_top.jpg diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst new file mode 100644 index 00000000000000..2fe3780236a064 --- /dev/null +++ b/boards/nxp/mr_canhubk3/doc/index.rst @@ -0,0 +1,339 @@ +.. _mr_canhubk3: + +NXP MR-CANHUBK3 +############### + +Overview +******** + +`NXP MR-CANHUBK3`_ is an evaluation board for mobile robotics applications such +as autonomous mobile robots (AMR) and automated guided vehicles (AGV). It +features an `NXP S32K344`_ general-purpose automotive microcontroller based on +an Arm Cortex-M7 core (Lock-Step). + +.. image:: img/mr_canhubk3_top.jpg + :align: center + :alt: NXP MR-CANHUBK3 (TOP) + +Hardware +******** + +- NXP S32K344 + - Arm Cortex-M7 (Lock-Step), 160 MHz (Max.) + - 4 MB of program flash, with ECC + - 320 KB RAM, with ECC + - Ethernet 100 Mbps, CAN FD, FlexIO, QSPI + - 12-bit 1 Msps ADC, 16-bit eMIOS timer + +- `NXP FS26 Safety System Basis Chip`_ + +- Interfaces: + - Console UART + - 6x CAN FD + - 100Base-T1 Ethernet + - JST-GH connectors and I/O headers for I2C, SPI, GPIO, + PWM, etc. + +More information about the hardware and design resources can be found at +`NXP MR-CANHUBK3`_ website. + +Supported Features +================== + +The ``mr_canhubk3`` board configuration supports the following hardware features: + +============ ========== ================================ +Interface Controller Driver/Component +============ ========== ================================ +SIUL2 on-chip | pinctrl + | gpio + | external interrupt controller +WKPU on-chip interrupt controller +LPUART on-chip serial +QSPI on-chip flash +FLEXCAN on-chip can +LPI2C on-chip i2c +ADC SAR on-chip adc +LPSPI on-chip spi +WDT FS26 SBC watchdog +EMAC on-chip ethernet + mdio +eMIOS on-chip pwm +EDMA on-chip dma +============ ========== ================================ + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/nxp/mr_canhubk3/mr_canhubk3_defconfig`. + +Connections and IOs +=================== + +Each GPIO port is divided into two banks: low bank, from pin 0 to 15, and high +bank, from pin 16 to 31. For example, ``PTA2`` is the pin 2 of ``gpioa_l`` (low +bank), and ``PTA20`` is the pin 4 of ``gpioa_h`` (high bank). + +The GPIO controller provides the option to route external input pad interrupts +to either the SIUL2 EIRQ or WKPU interrupt controllers, as supported by the SoC. +By default, GPIO interrupts are routed to SIUL2 EIRQ interrupt controller, +unless they are explicity configured to be directed to the WKPU interrupt +controller, as outlined in :zephyr_file:`dts/bindings/gpio/nxp,s32-gpio.yaml`. + +To find information about which GPIOs are compatible with each interrupt +controller, refer to the device reference manual. + +.. note:: + + It is important to highlight that the current board configuration lacks + support for wake-up events and power-management features. WKPU functionality + is restricted solely to serving as an interrupt controller. + +LEDs +---- + +The MR-CANHUBK3 board has one user RGB LED: + +======================= ===== ===== =================================== +Devicetree node Color Pin Pin Functions +======================= ===== ===== =================================== +led0 / user_led1_red Red PTE14 FXIO D7 / EMIOS0 CH19 +led1 / user_led1_green Green PTA27 FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10 +led2 / user_led1_blue Blue PTE12 FXIO D8 / EMIOS1 CH5 +======================= ===== ===== =================================== + +The user can control the LEDs in any way. An output of ``0`` illuminates the LED. + +Buttons +------- + +The MR-CANHUBK3 board has two user buttons: + +======================= ===== ===== ============== +Devicetree node Label Pin Pin Functions +======================= ===== ===== ============== +sw0 / user_button_1 SW1 PTD15 EIRQ31 +sw0 / user_button_2 SW2 PTA25 EIRQ5 / WKPU34 +======================= ===== ===== ============== + +System Clock +============ + +The Arm Cortex-M7 (Lock-Step) are configured to run at 160 MHz. + +Serial Console +============== + +By default, the serial console is provided through ``lpuart2`` on the 7-pin +DCD-LZ debug connector ``P6``. + +========= ===== ============ +Connector Pin Pin Function +========= ===== ============ +P6.2 PTA9 LPUART2_TX +P6.3 PTA8 LPUART2_RX +========= ===== ============ + +CAN +=== + +CAN is provided through FLEXCAN interface with 6 instances. + +=============== ======= =============== ============= +Devicetree node Pin Pin Function Bus Connector +=============== ======= =============== ============= +flexcan0 | PTA6 | PTA6_CAN0_RX P12/P13 + | PTA7 | PTA7_CAN0_TX +flexcan1 | PTC9 | PTC9_CAN0_RX P14/P15 + | PTC8 | PTC8_CAN0_TX +flexcan2 | PTE25 | PTE25_CAN0_RX P16/P17 + | PTE24 | PTE24_CAN0_TX +flexcan3 | PTC29 | PTC29_CAN0_RX P18/019 + | PTC28 | PTC28_CAN0_TX +flexcan4 | PTC31 | PTC31_CAN0_RX P20/P21 + | PTC30 | PTC30_CAN0_TX +flexcan5 | PTC11 | PTC11_CAN0_RX P22/P23 + | PTC10 | PTC10_CAN0_TX +=============== ======= =============== ============= + +.. note:: + There is limitation by HAL SDK, so CAN only has support maximum 64 message buffers (MBs) + and support maximum 32 message buffers for concurrent active instances with 8 bytes + payload. We need to pay attention to configuration options: + + 1. :kconfig:option:`CONFIG_CAN_MAX_MB` must be less or equal than the + maximum number of message buffers that is according to the table below. + + 2. :kconfig:option:`CONFIG_CAN_MAX_FILTER` must be less or equal than + :kconfig:option:`CONFIG_CAN_MAX_MB`. + +=============== ========== ================ ================ +Devicetree node Payload Hardware support Software support +=============== ========== ================ ================ +flexcan0 | 8 bytes | 96 MBs | 64 MBs + | 16 bytes | 63 MBs | 42 MBs + | 32 bytes | 36 MBs | 24 MBs + | 64 bytes | 21 MBs | 14 MBs +flexcan1 | 8 bytes | 64 MBs | 64 MBs + | 16 bytes | 42 MBs | 42 MBs + | 32 bytes | 24 MBs | 24 MBs + | 64 bytes | 14 MBs | 14 MBs +flexcan2 | 8 bytes | 64 MBs | 64 MBs + | 16 bytes | 42 MBs | 42 MBs + | 32 bytes | 24 MBs | 24 MBs + | 64 bytes | 14 MBs | 14 MBs +flexcan3 | 8 bytes | 32 MBs | 32 MBs + | 16 bytes | 21 MBs | 21 MBs + | 32 bytes | 12 MBs | 12 MBs + | 64 bytes | 7 MBs | 7 MBs +flexcan4 | 8 bytes | 32 MBs | 32 MBs + | 16 bytes | 21 MBs | 21 MBs + | 32 bytes | 12 MBs | 12 MBs + | 64 bytes | 7 MBs | 7 MBs +flexcan5 | 8 bytes | 32 MBs | 32 MBs + | 16 bytes | 21 MBs | 21 MBs + | 32 bytes | 12 MBs | 12 MBs + | 64 bytes | 7 MBs | 7 MBs +=============== ========== ================ ================ + +.. note:: + A CAN bus usually requires 60 Ohm termination at both ends of the bus. This may be + accomplished using one of the included CAN termination boards. For more details, refer + to the section ``6.3 CAN Connectors`` in the Hardware User Manual of `NXP MR-CANHUBK3`_. + +I2C +=== + +I2C is provided through LPI2C interface with 2 instances ``lpi2c0`` and ``lpi2c1`` +on corresponding connectors ``P4``, ``P3``. + +========= ===== ============ +Connector Pin Pin Function +========= ===== ============ +P3.2 PTD9 LPI2C1_SCL +P3.3 PTD8 LPI2C1_SDA +P4.3 PTD14 LPI2C0_SCL +P4.4 PTD13 LPI2C0_SDA +========= ===== ============ + +ADC +=== + +ADC is provided through ADC SAR controller with 3 instances. ADC channels are divided into +3 groups (precision, standard and external). + +.. note:: + All channels of an instance only run on 1 group channel at the same time. + +FS26 SBC Watchdog +================= + +On normal operation after the board is powered on, there is a window of 256 ms +on which the FS26 watchdog must be serviced with a good token refresh, otherwise +the watchdog will signal a reset to the MCU. This board configuration enables +the FS26 watchdog driver that handles this initialization. + +.. note:: + + The FS26 can also be started in debug mode (watchdog disabled) following + these steps: + + 1. Power off the board. + 2. Remove the jumper ``JP1`` (pins 1-2 open), which is connected by default. + 3. Power on the board. + 4. Reconnect the jumper ``JP1`` (pins 1-2 shorted). + +External Flash +============== + +The on-board MX25L6433F 64M-bit multi-I/O Serial NOR Flash memory is connected +to the QSPI controller port A1. This board configuration selects it as the +default flash controller. + +Ethernet +======== + +This board has a single instance of Ethernet Media Access Controller (EMAC) +interfacing with a `NXP TJA1103`_ 100Base-T1 Ethernet PHY. Currently, there is +limited driver for this PHY that allows for overiding the default pin strapping configuration for +the PHY (RMII, master, autonomous mode enabled, polarity correction enabled) +to slave mode. + +The 100Base-T1 signals are available in connector ``P9`` and can be converted to +100Base-T using a Ethernet media converter such as `RDDRONE-T1ADAPT`_. + +Programming and Debugging +************************* + +Applications for the ``mr_canhubk3`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ +West runners for flashing and debugging applications. Follow the steps described +in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, +to setup the flash and debug host tools for these runners, respectively. The +default runner is J-Link. + +Flashing +======== + +Run the ``west flash`` command to flash the application using SEGGER J-Link. +Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. + +The Lauterbach TRACE32 runner supports additional options that can be passed +through command line: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile= loadTo= + eraseFlash= verifyFlash= + +Where: + +- ```` is the path to the Zephyr application ELF in the output + directory +- ``loadTo=flash`` loads the application to the SoC internal program flash + (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the + application to SRAM. Default is ``flash``. +- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the + application is downloaded to either Flash or SRAM. This routine takes time to + execute. Default is ``no``. +- ``verifyFlash=yes`` verify the SoC internal flash content after programming + (use together with ``loadTo=flash``). Default is ``no``. + +For example, to erase and verify flash content: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes + +Debugging +========= + +Run the ``west debug`` command to start a GDB session using SEGGER J-Link. +Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 +software debugging interface. + +References +********** + +.. target-notes:: + +.. _NXP MR-CANHUBK3: + https://www.nxp.com/design/development-boards/automotive-development-platforms/s32k-mcu-platforms/s32k344-evaluation-board-for-mobile-robotics-incorporating-100baset1-and-six-can-fd:MR-CANHUBK344 + +.. _NXP S32K344: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k3-microcontrollers-for-automotive-general-purpose:S32K3 + +.. _NXP FS26 Safety System Basis Chip: + https://www.nxp.com/products/power-management/pmics-and-sbcs/safety-sbcs/safety-system-basis-chip-with-low-power-fit-for-asil-d:FS26 + +.. _NXP TJA1103: + https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/asil-b-compliant-100base-t1-ethernet-phy:TJA1103 + +.. _RDDRONE-T1ADAPT: + https://www.nxp.com/products/interfaces/ethernet-/automotive-ethernet-phys/ethernet-media-converter-for-drones-rovers-mobile-robotics-and-automotive:RDDRONE-T1ADAPT + +.. _Lauterbach TRACE32: + https://www.lauterbach.com + +.. _SEGGER J-Link: + https://wiki.segger.com/NXP_S32K3xx diff --git a/boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi b/boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi similarity index 100% rename from boards/arm/mr_canhubk3/mr_canhubk3-pinctrl.dtsi rename to boards/nxp/mr_canhubk3/mr_canhubk3-pinctrl.dtsi diff --git a/boards/arm/mr_canhubk3/mr_canhubk3.dts b/boards/nxp/mr_canhubk3/mr_canhubk3.dts similarity index 100% rename from boards/arm/mr_canhubk3/mr_canhubk3.dts rename to boards/nxp/mr_canhubk3/mr_canhubk3.dts diff --git a/boards/arm/mr_canhubk3/mr_canhubk3.yaml b/boards/nxp/mr_canhubk3/mr_canhubk3.yaml similarity index 100% rename from boards/arm/mr_canhubk3/mr_canhubk3.yaml rename to boards/nxp/mr_canhubk3/mr_canhubk3.yaml diff --git a/boards/arm/mr_canhubk3/mr_canhubk3_defconfig b/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig similarity index 79% rename from boards/arm/mr_canhubk3/mr_canhubk3_defconfig rename to boards/nxp/mr_canhubk3/mr_canhubk3_defconfig index d8182ce8327bb6..b6d3e6e78c7958 100644 --- a/boards/arm/mr_canhubk3/mr_canhubk3_defconfig +++ b/boards/nxp/mr_canhubk3/mr_canhubk3_defconfig @@ -1,9 +1,6 @@ -# Copyright 2023 NXP +# Copyright 2023-2024 NXP # SPDX-License-Identifier: Apache-2.0 -CONFIG_BOARD_MR_CANHUBK3=y -CONFIG_SOC_S32K344=y -CONFIG_SOC_SERIES_S32K3XX=y CONFIG_BUILD_OUTPUT_HEX=y # Use Systick as system clock diff --git a/boards/arm/mr_canhubk3/support/debug.cmm b/boards/nxp/mr_canhubk3/support/debug.cmm similarity index 100% rename from boards/arm/mr_canhubk3/support/debug.cmm rename to boards/nxp/mr_canhubk3/support/debug.cmm diff --git a/boards/arm/mr_canhubk3/support/flash.cmm b/boards/nxp/mr_canhubk3/support/flash.cmm similarity index 100% rename from boards/arm/mr_canhubk3/support/flash.cmm rename to boards/nxp/mr_canhubk3/support/flash.cmm diff --git a/boards/arm/mr_canhubk3/support/startup.cmm b/boards/nxp/mr_canhubk3/support/startup.cmm similarity index 100% rename from boards/arm/mr_canhubk3/support/startup.cmm rename to boards/nxp/mr_canhubk3/support/startup.cmm diff --git a/boards/arm64/nxp_ls1046ardb/CMakeLists.txt b/boards/nxp/rddrone_fmuk66/CMakeLists.txt similarity index 100% rename from boards/arm64/nxp_ls1046ardb/CMakeLists.txt rename to boards/nxp/rddrone_fmuk66/CMakeLists.txt diff --git a/boards/nxp/rddrone_fmuk66/Kconfig.defconfig b/boards/nxp/rddrone_fmuk66/Kconfig.defconfig new file mode 100644 index 00000000000000..b9a6f46965511f --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/Kconfig.defconfig @@ -0,0 +1,27 @@ +# RDDRONE-FMUK66 board + +# Copyright (c) 2021, Electromaticus LLC, 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RDDRONE_FMUK66 + +config OSC_XTAL0_FREQ + default 16000000 + +config MCG_PRDIV0 + default 0x0 + +config MCG_VDIV0 + default 0x4 + +config MCG_FCRDIV + default 1 + +if NETWORKING + +config NET_L2_ETHERNET + default y if !MODEM + +endif # NETWORKING + +endif # BOARD_RDDRONE_FMUK66 diff --git a/boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 b/boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 new file mode 100644 index 00000000000000..5587aeeaf66504 --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/Kconfig.rddrone_fmuk66 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RDDRONE_FMUK66 + select SOC_MK66F18 + select SOC_PART_NUMBER_MK66FN2M0VLQ18 diff --git a/boards/arm/rddrone_fmuk66/board.cmake b/boards/nxp/rddrone_fmuk66/board.cmake similarity index 100% rename from boards/arm/rddrone_fmuk66/board.cmake rename to boards/nxp/rddrone_fmuk66/board.cmake diff --git a/boards/nxp/rddrone_fmuk66/board.yml b/boards/nxp/rddrone_fmuk66/board.yml new file mode 100644 index 00000000000000..40707b2f2e4f9d --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/board.yml @@ -0,0 +1,5 @@ +board: + name: rddrone_fmuk66 + vendor: nxp + socs: + - name: mk66f18 diff --git a/boards/nxp/rddrone_fmuk66/doc/index.rst b/boards/nxp/rddrone_fmuk66/doc/index.rst new file mode 100644 index 00000000000000..69d862455ac624 --- /dev/null +++ b/boards/nxp/rddrone_fmuk66/doc/index.rst @@ -0,0 +1,202 @@ +.. _rddrone_fmuk66: + +NXP RDDRONE-FMUK66 +################## + +Overview +******** + +The RDDRONE FMUK66 is an drone control board with commonly used peripheral +connectors and a Kinetis K66 on board. + +- Comes with a J-Link Edu Mini for programming and UART console. + +.. image:: rddrone_fmuk66.jpg + :align: center + :alt: RDDRONE-FMUK66 + +Hardware +******** + +- MK66FN2MOVLQ18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 144 Low profile Quad Flat Package (LQFP)) +- Dual role USB interface with micro-B USB connector +- RGB LED +- FXOS8700CQ accelerometer and magnetometer +- FXAS21002CQ gyro +- BMM150 magnetometer +- ML3114A2 barometer +- BMP280 barometer +- Connector for PWM servo/motor controls +- Connector for UART GPS/GLONASS +- SDHC + +For more information about the K64F SoC and FRDM-K64F board: + +- `K66F Website`_ +- `K66F Datasheet`_ +- `K66F Reference Manual`_ +- `RDDRONE-FMUK66 Website`_ +- `RDDRONE-FMUK66 User Guide`_ +- `RDDRONE-FMUK66 Schematics`_ + +Supported Features +================== + +The rddrone-fmuk66 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | dma | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig` + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The K66F SoC is configured to use the 16 MHz external oscillator on the board +with the on-chip PLL to generate a 160 MHz system clock. + +Serial Port +=========== + +The K66F SoC has six UARTs. LPUART0 is configured for the console, UART0 is labeled Serial 2, +UART2 is labeled GPS, UART4 is labeled Serial 1. Any of these UARTs may be used as the console by +overlaying the board device tree. + +USB +=== + +The K66F SoC has a USB OTG (USBOTG) controller that supports both +device and host functions through its micro USB connector (K66F USB). +Only USB device function is supported in Zephyr at the moment. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use jlink. The board package +with accessories comes with a jlink mini edu and cable specifically for this board +along with a usb to uart that connects directly to the jlink mini edu. This is the expected +default configuration for programming and getting a console. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rddrone-fmuk66 + :gen-args: + :goals: build + +Configuring a Console +===================== + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rddrone-fmuk66 + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.7.0 ***** + Hello World! rddrone-fmuk66 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rddrone-fmuk66 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.7.0 ***** + Hello World! rddrone-fmuk66 + +.. _RDDRONE-FMUK66 Website: + +https://www.nxp.com/design/designs/px4-robotic-drone-vehicle-flight-management-unit-vmu-fmu-rddrone-fmuk66:RDDRONE-FMUK66 + +.. _RDDRONE-FMUK66 User Guide: + +https://nxp.gitbook.io/hovergames/userguide/getting-started + +.. _RDDRONE-FMUK66 Schematics: + +https://www.nxp.com/webapp/Download?colCode=SPF-39053 + +.. _K66F Website: + +https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 + +.. _K66F Datasheet: + +https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf + +.. _K66F Reference Manual: + +https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 diff --git a/boards/arm/rddrone_fmuk66/doc/rddrone_fmuk66.jpg b/boards/nxp/rddrone_fmuk66/doc/rddrone_fmuk66.jpg similarity index 100% rename from boards/arm/rddrone_fmuk66/doc/rddrone_fmuk66.jpg rename to boards/nxp/rddrone_fmuk66/doc/rddrone_fmuk66.jpg diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi similarity index 100% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66-pinctrl.dtsi diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts similarity index 100% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66.dts rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66.dts diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66.yaml b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml similarity index 100% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66.yaml rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66.yaml diff --git a/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig similarity index 86% rename from boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig rename to boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig index b8aa9785942b7d..fe63a4dd234cc8 100644 --- a/boards/arm/rddrone_fmuk66/rddrone_fmuk66_defconfig +++ b/boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MK66F18=y -CONFIG_SOC_SERIES_KINETIS_K6X=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/nxp/s32z2xxdc2/Kconfig.defconfig b/boards/nxp/s32z2xxdc2/Kconfig.defconfig new file mode 100644 index 00000000000000..f54f3ca4d13487 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 + +config BUILD_OUTPUT_BIN + default n + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +config UART_CONSOLE + default y + +endif # SERIAL + +if SHELL + +config SHELL_STACK_SIZE + default 4096 + +endif # SHELL + +endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1 diff --git a/boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 b/boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 new file mode 100644 index 00000000000000..ed9e2ea917f870 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/Kconfig.s32z2xxdc2 @@ -0,0 +1,7 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_S32Z2XXDC2 + select SOC_S32Z270_RTU0 if BOARD_S32Z2XXDC2_S32Z270_RTU0 + select SOC_S32Z270_RTU1 if BOARD_S32Z2XXDC2_S32Z270_RTU1 + select SOC_PART_NUMBER_P32Z270ADCK0MJFT if BOARD_S32Z2XXDC2 diff --git a/boards/arm/s32z270dc2_r52/board.cmake b/boards/nxp/s32z2xxdc2/board.cmake similarity index 100% rename from boards/arm/s32z270dc2_r52/board.cmake rename to boards/nxp/s32z2xxdc2/board.cmake diff --git a/boards/nxp/s32z2xxdc2/board.yml b/boards/nxp/s32z2xxdc2/board.yml new file mode 100644 index 00000000000000..bffe1839c3c292 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/board.yml @@ -0,0 +1,11 @@ +board: + name: s32z2xxdc2 + vendor: nxp + revision: + format: letter + default: B + revisions: + - name: B + - name: D + socs: + - name: s32z270 diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst new file mode 100644 index 00000000000000..18660e2fee5fb6 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/doc/index.rst @@ -0,0 +1,310 @@ +.. _s32z2xxdc2: + +NXP X-S32Z27X-DC (DC2) +###################### + +Overview +******** + +The X-S32Z27X-DC (DC2) board is based on the NXP S32Z2 Real-Time Processor, +which includes two Real-Time Units (RTU) composed of four ARM Cortex-R52 cores +each, with flexible split/lock configurations. + +There is one Zephyr board per SoC/RTU: + +- ``s32z2xxdc2/s32z270/rtu0``, for S32Z270/RTU0 +- ``s32z2xxdc2/s32z270/rtu1``, for S32Z270/RTU1. + +Hardware +******** + +Information about the hardware and design resources can be found at +`NXP S32Z2 Real-Time Processors website`_. + +Supported Features +================== + +The boards support the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| Arm GIC | on-chip | interrupt_controller | ++-----------+------------+-------------------------------------+ +| Arm Timer | on-chip | timer | ++-----------+------------+-------------------------------------+ +| LINFlexD | on-chip | serial | ++-----------+------------+-------------------------------------+ +| MRU | on-chip | mbox | ++-----------+------------+-------------------------------------+ +| NETC | on-chip | ethernet | +| | | | +| | | mdio | ++-----------+------------+-------------------------------------+ +| SIUL2 | on-chip | pinctrl | +| | | | +| | | gpio | +| | | | +| | | external interrupt controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| SWT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| CANEXCEL | on-chip | can | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The SoC's pads are grouped into ports and pins for consistency with GPIO driver +and the HAL drivers used by this Zephyr port. The following table summarizes +the mapping between pads and ports/pins. This must be taken into account when +using GPIO driver or configuring the pinmuxing for the device drivers. + ++-------------------+-------------+ +| Pads | Port/Pins | ++===================+=============+ +| PAD_000 - PAD_015 | PA0 - PA15 | ++-------------------+-------------+ +| PAD_016 - PAD_030 | PB0 - PB14 | ++-------------------+-------------+ +| PAD_031 | PC15 | ++-------------------+-------------+ +| PAD_032 - PAD_047 | PD0 - PD15 | ++-------------------+-------------+ +| PAD_048 - PAD_063 | PE0 - PE15 | ++-------------------+-------------+ +| PAD_064 - PAD_079 | PF0 - PF15 | ++-------------------+-------------+ +| PAD_080 - PAD_091 | PG0 - PG11 | ++-------------------+-------------+ +| PAD_092 - PAD_095 | PH12 - PH15 | ++-------------------+-------------+ +| PAD_096 - PAD_111 | PI0 - PI15 | ++-------------------+-------------+ +| PAD_112 - PAD_127 | PJ0 - PJ15 | ++-------------------+-------------+ +| PAD_128 - PAD_143 | PK0 - PK15 | ++-------------------+-------------+ +| PAD_144 - PAD_145 | PL0 - PL1 | ++-------------------+-------------+ +| PAD_146 - PAD_159 | PM2 - PM15 | ++-------------------+-------------+ +| PAD_160 - PAD_169 | PN0 - PN9 | ++-------------------+-------------+ +| PAD_170 - PAD_173 | PO10 - PO13 | ++-------------------+-------------+ + +This board does not include user LED's or switches, which are needed for some +of the samples such as :zephyr:code-sample:`blinky` or :zephyr:code-sample:`button`. +Follow the steps described in the sample description to enable support for this +board. + +System Clock +============ + +The Cortex-R52 cores are configured to run at 800 MHz. + +Serial Port +=========== + +The SoC has 12 LINFlexD instances that can be used in UART mode. The console can +be accessed by default on the USB micro-B connector `J119`. + +Watchdog +======== + +The watchdog driver only supports triggering an interrupt upon timer expiration. +Zephyr is currently running from SRAM on this board, thus system reset is not +supported. + +Ethernet +======== + +NETC driver supports to manage the Physical Station Interface (PSI0) and/or a +single Virtual SI (VSI). The rest of the VSI's shall be assigned to different +cores of the system. Refer to :ref:`nxp_s32_netc-samples` to learn how to +configure the Ethernet network controller. + +Controller Area Network (CAN) +============================= + +Currently, the CANXL transceiver is not populated in this board. So CAN transceiver +connection is required for running external traffic. We can use any CAN transceiver, +which supports CAN 2.0 and CAN FD protocol. + +CAN driver supports classic (CAN 2.0) and CAN FD mode. Remote transmission request is +not supported as this feature is not available on NXP S32 CANXL HAL. + +Programming and Debugging +************************* + +Applications for the ``s32z2xxdc2`` boards can be built in the usual way as +documented in :ref:`build_an_application`. + +Currently is only possible to load and execute a Zephyr application binary on +this board from the core internal SRAM. + +This board supports West runners for the following debug tools: + +- :ref:`NXP S32 Debug Probe ` (default) +- :ref:`Lauterbach TRACE32 ` + +Follow the installation steps of the debug tool you plan to use before loading +your firmware. + +Set-up the Board +================ + +Connect the external debugger probe to the board's JTAG connector (``J134``) +and to the host computer via USB or Ethernet, as supported by the probe. + +For visualizing the serial output, connect the board's USB/UART port (``J119``) to +the host computer and run your favorite terminal program to listen for output. +For example, using the cross-platform `pySerial miniterm`_ terminal: + +.. code-block:: console + + python -m serial.tools.miniterm 115200 + +Replace ```` with the port where the board can be found. For example, +under Linux, ``/dev/ttyUSB0``. + +Debugging +========= + +You can build and debug the :ref:`hello_world` sample for the board +``s32z2xxdc2/s32z270/rtu0`` with: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build debug + +In case you are using a newer PCB revision, you have to use an adapted board +definition as the default PCB revision is B. For example, if using revision D: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2@D/s32z270/rtu0 + :goals: build debug + :compact: + +At this point you can do your normal debug session. Set breakpoints and then +:kbd:`c` to continue into the program. You should see the following message in +the terminal: + +.. code-block:: console + + Hello World! s32z2xxdc2 + +To debug with Lauterbach TRACE32 softare run instead: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build debug -r trace32 + :compact: + +Flashing +======== + +Follow these steps if you just want to download the application to the board +SRAM and run. + +``flash`` command is supported only by the Lauterbach TRACE32 runner: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build flash -r trace32 + :compact: + +.. note:: + Currently, the Lauterbach start-up scripts executed with ``flash`` and + ``debug`` commands perform the same steps to initialize the SoC and + load the application to SRAM. The difference is that ``flash`` hides the + Lauterbach TRACE32 interface, executes the application and exits. + +To imitate a similar behavior using NXP S32 Debug Probe runner, you can run the +``debug`` command with GDB in batch mode: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build debug --tool-opt='--batch' + :compact: + +RTU and Core Configuration +========================== + +This Zephyr port can only run single core in any of the Cortex-R52 cores, +either in lock-step or split-lock mode. By default, Zephyr runs on the first +core of the RTU chosen and in lock-step mode (which is the reset +configuration). + +To build for split-lock mode, the :kconfig:option:`CONFIG_DCLS` must be +disabled from your application Kconfig file. + +By default the board configuration will set the runner arguments according to +the build configuration. To debug for a core different than the default use: + +.. tabs:: + + .. group-tab:: lockstep configuration + + .. code-block:: console + + west debug --core-name='R52___LS' + + .. group-tab:: split-lock configuration + + .. code-block:: console + + west debug --core-name='R52__' + +Where: + +- ```` is the zero-based RTU index +- ```` is the zero-based core index relative to the RTU on which to + run the Zephyr application (0, 1, 2 or 3) + +For example, to build the :ref:`hello_world` sample for the board +``s32z2xxdc2/s32z270/rtu0`` with split-lock core configuration: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: s32z2xxdc2/s32z270/rtu0 + :goals: build + :gen-args: -DCONFIG_DCLS=n + :compact: + +To execute this sample in the second core of RTU0 in split-lock mode: + +.. code-block:: console + + west debug --core-name='R52_0_1' + +If using Lauterbach TRACE32, all runner parameters must be overridden from command +line: + +.. code-block:: console + + west debug --startup-args elfFile= rtu= core= lockstep= + +Where ```` is the path to the Zephyr application ELF in the output +directory. + +References +********** + +.. target-notes:: + +.. _NXP S32Z2 Real-Time Processors website: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32z-and-s32e-real-time-processors/s32z2-safe-and-secure-high-performance-real-time-processors:S32Z2 + +.. _pySerial miniterm: + https://pyserial.readthedocs.io/en/latest/tools.html#module-serial.tools.miniterm diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi new file mode 100644 index 00000000000000..10fda8bb439352 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi @@ -0,0 +1,51 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "s32z2xxdc2_s32z270_pinctrl.dtsi" + +&swt0 { + status = "okay"; +}; + +&emdio { + pinctrl-0 = <&emdio_default>; + pinctrl-names = "default"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy"; + reg = <0x7>; + status = "okay"; + }; +}; + +&enetc_psi0 { + local-mac-address = [00 00 00 01 02 00]; + pinctrl-0 = <ð0_default>; + pinctrl-names = "default"; + clock-frequency = <300000000>; + phy-handle = <&phy0>; + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_default>; + pinctrl-names = "default"; + bus-speed = <125000>; + sample-point = <875>; + bus-speed-data = <1000000>; + sample-point-data = <875>; + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_default>; + pinctrl-names = "default"; + bus-speed = <125000>; + sample-point = <875>; + bus-speed-data = <1000000>; + sample-point-data = <875>; +}; diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_r52-pinctrl-common.dtsi rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts new file mode 100644 index 00000000000000..37c2f6b74ffe93 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts @@ -0,0 +1,33 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "s32z2xxdc2_s32z270.dtsi" + +/ { + model = "NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores"; + compatible = "nxp,s32z270"; + + chosen { + zephyr,sram = &sram0; + zephyr,canbus = &can0; + }; + + aliases { + watchdog0 = &swt0; + }; +}; + +&mru0 { + rx-channels = <1>; + status = "okay"; +}; + +&enetc_psi0 { + mboxes = <&mru0 0>; + mbox-names = "rx"; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml new file mode 100644 index 00000000000000..9bbb05c64140c8 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2/s32z270/rtu0 +name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_B.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_B.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_B.overlay diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu0_r52_D.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.overlay diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml new file mode 100644 index 00000000000000..75d0455ee593c8 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml @@ -0,0 +1,19 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2@D/s32z270/rtu0 +name: NXP X-S32Z270-DC (DC2) on RTU0 Cortex-R52 cores (rev. D) +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig new file mode 100644 index 00000000000000..d7f502c0af0061 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_defconfig @@ -0,0 +1,11 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n +CONFIG_ISR_STACK_SIZE=512 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 +CONFIG_ARM_MPU=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts new file mode 100644 index 00000000000000..ce5d16260ab1a0 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts @@ -0,0 +1,35 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "s32z2xxdc2_s32z270.dtsi" + +/ { + model = "NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores"; + compatible = "nxp,s32z270"; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,canbus = &can0; + }; + + aliases { + watchdog0 = &swt0; + }; +}; + +&mru4 { + rx-channels = <1>; + status = "okay"; +}; + +&enetc_psi0 { + mboxes = <&mru4 0>; + mbox-names = "rx"; +}; diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml new file mode 100644 index 00000000000000..77a57961550e9c --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2/s32z270/rtu1 +name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_B.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_B.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_B.overlay diff --git a/boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.overlay similarity index 100% rename from boards/arm/s32z270dc2_r52/s32z270dc2_rtu1_r52_D.overlay rename to boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.overlay diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml new file mode 100644 index 00000000000000..1d99009466c1bb --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml @@ -0,0 +1,19 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +identifier: s32z2xxdc2@D/s32z270/rtu1 +name: NXP X-S32Z270-DC (DC2) on RTU1 Cortex-R52 cores (rev. D) +type: mcu +arch: arm +ram: 1024 +toolchain: + - zephyr +supported: + - uart + - gpio + - watchdog + - netif:eth + - can + - spi + - counter +vendor: nxp diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig new file mode 100644 index 00000000000000..d7f502c0af0061 --- /dev/null +++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_defconfig @@ -0,0 +1,11 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=n +CONFIG_ISR_STACK_SIZE=512 +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000 +CONFIG_ARM_MPU=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/boards/arm/s32z270dc2_r52/support/debug.cmm b/boards/nxp/s32z2xxdc2/support/debug.cmm similarity index 77% rename from boards/arm/s32z270dc2_r52/support/debug.cmm rename to boards/nxp/s32z2xxdc2/support/debug.cmm index f4e524ff38881e..6c5054a5bd047c 100644 --- a/boards/arm/s32z270dc2_r52/support/debug.cmm +++ b/boards/nxp/s32z2xxdc2/support/debug.cmm @@ -1,8 +1,8 @@ ;******************************************************************************* -; Copyright 2022 NXP * +; Copyright 2022,2024 NXP * ; SPDX-License-Identifier: Apache-2.0 * ; * -; Lauterbach TRACE32 start-up script for debugging s32z270dc2_r52 * +; Lauterbach TRACE32 start-up script for debugging s32z2xxdc2 * ; * ;******************************************************************************* diff --git a/boards/arm/s32z270dc2_r52/support/flash.cmm b/boards/nxp/s32z2xxdc2/support/flash.cmm similarity index 77% rename from boards/arm/s32z270dc2_r52/support/flash.cmm rename to boards/nxp/s32z2xxdc2/support/flash.cmm index 60e3c103a3f9a8..1bfad445e83700 100644 --- a/boards/arm/s32z270dc2_r52/support/flash.cmm +++ b/boards/nxp/s32z2xxdc2/support/flash.cmm @@ -1,8 +1,8 @@ ;******************************************************************************* -; Copyright 2022 NXP * +; Copyright 2022,2024 NXP * ; SPDX-License-Identifier: Apache-2.0 * ; * -; Lauterbach TRACE32 start-up script for flashing s32z270dc2_r52 * +; Lauterbach TRACE32 start-up script for flashing s32z2xxdc2 * ; * ;******************************************************************************* diff --git a/boards/arm/s32z270dc2_r52/support/startup.cmm b/boards/nxp/s32z2xxdc2/support/startup.cmm similarity index 100% rename from boards/arm/s32z270dc2_r52/support/startup.cmm rename to boards/nxp/s32z2xxdc2/support/startup.cmm diff --git a/boards/arm/twr_ke18f/CMakeLists.txt b/boards/nxp/twr_ke18f/CMakeLists.txt similarity index 100% rename from boards/arm/twr_ke18f/CMakeLists.txt rename to boards/nxp/twr_ke18f/CMakeLists.txt diff --git a/boards/arm/twr_ke18f/Kconfig b/boards/nxp/twr_ke18f/Kconfig similarity index 100% rename from boards/arm/twr_ke18f/Kconfig rename to boards/nxp/twr_ke18f/Kconfig diff --git a/boards/nxp/twr_ke18f/Kconfig.defconfig b/boards/nxp/twr_ke18f/Kconfig.defconfig new file mode 100644 index 00000000000000..46d718137c5363 --- /dev/null +++ b/boards/nxp/twr_ke18f/Kconfig.defconfig @@ -0,0 +1,17 @@ +# TWR-KE18F board + +# Copyright (c) 2019 Vestas Wind Systems A/S +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TWR_KE18F + +config I2C_MCUX_LPI2C_BUS_RECOVERY + default y + depends on I2C_MCUX_LPI2C && PINCTRL + +# The KE1xF has 8 MPU regions, which is not enough for both HW stack protection +# and userspace. Only enable HW stack protection if userspace is not enabled. +config HW_STACK_PROTECTION + default y if !USERSPACE + +endif # BOARD_TWR_KE18F diff --git a/boards/nxp/twr_ke18f/Kconfig.twr_ke18f b/boards/nxp/twr_ke18f/Kconfig.twr_ke18f new file mode 100644 index 00000000000000..dbd881ae4b4cb8 --- /dev/null +++ b/boards/nxp/twr_ke18f/Kconfig.twr_ke18f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TWR_KE18F + select SOC_MKE18F16 + select SOC_PART_NUMBER_MKE18F512VLL16 diff --git a/boards/arm/twr_ke18f/board.cmake b/boards/nxp/twr_ke18f/board.cmake similarity index 100% rename from boards/arm/twr_ke18f/board.cmake rename to boards/nxp/twr_ke18f/board.cmake diff --git a/boards/nxp/twr_ke18f/board.yml b/boards/nxp/twr_ke18f/board.yml new file mode 100644 index 00000000000000..ffaf5fb235f4d3 --- /dev/null +++ b/boards/nxp/twr_ke18f/board.yml @@ -0,0 +1,5 @@ +board: + name: twr_ke18f + vendor: nxp + socs: + - name: mke18f16 diff --git a/boards/arm/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg b/boards/nxp/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg similarity index 100% rename from boards/arm/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg rename to boards/nxp/twr_ke18f/doc/TWR-KE18F-DEVICE.jpg diff --git a/boards/nxp/twr_ke18f/doc/index.rst b/boards/nxp/twr_ke18f/doc/index.rst new file mode 100644 index 00000000000000..a72227beb67663 --- /dev/null +++ b/boards/nxp/twr_ke18f/doc/index.rst @@ -0,0 +1,254 @@ +.. _twr_ke18f: + +NXP TWR-KE18F +############# + +Overview +******** + +The TWR-KE18F is a development board for NXP Kinetis KE1xF 32-bit +MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, +running an open source bootloader, offers options for serial +communication, flash programming, and run-control debugging. + +.. figure:: TWR-KE18F-DEVICE.jpg + :align: center + :alt: TWR-KE18F + + TWR-KE18F (Credit: NXP) + +Hardware +******** + +- MKE18F512VLL16 MCU (up to 168 MHz, 512 KB flash memory, 64 KB RAM, + and 100 Low profile Quad Flat Package (LQFP)) +- 3.3 V or 5 V MCU operation +- 6-axis FXOS8700CQ digital accelerometer and magnetometer +- RGB LED +- Four user LEDs +- Two user push-buttons +- Potentiometer +- Thermistor +- Infrared port (IrDA) +- CAN pin header +- Flex I/O pin header + +For more information about the KE1xF SoC and the TWR-KE18F board, see +these NXP reference documents: + +- `KE1xF Website`_ +- `KE1xF Datasheet`_ +- `KE1xF Reference Manual`_ +- `TWR-KE18F Website`_ +- `TWR-KE18F User Guide`_ +- `TWR-KE18F Schematics`_ + +Supported Features +================== + +The twr_ke18f board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | trigger supported with H/W mods | +| | | explained below; | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| ACMP | on-chip | analog comparator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/twr_ke18f/twr_ke18f_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The KE18 SoC is configured to use the 8 MHz external oscillator on the +board with the on-chip PLL to generate a 120 MHz system clock. + +Serial Port +=========== + +The KE18 SoC has three UARTs. UART0 is configured for the console. The +remaining UARTs are not used. + +Accelerometer and magnetometer +============================== + +The TWR-KE18F board by default only supports polling the FXOS8700 +accelerometer and magnetometer for sensor values +(``CONFIG_FXOS8700_TRIGGER_NONE=y``). + +In order to support FXOS8700 triggers (interrupts) the 0 ohm resistors +``R47`` and ``R57`` must be mounted on the TWR-KE18F board. The +devicetree must also be modified to describe the FXOS8700 interrupt +GPIOs: + +.. code-block:: devicetree + + /dts-v1/; + + &fxos8700 { + int1-gpios = <&gpioa 14 0>; + int2-gpios = <&gpioc 17 0>; + }; + +Finally, a trigger option must be enabled in Kconfig (either +``FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or +``FXOS8700_TRIGGER_OWN_THREAD=y``). + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`. + +Early versions of this board have an outdated version of the OpenSDA bootloader +and require an update. Please see the `DAPLink Bootloader Update`_ page for +instructions to update from the CMSIS-DAP bootloader to the DAPLink bootloader. + +Option 1: :ref:`opensda-daplink-onboard-debug-probe` (Recommended) +------------------------------------------------------------------ + +Install the :ref:`pyocd-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-daplink-onboard-debug-probe` to program +the `OpenSDA DAPLink TWR-KE18F Firmware`_. + +Option 2: :ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Firmware for TWR-KE18F`_. + +Add the arguments ``-DBOARD_FLASH_RUNNER=jlink`` and +``-DBOARD_DEBUG_RUNNER=jlink`` when you invoke ``west build`` to override the +default runner from pyOCD to J-Link: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_ke18f + :gen-args: -DBOARD_FLASH_RUNNER=jlink -DBOARD_DEBUG_RUNNER=jlink + :goals: build + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J2. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_ke18f + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_ke18f + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_ke18f + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_ke18f + +.. _TWR-KE18F Website: + https://www.nxp.com/TWR-KE18F + +.. _TWR-KE18F User Guide: + https://www.nxp.com/docs/en/user-guide/TWRKE18FUG.pdf + +.. _TWR-KE18F Schematics: + https://www.nxp.com/webapp/Download?colCode=TWR-KE18F-SCH-DESIGNFILES + +.. _KE1xF Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/e-series5v-robustm0-plus-m4/kinetis-ke1xf-168mhz-performance-with-can-5v-microcontrollers-based-on-arm-cortex-m4:KE1xF + +.. _KE1xF Datasheet: + https://www.nxp.com/docs/en/data-sheet/KE1xFP100M168SF0.pdf + +.. _KE1xF Reference Manual: + https://www.nxp.com/docs/en/reference-manual/KE1xFP100M168SF0RM.pdf + +.. _DAPLink Bootloader Update: + https://os.mbed.com/blog/entry/DAPLink-bootloader-update/ + +.. _OpenSDA DAPLink TWR-KE18F Firmware: + https://www.nxp.com/support/developer-resources/run-time-software/kinetis-developer-resources/ides-for-kinetis-mcus/opensda-serial-and-debug-adapter:OPENSDA#TWR-KE18F + +.. _OpenSDA J-Link Firmware for TWR-KE18F: + https://www.segger.com/downloads/jlink/OpenSDA_TWR-KE18F diff --git a/boards/arm/twr_ke18f/dts/bindings/nxp,flexio.yaml b/boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml similarity index 100% rename from boards/arm/twr_ke18f/dts/bindings/nxp,flexio.yaml rename to boards/nxp/twr_ke18f/dts/bindings/nxp,flexio.yaml diff --git a/boards/arm/twr_ke18f/dts/lpspi0_pcs2.overlay b/boards/nxp/twr_ke18f/dts/lpspi0_pcs2.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi0_pcs2.overlay rename to boards/nxp/twr_ke18f/dts/lpspi0_pcs2.overlay diff --git a/boards/arm/twr_ke18f/dts/lpspi1_pcs0.overlay b/boards/nxp/twr_ke18f/dts/lpspi1_pcs0.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi1_pcs0.overlay rename to boards/nxp/twr_ke18f/dts/lpspi1_pcs0.overlay diff --git a/boards/arm/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay b/boards/nxp/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay rename to boards/nxp/twr_ke18f/dts/lpspi1_pcs0_pcs2.overlay diff --git a/boards/arm/twr_ke18f/dts/lpspi1_pcs2.overlay b/boards/nxp/twr_ke18f/dts/lpspi1_pcs2.overlay similarity index 100% rename from boards/arm/twr_ke18f/dts/lpspi1_pcs2.overlay rename to boards/nxp/twr_ke18f/dts/lpspi1_pcs2.overlay diff --git a/boards/arm/twr_ke18f/pinmux.c b/boards/nxp/twr_ke18f/pinmux.c similarity index 100% rename from boards/arm/twr_ke18f/pinmux.c rename to boards/nxp/twr_ke18f/pinmux.c diff --git a/boards/arm/twr_ke18f/twr_ke18f-pinctrl.dtsi b/boards/nxp/twr_ke18f/twr_ke18f-pinctrl.dtsi similarity index 100% rename from boards/arm/twr_ke18f/twr_ke18f-pinctrl.dtsi rename to boards/nxp/twr_ke18f/twr_ke18f-pinctrl.dtsi diff --git a/boards/arm/twr_ke18f/twr_ke18f.dts b/boards/nxp/twr_ke18f/twr_ke18f.dts similarity index 100% rename from boards/arm/twr_ke18f/twr_ke18f.dts rename to boards/nxp/twr_ke18f/twr_ke18f.dts diff --git a/boards/arm/twr_ke18f/twr_ke18f.yaml b/boards/nxp/twr_ke18f/twr_ke18f.yaml similarity index 100% rename from boards/arm/twr_ke18f/twr_ke18f.yaml rename to boards/nxp/twr_ke18f/twr_ke18f.yaml diff --git a/boards/nxp/twr_ke18f/twr_ke18f_defconfig b/boards/nxp/twr_ke18f/twr_ke18f_defconfig new file mode 100644 index 00000000000000..1890a4409028d3 --- /dev/null +++ b/boards/nxp/twr_ke18f/twr_ke18f_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y + +# Enable MPU +CONFIG_ARM_MPU=y diff --git a/boards/arm64/roc_rk3568_pc/CMakeLists.txt b/boards/nxp/twr_kv58f220m/CMakeLists.txt similarity index 100% rename from boards/arm64/roc_rk3568_pc/CMakeLists.txt rename to boards/nxp/twr_kv58f220m/CMakeLists.txt diff --git a/boards/nxp/twr_kv58f220m/Kconfig.defconfig b/boards/nxp/twr_kv58f220m/Kconfig.defconfig new file mode 100644 index 00000000000000..e77978b430ad0f --- /dev/null +++ b/boards/nxp/twr_kv58f220m/Kconfig.defconfig @@ -0,0 +1,20 @@ +# TWR-KV58F220M board + +# Copyright (c) 2019 SEAL AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TWR_KV58F220M + +config OSC_XTAL0_FREQ + default 50000000 + +config MCG_PRDIV0 + default 0x3 + +config MCG_VDIV0 + default 0x16 + +config MCG_FCRDIV + default 1 + +endif # BOARD_TWR_KV58F220M diff --git a/boards/nxp/twr_kv58f220m/Kconfig.twr_kv58f220m b/boards/nxp/twr_kv58f220m/Kconfig.twr_kv58f220m new file mode 100644 index 00000000000000..280f8b625a4d0f --- /dev/null +++ b/boards/nxp/twr_kv58f220m/Kconfig.twr_kv58f220m @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TWR_KV58F220M + select SOC_MKV58F24 + select SOC_PART_NUMBER_MKV58F1M0VLQ24 diff --git a/boards/arm/twr_kv58f220m/board.cmake b/boards/nxp/twr_kv58f220m/board.cmake similarity index 100% rename from boards/arm/twr_kv58f220m/board.cmake rename to boards/nxp/twr_kv58f220m/board.cmake diff --git a/boards/nxp/twr_kv58f220m/board.yml b/boards/nxp/twr_kv58f220m/board.yml new file mode 100644 index 00000000000000..536e16c178f28b --- /dev/null +++ b/boards/nxp/twr_kv58f220m/board.yml @@ -0,0 +1,5 @@ +board: + name: twr_kv58f220m + vendor: nxp + socs: + - name: mkv58f24 diff --git a/boards/nxp/twr_kv58f220m/doc/index.rst b/boards/nxp/twr_kv58f220m/doc/index.rst new file mode 100644 index 00000000000000..98cc3a880afe75 --- /dev/null +++ b/boards/nxp/twr_kv58f220m/doc/index.rst @@ -0,0 +1,200 @@ +.. _twr_kv58f220m: + +NXP TWR-KV58F220M +################# + +Overview +******** + +The TWR-KV58F220M is a development board for NXP Kinetis KV5x 32-bit +MCU-based platforms. The onboard OpenSDAv2 serial and debug adapter, +running an open source bootloader, offers options for serial +communication, flash programming, and run-control debugging. + +.. figure:: twr_kv58f220m.jpg + :align: center + :alt: TWR-KV58F220M + + TWR-KV58F220M (Credit: NXP) + +Hardware +******** + +- MKV58F1M0VLQ24 MCU (up to 240 MHz, 1 MB flash memory, 256 KB RAM, + and 144 Low profile Quad Flat Package (LQFP)) +- 1.8 V or 3.3 V MCU operation +- 6-axis FXOS8700CQ digital accelerometer and magnetometer +- Four user LEDs +- Four user push-buttons +- Potentiometer +- Two general purpose TWRPI headers +- Motor pin header + +For more information about the KV5x SoC and the TWR-KV58F220M board, see +these NXP reference documents: + +- `KV5x Website`_ +- `KV5x Datasheet`_ +- `KV5x Reference Manual`_ +- `TWR-KV58F220M Website`_ +- `TWR-KV58F220M User Guide`_ +- `TWR-KV58F220M Schematics`_ + +Supported Features +================== + +The twr_kv58f220m board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig`. + +Other hardware features are not currently supported by the port. + +System Clock +============ + +The KV58 SoC is configured to use the 50 MHz external oscillator on the +board with the on-chip PLL to generate a 237.5 MHz system clock. + +Serial Port +=========== + +The KV58 SoC has six UARTs. UART0 is configured for the console. The +remaining UARTs are not used. + +Accelerometer and magnetometer +============================== + +The TWR-KV58F220M board by default only supports polling the FXOS8700 +accelerometer and magnetometer for sensor values +(``CONFIG_FXOS8700_TRIGGER_NONE=y``). + +In order to support FXOS8700 triggers (interrupts), shunts must be placed on +the jumpers ``J2`` and ``J9``. A trigger option also must be enabled in Kconfig +(either ``CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD=y`` or +``CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y``). + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +This board integrates an OpenSDA debug probe. However, it can currently only be +used for flashing the KV58 SoC by copying the compiled firmware to the USB Mass +Storage Device. The board cannot be debugged using the OpenSDA probe, since +pyOCD does not support the target. The OpenSDA J-Link firmware (as of release +2019-06-03) also cannot be used, since the flash algorithm for the KV58 seems to +be broken at the time of writing. + +An external J-Link debug probe connected to the JTAG header J13 is used to debug +the target. + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :tool: all + :board: twr_kv58f220m + :goals: build + +Configuring a Console +===================== + +Even though the OpenSDA probe cannot be used for debugging, we will use it as a +USB-to-serial adapter for the serial console. + +Connect a USB cable from your PC to J22. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_kv58f220m + :goals: flash + +Open a serial terminal, reset the board (press the SW1 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_kv58f220m + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: twr_kv58f220m + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx ***** + Hello World! twr_kv58f220m + +.. _TWR-KV58F220M Website: + https://www.nxp.com/TWR-KV58F220M + +.. _TWR-KV58F220M User Guide: + https://www.nxp.com/webapp/Download?colCode=TWRKV58F220MUG + +.. _TWR-KV58F220M Schematics: + https://www.nxp.com/webapp/Download?colCode=TWR-KV58F220M-SCH + +.. _KV5x Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/general-purpose-mcus/kv-series-cortex-m4-m0-plus-m7/kinetis-kv5x-240-mhz-motor-control-and-power-conversion-ethernet-mcus-based-on-arm-cortex-m7:KV5x + +.. _KV5x Datasheet: + https://www.nxp.com/docs/en/data-sheet/KV5XP144M240.pdf + +.. _KV5x Reference Manual: + https://www.nxp.com/webapp/Download?colCode=KV5XP144M240RM diff --git a/boards/arm/twr_kv58f220m/doc/twr_kv58f220m.jpg b/boards/nxp/twr_kv58f220m/doc/twr_kv58f220m.jpg similarity index 100% rename from boards/arm/twr_kv58f220m/doc/twr_kv58f220m.jpg rename to boards/nxp/twr_kv58f220m/doc/twr_kv58f220m.jpg diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi b/boards/nxp/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi similarity index 100% rename from boards/arm/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi rename to boards/nxp/twr_kv58f220m/twr_kv58f220m-pinctrl.dtsi diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m.dts b/boards/nxp/twr_kv58f220m/twr_kv58f220m.dts similarity index 100% rename from boards/arm/twr_kv58f220m/twr_kv58f220m.dts rename to boards/nxp/twr_kv58f220m/twr_kv58f220m.dts diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m.yaml b/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml similarity index 100% rename from boards/arm/twr_kv58f220m/twr_kv58f220m.yaml rename to boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml diff --git a/boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig b/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig similarity index 75% rename from boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig rename to boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig index c46bf43c2a660f..88afd604b5b802 100644 --- a/boards/arm/twr_kv58f220m/twr_kv58f220m_defconfig +++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_KINETIS_KV5X=y -CONFIG_SOC_MKV58F24=y -CONFIG_BOARD_TWR_KV58F220M=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/nxp/ucans32k1sic/Kconfig.defconfig b/boards/nxp/ucans32k1sic/Kconfig.defconfig new file mode 100644 index 00000000000000..9c6542625ba8e1 --- /dev/null +++ b/boards/nxp/ucans32k1sic/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UCANS32K1SIC + +if SERIAL + +config UART_CONSOLE + default y + +endif # SERIAL + +if CAN + +config GPIO + default y + +endif # CAN + +endif # BOARD_UCANS32K1SIC diff --git a/boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic b/boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic new file mode 100644 index 00000000000000..26ec94435f40b3 --- /dev/null +++ b/boards/nxp/ucans32k1sic/Kconfig.ucans32k1sic @@ -0,0 +1,6 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UCANS32K1SIC + select SOC_S32K146 + select SOC_PART_NUMBER_FS32K146UAT0VLHT diff --git a/boards/arm/ucans32k1sic/board.cmake b/boards/nxp/ucans32k1sic/board.cmake similarity index 100% rename from boards/arm/ucans32k1sic/board.cmake rename to boards/nxp/ucans32k1sic/board.cmake diff --git a/boards/nxp/ucans32k1sic/board.yml b/boards/nxp/ucans32k1sic/board.yml new file mode 100644 index 00000000000000..87964b5201fbcc --- /dev/null +++ b/boards/nxp/ucans32k1sic/board.yml @@ -0,0 +1,5 @@ +board: + name: ucans32k1sic + vendor: nxp + socs: + - name: s32k146 diff --git a/boards/arm/ucans32k1sic/doc/img/ucans32k1sic_top.webp b/boards/nxp/ucans32k1sic/doc/img/ucans32k1sic_top.webp similarity index 100% rename from boards/arm/ucans32k1sic/doc/img/ucans32k1sic_top.webp rename to boards/nxp/ucans32k1sic/doc/img/ucans32k1sic_top.webp diff --git a/boards/nxp/ucans32k1sic/doc/index.rst b/boards/nxp/ucans32k1sic/doc/index.rst new file mode 100644 index 00000000000000..969d67e815ae04 --- /dev/null +++ b/boards/nxp/ucans32k1sic/doc/index.rst @@ -0,0 +1,197 @@ +.. _ucans32k1sic: + +NXP UCANS32K1SIC +################ + +Overview +******** + +`NXP UCANS32K1SIC`_ is a CAN signal improvement capability (SIC) evaluation +board designed for both automotive and industrial applications. The UCANS32K1SIC +provides two CAN SIC interfaces and is based on the 32-bit Arm Cortex-M4F +`NXP S32K146`_ microcontroller. + +.. image:: img/ucans32k1sic_top.webp + :align: center + :alt: NXP UCANS32K1SIC (TOP) + +Hardware +******** + +- NXP S32K146 + - Arm Cortex-M4F @ up to 112 Mhz + - 1 MB Flash + - 128 KB SRAM + - up to 127 I/Os + - 3x FlexCAN with 2x FD + - eDMA, 12-bit ADC, MPU, ECC and more. + +- Interfaces: + - DCD-LZ debug interface with SWD + Console / UART + - Dual CAN FD PHYs with dual connectors for daisy chain operation + - JST-GH DroneCode compliant standard connectors and I/O headers + - user RGB LED and button. + +More information about the hardware and design resources can be found at +`NXP UCANS32K1SIC`_ website. + +Supported Features +================== + +The ``ucans32k1sic`` board configuration supports the following hardware features: + +============ ========== ================================ +Interface Controller Driver/Component +============ ========== ================================ +SYSMPU on-chip mpu +PORT on-chip pinctrl +GPIO on-chip gpio +LPUART on-chip serial +LPI2C on-chip i2c +LPSPI on-chip spi +FTM on-chip pwm +FlexCAN on-chip can +Watchdog on-chip watchdog +RTC on-chip counter +============ ========== ================================ + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/nxp/ucans32k1sic/ucans32k1sic_defconfig`. + +Connections and IOs +=================== + +This board has 5 GPIO ports named from ``gpioa`` to ``gpioe``. + +Pin control can be further configured from your application overlay by adding +children nodes with the desired pinmux configuration to the singleton node +``pinctrl``. Supported properties are described in +:zephyr_file:`dts/bindings/pinctrl/nxp,kinetis-pinctrl.yaml`. + +LEDs +---- + +The UCANS32K1SIC board has one user RGB LED that can be used either as a GPIO +LED or as a PWM LED. + +.. table:: RGB LED as GPIO LED + :widths: auto + + =============== ================ =============== ===== + Devicetree node Devicetree alias Label Pin + =============== ================ =============== ===== + led1_red led0 LED1_RGB_RED PTD15 + led1_green led1 LED1_RGB_GREEN PTD16 + led1_blue led2 LED1_RGB_BLUE PTD0 + =============== ================ =============== ===== + +.. table:: RGB LED as PWM LED + :widths: auto + + =============== ======================== ================== ================ + Devicetree node Devicetree alias Label Pin + =============== ======================== ================== ================ + led1_red_pwm pwm-led0 / red-pwm-led LED1_RGB_RED_PWM PTD15 / FTM0_CH0 + led1_green_pwm pwm-led1 / green-pwm-led LED1_RGB_GREEN_PWM PTD16 / FTM0_CH1 + led1_blue_pwm pwm-led2 / blue-pwm-led LED1_RGB_BLUE_PWM PTD0 / FTM0_CH2 + =============== ======================== ================== ================ + +The user can control the LEDs in any way. An output of ``0`` illuminates the LED. + +Buttons +------- + +The UCANS32K1SIC board has one user button: + +======================= ============== ===== +Devicetree node Label Pin +======================= ============== ===== +sw0 / button_3 SW3 PTD15 +======================= ============== ===== + +Serial Console +============== + +The serial console is provided via ``lpuart1`` on the 7-pin DCD-LZ debug +connector ``P6``. + +========= ===== ============ +Connector Pin Pin Function +========= ===== ============ +P6.2 PTC7 LPUART1_TX +P6.3 PTC6 LPUART1_RX +========= ===== ============ + +System Clock +============ + +The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode). + +Programming and Debugging +************************* + +Applications for the ``ucans32k1sic`` board can be built in the usual way as +documented in :ref:`build_an_application`. + +This board configuration supports `Lauterbach TRACE32`_ and `SEGGER J-Link`_ +West runners for flashing and debugging applications. Follow the steps described +in :ref:`lauterbach-trace32-debug-host-tools` and :ref:`jlink-debug-host-tools`, +to setup the flash and debug host tools for these runners, respectively. The +default runner is J-Link. + +Flashing +======== + +Run the ``west flash`` command to flash the application using SEGGER J-Link. +Alternatively, run ``west flash -r trace32`` to use Lauterbach TRACE32. + +The Lauterbach TRACE32 runner supports additional options that can be passed +through command line: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile= loadTo= + eraseFlash= verifyFlash= + +Where: + +- ```` is the path to the Zephyr application ELF in the output + directory +- ``loadTo=flash`` loads the application to the SoC internal program flash + (:kconfig:option:`CONFIG_XIP` must be set), and ``loadTo=sram`` load the + application to SRAM. The default is ``flash``. +- ``eraseFlash=yes`` erases the whole content of SoC internal flash before the + application is downloaded to either Flash or SRAM. This routine takes time to + execute. The default is ``no``. +- ``verifyFlash=yes`` verify the SoC internal flash content after programming + (use together with ``loadTo=flash``). The default is ``no``. + +For example, to erase and verify flash content: + +.. code-block:: console + + west flash -r trace32 --startup-args elfFile=build/zephyr/zephyr.elf loadTo=flash eraseFlash=yes verifyFlash=yes + +Debugging +========= + +Run the ``west debug`` command to start a GDB session using SEGGER J-Link. +Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32 +software debugging interface. + +References +********** + +.. target-notes:: + +.. _NXP UCANS32K1SIC: + https://www.nxp.com/design/development-boards/analog-toolbox/can-sic-evaluation-board:UCANS32K1SIC + +.. _NXP S32K146: + https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32k-auto-general-purpose-mcus/s32k1-microcontrollers-for-automotive-general-purpose:S32K1 + +.. _Lauterbach TRACE32: + https://www.lauterbach.com + +.. _SEGGER J-Link: + https://wiki.segger.com/S32Kxxx diff --git a/boards/arm/ucans32k1sic/support/debug.cmm b/boards/nxp/ucans32k1sic/support/debug.cmm similarity index 100% rename from boards/arm/ucans32k1sic/support/debug.cmm rename to boards/nxp/ucans32k1sic/support/debug.cmm diff --git a/boards/arm/ucans32k1sic/support/flash.cmm b/boards/nxp/ucans32k1sic/support/flash.cmm similarity index 100% rename from boards/arm/ucans32k1sic/support/flash.cmm rename to boards/nxp/ucans32k1sic/support/flash.cmm diff --git a/boards/arm/ucans32k1sic/support/startup.cmm b/boards/nxp/ucans32k1sic/support/startup.cmm similarity index 100% rename from boards/arm/ucans32k1sic/support/startup.cmm rename to boards/nxp/ucans32k1sic/support/startup.cmm diff --git a/boards/arm/ucans32k1sic/ucans32k1sic-pinctrl.dtsi b/boards/nxp/ucans32k1sic/ucans32k1sic-pinctrl.dtsi similarity index 100% rename from boards/arm/ucans32k1sic/ucans32k1sic-pinctrl.dtsi rename to boards/nxp/ucans32k1sic/ucans32k1sic-pinctrl.dtsi diff --git a/boards/arm/ucans32k1sic/ucans32k1sic.dts b/boards/nxp/ucans32k1sic/ucans32k1sic.dts similarity index 100% rename from boards/arm/ucans32k1sic/ucans32k1sic.dts rename to boards/nxp/ucans32k1sic/ucans32k1sic.dts diff --git a/boards/arm/ucans32k1sic/ucans32k1sic.yaml b/boards/nxp/ucans32k1sic/ucans32k1sic.yaml similarity index 100% rename from boards/arm/ucans32k1sic/ucans32k1sic.yaml rename to boards/nxp/ucans32k1sic/ucans32k1sic.yaml diff --git a/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig new file mode 100644 index 00000000000000..e852568a799ab4 --- /dev/null +++ b/boards/nxp/ucans32k1sic/ucans32k1sic_defconfig @@ -0,0 +1,17 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +# Use Systick as system clock +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000 + +# Run from internal program flash +CONFIG_XIP=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y diff --git a/boards/arm64/rpi_4b/CMakeLists.txt b/boards/nxp/usb_kw24d512/CMakeLists.txt similarity index 100% rename from boards/arm64/rpi_4b/CMakeLists.txt rename to boards/nxp/usb_kw24d512/CMakeLists.txt diff --git a/boards/nxp/usb_kw24d512/Kconfig.defconfig b/boards/nxp/usb_kw24d512/Kconfig.defconfig new file mode 100644 index 00000000000000..edee8ad53a38a4 --- /dev/null +++ b/boards/nxp/usb_kw24d512/Kconfig.defconfig @@ -0,0 +1,28 @@ +# USB-KW24D512 board + +# Copyright (c) 2017, Phytec Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_USB_KW24D512 + +config OSC_XTAL0_FREQ + # The MCU is configured to use 4 MHz external + # clock from the transceiver provided at the CLK_OUT output. + # CLK_OUT is internally connected to the input pin EXTAL0 + # of the MCU. + default 4000000 + +config MCG_PRDIV0 + default 0x1 + +config MCG_VDIV0 + default 0x0 + +config MCG_FCRDIV + default 2 + +config MCR20A_IS_PART_OF_KW2XD_SIP + default y + depends on IEEE802154_MCR20A + +endif # BOARD_USB_KW24D512 diff --git a/boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 b/boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 new file mode 100644 index 00000000000000..768435783af66f --- /dev/null +++ b/boards/nxp/usb_kw24d512/Kconfig.usb_kw24d512 @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_USB_KW24D512 + select SOC_MKW24D5 + select SOC_PART_NUMBER_MKW24D512VHA5 diff --git a/boards/arm/usb_kw24d512/board.cmake b/boards/nxp/usb_kw24d512/board.cmake similarity index 100% rename from boards/arm/usb_kw24d512/board.cmake rename to boards/nxp/usb_kw24d512/board.cmake diff --git a/boards/nxp/usb_kw24d512/board.yml b/boards/nxp/usb_kw24d512/board.yml new file mode 100644 index 00000000000000..21dae9f84358da --- /dev/null +++ b/boards/nxp/usb_kw24d512/board.yml @@ -0,0 +1,5 @@ +board: + name: usb_kw24d512 + vendor: nxp + socs: + - name: mkw24d5 diff --git a/boards/nxp/usb_kw24d512/doc/index.rst b/boards/nxp/usb_kw24d512/doc/index.rst new file mode 100644 index 00000000000000..b617edcf6d6f8d --- /dev/null +++ b/boards/nxp/usb_kw24d512/doc/index.rst @@ -0,0 +1,230 @@ +.. _usb_kw24d512: + +NXP USB-KW24D512 +################ + +Overview +******** + +The USB-KW24D512 is an evaluation board in a convenient USB dongle +form factor based on the NXP MKW24D512 System-in-Package (SiP) device +(KW2xD wireless MCU series). +MKW24D512 wireless MCU provides a low-power, compact device with +integrated IEEE 802.15.4 radio. The board can be used as a packet sniffer, +network node, border router or as a development board. + +Hardware +******** + +- Kinetis KW2xD-2.4 GHz 802.15.4 Wireless Radio Microcontroller + (50 MHz, 512 KB flash memory, 64 KB RAM, low-power, crystal-less USB) +- USB Type A Connector +- Two blue LEDs +- One user push button +- One reset button +- Integrated PCB Folded F-type antenna +- 10-pin (0.05”) JTAG debug port for target MCU + +For more information about the KW2xD SiP and USB-KW24D512 board: + +- `KW2xD Website`_ +- `KW2xD Datasheet`_ +- `KW2xD Reference Manual`_ +- `USB-KW24D512 Website`_ +- `USB-KW24D512 Hardware Reference Manual`_ + +Supported Features +================== + +The USB-KW24D512 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| RNGA | on-chip | entropy; | +| | | random | ++-----------+------------+-------------------------------------+ +| FTFL | on-chip | flash programming | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/nxp/usb_kw24d512/usb_kw24d512_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The KW2xD SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+--------------------------------------+ +| Name | Function | Usage | ++=======+=================+======================================+ +| PTA1 | UART0_RX | UART Console | ++-------+-----------------+--------------------------------------+ +| PTA2 | UART0_TX | UART Console | ++-------+-----------------+--------------------------------------+ +| PTC4 | GPIO | SW1 | ++-------+-----------------+--------------------------------------+ +| PTD4 | GPIO | Blue LED (D2) | ++-------+-----------------+--------------------------------------+ +| PTD5 | GPIO | Blue LED (D3) | ++-------+-----------------+--------------------------------------+ +| PTB10 | SPI1_PCS0 | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB11 | SPI1_SCK | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB16 | SPI1_SOUT | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB17 | SPI1_SIN | internal connected to MCR20A | ++-------+-----------------+--------------------------------------+ +| PTB19 | GPIO | internal connected to MCR20A (Reset) | ++-------+-----------------+--------------------------------------+ +| PTB3 | GPIO | internal connected to MCR20A (IRQ_B) | ++-------+-----------------+--------------------------------------+ +| PTC0 | GPIO | internal connected to MCR20A (GPIO5) | ++-------+-----------------+--------------------------------------+ + +System Clock +============ + +USB-KW24D512 contains 32 MHz oscillator crystal, which is connected to the +clock pins of the radio transceiver. The MCU is configured to +use the 4 MHz external clock from the transceiver with the on-chip PLL +to generate a 48 MHz system clock. + +Serial Port +=========== + +The KW2xD SoC has three UARTs. One is configured and can be used for the +console, but it uses the same pins as the JTAG interface and is only +accessible via the JTAG SWD connector. + +USB +=== + +The KW2xD SoC has a USB OTG (USBOTG) controller that supports both +device and host functions. Only USB device function is supported in Zephyr +at the moment. The USB-KW24D512 board has a USB Type A connector and +can only be used in device mode. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`jlink-external-debug-probe`. + +:ref:`jlink-external-debug-probe` +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Attach a J-Link 10-pin connector to J1. + +Configuring a Console +===================== + +The console is available using `Segger RTT`_. + +Connect a USB cable from your PC to J5. + +Once you have started a debug session, run telnet: + +.. code-block:: console + + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + SEGGER J-Link V6.44 - Real time terminal output + SEGGER J-Link ARM V10.1, SN=600111924 + Process: JLinkGDBServerCLExe + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: usb_kw24d512 + :goals: flash + +The Segger RTT console is only available during a debug session. Use ``attach`` +to start one: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: usb_kw24d512 + :goals: attach + +Run telnet as shown earlier, and you should see the following message in the +terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! usb_kw24d512 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: usb_kw24d512 + :goals: debug + +Run telnet as shown earlier, step through the application in your debugger, and +you should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v1.14.0-rc1 ***** + Hello World! usb_kw24d512 + +.. _USB-KW24D512 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/ieee-802.15.4-packet-sniffer-usb-dongle-form-factor:USB-KW24D512 + +.. _USB-KW24D512 Hardware Reference Manual: + https://www.nxp.com/webapp/Download?colCode=USB-KW2XHWRM + +.. _KW2xD Website: + https://www.nxp.com/products/wireless/thread/kinetis-kw2xd-2.4-ghz-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m4-core:KW2xD + +.. _KW2xD Datasheet: + https://www.nxp.com/docs/en/data-sheet/MKW2xDxxx.pdf + +.. _KW2xD Reference Manual: + https://www.nxp.com/webapp/Download?colCode=MKW2XDXXXRM + +.. _Segger RTT: + https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/ diff --git a/boards/arm/usb_kw24d512/usb_kw24d512-pinctrl.dtsi b/boards/nxp/usb_kw24d512/usb_kw24d512-pinctrl.dtsi similarity index 100% rename from boards/arm/usb_kw24d512/usb_kw24d512-pinctrl.dtsi rename to boards/nxp/usb_kw24d512/usb_kw24d512-pinctrl.dtsi diff --git a/boards/arm/usb_kw24d512/usb_kw24d512.dts b/boards/nxp/usb_kw24d512/usb_kw24d512.dts similarity index 100% rename from boards/arm/usb_kw24d512/usb_kw24d512.dts rename to boards/nxp/usb_kw24d512/usb_kw24d512.dts diff --git a/boards/arm/usb_kw24d512/usb_kw24d512.yaml b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml similarity index 100% rename from boards/arm/usb_kw24d512/usb_kw24d512.yaml rename to boards/nxp/usb_kw24d512/usb_kw24d512.yaml diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig b/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig new file mode 100644 index 00000000000000..005cd998960f0e --- /dev/null +++ b/boards/nxp/usb_kw24d512/usb_kw24d512_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_RTT_CONSOLE=y +CONFIG_USE_SEGGER_RTT=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_OSC_EXTERNAL=y diff --git a/boards/nxp/vmu_rt1170/CMakeLists.txt b/boards/nxp/vmu_rt1170/CMakeLists.txt new file mode 100644 index 00000000000000..2a12ecb3611361 --- /dev/null +++ b/boards/nxp/vmu_rt1170/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright 2023 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_library() + set(RT1170_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1170") + if(CONFIG_BOOT_FLEXSPI_NOR) + # Include flash configuration block for RT1170 EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN12238 for more information. + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(flexspi_nor_config.c) + zephyr_library_include_directories(${RT1170_BOARD_DIR}/xip) + endif() +endif() + +if(CONFIG_MCUX_GPT_TIMER) + message(WARNING "You appear to be using the GPT hardware timer. " + "This timer will enable lower power modes, but at the cost of reduced " + "hardware timer resolution") +endif() diff --git a/boards/nxp/vmu_rt1170/Kconfig.defconfig b/boards/nxp/vmu_rt1170/Kconfig.defconfig new file mode 100644 index 00000000000000..f0f7bffa888b06 --- /dev/null +++ b/boards/nxp/vmu_rt1170/Kconfig.defconfig @@ -0,0 +1,38 @@ +# VMU_RT1170 board + +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_VMU_RT1170 + +if DISK_DRIVERS + +config IMX_USDHC_DAT3_PWR_TOGGLE + default y + +endif # DISK_DRIVERS + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM if CPU_CORTEX_M7 + default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM if CPU_CORTEX_M4 +endchoice + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +if NETWORKING + +config NET_L2_ETHERNET + default y if CPU_CORTEX_M7 # No cache memory support is required for driver + +config ETH_MCUX_PHY_RESET + default n + +config ETH_MCUX_RMII_EXT_CLK + default y + +endif # NETWORKING + + +endif # BOARD_VMU_RT1170 diff --git a/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 new file mode 100644 index 00000000000000..cfd9ba449db94d --- /dev/null +++ b/boards/nxp/vmu_rt1170/Kconfig.vmu_rt1170 @@ -0,0 +1,6 @@ +# Copyright 2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VMU_RT1170_MIMXRT1176_CM7 + select SOC_MIMXRT1176_CM7 + select SOC_PART_NUMBER_MIMXRT1176DVMAA diff --git a/boards/arm/vmu_rt1170/board.cmake b/boards/nxp/vmu_rt1170/board.cmake similarity index 100% rename from boards/arm/vmu_rt1170/board.cmake rename to boards/nxp/vmu_rt1170/board.cmake diff --git a/boards/nxp/vmu_rt1170/board.yml b/boards/nxp/vmu_rt1170/board.yml new file mode 100644 index 00000000000000..91d9d2e83b2dec --- /dev/null +++ b/boards/nxp/vmu_rt1170/board.yml @@ -0,0 +1,5 @@ +board: + name: vmu_rt1170 + vendor: nxp + socs: + - name: mimxrt1176 diff --git a/boards/arm/vmu_rt1170/doc/index.rst b/boards/nxp/vmu_rt1170/doc/index.rst similarity index 100% rename from boards/arm/vmu_rt1170/doc/index.rst rename to boards/nxp/vmu_rt1170/doc/index.rst diff --git a/boards/arm/vmu_rt1170/doc/vmu_rt1170.jpg b/boards/nxp/vmu_rt1170/doc/vmu_rt1170.jpg similarity index 100% rename from boards/arm/vmu_rt1170/doc/vmu_rt1170.jpg rename to boards/nxp/vmu_rt1170/doc/vmu_rt1170.jpg diff --git a/boards/nxp/vmu_rt1170/flexspi_nor_config.c b/boards/nxp/vmu_rt1170/flexspi_nor_config.c new file mode 100644 index 00000000000000..85ad476cf84c05 --- /dev/null +++ b/boards/nxp/vmu_rt1170/flexspi_nor_config.c @@ -0,0 +1,149 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/*! + * @brief ROM API init + * + * Get the bootloader api entry address. + */ +void ROM_API_Init(void); + +/*! + * @brief Initialize Serial NOR devices via FLEXSPI + * + * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. + * + * @param instance storage the instance of FLEXSPI. + * @param config A pointer to the storage for the driver runtime state. + * + * @retval kStatus_Success Api was executed successfully. + * @retval kStatus_InvalidArgument A invalid argument is provided. + * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. + * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. + * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout + */ +status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, struct flexspi_nor_config_t *config); + + + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +/* Config used for booting */ + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackInternally, + .csHoldTime = 1u, + .csSetupTime = 1u, + .sflashPadType = kSerialFlash_1Pad, + .serialClkFreq = kFlexSpiSerialClk_80MHz, + .sflashA1Size = 64u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x03, RADDR_SDR, + FLEXSPI_1PAD, 0x18), + FLEXSPI_LUT_SEQ(READ_SDR, FLEXSPI_1PAD, + 0x04, STOP, + FLEXSPI_1PAD, 0), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ + +/* Config used for code execution */ +const struct flexspi_nor_config_t g_flash_fast_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = kFlexSPIReadSampleClk_ExternalInputFromDqsPad, + .csHoldTime = 1, + .csSetupTime = 1, + .deviceModeCfgEnable = 1, + .deviceModeType = kDeviceConfigCmdType_Spi2Xpi, + .waitTimeCfgCommands = 1, + .deviceModeSeq = { + .seqNum = 1, + .seqId = 6, /* See Lookup table for more details */ + .reserved = 0, + }, + .deviceModeArg = 2, /* Enable OPI DDR mode */ + .controllerMiscOption = + (1u << kFlexSpiMiscOffset_SafeConfigFreqEnable) + | (1u << kFlexSpiMiscOffset_DdrModeEnable), + .deviceType = kFlexSpiDeviceType_SerialNOR, + .sflashPadType = kSerialFlash_8Pads, + .serialClkFreq = kFlexSpiSerialClk_200MHz, + .sflashA1Size = 64ul * 1024u * 1024u, + .busyOffset = 0u, + .busyBitPolarity = 0u, + .lookupTable = { + /* Read */ + [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, + 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), + [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, + 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04), + [0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, + 0x04, STOP, FLEXSPI_1PAD, 0x00), + + /* Write enable SPI */ + [4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x06, STOP, FLEXSPI_1PAD, 0x00), + + /*Write Configuration Register 2 =01, Enable OPI DDR mode*/ + [4 * 6 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x72, CMD_SDR, FLEXSPI_1PAD, 0x00), + [4 * 6 + 1] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x00, CMD_SDR, FLEXSPI_1PAD, 0x00), + [4 * 6 + 2] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0x00, WRITE_SDR, FLEXSPI_1PAD, 0x01), + + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 64u * 1024u, + .isUniformBlockSize = false, + .ipcmdSerialClkFreq = 1, + .serialNorType = 2, + .reserve2[0] = 0x7008200, +}; + + +__ramfunc int imxrt_reclock_initialize(void) +{ + const uint32_t instance = 1; + + volatile struct flexspi_nor_config_t bootConfig; + + memcpy((struct flexspi_nor_config_t *)&bootConfig, &g_flash_fast_config, + sizeof(struct flexspi_nor_config_t)); + bootConfig.memConfig.tag = FLEXSPI_CFG_BLK_TAG; + + ROM_API_Init(); + + ROM_FLEXSPI_NorFlash_Init(instance, (struct flexspi_nor_config_t *)&bootConfig); + + return 0; +} + +SYS_INIT(imxrt_reclock_initialize, PRE_KERNEL_1, 0); diff --git a/boards/arm/vmu_rt1170/vmu_rt1170-pinctrl.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi similarity index 100% rename from boards/arm/vmu_rt1170/vmu_rt1170-pinctrl.dtsi rename to boards/nxp/vmu_rt1170/vmu_rt1170-pinctrl.dtsi diff --git a/boards/arm/vmu_rt1170/vmu_rt1170.dts b/boards/nxp/vmu_rt1170/vmu_rt1170.dts similarity index 100% rename from boards/arm/vmu_rt1170/vmu_rt1170.dts rename to boards/nxp/vmu_rt1170/vmu_rt1170.dts diff --git a/boards/arm/vmu_rt1170/vmu_rt1170.dtsi b/boards/nxp/vmu_rt1170/vmu_rt1170.dtsi similarity index 100% rename from boards/arm/vmu_rt1170/vmu_rt1170.dtsi rename to boards/nxp/vmu_rt1170/vmu_rt1170.dtsi diff --git a/boards/arm/vmu_rt1170/vmu_rt1170.yaml b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml similarity index 89% rename from boards/arm/vmu_rt1170/vmu_rt1170.yaml rename to boards/nxp/vmu_rt1170/vmu_rt1170.yaml index 2eb4ce0e5889e2..9446ece2d955a5 100644 --- a/boards/arm/vmu_rt1170/vmu_rt1170.yaml +++ b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -identifier: vmu_rt1170 +identifier: vmu_rt1170/mimxrt1176/cm7 name: NXP VMU RT1170 type: mcu arch: arm diff --git a/boards/arm/vmu_rt1170/vmu_rt1170_defconfig b/boards/nxp/vmu_rt1170/vmu_rt1170_defconfig similarity index 86% rename from boards/arm/vmu_rt1170/vmu_rt1170_defconfig rename to boards/nxp/vmu_rt1170/vmu_rt1170_defconfig index 875d84e7b64434..e6d72e55f463bc 100644 --- a/boards/arm/vmu_rt1170/vmu_rt1170_defconfig +++ b/boards/nxp/vmu_rt1170/vmu_rt1170_defconfig @@ -4,8 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1176_CM7=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_CONSOLE=y CONFIG_SHELL=y CONFIG_UART_CONSOLE=y diff --git a/boards/olimex/index.rst b/boards/olimex/index.rst new file mode 100644 index 00000000000000..17494488d61cf9 --- /dev/null +++ b/boards/olimex/index.rst @@ -0,0 +1,10 @@ +.. _boards-olimex: + +OLIMEX Ltd. +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit b/boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit new file mode 100644 index 00000000000000..f1c883d3577b67 --- /dev/null +++ b/boards/olimex/lora_stm32wl_devkit/Kconfig.olimex_lora_stm32wl_devkit @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Martin Jäger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_LORA_STM32WL_DEVKIT + select SOC_STM32WLE5XX diff --git a/boards/arm/olimex_lora_stm32wl_devkit/board.cmake b/boards/olimex/lora_stm32wl_devkit/board.cmake similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/board.cmake rename to boards/olimex/lora_stm32wl_devkit/board.cmake diff --git a/boards/olimex/lora_stm32wl_devkit/board.yml b/boards/olimex/lora_stm32wl_devkit/board.yml new file mode 100644 index 00000000000000..511de6634d2b36 --- /dev/null +++ b/boards/olimex/lora_stm32wl_devkit/board.yml @@ -0,0 +1,11 @@ +board: + name: olimex_lora_stm32wl_devkit + vendor: olimex + revision: + format: letter + default: "C" + revisions: + - name: "C" + - name: "D" + socs: + - name: stm32wle5xx diff --git a/boards/arm/olimex_lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg b/boards/olimex/lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg rename to boards/olimex/lora_stm32wl_devkit/doc/olimex-stm32wl-devkit.jpg diff --git a/boards/arm/olimex_lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst similarity index 95% rename from boards/arm/olimex_lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst rename to boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst index cd7d3436296d70..84e219fc1700df 100644 --- a/boards/arm/olimex_lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst +++ b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst @@ -81,10 +81,10 @@ hardware features: Other hardware features are not yet supported on this Zephyr port. -The default configuration can be found in the defconfig and dts files: +The default configuration can be found in: -- :zephyr_file:`boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig` -- :zephyr_file:`boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts` +- :zephyr_file:`boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig` +- :zephyr_file:`boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts` Programming and Debugging ************************* diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.conf diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.overlay diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.yaml b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.yaml rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.conf diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay similarity index 100% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.overlay diff --git a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml new file mode 100644 index 00000000000000..29559d1e262dd6 --- /dev/null +++ b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml @@ -0,0 +1,20 @@ +identifier: olimex_lora_stm32wl_devkit@D +name: Olimex LoRa STM32WL DevKit +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 64 +flash: 256 +supported: + - counter + - gpio + - i2c + - nvs + - spi + - uart + - watchdog + - lora +vendor: olimex diff --git a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig similarity index 83% rename from boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig rename to boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig index 5e6649fe25ac06..0d6dc9f80d3dd9 100644 --- a/boards/arm/olimex_lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig +++ b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WLE5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/olimex/olimex_esp32_evb/Kconfig b/boards/olimex/olimex_esp32_evb/Kconfig new file mode 100644 index 00000000000000..c13221afa37033 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_ESP32_EVB + select SOC_ESP32_PROCPU if BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU diff --git a/boards/olimex/olimex_esp32_evb/Kconfig.defconfig b/boards/olimex/olimex_esp32_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..c15264f5538df7 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Olimex ESP32-EVB board configuration + +# Copyright (c) 2022 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_OLIMEX_ESP32_EVB_ESP32_PROCPU + +if BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_OLIMEX_ESP32_EVB_ESP32_APPCPU diff --git a/boards/olimex/olimex_esp32_evb/Kconfig.olimex_esp32_evb b/boards/olimex/olimex_esp32_evb/Kconfig.olimex_esp32_evb new file mode 100644 index 00000000000000..850460473ae296 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/Kconfig.olimex_esp32_evb @@ -0,0 +1,7 @@ +# Olimex ESP32-EVB board configuration + +# Copyright (c) 2022 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_ESP32_EVB + select SOC_ESP32_WROVER_E_N8R2 diff --git a/boards/xtensa/odroid_go/Kconfig.sysbuild b/boards/olimex/olimex_esp32_evb/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/odroid_go/Kconfig.sysbuild rename to boards/olimex/olimex_esp32_evb/Kconfig.sysbuild diff --git a/boards/xtensa/m5stack_atoms3_lite/board.cmake b/boards/olimex/olimex_esp32_evb/board.cmake similarity index 100% rename from boards/xtensa/m5stack_atoms3_lite/board.cmake rename to boards/olimex/olimex_esp32_evb/board.cmake diff --git a/boards/olimex/olimex_esp32_evb/board.yml b/boards/olimex/olimex_esp32_evb/board.yml new file mode 100644 index 00000000000000..8dc816efceba10 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_esp32_evb + vendor: olimex + socs: + - name: esp32 diff --git a/boards/xtensa/olimex_esp32_evb/doc/ESP32-EVB.jpg b/boards/olimex/olimex_esp32_evb/doc/ESP32-EVB.jpg similarity index 100% rename from boards/xtensa/olimex_esp32_evb/doc/ESP32-EVB.jpg rename to boards/olimex/olimex_esp32_evb/doc/ESP32-EVB.jpg diff --git a/boards/olimex/olimex_esp32_evb/doc/index.rst b/boards/olimex/olimex_esp32_evb/doc/index.rst new file mode 100644 index 00000000000000..38df52c4920710 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/doc/index.rst @@ -0,0 +1,265 @@ +.. _olimex_esp32_evb: + +Olimex ESP32-EVB +################ + +Overview +******** + +The Olimex ESP32-EVB is an OSHW certified, open-source IoT board based on the +Espressif ESP32-WROOM-32E/UE module. It has a wired 100Mbit/s Ethernet Interface, +Bluetooth LE, WiFi, infrared remote control, and CAN connectivity. Two relays +allows switching power appliances on and off. + +The board can operate from a single LiPo backup battery as it has an internal +LiPo battery charger. There is no step-up converter, so relays, CAN, and USB +power does not work when running off battery. + +.. figure:: ESP32-EVB.jpg + :align: center + :alt: ESP32-EVB + + ESP32-EVB (Credit: Olimex) + +Hardware +******** + +- ESP32-WROOM-32E/UE module with 4MB flash. +- On-board programmer, CH340T USB-to-UART +- WiFi, Bluetooth LE connectivity. +- 100Mbit/s Ethernet interface, Microchip LAN8710A PHY. +- MicroSD card slot. +- 2 x 10A/250VAC (15A/120VAC 15A/24VDC) relays with connectors and status LEDs. +- CAN interface, Microchip MCP2562-E high-speed CAN transceiver. +- IR receiver and transmitter, up to 5 meters distance. +- BL4054B LiPo battery charger with status LEDs for stand-alone operation during + power outages. +- Power jack for external 5VDC power supply. +- Univeral EXTension (UEXT) connector for connecting UEXT modules. +- User push button. +- 40 pin GPIO connector with all ESP32 pins. + +For more information about the ESP32-EVB and the ESP32-WROOM-32E/UE module, see +these reference documents: + +- `ESP32-EVB Website`_ +- `ESP32-EVB Schematic`_ +- `ESP32-EVB GitHub Repository`_ +- `ESP32-WROOM32-E/UE Datasheet`_ + +Supported Features +****************** + +The olimex_esp32_evb board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| EFUSE | on-chip | hwinfo, device ID | ++-----------+------------+-------------------------------------+ +| FLASH | module | External flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | I2C | ++-----------+------------+-------------------------------------+ +| INTERRUPT | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| IO_MUX | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TIMG | on-chip | counter | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| TWAI | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | uart | ++-----------+------------+-------------------------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| WiFi | on-chip | WiFi | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig``. + +Other hardware features are not currently supported by the port. + +System requirements +******************* + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: olimex_esp32_evb + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``olimex_esp32_evb`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! olimex_esp32_evb + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: olimex_esp32_evb/esp32/procpu + :goals: debug + +References +********** + +.. _ESP32-EVB Website: + https://www.olimex.com/Products/IoT/ESP32/ESP32-EVB/open-source-hardware + +.. _ESP32-EVB Schematic: + https://github.com/OLIMEX/ESP32-EVB/raw/master/HARDWARE/REV-I/ESP32-EVB_Rev_I.pdf + +.. _ESP32-EVB GitHub Repository: + https://github.com/OLIMEX/ESP32-EVB + +.. _ESP32-WROOM32-E/UE Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32e_esp32-wroom-32ue_datasheet_en.pdf + +.. _OpenOCD ESP32: + https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi similarity index 100% rename from boards/xtensa/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi rename to boards/olimex/olimex_esp32_evb/olimex_esp32_evb-pinctrl.dtsi diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.dts new file mode 100644 index 00000000000000..c52b029ea552a3 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "Espressif ESP32-DevkitC APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.yaml b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.yaml new file mode 100644 index 00000000000000..9e81868de21810 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: olimex_esp32_evb/esp32/appcpu +name: Olimex ESP32-EVB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..6caadbd90ce687 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_appcpu_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y +CONFIG_CONSOLE=n +CONFIG_SERIAL=n +CONFIG_UART_CONSOLE=n +CONFIG_GPIO=n diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.dts similarity index 100% rename from boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.dts rename to boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.dts diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.yaml b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.yaml new file mode 100644 index 00000000000000..f4929c52b42043 --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu.yaml @@ -0,0 +1,20 @@ +identifier: olimex_esp32_evb/esp32/procpu +name: Olimex ESP32-EVB +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - can + - counter + - gpio + - hwinfo + - i2c + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: olimex diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig new file mode 100644 index 00000000000000..f029cac9e9e77b --- /dev/null +++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_esp32_procpu_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/olimex_esp32_evb/support/openocd.cfg b/boards/olimex/olimex_esp32_evb/support/openocd.cfg similarity index 100% rename from boards/xtensa/olimex_esp32_evb/support/openocd.cfg rename to boards/olimex/olimex_esp32_evb/support/openocd.cfg diff --git a/boards/olimex/olimexino_stm32/Kconfig.defconfig b/boards/olimex/olimexino_stm32/Kconfig.defconfig new file mode 100644 index 00000000000000..1f2ff6acf969df --- /dev/null +++ b/boards/olimex/olimexino_stm32/Kconfig.defconfig @@ -0,0 +1,12 @@ +# OLIMEXINO-STM32 board configuration + +# Copyright (c) 2016, I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_OLIMEXINO_STM32 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_OLIMEXINO_STM32 diff --git a/boards/olimex/olimexino_stm32/Kconfig.olimexino_stm32 b/boards/olimex/olimexino_stm32/Kconfig.olimexino_stm32 new file mode 100644 index 00000000000000..523f1c9902329e --- /dev/null +++ b/boards/olimex/olimexino_stm32/Kconfig.olimexino_stm32 @@ -0,0 +1,5 @@ +# Copyright (c) 2016, I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEXINO_STM32 + select SOC_STM32F103XB diff --git a/boards/arm/olimexino_stm32/board.cmake b/boards/olimex/olimexino_stm32/board.cmake similarity index 100% rename from boards/arm/olimexino_stm32/board.cmake rename to boards/olimex/olimexino_stm32/board.cmake diff --git a/boards/olimex/olimexino_stm32/board.yml b/boards/olimex/olimexino_stm32/board.yml new file mode 100644 index 00000000000000..0944c4bb280574 --- /dev/null +++ b/boards/olimex/olimexino_stm32/board.yml @@ -0,0 +1,5 @@ +board: + name: olimexino_stm32 + vendor: olimex + socs: + - name: stm32f103xb diff --git a/boards/arm/olimexino_stm32/doc/img/olimexino-stm32-front.jpg b/boards/olimex/olimexino_stm32/doc/img/olimexino-stm32-front.jpg similarity index 100% rename from boards/arm/olimexino_stm32/doc/img/olimexino-stm32-front.jpg rename to boards/olimex/olimexino_stm32/doc/img/olimexino-stm32-front.jpg diff --git a/boards/arm/olimexino_stm32/doc/img/olimexino_stm32.jpg b/boards/olimex/olimexino_stm32/doc/img/olimexino_stm32.jpg similarity index 100% rename from boards/arm/olimexino_stm32/doc/img/olimexino_stm32.jpg rename to boards/olimex/olimexino_stm32/doc/img/olimexino_stm32.jpg diff --git a/boards/arm/olimexino_stm32/doc/index.rst b/boards/olimex/olimexino_stm32/doc/index.rst similarity index 100% rename from boards/arm/olimexino_stm32/doc/index.rst rename to boards/olimex/olimexino_stm32/doc/index.rst diff --git a/boards/arm/olimexino_stm32/olimexino_stm32.dts b/boards/olimex/olimexino_stm32/olimexino_stm32.dts similarity index 100% rename from boards/arm/olimexino_stm32/olimexino_stm32.dts rename to boards/olimex/olimexino_stm32/olimexino_stm32.dts diff --git a/boards/arm/olimexino_stm32/olimexino_stm32.yaml b/boards/olimex/olimexino_stm32/olimexino_stm32.yaml similarity index 100% rename from boards/arm/olimexino_stm32/olimexino_stm32.yaml rename to boards/olimex/olimexino_stm32/olimexino_stm32.yaml diff --git a/boards/arm/olimexino_stm32/olimexino_stm32_defconfig b/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig similarity index 85% rename from boards/arm/olimexino_stm32/olimexino_stm32_defconfig rename to boards/olimex/olimexino_stm32/olimexino_stm32_defconfig index f8edab4b9803ff..9472e788675c1f 100644 --- a/boards/arm/olimexino_stm32/olimexino_stm32_defconfig +++ b/boards/olimex/olimexino_stm32/olimexino_stm32_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimexino_stm32/support/openocd.cfg b/boards/olimex/olimexino_stm32/support/openocd.cfg similarity index 100% rename from boards/arm/olimexino_stm32/support/openocd.cfg rename to boards/olimex/olimexino_stm32/support/openocd.cfg diff --git a/boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 b/boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 new file mode 100644 index 00000000000000..0272cc31f5b8b6 --- /dev/null +++ b/boards/olimex/stm32_e407/Kconfig.olimex_stm32_e407 @@ -0,0 +1,5 @@ +# Copyright (c) 2017, Erwin Rol +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_E407 + select SOC_STM32F407XG diff --git a/boards/arm/black_f407zg_pro/board.cmake b/boards/olimex/stm32_e407/board.cmake similarity index 100% rename from boards/arm/black_f407zg_pro/board.cmake rename to boards/olimex/stm32_e407/board.cmake diff --git a/boards/olimex/stm32_e407/board.yml b/boards/olimex/stm32_e407/board.yml new file mode 100644 index 00000000000000..b01060566dc4fd --- /dev/null +++ b/boards/olimex/stm32_e407/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_e407 + vendor: olimex + socs: + - name: stm32f407xx diff --git a/boards/arm/olimex_stm32_e407/doc/img/olimex-stm32-e407-front.jpg b/boards/olimex/stm32_e407/doc/img/olimex-stm32-e407-front.jpg similarity index 100% rename from boards/arm/olimex_stm32_e407/doc/img/olimex-stm32-e407-front.jpg rename to boards/olimex/stm32_e407/doc/img/olimex-stm32-e407-front.jpg diff --git a/boards/arm/olimex_stm32_e407/doc/img/olimex_stm32_e407.jpg b/boards/olimex/stm32_e407/doc/img/olimex_stm32_e407.jpg similarity index 100% rename from boards/arm/olimex_stm32_e407/doc/img/olimex_stm32_e407.jpg rename to boards/olimex/stm32_e407/doc/img/olimex_stm32_e407.jpg diff --git a/boards/arm/olimex_stm32_e407/doc/index.rst b/boards/olimex/stm32_e407/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_e407/doc/index.rst rename to boards/olimex/stm32_e407/doc/index.rst diff --git a/boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts b/boards/olimex/stm32_e407/olimex_stm32_e407.dts similarity index 100% rename from boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts rename to boards/olimex/stm32_e407/olimex_stm32_e407.dts diff --git a/boards/arm/olimex_stm32_e407/olimex_stm32_e407.yaml b/boards/olimex/stm32_e407/olimex_stm32_e407.yaml similarity index 100% rename from boards/arm/olimex_stm32_e407/olimex_stm32_e407.yaml rename to boards/olimex/stm32_e407/olimex_stm32_e407.yaml diff --git a/boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig b/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig similarity index 84% rename from boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig rename to boards/olimex/stm32_e407/olimex_stm32_e407_defconfig index ad325266c72c97..c729b83e3d0506 100644 --- a/boards/arm/olimex_stm32_e407/olimex_stm32_e407_defconfig +++ b/boards/olimex/stm32_e407/olimex_stm32_e407_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_e407/support/openocd.cfg b/boards/olimex/stm32_e407/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_e407/support/openocd.cfg rename to boards/olimex/stm32_e407/support/openocd.cfg diff --git a/boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 b/boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 new file mode 100644 index 00000000000000..d88ee02890ab5a --- /dev/null +++ b/boards/olimex/stm32_h103/Kconfig.olimex_stm32_h103 @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Josep Puigdemont +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_H103 + select SOC_STM32F103XB diff --git a/boards/arm/olimex_stm32_h103/board.cmake b/boards/olimex/stm32_h103/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_h103/board.cmake rename to boards/olimex/stm32_h103/board.cmake diff --git a/boards/olimex/stm32_h103/board.yml b/boards/olimex/stm32_h103/board.yml new file mode 100644 index 00000000000000..2917e4e19d9691 --- /dev/null +++ b/boards/olimex/stm32_h103/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_h103 + vendor: olimex + socs: + - name: stm32f103xb diff --git a/boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg b/boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg similarity index 100% rename from boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg rename to boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_bottom.jpg diff --git a/boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_top.jpg b/boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_top.jpg similarity index 100% rename from boards/arm/olimex_stm32_h103/doc/img/olimex_stm32_h103_top.jpg rename to boards/olimex/stm32_h103/doc/img/olimex_stm32_h103_top.jpg diff --git a/boards/arm/olimex_stm32_h103/doc/index.rst b/boards/olimex/stm32_h103/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_h103/doc/index.rst rename to boards/olimex/stm32_h103/doc/index.rst diff --git a/boards/arm/olimex_stm32_h103/olimex_stm32_h103.dts b/boards/olimex/stm32_h103/olimex_stm32_h103.dts similarity index 100% rename from boards/arm/olimex_stm32_h103/olimex_stm32_h103.dts rename to boards/olimex/stm32_h103/olimex_stm32_h103.dts diff --git a/boards/arm/olimex_stm32_h103/olimex_stm32_h103.yaml b/boards/olimex/stm32_h103/olimex_stm32_h103.yaml similarity index 100% rename from boards/arm/olimex_stm32_h103/olimex_stm32_h103.yaml rename to boards/olimex/stm32_h103/olimex_stm32_h103.yaml diff --git a/boards/arm/olimex_stm32_h103/olimex_stm32_h103_defconfig b/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig similarity index 81% rename from boards/arm/olimex_stm32_h103/olimex_stm32_h103_defconfig rename to boards/olimex/stm32_h103/olimex_stm32_h103_defconfig index 7dc8d8f3b6fc07..9fd4400ac206eb 100644 --- a/boards/arm/olimex_stm32_h103/olimex_stm32_h103_defconfig +++ b/boards/olimex/stm32_h103/olimex_stm32_h103_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XB=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/arm/olimex_stm32_h103/support/openocd.cfg b/boards/olimex/stm32_h103/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_h103/support/openocd.cfg rename to boards/olimex/stm32_h103/support/openocd.cfg diff --git a/boards/arm/olimex_stm32_h103/support/openocd_olimex_jtag.cfg b/boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg similarity index 100% rename from boards/arm/olimex_stm32_h103/support/openocd_olimex_jtag.cfg rename to boards/olimex/stm32_h103/support/openocd_olimex_jtag.cfg diff --git a/boards/arm/olimex_stm32_h103/support/openocd_stlink.cfg b/boards/olimex/stm32_h103/support/openocd_stlink.cfg similarity index 100% rename from boards/arm/olimex_stm32_h103/support/openocd_stlink.cfg rename to boards/olimex/stm32_h103/support/openocd_stlink.cfg diff --git a/boards/olimex/stm32_h405/Kconfig.olimex_stm32_h405 b/boards/olimex/stm32_h405/Kconfig.olimex_stm32_h405 new file mode 100644 index 00000000000000..e6797add494bd7 --- /dev/null +++ b/boards/olimex/stm32_h405/Kconfig.olimex_stm32_h405 @@ -0,0 +1,5 @@ +# Copyright (c) 2020, 2021 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_H405 + select SOC_STM32F405XX diff --git a/boards/arm/olimex_stm32_h405/board.cmake b/boards/olimex/stm32_h405/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_h405/board.cmake rename to boards/olimex/stm32_h405/board.cmake diff --git a/boards/olimex/stm32_h405/board.yml b/boards/olimex/stm32_h405/board.yml new file mode 100644 index 00000000000000..bd0e8f4beaa97e --- /dev/null +++ b/boards/olimex/stm32_h405/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_h405 + vendor: olimex + socs: + - name: stm32f405xx diff --git a/boards/arm/olimex_stm32_h405/doc/index.rst b/boards/olimex/stm32_h405/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_h405/doc/index.rst rename to boards/olimex/stm32_h405/doc/index.rst diff --git a/boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_bottom.jpg b/boards/olimex/stm32_h405/doc/olimex_stm32_h405_bottom.jpg similarity index 100% rename from boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_bottom.jpg rename to boards/olimex/stm32_h405/doc/olimex_stm32_h405_bottom.jpg diff --git a/boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_top.jpg b/boards/olimex/stm32_h405/doc/olimex_stm32_h405_top.jpg similarity index 100% rename from boards/arm/olimex_stm32_h405/doc/olimex_stm32_h405_top.jpg rename to boards/olimex/stm32_h405/doc/olimex_stm32_h405_top.jpg diff --git a/boards/arm/olimex_stm32_h405/olimex_stm32_h405.dts b/boards/olimex/stm32_h405/olimex_stm32_h405.dts similarity index 100% rename from boards/arm/olimex_stm32_h405/olimex_stm32_h405.dts rename to boards/olimex/stm32_h405/olimex_stm32_h405.dts diff --git a/boards/arm/olimex_stm32_h405/olimex_stm32_h405.yaml b/boards/olimex/stm32_h405/olimex_stm32_h405.yaml similarity index 100% rename from boards/arm/olimex_stm32_h405/olimex_stm32_h405.yaml rename to boards/olimex/stm32_h405/olimex_stm32_h405.yaml diff --git a/boards/arm/olimex_stm32_h405/olimex_stm32_h405_defconfig b/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig similarity index 84% rename from boards/arm/olimex_stm32_h405/olimex_stm32_h405_defconfig rename to boards/olimex/stm32_h405/olimex_stm32_h405_defconfig index ca015a21976c5a..c729b83e3d0506 100644 --- a/boards/arm/olimex_stm32_h405/olimex_stm32_h405_defconfig +++ b/boards/olimex/stm32_h405/olimex_stm32_h405_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F405XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_h405/support/openocd.cfg b/boards/olimex/stm32_h405/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_h405/support/openocd.cfg rename to boards/olimex/stm32_h405/support/openocd.cfg diff --git a/boards/olimex/stm32_h407/Kconfig.olimex_stm32_h407 b/boards/olimex/stm32_h407/Kconfig.olimex_stm32_h407 new file mode 100644 index 00000000000000..12c963662729ec --- /dev/null +++ b/boards/olimex/stm32_h407/Kconfig.olimex_stm32_h407 @@ -0,0 +1,5 @@ +# Copyright (c) 2018, Reto Schneider +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_H407 + select SOC_STM32F407XG diff --git a/boards/arm/olimex_stm32_e407/board.cmake b/boards/olimex/stm32_h407/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_e407/board.cmake rename to boards/olimex/stm32_h407/board.cmake diff --git a/boards/olimex/stm32_h407/board.yml b/boards/olimex/stm32_h407/board.yml new file mode 100644 index 00000000000000..5d2f0d7a78370d --- /dev/null +++ b/boards/olimex/stm32_h407/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_h407 + vendor: olimex + socs: + - name: stm32f407xx diff --git a/boards/arm/olimex_stm32_h407/doc/img/olimex-stm32-h407-front.jpg b/boards/olimex/stm32_h407/doc/img/olimex-stm32-h407-front.jpg similarity index 100% rename from boards/arm/olimex_stm32_h407/doc/img/olimex-stm32-h407-front.jpg rename to boards/olimex/stm32_h407/doc/img/olimex-stm32-h407-front.jpg diff --git a/boards/arm/olimex_stm32_h407/doc/img/olimex_stm32_h407.jpg b/boards/olimex/stm32_h407/doc/img/olimex_stm32_h407.jpg similarity index 100% rename from boards/arm/olimex_stm32_h407/doc/img/olimex_stm32_h407.jpg rename to boards/olimex/stm32_h407/doc/img/olimex_stm32_h407.jpg diff --git a/boards/arm/olimex_stm32_h407/doc/index.rst b/boards/olimex/stm32_h407/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_h407/doc/index.rst rename to boards/olimex/stm32_h407/doc/index.rst diff --git a/boards/arm/olimex_stm32_h407/olimex_stm32_h407.dts b/boards/olimex/stm32_h407/olimex_stm32_h407.dts similarity index 100% rename from boards/arm/olimex_stm32_h407/olimex_stm32_h407.dts rename to boards/olimex/stm32_h407/olimex_stm32_h407.dts diff --git a/boards/arm/olimex_stm32_h407/olimex_stm32_h407.yaml b/boards/olimex/stm32_h407/olimex_stm32_h407.yaml similarity index 100% rename from boards/arm/olimex_stm32_h407/olimex_stm32_h407.yaml rename to boards/olimex/stm32_h407/olimex_stm32_h407.yaml diff --git a/boards/arm/olimex_stm32_h407/olimex_stm32_h407_defconfig b/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig similarity index 84% rename from boards/arm/olimex_stm32_h407/olimex_stm32_h407_defconfig rename to boards/olimex/stm32_h407/olimex_stm32_h407_defconfig index ad325266c72c97..c729b83e3d0506 100644 --- a/boards/arm/olimex_stm32_h407/olimex_stm32_h407_defconfig +++ b/boards/olimex/stm32_h407/olimex_stm32_h407_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_h407/support/openocd.cfg b/boards/olimex/stm32_h407/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_h407/support/openocd.cfg rename to boards/olimex/stm32_h407/support/openocd.cfg diff --git a/boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 b/boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 new file mode 100644 index 00000000000000..7c61fe39272185 --- /dev/null +++ b/boards/olimex/stm32_p405/Kconfig.olimex_stm32_p405 @@ -0,0 +1,5 @@ +# Copyright (c) 2017, Erwin Rol +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_OLIMEX_STM32_P405 + select SOC_STM32F405XX diff --git a/boards/arm/olimex_stm32_p405/board.cmake b/boards/olimex/stm32_p405/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_p405/board.cmake rename to boards/olimex/stm32_p405/board.cmake diff --git a/boards/olimex/stm32_p405/board.yml b/boards/olimex/stm32_p405/board.yml new file mode 100644 index 00000000000000..12201ed22c9b49 --- /dev/null +++ b/boards/olimex/stm32_p405/board.yml @@ -0,0 +1,5 @@ +board: + name: olimex_stm32_p405 + vendor: olimex + socs: + - name: stm32f405xx diff --git a/boards/arm/olimex_stm32_p405/doc/img/olimex-stm32-p405-front.jpg b/boards/olimex/stm32_p405/doc/img/olimex-stm32-p405-front.jpg similarity index 100% rename from boards/arm/olimex_stm32_p405/doc/img/olimex-stm32-p405-front.jpg rename to boards/olimex/stm32_p405/doc/img/olimex-stm32-p405-front.jpg diff --git a/boards/arm/olimex_stm32_p405/doc/img/olimex_stm32_p405.jpg b/boards/olimex/stm32_p405/doc/img/olimex_stm32_p405.jpg similarity index 100% rename from boards/arm/olimex_stm32_p405/doc/img/olimex_stm32_p405.jpg rename to boards/olimex/stm32_p405/doc/img/olimex_stm32_p405.jpg diff --git a/boards/arm/olimex_stm32_p405/doc/index.rst b/boards/olimex/stm32_p405/doc/index.rst similarity index 100% rename from boards/arm/olimex_stm32_p405/doc/index.rst rename to boards/olimex/stm32_p405/doc/index.rst diff --git a/boards/arm/olimex_stm32_p405/olimex_stm32_p405.dts b/boards/olimex/stm32_p405/olimex_stm32_p405.dts similarity index 100% rename from boards/arm/olimex_stm32_p405/olimex_stm32_p405.dts rename to boards/olimex/stm32_p405/olimex_stm32_p405.dts diff --git a/boards/arm/olimex_stm32_p405/olimex_stm32_p405.yaml b/boards/olimex/stm32_p405/olimex_stm32_p405.yaml similarity index 100% rename from boards/arm/olimex_stm32_p405/olimex_stm32_p405.yaml rename to boards/olimex/stm32_p405/olimex_stm32_p405.yaml diff --git a/boards/arm/olimex_stm32_p405/olimex_stm32_p405_defconfig b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig similarity index 85% rename from boards/arm/olimex_stm32_p405/olimex_stm32_p405_defconfig rename to boards/olimex/stm32_p405/olimex_stm32_p405_defconfig index 18d48f08e1a5c4..758675b14ba443 100644 --- a/boards/arm/olimex_stm32_p405/olimex_stm32_p405_defconfig +++ b/boards/olimex/stm32_p405/olimex_stm32_p405_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F405XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_p405/support/openocd.cfg b/boards/olimex/stm32_p405/support/openocd.cfg similarity index 100% rename from boards/arm/olimex_stm32_p405/support/openocd.cfg rename to boards/olimex/stm32_p405/support/openocd.cfg diff --git a/boards/openisa/index.rst b/boards/openisa/index.rst new file mode 100644 index 00000000000000..d1a8c33af06124 --- /dev/null +++ b/boards/openisa/index.rst @@ -0,0 +1,10 @@ +.. _boards-openisa: + +OpenISA +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/openisa/rv32m1_vega/Kconfig.defconfig b/boards/openisa/rv32m1_vega/Kconfig.defconfig new file mode 100644 index 00000000000000..08279d8ed04304 --- /dev/null +++ b/boards/openisa/rv32m1_vega/Kconfig.defconfig @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2018 Foundries.io Ltd + +if BOARD_RV32M1_VEGA + +if BT + +config BT_CTLR + default y + +#TODO: Resolve the complete non-BLE support for crypto CAU3 firmware/driver +#config HAS_RV32M1_CAU3 +# bool +# default y if BT_CTLR_CRYPTO && !BT_CTLR_LE_ENC_SUPPORT + +config HAS_RV32M1_CAU3_BLE + bool + default y if BT_CTLR_CRYPTO && \ + (BT_CTLR_LE_ENC_SUPPORT || BT_CTLR_PRIVACY_SUPPORT) + +config RV32M1_INTMUX_CHANNEL_2 + default n + +config RV32M1_INTMUX_CHANNEL_3 + default n + +endif # BT + +endif # BOARD_RV32M1_VEGA diff --git a/boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega b/boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega new file mode 100644 index 00000000000000..40134c6f4422b2 --- /dev/null +++ b/boards/openisa/rv32m1_vega/Kconfig.rv32m1_vega @@ -0,0 +1,6 @@ +# Copyright 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RV32M1_VEGA + select SOC_OPENISA_RV32M1_RI5CY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_RI5CY + select SOC_OPENISA_RV32M1_ZERO_RISCY if BOARD_RV32M1_VEGA_OPENISA_RV32M1_ZERO_RISCY diff --git a/boards/openisa/rv32m1_vega/board.cmake b/boards/openisa/rv32m1_vega/board.cmake new file mode 100644 index 00000000000000..8bc69de47a52e5 --- /dev/null +++ b/boards/openisa/rv32m1_vega/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2018 Foundries.io Ltd + +set(OPENOCD_USE_LOAD_IMAGE NO) + +if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg") +elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/openisa/rv32m1_vega/board.yml b/boards/openisa/rv32m1_vega/board.yml new file mode 100644 index 00000000000000..5813a21b54f209 --- /dev/null +++ b/boards/openisa/rv32m1_vega/board.yml @@ -0,0 +1,5 @@ +board: + name: rv32m1_vega + vendor: openisa + socs: + - name: openisa_rv32m1 diff --git a/boards/openisa/rv32m1_vega/doc/index.rst b/boards/openisa/rv32m1_vega/doc/index.rst new file mode 100644 index 00000000000000..339b8dc5e0ccd4 --- /dev/null +++ b/boards/openisa/rv32m1_vega/doc/index.rst @@ -0,0 +1,841 @@ +.. highlight:: sh + +.. _rv32m1_vega: + +OpenISA VEGAboard +################# + +Overview +******** + +The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs, +on-die XIP flash, and a full complement of peripherals, including a +2.4 GHz multi-protocol radio. It also has built-in sensors and +Arduino-style expansion connectors. + +.. figure:: rv32m1_vega.jpg + :align: center + :alt: RV32M1-VEGA + + OpenISA VEGAboard (image copyright: www.open-isa.org) + +The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are +respectively based on the `PULP platform`_ designs by the same names: +`RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more +flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a +"secondary" core. The main ZERO-RISCY use-case is as a wireless +coprocessor for applications running on RI5CY. The two cores can +communicate via shared memory and messaging peripherals. + +Currently, Zephyr supports RI5CY with the ``rv32m1_vega/openisa_rv32m1/ri5cy`` board +configuration name, and ZERO_RISCY with the ``rv32m1_vega/openisa_rv32m1/zero_riscy`` board +configuration name. + +Hardware +******** + +The VEGAboard includes the following features. + +RV32M1 multi-core SoC: + +- 1 MiB flash and 192 KiB SRAM (RI5CY core) +- 256 KiB flash and 128 KiB SRAM (ZERO-RISCY core) +- Low power modes +- DMA support +- Watchdog, CRC, cryptographic acceleration, ADC, DAC, comparator, + timers, PWM, RTC, I2C, UART, SPI, external memory, I2S, smart + card, USB full-speed, uSDHC, and 2.4 GHz multiprotocol radio + peripherals + +On-board sensors and peripherals: + +- 32 Mbit SPI flash +- 6-axis accelerometer, magnetometer, and temperature sensor (FXOS8700) +- Ambient light sensor +- RGB LED +- microSD card slot +- Antenna interface + +Additional features: + +- Form-factor compatible with Arduino Uno Rev 3 expansion connector + layout (not all Arduino shields may be pin-compatible) +- UART via USB using separate OpenSDA chip +- RISC-V flash and debug using external JTAG dongle (not included) via + 2x5 5 mil pitch connector (commonly called the "ARM 10-pin JTAG" + connector) + +Supported Features +================== + +Zephyr's RI5CY configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``, currently supports +the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| EVENT | on-chip | event unit interrupt controller | ++-----------+------------+-------------------------------------+ +| INTMUX | on-chip | level 2 interrupt controller | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | lptmr-based system timer | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | ++-----------+------------+-------------------------------------+ + +Zephyr's ZERO-RISCY configuration, ``rv32m1_vega/openisa_rv32m1/zero_riscy``, currently +supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| EVENT | on-chip | event unit interrupt controller | ++-----------+------------+-------------------------------------+ +| INTMUX | on-chip | level 2 interrupt controller | ++-----------+------------+-------------------------------------+ +| LPTMR | on-chip | lptmr-based system timer | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| TPM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SENSOR | off-chip | fxos8700 polling; | +| | | fxos8700 trigger; | ++-----------+------------+-------------------------------------+ + +BLE Software Link Layer experimental support +================================================== +This is an experimental feature supported on the Zephyr's RI5CY +configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``. It uses the Software Link Layer +framework by Nordic Semi to enable the on-SoC radio and transceiver for +implementing a software defined BLE controller. By using both the controller +and the host stack available in Zephyr, the following BLE samples can be used +with this board: + +- beacon +- central +- central_hr +- eddystone +- hci_uart +- ibeacon +- peripheral_csc (Cycling Speed Cadence) +- peripheral_dis (Device Information Service) +- peripheral_esp (Environmental Sensing Service) +- peripheral_hr (Heart Rate) +- peripheral_ht (Health Thermometer) +- peripheral +- scan_adv + +.. note:: + + BLE Software Link Layer limitations: + + - no 512/256 Kbps PHY + - no TX power adjustment + + +Connections and IOs +=================== + +RV32M1 SoC pins are brought out to Arduino-style expansion connectors. +These are 2 pins wide each, adding an additional row of expansion pins +per header compared to the standard Arduino layout. + +They are described in the tables in the following subsections. Since +pins are usually grouped by logical function in rows on these headers, +the odd- and even-numbered pins are listed in separate tables. The +"Port/bit" columns refer to the SoC PORT and GPIO peripheral +naming scheme, e.g. "E/13" means PORTE/GPIOE pin 13. + +See the schematic and chip reference manual for details. +(Documentation is available from the `OpenISA GitHub releases`_ page.) + +.. note:: + + Pins with peripheral functionality may also be muxed as GPIOs. + +**Top right expansion header (J1)** + +Odd/bottom pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +1 E/13 I2S_TX_BCLK +3 E/14 I2S_TX_FS +5 E/15 I2S_TXD +7 E/19 I2S_MCLK +9 E/16 I2S_RX_BCLK +11 E/21 SOF_OUT +13 E/17 I2S_RX_FS +15 E/18 I2S_RXD +=== ======== ================= + +Even/top pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +2 A/25 UART1_RX +4 A/26 UART1_TX +6 A/27 GPIO +8 B/13 PWM +10 B/14 GPIO +12 A/30 PWM +14 A/31 PWM/CMP +16 B/1 GPIO +=== ======== ================= + +**Top left expansion header (J2)** + +Odd/bottom pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +1 D/5 FLEXIO_D25 +3 D/4 FLEXIO_D24 +5 D/3 FLEXIO_D23 +7 D/2 FLEXIO_D22 +9 D/1 FLEXIO_D21 +11 D/0 FLEXIO_D20 +13 C/30 FLEXIO_D19 +15 C/29 FLEXIO_D18 +17 C/28 FLEXIO_D17 +19 B/29 FLEXIO_D16 +=== ======== ================= + +Even/top pins: + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +2 B/2 GPIO +4 B/3 PWM +6 B/6 SPI0_PCS2 +8 B/5 SPI0_SOUT +10 B/7 SPI0_SIN +12 B/4 SPI0_SCK +14 - GND +16 - AREF +18 C/9 I2C0_SDA +20 C/10 I2C0_SCL +=== ======== ================= + +**Bottom left expansion header (J3)** + +Note that the headers at the bottom of the board have odd-numbered +pins on the top, unlike the headers at the top of the board. + +Odd/top pins: + +=== ======== ==================== +Pin Port/bit Function +=== ======== ==================== +1 A/21 ARDUINO_EMVSIM_PD +3 A/20 ARDUINO_EMVSIM_IO +5 A/19 ARDUINO_EMVSIM_VCCEN +7 A/18 ARDUINO_EMVSIM_RST +9 A/17 ARDUINO_EMVSIM_CLK +11 B/17 FLEXIO_D7 +13 B/16 FLEXIO_D6 +15 B/15 FLEXIO_D5 +=== ======== ==================== + +Even/bottom pins: note that these are mostly power-related. + +=== ======== ================= +Pin Port/bit Function +=== ======== ================= +2 - SDA_GPIO0 +4 - BRD_IO_PER +6 - RST_SDA +8 - BRD_IO_PER +10 - P5V_INPUT +12 - GND +14 - GND +16 - P5-9V VIN +=== ======== ================= + +**Bottom right expansion header (J4)** + +Note that the headers at the bottom of the board have odd-numbered +pins on the top, unlike the headers at the top of the board. + +Odd/top pins: + +=== ======== ======================================== +Pin Port/bit Function +=== ======== ======================================== +1 - TAMPER2 +3 - TAMPER1/RTC_CLKOUT +5 - TAMPER0/RTC_WAKEUP_b +7 E/2 ADC0_SE19 +9 E/5 LPCMP1_IN2/LPCMP1_OUT +11 - DAC0_OUT/ADC0_SE16/LPCMP0_IN3/LPCMP1_IN3 +=== ======== ======================================== + +Even/bottom pins: + +=== ======== =========================================== +Pin Port/bit Function +=== ======== =========================================== +2 C/11 ADC0_SE6 +4 C/12 ADC0_SE7 +6 B/9 ADC0_SE3 +8 E/4 ADC0_SE21 +10 E/10 ADC0_SE19 (and E/10, I2C3_SDA via 0 Ohm DNP) +12 E/11 ADC0_SE20 (and E/11, I2C3_SCL via 0 Ohm DNP) +=== ======== =========================================== + +Additional Pins +--------------- + +For an up-to-date description of additional pins (such as buttons, +LEDs, etc.) supported by Zephyr, see the board DTS files in the Zephyr +source code, i.e. +:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts` for RI5CY and +:zephyr_file:`boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts` for +ZERO-RISCY. + +See the schematic in the documentation available from the `OpenISA +GitHub releases`_ page for additional details. + +System Clocks +============= + +The RI5CY and ZERO-RISCY cores are configured to use the slow internal +reference clock (SIRC) as the clock source for an LPTMR peripheral to manage +the system timer, and the fast internal reference clock (FIRC) to generate a +48MHz core clock. + +Serial Port +=========== + +The USB connector at the top left of the board (near the RESET button) is +connected to an OpenSDA chip which provides a serial USB device. This is +connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by +default for console and logging. + +.. warning:: + + The OpenSDA chip cannot be used to flash or debug the RISC-V cores. + + See the next section for flash and debug instructions for the + RISC-V cores using an external JTAG dongle. + +Programming and Debugging +************************* + +.. _rv32m1-programming-hw: + +.. important:: + + To use this board, you will need: + + - a `SEGGER J-Link`_ debug probe to debug the RISC-V cores + - a J-Link `9-Pin Cortex-M Adapter`_ board and ribbon cable + - the SEGGER `J-Link Software and Documentation Pack`_ software + installed + + A JTAG dongle is not included with the board itself. + +Follow these steps to: + +#. Get a toolchain and OpenOCD +#. Set up the board for booting RI5CY +#. Compile a Zephyr application for the RI5CY core +#. Flash the application to your board +#. Debug the board using GDB + +.. _rv32m1-toolchain-openocd: + +Get the Toolchain and OpenOCD +============================= + +Before programming and debugging, you first need to get a GNU +toolchain and an OpenOCD build. There are vendor-specific versions of +each for the RV32M1 SoC\ [#toolchain_openocd]_. + +Option 1 (Recommended): Prebuilt Toolchain and OpenOCD +------------------------------------------------------ + +The following prebuilt toolchains and OpenOCD archives are available +on the `OpenISA GitHub releases`_ page: + +- :file:`Toolchain_Linux.tar.gz` +- :file:`Toolchain_Mac.tar.gz` +- :file:`Toolchain_Windows.zip` + +Download and extract the archive for your system, then extract the +toolchain and OpenOCD archives inside. + +Linux:: + + tar xvzf Toolchain_Linux.tar.gz + tar xvzf openocd.tar.gz + tar xvzf riscv32-unknown-elf-gcc.tar.gz + mv openocd ~/rv32m1-openocd + mv riscv32-unknown-elf-gcc ~ + +macOS (unfortunately, the OpenISA 1.0.0 release's Mac +:file:`riscv32-unknown-elf-gcc.tar.gz` file doesn't expand into a +:file:`riscv32-unknown-elf-gcc` directory, so it has to be created):: + + tar xvzf Toolchain_Mac.tar.gz + tar xvzf openocd.tar.gz + mkdir riscv32-unknown-elf-gcc + mv riscv32-unknown-elf-gcc.tar.gz riscv32-unknown-elf-gcc + cd riscv32-unknown-elf-gcc/ + tar xvzf riscv32-unknown-elf-gcc.tar.gz + cd .. + mv openocd ~/rv32m1-openocd + mv riscv32-unknown-elf-gcc ~ + +Windows: + +#. Extract :file:`Toolchain_Windows.zip` in the file manager +#. Extract the :file:`openocd.zip` and :file:`riscv32-unknown-elf-gcc.zip` files + in the resulting :file:`Toolchain_Windows` folder +#. Move the extracted :file:`openocd` folder to :file:`C:\\rv32m1-openocd` +#. Move the extracted :file:`riscv32-unknown-elf-gcc` folder to + :file:`C:\\riscv32-unknown-elf-gcc` + +For simplicity, this guide assumes: + +- You put the extracted toolchain at :file:`~/riscv32-unknown-elf-gcc` + on macOS or Linux, and :file:`C:\\riscv32-unknown-elf-gcc` on + Windows. +- You put the extracted OpenOCD binary at :file:`~/rv32m1-openocd` on + macOS or Linux, and the OpenOCD folder into :file:`C:\\rv32m1-openocd` + on Windows. + +You can put them elsewhere, but be aware: + +- If you put the toolchain somewhere else, you will need to change + the ``CROSS_COMPILE`` value described below accordingly. +- If you put OpenOCD somewhere else, you will need to change the + OpenOCD path in the flashing and debugging instructions below. +- Don't use installation directories with spaces anywhere in the path; + this won't work with Zephyr's build system. + +Option 2: Building Toolchain and OpenOCD From Source +---------------------------------------------------- + +See :ref:`rv32m1_vega_toolchain_build`. + +.. _rv32m1-vega-jtag: + +JTAG Setup +========== + +This section describes how to connect to your board via the J-Link +debugger and adapter board. See the :ref:`above information +` for details on required hardware. + +#. Connect the J-Link debugger through the adapter board to the + VEGAboard as shown in the figure. + + .. figure:: rv32m1_vega_jtag.jpg + :align: center + :alt: RV32M1-VEGA + + VEGAboard connected properly to J-Link debugger. + VEGAboard connector J55 should be used. Pin 1 is on the bottom left. + +#. Power the VEGAboard via USB. The OpenSDA connector at the top left + is recommended for UART access. + +#. Make sure your J-Link is connected to your computer via USB. + +One-Time Board Setup For Booting RI5CY or ZERO-RISCY +==================================================== + +Next, you'll need to make sure your board boots the RI5CY or ZERO-RISCY core. +**You only need to do this once.** + +The RV32M1 SoC on the VEGAboard has multiple cores, any of which can +be selected as the boot core. Before flashing and debugging, you'll +first make sure you're booting the right core. + +**Linux and macOS**: + +.. note:: + + Linux users: to run these commands as a normal user, you will need + to install the `60-openocd.rules`_ udev rules file (usually by + placing it in :file:`/etc/udev/rules.d`, then unplugging and + plugging the J-Link in again via USB). + +.. note:: + + These Zephyr-specific instructions differ slightly from the + equivalent SDK ones. The Zephyr OpenOCD configuration file does not + run ``init``, so you have to do it yourself as explained below. + +1. In one terminal, use OpenOCD to connect to the board:: + + ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg + + The output should look like this: + + .. code-block:: console + + $ ~/rv32m1-openocd -f boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg + Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29) + [...] + Info : Listening on port 3333 for gdb connections + Info : Listening on port 6666 for tcl connections + Info : Listening on port 4444 for telnet connections + +2. In another terminal, connect to OpenOCD's telnet server and execute + the ``init`` and ``ri5cy_boot`` commands **with the reset button on + the board (at top left) pressed down**:: + + $ telnet localhost 4444 + Trying 127.0.0.1... + Connected to localhost. + Escape character is '^]'. + Open On-Chip Debugger + > init + > ri5cy_boot + + To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with + ``zero_boot``. + + The reset button is at top left, as shown in the following figure. + + .. figure:: ri5cy_boot.jpg + :align: center + :alt: Reset button is pressed + + Now quit the telnet session in this terminal and exit OpenOCD in the + other terminal. + +3. Unplug your J-Link and VEGAboard, and plug them back in. + +**Windows**: + +In one cmd.exe prompt in the Zephyr directory:: + + C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\openisa\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg + +In a telnet program of your choice: + +#. Connect to localhost port 4444 using telnet. +#. Run ``init`` and ``ri5cy_boot`` as shown above, with RESET held down. +#. Quit the OpenOCD and telnet sessions. +#. Unplug your J-Link and VEGAboard, and plug them back in. + + To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with + ``zero_boot``. + +Compiling a Program +=================== + +.. important:: + + These instructions assume you've set up a development system, + cloned the Zephyr repository, and installed Python dependencies as + described in the :ref:`getting_started`. + + You should also have already downloaded and installed the toolchain + and OpenOCD as described above in :ref:`rv32m1-toolchain-openocd`. + +The first step is to set up environment variables to point at your +toolchain and OpenOCD:: + + # Linux or macOS + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + export CROSS_COMPILE=~/riscv32-unknown-elf-gcc/bin/riscv32-unknown-elf- + + # Windows + set ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + set CROSS_COMPILE=C:\riscv32-unknown-elf-gcc\bin\riscv32-unknown-elf- + +.. note:: + + The above only sets these variables for your current shell session. + You need to make sure this happens every time you use this board. + +Now let's compile the :ref:`hello_world` application. (You can try +others as well; see :ref:`samples-and-demos` for more.) + +.. We can't use zephyr-app-commands to provide build instructions + due to the below mentioned linker issue. + +Due to a toolchain `linker issue`_, you need to add an option setting +``CMAKE_REQUIRED_FLAGS`` when running CMake to generate a build system +(see :ref:`application` for information about Zephyr's build system). + +Linux and macOS (run this in a terminal from the Zephyr directory):: + + # Set up environment and create build directory: + source zephyr-env.sh + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :tool: cmake + :cd-into: + :board: rv32m1_vega/openisa_rv32m1/ri5cy + :gen-args: -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=/dev/null + :goals: build + +Windows (run this in a ``cmd`` prompt, from the Zephyr directory):: + + # Set up environment and create build directory + zephyr-env.cmd + cd samples\hello_world + mkdir build & cd build + + # Use CMake to generate a Ninja-based build system: + type NUL > empty.ld + cmake -GNinja -DBOARD=rv32m1_vega/openisa_rv32m1/ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.ld .. + + # Build the sample + ninja + +Flashing +======== + +.. note:: + + Make sure you've done the :ref:`JTAG setup `, and + that the VEGAboard's top left USB connector is connected to your + computer too (for UART access). + +.. note:: + + Linux users: to run these commands as a normal user, you will need + to install the `60-openocd.rules`_ udev rules file (usually by + placing it in :file:`/etc/udev/rules.d`, then unplugging and + plugging the J-Link in again via USB). + +Make sure you've followed the above instructions to set up your board +and build a program first. + +Since you need to use a special OpenOCD, the easiest way to flash is +by using :ref:`west flash ` instead of ``ninja +flash`` like you might see with other Zephyr documentation. + +Run these commands from the build directory where you ran ``ninja`` in +the above section. + +Linux and macOS:: + + # Don't use "~/rv32m1-openocd". It won't work. + west flash --openocd=$HOME/rv32m1-openocd + +Windows:: + + west flash --openocd=C:\rv32m1-openocd\bin\openocd.exe + +If you have problems: + +- Make sure you don't have another ``openocd`` process running in the + background. +- Unplug the boards and plug them back in. +- On Linux, make sure udev rules are installed, as described above. + +As an alternative, for manual steps to run OpenOCD and GDB to flash, +see the `SDK README`_. + +Debugging +========= + +.. note:: + + Make sure you've done the :ref:`JTAG setup `, and + that the VEGAboard's top left USB connector is connected to your + computer too (for UART access). + +.. note:: + + Linux users: to run these commands as a normal user, you will need + to install the `60-openocd.rules`_ udev rules file (usually by + placing it in :file:`/etc/udev/rules.d`, then unplugging and + plugging the J-Link in again via USB). + +Make sure you've followed the above instructions to set up your board +and build a program first. + +To debug with gdb:: + + # Linux, macOS + west debug --openocd=$HOME/rv32m1-openocd + + # Windows + west debug --openocd=C:\rv32m1-openocd\bin\openocd.exe + +Then, from the ``(gdb)`` prompt, follow these steps to halt the core, +load the binary (:file:`zephyr.elf`), and re-sync with the OpenOCD +server:: + + (gdb) monitor init + (gdb) monitor reset halt + (gdb) load + (gdb) monitor gdb_sync + (gdb) stepi + +You can then set breakpoints and debug using normal GDB commands. + +.. note:: + + GDB can get out of sync with the target if you execute commands + that reset it. To reset RI5CY and get GDB back in sync with it + without reloading the binary:: + + (gdb) monitor reset halt + (gdb) monitor gdb_sync + (gdb) stepi + +If you have problems: + +- Make sure you don't have another ``openocd`` process running in the + background. +- Unplug the boards and plug them back in. +- On Linux, make sure udev rules are installed, as described above. + +References +********** + +- OpenISA developer portal: http://open-isa.org +- `OpenISA GitHub releases`_: includes toolchain and OpenOCD + prebuilts, as well as documentation, such as the SoC datasheet and + reference manual, board schematic and user guides, etc. +- Base toolchain: `pulp-riscv-gnu-toolchain`_; extra toolchain patches: + `rv32m1_gnu_toolchain_patch`_ (only needed if building from source). +- OpenOCD repository: `rv32m1-openocd`_ (only needed if building from + source). +- Vendor SDK: `rv32m1_sdk_riscv`_. Contains HALs, non-Zephyr sample + applications, and information on using the board with Eclipse which + may be interesting when combined with the Eclipse Debugging + information in the :ref:`application`. + +.. _rv32m1_vega_toolchain_build: + +Appendix: Building Toolchain and OpenOCD from Source +**************************************************** + +.. note:: + + Toolchain and OpenOCD build instructions are provided for Linux and + macOS only. + + Instructions for building OpenOCD have only been verified on Linux. + +.. warning:: + + Don't use installation directories with spaces anywhere in + the path; this won't work with Zephyr's build system. + +Ubuntu 18.04 users need to install these additional dependencies:: + + sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \ + libmpfr-dev libgmp-dev gawk build-essential bison \ + flex texinfo gperf libtool patchutils bc zlib1g-dev \ + libusb-1.0-0-dev libudev1 libudev-dev g++ + +Users of other Linux distributions need to install the above packages +with their system package manager. + +macOS users need to install dependencies with Homebrew:: + + brew install gawk gnu-sed gmp mpfr libmpc isl zlib + +The build toolchain is based on the `pulp-riscv-gnu-toolchain`_, with +some additional patches hosted in a separate repository, +`rv32m1_gnu_toolchain_patch`_. To build the toolchain, follow the +instructions in the ``rv32m1_gnu_toolchain_patch`` repository's +`readme.md`_ file to apply the patches, then run:: + + ./configure --prefix= --with-arch=rv32imc --with-cmodel=medlow --enable-multilib + make + +If you set ```` to +:file:`~/riscv32-unknown-elf-gcc`, you can use the above instructions +for setting ``CROSS_COMPILE`` when building Zephyr +applications. If you set it to something else, you will need to update +your ``CROSS_COMPILE`` setting accordingly. + +.. note:: + + Strangely, there is no separate ``make install`` step for the + toolchain. That is, the ``make`` invocation both builds and + installs the toolchain. This means ``make`` has to be run as root + if you want to set ``--prefix`` to a system directory such as + :file:`/usr/local` or :file:`/opt` on Linux. + +To build OpenOCD, clone the `rv32m1-openocd`_ repository, then run +these from the repository top level:: + + ./bootstrap + ./configure --prefix= + make + make install + +If ```` is :file:`~/rv32m1-openocd`, you +should set your OpenOCD path to :file:`~/rv32m1-openocd/bin/openocd` +in the above flash and debug instructions. + +.. _RI5CY: + https://github.com/pulp-platform/riscv +.. _ZERO-RISCY: + https://github.com/pulp-platform/zero-riscy +.. _PULP platform: + http://iis-projects.ee.ethz.ch/index.php/PULP + +.. _pulp-riscv-gnu-toolchain: + https://github.com/pulp-platform/pulp-riscv-gnu-toolchain +.. _rv32m1_gnu_toolchain_patch: + https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch +.. _rv32m1-openocd: + https://github.com/open-isa-rv32m1/rv32m1-openocd +.. _readme.md: + https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch/blob/master/readme.md +.. _OpenISA GitHub releases: + https://github.com/open-isa-org/open-isa.org/releases +.. _rv32m1_sdk_riscv: + https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv +.. _linker issue: + https://github.com/pulp-platform/pulpino/issues/240 +.. _60-openocd.rules: + https://github.com/open-isa-rv32m1/rv32m1-openocd/blob/master/contrib/60-openocd.rules +.. _SEGGER J-Link: + https://www.segger.com/products/debug-probes/j-link/ +.. _9-Pin Cortex-M Adapter: + https://www.segger.com/products/debug-probes/j-link/accessories/adapters/9-pin-cortex-m-adapter/ +.. _J-Link Software and Documentation Pack: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack +.. _SDK README: + https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv/blob/master/readme.md + +.. rubric:: Footnotes + +.. [#toolchain_openocd] + + For Linux users, the RISC-V toolchain in the :ref:`Zephyr SDK + ` may work, but it hasn't been thoroughly tested with this + SoC, and will not allow use of any available RISC-V ISA extensions. + + Support for the RV32M1 SoC is not currently available in the OpenOCD + upstream repository or the OpenOCD build in the Zephyr SDK. diff --git a/boards/riscv/rv32m1_vega/doc/ri5cy_boot.jpg b/boards/openisa/rv32m1_vega/doc/ri5cy_boot.jpg similarity index 100% rename from boards/riscv/rv32m1_vega/doc/ri5cy_boot.jpg rename to boards/openisa/rv32m1_vega/doc/ri5cy_boot.jpg diff --git a/boards/riscv/rv32m1_vega/doc/rv32m1_vega.jpg b/boards/openisa/rv32m1_vega/doc/rv32m1_vega.jpg similarity index 100% rename from boards/riscv/rv32m1_vega/doc/rv32m1_vega.jpg rename to boards/openisa/rv32m1_vega/doc/rv32m1_vega.jpg diff --git a/boards/riscv/rv32m1_vega/doc/rv32m1_vega_jtag.jpg b/boards/openisa/rv32m1_vega/doc/rv32m1_vega_jtag.jpg similarity index 100% rename from boards/riscv/rv32m1_vega/doc/rv32m1_vega_jtag.jpg rename to boards/openisa/rv32m1_vega/doc/rv32m1_vega_jtag.jpg diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega-pinctrl.dtsi b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1-pinctrl.dtsi similarity index 100% rename from boards/riscv/rv32m1_vega/rv32m1_vega-pinctrl.dtsi rename to boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1-pinctrl.dtsi diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi new file mode 100644 index 00000000000000..f23b0ddd2e1b8e --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1.dtsi @@ -0,0 +1,176 @@ +/* + * Copyright 2018 Foundries.io Ltd + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "rv32m1_vega_openisa_rv32m1-pinctrl.dtsi" +#include + +/ { + aliases { + led0 = &green_led; + led1 = &blue_led; + led2 = &red_led; + led3 = &sts_led; + pwm-led0 = &blue_pwm_led; + pwm-led1 = &green_pwm_led; + pwm-led2 = &red_pwm_led; + blue-pwm-led = &blue_pwm_led; + green-pwm-led = &green_pwm_led; + red-pwm-led = &red_pwm_led; + sw0 = &user_button_2; + sw1 = &user_button_3; + sw2 = &user_button_4; + sw3 = &user_button_5; + magn0 = &fxos8700; + accel0 = &fxos8700; + }; + + leds { + compatible = "gpio-leds"; + blue_led: led_0 { + gpios = <&gpioa 22 GPIO_ACTIVE_HIGH>; + label = "User LD1"; + }; + green_led: led_1 { + gpios = <&gpioa 23 GPIO_ACTIVE_HIGH>; + label = "User LD2"; + }; + red_led: led_2 { + gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; + label = "User LD3"; + }; + sts_led: led_3 { + gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>; + label = "User LD4"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + blue_pwm_led: pwm_led_0 { + pwms = <&tpm2 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "User PWM LD1"; + }; + green_pwm_led: pwm_led_1 { + pwms = <&tpm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "User PWM LD2"; + }; + red_pwm_led: pwm_led_2 { + pwms = <&tpm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; + label = "User PWM LD3"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_2: button_0 { + label = "User SW2"; + gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_3: button_1 { + label = "User SW3"; + gpios = <&gpioe 8 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_4: button_2 { + label = "User SW4"; + gpios = <&gpioe 9 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_5: button_3 { + label = "User SW5"; + gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpioc 11 0>, /* A0 */ + <1 0 &gpioc 12 0>, /* A1 */ + <2 0 &gpiob 9 0>, /* A2 */ + <3 0 &gpioe 4 0>, /* A3 */ + <4 0 &gpioe 10 0>, /* A4 */ + <5 0 &gpioe 11 0>, /* A5 */ + <6 0 &gpioa 25 0>, /* D0 */ + <7 0 &gpioa 26 0>, /* D1 */ + <8 0 &gpioa 27 0>, /* D2 */ + <9 0 &gpiob 13 0>, /* D3 */ + <10 0 &gpiob 14 0>, /* D4 */ + <11 0 &gpioa 30 0>, /* D5 */ + <12 0 &gpioa 31 0>, /* D6 */ + <13 0 &gpiob 1 0>, /* D7 */ + <14 0 &gpiob 2 0>, /* D8 */ + <15 0 &gpiob 3 0>, /* D9 */ + <16 0 &gpiob 6 0>, /* D10 */ + <17 0 &gpiob 5 0>, /* D11 */ + <18 0 &gpiob 7 0>, /* D12 */ + <19 0 &gpiob 4 0>, /* D13 */ + <20 0 &gpioc 9 0>, /* D14 */ + <21 0 &gpioc 10 0>; /* D15 */ + }; +}; + +arduino_serial: &lpuart1 { + pinctrl-0 = <&lpuart1_default>; + pinctrl-names = "default"; +}; + +&lpuart0 { + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&lpuart0_default>; + pinctrl-names = "default"; +}; + +arduino_i2c: &lpi2c0 { + status = "okay"; + pinctrl-0 = <&lpi2c0_default>; + pinctrl-names = "default"; +}; + +&lpi2c3 { + status = "okay"; + pinctrl-0 = <&lpi2c3_default>; + pinctrl-names = "default"; + + fxos8700: fxos8700@1e { + compatible = "nxp,fxos8700"; + reg = <0x1e>; + reset-gpios = <&gpioe 27 GPIO_ACTIVE_HIGH>; + int1-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>; + int2-gpios = <&gpioe 22 GPIO_ACTIVE_LOW>; + }; +}; + +arduino_spi: &lpspi0 { + status = "okay"; + pinctrl-0 = <&lpspi0_default>; + pinctrl-names = "default"; +}; + +&lpspi1 { + status = "okay"; + cs-gpios = <&gpiob 22 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&lpspi1_default>; + pinctrl-names = "default"; + + mx25r32: mx25r3235f@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <80000000>; + jedec-id = [c2 28 16]; + size = <33554432>; + }; +}; + +&tpm2 { + status = "okay"; + pinctrl-0 = <&tpm2_default>; + pinctrl-names = "default"; +}; diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig new file mode 100644 index 00000000000000..908f07c0198975 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright 2018 Foundries.io Ltd + +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_MULTI_LEVEL_INTERRUPTS=y diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts new file mode 100644 index 00000000000000..b21e9b960ec1a3 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.dts @@ -0,0 +1,60 @@ +/* + * Copyright 2018 Foundries.io Ltd + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "openisa/rv32m1_ri5cy.dtsi" +#include "rv32m1_vega_openisa_rv32m1.dtsi" + +/ { + model = "OpenISA RV32M1 Vega RI5CY"; + compatible = "openisa,rv32m1"; + + chosen { + zephyr,sram = &m4_dtcm; + zephyr,flash = &m4_flash; + zephyr,console = &lpuart0; + zephyr,shell-uart = &lpuart0; + zephyr,uart-pipe = &lpuart0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + spi-flash0 = &mx25r32; + }; +}; + +&m4_flash { + /* + * For more information, see: + * http://docs.zephyrproject.org/latest/guides/dts/index.html + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + slot0_partition: partition@0 { + label = "image-0"; + reg = <0x00000000 0x00069000>; + }; + slot1_partition: partition@69000 { + label = "image-1"; + reg = <0x00069000 0x00069000>; + }; + scratch_partition: partition@d2000 { + label = "image-scratch"; + reg = <0x000d2000 0x0001e000>; + }; + storage_partition: partition@f0000 { + label = "storage"; + reg = <0x000f0000 0x00004000>; + }; + boot_partition: partition@f4000 { + label = "mcuboot"; + reg = <0x000f4000 0x0000C000>; + }; + }; +}; diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml new file mode 100644 index 00000000000000..59add3074d0e65 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_ri5cy.yaml @@ -0,0 +1,15 @@ +identifier: rv32m1_vega/openisa_rv32m1/ri5cy +name: RV32M1-VEGA (RI5CY) +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +supported: + - arduino_gpio + - arduino_i2c + - arduino_spi + - i2c + - pwm + - spi +vendor: openisa diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts new file mode 100644 index 00000000000000..10d2382ca944b1 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.dts @@ -0,0 +1,22 @@ +/* + * Copyright 2018 Foundries.io Ltd + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include "openisa/rv32m1_zero_riscy.dtsi" +#include "rv32m1_vega_openisa_rv32m1.dtsi" + +/ { + model = "OpenISA RV32M1 Vega Zero RISCY"; + compatible = "openisa,rv32m1"; + + chosen { + zephyr,sram = &m0_tcm; + zephyr,flash = &m0_flash; + zephyr,console = &lpuart0; + zephyr,uart-pipe = &lpuart0; + zephyr,code-partition = &zero_riscy_code_partition; + }; +}; diff --git a/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml new file mode 100644 index 00000000000000..0a2886ffabe213 --- /dev/null +++ b/boards/openisa/rv32m1_vega/rv32m1_vega_openisa_rv32m1_zero_riscy.yaml @@ -0,0 +1,13 @@ +identifier: rv32m1_vega/openisa_rv32m1/zero_riscy +name: RV32M1-VEGA (ZERO-RISCY) +type: mcu +arch: riscv +toolchain: + - cross-compile + - zephyr +supported: + - arduino_gpio + - arduino_i2c + - i2c + - pwm +vendor: openisa diff --git a/boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg similarity index 100% rename from boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg rename to boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg diff --git a/boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg b/boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg similarity index 100% rename from boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg rename to boards/openisa/rv32m1_vega/support/openocd_rv32m1_vega_zero_riscy.cfg diff --git a/boards/others/black_f407ve/Kconfig.black_f407ve b/boards/others/black_f407ve/Kconfig.black_f407ve new file mode 100644 index 00000000000000..09ce6d70f2b60e --- /dev/null +++ b/boards/others/black_f407ve/Kconfig.black_f407ve @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACK_F407VE + select SOC_STM32F407XE diff --git a/boards/others/black_f407ve/Kconfig.defconfig b/boards/others/black_f407ve/Kconfig.defconfig new file mode 100644 index 00000000000000..2d08ba38cebb91 --- /dev/null +++ b/boards/others/black_f407ve/Kconfig.defconfig @@ -0,0 +1,12 @@ +# black_f407ve board configuration + +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BLACK_F407VE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACK_F407VE diff --git a/boards/arm/black_f407ve/black_f407ve.dts b/boards/others/black_f407ve/black_f407ve.dts similarity index 100% rename from boards/arm/black_f407ve/black_f407ve.dts rename to boards/others/black_f407ve/black_f407ve.dts diff --git a/boards/arm/black_f407ve/black_f407ve.yaml b/boards/others/black_f407ve/black_f407ve.yaml similarity index 100% rename from boards/arm/black_f407ve/black_f407ve.yaml rename to boards/others/black_f407ve/black_f407ve.yaml diff --git a/boards/arm/black_f407ve/black_f407ve_defconfig b/boards/others/black_f407ve/black_f407ve_defconfig similarity index 85% rename from boards/arm/black_f407ve/black_f407ve_defconfig rename to boards/others/black_f407ve/black_f407ve_defconfig index 03fd48b1072484..02216f83f72b01 100644 --- a/boards/arm/black_f407ve/black_f407ve_defconfig +++ b/boards/others/black_f407ve/black_f407ve_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/black_f407ve/board.cmake b/boards/others/black_f407ve/board.cmake similarity index 100% rename from boards/arm/black_f407ve/board.cmake rename to boards/others/black_f407ve/board.cmake diff --git a/boards/others/black_f407ve/board.yml b/boards/others/black_f407ve/board.yml new file mode 100644 index 00000000000000..472d766cbc7a6f --- /dev/null +++ b/boards/others/black_f407ve/board.yml @@ -0,0 +1,5 @@ +board: + name: black_f407ve + vendor: others + socs: + - name: stm32f407xx diff --git a/boards/arm/black_f407ve/doc/img/black_f407ve.jpg b/boards/others/black_f407ve/doc/img/black_f407ve.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/black_f407ve.jpg rename to boards/others/black_f407ve/doc/img/black_f407ve.jpg diff --git a/boards/arm/black_f407ve/doc/img/stm32f407vet6_left02.jpg b/boards/others/black_f407ve/doc/img/stm32f407vet6_left02.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/stm32f407vet6_left02.jpg rename to boards/others/black_f407ve/doc/img/stm32f407vet6_left02.jpg diff --git a/boards/arm/black_f407ve/doc/img/stm32f407vet6_right01.jpg b/boards/others/black_f407ve/doc/img/stm32f407vet6_right01.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/stm32f407vet6_right01.jpg rename to boards/others/black_f407ve/doc/img/stm32f407vet6_right01.jpg diff --git a/boards/arm/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg b/boards/others/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg similarity index 100% rename from boards/arm/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg rename to boards/others/black_f407ve/doc/img/stm32f407vet6_st-link02.jpg diff --git a/boards/others/black_f407ve/doc/index.rst b/boards/others/black_f407ve/doc/index.rst new file mode 100644 index 00000000000000..a338e7ccf4b6a4 --- /dev/null +++ b/boards/others/black_f407ve/doc/index.rst @@ -0,0 +1,243 @@ +.. _black_f407ve_board: + +Black STM32 F407VE Development Board +#################################### + +Overview +******** + +The BLACK_F407VE board features an ARM Cortex-M4 based STM32F407xx MCU +with a wide range of connectivity support and configurations. There are +multiple version of this board like ``black_f407ve``. +Here are some highlights of the BLACK_F407VE board: + +- STM32 microcontroller in LQFP100 package +- Extension header for all LQFP100 I/Os for quick connection to prototyping + board and easy probing +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V) + - Power management access point + +- Three LEDs: + + - 3.3 V power on (LD0) + - Two user LEDs: green (LD1), green (LD2) + +- Four push-buttons: RESET, K0, K1 and WK_UP +- Mini-AB connector + +.. image:: img/black_f407ve.jpg + :align: center + :alt: BLACK_F407VE + +See also board descriptions at `STM32-base website`_, +`STM32F407VET6 black board`_ and `MCUDev Black STM32F407VET6`_ + +.. warning:: The +5V pins on this board are directly connected to the +5V pin + of the USB connector. There is no protection in place. Do not + power this board through USB and an external power supply at + the same time. + + +Hardware +******** + +BLACK_F407VE board provides the following hardware components: + +- STM32F407VET6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 8MHz system crystal +- 32.768KHz RTC crystal +- JTAG/SWD header +- 512 kB Flash +- 192+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC battery CR1220 +- Advanced-control Timer (2) +- General Purpose Timers (12) +- Watchdog Timers (2) +- USART (3), UART (2) +- I2C (3) +- I2S (2) +- SPI (3) +- SDIO (1) +- CAN (2) +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- CRC calculation unit +- True random number generator +- DMA Controller +- Micro SD +- 1x 10/100 Ethernet MAC +- 1x 8 to 12-bit Parallel Camera interface +- Micro USB for power and comms +- 2x jumpers for bootloader selection +- 2x16 FMSC LCD Interface +- NRF24L01 socket +- Dimensions: 85.1mm x 72.45mm + +More information about STM32F407VE SOC can be found here: + - `STM32F407VE on www.st.com`_ + +Supported Features +================== + +The Zephyr black_f407ve board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver. + Zephyr default configuration uses CAN_2 exclusively, as + simultaneous use of CAN_1 and CAN_2 is not yet supported. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/others/black_f407ve/black_f407ve_defconfig` + + +Pin Mapping +=========== + +BLACK_F407VE has 5 GPIO controllers. These controllers are responsible for pin +muxing, input/output, pull-up, etc. + +.. image:: img/stm32f407vet6_left02.jpg + :align: center + :alt: left pins + +.. image:: img/stm32f407vet6_right01.jpg + :align: center + :alt: right pins + +.. image:: img/stm32f407vet6_st-link02.jpg + :align: center + :alt: bottom and top pins + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PA0 +- LD3 : PD13 +- LD4 : PD12 +- LD5 : PD14 +- LD6 : PD15 +- USB DM : PA11 +- USB DP : PA12 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- CAN2_RX : PB12 +- CAN2_TX : PB13 +- SPI1 MISO : PB4 +- SPI1 MOSI : PB5 +- SPI1 SCK : PB3 +- SPI1 Flash CS : PB0 +- SPI2 MISO : PC2 +- SPI2 MOSI : PC3 +- SPI2 SCK : PB10 + +System Clock +============ + +BLACK_F407VE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock +at 168MHz, driven by 8MHz high speed external clock. + +Serial Port +=========== + +BLACK_F407VE has up to 6 UARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. +Please note that ST-Link Virtual Com Port is not wired to chip serial port. +In order to enable console output you should use a serial cable and connect +it to UART1 pins (PA9/PA10). + + +Programming and Debugging +************************* + +Applications for the ``black_f407ve`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +BLACK_F407VE board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to BLACK_F407VE +--------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: black_f407ve + :goals: build flash + +You should see user led "LD1" blinking. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: black_f407ve + :maybe-skip-config: + :goals: debug + +.. _STM32-base website: + https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0.html + +.. _STM32F407VE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f407ve.html + +.. _STM32F407VET6 black board: + https://os.mbed.com/users/hudakz/code/STM32F407VET6_Hello/ + +.. _MCUDev Black STM32F407VET6: + https://github.com/mcauser/BLACK_F407VE diff --git a/boards/arm/black_f407ve/support/openocd.cfg b/boards/others/black_f407ve/support/openocd.cfg similarity index 100% rename from boards/arm/black_f407ve/support/openocd.cfg rename to boards/others/black_f407ve/support/openocd.cfg diff --git a/boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro b/boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro new file mode 100644 index 00000000000000..162f8ad71dec68 --- /dev/null +++ b/boards/others/black_f407zg_pro/Kconfig.black_f407zg_pro @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACK_F407ZG_PRO + select SOC_STM32F407XG diff --git a/boards/others/black_f407zg_pro/Kconfig.defconfig b/boards/others/black_f407zg_pro/Kconfig.defconfig new file mode 100644 index 00000000000000..52929e95a9de83 --- /dev/null +++ b/boards/others/black_f407zg_pro/Kconfig.defconfig @@ -0,0 +1,12 @@ +# black_f407zg board configuration + +# Copyright (c) 2020 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_BLACK_F407ZG_PRO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACK_F407ZG_PRO diff --git a/boards/arm/black_f407zg_pro/black_f407zg_pro.dts b/boards/others/black_f407zg_pro/black_f407zg_pro.dts similarity index 100% rename from boards/arm/black_f407zg_pro/black_f407zg_pro.dts rename to boards/others/black_f407zg_pro/black_f407zg_pro.dts diff --git a/boards/arm/black_f407zg_pro/black_f407zg_pro.yaml b/boards/others/black_f407zg_pro/black_f407zg_pro.yaml similarity index 100% rename from boards/arm/black_f407zg_pro/black_f407zg_pro.yaml rename to boards/others/black_f407zg_pro/black_f407zg_pro.yaml diff --git a/boards/arm/black_f407zg_pro/black_f407zg_pro_defconfig b/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig similarity index 85% rename from boards/arm/black_f407zg_pro/black_f407zg_pro_defconfig rename to boards/others/black_f407zg_pro/black_f407zg_pro_defconfig index 3e74a5e5885fa4..02216f83f72b01 100644 --- a/boards/arm/black_f407zg_pro/black_f407zg_pro_defconfig +++ b/boards/others/black_f407zg_pro/black_f407zg_pro_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/olimex_stm32_h407/board.cmake b/boards/others/black_f407zg_pro/board.cmake similarity index 100% rename from boards/arm/olimex_stm32_h407/board.cmake rename to boards/others/black_f407zg_pro/board.cmake diff --git a/boards/others/black_f407zg_pro/board.yml b/boards/others/black_f407zg_pro/board.yml new file mode 100644 index 00000000000000..dc322315620da7 --- /dev/null +++ b/boards/others/black_f407zg_pro/board.yml @@ -0,0 +1,5 @@ +board: + name: black_f407zg_pro + vendor: others + socs: + - name: stm32f407xx diff --git a/boards/arm/black_f407zg_pro/doc/img/black_f407zg_pro.jpg b/boards/others/black_f407zg_pro/doc/img/black_f407zg_pro.jpg similarity index 100% rename from boards/arm/black_f407zg_pro/doc/img/black_f407zg_pro.jpg rename to boards/others/black_f407zg_pro/doc/img/black_f407zg_pro.jpg diff --git a/boards/others/black_f407zg_pro/doc/index.rst b/boards/others/black_f407zg_pro/doc/index.rst new file mode 100644 index 00000000000000..1ca764cdf1d786 --- /dev/null +++ b/boards/others/black_f407zg_pro/doc/index.rst @@ -0,0 +1,216 @@ +.. _black_f407zg_pro_board: + +Black STM32 F407ZG Pro Development Board +######################################## + +Overview +******** + +The BLACK_F407ZG_PRO board features an ARM Cortex-M4 based STM32F407zg MCU +with a wide range of connectivity support and configurations. There are +multiple version of this board like ``black_f407ve``. +Here are some highlights of the BLACK_F407ZG_PRO board: + +- STM32 microcontroller in LQFP144 package +- Extension header for all LQFP144 I/Os for quick connection to prototyping + board and easy probing +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V) + - Power management access point + +- Three LEDs: + + - 3.3 V power on (LD0) + - Two user LEDs: green (LD1), green (LD2) + +- Four push-buttons: RESET, K0, K1 and WK_UP +- Mini-AB connector + +.. image:: img/black_f407zg_pro.jpg + :align: center + :alt: BLACK_F407ZG_PRO + +.. warning:: The +5V pins on this board are directly connected to the +5V pin + of the USB connector. There is no protection in place. Do not + power this board through USB and an external power supply at + the same time. + + +Hardware +******** + +BLACK_F407ZG_PRO board provides the following hardware components: + +- STM32F407ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 8MHz system crystal +- 32.768KHz RTC crystal +- JTAG/SWD header +- 1024 kB Flash +- 192+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC battery CR1220 +- Advanced-control Timer (2) +- General Purpose Timers (12) +- Watchdog Timers (2) +- USART (3), UART (2) +- I2C (3) +- I2S (2) +- SPI (3) +- SDIO (1) +- CAN (2) +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- CRC calculation unit +- True random number generator +- DMA Controller +- Micro SD +- 1x 10/100 Ethernet MAC +- 1x 8 to 12-bit Parallel Camera interface +- Micro USB for power and comms +- 2x jumpers for bootloader selection +- 2x16 FMSC LCD Interface +- NRF24L01 socket +- Dimensions: 102.5mm x 74.56mm + +More information about STM32F407ZG SOC can be found here: + - `STM32F407ZG on www.st.com`_ + +Supported Features +================== + +The Zephyr black_f407zg_pro board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver. + Zephyr default configuration uses CAN_2 exclusively, as + simultaneous use of CAN_1 and CAN_2 is not yet supported. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/others/black_f407zg_pro/black_f407zg_pro_defconfig` + + +Pin Mapping +=========== + +BLACK_F407ZG_PRO has 7 GPIO controllers. These controllers are responsible for pin +muxing, input/output, pull-up, etc. + + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PA0 +- LD3 : PD13 +- LD4 : PD12 +- LD5 : PD14 +- LD6 : PD15 +- USB DM : PA11 +- USB DP : PA12 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- CAN2_RX : PB12 +- CAN2_TX : PB13 +- SPI2 MISO : PC2 +- SPI2 MOSI : PC3 +- SPI2 SCK : PB10 + +System Clock +============ + +BLACK_F407ZG_PRO System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock +at 168MHz, driven by 8MHz high speed external clock. + +Serial Port +=========== + +BLACK_F407ZG_PRO has up to 6 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. +Please note that ST-Link Virtual Com Port is not wired to chip serial port. +In order to enable console output you should use a serial cable and connect +it to UART2 pins (PA2/PA3). + + +Programming and Debugging +************************* + +Applications for the ``black_f407zg_pro`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +BLACK_F407ZG_PRO board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to BLACK_F407ZG_PRO +------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: black_f407zg_pro + :goals: build flash + +You should see user led "LD1" blinking. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: black_f407zg_pro + :maybe-skip-config: + :goals: debug + +.. _STM32F407ZG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32f407zg.html diff --git a/boards/arm/black_f407zg_pro/support/openocd.cfg b/boards/others/black_f407zg_pro/support/openocd.cfg similarity index 100% rename from boards/arm/black_f407zg_pro/support/openocd.cfg rename to boards/others/black_f407zg_pro/support/openocd.cfg diff --git a/boards/others/icev_wireless/Kconfig.defconfig b/boards/others/icev_wireless/Kconfig.defconfig new file mode 100644 index 00000000000000..96ed16249d4aeb --- /dev/null +++ b/boards/others/icev_wireless/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2022 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/others/icev_wireless/Kconfig.icev_wireless b/boards/others/icev_wireless/Kconfig.icev_wireless new file mode 100644 index 00000000000000..22ef32910e5271 --- /dev/null +++ b/boards/others/icev_wireless/Kconfig.icev_wireless @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ICEV_WIRELESS + select SOC_ESP32C3_MINI_N4 diff --git a/boards/xtensa/olimex_esp32_evb/Kconfig.sysbuild b/boards/others/icev_wireless/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/olimex_esp32_evb/Kconfig.sysbuild rename to boards/others/icev_wireless/Kconfig.sysbuild diff --git a/boards/xtensa/m5stack_core2/board.cmake b/boards/others/icev_wireless/board.cmake similarity index 100% rename from boards/xtensa/m5stack_core2/board.cmake rename to boards/others/icev_wireless/board.cmake diff --git a/boards/others/icev_wireless/board.yml b/boards/others/icev_wireless/board.yml new file mode 100644 index 00000000000000..2dcef96cbdfac5 --- /dev/null +++ b/boards/others/icev_wireless/board.yml @@ -0,0 +1,5 @@ +board: + name: icev_wireless + vendor: others + socs: + - name: esp32c3 diff --git a/boards/riscv/icev_wireless/doc/img/icev_wireless.jpg b/boards/others/icev_wireless/doc/img/icev_wireless.jpg similarity index 100% rename from boards/riscv/icev_wireless/doc/img/icev_wireless.jpg rename to boards/others/icev_wireless/doc/img/icev_wireless.jpg diff --git a/boards/riscv/icev_wireless/doc/img/icev_wireless_back.jpg b/boards/others/icev_wireless/doc/img/icev_wireless_back.jpg similarity index 100% rename from boards/riscv/icev_wireless/doc/img/icev_wireless_back.jpg rename to boards/others/icev_wireless/doc/img/icev_wireless_back.jpg diff --git a/boards/riscv/icev_wireless/doc/img/icev_wireless_pinout.jpg b/boards/others/icev_wireless/doc/img/icev_wireless_pinout.jpg similarity index 100% rename from boards/riscv/icev_wireless/doc/img/icev_wireless_pinout.jpg rename to boards/others/icev_wireless/doc/img/icev_wireless_pinout.jpg diff --git a/boards/others/icev_wireless/doc/index.rst b/boards/others/icev_wireless/doc/index.rst new file mode 100644 index 00000000000000..a931bb33da7c04 --- /dev/null +++ b/boards/others/icev_wireless/doc/index.rst @@ -0,0 +1,259 @@ +.. _icev_wireless: + +ICE-V Wireless +############## + +Overview +******** + +The ICE-V Wireless is a combined ESP32C3 and iCE40 FPGA board. + +See the `ICE-V Wireless Github Project`_ for details. + +.. figure:: img/icev_wireless.jpg + :align: center + :alt: ICE-V Wireless + + ICE-V Wireless + +Hardware +******** + +This board combines an Espressif ESP32-C3-MINI-1 (which includes 4MB of flash in the module) with a +Lattice iCE40UP5k-SG48 FPGA to allow WiFi and Bluetooth control of the FPGA. ESP32 and FPGA I/O is +mostly uncommitted except for the pins used for SPI communication between ESP32 and FPGA. Several +of the ESP32C3 GPIO pins are available for additonal interfaces such as serial, ADC, I2C, etc. + +For details on ESP32-C3 hardware please refer to the following resources: + +* `ESP32-C3-MINI-1 Datasheet`_ +* `ESP32-C3 Datasheet`_ +* `ESP32-C3 Technical Reference Manual`_ + +For details on iCE40 hardware please refer to the following resources: + +* `iCE40 UltraPlus Family Datasheet`_ + +Supported Features +================== + +The ICE-V Wireless board configuration supports the following hardware +features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| ADC | on-chip | | ++-----------+------------+------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The ICE-V Wireless provides 1 row of reference, ESP32-C3, and iCE40 signals +brought out to J3, as well as 3 PMOD connectors for interfacing directly to +the iCE40 FPGA. Note that several of the iCE40 pins brought out to the PMOD +connectors are capable of operating as differential pairs. + +.. figure:: img/icev_wireless_back.jpg + :align: center + :alt: ICE-V Wireless (Back) + + ICE-V Wireless (Back) + +The J3 pins are 4V, 3.3V, NRST, GPIO2, GPIO3, GPIO8, GPIO9, GPIO10, GPIO20, +GPIO21, FPGA_P34, and GND. Note that GPIO2 and GPIO3 may be configured for +ADC operation. + +For PMOD details, please refer to the `PMOD Specification`_ and the image +below. + +.. figure:: img/icev_wireless_pinout.jpg + :align: center + :alt: ICE-V Wireless Pinout + +Programming and Debugging +************************* + +Programming and debugging for the ICE-V Wireless ESP32-C3 target is +incredibly easy 🎉 following the steps below. + +Building and Flashing +********************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: icev_wireless + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +For the :code:`Hello, world!` application, follow the instructions below. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: icev_wireless + :goals: build flash + +Open the serial monitor using the following command: + +.. code-block:: console + + $ west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! icev_wireless + +Debugging +********* + +As with much custom hardware, the ESP32C3 modules require patches to +OpenOCD that are not upstreamed. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained by running the following extension: + +.. code-block:: console + + west espressif install + +.. note:: + + By default, the OpenOCD will be downloaded and installed under $HOME/.espressif/tools/zephyr directory + (%USERPROFILE%/.espressif/tools/zephyr on Windows). + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: icev_wireless + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: icev_wireless + :maybe-skip-config: + :goals: debug + +References +********** + +.. _ICE-V Wireless Github Project: + https://github.com/ICE-V-Wireless/ICE-V-Wireless + +.. _ESP32-C3-MINI-1 Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf + +.. _ESP32-C3 Datasheet: + https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf + +.. _ESP32-C3 Technical Reference Manual: + https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf + +.. _iCE40 UltraPlus Family Datasheet: + https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/iCE/iCE40-UltraPlus-Family-Data-Sheet.ashx + +.. _PMOD Specification: + https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf diff --git a/boards/riscv/icev_wireless/icev_wireless-pinctrl.dtsi b/boards/others/icev_wireless/icev_wireless-pinctrl.dtsi similarity index 100% rename from boards/riscv/icev_wireless/icev_wireless-pinctrl.dtsi rename to boards/others/icev_wireless/icev_wireless-pinctrl.dtsi diff --git a/boards/riscv/icev_wireless/icev_wireless.dts b/boards/others/icev_wireless/icev_wireless.dts similarity index 98% rename from boards/riscv/icev_wireless/icev_wireless.dts rename to boards/others/icev_wireless/icev_wireless.dts index 1e5719fe2aaa10..8ed474200e0bc5 100644 --- a/boards/riscv/icev_wireless/icev_wireless.dts +++ b/boards/others/icev_wireless/icev_wireless.dts @@ -11,7 +11,7 @@ #include / { - model = "icev_wireless"; + model = "ICEV Wireless"; compatible = "espressif,esp32c3"; chosen { diff --git a/boards/riscv/icev_wireless/icev_wireless.yaml b/boards/others/icev_wireless/icev_wireless.yaml similarity index 100% rename from boards/riscv/icev_wireless/icev_wireless.yaml rename to boards/others/icev_wireless/icev_wireless.yaml diff --git a/boards/others/icev_wireless/icev_wireless_defconfig b/boards/others/icev_wireless/icev_wireless_defconfig new file mode 100644 index 00000000000000..ef633ce56a18e2 --- /dev/null +++ b/boards/others/icev_wireless/icev_wireless_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/riscv/icev_wireless/support/openocd.cfg b/boards/others/icev_wireless/support/openocd.cfg similarity index 100% rename from boards/riscv/icev_wireless/support/openocd.cfg rename to boards/others/icev_wireless/support/openocd.cfg diff --git a/boards/others/index.rst b/boards/others/index.rst new file mode 100644 index 00000000000000..c39d99c4d08815 --- /dev/null +++ b/boards/others/index.rst @@ -0,0 +1,10 @@ +.. _boards-others: + +Other and unknown vendors +######################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/riscv/neorv32/CMakeLists.txt b/boards/others/neorv32/CMakeLists.txt similarity index 100% rename from boards/riscv/neorv32/CMakeLists.txt rename to boards/others/neorv32/CMakeLists.txt diff --git a/boards/others/neorv32/Kconfig b/boards/others/neorv32/Kconfig new file mode 100644 index 00000000000000..57e0edc10d66e8 --- /dev/null +++ b/boards/others/neorv32/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NEORV32 + select SOC_NEORV32_V1_8_6 if "$(BOARD_REVISION)" = "1.8.6" diff --git a/boards/others/neorv32/Kconfig.neorv32 b/boards/others/neorv32/Kconfig.neorv32 new file mode 100644 index 00000000000000..1e5efecd08fae6 --- /dev/null +++ b/boards/others/neorv32/Kconfig.neorv32 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NEORV32 + select SOC_NEORV32 diff --git a/boards/riscv/neorv32/board.cmake b/boards/others/neorv32/board.cmake similarity index 100% rename from boards/riscv/neorv32/board.cmake rename to boards/others/neorv32/board.cmake diff --git a/boards/others/neorv32/board.yml b/boards/others/neorv32/board.yml new file mode 100644 index 00000000000000..f12fa42b78fbc7 --- /dev/null +++ b/boards/others/neorv32/board.yml @@ -0,0 +1,10 @@ +board: + name: neorv32 + vendor: others + revision: + format: major.minor.patch + default: "1.8.6" + revisions: + - name: "1.8.6" + socs: + - name: neorv32 diff --git a/boards/riscv/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst similarity index 100% rename from boards/riscv/neorv32/doc/index.rst rename to boards/others/neorv32/doc/index.rst diff --git a/boards/riscv/neorv32/neorv32.dts b/boards/others/neorv32/neorv32.dts similarity index 100% rename from boards/riscv/neorv32/neorv32.dts rename to boards/others/neorv32/neorv32.dts diff --git a/boards/riscv/neorv32/neorv32.yaml b/boards/others/neorv32/neorv32.yaml similarity index 100% rename from boards/riscv/neorv32/neorv32.yaml rename to boards/others/neorv32/neorv32.yaml diff --git a/boards/riscv/neorv32/neorv32_defconfig b/boards/others/neorv32/neorv32_defconfig similarity index 84% rename from boards/riscv/neorv32/neorv32_defconfig rename to boards/others/neorv32/neorv32_defconfig index 7dc8a74ffff164..2642d046b500dc 100644 --- a/boards/riscv/neorv32/neorv32_defconfig +++ b/boards/others/neorv32/neorv32_defconfig @@ -1,9 +1,7 @@ # Copyright (c) 2021 Henrik Brix Andersen # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_NEORV32=y CONFIG_SOC_NEORV32_ISA_C=y -CONFIG_BOARD_NEORV32=y CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/neorv32/support/neorv32.cfg b/boards/others/neorv32/support/neorv32.cfg similarity index 100% rename from boards/riscv/neorv32/support/neorv32.cfg rename to boards/others/neorv32/support/neorv32.cfg diff --git a/boards/riscv/neorv32/support/openocd.cfg b/boards/others/neorv32/support/openocd.cfg similarity index 100% rename from boards/riscv/neorv32/support/openocd.cfg rename to boards/others/neorv32/support/openocd.cfg diff --git a/boards/others/stm32_min_dev/Kconfig.stm32_min_dev b/boards/others/stm32_min_dev/Kconfig.stm32_min_dev new file mode 100644 index 00000000000000..6ca578a2287dda --- /dev/null +++ b/boards/others/stm32_min_dev/Kconfig.stm32_min_dev @@ -0,0 +1,7 @@ +# STM32 Minimum Development Board Configuration + +# Copyright (c) 2017, embedjournal.com +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32_MIN_DEV + select SOC_STM32F103X8 diff --git a/boards/arm/stm32_min_dev/board.cmake b/boards/others/stm32_min_dev/board.cmake similarity index 100% rename from boards/arm/stm32_min_dev/board.cmake rename to boards/others/stm32_min_dev/board.cmake diff --git a/boards/others/stm32_min_dev/board.yml b/boards/others/stm32_min_dev/board.yml new file mode 100644 index 00000000000000..28a35697379178 --- /dev/null +++ b/boards/others/stm32_min_dev/board.yml @@ -0,0 +1,7 @@ +board: + name: stm32_min_dev + vendor: others + revision: + format: custom + socs: + - name: stm32f103xb diff --git a/boards/arm/stm32_min_dev/doc/img/stm32_min_dev.jpg b/boards/others/stm32_min_dev/doc/img/stm32_min_dev.jpg similarity index 100% rename from boards/arm/stm32_min_dev/doc/img/stm32_min_dev.jpg rename to boards/others/stm32_min_dev/doc/img/stm32_min_dev.jpg diff --git a/boards/arm/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg b/boards/others/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg similarity index 100% rename from boards/arm/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg rename to boards/others/stm32_min_dev/doc/img/stm32_min_dev_pinout_blue.jpg diff --git a/boards/others/stm32_min_dev/doc/index.rst b/boards/others/stm32_min_dev/doc/index.rst new file mode 100644 index 00000000000000..61caf674f95921 --- /dev/null +++ b/boards/others/stm32_min_dev/doc/index.rst @@ -0,0 +1,186 @@ +.. _stm32_min_dev: + +STM32 Minimum Development Board +############################### + +Overview +******** + +The STM32 Minimum Development Board, is a popular and inexpensive +breadboard-friendly breakout board for the `STM32F103x8`_ CPU. There +are two variants of the board: + +- Blue Pill Board +- Black Pill Board + +Zephyr applications can use the stm32_min_dev@blue or stm32_min_dev@black board +configuration to use these boards. + +.. figure:: img/stm32_min_dev.jpg + :align: center + :alt: STM32 Minimum Development Board + + STM32 Minimum Development Board + +As the name suggests, these boards have the bare minimum components required to +power on the CPU. For practical use, you'll need to add additional components +and circuits using a breadboard, for example. + +Pin Mapping +=========== + +This port is a starting point for your own customizations and not a complete +port for a specific board. Most of the GPIOs on the STM32 SoC has been exposed +in the external header with silk screen labels that match the SoC's pin names. + +Each board vendor has their own variations in pin mapping on their boards' +external connectors and placement of components. Many vendors use port PC13/PB12 +for connecting an LED, so only this device is supported by our Zephyr port. +Additional device support is left for the user to implement. + +More information on hooking up peripherals and lengthy how to articles can be +found at `EmbedJournal`_. + +The pinout diagram of STM32 Minimum Development Blue Pill board can be seen +below. The Black Pill's one is similar: + +.. figure:: img/stm32_min_dev_pinout_blue.jpg + :align: center + :alt: Pinout for STM32 Minimum Development Blue Pill Board + + Pinout for STM32 Minimum Development Blue Pill Board + + +STLinkV2 connection: +==================== + +The board can be flashed by using STLinkV2 with the following connections. + ++--------+---------------+ +| Pin | STLINKv2 | ++========+===============+ +| G | GND | ++--------+---------------+ +| CLK | Clock | ++--------+---------------+ +| IO | SW IO | ++--------+---------------+ +| V3 | VCC | ++--------+---------------+ + +Boot Configuration +================== + +The boot configuration for this board is configured through jumpers on B0 (Boot 0) +and B1 (Boot 1). The pins B0 and B1 are present in between logic 0 and 1 lines. The +silk screen on the PCB reads BX- or BX+ to indicate 0 and 1 logic lines for B0 and B1 +respectively. + ++--------+--------+-------------------+---------------------------------------------+ +| Boot 1 | Boot 0 | Boot Mode | Aliasing | ++========+========+===================+=============================================+ +| X | 0 | Main Flash Memory | Main flash memory is selected as boot space | ++--------+--------+-------------------+---------------------------------------------+ +| 0 | 1 | System Memory | System memory is selected as boot space | ++--------+--------+-------------------+---------------------------------------------+ +| 1 | 1 | Embedded SRAM | Embedded SRAM is selected as boot space | ++--------+--------+-------------------+---------------------------------------------+ + + +Supported Features +================== + +The stm32_min_dev board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| USB | on-chip | USB device | ++-----------+------------+----------------------+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX: PA9/PA10 +- UART_2 TX/RX: PA2/PA3 +- UART_3 TX/RX: PB10/PB11 +- I2C_1 SCL/SDA : PB6/PB7 +- I2C_2 SCL/SDA : PB10/PB11 +- PWM_1_CH1: PA8 +- SPI_1 NSS_OE/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 +- SPI_2 NSS_OE/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 +- USB_DC DM/DP: PA11/PA12 +- ADC_1: PA0 + +System Clock +------------ + +The on-board 8Mhz crystal is used to produce a 72Mhz system clock with PLL. + +Serial Port +----------- + +STM32 Minimum Development Board has 3 U(S)ARTs. The Zephyr console output is +assigned to UART_1. Default settings are 115200 8N1. + +On-Board LEDs +------------- + +The board has one on-board LED that is connected to PB12/PC13 on the black/blue +variants respectively. + +Programming and Debugging +************************* + +Applications for the ``stm32_min_dev@(blue|black)`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32_min_dev + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32_min_dev + :maybe-skip-config: + :goals: debug + +.. _STM32F103x8: + https://www.st.com/resource/en/datasheet/stm32f103c8.pdf +.. _EmbedJournal: + https://embedjournal.com/tag/stm32-min-dev/ diff --git a/boards/others/stm32_min_dev/revision.cmake b/boards/others/stm32_min_dev/revision.cmake new file mode 100644 index 00000000000000..37dc3550db83b3 --- /dev/null +++ b/boards/others/stm32_min_dev/revision.cmake @@ -0,0 +1,8 @@ +set(BOARD_REVISIONS "blue" "black") +if(NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION "blue") +else() + if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS) + message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for stm32_min_dev. Accepted revisions: ${BOARD_REVISIONS}") + endif() +endif() diff --git a/boards/arm/stm32_min_dev/stm32_min_dev.dtsi b/boards/others/stm32_min_dev/stm32_min_dev.dts similarity index 100% rename from boards/arm/stm32_min_dev/stm32_min_dev.dtsi rename to boards/others/stm32_min_dev/stm32_min_dev.dts diff --git a/boards/others/stm32_min_dev/stm32_min_dev_black.yaml b/boards/others/stm32_min_dev/stm32_min_dev_black.yaml new file mode 100644 index 00000000000000..0740dc17fafb39 --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_black.yaml @@ -0,0 +1,15 @@ +identifier: stm32_min_dev@black +name: STM32 Minimum Development Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 20 +supported: + - i2c + - pwm + - spi + - adc + - gpio diff --git a/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml b/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml new file mode 100644 index 00000000000000..8249d6f9719925 --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_blue.yaml @@ -0,0 +1,15 @@ +identifier: stm32_min_dev@blue +name: STM32 Minimum Development Board +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 20 +supported: + - i2c + - pwm + - spi + - adc + - gpio diff --git a/boards/others/stm32_min_dev/stm32_min_dev_defconfig b/boards/others/stm32_min_dev/stm32_min_dev_defconfig new file mode 100644 index 00000000000000..ac78c1fed4e087 --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_defconfig @@ -0,0 +1,21 @@ +# STM32 Minimum Development Board Configuration +# +# Copyright (c) 2019, embedjournal.com +# +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# enable clock control +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_black.overlay b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_black.overlay new file mode 100644 index 00000000000000..25b8bf2688cc18 --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_black.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2019, embedjournal.com + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "STM32 Minimum Development Board (Black)"; + compatible = "stm32_min_dev_black", "st,stm32f103c8"; + + leds { + led: led { + gpios = <&gpiob 12 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_blue.overlay b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_blue.overlay new file mode 100644 index 00000000000000..41f657276d5c95 --- /dev/null +++ b/boards/others/stm32_min_dev/stm32_min_dev_stm32f103xb_blue.overlay @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2017, embedjournal.com + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "STM32 Minimum Development Board (Blue)"; + compatible = "stm32_min_dev_blue", "st,stm32f103c8"; + + leds { + led: led { + gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/boards/arm/stm32_min_dev/support/openocd.cfg b/boards/others/stm32_min_dev/support/openocd.cfg similarity index 100% rename from boards/arm/stm32_min_dev/support/openocd.cfg rename to boards/others/stm32_min_dev/support/openocd.cfg diff --git a/boards/others/stm32f030_demo/Kconfig.stm32f030_demo b/boards/others/stm32f030_demo/Kconfig.stm32f030_demo new file mode 100644 index 00000000000000..b349bf791c7f7a --- /dev/null +++ b/boards/others/stm32f030_demo/Kconfig.stm32f030_demo @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F030_DEMO + select SOC_STM32F030X4 diff --git a/boards/arm/stm32f030_demo/board.cmake b/boards/others/stm32f030_demo/board.cmake similarity index 100% rename from boards/arm/stm32f030_demo/board.cmake rename to boards/others/stm32f030_demo/board.cmake diff --git a/boards/others/stm32f030_demo/board.yml b/boards/others/stm32f030_demo/board.yml new file mode 100644 index 00000000000000..348d40a665b88a --- /dev/null +++ b/boards/others/stm32f030_demo/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f030_demo + vendor: others + socs: + - name: stm32f030x6 diff --git a/boards/arm/stm32f030_demo/doc/img/stm32f030_demo.jpg b/boards/others/stm32f030_demo/doc/img/stm32f030_demo.jpg similarity index 100% rename from boards/arm/stm32f030_demo/doc/img/stm32f030_demo.jpg rename to boards/others/stm32f030_demo/doc/img/stm32f030_demo.jpg diff --git a/boards/others/stm32f030_demo/doc/index.rst b/boards/others/stm32f030_demo/doc/index.rst new file mode 100644 index 00000000000000..8080f2b33d91d7 --- /dev/null +++ b/boards/others/stm32f030_demo/doc/index.rst @@ -0,0 +1,123 @@ +.. _stm32f030_demo: + +STM32F030 DEMO BOARD +#################### + +This board has the bare minimum components required to power on +the STM32F030F4P6 MCU. Most of the GPIOs on the STM32 SoC have +been exposed in the external headers with silk screen labels +that match the SoC's pin names. + +For practical use, you'll need to add additional components +and circuits using a breadboard, for example. + +.. image:: img/stm32f030_demo.jpg + :align: center + :alt: STM32F030 DEMO BOARD + +More information about the board can be found at the `stm32-base.org website`_. + +More information about STM32F030F4P6 can be found here: + +- `STM32F030 reference manual`_ +- `STM32F030 data sheet`_ + +Hardware +******** + +- STM32F030F4P6 ARM Cortex-M0 processor, frequency up to 48 MHz +- 16 KiB of flash memory and 4 KiB of RAM +- 8 MHz quartz crystal +- 1 user LED +- One reset button +- 2-way jumper (BOOT0) +- Serial (1x4 male dupont (2.54mm)) +- SWD (1x4 male dupont (2.54mm)) +- USB port (power only) + +Supported Features +================== + +The Zephyr stm32f030_demo board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/others/stm32f030_demo/stm32f030_demo_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- LED : PA4 + +Programming and Debugging +************************* + +Applications for the ``stm32f030_demo`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The board can be flashed by using ST-LINKV2 in-circuit debugger and programmer. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F030 DEMO BOARD +----------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f030_demo + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f030_demo + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _stm32-base.org website: + https://stm32-base.org/boards/STM32F030F4P6-STM32F030-DEMO-BOARD-V1.1 + +.. _STM32F030 reference manual: + https://www.st.com/resource/en/reference_manual/dm00091010.pdf + +.. _STM32F030 data sheet: + https://www.st.com/resource/en/datasheet/stm32f030f4.pdf diff --git a/boards/arm/stm32f030_demo/stm32f030_demo.dts b/boards/others/stm32f030_demo/stm32f030_demo.dts similarity index 100% rename from boards/arm/stm32f030_demo/stm32f030_demo.dts rename to boards/others/stm32f030_demo/stm32f030_demo.dts diff --git a/boards/arm/stm32f030_demo/stm32f030_demo.yaml b/boards/others/stm32f030_demo/stm32f030_demo.yaml similarity index 100% rename from boards/arm/stm32f030_demo/stm32f030_demo.yaml rename to boards/others/stm32f030_demo/stm32f030_demo.yaml diff --git a/boards/arm/stm32f030_demo/stm32f030_demo_defconfig b/boards/others/stm32f030_demo/stm32f030_demo_defconfig similarity index 80% rename from boards/arm/stm32f030_demo/stm32f030_demo_defconfig rename to boards/others/stm32f030_demo/stm32f030_demo_defconfig index 1e436d1e3ea389..d7de7d90f541eb 100644 --- a/boards/arm/stm32f030_demo/stm32f030_demo_defconfig +++ b/boards/others/stm32f030_demo/stm32f030_demo_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F030X4=y - # Kernel Options due to Low Memory (4k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/stm32f030_demo/support/openocd.cfg b/boards/others/stm32f030_demo/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f030_demo/support/openocd.cfg rename to boards/others/stm32f030_demo/support/openocd.cfg diff --git a/boards/others/stm32f401_mini/Kconfig.defconfig b/boards/others/stm32f401_mini/Kconfig.defconfig new file mode 100644 index 00000000000000..b622b27da9822e --- /dev/null +++ b/boards/others/stm32f401_mini/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2022 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +# STM32 Mini F401 board definitions + +if BOARD_STM32F401_MINI + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_STM32F401_MINI diff --git a/boards/others/stm32f401_mini/Kconfig.stm32f401_mini b/boards/others/stm32f401_mini/Kconfig.stm32f401_mini new file mode 100644 index 00000000000000..8b1c204760e040 --- /dev/null +++ b/boards/others/stm32f401_mini/Kconfig.stm32f401_mini @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F401_MINI + select SOC_STM32F401XC diff --git a/boards/arm/stm32f401_mini/board.cmake b/boards/others/stm32f401_mini/board.cmake similarity index 100% rename from boards/arm/stm32f401_mini/board.cmake rename to boards/others/stm32f401_mini/board.cmake diff --git a/boards/others/stm32f401_mini/board.yml b/boards/others/stm32f401_mini/board.yml new file mode 100644 index 00000000000000..b6ec3cd3af8ef4 --- /dev/null +++ b/boards/others/stm32f401_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f401_mini + vendor: others + socs: + - name: stm32f401xc diff --git a/boards/arm/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg b/boards/others/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg similarity index 100% rename from boards/arm/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg rename to boards/others/stm32f401_mini/doc/img/STM32_Mini_F401-1.jpg diff --git a/boards/others/stm32f401_mini/doc/index.rst b/boards/others/stm32f401_mini/doc/index.rst new file mode 100644 index 00000000000000..b24538f3137578 --- /dev/null +++ b/boards/others/stm32f401_mini/doc/index.rst @@ -0,0 +1,153 @@ +.. _stm32f401_mini: + +STM32 Mini F401 +############### + +Overview +******** + +The STM32 Mini F401 is an extremely low cost and bare-bones +development board featuring the STM32F401CC, see `STM32F401CC website`_. +More info about the board with schematics available `here `_ + +.. image:: img/STM32_Mini_F401-1.jpg + :align: center + :alt: STM32 Mini F401 + +Hardware +******** + +The STM32F401CC based board provides the following +hardware components: + +- STM32F401CCU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 256 KB Flash +- 64 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (4) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr stm32f401_mini board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/others/stm32f401_mini/stm32f401_mini_defconfig` + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- SW0 : PB2 (routed to BOOT1 dip switch) +- LED0 : PC13 + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 84MHz. + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin, which on this board +is a dip switch. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by setting the BOOT0 dip switch position to ON. Reset the board with the NRST button. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f401_mini + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F401CCU6-STM32-Mini-F401 + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F401CC website: + https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html diff --git a/boards/arm/stm32f401_mini/stm32f401_mini.dts b/boards/others/stm32f401_mini/stm32f401_mini.dts similarity index 100% rename from boards/arm/stm32f401_mini/stm32f401_mini.dts rename to boards/others/stm32f401_mini/stm32f401_mini.dts diff --git a/boards/arm/stm32f401_mini/stm32f401_mini.yaml b/boards/others/stm32f401_mini/stm32f401_mini.yaml similarity index 100% rename from boards/arm/stm32f401_mini/stm32f401_mini.yaml rename to boards/others/stm32f401_mini/stm32f401_mini.yaml diff --git a/boards/arm/stm32f401_mini/stm32f401_mini_defconfig b/boards/others/stm32f401_mini/stm32f401_mini_defconfig similarity index 86% rename from boards/arm/stm32f401_mini/stm32f401_mini_defconfig rename to boards/others/stm32f401_mini/stm32f401_mini_defconfig index cd8cbcfcad1e30..8f08a2bfe96c87 100644 --- a/boards/arm/stm32f401_mini/stm32f401_mini_defconfig +++ b/boards/others/stm32f401_mini/stm32f401_mini_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f401cc/support/openocd.cfg b/boards/others/stm32f401_mini/support/openocd.cfg similarity index 100% rename from boards/arm/blackpill_f401cc/support/openocd.cfg rename to boards/others/stm32f401_mini/support/openocd.cfg diff --git a/boards/panasonic/index.rst b/boards/panasonic/index.rst new file mode 100644 index 00000000000000..cc32d30559f860 --- /dev/null +++ b/boards/panasonic/index.rst @@ -0,0 +1,10 @@ +.. _boards-panasonic: + +Panasonic Corporation +##################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/pan1770_evb/Kconfig b/boards/panasonic/pan1770_evb/Kconfig similarity index 100% rename from boards/arm/pan1770_evb/Kconfig rename to boards/panasonic/pan1770_evb/Kconfig diff --git a/boards/panasonic/pan1770_evb/Kconfig.defconfig b/boards/panasonic/pan1770_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..8a91e35369a2c8 --- /dev/null +++ b/boards/panasonic/pan1770_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1770 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1770_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1770_EVB diff --git a/boards/panasonic/pan1770_evb/Kconfig.pan1770_evb b/boards/panasonic/pan1770_evb/Kconfig.pan1770_evb new file mode 100644 index 00000000000000..26aa94c1f71946 --- /dev/null +++ b/boards/panasonic/pan1770_evb/Kconfig.pan1770_evb @@ -0,0 +1,7 @@ +# PAN1770 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1770_EVB + select SOC_NRF52840_QIAA diff --git a/boards/arm/pan1770_evb/board.cmake b/boards/panasonic/pan1770_evb/board.cmake similarity index 100% rename from boards/arm/pan1770_evb/board.cmake rename to boards/panasonic/pan1770_evb/board.cmake diff --git a/boards/panasonic/pan1770_evb/board.yml b/boards/panasonic/pan1770_evb/board.yml new file mode 100644 index 00000000000000..0808b91b99b17e --- /dev/null +++ b/boards/panasonic/pan1770_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1770_evb + vendor: panasonic + socs: + - name: nrf52840 diff --git a/boards/arm/pan1770_evb/doc/index.rst b/boards/panasonic/pan1770_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1770_evb/doc/index.rst rename to boards/panasonic/pan1770_evb/doc/index.rst diff --git a/boards/arm/pan1770_evb/doc/pan1770_evaluation_board.jpg b/boards/panasonic/pan1770_evb/doc/pan1770_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1770_evb/doc/pan1770_evaluation_board.jpg rename to boards/panasonic/pan1770_evb/doc/pan1770_evaluation_board.jpg diff --git a/boards/arm/pan1770_evb/pan1770_evb-pinctrl.dtsi b/boards/panasonic/pan1770_evb/pan1770_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1770_evb/pan1770_evb-pinctrl.dtsi rename to boards/panasonic/pan1770_evb/pan1770_evb-pinctrl.dtsi diff --git a/boards/arm/pan1770_evb/pan1770_evb.dts b/boards/panasonic/pan1770_evb/pan1770_evb.dts similarity index 100% rename from boards/arm/pan1770_evb/pan1770_evb.dts rename to boards/panasonic/pan1770_evb/pan1770_evb.dts diff --git a/boards/arm/pan1770_evb/pan1770_evb.yaml b/boards/panasonic/pan1770_evb/pan1770_evb.yaml similarity index 100% rename from boards/arm/pan1770_evb/pan1770_evb.yaml rename to boards/panasonic/pan1770_evb/pan1770_evb.yaml diff --git a/boards/arm/pan1770_evb/pan1770_evb_defconfig b/boards/panasonic/pan1770_evb/pan1770_evb_defconfig similarity index 82% rename from boards/arm/pan1770_evb/pan1770_evb_defconfig rename to boards/panasonic/pan1770_evb/pan1770_evb_defconfig index 7fbc9b874080db..5d2537faace208 100644 --- a/boards/arm/pan1770_evb/pan1770_evb_defconfig +++ b/boards/panasonic/pan1770_evb/pan1770_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PAN1770_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52_vbluno52/pre_dt_board.cmake b/boards/panasonic/pan1770_evb/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52_vbluno52/pre_dt_board.cmake rename to boards/panasonic/pan1770_evb/pre_dt_board.cmake diff --git a/boards/arm/pan1780_evb/Kconfig b/boards/panasonic/pan1780_evb/Kconfig similarity index 100% rename from boards/arm/pan1780_evb/Kconfig rename to boards/panasonic/pan1780_evb/Kconfig diff --git a/boards/panasonic/pan1780_evb/Kconfig.defconfig b/boards/panasonic/pan1780_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..81bb7a60819b09 --- /dev/null +++ b/boards/panasonic/pan1780_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1780 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1780_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1780_EVB diff --git a/boards/panasonic/pan1780_evb/Kconfig.pan1780_evb b/boards/panasonic/pan1780_evb/Kconfig.pan1780_evb new file mode 100644 index 00000000000000..079b30fac68c41 --- /dev/null +++ b/boards/panasonic/pan1780_evb/Kconfig.pan1780_evb @@ -0,0 +1,7 @@ +# PAN1780 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1780_EVB + select SOC_NRF52840_QIAA diff --git a/boards/arm/pan1780_evb/board.cmake b/boards/panasonic/pan1780_evb/board.cmake similarity index 100% rename from boards/arm/pan1780_evb/board.cmake rename to boards/panasonic/pan1780_evb/board.cmake diff --git a/boards/panasonic/pan1780_evb/board.yml b/boards/panasonic/pan1780_evb/board.yml new file mode 100644 index 00000000000000..53a9a68192aa84 --- /dev/null +++ b/boards/panasonic/pan1780_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1780_evb + vendor: panasonic + socs: + - name: nrf52840 diff --git a/boards/arm/pan1780_evb/doc/index.rst b/boards/panasonic/pan1780_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1780_evb/doc/index.rst rename to boards/panasonic/pan1780_evb/doc/index.rst diff --git a/boards/arm/pan1780_evb/doc/pan1780_evaluation_board.jpg b/boards/panasonic/pan1780_evb/doc/pan1780_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1780_evb/doc/pan1780_evaluation_board.jpg rename to boards/panasonic/pan1780_evb/doc/pan1780_evaluation_board.jpg diff --git a/boards/arm/pan1780_evb/pan1780_evb-pinctrl.dtsi b/boards/panasonic/pan1780_evb/pan1780_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1780_evb/pan1780_evb-pinctrl.dtsi rename to boards/panasonic/pan1780_evb/pan1780_evb-pinctrl.dtsi diff --git a/boards/arm/pan1780_evb/pan1780_evb.dts b/boards/panasonic/pan1780_evb/pan1780_evb.dts similarity index 100% rename from boards/arm/pan1780_evb/pan1780_evb.dts rename to boards/panasonic/pan1780_evb/pan1780_evb.dts diff --git a/boards/arm/pan1780_evb/pan1780_evb.yaml b/boards/panasonic/pan1780_evb/pan1780_evb.yaml similarity index 100% rename from boards/arm/pan1780_evb/pan1780_evb.yaml rename to boards/panasonic/pan1780_evb/pan1780_evb.yaml diff --git a/boards/arm/pan1780_evb/pan1780_evb_defconfig b/boards/panasonic/pan1780_evb/pan1780_evb_defconfig similarity index 82% rename from boards/arm/pan1780_evb/pan1780_evb_defconfig rename to boards/panasonic/pan1780_evb/pan1780_evb_defconfig index 1bb9d720f521cb..16b6ca3b45033b 100644 --- a/boards/arm/pan1780_evb/pan1780_evb_defconfig +++ b/boards/panasonic/pan1780_evb/pan1780_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PAN1780_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52805/pre_dt_board.cmake b/boards/panasonic/pan1780_evb/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52805/pre_dt_board.cmake rename to boards/panasonic/pan1780_evb/pre_dt_board.cmake diff --git a/boards/arm/pan1781_evb/Kconfig b/boards/panasonic/pan1781_evb/Kconfig similarity index 100% rename from boards/arm/pan1781_evb/Kconfig rename to boards/panasonic/pan1781_evb/Kconfig diff --git a/boards/panasonic/pan1781_evb/Kconfig.defconfig b/boards/panasonic/pan1781_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..518676e36437fb --- /dev/null +++ b/boards/panasonic/pan1781_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1781 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1781_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1781_EVB diff --git a/boards/panasonic/pan1781_evb/Kconfig.pan1781_evb b/boards/panasonic/pan1781_evb/Kconfig.pan1781_evb new file mode 100644 index 00000000000000..e7253895d08aa9 --- /dev/null +++ b/boards/panasonic/pan1781_evb/Kconfig.pan1781_evb @@ -0,0 +1,7 @@ +# PAN1781 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1781_EVB + select SOC_NRF52820_QDAA diff --git a/boards/arm/pan1781_evb/board.cmake b/boards/panasonic/pan1781_evb/board.cmake similarity index 100% rename from boards/arm/pan1781_evb/board.cmake rename to boards/panasonic/pan1781_evb/board.cmake diff --git a/boards/panasonic/pan1781_evb/board.yml b/boards/panasonic/pan1781_evb/board.yml new file mode 100644 index 00000000000000..64a5a23996164f --- /dev/null +++ b/boards/panasonic/pan1781_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1781_evb + vendor: panasonic + socs: + - name: nrf52820 diff --git a/boards/arm/pan1781_evb/doc/index.rst b/boards/panasonic/pan1781_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1781_evb/doc/index.rst rename to boards/panasonic/pan1781_evb/doc/index.rst diff --git a/boards/arm/pan1781_evb/doc/pan1781_evaluation_board.jpg b/boards/panasonic/pan1781_evb/doc/pan1781_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1781_evb/doc/pan1781_evaluation_board.jpg rename to boards/panasonic/pan1781_evb/doc/pan1781_evaluation_board.jpg diff --git a/boards/arm/pan1781_evb/pan1781_evb-pinctrl.dtsi b/boards/panasonic/pan1781_evb/pan1781_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1781_evb/pan1781_evb-pinctrl.dtsi rename to boards/panasonic/pan1781_evb/pan1781_evb-pinctrl.dtsi diff --git a/boards/arm/pan1781_evb/pan1781_evb.dts b/boards/panasonic/pan1781_evb/pan1781_evb.dts similarity index 100% rename from boards/arm/pan1781_evb/pan1781_evb.dts rename to boards/panasonic/pan1781_evb/pan1781_evb.dts diff --git a/boards/arm/pan1781_evb/pan1781_evb.yaml b/boards/panasonic/pan1781_evb/pan1781_evb.yaml similarity index 100% rename from boards/arm/pan1781_evb/pan1781_evb.yaml rename to boards/panasonic/pan1781_evb/pan1781_evb.yaml diff --git a/boards/arm/pan1781_evb/pan1781_evb_defconfig b/boards/panasonic/pan1781_evb/pan1781_evb_defconfig similarity index 82% rename from boards/arm/pan1781_evb/pan1781_evb_defconfig rename to boards/panasonic/pan1781_evb/pan1781_evb_defconfig index 90e88bd4e1c59c..444314839f6cce 100644 --- a/boards/arm/pan1781_evb/pan1781_evb_defconfig +++ b/boards/panasonic/pan1781_evb/pan1781_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52820_QDAA=y -CONFIG_BOARD_PAN1781_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/pan1782_evb/Kconfig b/boards/panasonic/pan1782_evb/Kconfig similarity index 100% rename from boards/arm/pan1782_evb/Kconfig rename to boards/panasonic/pan1782_evb/Kconfig diff --git a/boards/panasonic/pan1782_evb/Kconfig.defconfig b/boards/panasonic/pan1782_evb/Kconfig.defconfig new file mode 100644 index 00000000000000..c9136006be489f --- /dev/null +++ b/boards/panasonic/pan1782_evb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# PAN1782 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PAN1782_EVB + +config BT_CTLR + default BT + +endif # BOARD_PAN1782_EVB diff --git a/boards/panasonic/pan1782_evb/Kconfig.pan1782_evb b/boards/panasonic/pan1782_evb/Kconfig.pan1782_evb new file mode 100644 index 00000000000000..d0a403f0380db6 --- /dev/null +++ b/boards/panasonic/pan1782_evb/Kconfig.pan1782_evb @@ -0,0 +1,7 @@ +# PAN1782 EVB configuration + +# Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1782_EVB + select SOC_NRF52833_QIAA diff --git a/boards/arm/pan1782_evb/board.cmake b/boards/panasonic/pan1782_evb/board.cmake similarity index 100% rename from boards/arm/pan1782_evb/board.cmake rename to boards/panasonic/pan1782_evb/board.cmake diff --git a/boards/panasonic/pan1782_evb/board.yml b/boards/panasonic/pan1782_evb/board.yml new file mode 100644 index 00000000000000..649e5507d825a8 --- /dev/null +++ b/boards/panasonic/pan1782_evb/board.yml @@ -0,0 +1,5 @@ +board: + name: pan1782_evb + vendor: panasonic + socs: + - name: nrf52833 diff --git a/boards/arm/pan1782_evb/doc/index.rst b/boards/panasonic/pan1782_evb/doc/index.rst similarity index 100% rename from boards/arm/pan1782_evb/doc/index.rst rename to boards/panasonic/pan1782_evb/doc/index.rst diff --git a/boards/arm/pan1782_evb/doc/pan1782_evaluation_board.jpg b/boards/panasonic/pan1782_evb/doc/pan1782_evaluation_board.jpg similarity index 100% rename from boards/arm/pan1782_evb/doc/pan1782_evaluation_board.jpg rename to boards/panasonic/pan1782_evb/doc/pan1782_evaluation_board.jpg diff --git a/boards/arm/pan1782_evb/pan1782_evb-pinctrl.dtsi b/boards/panasonic/pan1782_evb/pan1782_evb-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1782_evb/pan1782_evb-pinctrl.dtsi rename to boards/panasonic/pan1782_evb/pan1782_evb-pinctrl.dtsi diff --git a/boards/arm/pan1782_evb/pan1782_evb.dts b/boards/panasonic/pan1782_evb/pan1782_evb.dts similarity index 100% rename from boards/arm/pan1782_evb/pan1782_evb.dts rename to boards/panasonic/pan1782_evb/pan1782_evb.dts diff --git a/boards/arm/pan1782_evb/pan1782_evb.yaml b/boards/panasonic/pan1782_evb/pan1782_evb.yaml similarity index 100% rename from boards/arm/pan1782_evb/pan1782_evb.yaml rename to boards/panasonic/pan1782_evb/pan1782_evb.yaml diff --git a/boards/arm/pan1782_evb/pan1782_evb_defconfig b/boards/panasonic/pan1782_evb/pan1782_evb_defconfig similarity index 84% rename from boards/arm/pan1782_evb/pan1782_evb_defconfig rename to boards/panasonic/pan1782_evb/pan1782_evb_defconfig index 989049684167cb..af565be5cb1c07 100644 --- a/boards/arm/pan1782_evb/pan1782_evb_defconfig +++ b/boards/panasonic/pan1782_evb/pan1782_evb_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Panasonic Industrial Devices Europe GmbH # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_PAN1782_EVB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/panasonic/pan1783/CMakeLists.txt b/boards/panasonic/pan1783/CMakeLists.txt new file mode 100644 index 00000000000000..88360ce24f700f --- /dev/null +++ b/boards/panasonic/pan1783/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF5340_CPUAPP_QKAA AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(pan1783_nrf5340_cpunet_reset.c) +endif() diff --git a/boards/panasonic/pan1783/Kconfig b/boards/panasonic/pan1783/Kconfig new file mode 100644 index 00000000000000..671d17acad9ede --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig @@ -0,0 +1,56 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF5340_CPUAPP_QKAA + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "pan1783_evb/nrf5340/cpunet" if BOARD_PAN1783_EVB_NRF5340_CPUAPP + default "pan1783a_evb/nrf5340/cpunet" if BOARD_PAN1783A_EVB_NRF5340_CPUAPP + default "pan1783a_pa_evb/nrf5340/cpunet" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # SOC_NRF5340_CPUAPP_QKAA + +config DOMAIN_CPUAPP_BOARD + string + default "pan1783_evb/nrf5340/cpuapp" if BOARD_PAN1783_EVB_NRF5340_CPUNET + default "pan1783a_evb/nrf5340/cpuapp" if BOARD_PAN1783A_EVB_NRF5340_CPUNET + default "pan1783a_pa_evb/nrf5340/cpuapp" if BOARD_PAN1783A_PA_EVB_NRF5340_CPUNET + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. diff --git a/boards/panasonic/pan1783/Kconfig.defconfig b/boards/panasonic/pan1783/Kconfig.defconfig new file mode 100644 index 00000000000000..ec08e860bbde52 --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.defconfig @@ -0,0 +1,26 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config MBOX_NRFX_IPC + default MBOX + +if SOC_NRF5340_CPUAPP_QKAA + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # SOC_NRF5340_CPUAPP_QKAA + +if SOC_NRF5340_CPUNET_QKAA + +config BT_CTLR + default y if BT + +endif # SOC_NRF5340_CPUNET_QKAA diff --git a/boards/panasonic/pan1783/Kconfig.pan1783_evb b/boards/panasonic/pan1783/Kconfig.pan1783_evb new file mode 100644 index 00000000000000..7476162e39a617 --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.pan1783_evb @@ -0,0 +1,8 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1783_EVB + select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783_EVB_NRF5340_CPUAPP + select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783_EVB_NRF5340_CPUNET diff --git a/boards/panasonic/pan1783/Kconfig.pan1783a_evb b/boards/panasonic/pan1783/Kconfig.pan1783a_evb new file mode 100644 index 00000000000000..f7b2b005a69eb7 --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.pan1783a_evb @@ -0,0 +1,8 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1783A_EVB + select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783A_EVB_NRF5340_CPUAPP + select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783A_EVB_NRF5340_CPUNET diff --git a/boards/panasonic/pan1783/Kconfig.pan1783a_pa_evb b/boards/panasonic/pan1783/Kconfig.pan1783a_pa_evb new file mode 100644 index 00000000000000..46a47ca0f67d33 --- /dev/null +++ b/boards/panasonic/pan1783/Kconfig.pan1783a_pa_evb @@ -0,0 +1,8 @@ +# PAN1783 EVB board configuration + +# Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PAN1783A_PA_EVB + select SOC_NRF5340_CPUAPP_QKAA if BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP + select SOC_NRF5340_CPUNET_QKAA if BOARD_PAN1783A_PA_EVB_NRF5340_CPUNET diff --git a/boards/panasonic/pan1783/board.cmake b/boards/panasonic/pan1783/board.cmake new file mode 100644 index 00000000000000..1a211bc95c9fbd --- /dev/null +++ b/boards/panasonic/pan1783/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF5340_CPUAPP_QKAA) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +endif() + +if(CONFIG_SOC_NRF5340_CPUNET_QKAA) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/panasonic/pan1783/board.yml b/boards/panasonic/pan1783/board.yml new file mode 100644 index 00000000000000..461763d86f2b72 --- /dev/null +++ b/boards/panasonic/pan1783/board.yml @@ -0,0 +1,13 @@ +boards: +- name: pan1783_evb + vendor: panasonic + socs: + - name: nrf5340 +- name: pan1783a_evb + vendor: panasonic + socs: + - name: nrf5340 +- name: pan1783a_pa_evb + vendor: panasonic + socs: + - name: nrf5340 diff --git a/boards/arm/pan1783/doc/img/pan1783_evb.webp b/boards/panasonic/pan1783/doc/img/pan1783_evb.webp similarity index 100% rename from boards/arm/pan1783/doc/img/pan1783_evb.webp rename to boards/panasonic/pan1783/doc/img/pan1783_evb.webp diff --git a/boards/arm/pan1783/doc/index.rst b/boards/panasonic/pan1783/doc/index.rst similarity index 100% rename from boards/arm/pan1783/doc/index.rst rename to boards/panasonic/pan1783/doc/index.rst diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts new file mode 100644 index 00000000000000..27bfbbc52e98c3 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Panasonic PAN1783 EVB (NRF5340) Application"; + compatible = "panasonic,pan1783-evb-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + }; +}; diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000000..401745b33336bc --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml @@ -0,0 +1,21 @@ +identifier: pan1783_evb/nrf5340/cpuapp +name: PAN1783-EVB-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usb_cdc + - usb_device + - netif:openthread + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..f158f01995ffb3 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts new file mode 100644 index 00000000000000..28feb6d660faa4 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpunet_common.dtsi" + +/ { + model = "Panasonic PAN1783 EVB (NRF5340) Network"; + compatible = "panasonic,pan1783-evb-cpunet"; + + chosen { + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + }; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml new file mode 100644 index 00000000000000..510ceef5691b80 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml @@ -0,0 +1,14 @@ +identifier: pan1783_evb/nrf5340/cpunet +name: PAN1783-EVB-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - watchdog + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..71784075dfd7b4 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pan1783_cpuapp_common-pinctrl.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1783/pan1783_cpuapp_common-pinctrl.dtsi rename to boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi new file mode 100644 index 00000000000000..fae7f566fccfe5 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_common.dtsi @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "pan1783_nrf5340_cpuapp_common-pinctrl.dtsi" +#include + +/ { + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci-ipc = &ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + evb_led1: evb_led_1 { + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + label = "LED1 on EVB"; + }; + evb_led2: evb_led_2 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "LED2 on EVB"; + }; + evb_led3: evb_led_3 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "LED3 on EVB"; + }; + evb_led4: evb_led_4 { + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + label = "LED4 on EVB"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_evb_led1: pwm_evb_led_1 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + evb_sw1: evb_sw_1 { + gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1 on EVB"; + zephyr,code = ; + }; + evb_sw2: evb_sw_2 { + gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2 on EVB"; + zephyr,code = ; + }; + evb_sw3: evb_sw_3 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3 on EVB"; + zephyr,code = ; + }; + evb_sw4: evb_sw_4 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW4 on EVB"; + zephyr,code = ; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* AN */ + /* Not a GPIO*/ /* RST */ + <2 0 &gpio1 12 0>, /* CS */ + <3 0 &gpio1 15 0>, /* SCK */ + <4 0 &gpio1 14 0>, /* MISO */ + <5 0 &gpio1 13 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpio1 7 0>, /* PWM */ + <7 0 &gpio1 4 0>, /* INT */ + <8 0 &gpio1 0 0>, /* RX */ + <9 0 &gpio1 1 0>, /* TX */ + <10 0 &gpio1 3 0>, /* SCL */ + <11 0 &gpio1 2 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 6 0>, /* A2 */ + <3 0 &gpio0 7 0>, /* A3 */ + <4 0 &gpio0 25 0>, /* A4 */ + <5 0 &gpio0 26 0>, /* A5 */ + <6 0 &gpio1 0 0>, /* D0 */ + <7 0 &gpio1 1 0>, /* D1 */ + <8 0 &gpio1 4 0>, /* D2 */ + <9 0 &gpio1 5 0>, /* D3 */ + <10 0 &gpio1 6 0>, /* D4 */ + <11 0 &gpio1 7 0>, /* D5 */ + <12 0 &gpio1 8 0>, /* D6 */ + <13 0 &gpio1 9 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio1 2 0>, /* D14 */ + <21 0 &gpio1 3 0>; /* D15 */ + }; + + arduino_adc: analog-connector { + compatible = "arduino,uno-adc"; + #io-channel-cells = <1>; + io-channel-map = <0 &adc 0>, /* A0 = P0.4 = AIN0 */ + <1 &adc 1>, /* A1 = P0.5 = AIN1 */ + <2 &adc 2>, /* A2 = P0.6 = AIN2 */ + <3 &adc 3>, /* A3 = P0.7 = AIN3 */ + <4 &adc 4>, /* A4 = P0.25 = AIN4 */ + <5 &adc 5>; /* A5 = P0.26 = AIN5 */ + }; + + gpio_fwd: nrf-gpio-forwarder { + compatible = "nordic,nrf-gpio-forwarder"; + status = "disabled"; + uart { + gpios = <&gpio0 20 0>, <&gpio0 22 0>, <&gpio0 11 0>, <&gpio0 10 0>; + }; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &evb_led1; + led1 = &evb_led2; + led2 = &evb_led3; + led3 = &evb_led4; + pwm-led0 = &pwm_evb_led1; + sw0 = &evb_sw1; + sw1 = &evb_sw2; + sw2 = &evb_sw3; + sw3 = &evb_sw4; + bootloader-led0 = &evb_led1; + mcuboot-button0 = &evb_sw1; + mcuboot-led0 = &evb_led1; + watchdog0 = &wdt0; + spi-flash0 = &mx25r64; + }; +}; + +&adc { + status = "okay"; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c1 { + compatible = "nordic,nrf-twim"; + status = "okay"; + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { + compatible = "nordic,qspi-nor"; + reg = <0>; + /* MX25R64 supports only pp and pp4io */ + writeoc = "pp4io"; + /* MX25R64 supports all readoc options */ + readoc = "read4io"; + sck-frequency = <8000000>; + jedec-id = [ c2 28 17 ]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +arduino_serial: &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_i2c: &i2c1 {}; + +arduino_spi: &spi4 { + compatible = "nordic,nrf-spim"; + status = "okay"; + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + pinctrl-0 = <&spi4_default>; + pinctrl-1 = <&spi4_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash0 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + }; + slot0_partition: partition@10000 { + label = "image-0"; + }; + slot1_partition: partition@80000 { + label = "image-1"; + }; + /* 0xf0000 to 0xf7fff reserved for TF-M partitions */ + storage_partition: partition@f8000 { + label = "storage"; + reg = <0x000f8000 0x00008000>; + }; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; + +/ { + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram0_image: image@20000000 { + /* Zephyr image(s) memory */ + }; + + sram0_s: image_s@20000000 { + /* Secure image memory */ + }; + }; +}; + +/* Include partition configuration file */ +#include "pan1783_nrf5340_cpuapp_partition_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi new file mode 100644 index 00000000000000..a6edad09bba820 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpuapp_partition_conf.dtsi @@ -0,0 +1,38 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* + * Default Flash planning for pan1783_evb CPUAPP (Application MCU). + * + * Secure image will be placed, by default, in flash0 + * (or in slot0, if MCUboot is present). + * Secure image will use sram0 for system memory. + * + */ + +&slot0_partition { + reg = <0x00010000 0x40000>; +}; + +&slot1_partition { + reg = <0x00080000 0x40000>; +}; + +/* Default SRAM planning when building for nRF5340 + * - Lowest 448 kB SRAM allocated to Secure image (sram0_s) + * - Upper 64 kB SRAM allocated as Shared memory (sram0_shared) + * (see shared_sram_planning_conf.dtsi) + */ +&sram0_image { + reg = <0x20000000 DT_SIZE_K(448)>; +}; + +&sram0_s { + reg = <0x20000000 0x70000>; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/arm/pan1783/pan1783_cpunet-pinctrl.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/pan1783/pan1783_cpunet-pinctrl.dtsi rename to boards/panasonic/pan1783/pan1783_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi new file mode 100644 index 00000000000000..a23b1d87b1089f --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_common.dtsi @@ -0,0 +1,207 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "pan1783_nrf5340_cpunet-pinctrl.dtsi" +#include + +/ { + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,bt-hci-ipc = &ipc0; + nordic,802154-spinel-ipc = &ipc0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + evb_led1: evb_led_1 { + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + label = "LED1 on EVB"; + }; + evb_led2: evb_led_2 { + gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; + label = "LED2 on EVB"; + }; + evb_led3: evb_led_3 { + gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + label = "LED3 on EVB"; + }; + evb_led4: evb_led_4 { + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + label = "LED4 on EVB"; + }; + }; + + buttons { + compatible = "gpio-keys"; + evb_sw1: evb_sw_1 { + gpios = <&gpio0 23 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW1 on EVB"; + zephyr,code = ; + }; + evb_sw2: evb_sw_2 { + gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW2 on EVB"; + zephyr,code = ; + }; + evb_sw3: evb_sw_3 { + gpios = <&gpio0 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW3 on EVB"; + zephyr,code = ; + }; + evb_sw4: evb_sw_4 { + gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "SW4 on EVB"; + zephyr,code = ; + }; + }; + + mikrobus_header: mikrobus-connector { + compatible = "mikro-bus"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* AN */ + /* Not a GPIO*/ /* RST */ + <2 0 &gpio1 12 0>, /* CS */ + <3 0 &gpio1 15 0>, /* SCK */ + <4 0 &gpio1 14 0>, /* MISO */ + <5 0 &gpio1 13 0>, /* MOSI */ + /* +3.3V */ + /* GND */ + <6 0 &gpio1 7 0>, /* PWM */ + <7 0 &gpio1 4 0>, /* INT */ + <8 0 &gpio1 0 0>, /* RX */ + <9 0 &gpio1 1 0>, /* TX */ + <10 0 &gpio1 3 0>, /* SCL */ + <11 0 &gpio1 2 0>; /* SDA */ + /* +5V */ + /* GND */ + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 4 0>, /* A0 */ + <1 0 &gpio0 5 0>, /* A1 */ + <2 0 &gpio0 6 0>, /* A2 */ + <3 0 &gpio0 7 0>, /* A3 */ + <4 0 &gpio0 25 0>, /* A4 */ + <5 0 &gpio0 26 0>, /* A5 */ + <6 0 &gpio1 0 0>, /* D0 */ + <7 0 &gpio1 1 0>, /* D1 */ + <8 0 &gpio1 4 0>, /* D2 */ + <9 0 &gpio1 5 0>, /* D3 */ + <10 0 &gpio1 6 0>, /* D4 */ + <11 0 &gpio1 7 0>, /* D5 */ + <12 0 &gpio1 8 0>, /* D6 */ + <13 0 &gpio1 9 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio1 2 0>, /* D14 */ + <21 0 &gpio1 3 0>; /* D15 */ + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &evb_led1; + led1 = &evb_led2; + led2 = &evb_led3; + led3 = &evb_led4; + sw0 = &evb_sw1; + sw1 = &evb_sw2; + sw2 = &evb_sw3; + sw3 = &evb_sw4; + bootloader-led0 = &evb_led1; + mcuboot-button0 = &evb_sw1; + mcuboot-led0 = &evb_led1; + watchdog0 = &wdt0; + }; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&uart0 { + status = "disabled"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_serial: &uart0 {}; + +arduino_i2c: &i2c0 { + compatible = "nordic,nrf-twim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_spi: &spi0 { + compatible = "nordic,nrf-spim"; + /* Cannot be used together with uart0. */ + /* status = "okay"; */ + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&flash1 { + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0xc000>; + }; + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000C000 0x17000>; + }; + slot1_partition: partition@23000 { + label = "image-1"; + reg = <0x00023000 0x17000>; + }; + storage_partition: partition@3a000 { + label = "storage"; + reg = <0x0003a000 0x6000>; + }; + }; +}; + +&ieee802154 { + status = "okay"; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c new file mode 100644 index 00000000000000..bf0626ce30b2ec --- /dev/null +++ b/boards/panasonic/pan1783/pan1783_nrf5340_cpunet_reset.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + +#include +#include + +#if defined(CONFIG_BOARD_PAN1783_EVB_NRF5340_CPUAPP) +LOG_MODULE_REGISTER(pan1783_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); +#elif defined(CONFIG_BOARD_PAN1783A_EVB_NRF5340_CPUAPP) +LOG_MODULE_REGISTER(pan1783a_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); +#elif defined(CONFIG_BOARD_PAN1783A_PA_EVB_NRF5340_CPUAPP) +LOG_MODULE_REGISTER(pan1783a_pa_evb_cpuapp, CONFIG_LOG_DEFAULT_LEVEL); +#else +#error "No board selected!" +#endif + +#if defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) +#include <../subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h> +#else +#define DEBUG_SETUP() +#endif + +static void remoteproc_mgr_config(void) +{ + /* Route Bluetooth Controller Debug Pins */ + DEBUG_SETUP(); + + /* Retain nRF5340 Network MCU */ + NRF_SPU->EXTDOMAIN[0].PERM = 1 << 4; +} + +static int remoteproc_mgr_boot(void) +{ + /* Configure permissions for the Network MCU. */ + remoteproc_mgr_config(); + + /* Release the Network MCU, 'Release force off signal' */ + nrf_reset_network_force_off(NRF_RESET, false); + + LOG_DBG("Network MCU released."); + + return 0; +} + +SYS_INIT(remoteproc_mgr_boot, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE); diff --git a/boards/arm/pan1783/pan1783_shared_sram_planning_conf.dtsi b/boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi similarity index 100% rename from boards/arm/pan1783/pan1783_shared_sram_planning_conf.dtsi rename to boards/panasonic/pan1783/pan1783_nrf5340_shared_sram_planning_conf.dtsi diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts new file mode 100644 index 00000000000000..b47b14510fe0bf --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.dts @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Panasonic PAN1783A EVB (NRF5340) Application"; + compatible = "panasonic,pan1783a-evb-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + }; +}; diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000000..f5a789788bfc24 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml @@ -0,0 +1,21 @@ +identifier: pan1783a_evb/nrf5340/cpuapp +name: PAN1783A-EVB-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usb_cdc + - usb_device + - netif:openthread + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp_defconfig b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..f158f01995ffb3 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts new file mode 100644 index 00000000000000..44d61d69c25aa8 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.dts @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpunet_common.dtsi" + +/ { + model = "Panasonic PAN1783A EVB (NRF5340) Network"; + compatible = "panasonic,pan1783a-evb-cpunet"; + + chosen { + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + }; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml new file mode 100644 index 00000000000000..4904371041c7f6 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml @@ -0,0 +1,14 @@ +identifier: pan1783a_evb/nrf5340/cpunet +name: PAN1783A-EVB-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - watchdog + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet_defconfig b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..71784075dfd7b4 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts new file mode 100644 index 00000000000000..1bddfdb986292f --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.dts @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpuapp_common.dtsi" + +/ { + model = "Panasonic PAN1783A-PA EVB (NRF5340) Application"; + compatible = "panasonic,pan1783a_pa-evb-cpuapp"; + + chosen { + zephyr,sram = &sram0_image; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,sram-secure-partition = &sram0_s; + }; +}; + +&gpio_fwd { + /delete-node/ uart; + + status = "okay"; + fem { + gpios = <&gpio0 19 0>, <&gpio0 21 0>; + }; +}; diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml new file mode 100644 index 00000000000000..dc5600a999a57f --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml @@ -0,0 +1,21 @@ +identifier: pan1783a_pa_evb/nrf5340/cpuapp +name: PAN1783A-PA-EVB-application-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 448 +flash: 1024 +supported: + - gpio + - i2c + - i2s + - pwm + - watchdog + - usb_cdc + - usb_device + - netif:openthread + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp_defconfig b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..f158f01995ffb3 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts new file mode 100644 index 00000000000000..4856deaa3a16bd --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.dts @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2023 Panasonic Industrial Devices Europe GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include "pan1783_nrf5340_cpunet_common.dtsi" + +/ { + model = "Panasonic PAN1783A-PA EVB (NRF5340) Network"; + compatible = "panasonic,pan1783a_pa-evb-cpunet"; + + chosen { + zephyr,sram = &sram1; + zephyr,flash = &flash1; + zephyr,code-partition = &slot0_partition; + }; + + nrf_radio_fem: fem_node { + compatible = "skyworks,sky66407-11", "generic-fem-two-ctrl-pins"; + ctx-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; + crx-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; + }; +}; + +&radio { + fem = <&nrf_radio_fem>; +}; + +/* Include shared RAM configuration file */ +#include "pan1783_nrf5340_shared_sram_planning_conf.dtsi" diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml new file mode 100644 index 00000000000000..14ff8c16914ddb --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml @@ -0,0 +1,14 @@ +identifier: pan1783a_pa_evb/nrf5340/cpunet +name: PAN1783A-PA-EVB-network-MCU +type: mcu +arch: arm +toolchain: + - gnuarmemb + - xtools + - zephyr +ram: 64 +flash: 256 +supported: + - watchdog + - gpio +vendor: panasonic diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..71784075dfd7b4 --- /dev/null +++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Clock config +CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=n diff --git a/boards/arm/pan1783/pre_dt_board.cmake b/boards/panasonic/pan1783/pre_dt_board.cmake similarity index 100% rename from boards/arm/pan1783/pre_dt_board.cmake rename to boards/panasonic/pan1783/pre_dt_board.cmake diff --git a/boards/arm/particle_argon/CMakeLists.txt b/boards/particle/argon/CMakeLists.txt similarity index 100% rename from boards/arm/particle_argon/CMakeLists.txt rename to boards/particle/argon/CMakeLists.txt diff --git a/boards/arm/particle_argon/Kconfig b/boards/particle/argon/Kconfig similarity index 100% rename from boards/arm/particle_argon/Kconfig rename to boards/particle/argon/Kconfig diff --git a/boards/particle/argon/Kconfig.defconfig b/boards/particle/argon/Kconfig.defconfig new file mode 100644 index 00000000000000..72954154c71f8d --- /dev/null +++ b/boards/particle/argon/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Particle Argon board configuration + +# Copyright (c) 2018 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PARTICLE_ARGON + +config BT_CTLR + default BT + +endif # BOARD_PARTICLE_ARGON diff --git a/boards/particle/argon/Kconfig.particle_argon b/boards/particle/argon/Kconfig.particle_argon new file mode 100644 index 00000000000000..3a056b673b6731 --- /dev/null +++ b/boards/particle/argon/Kconfig.particle_argon @@ -0,0 +1,7 @@ +# Particle Argon configuration + +# Copyright (c) 2018 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PARTICLE_ARGON + select SOC_NRF52840_QIAA diff --git a/boards/arm/particle_argon/board.c b/boards/particle/argon/board.c similarity index 100% rename from boards/arm/particle_argon/board.c rename to boards/particle/argon/board.c diff --git a/boards/arm/particle_argon/board.cmake b/boards/particle/argon/board.cmake similarity index 100% rename from boards/arm/particle_argon/board.cmake rename to boards/particle/argon/board.cmake diff --git a/boards/particle/argon/board.yml b/boards/particle/argon/board.yml new file mode 100644 index 00000000000000..08eadfda743b72 --- /dev/null +++ b/boards/particle/argon/board.yml @@ -0,0 +1,5 @@ +board: + name: particle_argon + vendor: particle + socs: + - name: nrf52840 diff --git a/boards/arm/particle_argon/doc/img/particle_argon.jpg b/boards/particle/argon/doc/img/particle_argon.jpg similarity index 100% rename from boards/arm/particle_argon/doc/img/particle_argon.jpg rename to boards/particle/argon/doc/img/particle_argon.jpg diff --git a/boards/arm/particle_argon/doc/index.rst b/boards/particle/argon/doc/index.rst similarity index 100% rename from boards/arm/particle_argon/doc/index.rst rename to boards/particle/argon/doc/index.rst diff --git a/boards/arm/particle_argon/dts/mesh_feather-pinctrl.dtsi b/boards/particle/argon/dts/mesh_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather-pinctrl.dtsi rename to boards/particle/argon/dts/mesh_feather-pinctrl.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather.dtsi b/boards/particle/argon/dts/mesh_feather.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather.dtsi rename to boards/particle/argon/dts/mesh_feather.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_i2c1_twi1.dtsi b/boards/particle/argon/dts/mesh_feather_i2c1_twi1.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_i2c1_twi1.dtsi rename to boards/particle/argon/dts/mesh_feather_i2c1_twi1.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_spi1_spi3.dtsi b/boards/particle/argon/dts/mesh_feather_spi1_spi3.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_spi1_spi3.dtsi rename to boards/particle/argon/dts/mesh_feather_spi1_spi3.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_spi_spi1.dtsi b/boards/particle/argon/dts/mesh_feather_spi_spi1.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_spi_spi1.dtsi rename to boards/particle/argon/dts/mesh_feather_spi_spi1.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_spi_spi3.dtsi b/boards/particle/argon/dts/mesh_feather_spi_spi3.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_spi_spi3.dtsi rename to boards/particle/argon/dts/mesh_feather_spi_spi3.dtsi diff --git a/boards/arm/particle_argon/dts/mesh_feather_uart1_rtscts.dtsi b/boards/particle/argon/dts/mesh_feather_uart1_rtscts.dtsi similarity index 100% rename from boards/arm/particle_argon/dts/mesh_feather_uart1_rtscts.dtsi rename to boards/particle/argon/dts/mesh_feather_uart1_rtscts.dtsi diff --git a/boards/arm/particle_argon/particle_argon-pinctrl.dtsi b/boards/particle/argon/particle_argon-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_argon/particle_argon-pinctrl.dtsi rename to boards/particle/argon/particle_argon-pinctrl.dtsi diff --git a/boards/arm/particle_argon/particle_argon.dts b/boards/particle/argon/particle_argon.dts similarity index 100% rename from boards/arm/particle_argon/particle_argon.dts rename to boards/particle/argon/particle_argon.dts diff --git a/boards/arm/particle_argon/particle_argon.yaml b/boards/particle/argon/particle_argon.yaml similarity index 100% rename from boards/arm/particle_argon/particle_argon.yaml rename to boards/particle/argon/particle_argon.yaml diff --git a/boards/arm/particle_argon/particle_argon_defconfig b/boards/particle/argon/particle_argon_defconfig similarity index 76% rename from boards/arm/particle_argon/particle_argon_defconfig rename to boards/particle/argon/particle_argon_defconfig index 5f3f7a7e2b5348..78464adc4aaef8 100644 --- a/boards/arm/particle_argon/particle_argon_defconfig +++ b/boards/particle/argon/particle_argon_defconfig @@ -4,10 +4,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PARTICLE_ARGON=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52810/pre_dt_board.cmake b/boards/particle/argon/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52810/pre_dt_board.cmake rename to boards/particle/argon/pre_dt_board.cmake diff --git a/boards/arm/particle_boron/CMakeLists.txt b/boards/particle/boron/CMakeLists.txt similarity index 100% rename from boards/arm/particle_boron/CMakeLists.txt rename to boards/particle/boron/CMakeLists.txt diff --git a/boards/arm/particle_boron/Kconfig b/boards/particle/boron/Kconfig similarity index 100% rename from boards/arm/particle_boron/Kconfig rename to boards/particle/boron/Kconfig diff --git a/boards/particle/boron/Kconfig.defconfig b/boards/particle/boron/Kconfig.defconfig new file mode 100644 index 00000000000000..cce1a36897fae5 --- /dev/null +++ b/boards/particle/boron/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Particle Boron board configuration + +# Copyright (c) 2018 Peter Bigot Consulting, LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PARTICLE_BORON + +config BT_CTLR + default BT + +if MODEM + +config MODEM_UBLOX_SARA + default y + +choice MODEM_UBLOX_SARA_VARIANT + default MODEM_UBLOX_SARA_R4 +endchoice + +config UART_INTERRUPT_DRIVEN + default y + +endif # MODEM + +endif # BOARD_PARTICLE_BORON diff --git a/boards/particle/boron/Kconfig.particle_boron b/boards/particle/boron/Kconfig.particle_boron new file mode 100644 index 00000000000000..d5a1d5be0fb261 --- /dev/null +++ b/boards/particle/boron/Kconfig.particle_boron @@ -0,0 +1,7 @@ +# Particle Boron configuration + +# Copyright (c) 2018 Peter Bigot Consulting, LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PARTICLE_BORON + select SOC_NRF52840_QIAA diff --git a/boards/arm/particle_boron/board.c b/boards/particle/boron/board.c similarity index 100% rename from boards/arm/particle_boron/board.c rename to boards/particle/boron/board.c diff --git a/boards/arm/particle_boron/board.cmake b/boards/particle/boron/board.cmake similarity index 100% rename from boards/arm/particle_boron/board.cmake rename to boards/particle/boron/board.cmake diff --git a/boards/particle/boron/board.yml b/boards/particle/boron/board.yml new file mode 100644 index 00000000000000..bb77655e8c01f2 --- /dev/null +++ b/boards/particle/boron/board.yml @@ -0,0 +1,5 @@ +board: + name: particle_boron + vendor: particle + socs: + - name: nrf52840 diff --git a/boards/arm/particle_boron/doc/img/particle_boron.jpg b/boards/particle/boron/doc/img/particle_boron.jpg similarity index 100% rename from boards/arm/particle_boron/doc/img/particle_boron.jpg rename to boards/particle/boron/doc/img/particle_boron.jpg diff --git a/boards/arm/particle_boron/doc/index.rst b/boards/particle/boron/doc/index.rst similarity index 100% rename from boards/arm/particle_boron/doc/index.rst rename to boards/particle/boron/doc/index.rst diff --git a/boards/arm/particle_boron/dts/mesh_feather-pinctrl.dtsi b/boards/particle/boron/dts/mesh_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather-pinctrl.dtsi rename to boards/particle/boron/dts/mesh_feather-pinctrl.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather.dtsi b/boards/particle/boron/dts/mesh_feather.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather.dtsi rename to boards/particle/boron/dts/mesh_feather.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather_spi1_spi3.dtsi b/boards/particle/boron/dts/mesh_feather_spi1_spi3.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather_spi1_spi3.dtsi rename to boards/particle/boron/dts/mesh_feather_spi1_spi3.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather_spi_spi3.dtsi b/boards/particle/boron/dts/mesh_feather_spi_spi3.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather_spi_spi3.dtsi rename to boards/particle/boron/dts/mesh_feather_spi_spi3.dtsi diff --git a/boards/arm/particle_boron/dts/mesh_feather_uart1_rtscts.dtsi b/boards/particle/boron/dts/mesh_feather_uart1_rtscts.dtsi similarity index 100% rename from boards/arm/particle_boron/dts/mesh_feather_uart1_rtscts.dtsi rename to boards/particle/boron/dts/mesh_feather_uart1_rtscts.dtsi diff --git a/boards/arm/particle_boron/particle_boron-pinctrl.dtsi b/boards/particle/boron/particle_boron-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_boron/particle_boron-pinctrl.dtsi rename to boards/particle/boron/particle_boron-pinctrl.dtsi diff --git a/boards/arm/particle_boron/particle_boron.dts b/boards/particle/boron/particle_boron.dts similarity index 100% rename from boards/arm/particle_boron/particle_boron.dts rename to boards/particle/boron/particle_boron.dts diff --git a/boards/arm/particle_boron/particle_boron.yaml b/boards/particle/boron/particle_boron.yaml similarity index 100% rename from boards/arm/particle_boron/particle_boron.yaml rename to boards/particle/boron/particle_boron.yaml diff --git a/boards/arm/particle_boron/particle_boron_defconfig b/boards/particle/boron/particle_boron_defconfig similarity index 83% rename from boards/arm/particle_boron/particle_boron_defconfig rename to boards/particle/boron/particle_boron_defconfig index 453981d2a6437f..b2fb4cb49c51a8 100644 --- a/boards/arm/particle_boron/particle_boron_defconfig +++ b/boards/particle/boron/particle_boron_defconfig @@ -3,10 +3,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_PARTICLE_BORON=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nrf52dk_nrf52832/pre_dt_board.cmake b/boards/particle/boron/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf52dk_nrf52832/pre_dt_board.cmake rename to boards/particle/boron/pre_dt_board.cmake diff --git a/boards/particle/index.rst b/boards/particle/index.rst new file mode 100644 index 00000000000000..c5bf20bb5c8633 --- /dev/null +++ b/boards/particle/index.rst @@ -0,0 +1,10 @@ +.. _boards-particle: + +Particle Industries +################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/particle/nrf51_blenano/Kconfig.defconfig b/boards/particle/nrf51_blenano/Kconfig.defconfig new file mode 100644 index 00000000000000..fb61b031143103 --- /dev/null +++ b/boards/particle/nrf51_blenano/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 BLENANO board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51_BLENANO + +config BT_CTLR + default BT + +endif # BOARD_NRF51_BLENANO diff --git a/boards/particle/nrf51_blenano/Kconfig.nrf51_blenano b/boards/particle/nrf51_blenano/Kconfig.nrf51_blenano new file mode 100644 index 00000000000000..19888cdc2029ed --- /dev/null +++ b/boards/particle/nrf51_blenano/Kconfig.nrf51_blenano @@ -0,0 +1,7 @@ +# nRF51 BLENANO board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51_BLENANO + select SOC_NRF51822_QFAA diff --git a/boards/arm/nrf51_blenano/board.cmake b/boards/particle/nrf51_blenano/board.cmake similarity index 100% rename from boards/arm/nrf51_blenano/board.cmake rename to boards/particle/nrf51_blenano/board.cmake diff --git a/boards/particle/nrf51_blenano/board.yml b/boards/particle/nrf51_blenano/board.yml new file mode 100644 index 00000000000000..bc651160fa41d8 --- /dev/null +++ b/boards/particle/nrf51_blenano/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51_blenano + vendor: particle + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51_blenano/doc/img/daplink.jpg b/boards/particle/nrf51_blenano/doc/img/daplink.jpg similarity index 100% rename from boards/arm/nrf51_blenano/doc/img/daplink.jpg rename to boards/particle/nrf51_blenano/doc/img/daplink.jpg diff --git a/boards/arm/nrf51_blenano/doc/img/nrf51_blenano.jpg b/boards/particle/nrf51_blenano/doc/img/nrf51_blenano.jpg similarity index 100% rename from boards/arm/nrf51_blenano/doc/img/nrf51_blenano.jpg rename to boards/particle/nrf51_blenano/doc/img/nrf51_blenano.jpg diff --git a/boards/arm/nrf51_blenano/doc/index.rst b/boards/particle/nrf51_blenano/doc/index.rst similarity index 100% rename from boards/arm/nrf51_blenano/doc/index.rst rename to boards/particle/nrf51_blenano/doc/index.rst diff --git a/boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422-pinctrl.dtsi b/boards/particle/nrf51_blenano/nrf51_blenano-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/nrf51dongle_nrf51422-pinctrl.dtsi rename to boards/particle/nrf51_blenano/nrf51_blenano-pinctrl.dtsi diff --git a/boards/arm/nrf51_blenano/nrf51_blenano.dts b/boards/particle/nrf51_blenano/nrf51_blenano.dts similarity index 100% rename from boards/arm/nrf51_blenano/nrf51_blenano.dts rename to boards/particle/nrf51_blenano/nrf51_blenano.dts diff --git a/boards/arm/nrf51_blenano/nrf51_blenano.yaml b/boards/particle/nrf51_blenano/nrf51_blenano.yaml similarity index 100% rename from boards/arm/nrf51_blenano/nrf51_blenano.yaml rename to boards/particle/nrf51_blenano/nrf51_blenano.yaml diff --git a/boards/particle/nrf51_blenano/nrf51_blenano_defconfig b/boards/particle/nrf51_blenano/nrf51_blenano_defconfig new file mode 100644 index 00000000000000..1289685e1e806e --- /dev/null +++ b/boards/particle/nrf51_blenano/nrf51_blenano_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51_vbluno51/pre_dt_board.cmake b/boards/particle/nrf51_blenano/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51_vbluno51/pre_dt_board.cmake rename to boards/particle/nrf51_blenano/pre_dt_board.cmake diff --git a/boards/particle/nrf52_blenano2/Kconfig.defconfig b/boards/particle/nrf52_blenano2/Kconfig.defconfig new file mode 100644 index 00000000000000..df0bcd9b33a529 --- /dev/null +++ b/boards/particle/nrf52_blenano2/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 BLENANO 2 board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_BLENANO2 + +config BT_CTLR + default BT + +endif # BOARD_NRF52_BLENANO2 diff --git a/boards/particle/nrf52_blenano2/Kconfig.nrf52_blenano2 b/boards/particle/nrf52_blenano2/Kconfig.nrf52_blenano2 new file mode 100644 index 00000000000000..f48ace77e7ae0d --- /dev/null +++ b/boards/particle/nrf52_blenano2/Kconfig.nrf52_blenano2 @@ -0,0 +1,7 @@ +# nRF52 BLENANO 2 board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_BLENANO2 + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_blenano2/board.cmake b/boards/particle/nrf52_blenano2/board.cmake similarity index 100% rename from boards/arm/nrf52_blenano2/board.cmake rename to boards/particle/nrf52_blenano2/board.cmake diff --git a/boards/particle/nrf52_blenano2/board.yml b/boards/particle/nrf52_blenano2/board.yml new file mode 100644 index 00000000000000..fedad35babcbfc --- /dev/null +++ b/boards/particle/nrf52_blenano2/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_blenano2 + vendor: particle + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_blenano2/doc/dap.jpg b/boards/particle/nrf52_blenano2/doc/dap.jpg similarity index 100% rename from boards/arm/nrf52_blenano2/doc/dap.jpg rename to boards/particle/nrf52_blenano2/doc/dap.jpg diff --git a/boards/arm/nrf52_blenano2/doc/index.rst b/boards/particle/nrf52_blenano2/doc/index.rst similarity index 100% rename from boards/arm/nrf52_blenano2/doc/index.rst rename to boards/particle/nrf52_blenano2/doc/index.rst diff --git a/boards/arm/nrf52_blenano2/doc/nrf52_blenano2.jpg b/boards/particle/nrf52_blenano2/doc/nrf52_blenano2.jpg similarity index 100% rename from boards/arm/nrf52_blenano2/doc/nrf52_blenano2.jpg rename to boards/particle/nrf52_blenano2/doc/nrf52_blenano2.jpg diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi b/boards/particle/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi rename to boards/particle/nrf52_blenano2/nrf52_blenano2-pinctrl.dtsi diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2.dts b/boards/particle/nrf52_blenano2/nrf52_blenano2.dts similarity index 100% rename from boards/arm/nrf52_blenano2/nrf52_blenano2.dts rename to boards/particle/nrf52_blenano2/nrf52_blenano2.dts diff --git a/boards/arm/nrf52_blenano2/nrf52_blenano2.yaml b/boards/particle/nrf52_blenano2/nrf52_blenano2.yaml similarity index 100% rename from boards/arm/nrf52_blenano2/nrf52_blenano2.yaml rename to boards/particle/nrf52_blenano2/nrf52_blenano2.yaml diff --git a/boards/particle/nrf52_blenano2/nrf52_blenano2_defconfig b/boards/particle/nrf52_blenano2/nrf52_blenano2_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/particle/nrf52_blenano2/nrf52_blenano2_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf9160dk_nrf52840/pre_dt_board.cmake b/boards/particle/nrf52_blenano2/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf9160dk_nrf52840/pre_dt_board.cmake rename to boards/particle/nrf52_blenano2/pre_dt_board.cmake diff --git a/boards/arm/particle_xenon/CMakeLists.txt b/boards/particle/xenon/CMakeLists.txt similarity index 100% rename from boards/arm/particle_xenon/CMakeLists.txt rename to boards/particle/xenon/CMakeLists.txt diff --git a/boards/arm/particle_xenon/Kconfig b/boards/particle/xenon/Kconfig similarity index 100% rename from boards/arm/particle_xenon/Kconfig rename to boards/particle/xenon/Kconfig diff --git a/boards/particle/xenon/Kconfig.defconfig b/boards/particle/xenon/Kconfig.defconfig new file mode 100644 index 00000000000000..1cd3ad31f06753 --- /dev/null +++ b/boards/particle/xenon/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Particle Xenon board configuration + +# Copyright (c) 2018 Endre Karlson +# Copyright (c) 2018 Peter Bigot Consulting, LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PARTICLE_XENON + +config BT_CTLR + default BT + +endif # BOARD_PARTICLE_XENON diff --git a/boards/particle/xenon/Kconfig.particle_xenon b/boards/particle/xenon/Kconfig.particle_xenon new file mode 100644 index 00000000000000..84487057f49ed7 --- /dev/null +++ b/boards/particle/xenon/Kconfig.particle_xenon @@ -0,0 +1,7 @@ +# Particle Xenon configuration + +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PARTICLE_XENON + select SOC_NRF52840_QIAA diff --git a/boards/arm/particle_xenon/board.c b/boards/particle/xenon/board.c similarity index 100% rename from boards/arm/particle_xenon/board.c rename to boards/particle/xenon/board.c diff --git a/boards/arm/particle_xenon/board.cmake b/boards/particle/xenon/board.cmake similarity index 100% rename from boards/arm/particle_xenon/board.cmake rename to boards/particle/xenon/board.cmake diff --git a/boards/particle/xenon/board.yml b/boards/particle/xenon/board.yml new file mode 100644 index 00000000000000..a681db97a1ff7c --- /dev/null +++ b/boards/particle/xenon/board.yml @@ -0,0 +1,5 @@ +board: + name: particle_xenon + vendor: particle + socs: + - name: nrf52840 diff --git a/boards/arm/particle_xenon/doc/img/particle_xenon.jpg b/boards/particle/xenon/doc/img/particle_xenon.jpg similarity index 100% rename from boards/arm/particle_xenon/doc/img/particle_xenon.jpg rename to boards/particle/xenon/doc/img/particle_xenon.jpg diff --git a/boards/arm/particle_xenon/doc/index.rst b/boards/particle/xenon/doc/index.rst similarity index 100% rename from boards/arm/particle_xenon/doc/index.rst rename to boards/particle/xenon/doc/index.rst diff --git a/boards/arm/particle_xenon/dts/mesh_feather-pinctrl.dtsi b/boards/particle/xenon/dts/mesh_feather-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather-pinctrl.dtsi rename to boards/particle/xenon/dts/mesh_feather-pinctrl.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather.dtsi b/boards/particle/xenon/dts/mesh_feather.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather.dtsi rename to boards/particle/xenon/dts/mesh_feather.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_i2c1_twi1.dtsi b/boards/particle/xenon/dts/mesh_feather_i2c1_twi1.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_i2c1_twi1.dtsi rename to boards/particle/xenon/dts/mesh_feather_i2c1_twi1.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_spi1_spi3.dtsi b/boards/particle/xenon/dts/mesh_feather_spi1_spi3.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_spi1_spi3.dtsi rename to boards/particle/xenon/dts/mesh_feather_spi1_spi3.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_spi_spi1.dtsi b/boards/particle/xenon/dts/mesh_feather_spi_spi1.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_spi_spi1.dtsi rename to boards/particle/xenon/dts/mesh_feather_spi_spi1.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_spi_spi3.dtsi b/boards/particle/xenon/dts/mesh_feather_spi_spi3.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_spi_spi3.dtsi rename to boards/particle/xenon/dts/mesh_feather_spi_spi3.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_feather_uart1_rtscts.dtsi b/boards/particle/xenon/dts/mesh_feather_uart1_rtscts.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_feather_uart1_rtscts.dtsi rename to boards/particle/xenon/dts/mesh_feather_uart1_rtscts.dtsi diff --git a/boards/arm/particle_xenon/dts/mesh_xenon_uart2.dtsi b/boards/particle/xenon/dts/mesh_xenon_uart2.dtsi similarity index 100% rename from boards/arm/particle_xenon/dts/mesh_xenon_uart2.dtsi rename to boards/particle/xenon/dts/mesh_xenon_uart2.dtsi diff --git a/boards/arm/particle_xenon/particle_xenon-pinctrl.dtsi b/boards/particle/xenon/particle_xenon-pinctrl.dtsi similarity index 100% rename from boards/arm/particle_xenon/particle_xenon-pinctrl.dtsi rename to boards/particle/xenon/particle_xenon-pinctrl.dtsi diff --git a/boards/arm/particle_xenon/particle_xenon.dts b/boards/particle/xenon/particle_xenon.dts similarity index 100% rename from boards/arm/particle_xenon/particle_xenon.dts rename to boards/particle/xenon/particle_xenon.dts diff --git a/boards/arm/particle_xenon/particle_xenon.yaml b/boards/particle/xenon/particle_xenon.yaml similarity index 100% rename from boards/arm/particle_xenon/particle_xenon.yaml rename to boards/particle/xenon/particle_xenon.yaml diff --git a/boards/particle/xenon/particle_xenon_defconfig b/boards/particle/xenon/particle_xenon_defconfig new file mode 100644 index 00000000000000..918f925556e8bd --- /dev/null +++ b/boards/particle/xenon/particle_xenon_defconfig @@ -0,0 +1,17 @@ +# +# Copyright (c) 2018, Endre Karlson +# +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/particle_argon/pre_dt_board.cmake b/boards/particle/xenon/pre_dt_board.cmake similarity index 100% rename from boards/arm/particle_argon/pre_dt_board.cmake rename to boards/particle/xenon/pre_dt_board.cmake diff --git a/boards/phytec/index.rst b/boards/phytec/index.rst new file mode 100644 index 00000000000000..0bde22965df24c --- /dev/null +++ b/boards/phytec/index.rst @@ -0,0 +1,10 @@ +.. _boards-phytec: + +PHYTEC Messtechnik GmbH +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig new file mode 100644 index 00000000000000..ec8c8486351c7a --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.defconfig @@ -0,0 +1,15 @@ +# MIMX8MM_PHYBOARD_POLIS board defconfig +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMX8MM_PHYBOARD_POLIS + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_MIMX8MM_PHYBOARD_POLIS diff --git a/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis new file mode 100644 index 00000000000000..0039e251a76c71 --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/Kconfig.mimx8mm_phyboard_polis @@ -0,0 +1,7 @@ +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMX8MM_PHYBOARD_POLIS + select SOC_PART_NUMBER_MIMX8MM6DVTLZ + select SOC_MIMX8MM6_M4 if BOARD_MIMX8MM_PHYBOARD_POLIS_MIMX8MM6_M4 diff --git a/boards/arm/mimx8mm_evk/board.cmake b/boards/phytec/mimx8mm_phyboard_polis/board.cmake similarity index 100% rename from boards/arm/mimx8mm_evk/board.cmake rename to boards/phytec/mimx8mm_phyboard_polis/board.cmake diff --git a/boards/phytec/mimx8mm_phyboard_polis/board.yml b/boards/phytec/mimx8mm_phyboard_polis/board.yml new file mode 100644 index 00000000000000..1c416b90eb165b --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/board.yml @@ -0,0 +1,5 @@ +board: + name: mimx8mm_phyboard_polis + vendor: phytec + socs: + - name: mimx8mm6 diff --git a/boards/arm/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg b/boards/phytec/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg rename to boards/phytec/mimx8mm_phyboard_polis/doc/img/PEB-EVAL-01.jpg diff --git a/boards/arm/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg b/boards/phytec/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg rename to boards/phytec/mimx8mm_phyboard_polis/doc/img/phyBOARD-Polis.jpg diff --git a/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst b/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst new file mode 100644 index 00000000000000..1568a6f3f2b2ce --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/doc/index.rst @@ -0,0 +1,342 @@ +.. _mimx8mm_phyboard_polis: + +PhyBOARD Polis (NXP i.MX8M Mini) +################################ + +Overview +******** + +The phyBOARD-Polis, either a development platform for the +phyCORE-i.MX 8M Mini/Nano, or a powerful, industry-compatible single-board +computer for immediate implementation of your product idea. As a development +platform, the phyBOARD-Polis serves as reference design for your +customer-specific application and enables parallel development of the software +and carrier board for the phyCORE-i.MX 8M Mini/Nano. + + +As a powerful, industrial single-board computer (SBC), the phyBOARD-Polis is +equipped with a variety of standard interfaces which are available on standard +or socket/pin header connectors, while interesting extensions of the +phyCORE-i.MX 8M Mini/Nano features such as CAN FD, WLAN and an integrated +TPM chip further extend the range of applications that can be developed with +the phyCORE-i.MX 8M Mini/Nano. + +- Board features: + + - RAM: 512MB - 4GB (LPDDR4) + - Storage: + + - 4GB - 128GB eMMC + - 8MB - 128MB SPI NOR Flash + - microSD Interfacce + - 4kB EEPROM + - Wireless: + + - WiFi: 802.11 b/g/n (ac) 2,4 GHz / 5 GHz + - BLE 4.2 + - USB: + + - 1x USB2.0 OTG + - 1x USB2.0 + - Ethernet: 1x 10/100/1000BASE-T + - Interfaces: + - 1x RS232 / RS485 + - 2x UART + - 3x I²C + - 2x SPI + - Up to 4x PWM + - 4x SAI + - 1x MIPI CSI-2 + - 1x MIPI DSI-2 + - 2x MMC/SD/SDIO + - 1x PCIe (mini PCIE) + - LEDs: + + - 1x Status LED (3 Color LED) + - 1x Debug UART LED + - Debug + + - JTAG 20-pin connector + - MicroUSB for UART debug, two COM ports for A53 and M4 + +.. image:: img/phyBOARD-Polis.jpg + :align: center + :alt: PhyBOARD Polis + :width: 500 + +More information about the board can be found at the +`PHYTEC website`_. + +Supported Features +================== + +The Zephyr ``mimx8mm_phyboard_polis/mimx8mm6/m4`` board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig`. + +It is recommended to disable peripherals used by the M4 core on the Linux host. + +Other hardware features are not currently supported with Zephyr on the +M4-Core. + +Connections and IOs +=================== + +The following components are tested and working correctly. + +UART: +----- + +Zephyr is configured to use UART4 on the PhyBoard Polis by default to minimize +problems with the A53-Core because UART4 is only accessible from the M4-Core. + ++---------------+-----------------+-----------------------------------+ +| Board Name | SoM Name | Usage | ++===============+=================+===================================+ +| RS232/485 | UART1 | RS232 / RS485 with flow-control | ++---------------+-----------------+-----------------------------------+ +| To WiFi Module| UART2 | UART to WiFi/BLE Module | ++---------------+-----------------+-----------------------------------+ +| Debug USB(A53)| UART3 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ +| Debug USB(M4) | UART4 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ + +.. note:: + Please note, that the to UART2 connected Wifi/BLE Module isn't working with + Zephyr yet. + +.. warning:: + On Boards with the version number 1532.1 UART4 isn't connected to the Debug + USB. UART4 connects to pin 10(RX) and 12(TX) on the X8 pinheader. + + +LEDs: +----- + +Zephyr has the 3-color status LED configured. The led0 alias (the standard +Zephyr led) is configured to be the blue led. The LED can also light up in red +and green. + +GPIO: +----- + +The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mm devicetree +created by NXP. You can find it here: + +:zephyr_file:`dts/arm/nxp/nxp_imx8m_m4.dtsi`. + +The Pinout of the PhyBOARD Polis can be found here: + +`PHYTEC website`_ + +System Clock +============ + +The M4 Core is configured to run at a 400 MHz clock speed. + + +Programming and Debugging +************************* + +The i.MX8MM does not have a separate flash for the M4-Core. Because of this +the A53-Core has to load the program for the M4-Core to the right memory +address, set the PC and start the processor. +This can be done with U-Boot or Phytec's Linux BSP via remoteproc. + +Because remoteproc in Phytec's BSP only writes to the TCM memory area, +everything was tested in this memory area. + +You can read more about remoteproc in Phytec's BSP here: `Remoteproc BSP`_ + +These are the memory mapping for A53 and M4: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0093FFFF | 0x20200000-0x2023FFFF | 0x00900000-0x0093FFFF | 256KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3) + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file ``boards/arm/mimx8mm_evk/mimx8mm_evk.dts`` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. +The available configurations are: + +If you don't want to use the TCM memory area, you can either overwrite the +boards devicetree in your program or edit the board devicetree located here: + +:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts`. + +You also have to set XIP=n or edit the boards defconfig file, if you don't want +the TCM memory area to be used. You can find the defconf file here: + +:zephyr_file:`boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig`. + +The following configurations are possible for the flash and sram chosen nodes +to change the used memory area: + +.. code-block:: none + + "zephyr,flash" + - &tcml_code + - &ocram_code + - &ocram_s_code + + "zephyr,sram" + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + + +Starting the M4-Core via U-Boot +=============================== + +Load the compiled zephyr.bin to memory address 0x4800000. +This should output something like this: + +.. code-block:: console + + u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin + Using ethernet@30be0000 device + TFTP from server 192.168.3.10; our IP address is 192.168.3.11 + Filename 'zepyhr.bin'. + Load address: 0x48000000 + Loading: ## + 2 KiB/s + done + Bytes transferred = 27240 (6a68 hex) + +Because it's not possible to load directly to the TCM memory area you have to +copy the binaries. The last argument given is the size of the file in bytes, +you can copy it from the output of the last command. + +.. code-block:: console + + u-boot=> cp.b 0x48000000 0x7e0000 27240 + +And finaly starting the M4-Core at the right memory address: + +.. code-block:: console + + u-boot=> bootaux 0x7e0000 + ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... + + +Starting the M4-Core via remoteproc +=================================== + +Copy the zepyhr.elf to ``/lib/firmware`` on the target. Maybe a Zephyr sample +will be included in a future BSP release. + +.. note:: + In order to use remoteproc you have to add ``imx8mm-phycore-rpmsg.dtbo`` at + the end of the line in the ``/boot/bootenv.txt``, then reboot the target. + +.. warning:: + Remoteproc only reads firmware files from the ``/lib/firmware`` directory! + If you try to load a binary from another location unexpected errors will + occur! + +To load and start a firmware use this commands: + +.. code-block:: console + + target$ echo /lib/firmware/zepyhr.elf > /sys/class/remoteproc/remoteproc0/firmware + target$ echo start > /sys/class/remoteproc/remoteproc0/state + [ 90.700611] remoteproc remoteproc0: powering up imx-rproc + [ 90.706114] remoteproc remoteproc0: Direct firmware load for /lib/firmware/zepyhr.elf failed w2 + [ 90.716571] remoteproc remoteproc0: Falling back to sysfs fallback for: /lib/firmware/zepyhr.elf + [ 90.739280] remoteproc remoteproc0: Booting fw image /lib/firmware/zepyhr.elf, size 599356 + [ 90.804448] remoteproc remoteproc0: remote processor imx-rproc is now up + + +The M4-Core is now started up and running. You can see the output from Zephyr +on UART4. + +Debugging +========= + +The PhyBOARD Polis can be debugged using a JTAG Debugger. +The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's +``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. +You can find the JLink Software package here: `JLink Software`_ + +.. figure:: img/PEB-EVAL-01.jpg + :alt: PEB-EVAL-01 + :width: 350 + + PEB-EVAL-01 + +To debug efficiently you should use multiple terminals: + +(But its also possible to use ``west debug``) + +After connecting everything and building with west use this command while in +the directory of the program you build earlier to start a debug server: + +.. code-block:: console + + host$ west debugserver + +West automatically connects via the JLink to the Target. And keeps open a +debug server. + +Use another terminal, start gdb, connect to target and load Zephyr on the +target: + +.. code-block:: console + + host$ gdb-multiarch build/zephyr/zephyr.elf -tui + (gdb) targ rem :2331 + Remote debugging using :2331 + 0x1ffe0008 in _vector_table () + (gdb) mon halt + (gdb) mon reset + (gdb) c + Continuing. + +The program can be debugged using standard gdb techniques. + +.. _PHYTEC website: + https://www.phytec.de/produkte/single-board-computer/phyboard-polis-imx8m-mini/ + +.. _PhyBOARD Polis pinout: + https://download.phytec.de/Products/phyBOARD-Polis-iMX8M_Mini/TechData/phyCORE-i.MX8M_MINI_Pin_Muxing_Table.A1.xlsx?_ga=2.237582016.1177557183.1660563641-1900651135.1634193918 + +.. _Remoteproc BSP: + https://wiki.phytec.com/pages/releaseview.action?pageId=472257137#L1002e.A3i.MX8MMini/NanoBSPManual-RunningExamplesfromLinuxusingRemoteproc + +.. _i.MX 8M Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MMRM + +.. _JLink Software: + https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi rename to boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis-pinctrl.dtsi diff --git a/boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.dts b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts similarity index 100% rename from boards/arm/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis.dts rename to boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.dts diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml new file mode 100644 index 00000000000000..0125a4fa399501 --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2020 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimx8mm_phyboard_polis/mimx8mm6/m4 +name: Phyboard Polis i.MX8M Mini +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig new file mode 100644 index 00000000000000..9fad86a42a7feb --- /dev/null +++ b/boards/phytec/mimx8mm_phyboard_polis/mimx8mm_phyboard_polis_mimx8mm6_m4_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y diff --git a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig new file mode 100644 index 00000000000000..e860faf97cfb01 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.defconfig @@ -0,0 +1,15 @@ +# PhyBOARD Pollux (i.MX8MP) defconfig + +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMX8MP_PHYBOARD_POLLUX + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_MIMX8MP_PHYBOARD_POLLUX diff --git a/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux new file mode 100644 index 00000000000000..75165bf5a29876 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/Kconfig.mimx8mp_phyboard_pollux @@ -0,0 +1,6 @@ +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMX8MP_PHYBOARD_POLLUX + select SOC_MIMX8MP_M7 if BOARD_MIMX8MP_PHYBOARD_POLLUX_MIMX8ML8_M7 + select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/mimx8mp_phyboard_pollux/board.cmake b/boards/phytec/mimx8mp_phyboard_pollux/board.cmake similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/board.cmake rename to boards/phytec/mimx8mp_phyboard_pollux/board.cmake diff --git a/boards/phytec/mimx8mp_phyboard_pollux/board.yml b/boards/phytec/mimx8mp_phyboard_pollux/board.yml new file mode 100644 index 00000000000000..b871a53e370824 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/board.yml @@ -0,0 +1,5 @@ +board: + name: mimx8mp_phyboard_pollux + vendor: phytec + socs: + - name: mimx8ml8 diff --git a/boards/arm/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg b/boards/phytec/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg rename to boards/phytec/mimx8mp_phyboard_pollux/doc/img/PEB-EVAL-01.jpg diff --git a/boards/arm/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg b/boards/phytec/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg rename to boards/phytec/mimx8mp_phyboard_pollux/doc/img/Phyboard_Pollux.jpg diff --git a/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst new file mode 100644 index 00000000000000..501c7f541a0ce8 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/doc/index.rst @@ -0,0 +1,272 @@ +.. _mimx8mp_phyboard_pollux: + +PhyBOARD Pollux (NXP i.MX8M Plus) +################################# + +Overview +******** + +The PhyBOARD Pollux is based upon the PhyCore-i.MX8M Plus SOM which is based on +the NXP i.MX8M Plus SoC. The SoC includes four Coretex-A53 cores and one +Coretex-M7 core for real time applications like Zephyr. The PhyBOARD Pollux +can be used for various applications like SmartHomes, Industry 4.0, IoT etc. +It features a lots of interfaces and computing capacity. It can be used as +a reference, to develop or in the final product too. + + +Board features: + +- Memory: + + - RAM: 256MB - 8GB LPDDR4 + - EEPROM: 4kB - 32kB + - eMMC: 4GB - 64GB (eMMC 5.1) + - SPI NOR Flash: 4MB - 256MB +- Interfaces: + + - Ethernet: 2x 10/100/1000BASE-T (1x TSN Support) + - USB: 2x 3.0 Host + - Serial: 1x RS232 / RS485 Full Duplex / Half Duplex + - CAN: 2x CAN FD + - Digital I/O: via Expansion Connector + - PCIe: 1x miniPCIe + - MMX/SD/SDIO: microSD slot + - Display: LVDS(1x4 or 1x8), MIPI DSI(1x4), HDMI + - Audio: SAI + - Camera: 2x MIPI CSI-2 (PhyCAM-M) + - Expansion Bus: I2C, SPI, SDIO, UART, USB + - JTAG: via PEB-EVAL-01 +- LEDs: + + - 1x Multicolor Status LED via I2C + + +.. image:: img/Phyboard_Pollux.jpg + :width: 720px + :align: center + :height: 405px + :alt: PhyBOARD Pollux + +More information about the board can be found at the +`PHYTEC website`_. + +Supported Features +================== + +The Zephyr mimx8mp_phyboard_polis board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig`. + +It's recommended to disable peripherals used by the M7-Core on the host running +on the Linux host. + +Other hardware features are not currently supported with Zephyr on the +M7-Core. + +Connections and IOs +=================== + +The following Compontens are tested and working correctly. + +UART +---- + ++---------------+-----------------+-----------------------------------+ +| Board Name | SoM Name | Usage | ++===============+=================+===================================+ +| Debug USB(A53)| UART1 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ +| Wo WiFi Module| UART3 | UART to WiFi/BLE Module | ++---------------+-----------------+-----------------------------------+ +| Debug USB(M4) | UART4 | UART Debug Console via USB | ++---------------+-----------------+-----------------------------------+ + +.. note:: + Please note, that the, to UART3 connected, Wifi/BLE Module isn't working with + Zephyr yet. UART3 can also be used through pin 31(RX) and 33(TX) of the + X6 Connector. + +GPIO +---- + +The pinmuxing for the GPIOs is the standard pinmuxing of the mimx8mp devicetree +created by NXP. You can find it here: + +:zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. + +The Pinout of the PhyBOARD Polis can be found here: + +`PHYTEC website`_ + +Programming and Debugging +************************* + +The i.MX8MP does not have a separate flash for the M7-Core. Because of this +the A53-Core has to load the program for the M7-Core to the right memory +address, set the PC and start the processor. +This can only by done with u-boot at the moment. We are working on our BSP to +enable remoteproc support. + +The M7 can use up to 3 different RAMs (currently, only two configurations are +supported: ITCM and DDR). These are the memory mapping for A53 and M7: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the +`i.MX 8M Plus Applications Processor Reference Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which memory region will be used. This +configuration is done in the devicetree and the defconfig / the config of your +program. + +**By default Zephyr will use the TCM memory region.** You can configure it like +this for the DDR region: + +In the devicetree overwrite the following nodes like this: + +.. code-block:: DTS + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + }; + +change it to + +.. code-block:: DTS + + chosen { + /* DDR */ + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + }; + + +In your prj.conf overwrite the configuration like this for the **DDR** memory +region: + +.. code-block:: console + + CONFIG_CODE_DDR=y + CONFIG_CODE_ITCM=n + + +Starting the M7-Core via U-Boot +=============================== + +Load the compiled zephyr.bin to memory address 0x4800000. +This should output something like this: + +.. code-block:: console + + u-boot=> tftp 0x48000000 192.168.3.10:zyphr.bin + Using ethernet@30be0000 device + TFTP from server 192.168.3.10; our IP address is 192.168.3.11 + Filename 'zepyhr.bin'. + Load address: 0x48000000 + Loading: ## + 2 KiB/s + done + Bytes transferred = 27240 (6a68 hex) + +Because it's not possible to load directly to the TCM memory area you have to +copy the binaries. The last argument given is the size of the file in bytes, +you can copy it from the output of the last command. + +.. code-block:: console + + u-boot=> cp.b 0x48000000 0x7e0000 27240 + +And finaly starting the M7-Core at the right memory address: + +.. code-block:: console + + u-boot=> bootaux 0x7e0000 + ## Starting auxiliary core stack = 0x20003A58, pc = 0x1FFE1905... + +Debugging +========= + +The PhyBOARD Polis can be debugged using a JTAG Debugger. +The easiest way to do that is to use a SEGGER JLink Debugger and Phytec's +``PEB-EVAL-01`` Shield, which can be directly connected to the JLink. +You can find the JLink Software package here: `JLink Software`_ + +.. figure:: img/PEB-EVAL-01.jpg + :alt: PEB-EVAL-01 + :width: 350 + + PEB-EVAL-01 + +To debug efficiently you have to use multiple terminals: + +After connecting everything and building with west use this command while in +the directory of the program you build earlier to start a debug server: + +.. code-block:: console + + host$ west debugserver + +West automatically connects via the JLink to the Target and keeps open a +debug server. + +Use another terminal, start gdb, connect to target and load Zephyr on the +target: + +.. code-block:: console + + host$ gdb-multiarch build/zephyr/zephyr.elf -tui + (gdb) targ rem :2331 + Remote debugging using :2331 + 0x1ffe0008 in _vector_table () + (gdb) mon halt + (gdb) mon reset + (gdb) c + Continuing. + +The program can be debugged using standard gdb techniques. + +References +========== + +.. _PHYTEC website: + https://www.phytec.de/produkte/single-board-computer/phyboard-pollux/ + +.. _i.MX 8M Plus Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MPRM + +.. _JLink Software: + https://www.segger.com/downloads/jlink/ diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi rename to boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux-pinctrl.dtsi diff --git a/boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.dts b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts similarity index 100% rename from boards/arm/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux.dts rename to boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.dts diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml new file mode 100644 index 00000000000000..aa2cc09a553c29 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7.yaml @@ -0,0 +1,24 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimx8mp_phyboard_pollux/mimx8ml8/m7 +name: PhyBOARD Pollux (i.MX8MP) +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - uart + - gpio +vendor: nxp diff --git a/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig new file mode 100644 index 00000000000000..4926fdbe4e1e96 --- /dev/null +++ b/boards/phytec/mimx8mp_phyboard_pollux/mimx8mp_phyboard_pollux_mimx8ml8_m7_defconfig @@ -0,0 +1,20 @@ +# +# Copyright (c) 2022 PHYTEC Messtechnik GmbH +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y + +# y for TCM memory space +CONFIG_CODE_ITCM=y + +# y for DDR memory space +CONFIG_CODE_DDR=n + +CONFIG_PINCTRL=y diff --git a/boards/phytec/phyboard_lyra_am62x/Kconfig.phyboard_lyra_am62x b/boards/phytec/phyboard_lyra_am62x/Kconfig.phyboard_lyra_am62x new file mode 100644 index 00000000000000..1b9c5eb8161d85 --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/Kconfig.phyboard_lyra_am62x @@ -0,0 +1,11 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2023 Texas Instruments Incorporated +# Copyright (c) 2023 L Lakshmanan +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYBOARD_LYRA_AM62X + select SOC_AM6234_M4 if BOARD_PHYBOARD_LYRA_AM62X_AM6234_M4 + help + PHYTEC AM62x M4 phyBOARD-Lyra diff --git a/boards/phytec/phyboard_lyra_am62x/board.yml b/boards/phytec/phyboard_lyra_am62x/board.yml new file mode 100644 index 00000000000000..d91be2b4786a85 --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/board.yml @@ -0,0 +1,5 @@ +board: + name: phyboard_lyra_am62x + vendor: phytec + socs: + - name: am6234 diff --git a/boards/arm/am62x_m4/doc/img/phyCORE-AM62x_Lyra_frontside.webp b/boards/phytec/phyboard_lyra_am62x/doc/img/phyCORE-AM62x_Lyra_frontside.webp similarity index 100% rename from boards/arm/am62x_m4/doc/img/phyCORE-AM62x_Lyra_frontside.webp rename to boards/phytec/phyboard_lyra_am62x/doc/img/phyCORE-AM62x_Lyra_frontside.webp diff --git a/boards/phytec/phyboard_lyra_am62x/doc/index.rst b/boards/phytec/phyboard_lyra_am62x/doc/index.rst new file mode 100644 index 00000000000000..f18636318fd6a7 --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/doc/index.rst @@ -0,0 +1,145 @@ +.. _am62x_m4_phyboard_lyra: + +AM62x phyBOARD-Lyra M4F Core +############################ + +Overview +******** + +The AM62x phyBOARD-Lyra board configuration is used by Zephyr applications +that run on the TI AM62x platform. The board configuration provides support +for the ARM Cortex-M4F MCU core and the following features: + +- Nested Vector Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) + +The board configuration also enables support for the semihosting debugging console. + +See the `PHYTEC AM62x Product Page`_ for details. + +.. figure:: img/phyCORE-AM62x_Lyra_frontside.webp + :align: center + :alt: AM62x phyBOARD-Lyra + + PHYTEC phyBOARD-Lyra with the phyCORE-AM62x SoM + +Hardware +******** +The AM62x phyBOARD-Lyra kit features the AM62x SoC, which is composed of a +quad Cortex-A53 cluster and a single Cortex-M4 core in the MCU domain. Zephyr +is ported to run on the M4F core and the following listed hardware +specifications are used: + +- Low-power ARM Cortex-M4F +- Memory + + - 256KB of SRAM + - 2GB of DDR4 + +- Debug + + - XDS110 based JTAG + +Supported Features +================== + +The am62x_m4_phyboard_lyra configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 400 MHz. + +DDR RAM +------- + +The board has 2GB of DDR RAM available. This board configuration +allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +MCU domain UART (MCU_UART0). + +SD Card +******* + +Download PHYTEC's official `WIC`_ as well as `BMAP`_ and flash the WIC file with +an etching software onto an SD-card. This will boot Linux on the A53 application +cores of the SoM. These cores will then load the zephyr binary on the M4 core +using remoteproc. + +The default configuration can be found in +:zephyr_file:`boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig` + +Flashing +******** + +The Linux running on the A53 uses the remoteproc framework to manage the M4F co-processor. +Therefore, the testing requires the binary to be copied to the SD card to allow the A53 cores to +load it while booting using remoteproc. + +To test the M4F core, we build the `hello_world` sample with the following command. + +.. code-block:: console + + # From the root of the Zephyr repository + west build -p -b phyboard_lyra_am62x/am6234/m4 samples/hello_world + +This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. + +We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. + +.. code-block:: console + + # Mount the SD card at sdcard for example + sudo mount /dev/sdX sdcard + # copy the elf to the /lib/firmware directory + sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw + +The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. + +To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `phyBOARD SD Card Booting Essentials`_. + +After changing the boot mode, stop in U-Boot to enable the M4F co-processor. + +.. code-block:: console + + setenv overlays k3-am62-phyboard-lyra-rpmsg.dtbo + # Save the overlays variable permanently + saveenv + boot + +The board should boot into Linux and the binary will run and print Hello world to the MCU_UART0 +port. + + + +.. _PHYTEC AM62x Product Page: + https://www.phytec.com/product/phycore-am62x/ + +.. _WIC: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz + +.. _BMAP: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap + +.. _phyBOARD SD Card Booting Essentials: + https://docs.phytec.com/latest/phycore-am62x/bootingessentials/sdcard.html diff --git a/boards/arm/am62x_m4/am62x_m4_phyboard_lyra.dts b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.dts similarity index 100% rename from boards/arm/am62x_m4/am62x_m4_phyboard_lyra.dts rename to boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.dts diff --git a/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.yaml b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.yaml new file mode 100644 index 00000000000000..df0e8ec65bd161 --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4.yaml @@ -0,0 +1,8 @@ +identifier: phyboard_lyra_am62x/am6234/m4 +name: PHYTEC AM62x M4 phyBOARD-Lyra +type: mcu +arch: arm +toolchain: + - zephyr +ram: 192 +vendor: phytec diff --git a/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig new file mode 100644 index 00000000000000..7e20705fa3fc5e --- /dev/null +++ b/boards/phytec/phyboard_lyra_am62x/phyboard_lyra_am62x_am6234_m4_defconfig @@ -0,0 +1,25 @@ +# PHYTEC AM62x M4 phyBOARD-Lyra +# +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Author: Daniel Schultz +# +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_CORTEX_M_SYSTICK=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Enable Pinctrl +CONFIG_PINCTRL=y + +# Serial Driver +CONFIG_SERIAL=y + +# GPIO Driver +CONFIG_GPIO=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/phytec/phycore_am62x/Kconfig.phycore_am62x b/boards/phytec/phycore_am62x/Kconfig.phycore_am62x new file mode 100644 index 00000000000000..8c66cb29198dbc --- /dev/null +++ b/boards/phytec/phycore_am62x/Kconfig.phycore_am62x @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PHYCORE_AM62X + select SOC_AM6234_A53 if BOARD_PHYCORE_AM62X_AM6234_A53 diff --git a/boards/phytec/phycore_am62x/board.yml b/boards/phytec/phycore_am62x/board.yml new file mode 100644 index 00000000000000..ae8e3412ff4413 --- /dev/null +++ b/boards/phytec/phycore_am62x/board.yml @@ -0,0 +1,5 @@ +board: + name: phycore_am62x + vendor: phytec + socs: + - name: am6234 diff --git a/boards/phytec/phycore_am62x/doc/index.rst b/boards/phytec/phycore_am62x/doc/index.rst new file mode 100644 index 00000000000000..fd711350fe3d47 --- /dev/null +++ b/boards/phytec/phycore_am62x/doc/index.rst @@ -0,0 +1,109 @@ +.. _phycore_am62x_a53: + +PHYTEC phyCORE-AM62x (Cortex-A53) +################################# + +Overview +******** + +PHYTEC phyCORE-AM62x board is based on TI Sitara applications +processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core. +Zephyr OS is ported to run on the Cortex®-A53 core. + +- Board features: + + - RAM: 2GB DDR4 + - Storage: + + - 16GB eMMC + - 64MB OSPI NOR + - 4KB EEPROM + - Ethernet + +More information about the board can be found at the +`PHYTEC website`_. + +Supported Features +================== + +The Zephyr phycore_am62x_a53 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| GIC-v3 | on-chip | interrupt controller | ++-----------+------------+-------------------------------------+ +| ARM TIMER | on-chip | system clock | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 200 MHz. + +DDR RAM +------- + +The board has 2GB of DDR RAM available. This board configuration +allocates Zephyr 1MB of RAM (0x82000000 to 0x82100000). + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +CPU's UART0. + +SD Card +******* + +Download PHYTEC's official `WIC`_ and `bmap`_ files and flash the WIC file with +bmap-tools on a SD-card. + +.. code-block:: console + + bmaptool copy phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz /dev/sdX + +Building +******** + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: phycore_am62x/am6234/a53 + :zephyr-app: samples/hello_world + :goals: build + +Programming +*********** + +Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and +plug the SD card into the board. Power it up and stop the u-boot execution at +prompt. + +Use U-Boot to load and kick zephyr.bin: + +.. code-block:: console + + fatload mmc 1:1 0x82000000 zephyr.bin; dcache flush; icache flush; dcache off; icache off; go 0x82000000 + + +.. + References + +.. _PHYTEC website: + https://www.phytec.com/product/phycore-am62x/ + +.. _WIC: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.xz + +.. _Bmap: + https://download.phytec.de/Software/Linux/BSP-Yocto-AM62x/BSP-Yocto-AM62x-PD23.1.0/images/yogurt/phyboard-lyra-am62xx-2/phytec-qt5demo-image-phyboard-lyra-am62xx-2.wic.bmap diff --git a/boards/arm64/phycore_am62x_a53/phycore_am62x_a53.dts b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.dts similarity index 100% rename from boards/arm64/phycore_am62x_a53/phycore_am62x_a53.dts rename to boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.dts diff --git a/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.yaml b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.yaml new file mode 100644 index 00000000000000..b12e8863b506b0 --- /dev/null +++ b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53.yaml @@ -0,0 +1,13 @@ +identifier: phycore_am62x/am6234/a53 +name: PHYTEC phyCORE-AM62x A53 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 1024 +testing: + ignore_tags: + - net + - bluetooth +vendor: ti diff --git a/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53_defconfig b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53_defconfig new file mode 100644 index 00000000000000..527a3fc23473da --- /dev/null +++ b/boards/phytec/phycore_am62x/phycore_am62x_am6234_a53_defconfig @@ -0,0 +1,25 @@ +# SPDX-License-Identifier: Apache-2.0 + +# ARM Options +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_ARMV8_A_NS=y +CONFIG_ARM64_VA_BITS_36=y +CONFIG_ARM64_PA_BITS_36=y + +# Cache Options +CONFIG_CACHE_MANAGEMENT=y +CONFIG_DCACHE_LINE_SIZE_DETECT=y +CONFIG_ICACHE_LINE_SIZE_DETECT=y + +# Platform Configuration + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/reel_board/CMakeLists.txt b/boards/phytec/reel_board/CMakeLists.txt similarity index 100% rename from boards/arm/reel_board/CMakeLists.txt rename to boards/phytec/reel_board/CMakeLists.txt diff --git a/boards/phytec/reel_board/Kconfig b/boards/phytec/reel_board/Kconfig new file mode 100644 index 00000000000000..7c826262404b38 --- /dev/null +++ b/boards/phytec/reel_board/Kconfig @@ -0,0 +1,10 @@ +# reel board configuration + +# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_REEL_BOARD diff --git a/boards/phytec/reel_board/Kconfig.defconfig b/boards/phytec/reel_board/Kconfig.defconfig new file mode 100644 index 00000000000000..68061a3ef3b380 --- /dev/null +++ b/boards/phytec/reel_board/Kconfig.defconfig @@ -0,0 +1,40 @@ +# reel board configuration + +# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_REEL_BOARD + +config I2C + default y + +config BT_CTLR + default y + depends on BT + +if FXOS8700 + +choice FXOS8700_MODE + default FXOS8700_MODE_ACCEL +endchoice + +endif # FXOS8700 + +if LVGL + +choice LV_COLOR_DEPTH + default LV_COLOR_DEPTH_1 +endchoice + +config LV_Z_BITS_PER_PIXEL + default 1 + +config LV_DPI_DEF + default 130 + +config LV_Z_VDB_SIZE + default 16 + +endif # LVGL + +endif # BOARD_REEL_BOARD diff --git a/boards/phytec/reel_board/Kconfig.reel_board b/boards/phytec/reel_board/Kconfig.reel_board new file mode 100644 index 00000000000000..78eee825ccd0dd --- /dev/null +++ b/boards/phytec/reel_board/Kconfig.reel_board @@ -0,0 +1,7 @@ +# reel board configuration + +# Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_REEL_BOARD + select SOC_NRF52840_QIAA diff --git a/boards/arm/reel_board/board.c b/boards/phytec/reel_board/board.c similarity index 100% rename from boards/arm/reel_board/board.c rename to boards/phytec/reel_board/board.c diff --git a/boards/arm/reel_board/board.cmake b/boards/phytec/reel_board/board.cmake similarity index 100% rename from boards/arm/reel_board/board.cmake rename to boards/phytec/reel_board/board.cmake diff --git a/boards/phytec/reel_board/board.yml b/boards/phytec/reel_board/board.yml new file mode 100644 index 00000000000000..75878900418a99 --- /dev/null +++ b/boards/phytec/reel_board/board.yml @@ -0,0 +1,11 @@ +board: + name: reel_board + vendor: phytec + socs: + - name: nrf52840 + revision: + format: number + default: "1" + revisions: + - name: "1" + - name: "2" diff --git a/boards/arm/reel_board/doc/img/link_board_base.jpg b/boards/phytec/reel_board/doc/img/link_board_base.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/link_board_base.jpg rename to boards/phytec/reel_board/doc/img/link_board_base.jpg diff --git a/boards/arm/reel_board/doc/img/rb_lb_shield.jpg b/boards/phytec/reel_board/doc/img/rb_lb_shield.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/rb_lb_shield.jpg rename to boards/phytec/reel_board/doc/img/rb_lb_shield.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board.jpg b/boards/phytec/reel_board/doc/img/reel_board.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board.jpg rename to boards/phytec/reel_board/doc/img/reel_board.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_debug.jpg b/boards/phytec/reel_board/doc/img/reel_board_debug.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_debug.jpg rename to boards/phytec/reel_board/doc/img/reel_board_debug.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_descr_back.jpg b/boards/phytec/reel_board/doc/img/reel_board_descr_back.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_descr_back.jpg rename to boards/phytec/reel_board/doc/img/reel_board_descr_back.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_excon.jpg b/boards/phytec/reel_board/doc/img/reel_board_excon.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_excon.jpg rename to boards/phytec/reel_board/doc/img/reel_board_excon.jpg diff --git a/boards/arm/reel_board/doc/img/reel_board_tp.jpg b/boards/phytec/reel_board/doc/img/reel_board_tp.jpg similarity index 100% rename from boards/arm/reel_board/doc/img/reel_board_tp.jpg rename to boards/phytec/reel_board/doc/img/reel_board_tp.jpg diff --git a/boards/phytec/reel_board/doc/index.rst b/boards/phytec/reel_board/doc/index.rst new file mode 100644 index 00000000000000..79001a009e5501 --- /dev/null +++ b/boards/phytec/reel_board/doc/index.rst @@ -0,0 +1,564 @@ +.. _reel_board: + +reel board +########## + +Overview +******** + +`reel board`_ is a evaluation board based on the Nordic Semiconductor +nRF52840 SoC. The board was developed by PHYTEC Messtechnik GmbH in +cooperation with Zephyr Project for the Hackathon - "Get Connected". +The board has a built-in debug adapter based on the DAPLink interface +firmware and NXP MK20DX128VFM5 SoC. + +It is equipped with the Electrophoretic (electronic ink) Display (EPD), +environmental (temperature, humidity, light, accelerometer) sensors, and +Bluetooth connectivity making it easy to experiment and evaluate the +Zephyr OS in these kinds of use cases: + +* battery powered sensor node +* low-power, low-cost human-machine interface (HMI) for remote + control and environmental sensor monitoring +* temperature and humidity monitor on your table +* product, name or price tag +* interactive badge for meetings and conferences + +The board provides support for the Nordic Semiconductor nRF52840 ARM |reg| +Cortex |reg|-M4F SoC with an integrated 2.4 GHz transceiver supporting Bluetooth +|reg| Low Energy and IEEE |reg| 802.15.4. + +The schematic can be found on the `reel board website`_. + +Hardware +******** + +On the front of the board are RGB-LED, ADPS9960 and HDC1010 sensors, +and Electrophoretic Display. +The RGB-LED is controlled by the nRF52840 via GPIO pins. +Display is controlled by the nRF52840 via SPI and 3 GPIOs. + +On the back side of the board are all other components such as nRF52840, +a circuit for the Debug Adapter, On/Off and power source switch, battery holder, +buttons and the MMA8652FC (accelerometer) sensor. + +ADPS9960 is a Digital Proximity, Ambient Light, RGB and Gesture sensor. +HDC1010 is a digital humidity and temperature sensor. +MMA8652FC is a 12-bit Digital Accelerometer. +All sensors are connected to the I2C bus and one GPIO pin each, +which can be used as an interrupt source. + +.. figure:: img/reel_board.jpg + :align: center + :alt: reel board front + + reel board front (Credit: PHYTEC) + +.. figure:: img/reel_board_descr_back.jpg + :align: center + :alt: reel board back + + reel board back (Credit: PHYTEC) + +Since PCB version 1507.2, the nRF52840 SoC is not soldered directly to +the board but integrated as a module on a NOTM.2 adapter. +The wiring is identical for versions 1507.1 and 1507.2. + +.. _reel_board_display: + +Display +======= + +GDEH0213B1 is the display with which the board was introduced +in 2018. Unfortunately, this display has been discontinued. +Currently the board is delivered with the display GDEH0213B72. +It is expected that the display will be replaced over time +due the short product lifecycle of this type of displays. +The following table lists the displays used on the reel board. +The label on the ribbon cable can help to distinguish the displays. +According to the display type, the correct designation must be +used for building an application. + ++--------------+--------------------+----------------------+-------------------+ +| Display | Ribbon Cable Label | Controller / Driver | Board Designation | ++==============+====================+======================+===================+ +| Good Display | HINK-E0213 | SSD1673 / | reel_board | +| GDEH0213B1 | | ssd16xx | | ++--------------+--------------------+----------------------+-------------------+ +| Good Display | HINK-E0213A22 | SSD1675A / | reel_board@2 | +| GDEH0213B72 | | ssd16xx | | ++--------------+--------------------+----------------------+-------------------+ + +Power supply +============ + +The board is optimized for low power applications and supports two +power source configurations, battery and micro USB connector. + +The On/Off switch can choose which power source is used. + +reel board uses a TPS610981 boost converter to generate supply voltage +for nRF52840 and peripherals (sensors and EPD). +The boost converter has two modes: + +* Active mode - supply voltages for nRF52840 and peripherals are on +* Low Power mode - only supply voltage for nRF52840 is on + +The mode is controlled by MODE pin (P1.00). + +.. note:: + Actually there is no possibility to reduce energy consumption by the + Low Power mode. Both voltages are always on, see: + :zephyr_file:`boards/phytec/reel_board/board.c` + +Supported Features +================== + +The reel_board board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| UART | on-chip | serial port | ++-----------+------------+----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| SENSOR | off-chip | MMA8652FC polling: | +| | | ADPS9960 polling: | +| | | HDC1010 polling | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +Port P0 +------- + ++-------+----------------------------+---------------------------+ +| Name | Function | Usage | ++=======+============================+===========================+ +| P0.00 | XL1 | 32.768 kHz oscillator | ++-------+----------------------------+---------------------------+ +| P0.01 | XL2 | 32.768 kHz oscillator | ++-------+----------------------------+---------------------------+ +| P0.02 | expansion connector pin 30 | None | ++-------+----------------------------+---------------------------+ +| P0.03 | expansion connector pin 31 | None | ++-------+----------------------------+---------------------------+ +| P0.04 | expansion connector pin 19 | None | ++-------+----------------------------+---------------------------+ +| P0.05 | expansion connector pin 11 | None | ++-------+----------------------------+---------------------------+ +| P0.06 | UART0_TX | UART Console over USB | ++-------+----------------------------+---------------------------+ +| P0.07 | Button | user button (S5) | ++-------+----------------------------+---------------------------+ +| P0.08 | UART0_RX | UART Console over USB | ++-------+----------------------------+---------------------------+ +| P0.09 | expansion connector pin 27 | None | ++-------+----------------------------+---------------------------+ +| P0.10 | expansion connector pin 29 | None | ++-------+----------------------------+---------------------------+ +| P0.11 | RGB LED (red) | GPIO | ++-------+----------------------------+---------------------------+ +| P0.12 | RGB LED (green) | GPIO | ++-------+----------------------------+---------------------------+ +| P0.13 | PWM LED | Buzzer | GPIO | ++-------+----------------------------+---------------------------+ +| P0.14 | EPD Busy output | GPIO | ++-------+----------------------------+---------------------------+ +| P0.15 | EPD Reset input | GPIO | ++-------+----------------------------+---------------------------+ +| P0.16 | EPD DC input | GPIO | ++-------+----------------------------+---------------------------+ +| P0.17 | EPD SPI3_CS | SPI | ++-------+----------------------------+---------------------------+ +| P0.18 | CPU Reset | Reset (S4) | ++-------+----------------------------+---------------------------+ +| P0.19 | EPD SPI3_CLK | SPI | ++-------+----------------------------+---------------------------+ +| P0.20 | EPD SPI3_MOSI | SPI | ++-------+----------------------------+---------------------------+ +| P0.21 | SPI3_MISO | SPI (not connected) | ++-------+----------------------------+---------------------------+ +| P0.22 | HDC1010 DRDYn | GPIO | ++-------+----------------------------+---------------------------+ +| P0.23 | APDS9960 INT | GPIO | ++-------+----------------------------+---------------------------+ +| P0.24 | MMA8652FC INT1 | GPIO | ++-------+----------------------------+---------------------------+ +| P0.25 | MMA8652FC INT2 | GPIO | ++-------+----------------------------+---------------------------+ +| P0.26 | I2C_0 | I2C | ++-------+----------------------------+---------------------------+ +| P0.27 | I2C_0 | I2C | ++-------+----------------------------+---------------------------+ +| P0.28 | expansion connector pin 3 | None | ++-------+----------------------------+---------------------------+ +| P0.29 | expansion connector pin 52 | None | ++-------+----------------------------+---------------------------+ +| P0.30 | expansion connector pin 1 | None | ++-------+----------------------------+---------------------------+ +| P0.31 | expansion connector pin 37 | None | ++-------+----------------------------+---------------------------+ + +Port P1 +------- + ++-------+----------------------------+---------------------------+ +| Name | Function | Usage | ++=======+============================+===========================+ +| P1.00 | peripheral power on | GPIO | ++-------+----------------------------+---------------------------+ +| P1.01 | expansion connector pin 32 | None | ++-------+----------------------------+---------------------------+ +| P1.02 | expansion connector pin 34 | None | ++-------+----------------------------+---------------------------+ +| P1.03 | expansion connector pin 17 | None | ++-------+----------------------------+---------------------------+ +| P1.04 | expansion connector pin 15 | None | ++-------+----------------------------+---------------------------+ +| P1.05 | expansion connector pin 13 | None | ++-------+----------------------------+---------------------------+ +| P1.06 | expansion connector pin 33 | None | ++-------+----------------------------+---------------------------+ +| P1.07 | expansion connector pin 35 | None | ++-------+----------------------------+---------------------------+ +| P1.08 | expansion connector pin 45 | None | ++-------+----------------------------+---------------------------+ +| P1.09 | RGB LED (blue) | GPIO | ++-------+----------------------------+---------------------------+ +| P1.10 | expansion connector pin 47 | None | ++-------+----------------------------+---------------------------+ +| P1.11 | expansion connector pin 49 | None | ++-------+----------------------------+---------------------------+ +| P1.12 | expansion connector pin 51 | None | ++-------+----------------------------+---------------------------+ +| P1.13 | expansion connector pin 36 | None | ++-------+----------------------------+---------------------------+ +| P1.14 | expansion connector pin 48 | None | ++-------+----------------------------+---------------------------+ +| P1.15 | expansion connector pin 50 | None | ++-------+----------------------------+---------------------------+ + +Solder Jumper and Testpoints +============================ + +There are several labeled solder jumpers on the board. +These can be used to connect a logic analyzer to check the behavior of a +driver or to measure the voltage of a signal. + +.. figure:: img/reel_board_tp.jpg + :align: center + :alt: reel board Jumper and Testpoints + + reel board testpoints (Credit: PHYTEC) + +I2C bus and sensors testpoints +------------------------------ + ++-------+-----------------------+---------------------------+ +| Name | Type | Usage | ++=======+=======================+===========================+ +| J19 | closed solder jumper | testpoint I2C SDA | ++-------+-----------------------+---------------------------+ +| J20 | closed solder jumper | testpoint I2C SCL | ++-------+-----------------------+---------------------------+ +| J7 | closed solder jumper | testpoint INT1 MMA8652FC | ++-------+-----------------------+---------------------------+ +| J24 | closed solder jumper | testpoint INT2 MMA8652FC | ++-------+-----------------------+---------------------------+ +| J11 | closed solder jumper | testpoint INT APDS9960 | ++-------+-----------------------+---------------------------+ +| J12 | closed solder jumper | testpoint DRDYn HDC1010 | ++-------+-----------------------+---------------------------+ + +EPD testpoints +-------------- + ++-------+-----------------------+---------------------------+ +| Name | Type | Usage | ++=======+=======================+===========================+ +| J13 | closed solder jumper | testpoint EPD Busy | ++-------+-----------------------+---------------------------+ +| J14 | closed solder jumper | testpoint EPD Reset | ++-------+-----------------------+---------------------------+ +| J15 | closed solder jumper | testpoint EPD DC | ++-------+-----------------------+---------------------------+ +| J16 | closed solder jumper | testpoint EPD SPI_CS | ++-------+-----------------------+---------------------------+ +| J17 | closed solder jumper | testpoint EPD SPI_CLK | ++-------+-----------------------+---------------------------+ +| J18 | closed solder jumper | testpoint EPD SPI_MOSI | ++-------+-----------------------+---------------------------+ + +Power supply testpoint +---------------------- + ++-------+-----------------------+-------------------------------------------+ +| Name | Type | Usage | ++=======+=======================+===========================================+ +| J21 | closed solder jumper | testpoint peripheral voltage on/off | ++-------+-----------------------+-------------------------------------------+ +| TP11 | testpoint | testpoint peripheral voltage | ++-------+-----------------------+-------------------------------------------+ +| TP12 | testpoint | testpoint nRF52840 supply voltage VDD_nRF | ++-------+-----------------------+-------------------------------------------+ +| TP13 | testpoint | testpoint boost converter input voltage | ++-------+-----------------------+-------------------------------------------+ + +Built-in Debug Adapter +====================== + +The debug adapter is based on the DAPLink interface firmware and +NXP MK20DX128VFM5 SoC. The adapter is powered via a micro USB connector and +is always on when the board is connected to the USB host. +reel board can be flashed and debugged, powered either from battery or USB. +If the Adapter is powered via USB, the Adapter circuit heats the board +slightly and the temperature sensor can output values up to 1.5 degrees higher. + +.. figure:: img/reel_board_debug.jpg + :align: center + :alt: reel board Debug Adapter + + reel board Debug Adapter overview (Credit: PHYTEC) + +Debug Adapter Firmware +---------------------- + +DAPLink firmware for the adapter can be found at `DAPLink reel board Firmware`_. +To update the firmware (if necessary), the adapter must be started in bootloader +mode. For this, the board should be disconnected from the USB host, +the J22 should be closed (use tweezers for this) and the board reconnected to +the USB host. + +Debug Adapter Jumper +-------------------- + ++-------+-----------------------+----------------------------------------------+ +| Name | Type | Usage | ++=======+=======================+==============================================+ +| J3 | open solder jumper | close to pass UART TX to external adapter | ++-------+-----------------------+----------------------------------------------+ +| J4 | open solder jumper | close to pass UART RX to external adapter | ++-------+-----------------------+----------------------------------------------+ +| J22 | open solder jumper | close to start adapter in bootloader mode | ++-------+-----------------------+----------------------------------------------+ + +Adapter LEDs +------------ + ++-------+-----------------------+--------------------------------+ +| Name | Type | Usage | ++=======+=======================+================================+ +| D11 | green | flashes when adapter is active | ++-------+-----------------------+--------------------------------+ +| D14 | red | reserved | ++-------+-----------------------+--------------------------------+ +| D15 | yellow | reserved | ++-------+-----------------------+--------------------------------+ + +Expansion Connector +************************ + +The expansion connector has the same dimensions and similar pinout +as the BBC MicroBit edge connector. The expansion components that are +designed especially for the reel board are called link boards. + +.. figure:: img/reel_board_excon.jpg + :align: center + :alt: reel board Expansion Connector + + reel board Expansion Connector (Credit: PHYTEC) + +link board BASE +=============== + +link board BASE is a passive expansion board and allows other link boards or +third party shields in Arduino UNO R3 format to be connected to the reel board. +In addition, it includes a NOTM.2 connector and more powerful DCDC converter +then reel board. + +.. figure:: img/rb_lb_shield.jpg + :align: center + :alt: reel board and link board BASE + + reel board and link board BASE (Credit: PHYTEC) + +link board BASE can be used in combination with other link boards or +third party shields in two ways: + + As an adapter + reel board is plugged into the link board BASE. Both peripherals on + reel board and shields can be used as long as there is no conflict + between I2C devices. Care should be taken to provide enough power + to the complete circuit. + + Stand-alone + NOTM.2 adapter is removed from the reel board and + connected to NOTM.2 connector on the link board BASE. + The wiring to the shield connector is identical to the + configuration above and no software modifications for the shield + are necessary. + Stand-alone configuration is more suitable for applications where + peripherals on the reel board are not used or in conflict, + power provided by the reel board is not enough, + or for prototypes in the field. + +.. figure:: img/link_board_base.jpg + :align: center + :alt: link board BASE + + link board BASE (Credit: PHYTEC) + +Components on the link board BASE: + + reel board Connector: + 2x40 position edge connector. + + Micro USB Connector: + USB can be used as power source. USB data lines are wired + to NOTM.2 connector. + + NOTM.2 Connector: + Connector for NOTM.2 adapter. If the connector is used then + reel board should be removed from reel board connector. + + SWD Connector X11: + Wired to NOTM.2 connector. A debug probe can + be connected to program or debug MCU in Stand-alone configuration. + + Alternative Power Source X5 or X9: + Positive pin is closer to the + character. Nominal voltage is + 3.3V, there is no protection against reverse polarity or overvoltage. + Use it with care. + + Shield Connector: + Connector for link boards and third party shields in Arduino UNO R3 + format. Only shields designed for 3.3V supply voltage are supported. + +Meaning of the Power Source Switch positions: + + EXT + link board BASE is powered from Alternative Power Source Connector + X9 or X5. + + USB + link board BASE is powered from USB connector (via DCDC converter). + + RB + link board BASE is powered from reel board. The available power is + below 0.3W and depends on which source is used to power the reel board. + +Programming and Debugging +************************* + +Applications for the ``reel_board`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing +======== + +If you use Linux, create a udev rule (as ``root``) to fix a permission issue +when not using root for flashing. + +.. code-block:: console + + # echo 'ATTR{idProduct}=="0204", ATTR{idVendor}=="0d28", MODE="0666", GROUP="plugdev"' > /etc/udev/rules.d/50-cmsis-dap.rules + +Reload the rules and replug the device. + +.. code-block:: console + + $ sudo udevadm control --reload-rules + +Finally, unplug and plug the board again for the rules to take effect. + +Build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the reel board +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: reel_board + :goals: build flash + +.. note:: + Please use reel_board@2 to build a application for the board equipped with + the GDEH0213B72, see :ref:`reel_board_display`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: reel_board@2 + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: reel_board + :maybe-skip-config: + :goals: debug + + +Testing the LEDs and buttons +**************************** + +There are 2 samples that allow you to test that the buttons (switches) and +LEDs on the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. + +References +********** + +.. _reel board Website: + https://www.phytec.de/reelboard/ + +.. target-notes:: + +.. _reel board: + https://www.phytec.de/reelboard/ + +.. _DAPLink reel board Firmware: + https://github.com/PHYTEC-Messtechnik-GmbH/DAPLink/tree/reel-board diff --git a/boards/arm/reel_board/dts/reel_board-pinctrl.dtsi b/boards/phytec/reel_board/dts/reel_board-pinctrl.dtsi similarity index 100% rename from boards/arm/reel_board/dts/reel_board-pinctrl.dtsi rename to boards/phytec/reel_board/dts/reel_board-pinctrl.dtsi diff --git a/boards/arm/reel_board/dts/reel_board.dtsi b/boards/phytec/reel_board/dts/reel_board.dtsi similarity index 100% rename from boards/arm/reel_board/dts/reel_board.dtsi rename to boards/phytec/reel_board/dts/reel_board.dtsi diff --git a/boards/arm/particle_boron/pre_dt_board.cmake b/boards/phytec/reel_board/pre_dt_board.cmake similarity index 100% rename from boards/arm/particle_boron/pre_dt_board.cmake rename to boards/phytec/reel_board/pre_dt_board.cmake diff --git a/boards/arm/reel_board/reel_board-pinctrl.dtsi b/boards/phytec/reel_board/reel_board-pinctrl.dtsi similarity index 100% rename from boards/arm/reel_board/reel_board-pinctrl.dtsi rename to boards/phytec/reel_board/reel_board-pinctrl.dtsi diff --git a/boards/arm/reel_board/reel_board.dts b/boards/phytec/reel_board/reel_board.dts similarity index 100% rename from boards/arm/reel_board/reel_board.dts rename to boards/phytec/reel_board/reel_board.dts diff --git a/boards/arm/reel_board/reel_board.yaml b/boards/phytec/reel_board/reel_board_1.yaml similarity index 100% rename from boards/arm/reel_board/reel_board.yaml rename to boards/phytec/reel_board/reel_board_1.yaml diff --git a/boards/phytec/reel_board/reel_board_defconfig b/boards/phytec/reel_board/reel_board_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/phytec/reel_board/reel_board_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/reel_board/reel_board_v2-pinctrl.dtsi b/boards/phytec/reel_board/reel_board_nrf52840_2-pinctrl.dtsi similarity index 100% rename from boards/arm/reel_board/reel_board_v2-pinctrl.dtsi rename to boards/phytec/reel_board/reel_board_nrf52840_2-pinctrl.dtsi diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.overlay b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay new file mode 100644 index 00000000000000..b6652cbf4e8c12 --- /dev/null +++ b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2018-2019 PHYTEC Messtechnik GmbH + * Copyright (c) 2017 Linaro Limited + * Copyright (c) 2023 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "reel_board_nrf52840_2-pinctrl.dtsi" + +/ { + model = "reel board v2"; + compatible = "phytec,reel_board_v2"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + zephyr,display = &ssd16xx; + }; + + aliases { + watchdog0 = &wdt0; + }; +}; + +&spi1 { + compatible = "nordic,nrf-spi"; + status = "okay"; + cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; + ssd16xx: ssd16xxfb@0 { + compatible = "gooddisplay,gdeh0213b72", "solomon,ssd1675a"; + spi-max-frequency = <4000000>; + reg = <0>; + width = <250>; + height = <122>; + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + busy-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + + full { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x26>; + border-waveform = <0x03>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + /* + * Waveform Composition + * + * There are 7 Voltage Source (VS) Level groups + * n = {0,1,2...6}, each group contains + * 4 phases x = {A,B,C,D}. + * 2 bits represent the voltage in a phase: + * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2 + * + * For example 0x80 represents sequence VSL-VSS-VSS-VSS, + */ + 80 60 40 00 00 00 00 /* LUT0: BB: VS 0..6 */ + 10 60 20 00 00 00 00 /* LUT1: BW: VS 0..6 */ + 80 60 40 00 00 00 00 /* LUT2: WB: VS 0..6 */ + 10 60 20 00 00 00 00 /* LUT3: WW: VS 0..6 */ + 00 00 00 00 00 00 00 /* LUT4: VCOM: VS 0..6 */ + /* + * TPnx determines the length of each phase, + * and RPn repeat count of a sequence. + * TPnA, TPnB, TPnC, TPnD, RPn + * + * For example TP0A=3, TP0B=3, and RP0=2: + * VS sequence : VSL-VSS-VSS-VSS + * number of Gate Pulses (length) : 3 3 0 0 + * repeat count : 2 + */ + 03 03 00 00 02 /* TP0A TP0B TP0C TP0D RP0 */ + 09 09 00 00 02 /* TP1A TP1B TP1C TP1D RP1 */ + 03 03 00 00 02 /* TP2A TP2B TP2C TP2D RP2 */ + 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ + 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ + 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ + 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ + ]; + }; + + partial { + gdv = [15]; + sdv = [41 a8 32]; + vcom = <0x26>; + border-waveform = <0x01>; + dummy-line = <0x30>; + gate-line-width = <0x0a>; + lut = [ + 00 00 00 00 00 00 00 /* LUT0: BB: VS0..6 */ + 80 00 00 00 00 00 00 /* LUT1: BW: VS0..6 */ + 40 00 00 00 00 00 00 /* LUT2: WB: VS0..6 */ + 80 00 00 00 00 00 00 /* LUT3: WW: VS0..6 */ + 00 00 00 00 00 00 00 /* LUT4: VCOM: VS0..6 */ + 0A 00 00 00 04 /* TP0A TP0B TP0C TP0D RP0 */ + 00 00 00 00 00 /* TP1A TP1B TP1C TP1D RP1 */ + 00 00 00 00 00 /* TP2A TP2B TP2C TP2D RP2 */ + 00 00 00 00 00 /* TP3A TP3B TP3C TP3D RP3 */ + 00 00 00 00 00 /* TP4A TP4B TP4C TP4D RP4 */ + 00 00 00 00 00 /* TP5A TP5B TP5C TP5D RP5 */ + 00 00 00 00 00 /* TP6A TP6B TP6C TP6D RP6 */ + ]; + }; + }; +}; diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.yaml b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml new file mode 100644 index 00000000000000..dc6361d4f50197 --- /dev/null +++ b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml @@ -0,0 +1,22 @@ +identifier: reel_board@2 +name: reel-board +type: mcu +arch: arm +ram: 512 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - spi + - gpio + - usb_device + - usb_cdc + - ble + - pwm + - arduino_i2c + - arduino_spi + - arduino_gpio +vendor: phytec diff --git a/boards/arm/reel_board/support/pyocd.yaml b/boards/phytec/reel_board/support/pyocd.yaml similarity index 100% rename from boards/arm/reel_board/support/pyocd.yaml rename to boards/phytec/reel_board/support/pyocd.yaml diff --git a/boards/pine64/index.rst b/boards/pine64/index.rst new file mode 100644 index 00000000000000..2be21aa3a123f0 --- /dev/null +++ b/boards/pine64/index.rst @@ -0,0 +1,10 @@ +.. _boards-pine64: + +Pine64 +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/pine64/pinetime_devkit0/Kconfig.defconfig b/boards/pine64/pinetime_devkit0/Kconfig.defconfig new file mode 100644 index 00000000000000..adfebb274d97df --- /dev/null +++ b/boards/pine64/pinetime_devkit0/Kconfig.defconfig @@ -0,0 +1,21 @@ +# PineTime DevKit0 board configuration + +# Copyright (c) 2020 Stephane Dorre +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PINETIME_DEVKIT0 + +config BT_CTLR + default BT + +config INPUT + default y if LVGL + +if FLASH + +config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE + default 4096 + +endif # FLASH + +endif # BOARD_PINETIME_DEVKIT0 diff --git a/boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 b/boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 new file mode 100644 index 00000000000000..e2a5705c17135b --- /dev/null +++ b/boards/pine64/pinetime_devkit0/Kconfig.pinetime_devkit0 @@ -0,0 +1,7 @@ +# PineTime DevKit0 board configuration + +# Copyright (c) 2020 Stephane Dorre +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PINETIME_DEVKIT0 + select SOC_NRF52832_QFAA diff --git a/boards/arm/pinetime_devkit0/board.cmake b/boards/pine64/pinetime_devkit0/board.cmake similarity index 100% rename from boards/arm/pinetime_devkit0/board.cmake rename to boards/pine64/pinetime_devkit0/board.cmake diff --git a/boards/pine64/pinetime_devkit0/board.yml b/boards/pine64/pinetime_devkit0/board.yml new file mode 100644 index 00000000000000..e4c926cf96b0b7 --- /dev/null +++ b/boards/pine64/pinetime_devkit0/board.yml @@ -0,0 +1,5 @@ +board: + name: pinetime_devkit0 + vendor: pine64 + socs: + - name: nrf52832 diff --git a/boards/arm/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg b/boards/pine64/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg similarity index 100% rename from boards/arm/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg rename to boards/pine64/pinetime_devkit0/doc/img/PineTime_DevKit0.jpg diff --git a/boards/arm/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg b/boards/pine64/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg similarity index 100% rename from boards/arm/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg rename to boards/pine64/pinetime_devkit0/doc/img/PineTime_SWD_location.jpg diff --git a/boards/arm/pinetime_devkit0/doc/img/PineTime_leaflet.jpg b/boards/pine64/pinetime_devkit0/doc/img/PineTime_leaflet.jpg similarity index 100% rename from boards/arm/pinetime_devkit0/doc/img/PineTime_leaflet.jpg rename to boards/pine64/pinetime_devkit0/doc/img/PineTime_leaflet.jpg diff --git a/boards/arm/pinetime_devkit0/doc/index.rst b/boards/pine64/pinetime_devkit0/doc/index.rst similarity index 100% rename from boards/arm/pinetime_devkit0/doc/index.rst rename to boards/pine64/pinetime_devkit0/doc/index.rst diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi b/boards/pine64/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi similarity index 100% rename from boards/arm/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi rename to boards/pine64/pinetime_devkit0/pinetime_devkit0-pinctrl.dtsi diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0.dts b/boards/pine64/pinetime_devkit0/pinetime_devkit0.dts similarity index 100% rename from boards/arm/pinetime_devkit0/pinetime_devkit0.dts rename to boards/pine64/pinetime_devkit0/pinetime_devkit0.dts diff --git a/boards/arm/pinetime_devkit0/pinetime_devkit0.yaml b/boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml similarity index 100% rename from boards/arm/pinetime_devkit0/pinetime_devkit0.yaml rename to boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml diff --git a/boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig b/boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig new file mode 100644 index 00000000000000..353082fbb63fff --- /dev/null +++ b/boards/pine64/pinetime_devkit0/pinetime_devkit0_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y + +CONFIG_GPIO=y + +CONFIG_SERIAL=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/particle_xenon/pre_dt_board.cmake b/boards/pine64/pinetime_devkit0/pre_dt_board.cmake similarity index 100% rename from boards/arm/particle_xenon/pre_dt_board.cmake rename to boards/pine64/pinetime_devkit0/pre_dt_board.cmake diff --git a/boards/pjrc/index.rst b/boards/pjrc/index.rst new file mode 100644 index 00000000000000..9a8e66fea3f474 --- /dev/null +++ b/boards/pjrc/index.rst @@ -0,0 +1,10 @@ +.. _boards-pjrc: + +PJRC +#### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/pjrc/teensy4/CMakeLists.txt b/boards/pjrc/teensy4/CMakeLists.txt new file mode 100644 index 00000000000000..7b0c243fbbb5a8 --- /dev/null +++ b/boards/pjrc/teensy4/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(XIP_BOOT_HEADER_DCD_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + zephyr_library_sources(flexspi_nor_config.c) + zephyr_library_sources_ifdef(CONFIG_DEVICE_CONFIGURATION_DATA teensy4_sdram_ini_dcd.c) +endif() diff --git a/boards/pjrc/teensy4/Kconfig.defconfig b/boards/pjrc/teensy4/Kconfig.defconfig new file mode 100644 index 00000000000000..4bdd626e94a62d --- /dev/null +++ b/boards/pjrc/teensy4/Kconfig.defconfig @@ -0,0 +1,16 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_TEENSY40 || BOARD_TEENSY41 + +config BUILD_OUTPUT_HEX + bool + default y + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_TEENSY40 || BOARD_TEENSY41 diff --git a/boards/pjrc/teensy4/Kconfig.teensy40 b/boards/pjrc/teensy4/Kconfig.teensy40 new file mode 100644 index 00000000000000..bcc62d6bb4238f --- /dev/null +++ b/boards/pjrc/teensy4/Kconfig.teensy40 @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_TEENSY40 + select SOC_PART_NUMBER_MIMXRT1062DVJ6A diff --git a/boards/pjrc/teensy4/Kconfig.teensy41 b/boards/pjrc/teensy4/Kconfig.teensy41 new file mode 100644 index 00000000000000..d66c5f979a0f26 --- /dev/null +++ b/boards/pjrc/teensy4/Kconfig.teensy41 @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020, Bernhard Kraemer +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_TEENSY41 + select SOC_PART_NUMBER_MIMXRT1062DVL6A diff --git a/boards/pjrc/teensy4/board.yml b/boards/pjrc/teensy4/board.yml new file mode 100644 index 00000000000000..7906ae3b8236ef --- /dev/null +++ b/boards/pjrc/teensy4/board.yml @@ -0,0 +1,9 @@ +boards: + - name: teensy40 + vendor: pjrc + socs: + - name: mimxrt1062 + - name: teensy41 + vendor: pjrc + socs: + - name: mimxrt1062 diff --git a/boards/arm/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst similarity index 100% rename from boards/arm/teensy4/doc/index.rst rename to boards/pjrc/teensy4/doc/index.rst diff --git a/boards/arm/teensy4/doc/teensy40.jpg b/boards/pjrc/teensy4/doc/teensy40.jpg similarity index 100% rename from boards/arm/teensy4/doc/teensy40.jpg rename to boards/pjrc/teensy4/doc/teensy40.jpg diff --git a/boards/arm/teensy4/doc/teensy41.jpg b/boards/pjrc/teensy4/doc/teensy41.jpg similarity index 100% rename from boards/arm/teensy4/doc/teensy41.jpg rename to boards/pjrc/teensy4/doc/teensy41.jpg diff --git a/boards/pjrc/teensy4/flexspi_nor_config.c b/boards/pjrc/teensy4/flexspi_nor_config.c new file mode 100644 index 00000000000000..020bf6abd57b26 --- /dev/null +++ b/boards/pjrc/teensy4/flexspi_nor_config.c @@ -0,0 +1,44 @@ +/* + * Copyright (c) 2019, MADMACHINE LIMITED + * Copyright (c) 2021, Bernhard Kraemer + * + * refer to hal_nxp board file + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__((section(".boot_hdr.conf"))) +#elif defined(__ICCARM__) +#pragma location = ".boot_hdr.conf" +#endif + +const struct flexspi_nor_config_t Qspiflash_config = { + .memConfig = { + .tag = FLEXSPI_CFG_BLK_TAG, + .version = FLEXSPI_CFG_BLK_VERSION, + .readSampleClkSrc = + kFlexSPIReadSampleClk_LoopbackFromDqsPad, + .csHoldTime = 3u, + .csSetupTime = 3u, + .sflashPadType = kSerialFlash_4Pads, + .serialClkFreq = kFlexSpiSerialClk_100MHz, + .sflashA1Size = 8u * 1024u * 1024u, + .lookupTable = { + FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, + 0xEB, RADDR_SDR, + FLEXSPI_4PAD, 0x18), + FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, + 0x06, READ_SDR, + FLEXSPI_4PAD, 0x04), + }, + }, + .pageSize = 256u, + .sectorSize = 4u * 1024u, + .blockSize = 256u * 1024u, + .isUniformBlockSize = false, +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ diff --git a/boards/arm/teensy4/teensy4-pinctrl.dtsi b/boards/pjrc/teensy4/teensy4-pinctrl.dtsi similarity index 100% rename from boards/arm/teensy4/teensy4-pinctrl.dtsi rename to boards/pjrc/teensy4/teensy4-pinctrl.dtsi diff --git a/boards/arm/teensy4/teensy40.dts b/boards/pjrc/teensy4/teensy40.dts similarity index 100% rename from boards/arm/teensy4/teensy40.dts rename to boards/pjrc/teensy4/teensy40.dts diff --git a/boards/arm/teensy4/teensy40.yaml b/boards/pjrc/teensy4/teensy40.yaml similarity index 100% rename from boards/arm/teensy4/teensy40.yaml rename to boards/pjrc/teensy4/teensy40.yaml diff --git a/boards/arm/teensy4/teensy40_defconfig b/boards/pjrc/teensy4/teensy40_defconfig similarity index 79% rename from boards/arm/teensy4/teensy40_defconfig rename to boards/pjrc/teensy4/teensy40_defconfig index 89b2890fbe2f84..1d186d986c48ad 100644 --- a/boards/arm/teensy4/teensy40_defconfig +++ b/boards/pjrc/teensy4/teensy40_defconfig @@ -4,10 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_DEVICE_CONFIGURATION_DATA=n -CONFIG_BOARD_TEENSY40=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/teensy4/teensy41.dts b/boards/pjrc/teensy4/teensy41.dts similarity index 100% rename from boards/arm/teensy4/teensy41.dts rename to boards/pjrc/teensy4/teensy41.dts diff --git a/boards/arm/teensy4/teensy41.yaml b/boards/pjrc/teensy4/teensy41.yaml similarity index 100% rename from boards/arm/teensy4/teensy41.yaml rename to boards/pjrc/teensy4/teensy41.yaml diff --git a/boards/arm/teensy4/teensy41_defconfig b/boards/pjrc/teensy4/teensy41_defconfig similarity index 79% rename from boards/arm/teensy4/teensy41_defconfig rename to boards/pjrc/teensy4/teensy41_defconfig index 018d31d009ebc8..1d186d986c48ad 100644 --- a/boards/arm/teensy4/teensy41_defconfig +++ b/boards/pjrc/teensy4/teensy41_defconfig @@ -4,10 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_MIMXRT1062=y -CONFIG_SOC_SERIES_IMX_RT=y CONFIG_DEVICE_CONFIGURATION_DATA=n -CONFIG_BOARD_TEENSY41=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/posix/native_posix/CMakeLists.txt b/boards/posix/native_posix/CMakeLists.txt deleted file mode 100644 index 20210a46a81d89..00000000000000 --- a/boards/posix/native_posix/CMakeLists.txt +++ /dev/null @@ -1,33 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_compile_definitions(NO_POSIX_CHEATS) -zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L _XOPEN_SOURCE=600 _XOPEN_SOURCE_EXTENDED) - -zephyr_library_sources( - hw_models_top.c - timer_model.c - native_rtc.c - irq_handler.c - irq_ctrl.c - main.c - tracing.c - cmdline_common.c - cmdline.c - cpu_wait.c - hw_counter.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include - ) - -if(CONFIG_HAS_SDL) - add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) -endif() - -zephyr_ld_options( - -lm -) diff --git a/boards/posix/native_posix/Kconfig b/boards/posix/native_posix/Kconfig deleted file mode 100644 index 42a77bdf6c7b9a..00000000000000 --- a/boards/posix/native_posix/Kconfig +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_POSIX - bool - imply NATIVE_POSIX_TIMER - select POSIX_ARCH_CONSOLE - select NATIVE_APPLICATION - -if BOARD_NATIVE_POSIX - -comment "Native POSIX options" - -config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME - bool "Slow down execution to real time" - default n if ARCH_POSIX_LIBFUZZER - default y if BT_USERCHAN || !TEST - help - When selected the execution of the process will be slowed down to real time. - (if there is a lot of load it may be slower than real time) - If deselected, the process will run as fast as possible. - Note that this only decouples simulated time from real/wall time. In either - case the zephyr kernel and application cannot tell the difference unless they - interact with some other driver/device which runs at real time. - -source "boards/$(ARCH)/common/sdl/Kconfig" - -endif # BOARD_NATIVE_POSIX diff --git a/boards/posix/native_posix/Kconfig.board b/boards/posix/native_posix/Kconfig.board deleted file mode 100644 index 4367cd5063158d..00000000000000 --- a/boards/posix/native_posix/Kconfig.board +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_POSIX_32BIT - bool "Native POSIX for 32-bit host" - depends on SOC_POSIX - select BOARD_NATIVE_POSIX - help - Will produce a console Linux process which can be executed natively - as a 32-bit executable. - It provides some minimal needed models: - An interrupt controller, timer (system tick), and redirects kernel prints to - stdout. - -config BOARD_NATIVE_POSIX_64BIT - bool "Native POSIX for 64-bit host" - depends on SOC_POSIX - select BOARD_NATIVE_POSIX - select 64BIT - help - Will produce a console Linux process which can be executed natively - as a 64-bit executable. - It provides some minimal needed models: - An interrupt controller, timer (system tick), and redirects kernel prints to - stdout. diff --git a/boards/posix/native_posix/Kconfig.defconfig b/boards/posix/native_posix/Kconfig.defconfig deleted file mode 100644 index 985e66618474d4..00000000000000 --- a/boards/posix/native_posix/Kconfig.defconfig +++ /dev/null @@ -1,72 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NATIVE_POSIX - -config BUILD_OUTPUT_BIN - default n - -config BUILD_OUTPUT_EXE - default y - -config OUTPUT_PRINT_MEMORY_USAGE - default n - -config BOARD - default "native_posix_64" if BOARD_NATIVE_POSIX_64BIT - default "native_posix" - -if NETWORKING - -config NET_L2_ETHERNET - default y if !NET_LOOPBACK && !NET_TEST - -config ETH_NATIVE_POSIX - default y if NET_L2_ETHERNET && ETH_DRIVER - -endif # NETWORKING - -choice BT_HCI_BUS_TYPE - default BT_USERCHAN - depends on BT_HCI -endchoice - -if LOG - -# For native_posix we can log synchronously without any problem -# Doing so will be nicer for debugging -choice LOG_MODE - default LOG_MODE_IMMEDIATE -endchoice - -endif # LOG - -if CONSOLE - -config POSIX_ARCH_CONSOLE - default y if !SERIAL - -config UART_CONSOLE - default y if SERIAL - -endif # CONSOLE - -config FLASH_SIMULATOR - default y - depends on FLASH - -config USB_NATIVE_POSIX - default y - depends on USB_DEVICE_DRIVER - -config EEPROM_SIMULATOR - default y - depends on EEPROM - -if I2C - -config EMUL - default y - -endif # I2C - -endif # BOARD_NATIVE_POSIX diff --git a/boards/posix/native_posix/native_posix_64_defconfig b/boards/posix/native_posix/native_posix_64_defconfig deleted file mode 100644 index 5ccadf2bc6aed7..00000000000000 --- a/boards/posix/native_posix/native_posix_64_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_POSIX_64BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_posix/native_posix_defconfig b/boards/posix/native_posix/native_posix_defconfig deleted file mode 100644 index ee7f4b92eda467..00000000000000 --- a/boards/posix/native_posix/native_posix_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_POSIX_32BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_sim/CMakeLists.txt b/boards/posix/native_sim/CMakeLists.txt deleted file mode 100644 index 5ddf0e5f143c4e..00000000000000 --- a/boards/posix/native_sim/CMakeLists.txt +++ /dev/null @@ -1,39 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_compile_definitions(NO_POSIX_CHEATS) - -zephyr_library_sources( - cmdline.c - cpu_wait.c - nsi_if.c - irq_handler.c - misc.c - posix_arch_if.c - ) - -zephyr_include_directories( - ${NSI_DIR}/common/src/include - ${NSI_DIR}/native/src/include -) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include -) - -if(CONFIG_HAS_SDL) - add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl) -endif() - -add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/extra_args/ - ${CMAKE_CURRENT_BINARY_DIR}/extra_args -) - -set(nsi_config_content - ${nsi_config_content} - "NSI_NATIVE=1" -) - -include(../common/natsim_config.cmake) diff --git a/boards/posix/native_sim/Kconfig b/boards/posix/native_sim/Kconfig deleted file mode 100644 index ddf76a5f157ae6..00000000000000 --- a/boards/posix/native_sim/Kconfig +++ /dev/null @@ -1,51 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_SIM - bool "Native simulator (Single Core)" - select POSIX_ARCH_CONSOLE - select NATIVE_LIBRARY - select NATIVE_POSIX_TIMER - depends on SOC_POSIX - imply BOARD_NATIVE_POSIX if NATIVE_SIM_NATIVE_POSIX_COMPAT - -if BOARD_NATIVE_SIM - -comment "Native Simular (Single Core) options" - -config NATIVE_SIM_NATIVE_POSIX_COMPAT - bool "Pretend to be a native_posix board" - default y - help - When this option is set the native_sim board will pretend to be - a native_posix board from kconfig point of view, to allow using it directly with - code which was meant for the native_posix board and checks for the macro - CONFIG_BOARD_NATIVE_POSIX, or requires other kconfig options which depend on it. - -config NATIVE_SIM_SLOWDOWN_TO_REAL_TIME - bool "Slow down execution to real time" - default n if ARCH_POSIX_LIBFUZZER - default y if BT_USERCHAN || !TEST - help - When selected the execution of the process will be slowed down to real time. - (if there is a lot of load it may be slower than real time) - If deselected, the process will run as fast as possible. - Note that this only decouples simulated time from real/wall time. In either - case the zephyr kernel and application cannot tell the difference unless they - interact with some other driver/device which runs at real time. - -# This option definition exists only to enable NATIVE_SIM_NATIVE_POSIX_COMPAT -config BOARD_NATIVE_POSIX - bool - -config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME - bool "Slow down execution to real time (native_posix compat)" - select NATIVE_SIM_SLOWDOWN_TO_REAL_TIME - help - Transitional option which allows applications which targeted native_posix - to set the correct native_sim option (CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME) - -source "boards/$(ARCH)/common/sdl/Kconfig" -source "boards/$(ARCH)/common/extra_args/Kconfig" - -endif # BOARD_NATIVE_SIM diff --git a/boards/posix/native_sim/Kconfig.board b/boards/posix/native_sim/Kconfig.board deleted file mode 100644 index 7cc9ead031f4d0..00000000000000 --- a/boards/posix/native_sim/Kconfig.board +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NATIVE_SIM_32BIT - bool "Native simulation, 32-bit mode" - select BOARD_NATIVE_SIM - help - Will produce a console Linux process which can be executed natively - as a 32-bit executable. - -config BOARD_NATIVE_SIM_64BIT - bool "Native simulation, 64-bit mode" - select BOARD_NATIVE_SIM - select 64BIT - help - Will produce a console Linux process which can be executed natively - as a 64-bit executable. diff --git a/boards/posix/native_sim/Kconfig.defconfig b/boards/posix/native_sim/Kconfig.defconfig deleted file mode 100644 index c4bcb6184a3d79..00000000000000 --- a/boards/posix/native_sim/Kconfig.defconfig +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NATIVE_SIM - -config BUILD_OUTPUT_BIN - default n - -config BUILD_OUTPUT_EXE - default y - -config OUTPUT_PRINT_MEMORY_USAGE - default n - -config BOARD - default "native_sim_64" if BOARD_NATIVE_SIM_64BIT - default "native_sim" - -if NETWORKING - -config NET_L2_ETHERNET - default y if !NET_LOOPBACK && !NET_TEST - -config ETH_NATIVE_POSIX - default y if NET_L2_ETHERNET && ETH_DRIVER - -endif # NETWORKING - -choice BT_HCI_BUS_TYPE - default BT_USERCHAN - depends on BT_HCI -endchoice - -if LOG - -# For native_sim we can log synchronously without any problem -# Doing so will be nicer for debugging -choice LOG_MODE - default LOG_MODE_IMMEDIATE -endchoice - -endif # LOG - -if CONSOLE - -config POSIX_ARCH_CONSOLE - default y if !SERIAL - -config UART_CONSOLE - default y if SERIAL - -endif # CONSOLE - -config FLASH_SIMULATOR - default y - depends on FLASH - -config USB_NATIVE_POSIX - default y - depends on USB_DEVICE_DRIVER - -config EEPROM_SIMULATOR - default y - depends on EEPROM - -if I2C - -config EMUL - default y - -endif # I2C - -endif # BOARD_NATIVE_SIM diff --git a/boards/posix/native_sim/board.cmake b/boards/posix/native_sim/board.cmake deleted file mode 100644 index d9d444c1be9402..00000000000000 --- a/boards/posix/native_sim/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS native) - -board_set_debugger_ifnset(native_gdb) -board_finalize_runner_args(native_gdb) diff --git a/boards/posix/native_sim/native_sim_64_defconfig b/boards/posix/native_sim/native_sim_64_defconfig deleted file mode 100644 index abd666317cd2e7..00000000000000 --- a/boards/posix/native_sim/native_sim_64_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_SIM_64BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/native_sim/native_sim_defconfig b/boards/posix/native_sim/native_sim_defconfig deleted file mode 100644 index f3f1e1299c15c3..00000000000000 --- a/boards/posix/native_sim/native_sim_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NATIVE_SIM_32BIT=y -CONFIG_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 diff --git a/boards/posix/nrf_bsim/CMakeLists.txt b/boards/posix/nrf_bsim/CMakeLists.txt deleted file mode 100644 index 3ff7d632d4f2a6..00000000000000 --- a/boards/posix/nrf_bsim/CMakeLists.txt +++ /dev/null @@ -1,80 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# Copyright (c) 2018 Oticon A/S -# SPDX-License-Identifier: Apache-2.0 - -find_package(BabbleSim) - -zephyr_library() - -# Due to the BLE controller assumption about enum size -zephyr_compile_options( - -fshort-enums -) -# Structures layouts needs to match in the interface between the runner and the embedded SW -# The nrfx HAL uses enums in its definitions,so they need to have the same size in both, -# as both the HW models and embedded SW use them. -target_compile_options(native_simulator INTERFACE -fshort-enums) - -zephyr_library_sources( - irq_handler.c - cpu_wait.c - argparse.c - nsi_if.c - soc/nrfx_coredep.c - common/bstests_entry.c - common/cmsis/cmsis.c - common/trace_hook.c -) - -# Include sync_rtc from real SOC code if enabled -zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC - ${ZEPHYR_BASE}/soc/arm/nordic_nrf/nrf53/sync_rtc.c - ) - -target_sources(native_simulator INTERFACE - common/bsim_args_runner.c - common/bsim_extra_cpu_if_stubs.c - common/phy_sync_ctrl.c - common/runner_hooks.c - common/posix_arch_if.c - common/trace_hook.c -) - -if (CONFIG_IPC_SERVICE AND CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP) - zephyr_library_sources( - ipc_backend.c - ) -endif() - -zephyr_include_directories( - soc - common - common/cmsis - ${NSI_DIR}/common/src/include -) - -zephyr_library_include_directories( - ${BSIM_COMPONENTS_PATH}/libUtilv1/src/ - ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/ - ${BSIM_COMPONENTS_PATH}/libRandv2/src/ - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include - common/ -) - -set(libpath ${BSIM_OUT_PATH}/lib) -set_property(TARGET native_simulator APPEND PROPERTY RUNNER_LINK_LIBRARIES - ${libpath}/libUtilv1.32.a - ${libpath}/libPhyComv1.32.a - ${libpath}/lib2G4PhyComv1.32.a - ${libpath}/libRandv2.32.a -) - -target_compile_options(native_simulator INTERFACE - "-DNSI_PRIMARY_MCU_N=${CONFIG_NATIVE_SIMULATOR_PRIMARY_MCU_INDEX}") - -add_subdirectory(${ZEPHYR_BASE}/boards/${ARCH}/common/extra_args/ - ${CMAKE_CURRENT_BINARY_DIR}/extra_args -) - -include(../common/natsim_config.cmake) diff --git a/boards/posix/nrf_bsim/Kconfig b/boards/posix/nrf_bsim/Kconfig deleted file mode 100644 index b43db7fac4a317..00000000000000 --- a/boards/posix/nrf_bsim/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_BSIM_NRFXX - -# The following file is normally parsed only for the ARM architecture, which is -# used by Nordic SoCs, so to make the symbols defined in this file available for -# the simulated nrf5x_bsim boards, which use the POSIX architecture, the file -# must be read also from here. -source "soc/common/nordic_nrf/Kconfig.peripherals" - -source "boards/$(ARCH)/common/extra_args/Kconfig" - -endif # SOC_SERIES_BSIM_NRFXX - - -# This would eventually be shared by a possible family of simulated NRF boards -# which use BabbleSim. When that happens, we can move this to a common -# Kconfig file - -config SOC_SERIES_BSIM_NRFXX - bool - select NATIVE_LIBRARY - select SOC_COMPATIBLE_NRF - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select PINCTRL_DYNAMIC if PINCTRL - help - Any NRF simulated SOC with BabbleSim, based on the POSIX arch - -config SOC_SERIES_BSIM_NRF52X - bool - select SOC_SERIES_BSIM_NRFXX - select SOC_COMPATIBLE_NRF52X - help - Any NRF52 simulated SOC with BabbleSim, based on the POSIX arch - -config SOC_SERIES_BSIM_NRF53X - bool - select SOC_SERIES_BSIM_NRFXX - select SOC_COMPATIBLE_NRF53X - help - Any NRF53 simulated SOC with BabbleSim, based on the POSIX arch - -if BOARD_NRF5340BSIM_NRF5340_CPUAPP - -# Replica of the option provided by the BOARD_NRF5340DK_NRF5340_CPUAPP board so samples can be -# reused as is -config BOARD_ENABLE_CPUNET - bool "NRF53 Network MCU" - -endif # BOARD_NRF5340BSIM_NRF5340_CPUNET - -if SOC_SERIES_BSIM_NRF53X - -# Let's reuse the RTC sync options so applications which use it can be reused as is -source "soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc" - -endif # SOC_SERIES_BSIM_NRF53X diff --git a/boards/posix/nrf_bsim/Kconfig.board b/boards/posix/nrf_bsim/Kconfig.board deleted file mode 100644 index fcfbae4d4e762a..00000000000000 --- a/boards/posix/nrf_bsim/Kconfig.board +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF52_BSIM - bool "NRF52 simulation model" - select SOC_SERIES_BSIM_NRF52X - select SOC_COMPATIBLE_NRF52833 - select NRF_RTC_TIMER - select CLOCK_CONTROL - help - Will produce a console Linux process which can be executed natively. - It needs the BabbleSim simulator both in compile time and to execute - -config BOARD_NRF5340BSIM_NRF5340_CPUNET - bool "Simulated NRF53 Network core" - select SOC_SERIES_BSIM_NRF53X - select SOC_COMPATIBLE_NRF5340_CPUNET - select NRF_RTC_TIMER - select CLOCK_CONTROL - help - Will produce a console Linux process which can be executed natively. - It needs the BabbleSim simulator both in compile time and to execute - -config BOARD_NRF5340BSIM_NRF5340_CPUAPP - bool "Simulated NRF53 Application core" - select SOC_SERIES_BSIM_NRF53X - select SOC_COMPATIBLE_NRF5340_CPUAPP - select NRF_RTC_TIMER - select CLOCK_CONTROL - help - Will produce a console Linux process which can be executed natively. - It needs the BabbleSim simulator both in compile time and to execute diff --git a/boards/posix/nrf_bsim/Kconfig.defconfig b/boards/posix/nrf_bsim/Kconfig.defconfig deleted file mode 100644 index d4e48ada7ad3b8..00000000000000 --- a/boards/posix/nrf_bsim/Kconfig.defconfig +++ /dev/null @@ -1,94 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_BSIM_NRFXX - -config BUILD_OUTPUT_BIN - default n - -config BUILD_OUTPUT_EXE - # When the IPC service is used, the net core image requires the application core image, as it needs - # access to its IPC buffer. Without it, the executable cannot be built. - default y if !(BOARD_NRF5340BSIM_NRF5340_CPUNET && IPC_SERVICE && (NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS = "")) - -config OUTPUT_PRINT_MEMORY_USAGE - default n - -config BOARD - default "nrf52_bsim" if BOARD_NRF52_BSIM - default "nrf5340bsim_nrf5340_cpunet" if BOARD_NRF5340BSIM_NRF5340_CPUNET - default "nrf5340bsim_nrf5340_cpuapp" if BOARD_NRF5340BSIM_NRF5340_CPUAPP - -config NATIVE_SIMULATOR_NUMBER_MCUS - default 2 if BOARD_NRF5340BSIM_NRF5340_CPUNET || BOARD_NRF5340BSIM_NRF5340_CPUAPP - default 1 - -config NATIVE_SIMULATOR_MCU_N - default 1 if BOARD_NRF5340BSIM_NRF5340_CPUNET - default 0 - -config NATIVE_SIMULATOR_AUTOSTART_MCU - default y if BOARD_NRF5340BSIM_NRF5340_CPUNET - -config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX - default 1 if SOC_SERIES_BSIM_NRF53X - default 0 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 if !TICKLESS_KERNEL - default 32768 - -config BT_CTLR - default y if BOARD_NRF52_BSIM || BOARD_NRF5340BSIM_NRF5340_CPUNET - depends on BT - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 4096 if BT_HCI_IPC - default 4096 if NRF_802154_SER_HOST && BOARD_NRF5340BSIM_NRF5340_CPUAPP - default 4096 if NRF_802154_SER_RADIO && BOARD_NRF5340BSIM_NRF5340_CPUNET - -if BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET - -config MBOX_NRFX_IPC - default MBOX - -endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP || BOARD_NRF5340BSIM_NRF5340_CPUNET - -if BOARD_NRF5340BSIM_NRF5340_CPUAPP - -config IPC_SERVICE_BACKEND_RPMSG_SHMEM_RESET - default y if IPC_SERVICE_BACKEND_RPMSG - -choice BT_HCI_BUS_TYPE - default BT_HCI_IPC -endchoice - -endif # BOARD_NRF5340BSIM_NRF5340_CPUAPP - -# The 15.4 driver Tx encryption is currently not functional with this -# simulated board => we disable it by default. With this Openthread will normally -# default to encrypt packets on its own. -config NRF_802154_ENCRYPTION - default n - -if LOG - -# For this board we can log synchronously without any problem -# Doing so will be nicer for debugging -choice LOG_MODE - default LOG_MODE_IMMEDIATE -endchoice - -endif # LOG - -if CONSOLE - -config POSIX_ARCH_CONSOLE - default y - -endif # CONSOLE - -endif # SOC_SERIES_BSIM_NRFXX diff --git a/boards/posix/nrf_bsim/board.cmake b/boards/posix/nrf_bsim/board.cmake deleted file mode 100644 index d9d444c1be9402..00000000000000 --- a/boards/posix/nrf_bsim/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS native) - -board_set_debugger_ifnset(native_gdb) -board_finalize_runner_args(native_gdb) diff --git a/boards/posix/nrf_bsim/nrf52_bsim_defconfig b/boards/posix/nrf_bsim/nrf52_bsim_defconfig deleted file mode 100644 index 953e8c1aa931e6..00000000000000 --- a/boards/posix/nrf_bsim/nrf52_bsim_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NRF52_BSIM=y -CONFIG_CONSOLE=y -CONFIG_NO_OPTIMIZATIONS=y -CONFIG_LOG_BACKEND_UART=n diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig b/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig deleted file mode 100644 index fcf14c5b33af6f..00000000000000 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpuapp_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP=y -CONFIG_CONSOLE=y -CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig b/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig deleted file mode 100644 index 5da7b71af05831..00000000000000 --- a/boards/posix/nrf_bsim/nrf5340bsim_nrf5340_cpunet_defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_POSIX=y -CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUNET=y -CONFIG_CONSOLE=y -CONFIG_NO_OPTIMIZATIONS=y diff --git a/boards/posix/nrf_bsim/pre_dt_board.cmake b/boards/posix/nrf_bsim/pre_dt_board.cmake deleted file mode 100644 index 3369c21d3af5ba..00000000000000 --- a/boards/posix/nrf_bsim/pre_dt_board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - power@40000000 & clock@40000000 & bprot@40000000 -# - acl@4001e000 & flash-controller@4001e000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/posix/nrf_bsim/soc/pinctrl_soc.h b/boards/posix/nrf_bsim/soc/pinctrl_soc.h deleted file mode 100644 index f0be0443d5b8aa..00000000000000 --- a/boards/posix/nrf_bsim/soc/pinctrl_soc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H -#define BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H - -/* We reuse the real SOC's header: */ -#include "../soc/common/nordic_nrf/pinctrl_soc.h" - -#endif /* BOARDS_POSIX_NRF_BSIM_SOC_PINCTRL_SOC_H */ diff --git a/boards/arc/iotdk/CMakeLists.txt b/boards/qemu/arc/CMakeLists.txt similarity index 100% rename from boards/arc/iotdk/CMakeLists.txt rename to boards/qemu/arc/CMakeLists.txt diff --git a/boards/qemu/arc/Kconfig b/boards/qemu/arc/Kconfig new file mode 100644 index 00000000000000..c335cfb8dcf9c3 --- /dev/null +++ b/boards/qemu/arc/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_ARC + select QEMU_TARGET + select HAS_COVERAGE_SUPPORT diff --git a/boards/qemu/arc/Kconfig.defconfig b/boards/qemu/arc/Kconfig.defconfig new file mode 100644 index 00000000000000..ed5b1f0c014a05 --- /dev/null +++ b/boards/qemu/arc/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2020,2021 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_ARC + +if NETWORKING + +config NET_L2_ETHERNET + default y + +# Required to satisfy dependency of networking stack on RNG +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +endif diff --git a/boards/qemu/arc/Kconfig.qemu_arc b/boards/qemu/arc/Kconfig.qemu_arc new file mode 100644 index 00000000000000..69b406379ebdbd --- /dev/null +++ b/boards/qemu/arc/Kconfig.qemu_arc @@ -0,0 +1,9 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_ARC + select SOC_QEMU_ARC_EM if BOARD_QEMU_ARC_QEMU_ARC_EM + select SOC_QEMU_ARC_HS if BOARD_QEMU_ARC_QEMU_ARC_HS || BOARD_QEMU_ARC_QEMU_ARC_HS_XIP + select SOC_QEMU_ARC_HS5X if BOARD_QEMU_ARC_QEMU_ARC_HS5X + select SOC_QEMU_ARC_HS6X if BOARD_QEMU_ARC_QEMU_ARC_HS6X diff --git a/boards/arc/qemu_arc/arc_mpu_regions.c b/boards/qemu/arc/arc_mpu_regions.c similarity index 100% rename from boards/arc/qemu_arc/arc_mpu_regions.c rename to boards/qemu/arc/arc_mpu_regions.c diff --git a/boards/qemu/arc/board.cmake b/boards/qemu/arc/board.cmake new file mode 100644 index 00000000000000..569343d273c475 --- /dev/null +++ b/boards/qemu/arc/board.cmake @@ -0,0 +1,44 @@ +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_CPU_TYPE_${ARCH} arc) + +if(${CONFIG_SOC_QEMU_ARC_EM}) + set(QEMU_CPU_TYPE_${ARCH} arcem) + set(QEMU_FLAGS_${ARCH} -cpu arcem) +elseif(${CONFIG_SOC_QEMU_ARC_HS}) + set(QEMU_CPU_TYPE_${ARCH} archs) + set(QEMU_FLAGS_${ARCH} -cpu archs) +elseif(${CONFIG_SOC_QEMU_ARC_HS5X}) + set(QEMU_ARCH arc) + set(QEMU_CPU_TYPE_${ARCH} hs5x) + set(QEMU_FLAGS_${ARCH} -cpu hs5x) +elseif(${CONFIG_SOC_QEMU_ARC_HS6X}) + set(QEMU_ARCH arc64) + set(QEMU_CPU_TYPE_${ARCH} hs6x) + set(QEMU_FLAGS_${ARCH} -cpu hs6x) +endif() + +# For old QEMU we had 'simhs' qemu board, however we are going to rename it +# to 'virt' board. It will be renamed in ARC QEMU in the nearest Zephyr SDK +# (where ARCv3 HS6x support will be added to QEMU) +# Let's rely on the QEMU defaults instead of specifying exact board name, +# until the updated Zephyr SDK will be set as default. By that we keep both SDKs +# (old and new) working for ARCv2. +# After that we can specify board explicitly with '-M virt' option. +list(APPEND QEMU_FLAGS_${ARCH} + -m 8M + -nographic + -no-reboot + -monitor none + -global cpu.firq=false + -global cpu.num-irqlevels=15 + -global cpu.num-irq=25 + -global cpu.ext-irq=20 + -global cpu.freq_hz=10000000 + -global cpu.timer0=true + -global cpu.timer1=true + -global cpu.has-mpu=true + -global cpu.mpu-numreg=16 + ) + +set(BOARD_DEBUG_RUNNER qemu) diff --git a/boards/qemu/arc/board.yml b/boards/qemu/arc/board.yml new file mode 100644 index 00000000000000..1fb49911afa9c6 --- /dev/null +++ b/boards/qemu/arc/board.yml @@ -0,0 +1,10 @@ +board: + name: qemu_arc + vendor: qemu + socs: + - name: qemu_arc_em + - name: qemu_arc_hs + variants: + - name: xip + - name: qemu_arc_hs5x + - name: qemu_arc_hs6x diff --git a/boards/qemu/arc/doc/index.rst b/boards/qemu/arc/doc/index.rst new file mode 100644 index 00000000000000..0aef5d8dc39bd3 --- /dev/null +++ b/boards/qemu/arc/doc/index.rst @@ -0,0 +1,102 @@ +.. _qemu_arc: + +ARCv2 & ARCv3 Emulation (QEMU) +############################### + +Overview +******** + +This board configuration will use QEMU to emulate set of generic +ARCv2 and ARCv3 hardware platforms. + +The following features of ARC ISA cores are currently supported: + +* CPU: + * ARCv2 EM + * ARCv2 HS3x + * ARCv3 HS5x + * ARCv3 HS6x +* Only little-endian configurations +* Full 32 register set +* ARC core free-running timers/counters Timer0 & Timer1 +* ARC core interrupt controller with multiple priority levels +* DW UART +* 5 slots for MMIO Virtio devices + +Hardware +******** +Supported Features +================== + +The following hardware features are supported: + ++--------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++==============+============+======================+ +| ARCv2 INTC | on-chip | interrupt controller | ++--------------+------------+----------------------+ +| DW UART | on-chip | serial port | ++--------------+------------+----------------------+ +| ARC TIMER0 | on-chip | system clock | ++--------------+------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 1 MHz. + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +DesignWare UART. + +Known Problems or Limitations +============================== + +The following platform features are unsupported: + +* Memory-protection unit (MPU) +* MMIO Virtio Ethernet + +Programming and Debugging +************************* + +Use this configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample +(note you may use ``qemu_arc/qemu_em``, ``qemu_arc/qemu_hs``, ``qemu_arc/qemu_hs5x`` or +``qemu_arc/qemu_hs6x`` depending on target CPU): + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_arc/qemu_em + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.2.0-2486-g7dbfcf4bab57 *** + threadA: Hello World from qemu_arc! + threadB: Hello World from qemu_arc! + threadA: Hello World from qemu_arc! + threadB: Hello World from qemu_arc! + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. + +References +********** + +1.`Programmer’s Reference Manual for ARC HS + `_ diff --git a/boards/arc/qemu_arc/qemu_arc.dtsi b/boards/qemu/arc/qemu_arc.dtsi similarity index 100% rename from boards/arc/qemu_arc/qemu_arc.dtsi rename to boards/qemu/arc/qemu_arc.dtsi diff --git a/boards/arc/qemu_arc/qemu_arc_em.dts b/boards/qemu/arc/qemu_arc_qemu_arc_em.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_em.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_em.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml new file mode 100644 index 00000000000000..15adaf6b25af4b --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_em.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_em +name: QEMU Emulation for ARC EM +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig new file mode 100644 index 00000000000000..681d200814773c --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_em_defconfig @@ -0,0 +1,10 @@ +CONFIG_XIP=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml new file mode 100644 index 00000000000000..92ea09d4ee8dfc --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs.yaml @@ -0,0 +1,15 @@ +identifier: qemu_arc/qemu_arc_hs +name: QEMU Emulation for ARC HS +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/qemu_arc/qemu_arc_hs5x.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs5x.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs5x.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml new file mode 100644 index 00000000000000..152fbf0b5c0009 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_hs5x +name: QEMU Emulation for ARC HS5x +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig new file mode 100644 index 00000000000000..31f5cff2f42c19 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs5x_defconfig @@ -0,0 +1,10 @@ +CONFIG_ISA_ARCV3=y +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/arc/qemu_arc/qemu_arc_hs6x.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs6x.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs6x.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml new file mode 100644 index 00000000000000..94b4342a40af9a --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_hs6x +name: QEMU Emulation for ARC HS6x +type: qemu +simulation: qemu +arch: arc +toolchain: + - cross-compile + - zephyr +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig new file mode 100644 index 00000000000000..31f5cff2f42c19 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs6x_defconfig @@ -0,0 +1,10 @@ +CONFIG_ISA_ARCV3=y +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig new file mode 100644 index 00000000000000..d2fd7fddaa6771 --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_defconfig @@ -0,0 +1,10 @@ +CONFIG_XIP=n +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/qemu_arc/qemu_arc_hs_xip.dts b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.dts similarity index 100% rename from boards/arc/qemu_arc/qemu_arc_hs_xip.dts rename to boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.dts diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml new file mode 100644 index 00000000000000..dec824ec6b049c --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip.yaml @@ -0,0 +1,14 @@ +identifier: qemu_arc/qemu_arc_hs/xip +name: QEMU Emulation for ARC HS (XIP) +type: qemu +simulation: qemu +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig new file mode 100644 index 00000000000000..681d200814773c --- /dev/null +++ b/boards/qemu/arc/qemu_arc_qemu_arc_hs_xip_defconfig @@ -0,0 +1,10 @@ +CONFIG_XIP=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_HAS_STACK_CHECKING=n +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/qemu/cortex_a53/Kconfig b/boards/qemu/cortex_a53/Kconfig new file mode 100644 index 00000000000000..13f79db59cbac1 --- /dev/null +++ b/boards/qemu/cortex_a53/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config QEMU_CORTEX_A53_ETH_E1000 + bool + default y if !NET_TEST + depends on BOARD_QEMU_CORTEX_A53 && NETWORKING && DT_HAS_INTEL_E1000_ENABLED + select ETH_E1000 + select NET_L2_ETHERNET + select PCIE + select PCIE_CONTROLLER + select PCIE_ECAM diff --git a/boards/qemu/cortex_a53/Kconfig.defconfig b/boards/qemu/cortex_a53/Kconfig.defconfig new file mode 100644 index 00000000000000..70fe11c6d73cf8 --- /dev/null +++ b/boards/qemu/cortex_a53/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_A53 + +config BUILD_OUTPUT_BIN + default y + +config MAX_THREAD_BYTES + default 3 + +if NETWORKING + +choice NET_QEMU_NETWORKING + default NET_QEMU_ETHERNET if QEMU_CORTEX_A53_ETH_E1000 +endchoice + +config NET_DRIVERS + default n if QEMU_CORTEX_A53_ETH_E1000 + +endif # NETWORKING + +# QEMU PCI requires at least 256M of virtual space +config KERNEL_VM_SIZE + default 0x80000000 if PCIE + +# QEMU PCI requires physical addresses with more than 32 bits +choice ARM64_VA_BITS + default ARM64_VA_BITS_40 if PCIE +endchoice + +choice ARM64_PA_BITS + default ARM64_PA_BITS_40 if PCIE +endchoice + +if QEMU_ICOUNT + +config QEMU_ICOUNT_SHIFT + default 4 + +config QEMU_ICOUNT_SLEEP + default y + +endif # QEMU_ICOUNT + +endif # BOARD_QEMU_CORTEX_A53 diff --git a/boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 b/boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 new file mode 100644 index 00000000000000..a7d876a9e558eb --- /dev/null +++ b/boards/qemu/cortex_a53/Kconfig.qemu_cortex_a53 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_A53 + select SOC_QEMU_CORTEX_A53 diff --git a/boards/qemu/cortex_a53/board.cmake b/boards/qemu/cortex_a53/board.cmake new file mode 100644 index 00000000000000..7cc424e4544c51 --- /dev/null +++ b/boards/qemu/cortex_a53/board.cmake @@ -0,0 +1,30 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH aarch64) + +set(QEMU_CPU_TYPE_${ARCH} cortex-a53) + +if(CONFIG_ARMV8_A_NS) + set(QEMU_MACH virt,gic-version=3) +else() + set(QEMU_MACH virt,secure=on,gic-version=3) +endif() + +set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -nographic + -machine ${QEMU_MACH} + ) + +if(CONFIG_XIP) + # This should be equivalent to + # ... -drive if=pflash,file=build/zephyr/zephyr.bin,format=raw + # without having to pad the binary file to the FLASH size + set(QEMU_KERNEL_OPTION + -bios ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ) +endif() + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_a53/board.yml b/boards/qemu/cortex_a53/board.yml new file mode 100644 index 00000000000000..ab04f6ac8f1ee0 --- /dev/null +++ b/boards/qemu/cortex_a53/board.yml @@ -0,0 +1,8 @@ +board: + name: qemu_cortex_a53 + vendor: arm + socs: + - name: qemu_cortex_a53 + variants: + - name: smp + - name: xip diff --git a/boards/arm64/qemu_cortex_a53/doc/index.rst b/boards/qemu/cortex_a53/doc/index.rst similarity index 100% rename from boards/arm64/qemu_cortex_a53/doc/index.rst rename to boards/qemu/cortex_a53/doc/index.rst diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53.dts b/boards/qemu/cortex_a53/qemu_cortex_a53.dts similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53.dts rename to boards/qemu/cortex_a53/qemu_cortex_a53.dts diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53.yaml similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53.yaml rename to boards/qemu/cortex_a53/qemu_cortex_a53.yaml diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_defconfig b/boards/qemu/cortex_a53/qemu_cortex_a53_defconfig new file mode 100644 index 00000000000000..26b07e5862ca35 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM_ARCH_TIMER=y + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Avoid timing skew in tests +CONFIG_QEMU_ICOUNT=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.dts b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.dts similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53_smp.dts rename to boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.dts diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml new file mode 100644 index 00000000000000..4804d0645646b2 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp.yaml @@ -0,0 +1,17 @@ +identifier: qemu_cortex_a53/qemu_cortex_a53/smp +name: QEMU Emulation for Cortex-A53 SMP +type: qemu +simulation: qemu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +supported: + - smp +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: qemu diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig new file mode 100644 index 00000000000000..6309964906590a --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_smp_defconfig @@ -0,0 +1,29 @@ +CONFIG_ARM_ARCH_TIMER=y + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# icount does not work well with SMP +CONFIG_QEMU_ICOUNT=n + +# We have multiple QEMU-A53 boards, so let us exercise ARMV8_A_NS on this one +# (plus it is needed for SMP) +CONFIG_ARMV8_A_NS=y + +# PSCI is supported with NS +CONFIG_PM_CPU_OPS=y + +# SMP-related +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TIMEOUT_64BIT=y diff --git a/boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.dts b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.dts similarity index 100% rename from boards/arm64/qemu_cortex_a53/qemu_cortex_a53_xip.dts rename to boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.dts diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml new file mode 100644 index 00000000000000..5805780ee333c5 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip.yaml @@ -0,0 +1,14 @@ +identifier: qemu_cortex_a53/qemu_cortex_a53/xip +name: QEMU Emulation for Cortex-A53 (XIP) +type: qemu +simulation: qemu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 128 +testing: + default: true + only_tags: + - xip +vendor: qemu diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig new file mode 100644 index 00000000000000..f38fd56af71cd2 --- /dev/null +++ b/boards/qemu/cortex_a53/qemu_cortex_a53_qemu_cortex_a53_xip_defconfig @@ -0,0 +1,20 @@ +CONFIG_ARM_ARCH_TIMER=y + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable serial port +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Avoid timing skew in tests +CONFIG_QEMU_ICOUNT=y + +# Enable XIP +CONFIG_XIP=y diff --git a/boards/qemu/cortex_a9/Kconfig b/boards/qemu/cortex_a9/Kconfig new file mode 100644 index 00000000000000..f5d8700f0bef6b --- /dev/null +++ b/boards/qemu/cortex_a9/Kconfig @@ -0,0 +1,9 @@ +# +# Kconfig - Cortex-A9 QEMU Emulation +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_CORTEX_A9 + select QEMU_TARGET diff --git a/boards/qemu/cortex_a9/Kconfig.defconfig b/boards/qemu/cortex_a9/Kconfig.defconfig new file mode 100644 index 00000000000000..c2051fe54087fd --- /dev/null +++ b/boards/qemu/cortex_a9/Kconfig.defconfig @@ -0,0 +1,70 @@ +# +# Kconfig - Cortex-A9 (Zynq-7000) QEMU Emulation +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_QEMU_CORTEX_A9 + +config BUILD_OUTPUT_BIN + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 111111111 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +if LOG_PROCESS_THREAD + +config LOG_PROCESS_THREAD_STACK_SIZE + default 8192 + +endif # LOG_PROCESS_THREAD + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config NET_TX_STACK_SIZE + default 8192 + +config NET_RX_STACK_SIZE + default 8192 + +if NET_TCP + +config NET_TCP_WORKQ_STACK_SIZE + default 8192 + +endif # NET_TCP + +if NET_MGMT_EVENT + +config NET_MGMT_EVENT_STACK_SIZE + default 8192 + +endif # NET_MGMT_EVENT + +config TEST_RANDOM_GENERATOR + default y + +endif # NETWORKING + +if QEMU_ICOUNT + +config QEMU_ICOUNT_SHIFT + default 3 + +config QEMU_ICOUNT_SLEEP + default y + +endif # QEMU_ICOUNT + +config SHELL_STACK_SIZE + default 8192 if SHELL + +endif # BOARD_QEMU_CORTEX_A9 diff --git a/boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 b/boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 new file mode 100644 index 00000000000000..9e869cc2f662e6 --- /dev/null +++ b/boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9 @@ -0,0 +1,9 @@ +# +# Kconfig - Cortex-A9 QEMU Emulation +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_CORTEX_A9 + select SOC_XILINX_XC7Z007S diff --git a/boards/qemu/cortex_a9/board.cmake b/boards/qemu/cortex_a9/board.cmake new file mode 100644 index 00000000000000..45d2dcd7138b48 --- /dev/null +++ b/boards/qemu/cortex_a9/board.cmake @@ -0,0 +1,21 @@ +# +# Copyright (c) 2021, Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH xilinx-aarch64) + +set(QEMU_CPU_TYPE_${ARCH} cortex-a9) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine arm-generic-fdt-7series + -dtb ${CMAKE_CURRENT_LIST_DIR}/fdt-zynq7000s.dtb + ) + +set(QEMU_KERNEL_OPTION + "-device;loader,file=\$,cpu-num=0" + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_a9/board.yml b/boards/qemu/cortex_a9/board.yml new file mode 100644 index 00000000000000..72cba6ce8d9402 --- /dev/null +++ b/boards/qemu/cortex_a9/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_a9 + vendor: qemu + socs: + - name: xc7z007s diff --git a/boards/arm/qemu_cortex_a9/fdt-zynq7000s.dtb b/boards/qemu/cortex_a9/fdt-zynq7000s.dtb similarity index 100% rename from boards/arm/qemu_cortex_a9/fdt-zynq7000s.dtb rename to boards/qemu/cortex_a9/fdt-zynq7000s.dtb diff --git a/boards/arm/qemu_cortex_a9/qemu_cortex_a9.dts b/boards/qemu/cortex_a9/qemu_cortex_a9.dts similarity index 100% rename from boards/arm/qemu_cortex_a9/qemu_cortex_a9.dts rename to boards/qemu/cortex_a9/qemu_cortex_a9.dts diff --git a/boards/arm/qemu_cortex_a9/qemu_cortex_a9.yaml b/boards/qemu/cortex_a9/qemu_cortex_a9.yaml similarity index 100% rename from boards/arm/qemu_cortex_a9/qemu_cortex_a9.yaml rename to boards/qemu/cortex_a9/qemu_cortex_a9.yaml diff --git a/boards/arm/qemu_cortex_a9/qemu_cortex_a9_defconfig b/boards/qemu/cortex_a9/qemu_cortex_a9_defconfig similarity index 82% rename from boards/arm/qemu_cortex_a9/qemu_cortex_a9_defconfig rename to boards/qemu/cortex_a9/qemu_cortex_a9_defconfig index 01c7b5191b8a24..16149af1d7c6d7 100644 --- a/boards/arm/qemu_cortex_a9/qemu_cortex_a9_defconfig +++ b/boards/qemu/cortex_a9/qemu_cortex_a9_defconfig @@ -4,11 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_BOARD_QEMU_CORTEX_A9=y - -CONFIG_SOC_SERIES_XILINX_XC7ZXXXS=y -CONFIG_SOC_XILINX_XC7Z007S=y - CONFIG_ARM_ARCH_TIMER=y CONFIG_SERIAL=y diff --git a/boards/arm/qemu_cortex_m0/CMakeLists.txt b/boards/qemu/cortex_m0/CMakeLists.txt similarity index 100% rename from boards/arm/qemu_cortex_m0/CMakeLists.txt rename to boards/qemu/cortex_m0/CMakeLists.txt diff --git a/boards/qemu/cortex_m0/Kconfig b/boards/qemu/cortex_m0/Kconfig new file mode 100644 index 00000000000000..e0fd84c85d275f --- /dev/null +++ b/boards/qemu/cortex_m0/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M0 + select QEMU_TARGET + +config NRF_TIMER_TIMER + bool "nRF Timer Counter (NRF_TIMER0) Timer" + depends on CLOCK_CONTROL + depends on SOC_COMPATIBLE_NRF + depends on SYS_CLOCK_EXISTS + select TICKLESS_CAPABLE + default y + help + This module implements a kernel device driver for the nRF Timer + Counter NRF_TIMER0 and provides the standard "system clock driver" + interfaces. diff --git a/boards/qemu/cortex_m0/Kconfig.defconfig b/boards/qemu/cortex_m0/Kconfig.defconfig new file mode 100644 index 00000000000000..3bdf627121275a --- /dev/null +++ b/boards/qemu/cortex_m0/Kconfig.defconfig @@ -0,0 +1,17 @@ +# QEMU Cortex-M0 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_M0 + +config NRF_RTC_TIMER + default n if SYS_CLOCK_EXISTS + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 100 + +endif # BOARD_QEMU_CORTEX_M0 diff --git a/boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 b/boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 new file mode 100644 index 00000000000000..9c99bb7d2f3bb2 --- /dev/null +++ b/boards/qemu/cortex_m0/Kconfig.qemu_cortex_m0 @@ -0,0 +1,7 @@ +# QEMU Cortex-M0 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M0 + select SOC_NRF51822_QFAA diff --git a/boards/arm/qemu_cortex_m0/board.cmake b/boards/qemu/cortex_m0/board.cmake similarity index 100% rename from boards/arm/qemu_cortex_m0/board.cmake rename to boards/qemu/cortex_m0/board.cmake diff --git a/boards/qemu/cortex_m0/board.yml b/boards/qemu/cortex_m0/board.yml new file mode 100644 index 00000000000000..fc71c63896ba11 --- /dev/null +++ b/boards/qemu/cortex_m0/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_m0 + vendor: nordic + socs: + - name: nrf51822 diff --git a/boards/arm/qemu_cortex_m0/doc/index.rst b/boards/qemu/cortex_m0/doc/index.rst similarity index 100% rename from boards/arm/qemu_cortex_m0/doc/index.rst rename to boards/qemu/cortex_m0/doc/index.rst diff --git a/boards/arm/qemu_cortex_m0/nrf_timer_timer.c b/boards/qemu/cortex_m0/nrf_timer_timer.c similarity index 100% rename from boards/arm/qemu_cortex_m0/nrf_timer_timer.c rename to boards/qemu/cortex_m0/nrf_timer_timer.c diff --git a/boards/arm/nrf51dk_nrf51422/pre_dt_board.cmake b/boards/qemu/cortex_m0/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51dk_nrf51422/pre_dt_board.cmake rename to boards/qemu/cortex_m0/pre_dt_board.cmake diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0-pinctrl.dtsi b/boards/qemu/cortex_m0/qemu_cortex_m0-pinctrl.dtsi similarity index 100% rename from boards/arm/qemu_cortex_m0/qemu_cortex_m0-pinctrl.dtsi rename to boards/qemu/cortex_m0/qemu_cortex_m0-pinctrl.dtsi diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0.dts b/boards/qemu/cortex_m0/qemu_cortex_m0.dts similarity index 100% rename from boards/arm/qemu_cortex_m0/qemu_cortex_m0.dts rename to boards/qemu/cortex_m0/qemu_cortex_m0.dts diff --git a/boards/arm/qemu_cortex_m0/qemu_cortex_m0.yaml b/boards/qemu/cortex_m0/qemu_cortex_m0.yaml similarity index 100% rename from boards/arm/qemu_cortex_m0/qemu_cortex_m0.yaml rename to boards/qemu/cortex_m0/qemu_cortex_m0.yaml diff --git a/boards/qemu/cortex_m0/qemu_cortex_m0_defconfig b/boards/qemu/cortex_m0/qemu_cortex_m0_defconfig new file mode 100644 index 00000000000000..6b0fce4e16a1a1 --- /dev/null +++ b/boards/qemu/cortex_m0/qemu_cortex_m0_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_QEMU_ICOUNT_SHIFT=6 + +# Enable GPIO +CONFIG_GPIO=y + +# Clock control +CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# icount is kinda broken when the NRF timer emulation is used +CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/cortex_m3/Kconfig b/boards/qemu/cortex_m3/Kconfig new file mode 100644 index 00000000000000..eef57a4eea4196 --- /dev/null +++ b/boards/qemu/cortex_m3/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M3 + select QEMU_TARGET diff --git a/boards/qemu/cortex_m3/Kconfig.defconfig b/boards/qemu/cortex_m3/Kconfig.defconfig new file mode 100644 index 00000000000000..07f168ce4145bb --- /dev/null +++ b/boards/qemu/cortex_m3/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_M3 + +config BUILD_OUTPUT_BIN + default n + +# DWT is not properly emulated in QEMU +choice NULL_POINTER_EXCEPTION_DETECTION + bool + default NULL_POINTER_EXCEPTION_DETECTION_NONE +endchoice + +endif # BOARD_QEMU_CORTEX_M3 diff --git a/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 b/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 new file mode 100644 index 00000000000000..0e8d2cb23015c0 --- /dev/null +++ b/boards/qemu/cortex_m3/Kconfig.qemu_cortex_m3 @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_M3 + select SOC_TI_LM3S6965 + help + Cortex-M3 Emulation (QEMU) diff --git a/boards/qemu/cortex_m3/board.cmake b/boards/qemu/cortex_m3/board.cmake new file mode 100644 index 00000000000000..47d20e706a9776 --- /dev/null +++ b/boards/qemu/cortex_m3/board.cmake @@ -0,0 +1,13 @@ +# Copyright (c) 2016 Zephyr Contributors +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_CPU_TYPE_${ARCH} cortex-m3) +set(QEMU_FLAGS_${ARCH} + -cpu ${QEMU_CPU_TYPE_${ARCH}} + -machine lm3s6965evb + -nographic + -vga none + ) +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_m3/board.yml b/boards/qemu/cortex_m3/board.yml new file mode 100644 index 00000000000000..5566adb5e02f91 --- /dev/null +++ b/boards/qemu/cortex_m3/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_m3 + vendor: qemu + socs: + - name: ti_lm3s6965 diff --git a/boards/arm/qemu_cortex_m3/doc/index.rst b/boards/qemu/cortex_m3/doc/index.rst similarity index 100% rename from boards/arm/qemu_cortex_m3/doc/index.rst rename to boards/qemu/cortex_m3/doc/index.rst diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts b/boards/qemu/cortex_m3/qemu_cortex_m3.dts similarity index 95% rename from boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts rename to boards/qemu/cortex_m3/qemu_cortex_m3.dts index 2d8e2f02dc6f32..2e0bd95755f275 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.dts +++ b/boards/qemu/cortex_m3/qemu_cortex_m3.dts @@ -1,3 +1,4 @@ +/* Copyright (c) 2016 Zephyr Contributors */ /* SPDX-License-Identifier: Apache-2.0 */ /dts-v1/; diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3.yaml b/boards/qemu/cortex_m3/qemu_cortex_m3.yaml similarity index 100% rename from boards/arm/qemu_cortex_m3/qemu_cortex_m3.yaml rename to boards/qemu/cortex_m3/qemu_cortex_m3.yaml diff --git a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig b/boards/qemu/cortex_m3/qemu_cortex_m3_defconfig similarity index 77% rename from boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig rename to boards/qemu/cortex_m3/qemu_cortex_m3_defconfig index 7abc1e1d58a5fd..ed69699fa71014 100644 --- a/boards/arm/qemu_cortex_m3/qemu_cortex_m3_defconfig +++ b/boards/qemu/cortex_m3/qemu_cortex_m3_defconfig @@ -1,8 +1,7 @@ +# Copyright (c) 2016 Zephyr Contributors # SPDX-License-Identifier: Apache-2.0 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000 -CONFIG_SOC_TI_LM3S6965=y -CONFIG_BOARD_QEMU_CORTEX_M3=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/qemu/cortex_r5/Kconfig b/boards/qemu/cortex_r5/Kconfig new file mode 100644 index 00000000000000..1b7fa887f417c0 --- /dev/null +++ b/boards/qemu/cortex_r5/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_R5 + select QEMU_TARGET diff --git a/boards/qemu/cortex_r5/Kconfig.defconfig b/boards/qemu/cortex_r5/Kconfig.defconfig new file mode 100644 index 00000000000000..a6ea313a4ab886 --- /dev/null +++ b/boards/qemu/cortex_r5/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_CORTEX_R5 + +config BUILD_OUTPUT_BIN + default n + +if USERSPACE + +config COMPILER_ISA_THUMB2 + default n + +endif + +endif # BOARD_QEMU_CORTEX_R5 diff --git a/boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 b/boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 new file mode 100644 index 00000000000000..054936f844b009 --- /dev/null +++ b/boards/qemu/cortex_r5/Kconfig.qemu_cortex_r5 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_CORTEX_R5 + select SOC_XILINX_ZYNQMP_RPU diff --git a/boards/qemu/cortex_r5/board.cmake b/boards/qemu/cortex_r5/board.cmake new file mode 100644 index 00000000000000..0b35a9e6e4b865 --- /dev/null +++ b/boards/qemu/cortex_r5/board.cmake @@ -0,0 +1,21 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) +set(QEMU_ARCH xilinx-aarch64) + +set(QEMU_CPU_TYPE_${ARCH} cortex-r5) +set(QEMU_FLAGS_${ARCH} + -nographic + -machine arm-generic-fdt + -dtb ${CMAKE_CURRENT_LIST_DIR}/fdt-single_arch-zcu102-arm.dtb + ) + +set(QEMU_KERNEL_OPTION + "-device;loader,file=\$,cpu-num=4" + "-device;loader,addr=0xff5e023c,data=0x80008fde,data-len=4" + "-device;loader,addr=0xff9a0000,data=0x80000218,data-len=4" + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/cortex_r5/board.yml b/boards/qemu/cortex_r5/board.yml new file mode 100644 index 00000000000000..6cf5b2fee95437 --- /dev/null +++ b/boards/qemu/cortex_r5/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_cortex_r5 + vendor: qemu + socs: + - name: zynqmp_rpu diff --git a/boards/arm/qemu_cortex_r5/doc/index.rst b/boards/qemu/cortex_r5/doc/index.rst similarity index 100% rename from boards/arm/qemu_cortex_r5/doc/index.rst rename to boards/qemu/cortex_r5/doc/index.rst diff --git a/boards/arm/qemu_cortex_r5/fdt-single_arch-zcu102-arm.dtb b/boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb similarity index 100% rename from boards/arm/qemu_cortex_r5/fdt-single_arch-zcu102-arm.dtb rename to boards/qemu/cortex_r5/fdt-single_arch-zcu102-arm.dtb diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts b/boards/qemu/cortex_r5/qemu_cortex_r5.dts similarity index 100% rename from boards/arm/qemu_cortex_r5/qemu_cortex_r5.dts rename to boards/qemu/cortex_r5/qemu_cortex_r5.dts diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5.yaml b/boards/qemu/cortex_r5/qemu_cortex_r5.yaml similarity index 100% rename from boards/arm/qemu_cortex_r5/qemu_cortex_r5.yaml rename to boards/qemu/cortex_r5/qemu_cortex_r5.yaml diff --git a/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig b/boards/qemu/cortex_r5/qemu_cortex_r5_defconfig similarity index 79% rename from boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig rename to boards/qemu/cortex_r5/qemu_cortex_r5_defconfig index ac7ff922ed76f2..40e22978ec0b93 100644 --- a/boards/arm/qemu_cortex_r5/qemu_cortex_r5_defconfig +++ b/boards/qemu/cortex_r5/qemu_cortex_r5_defconfig @@ -1,5 +1,3 @@ -CONFIG_SOC_XILINX_ZYNQMP_RPU=y -CONFIG_BOARD_QEMU_CORTEX_R5=y CONFIG_XIP=n CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/qemu/index.rst b/boards/qemu/index.rst new file mode 100644 index 00000000000000..6f640ed331137c --- /dev/null +++ b/boards/qemu/index.rst @@ -0,0 +1,10 @@ +.. _boards-qemu: + +QEMU +#### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/qemu/kvm_arm64/Kconfig b/boards/qemu/kvm_arm64/Kconfig new file mode 100644 index 00000000000000..960c63886abfd8 --- /dev/null +++ b/boards/qemu/kvm_arm64/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_KVM_ARM64 + select ARM64 + select QEMU_TARGET diff --git a/boards/qemu/kvm_arm64/Kconfig.defconfig b/boards/qemu/kvm_arm64/Kconfig.defconfig new file mode 100644 index 00000000000000..7d13e73aa7f471 --- /dev/null +++ b/boards/qemu/kvm_arm64/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_KVM_ARM64 + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_QEMU_KVM_ARM64 diff --git a/boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 b/boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 new file mode 100644 index 00000000000000..6f4df12bad6f45 --- /dev/null +++ b/boards/qemu/kvm_arm64/Kconfig.qemu_kvm_arm64 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Huawei France Technologies SASU +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_KVM_ARM64 + select SOC_QEMU_VIRT_ARM64 diff --git a/boards/arm64/qemu_kvm_arm64/board.cmake b/boards/qemu/kvm_arm64/board.cmake similarity index 100% rename from boards/arm64/qemu_kvm_arm64/board.cmake rename to boards/qemu/kvm_arm64/board.cmake diff --git a/boards/qemu/kvm_arm64/board.yml b/boards/qemu/kvm_arm64/board.yml new file mode 100644 index 00000000000000..dd0edf80316d2a --- /dev/null +++ b/boards/qemu/kvm_arm64/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_kvm_arm64 + vendor: arm + socs: + - name: qemu_virt_arm64 diff --git a/boards/arm64/qemu_kvm_arm64/doc/index.rst b/boards/qemu/kvm_arm64/doc/index.rst similarity index 100% rename from boards/arm64/qemu_kvm_arm64/doc/index.rst rename to boards/qemu/kvm_arm64/doc/index.rst diff --git a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.dts b/boards/qemu/kvm_arm64/qemu_kvm_arm64.dts similarity index 100% rename from boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.dts rename to boards/qemu/kvm_arm64/qemu_kvm_arm64.dts diff --git a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.yaml b/boards/qemu/kvm_arm64/qemu_kvm_arm64.yaml similarity index 100% rename from boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64.yaml rename to boards/qemu/kvm_arm64/qemu_kvm_arm64.yaml diff --git a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64_defconfig b/boards/qemu/kvm_arm64/qemu_kvm_arm64_defconfig similarity index 83% rename from boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64_defconfig rename to boards/qemu/kvm_arm64/qemu_kvm_arm64_defconfig index f94384176d92c4..0060ce3f82f9a0 100644 --- a/boards/arm64/qemu_kvm_arm64/qemu_kvm_arm64_defconfig +++ b/boards/qemu/kvm_arm64/qemu_kvm_arm64_defconfig @@ -1,5 +1,3 @@ -CONFIG_SOC_QEMU_VIRT_ARM64=y -CONFIG_BOARD_QEMU_KVM_ARM64=y CONFIG_ARM_ARCH_TIMER=y CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/leon3/Kconfig b/boards/qemu/leon3/Kconfig new file mode 100644 index 00000000000000..f99064ef58cbc2 --- /dev/null +++ b/boards/qemu/leon3/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_LEON3 + select QEMU_TARGET + select CPU_HAS_FPU diff --git a/boards/qemu/leon3/Kconfig.defconfig b/boards/qemu/leon3/Kconfig.defconfig new file mode 100644 index 00000000000000..f90c04a345cdb2 --- /dev/null +++ b/boards/qemu/leon3/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_LEON3 + +config UART_INTERRUPT_DRIVEN + default y + +endif diff --git a/boards/qemu/leon3/Kconfig.qemu_leon3 b/boards/qemu/leon3/Kconfig.qemu_leon3 new file mode 100644 index 00000000000000..06d2be337b0dac --- /dev/null +++ b/boards/qemu/leon3/Kconfig.qemu_leon3 @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_LEON3 + select SOC_LEON3 diff --git a/boards/sparc/qemu_leon3/board.cmake b/boards/qemu/leon3/board.cmake similarity index 100% rename from boards/sparc/qemu_leon3/board.cmake rename to boards/qemu/leon3/board.cmake diff --git a/boards/qemu/leon3/board.yml b/boards/qemu/leon3/board.yml new file mode 100644 index 00000000000000..6d4fdc189bf799 --- /dev/null +++ b/boards/qemu/leon3/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_leon3 + vendor: gaisler + socs: + - name: leon3 diff --git a/boards/sparc/qemu_leon3/doc/index.rst b/boards/qemu/leon3/doc/index.rst similarity index 100% rename from boards/sparc/qemu_leon3/doc/index.rst rename to boards/qemu/leon3/doc/index.rst diff --git a/boards/sparc/qemu_leon3/qemu_leon3.dts b/boards/qemu/leon3/qemu_leon3.dts similarity index 100% rename from boards/sparc/qemu_leon3/qemu_leon3.dts rename to boards/qemu/leon3/qemu_leon3.dts diff --git a/boards/sparc/qemu_leon3/qemu_leon3.yaml b/boards/qemu/leon3/qemu_leon3.yaml similarity index 100% rename from boards/sparc/qemu_leon3/qemu_leon3.yaml rename to boards/qemu/leon3/qemu_leon3.yaml diff --git a/boards/sparc/qemu_leon3/qemu_leon3_defconfig b/boards/qemu/leon3/qemu_leon3_defconfig similarity index 77% rename from boards/sparc/qemu_leon3/qemu_leon3_defconfig rename to boards/qemu/leon3/qemu_leon3_defconfig index 7f57d930478e92..72f7285f6087d7 100644 --- a/boards/sparc/qemu_leon3/qemu_leon3_defconfig +++ b/boards/qemu/leon3/qemu_leon3_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_LEON3=y -CONFIG_BOARD_QEMU_LEON3=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/qemu/malta/Kconfig b/boards/qemu/malta/Kconfig new file mode 100644 index 00000000000000..5813610828d1e0 --- /dev/null +++ b/boards/qemu/malta/Kconfig @@ -0,0 +1,9 @@ +# +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_MALTA + select QEMU_TARGET + select BIG_ENDIAN if BOARD_QEMU_MALTA_QEMU_MALTA_BE diff --git a/boards/qemu/malta/Kconfig.defconfig b/boards/qemu/malta/Kconfig.defconfig new file mode 100644 index 00000000000000..fb24d3b5b473db --- /dev/null +++ b/boards/qemu/malta/Kconfig.defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_QEMU_MALTA + +config BUILD_OUTPUT_BIN + default n + +endif # BOARD_QEMU_MALTA diff --git a/boards/qemu/malta/Kconfig.qemu_malta b/boards/qemu/malta/Kconfig.qemu_malta new file mode 100644 index 00000000000000..fe93f3b3874ffb --- /dev/null +++ b/boards/qemu/malta/Kconfig.qemu_malta @@ -0,0 +1,8 @@ +# +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 +# + +config BOARD_QEMU_MALTA + select SOC_QEMU_MALTA diff --git a/boards/mips/qemu_malta/board.cmake b/boards/qemu/malta/board.cmake similarity index 100% rename from boards/mips/qemu_malta/board.cmake rename to boards/qemu/malta/board.cmake diff --git a/boards/qemu/malta/board.yml b/boards/qemu/malta/board.yml new file mode 100644 index 00000000000000..050bd381c734a4 --- /dev/null +++ b/boards/qemu/malta/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_malta + vendor: qemu + socs: + - name: qemu_malta + variants: + - name: 'be' diff --git a/boards/qemu/malta/doc/index.rst b/boards/qemu/malta/doc/index.rst new file mode 100644 index 00000000000000..178d787f9515f1 --- /dev/null +++ b/boards/qemu/malta/doc/index.rst @@ -0,0 +1,106 @@ +.. _qemu_malta: + +MIPS Malta Emulation (QEMU) +########################### + +Overview +******** + +This board configuration will use QEMU to emulate the MIPS Malta platform. + +This configuration provides support for an MIPS 4Kc/24Kc CPU cores and these devices: + +* CP0 Interrupt Controller +* CP0 Core Timer +* NS16550 UART + + +.. note:: + This board configuration makes no claims about its suitability for use + with an actual MIPS Malta hardware system, or any other hardware system. + +Hardware +******** + +Supported Features +================== + +The following hardware features are supported: + ++----------------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++================+============+======================+ +| CP0 IntC | on-chip | interrupt controller | ++----------------+------------+----------------------+ +| CP0 Core Timer | on-chip | system clock | ++----------------+------------+----------------------+ +| NS16550 | FPGA | serial port | +| UART | | | ++----------------+------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +Devices +======== +System Clock +------------ + +Qemu CP0 timer uses a clock frequency of 200 MHz, +see target/mips/cp0_timer.c in Qemu source tree for details. + +Serial Port +----------- + +This board configuration uses a single serial communication channel +with the FPGA UART2. + +Programming and Debugging +************************* + +Use this configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_malta + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build v2.7.99-1627-g9bea7790d620 *** + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + thread_a: Hello World from cpu 0 on qemu_malta! + thread_b: Hello World from cpu 0 on qemu_malta! + + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + + +Big-Endian +========== + +Use this configuration to run :zephyr:code-sample:`synchronization` sample in big-endian mode: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_malta//be + :goals: run + + +References +********** + +https://www.qemu.org/ +https://www.linux-mips.org/wiki/MIPS_Malta diff --git a/boards/mips/qemu_malta/qemu_malta.dts b/boards/qemu/malta/qemu_malta.dts similarity index 100% rename from boards/mips/qemu_malta/qemu_malta.dts rename to boards/qemu/malta/qemu_malta.dts diff --git a/boards/mips/qemu_malta/qemu_malta.yaml b/boards/qemu/malta/qemu_malta.yaml similarity index 100% rename from boards/mips/qemu_malta/qemu_malta.yaml rename to boards/qemu/malta/qemu_malta.yaml diff --git a/boards/qemu/malta/qemu_malta_defconfig b/boards/qemu/malta/qemu_malta_defconfig new file mode 100644 index 00000000000000..fe217db926bc96 --- /dev/null +++ b/boards/qemu/malta/qemu_malta_defconfig @@ -0,0 +1,6 @@ +CONFIG_MIPS_CP0_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT=y +CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/mips/qemu_malta/qemu_malta_be.dts b/boards/qemu/malta/qemu_malta_qemu_malta_be.dts similarity index 100% rename from boards/mips/qemu_malta/qemu_malta_be.dts rename to boards/qemu/malta/qemu_malta_qemu_malta_be.dts diff --git a/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml new file mode 100644 index 00000000000000..98aa9884dbf351 --- /dev/null +++ b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml @@ -0,0 +1,16 @@ +identifier: qemu_malta//be +name: QEMU emulation for MIPS (big endian) +type: qemu +simulation: qemu +arch: mips +toolchain: + - zephyr + - xtools +ram: 1024 +flash: 512 +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: qemu diff --git a/boards/qemu/malta/qemu_malta_qemu_malta_be_defconfig b/boards/qemu/malta/qemu_malta_qemu_malta_be_defconfig new file mode 100644 index 00000000000000..fe217db926bc96 --- /dev/null +++ b/boards/qemu/malta/qemu_malta_qemu_malta_be_defconfig @@ -0,0 +1,6 @@ +CONFIG_MIPS_CP0_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_QEMU_ICOUNT=y +CONFIG_QEMU_ICOUNT_SHIFT=3 diff --git a/boards/qemu/nios2/Kconfig b/boards/qemu/nios2/Kconfig new file mode 100644 index 00000000000000..22dbe917954838 --- /dev/null +++ b/boards/qemu/nios2/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_NIOS2 + select QEMU_TARGET diff --git a/boards/qemu/nios2/Kconfig.defconfig b/boards/qemu/nios2/Kconfig.defconfig new file mode 100644 index 00000000000000..81494ff905ec41 --- /dev/null +++ b/boards/qemu/nios2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_NIOS2 + +config BUILD_OUTPUT_BIN + default n + +endif diff --git a/boards/qemu/nios2/Kconfig.qemu_nios2 b/boards/qemu/nios2/Kconfig.qemu_nios2 new file mode 100644 index 00000000000000..23292f07ffb126 --- /dev/null +++ b/boards/qemu/nios2/Kconfig.qemu_nios2 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_NIOS2 + select SOC_QEMU_NIOS2 diff --git a/boards/qemu/nios2/board.cmake b/boards/qemu/nios2/board.cmake new file mode 100644 index 00000000000000..9f9bf21124c84f --- /dev/null +++ b/boards/qemu/nios2/board.cmake @@ -0,0 +1,13 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_CPU_TYPE_${ARCH} nios2) + +set(QEMU_FLAGS_${ARCH} + -machine altera_10m50_zephyr + -nographic + ) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/nios2/board.yml b/boards/qemu/nios2/board.yml new file mode 100644 index 00000000000000..93f6487d31887f --- /dev/null +++ b/boards/qemu/nios2/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_nios2 + vendor: altr + socs: + - name: qemu_nios2 diff --git a/boards/nios2/qemu_nios2/doc/index.rst b/boards/qemu/nios2/doc/index.rst similarity index 100% rename from boards/nios2/qemu_nios2/doc/index.rst rename to boards/qemu/nios2/doc/index.rst diff --git a/boards/nios2/qemu_nios2/qemu_nios2.dts b/boards/qemu/nios2/qemu_nios2.dts similarity index 100% rename from boards/nios2/qemu_nios2/qemu_nios2.dts rename to boards/qemu/nios2/qemu_nios2.dts diff --git a/boards/nios2/qemu_nios2/qemu_nios2.yaml b/boards/qemu/nios2/qemu_nios2.yaml similarity index 100% rename from boards/nios2/qemu_nios2/qemu_nios2.yaml rename to boards/qemu/nios2/qemu_nios2.yaml diff --git a/boards/nios2/qemu_nios2/qemu_nios2_defconfig b/boards/qemu/nios2/qemu_nios2_defconfig similarity index 80% rename from boards/nios2/qemu_nios2/qemu_nios2_defconfig rename to boards/qemu/nios2/qemu_nios2_defconfig index 7820e1f8fc576b..feda1075277c32 100644 --- a/boards/nios2/qemu_nios2/qemu_nios2_defconfig +++ b/boards/qemu/nios2/qemu_nios2_defconfig @@ -1,7 +1,6 @@ +# Copyright (c) 2018 Intel Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_NIOS2_QEMU=y -CONFIG_BOARD_QEMU_NIOS2=y CONFIG_HAS_ALTERA_HAL=y CONFIG_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/qemu/riscv32/Kconfig b/boards/qemu/riscv32/Kconfig new file mode 100644 index 00000000000000..96de9ecb507345 --- /dev/null +++ b/boards/qemu/riscv32/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32 + select QEMU_TARGET diff --git a/boards/qemu/riscv32/Kconfig.defconfig b/boards/qemu/riscv32/Kconfig.defconfig new file mode 100644 index 00000000000000..8564054e21de5f --- /dev/null +++ b/boards/qemu/riscv32/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV32 + +# Use thread local storage by default so that this feature gets more CI coverage. +config THREAD_LOCAL_STORAGE + default y + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +config QEMU_ICOUNT_SHIFT + default 6 if QEMU_ICOUNT + +endif # BOARD_QEMU_RISCV32 diff --git a/boards/qemu/riscv32/Kconfig.qemu_riscv32 b/boards/qemu/riscv32/Kconfig.qemu_riscv32 new file mode 100644 index 00000000000000..39f614e955b09c --- /dev/null +++ b/boards/qemu/riscv32/Kconfig.qemu_riscv32 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32 + select SOC_QEMU_VIRT_RISCV32 diff --git a/boards/qemu/riscv32/board.cmake b/boards/qemu/riscv32/board.cmake new file mode 100644 index 00000000000000..1e13b4b5176cb8 --- /dev/null +++ b/boards/qemu/riscv32/board.cmake @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_binary_suffix riscv32) +set(QEMU_CPU_TYPE_${ARCH} riscv32) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine virt + -bios none + -m 256 +) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv32/board.yml b/boards/qemu/riscv32/board.yml new file mode 100644 index 00000000000000..0ba208612a9906 --- /dev/null +++ b/boards/qemu/riscv32/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_riscv32 + vendor: qemu + socs: + - name: qemu_virt_riscv32 + variants: + - name: smp diff --git a/boards/riscv/qemu_riscv32/doc/index.rst b/boards/qemu/riscv32/doc/index.rst similarity index 100% rename from boards/riscv/qemu_riscv32/doc/index.rst rename to boards/qemu/riscv32/doc/index.rst diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32.dts b/boards/qemu/riscv32/qemu_riscv32.dts similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32.dts rename to boards/qemu/riscv32/qemu_riscv32.dts diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32.yaml b/boards/qemu/riscv32/qemu_riscv32.yaml similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32.yaml rename to boards/qemu/riscv32/qemu_riscv32.yaml diff --git a/boards/qemu/riscv32/qemu_riscv32_defconfig b/boards/qemu/riscv32/qemu_riscv32_defconfig new file mode 100644 index 00000000000000..7a822571bb3c39 --- /dev/null +++ b/boards/qemu/riscv32/qemu_riscv32_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_STACK_SENTINEL=y +CONFIG_XIP=n +CONFIG_RISCV_PMP=y diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml new file mode 100644 index 00000000000000..ee9af4a3083f85 --- /dev/null +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml @@ -0,0 +1,16 @@ +identifier: qemu_riscv32/qemu_virt_riscv32/smp +name: QEMU Emulation for RISC-V 32-bit SMP +type: qemu +simulation: qemu +arch: riscv +toolchain: + - zephyr + - xtools +supported: + - netif + - smp +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig new file mode 100644 index 00000000000000..412b05982f3028 --- /dev/null +++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_IDLE_STACK_SIZE=1024 +CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/riscv32_xip/Kconfig b/boards/qemu/riscv32_xip/Kconfig new file mode 100644 index 00000000000000..233b31d0f18601 --- /dev/null +++ b/boards/qemu/riscv32_xip/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32_XIP + select QEMU_TARGET diff --git a/boards/qemu/riscv32_xip/Kconfig.defconfig b/boards/qemu/riscv32_xip/Kconfig.defconfig new file mode 100644 index 00000000000000..27142fceed5732 --- /dev/null +++ b/boards/qemu/riscv32_xip/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV32_XIP + +# Use thread local storage by default so that this feature gets more CI coverage. +config THREAD_LOCAL_STORAGE + default y + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_QEMU_RISCV32_XIP diff --git a/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip new file mode 100644 index 00000000000000..ac31b7857eb918 --- /dev/null +++ b/boards/qemu/riscv32_xip/Kconfig.qemu_riscv32_xip @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32_XIP + select SOC_SIFIVE_FREEDOM_FE310 diff --git a/boards/qemu/riscv32_xip/board.cmake b/boards/qemu/riscv32_xip/board.cmake new file mode 100644 index 00000000000000..d1132858b48bcf --- /dev/null +++ b/boards/qemu/riscv32_xip/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +set(SUPPORTED_EMU_PLATFORMS qemu) + +set(QEMU_binary_suffix riscv32) +set(QEMU_CPU_TYPE_${ARCH} riscv32) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine sifive_e +) + +board_set_debugger_ifnset(qemu) diff --git a/boards/qemu/riscv32_xip/board.yml b/boards/qemu/riscv32_xip/board.yml new file mode 100644 index 00000000000000..beca29532f45bd --- /dev/null +++ b/boards/qemu/riscv32_xip/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_riscv32_xip + vendor: qemu + socs: + - name: fe310 diff --git a/boards/qemu/riscv32_xip/doc/index.rst b/boards/qemu/riscv32_xip/doc/index.rst new file mode 100644 index 00000000000000..4cc4f30522fda0 --- /dev/null +++ b/boards/qemu/riscv32_xip/doc/index.rst @@ -0,0 +1,55 @@ +.. _qemu_riscv32_xip: + +RISCV32 XIP Emulation (QEMU) +############################ + +Overview +******** + +The RISCV32 XIP QEMU board configuration is used to emulate the RISCV32 architecture. + +Programming and Debugging +************************* + +Applications for the ``qemu_riscv32_xip`` board configuration can be built and run in +the usual way for emulated boards (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +While this board is emulated and you can't "flash" it, you can use this +configuration to run basic Zephyr applications and kernel tests in the QEMU +emulated environment. For example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: qemu_riscv32_xip + :goals: run + +This will build an image with the synchronization sample app, boot it using +QEMU, and display the following console output: + +.. code-block:: console + + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + thread_b: Hello World from cpu 0 on qemu_riscv32_xip! + thread_a: Hello World from cpu 0 on qemu_riscv32_xip! + +Exit QEMU by pressing :kbd:`CTRL+A` :kbd:`x`. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi b/boards/qemu/riscv32_xip/qemu_riscv32_xip-pinctrl.dtsi similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi rename to boards/qemu/riscv32_xip/qemu_riscv32_xip-pinctrl.dtsi diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts b/boards/qemu/riscv32_xip/qemu_riscv32_xip.dts similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32_xip.dts rename to boards/qemu/riscv32_xip/qemu_riscv32_xip.dts diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip.yaml b/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml similarity index 100% rename from boards/riscv/qemu_riscv32/qemu_riscv32_xip.yaml rename to boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml diff --git a/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig new file mode 100644 index 00000000000000..f9bc269d13f278 --- /dev/null +++ b/boards/qemu/riscv32_xip/qemu_riscv32_xip_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 +CONFIG_QEMU_ICOUNT_SHIFT=6 +CONFIG_RISCV_CORE_E31=y diff --git a/boards/qemu/riscv32e/Kconfig b/boards/qemu/riscv32e/Kconfig new file mode 100644 index 00000000000000..515c3d7287ab0f --- /dev/null +++ b/boards/qemu/riscv32e/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32E + select QEMU_TARGET diff --git a/boards/qemu/riscv32e/Kconfig.defconfig b/boards/qemu/riscv32e/Kconfig.defconfig new file mode 100644 index 00000000000000..c3424c8722a924 --- /dev/null +++ b/boards/qemu/riscv32e/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV32E + +# Use thread local storage by default so that this feature gets more CI coverage. +config THREAD_LOCAL_STORAGE + default y + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_QEMU_RISCV32E diff --git a/boards/qemu/riscv32e/Kconfig.qemu_riscv32e b/boards/qemu/riscv32e/Kconfig.qemu_riscv32e new file mode 100644 index 00000000000000..f1256088e617cc --- /dev/null +++ b/boards/qemu/riscv32e/Kconfig.qemu_riscv32e @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV32E + select SOC_QEMU_VIRT_RISCV32E diff --git a/boards/riscv/qemu_riscv32e/board.cmake b/boards/qemu/riscv32e/board.cmake similarity index 100% rename from boards/riscv/qemu_riscv32e/board.cmake rename to boards/qemu/riscv32e/board.cmake diff --git a/boards/qemu/riscv32e/board.yml b/boards/qemu/riscv32e/board.yml new file mode 100644 index 00000000000000..cc8e6f0beccf60 --- /dev/null +++ b/boards/qemu/riscv32e/board.yml @@ -0,0 +1,5 @@ +board: + name: qemu_riscv32e + vendor: qemu + socs: + - name: qemu_virt_riscv32e diff --git a/boards/riscv/qemu_riscv32e/doc/index.rst b/boards/qemu/riscv32e/doc/index.rst similarity index 100% rename from boards/riscv/qemu_riscv32e/doc/index.rst rename to boards/qemu/riscv32e/doc/index.rst diff --git a/boards/riscv/qemu_riscv32e/qemu_riscv32e.dts b/boards/qemu/riscv32e/qemu_riscv32e.dts similarity index 100% rename from boards/riscv/qemu_riscv32e/qemu_riscv32e.dts rename to boards/qemu/riscv32e/qemu_riscv32e.dts diff --git a/boards/riscv/qemu_riscv32e/qemu_riscv32e.yaml b/boards/qemu/riscv32e/qemu_riscv32e.yaml similarity index 100% rename from boards/riscv/qemu_riscv32e/qemu_riscv32e.yaml rename to boards/qemu/riscv32e/qemu_riscv32e.yaml diff --git a/boards/riscv/qemu_riscv32e/qemu_riscv32e_defconfig b/boards/qemu/riscv32e/qemu_riscv32e_defconfig similarity index 76% rename from boards/riscv/qemu_riscv32e/qemu_riscv32e_defconfig rename to boards/qemu/riscv32e/qemu_riscv32e_defconfig index 1f1c46acb10c64..affc1eeffb7406 100644 --- a/boards/riscv/qemu_riscv32e/qemu_riscv32e_defconfig +++ b/boards/qemu/riscv32e/qemu_riscv32e_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV32E=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/qemu/riscv64/Kconfig b/boards/qemu/riscv64/Kconfig new file mode 100644 index 00000000000000..6adb7c150323a5 --- /dev/null +++ b/boards/qemu/riscv64/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV64 + select QEMU_TARGET diff --git a/boards/qemu/riscv64/Kconfig.defconfig b/boards/qemu/riscv64/Kconfig.defconfig new file mode 100644 index 00000000000000..90a501d002d0f3 --- /dev/null +++ b/boards/qemu/riscv64/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_RISCV64 + +config BUILD_OUTPUT_BIN + default n + +config HAS_COVERAGE_SUPPORT + default y + +config QEMU_ICOUNT_SHIFT + default 6 if QEMU_ICOUNT + +endif # BOARD_QEMU_RISCV64 diff --git a/boards/qemu/riscv64/Kconfig.qemu_riscv64 b/boards/qemu/riscv64/Kconfig.qemu_riscv64 new file mode 100644 index 00000000000000..7d136aebb22716 --- /dev/null +++ b/boards/qemu/riscv64/Kconfig.qemu_riscv64 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_RISCV64 + select SOC_QEMU_VIRT_RISCV64 diff --git a/boards/riscv/qemu_riscv64/board.cmake b/boards/qemu/riscv64/board.cmake similarity index 100% rename from boards/riscv/qemu_riscv64/board.cmake rename to boards/qemu/riscv64/board.cmake diff --git a/boards/qemu/riscv64/board.yml b/boards/qemu/riscv64/board.yml new file mode 100644 index 00000000000000..aa51fd1fdbaeb7 --- /dev/null +++ b/boards/qemu/riscv64/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_riscv64 + vendor: qemu + socs: + - name: qemu_virt_riscv64 + variants: + - name: smp diff --git a/boards/riscv/qemu_riscv64/doc/index.rst b/boards/qemu/riscv64/doc/index.rst similarity index 100% rename from boards/riscv/qemu_riscv64/doc/index.rst rename to boards/qemu/riscv64/doc/index.rst diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64.dts b/boards/qemu/riscv64/qemu_riscv64.dts similarity index 100% rename from boards/riscv/qemu_riscv64/qemu_riscv64.dts rename to boards/qemu/riscv64/qemu_riscv64.dts diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64.yaml b/boards/qemu/riscv64/qemu_riscv64.yaml similarity index 100% rename from boards/riscv/qemu_riscv64/qemu_riscv64.yaml rename to boards/qemu/riscv64/qemu_riscv64.yaml diff --git a/boards/qemu/riscv64/qemu_riscv64_defconfig b/boards/qemu/riscv64/qemu_riscv64_defconfig new file mode 100644 index 00000000000000..18dbae0da77551 --- /dev/null +++ b/boards/qemu/riscv64/qemu_riscv64_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_PRIVILEGED_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_STACK_SENTINEL=y +CONFIG_XIP=n +CONFIG_RISCV_PMP=y diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml new file mode 100644 index 00000000000000..3b39ef7499d0d1 --- /dev/null +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml @@ -0,0 +1,15 @@ +identifier: qemu_riscv64/qemu_virt_riscv64/smp +name: QEMU Emulation for RISC-V 64-bit SMP +type: qemu +simulation: qemu +arch: riscv +toolchain: + - zephyr +supported: + - netif + - smp +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig new file mode 100644 index 00000000000000..412b05982f3028 --- /dev/null +++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_IDLE_STACK_SIZE=1024 +CONFIG_QEMU_ICOUNT=n diff --git a/boards/qemu/x86/CMakeLists.txt b/boards/qemu/x86/CMakeLists.txt new file mode 100644 index 00000000000000..1f37a49df8cbe8 --- /dev/null +++ b/boards/qemu/x86/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +if(CONFIG_BOARD_QEMU_X86_64 AND CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -i ${ZEPHYR_BASE}/include + -o ${CMAKE_OBJCOPY} + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/qemu/x86/Kconfig b/boards/qemu/x86/Kconfig new file mode 100644 index 00000000000000..092f34f453d5ec --- /dev/null +++ b/boards/qemu/x86/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86 + bool + select CPU_HAS_FPU + +config BOARD_QEMU_X86_64 + bool + select X86_64 + +config BOARD_QEMU_X86_LAKEMONT + bool + select CPU_HAS_FPU + +config BOARD_QEMU_X86_TINY + bool + select CPU_HAS_FPU diff --git a/boards/qemu/x86/Kconfig.defconfig b/boards/qemu/x86/Kconfig.defconfig new file mode 100644 index 00000000000000..5afe94d68e5d56 --- /dev/null +++ b/boards/qemu/x86/Kconfig.defconfig @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +if BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY + +# The EEPROM emulator must be initialized after the flash simulator +config EEPROM_INIT_PRIORITY + default 60 + depends on EEPROM + +config BUILD_OUTPUT_BIN + default n + +config QEMU_TARGET + default y + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY + + +if BOARD_QEMU_X86 + +config FLASH_SIMULATOR + default y + depends on FLASH + +config KERNEL_VM_SIZE + default 0x10000000 if ACPI + +config MULTIBOOT + default y + +config MULTIBOOT_INFO + default y if MULTIBOOT + +config MULTIBOOT_MEMMAP + default y if MULTIBOOT + +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + +endif # BOARD_QEMU_X86 + + +if BOARD_QEMU_X86_64 + +config KERNEL_VM_SIZE + default 0x10000000 if ACPI + +endif # BOARD_QEMU_X86_64 + + +if BOARD_QEMU_X86_LAKEMONT + +config KERNEL_VM_SIZE + default 0x400000 + +config MULTIBOOT + # This is needed for QEMU to load the ELF image + default y + +config X86_PC_COMPATIBLE + # QEMU presents a PC-compatible machine + default y + +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + +endif # BOARD_QEMU_X86_LAKEMONT + + +if BOARD_QEMU_X86_TINY + +config KERNEL_VM_SIZE + default 0x400000 + +config MULTIBOOT + # This is needed for QEMU to load the ELF image + default y + +config X86_PC_COMPATIBLE + # QEMU presents a PC-compatible machine + default y + +config QEMU_ICOUNT + default n if HPET_TIMER && SHELL + +config QEMU_ICOUNT_SHIFT + default 5 + +config HAVE_CUSTOM_LINKER_SCRIPT + default y + +config CUSTOM_LINKER_SCRIPT + default "${ZEPHYR_BASE}/boards/qemu/x86/qemu_x86_tiny.ld" + +config X86_EXTRA_PAGE_TABLE_PAGES + # This is needed for gen_mmu.py to map the flash into memory + default 2 if DEMAND_PAGING && !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT + +config DEMAND_PAGING_PAGE_FRAMES_RESERVE + # Need to accommodate the heap for newlib or common malloc in libc-hook.c + default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0) + +endif # BOARD_QEMU_X86_TINY diff --git a/boards/qemu/x86/Kconfig.qemu_x86 b/boards/qemu/x86/Kconfig.qemu_x86 new file mode 100644 index 00000000000000..126afd6fd68da5 --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86 + select SOC_ATOM diff --git a/boards/qemu/x86/Kconfig.qemu_x86_64 b/boards/qemu/x86/Kconfig.qemu_x86_64 new file mode 100644 index 00000000000000..2ee42f2b2113d0 --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86_64 @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86_64 + select SOC_ATOM diff --git a/boards/qemu/x86/Kconfig.qemu_x86_lakemont b/boards/qemu/x86/Kconfig.qemu_x86_lakemont new file mode 100644 index 00000000000000..f48e1b99c2aff1 --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86_lakemont @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86_LAKEMONT + select SOC_LAKEMONT diff --git a/boards/qemu/x86/Kconfig.qemu_x86_tiny b/boards/qemu/x86/Kconfig.qemu_x86_tiny new file mode 100644 index 00000000000000..c6468168f9e11d --- /dev/null +++ b/boards/qemu/x86/Kconfig.qemu_x86_tiny @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_X86_TINY + select SOC_ATOM diff --git a/boards/qemu/x86/board.cmake b/boards/qemu/x86/board.cmake new file mode 100644 index 00000000000000..2738f43bddefab --- /dev/null +++ b/boards/qemu/x86/board.cmake @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +set(SUPPORTED_EMU_PLATFORMS qemu) + +if(NOT CONFIG_REBOOT) + set(REBOOT_FLAG -no-reboot) +endif() + +if(CONFIG_X86_64) + set(QEMU_binary_suffix x86_64) + set(QEMU_CPU_TYPE_${ARCH} qemu64,+x2apic) + if("${CONFIG_MP_MAX_NUM_CPUS}" STREQUAL "1") + # icount works with 1 CPU so we can enable it here. + # FIXME: once this works across configs, remove this line and set + # CONFIG_QEMU_ICOUNT_SHIFT in defconfig instead. + list(APPEND QEMU_EXTRA_FLAGS -icount shift=5,align=off,sleep=off -rtc clock=vm) + endif() +else() + set(QEMU_CPU_TYPE_${ARCH} qemu32,+nx,+pae) +endif() + +if(CONFIG_XIP) + # Extra 4MB to emulate flash area + math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024 + 4") +elseif(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING + AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + # Flash is at 4MB-8MB, so need this to be large enough + math(EXPR QEMU_MEMORY_SIZE_MB "8") +else() + math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024") +endif() + +set(QEMU_CPU_FLAGS "") +if(CONFIG_X86_MMX) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmx") + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmxext") +endif() +if(CONFIG_X86_SSE) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse") +endif() +if(CONFIG_X86_SSE2) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse2") +endif() +if(CONFIG_X86_SSE3) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "pni") +endif() +if(CONFIG_X86_SSSE3) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "ssse3") +endif() +if(CONFIG_X86_SSE41) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.1") +endif() +if(CONFIG_X86_SSE42) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.2") +endif() +if(CONFIG_X86_SSE4A) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4a") +endif() +if(NOT CONFIG_X86_64 AND CONFIG_CACHE_MANAGEMENT) + string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "clflush") +endif() + +set(QEMU_FLAGS_${ARCH} + -m ${QEMU_MEMORY_SIZE_MB} + -cpu ${QEMU_CPU_TYPE_${ARCH}}${QEMU_CPU_FLAGS} + -machine q35 + -device isa-debug-exit,iobase=0xf4,iosize=0x04 + ${REBOOT_FLAG} + -nographic + ) + +if(NOT CONFIG_ACPI) + list(APPEND QEMU_FLAGS_${ARCH} -no-acpi) +endif() + +# TODO: Support debug +# board_set_debugger_ifnset(qemu) +# debugserver: QEMU_EXTRA_FLAGS += -s -S +# debugserver: qemu + +if(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING + AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) + # This is to map the flash so it is accessible. + math(EXPR QEMU_FLASH_SIZE_KB "${CONFIG_FLASH_SIZE} * 1024") + set(X86_EXTRA_GEN_MMU_ARGUMENTS + --map ${CONFIG_FLASH_BASE_ADDRESS},${QEMU_FLASH_SIZE_KB},W) +endif() diff --git a/boards/qemu/x86/board.yml b/boards/qemu/x86/board.yml new file mode 100644 index 00000000000000..75d0cd6eb4b5bd --- /dev/null +++ b/boards/qemu/x86/board.yml @@ -0,0 +1,25 @@ +boards: + + - name: qemu_x86 + socs: + - name: atom + variants: + - name: 'nokpti' + - name: 'nommu' + - name: 'nopae' + - name: 'virt' + - name: 'xip' + + - name: qemu_x86_lakemont + socs: + - name: lakemont + + - name: qemu_x86_64 + socs: + - name: atom + variants: + - name: 'nokpti' + + - name: qemu_x86_tiny + socs: + - name: atom diff --git a/boards/x86/qemu_x86/doc/index.rst b/boards/qemu/x86/doc/index.rst similarity index 100% rename from boards/x86/qemu_x86/doc/index.rst rename to boards/qemu/x86/doc/index.rst diff --git a/boards/x86/qemu_x86/qemu_x86.dts b/boards/qemu/x86/qemu_x86.dts similarity index 97% rename from boards/x86/qemu_x86/qemu_x86.dts rename to boards/qemu/x86/qemu_x86.dts index 6117d7927abc53..85e3f56c36e6db 100644 --- a/boards/x86/qemu_x86/qemu_x86.dts +++ b/boards/qemu/x86/qemu_x86.dts @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2019 Intel Corp. */ /dts-v1/; @@ -12,7 +13,7 @@ #endif #define DT_FLASH_SIZE DT_SIZE_K(4096) -#include +#include #include / { diff --git a/boards/x86/qemu_x86/qemu_x86.yaml b/boards/qemu/x86/qemu_x86.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86.yaml rename to boards/qemu/x86/qemu_x86.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_64.dts b/boards/qemu/x86/qemu_x86_64.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_64.dts rename to boards/qemu/x86/qemu_x86_64.dts diff --git a/boards/x86/qemu_x86/qemu_x86_64.yaml b/boards/qemu/x86/qemu_x86_64.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_64.yaml rename to boards/qemu/x86/qemu_x86_64.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_64_nokpti.dts b/boards/qemu/x86/qemu_x86_64_atom_nokpti.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_64_nokpti.dts rename to boards/qemu/x86/qemu_x86_64_atom_nokpti.dts diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml new file mode 100644 index 00000000000000..22033bdc24d199 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml @@ -0,0 +1,18 @@ +identifier: qemu_x86_64/atom/nokpti +name: QEMU Emulation for X86_64 (KPTI disabled) +type: qemu +arch: x86 +toolchain: + - zephyr + - xtools +supported: + - smp +simulation: qemu +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig new file mode 100644 index 00000000000000..01dd154ba5ace1 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_KPTI=n diff --git a/boards/x86/qemu_x86/qemu_x86_64_defconfig b/boards/qemu/x86/qemu_x86_64_defconfig similarity index 88% rename from boards/x86/qemu_x86/qemu_x86_64_defconfig rename to boards/qemu/x86/qemu_x86_64_defconfig index 9f37e55e13872c..9ca58bfcb7076c 100644 --- a/boards/x86/qemu_x86/qemu_x86_64_defconfig +++ b/boards/qemu/x86/qemu_x86_64_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86_64=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/qemu_x86/qemu_x86_nokpti.dts b/boards/qemu/x86/qemu_x86_atom_nokpti.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_nokpti.dts rename to boards/qemu/x86/qemu_x86_atom_nokpti.dts diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml new file mode 100644 index 00000000000000..54b8d1857d9b65 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml @@ -0,0 +1,16 @@ +identifier: qemu_x86/atom/nokpti +name: QEMU Emulation for X86 (KPTI disabled) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig new file mode 100644 index 00000000000000..01dd154ba5ace1 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nokpti_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_KPTI=n diff --git a/boards/qemu/x86/qemu_x86_atom_nommu.dts b/boards/qemu/x86/qemu_x86_atom_nommu.dts new file mode 100644 index 00000000000000..0713146821deb5 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nommu.dts @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2019 Intel Corp. */ + +#include "qemu_x86.dts" diff --git a/boards/qemu/x86/qemu_x86_atom_nommu.yaml b/boards/qemu/x86/qemu_x86_atom_nommu.yaml new file mode 100644 index 00000000000000..1076c2f3f87c1b --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nommu.yaml @@ -0,0 +1,14 @@ +identifier: qemu_x86/atom/nommu +name: QEMU Emulation for X86 (MMU disabled) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nommu_defconfig b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig new file mode 100644 index 00000000000000..32dbada07b40a4 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nommu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_MMU=n +CONFIG_SCHED_DUMB=y +CONFIG_WAITQ_DUMB=y +CONFIG_X86_VERY_EARLY_CONSOLE=n diff --git a/boards/x86/qemu_x86/qemu_x86_nopae.dts b/boards/qemu/x86/qemu_x86_atom_nopae.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_nopae.dts rename to boards/qemu/x86/qemu_x86_atom_nopae.dts diff --git a/boards/qemu/x86/qemu_x86_atom_nopae.yaml b/boards/qemu/x86/qemu_x86_atom_nopae.yaml new file mode 100644 index 00000000000000..2d3b46acc3f99f --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nopae.yaml @@ -0,0 +1,16 @@ +identifier: qemu_x86/atom/nopae +name: QEMU Emulation for X86 (32-bit page tables) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_nopae_defconfig b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig new file mode 100644 index 00000000000000..36ec7d7d8e52dd --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_nopae_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_PAE=n diff --git a/boards/x86/qemu_x86/qemu_x86_virt.dts b/boards/qemu/x86/qemu_x86_atom_virt.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_virt.dts rename to boards/qemu/x86/qemu_x86_atom_virt.dts diff --git a/boards/qemu/x86/qemu_x86_atom_virt.yaml b/boards/qemu/x86/qemu_x86_atom_virt.yaml new file mode 100644 index 00000000000000..ac656ad922dd76 --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_virt.yaml @@ -0,0 +1,16 @@ +identifier: qemu_x86/atom/virt +name: QEMU Emulation for X86 (Run in Virtual Address Space) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - kernel + - userspace + ignore_tags: + - benchmark +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_virt_defconfig b/boards/qemu/x86/qemu_x86_atom_virt_defconfig new file mode 100644 index 00000000000000..6c1679d772814e --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_virt_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_SRAM_OFFSET=0x100000 +CONFIG_KERNEL_VM_SIZE=0x400000 +CONFIG_KERNEL_VM_BASE=0x40000000 +CONFIG_KERNEL_VM_OFFSET=0 + +CONFIG_LINKER_USE_BOOT_SECTION=y +CONFIG_LINKER_USE_PINNED_SECTION=y diff --git a/boards/x86/qemu_x86/qemu_x86_xip.dts b/boards/qemu/x86/qemu_x86_atom_xip.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_xip.dts rename to boards/qemu/x86/qemu_x86_atom_xip.dts diff --git a/boards/qemu/x86/qemu_x86_atom_xip.yaml b/boards/qemu/x86/qemu_x86_atom_xip.yaml new file mode 100644 index 00000000000000..f55d0b2097ad6b --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_xip.yaml @@ -0,0 +1,13 @@ +identifier: qemu_x86/atom/xip +name: QEMU Emulation for X86 (XIP enabled) +type: qemu +arch: x86 +simulation: qemu +toolchain: + - zephyr + - xtools +testing: + default: true + only_tags: + - xip +vendor: qemu diff --git a/boards/qemu/x86/qemu_x86_atom_xip_defconfig b/boards/qemu/x86/qemu_x86_atom_xip_defconfig new file mode 100644 index 00000000000000..c186d56827589f --- /dev/null +++ b/boards/qemu/x86/qemu_x86_atom_xip_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. + +CONFIG_X86_MMU=n +CONFIG_XIP=y diff --git a/boards/x86/qemu_x86/qemu_x86_defconfig b/boards/qemu/x86/qemu_x86_defconfig similarity index 88% rename from boards/x86/qemu_x86/qemu_x86_defconfig rename to boards/qemu/x86/qemu_x86_defconfig index 75320082a68f3f..754f0a47c83b20 100644 --- a/boards/x86/qemu_x86/qemu_x86_defconfig +++ b/boards/qemu/x86/qemu_x86_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont.dts b/boards/qemu/x86/qemu_x86_lakemont.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_lakemont.dts rename to boards/qemu/x86/qemu_x86_lakemont.dts diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont.yaml b/boards/qemu/x86/qemu_x86_lakemont.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_lakemont.yaml rename to boards/qemu/x86/qemu_x86_lakemont.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig b/boards/qemu/x86/qemu_x86_lakemont_defconfig similarity index 85% rename from boards/x86/qemu_x86/qemu_x86_lakemont_defconfig rename to boards/qemu/x86/qemu_x86_lakemont_defconfig index c4902a34a6c50f..754f0a47c83b20 100644 --- a/boards/x86/qemu_x86/qemu_x86_lakemont_defconfig +++ b/boards/qemu/x86/qemu_x86_lakemont_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_LAKEMONT=y -CONFIG_BOARD_QEMU_X86_LAKEMONT=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/x86/qemu_x86/qemu_x86_tiny.dts b/boards/qemu/x86/qemu_x86_tiny.dts similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_tiny.dts rename to boards/qemu/x86/qemu_x86_tiny.dts diff --git a/boards/x86/qemu_x86/qemu_x86_tiny.ld b/boards/qemu/x86/qemu_x86_tiny.ld similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_tiny.ld rename to boards/qemu/x86/qemu_x86_tiny.ld diff --git a/boards/x86/qemu_x86/qemu_x86_tiny.yaml b/boards/qemu/x86/qemu_x86_tiny.yaml similarity index 100% rename from boards/x86/qemu_x86/qemu_x86_tiny.yaml rename to boards/qemu/x86/qemu_x86_tiny.yaml diff --git a/boards/x86/qemu_x86/qemu_x86_tiny_defconfig b/boards/qemu/x86/qemu_x86_tiny_defconfig similarity index 93% rename from boards/x86/qemu_x86/qemu_x86_tiny_defconfig rename to boards/qemu/x86/qemu_x86_tiny_defconfig index 8b8111746f6005..349e1b6ec711c5 100644 --- a/boards/x86/qemu_x86/qemu_x86_tiny_defconfig +++ b/boards/qemu/x86/qemu_x86_tiny_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 Intel Corp. -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86_TINY=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/qemu/xtensa/Kconfig b/boards/qemu/xtensa/Kconfig new file mode 100644 index 00000000000000..8cdc6ec28ff21e --- /dev/null +++ b/boards/qemu/xtensa/Kconfig @@ -0,0 +1,9 @@ +# XTENSA board configuration + +# Copyright (c) 2017, 2023 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_XTENSA + select QEMU_TARGET + select ARCH_SUPPORTS_COREDUMP + select XTENSA_MMU if BOARD_QEMU_XTENSA_DC233C_MMU diff --git a/boards/qemu/xtensa/Kconfig.defconfig b/boards/qemu/xtensa/Kconfig.defconfig new file mode 100644 index 00000000000000..081971b5e81084 --- /dev/null +++ b/boards/qemu/xtensa/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2017, 2023 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_QEMU_XTENSA + +config BUILD_OUTPUT_BIN + default n + +config IPM_CONSOLE_STACK_SIZE + default 2048 if IPM_CONSOLE_RECEIVER + +endif # BOARD_QEMU_XTENSA diff --git a/boards/qemu/xtensa/Kconfig.qemu_xtensa b/boards/qemu/xtensa/Kconfig.qemu_xtensa new file mode 100644 index 00000000000000..f0aa1c8010c3ba --- /dev/null +++ b/boards/qemu/xtensa/Kconfig.qemu_xtensa @@ -0,0 +1,7 @@ +# XTENSA board configuration + +# Copyright (c) 2017, 2023 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QEMU_XTENSA + select SOC_XTENSA_DC233C diff --git a/boards/qemu/xtensa/board.cmake b/boards/qemu/xtensa/board.cmake new file mode 100644 index 00000000000000..40818845da6d02 --- /dev/null +++ b/boards/qemu/xtensa/board.cmake @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +set(SUPPORTED_EMU_PLATFORMS qemu) + +if(CONFIG_BOARD_QEMU_XTENSA) + set(QEMU_CPU_TYPE_${ARCH} dc233c) + + set(QEMU_FLAGS_${ARCH} + -machine sim -semihosting -nographic -cpu dc233c + ) +endif() + +# TODO: Support debug +# board_set_debugger_ifnset(qemu) +# debugserver: QEMU_EXTRA_FLAGS += -s -S +# debugserver: qemu diff --git a/boards/qemu/xtensa/board.yml b/boards/qemu/xtensa/board.yml new file mode 100644 index 00000000000000..1441dcc25fc6ab --- /dev/null +++ b/boards/qemu/xtensa/board.yml @@ -0,0 +1,7 @@ +board: + name: qemu_xtensa + vendor: cdns + socs: + - name: dc233c + variants: + - name: mmu diff --git a/boards/xtensa/qemu_xtensa/doc/index.rst b/boards/qemu/xtensa/doc/index.rst similarity index 100% rename from boards/xtensa/qemu_xtensa/doc/index.rst rename to boards/qemu/xtensa/doc/index.rst diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa.dts b/boards/qemu/xtensa/qemu_xtensa.dts similarity index 100% rename from boards/xtensa/qemu_xtensa/qemu_xtensa.dts rename to boards/qemu/xtensa/qemu_xtensa.dts diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa.yaml b/boards/qemu/xtensa/qemu_xtensa.yaml similarity index 100% rename from boards/xtensa/qemu_xtensa/qemu_xtensa.yaml rename to boards/qemu/xtensa/qemu_xtensa.yaml diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.dts b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.dts similarity index 100% rename from boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.dts rename to boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.dts diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml new file mode 100644 index 00000000000000..61ab14c9130526 --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml @@ -0,0 +1,13 @@ +identifier: qemu_xtensa/dc233c/mmu +name: QEMU Emulation for Xtensa with MMU +type: qemu +simulation: qemu +arch: xtensa +toolchain: + - zephyr + - xtools +testing: + default: true + ignore_tags: + - net + - bluetooth diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu_defconfig b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu_defconfig new file mode 100644 index 00000000000000..d23b5a9f174f77 --- /dev/null +++ b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 +CONFIG_STACK_SENTINEL=y +CONFIG_GEN_ISR_TABLES=y +CONFIG_GEN_IRQ_VECTOR_TABLE=n +CONFIG_SIMULATOR_XTENSA=y +CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_defconfig b/boards/qemu/xtensa/qemu_xtensa_defconfig similarity index 82% rename from boards/xtensa/qemu_xtensa/qemu_xtensa_defconfig rename to boards/qemu/xtensa/qemu_xtensa_defconfig index ec51bb17a3852d..d23b5a9f174f77 100644 --- a/boards/xtensa/qemu_xtensa/qemu_xtensa_defconfig +++ b/boards/qemu/xtensa/qemu_xtensa_defconfig @@ -1,9 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_BOARD_QEMU_XTENSA=y CONFIG_CONSOLE=y -CONFIG_SOC_XTENSA_DC233C=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 CONFIG_STACK_SENTINEL=y CONFIG_GEN_ISR_TABLES=y diff --git a/boards/arm/decawave_dwm1001_dev/Kconfig b/boards/qorvo/decawave_dwm1001_dev/Kconfig similarity index 100% rename from boards/arm/decawave_dwm1001_dev/Kconfig rename to boards/qorvo/decawave_dwm1001_dev/Kconfig diff --git a/boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev b/boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev new file mode 100644 index 00000000000000..ba9f6965b1d923 --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/Kconfig.decawave_dwm1001_dev @@ -0,0 +1,7 @@ +# DecaWave DWM1001 board configuration + +# Copyright (c) 2019 Stéphane D'Alu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DECAWAVE_DWM1001_DEV + select SOC_NRF52832_QFAA diff --git a/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig b/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig new file mode 100644 index 00000000000000..cd2a985b1ebc8e --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/Kconfig.defconfig @@ -0,0 +1,18 @@ +# DecaWave DWM1001 board configuration + +# Copyright (c) 2019 Stéphane D'Alu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DECAWAVE_DWM1001_DEV + +config BT_CTLR + default BT + +config I2C + default SENSOR + +config SPI + default y + depends on IEEE802154 + +endif # BOARD_DECAWAVE_DWM1001_DEV diff --git a/boards/arm/decawave_dwm1001_dev/board.cmake b/boards/qorvo/decawave_dwm1001_dev/board.cmake similarity index 100% rename from boards/arm/decawave_dwm1001_dev/board.cmake rename to boards/qorvo/decawave_dwm1001_dev/board.cmake diff --git a/boards/qorvo/decawave_dwm1001_dev/board.yml b/boards/qorvo/decawave_dwm1001_dev/board.yml new file mode 100644 index 00000000000000..f1d0ae7def009f --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/board.yml @@ -0,0 +1,5 @@ +board: + name: decawave_dwm1001_dev + vendor: qorvo + socs: + - name: nrf52832 diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi similarity index 100% rename from boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi rename to boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev-pinctrl.dtsi diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.dts b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts similarity index 100% rename from boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.dts rename to boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.dts diff --git a/boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml similarity index 100% rename from boards/arm/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml rename to boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml diff --git a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig new file mode 100644 index 00000000000000..bb14402e1bb965 --- /dev/null +++ b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable RTT +CONFIG_USE_SEGGER_RTT=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_RTT_CONSOLE=y diff --git a/boards/arm/decawave_dwm1001_dev/doc/index.rst b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst similarity index 100% rename from boards/arm/decawave_dwm1001_dev/doc/index.rst rename to boards/qorvo/decawave_dwm1001_dev/doc/index.rst diff --git a/boards/arm/pinetime_devkit0/pre_dt_board.cmake b/boards/qorvo/decawave_dwm1001_dev/pre_dt_board.cmake similarity index 100% rename from boards/arm/pinetime_devkit0/pre_dt_board.cmake rename to boards/qorvo/decawave_dwm1001_dev/pre_dt_board.cmake diff --git a/boards/qorvo/index.rst b/boards/qorvo/index.rst new file mode 100644 index 00000000000000..e7bd9b34aff003 --- /dev/null +++ b/boards/qorvo/index.rst @@ -0,0 +1,10 @@ +.. _boards-qorvo: + +Qorvo, Inc. +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/quicklogic/index.rst b/boards/quicklogic/index.rst new file mode 100644 index 00000000000000..9c28f1050539e5 --- /dev/null +++ b/boards/quicklogic/index.rst @@ -0,0 +1,10 @@ +.. _boards-quicklogic: + +QuickLogic Corp. +################ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/qomu/Kconfig b/boards/quicklogic/qomu/Kconfig similarity index 100% rename from boards/arm/qomu/Kconfig rename to boards/quicklogic/qomu/Kconfig diff --git a/boards/quicklogic/qomu/Kconfig.qomu b/boards/quicklogic/qomu/Kconfig.qomu new file mode 100644 index 00000000000000..285ae1bf122341 --- /dev/null +++ b/boards/quicklogic/qomu/Kconfig.qomu @@ -0,0 +1,7 @@ +# QuickLogic Qomu board + +# Copyright (c) 2022 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QOMU + select SOC_EOS_S3 diff --git a/boards/quicklogic/qomu/board.yml b/boards/quicklogic/qomu/board.yml new file mode 100644 index 00000000000000..e71125610fad84 --- /dev/null +++ b/boards/quicklogic/qomu/board.yml @@ -0,0 +1,5 @@ +board: + name: qomu + vendor: quicklogic + socs: + - name: quicklogic_eos_s3 diff --git a/boards/arm/qomu/doc/img/qomu-board.png b/boards/quicklogic/qomu/doc/img/qomu-board.png similarity index 100% rename from boards/arm/qomu/doc/img/qomu-board.png rename to boards/quicklogic/qomu/doc/img/qomu-board.png diff --git a/boards/arm/qomu/doc/index.rst b/boards/quicklogic/qomu/doc/index.rst similarity index 100% rename from boards/arm/qomu/doc/index.rst rename to boards/quicklogic/qomu/doc/index.rst diff --git a/boards/arm/qomu/qomu.dts b/boards/quicklogic/qomu/qomu.dts similarity index 100% rename from boards/arm/qomu/qomu.dts rename to boards/quicklogic/qomu/qomu.dts diff --git a/boards/arm/qomu/qomu.yaml b/boards/quicklogic/qomu/qomu.yaml similarity index 100% rename from boards/arm/qomu/qomu.yaml rename to boards/quicklogic/qomu/qomu.yaml diff --git a/boards/arm/qomu/qomu_defconfig b/boards/quicklogic/qomu/qomu_defconfig similarity index 88% rename from boards/arm/qomu/qomu_defconfig rename to boards/quicklogic/qomu/qomu_defconfig index 4f1698412896fa..c1d806d7b57754 100644 --- a/boards/arm/qomu/qomu_defconfig +++ b/boards/quicklogic/qomu/qomu_defconfig @@ -2,14 +2,12 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=n -CONFIG_SOC_EOS_S3=y -CONFIG_BOARD_QOMU=y -# system clock +# System clock CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=61440000 CONFIG_CORTEX_M_SYSTICK=y -# console +# Console CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/quick_feather/Kconfig b/boards/quicklogic/quick_feather/Kconfig similarity index 100% rename from boards/arm/quick_feather/Kconfig rename to boards/quicklogic/quick_feather/Kconfig diff --git a/boards/quicklogic/quick_feather/Kconfig.quick_feather b/boards/quicklogic/quick_feather/Kconfig.quick_feather new file mode 100644 index 00000000000000..244356b5c3697a --- /dev/null +++ b/boards/quicklogic/quick_feather/Kconfig.quick_feather @@ -0,0 +1,7 @@ +# Quick Feather board + +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_QUICK_FEATHER + select SOC_EOS_S3 diff --git a/boards/quicklogic/quick_feather/board.yml b/boards/quicklogic/quick_feather/board.yml new file mode 100644 index 00000000000000..3ca618cbe34e2b --- /dev/null +++ b/boards/quicklogic/quick_feather/board.yml @@ -0,0 +1,5 @@ +board: + name: quick_feather + vendor: quicklogic + socs: + - name: quicklogic_eos_s3 diff --git a/boards/arm/quick_feather/doc/img/feather-board.jpg b/boards/quicklogic/quick_feather/doc/img/feather-board.jpg similarity index 100% rename from boards/arm/quick_feather/doc/img/feather-board.jpg rename to boards/quicklogic/quick_feather/doc/img/feather-board.jpg diff --git a/boards/quicklogic/quick_feather/doc/index.rst b/boards/quicklogic/quick_feather/doc/index.rst new file mode 100644 index 00000000000000..d5bf1e7026de37 --- /dev/null +++ b/boards/quicklogic/quick_feather/doc/index.rst @@ -0,0 +1,125 @@ +.. _quickfeather: + +QuickFeather +############ + +Overview +******** + +The QuickFeather development board is a platform with an on-board QuickLogic +EOS S3 Sensor Processing Platform. + + +.. figure:: img/feather-board.jpg + :align: center + :alt: QuickFeather + + QuickFeather (Credit: QuickLogic) + +Hardware +******** + +- QuickLogic EOS S3 MCU Platform +- mCube MC3635 accelerometer +- Infineon DPS310 pressure sensor +- Infineon IM69D130 MEMS microphone +- 16 Mbit of on-board flash memory +- User button +- RGB LED +- Integrated battery charger + +Detailed information about the board can be found in a `QuickFeather repository`_. + +Supported Features +================== + +The QuickFeather configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/quicklogic/quick_feather/quick_feather_defconfig`. + +Connections and IOs +=================== + +Detailed information about pinouts is available in the `schematics document`_. + +Programming and Debugging +************************* + +Flashing +======== + +The QuickFeather platform by default boots from flash. Currently +the Zephyr port only enables loading the program directly to SRAM using either +OpenOCD and a SWD programmer or SEGGER JLink. + +OpenOCD +------- + +In order to connect to the target a SWD programmer supported in +OpenOCD is needed. To connect to the board run: + +.. code-block:: console + + openocd -f /path/to/swd-programmer.cfg -f tcl/board/quicklogic_quickfeather.cfg -c "init" -c "reset halt" + +`The QuickFeather OpenOCD config`_ can be found in the OpenOCD mainline repository. + +JLink +----- + +To connect to the QuickFeather board with JLink please follow instructions +in the `QuickFeather User Guide`_. + +Debugging +========= + +To debug the QuickFeather board please connect to the target with either +OpenOCD or JLink and use GDB distributed in Zephyr's SDK in *arm-zephyr-eabi/bin* +directory. + +To load basic sample via GDB: + +- Build the sample in an usual way: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: quick_feather + :goals: build + +- Connect to the target using either OpenOCD or JLink +- Connect via GDB and load an ELF file: + +.. code-block:: console + + /path/to/zephyr-sdk/arm-zephyr-eabi/bin/arm-zephyr-eabi-gdb + target remote + file + load + continue + +References +********** + +.. target-notes:: + +.. _QuickFeather repository: + https://github.com/QuickLogic-Corp/quick-feather-dev-board + +.. _schematics document: + https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/quickfeather-board.pdf + +.. _The QuickFeather OpenOCD config: + https://sourceforge.net/p/openocd/code/ci/master/tree/tcl/board/quicklogic_quickfeather.cfg + +.. _QuickFeather User Guide: + https://github.com/QuickLogic-Corp/quick-feather-dev-board/blob/master/doc/QuickFeather_UserGuide.pdf diff --git a/boards/arm/quick_feather/quick_feather.dts b/boards/quicklogic/quick_feather/quick_feather.dts similarity index 100% rename from boards/arm/quick_feather/quick_feather.dts rename to boards/quicklogic/quick_feather/quick_feather.dts diff --git a/boards/arm/quick_feather/quick_feather.yaml b/boards/quicklogic/quick_feather/quick_feather.yaml similarity index 100% rename from boards/arm/quick_feather/quick_feather.yaml rename to boards/quicklogic/quick_feather/quick_feather.yaml diff --git a/boards/arm/quick_feather/quick_feather_defconfig b/boards/quicklogic/quick_feather/quick_feather_defconfig similarity index 86% rename from boards/arm/quick_feather/quick_feather_defconfig rename to boards/quicklogic/quick_feather/quick_feather_defconfig index 6f88908e44c52a..137acf1e62a0e1 100644 --- a/boards/arm/quick_feather/quick_feather_defconfig +++ b/boards/quicklogic/quick_feather/quick_feather_defconfig @@ -2,13 +2,11 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=n -CONFIG_SOC_EOS_S3=y -CONFIG_BOARD_QUICK_FEATHER=y -# system clock +# System clock CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=61440000 -# console +# Console CONFIG_SERIAL=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/rak/index.rst b/boards/rak/index.rst new file mode 100644 index 00000000000000..334d985e609270 --- /dev/null +++ b/boards/rak/index.rst @@ -0,0 +1,10 @@ +.. _boards-rak: + +RAKwireless +########### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/rak/rak4631/Kconfig.defconfig b/boards/rak/rak4631/Kconfig.defconfig new file mode 100644 index 00000000000000..bf7cf003b2932b --- /dev/null +++ b/boards/rak/rak4631/Kconfig.defconfig @@ -0,0 +1,11 @@ +# RAKWIRELESS RAK4631 Board configuration + +# Copyright (c) 2021 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAK4631 + +config BT_CTLR + default BT + +endif # BOARD_RAK4631 diff --git a/boards/rak/rak4631/Kconfig.rak4631 b/boards/rak/rak4631/Kconfig.rak4631 new file mode 100644 index 00000000000000..4ba2754e42fc8c --- /dev/null +++ b/boards/rak/rak4631/Kconfig.rak4631 @@ -0,0 +1,7 @@ +# RAKWIRELESS RAK4631 selection + +# Copyright (c) 2021 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAK4631 + select SOC_NRF52840_QIAA diff --git a/boards/arm/rak4631_nrf52840/board.cmake b/boards/rak/rak4631/board.cmake similarity index 100% rename from boards/arm/rak4631_nrf52840/board.cmake rename to boards/rak/rak4631/board.cmake diff --git a/boards/rak/rak4631/board.yml b/boards/rak/rak4631/board.yml new file mode 100644 index 00000000000000..a3b886728233ef --- /dev/null +++ b/boards/rak/rak4631/board.yml @@ -0,0 +1,5 @@ +board: + name: rak4631 + vendor: rakwireless + socs: + - name: nrf52840 diff --git a/boards/arm/rak4631_nrf52840/doc/img/rak4631-front-parts.jpg b/boards/rak/rak4631/doc/img/rak4631-front-parts.jpg similarity index 100% rename from boards/arm/rak4631_nrf52840/doc/img/rak4631-front-parts.jpg rename to boards/rak/rak4631/doc/img/rak4631-front-parts.jpg diff --git a/boards/rak/rak4631/doc/index.rst b/boards/rak/rak4631/doc/index.rst new file mode 100644 index 00000000000000..ffa39ca8265911 --- /dev/null +++ b/boards/rak/rak4631/doc/index.rst @@ -0,0 +1,154 @@ +.. _rak4631_nrf52840: + +RAK4631 +####### + +Overview +******** + +RAK4631 is a WisBlock Core module for RAK WisBlock. +It extends the WisBlock series with a powerful +Nordic nRF52840 MCU that supports Bluetooth 5.0 +(Bluetooth Low Energy) and the newest LoRa transceiver +from Semtech, the SX1262. The Semtech SX1262 has compared +to the older SX127x series a lower power consumption at +the same TX power. This makes the RAK4631 an ultra-low +power communication solution. RAK4631 can be comfortably +programmed with ZephyrRTOS. + +.. image:: img/rak4631-front-parts.jpg + :align: center + :alt: RAK4631-NRF52840 + +Hardware +******** + +To use a RAK4631, you need at least a WisBlock Base +to plug the module in. WisBlock Base is the power +supply for the RAK4631 module and has the +programming/debug interface. + +- nRF52840 ARM Cortex-M4F Processor +- 64 MHz CPU clock +- 1 Micro-AB USB OTG host/device +- Semtech SX1262 low power high range LoRa transceiver +- iPEX connectors for the LORA antenna and BLE antenna. +- Multiple interfaces, I2C, UART, GPIO, ADC +- 2 user LEDs on RAK5005 mother Board +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +Supported Features +================== + +The ``rak4631/nrf52840`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RADIO | on-board | LoRa (SX1262) | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The default board configuration can be found in +:zephyr_file:`boards/rak/rak4631/rak4631_nrf52840_defconfig` + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P1.3 +* LED2 (blue) = P1.4 + +Programming and Debugging +************************* + +The RAK4631 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the NRF52840 chip. You can use JLink to communicate with +the NRF52840. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the RAK4631 board to your host computer using the USB debug port. + Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak4631/nrf52840 + :goals: build flash + + You should see "Hello World! rak4631_nrf52840" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak4631/nrf52840 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _RAK4631 Product Description: + https://docs.rakwireless.com/Product-Categories/WisBlock/RAK4631/Datasheet/#overview + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/pinnacle_100_dvk/pre_dt_board.cmake b/boards/rak/rak4631/pre_dt_board.cmake similarity index 100% rename from boards/arm/pinnacle_100_dvk/pre_dt_board.cmake rename to boards/rak/rak4631/pre_dt_board.cmake diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840-pinctrl.dtsi b/boards/rak/rak4631/rak4631_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840-pinctrl.dtsi rename to boards/rak/rak4631/rak4631_nrf52840-pinctrl.dtsi diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts b/boards/rak/rak4631/rak4631_nrf52840.dts similarity index 100% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840.dts rename to boards/rak/rak4631/rak4631_nrf52840.dts diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.yaml b/boards/rak/rak4631/rak4631_nrf52840.yaml similarity index 89% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840.yaml rename to boards/rak/rak4631/rak4631_nrf52840.yaml index fb56f5275f6c62..42c638ac35c714 100644 --- a/boards/arm/rak4631_nrf52840/rak4631_nrf52840.yaml +++ b/boards/rak/rak4631/rak4631_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: rak4631_nrf52840 +identifier: rak4631/nrf52840 name: RAK4631-NRF52840 type: mcu arch: arm diff --git a/boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig b/boards/rak/rak4631/rak4631_nrf52840_defconfig similarity index 77% rename from boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig rename to boards/rak/rak4631/rak4631_nrf52840_defconfig index bfdc1718875cd6..8daa29dc47326f 100644 --- a/boards/arm/rak4631_nrf52840/rak4631_nrf52840_defconfig +++ b/boards/rak/rak4631/rak4631_nrf52840_defconfig @@ -1,7 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_RAK4631_NRF52840=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/rak/rak5010/Kconfig.defconfig b/boards/rak/rak5010/Kconfig.defconfig new file mode 100644 index 00000000000000..302f7fecd07ed6 --- /dev/null +++ b/boards/rak/rak5010/Kconfig.defconfig @@ -0,0 +1,11 @@ +# RAKWIRELESS RAK5010 Board configuration + +# Copyright (c) 2020 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAK5010 + +config BT_CTLR + default BT + +endif # BOARD_RAK5010 diff --git a/boards/rak/rak5010/Kconfig.rak5010 b/boards/rak/rak5010/Kconfig.rak5010 new file mode 100644 index 00000000000000..ced2b62b39c411 --- /dev/null +++ b/boards/rak/rak5010/Kconfig.rak5010 @@ -0,0 +1,7 @@ +# RAKWIRELESS RAK5010 selection + +# Copyright (c) 2020 Guillaume Paquet +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAK5010_NRF52840 + select SOC_NRF52840_QIAA diff --git a/boards/arm/rak5010_nrf52840/board.cmake b/boards/rak/rak5010/board.cmake similarity index 100% rename from boards/arm/rak5010_nrf52840/board.cmake rename to boards/rak/rak5010/board.cmake diff --git a/boards/rak/rak5010/board.yml b/boards/rak/rak5010/board.yml new file mode 100644 index 00000000000000..c681ac27cb7f09 --- /dev/null +++ b/boards/rak/rak5010/board.yml @@ -0,0 +1,5 @@ +board: + name: rak5010 + vendor: rakwireless + socs: + - name: nrf52840 diff --git a/boards/arm/rak5010_nrf52840/doc/img/rak5010-front-parts.jpg b/boards/rak/rak5010/doc/img/rak5010-front-parts.jpg similarity index 100% rename from boards/arm/rak5010_nrf52840/doc/img/rak5010-front-parts.jpg rename to boards/rak/rak5010/doc/img/rak5010-front-parts.jpg diff --git a/boards/rak/rak5010/doc/index.rst b/boards/rak/rak5010/doc/index.rst new file mode 100644 index 00000000000000..fac00cf72dfa02 --- /dev/null +++ b/boards/rak/rak5010/doc/index.rst @@ -0,0 +1,159 @@ +.. _rak5010_nrf52840: + +RAK5010 +####### + +Overview +******** + +WisTrio NB-IoT Tracker Pro (RAK5010) is a tracker +with integrated LTE CAT M1 & NB1, GPS, BLE, and sensors. +It is built on the Quectel BG96 LTE CAT M1 & NB1 module, +which has an integrated GPS receiver. The MCU running +the board is a Nordic nRF52840 controller. + +As it has both GPS and BLE it can be used for outdoor +and indoor scenarios, where location-based services need be present. + +The built-in sensors for RAK5010 are temperature and +humidity sensor, motion sensor, pressure sensor, and light sensor. +The extension IOs allow adding more sensors in addition to the on-board ones. + +This board is particularly suitable to be used as a +quick testing and prototyping tool for applications +requiring NB-IoT connectivity. Application development +supports the GCC environment. + +.. image:: img/rak5010-front-parts.jpg + :align: center + :alt: RAK5010-NRF52840 + +Hardware +******** + +- nRF52840 ARM Cortex-M4F Processor +- 32.768 kHz crystal oscillator +- 1 Micro-AB USB OTG host/device +- Quectel BG96, with LTE CAT M1, LTE NB1, and GNSS +- iPEX connectors for the LTE and GPS antenna and an on-board ceramic antenna for the BLE. +- nano-SIM and ESIM options. +- Multiple interfaces, I2C, UART, GPIO, ADC +- 1 user LED +- 1 SHTC3 Humidity and Temperature Sensor +- 1 OPT3001DNPR Ambient Light Sensor +- 1 LPS22HB Pressure Sensor +- 1 LIS3DH Motion Sensor +- Powered by either Micro USB, 3.7V rechargeable battery or a 5V Solar Panel Port + +Supported Features +================== + +The ``rak5010/nrf52840`` board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +LED +--- + +* LED0 (green) = P0.12 + + +Programming and Debugging +************************* + +The RAK5010 board shall be connected to a Segger Embedded Debugger Unit +`J-Link OB `_. This provides a debug +interface to the NRF52840 chip. You can use JLink to communicate with +the NRF52840. + +Flashing +======== + +#. Download JLink from the Segger `JLink Downloads Page`_. Go to the section + "J-Link Software and Documentation Pack" and install the "J-Link Software + and Documentation pack for Linux". The application JLinkExe needs to be + accessible from your path. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyACM0 -o + + The -o option tells minicom not to send the modem initialization string. + Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the RAK5010 board to your host computer using the USB debug port. + Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak5010/nrf52840 + :goals: build flash + + You should see "Hello World! rak5010_nrf52840" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rak5010/nrf52840 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _RAK5010 Product Description: + https://doc.rakwireless.com/datasheet/rakproducts/rak5010-wistrio-nb-iot-tracker-datasheet + +.. _JLink Downloads Page: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/rak4631_nrf52840/pre_dt_board.cmake b/boards/rak/rak5010/pre_dt_board.cmake similarity index 100% rename from boards/arm/rak4631_nrf52840/pre_dt_board.cmake rename to boards/rak/rak5010/pre_dt_board.cmake diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840-pinctrl.dtsi b/boards/rak/rak5010/rak5010_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840-pinctrl.dtsi rename to boards/rak/rak5010/rak5010_nrf52840-pinctrl.dtsi diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts b/boards/rak/rak5010/rak5010_nrf52840.dts similarity index 100% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840.dts rename to boards/rak/rak5010/rak5010_nrf52840.dts diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.yaml b/boards/rak/rak5010/rak5010_nrf52840.yaml similarity index 88% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840.yaml rename to boards/rak/rak5010/rak5010_nrf52840.yaml index 1238add9d373df..21b8e122970418 100644 --- a/boards/arm/rak5010_nrf52840/rak5010_nrf52840.yaml +++ b/boards/rak/rak5010/rak5010_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: rak5010_nrf52840 +identifier: rak5010/nrf52840 name: RAK5010-NRF52840 type: mcu arch: arm diff --git a/boards/arm/rak5010_nrf52840/rak5010_nrf52840_defconfig b/boards/rak/rak5010/rak5010_nrf52840_defconfig similarity index 77% rename from boards/arm/rak5010_nrf52840/rak5010_nrf52840_defconfig rename to boards/rak/rak5010/rak5010_nrf52840_defconfig index b7e873c3f03656..8daa29dc47326f 100644 --- a/boards/arm/rak5010_nrf52840/rak5010_nrf52840_defconfig +++ b/boards/rak/rak5010/rak5010_nrf52840_defconfig @@ -1,7 +1,4 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_RAK5010_NRF52840=y # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/raspberrypi/index.rst b/boards/raspberrypi/index.rst new file mode 100644 index 00000000000000..5128a34a3b5e80 --- /dev/null +++ b/boards/raspberrypi/index.rst @@ -0,0 +1,10 @@ +.. _boards-raspberrypi: + +Raspberry Pi Foundation +####################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm64/mimx93_evk/board.cmake b/boards/raspberrypi/rpi_4b/CMakeLists.txt similarity index 100% rename from boards/arm64/mimx93_evk/board.cmake rename to boards/raspberrypi/rpi_4b/CMakeLists.txt diff --git a/boards/raspberrypi/rpi_4b/Kconfig.defconfig b/boards/raspberrypi/rpi_4b/Kconfig.defconfig new file mode 100644 index 00000000000000..70e623172483bb --- /dev/null +++ b/boards/raspberrypi/rpi_4b/Kconfig.defconfig @@ -0,0 +1,2 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/raspberrypi/rpi_4b/Kconfig.rpi_4b b/boards/raspberrypi/rpi_4b/Kconfig.rpi_4b new file mode 100644 index 00000000000000..ca717ac191e2b5 --- /dev/null +++ b/boards/raspberrypi/rpi_4b/Kconfig.rpi_4b @@ -0,0 +1,5 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_4B + select SOC_BCM2711 diff --git a/boards/arm64/nxp_ls1046ardb/board.cmake b/boards/raspberrypi/rpi_4b/board.cmake similarity index 100% rename from boards/arm64/nxp_ls1046ardb/board.cmake rename to boards/raspberrypi/rpi_4b/board.cmake diff --git a/boards/raspberrypi/rpi_4b/board.yml b/boards/raspberrypi/rpi_4b/board.yml new file mode 100644 index 00000000000000..a84904f9b29aa1 --- /dev/null +++ b/boards/raspberrypi/rpi_4b/board.yml @@ -0,0 +1,5 @@ +board: + name: rpi_4b + vendor: raspberrypi + socs: + - name: bcm2711 diff --git a/boards/raspberrypi/rpi_4b/doc/index.rst b/boards/raspberrypi/rpi_4b/doc/index.rst new file mode 100644 index 00000000000000..e31845fdea939e --- /dev/null +++ b/boards/raspberrypi/rpi_4b/doc/index.rst @@ -0,0 +1,70 @@ +.. rpi_4b: + +Raspberry Pi 4 Model B (Cortex-A72) +################################### + +Overview +******** +see + +Hardware +******** +see + +Supported Features +================== +The Raspberry Pi 4 Model B board configuration supports the following +hardware features: + +.. list-table:: + :header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - GIC-400 + - N/A + - :dtcompatible:`arm,gic-v2` + * - GPIO + - :kconfig:option:`CONFIG_GPIO` + - :dtcompatible:`brcm,bcm2711-gpio` + * - UART (Mini UART) + - :kconfig:option:`CONFIG_SERIAL` + - :dtcompatible:`brcm,bcm2711-aux-uart` + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/raspberry_pi/rpi_4b/rpi_4b_defconfig` + +Programming and Debugging +************************* + +TF Card +======= + +Prepare a TF card with MBR and FAT32. In the root directory of the TF card: + +1. Download and place these firmware files: + + * `bcm2711-rpi-4-b.dtb `_ + * `bootcode.bin `_ + * `start4.elf `_ + +2. Copy ``build/zephyr/zephyr.bin`` +3. Create a ``config.txt``: + + .. code-block:: text + + kernel=zephyr.bin + arm_64bit=1 + enable_uart=1 + uart_2ndstage=1 + +Insert the card and power on the board. You should see the following output on +the serial console (GPIO 14/15): + +.. code-block:: text + + *** Booting Zephyr OS build XXXXXXXXXXXX *** + Hello World! Raspberry Pi 4 Model B! diff --git a/boards/arm64/rpi_4b/rpi_4b.dts b/boards/raspberrypi/rpi_4b/rpi_4b.dts similarity index 100% rename from boards/arm64/rpi_4b/rpi_4b.dts rename to boards/raspberrypi/rpi_4b/rpi_4b.dts diff --git a/boards/arm64/rpi_4b/rpi_4b.yaml b/boards/raspberrypi/rpi_4b/rpi_4b.yaml similarity index 100% rename from boards/arm64/rpi_4b/rpi_4b.yaml rename to boards/raspberrypi/rpi_4b/rpi_4b.yaml diff --git a/boards/arm64/rpi_4b/rpi_4b_defconfig b/boards/raspberrypi/rpi_4b/rpi_4b_defconfig similarity index 90% rename from boards/arm64/rpi_4b/rpi_4b_defconfig rename to boards/raspberrypi/rpi_4b/rpi_4b_defconfig index fb79c77a1f66b0..124ef834088991 100644 --- a/boards/arm64/rpi_4b/rpi_4b_defconfig +++ b/boards/raspberrypi/rpi_4b/rpi_4b_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # Platform Configuration -CONFIG_SOC_BCM2711=y -CONFIG_BOARD_RPI_4B=y CONFIG_ARM64_VA_BITS_36=y CONFIG_ARM64_PA_BITS_36=y diff --git a/boards/raspberrypi/rpi_pico/Kconfig.defconfig b/boards/raspberrypi/rpi_pico/Kconfig.defconfig new file mode 100644 index 00000000000000..1b4c3175a5187d --- /dev/null +++ b/boards/raspberrypi/rpi_pico/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RPI_PICO + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_RPI_PICO diff --git a/boards/raspberrypi/rpi_pico/Kconfig.rpi_pico b/boards/raspberrypi/rpi_pico/Kconfig.rpi_pico new file mode 100644 index 00000000000000..cde6b9c8d27493 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/Kconfig.rpi_pico @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RPI_PICO + select SOC_RP2040 diff --git a/boards/arm/rpi_pico/board.cmake b/boards/raspberrypi/rpi_pico/board.cmake similarity index 100% rename from boards/arm/rpi_pico/board.cmake rename to boards/raspberrypi/rpi_pico/board.cmake diff --git a/boards/raspberrypi/rpi_pico/board.yml b/boards/raspberrypi/rpi_pico/board.yml new file mode 100644 index 00000000000000..e4f8e5bc8d55d6 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/board.yml @@ -0,0 +1,7 @@ +board: + name: rpi_pico + vendor: raspberrypi + socs: + - name: rp2040 + variants: + - name: w diff --git a/boards/arm/rpi_pico/doc/img/rpi_pico.jpg b/boards/raspberrypi/rpi_pico/doc/img/rpi_pico.jpg similarity index 100% rename from boards/arm/rpi_pico/doc/img/rpi_pico.jpg rename to boards/raspberrypi/rpi_pico/doc/img/rpi_pico.jpg diff --git a/boards/arm/rpi_pico/doc/img/rpi_pico_w.jpg b/boards/raspberrypi/rpi_pico/doc/img/rpi_pico_w.jpg similarity index 100% rename from boards/arm/rpi_pico/doc/img/rpi_pico_w.jpg rename to boards/raspberrypi/rpi_pico/doc/img/rpi_pico_w.jpg diff --git a/boards/arm/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst similarity index 100% rename from boards/arm/rpi_pico/doc/index.rst rename to boards/raspberrypi/rpi_pico/doc/index.rst diff --git a/boards/arm/rpi_pico/rpi_pico-common.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi similarity index 100% rename from boards/arm/rpi_pico/rpi_pico-common.dtsi rename to boards/raspberrypi/rpi_pico/rpi_pico-common.dtsi diff --git a/boards/arm/rpi_pico/rpi_pico-pinctrl.dtsi b/boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi similarity index 100% rename from boards/arm/rpi_pico/rpi_pico-pinctrl.dtsi rename to boards/raspberrypi/rpi_pico/rpi_pico-pinctrl.dtsi diff --git a/boards/arm/rpi_pico/rpi_pico.dts b/boards/raspberrypi/rpi_pico/rpi_pico.dts similarity index 75% rename from boards/arm/rpi_pico/rpi_pico.dts rename to boards/raspberrypi/rpi_pico/rpi_pico.dts index 97d721024d7497..f92c55c6825e38 100644 --- a/boards/arm/rpi_pico/rpi_pico.dts +++ b/boards/raspberrypi/rpi_pico/rpi_pico.dts @@ -8,6 +8,10 @@ #include "rpi_pico-common.dtsi" +/* Only the rpi_pico/rp2040 has a pwm. */ +/* This define can be used to avoid sourcing board overlays when the PWM is not available */ +#define HAS_DT_PWM_LED 1 + / { leds { compatible = "gpio-leds"; diff --git a/boards/arm/rpi_pico/rpi_pico.yaml b/boards/raspberrypi/rpi_pico/rpi_pico.yaml similarity index 100% rename from boards/arm/rpi_pico/rpi_pico.yaml rename to boards/raspberrypi/rpi_pico/rpi_pico.yaml diff --git a/boards/arm/rpi_pico/rpi_pico_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_defconfig similarity index 78% rename from boards/arm/rpi_pico/rpi_pico_defconfig rename to boards/raspberrypi/rpi_pico/rpi_pico_defconfig index 111edceb147e00..df003531af9c87 100644 --- a/boards/arm/rpi_pico/rpi_pico_defconfig +++ b/boards/raspberrypi/rpi_pico/rpi_pico_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_RPI_PICO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/boards/arm/rpi_pico/rpi_pico_w.dts b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts similarity index 100% rename from boards/arm/rpi_pico/rpi_pico_w.dts rename to boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.dts diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml new file mode 100644 index 00000000000000..581645830a778a --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml @@ -0,0 +1,24 @@ +identifier: rpi_pico/rp2040/w +name: RaspberryPi-Pico-w +type: mcu +arch: arm +flash: 2048 +ram: 264 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart + - gpio + - adc + - i2c + - spi + - hwinfo + - watchdog + - pwm + - flash + - dma + - pio + - counter + - clock diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig new file mode 100644 index 00000000000000..df003531af9c87 --- /dev/null +++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w_defconfig @@ -0,0 +1,11 @@ +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y +CONFIG_USE_DT_CODE_PARTITION=y +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_RESET=y +CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/rpi_pico/support/openocd.cfg b/boards/raspberrypi/rpi_pico/support/openocd.cfg similarity index 100% rename from boards/arm/rpi_pico/support/openocd.cfg rename to boards/raspberrypi/rpi_pico/support/openocd.cfg diff --git a/boards/raytac/index.rst b/boards/raytac/index.rst new file mode 100644 index 00000000000000..a3471445b5f793 --- /dev/null +++ b/boards/raytac/index.rst @@ -0,0 +1,10 @@ +.. _boards-raytac: + +Raytac Corporation +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/raytac/mdbt50q_db_33/Kconfig b/boards/raytac/mdbt50q_db_33/Kconfig new file mode 100644 index 00000000000000..33290b29c1f1b9 --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/Kconfig @@ -0,0 +1,10 @@ +# Raytac MDBT50Q-DB-33 nRF52833 board configuration + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_RAYTAC_MDBT50Q_DB_33 diff --git a/boards/raytac/mdbt50q_db_33/Kconfig.defconfig b/boards/raytac/mdbt50q_db_33/Kconfig.defconfig new file mode 100644 index 00000000000000..bb5e7c4a14dc05 --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Raytac MDBT50Q-DB-33 NRF52833 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_DB_33 + +config BT_CTLR + default BT + +endif # BOARD_RAYTAC_MDBT50Q_DB_33 diff --git a/boards/raytac/mdbt50q_db_33/Kconfig.raytac_mdbt50q_db_33 b/boards/raytac/mdbt50q_db_33/Kconfig.raytac_mdbt50q_db_33 new file mode 100644 index 00000000000000..edd49089253c01 --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/Kconfig.raytac_mdbt50q_db_33 @@ -0,0 +1,7 @@ +# Raytac MDBT50Q-DB-33 nRF52833 board configuration + +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT50Q_DB_33 + select SOC_NRF52833_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/board.cmake b/boards/raytac/mdbt50q_db_33/board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/board.cmake rename to boards/raytac/mdbt50q_db_33/board.cmake diff --git a/boards/raytac/mdbt50q_db_33/board.yml b/boards/raytac/mdbt50q_db_33/board.yml new file mode 100644 index 00000000000000..dbad99fd48979f --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/board.yml @@ -0,0 +1,5 @@ +board: + name: raytac_mdbt50q_db_33 + vendor: raytac + socs: + - name: nrf52833 diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/img/mdbt50q_db_33.jpg b/boards/raytac/mdbt50q_db_33/doc/img/mdbt50q_db_33.jpg similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/doc/img/mdbt50q_db_33.jpg rename to boards/raytac/mdbt50q_db_33/doc/img/mdbt50q_db_33.jpg diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst new file mode 100644 index 00000000000000..b078dd2984e0e3 --- /dev/null +++ b/boards/raytac/mdbt50q_db_33/doc/index.rst @@ -0,0 +1,213 @@ +.. _raytac_mdbt50q_db_33_nrf52833: + +Raytac MDBT50Q-DB-33 +#################### + +Overview +******** + +The Raytac MDBT50Q-DB-33 hardware provides support for the +Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/mdbt50q_db_33.jpg + :width: 442px + :align: center + :alt: MDBT50Q-DB-33 + +More information about the board can be found at the `MDBT50Q-DB-33 website`_. +The `MDBT50Q-DB-33 Specification`_ contains the demo board's datasheet. +The `MDBT50Q-DB-33 Schematic`_ contains the demo board's schematic. + +Hardware +******** +- Module Demo Board build by MDBT50Q-512K +- Nordic nRF52833 SoC Solution +- A recommnded 3rd-party module by Nordic Semiconductor. +- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified +- Supports BT5 Long Range Features +- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC +- 32-bit ARM® Cortex™ M4F CPU +- 512kB Flash Memory/128kB RAM +- RoHs & Reach Compiant. +- 42 GPIO +- Chip Antenna +- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. +- 3 User LEDs +- 4 User buttons +- 1 Mini USB connector for power supply and USB communication +- SWD connector for FW programing +- J-Link interface for FW programing +- UART interface for UART communication + +Supported Features +================== + +The raytac_mdbt50q_db_33/nrf52833 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `MDBT50Q-DB-33 website`_ and `MDBT50Q-DB-33 Specification`_ +for a complete list of Raytac MDBT50Q-DB-33 board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (red) = P0.14 +* LED3 (blue) = P0.15 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 + +UART +---- +* RXD = P0.08 +* TXD = P0.06 +* RTS = P0.05 +* CTS = P0.07 + +Programming and Debugging +************************* + +Applications for the ``raytac_mdbt50q_db_33/nrf52833`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +.. note:: + Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_33/nrf52833 board + requires an external J-Link programmer. The programmer is attached to the J1 + or J9 SWD connector. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_33/nrf52833 +J10 connector. Then run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the USB to TTL converter +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_mdbt50q_db_33/nrf52833 + :goals: build flash + +Debugging +========= + +The ``raytac_mdbt50q_db_33/nrf52833`` board does not have an on-board-J-Link debug IC, +however, instructions from the :ref:`nordic_segger` page also apply to this board. +Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER +J-Link OB IF to debug. + +Testing the LEDs and buttons in the Raytac MDBT50Q-DB-33 +******************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts`. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `MDBT50Q-DB-33 Specification`_, chapter 2.5 'Pin Assignment'. +Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O +only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, +UART, and PWM. + +References +********** + +.. target-notes:: + +.. _MDBT50Q-DB-33 website: + https://www.raytac.com/product/ins.php?index_id=97 +.. _MDBT50Q-DB-33 Specification: + https://www.raytac.com/download/index.php?index_id=46 +.. _MDBT50Q-DB-33 Schematic: + https://www.raytac.com/upload/catalog_b/407c1150fa33511a47e8a2f85d106ff3.jpg +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html diff --git a/boards/arm/rak5010_nrf52840/pre_dt_board.cmake b/boards/raytac/mdbt50q_db_33/pre_dt_board.cmake similarity index 100% rename from boards/arm/rak5010_nrf52840/pre_dt_board.cmake rename to boards/raytac/mdbt50q_db_33/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.dts b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.dts rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.dts diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.yaml b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml similarity index 89% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.yaml rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml index 9284c90aa8eac9..673705fa1237b2 100644 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833.yaml +++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt50q_db_33_nrf52833 +identifier: raytac_mdbt50q_db_33/nrf52833 name: Raytac MDBT50Q-DB-33 nRF52833 type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833_defconfig b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833_defconfig similarity index 79% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833_defconfig rename to boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833_defconfig index 1176302a56d27e..d0b9df8255d576 100644 --- a/boards/arm/raytac_mdbt50q_db_33_nrf52833/raytac_mdbt50q_db_33_nrf52833_defconfig +++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_RAYTAC_MDBT50Q_DB_33_NRF52833=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/raytac/mdbt50q_db_40/Kconfig b/boards/raytac/mdbt50q_db_40/Kconfig new file mode 100644 index 00000000000000..bb2c5c4ad7751b --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/Kconfig @@ -0,0 +1,18 @@ +# Raytac MDBT50Q-DB-40 nRF52840 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_DB_40 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + +endif # BOARD_RAYTAC_MDBT50Q_DB_40 diff --git a/boards/raytac/mdbt50q_db_40/Kconfig.defconfig b/boards/raytac/mdbt50q_db_40/Kconfig.defconfig new file mode 100644 index 00000000000000..2919530e87c992 --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Raytac MDBT50Q-DB-40 NRF52840 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT50Q_DB_40 + +config BT_CTLR + default BT + +endif # BOARD_RAYTAC_MDBT50Q_DB_40 diff --git a/boards/raytac/mdbt50q_db_40/Kconfig.raytac_mdbt50q_db_40 b/boards/raytac/mdbt50q_db_40/Kconfig.raytac_mdbt50q_db_40 new file mode 100644 index 00000000000000..30fb87de803e97 --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/Kconfig.raytac_mdbt50q_db_40 @@ -0,0 +1,7 @@ +# Raytac MDBT50Q-DB-40 nRF52840 board configuration + +# Copyright (c) 2022 Raytac Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT50Q_DB_40 + select SOC_NRF52840_QIAA diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/board.cmake b/boards/raytac/mdbt50q_db_40/board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/board.cmake rename to boards/raytac/mdbt50q_db_40/board.cmake diff --git a/boards/raytac/mdbt50q_db_40/board.yml b/boards/raytac/mdbt50q_db_40/board.yml new file mode 100644 index 00000000000000..a8c109b715f78b --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/board.yml @@ -0,0 +1,5 @@ +board: + name: raytac_mdbt50q_db_40 + vendor: raytac + socs: + - name: nrf52840 diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/img/mdbt50q_db_40.jpg b/boards/raytac/mdbt50q_db_40/doc/img/mdbt50q_db_40.jpg similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/doc/img/mdbt50q_db_40.jpg rename to boards/raytac/mdbt50q_db_40/doc/img/mdbt50q_db_40.jpg diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst new file mode 100644 index 00000000000000..f9d79818f6a8e2 --- /dev/null +++ b/boards/raytac/mdbt50q_db_40/doc/index.rst @@ -0,0 +1,215 @@ +.. _raytac_mdbt50q_db_40_nrf52840: + +Raytac MDBT50Q-DB-40 +#################### + +Overview +******** + +The Raytac MDBT50Q-DB-40 hardware provides support for the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/mdbt50q_db_40.jpg + :width: 442px + :align: center + :alt: MDBT50Q-DB-40 + +More information about the board can be found at the `MDBT50Q-DB-40 website`_. +The `MDBT50Q-DB-40 Specification`_ contains the demo board's datasheet. +The `MDBT50Q-DB-40 Schematic`_ contains the demo board's schematic. + +Hardware +******** +- Module Demo Board build by MDBT50Q-1MV2 +- Nordic nRF52840 SoC Solution Version: 2 +- A recommnded 3rd-party module by Nordic Semiconductor. +- BT5.2&BT5.1&BT5 Bluetooth Specification Cerified +- Supports BT5 Long Range Features +- Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC +- 32-bit ARM® Cortex™ M4F CPU +- 1MB Flash Memory/256kB RAM +- RoHs & Reach Compiant. +- 48 GPIO +- Chip Antenna +- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. +- 3 User LEDs +- 4 User buttons +- 1 Mini USB connector for power supply and USB communication +- SWD connector for FW programing +- J-Link interface for FW programing +- UART interface for UART communication + +Supported Features +================== + +The raytac_mdbt50q_db_40/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | qspi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `MDBT50Q-DB-40 website`_ and `MDBT50Q-DB-40 Specification`_ +for a complete list of Raytac MDBT50Q-DB-40 board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.13 +* LED2 (red) = P0.14 +* LED3 (blue) = P0.15 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 + +UART +---- +* RXD = P0.08 +* TXD = P0.06 +* RTS = P0.05 +* CTS = P0.07 + +Programming and Debugging +************************* + +Applications for the ``raytac_mdbt50q_db_40/nrf52840`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +.. note:: + Flashing and Debugging Zephyr onto the raytac_mdbt50q_db_40/nrf52840 board + requires an external J-Link programmer. The programmer is attached to the J1 + or J9 SWD connector. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Use a USB to TTL converter to connect the computer and raytac_mdbt50q_db_40/nrf52840 +J10 connector. Then run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the USB to TTL converter +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_mdbt50q_db_40/nrf52840 + :goals: build flash + +Debugging +========= + +The ``raytac_mdbt50q_db_40/nrf52840`` board does not have an on-board-J-Link debug IC, +however, instructions from the :ref:`nordic_segger` page also apply to this board. +Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER +J-Link OB IF to debug. + +Testing the LEDs and buttons in the MDBT50Q-DB-40 +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts`. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the `MDBT50Q-DB-40 Specification`_, chapter 2.5 'Pin Assignment'. +Select the pins marked 'General-purpose I/O'. Note that pins marked as 'low-frequency I/O +only' can only be used in under-10KHz applications. They are not suitable for SPI, I2C, +UART, and PWM. + +References +********** + +.. target-notes:: + +.. _MDBT50Q-DB-40 website: + https://www.raytac.com/product/ins.php?index_id=81 +.. _MDBT50Q-DB-40 Specification: + https://www.raytac.com/download/index.php?index_id=43 +.. _MDBT50Q-DB-40 Schematic: + https://www.raytac.com/upload/catalog_b/134ade06b5db3dd5803d27c5b17f22f3.jpg +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt50q_db_33_nrf52833/pre_dt_board.cmake b/boards/raytac/mdbt50q_db_40/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_33_nrf52833/pre_dt_board.cmake rename to boards/raytac/mdbt50q_db_40/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.dts b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.dts rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.dts diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.yaml b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml similarity index 90% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.yaml rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml index 7c6626fbe34b47..15ba012594ee85 100644 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840.yaml +++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml @@ -3,7 +3,7 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt50q_db_40_nrf52840 +identifier: raytac_mdbt50q_db_40/nrf52840 name: Raytac MDBT50Q_DB_40_NRF52840 type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840_defconfig b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840_defconfig similarity index 79% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840_defconfig rename to boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840_defconfig index 3651902f7403a5..7515c65a6a7895 100644 --- a/boards/arm/raytac_mdbt50q_db_40_nrf52840/raytac_mdbt50q_db_40_nrf52840_defconfig +++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2022 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_RAYTAC_MDBT50Q_DB_40_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/raytac/mdbt53_db_40/CMakeLists.txt b/boards/raytac/mdbt53_db_40/CMakeLists.txt new file mode 100644 index 00000000000000..44bcab2993ea94 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(raytac_mdbt53_db_40_nrf5340_cpunet_reset.c) +endif() diff --git a/boards/raytac/mdbt53_db_40/Kconfig b/boards/raytac/mdbt53_db_40/Kconfig new file mode 100644 index 00000000000000..a436b55cfb4748 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/Kconfig @@ -0,0 +1,61 @@ +# Ratac MDBT53-DB-40 nRF5340 board configuration + +# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "raytac_mdbt53_db_40/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "raytac_mdbt53_db_40/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/Kconfig.defconfig b/boards/raytac/mdbt53_db_40/Kconfig.defconfig new file mode 100644 index 00000000000000..7bb0e9da9484c9 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/Kconfig.defconfig @@ -0,0 +1,77 @@ +# Raytac MDBT53-DB-40 nRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/Kconfig.raytac_mdbt53_db_40 b/boards/raytac/mdbt53_db_40/Kconfig.raytac_mdbt53_db_40 new file mode 100644 index 00000000000000..52d6bfd6dbbc78 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/Kconfig.raytac_mdbt53_db_40 @@ -0,0 +1,9 @@ +# Raytac MDBT53-DB-40 NRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT53_DB_40 + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53_db_40/board.cmake b/boards/raytac/mdbt53_db_40/board.cmake new file mode 100644 index 00000000000000..e181f29ca44baf --- /dev/null +++ b/boards/raytac/mdbt53_db_40/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(CONFIG_BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/raytac/mdbt53_db_40/board.yml b/boards/raytac/mdbt53_db_40/board.yml new file mode 100644 index 00000000000000..84bef186b33664 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/board.yml @@ -0,0 +1,8 @@ +board: + name: raytac_mdbt53_db_40 + vendor: raytac + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/doc/img/MDBT53-DB-40.jpg b/boards/raytac/mdbt53_db_40/doc/img/MDBT53-DB-40.jpg similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/doc/img/MDBT53-DB-40.jpg rename to boards/raytac/mdbt53_db_40/doc/img/MDBT53-DB-40.jpg diff --git a/boards/raytac/mdbt53_db_40/doc/index.rst b/boards/raytac/mdbt53_db_40/doc/index.rst new file mode 100644 index 00000000000000..a57fc5225dc5f8 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/doc/index.rst @@ -0,0 +1,271 @@ +.. _raytac_mdbt53_db_40_nrf5340: + +Raytac MDBT53-DB-40 +################### + +Overview +******** + +Raytac MDBT53-DB-40 demo board is a development board based on the Raytac MDBT53-1M module, +using Nordic Semiconductor nRF5340 ARM Cortex-M33 SoC. Its design concept is to connect all +of the module's pins to 2.54mm pin headers. It is convenient for developers to verify whether +the modules are connected to other peripheral devices or sensors as a tool for software development. + +The nRF5340 inside the MDBT53-1M module is a +dual-core SoC based on the Arm® Cortex®-M33 architecture, with: + +* a full-featured Arm Cortex-M33F core with DSP instructions, FPU, and + Armv8-M Security Extension, running at up to 128 MHz, referred to as + the **application core** +* a secondary Arm Cortex-M33 core, with a reduced feature set, running + at a fixed 64 MHz, referred to as the **network core**. + +The ``raytac_mdbt53_db_40/nrf5340/cpuapp`` build target provides support for the application +core on the nRF5340 SoC. The ``raytac_mdbt53_db_40/nrf5340/cpuapp`` build target provides +support for the network core on the nRF5340 SoC. + +nRF5340 SoC provides support for the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`QSPI (Quad Serial Peripheral Interface)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/MDBT53-DB-40.jpg + :width: 442px + :align: center + :alt: MDBT53-DB-40 + + MDBT53-DB-40 (Credit: Raytac Corporation) + +More information about the board can be found at the `MDBT53-DB-40 website`_. +The `MDBT53-DB-40 Specification`_ contains the demo board's datasheet. +The `MDBT53-DB-40 Schematic`_ contains the demo board's schematic. + +Hardware +******** +- Module Demo Board build by MDBT53-1M +- Nordic nRF5340 SoC Solution +- A recommnded 3rd-party module by Nordic Semiconductor. +- Dual-core Arm® Cortex® M33 +- 1MB/256KB Flash Memory; 512kB/ 64kB RAM +- Supports BT5 Long Range Features +- Bluetooth specification v5.2 +- Supports Bluetooth Direction Finding & Mesh +- Supports Bluetooth low energy audio +- Certifications: FCC, IC, CE, Telec (MIC), KC, SRRC, NCC, RCM, WPC +- RoHs & Reach Compiant. +- 48 GPIO +- Chip Antenna +- Interfaces: SPI, UART, I2C, I2S, PWM, ADC, NFC, and USB +- Highly flexible multiprotocol SoC ideally suited for Bluetooth® Low Energy, ANT+, Zigbee, Thread (802.15.4) ultra low-power wireless applications. +- 4 User LEDs +- 4 User buttons +- 1 Mini USB connector for power supply +- SWD connector for FW programing +- J-Link interface for FW programing +- UART interface for UART communication + +Supported Features +================== + +The ``raytac_mdbt53_db_40_nrf5340/cpuapp`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| QSPI(M) | on-chip | nor | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| SPU | on-chip | system protection | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +The ``raytac_mdbt53_db_40_nrf5340/cpunet`` board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UARTE | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `MDBT53-DB-40 website`_ and `MDBT53-DB-40 Specification`_ +for a complete list of Raytac MDBT53-DB-40 board hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (green) = P0.28 +* LED2 (red) = P0.30 +* LED3 = P0.31 +* LED4 = P0.29 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.24 +* BUTTON2 = SW2 = P0.08 +* BUTTON3 = SW3 = P0.23 +* BUTTON4 = SW4 = P0.09 + +UART +---- +* RX = P0.22 +* TX = P0.20 +* RTS = P0.19 +* CTS = P0.21 + + +Security components +=================== + +- Implementation Defined Attribution Unit (`IDAU`_) on the application core. + The IDAU is implemented with the System Protection Unit and is used to + define secure and non-secure memory maps. By default, all of the memory + space (Flash, SRAM, and peripheral address space) is defined to be secure + accessible only. +- Secure boot. + +Programming and Debugging +************************* + +nRF5340 application core supports the Armv8-M Security Extension. +Applications built for the ``raytac_mdbt53_db_40/nrf5340/cpuapp`` board by +default boot in the Secure state. + +nRF5340 network core does not support the Armv8-M Security Extension. +nRF5340 IDAU may configure bus accesses by the nRF5340 network core +to have Secure attribute set; the latter allows to build and run +Secure only applications on the nRF5340 SoC. + +Applications for the ``raytac_mdbt53_db_40_nrf5340`` board configuration can be +built, flashed, and debugged in the usual way. See :ref:`build_an_application` and +:ref:`application_run` for more details on building and running. + +.. note:: + Flashing and Debugging Zephyr onto the raytac_mdbt53_db_40_nrf5340 board + requires an external J-Link programmer. The programmer is attached to the J1 + or J9 SWD connector. + + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. warning:: + + The nRF5340 has a flash read-back protection feature. When flash read-back + protection is active, you will need to recover the chip before reflashing. + If you are flashing with :ref:`west `, run + this command for more details on the related ``--recover`` option: + +Here is an example for the :ref:`hello_world` application. + +Use a USB to TTL converter to connect the computer and raytac_mdbt53_db_40_nrf5340 +J10 connector. Then run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the USB to TTL converter +can be found. For example, under Linux, :code:`/dev/ttyUSB0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: raytac_mdbt53_db_40_nrf5340 + :goals: build flash + +Debugging +========= + +The ``raytac_mdbt53_db_40_nrf5340`` board does not have an on-board-J-Link debug IC, +however, instructions from the :ref:`nordic_segger` page also apply to this board. +Use the Debug out connector of nRF52x DK to connect to the J1 connector, and use SEGGER +J-Link OB IF to debug. + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + + +References +********** + +.. _IDAU: + https://developer.arm.com/docs/100690/latest/attribution-units-sau-and-idau +.. _MDBT53-DB-40 website: + https://www.raytac.com/product/ins.php?index_id=139 +.. _MDBT53-DB-40 Specification: + https://www.raytac.com/download/index.php?index_id=60 +.. _MDBT53-DB-40 Schematic: + https://www.raytac.com/upload/catalog_b/8b5e364600a9cc8c53a869733e97f07e.jpg +.. _J-Link Software and documentation pack: + https://www.segger.com/jlink-software.html diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/pre_dt_board.cmake b/boards/raytac/mdbt53_db_40/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/pre_dt_board.cmake rename to boards/raytac/mdbt53_db_40/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml similarity index 85% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml index 4f70a9e375d392..f962784606bd36 100644 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53_db_40_nrf5340_cpuapp +identifier: raytac_mdbt53_db_40/nrf5340/cpuapp name: RAYTAC-MDBT53-DB-40-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_common.dts diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml similarity index 84% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml index 5c402d46273586..46fbe1ea1928e2 100644 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53_db_40_nrf5340_cpuapp_ns +identifier: raytac_mdbt53_db_40/nrf5340/cpuapp/ns name: RAYTAC-MDBT53-DB-40-NRF52840-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000000..2a74dd56f4144a --- /dev/null +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_partition_conf.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.dts diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml similarity index 87% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.yaml rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml index bf82a0627c18af..b6badb279f9a96 100644 --- a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet.yaml +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml @@ -2,7 +2,7 @@ # Copyright (c) 2023 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt53_db_40_nrf5340_cpunet +identifier: raytac_mdbt53_db_40/nrf5340/cpunet name: RAYTAC MDBT53-DB-40-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_common.dts diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..56940c43a096e0 --- /dev/null +++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet_reset.c diff --git a/boards/arm64/roc_rk3568_pc/board.cmake b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig similarity index 100% rename from boards/arm64/roc_rk3568_pc/board.cmake rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_defconfig diff --git a/boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53_db_40_nrf5340/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts rename to boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_shared_sram_planning_conf.dts diff --git a/boards/raytac/mdbt53v_db_40/CMakeLists.txt b/boards/raytac/mdbt53v_db_40/CMakeLists.txt new file mode 100644 index 00000000000000..b31ed4ce0f2035 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +if((CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) + AND CONFIG_BOARD_ENABLE_CPUNET) + zephyr_library() + zephyr_library_sources(raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c) +endif() diff --git a/boards/raytac/mdbt53v_db_40/Kconfig b/boards/raytac/mdbt53v_db_40/Kconfig new file mode 100644 index 00000000000000..fb688bae818fe8 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/Kconfig @@ -0,0 +1,61 @@ +# Ratac MDBT53V-DB-40 nRF5340 board configuration + +# Copyright (c) 2019 - 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +config BOARD_ENABLE_DCDC_APP + bool "Application MCU DCDC converter" + select SOC_DCDC_NRF53X_APP + default y + +config BOARD_ENABLE_DCDC_NET + bool "Network MCU DCDC converter" + select SOC_DCDC_NRF53X_NET + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF53X_HV + default y + +config BOARD_ENABLE_CPUNET + bool "NRF53 Network MCU" + select SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 if \ + $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER)) + help + This option enables releasing the Network 'force off' signal, which + as a consequence will power up the Network MCU during system boot. + Additionally, the option allocates GPIO pins that will be used by UARTE + of the Network MCU. + Note: GPIO pin allocation can only be configured by the secure Application + MCU firmware, so when this option is used with the non-secure version of + the board, the application needs to take into consideration, that the + secure firmware image must already have configured GPIO allocation for the + Network MCU. + default y if (BT || NRF_802154_SER_HOST) + +config DOMAIN_CPUNET_BOARD + string + default "raytac_mdbt53v_db_40/nrf5340/cpunet" + depends on BOARD_ENABLE_CPUNET + help + The board which will be used for CPUNET domain when creating a multi + image application where one or more images should be located on + another board. For example hci_ipc on the nRF5340_cpunet for + Bluetooth applications. + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET + +config DOMAIN_CPUAPP_BOARD + string + default "raytac_mdbt53v_db_40/nrf5340/cpuapp" + help + The board which will be used for CPUAPP domain when creating a multi + image application where one or more images should be located on + another board. + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/Kconfig.defconfig b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig new file mode 100644 index 00000000000000..9cdb1683eed02f --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/Kconfig.defconfig @@ -0,0 +1,77 @@ +# Raytac MDBT53V-DB-40 nRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +# Code Partition: +# +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# SRAM Partition: +# +# If the secure firmware is to be combined with a non-secure image +# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always +# be restricted to the secure image SRAM partition (sram-secure-partition). +# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram +# may be used by the image. +# +# For the non-secure version of the board, the firmware image SRAM is +# always restricted to the allocated non-secure SRAM partition. +# +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition +DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config SRAM_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K) + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +choice BT_HCI_BUS_TYPE + default BT_HCI_IPC if BT +endchoice + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 4096 if BT_HCI_IPC + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + +config IPM_NRFX + default IPM + +config MBOX_NRFX_IPC + default MBOX + +if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET + +config BT_CTLR + default y if BT + +endif # BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/Kconfig.raytac_mdbt53v_db_40 b/boards/raytac/mdbt53v_db_40/Kconfig.raytac_mdbt53v_db_40 new file mode 100644 index 00000000000000..1d72e87151c691 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/Kconfig.raytac_mdbt53v_db_40 @@ -0,0 +1,9 @@ +# Raytac MDBT53-DB-40 NRF5340 board configuration + +# Copyright (c) 2019-2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RAYTAC_MDBT53V_DB_40 + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP + select SOC_NRF5340_CPUAPP_QKAA if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS + select SOC_NRF5340_CPUNET_QKAA if BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET diff --git a/boards/raytac/mdbt53v_db_40/board.cmake b/boards/raytac/mdbt53v_db_40/board.cmake new file mode 100644 index 00000000000000..da45d8b8e838e2 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP OR CONFIG_BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUAPP_NS) + board_runner_args(jlink "--device=nrf5340_xxaa_app" "--speed=4000") +elseif(BOARD_RAYTAC_MDBT53V_DB_40_NRF5340_CPUNET) + board_runner_args(jlink "--device=nrf5340_xxaa_net" "--speed=4000") +endif() + +include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/raytac/mdbt53v_db_40/board.yml b/boards/raytac/mdbt53v_db_40/board.yml new file mode 100644 index 00000000000000..9d3bfd4689baef --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/board.yml @@ -0,0 +1,8 @@ +board: + name: raytac_mdbt53v_db_40 + vendor: raytac + socs: + - name: 'nrf5340' + variants: + - name: 'ns' + cpucluster: 'cpuapp' diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/img/MDBT53V-DB-40.jpg b/boards/raytac/mdbt53v_db_40/doc/img/MDBT53V-DB-40.jpg similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/img/MDBT53V-DB-40.jpg rename to boards/raytac/mdbt53v_db_40/doc/img/MDBT53V-DB-40.jpg diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/index.rst b/boards/raytac/mdbt53v_db_40/doc/index.rst similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/doc/index.rst rename to boards/raytac/mdbt53v_db_40/doc/index.rst diff --git a/boards/arm/thingy53_nrf5340/pre_dt_board.cmake b/boards/raytac/mdbt53v_db_40/pre_dt_board.cmake similarity index 100% rename from boards/arm/thingy53_nrf5340/pre_dt_board.cmake rename to boards/raytac/mdbt53v_db_40/pre_dt_board.cmake diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml similarity index 83% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml index c9552cb6202cff..bd5763672682b9 100644 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53v_db_40_nrf5340_cpuapp +identifier: raytac_mdbt53v_db_40/nrf5340/cpuapp name: RAYTAC-MDBT53V-DB-40-NRF5340-application-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_common.dts diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig new file mode 100644 index 00000000000000..c486d8323821a2 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml similarity index 81% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml index 5251dc8737f473..e5340237e6a98e 100644 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml @@ -1,4 +1,4 @@ -identifier: raytac_mdbt53v_db_40_nrf5340_cpuapp_ns +identifier: raytac_mdbt53v_db_40/nrf5340/cpuapp/ns name: RAYTAC-MDBT53V-DB-40-NRF52840-application-MCU-Non-Secure type: mcu arch: arm diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig new file mode 100644 index 00000000000000..2a74dd56f4144a --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_partition_conf.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet-pinctrl.dtsi diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.dts diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml similarity index 86% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml index a76a74a6598efd..eb5cac4d60941d 100644 --- a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml @@ -2,7 +2,7 @@ # Copyright (c) 2023 Raytac Corporation # SPDX-License-Identifier: Apache-2.0 -identifier: raytac_mdbt53v_db_40_nrf5340_cpunet +identifier: raytac_mdbt53v_db_40/nrf5340/cpunet name: RAYTAC MDBT53V-DB-40-NRF5340-network-MCU type: mcu arch: arm diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_common.dts diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig new file mode 100644 index 00000000000000..56940c43a096e0 --- /dev/null +++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet_reset.c diff --git a/boards/arm64/rpi_4b/board.cmake b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig similarity index 100% rename from boards/arm64/rpi_4b/board.cmake rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_defconfig diff --git a/boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts similarity index 100% rename from boards/arm/raytac_mdbt53v_db_40_nrf5340/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts rename to boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_shared_sram_planning_conf.dts diff --git a/boards/renesas/da14695_dk_usb/Kconfig.da14695_dk_usb b/boards/renesas/da14695_dk_usb/Kconfig.da14695_dk_usb new file mode 100644 index 00000000000000..7a321bc345b4e8 --- /dev/null +++ b/boards/renesas/da14695_dk_usb/Kconfig.da14695_dk_usb @@ -0,0 +1,7 @@ +# DA14695 Development Kit USB board configuration + +# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DA14695_DK_USB + select SOC_DA14695 diff --git a/boards/arm/da14695_dk_usb/board.cmake b/boards/renesas/da14695_dk_usb/board.cmake similarity index 100% rename from boards/arm/da14695_dk_usb/board.cmake rename to boards/renesas/da14695_dk_usb/board.cmake diff --git a/boards/renesas/da14695_dk_usb/board.yml b/boards/renesas/da14695_dk_usb/board.yml new file mode 100644 index 00000000000000..b9d3f06cb1d097 --- /dev/null +++ b/boards/renesas/da14695_dk_usb/board.yml @@ -0,0 +1,5 @@ +board: + name: da14695_dk_usb + vendor: renesas + socs: + - name: da14695 diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi b/boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi similarity index 100% rename from boards/arm/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi rename to boards/renesas/da14695_dk_usb/da14695_dk_usb-pinctrl.dtsi diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb.dts b/boards/renesas/da14695_dk_usb/da14695_dk_usb.dts similarity index 100% rename from boards/arm/da14695_dk_usb/da14695_dk_usb.dts rename to boards/renesas/da14695_dk_usb/da14695_dk_usb.dts diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb.yaml b/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml similarity index 100% rename from boards/arm/da14695_dk_usb/da14695_dk_usb.yaml rename to boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml diff --git a/boards/arm/da14695_dk_usb/da14695_dk_usb_defconfig b/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig similarity index 77% rename from boards/arm/da14695_dk_usb/da14695_dk_usb_defconfig rename to boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig index d0a672430343df..737b2cdd1b3853 100644 --- a/boards/arm/da14695_dk_usb/da14695_dk_usb_defconfig +++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb_defconfig @@ -4,10 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_DA1469X=y -CONFIG_SOC_DA14695=y -CONFIG_BOARD_DA14695_DK_USB=y - CONFIG_HW_STACK_PROTECTION=y CONFIG_GPIO=y diff --git a/boards/arm/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg b/boards/renesas/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg similarity index 100% rename from boards/arm/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg rename to boards/renesas/da14695_dk_usb/doc/da14695-00hqdevkt-u-usb-board.jpg diff --git a/boards/arm/da14695_dk_usb/doc/index.rst b/boards/renesas/da14695_dk_usb/doc/index.rst similarity index 100% rename from boards/arm/da14695_dk_usb/doc/index.rst rename to boards/renesas/da14695_dk_usb/doc/index.rst diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.da1469x_dk_pro b/boards/renesas/da1469x_dk_pro/Kconfig.da1469x_dk_pro new file mode 100644 index 00000000000000..890b918347deae --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/Kconfig.da1469x_dk_pro @@ -0,0 +1,7 @@ +# DA1469x series Development Kit Pro board configuration + +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DA1469X_DK_PRO + select SOC_DA14699 diff --git a/boards/arm/da1469x_dk_pro/board.cmake b/boards/renesas/da1469x_dk_pro/board.cmake similarity index 100% rename from boards/arm/da1469x_dk_pro/board.cmake rename to boards/renesas/da1469x_dk_pro/board.cmake diff --git a/boards/renesas/da1469x_dk_pro/board.yml b/boards/renesas/da1469x_dk_pro/board.yml new file mode 100644 index 00000000000000..09ab03c0b26c05 --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/board.yml @@ -0,0 +1,5 @@ +board: + name: da1469x_dk_pro + vendor: renesas + socs: + - name: da14699 diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi similarity index 100% rename from boards/arm/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi rename to boards/renesas/da1469x_dk_pro/da1469x_dk_pro-pinctrl.dtsi diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro.dts b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts similarity index 100% rename from boards/arm/da1469x_dk_pro/da1469x_dk_pro.dts rename to boards/renesas/da1469x_dk_pro/da1469x_dk_pro.dts diff --git a/boards/arm/da1469x_dk_pro/da1469x_dk_pro.yaml b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml similarity index 100% rename from boards/arm/da1469x_dk_pro/da1469x_dk_pro.yaml rename to boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig new file mode 100644 index 00000000000000..e31b6eb8457f39 --- /dev/null +++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_GPIO=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y + +CONFIG_BUILD_OUTPUT_HEX=n + +CONFIG_I2C=y +CONFIG_I2C_CALLBACK=y diff --git a/boards/arm/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg b/boards/renesas/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg similarity index 100% rename from boards/arm/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg rename to boards/renesas/da1469x_dk_pro/doc/da14695-00hqdevkt-board.jpg diff --git a/boards/arm/da1469x_dk_pro/doc/index.rst b/boards/renesas/da1469x_dk_pro/doc/index.rst similarity index 100% rename from boards/arm/da1469x_dk_pro/doc/index.rst rename to boards/renesas/da1469x_dk_pro/doc/index.rst diff --git a/boards/renesas/index.rst b/boards/renesas/index.rst new file mode 100644 index 00000000000000..2597c70e29e5d6 --- /dev/null +++ b/boards/renesas/index.rst @@ -0,0 +1,10 @@ +.. _boards-renesas: + +Renesas Electronics Corporation +############################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/renesas/rcar_h3ulcb/Kconfig.defconfig b/boards/renesas/rcar_h3ulcb/Kconfig.defconfig new file mode 100644 index 00000000000000..6586e5575bcc51 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RCAR_H3ULCB + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_RCAR_H3ULCB diff --git a/boards/renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb b/boards/renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb new file mode 100644 index 00000000000000..87d3065cd8f026 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/Kconfig.rcar_h3ulcb @@ -0,0 +1,6 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_H3ULCB + select SOC_R8A77951_R7 if BOARD_RCAR_H3ULCB_R8A77951_R7 + select SOC_R8A77951_A57 if BOARD_RCAR_H3ULCB_R8A77951_A57 diff --git a/boards/renesas/rcar_h3ulcb/board.cmake b/boards/renesas/rcar_h3ulcb/board.cmake new file mode 100644 index 00000000000000..963f11d9f47df9 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_RCAR_H3ULCB_R8A77951_R7) + board_runner_args(openocd "--use-elf") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +endif() diff --git a/boards/renesas/rcar_h3ulcb/board.yml b/boards/renesas/rcar_h3ulcb/board.yml new file mode 100644 index 00000000000000..7989c688e8126d --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_h3ulcb + vendor: renesas + socs: + - name: r8a77951 diff --git a/boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_bottom.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg similarity index 100% rename from boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_bottom.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_bottom.jpg diff --git a/boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg similarity index 100% rename from boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_features.jpg diff --git a/boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg similarity index 100% rename from boards/arm/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_starter_kit.jpg diff --git a/boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_top.jpg b/boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg similarity index 100% rename from boards/arm64/rcar_h3ulcb_ca57/doc/img/rcar_h3ulcb_top.jpg rename to boards/renesas/rcar_h3ulcb/doc/img/rcar_h3ulcb_top.jpg diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst new file mode 100644 index 00000000000000..038666ad623416 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_a57.rst @@ -0,0 +1,85 @@ +.. _rcar_h3ulcb_ca57: + +R-CAR H3 ARM CA57 (ARMv8) +######################### + +Overview +******** +The R-Car H3 is an SOC that features the basic functions for next-generation +car navigation systems. + +Hardware +******** +The R-Car H3 includes: + +* four 1.5-GHz ARM Cortex-A57 MPCore cores; +* four 1.2-GHz ARM Cortex-A53 MPCore cores; +* memory controller for LPDDR4-3200 with 32 bits x 4 channels; +* 2 channels for HDMI1.4b output and 1channel for RGB888 output and 1channel for LVDS; +* 4 channels MIPI-CSI2 Video Input, 2channels digital Video Input; +* serial ATA interface; +* USB3.0 x 2ch and USB2.0 x 3ch interfaces; +* 800-MHz ARM Cortex-R7 core; +* two- and three-dimensional graphics engines; +* video processing units; +* sound processing units; +* MediaLB interface; +* SD card host interface; +* USB3.0 and USB2.0 interfaces; +* PCI Express interface; +* CAN interface; +* EtherAVB. + +Connections and IOs +=================== + +H3ULCB Board +------------ + +Here are official IOs figures from eLinux for H3ULCB board: + +.. figure:: img/rcar_h3ulcb_top.jpg + :align: center + +.. figure:: img/rcar_h3ulcb_bottom.jpg + :align: center + +Supported Features +================== +The Renesas rcar_h3ulcb_ca57 board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig`` + +Programming and Debugging +************************* + +Flashing +======== + +The flash on board is not supported by Zephyr at this time. + +References +********** + +- `Renesas R-Car Development Support website`_ +- `eLinux R-Car Starter Kit page`_ + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux R-Car Starter Kit page: + https://elinux.org/R-Car/Boards/H3SK diff --git a/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst new file mode 100644 index 00000000000000..5fcd4fa090910f --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/doc/rcar_h3ulcb_r7.rst @@ -0,0 +1,276 @@ +.. _rcar_h3ulcb_boards: + +Renesas R-Car H3ULCB +#################### + +Overview +******** +- The H3 Starter Kit board is designed for evaluating the features and performance of the R-CAR H3 device from Renesas Electronics and it is also used for developing and evaluating application software for these R-CAR H3. + +- The H3 Starter Kit, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, via 440pin connector on bottom side. + +It is possible to order 2 different types of H3 Starter Kit Boards, one with Ethernet connection onboard and one with Ethernet connection on ComExpress. + +.. figure:: img/rcar_h3ulcb_starter_kit.jpg + :align: center + :alt: R-Car starter kit + +.. note:: The H3ULCB board can be plugged on a Renesas Kingfisher Infotainment daughter board through COM Express connector in order to physically access more I/O. CAUTION: In this case, power supply is managed by the daughter board. + +More information about the board can be found at `Renesas R-Car Starter Kit website`_. + +Hardware +******** + +Hardware capabilities for the H3ULCB for can be found on the `eLinux H3SK page`_ of the board. + +.. figure:: img/rcar_h3ulcb_features.jpg + :align: center + :alt: R-Car starter kit features + +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. + +More information about the SoC that equips the board can be found here: + +- `Renesas R-Car H3 chip`_ + +Supported Features +================== + +Here is the current supported features when running Zephyr Project on the R-Car ULCB CR7: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINMUX | pinmux | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| GPIO | gpio | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++ + + + +| | FT232RQ / CP2102 | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| CAN | can | normal mode | ++ + + + +| | TCAN332GDCNT | loopback mode | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | ++-----------+------------------------------+--------------------------------+ +| PWM | pwm | All channels | ++-----------+------------------------------+--------------------------------+ + +It's also currently possible to write on the ram console. + +More features will be supported soon. + +Connections and IOs +=================== + +H3ULCB Board +------------ + +Here are official IOs figures from eLinux for H3ULCB board: + +`H3SK top view`_ + +`H3SK bottom view`_ + +Kingfisher Infotainment daughter board +-------------------------------------- + +When connected to Kingfisher Infotainment board through COMExpress connector, the board is exposing much more IOs. + +Here are official IOs figures from eLinux for Kingfisher Infotainment board: + +`Kingfisher top view`_ + +`Kingfisher bottom view`_ + +GPIO +---- + +By running Zephyr on H3ULCB, the software readable push button 'SW3' can be used as input, and the software controllable LED 'LED5' can be used as output. + +UART +---- + +H3ULCB board is providing two serial ports, only one is commonly available on the board, however, the second one can be made available either by welding components or by plugging the board on a Kingfisher Infotainment daughter board. + +Here is information about these serial ports: + ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| Physical Interface | Physical Location | Software Interface | Converter | Further Information | ++====================+===================+====================+===========+======================================+ +| CN12 DEBUG SERIAL | ULCB Board | SCIF2 | FT232RQ | Used by U-BOOT & Linux | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN10 DEBUG SERIAL | ULCB Board | SCIF1 | CP2102 | Non-welded | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ +| CN04 DEBUG SERIAL | Kingfisher | SCIF1 | | Secondary UART // Through ComExpress | ++--------------------+-------------------+--------------------+-----------+--------------------------------------+ + +.. note:: The Zephyr console output is assigned to SCIF1 (commonly used on Kingfisher daughter board) with settings 115200 8N1 without hardware flow control by default. + +Here is CN04 UART interface pinout (depending on your Kingfisher board version): + ++--------+----------+----------+ +| Signal | Pin KF03 | Pin KF04 | ++========+==========+==========+ +| RXD | 3 | 4 | ++--------+----------+----------+ +| TXD | 5 | 2 | ++--------+----------+----------+ +| RTS | 4 | 1 | ++--------+----------+----------+ +| CTS | 6 | 3 | ++--------+----------+----------+ +| GND | 9 | 6 | ++--------+----------+----------+ + +CAN +--- + +H3ULCB board provides two CAN interfaces. Both interfaces are available on the Kingfisher daughter board. + ++--------------------+--------------------+--------------+ +| Physical Interface | Software Interface | Transceiver | ++====================+====================+==============+ +| CN17 | CAN0 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ +| CN18 | CAN1 | TCAN332GDCNT | ++--------------------+--------------------+--------------+ + +.. note:: Interfaces are set to 125 kbit/s by default. + +The following table lists CAN physical interfaces pinout: + ++-----+--------+ +| Pin | Signal | ++=====+========+ +| 1 | CANH | ++-----+--------+ +| 2 | CANL | ++-----+--------+ +| 3 | GND | ++-----+--------+ + +I2C +--- + +H3ULCB board provides two I2C buses. Unfortunately direct access to these buses is not available through connectors. + +I2C is mainly used to manage and power on multiple of onboard chips on the H3ULCB and Kingfisher daughter board. + +Embedded I2C devices and I/O expanders are not yet supported. The current I2C support therefore does not make any devices available to the user at this time. + +PWM +--- + +ULCB boards provide one PWM controller with a maximum of 7 channels [0..6]. H3ULCB does provide the pwm0 from test pin CP8 only. + +When plugged on a Kingfisher daughter board, pwm4 channel is available on CN7 LVDS connector. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected with a SICA20I2P adapter to CN3 on H3ULCB. + +.. note:: + See `eLinux Kingfisher page`_ "Known issues" section if you encounter problem with JTAG. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN04 of your Kingfisher daughter board. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_h3ulcb/r8a77951/r7`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_h3ulcb/r8a77951/r7 + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_h3ulcb + +References +********** + +- `Renesas R-Car Starter Kit website`_ +- `Renesas R-Car H3 chip`_ +- `eLinux H3SK page`_ +- `eLinux Kingfisher page`_ + +.. _Renesas R-Car Starter Kit website: + https://www.renesas.com/br/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-m3-starter-kit + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _eLinux H3SK page: + https://elinux.org/R-Car/Boards/H3SK + +.. _H3SK top view: + https://elinux.org/images/1/1f/R-Car-H3-topview.jpg + +.. _H3SK bottom view: + https://elinux.org/images/c/c2/R-Car-H3-bottomview.jpg + +.. _eLinux Kingfisher page: + https://elinux.org/R-Car/Boards/Kingfisher + +.. _Kingfisher top view: + https://elinux.org/images/0/08/Kfisher_top_specs.png + +.. _Kingfisher bottom view: + https://elinux.org/images/0/06/Kfisher_bot_specs.png + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57-pinctrl.dtsi b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi similarity index 100% rename from boards/arm64/rcar_h3ulcb_ca57/rcar_h3ulcb_ca57-pinctrl.dtsi rename to boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts new file mode 100644 index 00000000000000..5a2bef11c82bd0 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include +#include "rcar_h3ulcb_r8a77951_a57-pinctrl.dtsi" + +/ { + model = "H3ULCB CA57"; + + chosen { + zephyr,sram = &ram; + zephyr,console = &scif2; + zephyr,shell-uart = &scif2; + }; + + ram: memory@48000000 { + device_type = "mmio-sram"; + reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml new file mode 100644 index 00000000000000..13d59c78801bc3 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57.yaml @@ -0,0 +1,17 @@ +identifier: rcar_h3ulcb/r8a77951/a57 +name: Renesas H3ULCB based on r8a77951 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 512 +supported: + - clock_control + - uart +testing: + ignore_tags: + - net + - bluetooth + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig new file mode 100644 index 00000000000000..802c04ef5eacb6 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_a57_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 +CONFIG_XIP=n + +CONFIG_MAX_XLAT_TABLES=24 +CONFIG_ARMV8_A_NS=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable clock control +CONFIG_CLOCK_CONTROL=y diff --git a/boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi similarity index 100% rename from boards/arm/rcar_h3ulcb/rcar_h3ulcb_cr7-pinctrl.dtsi rename to boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts new file mode 100644 index 00000000000000..a5a23e779d819f --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.dts @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021 IoT.bzh + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include "rcar_h3ulcb_r8a77951_r7-pinctrl.dtsi" +#include + +/ { + model = "Renesas h3ulcb board"; + compatible = "renesas,h3ulcb-cr7"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &scif1; + zephyr,shell-uart = &scif1; + zephyr,canbus = &can0; + }; + + leds { + compatible = "gpio-leds"; + user_led: led_5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: sw3 { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + label = "User switch"; + zephyr,code = ; + }; + }; + + aliases { + pwm-0 = &pwm0; + led0 = &user_led; + sw0 = &user_button; + }; +}; + +&cmt0 { + status = "okay"; + clock-frequency = <32000>; +}; + +&gpio6 { + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm0_default>; + pinctrl-names = "default"; +}; + +&can0 { + pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; + bus-speed = <125000>; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml new file mode 100644 index 00000000000000..30e9cfb1f180ef --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7.yaml @@ -0,0 +1,17 @@ +identifier: rcar_h3ulcb/r8a77951/r7 +name: Cortex r7 for Renesas H3ULCB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - i2c + - can + - gpio + - clock_control + - uart +testing: + ignore_tags: + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7_defconfig b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7_defconfig new file mode 100644 index 00000000000000..b70c8f29e22ec2 --- /dev/null +++ b/boards/renesas/rcar_h3ulcb/rcar_h3ulcb_r8a77951_r7_defconfig @@ -0,0 +1,10 @@ +CONFIG_CLOCK_CONTROL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 +CONFIG_CONSOLE=y +CONFIG_RAM_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0 +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/renesas/rcar_salvator_x/Kconfig.rcar_salvator_x b/boards/renesas/rcar_salvator_x/Kconfig.rcar_salvator_x new file mode 100644 index 00000000000000..eac2470dc3e002 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/Kconfig.rcar_salvator_x @@ -0,0 +1,5 @@ +# Copyright (c) 2022 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_SALVATOR_X + select SOC_R8A77951_R7 diff --git a/boards/arm/rcar_h3_salvatorx/board.cmake b/boards/renesas/rcar_salvator_x/board.cmake similarity index 100% rename from boards/arm/rcar_h3_salvatorx/board.cmake rename to boards/renesas/rcar_salvator_x/board.cmake diff --git a/boards/renesas/rcar_salvator_x/board.yml b/boards/renesas/rcar_salvator_x/board.yml new file mode 100644 index 00000000000000..b85c3aebe67af4 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_salvator_x + vendor: renesas + socs: + - name: r8a77951 diff --git a/boards/arm/rcar_h3_salvatorx/doc/img/r-car-h3-salvator-x-connections.jpg b/boards/renesas/rcar_salvator_x/doc/img/r-car-h3-salvator-x-connections.jpg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/doc/img/r-car-h3-salvator-x-connections.jpg rename to boards/renesas/rcar_salvator_x/doc/img/r-car-h3-salvator-x-connections.jpg diff --git a/boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_features.jpg b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_features.jpg rename to boards/renesas/rcar_salvator_x/doc/img/rcar_h3_features.jpg diff --git a/boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_salvatorx.jpg b/boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/doc/img/rcar_h3_salvatorx.jpg rename to boards/renesas/rcar_salvator_x/doc/img/rcar_h3_salvatorx.jpg diff --git a/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst new file mode 100644 index 00000000000000..e95049a42c4303 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/doc/rcar_salvator_x.rst @@ -0,0 +1,183 @@ +.. _rcar_h3_salvatorx_boards: + +Renesas R-Car H3 Salvator-X +########################### + +Overview +******** +- The H3 Salvator-X board is designed for evaluating the features and performance + of the R-CAR H3 device from Renesas Electronics and it is also used for developing + and evaluating application software for these R-CAR H3. + +- The H3 Salvator-X, based on the R-CAR H3 SIP, comes with LPDDR4 @4GB in 2-channel, + each 64-bit wide+Hyperflash @64MB, CSI2 interfaces and several communication interfaces + like USB, Ethernet, HDMI and can work standalone or can be adapted to other boards, + via 440pin connector on bottom side. + +.. figure:: img/rcar_h3_salvatorx.jpg + :align: center + :alt: R-Car Salvator-X kit + +More information about the board can be found at `Renesas R-Car Development Support website`_. + +Hardware +******** + +Hardware capabilities for the H3 Salvator-X for can be found on the `eLinux H3 Salvator-X page`_ +of the board. + +.. figure:: img/rcar_h3_features.jpg + :align: center + :alt: R-Car Salvator-X features + +.. note:: Zephyr will be booted on the CR7 processor provided for RTOS purpose. + +More information about the SoC that equips the board can be found here: + +- `Renesas R-Car H3 chip`_ + +Supported Features +================== + +Here is the current supported features when running Zephyr Project on the R-Car Salvator-X CR7: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| GPIO | gpio | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++ + + + +| | FT232RQ / CP2102 | serial port-interrupt | ++-----------+------------------------------+--------------------------------+ +| CAN | can | normal mode | ++ + + + +| | TCAN332GDCNT | loopback mode | ++-----------+------------------------------+--------------------------------+ +| I2C | i2c | interrupt driven | ++-----------+------------------------------+--------------------------------+ + +It's also currently possible to write on the ram console. + +Connections and IOs +=================== + +.. figure:: img/r-car-h3-salvator-x-connections.jpg + :align: center + :alt: R-Car Salvator-X connections + +GPIO +---- + +By running Zephyr on H3 Salvator-X, the software readable push buttons 'SW20', +'SW21', 'SW22' can be used as input, and the software contollable LEDs 'LED4', +'LED5', 'LED6' can be used as output. + +UART +---- + +Salvator-X board is providing two serial ports: + +- one is for A53/A57 processors +- the other one is for CR7 + +Both ports are converted to USB through CP2102 converters and they are exposed +as follows: + ++-----------+-----------+ +| Connector | Processor | ++===========+===========+ +| CN25 | A53/A57 | ++-----------+-----------+ +| CN26 | CR7 | ++-----------+-----------+ + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Supported Debug Probe +===================== + +The "Olimex ARM-USB-OCD-H" probe is the only officially supported probe. This +probe is supported by OpenOCD that is shipped with the Zephyr SDK. + +The "Olimex ARM-USB-OCD-H" probe needs to be connected to CN1 on Salvator-X. + +Configuring a Console +===================== + +Connect a USB cable from your PC to CN25 and/or CN26 then use the following +settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +First of all, open your serial terminal. + +Applications for the ``rcar_salvator_x`` board configuration can be built +in the usual way (see :ref:`build_an_application` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: flash + +You should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +Debugging +========= + +First of all, open your serial terminal. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: rcar_salvator_x + :goals: debug + +You will then get access to a GDB session for debug. + +By continuing the app, you should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build v2.6.0-rc1 *** + Hello World! rcar_salvator_x + +References +********** + +- `Renesas R-Car H3 chip`_ +- `Renesas R-Car Development Support website`_ +- `eLinux H3 Salvator-X page`_ + +.. _Renesas R-Car H3 chip: + https://www.renesas.com/eu/en/products/automotive-products/automotive-system-chips-socs/r-car-h3-high-end-automotive-system-chip-soc-vehicle-infotainment-and-driving-safety-support + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux H3 Salvator-X page: + https://elinux.org/R-Car/Boards/Salvator-X + +.. _Install a toolchain: + https://docs.zephyrproject.org/latest/getting_started/index.html#install-a-toolchain diff --git a/boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7-pinctrl.dtsi b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7-pinctrl.dtsi similarity index 100% rename from boards/arm/rcar_h3_salvatorx/rcar_h3_salvatorx_cr7-pinctrl.dtsi rename to boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7-pinctrl.dtsi diff --git a/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.dts b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.dts new file mode 100644 index 00000000000000..ce5c046f54ad9e --- /dev/null +++ b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.dts @@ -0,0 +1,93 @@ +/* + * Copyright (c) 2022 BayLibre, SAS + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include "rcar_salvator_x_r8a77951_r7-pinctrl.dtsi" +#include + +/ { + model = "Renesas h3 Salvator-X board"; + compatible = "renesas,h3-salvatorx-cr7"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &scif1; + zephyr,shell-uart = &scif1; + zephyr,canbus = &can0; + }; + + leds { + compatible = "gpio-leds"; + user_led_0: led_4 { + gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + label = "led4"; + }; + user_led_1: led_5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + label = "led5"; + }; + user_led_2: led_6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + label = "led6"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_0: sw20 { + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + label = "sw20"; + zephyr,code = ; + }; + user_button_1: sw21 { + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>; + label = "sw21"; + zephyr,code = ; + }; + user_button_2: sw22 { + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>; + label = "sw22"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &user_led_1; + sw0 = &user_button_0; + }; +}; + +&cmt0 { + status = "okay"; + clock-frequency = <32000>; +}; + +&gpio6 { + status = "okay"; +}; + +&can0 { + pinctrl-0 = <&can0_data_a_tx_default &can0_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; + bus-speed = <125000>; +}; + +&scif1 { + pinctrl-0 = <&scif1_data_a_tx_default &scif1_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; diff --git a/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.yaml b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.yaml new file mode 100644 index 00000000000000..589a0ec03a6177 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7.yaml @@ -0,0 +1,16 @@ +identifier: rcar_salvator_x/r8a77951/r7 +name: Cortex r7 for Renesas H3 Salvator-X +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - i2c + - gpio + - clock_control + - uart +testing: + ignore_tags: + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7_defconfig b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7_defconfig new file mode 100644 index 00000000000000..b70c8f29e22ec2 --- /dev/null +++ b/boards/renesas/rcar_salvator_x/rcar_salvator_x_r8a77951_r7_defconfig @@ -0,0 +1,10 @@ +CONFIG_CLOCK_CONTROL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000 +CONFIG_CONSOLE=y +CONFIG_RAM_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0 +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/rcar_h3_salvatorx/support/openocd.cfg b/boards/renesas/rcar_salvator_x/support/openocd.cfg similarity index 100% rename from boards/arm/rcar_h3_salvatorx/support/openocd.cfg rename to boards/renesas/rcar_salvator_x/support/openocd.cfg diff --git a/boards/renesas/rcar_salvator_xs/Kconfig.defconfig b/boards/renesas/rcar_salvator_xs/Kconfig.defconfig new file mode 100644 index 00000000000000..099fee1ebd8689 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RCAR_SALVATOR_XS + +config BUILD_OUTPUT_BIN + default y + +endif # BOARD_RCAR_SALVATOR_XS diff --git a/boards/renesas/rcar_salvator_xs/Kconfig.rcar_salvator_xs b/boards/renesas/rcar_salvator_xs/Kconfig.rcar_salvator_xs new file mode 100644 index 00000000000000..d18a34388ff391 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/Kconfig.rcar_salvator_xs @@ -0,0 +1,5 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_SALVATOR_XS + select SOC_R8A77961 diff --git a/boards/renesas/rcar_salvator_xs/board.yml b/boards/renesas/rcar_salvator_xs/board.yml new file mode 100644 index 00000000000000..b48fda7ff48c5e --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_salvator_xs + vendor: renesas + socs: + - name: r8a77961 diff --git a/boards/renesas/rcar_salvator_xs/doc/index.rst b/boards/renesas/rcar_salvator_xs/doc/index.rst new file mode 100644 index 00000000000000..a9900158169fc2 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/doc/index.rst @@ -0,0 +1,68 @@ +.. _rcar_salvator_xs: + +R-CAR Salvator XS M3 ARM CA57 (ARMv8) +##################################### + +Overview +******** +The R-Car M3-W is an SOC that features the basic functions for next-generation +car navigation systems. + +Hardware +******** +The R-Car M3-W includes: + +* two 1.5-GHz ARM Cortex-A57 MPCore cores; +* four 1.3-GHz ARM Cortex-A53 MPCore cores, +* memory controller for LPDDR4-3200 with 32 bits x 2 channels; +* 1 channels for HDMI1.4b output and 1 channel for RGB888 output and 1channel for LVDS; +* 2 channels MIPI-CSI2 Video Input, 2 channels digital Video Input; +* USB3.0 x 1ch and USB2.0 x 2ch interfaces; +* 800-MHz ARM Cortex-R7 core; +* two- and three-dimensional graphics engines; +* video processing units; +* sound processing units; +* MediaLB interface; +* SD card host interface; +* USB3.0 and USB2.0 interfaces; +* PCI Express interface; +* CAN interface; +* EtherAVB. + +Supported Features +================== +The Renesas rcar_salvator_xs board configuration supports the following +hardware features: + ++-----------+------------------------------+--------------------------------+ +| Interface | Driver/components | Support level | ++===========+==============================+================================+ +| PINCTRL | pinctrl | | ++-----------+------------------------------+--------------------------------+ +| CLOCK | clock_control | | ++-----------+------------------------------+--------------------------------+ +| UART | uart | serial port-polling | ++-----------+------------------------------+--------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in +:zephyr_file:`boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig` + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +References +********** + +- `Renesas R-Car Development Support website`_ +- `eLinux Salvator-XS page`_ + +.. _Renesas R-Car Development Support website: + https://www.renesas.com/us/en/support/partners/r-car-consortium/r-car-development-support + +.. _eLinux Salvator-XS page: + https://elinux.org/R-Car/Boards/Salvator-XS diff --git a/boards/arm64/rcar_salvator_xs_m3/salvator_xs_m3-pinctrl.dtsi b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi similarity index 100% rename from boards/arm64/rcar_salvator_xs_m3/salvator_xs_m3-pinctrl.dtsi rename to boards/renesas/rcar_salvator_xs/rcar_salvator_xs-pinctrl.dtsi diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts new file mode 100644 index 00000000000000..9c6bfc9a6ebf91 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.dts @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2023 EPAM Systems + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include +#include "rcar_salvator_xs-pinctrl.dtsi" + +/ { + model = "Salvator XS M3"; + + chosen { + zephyr,sram = &ram; + zephyr,console = &scif2; + zephyr,shell-uart = &scif2; + }; + + ram: memory@48000000 { + device_type = "mmio-sram"; + reg = <0x0 0x48000000 0x0 DT_SIZE_M(512)>; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_data_a_tx_default &scif2_data_a_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.yaml b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.yaml new file mode 100644 index 00000000000000..904c5dc58d991a --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs.yaml @@ -0,0 +1,17 @@ +identifier: rcar_salvator_xs +name: Renesas Salvator XS M3 based on r8a77961 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 512 +supported: + - clock_control + - uart +testing: + ignore_tags: + - net + - bluetooth + - isotp +vendor: renesas diff --git a/boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig new file mode 100644 index 00000000000000..802c04ef5eacb6 --- /dev/null +++ b/boards/renesas/rcar_salvator_xs/rcar_salvator_xs_defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +# Cache management +CONFIG_CACHE_MANAGEMENT=y + +# Enable UART driver +CONFIG_SERIAL=y +CONFIG_AARCH64_IMAGE_HEADER=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8300000 +CONFIG_XIP=n + +CONFIG_MAX_XLAT_TABLES=24 +CONFIG_ARMV8_A_NS=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable clock control +CONFIG_CLOCK_CONTROL=y diff --git a/boards/renesas/rcar_spider_s4/Kconfig.rcar_spider_s4 b/boards/renesas/rcar_spider_s4/Kconfig.rcar_spider_s4 new file mode 100644 index 00000000000000..7f6bacf48940c4 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/Kconfig.rcar_spider_s4 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RCAR_SPIDER_S4 + select SOC_R8A779F0 diff --git a/boards/arm/rcar_h3ulcb/board.cmake b/boards/renesas/rcar_spider_s4/board.cmake similarity index 100% rename from boards/arm/rcar_h3ulcb/board.cmake rename to boards/renesas/rcar_spider_s4/board.cmake diff --git a/boards/renesas/rcar_spider_s4/board.yml b/boards/renesas/rcar_spider_s4/board.yml new file mode 100644 index 00000000000000..560ed7f2ae83d9 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/board.yml @@ -0,0 +1,5 @@ +board: + name: rcar_spider_s4 + vendor: renesas + socs: + - name: r8a779f0 diff --git a/boards/arm/rcar_spider/doc/img/rcar_s4_block_diagram.jpg b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg similarity index 100% rename from boards/arm/rcar_spider/doc/img/rcar_s4_block_diagram.jpg rename to boards/renesas/rcar_spider_s4/doc/img/rcar_s4_block_diagram.jpg diff --git a/boards/arm/rcar_spider/doc/img/rcar_s4_spider_full.jpg b/boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg similarity index 100% rename from boards/arm/rcar_spider/doc/img/rcar_s4_spider_full.jpg rename to boards/renesas/rcar_spider_s4/doc/img/rcar_s4_spider_full.jpg diff --git a/boards/arm/rcar_spider/doc/rcar_spider.rst b/boards/renesas/rcar_spider_s4/doc/rcar_spider.rst similarity index 97% rename from boards/arm/rcar_spider/doc/rcar_spider.rst rename to boards/renesas/rcar_spider_s4/doc/rcar_spider.rst index 33deb1f27a8d1b..933c7054130cfb 100644 --- a/boards/arm/rcar_spider/doc/rcar_spider.rst +++ b/boards/renesas/rcar_spider_s4/doc/rcar_spider.rst @@ -141,12 +141,12 @@ Flashing First of all, open your serial terminal. -Applications for the ``rcar_spider_cr52`` board configuration can be built in the +Applications for the ``rcar_spider_s4`` board configuration can be built in the usual way (see :ref:`build_an_application` for more details). .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: rcar_spider_cr52 + :board: rcar_spider_s4 :goals: flash You should see the following message in the terminal: @@ -154,7 +154,7 @@ You should see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_cr52 + Hello World! rcar_spider_s4 Debugging ========= @@ -165,7 +165,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: rcar_spider_cr52 + :board: rcar_spider_s4 :goals: debug You will then get access to a GDB session for debugging. @@ -175,7 +175,7 @@ By continuing the app, you should see the following message in the terminal: .. code-block:: console *** Booting Zephyr OS build v3.3.0-rc2 *** - Hello World! rcar_spider_cr52 + Hello World! rcar_spider_s4 References ********** diff --git a/boards/arm/rcar_spider/rcar_spider_cr52-pinctrl.dtsi b/boards/renesas/rcar_spider_s4/rcar_spider_s4-pinctrl.dtsi similarity index 100% rename from boards/arm/rcar_spider/rcar_spider_cr52-pinctrl.dtsi rename to boards/renesas/rcar_spider_s4/rcar_spider_s4-pinctrl.dtsi diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4.dts b/boards/renesas/rcar_spider_s4/rcar_spider_s4.dts new file mode 100644 index 00000000000000..367c867682da29 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2023 IoT.bzh + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +/dts-v1/; +#include +#include "rcar_spider_s4-pinctrl.dtsi" +#include + +/ { + model = "Renesas Spider board"; + compatible = "renesas,spider-s4"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &scif0; + zephyr,shell-uart = &scif0; + }; + + leds { + compatible = "gpio-leds"; + user_led: led_8 { + gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: sw10 { + gpios = <&gpio4 13 GPIO_ACTIVE_LOW>; + label = "User switch"; + zephyr,code = ; + }; + }; + + aliases { + led0 = &user_led; + sw0 = &user_button; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_data_tx_default &scif0_data_rx_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4.yaml b/boards/renesas/rcar_spider_s4/rcar_spider_s4.yaml new file mode 100644 index 00000000000000..92b98f20d302d1 --- /dev/null +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4.yaml @@ -0,0 +1,11 @@ +identifier: rcar_spider_s4 +name: Cortex r52 for Renesas Spider +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - clock_control + - uart diff --git a/boards/renesas/rcar_spider_s4/rcar_spider_s4_defconfig b/boards/renesas/rcar_spider_s4/rcar_spider_s4_defconfig new file mode 100644 index 00000000000000..0b1a3fb8df8fdb --- /dev/null +++ b/boards/renesas/rcar_spider_s4/rcar_spider_s4_defconfig @@ -0,0 +1,10 @@ +CONFIG_CLOCK_CONTROL=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12500000 +CONFIG_CONSOLE=y +CONFIG_RAM_CONSOLE=y +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0 +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y diff --git a/boards/arm/rcar_spider/support/openocd.cfg b/boards/renesas/rcar_spider_s4/support/openocd.cfg similarity index 100% rename from boards/arm/rcar_spider/support/openocd.cfg rename to boards/renesas/rcar_spider_s4/support/openocd.cfg diff --git a/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit b/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit new file mode 100644 index 00000000000000..83f98b5c90bedd --- /dev/null +++ b/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RZT2M_STARTER_KIT + select SOC_RENESAS_RZT2M diff --git a/boards/arm/rzt2m_starterkit/board.cmake b/boards/renesas/rzt2m_starterkit/board.cmake similarity index 100% rename from boards/arm/rzt2m_starterkit/board.cmake rename to boards/renesas/rzt2m_starterkit/board.cmake diff --git a/boards/renesas/rzt2m_starterkit/board.yml b/boards/renesas/rzt2m_starterkit/board.yml new file mode 100644 index 00000000000000..def32c06cd2a6b --- /dev/null +++ b/boards/renesas/rzt2m_starterkit/board.yml @@ -0,0 +1,5 @@ +board: + name: rzt2m_starter_kit + vendor: renesas + socs: + - name: renesas_rzt2m diff --git a/boards/arm/rzt2m_starterkit/doc/index.rst b/boards/renesas/rzt2m_starterkit/doc/index.rst similarity index 100% rename from boards/arm/rzt2m_starterkit/doc/index.rst rename to boards/renesas/rzt2m_starterkit/doc/index.rst diff --git a/boards/arm/rzt2m_starterkit/doc/rzt2m_starterkit.png b/boards/renesas/rzt2m_starterkit/doc/rzt2m_starterkit.png similarity index 100% rename from boards/arm/rzt2m_starterkit/doc/rzt2m_starterkit.png rename to boards/renesas/rzt2m_starterkit/doc/rzt2m_starterkit.png diff --git a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit.yaml b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit.yaml similarity index 100% rename from boards/arm/rzt2m_starterkit/rzt2m_starter_kit.yaml rename to boards/renesas/rzt2m_starterkit/rzt2m_starter_kit.yaml diff --git a/boards/arm/rzt2m_starterkit/rzt2m_starter_kit.dts b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts similarity index 100% rename from boards/arm/rzt2m_starterkit/rzt2m_starter_kit.dts rename to boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts diff --git a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig new file mode 100644 index 00000000000000..18f0eb4aee7b88 --- /dev/null +++ b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/renode/index.rst b/boards/renode/index.rst new file mode 100644 index 00000000000000..dcad0d00dcfbf2 --- /dev/null +++ b/boards/renode/index.rst @@ -0,0 +1,10 @@ +.. _boards-renode: + +Renode +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/renode/riscv32_virtual/Kconfig.riscv32_virtual b/boards/renode/riscv32_virtual/Kconfig.riscv32_virtual new file mode 100644 index 00000000000000..ead3da9543e57d --- /dev/null +++ b/boards/renode/riscv32_virtual/Kconfig.riscv32_virtual @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RISCV32_VIRTUAL + select SOC_RISCV_VIRTUAL_RENODE diff --git a/boards/riscv/riscv32_virtual/board.cmake b/boards/renode/riscv32_virtual/board.cmake similarity index 100% rename from boards/riscv/riscv32_virtual/board.cmake rename to boards/renode/riscv32_virtual/board.cmake diff --git a/boards/renode/riscv32_virtual/board.yml b/boards/renode/riscv32_virtual/board.yml new file mode 100644 index 00000000000000..b059266009a954 --- /dev/null +++ b/boards/renode/riscv32_virtual/board.yml @@ -0,0 +1,5 @@ +board: + name: riscv32_virtual + vendor: renode + socs: + - name: riscv_virtual_renode diff --git a/boards/riscv/riscv32_virtual/doc/index.rst b/boards/renode/riscv32_virtual/doc/index.rst similarity index 100% rename from boards/riscv/riscv32_virtual/doc/index.rst rename to boards/renode/riscv32_virtual/doc/index.rst diff --git a/boards/riscv/riscv32_virtual/riscv32_virtual.dts b/boards/renode/riscv32_virtual/riscv32_virtual.dts similarity index 100% rename from boards/riscv/riscv32_virtual/riscv32_virtual.dts rename to boards/renode/riscv32_virtual/riscv32_virtual.dts diff --git a/boards/riscv/riscv32_virtual/riscv32_virtual.yaml b/boards/renode/riscv32_virtual/riscv32_virtual.yaml similarity index 100% rename from boards/riscv/riscv32_virtual/riscv32_virtual.yaml rename to boards/renode/riscv32_virtual/riscv32_virtual.yaml diff --git a/boards/riscv/riscv32_virtual/riscv32_virtual_defconfig b/boards/renode/riscv32_virtual/riscv32_virtual_defconfig similarity index 78% rename from boards/riscv/riscv32_virtual/riscv32_virtual_defconfig rename to boards/renode/riscv32_virtual/riscv32_virtual_defconfig index 4dcad0a7ea1040..911302fc640e64 100644 --- a/boards/riscv/riscv32_virtual/riscv32_virtual_defconfig +++ b/boards/renode/riscv32_virtual/riscv32_virtual_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2023 Meta # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_RISCV32_VIRTUAL_RENODE=y -CONFIG_BOARD_RISCV32_VIRTUAL=y CONFIG_CONSOLE=y CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/riscv32_virtual/support/riscv32_virtual.repl b/boards/renode/riscv32_virtual/support/riscv32_virtual.repl similarity index 100% rename from boards/riscv/riscv32_virtual/support/riscv32_virtual.repl rename to boards/renode/riscv32_virtual/support/riscv32_virtual.repl diff --git a/boards/riscv/riscv32_virtual/support/riscv32_virtual.resc b/boards/renode/riscv32_virtual/support/riscv32_virtual.resc similarity index 100% rename from boards/riscv/riscv32_virtual/support/riscv32_virtual.resc rename to boards/renode/riscv32_virtual/support/riscv32_virtual.resc diff --git a/boards/riscv/adp_xc7k_ae350/Kconfig.board b/boards/riscv/adp_xc7k_ae350/Kconfig.board deleted file mode 100644 index 5b58e01fbfdb6d..00000000000000 --- a/boards/riscv/adp_xc7k_ae350/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ADP_XC7K_AE350 - bool "Andes ADP-XC7K AE350 Platform" - depends on SOC_ANDES_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig b/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig deleted file mode 100644 index 7438c2eae72ec1..00000000000000 --- a/boards/riscv/adp_xc7k_ae350/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "adp_xc7k_ae350" if BOARD_ADP_XC7K_AE350 diff --git a/boards/riscv/adp_xc7k_ae350/doc/index.rst b/boards/riscv/adp_xc7k_ae350/doc/index.rst deleted file mode 100644 index c12c04cabc40d9..00000000000000 --- a/boards/riscv/adp_xc7k_ae350/doc/index.rst +++ /dev/null @@ -1,334 +0,0 @@ -.. _adp_xc7k_ae350: - -Andes ADP-XC7K AE350 -#################### - -Overview -******** - -ADP-XC7K AE350 board is for AndeShape AE350 platform on ADP-XC7K series -FPGA-based development boards. - -ADP-XC7K series are FPGA-based development and prototyping boards for evaluation of -variety of AndesCore processors and AndeShape SoC platform IPs. -AE350 is a RISC-V platform which can integrate AndesCore CPUs with a collection -of fundamental peripheral IPs. - -1st figure shows the green PCB is ADP-XC7K160 and 2nd figure shows the red PCB is ADP-XC7K410. - -.. image:: img/adp_xc7k160.jpg - :align: center - :alt: ADP-XC7K160 - -.. image:: img/adp_xc7k410.jpg - :align: center - :alt: ADP-XC7K410 - -More information can be found on `ADP-XC7K160/410`_ and `AndeShape AE350`_ websites. - -Hardware -******** - -The ADP-XC7K AE350 platform integrates 1 ~ 4 cores 32/64-bit 60MHz RISC-V CPUs, DSP, -1GB RAM, Cache, SPI flash memory, ethernet controller and other peripherals. - -The ADP-XC7K AE350 platform provides following hardware components: - -- 1 ~ 4 cores 32/64-bit 60MHz AndeStar v5 RISC-V CPUs -- 1GB on-board SDRAM -- 2MB SPI flash memory (1MB can be used for XIP) -- UART -- I2C -- SPI -- GPIO -- PWM -- DMA -- 10/100 Ethernet RJ45 port -- LCD module connector -- 16KB I2C EEPROM -- SD memory card slot -- MIC-in, Line-in, and Line-out with AC97 audio codec - -Supported Features -================== - -The ``adp_xc7k_ae350`` board configuration supports the following hardware features: - -+----------------+------------+----------------------+ -| Interface | Controller | Driver/Component | -+================+============+======================+ -| PLIC | on-chip | interrupt_controller | -+----------------+------------+----------------------+ -| RISC-V Machine | on-chip | timer | -| Timer | | | -+----------------+------------+----------------------+ -| GPIO | on-chip | gpio | -+----------------+------------+----------------------+ -| UART | on-chip | serial | -+----------------+------------+----------------------+ -| COUNTER | on-chip | counter | -+----------------+------------+----------------------+ -| SPI | on-chip | spi | -+----------------+------------+----------------------+ -| I2C | on-chip | i2c | -+----------------+------------+----------------------+ -| EEPROM | on-chip | eeprom | -+----------------+------------+----------------------+ -| FLASH | on-chip | flash | -+----------------+------------+----------------------+ -| HWINFO | on-chip | syscon | -+----------------+------------+----------------------+ -| MAILBOX | on-chip | mbox | -+----------------+------------+----------------------+ -| DMA | on-chip | dma | -+----------------+------------+----------------------+ -| WATCHDOG | on-chip | wdt | -+----------------+------------+----------------------+ - -Other hardware features are not supported yet. - -Connections and IOs -=================== - -The ADP-XC7K AE350 platform has 1 GPIO controller. It providing 32 bits of IO. -It is responsible for pin input/output, pull-up, etc. - -Mapping from GPIO controller to the ADP-XC7K board pins: - -+--------------------+--------------------+ -| GPIO controller | Usage / Board pins | -+====================+====================+ -| **Push Buttons** | | -+--------------------+--------------------+ -| GPIO.0 | SW1 | -+--------------------+--------------------+ -| GPIO.1 | SW2 | -+--------------------+--------------------+ -| GPIO.2 | SW3 | -+--------------------+--------------------+ -| GPIO.3 | SW4 | -+--------------------+--------------------+ -| GPIO.4 | SW5 | -+--------------------+--------------------+ -| GPIO.5 | SW6 | -+--------------------+--------------------+ -| GPIO.6 | SW7 | -+--------------------+--------------------+ -| **7-Segment LED1** | | -+--------------------+--------------------+ -| GPIO.16 | 7SEG1.A | -+--------------------+--------------------+ -| GPIO.17 | 7SEG1.B | -+--------------------+--------------------+ -| GPIO.18 | 7SEG1.C | -+--------------------+--------------------+ -| GPIO.19 | 7SEG1.D | -+--------------------+--------------------+ -| GPIO.20 | 7SEG1.E | -+--------------------+--------------------+ -| GPIO.21 | 7SEG1.F | -+--------------------+--------------------+ -| GPIO.22 | 7SEG1.G | -+--------------------+--------------------+ -| GPIO.23 | 7SEG1.DP | -+--------------------+--------------------+ -| **7-Segment LED2** | | -+--------------------+--------------------+ -| GPIO.24 | 7SEG2.A | -+--------------------+--------------------+ -| GPIO.25 | 7SEG2.B | -+--------------------+--------------------+ -| GPIO.26 | 7SEG2.C | -+--------------------+--------------------+ -| GPIO.27 | 7SEG2.D | -+--------------------+--------------------+ -| GPIO.28 | 7SEG2.E | -+--------------------+--------------------+ -| GPIO.29 | 7SEG2.F | -+--------------------+--------------------+ -| GPIO.30 | 7SEG2.G | -+--------------------+--------------------+ -| GPIO.31 | 7SEG2.DP | -+--------------------+--------------------+ -| **GPIO pins** | | -+--------------------+--------------------+ -| GPIO.7 | IDE_CON1.4 | -+--------------------+--------------------+ -| GPIO.8 | IDE_CON1.6 | -+--------------------+--------------------+ -| GPIO.9 | IDE_CON1.8 | -+--------------------+--------------------+ -| GPIO.10 | IDE_CON1.10 | -+--------------------+--------------------+ -| GPIO.11 | IDE_CON1.11 | -+--------------------+--------------------+ -| GPIO.12 | IDE_CON1.12 | -+--------------------+--------------------+ -| GPIO.13 | IDE_CON1.13 | -+--------------------+--------------------+ -| GPIO.14 | IDE_CON1.14 | -+--------------------+--------------------+ -| GPIO.15 | IDE_CON1.15 | -+--------------------+--------------------+ - -Other peripheral mapping are listed below: - -+-------------+---------------------------------+ -| Peripherals | Usage / Board pins | -+=============+=================================+ -| SPI_1 | internal connected to SPI Flash | -+-------------+---------------------------------+ -| SPI_2_CS | IDE_CON1.37 | -+-------------+---------------------------------+ -| SPI_2_MOSI | IDE_CON1.36 | -+-------------+---------------------------------+ -| SPI_2_MISO | IDE_CON1.38 | -+-------------+---------------------------------+ -| SPI_2_SCLK | IDE_CON1.35 | -+-------------+---------------------------------+ -| I2C_SDA | J27.1 | -+-------------+---------------------------------+ -| I2C_SCL | J27.2 | -+-------------+---------------------------------+ - -System Clock ------------- - -The ADP-XC7K AE350 platform has 60MHz core clock. - -Serial Port ------------ - -The ADP-XC7K AE350 platform has 2 UARTs. -The Zephyr console output is by default assigned to UART2 and the default -settings are 115200 8N1. - -Programming and debugging -************************* - -For debugging zephyr applications or burning them into a flash, you will need to -connect Andes ICE from host computer to ADP-XC7K board and execute the -Andes ICE management software, ICEman, on this host computer. - -Connecting Andes ICE (AICE) -=========================== - -AICE is used for flashing and debugging the board. Please connect AICE to both -ADP-XC7K board and the host computer as shown in the figure. - -.. image:: img/connect_aice.jpg - :align: center - :alt: Connect AICE - -More information can be found on `AICE-MINI+`_, `AICE-MICRO`_ website - -Building -======== - -You can build applications in the usual way. Here is an example for -the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: adp_xc7k_ae350 - :goals: build - -Flashing -======== - -Before flashing, you have to download ICEman (``ice.zip``) from the -`Andes Development Kit`_. -If you want to use XIP mode (``CONFIG_XIP=y``), you also need to download -the flash burner (``flash.zip``). - -At first, you should run ICEman when flashing and debugging program. - -.. code-block:: console - - # Enable execute file permission of ICEman - chmod a+x ./ICEman - - # Running the ICEman server - sudo ./ICEman -Z v5 - -.. note:: - - To run ICEman commands as a normal user, you will need to install the - :file:`70-ndsusb-v1.rules` udev rules file (usually by placing it in - :file:`/etc/udev/rules.d`, then unplugging and plugging the - AICE adapter in again via USB.). - -If ``CONFIG_XIP=n``, you can load the program (``zephyr.elf``) into RAM directly -and execute it. - -.. code-block:: console - - # Check the ICEman server is running - # Load the program into RAM and execute it - riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf - (gdb) target remote :1111 - (gdb) monitor reset halt - (gdb) load - (gdb) quit - -If ``CONFIG_XIP=y``, you need to burn the program (``zephyr.bin``) into flash memory -and execute it. - -.. code-block:: console - - # Check the ICEman server is running - # Burn the program into flash and execute it - /bin/target_burn_frontend \ - -P 4444 --unlock --verify --image=build/zephyr/zephyr.bin \ - --algorithm-bin=/target_bin/target_SPI_v5_[32|64].bin - - # Note: - # 1. Assume the flash burner is downloaded to directory - # 2. For algorithm-bin file, use target_SPI_v5_32.bin in RV32 platform and - # use target_SPI_v5_64.bin in RV64 platform - -Open a serial terminal with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -you should see the following message in the terminal: - -.. code-block:: console - - ***** Booting Zephyr OS v2.4.0 ***** - Hello World! adp_xc7k_ae350 - -Debugging -========= - -.. code-block:: console - - # Check the ICEman server is running - # Load and debug program - ./riscv64-zephyr-elf-gdb build/zephyr/zephyr.elf - (gdb) target remote :1111 - (gdb) monitor reset halt - (gdb) load - -If ``CONFIG_XIP=y``, please follow the flashing section to burn the program into -flash memory first. -Then, you can use GDB to debug program by above commands but do NOT execute ``load`` -command since the program has been placed in the flash memory. - -References -********** - -.. target-notes:: - -.. _ADP-XC7K160/410: http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/ - -.. _AndeShape AE350: http://www.andestech.com/en/products-solutions/andeshape-platforms/ae350-axi-based-platform-pre-integrated-with-n25f-nx25f-a25-ax25/ - -.. _AICE-MINI+: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-mini-plus/ - -.. _AICE-MICRO: http://www.andestech.com/en/products-solutions/andeshape-platforms/aice-micro/ - -.. _Andes Development Kit: https://github.com/andestech/Andes-Development-Kit/releases diff --git a/boards/riscv/beaglev_fire/Kconfig.board b/boards/riscv/beaglev_fire/Kconfig.board deleted file mode 100644 index 55b59d4ac922a6..00000000000000 --- a/boards/riscv/beaglev_fire/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_BEAGLEV_FIRE - bool "Beagleboard BeagleV-Fire" - depends on SOC_POLARFIRE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/riscv/beaglev_fire/Kconfig.defconfig b/boards/riscv/beaglev_fire/Kconfig.defconfig deleted file mode 100644 index df89660bcb65dc..00000000000000 --- a/boards/riscv/beaglev_fire/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "beaglev_fire" - depends on BOARD_BEAGLEV_FIRE diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.board b/boards/riscv/esp32c3_devkitm/Kconfig.board deleted file mode 100644 index 51f0f3957df987..00000000000000 --- a/boards/riscv/esp32c3_devkitm/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32C3 devkitm board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32C3_DEVKITM - bool "ESP32C3 Devkit-M Board" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_MINI_N4 -endchoice diff --git a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig b/boards/riscv/esp32c3_devkitm/Kconfig.defconfig deleted file mode 100644 index 922368f923be24..00000000000000 --- a/boards/riscv/esp32c3_devkitm/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# ESP32C3 devkitm board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32c3_devkitm" - depends on BOARD_ESP32C3_DEVKITM - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/esp32c3_devkitm/doc/index.rst b/boards/riscv/esp32c3_devkitm/doc/index.rst deleted file mode 100644 index 26f1521e0874fa..00000000000000 --- a/boards/riscv/esp32c3_devkitm/doc/index.rst +++ /dev/null @@ -1,241 +0,0 @@ -.. _esp32c3_devkitm: - -ESP32-C3 -######## - -Overview -******** - -ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, -based on the open-source RISC-V architecture. It strikes the right balance of power, -I/O capabilities and security, thus offering the optimal cost-effective -solution for connected devices. -The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, -but it also facilitates a variety of use-cases based on dual connectivity. [1]_ - -The features include the following: - -- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz -- 400 KB of internal RAM -- 802.11b/g/n/e/i -- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh -- Various peripherals: - - - 12-bit ADC with up to 6 channels - - TWAI compatible with CAN bus 2.0 - - Temperature sensor - - 3x SPI - - 1x I2S - - 1x I2C - - 2x UART - - LED PWM with up to 6 channels - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - -Supported Features -================== - -Current Zephyr's ESP32-C3-Devkitm board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32c3_devkitm - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: build - -The usual ``flash`` target will work with the ``esp32c3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32c3_devkitm - -Debugging -********* - -As with much custom hardware, the ESP32-C3 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_devkitm - :goals: debug - -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-c3 -.. _ESP32C3 Devkitm User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32c3/hw-reference/esp32c3/user-guide-devkitm-1.html -.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig deleted file mode 100644 index 1ca521d9d95915..00000000000000 --- a/boards/riscv/esp32c3_devkitm/esp32c3_devkitm_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32C3_DEVKITM=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/Kconfig.board b/boards/riscv/esp32c3_luatos_core/Kconfig.board deleted file mode 100644 index ac7b48a7a3678d..00000000000000 --- a/boards/riscv/esp32c3_luatos_core/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32C3_LUATOS_CORE - bool "luatos ESP32C3-CORE Board" - depends on SOC_SERIES_ESP32C3 - -config BOARD_ESP32C3_LUATOS_CORE_USB - bool "luatos ESP32C3-CORE Board without UART chip" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_MINI_N4 -endchoice diff --git a/boards/riscv/esp32c3_luatos_core/Kconfig.defconfig b/boards/riscv/esp32c3_luatos_core/Kconfig.defconfig deleted file mode 100644 index 82e3a5a0c94893..00000000000000 --- a/boards/riscv/esp32c3_luatos_core/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# ESP32C3 core board configuration - -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32c3_luatos_core" - depends on BOARD_ESP32C3_LUATOS_CORE || BOARD_ESP32C3_LUATOS_CORE_USB - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/esp32c3_luatos_core/doc/index.rst b/boards/riscv/esp32c3_luatos_core/doc/index.rst deleted file mode 100644 index fae8e2eb178b4c..00000000000000 --- a/boards/riscv/esp32c3_luatos_core/doc/index.rst +++ /dev/null @@ -1,259 +0,0 @@ -.. _esp32c3_luatos_core: - -ESP32C3_LUATOS_CORE -################### - -Overview -******** - -ESP32-C3 is a single-core Wi-Fi and Bluetooth 5 (LE) microcontroller SoC, -based on the open-source RISC-V architecture. It strikes the right balance of power, -I/O capabilities and security, thus offering the optimal cost-effective -solution for connected devices. -The availability of Wi-Fi and Bluetooth 5 (LE) connectivity not only makes the device configuration easy, -but it also facilitates a variety of use-cases based on dual connectivity. [1]_ - -The features include the following: - -- 32-bit core RISC-V microcontroller with a maximum clock speed of 160 MHz -- 400 KB of internal RAM -- 802.11b/g/n/e/i -- A Bluetooth LE subsystem that supports features of Bluetooth 5 and Bluetooth Mesh -- Various peripherals: - - - 12-bit ADC with up to 6 channels - - TWAI compatible with CAN bus 2.0 - - Temperature sensor - - 3x SPI - - 1x I2S - - 1x I2C - - 2x UART - - LED PWM with up to 6 channels - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - -There are two version hardware of this board. The difference between them is the ch343 chip. - -1. USB-C connect to UART over CH343 chip(esp32c3_luatos_core) - -.. image:: img/esp32c3_luatos_core.jpg - :align: center - :alt: esp32c3_luatos_core - -2. USB-C connect to esp32 chip directly(esp32c3_luatos_core_usb) - -.. image:: img/esp32c3_luatos_core_usb.jpg - :align: center - :alt: esp32c3_luatos_core_usb - -Supported Features -================== - -Current Zephyr's ESP32C3_LUATOS_CORE board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -.. image:: img/esp32c3_luatos_core_pinfunc.jpg - :align: center - :alt: esp32c3_luatos_core_pinfunc - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32c3_luatos_core - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: build - -The usual ``flash`` target will work with the ``esp32c3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32c3_luatos_core - -Debugging -********* - -As with much custom hardware, the ESP32-C3 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32c3_luatos_core - :goals: debug - -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-c3 -.. _ESP32C3 Core Website: https://wiki.luatos.com/chips/esp32c3/board.html -.. _ESP32C3 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _ESP32C3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_defconfig b/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_defconfig deleted file mode 100644 index d3f8458a2ef1f4..00000000000000 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32C3_LUATOS_CORE=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.yaml b/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.yaml deleted file mode 100644 index ed8f1b2bc0a2a4..00000000000000 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32c3_luatos_core_usb -name: ESP32C3 LuatOS Core USB -type: mcu -arch: riscv -toolchain: - - zephyr -supported: - - adc - - gpio - - i2c - - watchdog - - uart - - dma - - pwm - - spi - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb_defconfig b/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb_defconfig deleted file mode 100644 index 0a441dde0bbc55..00000000000000 --- a/boards/riscv/esp32c3_luatos_core/esp32c3_luatos_core_usb_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32C3_LUATOS_CORE_USB=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/gd32vf103c_starter/Kconfig.board b/boards/riscv/gd32vf103c_starter/Kconfig.board deleted file mode 100644 index 747958bef1a61c..00000000000000 --- a/boards/riscv/gd32vf103c_starter/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32VF103C_STARTER - bool "GigaDevice GD32VF103C-STARTER" - depends on SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103c_starter/Kconfig.defconfig b/boards/riscv/gd32vf103c_starter/Kconfig.defconfig deleted file mode 100644 index 09c16cab05598b..00000000000000 --- a/boards/riscv/gd32vf103c_starter/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32VF103C_STARTER - -config BOARD - default "gd32vf103c_starter" - -endif # BOARD_GD32VF103C_STARTER diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter_defconfig b/boards/riscv/gd32vf103c_starter/gd32vf103c_starter_defconfig deleted file mode 100644 index 056959e18fb962..00000000000000 --- a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_GD32VF103C_STARTER=y - -CONFIG_GD32_HXTAL_8MHZ=y diff --git a/boards/riscv/gd32vf103v_eval/Kconfig.board b/boards/riscv/gd32vf103v_eval/Kconfig.board deleted file mode 100644 index 1893adae071f92..00000000000000 --- a/boards/riscv/gd32vf103v_eval/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GD32VF103V_EVAL - bool "GigaDevice GD32VF103V-EVAL" - depends on SOC_GD32VF103 diff --git a/boards/riscv/gd32vf103v_eval/Kconfig.defconfig b/boards/riscv/gd32vf103v_eval/Kconfig.defconfig deleted file mode 100644 index e3c8b4150f7207..00000000000000 --- a/boards/riscv/gd32vf103v_eval/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GD32VF103V_EVAL - -config BOARD - default "gd32vf103v_eval" - -endif # BOARD_GD32VF103V_EVAL diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval_defconfig b/boards/riscv/gd32vf103v_eval/gd32vf103v_eval_defconfig deleted file mode 100644 index 078392eed2a07d..00000000000000 --- a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_GD32VF103V_EVAL=y - -CONFIG_GD32_HXTAL_8MHZ=y - -CONFIG_GPIO=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/riscv/hifive1/Kconfig.board b/boards/riscv/hifive1/Kconfig.board deleted file mode 100644 index d2f40472f244d9..00000000000000 --- a/boards/riscv/hifive1/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE1 - bool "HiFive1 target" - depends on SOC_SIFIVE_FREEDOM_E340 diff --git a/boards/riscv/hifive1/Kconfig.defconfig b/boards/riscv/hifive1/Kconfig.defconfig deleted file mode 100644 index 33356cb4da795e..00000000000000 --- a/boards/riscv/hifive1/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE1 - -config BOARD - default "hifive1" - -config SYS_CLOCK_TICKS_PER_SEC - default 128 - -endif diff --git a/boards/riscv/hifive1/board.cmake b/boards/riscv/hifive1/board.cmake deleted file mode 100644 index 8d5f84761452fa..00000000000000 --- a/boards/riscv/hifive1/board.cmake +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS renode qemu) -set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/hifive1.resc) -set(RENODE_UART sysbus.uart0) - -set(QEMU_binary_suffix riscv32) -set(QEMU_CPU_TYPE_${ARCH} riscv32) - -set(QEMU_FLAGS_${ARCH} - -nographic - -machine sifive_e - ) - -board_set_flasher_ifnset(hifive1) -board_finalize_runner_args(hifive1) - -board_runner_args(openocd --cmd-load "hifive1-load") -board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt") -board_runner_args(openocd --cmd-post-verify "hifive1-post-verify") - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/hifive1/doc/index.rst b/boards/riscv/hifive1/doc/index.rst deleted file mode 100644 index 9482a6ad0d4b71..00000000000000 --- a/boards/riscv/hifive1/doc/index.rst +++ /dev/null @@ -1,62 +0,0 @@ -.. _hifive1: - -SiFive HiFive1 -############## - -Overview -******** - -The HiFive1 is an Arduino-compatible development board with -an FE310 RISC-V SoC. -More information can be found on -`SiFive's website `_. - -.. image:: img/hifive1.jpg - :align: center - :alt: SiFive HiFive1 board - -Programming and debugging -************************* - -Building -======== - -Applications for the ``hifive1`` board configuration can be built as usual -(see :ref:`build_an_application`) using the corresponding board name: - -.. zephyr-app-commands:: - :board: hifive1 - :goals: build - -Flashing -======== - -In order to upload the application to the device, you'll need OpenOCD with -RISC-V support. Download the tarball for your OS from the `SiFive website -`_ and extract it. - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can -overwrite that behavior by adding the -``-DOPENOCD=`` parameter when building: - -.. zephyr-app-commands:: - :board: hifive1 - :goals: build - :gen-args: -DOPENOCD= - -When using a custom toolchain it should be enough to have the downloaded -version of the binary in your ``PATH``. - -Now you can flash the application as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details): - -.. code-block:: console - - ninja flash - -Depending on your OS you might have to run the flash command as superuser. - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive1/hifive1_defconfig b/boards/riscv/hifive1/hifive1_defconfig deleted file mode 100644 index 8e4e8e21c1a243..00000000000000 --- a/boards/riscv/hifive1/hifive1_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_HIFIVE1=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/riscv/hifive1_revb/Kconfig.board b/boards/riscv/hifive1_revb/Kconfig.board deleted file mode 100644 index b0bf1edd156bb1..00000000000000 --- a/boards/riscv/hifive1_revb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE1_REVB - bool "HiFive1 Rev B target" - depends on SOC_SIFIVE_FREEDOM_E340 diff --git a/boards/riscv/hifive1_revb/Kconfig.defconfig b/boards/riscv/hifive1_revb/Kconfig.defconfig deleted file mode 100644 index 22b33b3d960b79..00000000000000 --- a/boards/riscv/hifive1_revb/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE1_REVB - -config BOARD - default "hifive1_revb" - -config HAS_FLASH_LOAD_OFFSET - default y - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) - -config FLASH_LOAD_OFFSET - default 0x0 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 - -endif diff --git a/boards/riscv/hifive1_revb/board.cmake b/boards/riscv/hifive1_revb/board.cmake deleted file mode 100644 index f339e968e86256..00000000000000 --- a/boards/riscv/hifive1_revb/board.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=FE310") -board_runner_args(jlink "--iface=JTAG") -board_runner_args(jlink "--speed=4000") -board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") -board_runner_args(jlink "--tool-opt=-autoconnect 1") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/riscv/hifive1_revb/doc/index.rst b/boards/riscv/hifive1_revb/doc/index.rst deleted file mode 100644 index 843192fe2cc192..00000000000000 --- a/boards/riscv/hifive1_revb/doc/index.rst +++ /dev/null @@ -1,49 +0,0 @@ -.. _hifive1_revb: - -SiFive HiFive1 Rev B -#################### - -Overview -******** - -The HiFive1 Rev B is an Arduino-compatible development board with -a SiFive FE310-G002 RISC-V SoC. - -.. image:: img/hifive1_revb.jpg - :align: center - :alt: SiFive HiFive1 Rev B board - -Programming and debugging -************************* - -Building -======== - -Applications for the ``hifive1_revb`` board configuration can be built as usual -(see :ref:`build_an_application`) using the corresponding board name: - -.. zephyr-app-commands:: - :board: hifive1_revb - :goals: build - -Flashing -======== - -The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and -debug the board, you'll need to install the -`Segger J-Link Software and Documentation Pack -`_ -and choose version V6.46a or later (Downloads for Windows, Linux, and macOS are -available). - -With the Segger J-Link Software installed, you can flash the application as usual -(see :ref:`build_an_application` and :ref:`application_run` for more details): - -.. code-block:: console - - west flash - -Debugging -========= - -Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi b/boards/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi deleted file mode 100644 index 093cdcb6a412f5..00000000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb-pinctrl.dtsi +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2022 Antmicro - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include - -&pinctrl { - /* UART0 */ - uart0_rx_default: uart0_rx_default { - pinmux = <16 SIFIVE_PINMUX_IOF0>; - }; - uart0_tx_default: uart0_tx_default { - pinmux = <17 SIFIVE_PINMUX_IOF0>; - }; - - /* SPI1 */ - spi1_cs0_default: spi1_cs0_default { - pinmux = <2 SIFIVE_PINMUX_IOF0>; - }; - spi1_mosi_default: spi1_mosi_default { - pinmux = <3 SIFIVE_PINMUX_IOF0>; - }; - spi1_miso_default: spi1_miso_default { - pinmux = <4 SIFIVE_PINMUX_IOF0>; - }; - spi1_sck_default: spi1_sck_default { - pinmux = <5 SIFIVE_PINMUX_IOF0>; - }; - spi1_cs2_default: spi1_cs2_default { - pinmux = <9 SIFIVE_PINMUX_IOF0>; - }; - spi1_cs3_default: spi1_cs3_default { - pinmux = <10 SIFIVE_PINMUX_IOF0>; - }; - - /* PWM0 */ - pwm0_0_default: pwm0_0_default { - pinmux = <0 SIFIVE_PINMUX_IOF1>; - }; - pwm0_1_default: pwm0_1_default { - pinmux = <1 SIFIVE_PINMUX_IOF1>; - }; - pwm0_2_default: pwm0_2_default { - pinmux = <2 SIFIVE_PINMUX_IOF1>; - }; - pwm0_3_default: pwm0_3_default { - pinmux = <3 SIFIVE_PINMUX_IOF1>; - }; - - /* PWM1 */ - pwm1_0_default: pwm1_0_default { - pinmux = <20 SIFIVE_PINMUX_IOF1>; - }; - pwm1_1_default: pwm1_1_default { - pinmux = <19 SIFIVE_PINMUX_IOF1>; - }; - pwm1_2_default: pwm1_2_default { - pinmux = <21 SIFIVE_PINMUX_IOF1>; - }; - pwm1_3_default: pwm1_3_default { - pinmux = <22 SIFIVE_PINMUX_IOF1>; - }; - - /* PWM2 */ - pwm2_0_default: pwm2_0_default { - pinmux = <10 SIFIVE_PINMUX_IOF1>; - }; - pwm2_1_default: pwm2_1_default { - pinmux = <11 SIFIVE_PINMUX_IOF1>; - }; - pwm2_2_default: pwm2_2_default { - pinmux = <12 SIFIVE_PINMUX_IOF1>; - }; - pwm2_3_default: pwm2_3_default { - pinmux = <13 SIFIVE_PINMUX_IOF1>; - }; - - /* I2C0 */ - i2c0_0_default: i2c0_0_default { - pinmux = <12 SIFIVE_PINMUX_IOF0>; - }; - i2c0_1_default: i2c0_1_default { - pinmux = <13 SIFIVE_PINMUX_IOF0>; - }; -}; diff --git a/boards/riscv/hifive1_revb/hifive1_revb.dts b/boards/riscv/hifive1_revb/hifive1_revb.dts deleted file mode 100644 index f01711d8c590c2..00000000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb.dts +++ /dev/null @@ -1,143 +0,0 @@ -/* Copyright (c) 2019 SiFive, Inc. */ -/* SPDX-License-Identifier: Apache-2.0 */ - -/dts-v1/; - -#include -#include -#include "hifive1_revb-pinctrl.dtsi" - -/ { - model = "SiFive HiFive 1 Rev B"; - compatible = "sifive,hifive1-revb"; - - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - watchdog0 = &wdog0; - }; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &dtim; - zephyr,flash = &flash0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 19 GPIO_ACTIVE_LOW>; - label = "Green LED"; - }; - led1: led_1 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "Blue LED"; - }; - led2: led_2 { - gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; - label = "Red LED"; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = /* A0 not connected */ - <1 0 &gpio0 9 0>, /* A1, also CS2 */ - <2 0 &gpio0 10 0>, /* A2, also WF_INT */ - <3 0 &gpio0 11 0>, /* A3 */ - <4 0 &gpio0 12 0>, /* A4 */ - <5 0 &gpio0 13 0>, /* A5 */ - <6 0 &gpio0 16 0>, /* D0, also TX */ - <7 0 &gpio0 17 0>, /* D1, also RX */ - <8 0 &gpio0 18 0>, /* D2 */ - <9 0 &gpio0 19 0>, /* D3 */ - <10 0 &gpio0 20 0>, /* D4 */ - <11 0 &gpio0 21 0>, /* D5 */ - <12 0 &gpio0 22 0>, /* D6 */ - <13 0 &gpio0 23 0>, /* D7 */ - <14 0 &gpio0 0 0>, /* D8 */ - <15 0 &gpio0 1 0>, /* D9 */ - <16 0 &gpio0 2 0>, /* D10 */ - <17 0 &gpio0 3 0>, /* D11, also MOSI */ - <18 0 &gpio0 4 0>, /* D12, also MISO */ - <19 0 &gpio0 5 0>, /* D13, also SCK */ - <20 0 &gpio0 12 0>, /* D14, also SDA */ - <21 0 &gpio0 13 0>; /* D15, also SCL */ - }; -}; - -&coreclk { - clock-frequency = ; - status = "okay"; -}; - -&gpio0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_rx_default &uart0_tx_default>; - pinctrl-names = "default"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; -}; - -/* disabled (used by Flash ROM by default) */ -&spi0 { - reg = <0x10014000 0x1000 0x20010000 0x3c0900>; - flash0: flash@0 { - compatible = "issi,is25lp128", "jedec,spi-nor"; - status = "disabled"; - size = <134217728>; - jedec-id = [96 60 18]; - reg = <0>; - spi-max-frequency = <133000000>; - }; -}; - -&spi1 { - status = "okay"; - pinctrl-0 = <&spi1_cs0_default - &spi1_mosi_default - &spi1_miso_default - &spi1_sck_default>; - pinctrl-names = "default"; -}; - -&spi2 { - status = "okay"; - pinctrl-0 = <&spi1_cs2_default - &spi1_mosi_default - &spi1_miso_default - &spi1_sck_default>; - pinctrl-names = "default"; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -arduino_i2c: &i2c0 { - status = "okay"; - clock-frequency = <100000>; - pinctrl-0 = <&i2c0_0_default &i2c0_1_default>; - pinctrl-names = "default"; -}; diff --git a/boards/riscv/hifive1_revb/hifive1_revb.yaml b/boards/riscv/hifive1_revb/hifive1_revb.yaml deleted file mode 100644 index 5a44018354ce83..00000000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: hifive1_revb -name: SiFive HiFive1 Rev B -type: mcu -arch: riscv -toolchain: - - zephyr -ram: 16 -testing: - ignore_tags: - - net - - bluetooth -supported: - - arduino_gpio - - arduino_i2c - - gpio - - i2c -vendor: sifive diff --git a/boards/riscv/hifive1_revb/hifive1_revb_defconfig b/boards/riscv/hifive1_revb/hifive1_revb_defconfig deleted file mode 100644 index b2119eecae9b59..00000000000000 --- a/boards/riscv/hifive1_revb/hifive1_revb_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_HIFIVE1_REVB=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_RISCV_CORE_E31=y diff --git a/boards/riscv/hifive_unleashed/Kconfig.board b/boards/riscv/hifive_unleashed/Kconfig.board deleted file mode 100644 index f6c623e992817e..00000000000000 --- a/boards/riscv/hifive_unleashed/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE_UNLEASHED - bool "HiFive Unleashed target" - depends on SOC_SIFIVE_FREEDOM_U540 diff --git a/boards/riscv/hifive_unleashed/Kconfig.defconfig b/boards/riscv/hifive_unleashed/Kconfig.defconfig deleted file mode 100644 index 213aab0aab942b..00000000000000 --- a/boards/riscv/hifive_unleashed/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE_UNLEASHED - -config BOARD - default "hifive_unleashed" - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig b/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig deleted file mode 100644 index 51d324d457d337..00000000000000 --- a/boards/riscv/hifive_unleashed/hifive_unleashed_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_U500=y -CONFIG_SOC_SIFIVE_FREEDOM_U540=y -CONFIG_BOARD_HIFIVE_UNLEASHED=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_XIP=n diff --git a/boards/riscv/hifive_unmatched/Kconfig.board b/boards/riscv/hifive_unmatched/Kconfig.board deleted file mode 100644 index bb303cc3aac4be..00000000000000 --- a/boards/riscv/hifive_unmatched/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HIFIVE_UNMATCHED - bool "HiFive Unmatched target" - depends on SOC_SIFIVE_FREEDOM_U740 diff --git a/boards/riscv/hifive_unmatched/Kconfig.defconfig b/boards/riscv/hifive_unmatched/Kconfig.defconfig deleted file mode 100644 index ee38da1c579178..00000000000000 --- a/boards/riscv/hifive_unmatched/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 Katsuhiro Suzuki -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_HIFIVE_UNMATCHED - -config BOARD - default "hifive_unmatched" - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig b/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig deleted file mode 100644 index be13ed10358664..00000000000000 --- a/boards/riscv/hifive_unmatched/hifive_unmatched_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_U700=y -CONFIG_SOC_SIFIVE_FREEDOM_U740=y -CONFIG_BOARD_HIFIVE_UNMATCHED=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_XIP=n diff --git a/boards/riscv/icev_wireless/Kconfig.board b/boards/riscv/icev_wireless/Kconfig.board deleted file mode 100644 index 21e7a72815ef27..00000000000000 --- a/boards/riscv/icev_wireless/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ICEV_WIRELESS - bool "ICE-V Wireless Board" - depends on SOC_ESP32C3 diff --git a/boards/riscv/icev_wireless/Kconfig.defconfig b/boards/riscv/icev_wireless/Kconfig.defconfig deleted file mode 100644 index 44157fd5b6a368..00000000000000 --- a/boards/riscv/icev_wireless/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2022 Friedt Professional Engineering Services, Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "icev_wireless" - depends on BOARD_ICEV_WIRELESS - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/icev_wireless/doc/index.rst b/boards/riscv/icev_wireless/doc/index.rst deleted file mode 100644 index a3ae804c66891e..00000000000000 --- a/boards/riscv/icev_wireless/doc/index.rst +++ /dev/null @@ -1,259 +0,0 @@ -.. _icev_wireless: - -ICE-V Wireless -############## - -Overview -******** - -The ICE-V Wireless is a combined ESP32C3 and iCE40 FPGA board. - -See the `ICE-V Wireless Github Project`_ for details. - -.. figure:: img/icev_wireless.jpg - :align: center - :alt: ICE-V Wireless - - ICE-V Wireless - -Hardware -******** - -This board combines an Espressif ESP32-C3-MINI-1 (which includes 4MB of flash in the module) with a -Lattice iCE40UP5k-SG48 FPGA to allow WiFi and Bluetooth control of the FPGA. ESP32 and FPGA I/O is -mostly uncommitted except for the pins used for SPI communication between ESP32 and FPGA. Several -of the ESP32C3 GPIO pins are available for additonal interfaces such as serial, ADC, I2C, etc. - -For details on ESP32-C3 hardware please refer to the following resources: - -* `ESP32-C3-MINI-1 Datasheet`_ -* `ESP32-C3 Datasheet`_ -* `ESP32-C3 Technical Reference Manual`_ - -For details on iCE40 hardware please refer to the following resources: - -* `iCE40 UltraPlus Family Datasheet`_ - -Supported Features -================== - -The ICE-V Wireless board configuration supports the following hardware -features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| ADC | on-chip | | -+-----------+------------+------------------+ - -Other hardware features have not been enabled yet for this board. - -Connections and IOs -=================== - -The ICE-V Wireless provides 1 row of reference, ESP32-C3, and iCE40 signals -brought out to J3, as well as 3 PMOD connectors for interfacing directly to -the iCE40 FPGA. Note that several of the iCE40 pins brought out to the PMOD -connectors are capable of operating as differential pairs. - -.. figure:: img/icev_wireless_back.jpg - :align: center - :alt: ICE-V Wireless (Back) - - ICE-V Wireless (Back) - -The J3 pins are 4V, 3.3V, NRST, GPIO2, GPIO3, GPIO8, GPIO9, GPIO10, GPIO20, -GPIO21, FPGA_P34, and GND. Note that GPIO2 and GPIO3 may be configured for -ADC operation. - -For PMOD details, please refer to the `PMOD Specification`_ and the image -below. - -.. figure:: img/icev_wireless_pinout.jpg - :align: center - :alt: ICE-V Wireless Pinout - -Programming and Debugging -************************* - -Programming and debugging for the ICE-V Wireless ESP32-C3 target is -incredibly easy 🎉 following the steps below. - -Building and Flashing -********************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: icev_wireless - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -For the :code:`Hello, world!` application, follow the instructions below. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: icev_wireless - :goals: build flash - -Open the serial monitor using the following command: - -.. code-block:: console - - $ west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! icev_wireless - -Debugging -********* - -As with much custom hardware, the ESP32C3 modules require patches to -OpenOCD that are not upstreamed. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained by running the following extension: - -.. code-block:: console - - west espressif install - -.. note:: - - By default, the OpenOCD will be downloaded and installed under $HOME/.espressif/tools/zephyr directory - (%USERPROFILE%/.espressif/tools/zephyr on Windows). - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: icev_wireless - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the -:ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: icev_wireless - :maybe-skip-config: - :goals: debug - -References -********** - -.. _ICE-V Wireless Github Project: - https://github.com/ICE-V-Wireless/ICE-V-Wireless - -.. _ESP32-C3-MINI-1 Datasheet: - https://www.espressif.com/sites/default/files/documentation/esp32-c3-mini-1_datasheet_en.pdf - -.. _ESP32-C3 Datasheet: - https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf - -.. _ESP32-C3 Technical Reference Manual: - https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf - -.. _iCE40 UltraPlus Family Datasheet: - https://www.latticesemi.com/-/media/LatticeSemi/Documents/DataSheets/iCE/iCE40-UltraPlus-Family-Data-Sheet.ashx - -.. _PMOD Specification: - https://digilent.com/reference/_media/reference/pmod/pmod-interface-specification-1_2_0.pdf diff --git a/boards/riscv/icev_wireless/icev_wireless_defconfig b/boards/riscv/icev_wireless/icev_wireless_defconfig deleted file mode 100644 index c5be5732a71be9..00000000000000 --- a/boards/riscv/icev_wireless/icev_wireless_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ICEV_WIRELESS=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/index.rst b/boards/riscv/index.rst deleted file mode 100644 index aecea8aa600c1d..00000000000000 --- a/boards/riscv/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-riscv: - -RISC-V Boards -############# - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/riscv/it82xx2_evb/Kconfig.board b/boards/riscv/it82xx2_evb/Kconfig.board deleted file mode 100644 index 1aa6f491d7ffbc..00000000000000 --- a/boards/riscv/it82xx2_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IT82XX2_EVB - bool "IT82XX2 EV-board" - depends on SOC_IT8XXX2 diff --git a/boards/riscv/it82xx2_evb/Kconfig.defconfig b/boards/riscv/it82xx2_evb/Kconfig.defconfig deleted file mode 100644 index 37d6dc601c9e3a..00000000000000 --- a/boards/riscv/it82xx2_evb/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IT82XX2_EVB - -config BOARD - default "it82xx2_evb" - -config INPUT - default y if KSCAN - -endif diff --git a/boards/riscv/it82xx2_evb/doc/index.rst b/boards/riscv/it82xx2_evb/doc/index.rst deleted file mode 100644 index 293cc5b156d7a0..00000000000000 --- a/boards/riscv/it82xx2_evb/doc/index.rst +++ /dev/null @@ -1,247 +0,0 @@ -.. _it82xx2_evb: - -ITE IT82XX2 series -###################### - -Overview -******** - -The IT82XX2 is a 32-bit RISC-V microcontroller. -And a highly integrated embedded controller with system functions. -It is suitable for mobile system applications. The picture below is -the IT82202 development board (also known as it82xx2_evb) and its debug card. - -.. figure:: it82xx2_evb_and_debug_card.jpg - :align: center - :alt: IT82202 EVB - -To find out more about ITE, visit our World Wide Web at:`ITE's website`_ - -Hardware -******** -The IT82XX2 series contains different chip types(ex, it82202, it82302), -and they support different hardware features. -Listing the IT82202 hardware features as following: - -- RISC-V RV32IMAFC instruction set -- 4KB instruction cache size -- 256KB SRAM in total -- Built-in 32.768 kHz clock generator -- Embedded Flash, 512K/1024K-byte e-flash -- eSPI, SSPI, SPI slave, BRAM, KBC, PECI, UART -- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG -- Support 6 Voltage Comparator -- Support Cryptographic Engine -- 6 SMBus channels, with 6 DMA controller, compatible with I2C -- USB 2.0 Full-speed Controller -- USB Type-c CC Logic -- USB Power Delivery - - -Supported Features -================== -currently supports the following hardware features: - -.. list-table:: Supported Features - :header-rows: 1 - :widths: auto - - * - Interface - - Controller - - Driver/Component - * - NVIC - - on-chip - - interrupt controller - * - FLASH - - on-chip - - flash controller - * - PINCTRL - - on-chip - - pin controller - * - ESPI - - on-chip - - espi - * - PECI - - on-chip - - peci - * - UART - - on-chip - - serial - * - GPIO - - on-chip - - gpio - * - PWM - - on-chip - - pwm - * - ADC - - on-chip - - adc - * - TIMER - - on-chip - - timer - * - WATCHDOG - - on-chip - - watchdog - * - KSCAN - - on-chip - - kscan - * - SENSOR - - on-chip - - voltage comparator - * - I2C - - on-chip - - i2c - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/riscv/it82xx2_evb/it82xx2_evb_defconfig` Kconfig file. - -Programming and debugging on it82202 -************************************ - -In order to upload the application to the device, -you'll need our flash tool and Download board. -You can get them at: `ITE's website`_. - -Wiring -======= -#. Connect the Download Board to your host computer using the USB cable. - -#. Connect the it82xx2_evb to the evolution motherboard. - -#. Connect the Download Board J5 to J41 on the evolution motherboard. - -#. Connect the USB to UART wire to J33 on the evolution motherboard. - - .. image:: it82xx2_evb_wiring.jpg - :align: center - :alt: it82xx2_evb wiring - - .. note:: Be careful during connection! - Use separate wires to connect I2C pins with pins on the it82xx2_evb board. - Wiring connection is described in the table below. - - +-------------+---------------+ - | J5 | it82xx2_evb | - | Connector | J41 Connector | - +=============+===============+ - | 2 | E0 | - +-------------+---------------+ - | 3 | E7 | - +-------------+---------------+ - | 4 | GND | - +-------------+---------------+ - - For USB to UART cable, connect the evolution motherboard as below: - - +-------------+---------------+ - | USB to UART | Evolution | - | cable | motherboard | - | | J33 Connector | - +=============+===============+ - | RX | B0 | - +-------------+---------------+ - | TX | B1 | - +-------------+---------------+ - | GND | GND | - +-------------+---------------+ - -Building -======== - -#. Build :ref:`hello_world` application as you would normally do - (see :`Zephyr Getting Started Guide`_):. - - .. zephyr-app-commands:: - :board: it82xx2_evb - :zephyr-app: samples/hello_world - :goals: build - -#. The file :file:`zephyr.bin` will be created by west. - -Flashing -======== - -Windows --------- - -Use the winflash tool to program a zephyr application -to the it82xx2 board flash. - -#. Open the winflash tool and make sure the order you open the switch is right. - First, turn on the Download board switch. - Second, turn on the it82xx2_evb board switch. - Then, configure your winflash tool like below. - - .. figure:: WinFlashTool_P2.jpg - :align: center - - .. figure:: WinFlashTool_P4.jpg - -#. Using the winflash tool flash ``zephyr.bin`` into your ITE board. - First, click the ``Load`` button and select your ``zephyr.bin`` file. - Second, click ``run`` to flash the image into board. - - .. figure:: WinFlashTool_P3.jpg - :align: center - -#. At this point, you have flashed your image into ITE board and - it will work if you turn on the ITE board. You can use a terminal program - to verify flashing worked correctly. - - For example, open device manager to find the USB Serial Port(COM4) and use your - terminal program to connect it(Speed: 115200). - - .. figure:: WinFlashTool_P1.jpg - :align: center - -#. Turn on the it82xx2_evb board switch, you should see ``"Hello World! it82xx2_evb"`` - sent by the board. If you don't see this message, press the Reset button and the - message should appear. - -Ubuntu --------- - -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -b 115200 - -#. Open a second terminal window and use the Linux flash tool to flash your board. - - .. code-block:: console - - $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin - - .. note:: The source code of ITE tool can be downloaded here: - https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 - -#. Split first and second terminal windows to view both of them. - You should see ``"Hello World! it82xx2_evb"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= - -it82xx2_evb board can be debugged by connecting USB to UART. We can write commands and -read messages through minicom in the Ubuntu terminal. - -Troubleshooting -=============== - -#. If the flash tool reports a failure, re-plug the 8390 Download board or - power cycle the it82xx2_evb board and try again. - -References -========== - -.. target-notes:: - -.. _ITE's website: https://www.ite.com.tw/zh-tw/product/view?mid=169 -.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/it8xxx2_evb/Kconfig.board b/boards/riscv/it8xxx2_evb/Kconfig.board deleted file mode 100644 index 52040e4854c2e1..00000000000000 --- a/boards/riscv/it8xxx2_evb/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_IT8XXX2_EVB - bool "IT8XXX2 EV-board" - depends on SOC_IT8XXX2 diff --git a/boards/riscv/it8xxx2_evb/Kconfig.defconfig b/boards/riscv/it8xxx2_evb/Kconfig.defconfig deleted file mode 100644 index 8c198316bed90d..00000000000000 --- a/boards/riscv/it8xxx2_evb/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_IT8XXX2_EVB - -config BOARD - default "it8xxx2_evb" - -if PM -config PM_DEVICE - default y - -choice PM_POLICY - default PM_POLICY_CUSTOM -endchoice -endif # PM - -config INPUT - default y if KSCAN - -endif # BOARD_IT8XXX2_EVB diff --git a/boards/riscv/it8xxx2_evb/doc/index.rst b/boards/riscv/it8xxx2_evb/doc/index.rst deleted file mode 100644 index 419a525c1e73b0..00000000000000 --- a/boards/riscv/it8xxx2_evb/doc/index.rst +++ /dev/null @@ -1,228 +0,0 @@ -.. _it8xxx2_evb: - -ITE IT8XXX2 series -###################### - -Overview -******** - -The IT8XXX2 is a 32-bit RISC-V Micro-controller. -And a highly integrated embedded controller with system functions. -It is suitable for mobile system applications. The picture below is -the IT81302 MECC board (also known as it8xxx2_evb) and its debug card. - -.. figure:: it8xxx2_evb_and_debug_card.jpg - :align: center - :alt: IT81302 EVB - -To find out more about ITE, visit our World Wide Web at:`ITE's website`_ - -Hardware -******** -The IT8XXX2 series contains different chip types(ex, it81302, it83202), -and they support different hardware features. -Listing the IT81302 hardware features as following: - -- RISC-V RV32IMAFC instruction set -- 4KB instruction cache size -- 60KB SDRAM in total -- Built-in 32.768 kHz clock generator -- PWM, eSPI, LPC, FLASH, UART, GPIO, Timer, Watchdog, ADC, JTAG -- 6 SMBus channels, with 3 DMA controllers, compatible with I2C -- SPI master/slave -- USB Type-c CC Logic -- USB Power Delivery -- Support KB scan - - -Supported Features -================== -currently supports the following hardware features: - -.. list-table:: Supported Features - :header-rows: 1 - :widths: auto - - * - Interface - - Controller - - Driver/Component - * - NVIC - - on-chip - - interrupt controller - * - TIMER - - on-chip - - timer - * - UART - - on-chip - - serial - * - GPIO - - on-chip - - gpio - * - ADC - - on-chip - - adc - * - I2C - - on-chip - - i2c - * - KSCAN - - on-chip - - kscan - - -Other hardware features are not currently supported by Zephyr. - -The default configuration can be found in the -:zephyr_file:`boards/riscv/it8xxx2_evb/it8xxx2_evb_defconfig` Kconfig file. - -Hardware reworks -**************** - -Before using the it8xxx2_evb, some hardware rework is needed. The HW rework -guide can be found in ITE's website. -https://www.ite.com.tw/uploads/product_download/IT81302_MECC_Rework_Guide_0927.pdf - -Programming and debugging on it83202 -************************************ - -In order to upload the application to the device, -you'll need our flash tool and Download board. -You can get them at: `ITE's website`_. - -Wiring -======= -#. Connect the Download Board to your host computer using the USB cable. - -#. Connect the it8xxx2_evb to your host computer or a 5V1A USB power supply. - -#. Connect the Download Board J5 to J8 on the it8xxx2_evb board. - -#. Connect the USB to UART wire to it8xxx2_evb. - - .. image:: it8xxx2_evb_wiring.jpg - :align: center - :alt: it8xxx2_evb wiring - - .. note:: Be careful during connection! - Use separate wires to connect I2C pins with pins on the it8xxx2_evb board. - Wiring connection is described in the table below. - - +-------------+---------------+ - | J5 | it8xxx2_evb | - | Connector | J8 Connector | - +=============+===============+ - | 2 | 1 | - +-------------+---------------+ - | 3 | 3 | - +-------------+---------------+ - | 4 | 5 | - +-------------+---------------+ - - For USB to UART cable, connect the it8xxx2_evb as below: - - +-------------+---------------+ - | USB to UART | it8xxx2_evb | - | cable | J5 Connector | - +=============+===============+ - | RX | J5.3 | - +-------------+---------------+ - | TX | J5.4 | - +-------------+---------------+ - | GND | eSPI Debug.10 | - +-------------+---------------+ - -Building -======== - -#. Build :ref:`hello_world` application as you would normally do - (see :`Zephyr Getting Started Guide`_):. - - .. zephyr-app-commands:: - :board: it8xxx2_evb - :zephyr-app: samples/hello_world - :goals: build - -#. The file :file:`zephyr.bin` will be created by west. - -Flashing -======== - -Windows --------- - -Use the winflash tool to program a zephyr application -to the it8xxx2 board flash. - -#. Open winflash tool and make sure the order you open the switch is right. - Fisrt, turn on the Download board switch. - Second, turn on the it8xxx2_evb board switch. - Then, configure your winflash tool like below. - - .. figure:: WinFlashTool_P2.jpg - :align: center - - .. figure:: WinFlashTool_P4.jpg - -#. Using winflash tool flash zephyr.bin into your ITE board. - First, click ``Load`` button and select your zephyr.bin file. - Second, click ``run`` to flash the iamge into board. - - .. figure:: WinFlashTool_P3.jpg - :align: center - -#. At this point, you have flashed your image into ITE board and - it will work if you turn on ITE board. You can use a terminal program - to verify flashing worked correctly. - - For example, open device manager to find the USB Serial Port(COM4) and use your - terminal program to connect it(Speed: 115200). - - .. figure:: WinFlashTool_P1.jpg - :align: center - -#. Turn on the it8xxx2_evb board switch, you should see ``"Hello World! it8xxx2_evb"`` - sent by the board. If you don't see this message, press the Reset button and the - message should appear. - -Ubuntu --------- - -#. Run your favorite terminal program to listen for output. - Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it. - - For example: - - .. code-block:: console - - $ minicom -D /dev/ttyUSB0 -b 115200 - -#. Open a second terminal window and use linux flash tool to flash your board. - - .. code-block:: console - - $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin - - .. note:: The source code of ITE tool can be downloaded here: - https://www.ite.com.tw/uploads/product_download/itedlb4-linux-v106.tar.bz2 - -#. Split first and second terminal windows to view both of them. - You should see ``"Hello World! it8xxx2_evb"`` in the first terminal window. - If you don't see this message, press the Reset button and the message should appear. - -Debugging -========= - -Supporting uart debug, currently. - -Troubleshooting -=============== - -#. If the flash tool reports a failure, re-plug the 8390 Download board or - power cycle the it8xxx2_evb board and try again. - -References -========== - -.. target-notes:: - -.. _ITE's website: http://www.ite.com.tw/en/product/view?mid=149 -.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html diff --git a/boards/riscv/litex_vexriscv/Kconfig.board b/boards/riscv/litex_vexriscv/Kconfig.board deleted file mode 100644 index de9d8026b6a009..00000000000000 --- a/boards/riscv/litex_vexriscv/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LITEX_VEXRISCV - bool "Board with LiteX/VexRiscV CPU" - depends on SOC_RISCV32_LITEX_VEXRISCV diff --git a/boards/riscv/litex_vexriscv/Kconfig.defconfig b/boards/riscv/litex_vexriscv/Kconfig.defconfig deleted file mode 100644 index ef0440b9a37e94..00000000000000 --- a/boards/riscv/litex_vexriscv/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_LITEX_VEXRISCV - -config BOARD - default "litex_vexriscv" - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # BOARD_LITEX_VEXRISCV diff --git a/boards/riscv/longan_nano/Kconfig.board b/boards/riscv/longan_nano/Kconfig.board deleted file mode 100644 index f656bdbf67a015..00000000000000 --- a/boards/riscv/longan_nano/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_LONGAN_NANO - bool "Sipeed Longan Nano target" - depends on SOC_GD32VF103 - -config BOARD_LONGAN_NANO_LITE - bool "Sipeed Longan Nano Lite target" - depends on SOC_GD32VF103 diff --git a/boards/riscv/longan_nano/Kconfig.defconfig b/boards/riscv/longan_nano/Kconfig.defconfig deleted file mode 100644 index af4f75cf898471..00000000000000 --- a/boards/riscv/longan_nano/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Sipeed longan nano Development Board Configuration - -# Copyright (c) 2021 Tokita, Hiroshi - -if BOARD_LONGAN_NANO || BOARD_LONGAN_NANO_LITE - -config BOARD - default "longan_nano" if BOARD_LONGAN_NANO - default "longan_nano_lite" if BOARD_LONGAN_NANO_LITE - -config DISK_DRIVER_SDMMC - default y if DISK_DRIVERS - -endif # BOARD_LONGAN_NANO || BOARD_LONGAN_NANO_LITE diff --git a/boards/riscv/longan_nano/longan_nano_lite.yaml b/boards/riscv/longan_nano/longan_nano_lite.yaml deleted file mode 100644 index 14f7e6fc9380ba..00000000000000 --- a/boards/riscv/longan_nano/longan_nano_lite.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: longan_nano_lite -name: Sipeed Longan Nano Lite -type: mcu -arch: riscv -toolchain: - - zephyr - - xtools -flash: 64 -ram: 20 -supported: - - watchdog - - dma - - spi -vendor: sipeed diff --git a/boards/riscv/longan_nano/longan_nano_lite_defconfig b/boards/riscv/longan_nano/longan_nano_lite_defconfig deleted file mode 100644 index 2c3743c01629b2..00000000000000 --- a/boards/riscv/longan_nano/longan_nano_lite_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Sipeed Longan Nano Lite board Configuration -# -# Copyright (c) 2021 Tokita, Hiroshi -# -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_LONGAN_NANO_LITE=y - -CONFIG_GD32_HXTAL_8MHZ=y - -CONFIG_SERIAL=y -CONFIG_UART_INTERRUPT_DRIVEN=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/riscv/m2gl025_miv/Kconfig.board b/boards/riscv/m2gl025_miv/Kconfig.board deleted file mode 100644 index 9f81fad406f355..00000000000000 --- a/boards/riscv/m2gl025_miv/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M2GL025_MIV - bool "Microchip M2GL025 IGLOO2 dev board with Mi-V CPU" - depends on SOC_MIV diff --git a/boards/riscv/m2gl025_miv/Kconfig.defconfig b/boards/riscv/m2gl025_miv/Kconfig.defconfig deleted file mode 100644 index 43f9c813c9a80a..00000000000000 --- a/boards/riscv/m2gl025_miv/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "m2gl025_miv" - depends on BOARD_M2GL025_MIV diff --git a/boards/riscv/mpfs_icicle/Kconfig.board b/boards/riscv/mpfs_icicle/Kconfig.board deleted file mode 100644 index e772b82d7f58cf..00000000000000 --- a/boards/riscv/mpfs_icicle/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021-2022 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_MPFS_ICICLE - bool "Microchip PolarFire SoC ICICLE kit" - depends on SOC_POLARFIRE - select 64BIT - select SCHED_IPI_SUPPORTED - select CPU_HAS_FPU_DOUBLE_PRECISION diff --git a/boards/riscv/mpfs_icicle/Kconfig.defconfig b/boards/riscv/mpfs_icicle/Kconfig.defconfig deleted file mode 100644 index 5993e6878c9b99..00000000000000 --- a/boards/riscv/mpfs_icicle/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2020-2021 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "mpfs_icicle" - depends on BOARD_MPFS_ICICLE diff --git a/boards/riscv/neorv32/Kconfig.board b/boards/riscv/neorv32/Kconfig.board deleted file mode 100644 index 6d85ebb2e402a5..00000000000000 --- a/boards/riscv/neorv32/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NEORV32 - bool "NEORV32 Processor (SoC)" - depends on SOC_NEORV32 diff --git a/boards/riscv/neorv32/Kconfig.defconfig b/boards/riscv/neorv32/Kconfig.defconfig deleted file mode 100644 index 350255fb06a2ad..00000000000000 --- a/boards/riscv/neorv32/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NEORV32 - -config BOARD - default "neorv32" - -endif # BOARD_NEORV32 diff --git a/boards/riscv/neorv32/neorv32_1_8_6.conf b/boards/riscv/neorv32/neorv32_1_8_6.conf deleted file mode 100644 index b1852631eeb6f5..00000000000000 --- a/boards/riscv/neorv32/neorv32_1_8_6.conf +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_NEORV32_V1_8_6=y diff --git a/boards/riscv/neorv32/revision.cmake b/boards/riscv/neorv32/revision.cmake deleted file mode 100644 index b09cf3696111ee..00000000000000 --- a/boards/riscv/neorv32/revision.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -board_check_revision( - FORMAT MAJOR.MINOR.PATCH - DEFAULT_REVISION 1.8.6 -) diff --git a/boards/riscv/niosv_g/Kconfig.board b/boards/riscv/niosv_g/Kconfig.board deleted file mode 100644 index bcc48f497d8085..00000000000000 --- a/boards/riscv/niosv_g/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NIOSV_G - bool "Intel FPGA Nios V/g General Purpose Processor" - depends on SOC_NIOSV_G diff --git a/boards/riscv/niosv_g/Kconfig.defconfig b/boards/riscv/niosv_g/Kconfig.defconfig deleted file mode 100644 index ecfc8b41bab2b2..00000000000000 --- a/boards/riscv/niosv_g/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NIOSV_G - -config BOARD - default "niosv_g" - -endif # BOARD_NIOSV_G diff --git a/boards/riscv/niosv_g/niosv_g_defconfig b/boards/riscv/niosv_g/niosv_g_defconfig deleted file mode 100644 index f933bca38746ff..00000000000000 --- a/boards/riscv/niosv_g/niosv_g_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NIOSV=y -CONFIG_SOC_NIOSV_G=y -CONFIG_BOARD_NIOSV_G=y -CONFIG_CONSOLE=y -CONFIG_PRINTK=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_XIP=n diff --git a/boards/riscv/niosv_m/Kconfig.board b/boards/riscv/niosv_m/Kconfig.board deleted file mode 100644 index 92e853c464087b..00000000000000 --- a/boards/riscv/niosv_m/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NIOSV_M - bool "Intel FPGA NIOSV Microcontroller Core Processor" - depends on SOC_NIOSV_M diff --git a/boards/riscv/niosv_m/Kconfig.defconfig b/boards/riscv/niosv_m/Kconfig.defconfig deleted file mode 100644 index 40d9389e25b7b7..00000000000000 --- a/boards/riscv/niosv_m/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NIOSV_M - -config BOARD - default "niosv_m" - -endif # BOARD_NIOSV_M diff --git a/boards/riscv/niosv_m/niosv_m_defconfig b/boards/riscv/niosv_m/niosv_m_defconfig deleted file mode 100644 index 1eba59917a34c6..00000000000000 --- a/boards/riscv/niosv_m/niosv_m_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NIOSV=y -CONFIG_SOC_NIOSV_M=y -CONFIG_BOARD_NIOSV_M=y -CONFIG_CONSOLE=y -CONFIG_PRINTK=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_ALTERA_JTAG=y -CONFIG_XIP=n diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board deleted file mode 100644 index 9bbbba60dd43dd..00000000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NRF54H20PDK_NRF54H20_CPUPPR - bool "nRF54H20 PDK nRF54H20 PPR MCU" - depends on SOC_NRF54H20_ENGA_CPUPPR diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig b/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig deleted file mode 100644 index 256976d65190c3..00000000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "nrf54h20pdk_nrf54h20_cpuppr" - depends on BOARD_NRF54H20PDK_NRF54H20_CPUPPR diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake b/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake deleted file mode 100644 index 4c63f1dd05ee45..00000000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/board.cmake +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) diff --git a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig b/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig deleted file mode 100644 index 112140693efa42..00000000000000 --- a/boards/riscv/nrf54h20pdk_nrf54h20/nrf54h20pdk_nrf54h20_cpuppr_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NRF54HX=y -CONFIG_SOC_NRF54H20=y -CONFIG_SOC_NRF54H20_ENGA_CPUPPR=y -CONFIG_BOARD_NRF54H20PDK_NRF54H20_CPUPPR=y - -CONFIG_USE_DT_CODE_PARTITION=y - -CONFIG_SERIAL=y - -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/riscv/opentitan_earlgrey/Kconfig.board b/boards/riscv/opentitan_earlgrey/Kconfig.board deleted file mode 100644 index 544c02b1b2aeb5..00000000000000 --- a/boards/riscv/opentitan_earlgrey/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 by Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OPENTITAN_EARLGREY - bool "OpenTitan Earl Grey Target" - depends on SOC_OPENTITAN diff --git a/boards/riscv/opentitan_earlgrey/Kconfig.defconfig b/boards/riscv/opentitan_earlgrey/Kconfig.defconfig deleted file mode 100644 index 743d2bd28a1f31..00000000000000 --- a/boards/riscv/opentitan_earlgrey/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 by Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OPENTITAN_EARLGREY - -config BOARD - default "opentitan_earlgrey" - -endif # BOARD_OPENTITAN_EARLGREY diff --git a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig b/boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig deleted file mode 100644 index 886e439b88ac42..00000000000000 --- a/boards/riscv/opentitan_earlgrey/opentitan_earlgrey_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 by Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_OPENTITAN=y -CONFIG_BOARD_OPENTITAN_EARLGREY=y -CONFIG_XIP=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/riscv/qemu_riscv32/Kconfig.board b/boards/riscv/qemu_riscv32/Kconfig.board deleted file mode 100644 index 7c94b59455cce2..00000000000000 --- a/boards/riscv/qemu_riscv32/Kconfig.board +++ /dev/null @@ -1,31 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32 - bool "QEMU RISCV32 target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config BOARD_QEMU_RISCV32_SMP - bool "QEMU RISCV32 SMP target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config BOARD_QEMU_RISCV32_XIP - bool "QEMU RISCV32 XIP target" - depends on SOC_SIFIVE_FREEDOM_E340 - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI diff --git a/boards/riscv/qemu_riscv32/Kconfig.defconfig b/boards/riscv/qemu_riscv32/Kconfig.defconfig deleted file mode 100644 index f0e0768d08278d..00000000000000 --- a/boards/riscv/qemu_riscv32/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_riscv32" if BOARD_QEMU_RISCV32 - default "qemu_riscv32_xip" if BOARD_QEMU_RISCV32_XIP - default "qemu_riscv32_smp" if BOARD_QEMU_RISCV32_SMP - -# Use thread local storage by default so that -# this feature gets more CI coverage. -config THREAD_LOCAL_STORAGE - default y diff --git a/boards/riscv/qemu_riscv32/board.cmake b/boards/riscv/qemu_riscv32/board.cmake deleted file mode 100644 index 9ade8c5ef285f3..00000000000000 --- a/boards/riscv/qemu_riscv32/board.cmake +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -set(QEMU_binary_suffix riscv32) -set(QEMU_CPU_TYPE_${ARCH} riscv32) - -if(CONFIG_BOARD_QEMU_RISCV32 OR CONFIG_BOARD_QEMU_RISCV32_SMP) - set(QEMU_FLAGS_${ARCH} - -nographic - -machine virt - -bios none - -m 256 - ) -else() - set(QEMU_FLAGS_${ARCH} - -nographic - -machine sifive_e - ) -endif() - - -board_set_debugger_ifnset(qemu) diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig deleted file mode 100644 index 946e679a6e81ab..00000000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV32=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_XIP=n -CONFIG_RISCV_PMP=y diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.dts b/boards/riscv/qemu_riscv32/qemu_riscv32_smp.dts deleted file mode 100644 index d335dbcde6feca..00000000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.yaml b/boards/riscv/qemu_riscv32/qemu_riscv32_smp.yaml deleted file mode 100644 index 38ffe83e83176d..00000000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_smp.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_riscv32_smp -name: QEMU Emulation for RISC-V 32-bit SMP -type: qemu -simulation: qemu -arch: riscv -toolchain: - - zephyr - - xtools -supported: - - netif - - smp -testing: - default: true - ignore_tags: - - net - - bluetooth diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig deleted file mode 100644 index 90f87ef6b988b8..00000000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_smp_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV32_SMP=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_XIP=n -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_QEMU_ICOUNT=n - -CONFIG_IDLE_STACK_SIZE=1024 -CONFIG_RISCV_PMP=y diff --git a/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig b/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig deleted file mode 100644 index 948fa909a08548..00000000000000 --- a/boards/riscv/qemu_riscv32/qemu_riscv32_xip_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_QEMU_RISCV32_XIP=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_PINCTRL=y -CONFIG_GPIO=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_RISCV_CORE_E31=y diff --git a/boards/riscv/qemu_riscv32e/Kconfig.board b/boards/riscv/qemu_riscv32e/Kconfig.board deleted file mode 100644 index ace6a7322dd554..00000000000000 --- a/boards/riscv/qemu_riscv32e/Kconfig.board +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV32E - bool "QEMU RISCV32E target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select HAS_COVERAGE_SUPPORT - select RISCV_ISA_RV32E - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI diff --git a/boards/riscv/qemu_riscv32e/Kconfig.defconfig b/boards/riscv/qemu_riscv32e/Kconfig.defconfig deleted file mode 100644 index 54d455ef540bf3..00000000000000 --- a/boards/riscv/qemu_riscv32e/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_riscv32e" if BOARD_QEMU_RISCV32E - -# Use thread local storage by default so that -# this feature gets more CI coverage. -config THREAD_LOCAL_STORAGE - default y diff --git a/boards/riscv/qemu_riscv64/Kconfig.board b/boards/riscv/qemu_riscv64/Kconfig.board deleted file mode 100644 index f75ba14b7a4c53..00000000000000 --- a/boards/riscv/qemu_riscv64/Kconfig.board +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2019 BayLibre SAS -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_RISCV64 - bool "QEMU RISCV64 target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select 64BIT - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU_DOUBLE_PRECISION - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config BOARD_QEMU_RISCV64_SMP - bool "QEMU RISCV64 SMP target" - depends on SOC_RISCV_VIRT - select QEMU_TARGET - select 64BIT - select HAS_COVERAGE_SUPPORT - select CPU_HAS_FPU_DOUBLE_PRECISION - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI diff --git a/boards/riscv/qemu_riscv64/Kconfig.defconfig b/boards/riscv/qemu_riscv64/Kconfig.defconfig deleted file mode 100644 index 7b5d8bfbdcfb4c..00000000000000 --- a/boards/riscv/qemu_riscv64/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019 BayLibre SAS -# SPDX-License-Identifier: Apache-2.0 - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_riscv64" if BOARD_QEMU_RISCV64 - default "qemu_riscv64_smp" if BOARD_QEMU_RISCV64_SMP diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_defconfig b/boards/riscv/qemu_riscv64/qemu_riscv64_defconfig deleted file mode 100644 index 6bfc46ac907af8..00000000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV64=y -CONFIG_PRIVILEGED_STACK_SIZE=2048 -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_QEMU_ICOUNT_SHIFT=6 -CONFIG_XIP=n -CONFIG_RISCV_PMP=y diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.dts b/boards/riscv/qemu_riscv64/qemu_riscv64_smp.dts deleted file mode 100644 index d335dbcde6feca..00000000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.dts +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,sram = &ram0; - }; -}; - -&uart0 { - status = "okay"; -}; diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.yaml b/boards/riscv/qemu_riscv64/qemu_riscv64_smp.yaml deleted file mode 100644 index 5daf38c7055b61..00000000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_smp.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: qemu_riscv64_smp -name: QEMU Emulation for RISC-V 64-bit SMP -type: qemu -simulation: qemu -arch: riscv -toolchain: - - zephyr -supported: - - netif - - smp -testing: - default: true - ignore_tags: - - net - - bluetooth diff --git a/boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig b/boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig deleted file mode 100644 index 265d84a1ded831..00000000000000 --- a/boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_RISCV_VIRT=y -CONFIG_BOARD_QEMU_RISCV64_SMP=y -CONFIG_PRIVILEGED_STACK_SIZE=2048 -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_STACK_SENTINEL=y -CONFIG_XIP=n -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_QEMU_ICOUNT=n - -CONFIG_IDLE_STACK_SIZE=1024 -CONFIG_RISCV_PMP=y -CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/riscv/riscv32_virtual/Kconfig.board b/boards/riscv/riscv32_virtual/Kconfig.board deleted file mode 100644 index c8722acb384bb0..00000000000000 --- a/boards/riscv/riscv32_virtual/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RISCV32_VIRTUAL - bool "riscv32_virtual" - depends on SOC_RISCV32_VIRTUAL_RENODE diff --git a/boards/riscv/riscv32_virtual/Kconfig.defconfig b/boards/riscv/riscv32_virtual/Kconfig.defconfig deleted file mode 100644 index 840b10fd59443d..00000000000000 --- a/boards/riscv/riscv32_virtual/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "riscv32_virtual" - depends on BOARD_RISCV32_VIRTUAL diff --git a/boards/riscv/rv32m1_vega/Kconfig.board b/boards/riscv/rv32m1_vega/Kconfig.board deleted file mode 100644 index 1c36ce9cd7e2fc..00000000000000 --- a/boards/riscv/rv32m1_vega/Kconfig.board +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_RV32M1_VEGA - bool "RV32M1 RISC-V cores" - depends on SOC_OPENISA_RV32M1_RISCV32 diff --git a/boards/riscv/rv32m1_vega/Kconfig.defconfig b/boards/riscv/rv32m1_vega/Kconfig.defconfig deleted file mode 100644 index 9446ac4a9aed82..00000000000000 --- a/boards/riscv/rv32m1_vega/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_RV32M1_VEGA - -config BOARD - default "rv32m1_vega_ri5cy" if SOC_OPENISA_RV32M1_RI5CY - default "rv32m1_vega_zero_riscy" if SOC_OPENISA_RV32M1_ZERO_RISCY - -if BT - -config BT_CTLR - default y - -#TODO: Resolve the complete non-BLE support for crypto CAU3 firmware/driver -#config HAS_RV32M1_CAU3 -# bool -# default y if BT_CTLR_CRYPTO && !BT_CTLR_LE_ENC_SUPPORT - -config HAS_RV32M1_CAU3_BLE - bool - default y if BT_CTLR_CRYPTO && \ - (BT_CTLR_LE_ENC_SUPPORT || BT_CTLR_PRIVACY_SUPPORT) - -config RV32M1_INTMUX_CHANNEL_2 - default n - -config RV32M1_INTMUX_CHANNEL_3 - default n - -endif # BT - -endif # BOARD_RV32M1_VEGA diff --git a/boards/riscv/rv32m1_vega/board.cmake b/boards/riscv/rv32m1_vega/board.cmake deleted file mode 100644 index dc1b5b256c427c..00000000000000 --- a/boards/riscv/rv32m1_vega/board.cmake +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(OPENOCD_USE_LOAD_IMAGE NO) - -if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_ri5cy.cfg") -elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) -board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_rv32m1_vega_zero_riscy.cfg") -endif() - -include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/riscv/rv32m1_vega/doc/index.rst b/boards/riscv/rv32m1_vega/doc/index.rst deleted file mode 100644 index a2f3d107224c89..00000000000000 --- a/boards/riscv/rv32m1_vega/doc/index.rst +++ /dev/null @@ -1,841 +0,0 @@ -.. highlight:: sh - -.. _rv32m1_vega: - -OpenISA VEGAboard -################# - -Overview -******** - -The VEGAboard contains the RV32M1 SoC, featuring two RISC-V CPUs, -on-die XIP flash, and a full complement of peripherals, including a -2.4 GHz multi-protocol radio. It also has built-in sensors and -Arduino-style expansion connectors. - -.. figure:: rv32m1_vega.jpg - :align: center - :alt: RV32M1-VEGA - - OpenISA VEGAboard (image copyright: www.open-isa.org) - -The two RISC-V CPUs are named RI5CY and ZERO-RISCY, and are -respectively based on the `PULP platform`_ designs by the same names: -`RI5CY`_ and `ZERO-RISCY`_. RI5CY is the "main" core; it has more -flash and RAM as well as a more powerful CPU design. ZERO-RISCY is a -"secondary" core. The main ZERO-RISCY use-case is as a wireless -coprocessor for applications running on RI5CY. The two cores can -communicate via shared memory and messaging peripherals. - -Currently, Zephyr supports RI5CY with the ``rv32m1_vega_ri5cy`` board -configuration name, and ZERO_RISCY with the ``rv32m1_vega_zero_riscy`` board -configuration name. - -Hardware -******** - -The VEGAboard includes the following features. - -RV32M1 multi-core SoC: - -- 1 MiB flash and 192 KiB SRAM (RI5CY core) -- 256 KiB flash and 128 KiB SRAM (ZERO-RISCY core) -- Low power modes -- DMA support -- Watchdog, CRC, cryptographic acceleration, ADC, DAC, comparator, - timers, PWM, RTC, I2C, UART, SPI, external memory, I2S, smart - card, USB full-speed, uSDHC, and 2.4 GHz multiprotocol radio - peripherals - -On-board sensors and peripherals: - -- 32 Mbit SPI flash -- 6-axis accelerometer, magnetometer, and temperature sensor (FXOS8700) -- Ambient light sensor -- RGB LED -- microSD card slot -- Antenna interface - -Additional features: - -- Form-factor compatible with Arduino Uno Rev 3 expansion connector - layout (not all Arduino shields may be pin-compatible) -- UART via USB using separate OpenSDA chip -- RISC-V flash and debug using external JTAG dongle (not included) via - 2x5 5 mil pitch connector (commonly called the "ARM 10-pin JTAG" - connector) - -Supported Features -================== - -Zephyr's RI5CY configuration, ``rv32m1_vega_ri5cy``, currently supports -the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| EVENT | on-chip | event unit interrupt controller | -+-----------+------------+-------------------------------------+ -| INTMUX | on-chip | level 2 interrupt controller | -+-----------+------------+-------------------------------------+ -| LPTMR | on-chip | lptmr-based system timer | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| TPM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -+-----------+------------+-------------------------------------+ - -Zephyr's ZERO-RISCY configuration, ``rv32m1_vega_zero_riscy``, currently -supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| EVENT | on-chip | event unit interrupt controller | -+-----------+------------+-------------------------------------+ -| INTMUX | on-chip | level 2 interrupt controller | -+-----------+------------+-------------------------------------+ -| LPTMR | on-chip | lptmr-based system timer | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial | -+-----------+------------+-------------------------------------+ -| I2C(M) | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| TPM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| SENSOR | off-chip | fxos8700 polling; | -| | | fxos8700 trigger; | -+-----------+------------+-------------------------------------+ - -BLE Software Link Layer experimental support -================================================== -This is an experimental feature supported on the Zephyr's RI5CY -configuration, ``rv32m1_vega_ri5cy``. It uses the Software Link Layer -framework by Nordic Semi to enable the on-SoC radio and transceiver for -implementing a software defined BLE controller. By using both the controller -and the host stack available in Zephyr, the following BLE samples can be used -with this board: - -- beacon -- central -- central_hr -- eddystone -- hci_uart -- ibeacon -- peripheral_csc (Cycling Speed Cadence) -- peripheral_dis (Device Information Service) -- peripheral_esp (Environmental Sensing Service) -- peripheral_hr (Heart Rate) -- peripheral_ht (Health Thermometer) -- peripheral -- scan_adv - -.. note:: - - BLE Software Link Layer limitations: - - - no 512/256 Kbps PHY - - no TX power adjustment - - -Connections and IOs -=================== - -RV32M1 SoC pins are brought out to Arduino-style expansion connectors. -These are 2 pins wide each, adding an additional row of expansion pins -per header compared to the standard Arduino layout. - -They are described in the tables in the following subsections. Since -pins are usually grouped by logical function in rows on these headers, -the odd- and even-numbered pins are listed in separate tables. The -"Port/bit" columns refer to the SoC PORT and GPIO peripheral -naming scheme, e.g. "E/13" means PORTE/GPIOE pin 13. - -See the schematic and chip reference manual for details. -(Documentation is available from the `OpenISA GitHub releases`_ page.) - -.. note:: - - Pins with peripheral functionality may also be muxed as GPIOs. - -**Top right expansion header (J1)** - -Odd/bottom pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -1 E/13 I2S_TX_BCLK -3 E/14 I2S_TX_FS -5 E/15 I2S_TXD -7 E/19 I2S_MCLK -9 E/16 I2S_RX_BCLK -11 E/21 SOF_OUT -13 E/17 I2S_RX_FS -15 E/18 I2S_RXD -=== ======== ================= - -Even/top pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -2 A/25 UART1_RX -4 A/26 UART1_TX -6 A/27 GPIO -8 B/13 PWM -10 B/14 GPIO -12 A/30 PWM -14 A/31 PWM/CMP -16 B/1 GPIO -=== ======== ================= - -**Top left expansion header (J2)** - -Odd/bottom pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -1 D/5 FLEXIO_D25 -3 D/4 FLEXIO_D24 -5 D/3 FLEXIO_D23 -7 D/2 FLEXIO_D22 -9 D/1 FLEXIO_D21 -11 D/0 FLEXIO_D20 -13 C/30 FLEXIO_D19 -15 C/29 FLEXIO_D18 -17 C/28 FLEXIO_D17 -19 B/29 FLEXIO_D16 -=== ======== ================= - -Even/top pins: - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -2 B/2 GPIO -4 B/3 PWM -6 B/6 SPI0_PCS2 -8 B/5 SPI0_SOUT -10 B/7 SPI0_SIN -12 B/4 SPI0_SCK -14 - GND -16 - AREF -18 C/9 I2C0_SDA -20 C/10 I2C0_SCL -=== ======== ================= - -**Bottom left expansion header (J3)** - -Note that the headers at the bottom of the board have odd-numbered -pins on the top, unlike the headers at the top of the board. - -Odd/top pins: - -=== ======== ==================== -Pin Port/bit Function -=== ======== ==================== -1 A/21 ARDUINO_EMVSIM_PD -3 A/20 ARDUINO_EMVSIM_IO -5 A/19 ARDUINO_EMVSIM_VCCEN -7 A/18 ARDUINO_EMVSIM_RST -9 A/17 ARDUINO_EMVSIM_CLK -11 B/17 FLEXIO_D7 -13 B/16 FLEXIO_D6 -15 B/15 FLEXIO_D5 -=== ======== ==================== - -Even/bottom pins: note that these are mostly power-related. - -=== ======== ================= -Pin Port/bit Function -=== ======== ================= -2 - SDA_GPIO0 -4 - BRD_IO_PER -6 - RST_SDA -8 - BRD_IO_PER -10 - P5V_INPUT -12 - GND -14 - GND -16 - P5-9V VIN -=== ======== ================= - -**Bottom right expansion header (J4)** - -Note that the headers at the bottom of the board have odd-numbered -pins on the top, unlike the headers at the top of the board. - -Odd/top pins: - -=== ======== ======================================== -Pin Port/bit Function -=== ======== ======================================== -1 - TAMPER2 -3 - TAMPER1/RTC_CLKOUT -5 - TAMPER0/RTC_WAKEUP_b -7 E/2 ADC0_SE19 -9 E/5 LPCMP1_IN2/LPCMP1_OUT -11 - DAC0_OUT/ADC0_SE16/LPCMP0_IN3/LPCMP1_IN3 -=== ======== ======================================== - -Even/bottom pins: - -=== ======== =========================================== -Pin Port/bit Function -=== ======== =========================================== -2 C/11 ADC0_SE6 -4 C/12 ADC0_SE7 -6 B/9 ADC0_SE3 -8 E/4 ADC0_SE21 -10 E/10 ADC0_SE19 (and E/10, I2C3_SDA via 0 Ohm DNP) -12 E/11 ADC0_SE20 (and E/11, I2C3_SCL via 0 Ohm DNP) -=== ======== =========================================== - -Additional Pins ---------------- - -For an up-to-date description of additional pins (such as buttons, -LEDs, etc.) supported by Zephyr, see the board DTS files in the Zephyr -source code, i.e. -:zephyr_file:`boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts` for RI5CY and -:zephyr_file:`boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts` for -ZERO-RISCY. - -See the schematic in the documentation available from the `OpenISA -GitHub releases`_ page for additional details. - -System Clocks -============= - -The RI5CY and ZERO-RISCY cores are configured to use the slow internal -reference clock (SIRC) as the clock source for an LPTMR peripheral to manage -the system timer, and the fast internal reference clock (FIRC) to generate a -48MHz core clock. - -Serial Port -=========== - -The USB connector at the top left of the board (near the RESET button) is -connected to an OpenSDA chip which provides a serial USB device. This is -connected to the LPUART0 peripheral which the RI5CY and ZERO-RISCY cores use by -default for console and logging. - -.. warning:: - - The OpenSDA chip cannot be used to flash or debug the RISC-V cores. - - See the next section for flash and debug instructions for the - RISC-V cores using an external JTAG dongle. - -Programming and Debugging -************************* - -.. _rv32m1-programming-hw: - -.. important:: - - To use this board, you will need: - - - a `SEGGER J-Link`_ debug probe to debug the RISC-V cores - - a J-Link `9-Pin Cortex-M Adapter`_ board and ribbon cable - - the SEGGER `J-Link Software and Documentation Pack`_ software - installed - - A JTAG dongle is not included with the board itself. - -Follow these steps to: - -#. Get a toolchain and OpenOCD -#. Set up the board for booting RI5CY -#. Compile a Zephyr application for the RI5CY core -#. Flash the application to your board -#. Debug the board using GDB - -.. _rv32m1-toolchain-openocd: - -Get the Toolchain and OpenOCD -============================= - -Before programming and debugging, you first need to get a GNU -toolchain and an OpenOCD build. There are vendor-specific versions of -each for the RV32M1 SoC\ [#toolchain_openocd]_. - -Option 1 (Recommended): Prebuilt Toolchain and OpenOCD ------------------------------------------------------- - -The following prebuilt toolchains and OpenOCD archives are available -on the `OpenISA GitHub releases`_ page: - -- :file:`Toolchain_Linux.tar.gz` -- :file:`Toolchain_Mac.tar.gz` -- :file:`Toolchain_Windows.zip` - -Download and extract the archive for your system, then extract the -toolchain and OpenOCD archives inside. - -Linux:: - - tar xvzf Toolchain_Linux.tar.gz - tar xvzf openocd.tar.gz - tar xvzf riscv32-unknown-elf-gcc.tar.gz - mv openocd ~/rv32m1-openocd - mv riscv32-unknown-elf-gcc ~ - -macOS (unfortunately, the OpenISA 1.0.0 release's Mac -:file:`riscv32-unknown-elf-gcc.tar.gz` file doesn't expand into a -:file:`riscv32-unknown-elf-gcc` directory, so it has to be created):: - - tar xvzf Toolchain_Mac.tar.gz - tar xvzf openocd.tar.gz - mkdir riscv32-unknown-elf-gcc - mv riscv32-unknown-elf-gcc.tar.gz riscv32-unknown-elf-gcc - cd riscv32-unknown-elf-gcc/ - tar xvzf riscv32-unknown-elf-gcc.tar.gz - cd .. - mv openocd ~/rv32m1-openocd - mv riscv32-unknown-elf-gcc ~ - -Windows: - -#. Extract :file:`Toolchain_Windows.zip` in the file manager -#. Extract the :file:`openocd.zip` and :file:`riscv32-unknown-elf-gcc.zip` files - in the resulting :file:`Toolchain_Windows` folder -#. Move the extracted :file:`openocd` folder to :file:`C:\\rv32m1-openocd` -#. Move the extracted :file:`riscv32-unknown-elf-gcc` folder to - :file:`C:\\riscv32-unknown-elf-gcc` - -For simplicity, this guide assumes: - -- You put the extracted toolchain at :file:`~/riscv32-unknown-elf-gcc` - on macOS or Linux, and :file:`C:\\riscv32-unknown-elf-gcc` on - Windows. -- You put the extracted OpenOCD binary at :file:`~/rv32m1-openocd` on - macOS or Linux, and the OpenOCD folder into :file:`C:\\rv32m1-openocd` - on Windows. - -You can put them elsewhere, but be aware: - -- If you put the toolchain somewhere else, you will need to change - the ``CROSS_COMPILE`` value described below accordingly. -- If you put OpenOCD somewhere else, you will need to change the - OpenOCD path in the flashing and debugging instructions below. -- Don't use installation directories with spaces anywhere in the path; - this won't work with Zephyr's build system. - -Option 2: Building Toolchain and OpenOCD From Source ----------------------------------------------------- - -See :ref:`rv32m1_vega_toolchain_build`. - -.. _rv32m1-vega-jtag: - -JTAG Setup -========== - -This section describes how to connect to your board via the J-Link -debugger and adapter board. See the :ref:`above information -` for details on required hardware. - -#. Connect the J-Link debugger through the adapter board to the - VEGAboard as shown in the figure. - - .. figure:: rv32m1_vega_jtag.jpg - :align: center - :alt: RV32M1-VEGA - - VEGAboard connected properly to J-Link debugger. - VEGAboard connector J55 should be used. Pin 1 is on the bottom left. - -#. Power the VEGAboard via USB. The OpenSDA connector at the top left - is recommended for UART access. - -#. Make sure your J-Link is connected to your computer via USB. - -One-Time Board Setup For Booting RI5CY or ZERO-RISCY -==================================================== - -Next, you'll need to make sure your board boots the RI5CY or ZERO-RISCY core. -**You only need to do this once.** - -The RV32M1 SoC on the VEGAboard has multiple cores, any of which can -be selected as the boot core. Before flashing and debugging, you'll -first make sure you're booting the right core. - -**Linux and macOS**: - -.. note:: - - Linux users: to run these commands as a normal user, you will need - to install the `60-openocd.rules`_ udev rules file (usually by - placing it in :file:`/etc/udev/rules.d`, then unplugging and - plugging the J-Link in again via USB). - -.. note:: - - These Zephyr-specific instructions differ slightly from the - equivalent SDK ones. The Zephyr OpenOCD configuration file does not - run ``init``, so you have to do it yourself as explained below. - -1. In one terminal, use OpenOCD to connect to the board:: - - ~/rv32m1-openocd -f boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg - - The output should look like this: - - .. code-block:: console - - $ ~/rv32m1-openocd -f boards/riscv/rv32m1_vega/support/openocd_rv32m1_vega_ri5cy.cfg - Open On-Chip Debugger 0.10.0+dev-00431-ge1ec3c7d (2018-10-31-07:29) - [...] - Info : Listening on port 3333 for gdb connections - Info : Listening on port 6666 for tcl connections - Info : Listening on port 4444 for telnet connections - -2. In another terminal, connect to OpenOCD's telnet server and execute - the ``init`` and ``ri5cy_boot`` commands **with the reset button on - the board (at top left) pressed down**:: - - $ telnet localhost 4444 - Trying 127.0.0.1... - Connected to localhost. - Escape character is '^]'. - Open On-Chip Debugger - > init - > ri5cy_boot - - To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with - ``zero_boot``. - - The reset button is at top left, as shown in the following figure. - - .. figure:: ri5cy_boot.jpg - :align: center - :alt: Reset button is pressed - - Now quit the telnet session in this terminal and exit OpenOCD in the - other terminal. - -3. Unplug your J-Link and VEGAboard, and plug them back in. - -**Windows**: - -In one cmd.exe prompt in the Zephyr directory:: - - C:\rv32m1-openocd\bin\openocd.exe rv32m1-openocd -f boards\riscv32\rv32m1_vega\support\openocd_rv32m1_vega_ri5cy.cfg - -In a telnet program of your choice: - -#. Connect to localhost port 4444 using telnet. -#. Run ``init`` and ``ri5cy_boot`` as shown above, with RESET held down. -#. Quit the OpenOCD and telnet sessions. -#. Unplug your J-Link and VEGAboard, and plug them back in. - - To boot the ZERO-RISCY core instead, replace ``ri5cy_boot`` above with - ``zero_boot``. - -Compiling a Program -=================== - -.. important:: - - These instructions assume you've set up a development system, - cloned the Zephyr repository, and installed Python dependencies as - described in the :ref:`getting_started`. - - You should also have already downloaded and installed the toolchain - and OpenOCD as described above in :ref:`rv32m1-toolchain-openocd`. - -The first step is to set up environment variables to point at your -toolchain and OpenOCD:: - - # Linux or macOS - export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile - export CROSS_COMPILE=~/riscv32-unknown-elf-gcc/bin/riscv32-unknown-elf- - - # Windows - set ZEPHYR_TOOLCHAIN_VARIANT=cross-compile - set CROSS_COMPILE=C:\riscv32-unknown-elf-gcc\bin\riscv32-unknown-elf- - -.. note:: - - The above only sets these variables for your current shell session. - You need to make sure this happens every time you use this board. - -Now let's compile the :ref:`hello_world` application. (You can try -others as well; see :ref:`samples-and-demos` for more.) - -.. We can't use zephyr-app-commands to provide build instructions - due to the below mentioned linker issue. - -Due to a toolchain `linker issue`_, you need to add an option setting -``CMAKE_REQUIRED_FLAGS`` when running CMake to generate a build system -(see :ref:`application` for information about Zephyr's build system). - -Linux and macOS (run this in a terminal from the Zephyr directory):: - - # Set up environment and create build directory: - source zephyr-env.sh - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :tool: cmake - :cd-into: - :board: rv32m1_vega_ri5cy - :gen-args: -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=/dev/null - :goals: build - -Windows (run this in a ``cmd`` prompt, from the Zephyr directory):: - - # Set up environment and create build directory - zephyr-env.cmd - cd samples\hello_world - mkdir build & cd build - - # Use CMake to generate a Ninja-based build system: - type NUL > empty.ld - cmake -GNinja -DBOARD=rv32m1_vega_ri5cy -DCMAKE_REQUIRED_FLAGS=-Wl,-dT=%cd%\empty.ld .. - - # Build the sample - ninja - -Flashing -======== - -.. note:: - - Make sure you've done the :ref:`JTAG setup `, and - that the VEGAboard's top left USB connector is connected to your - computer too (for UART access). - -.. note:: - - Linux users: to run these commands as a normal user, you will need - to install the `60-openocd.rules`_ udev rules file (usually by - placing it in :file:`/etc/udev/rules.d`, then unplugging and - plugging the J-Link in again via USB). - -Make sure you've followed the above instructions to set up your board -and build a program first. - -Since you need to use a special OpenOCD, the easiest way to flash is -by using :ref:`west flash ` instead of ``ninja -flash`` like you might see with other Zephyr documentation. - -Run these commands from the build directory where you ran ``ninja`` in -the above section. - -Linux and macOS:: - - # Don't use "~/rv32m1-openocd". It won't work. - west flash --openocd=$HOME/rv32m1-openocd - -Windows:: - - west flash --openocd=C:\rv32m1-openocd\bin\openocd.exe - -If you have problems: - -- Make sure you don't have another ``openocd`` process running in the - background. -- Unplug the boards and plug them back in. -- On Linux, make sure udev rules are installed, as described above. - -As an alternative, for manual steps to run OpenOCD and GDB to flash, -see the `SDK README`_. - -Debugging -========= - -.. note:: - - Make sure you've done the :ref:`JTAG setup `, and - that the VEGAboard's top left USB connector is connected to your - computer too (for UART access). - -.. note:: - - Linux users: to run these commands as a normal user, you will need - to install the `60-openocd.rules`_ udev rules file (usually by - placing it in :file:`/etc/udev/rules.d`, then unplugging and - plugging the J-Link in again via USB). - -Make sure you've followed the above instructions to set up your board -and build a program first. - -To debug with gdb:: - - # Linux, macOS - west debug --openocd=$HOME/rv32m1-openocd - - # Windows - west debug --openocd=C:\rv32m1-openocd\bin\openocd.exe - -Then, from the ``(gdb)`` prompt, follow these steps to halt the core, -load the binary (:file:`zephyr.elf`), and re-sync with the OpenOCD -server:: - - (gdb) monitor init - (gdb) monitor reset halt - (gdb) load - (gdb) monitor gdb_sync - (gdb) stepi - -You can then set breakpoints and debug using normal GDB commands. - -.. note:: - - GDB can get out of sync with the target if you execute commands - that reset it. To reset RI5CY and get GDB back in sync with it - without reloading the binary:: - - (gdb) monitor reset halt - (gdb) monitor gdb_sync - (gdb) stepi - -If you have problems: - -- Make sure you don't have another ``openocd`` process running in the - background. -- Unplug the boards and plug them back in. -- On Linux, make sure udev rules are installed, as described above. - -References -********** - -- OpenISA developer portal: http://open-isa.org -- `OpenISA GitHub releases`_: includes toolchain and OpenOCD - prebuilts, as well as documentation, such as the SoC datasheet and - reference manual, board schematic and user guides, etc. -- Base toolchain: `pulp-riscv-gnu-toolchain`_; extra toolchain patches: - `rv32m1_gnu_toolchain_patch`_ (only needed if building from source). -- OpenOCD repository: `rv32m1-openocd`_ (only needed if building from - source). -- Vendor SDK: `rv32m1_sdk_riscv`_. Contains HALs, non-Zephyr sample - applications, and information on using the board with Eclipse which - may be interesting when combined with the Eclipse Debugging - information in the :ref:`application`. - -.. _rv32m1_vega_toolchain_build: - -Appendix: Building Toolchain and OpenOCD from Source -**************************************************** - -.. note:: - - Toolchain and OpenOCD build instructions are provided for Linux and - macOS only. - - Instructions for building OpenOCD have only been verified on Linux. - -.. warning:: - - Don't use installation directories with spaces anywhere in - the path; this won't work with Zephyr's build system. - -Ubuntu 18.04 users need to install these additional dependencies:: - - sudo apt-get install autoconf automake autotools-dev curl libmpc-dev \ - libmpfr-dev libgmp-dev gawk build-essential bison \ - flex texinfo gperf libtool patchutils bc zlib1g-dev \ - libusb-1.0-0-dev libudev1 libudev-dev g++ - -Users of other Linux distributions need to install the above packages -with their system package manager. - -macOS users need to install dependencies with Homebrew:: - - brew install gawk gnu-sed gmp mpfr libmpc isl zlib - -The build toolchain is based on the `pulp-riscv-gnu-toolchain`_, with -some additional patches hosted in a separate repository, -`rv32m1_gnu_toolchain_patch`_. To build the toolchain, follow the -instructions in the ``rv32m1_gnu_toolchain_patch`` repository's -`readme.md`_ file to apply the patches, then run:: - - ./configure --prefix= --with-arch=rv32imc --with-cmodel=medlow --enable-multilib - make - -If you set ```` to -:file:`~/riscv32-unknown-elf-gcc`, you can use the above instructions -for setting ``CROSS_COMPILE`` when building Zephyr -applications. If you set it to something else, you will need to update -your ``CROSS_COMPILE`` setting accordingly. - -.. note:: - - Strangely, there is no separate ``make install`` step for the - toolchain. That is, the ``make`` invocation both builds and - installs the toolchain. This means ``make`` has to be run as root - if you want to set ``--prefix`` to a system directory such as - :file:`/usr/local` or :file:`/opt` on Linux. - -To build OpenOCD, clone the `rv32m1-openocd`_ repository, then run -these from the repository top level:: - - ./bootstrap - ./configure --prefix= - make - make install - -If ```` is :file:`~/rv32m1-openocd`, you -should set your OpenOCD path to :file:`~/rv32m1-openocd/bin/openocd` -in the above flash and debug instructions. - -.. _RI5CY: - https://github.com/pulp-platform/riscv -.. _ZERO-RISCY: - https://github.com/pulp-platform/zero-riscy -.. _PULP platform: - http://iis-projects.ee.ethz.ch/index.php/PULP - -.. _pulp-riscv-gnu-toolchain: - https://github.com/pulp-platform/pulp-riscv-gnu-toolchain -.. _rv32m1_gnu_toolchain_patch: - https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch -.. _rv32m1-openocd: - https://github.com/open-isa-rv32m1/rv32m1-openocd -.. _readme.md: - https://github.com/open-isa-rv32m1/rv32m1_gnu_toolchain_patch/blob/master/readme.md -.. _OpenISA GitHub releases: - https://github.com/open-isa-org/open-isa.org/releases -.. _rv32m1_sdk_riscv: - https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv -.. _linker issue: - https://github.com/pulp-platform/pulpino/issues/240 -.. _60-openocd.rules: - https://github.com/open-isa-rv32m1/rv32m1-openocd/blob/master/contrib/60-openocd.rules -.. _SEGGER J-Link: - https://www.segger.com/products/debug-probes/j-link/ -.. _9-Pin Cortex-M Adapter: - https://www.segger.com/products/debug-probes/j-link/accessories/adapters/9-pin-cortex-m-adapter/ -.. _J-Link Software and Documentation Pack: - https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack -.. _SDK README: - https://github.com/open-isa-rv32m1/rv32m1_sdk_riscv/blob/master/readme.md - -.. rubric:: Footnotes - -.. [#toolchain_openocd] - - For Linux users, the RISC-V toolchain in the :ref:`Zephyr SDK - ` may work, but it hasn't been thoroughly tested with this - SoC, and will not allow use of any available RISC-V ISA extensions. - - Support for the RV32M1 SoC is not currently available in the OpenOCD - upstream repository or the OpenOCD build in the Zephyr SDK. diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega.dtsi b/boards/riscv/rv32m1_vega/rv32m1_vega.dtsi deleted file mode 100644 index b416b0a4806d1d..00000000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega.dtsi +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright 2018 Foundries.io Ltd - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "rv32m1_vega-pinctrl.dtsi" -#include - -/ { - aliases { - led0 = &green_led; - led1 = &blue_led; - led2 = &red_led; - led3 = &sts_led; - pwm-led0 = &blue_pwm_led; - pwm-led1 = &green_pwm_led; - pwm-led2 = &red_pwm_led; - blue-pwm-led = &blue_pwm_led; - green-pwm-led = &green_pwm_led; - red-pwm-led = &red_pwm_led; - sw0 = &user_button_2; - sw1 = &user_button_3; - sw2 = &user_button_4; - sw3 = &user_button_5; - magn0 = &fxos8700; - accel0 = &fxos8700; - }; - - leds { - compatible = "gpio-leds"; - blue_led: led_0 { - gpios = <&gpioa 22 GPIO_ACTIVE_HIGH>; - label = "User LD1"; - }; - green_led: led_1 { - gpios = <&gpioa 23 GPIO_ACTIVE_HIGH>; - label = "User LD2"; - }; - red_led: led_2 { - gpios = <&gpioa 24 GPIO_ACTIVE_HIGH>; - label = "User LD3"; - }; - sts_led: led_3 { - gpios = <&gpioe 0 GPIO_ACTIVE_HIGH>; - label = "User LD4"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - blue_pwm_led: pwm_led_0 { - pwms = <&tpm2 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "User PWM LD1"; - }; - green_pwm_led: pwm_led_1 { - pwms = <&tpm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "User PWM LD2"; - }; - red_pwm_led: pwm_led_2 { - pwms = <&tpm2 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>; - label = "User PWM LD3"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - user_button_2: button_0 { - label = "User SW2"; - gpios = <&gpioa 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_3: button_1 { - label = "User SW3"; - gpios = <&gpioe 8 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_4: button_2 { - label = "User SW4"; - gpios = <&gpioe 9 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_5: button_3 { - label = "User SW5"; - gpios = <&gpioe 12 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpioc 11 0>, /* A0 */ - <1 0 &gpioc 12 0>, /* A1 */ - <2 0 &gpiob 9 0>, /* A2 */ - <3 0 &gpioe 4 0>, /* A3 */ - <4 0 &gpioe 10 0>, /* A4 */ - <5 0 &gpioe 11 0>, /* A5 */ - <6 0 &gpioa 25 0>, /* D0 */ - <7 0 &gpioa 26 0>, /* D1 */ - <8 0 &gpioa 27 0>, /* D2 */ - <9 0 &gpiob 13 0>, /* D3 */ - <10 0 &gpiob 14 0>, /* D4 */ - <11 0 &gpioa 30 0>, /* D5 */ - <12 0 &gpioa 31 0>, /* D6 */ - <13 0 &gpiob 1 0>, /* D7 */ - <14 0 &gpiob 2 0>, /* D8 */ - <15 0 &gpiob 3 0>, /* D9 */ - <16 0 &gpiob 6 0>, /* D10 */ - <17 0 &gpiob 5 0>, /* D11 */ - <18 0 &gpiob 7 0>, /* D12 */ - <19 0 &gpiob 4 0>, /* D13 */ - <20 0 &gpioc 9 0>, /* D14 */ - <21 0 &gpioc 10 0>; /* D15 */ - }; -}; - -arduino_serial: &lpuart1 { - pinctrl-0 = <&lpuart1_default>; - pinctrl-names = "default"; -}; - -&lpuart0 { - current-speed = <115200>; - status = "okay"; - pinctrl-0 = <&lpuart0_default>; - pinctrl-names = "default"; -}; - -arduino_i2c: &lpi2c0 { - status = "okay"; - pinctrl-0 = <&lpi2c0_default>; - pinctrl-names = "default"; -}; - -&lpi2c3 { - status = "okay"; - pinctrl-0 = <&lpi2c3_default>; - pinctrl-names = "default"; - - fxos8700: fxos8700@1e { - compatible = "nxp,fxos8700"; - reg = <0x1e>; - reset-gpios = <&gpioe 27 GPIO_ACTIVE_HIGH>; - int1-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>; - int2-gpios = <&gpioe 22 GPIO_ACTIVE_LOW>; - }; -}; - -arduino_spi: &lpspi0 { - status = "okay"; - pinctrl-0 = <&lpspi0_default>; - pinctrl-names = "default"; -}; - -&lpspi1 { - status = "okay"; - cs-gpios = <&gpiob 22 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&lpspi1_default>; - pinctrl-names = "default"; - - mx25r32: mx25r3235f@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <80000000>; - jedec-id = [c2 28 16]; - size = <33554432>; - }; -}; - -&tpm2 { - status = "okay"; - pinctrl-0 = <&tpm2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts deleted file mode 100644 index fb68675989c937..00000000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.dts +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright 2018 Foundries.io Ltd - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "openisa/rv32m1_ri5cy.dtsi" -#include "rv32m1_vega.dtsi" - -/ { - model = "OpenISA RV32M1 Vega RI5CY"; - compatible = "openisa,rv32m1"; - - chosen { - zephyr,sram = &m4_dtcm; - zephyr,flash = &m4_flash; - zephyr,console = &lpuart0; - zephyr,shell-uart = &lpuart0; - zephyr,uart-pipe = &lpuart0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - spi-flash0 = &mx25r32; - }; -}; - -&m4_flash { - /* - * For more information, see: - * http://docs.zephyrproject.org/latest/guides/dts/index.html - */ - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - slot0_partition: partition@0 { - label = "image-0"; - reg = <0x00000000 0x00069000>; - }; - slot1_partition: partition@69000 { - label = "image-1"; - reg = <0x00069000 0x00069000>; - }; - scratch_partition: partition@d2000 { - label = "image-scratch"; - reg = <0x000d2000 0x0001e000>; - }; - storage_partition: partition@f0000 { - label = "storage"; - reg = <0x000f0000 0x00004000>; - }; - boot_partition: partition@f4000 { - label = "mcuboot"; - reg = <0x000f4000 0x0000C000>; - }; - }; -}; diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml deleted file mode 100644 index cddd5e221e8f25..00000000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy.yaml +++ /dev/null @@ -1,15 +0,0 @@ -identifier: rv32m1_vega_ri5cy -name: RV32M1-VEGA (RI5CY) -type: mcu -arch: riscv -toolchain: - - cross-compile - - zephyr -supported: - - arduino_gpio - - arduino_i2c - - arduino_spi - - i2c - - pwm - - spi -vendor: openisa diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig b/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig deleted file mode 100644 index 51071efb902b1a..00000000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_ri5cy_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_OPENISA_RV32M1_RISCV32=y -CONFIG_SOC_OPENISA_RV32M1_RI5CY=y -CONFIG_BOARD_RV32M1_VEGA=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_MULTI_LEVEL_INTERRUPTS=y diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts deleted file mode 100644 index c59d7bd9b768c5..00000000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.dts +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright 2018 Foundries.io Ltd - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include "openisa/rv32m1_zero_riscy.dtsi" -#include "rv32m1_vega.dtsi" - -/ { - model = "OpenISA RV32M1 Vega Zero RISCY"; - compatible = "openisa,rv32m1"; - - chosen { - zephyr,sram = &m0_tcm; - zephyr,flash = &m0_flash; - zephyr,console = &lpuart0; - zephyr,uart-pipe = &lpuart0; - zephyr,code-partition = &zero_riscy_code_partition; - }; -}; diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml deleted file mode 100644 index 3ca9ac8c9e74b5..00000000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: rv32m1_vega_zero_riscy -name: RV32M1-VEGA (ZERO-RISCY) -type: mcu -arch: riscv -toolchain: - - cross-compile - - zephyr -supported: - - arduino_gpio - - arduino_i2c - - i2c - - pwm -vendor: openisa diff --git a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig b/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig deleted file mode 100644 index 627ed311846eb9..00000000000000 --- a/boards/riscv/rv32m1_vega/rv32m1_vega_zero_riscy_defconfig +++ /dev/null @@ -1,10 +0,0 @@ -CONFIG_SOC_OPENISA_RV32M1_RISCV32=y -CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY=y -CONFIG_BOARD_RV32M1_VEGA=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_MULTI_LEVEL_INTERRUPTS=y diff --git a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.board b/boards/riscv/sparkfun_red_v_things_plus/Kconfig.board deleted file mode 100644 index cc9e7b4f935d85..00000000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_SPARKFUN_RED_V_THINGS_PLUS - bool "SparkFun RED-V Things Plus board" - depends on SOC_SIFIVE_FREEDOM_E340 diff --git a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.defconfig b/boards/riscv/sparkfun_red_v_things_plus/Kconfig.defconfig deleted file mode 100644 index e505db59222f35..00000000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_SPARKFUN_RED_V_THINGS_PLUS - -config BOARD - default "sparkfun_red_v_things_plus" - -config HAS_FLASH_LOAD_OFFSET - default y - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) - -config FLASH_LOAD_OFFSET - default 0x0 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 - -endif diff --git a/boards/riscv/sparkfun_red_v_things_plus/board.cmake b/boards/riscv/sparkfun_red_v_things_plus/board.cmake deleted file mode 100644 index f339e968e86256..00000000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/board.cmake +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019 SiFive Inc. -# SPDX-License-Identifier: Apache-2.0 -board_runner_args(jlink "--device=FE310") -board_runner_args(jlink "--iface=JTAG") -board_runner_args(jlink "--speed=4000") -board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") -board_runner_args(jlink "--tool-opt=-autoconnect 1") -include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus_defconfig b/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus_defconfig deleted file mode 100644 index 8cf24ffbe09f6d..00000000000000 --- a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_SIFIVE_FREEDOM_E300=y -CONFIG_SOC_SIFIVE_FREEDOM_E340=y -CONFIG_BOARD_SPARKFUN_RED_V_THINGS_PLUS=y -CONFIG_GPIO=y -CONFIG_PINCTRL=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_SIFIVE_PORT_0=y -CONFIG_UART_CONSOLE=y -CONFIG_RISCV_CORE_E31=y -CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/riscv/stamp_c3/Kconfig.board b/boards/riscv/stamp_c3/Kconfig.board deleted file mode 100644 index 09ec15d6348295..00000000000000 --- a/boards/riscv/stamp_c3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack STAMP-C3 board configuration - -# Copyright 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_STAMP_C3 - bool "M5Stack STAMP-C3 Board" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_FX4 -endchoice diff --git a/boards/riscv/stamp_c3/Kconfig.defconfig b/boards/riscv/stamp_c3/Kconfig.defconfig deleted file mode 100644 index 911a8845d709e6..00000000000000 --- a/boards/riscv/stamp_c3/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# M5Stack STAMP-C3 board configuration - -# Copyright 2022 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "stamp_c3" - depends on BOARD_STAMP_C3 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -if BT - -choice BT_HCI_BUS_TYPE - default BT_ESP32 -endchoice - -endif # BT diff --git a/boards/riscv/stamp_c3/doc/index.rst b/boards/riscv/stamp_c3/doc/index.rst deleted file mode 100644 index 8da74e9e1d88ab..00000000000000 --- a/boards/riscv/stamp_c3/doc/index.rst +++ /dev/null @@ -1,205 +0,0 @@ -.. _stamp_c3: - -M5Stack STAMP-C3 -################## - -Overview -******** - -STAMP-C3 featuring ESPRESSIF ESP32-C3 RISC-V MCU with Wi-Fi connectivity -for IoT edge devices such as home appliances and Industrial Automation. - -For more details see the `M5Stack STAMP-C3`_ page. - -Supported Features -================== - -The STAMP-C3 board configuration supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| TWAI | on-chip | can_esp32_twai | -+-----------+------------+------------------+ - - -Prerequisites -************* - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: stamp_c3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: build - -The usual ``flash`` target will work with the ``stamp_c3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! stamp_c3 - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: stamp_c3 - :goals: debug - -References -********** - -.. target-notes:: - -.. _`M5Stack STAMP-C3`: https://docs.m5stack.com/en/core/stamp_c3 -.. _`ESP32C3 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf -.. _`ESP32C3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/stamp_c3/stamp_c3_defconfig b/boards/riscv/stamp_c3/stamp_c3_defconfig deleted file mode 100644 index 021a4e84162350..00000000000000 --- a/boards/riscv/stamp_c3/stamp_c3_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_STAMP_C3=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/riscv/titanium_ti60_f225/Kconfig.board b/boards/riscv/titanium_ti60_f225/Kconfig.board deleted file mode 100644 index bac70816b205cb..00000000000000 --- a/boards/riscv/titanium_ti60_f225/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TITANIUM_TI60_F225 - bool "Board with Efinix Sapphire riscv SoC" - depends on SOC_EFINIX_SAPPHIRE diff --git a/boards/riscv/titanium_ti60_f225/Kconfig.defconfig b/boards/riscv/titanium_ti60_f225/Kconfig.defconfig deleted file mode 100644 index 577c21b3d1a68f..00000000000000 --- a/boards/riscv/titanium_ti60_f225/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TITANIUM_TI60_F225 - -config BOARD - default "titanium_ti60_f225" - -endif # BOARD_TITANIUM_TI60_F225 diff --git a/boards/riscv/tlsr9518adk80d/Kconfig.board b/boards/riscv/tlsr9518adk80d/Kconfig.board deleted file mode 100644 index 971b34dc13b402..00000000000000 --- a/boards/riscv/tlsr9518adk80d/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_TLSR9518ADK80D - bool "Telink B91 Platform" - depends on SOC_TELINK_TLSR9518 diff --git a/boards/riscv/tlsr9518adk80d/Kconfig.defconfig b/boards/riscv/tlsr9518adk80d/Kconfig.defconfig deleted file mode 100644 index ce11f3aaabe2f6..00000000000000 --- a/boards/riscv/tlsr9518adk80d/Kconfig.defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_TLSR9518ADK80D - -config BOARD - default "tlsr9518adk80d" - -config SOC_FLASH_TELINK_B91 - default y if FLASH - -if BT - -# BLE Controller SDK from hal_telink requires -# Telink's toolchain with FPU support -config FPU - default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" - -config BT_HCI_ACL_FLOW_CONTROL - default n - -choice BT_HCI_BUS_TYPE - default BT_B91 -endchoice - -endif # BT - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition - -config FLASH_LOAD_OFFSET - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION - -# Buffer for image writter shall be less(multiple of access alignment) or -# equal to flash page. tlsr9518adk80d boards use external P25Q16 IC as -# flesh memory. Flash page size of the IC is 256 bytes. So that, it is -# maximum image writer buffer size for such kind of boards. -config IMG_BLOCK_BUF_SIZE - default 256 if MCUBOOT_IMG_MANAGER - -endif diff --git a/boards/riscv/tlsr9518adk80d/doc/index.rst b/boards/riscv/tlsr9518adk80d/doc/index.rst deleted file mode 100644 index 4bf62efdf782d7..00000000000000 --- a/boards/riscv/tlsr9518adk80d/doc/index.rst +++ /dev/null @@ -1,267 +0,0 @@ -.. _tlsr9518adk80d: - -Telink TLSR9518ADK80D -##################### - -Overview -******** - -The TLSR9518A Generic Starter Kit is a hardware platform which -can be used to verify the `Telink TLSR951x series chipset`_ and develop applications -for several 2.4 GHz air interface standards including Bluetooth 5.2 (Basic data -rate, Enhanced data rate, LE, Indoor positioning and BLE Mesh), -Zigbee 3.0, Homekit, 6LoWPAN, Thread and 2.4 Ghz proprietary. - -.. figure:: img/tlsr9518adk80d.jpg - :align: center - :alt: TLSR9518ADK80D - -More information about the board can be found at the `Telink B91 Generic Starter Kit Hardware Guide`_ website. - -Hardware -******** - -The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256 -KB SRAM (128 KB of Data Local Memory and 128 KB of Instruction Local Memory), external Flash memory, -stereo audio codec, 14 bit AUX ADC, analog and digital Microphone input, PWM, flexible IO interfaces, -and other peripheral blocks required for advanced IoT, hearable, and wearable devices. - -.. figure:: img/tlsr9518_block_diagram.jpg - :align: center - :alt: TLSR9518ADK80D_SOC - -The TLSR9518ADK80D default board configuration provides the following hardware components: - -- RF conducted antenna -- 1 MB External Flash memory with reset button -- Chip reset button -- Mini USB interface -- 4-wire JTAG -- 4 LEDs, Key matrix up to 4 keys -- 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path) -- Dual Digital microphone -- Stereo line-out - -Supported Features -================== - -The Zephyr TLSR9518ADK80D board configuration supports the following hardware features: - -+----------------+------------+------------------------------+ -| Interface | Controller | Driver/Component | -+================+============+==============================+ -| PLIC | on-chip | interrupt_controller | -+----------------+------------+------------------------------+ -| RISC-V Machine | on-chip | timer | -| Timer (32 KHz) | | | -+----------------+------------+------------------------------+ -| PINCTRL | on-chip | pinctrl | -+----------------+------------+------------------------------+ -| GPIO | on-chip | gpio | -+----------------+------------+------------------------------+ -| UART | on-chip | serial | -+----------------+------------+------------------------------+ -| PWM | on-chip | pwm | -+----------------+------------+------------------------------+ -| TRNG | on-chip | entropy | -+----------------+------------+------------------------------+ -| FLASH (MSPI) | on-chip | flash | -+----------------+------------+------------------------------+ -| RADIO | on-chip | Bluetooth, | -| | | ieee802154, OpenThread | -+----------------+------------+------------------------------+ -| SPI (Master) | on-chip | spi | -+----------------+------------+------------------------------+ -| I2C (Master) | on-chip | i2c | -+----------------+------------+------------------------------+ -| ADC | on-chip | adc | -+----------------+------------+------------------------------+ - -.. note:: - To support "button" example project PC3-KEY3 (J20-19, J20-20) jumper needs to be removed and KEY3 (J20-19) should be connected to VDD3_DCDC (J51-13) externally. - - For the rest example projects use the default jumpers configuration. - -Other hardware features and example projects are not supported yet. - -Limitations ------------ - -- Maximum 3 GPIO pins could be configured to generate interrupts simultaneously. All pins must be related to different ports and use different IRQ numbers. -- DMA mode is not supported by I2C, SPI and Serial Port. -- UART hardware flow control is not implemented. -- SPI Slave mode is not implemented. -- I2C Slave mode is not implemented. - -Default configuration and IOs -============================= - -System Clock ------------- - -The TLSR9518ADK80D board is configured to use the 24 MHz external crystal oscillator -with the on-chip PLL/DIV generating the 48 MHz system clock. -The following values also could be assigned to the system clock in the board DTS file -(``boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts``): - -- 16000000 -- 24000000 -- 32000000 -- 48000000 -- 64000000 -- 96000000 - -.. code-block:: - - &cpu0 { - clock-frequency = <48000000>; - }; - -PINs Configuration ------------------- - -The TLSR9518A SoC has five GPIO controllers (PORT_A to PORT_E), but only two are -currently enabled (PORT_B for LEDs control and PORT_C for buttons) in the board DTS file: - -- LED0 (blue): PB4, LED1 (green): PB5, LED2 (white): PB6, LED3 (red): PB7 -- Key Matrix SW0: PC2_PC3, SW1: PC2_PC1, SW2: PC0_PC3, SW3: PC0_PC1 - -Peripheral's pins on the SoC are mapped to the following GPIO pins in the -``boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts`` file: - -- UART0 TX: PB2, RX: PB3 -- UART1 TX: PC6, RX: PC7 -- PWM Channel 0: PB4 -- PSPI CS0: PC4, CLK: PC5, MISO: PC6, MOSI: PC7 -- HSPI CS0: PA1, CLK: PA2, MISO: PA3, MOSI: PA4 -- I2C SCL: PE1, SDA: PE3 - -Serial Port ------------ - -The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned to UART0. -The default settings are 115200 8N1. - -Programming and debugging -************************* - -Building -======== - -.. important:: - - These instructions assume you've set up a development environment as - described in the :ref:`getting_started`. - -To build applications using the default RISC-V toolchain from Zephyr SDK, just run the west build command. -Here is an example for the "hello_world" application. - -.. code-block:: console - - # From the root of the zephyr repository - west build -b tlsr9518adk80d samples/hello_world - -To use `Telink RISC-V Linux Toolchain`_, ``ZEPHYR_TOOLCHAIN_VARIANT`` and ``CROSS_COMPILE`` variables need to be set. -In addition ``CONFIG_FPU=y`` must be selected in ``boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig`` file since this -toolchain is compatible only with the float point unit usage. - -.. code-block:: console - - # Set Zephyr toolchain variant to cross-compile - export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile - # Specify the Telink RISC-V Toolchain location - export CROSS_COMPILE=~/toolchains/nds32le-elf-mculib-v5f/bin/riscv32-elf- - # From the root of the zephyr repository - west build -b tlsr9518adk80d samples/hello_world - -`Telink RISC-V Linux Toolchain`_ is available on the `Burning and Debugging Tools for TLSR9 Series in Linux`_ page. - -Open a serial terminal with the following settings: - -- Speed: 115200 -- Data: 8 bits -- Parity: None -- Stop bits: 1 - -Flash the board, reset and observe the following messages on the selected -serial port: - -.. code-block:: console - - *** Booting Zephyr OS version 2.5.0 *** - Hello World! tlsr9518adk80d - - -Flashing -======== - -To flash the TLSR9518ADK80D board see the sources below: - -- `Burning and Debugging Tools for all Series`_ -- `Burning and Debugging Tools for TLSR9 Series`_ -- `Burning and Debugging Tools for TLSR9 Series in Linux`_ - -It is also possible to use the west flash command, but additional steps are required to set it up: - -- Download `Telink RISC-V Linux Toolchain`_. The toolchain contains tools for the board flashing as well. -- Since the ICEman tool is created for the 32-bit OS version it is necessary to install additional packages in case of the 64-bit OS version. - -.. code-block:: console - - sudo dpkg --add-architecture i386 - sudo apt-get update - sudo apt-get install -y libc6:i386 libncurses5:i386 libstdc++6:i386 - -- Run the "ICEman.sh" script. - -.. code-block:: console - - # From the root of the {path to the Telink RISC-V Linux Toolchain}/ice repository - sudo ./ICEman.sh - -- Now you should be able to run the west flash command with the toolchain path specified (TELINK_TOOLCHAIN_PATH). - -.. code-block:: console - - west flash --telink-tools-path=$TELINK_TOOLCHAIN_PATH - -- You can also run the west flash command without toolchain path specification if add SPI_burn and ICEman to PATH. - -.. code-block:: console - - export PATH=$TELINK_TOOLCHAIN_PATH/flash/bin:"$PATH" - export PATH=$TELINK_TOOLCHAIN_PATH/ice:"$PATH" - -Debugging -========= - -This port supports UART debug and OpenOCD+GDB. The `west debug` command also supported. You may run -it in a simple way, like: - -.. code-block:: console - - west debug - -Or with additional arguments, like: - -.. code-block:: console - - west debug --gdb-port= --gdb-ex= - -Example: - -.. code-block:: console - - west debug --gdb-port=1111 --gdb-ex="-ex monitor reset halt -ex b main -ex continue" - -References -********** - -.. target-notes:: - -.. _Telink TLSR951x series chipset: https://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/ -.. _Telink B91 Generic Starter Kit Hardware Guide: https://wiki.telink-semi.cn/wiki/Hardware/B91_Generic_Starter_Kit_Hardware_Guide/ -.. _Telink RISC-V Linux Toolchain: https://wiki.telink-semi.cn/tools_and_sdk/Tools/IDE/telink_riscv_linux_toolchain.zip -.. _Burning and Debugging Tools for all Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-all-Series/ -.. _Burning and Debugging Tools for TLSR9 Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-TLSR9-Series/ -.. _Burning and Debugging Tools for TLSR9 Series in Linux: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/BDT_for_TLSR9_Series_in_Linux/ diff --git a/boards/riscv/xiao_esp32c3/Kconfig.board b/boards/riscv/xiao_esp32c3/Kconfig.board deleted file mode 100644 index f8a7e0ecb5b2ac..00000000000000 --- a/boards/riscv/xiao_esp32c3/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XIAO_ESP32C3 - bool "XIAO ESP32C3 Board" - depends on SOC_SERIES_ESP32C3 - -choice SOC_PART_NUMBER - default SOC_ESP32C3_FX4 -endchoice diff --git a/boards/riscv/xiao_esp32c3/Kconfig.defconfig b/boards/riscv/xiao_esp32c3/Kconfig.defconfig deleted file mode 100644 index 2852d11301d899..00000000000000 --- a/boards/riscv/xiao_esp32c3/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2022 Google LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "xiao_esp32c3" - depends on BOARD_XIAO_ESP32C3 - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/riscv/xiao_esp32c3/doc/index.rst b/boards/riscv/xiao_esp32c3/doc/index.rst deleted file mode 100644 index 18c56c3ff9bf5a..00000000000000 --- a/boards/riscv/xiao_esp32c3/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _xiao_esp32c3: - -XIAO ESP32C3 -############ - -Overview -******** - -Seeed Studio XIAO ESP32C3 is an IoT mini development board based on the -Espressif ESP32-C3 WiFi/Bluetooth dual-mode chip. - -For more details see the `Seeed Studio XIAO ESP32C3`_ wiki page. - -.. figure:: img/xiao_esp32c.jpg - :align: center - :alt: XIAO ESP32C3 - - XIAO ESP32C3 - -Hardware -******** - -This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It -has an USB-C port for programming and debugging, integrated battery charging -and an U.FL external antenna connector. It is based on a standard XIAO 14 pin -pinout. - -Supported Features -================== - -The XIAO ESP32C3 board configuration supports the following hardware features: - -+-----------+------------+------------------+ -| Interface | Controller | Driver/Component | -+===========+============+==================+ -| PMP | on-chip | arch/riscv | -+-----------+------------+------------------+ -| INTMTRX | on-chip | intc_esp32c3 | -+-----------+------------+------------------+ -| PINMUX | on-chip | pinctrl_esp32 | -+-----------+------------+------------------+ -| USB UART | on-chip | serial_esp32_usb | -+-----------+------------+------------------+ -| GPIO | on-chip | gpio_esp32 | -+-----------+------------+------------------+ -| UART | on-chip | uart_esp32 | -+-----------+------------+------------------+ -| I2C | on-chip | i2c_esp32 | -+-----------+------------+------------------+ -| SPI | on-chip | spi_esp32_spim | -+-----------+------------+------------------+ -| TWAI | on-chip | can_esp32_twai | -+-----------+------------+------------------+ - -Connections and IOs -=================== - -The board uses a standard XIAO pinout, the default pin mapping is the following: - -.. figure:: img/xiao_esp32c3_pinout.jpg - :align: center - :alt: XIAO ESP32C3 Pinout - - XIAO ESP32C3 Pinout - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: xiao_esp32c3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by Sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -For the :code:`Hello, world!` application, follow the instructions below. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32c3 - :goals: build flash - -Since the Zephyr console is by default on the `usb_serial` device, we use -the espressif monitor to view. - -.. code-block:: console - - $ west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! xiao_esp32c3 - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32c3 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32c3 - :goals: debug - -References -********** - -.. target-notes:: - -.. _`Seeed Studio XIAO ESP32C3`: https://wiki.seeedstudio.com/XIAO_ESP32C3_Getting_Started -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig b/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig deleted file mode 100644 index 0dc868fa60a934..00000000000000 --- a/boards/riscv/xiao_esp32c3/xiao_esp32c3_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_XIAO_ESP32C3=y -CONFIG_SOC_SERIES_ESP32C3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/ronoth/index.rst b/boards/ronoth/index.rst new file mode 100644 index 00000000000000..2c41a8c379c7cf --- /dev/null +++ b/boards/ronoth/index.rst @@ -0,0 +1,10 @@ +.. _boards-ronoth: + +Ronoth +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ronoth/lodev/Kconfig.defconfig b/boards/ronoth/lodev/Kconfig.defconfig new file mode 100644 index 00000000000000..23abc27cc1e667 --- /dev/null +++ b/boards/ronoth/lodev/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Ronoth LoDev board configuration +# Copyright (c) 2020/2021 Dean Weiten +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RONOTH_LODEV + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_RONOTH_LODEV diff --git a/boards/ronoth/lodev/Kconfig.ronoth_lodev b/boards/ronoth/lodev/Kconfig.ronoth_lodev new file mode 100644 index 00000000000000..a8f323fb3c9c07 --- /dev/null +++ b/boards/ronoth/lodev/Kconfig.ronoth_lodev @@ -0,0 +1,5 @@ +# Copyright (c) 2020/2021 Dean Weiten +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RONOTH_LODEV + select SOC_STM32L073XX diff --git a/boards/arm/ronoth_lodev/board.cmake b/boards/ronoth/lodev/board.cmake similarity index 100% rename from boards/arm/ronoth_lodev/board.cmake rename to boards/ronoth/lodev/board.cmake diff --git a/boards/ronoth/lodev/board.yml b/boards/ronoth/lodev/board.yml new file mode 100644 index 00000000000000..008f2e5a7f5b92 --- /dev/null +++ b/boards/ronoth/lodev/board.yml @@ -0,0 +1,5 @@ +board: + name: ronoth_lodev + vendor: ronoth + socs: + - name: stm32l073xx diff --git a/boards/arm/ronoth_lodev/doc/img/acsip_s76s.jpg b/boards/ronoth/lodev/doc/img/acsip_s76s.jpg similarity index 100% rename from boards/arm/ronoth_lodev/doc/img/acsip_s76s.jpg rename to boards/ronoth/lodev/doc/img/acsip_s76s.jpg diff --git a/boards/arm/ronoth_lodev/doc/img/lodev.jpg b/boards/ronoth/lodev/doc/img/lodev.jpg similarity index 100% rename from boards/arm/ronoth_lodev/doc/img/lodev.jpg rename to boards/ronoth/lodev/doc/img/lodev.jpg diff --git a/boards/arm/ronoth_lodev/doc/img/pinout.jpg b/boards/ronoth/lodev/doc/img/pinout.jpg similarity index 100% rename from boards/arm/ronoth_lodev/doc/img/pinout.jpg rename to boards/ronoth/lodev/doc/img/pinout.jpg diff --git a/boards/arm/ronoth_lodev/doc/index.rst b/boards/ronoth/lodev/doc/index.rst similarity index 100% rename from boards/arm/ronoth_lodev/doc/index.rst rename to boards/ronoth/lodev/doc/index.rst diff --git a/boards/arm/ronoth_lodev/doc/s76s.rst b/boards/ronoth/lodev/doc/s76s.rst similarity index 100% rename from boards/arm/ronoth_lodev/doc/s76s.rst rename to boards/ronoth/lodev/doc/s76s.rst diff --git a/boards/arm/ronoth_lodev/ronoth_lodev.dts b/boards/ronoth/lodev/ronoth_lodev.dts similarity index 100% rename from boards/arm/ronoth_lodev/ronoth_lodev.dts rename to boards/ronoth/lodev/ronoth_lodev.dts diff --git a/boards/arm/ronoth_lodev/ronoth_lodev.yaml b/boards/ronoth/lodev/ronoth_lodev.yaml similarity index 100% rename from boards/arm/ronoth_lodev/ronoth_lodev.yaml rename to boards/ronoth/lodev/ronoth_lodev.yaml diff --git a/boards/arm/ronoth_lodev/ronoth_lodev_defconfig b/boards/ronoth/lodev/ronoth_lodev_defconfig similarity index 77% rename from boards/arm/ronoth_lodev/ronoth_lodev_defconfig rename to boards/ronoth/lodev/ronoth_lodev_defconfig index 1e4ef45671f86a..ccccd7ca20fb55 100644 --- a/boards/arm/ronoth_lodev/ronoth_lodev_defconfig +++ b/boards/ronoth/lodev/ronoth_lodev_defconfig @@ -2,12 +2,6 @@ # Copyright (c) 2021 Dean Weiten # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L073XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/ruuvi/index.rst b/boards/ruuvi/index.rst new file mode 100644 index 00000000000000..1ef2779b5651d7 --- /dev/null +++ b/boards/ruuvi/index.rst @@ -0,0 +1,10 @@ +.. _boards-ruuvi: + +Ruuvi +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/ruuvi_ruuvitag/Kconfig b/boards/ruuvi/ruuvitag/Kconfig similarity index 100% rename from boards/arm/ruuvi_ruuvitag/Kconfig rename to boards/ruuvi/ruuvitag/Kconfig diff --git a/boards/ruuvi/ruuvitag/Kconfig.defconfig b/boards/ruuvi/ruuvitag/Kconfig.defconfig new file mode 100644 index 00000000000000..237d564c7462f2 --- /dev/null +++ b/boards/ruuvi/ruuvitag/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Ruuvi RuuviTag configuration + +# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_RUUVI_RUUVITAG + +config SPI + default y + +config BT_CTLR + default BT + +endif # BOARD_RUUVI_RUUVITAG diff --git a/boards/ruuvi/ruuvitag/Kconfig.ruuvi_ruuvitag b/boards/ruuvi/ruuvitag/Kconfig.ruuvi_ruuvitag new file mode 100644 index 00000000000000..29d7dfc5190978 --- /dev/null +++ b/boards/ruuvi/ruuvitag/Kconfig.ruuvi_ruuvitag @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_RUUVI_RUUVITAG + select SOC_NRF52832_QFAA diff --git a/boards/arm/ruuvi_ruuvitag/board.cmake b/boards/ruuvi/ruuvitag/board.cmake similarity index 100% rename from boards/arm/ruuvi_ruuvitag/board.cmake rename to boards/ruuvi/ruuvitag/board.cmake diff --git a/boards/ruuvi/ruuvitag/board.yml b/boards/ruuvi/ruuvitag/board.yml new file mode 100644 index 00000000000000..c8d45886d82b40 --- /dev/null +++ b/boards/ruuvi/ruuvitag/board.yml @@ -0,0 +1,5 @@ +board: + name: ruuvi_ruuvitag + vendor: ruuvi + socs: + - name: nrf52832 diff --git a/boards/arm/ruuvi_ruuvitag/doc/img/pinout.jpg b/boards/ruuvi/ruuvitag/doc/img/pinout.jpg similarity index 100% rename from boards/arm/ruuvi_ruuvitag/doc/img/pinout.jpg rename to boards/ruuvi/ruuvitag/doc/img/pinout.jpg diff --git a/boards/arm/ruuvi_ruuvitag/doc/img/ruuvitag.jpg b/boards/ruuvi/ruuvitag/doc/img/ruuvitag.jpg similarity index 100% rename from boards/arm/ruuvi_ruuvitag/doc/img/ruuvitag.jpg rename to boards/ruuvi/ruuvitag/doc/img/ruuvitag.jpg diff --git a/boards/ruuvi/ruuvitag/doc/index.rst b/boards/ruuvi/ruuvitag/doc/index.rst new file mode 100644 index 00000000000000..42348b8a38776b --- /dev/null +++ b/boards/ruuvi/ruuvitag/doc/index.rst @@ -0,0 +1,184 @@ +.. _ruuvi_ruuvitag: + +Ruuvi RuuviTag +############## + +Overview +******** + +RuuviTag is an advanced battery-operated open-source Bluetooth +enabled sensor beacon platform capable of sending temperature, humidity, +pressure, and motion information over Bluetooth Low Energy. + +.. figure:: img/ruuvitag.jpg + :align: center + :alt: RUUVI RuuviTag + + RUUVI RuuviTag (Credit: https://ruuvi.com/) + +More information about the board can be found at the +`ruuvitag website`_. + +Hardware +******** + +RuuviTag's have the following physical features: + +* Nordic Semiconductor nRF52832 System-on-Chip +* STMicroelectronics LIS2DH12 accelerometer +* Bosch BME 280 temperature + relative air humidity + air pressure sensor +* NFC™-A tag antenna +* 1000mAh CR2477 battery +* 2 buttons +* 1 Green LED +* 1 Red LED +* IP67 Enclosure +* Long range RF antenna + +Supported Features +================== + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ +| Humidity, | on-board | bme280 | +| Temp & Air| | | +| Pressure | | | ++-----------+------------+----------------------+ +| Acc | on-board | lis2dh12 | ++-----------+------------+----------------------+ + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.17 +* LED1 (green) = P0.19 + +Push buttons +------------ + +* BUTTON0 = SW1 = P0.13 + +Pin descriptions +---------------- + +.. figure:: img/pinout.jpg + :align: center + :alt: RUUVI Pinout + +* 2 = P0.29 = SPI_SCK +* 3 = P0.28 = SPI_MISO +* 10 = P0.04 = GPIO (can be used as a GPIO / ADC pin) +* 11 = P0.05 = GPIO (can be used as a GPIO / ADC pin) +* 12 = P0.25 = SPI_MOSI +* 13 = P0.19 = LED2 (green) / GPIO (can be used as a GPIO pin but the LED will blink) +* 14 = P0.17 = LED1 (red) / GPIO (can be used as a GPIO pin but the LED will blink) +* 15 = P0.13 = Button / GPIO (can be used as a GPIO pin) +* 16 = GND (Battery's negative contact) +* 17 = Battery's positive contact +* 18 = Battery's positive contact +* 19 = SWDIO +* 20 = SWDCLK +* 21 = P0.18 = SWO / GPIO (can be used as a GPIO pin) +* 22 = P0.21 = Reset / GPIO (can be used as a GPIO pin if no need to reset the device) +* 23 = GND (Battery's negative contact) +* 24 = P0.31 = GPIO (can be used as a GPIO / ADC pin) +* 25 = P0.30 = GPIO (can be used as a GPIO / ADC pin) + +GPIO = General Purpose Input Output pin + +P1 = Standard 10-pin ARM Cortex debug connector (on RuuviTag Rev.B1-B5) + +* 1 = VDD +* 2 = SWDIO +* 3 = GND (Battery's negative contact) +* 4 = SWDCLK +* 5 = GND (Battery's negative contact) +* 6 = SWO +* 7 = No Connect +* 8 = No Connect +* 9 = GND (Battery's negative contact) +* 10 = Reset + +P1 = TC2030 TagConnect (on RuuviTag Rev.B6) + +* 1 = Battery's positive contact +* 2 = SWDIO +* 3 = Reset +* 4 = SWDCLK +* 5 = GND (Battery's negative contact) +* 6 = SWO + + +Programming and Debugging +************************* + +Flashing +======== + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +The easiest way to flash Zephyr onto a RuuviTag requires an external Ruuvi DEVKIT. More information about the board can be found at the +`ruuvitag devkit`_. + +Once your tag is connected to the DEVKIT and connected to your PC, build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ruuvi_ruuvitag + :goals: build flash + +Advanced users may want to program the RuuviTag without the DEVKIT, this can be achieved via the SWDIO and SWDCLK pins located on the back of the RuuviTag. + +Debugging +========= + +If using the Ruuvi DEVKIT refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +Testing the LEDs and buttons on the RuuviTag +******************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in :file:`boards/ruuvi//ruuvi_ruuvitag/ruuvi_ruuvitag.dts`. + +References +********** + +.. target-notes:: + +.. _ruuvitag website: https://ruuvi.com +.. _ruuvitag datasheet: https://ruuvi.com/files/ruuvitag-tech-spec-2019-7.pdf +.. _ruuvitag devkit: https://lab.ruuvi.com/devshield/ diff --git a/boards/arm/raytac_mdbt50q_db_40_nrf52840/pre_dt_board.cmake b/boards/ruuvi/ruuvitag/pre_dt_board.cmake similarity index 100% rename from boards/arm/raytac_mdbt50q_db_40_nrf52840/pre_dt_board.cmake rename to boards/ruuvi/ruuvitag/pre_dt_board.cmake diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi similarity index 100% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag-pinctrl.dtsi diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.dts b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts similarity index 100% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.dts rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag.dts diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.yaml b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml similarity index 100% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag.yaml rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml diff --git a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag_defconfig b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig similarity index 76% rename from boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag_defconfig rename to boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig index 08403e5d814b46..9ece16276d2780 100644 --- a/boards/arm/ruuvi_ruuvitag/ruuvi_ruuvitag_defconfig +++ b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2020 Ruuvi Innovations Ltd (Oy) # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_RUUVI_RUUVITAG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/sc/index.rst b/boards/sc/index.rst new file mode 100644 index 00000000000000..1347be14086023 --- /dev/null +++ b/boards/sc/index.rst @@ -0,0 +1,10 @@ +.. _boards-space-cubics: + +Space Cubics +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sc/scobc_module1/Kconfig.defconfig b/boards/sc/scobc_module1/Kconfig.defconfig new file mode 100644 index 00000000000000..35aae16914772d --- /dev/null +++ b/boards/sc/scobc_module1/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Space Cubics OBC module 1 + +# Copyright (c) 2021 Space Cubics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SCOBC_MODULE1 + +config CPU_CORTEX_M_HAS_SYSTICK + default y + +config CPU_HAS_ARM_MPU + default y + +config NUM_IRQS + default 7 + +endif # BOARD_SCOBC_MODULE1 diff --git a/boards/sc/scobc_module1/Kconfig.scobc_module1 b/boards/sc/scobc_module1/Kconfig.scobc_module1 new file mode 100644 index 00000000000000..d8a7a3e5ac7815 --- /dev/null +++ b/boards/sc/scobc_module1/Kconfig.scobc_module1 @@ -0,0 +1,7 @@ +# Space Cubics OBC module 1 configuration + +# Copyright (c) 2021 Space Cubics, LLC. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SCOBC_MODULE1 + select SOC_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/boards/sc/scobc_module1/board.cmake b/boards/sc/scobc_module1/board.cmake new file mode 100644 index 00000000000000..a0f4d5f5fedd3f --- /dev/null +++ b/boards/sc/scobc_module1/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd "--use-elf" "--config=${BOARD_DIR}/support/openocd-ftdi.cfg") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/sc/scobc_module1/board.yml b/boards/sc/scobc_module1/board.yml new file mode 100644 index 00000000000000..d8f83a733acf6b --- /dev/null +++ b/boards/sc/scobc_module1/board.yml @@ -0,0 +1,5 @@ +board: + name: scobc_module1 + vendor: spacecubics + socs: + - name: designstart_fpga_cortex_m3 diff --git a/boards/arm/scobc_module1/doc/index.rst b/boards/sc/scobc_module1/doc/index.rst similarity index 100% rename from boards/arm/scobc_module1/doc/index.rst rename to boards/sc/scobc_module1/doc/index.rst diff --git a/boards/arm/scobc_module1/doc/scobc.jpg b/boards/sc/scobc_module1/doc/scobc.jpg similarity index 100% rename from boards/arm/scobc_module1/doc/scobc.jpg rename to boards/sc/scobc_module1/doc/scobc.jpg diff --git a/boards/arm/scobc_module1/dts/bindings/sc,hrmem.yaml b/boards/sc/scobc_module1/dts/bindings/sc,hrmem.yaml similarity index 100% rename from boards/arm/scobc_module1/dts/bindings/sc,hrmem.yaml rename to boards/sc/scobc_module1/dts/bindings/sc,hrmem.yaml diff --git a/boards/arm/scobc_module1/scobc_module1.dts b/boards/sc/scobc_module1/scobc_module1.dts similarity index 100% rename from boards/arm/scobc_module1/scobc_module1.dts rename to boards/sc/scobc_module1/scobc_module1.dts diff --git a/boards/arm/scobc_module1/scobc_module1.yaml b/boards/sc/scobc_module1/scobc_module1.yaml similarity index 100% rename from boards/arm/scobc_module1/scobc_module1.yaml rename to boards/sc/scobc_module1/scobc_module1.yaml diff --git a/boards/sc/scobc_module1/scobc_module1_defconfig b/boards/sc/scobc_module1/scobc_module1_defconfig new file mode 100644 index 00000000000000..f06a7a1dee82b2 --- /dev/null +++ b/boards/sc/scobc_module1/scobc_module1_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 +CONFIG_ARM_MPU=n + +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_XIP=n +CONFIG_FLASH_SIZE=0 +CONFIG_FLASH_BASE_ADDRESS=0x0 diff --git a/boards/arm/scobc_module1/support/akizuki-m-02990.cfg b/boards/sc/scobc_module1/support/akizuki-m-02990.cfg similarity index 100% rename from boards/arm/scobc_module1/support/akizuki-m-02990.cfg rename to boards/sc/scobc_module1/support/akizuki-m-02990.cfg diff --git a/boards/arm/scobc_module1/support/openocd-ft232r.cfg b/boards/sc/scobc_module1/support/openocd-ft232r.cfg similarity index 100% rename from boards/arm/scobc_module1/support/openocd-ft232r.cfg rename to boards/sc/scobc_module1/support/openocd-ft232r.cfg diff --git a/boards/arm/scobc_module1/support/openocd-ftdi.cfg b/boards/sc/scobc_module1/support/openocd-ftdi.cfg similarity index 100% rename from boards/arm/scobc_module1/support/openocd-ftdi.cfg rename to boards/sc/scobc_module1/support/openocd-ftdi.cfg diff --git a/boards/arm/scobc_module1/support/openocd.cfg b/boards/sc/scobc_module1/support/openocd.cfg similarity index 100% rename from boards/arm/scobc_module1/support/openocd.cfg rename to boards/sc/scobc_module1/support/openocd.cfg diff --git a/boards/arm/scobc_module1/support/scobc-module1.cfg b/boards/sc/scobc_module1/support/scobc-module1.cfg similarity index 100% rename from boards/arm/scobc_module1/support/scobc-module1.cfg rename to boards/sc/scobc_module1/support/scobc-module1.cfg diff --git a/boards/arm/faze/CMakeLists.txt b/boards/seagate/faze/CMakeLists.txt similarity index 100% rename from boards/arm/faze/CMakeLists.txt rename to boards/seagate/faze/CMakeLists.txt diff --git a/boards/seagate/faze/Kconfig.faze b/boards/seagate/faze/Kconfig.faze new file mode 100644 index 00000000000000..13e0852f58222c --- /dev/null +++ b/boards/seagate/faze/Kconfig.faze @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Seagate Technology LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_FAZE + select SOC_LPC11U67 diff --git a/boards/arm/faze/board.cmake b/boards/seagate/faze/board.cmake similarity index 100% rename from boards/arm/faze/board.cmake rename to boards/seagate/faze/board.cmake diff --git a/boards/seagate/faze/board.yml b/boards/seagate/faze/board.yml new file mode 100644 index 00000000000000..bd672fe549fca6 --- /dev/null +++ b/boards/seagate/faze/board.yml @@ -0,0 +1,5 @@ +board: + name: faze + vendor: seagate + socs: + - name: lpc11u67 diff --git a/boards/arm/faze/doc/firecuda-gaming-ssd.jpg b/boards/seagate/faze/doc/firecuda-gaming-ssd.jpg similarity index 100% rename from boards/arm/faze/doc/firecuda-gaming-ssd.jpg rename to boards/seagate/faze/doc/firecuda-gaming-ssd.jpg diff --git a/boards/arm/faze/doc/index.rst b/boards/seagate/faze/doc/index.rst similarity index 100% rename from boards/arm/faze/doc/index.rst rename to boards/seagate/faze/doc/index.rst diff --git a/boards/arm/faze/faze-pinctrl.dtsi b/boards/seagate/faze/faze-pinctrl.dtsi similarity index 100% rename from boards/arm/faze/faze-pinctrl.dtsi rename to boards/seagate/faze/faze-pinctrl.dtsi diff --git a/boards/arm/faze/faze.dts b/boards/seagate/faze/faze.dts similarity index 100% rename from boards/arm/faze/faze.dts rename to boards/seagate/faze/faze.dts diff --git a/boards/arm/faze/faze.yaml b/boards/seagate/faze/faze.yaml similarity index 100% rename from boards/arm/faze/faze.yaml rename to boards/seagate/faze/faze.yaml diff --git a/boards/arm/faze/faze_defconfig b/boards/seagate/faze/faze_defconfig similarity index 87% rename from boards/arm/faze/faze_defconfig rename to boards/seagate/faze/faze_defconfig index f6dc6fafb97dd0..257f6fb3c619e5 100644 --- a/boards/arm/faze/faze_defconfig +++ b/boards/seagate/faze/faze_defconfig @@ -7,8 +7,6 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_GPIO=y CONFIG_BUILD_OUTPUT_HEX=y -CONFIG_SOC_SERIES_LPC11U6X=y -CONFIG_SOC_LPC11U67=y CONFIG_MAIN_STACK_SIZE=512 CONFIG_ISR_STACK_SIZE=768 CONFIG_CLOCK_CONTROL_LPC11U6X_ENABLE_SRAM1=y diff --git a/boards/arm/lpcxpresso11u68/pre_dt_board.cmake b/boards/seagate/faze/pre_dt_board.cmake similarity index 100% rename from boards/arm/lpcxpresso11u68/pre_dt_board.cmake rename to boards/seagate/faze/pre_dt_board.cmake diff --git a/boards/arm/faze/support/openocd.cfg b/boards/seagate/faze/support/openocd.cfg similarity index 100% rename from boards/arm/faze/support/openocd.cfg rename to boards/seagate/faze/support/openocd.cfg diff --git a/boards/seagate/index.rst b/boards/seagate/index.rst new file mode 100644 index 00000000000000..6232f7d2a115d0 --- /dev/null +++ b/boards/seagate/index.rst @@ -0,0 +1,10 @@ +.. _boards-seagate: + +Seagate Technology PLC +###################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/seagate/legend/Kconfig.defconfig b/boards/seagate/legend/Kconfig.defconfig new file mode 100644 index 00000000000000..ac77ec7855e1e8 --- /dev/null +++ b/boards/seagate/legend/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Legend board family configuration + +# Copyright (c) 2021, Seagate Technology LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_LEGEND + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_LEGEND diff --git a/boards/seagate/legend/Kconfig.legend b/boards/seagate/legend/Kconfig.legend new file mode 100644 index 00000000000000..68ee4b4d56be44 --- /dev/null +++ b/boards/seagate/legend/Kconfig.legend @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Seagate Technology +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LEGEND + select SOC_STM32F070XB diff --git a/boards/arm/legend/board.cmake b/boards/seagate/legend/board.cmake similarity index 100% rename from boards/arm/legend/board.cmake rename to boards/seagate/legend/board.cmake diff --git a/boards/seagate/legend/board.yml b/boards/seagate/legend/board.yml new file mode 100644 index 00000000000000..0c100284bdeed2 --- /dev/null +++ b/boards/seagate/legend/board.yml @@ -0,0 +1,7 @@ +board: + name: legend + vendor: seagate + revision: + format: custom + socs: + - name: stm32f070xb diff --git a/boards/arm/legend/doc/img/firecuda_gaming_hard_drive.jpg b/boards/seagate/legend/doc/img/firecuda_gaming_hard_drive.jpg similarity index 100% rename from boards/arm/legend/doc/img/firecuda_gaming_hard_drive.jpg rename to boards/seagate/legend/doc/img/firecuda_gaming_hard_drive.jpg diff --git a/boards/arm/legend/doc/img/firecuda_gaming_hub.jpg b/boards/seagate/legend/doc/img/firecuda_gaming_hub.jpg similarity index 100% rename from boards/arm/legend/doc/img/firecuda_gaming_hub.jpg rename to boards/seagate/legend/doc/img/firecuda_gaming_hub.jpg diff --git a/boards/arm/legend/doc/index.rst b/boards/seagate/legend/doc/index.rst similarity index 100% rename from boards/arm/legend/doc/index.rst rename to boards/seagate/legend/doc/index.rst diff --git a/boards/arm/legend/legend.dts b/boards/seagate/legend/legend.dts similarity index 100% rename from boards/arm/legend/legend.dts rename to boards/seagate/legend/legend.dts diff --git a/boards/seagate/legend/legend_defconfig b/boards/seagate/legend/legend_defconfig new file mode 100644 index 00000000000000..8bb683ce992eb3 --- /dev/null +++ b/boards/seagate/legend/legend_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Clock Control +CONFIG_CLOCK_CONTROL=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/legend/legend_25hdd.overlay b/boards/seagate/legend/legend_stm32f070xb_25hdd.overlay similarity index 100% rename from boards/arm/legend/legend_25hdd.overlay rename to boards/seagate/legend/legend_stm32f070xb_25hdd.overlay diff --git a/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml b/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml new file mode 100644 index 00000000000000..a9eb85aee47a28 --- /dev/null +++ b/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml @@ -0,0 +1,20 @@ +identifier: legend@25hdd +name: Legend +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: seagate diff --git a/boards/arm/legend/legend_25ssd.overlay b/boards/seagate/legend/legend_stm32f070xb_25ssd.overlay similarity index 100% rename from boards/arm/legend/legend_25ssd.overlay rename to boards/seagate/legend/legend_stm32f070xb_25ssd.overlay diff --git a/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml b/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml new file mode 100644 index 00000000000000..db494bd878cb86 --- /dev/null +++ b/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml @@ -0,0 +1,20 @@ +identifier: legend@25ssd +name: Legend +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: seagate diff --git a/boards/arm/legend/legend_35.overlay b/boards/seagate/legend/legend_stm32f070xb_35.overlay similarity index 100% rename from boards/arm/legend/legend_35.overlay rename to boards/seagate/legend/legend_stm32f070xb_35.overlay diff --git a/boards/seagate/legend/legend_stm32f070xb_35.yaml b/boards/seagate/legend/legend_stm32f070xb_35.yaml new file mode 100644 index 00000000000000..37ed59788d9bba --- /dev/null +++ b/boards/seagate/legend/legend_stm32f070xb_35.yaml @@ -0,0 +1,20 @@ +identifier: legend@35 +name: Legend +type: mcu +arch: arm +ram: 16 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - i2c + - pwm + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: seagate diff --git a/boards/arm/legend/revision.cmake b/boards/seagate/legend/revision.cmake similarity index 100% rename from boards/arm/legend/revision.cmake rename to boards/seagate/legend/revision.cmake diff --git a/boards/arm/legend/support/openocd.cfg b/boards/seagate/legend/support/openocd.cfg similarity index 100% rename from boards/arm/legend/support/openocd.cfg rename to boards/seagate/legend/support/openocd.cfg diff --git a/boards/seco/index.rst b/boards/seco/index.rst new file mode 100644 index 00000000000000..c38b58dc14d892 --- /dev/null +++ b/boards/seco/index.rst @@ -0,0 +1,10 @@ +.. _boards-seco: + +SECO SpA +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/seco/stm32f3_seco_d23/Kconfig.stm32f3_seco_d23 b/boards/seco/stm32f3_seco_d23/Kconfig.stm32f3_seco_d23 new file mode 100644 index 00000000000000..0c8590e470def6 --- /dev/null +++ b/boards/seco/stm32f3_seco_d23/Kconfig.stm32f3_seco_d23 @@ -0,0 +1,5 @@ +# Copyright (c) 2022, SECO Spa +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F3_SECO_D23 + select SOC_STM32F302XC diff --git a/boards/arm/stm32f3_seco_d23/board.cmake b/boards/seco/stm32f3_seco_d23/board.cmake similarity index 100% rename from boards/arm/stm32f3_seco_d23/board.cmake rename to boards/seco/stm32f3_seco_d23/board.cmake diff --git a/boards/seco/stm32f3_seco_d23/board.yml b/boards/seco/stm32f3_seco_d23/board.yml new file mode 100644 index 00000000000000..a7976211a2ce0b --- /dev/null +++ b/boards/seco/stm32f3_seco_d23/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f3_seco_d23 + vendor: seco + socs: + - name: stm32f302xc diff --git a/boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg b/boards/seco/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg similarity index 100% rename from boards/arm/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg rename to boards/seco/stm32f3_seco_d23/doc/img/stm32f3_seco_d23.jpg diff --git a/boards/arm/stm32f3_seco_d23/doc/index.rst b/boards/seco/stm32f3_seco_d23/doc/index.rst similarity index 100% rename from boards/arm/stm32f3_seco_d23/doc/index.rst rename to boards/seco/stm32f3_seco_d23/doc/index.rst diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.dts similarity index 100% rename from boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.dts rename to boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.dts diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml similarity index 100% rename from boards/arm/stm32f3_seco_d23/stm32f3_seco_d23.yaml rename to boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml diff --git a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig similarity index 89% rename from boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig rename to boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig index 344746567adfb1..9432c4e814930c 100644 --- a/boards/arm/stm32f3_seco_d23/stm32f3_seco_d23_defconfig +++ b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23_defconfig @@ -3,9 +3,6 @@ # # Copyright (c) 2022, SECO Spa -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F302XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f3_seco_d23/support/openocd.cfg b/boards/seco/stm32f3_seco_d23/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f3_seco_d23/support/openocd.cfg rename to boards/seco/stm32f3_seco_d23/support/openocd.cfg diff --git a/boards/seeed/index.rst b/boards/seeed/index.rst new file mode 100644 index 00000000000000..dad6340153034b --- /dev/null +++ b/boards/seeed/index.rst @@ -0,0 +1,10 @@ +.. _boards-seeed: + +Seeed Technology Co., Ltd +######################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board b/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board new file mode 100644 index 00000000000000..691f4e748a2b66 --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/Kconfig.lora_e5_dev_board @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LORA_E5_DEV_BOARD + select SOC_STM32WLE5XX diff --git a/boards/seeed/lora_e5_dev_board/board.cmake b/boards/seeed/lora_e5_dev_board/board.cmake new file mode 100644 index 00000000000000..07d09a3aba0ea9 --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/board.cmake @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2021 Thomas Stranger + +board_runner_args(pyocd "--target=stm32wle5jcix") +board_runner_args(pyocd "--flash-opt=-O reset_type=hw") +board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset") +board_runner_args(jlink "--device=STM32WLE5JC" "--speed=4000" "--reset-after-load") +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") +board_runner_args(blackmagicprobe "--connect-rst") + +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake) diff --git a/boards/seeed/lora_e5_dev_board/board.yml b/boards/seeed/lora_e5_dev_board/board.yml new file mode 100644 index 00000000000000..b6691948f2b02c --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/board.yml @@ -0,0 +1,5 @@ +board: + name: lora_e5_dev_board + vendor: seeed + socs: + - name: stm32wle5xx diff --git a/boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg b/boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg similarity index 100% rename from boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg rename to boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board.jpg diff --git a/boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg b/boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg similarity index 100% rename from boards/arm/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg rename to boards/seeed/lora_e5_dev_board/doc/img/lora_e5_dev_board_pinout.jpg diff --git a/boards/arm/lora_e5_dev_board/doc/lora_e5_dev_board.rst b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst similarity index 97% rename from boards/arm/lora_e5_dev_board/doc/lora_e5_dev_board.rst rename to boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst index c3c91fc8f741bb..039c2addbf07c8 100644 --- a/boards/arm/lora_e5_dev_board/doc/lora_e5_dev_board.rst +++ b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst @@ -111,10 +111,9 @@ features: Other hardware features are not yet supported on this Zephyr port. -The default configuration can be found in the defconfig and dts files: - -- :zephyr_file:`boards/arm/lora_e5_dev_board/lora_e5_dev_board_defconfig` -- :zephyr_file:`boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts` +The default configuration can be found in: +- :zephyr_file:`boards/seeed_studio/lora_e5_dev_board/lora_e5_dev_board_defconfig` +- :zephyr_file:`boards/seeed_studio/lora_e5_dev_board/lora_e5_dev_board.dts` Connections and IOs @@ -215,7 +214,7 @@ set the RDP option byte to ``AA``, or use the STM32_Programmer_CLI passing the ``--readunprotect`` command to perform this read protection regression. The RDP level 1 to RDP level 0 regression will erase the factory programmed AT -firmware, from which seeed has neither released the source code nor a binary. +firmware, from which seeed studio has neither released the source code nor a binary. Also, note that on the module the ``BOOT0`` pin of the SOC is not accessible, so the system bootloader will only be executed if configured in the option bytes. diff --git a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts similarity index 99% rename from boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts rename to boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts index 02602825712fbe..64ea2f84726da2 100644 --- a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.dts +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include / { diff --git a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.yaml b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml similarity index 91% rename from boards/arm/lora_e5_dev_board/lora_e5_dev_board.yaml rename to boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml index 446bc1934cb06b..dede51f8125269 100644 --- a/boards/arm/lora_e5_dev_board/lora_e5_dev_board.yaml +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml @@ -17,4 +17,4 @@ supported: - uart - watchdog - lora -vendor: seeed +vendor: seeed studio diff --git a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig new file mode 100644 index 00000000000000..17aa77ac7f85bf --- /dev/null +++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2021 Thomas Stranger + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable regulator for the power-rails +CONFIG_REGULATOR=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/lora_e5_dev_board/support/openocd.cfg b/boards/seeed/lora_e5_dev_board/support/openocd.cfg similarity index 100% rename from boards/arm/lora_e5_dev_board/support/openocd.cfg rename to boards/seeed/lora_e5_dev_board/support/openocd.cfg diff --git a/boards/seeed/lora_e5_mini/Kconfig.lora_e5_mini b/boards/seeed/lora_e5_mini/Kconfig.lora_e5_mini new file mode 100644 index 00000000000000..47be610d84537c --- /dev/null +++ b/boards/seeed/lora_e5_mini/Kconfig.lora_e5_mini @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LORA_E5_MINI + select SOC_STM32WLE5XX diff --git a/boards/arm/lora_e5_dev_board/board.cmake b/boards/seeed/lora_e5_mini/board.cmake similarity index 100% rename from boards/arm/lora_e5_dev_board/board.cmake rename to boards/seeed/lora_e5_mini/board.cmake diff --git a/boards/seeed/lora_e5_mini/board.yml b/boards/seeed/lora_e5_mini/board.yml new file mode 100644 index 00000000000000..1643caea3c19cf --- /dev/null +++ b/boards/seeed/lora_e5_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: lora_e5_mini + vendor: seeed + socs: + - name: stm32wle5xx diff --git a/boards/arm/lora_e5_mini/doc/img/lora_e5_mini.jpg b/boards/seeed/lora_e5_mini/doc/img/lora_e5_mini.jpg similarity index 100% rename from boards/arm/lora_e5_mini/doc/img/lora_e5_mini.jpg rename to boards/seeed/lora_e5_mini/doc/img/lora_e5_mini.jpg diff --git a/boards/arm/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg b/boards/seeed/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg similarity index 100% rename from boards/arm/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg rename to boards/seeed/lora_e5_mini/doc/img/lora_e5_mini_pinout.jpg diff --git a/boards/seeed/lora_e5_mini/doc/index.rst b/boards/seeed/lora_e5_mini/doc/index.rst new file mode 100644 index 00000000000000..0b4120f2c8c1fe --- /dev/null +++ b/boards/seeed/lora_e5_mini/doc/index.rst @@ -0,0 +1,226 @@ +.. _lora_e5_mini: + +Seeed Studio LoRa-E5 mini +######################### + +Overview +******** + +LoRa-E5 mini is a compacted-sized development board suitable for the rapid +testing and building of small-sized LoRa device, exposing all capabilities of +Seeed Studio LoRa-E5 STM32WLE5JC module. + +.. image:: img/lora_e5_mini.jpg + :align: center + :alt: LoRa-E5 mini + +Hardware +******** + +The boards' LoRa-E5 Module packages a STM32WLE5JC SOC, a 32MHz TCXO, +and a 32.768kHz crystal oscillator in a 28-pin SMD package. +This STM32WLEJC SOC is powered by ARM Cortex-M4 core and integrates Semtech +SX126X LoRa IP to support (G)FSK, BPSK, (G)MSK, and LoRa modulations. + +- LoRa-E5 STM32WLE5JC Module with STM32WLE5JC multiprotocol LPWAN single-core + 32-bit microcontroller (Arm® Cortex®-M4 at 48 MHz) in 28-pin SMD package + featuring: + + - Ultra-low-power MCU + - RF transceiver (150 MHz to 960 MHz frequency range) supporting LoRa®, + (G)FSK, (G)MSK, and BPSK modulations + - 256-Kbyte Flash memory and 64-Kbyte SRAM + - Hardware encryption AES256-bit and a True random number generator + +- 1 user LED +- 2 serial communication (RX/TX) LEDs +- 1 boot/user and 1 reset push-button +- 32.768 kHz LSE crystal oscillator +- 32 MHz HSE oscillator +- Board connectors: + + - USB Type-C connector + - +/- (battery) power input pins (3-5V) + - SMA-K and IPEX antenna connectors + +- Delivered with SMA antenna (per default IPEX connector is disconnected) +- Flexible power-supply options: USB Type C or 3-5V battery soldered to +/- pins +- Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus, + and many other proprietary protocols +- All GPIOs led out from the LoRa-E5 STM32WLE5JC module +- 4x M2 mounting holes + +More information about the board can be found at the `LoRa-E5 mini Wiki`_. + +More information about LoRa-E5 STM32WLE5JC Module can be found here: + +- `LoRa-E5 STM32WLE5JC Module Wiki`_ +- `LoRa-E5 STM32WLE5JC Module datasheet`_ +- `STM32WLE5JC datasheet`_ +- `STM32WLE5JC reference manual`_ +- `STM32WLE5JC on www.st.com`_ + +Supported Features +================== + +The Zephyr LoRa-E5 mini configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | LoRa | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in: + +- :zephyr_file:`boards/seeed_studio/lora_e5_mini/lora_e5_mini_defconfig` +- :zephyr_file:`boards/seeed_studio/lora_e5_mini/lora_e5_mini.dts` + + +Connections and IOs +=================== + +LoRa-E5 mini has 4 GPIO controllers. These controllers are responsible for pin +muxing, input/output, pull-up, etc. + +Available pins: +--------------- + +.. image:: img/lora_e5_mini_pinout.jpg + :align: center + :alt: LoRa-E5 mini Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX : PB6 +- USART_1 RX : PB7 +- I2C_2_SCL : PB15 +- I2C_2_SDA : PA15 +- BOOT_PB : PB13 +- LED_1 : PB5 + +System Clock +------------ + +LoRa-E5 mini board System Clock could be driven by the low-power internal (MSI), +High-speed internal (HSI) or High-speed external (HSE) oscillator, as well as +main PLL clock. By default System clock is driven by the MSI clock at 48MHz. + +Programming and Debugging +************************* + +Applications for the ``lora_e5_mini`` board configuration can be built the +usual way (see :ref:`build_an_application`). + +In the factory the module is flashed with an DFU bootloader, an AT command +firmware, and the read protection level 1 is enabled. +So before you can program a Zephyr application to the module for the first time +you have to reset the read protection to level 0. +In case you use an st-link debugger you can use the STM32CubeProgrammer GUI to +set the RDP option byte to ``AA``, +or use the STM32_Programmer_CLI passing the ``--readunprotect`` command +to perform this read protection regression. +The RDP level 1 to RDP level 0 regression will erase the factory programmed AT +firmware, from which seeed studio has neither released the source code nor a binary. +Also, note that on the module the ``BOOT0`` pin of the SOC is not accessible, +so the system bootloader will only be executed if configured in the option bytes. + +Flashing +======== + +The LoRa-E5 mini does not include a on-board debug probe. +But the module can be debugged by connecting an external debug probe to the +2.54mm header. +Depending on the external probe used, ``openocd``, the ``stm32cubeprogrammer``, +``pyocd``, ``blackmagic``, or ``jlink`` runner can be used to flash the board. +Additional notes: + +- Pyocd: For STM32WL support Pyocd needs additional target information, which + can be installed by adding "pack" support with the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32wl + +Flashing an application to LoRa-E5 mini +--------------------------------------- + +Connect the LoRa-E5 to your host computer using the external debug probe. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your board: +Per default the console on ``usart1`` is available on the USB Type C connector +via the built-in USB to UART converter. + +.. code-block:: console + + $ picocom --baud 115200 /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: lora_e5_mini + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: lora_e5_mini + :maybe-skip-config: + :goals: debug + +.. _LoRa-E5 mini Wiki: + https://wiki.seeedstudio.com/LoRa_E5_mini/ + +.. _LoRa-E5 STM32WLE5JC Module Wiki: + https://wiki.seeedstudio.com/LoRa-E5_STM32WLE5JC_Module/ + +.. _LoRa-E5 STM32WLE5JC Module datasheet: + https://files.seeedstudio.com/products/317990687/res/LoRa-E5%20module%20datasheet_V1.0.pdf + +.. _STM32WLE5JC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32wle5jc.html + +.. _STM32WLE5JC datasheet: + https://www.st.com/resource/en/datasheet/stm32wle5jc.pdf + +.. _STM32WLE5JC reference manual: + https://www.st.com/resource/en/reference_manual/dm00530369-stm32wlex-advanced-armbased-32bit-mcus-with-subghz-radio-solution-stmicroelectronics.pdf diff --git a/boards/arm/lora_e5_mini/lora_e5_mini.dts b/boards/seeed/lora_e5_mini/lora_e5_mini.dts similarity index 98% rename from boards/arm/lora_e5_mini/lora_e5_mini.dts rename to boards/seeed/lora_e5_mini/lora_e5_mini.dts index e65572c6e35066..3eb9e803301c34 100644 --- a/boards/arm/lora_e5_mini/lora_e5_mini.dts +++ b/boards/seeed/lora_e5_mini/lora_e5_mini.dts @@ -5,7 +5,7 @@ */ /dts-v1/; -#include +#include #include / { diff --git a/boards/arm/lora_e5_mini/lora_e5_mini.yaml b/boards/seeed/lora_e5_mini/lora_e5_mini.yaml similarity index 91% rename from boards/arm/lora_e5_mini/lora_e5_mini.yaml rename to boards/seeed/lora_e5_mini/lora_e5_mini.yaml index 144ee2275ad366..72a8018b0e3192 100644 --- a/boards/arm/lora_e5_mini/lora_e5_mini.yaml +++ b/boards/seeed/lora_e5_mini/lora_e5_mini.yaml @@ -16,4 +16,4 @@ supported: - uart - watchdog - lora -vendor: seeed +vendor: seeed studio diff --git a/boards/arm/lora_e5_mini/lora_e5_mini_defconfig b/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig similarity index 83% rename from boards/arm/lora_e5_mini/lora_e5_mini_defconfig rename to boards/seeed/lora_e5_mini/lora_e5_mini_defconfig index 5e6649fe25ac06..0d6dc9f80d3dd9 100644 --- a/boards/arm/lora_e5_mini/lora_e5_mini_defconfig +++ b/boards/seeed/lora_e5_mini/lora_e5_mini_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WLE5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/lora_e5_mini/support/openocd.cfg b/boards/seeed/lora_e5_mini/support/openocd.cfg similarity index 100% rename from boards/arm/lora_e5_mini/support/openocd.cfg rename to boards/seeed/lora_e5_mini/support/openocd.cfg diff --git a/boards/seeed/seeeduino_xiao/Kconfig.seeeduino_xiao b/boards/seeed/seeeduino_xiao/Kconfig.seeeduino_xiao new file mode 100644 index 00000000000000..a66bf5bc5c018e --- /dev/null +++ b/boards/seeed/seeeduino_xiao/Kconfig.seeeduino_xiao @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SEEEDUINO_XIAO + select SOC_SAMD21G18A diff --git a/boards/arm/seeeduino_xiao/board.cmake b/boards/seeed/seeeduino_xiao/board.cmake similarity index 100% rename from boards/arm/seeeduino_xiao/board.cmake rename to boards/seeed/seeeduino_xiao/board.cmake diff --git a/boards/seeed/seeeduino_xiao/board.yml b/boards/seeed/seeeduino_xiao/board.yml new file mode 100644 index 00000000000000..386a3b3cbb6b4f --- /dev/null +++ b/boards/seeed/seeeduino_xiao/board.yml @@ -0,0 +1,5 @@ +board: + name: seeeduino_xiao + vendor: seeed + socs: + - name: samd21g18a diff --git a/boards/arm/seeeduino_xiao/doc/img/seeeduino_xiao.jpg b/boards/seeed/seeeduino_xiao/doc/img/seeeduino_xiao.jpg similarity index 100% rename from boards/arm/seeeduino_xiao/doc/img/seeeduino_xiao.jpg rename to boards/seeed/seeeduino_xiao/doc/img/seeeduino_xiao.jpg diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst new file mode 100644 index 00000000000000..17033e22ff7f95 --- /dev/null +++ b/boards/seeed/seeeduino_xiao/doc/index.rst @@ -0,0 +1,176 @@ +.. _seeeduino_xiao: + +Seeeduino XIAO +############## + +Overview +******** + +The Seeeduino XIAO is a tiny (20 mm x 17.5 mm) ARM development +board with onboard LEDs, USB port, and range of I/O broken out +onto 14 pins. + +.. image:: img/seeeduino_xiao.jpg + :align: center + :alt: Seeeduino XIAO + +Hardware +******** + +- ATSAMD21G18A ARM Cortex-M0+ processor at 48 MHz +- 256 KiB flash memory and 32 KiB of RAM +- Three user LEDs +- Native USB port + +Supported Features +================== + +The seeeduino_xiao board configuration supports the following hardware +features: + ++-----------+------------+------------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==========================================+ +| DMA | on-chip | Direct memory access | ++-----------+------------+------------------------------------------+ +| DAC | on-chip | Digital to analogue converter | ++-----------+------------+------------------------------------------+ +| Flash | on-chip | Can be used with LittleFS to store files | ++-----------+------------+------------------------------------------+ +| GPIO | on-chip | I/O ports | ++-----------+------------+------------------------------------------+ +| HWINFO | on-chip | Hardware info | ++-----------+------------+------------------------------------------+ +| I2C | on-chip | Inter-Integrated Circuit | ++-----------+------------+------------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------------+ +| SPI | on-chip | Serial Peripheral Interface ports | ++-----------+------------+------------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+------------------------------------------+ +| USART | on-chip | Serial ports | ++-----------+------------+------------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+------------------------------------------+ +| WDT | on-chip | Watchdog | ++-----------+------------+------------------------------------------+ + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/seeed_studio/seeeduino_xiao/seeeduino_xiao_defconfig`. + +Connections and IOs +=================== + +The `Seeeduino XIAO wiki`_ has detailed information about +the board including `pinouts`_ and the `schematic`_. + +System Clock +============ + +The SAMD21 MCU is configured to use the 32 kHz external crystal +with the on-chip PLL generating the 48 MHz system clock. The internal +APB and GCLK unit are set up in the same way as the upstream Arduino +libraries. + +SPI Port +======== + +The SAMD21 MCU has 6 SERCOM based SPIs. On the XIAO, SERCOM0 can be put +into SPI mode and used to connect to devices over pin 9 (MISO), pin 10 +(MOSI), and pin 8 (SCK). + +I2C Port +======== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM2 is available on +pin 4 (SDA) and pin 5 (SCL). + +Serial Port +=========== + +The SAMD21 MCU has 6 SERCOM based USARTs. On the XIAO, SERCOM4 is +the Zephyr console and is available on pins 7 (RX) and 6 (TX). + +USB Device Port +=============== + +The SAMD21 MCU has a USB device port that can be used to communicate +with a host PC. See the :ref:`usb-samples` sample applications for +more, such as the :zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual +serial port that echos characters back to the host PC. + +DAC +=== + +The SAMD21 MCU has a single channel DAC with 10 bits of resolution. On +the XIAO, the DAC is available on pin 0. + +Programming and Debugging +************************* + +The XIAO ships the BOSSA compatible UF2 bootloader. The bootloader can be +entered by shorting the RST and GND pads twice. + +Additionally, if :code:`CONFIG_USB_CDC_ACM` is enabled then the bootloader +will be entered automatically when you run :code:`west flash`. + +Flashing +======== + +#. Build the Zephyr kernel and the :ref:`hello_world` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: seeeduino_xiao + :goals: build + :compact: + +#. Connect the XIAO to your host computer using USB + +#. Connect a 3.3 V USB to serial adapter to the board and to the + host. See the `Serial Port`_ section above for the board's pin + connections. + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyUSB0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Short the RST and GND pads twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: seeeduino_xiao + :goals: flash + :compact: + + You should see "Hello World! seeeduino_xiao" in your terminal. + +References +********** + +.. target-notes:: + +.. _Seeeduino XIAO wiki: + https://wiki.seeedstudio.com/Seeeduino-XIAO/ + +.. _pinouts: + https://wiki.seeedstudio.com/Seeeduino-XIAO/#hardware-overview + +.. _schematic: + https://wiki.seeedstudio.com/Seeeduino-XIAO/#resourses diff --git a/boards/arm/seeeduino_xiao/pre_dt_board.cmake b/boards/seeed/seeeduino_xiao/pre_dt_board.cmake similarity index 100% rename from boards/arm/seeeduino_xiao/pre_dt_board.cmake rename to boards/seeed/seeeduino_xiao/pre_dt_board.cmake diff --git a/boards/arm/seeeduino_xiao/seeed_xiao_connector.dtsi b/boards/seeed/seeeduino_xiao/seeed_xiao_connector.dtsi similarity index 100% rename from boards/arm/seeeduino_xiao/seeed_xiao_connector.dtsi rename to boards/seeed/seeeduino_xiao/seeed_xiao_connector.dtsi diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi b/boards/seeed/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi similarity index 100% rename from boards/arm/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi rename to boards/seeed/seeeduino_xiao/seeeduino_xiao-pinctrl.dtsi diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao.dts b/boards/seeed/seeeduino_xiao/seeeduino_xiao.dts similarity index 100% rename from boards/arm/seeeduino_xiao/seeeduino_xiao.dts rename to boards/seeed/seeeduino_xiao/seeeduino_xiao.dts diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao.yaml b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml similarity index 96% rename from boards/arm/seeeduino_xiao/seeeduino_xiao.yaml rename to boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml index 73bfc8b114d847..b3532949edd820 100644 --- a/boards/arm/seeeduino_xiao/seeeduino_xiao.yaml +++ b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml @@ -2,20 +2,21 @@ identifier: seeeduino_xiao name: Seeeduino XIAO type: mcu arch: arm -ram: 32 -flash: 256 toolchain: - zephyr - gnuarmemb - xtools +flash: 256 +ram: 32 supported: - dma - dac - gpio - hwinfo - - spi - i2c + - spi - uart + - usb - usb_device - watchdog vendor: seeed diff --git a/boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig b/boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig similarity index 75% rename from boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig rename to boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig index 01123f55b5af3b..a53d4bd72837e4 100644 --- a/boards/arm/seeeduino_xiao/seeeduino_xiao_defconfig +++ b/boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig @@ -1,14 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_SAMD21=y -CONFIG_SOC_PART_NUMBER_SAMD21G18A=y -CONFIG_BOARD_SEEEDUINO_XIAO=y CONFIG_SOC_ATMEL_SAMD_XOSC32K=y CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN=y + +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_BOOTLOADER_BOSSA=y +CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y + CONFIG_CONSOLE=y +CONFIG_SERIAL=y CONFIG_UART_CONSOLE=y CONFIG_UART_INTERRUPT_DRIVEN=y -CONFIG_SERIAL=y -CONFIG_BOOTLOADER_BOSSA=y -CONFIG_BOOTLOADER_BOSSA_ADAFRUIT_UF2=y -CONFIG_BUILD_OUTPUT_UF2=y diff --git a/boards/arm/seeeduino_xiao/support/openocd.cfg b/boards/seeed/seeeduino_xiao/support/openocd.cfg similarity index 100% rename from boards/arm/seeeduino_xiao/support/openocd.cfg rename to boards/seeed/seeeduino_xiao/support/openocd.cfg diff --git a/boards/seeed/wio_terminal/Kconfig.defconfig b/boards/seeed/wio_terminal/Kconfig.defconfig new file mode 100644 index 00000000000000..4b742f1a228641 --- /dev/null +++ b/boards/seeed/wio_terminal/Kconfig.defconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Joel Guittet +# Wio Terminal board configuration + +# SPDX-License-Identifier: Apache-2.0 + +config LV_COLOR_16_SWAP + default y if LVGL diff --git a/boards/seeed/wio_terminal/Kconfig.wio_terminal b/boards/seeed/wio_terminal/Kconfig.wio_terminal new file mode 100644 index 00000000000000..a24d6f8df4a2c9 --- /dev/null +++ b/boards/seeed/wio_terminal/Kconfig.wio_terminal @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Joel Guittet +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WIO_TERMINAL + select SOC_SAMD51P19A diff --git a/boards/arm/wio_terminal/board.cmake b/boards/seeed/wio_terminal/board.cmake similarity index 100% rename from boards/arm/wio_terminal/board.cmake rename to boards/seeed/wio_terminal/board.cmake diff --git a/boards/seeed/wio_terminal/board.yml b/boards/seeed/wio_terminal/board.yml new file mode 100644 index 00000000000000..a7080a877775ef --- /dev/null +++ b/boards/seeed/wio_terminal/board.yml @@ -0,0 +1,5 @@ +board: + name: wio_terminal + vendor: seeed + socs: + - name: samd51p19a diff --git a/boards/arm/wio_terminal/doc/img/wio_terminal.png b/boards/seeed/wio_terminal/doc/img/wio_terminal.png similarity index 100% rename from boards/arm/wio_terminal/doc/img/wio_terminal.png rename to boards/seeed/wio_terminal/doc/img/wio_terminal.png diff --git a/boards/seeed/wio_terminal/doc/index.rst b/boards/seeed/wio_terminal/doc/index.rst new file mode 100644 index 00000000000000..e12212be4cc190 --- /dev/null +++ b/boards/seeed/wio_terminal/doc/index.rst @@ -0,0 +1,213 @@ +.. _wio_terminal: + +Wio Terminal +############ + +Overview +******** + +The Wio Terminal is a small (72 mm x 57 mm x 12 mm) and powerful ARM board with +wireless connectivity (2.4G/5G dual-band Wi-Fi and BLE 5.0), LCD display, +USB C port, FPC connector, microSD card slot, Raspberry Pi compatible 40-pins +header and 2 Grove connectors. + +.. image:: img/wio_terminal.png + :width: 500px + :align: center + :alt: Seeed Studio Wio Terminal + +Hardware +******** + +- ATSAMD51P19 ARM Cortex-M4F processor at 120 MHz +- 512 KiB flash memory and 192 KiB of RAM +- 4 MiB external flash +- MicroSD card slot +- RTL8720DN 2.4G/5G Dual Bands Wireless and BLE5.0 Combo Module +- 2.4inch LCD display +- LIS3DH accelerometer +- Microphone 1.0V-10V -42dB +- Speaker ≥78dB @10cm 4000Hz +- Light Sensor 400-1050nm +- Infrared Emitter 940nm +- GPIO 40 pin (Raspberry Pi compatible) +- 2x Grove connectors +- 1x user LED +- 3x user buttons +- 5-way user button +- Power/Reset/Boot mode switch +- Native USB port + +Supported Features +================== + +The wio_terminal board configuration supports the following hardware features: + +.. list-table:: + :header-rows: 1 + + * - Interface + - Controller + - Driver / Component + * - NVIC + - on-chip + - Nested vector interrupt controller + * - Flash + - on-chip + - Can be used with LittleFS to store files + * - SYSTICK + - on-chip + - Systick + * - WDT + - on-chip + - Watchdog + * - GPIO + - on-chip + - I/O ports + * - USART + - on-chip + - Serial port + * - I2C + - on-chip + - Inter-Integrated Circuit + * - SPI + - on-chip + - Serial Peripheral Interface port + * - TRNG + - on-chip + - True Random Number Generator + * - HWINFO + - on-chip + - Unique 128 bit serial number + * - RTC + - on-chip + - Real-Time Counter + * - USB + - on-chip + - USB device + * - PWM + - on-chip + - PWM + +Other hardware features are not currently supported by Zephyr. + +The default configuration can be found in the Kconfig file +:zephyr_file:`boards/seeed_studio/wio_terminal/wio_terminal_defconfig`. + +Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC. +To use the RTC, set :kconfig:option:`CONFIG_CORTEX_M_SYSTICK=n` and set +:kconfig:option:`CONFIG_SYS_CLOCK_TICKS_PER_SEC` to no more than 32 kHZ divided +by 7, i.e. no more than 4500. + +Connections and IOs +=================== + +The `Wio Terminal Getting started guide`_ has detailed information about the +board including `pinouts`_ and its `schematics`_. + +System Clock +============ + +The SAMD51 MCU is configured to use the 32.768 kHz internal oscillator with the +on-chip PLL generating the 120 MHz system clock. + +Serial Port +=========== + +Zephyr console output is available using the USB connector, which is used to +make the console available on PC as USB CDC class. + +USB Device Port +=============== + +The SAMD51 MCU has a USB device port that can be used to communicate with a +host PC. See the :ref:`usb-samples` sample applications for more, such as the +:zephyr:code-sample:`usb-cdc-acm` sample which sets up a virtual serial port that echos +characters back to the host PC. + +Programming and Debugging +************************* + +The Wio Terminal ships with an UF2 bootloader that is BOSSA compatible. The +bootloader can be entered by quickly tapping the reset button twice. + +The UF2 file is generated when building the application, and it is possible to +use it to flash the target. Enter the bootloader by quickly sliding the power +button twice, and copy the UF2 file to the USB mass storage device. The device +reboots on the new firmware after the UF2 file has finished transferring. + +Flashing +======== + +#. Build the Zephyr kernel and the :code:`button` sample application: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: build + :compact: + +#. Swipe the reset/power button down twice quickly to enter bootloader mode + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: flash + :compact: + + You should see the blue (user) LED flashing whenever you press the third + (counting from the top left) user button at the top of the Wio Terminal. + +Debugging +========= + +In addition to the built-in bootloader, the Wio Terminal can be flashed and +debugged using an SWD probe such as the Segger J-Link. + +#. Solder cables to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, + :code:`GND`, and :code:`3V3` pins. See `Test with SWD`_ for more + information. + +#. Connect the board to the probe by connecting the :code:`SWCLK`, + :code:`SWDIO`, :code:`RESET`, :code:`GND`, and :code:`3V3` pins on the + Wio Terminal to the :code:`SWCLK`, :code:`SWDIO`, :code:`RESET`, + :code:`GND`, and :code:`VTref` pins on the `J-Link`_. + +#. Flash the image: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: flash + :flash-args: -r openocd + :compact: + +#. Start debugging: + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/button + :board: wio_terminal + :goals: debug + :compact: + +References +********** + +.. target-notes:: + +.. _Wio Terminal Getting started guide: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/ + +.. _pinouts: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#pinout-diagram + +.. _schematics: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#resources + +.. _Test with SWD: + https://wiki.seeedstudio.com/Wio-Terminal-Getting-Started/#test-with-swd + +.. _J-Link: + https://www.segger.com/products/debug-probes/j-link/technology/interface-description/ diff --git a/boards/arm/wio_terminal/grove_connectors.dtsi b/boards/seeed/wio_terminal/grove_connectors.dtsi similarity index 100% rename from boards/arm/wio_terminal/grove_connectors.dtsi rename to boards/seeed/wio_terminal/grove_connectors.dtsi diff --git a/boards/arm/wio_terminal/pre_dt_board.cmake b/boards/seeed/wio_terminal/pre_dt_board.cmake similarity index 100% rename from boards/arm/wio_terminal/pre_dt_board.cmake rename to boards/seeed/wio_terminal/pre_dt_board.cmake diff --git a/boards/arm/wio_terminal/raspberrypi_40pins_connector.dtsi b/boards/seeed/wio_terminal/raspberrypi_40pins_connector.dtsi similarity index 100% rename from boards/arm/wio_terminal/raspberrypi_40pins_connector.dtsi rename to boards/seeed/wio_terminal/raspberrypi_40pins_connector.dtsi diff --git a/boards/arm/wio_terminal/support/openocd.cfg b/boards/seeed/wio_terminal/support/openocd.cfg similarity index 100% rename from boards/arm/wio_terminal/support/openocd.cfg rename to boards/seeed/wio_terminal/support/openocd.cfg diff --git a/boards/arm/wio_terminal/wio_terminal-pinctrl.dtsi b/boards/seeed/wio_terminal/wio_terminal-pinctrl.dtsi similarity index 100% rename from boards/arm/wio_terminal/wio_terminal-pinctrl.dtsi rename to boards/seeed/wio_terminal/wio_terminal-pinctrl.dtsi diff --git a/boards/arm/wio_terminal/wio_terminal.dts b/boards/seeed/wio_terminal/wio_terminal.dts similarity index 100% rename from boards/arm/wio_terminal/wio_terminal.dts rename to boards/seeed/wio_terminal/wio_terminal.dts diff --git a/boards/arm/wio_terminal/wio_terminal.yaml b/boards/seeed/wio_terminal/wio_terminal.yaml similarity index 100% rename from boards/arm/wio_terminal/wio_terminal.yaml rename to boards/seeed/wio_terminal/wio_terminal.yaml diff --git a/boards/arm/wio_terminal/wio_terminal_defconfig b/boards/seeed/wio_terminal/wio_terminal_defconfig similarity index 87% rename from boards/arm/wio_terminal/wio_terminal_defconfig rename to boards/seeed/wio_terminal/wio_terminal_defconfig index 353a699c150c58..20852ef411e9e6 100644 --- a/boards/arm/wio_terminal/wio_terminal_defconfig +++ b/boards/seeed/wio_terminal/wio_terminal_defconfig @@ -1,16 +1,14 @@ # Copyright (c) 2023 Joel Guittet +# Copyright (c) 2024 Gerson Fernando Budke # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_SAMD51=y -CONFIG_SOC_PART_NUMBER_SAMD51P19A=y CONFIG_SOC_ATMEL_SAMD5X_XOSC32K=y CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN=y -CONFIG_BOARD_WIO_TERMINAL=y + CONFIG_ARM_MPU=y CONFIG_CORTEX_M_SYSTICK=y CONFIG_HW_STACK_PROTECTION=y CONFIG_REGULATOR=y -CONFIG_GPIO=y # BOSSA bootloader CONFIG_BOOTLOADER_BOSSA=y diff --git a/boards/arm/xiao_ble/Kconfig b/boards/seeed/xiao_ble/Kconfig similarity index 100% rename from boards/arm/xiao_ble/Kconfig rename to boards/seeed/xiao_ble/Kconfig diff --git a/boards/seeed/xiao_ble/Kconfig.defconfig b/boards/seeed/xiao_ble/Kconfig.defconfig new file mode 100644 index 00000000000000..d02785ec152aa3 --- /dev/null +++ b/boards/seeed/xiao_ble/Kconfig.defconfig @@ -0,0 +1,21 @@ +# XIAO BLE board configuration + +# Copyright (c) 2022 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XIAO_BLE + +config BT_CTLR + default BT + +if USB_DEVICE_STACK + +config UART_CONSOLE + default CONSOLE + +config USB_DEVICE_INITIALIZE_AT_BOOT + default y + +endif # USB_DEVICE_STACK + +endif # BOARD_XIAO_BLE diff --git a/boards/seeed/xiao_ble/Kconfig.xiao_ble b/boards/seeed/xiao_ble/Kconfig.xiao_ble new file mode 100644 index 00000000000000..8901b7dcbdb51d --- /dev/null +++ b/boards/seeed/xiao_ble/Kconfig.xiao_ble @@ -0,0 +1,7 @@ +# XIAO BLE board configuration + +# Copyright (c) 2022 Marcin Niestroj +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_BLE + select SOC_NRF52840_QIAA diff --git a/boards/arm/xiao_ble/board.cmake b/boards/seeed/xiao_ble/board.cmake similarity index 100% rename from boards/arm/xiao_ble/board.cmake rename to boards/seeed/xiao_ble/board.cmake diff --git a/boards/seeed/xiao_ble/board.yml b/boards/seeed/xiao_ble/board.yml new file mode 100644 index 00000000000000..3f83399a7fba09 --- /dev/null +++ b/boards/seeed/xiao_ble/board.yml @@ -0,0 +1,7 @@ +board: + name: xiao_ble + vendor: seeed + socs: + - name: nrf52840 + variants: + - name: 'sense' diff --git a/boards/arm/xiao_ble/doc/img/xiao_ble.jpg b/boards/seeed/xiao_ble/doc/img/xiao_ble.jpg similarity index 100% rename from boards/arm/xiao_ble/doc/img/xiao_ble.jpg rename to boards/seeed/xiao_ble/doc/img/xiao_ble.jpg diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst new file mode 100644 index 00000000000000..a7f0778d3b3b8e --- /dev/null +++ b/boards/seeed/xiao_ble/doc/index.rst @@ -0,0 +1,219 @@ +.. _xiao_ble: + +XIAO BLE (Sense) +################ + +Overview +******** + +The Seeed XIAO BLE (Sense) is a tiny (21 mm x 17.5 mm) Nordic Semiconductor +nRF52840 ARM Cortex-M4F development board with onboard LEDs, USB port, QSPI +flash, battery charger, and range of I/O broken out into 14 pins. + +.. figure:: img/xiao_ble.jpg + :align: center + :alt: XIAO BLE + +Hardware +******** + +- Nordic nRF52840 Cortex-M4F processor at 64MHz +- 2MB QSPI Flash +- RGB LED +- USB Type-C Connector, nRF52840 acting as USB device +- Battery charger BQ25101 +- Reset button +- Bluetooth antenna +- LSM6DS3TR-C 6D IMU (3D accelerometer and 3D gyroscope) (XIAO BLE Sense only) +- PDM microphone (XIAO BLE Sense only) + +Supported Features +================== + +The xiao_ble board configuration supports the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash, QSPI flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. + +Connections and IOs +=================== + +The `XIAO BLE wiki`_ has detailed information about the board including +`pinouts`_ and the `schematic`_. + +LED +--- + +* LED1 (red) = P0.26 +* LED2 (green) = P0.30 +* LED3 (blue) = P0.06 + +Programming and Debugging +************************* + +The XIAO BLE ships with the `Adafruit nRF52 Bootloader`_ which supports flashing +using `UF2`_. Doing so allows easy flashing of new images, but does not support +debugging the device. For debugging please use `External Debugger`_. + +UF2 Flashing +============ + +To enter the bootloader, connect the USB port of the XIAO BLE to your host, and +double tap the reset botton to the left of the USB connector. A mass storage +device named `XIAO BLE` should appear on the host. Using the command line, or +your file manager copy the `zephyr/zephyr.uf2` file from your build to the base +of the `XIAO BLE` mass storage device. The XIAO BLE will automatically reset +and launch the newly flashed application. + +External Debugger +================= + +In order to support debugging the device, instead of using the bootloader, you +can use an :ref:`External Debug Probe `. To flash and debug Zephyr +applications you need to use `Seeeduino XIAO Expansion Board`_ or solder an SWD +header onto the back side of the board. + +For Segger J-Link debug probes, follow the instructions in the +:ref:`jlink-external-debug-probe` page to install and configure all the +necessary software. + +Flashing +-------- + +Setup and connect a supported debug probe (JLink, instructions at :ref:`jlink-external-debug-probe` or +BlackMagic Probe). Then build and flash applications as +usual (see :ref:`build_an_application` and :ref:`application_run` for more +details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board XIAO BLE +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. Just add +``CONFIG_BOOT_DELAY=5000`` to the configuration, so that USB CDC ACM is +initialized before any text is printed, as below: + +.. tabs:: + + .. group-tab:: XIAO BLE + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_ble + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + + .. group-tab:: XIAO BLE Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_ble/nrf52840/sense + :goals: build flash + :gen-args: -DCONFIG_BOOT_DELAY=5000 + +Debugging +--------- + +Refer to the :ref:`jlink-external-debug-probe` page to learn about debugging +boards with a Segger IC. + +Debugging using a BlackMagic Probe is also supported. + +Testing the LEDs in the XIAO BLE (Sense) +**************************************** + +There is a sample that allows to test that LEDs on the board are working +properly with Zephyr: + +.. tabs:: + + .. group-tab:: XIAO BLE + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: xiao_ble + :goals: build flash + + .. group-tab:: XIAO BLE Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: xiao_ble/nrf52840/sense + :goals: build flash + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The LED definitions can be found in +:zephyr_file:`boards/seeed_studio/xiao_ble/xiao_ble_common.dtsi`. + +Testing shell over USB in the XIAO BLE (Sense) +********************************************** + +There is a sample that allows to test shell interface over USB CDC ACM interface +with Zephyr: + +.. tabs:: + + .. group-tab:: XIAO BLE + + .. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :board: xiao_ble + :goals: build flash + + .. group-tab:: XIAO BLE Sense + + .. zephyr-app-commands:: + :zephyr-app: samples/subsys/shell/shell_module + :board: xiao_ble/nrf52840/sense + :goals: build flash + +References +********** + +.. target-notes:: + +.. _XIAO BLE wiki: https://wiki.seeedstudio.com/XIAO_BLE/ +.. _pinouts: https://wiki.seeedstudio.com/XIAO_BLE/#hardware-overview +.. _schematic: https://wiki.seeedstudio.com/XIAO_BLE/#resources +.. _Seeeduino XIAO Expansion Board: https://wiki.seeedstudio.com/Seeeduino-XIAO-Expansion-Board/ +.. _Adafruit nRF52 Bootloader: https://github.com/adafruit/Adafruit_nRF52_Bootloader +.. _UF2: https://github.com/microsoft/uf2 diff --git a/boards/arm/reel_board/pre_dt_board.cmake b/boards/seeed/xiao_ble/pre_dt_board.cmake similarity index 100% rename from boards/arm/reel_board/pre_dt_board.cmake rename to boards/seeed/xiao_ble/pre_dt_board.cmake diff --git a/boards/arm/xiao_ble/seeed_xiao_connector.dtsi b/boards/seeed/xiao_ble/seeed_xiao_connector.dtsi similarity index 100% rename from boards/arm/xiao_ble/seeed_xiao_connector.dtsi rename to boards/seeed/xiao_ble/seeed_xiao_connector.dtsi diff --git a/boards/arm/xiao_ble/xiao_ble-pinctrl.dtsi b/boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi similarity index 100% rename from boards/arm/xiao_ble/xiao_ble-pinctrl.dtsi rename to boards/seeed/xiao_ble/xiao_ble-pinctrl.dtsi diff --git a/boards/arm/xiao_ble/xiao_ble.dts b/boards/seeed/xiao_ble/xiao_ble.dts similarity index 100% rename from boards/arm/xiao_ble/xiao_ble.dts rename to boards/seeed/xiao_ble/xiao_ble.dts diff --git a/boards/arm/xiao_ble/xiao_ble.yaml b/boards/seeed/xiao_ble/xiao_ble.yaml similarity index 100% rename from boards/arm/xiao_ble/xiao_ble.yaml rename to boards/seeed/xiao_ble/xiao_ble.yaml diff --git a/boards/arm/xiao_ble/xiao_ble_common.dtsi b/boards/seeed/xiao_ble/xiao_ble_common.dtsi similarity index 100% rename from boards/arm/xiao_ble/xiao_ble_common.dtsi rename to boards/seeed/xiao_ble/xiao_ble_common.dtsi diff --git a/boards/seeed/xiao_ble/xiao_ble_defconfig b/boards/seeed/xiao_ble/xiao_ble_defconfig new file mode 100644 index 00000000000000..84eb3e97f22a57 --- /dev/null +++ b/boards/seeed/xiao_ble/xiao_ble_defconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y + +# Logger cannot use itself to log +CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + +# Enable USB +CONFIG_USB_DEVICE_STACK=y + +# Build UF2 by default, supported by the Adafruit nRF52 Bootloader +CONFIG_BUILD_OUTPUT_UF2=y +CONFIG_USE_DT_CODE_PARTITION=y diff --git a/boards/arm/xiao_ble/xiao_ble_sense.dts b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts similarity index 100% rename from boards/arm/xiao_ble/xiao_ble_sense.dts rename to boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.dts diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml new file mode 100644 index 00000000000000..dfb8bc4e8afb78 --- /dev/null +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml @@ -0,0 +1,24 @@ +identifier: xiao_ble/nrf52840/sense +name: XIAO BLE Sense +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - ble + - counter + - gpio + - i2c + - i2s + - pwm + - spi + - usb_cdc + - usb_device + - watchdog + - netif:openthread +vendor: seeed diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig new file mode 100644 index 00000000000000..ff4b012b93c4c2 --- /dev/null +++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Required to enable LSM6DS3TR-C power +CONFIG_REGULATOR=y diff --git a/boards/seeed/xiao_esp32c3/Kconfig.defconfig b/boards/seeed/xiao_esp32c3/Kconfig.defconfig new file mode 100644 index 00000000000000..f70e724ed8e0ca --- /dev/null +++ b/boards/seeed/xiao_esp32c3/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright 2022 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.sysbuild b/boards/seeed/xiao_esp32c3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/xiao_esp32s3/Kconfig.sysbuild rename to boards/seeed/xiao_esp32c3/Kconfig.sysbuild diff --git a/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 b/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 new file mode 100644 index 00000000000000..e4db49fc4a6fdb --- /dev/null +++ b/boards/seeed/xiao_esp32c3/Kconfig.xiao_esp32c3 @@ -0,0 +1,5 @@ +# Copyright 2022 Google LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32C3 + select SOC_ESP32C3_FX4 diff --git a/boards/xtensa/m5stack_stamps3/board.cmake b/boards/seeed/xiao_esp32c3/board.cmake similarity index 100% rename from boards/xtensa/m5stack_stamps3/board.cmake rename to boards/seeed/xiao_esp32c3/board.cmake diff --git a/boards/seeed/xiao_esp32c3/board.yml b/boards/seeed/xiao_esp32c3/board.yml new file mode 100644 index 00000000000000..2bd54cf346f660 --- /dev/null +++ b/boards/seeed/xiao_esp32c3/board.yml @@ -0,0 +1,5 @@ +board: + name: xiao_esp32c3 + vendor: seeed + socs: + - name: esp32c3 diff --git a/boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c.jpg b/boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c.jpg similarity index 100% rename from boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c.jpg rename to boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c.jpg diff --git a/boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg b/boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg similarity index 100% rename from boards/riscv/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg rename to boards/seeed/xiao_esp32c3/doc/img/xiao_esp32c3_pinout.jpg diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst new file mode 100644 index 00000000000000..11d5109b3cfd4f --- /dev/null +++ b/boards/seeed/xiao_esp32c3/doc/index.rst @@ -0,0 +1,218 @@ +.. _xiao_esp32c3: + +XIAO ESP32C3 +############ + +Overview +******** + +Seeed Studio XIAO ESP32C3 is an IoT mini development board based on the +Espressif ESP32-C3 WiFi/Bluetooth dual-mode chip. + +For more details see the `Seeed Studio XIAO ESP32C3`_ wiki page. + +.. figure:: img/xiao_esp32c.jpg + :align: center + :alt: XIAO ESP32C3 + + XIAO ESP32C3 + +Hardware +******** + +This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an U.FL external antenna connector. It is based on a standard XIAO 14 pin +pinout. + +Supported Features +================== + +The XIAO ESP32C3 board configuration supports the following hardware features: + ++-----------+------------+------------------+ +| Interface | Controller | Driver/Component | ++===========+============+==================+ +| PMP | on-chip | arch/riscv | ++-----------+------------+------------------+ +| INTMTRX | on-chip | intc_esp32c3 | ++-----------+------------+------------------+ +| PINMUX | on-chip | pinctrl_esp32 | ++-----------+------------+------------------+ +| USB UART | on-chip | serial_esp32_usb | ++-----------+------------+------------------+ +| GPIO | on-chip | gpio_esp32 | ++-----------+------------+------------------+ +| UART | on-chip | uart_esp32 | ++-----------+------------+------------------+ +| I2C | on-chip | i2c_esp32 | ++-----------+------------+------------------+ +| SPI | on-chip | spi_esp32_spim | ++-----------+------------+------------------+ +| TWAI | on-chip | can_esp32_twai | ++-----------+------------+------------------+ + +Connections and IOs +=================== + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_esp32c3_pinout.jpg + :align: center + :alt: XIAO ESP32C3 Pinout + + XIAO ESP32C3 Pinout + +Prerequisites +============= + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: xiao_esp32c3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by Sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +For the :code:`Hello, world!` application, follow the instructions below. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c3 + :goals: build flash + +Since the Zephyr console is by default on the `usb_serial` device, we use +the espressif monitor to view. + +.. code-block:: console + + $ west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! xiao_esp32c3 + +Debugging +********* + +As with much custom hardware, the ESP32 modules require patches to +OpenOCD that are not upstreamed yet. Espressif maintains their own fork of +the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ + +The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the +``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` +parameter when building. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c3 + :goals: build flash + :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32c3 + :goals: debug + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO ESP32C3`: https://wiki.seeedstudio.com/XIAO_ESP32C3_Getting_Started +.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/riscv/xiao_esp32c3/seeed_xiao_connector.dtsi b/boards/seeed/xiao_esp32c3/seeed_xiao_connector.dtsi similarity index 100% rename from boards/riscv/xiao_esp32c3/seeed_xiao_connector.dtsi rename to boards/seeed/xiao_esp32c3/seeed_xiao_connector.dtsi diff --git a/boards/riscv/xiao_esp32c3/support/openocd.cfg b/boards/seeed/xiao_esp32c3/support/openocd.cfg similarity index 100% rename from boards/riscv/xiao_esp32c3/support/openocd.cfg rename to boards/seeed/xiao_esp32c3/support/openocd.cfg diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi b/boards/seeed/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi similarity index 100% rename from boards/riscv/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi rename to boards/seeed/xiao_esp32c3/xiao_esp32c3-pinctrl.dtsi diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3.dts b/boards/seeed/xiao_esp32c3/xiao_esp32c3.dts similarity index 100% rename from boards/riscv/xiao_esp32c3/xiao_esp32c3.dts rename to boards/seeed/xiao_esp32c3/xiao_esp32c3.dts diff --git a/boards/riscv/xiao_esp32c3/xiao_esp32c3.yaml b/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml similarity index 100% rename from boards/riscv/xiao_esp32c3/xiao_esp32c3.yaml rename to boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig b/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig new file mode 100644 index 00000000000000..ef633ce56a18e2 --- /dev/null +++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/seeed/xiao_esp32s3/Kconfig b/boards/seeed/xiao_esp32s3/Kconfig new file mode 100644 index 00000000000000..20855be092e435 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32S3 + select SOC_ESP32S3_PROCPU if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU + select SOC_ESP32S3_APPCPU if BOARD_XIAO_ESP32S3_ESP32S3_APPCPU diff --git a/boards/seeed/xiao_esp32s3/Kconfig.defconfig b/boards/seeed/xiao_esp32s3/Kconfig.defconfig new file mode 100644 index 00000000000000..424820d78adc90 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XIAO_ESP32S3_ESP32S3_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_XIAO_ESP32S3_ESP32S3_PROCPU + +if BOARD_XIAO_ESP32S3_ESP32S3_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_XIAO_ESP32S3_ESP32S3_APPCPU diff --git a/boards/xtensa/yd_esp32/Kconfig.sysbuild b/boards/seeed/xiao_esp32s3/Kconfig.sysbuild similarity index 100% rename from boards/xtensa/yd_esp32/Kconfig.sysbuild rename to boards/seeed/xiao_esp32s3/Kconfig.sysbuild diff --git a/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 b/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 new file mode 100644 index 00000000000000..68c6020cd52593 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/Kconfig.xiao_esp32s3 @@ -0,0 +1,7 @@ +# XIAO ESP32S3 board configuration + +# Copyright (c) 2023 Seeed Studio inc. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XIAO_ESP32S3 + select SOC_ESP32S3_WROOM_N8R8 diff --git a/boards/xtensa/olimex_esp32_evb/board.cmake b/boards/seeed/xiao_esp32s3/board.cmake similarity index 100% rename from boards/xtensa/olimex_esp32_evb/board.cmake rename to boards/seeed/xiao_esp32s3/board.cmake diff --git a/boards/seeed/xiao_esp32s3/board.yml b/boards/seeed/xiao_esp32s3/board.yml new file mode 100644 index 00000000000000..02ba87e5bc21e1 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/board.yml @@ -0,0 +1,5 @@ +board: + name: xiao_esp32s3 + vendor: seeed + socs: + - name: esp32s3 diff --git a/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3.jpg b/boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3.jpg similarity index 100% rename from boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3.jpg rename to boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3.jpg diff --git a/boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg b/boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg similarity index 100% rename from boards/xtensa/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg rename to boards/seeed/xiao_esp32s3/doc/img/xiao_esp32s3_pinout.jpg diff --git a/boards/seeed/xiao_esp32s3/doc/index.rst b/boards/seeed/xiao_esp32s3/doc/index.rst new file mode 100644 index 00000000000000..1880e6ff9a4a12 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/doc/index.rst @@ -0,0 +1,243 @@ +.. _xiao_esp32s3: + +XIAO ESP32S3 +############ + +Overview +******** + +Seeed Studio XIAO ESP32S3 is an IoT mini development board based on the +Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. + +For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page. + +.. figure:: img/xiao_esp32s3.jpg + :align: center + :alt: XIAO ESP32S3 + + XIAO ESP32S3 + +Hardware +******** + +This board is based on the ESP32-S3 with 8MB of flash, WiFi and BLE support. It +has an USB-C port for programming and debugging, integrated battery charging +and an U.FL external antenna connector. It is based on a standard XIAO 14 pin +pinout. + +ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi +and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor +(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, +RF module, and numerous peripherals. + +Supported Features +================== + +Current Zephyr's XIAO ESP32S3 board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI/CAN | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| GDMA | on-chip | dma | ++------------+------------+-------------------------------------+ + +Connections and IOs +=================== + +The board uses a standard XIAO pinout, the default pin mapping is the following: + +.. figure:: img/xiao_esp32s3_pinout.jpg + :align: center + :alt: XIAO ESP32S3 Pinout + + XIAO ESP32S3 Pinout + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: xiao_esp32s3 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: build + +The usual ``flash`` target will work with the ``xiao_esp32s3`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32s3/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! xiao_esp32s3 + +Debugging +********* + +ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32-S3`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: xiao_esp32s3/esp32/procpu + :goals: debug +.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. target-notes:: + +.. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ diff --git a/boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi b/boards/seeed/xiao_esp32s3/seeed_xiao_connector.dtsi similarity index 100% rename from boards/xtensa/xiao_esp32s3/seeed_xiao_connector.dtsi rename to boards/seeed/xiao_esp32s3/seeed_xiao_connector.dtsi diff --git a/boards/xtensa/xiao_esp32s3/support/openocd.cfg b/boards/seeed/xiao_esp32s3/support/openocd.cfg similarity index 100% rename from boards/xtensa/xiao_esp32s3/support/openocd.cfg rename to boards/seeed/xiao_esp32s3/support/openocd.cfg diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi b/boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi similarity index 100% rename from boards/xtensa/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi rename to boards/seeed/xiao_esp32s3/xiao_esp32s3-pinctrl.dtsi diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.dts new file mode 100644 index 00000000000000..672c52a5cbac56 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.dts @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +/ { + model = "Seeed Xiao ESP32S3 APPCPU"; + compatible = "espressif,esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&trng0 { + status = "okay"; +}; + +&ipm0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 64kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x00010000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.yaml new file mode 100644 index 00000000000000..5d66048e038805 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: xiao_esp32s3/esp32s3/appcpu +name: XIAO ESP32S3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: seeed diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.dts b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.dts new file mode 100644 index 00000000000000..99d7f0deb75fb5 --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.dts @@ -0,0 +1,138 @@ +/* + * Copyright (c) 2023 Seeed Studio inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "xiao_esp32s3-pinctrl.dtsi" +#include "seeed_xiao_connector.dtsi" + +/ { + model = "Seeed Xiao ESP32S3 PROCPU"; + compatible = "seeed,xiao-esp32s3"; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &usb_serial; + zephyr,shell-uart = &usb_serial; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + aliases { + i2c-0 = &i2c0; + watchdog0 = &wdt0; + led0 = &led0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; + label = "BUILTIN LED"; + }; + }; + +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&usb_serial { + status = "okay"; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&trng0 { + status = "okay"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&twai { + pinctrl-0 = <&twai_default>; + pinctrl-names = "default"; + bus-speed = <125000>; +}; + +&timer0 { + status = "okay"; +}; + +&timer1 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x00000000 0x0000F000>; + read-only; + }; + + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.yaml new file mode 100644 index 00000000000000..8a1ace79ba69af --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu.yaml @@ -0,0 +1,22 @@ +identifier: xiao_esp32s3/esp32s3/procpu +name: XIAO ESP32S3 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - gpio + - uart + - i2c + - spi + - can + - counter + - watchdog + - entropy + - pwm + - dma +testing: + ignore_tags: + - net + - bluetooth +vendor: seeed diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu_defconfig new file mode 100644 index 00000000000000..6539bd42e5947e --- /dev/null +++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_esp32s3_procpu_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y +CONFIG_GPIO=y diff --git a/boards/segger/index.rst b/boards/segger/index.rst new file mode 100644 index 00000000000000..ec863c07d2d7bc --- /dev/null +++ b/boards/segger/index.rst @@ -0,0 +1,10 @@ +.. _boards-segger: + +SEGGER Microcontroller GmbH +########################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arm/ip_k66f/CMakeLists.txt b/boards/segger/ip_k66f/CMakeLists.txt similarity index 100% rename from boards/arm/ip_k66f/CMakeLists.txt rename to boards/segger/ip_k66f/CMakeLists.txt diff --git a/boards/segger/ip_k66f/Kconfig.defconfig b/boards/segger/ip_k66f/Kconfig.defconfig new file mode 100644 index 00000000000000..06952ee0707916 --- /dev/null +++ b/boards/segger/ip_k66f/Kconfig.defconfig @@ -0,0 +1,33 @@ +# IP-K66F board + +# Copyright (c) 2020 DENX Software Engineering GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_IP_K66F + +config OSC_XTAL0_FREQ + default 12000000 + +config MCG_PRDIV0 + default 0x0 + +config MCG_VDIV0 + default 0xe + +config MCG_FCRDIV + default 1 + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config ETH_MCUX_RMII_EXT_CLK + default y if ETH_MCUX + +config ETH_MCUX_NO_PHY_SMI + default y if ETH_MCUX + +endif # NETWORKING + +endif # BOARD_IP_K66F diff --git a/boards/segger/ip_k66f/Kconfig.ip_k66f b/boards/segger/ip_k66f/Kconfig.ip_k66f new file mode 100644 index 00000000000000..22ec9ddf3e3525 --- /dev/null +++ b/boards/segger/ip_k66f/Kconfig.ip_k66f @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IP_K66F + select SOC_MK66F18 + select SOC_PART_NUMBER_MK66FN2M0VMD18 diff --git a/boards/arm/ip_k66f/board.cmake b/boards/segger/ip_k66f/board.cmake similarity index 100% rename from boards/arm/ip_k66f/board.cmake rename to boards/segger/ip_k66f/board.cmake diff --git a/boards/segger/ip_k66f/board.yml b/boards/segger/ip_k66f/board.yml new file mode 100644 index 00000000000000..c1593280a49a63 --- /dev/null +++ b/boards/segger/ip_k66f/board.yml @@ -0,0 +1,5 @@ +board: + name: ip_k66f + vendor: segger + socs: + - name: mk66f18 diff --git a/boards/segger/ip_k66f/doc/index.rst b/boards/segger/ip_k66f/doc/index.rst new file mode 100644 index 00000000000000..5b4cd7195f0c5b --- /dev/null +++ b/boards/segger/ip_k66f/doc/index.rst @@ -0,0 +1,174 @@ +.. _ip_k66f: + +SEGGER IP Switch Board +###################### + +Overview +******** + +The Segger IP Switch Board is a Evaluation board based on NXP Kinetis K66 MCU. +It comes with Micrel/Microchip KSZ8794CNX integrated 4-port 10/100 managed +Ethernet switch with Gigabit RGMII/MII/RMII interface. + +- KSZ8794CNX enables evaluation for switch functions +- On-board debug probe J-Link-OB for programming + +.. image:: ip_k66f.jpg + :align: center + :alt: IP-K66F + +Hardware +******** + +- MK66FN2M0VMD18 MCU (180 MHz, 2 MB flash memory, 256 KB RAM, low-power, + crystal-less USB +- Dual role USB interface with micro-B USB connector +- 2 User LED +- On-board debug probe J-Link-OB for programming +- Micrel/Microchip Ethernet Switch KSZ8794CNX with 3 RJ45 connectors + +For more information about the K66F SoC and IP-K66F board: + +- `K66F Website`_ +- `K66F Datasheet`_ +- `K66F Reference Manual`_ +- `IP-K66F Website`_ +- `IP-K66F User Guide`_ +- `IP-K66F Schematics`_ + +Supported Features +================== + +The ip_k66f board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | soc flash | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/segger/ip_k66f/ip_k66f_defconfig` + +Micrel/Microchip KSZ8794CNX Ethernet Switch is not currently +supported. + +Connections and IOs +=================== + +The K66F SoC has five pairs of pinmux/gpio controllers. + ++-------+-----------------+---------------------------+ +| Name | Function | Usage | ++=======+=================+===========================+ +| PTA8 | GPIO | Red LED | ++-------+-----------------+---------------------------+ +| PTA10 | GPIO | RED LED | ++-------+-----------------+---------------------------+ + +System Clock +============ + +The K66F SoC is configured to use the 12 MHz low gain crystal oscillator on the +board with the on-chip PLL to generate a 180 MHz system clock. + +Serial Port +=========== + +The K66F SoC has six UARTs. None of them are used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-jlink-onboard-debug-probe`. + +:ref:`opensda-jlink-onboard-debug-probe` +-------------------------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Follow the instructions in :ref:`opensda-jlink-onboard-debug-probe` to program +the `OpenSDA J-Link Generic Firmware for V3.2 Bootloader`_. Note that Segger +does provide an OpenSDA J-Link Board-Specific Firmware for this board, however +it is not compatible with the DAPLink bootloader. + +The default flasher is ``jlink`` using the built-in SEGGER Jlink interface. + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ip_k66f + :goals: flash + +Red LED0 should blink at 1 second delay. + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: ip_k66f + :goals: debug + +Step through the application in your debugger. + +.. _IP-K66F Website: + https://www.segger.com/evaluate-our-software/segger/embosip-switch-board/ + +.. _IP-K66F User Guide: + https://www.segger.com/downloads/emnet/UM06002 + +.. _IP-K66F Schematics: + https://www.segger.com/downloads/emnet/embOSIP_SwitchBoard_V2.0_WEB_Schematic.pdf + +.. _K66F Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/k-series-cortex-m4/k6x-ethernet/kinetis-k66-180-mhz-dual-high-speed-full-speed-usbs-2mb-flash-microcontrollers-mcus-based-on-arm-cortex-m4-core:K66_180 + +.. _K66F Datasheet: + https://www.nxp.com/docs/en/data-sheet/K66P144M180SF5V2.pdf + +.. _K66F Reference Manual: + https://www.nxp.com/webapp/Download?colCode=K66P144M180SF5RMV2 + +.. _OpenSDA J-Link Generic Firmware for V3.2 Bootloader: + https://www.segger.com/downloads/jlink/OpenSDA_V3_2 + +Serial console +============== + +The ``ip_k66f`` board only uses Segger's RTT console for providing serial +console. There is no physical serial port available. + +- To communicate with this board one needs in one console: + +``/opt/SEGGER/JLink_V664/JLinkRTTLogger -Device MK66FN2M0XXX18 -RTTChannel 1 -if SWD -Speed 4000 ~/rtt.log`` + +- In another one: + +``nc localhost 19021`` diff --git a/boards/arm/ip_k66f/doc/ip_k66f.jpg b/boards/segger/ip_k66f/doc/ip_k66f.jpg similarity index 100% rename from boards/arm/ip_k66f/doc/ip_k66f.jpg rename to boards/segger/ip_k66f/doc/ip_k66f.jpg diff --git a/boards/arm/ip_k66f/ip_k66f-pinctrl.dtsi b/boards/segger/ip_k66f/ip_k66f-pinctrl.dtsi similarity index 100% rename from boards/arm/ip_k66f/ip_k66f-pinctrl.dtsi rename to boards/segger/ip_k66f/ip_k66f-pinctrl.dtsi diff --git a/boards/arm/ip_k66f/ip_k66f.dts b/boards/segger/ip_k66f/ip_k66f.dts similarity index 100% rename from boards/arm/ip_k66f/ip_k66f.dts rename to boards/segger/ip_k66f/ip_k66f.dts diff --git a/boards/arm/ip_k66f/ip_k66f.yaml b/boards/segger/ip_k66f/ip_k66f.yaml similarity index 100% rename from boards/arm/ip_k66f/ip_k66f.yaml rename to boards/segger/ip_k66f/ip_k66f.yaml diff --git a/boards/arm/ip_k66f/ip_k66f_defconfig b/boards/segger/ip_k66f/ip_k66f_defconfig similarity index 81% rename from boards/arm/ip_k66f/ip_k66f_defconfig rename to boards/segger/ip_k66f/ip_k66f_defconfig index 6bb29071f79f67..3a283228fafe63 100644 --- a/boards/arm/ip_k66f/ip_k66f_defconfig +++ b/boards/segger/ip_k66f/ip_k66f_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_MK66F18=y -CONFIG_SOC_SERIES_KINETIS_K6X=y -CONFIG_BOARD_IP_K66F=y CONFIG_GPIO=y CONFIG_PINCTRL=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000 diff --git a/boards/arm/ip_k66f/linker.ld b/boards/segger/ip_k66f/linker.ld similarity index 100% rename from boards/arm/ip_k66f/linker.ld rename to boards/segger/ip_k66f/linker.ld diff --git a/boards/arm/ip_k66f/support/openocd.cfg b/boards/segger/ip_k66f/support/openocd.cfg similarity index 100% rename from boards/arm/ip_k66f/support/openocd.cfg rename to boards/segger/ip_k66f/support/openocd.cfg diff --git a/boards/segger/trb_stm32f407/CMakeLists.txt b/boards/segger/trb_stm32f407/CMakeLists.txt new file mode 100644 index 00000000000000..9881313609aae2 --- /dev/null +++ b/boards/segger/trb_stm32f407/CMakeLists.txt @@ -0,0 +1 @@ +# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/segger/trb_stm32f407/Kconfig.segger_trb_stm32f407 b/boards/segger/trb_stm32f407/Kconfig.segger_trb_stm32f407 new file mode 100644 index 00000000000000..91d1e6a9b17b67 --- /dev/null +++ b/boards/segger/trb_stm32f407/Kconfig.segger_trb_stm32f407 @@ -0,0 +1,5 @@ +# Copyright (c) 2020, Erwin Rol +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SEGGER_TRB_STM32F407 + select SOC_STM32F407XE diff --git a/boards/arm/segger_trb_stm32f407/board.cmake b/boards/segger/trb_stm32f407/board.cmake similarity index 100% rename from boards/arm/segger_trb_stm32f407/board.cmake rename to boards/segger/trb_stm32f407/board.cmake diff --git a/boards/segger/trb_stm32f407/board.yml b/boards/segger/trb_stm32f407/board.yml new file mode 100644 index 00000000000000..52ba24a33eb0fe --- /dev/null +++ b/boards/segger/trb_stm32f407/board.yml @@ -0,0 +1,5 @@ +board: + name: segger_trb_stm32f407 + vendor: segger + socs: + - name: stm32f407xx diff --git a/boards/arm/segger_trb_stm32f407/doc/img/segger_trb_stm32f407.jpg b/boards/segger/trb_stm32f407/doc/img/segger_trb_stm32f407.jpg similarity index 100% rename from boards/arm/segger_trb_stm32f407/doc/img/segger_trb_stm32f407.jpg rename to boards/segger/trb_stm32f407/doc/img/segger_trb_stm32f407.jpg diff --git a/boards/arm/segger_trb_stm32f407/doc/index.rst b/boards/segger/trb_stm32f407/doc/index.rst similarity index 100% rename from boards/arm/segger_trb_stm32f407/doc/index.rst rename to boards/segger/trb_stm32f407/doc/index.rst diff --git a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.dts b/boards/segger/trb_stm32f407/segger_trb_stm32f407.dts similarity index 100% rename from boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.dts rename to boards/segger/trb_stm32f407/segger_trb_stm32f407.dts diff --git a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.yaml b/boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml similarity index 100% rename from boards/arm/segger_trb_stm32f407/segger_trb_stm32f407.yaml rename to boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml diff --git a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407_defconfig b/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig similarity index 86% rename from boards/arm/segger_trb_stm32f407/segger_trb_stm32f407_defconfig rename to boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig index 0ae4151a7d2175..9e96c29aafd2c2 100644 --- a/boards/arm/segger_trb_stm32f407/segger_trb_stm32f407_defconfig +++ b/boards/segger/trb_stm32f407/segger_trb_stm32f407_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst index 330a8ffd11a1e7..209b30293890a3 100644 --- a/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst +++ b/boards/shields/adafruit_2_8_tft_touch_v2/doc/index.rst @@ -61,7 +61,7 @@ Set ``-DSHIELD=adafruit_2_8_tft_touch_v2`` when you invoke ``west build``. For e .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: adafruit_2_8_tft_touch_v2 :goals: build diff --git a/boards/shields/adafruit_pca9685/doc/index.rst b/boards/shields/adafruit_pca9685/doc/index.rst index cb3e08e0d3ff19..ee6f1649fce525 100644 --- a/boards/shields/adafruit_pca9685/doc/index.rst +++ b/boards/shields/adafruit_pca9685/doc/index.rst @@ -32,7 +32,7 @@ For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_pwm - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: adafruit_pca9685 :goals: build diff --git a/boards/shields/arceli_eth_w5500/doc/index.rst b/boards/shields/arceli_eth_w5500/doc/index.rst index 359a91e482ae9f..467559be88163f 100644 --- a/boards/shields/arceli_eth_w5500/doc/index.rst +++ b/boards/shields/arceli_eth_w5500/doc/index.rst @@ -43,7 +43,7 @@ Set ``-DSHIELD=arceli_eth_w5500`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/net/dhcpv4_client - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: arceli_eth_w5500 :goals: build diff --git a/boards/shields/arduino_uno_click/doc/index.rst b/boards/shields/arduino_uno_click/doc/index.rst index c13c3cb8d8c38a..4e260a7db432e0 100644 --- a/boards/shields/arduino_uno_click/doc/index.rst +++ b/boards/shields/arduino_uno_click/doc/index.rst @@ -44,7 +44,7 @@ other mikroBUS shields. For example: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: sam_v71_xult + :board: sam_v71_xult/samv71q21 :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf :shield: "arduino_uno_click atmel_rf2xx_mikrobus" :goals: build diff --git a/boards/shields/atmel_rf2xx/doc/index.rst b/boards/shields/atmel_rf2xx/doc/index.rst index e9d2777fafe570..31670bf936daf0 100644 --- a/boards/shields/atmel_rf2xx/doc/index.rst +++ b/boards/shields/atmel_rf2xx/doc/index.rst @@ -265,15 +265,15 @@ details). Tested Boards ============= -+-----------------------------+------------------------------+-----------+ -| Board | Disabled Interface | Variation | -+=============================+==============================+===========+ -| ATMEL sam4s_xplained | | 2 | -+-----------------------------+------------------------------+-----------+ -| ATMEL sam4e_xpro | Ethernet | 3 , 4 | -+-----------------------------+------------------------------+-----------+ -| ATMEL sam_v71_xult | Ethernet | 3 , 4 , 5 | -+-----------------------------+------------------------------+-----------+ ++------------------------------+------------------------------+-----------+ +| Board | Disabled Interface | Variation | ++==============================+==============================+===========+ +| ATMEL sam4s_xplained | | 2 | ++------------------------------+------------------------------+-----------+ +| ATMEL sam4e_xpro | Ethernet | 3 , 4 | ++------------------------------+------------------------------+-----------+ +| ATMEL sam_v71_xult/samv71q21 | Ethernet | 3 , 4 , 5 | ++------------------------------+------------------------------+-----------+ Sample usage ************ @@ -303,7 +303,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: [sam4e_xpro | sam_v71_xult] + :board: [sam4e_xpro | sam_v71_xult/samv71q21] :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf :shield: [atmel_rf2xx_xpro | atmel_rf2xx_legacy] :goals: build flash @@ -312,7 +312,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: [sam_v71_xult | frdm_k64f | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi] :gen-args: -DOVERLAY_CONFIG=overlay-802154.conf :shield: atmel_rf2xx_arduino :goals: build flash diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst b/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst index ec62df14bf5765..ccd4fd1b410857 100644 --- a/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst +++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/doc/index.rst @@ -61,7 +61,7 @@ Set ``-DSHIELD=buydisplay_2_8_tft_touch_arduino`` when you invoke .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: buydisplay_2_8_tft_touch_arduino :goals: build diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst b/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst index 7950e967391276..bd8a505339f9c0 100644 --- a/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst +++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/doc/index.rst @@ -63,7 +63,7 @@ Set ``-DSHIELD=buydisplay_3_5_tft_touch_arduino`` when you invoke .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: buydisplay_3_5_tft_touch_arduino :goals: build diff --git a/boards/shields/ftdi_vm800c/doc/index.rst b/boards/shields/ftdi_vm800c/doc/index.rst index df72ff21111784..b1d2ab2d765393 100644 --- a/boards/shields/ftdi_vm800c/doc/index.rst +++ b/boards/shields/ftdi_vm800c/doc/index.rst @@ -80,7 +80,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/drivers/misc/ft800 :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: ftdi_vm800c :goals: build flash :compact: diff --git a/boards/shields/g1120b0mipi/boards/mimxrt1170_evk_cm7.overlay b/boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt1170_evk_cm7.overlay rename to boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/boards/shields/g1120b0mipi/boards/mimxrt1170_evkb_cm7.overlay b/boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt1170_evkb_cm7.overlay rename to boards/shields/g1120b0mipi/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.conf b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.conf rename to boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.overlay b/boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from boards/shields/g1120b0mipi/boards/mimxrt595_evk_cm33.overlay rename to boards/shields/g1120b0mipi/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/boards/shields/g1120b0mipi/doc/index.rst b/boards/shields/g1120b0mipi/doc/index.rst index ccfeae05833579..d13a4b49edcb67 100644 --- a/boards/shields/g1120b0mipi/doc/index.rst +++ b/boards/shields/g1120b0mipi/doc/index.rst @@ -55,7 +55,7 @@ example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: mimxrt595_evk_cm33 + :board: mimxrt595_evk/mimxrt595s/cm33 :shield: g1120b0mipi :goals: build diff --git a/boards/shields/index.rst b/boards/shields/index.rst deleted file mode 100644 index 5a73aba302def1..00000000000000 --- a/boards/shields/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-shields: - -Shields -####### - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/shields/inventek_eswifi/doc/index.rst b/boards/shields/inventek_eswifi/doc/index.rst index e19713acd3f957..9b0d9a46e1da3e 100644 --- a/boards/shields/inventek_eswifi/doc/index.rst +++ b/boards/shields/inventek_eswifi/doc/index.rst @@ -121,15 +121,15 @@ details). Tested Boards ============= -+-----------------------------+------------------------------+-----------+ -| Board | Disabled Interface | Variation | -+=============================+==============================+===========+ -| ATMEL sam_v71_xult | Ethernet | 2 , 3 | -+-----------------------------+------------------------------+-----------+ -| ST nucleo_f767zi | Ethernet | 2 , 3 | -+-----------------------------+------------------------------+-----------+ -| ST disco_l475_iot1 | | - | -+-----------------------------+------------------------------+-----------+ ++------------------------------+------------------------------+-----------+ +| Board | Disabled Interface | Variation | ++==============================+==============================+===========+ +| ATMEL sam_v71_xult/samv71q21 | Ethernet | 2 , 3 | ++------------------------------+------------------------------+-----------+ +| ST nucleo_f767zi | Ethernet | 2 , 3 | ++------------------------------+------------------------------+-----------+ +| ST disco_l475_iot1 | | - | ++------------------------------+------------------------------+-----------+ .. note:: ST disco_l475_iot1 already have an ISM43362 module with IWIN SPI @@ -152,7 +152,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/wifi :host-os: unix - :board: [sam_v71_xult | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | nucleo_f767zi] :shield: inventek_eswifi_arduino_uart :goals: build flash :compact: @@ -160,7 +160,7 @@ Set ``-DSHIELD=`` when you invoke ``west build``. .. zephyr-app-commands:: :zephyr-app: samples/net/wifi :host-os: unix - :board: [sam_v71_xult | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | nucleo_f767zi] :shield: inventek_eswifi_arduino_spi :goals: build flash :compact: diff --git a/boards/shields/ls0xx_generic/doc/index.rst b/boards/shields/ls0xx_generic/doc/index.rst index aec3c35e5dd9c0..415dbb0227ca36 100644 --- a/boards/shields/ls0xx_generic/doc/index.rst +++ b/boards/shields/ls0xx_generic/doc/index.rst @@ -92,7 +92,7 @@ Set ``-DSHIELD=ls013b7dh03`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: ls013b7dh03 :goals: build diff --git a/boards/shields/m5stack_core2_ext/doc/index.rst b/boards/shields/m5stack_core2_ext/doc/index.rst index 691ad98f4a22b7..9fdcf5bd0a09cf 100644 --- a/boards/shields/m5stack_core2_ext/doc/index.rst +++ b/boards/shields/m5stack_core2_ext/doc/index.rst @@ -43,7 +43,7 @@ For example: .. zephyr-app-commands:: :zephyr-app: samples/sensor/mpu6050 - :board: m5stack_core2 + :board: m5stack_core2/esp32/procpu :shield: m5stack_core2_ext :goals: build diff --git a/boards/shields/max7219/doc/index.rst b/boards/shields/max7219/doc/index.rst index 7413ec4e461e8f..8cc105545030fb 100644 --- a/boards/shields/max7219/doc/index.rst +++ b/boards/shields/max7219/doc/index.rst @@ -35,6 +35,6 @@ Set ``-DSHIELD=max7219_8x8`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/display/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: max7219_8x8 :goals: build diff --git a/boards/shields/mcp2515/doc/index.rst b/boards/shields/mcp2515/doc/index.rst index fd35aa0b2eb6e4..70082c0b9ccd5a 100644 --- a/boards/shields/mcp2515/doc/index.rst +++ b/boards/shields/mcp2515/doc/index.rst @@ -346,14 +346,14 @@ example: .. zephyr-app-commands:: :zephyr-app: samples/drivers/can/counter :tool: all - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :shield: dfrobot_can_bus_v2_0 :goals: build flash .. zephyr-app-commands:: :zephyr-app: samples/drivers/can/counter :tool: all - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: keyestudio_can_bus_ks0411 :goals: build flash diff --git a/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.conf b/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.conf rename to boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.overlay b/boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_cm33.overlay rename to boards/shields/rk055hdmipi4m/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.conf b/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.conf rename to boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.overlay b/boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_cm33.overlay rename to boards/shields/rk055hdmipi4ma0/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/boards/shields/st7735r/doc/index.rst b/boards/shields/st7735r/doc/index.rst index 015396b9690ef1..3004fde61637ac 100644 --- a/boards/shields/st7735r/doc/index.rst +++ b/boards/shields/st7735r/doc/index.rst @@ -54,7 +54,7 @@ Set ``-DSHIELD=st7735r_ada_160x128`` when you invoke ``west build``. For example .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: st7735r_ada_160x128 :goals: build diff --git a/boards/shields/st7789v_generic/doc/index.rst b/boards/shields/st7789v_generic/doc/index.rst index 8f16d5bf9d57d4..d9282b60bf9ecc 100644 --- a/boards/shields/st7789v_generic/doc/index.rst +++ b/boards/shields/st7789v_generic/doc/index.rst @@ -57,7 +57,7 @@ Set ``-DSHIELD=st7789v_tl019fqv01`` when you invoke ``west build``. For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: st7789v_tl019fqv01 :goals: build diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf similarity index 100% rename from boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.conf rename to boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.conf diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_m7.overlay rename to boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst index 815b65f57501d2..4e71b025ee386d 100644 --- a/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst +++ b/boards/shields/st_b_lcd40_dsi1_mb1166/doc/index.rst @@ -107,7 +107,7 @@ Set ``-DSHIELD="st_b_lcd40_dsi1_mb1166"`` when you invoke ``west build``. For ex .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: stm32h747i_disco_m7 + :board: stm32h747i_disco/stm32h747xx/m7 :shield: st_b_lcd40_dsi1_mb1166 :goals: build diff --git a/boards/shields/waveshare_epaper/doc/index.rst b/boards/shields/waveshare_epaper/doc/index.rst index 127d8af728e008..876ba1d107e8cd 100644 --- a/boards/shields/waveshare_epaper/doc/index.rst +++ b/boards/shields/waveshare_epaper/doc/index.rst @@ -83,7 +83,7 @@ For example: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: waveshare_epaper_gdeh0213b1 :goals: build diff --git a/boards/sifive/hifive1/Kconfig b/boards/sifive/hifive1/Kconfig new file mode 100644 index 00000000000000..304048665a7768 --- /dev/null +++ b/boards/sifive/hifive1/Kconfig @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE1 + select RISCV_CORE_E31 if "$(BOARD_REVISION)" = "B" diff --git a/boards/sifive/hifive1/Kconfig.defconfig b/boards/sifive/hifive1/Kconfig.defconfig new file mode 100644 index 00000000000000..841e2c9ce419a3 --- /dev/null +++ b/boards/sifive/hifive1/Kconfig.defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +if BOARD_HIFIVE1_FE310 + +config SYS_CLOCK_TICKS_PER_SEC + default 128 + +if "$(BOARD_REVISION)" = "B" + +config HAS_FLASH_LOAD_OFFSET + default y + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) + +config FLASH_LOAD_OFFSET + default 0x0 + +endif # "$(BOARD_REVISION)" = "B" + +endif # BOARD_HIFIVE1_FE310 diff --git a/boards/sifive/hifive1/Kconfig.hifive1 b/boards/sifive/hifive1/Kconfig.hifive1 new file mode 100644 index 00000000000000..29132f70288e66 --- /dev/null +++ b/boards/sifive/hifive1/Kconfig.hifive1 @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE1 + select SOC_SIFIVE_FREEDOM_FE310 diff --git a/boards/sifive/hifive1/board.cmake b/boards/sifive/hifive1/board.cmake new file mode 100644 index 00000000000000..4f39320870c18a --- /dev/null +++ b/boards/sifive/hifive1/board.cmake @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +set(SUPPORTED_EMU_PLATFORMS renode qemu) +set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/hifive1.resc) +set(RENODE_UART sysbus.uart0) + +set(QEMU_binary_suffix riscv32) +set(QEMU_CPU_TYPE_${ARCH} riscv32) + +set(QEMU_FLAGS_${ARCH} + -nographic + -machine sifive_e + ) + +if("${BOARD_REVISION}" STREQUAL "A") + board_set_flasher_ifnset(hifive1) + board_finalize_runner_args(hifive1) + board_runner_args(openocd --cmd-load "hifive1-load") + board_runner_args(openocd --cmd-reset-halt "hifive1-reset-halt") + board_runner_args(openocd --cmd-post-verify "hifive1-post-verify") + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +elseif("${BOARD_REVISION}" STREQUAL "B") + board_runner_args(jlink "--device=FE310") + board_runner_args(jlink "--iface=JTAG") + board_runner_args(jlink "--speed=4000") + board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") + board_runner_args(jlink "--tool-opt=-autoconnect 1") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +endif() diff --git a/boards/sifive/hifive1/board.yml b/boards/sifive/hifive1/board.yml new file mode 100644 index 00000000000000..2909cb5aaeb959 --- /dev/null +++ b/boards/sifive/hifive1/board.yml @@ -0,0 +1,11 @@ +board: + name: hifive1 + vendor: sifive + socs: + - name: fe310 + revision: + format: letter + default: "A" + revisions: + - name: "A" + - name: "B" diff --git a/boards/riscv/hifive1/doc/img/hifive1.jpg b/boards/sifive/hifive1/doc/img/hifive1.jpg similarity index 100% rename from boards/riscv/hifive1/doc/img/hifive1.jpg rename to boards/sifive/hifive1/doc/img/hifive1.jpg diff --git a/boards/riscv/hifive1_revb/doc/img/hifive1_revb.jpg b/boards/sifive/hifive1/doc/img/hifive1_revb.jpg similarity index 100% rename from boards/riscv/hifive1_revb/doc/img/hifive1_revb.jpg rename to boards/sifive/hifive1/doc/img/hifive1_revb.jpg diff --git a/boards/sifive/hifive1/doc/index.rst b/boards/sifive/hifive1/doc/index.rst new file mode 100644 index 00000000000000..2c3d2ba1fb6a7a --- /dev/null +++ b/boards/sifive/hifive1/doc/index.rst @@ -0,0 +1,97 @@ +.. _hifive1: + +SiFive HiFive1 +############## + +Overview +******** + +The HiFive1 is an Arduino-compatible development board with +an FE310 RISC-V SoC. Two revisions of this board are supported in Zephyr: +`HiFive1 `__ (also known as HiFive1 Rev A) +and `HiFive1 Rev B `__. + +.. figure:: img/hifive1.jpg + :align: center + :alt: SiFive HiFive1 board + + SiFive HiFive1 board (image courtesy of SiFive) + +.. figure:: img/hifive1_revb.jpg + :align: center + :alt: SiFive HiFive1 Rev B board + + SiFive HiFive1 Rev B board (image courtesy of SiFive) + +Programming and debugging +************************* + +Building +======== + +Applications for the HiFive1 board configuration can be built as usual (see +:ref:`build_an_application`) using the corresponding board name: + +.. tabs:: + + .. group-tab:: HiFive1 + + .. zephyr-app-commands:: + :board: hifive1 + :goals: build + + .. group-tab:: HiFive1 Rev B + + .. zephyr-app-commands:: + :board: hifive1@B + :goals: build + +Flashing +======== + + +HiFive1 +------- + +.. tabs:: + + .. group-tab:: HiFive1 + + In order to upload the application to the device, you'll need OpenOCD with + RISC-V support. Download the tarball for your OS from the `SiFive website + `_ and extract it. + + The Zephyr SDK uses a bundled version of OpenOCD by default. You can + overwrite that behavior by adding the + ``-DOPENOCD=`` parameter when building: + + .. zephyr-app-commands:: + :board: hifive1 + :goals: build + :gen-args: -DOPENOCD= + + When using a custom toolchain it should be enough to have the downloaded + version of the binary in your ``PATH``. + + .. group-tab:: HiFive1 Rev B + + The HiFive 1 Rev B uses Segger J-Link OB for flashing and debugging. To flash and + debug the board, you'll need to install the + `Segger J-Link Software and Documentation Pack + `_ + and choose version V6.46a or later (Downloads for Windows, Linux, and macOS are + available). + +Now you can flash the application as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details): + +.. code-block:: console + + west flash + +Depending on your OS you might have to run the flash command as superuser. + +Debugging +========= + +Refer to the detailed overview about :ref:`application_debugging`. diff --git a/boards/riscv/hifive1/hifive1-pinctrl.dtsi b/boards/sifive/hifive1/hifive1-pinctrl.dtsi similarity index 100% rename from boards/riscv/hifive1/hifive1-pinctrl.dtsi rename to boards/sifive/hifive1/hifive1-pinctrl.dtsi diff --git a/boards/riscv/hifive1/hifive1.dts b/boards/sifive/hifive1/hifive1.dts similarity index 100% rename from boards/riscv/hifive1/hifive1.dts rename to boards/sifive/hifive1/hifive1.dts diff --git a/boards/riscv/hifive1/hifive1.yaml b/boards/sifive/hifive1/hifive1.yaml similarity index 100% rename from boards/riscv/hifive1/hifive1.yaml rename to boards/sifive/hifive1/hifive1.yaml diff --git a/boards/sifive/hifive1/hifive1_defconfig b/boards/sifive/hifive1/hifive1_defconfig new file mode 100644 index 00000000000000..21c46be1caf86a --- /dev/null +++ b/boards/sifive/hifive1/hifive1_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_PINCTRL=y +CONFIG_GPIO=y diff --git a/boards/sifive/hifive1/hifive1_fe310_A_defconfig b/boards/sifive/hifive1/hifive1_fe310_A_defconfig new file mode 100644 index 00000000000000..7fe6d1a00e7c2e --- /dev/null +++ b/boards/sifive/hifive1/hifive1_fe310_A_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 SiFive, Inc. + +CONFIG_BUILD_OUTPUT_HEX=y diff --git a/boards/sifive/hifive1/hifive1_fe310_B.overlay b/boards/sifive/hifive1/hifive1_fe310_B.overlay new file mode 100644 index 00000000000000..e4afe2eef67fb7 --- /dev/null +++ b/boards/sifive/hifive1/hifive1_fe310_B.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024 Antmicro + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + model = "SiFive HiFive 1 Rev. B"; + compatible = "sifive,hifive1_revb"; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; + +&spi2 { + status = "okay"; + pinctrl-0 = <&spi1_cs2_default + &spi1_mosi_default + &spi1_miso_default + &spi1_sck_default>; + pinctrl-names = "default"; +}; diff --git a/boards/sifive/hifive1/hifive1_fe310_B.yaml b/boards/sifive/hifive1/hifive1_fe310_B.yaml new file mode 100644 index 00000000000000..8a82df4ab185c0 --- /dev/null +++ b/boards/sifive/hifive1/hifive1_fe310_B.yaml @@ -0,0 +1,17 @@ +identifier: hifive1@B +name: SiFive HiFive1 Rev B +type: mcu +arch: riscv +toolchain: + - zephyr +ram: 16 +testing: + ignore_tags: + - net + - bluetooth +supported: + - arduino_gpio + - arduino_i2c + - gpio + - i2c +vendor: sifive diff --git a/boards/riscv/hifive1/support/hifive1.resc b/boards/sifive/hifive1/support/hifive1.resc similarity index 100% rename from boards/riscv/hifive1/support/hifive1.resc rename to boards/sifive/hifive1/support/hifive1.resc diff --git a/boards/riscv/hifive1/support/openocd.cfg b/boards/sifive/hifive1/support/openocd.cfg similarity index 100% rename from boards/riscv/hifive1/support/openocd.cfg rename to boards/sifive/hifive1/support/openocd.cfg diff --git a/boards/sifive/hifive_unleashed/Kconfig.defconfig b/boards/sifive/hifive_unleashed/Kconfig.defconfig new file mode 100644 index 00000000000000..24541a6af9ccd7 --- /dev/null +++ b/boards/sifive/hifive_unleashed/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HIFIVE_UNLEASHED + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # BOARD_HIFIVE_UNLEASHED diff --git a/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed b/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed new file mode 100644 index 00000000000000..2fc2f15d50f6a5 --- /dev/null +++ b/boards/sifive/hifive_unleashed/Kconfig.hifive_unleashed @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE_UNLEASHED + select SOC_SIFIVE_FREEDOM_FU540 diff --git a/boards/riscv/hifive_unleashed/board.cmake b/boards/sifive/hifive_unleashed/board.cmake similarity index 100% rename from boards/riscv/hifive_unleashed/board.cmake rename to boards/sifive/hifive_unleashed/board.cmake diff --git a/boards/sifive/hifive_unleashed/board.yml b/boards/sifive/hifive_unleashed/board.yml new file mode 100644 index 00000000000000..f9dd3ce6e6b22e --- /dev/null +++ b/boards/sifive/hifive_unleashed/board.yml @@ -0,0 +1,5 @@ +board: + name: hifive_unleashed + vendor: sifive + socs: + - name: fu540 diff --git a/boards/riscv/hifive_unleashed/doc/img/hifive_unleashed.jpg b/boards/sifive/hifive_unleashed/doc/img/hifive_unleashed.jpg similarity index 100% rename from boards/riscv/hifive_unleashed/doc/img/hifive_unleashed.jpg rename to boards/sifive/hifive_unleashed/doc/img/hifive_unleashed.jpg diff --git a/boards/riscv/hifive_unleashed/doc/index.rst b/boards/sifive/hifive_unleashed/doc/index.rst similarity index 100% rename from boards/riscv/hifive_unleashed/doc/index.rst rename to boards/sifive/hifive_unleashed/doc/index.rst diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed.dts b/boards/sifive/hifive_unleashed/hifive_unleashed.dts similarity index 100% rename from boards/riscv/hifive_unleashed/hifive_unleashed.dts rename to boards/sifive/hifive_unleashed/hifive_unleashed.dts diff --git a/boards/riscv/hifive_unleashed/hifive_unleashed.yaml b/boards/sifive/hifive_unleashed/hifive_unleashed.yaml similarity index 100% rename from boards/riscv/hifive_unleashed/hifive_unleashed.yaml rename to boards/sifive/hifive_unleashed/hifive_unleashed.yaml diff --git a/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig b/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig new file mode 100644 index 00000000000000..39b107d3455328 --- /dev/null +++ b/boards/sifive/hifive_unleashed/hifive_unleashed_defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_GPIO=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n diff --git a/boards/riscv/hifive_unleashed/support/hifive_unleashed.resc b/boards/sifive/hifive_unleashed/support/hifive_unleashed.resc similarity index 100% rename from boards/riscv/hifive_unleashed/support/hifive_unleashed.resc rename to boards/sifive/hifive_unleashed/support/hifive_unleashed.resc diff --git a/boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg b/boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg similarity index 100% rename from boards/riscv/hifive_unleashed/support/openocd_hifive_unleashed.cfg rename to boards/sifive/hifive_unleashed/support/openocd_hifive_unleashed.cfg diff --git a/boards/sifive/hifive_unmatched/Kconfig.defconfig b/boards/sifive/hifive_unmatched/Kconfig.defconfig new file mode 100644 index 00000000000000..3ced33713cb146 --- /dev/null +++ b/boards/sifive/hifive_unmatched/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HIFIVE_UNMATCHED + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # BOARD_HIFIVE_UNMATCHED diff --git a/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched b/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched new file mode 100644 index 00000000000000..87911f3ccb3cc4 --- /dev/null +++ b/boards/sifive/hifive_unmatched/Kconfig.hifive_unmatched @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Katsuhiro Suzuki +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HIFIVE_UNMATCHED + select SOC_SIFIVE_FREEDOM_FU740 diff --git a/boards/riscv/hifive_unmatched/board.cmake b/boards/sifive/hifive_unmatched/board.cmake similarity index 100% rename from boards/riscv/hifive_unmatched/board.cmake rename to boards/sifive/hifive_unmatched/board.cmake diff --git a/boards/sifive/hifive_unmatched/board.yml b/boards/sifive/hifive_unmatched/board.yml new file mode 100644 index 00000000000000..703d94e852b3ae --- /dev/null +++ b/boards/sifive/hifive_unmatched/board.yml @@ -0,0 +1,5 @@ +board: + name: hifive_unmatched + vendor: sifive + socs: + - name: fu740 diff --git a/boards/riscv/hifive_unmatched/doc/img/hifive_unmatched.jpg b/boards/sifive/hifive_unmatched/doc/img/hifive_unmatched.jpg similarity index 100% rename from boards/riscv/hifive_unmatched/doc/img/hifive_unmatched.jpg rename to boards/sifive/hifive_unmatched/doc/img/hifive_unmatched.jpg diff --git a/boards/riscv/hifive_unmatched/doc/index.rst b/boards/sifive/hifive_unmatched/doc/index.rst similarity index 100% rename from boards/riscv/hifive_unmatched/doc/index.rst rename to boards/sifive/hifive_unmatched/doc/index.rst diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched.dts b/boards/sifive/hifive_unmatched/hifive_unmatched.dts similarity index 100% rename from boards/riscv/hifive_unmatched/hifive_unmatched.dts rename to boards/sifive/hifive_unmatched/hifive_unmatched.dts diff --git a/boards/riscv/hifive_unmatched/hifive_unmatched.yaml b/boards/sifive/hifive_unmatched/hifive_unmatched.yaml similarity index 100% rename from boards/riscv/hifive_unmatched/hifive_unmatched.yaml rename to boards/sifive/hifive_unmatched/hifive_unmatched.yaml diff --git a/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig b/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig new file mode 100644 index 00000000000000..02295cf19df96d --- /dev/null +++ b/boards/sifive/hifive_unmatched/hifive_unmatched_defconfig @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y +CONFIG_XIP=n diff --git a/boards/riscv/hifive_unmatched/support/hifive_unmatched.resc b/boards/sifive/hifive_unmatched/support/hifive_unmatched.resc similarity index 100% rename from boards/riscv/hifive_unmatched/support/hifive_unmatched.resc rename to boards/sifive/hifive_unmatched/support/hifive_unmatched.resc diff --git a/boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg b/boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg similarity index 100% rename from boards/riscv/hifive_unmatched/support/openocd_hifive_unmatched.cfg rename to boards/sifive/hifive_unmatched/support/openocd_hifive_unmatched.cfg diff --git a/boards/sifive/index.rst b/boards/sifive/index.rst new file mode 100644 index 00000000000000..2249014c08e595 --- /dev/null +++ b/boards/sifive/index.rst @@ -0,0 +1,10 @@ +.. _boards-sifive: + +SiFive +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig b/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig new file mode 100644 index 00000000000000..a24eda68abd036 --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/Kconfig.defconfig @@ -0,0 +1,20 @@ +# EFM32GG SLTB009A default board configuration +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_SLTB009A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +endif # BOARD_EFM32GG_SLTB009A diff --git a/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a b/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a new file mode 100644 index 00000000000000..e1f93ff9da9049 --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/Kconfig.efm32gg_sltb009a @@ -0,0 +1,6 @@ +# EFM32GG SLTB009A board configuration +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32GG_SLTB009A + select SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/boards/arm/efm32gg_sltb009a/board.cmake b/boards/silabs/efm32gg_sltb009a/board.cmake similarity index 100% rename from boards/arm/efm32gg_sltb009a/board.cmake rename to boards/silabs/efm32gg_sltb009a/board.cmake diff --git a/boards/silabs/efm32gg_sltb009a/board.yml b/boards/silabs/efm32gg_sltb009a/board.yml new file mode 100644 index 00000000000000..388301f55e1f28 --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32gg_sltb009a + vendor: silabs + socs: + - name: efm32gg12b810f1024gm64 diff --git a/boards/arm/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg b/boards/silabs/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg similarity index 100% rename from boards/arm/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg rename to boards/silabs/efm32gg_sltb009a/doc/efm32gg12-thunderboard-kit.jpg diff --git a/boards/silabs/efm32gg_sltb009a/doc/index.rst b/boards/silabs/efm32gg_sltb009a/doc/index.rst new file mode 100644 index 00000000000000..e27fcc34ba0f05 --- /dev/null +++ b/boards/silabs/efm32gg_sltb009a/doc/index.rst @@ -0,0 +1,165 @@ +.. _efm32gg_sltb009a: + +EFM32GG12 Thunderboard Kit +########################## + +Overview +******** + +The EFM32GG12 Thunderboard Kit (SLTB009A) is an evaluation platform for the EFM32GG12 GiantGecko Microcontroller, +featuring an ARM Cortex-M4 with FPU, 1024kB flash, and 192kB RAM. + +.. figure:: efm32gg12-thunderboard-kit.jpg + :align: center + :alt: SLTB009A + + SLTB009A (Credit: Silicon Labs) + +Hardware +******** + +- PDM stereo microphones +- USB connectivity +- On-board Segger J-Link USB debugger +- 2 user buttons and 2 LEDs +- USB C connector + +For more information about the WGM160P and SLTB009A board: + +- `SLTB009A Website`_ +- `SLTB009A User Guide`_ +- `EFM32GG12 Datasheet`_ +- `EFM32GG12 Reference Manual`_ + +Supported Features +================== + +The efm32gg_sltb009a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig` + +Connections and IOs +=================== + +The EFM32GG12 MCU has six GPIO controllers (PORTA to PORTF), all of which are +currently enabled for the SLTB009A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PE12 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA13 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PD5 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PD8 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | ++-------+-------------+-------------------------------------+ +| PC0 | I2C_SDA | SENSOR_I2C_SDA I2C0_SDA #1 | ++-------+-------------+-------------------------------------+ +| PC1 | I2C_SCL | SENSOR_I2C_SCL I2C0_SCL #1 | ++-------+-------------+-------------------------------------+ +| PC4 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | ++-------+-------------+-------------------------------------+ +| PC5 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG12 MCU is configured to work at 72 MHz. + +Serial Port +=========== + +The EFM32GG12 SoC has five USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLTB009A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLTB009A +-------------------------------------- + +Connect the SLTB009A to your host computer using the USB port. + +Here is an example to build and flash the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32gg_stb009a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efm32gg_sltb009a + +.. _SLTB009A Website: + https://www.silabs.com/development-tools/thunderboard/thunderboard-gg12-kit + +.. _SLTB009A User Guide: + https://www.silabs.com/documents/public/user-guides/ug371-sltb009a-user-guide.pdf + +.. _EFM32GG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg12-datasheet.pdf + +.. _EFM32GG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a-pinctrl.dtsi diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.dts b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.dts similarity index 100% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.dts rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.dts diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.yaml b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.yaml similarity index 100% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a.yaml rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a.yaml diff --git a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig similarity index 79% rename from boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig rename to boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig index 31f29cf85e5c97..2cfd7572706ba8 100644 --- a/boards/arm/efm32gg_sltb009a/efm32gg_sltb009a_defconfig +++ b/boards/silabs/efm32gg_sltb009a/efm32gg_sltb009a_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2023 Antmicro # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32GG12B=y -CONFIG_BOARD_EFM32GG_SLTB009A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/efm32gg_slwstk6121a/CMakeLists.txt b/boards/silabs/efm32gg_slwstk6121a/CMakeLists.txt similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/CMakeLists.txt rename to boards/silabs/efm32gg_slwstk6121a/CMakeLists.txt diff --git a/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig b/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig new file mode 100644 index 00000000000000..33e5b1192c0fec --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/Kconfig.defconfig @@ -0,0 +1,29 @@ +# EFM32GG SLWSTK6121A default board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# Copyright (c) 2020 Thorvald Natvig +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_SLWSTK6121A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_EFM32GG_SLWSTK6121A diff --git a/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a b/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a new file mode 100644 index 00000000000000..2e064a306f1193 --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/Kconfig.efm32gg_slwstk6121a @@ -0,0 +1,8 @@ +# EFM32GG SLWSTK6121A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# Copyright (c) 2020 Thorvald Natvig +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32GG_SLWSTK6121A + select SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/boards/arm/efm32gg_slwstk6121a/board.c b/boards/silabs/efm32gg_slwstk6121a/board.c similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/board.c rename to boards/silabs/efm32gg_slwstk6121a/board.c diff --git a/boards/arm/efm32gg_slwstk6121a/board.cmake b/boards/silabs/efm32gg_slwstk6121a/board.cmake similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/board.cmake rename to boards/silabs/efm32gg_slwstk6121a/board.cmake diff --git a/boards/arm/efm32gg_slwstk6121a/board.h b/boards/silabs/efm32gg_slwstk6121a/board.h similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/board.h rename to boards/silabs/efm32gg_slwstk6121a/board.h diff --git a/boards/silabs/efm32gg_slwstk6121a/board.yml b/boards/silabs/efm32gg_slwstk6121a/board.yml new file mode 100644 index 00000000000000..7f91de02759384 --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32gg_slwstk6121a + vendor: silabs + socs: + - name: efm32gg11b820f2048gm64 diff --git a/boards/silabs/efm32gg_slwstk6121a/doc/index.rst b/boards/silabs/efm32gg_slwstk6121a/doc/index.rst new file mode 100644 index 00000000000000..47d2a5a93a10f2 --- /dev/null +++ b/boards/silabs/efm32gg_slwstk6121a/doc/index.rst @@ -0,0 +1,186 @@ +.. _efm32gg_slwstk6121a: + +WGM160P Starter Kit +################### + +Overview +******** + +The WGM160P Starter Kit SLWSTK6121A comes with the BRD4321A radio board. +This radio boards contains a WGM160P module, which combines the WF200 Wi-Fi +transceiver with an EFM32GG11 microcontroller. + +.. figure:: wgm160p-starter-kit.jpg + :align: center + :alt: SLWSTK6121A + + SLWSTK6121A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel color Memory-LCD +- 2 user buttons and 2 LEDs +- Si7021 Humidity and Temperature Sensor +- On-board Segger J-Link USB and Ethernet debugger +- 10/100Base-TX ethernet PHY and RJ-45 jack (on included expansion board) +- MicroSD card slot +- USB Micro-AB connector + +For more information about the WGM160P and SLWSTK6121A board: + +- `WGM160P Website`_ +- `WGM160P Datasheet`_ +- `SLWSTK6121A Website`_ +- `SLWSTK6121A User Guide`_ +- `EFM32GG11 Datasheet`_ +- `EFM32GG11 Reference Manual`_ +- `WF200 Datasheet`_ + +Supported Features +================== + +The efm32gg_slwstk6121a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig` + +Other hardware features, including the WF200 WiFi transceiver, are +currently not supported by the port. + +Connections and IOs +=================== + +The WGM160P's EFM32GG11 SoC has six GPIO controllers (PORTA to PORTF), all of which are +currently enabled for the SLWSTK6121A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PD6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PD8 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE7 | UART_TX | UART TX Console VCOM_TX US0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE6 | UART_RX | UART RX Console VCOM_RX US0_RX #1 | ++-------+-------------+-------------------------------------+ +| PB11 | I2C_SDA | SENSOR_I2C_SDA I2C1_SDA #1 | ++-------+-------------+-------------------------------------+ +| PB12 | I2C_SCL | SENSOR_I2C_SCL I2C1_SCL #1 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32GG11 SoC has four USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The SLWSTK6121A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to SLWSTK6121A +-------------------------------------- + +Connect the SLWSTK6121A to your host computer using the USB port. + +Here is an example to build and flash the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32gg_slwstk6121a + :goals: flash + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efm32gg_slwstk6121a + +.. _WGM160P Website: + https://www.silabs.com/wireless/wi-fi/wfm160-series-1-modules + +.. _WGM160P Datasheet: + https://www.silabs.com/documents/public/data-sheets/wgm160p-datasheet.pdf + +.. _SLWSTK6121A Website: + https://www.silabs.com/development-tools/wireless/wi-fi/wgm160p-wifi-module-starter-kit + +.. _SLWSTK6121A User Guide: + https://www.silabs.com/documents/public/user-guides/ug351-brd4321a-user-guide.pdf + +.. _EFM32GG11 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf + +.. _EFM32GG11 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf + +.. _WF200 Datasheet: + https://www.silabs.com/documents/public/data-sheets/wf200-datasheet.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg b/boards/silabs/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg rename to boards/silabs/efm32gg_slwstk6121a/doc/wgm160p-starter-kit.jpg diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a-pinctrl.dtsi diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.dts diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a.yaml diff --git a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig similarity index 84% rename from boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig rename to boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig index 4eadfce741a39c..f7dfcb09cba846 100644 --- a/boards/arm/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig +++ b/boards/silabs/efm32gg_slwstk6121a/efm32gg_slwstk6121a_defconfig @@ -3,8 +3,6 @@ # Copyright (c) 2020 Thorvald Natvig # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32GG11B=y -CONFIG_BOARD_EFM32GG_SLWSTK6121A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/efm32gg_slwstk6121a/support/openocd.cfg b/boards/silabs/efm32gg_slwstk6121a/support/openocd.cfg similarity index 100% rename from boards/arm/efm32gg_slwstk6121a/support/openocd.cfg rename to boards/silabs/efm32gg_slwstk6121a/support/openocd.cfg diff --git a/boards/arm/efm32gg_stk3701a/CMakeLists.txt b/boards/silabs/efm32gg_stk3701a/CMakeLists.txt similarity index 100% rename from boards/arm/efm32gg_stk3701a/CMakeLists.txt rename to boards/silabs/efm32gg_stk3701a/CMakeLists.txt diff --git a/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig b/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig new file mode 100644 index 00000000000000..c56b944202f294 --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/Kconfig.defconfig @@ -0,0 +1,28 @@ +# EFM32GG STK3701A default board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_STK3701A + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_HFRCO_FREQ + default 72000000 + +config CMU_LFXO_FREQ + default 32768 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_EFM32GG_STK3701A diff --git a/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a b/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a new file mode 100644 index 00000000000000..058ea533a21466 --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/Kconfig.efm32gg_stk3701a @@ -0,0 +1,7 @@ +# EFM32GG STK3701A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32GG_STK3701A + select SOC_PART_NUMBER_EFM32GG11B820F2048GL192 diff --git a/boards/arm/efm32gg_stk3701a/board.c b/boards/silabs/efm32gg_stk3701a/board.c similarity index 100% rename from boards/arm/efm32gg_stk3701a/board.c rename to boards/silabs/efm32gg_stk3701a/board.c diff --git a/boards/arm/efm32gg_stk3701a/board.cmake b/boards/silabs/efm32gg_stk3701a/board.cmake similarity index 100% rename from boards/arm/efm32gg_stk3701a/board.cmake rename to boards/silabs/efm32gg_stk3701a/board.cmake diff --git a/boards/arm/efm32gg_stk3701a/board.h b/boards/silabs/efm32gg_stk3701a/board.h similarity index 100% rename from boards/arm/efm32gg_stk3701a/board.h rename to boards/silabs/efm32gg_stk3701a/board.h diff --git a/boards/silabs/efm32gg_stk3701a/board.yml b/boards/silabs/efm32gg_stk3701a/board.yml new file mode 100644 index 00000000000000..d69afebb60bbe2 --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32gg_stk3701a + vendor: silabs + socs: + - name: efm32gg11b820f2048gl192 diff --git a/boards/arm/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg b/boards/silabs/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg similarity index 100% rename from boards/arm/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg rename to boards/silabs/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg diff --git a/boards/silabs/efm32gg_stk3701a/doc/index.rst b/boards/silabs/efm32gg_stk3701a/doc/index.rst new file mode 100644 index 00000000000000..ddb5a1f38d7cc2 --- /dev/null +++ b/boards/silabs/efm32gg_stk3701a/doc/index.rst @@ -0,0 +1,200 @@ +.. _efm32gg_stk3701a: + +EFM32 Giant Gecko GG11 Starter Kit +################################## + +Overview +******** + +The EFM32 Giant Gecko Starter Kit EFM32GG-STK3701A contains an MCU from the +EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent +low power capabilities. + +.. figure:: efm32gg_stk3701a.jpg + :align: center + :alt: EFM32GG-SLSTK3701A + + EFM32GG-SLSTK3701A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel color Memory-LCD +- 2 user buttons, 2 LEDs and a touch slider +- Relative humidity, magnetic Hall Effect and inductive-capacitive metal sensor +- USB interface for Host/Device/OTG +- 32 Mb Quad-SPI Flash memory +- SD card slot +- RJ-45 Ethernet jack +- 2 digital microphones +- On-board Segger J-Link USB debugger + +For more information about the EFM32GG11 SoC and EFM32GG-STK3701A board: + +- `EFM32GG Series 1 Website`_ +- `EFM32GG11 Datasheet`_ +- `EFM32GG11 Reference Manual`_ +- `EFM32GG-STK3701A Website`_ +- `EFM32GG-STK3701A User Guide`_ +- `EFM32GG-STK3701A Schematics`_ + +Supported Features +================== + +The efm32gg_stk3701a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32GG11 SoC has nine GPIO controllers (PORTA to PORTI), all of which are +currently enabled for the EFM32GG-STK3701A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PH10 | GPIO | LED0 red | ++-------+-------------+-------------------------------------+ +| PH11 | GPIO | LED0 green | ++-------+-------------+-------------------------------------+ +| PH12 | GPIO | LED0 blue | ++-------+-------------+-------------------------------------+ +| PH13 | GPIO | LED1 red | ++-------+-------------+-------------------------------------+ +| PH14 | GPIO | LED1 green | ++-------+-------------+-------------------------------------+ +| PH15 | GPIO | LED1 blue | ++-------+-------------+-------------------------------------+ +| PC8 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PC9 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE1 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PH4 | UART_TX | UART TX Console VCOM_TX US0_TX #4 | ++-------+-------------+-------------------------------------+ +| PH5 | UART_RX | UART RX Console VCOM_RX US0_RX #4 | ++-------+-------------+-------------------------------------+ +| PI4 | I2C_SDA | SENSOR_I2C_SDA I2C2_SDA #7 | ++-------+-------------+-------------------------------------+ +| PI5 | I2C_SCL | SENSOR_I2C_SCL I2C2_SCL #7 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32GG11 SoC has six USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART4 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32GG-STK3701A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to EFM32GG-STK3701A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32gg_stk3701a + :goals: build + +Connect the EFM32GG-STK3701A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3701A) and +a USB Serial Port. Copy the generated zephyr.bin to the STK3701A drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efm32gg_stk3701a + + +.. _EFM32GG-STK3701A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-giant-gecko-gg11-starter-kit + +.. _EFM32GG-STK3701A User Guide: + https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf + +.. _EFM32GG-STK3701A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2204A-B00-schematic.pdf + +.. _EFM32GG Series 1 Website: + https://www.silabs.com/products/mcu/32-bit/efm32-giant-gecko-s1 + +.. _EFM32GG11 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf + +.. _EFM32GG11 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a-pinctrl.dtsi diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.dts similarity index 100% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.dts diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.yaml b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.yaml similarity index 100% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.yaml rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a.yaml diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig similarity index 81% rename from boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig rename to boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig index 61c099b57261e2..76b773c1f7c160 100644 --- a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig +++ b/boards/silabs/efm32gg_stk3701a/efm32gg_stk3701a_defconfig @@ -2,8 +2,6 @@ # Copyright (c) 2019 Oane Kingma # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32GG11B=y -CONFIG_BOARD_EFM32GG_STK3701A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/efm32gg_stk3701a/support/openocd.cfg b/boards/silabs/efm32gg_stk3701a/support/openocd.cfg similarity index 100% rename from boards/arm/efm32gg_stk3701a/support/openocd.cfg rename to boards/silabs/efm32gg_stk3701a/support/openocd.cfg diff --git a/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig b/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig new file mode 100644 index 00000000000000..c15834e72295a9 --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32HG SLSTK3400A board + +# Copyright (c) 2018, Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32HG_SLSTK3400A + +config CMU_HFXO_FREQ + default 24000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32HG_SLSTK3400A diff --git a/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a b/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a new file mode 100644 index 00000000000000..3ab1289920f456 --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/Kconfig.efm32hg_slstk3400a @@ -0,0 +1,7 @@ +# EFM32HG SLSTK3400A board + +# Copyright (c) 2018, Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32HG_SLSTK3400A + select SOC_PART_NUMBER_EFM32HG322F64 diff --git a/boards/silabs/efm32hg_slstk3400a/board.yml b/boards/silabs/efm32hg_slstk3400a/board.yml new file mode 100644 index 00000000000000..8aae393fcae68b --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32hg_slstk3400a + vendor: silabs + socs: + - name: efm32hg322f64 diff --git a/boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg b/boards/silabs/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg similarity index 100% rename from boards/arm/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg rename to boards/silabs/efm32hg_slstk3400a/doc/efm32hg_slstk3400a.jpg diff --git a/boards/silabs/efm32hg_slstk3400a/doc/index.rst b/boards/silabs/efm32hg_slstk3400a/doc/index.rst new file mode 100644 index 00000000000000..a1e0b84f16d9c5 --- /dev/null +++ b/boards/silabs/efm32hg_slstk3400a/doc/index.rst @@ -0,0 +1,176 @@ +.. _efm32hg_slstk3400a: + +EFM32HG-SLSTK3400A +################## + +Overview +******** + +The EFM32 Happy Gecko Starter Kit EFM32HG-SLSTK3400A contains a MCU from the +EFM32HG family built on ARM® Cortex®-M0+ processor with excellent low +power capabilities. + +.. figure:: efm32hg_slstk3400a.jpg + :align: center + :alt: EFM32HG-SLSTK3400A + + EFM32HG-SLSTK3400A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring system for precise current tracking +- Real-time energy and power profiling +- ARM Cortex M0+ with 64 kB Flash and 8 kB RAM +- 128 X 128 pixel Memory LCD +- 2 user buttons, 2 user LEDs and 2 touch buttons +- 20 pin expansion header +- Silicon Labs Si7021 Relative Humidity/Temperature sensor +- USB device interface +- Integrated SEGGER J-Link USB debugger/emulator with debug out functionality + + +See these documents for more information + +- `EFM32HG Website`_ +- `EFM32HG Datasheet`_ +- `EFM32HG Reference Manual`_ +- `EFM32HG-SLSTK3400A Website`_ +- `EFM32HG-SLSTK3400A User Guide`_ +- `EFM32HG-SLSTK3400A Schematics`_ + +Supported Features +================== + +The efm32hg_slstk3400 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32HG SoC has six GPIO controllers (PORTA to PORTF), but only three are +currently enabled (PORTB, PORTE and PORTF) for the EFM32HG-SLSTK3400A board. + +In the following table, the column Name contains Pin names. For example, PF4 +means Pin number 4 on PORTF, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PC9 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PC10 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PF2 | USART0_TX | USART Console EFM_BC_TX U0_TX #4 | ++-------+-------------+-------------------------------------+ +| PA9 | USART0_RX | USART Console EFM_BC_RX U0_RX #4 | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFM32HG SoC is configured to use the 24 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32HG SoC has two USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART1 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32HG-SLSTK3400 includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFM32-SLSTK3400A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32hg_slstk3400a + :goals: build + +Connect the EFM32HG-SLSTK3400A to your host computer using the USB port and +you should see a USB connection that exposes a mass storage device (STK3400) +and a USB Serial Port. Copy the generated ``zephyr.bin`` in the STK3400 drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you will see this message written to the serial port: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32HG-SLSTK3400A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-happy-gecko-starter-kit + +.. _EFM32HG-SLSTK3400A User Guide: + https://www.silabs.com/documents/public/user-guides/ug255-stk3400-user-guide.pdf + +.. _EFM32HG-SLSTK3400A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2012A-B01-schematic.pdf + +.. _EFM32HG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-happy-gecko + +.. _EFM32HG Datasheet: + https://www.silabs.com/documents/public/data-sheets/EFM32HG322.pdf + +.. _EFM32HG Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/EFM32HG-RM.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.dts b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.dts similarity index 100% rename from boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.dts rename to boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.dts diff --git a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml similarity index 100% rename from boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml rename to boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a.yaml diff --git a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig similarity index 82% rename from boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig rename to boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig index 834cb328d0cb30..957fedcc584dad 100644 --- a/boards/arm/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig +++ b/boards/silabs/efm32hg_slstk3400a/efm32hg_slstk3400a_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32HG=y -CONFIG_BOARD_EFM32HG_SLSTK3400A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig b/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig new file mode 100644 index 00000000000000..9853bf434cca96 --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32PG STK3401A board + +# Copyright (c) 2020, Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32PG_STK3401A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32PG_STK3401A diff --git a/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a b/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a new file mode 100644 index 00000000000000..42de02a430abaa --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/Kconfig.efm32pg_stk3401a @@ -0,0 +1,7 @@ +# EFM32PG STK3401A board + +# Copyright (c) 2020, Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32PG_STK3401A + select SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/boards/arm/efm32pg_stk3401a/board.cmake b/boards/silabs/efm32pg_stk3401a/board.cmake similarity index 100% rename from boards/arm/efm32pg_stk3401a/board.cmake rename to boards/silabs/efm32pg_stk3401a/board.cmake diff --git a/boards/silabs/efm32pg_stk3401a/board.yml b/boards/silabs/efm32pg_stk3401a/board.yml new file mode 100644 index 00000000000000..636c7e8c5621e7 --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32pg_stk3401a + vendor: silabs + socs: + - name: efm32pg1b200f256gm48 diff --git a/boards/arm/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg b/boards/silabs/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg similarity index 100% rename from boards/arm/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg rename to boards/silabs/efm32pg_stk3401a/doc/efm32pg_stk3401a.jpg diff --git a/boards/silabs/efm32pg_stk3401a/doc/index.rst b/boards/silabs/efm32pg_stk3401a/doc/index.rst new file mode 100644 index 00000000000000..a38930275a2651 --- /dev/null +++ b/boards/silabs/efm32pg_stk3401a/doc/index.rst @@ -0,0 +1,188 @@ +.. _efm32pg_stk3401a: + +EFM32 Pearl Gecko Starter Kit +############################# + +Overview +******** + +The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3401A contains an MCU from the +EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: efm32pg_stk3401a.jpg + :align: center + :alt: EFM32PG-SLSTK3401A + + EFM32PG-SLSTK3401A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel Memory-LCD +- 2 user buttons, 2 LEDs and 2 capacitive buttons +- Humidity and temperature sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32PG SoC and EFM32PG-STK3401A board: + +- `EFM32PG Website`_ +- `EFM32PG1 Datasheet`_ +- `EFM32PG1 Reference Manual`_ +- `EFM32PG-STK3401A Website`_ +- `EFM32PG-STK3401A User Guide`_ + +Supported Features +================== + +The efm32pg_stk3401a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32PG1 SoC has five GPIO controllers (PORTA to PORTD and PORTF) and +all are enabled for the EFM32PG-STK3401A board. + +In the following table, the column **Name** contains pin names. For example, PF4 +means pin number 4 on PORTF, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | ++-------+-------------+-------------------------------------+ +| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | ++-------+-------------+-------------------------------------+ +| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | ++-------+-------------+-------------------------------------+ +| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32PG SoC is configured to use the 40 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG SoC has two USARTs and one Low Energy UART (LEUART). + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32PG-STK3401A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to EFM32PG-STK3401A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32pg_stk3401a + :goals: build + +Connect the EFM32PG-STK3401A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3401A). +Copy the generated zephyr.bin to the STK3401A drive. + +Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the +expansion header. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32PG-STK3401A Website: + https://www.silabs.com/development-tools/mcu/32-bit/efm32pg1-starter-kit + +.. _EFM32PG-STK3401A User Guide: + https://www.silabs.com/documents/public/user-guides/ug154-stk3401-user-guide.pdf + +.. _EFM32PG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko + +.. _EFM32PG1 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg1-datasheet.pdf + +.. _EFM32PG1 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg1-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a-pinctrl.dtsi diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.dts b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.dts similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.dts rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.dts diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.yaml b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.yaml similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a.yaml rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a.yaml diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_common.dtsi diff --git a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig similarity index 75% rename from boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig rename to boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig index 541e45f901f339..f220c60c9a879e 100644 --- a/boards/arm/efm32pg_stk3401a/efm32pg_stk3401a_defconfig +++ b/boards/silabs/efm32pg_stk3401a/efm32pg_stk3401a_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32PG1B=y -CONFIG_BOARD_EFM32PG_STK3401A=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig b/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig new file mode 100644 index 00000000000000..3d9a498ecd5984 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/Kconfig.defconfig @@ -0,0 +1,15 @@ +# EFM32PG STK3402A board + +# Copyright (c) 2018, Christian Taedcke +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32PG_STK3402A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32PG_STK3402A diff --git a/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a b/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a new file mode 100644 index 00000000000000..7f4bea414753e4 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/Kconfig.efm32pg_stk3402a @@ -0,0 +1,9 @@ +# EFM32PG STK3402A board + +# Copyright (c) 2018, Christian Taedcke +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32PG_STK3402A + select SOC_PART_NUMBER_EFM32PG12B500F1024GL125 if BOARD_EFM32PG_STK3402A_EFM32PG12B500F1024GL125 + select SOC_PART_NUMBER_EFM32JG12B500F1024GL125 if BOARD_EFM32PG_STK3402A_EFM32JG12B500F1024GL125 diff --git a/boards/arm/efm32pg_stk3402a/board.cmake b/boards/silabs/efm32pg_stk3402a/board.cmake similarity index 100% rename from boards/arm/efm32pg_stk3402a/board.cmake rename to boards/silabs/efm32pg_stk3402a/board.cmake diff --git a/boards/silabs/efm32pg_stk3402a/board.yml b/boards/silabs/efm32pg_stk3402a/board.yml new file mode 100644 index 00000000000000..068aa663798de3 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/board.yml @@ -0,0 +1,6 @@ +board: + name: efm32pg_stk3402a + vendor: silabs + socs: + - name: efm32pg12b500f1024gl125 + - name: efm32jg12b500f1024gl125 diff --git a/boards/arm/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg b/boards/silabs/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg similarity index 100% rename from boards/arm/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg rename to boards/silabs/efm32pg_stk3402a/doc/efm32pg_stk3402a.jpg diff --git a/boards/silabs/efm32pg_stk3402a/doc/index.rst b/boards/silabs/efm32pg_stk3402a/doc/index.rst new file mode 100644 index 00000000000000..8014f310b0c2a1 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/doc/index.rst @@ -0,0 +1,212 @@ +.. _efm32pg_stk3402a: + +EFM32 Pearl Gecko Starter Kit +############################# + +Overview +******** + +The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A contains an MCU from the +EFM32PG family built on an ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: efm32pg_stk3402a.jpg + :align: center + :alt: EFM32PG-SLSTK3402A + + EFM32PG-SLSTK3402A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel Memory-LCD +- 2 user buttons, 2 LEDs and a touch slider +- Humidity, temperature, and inductive-capacitive metal sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32PG SoC and EFM32PG-STK3402A board: + +- `EFM32PG Website`_ +- `EFM32PG12 Datasheet`_ +- `EFM32PG12 Reference Manual`_ +- `EFM32PG-STK3402A Website`_ +- `EFM32PG-STK3402A User Guide`_ +- `EFM32PG-STK3402A Schematics`_ + +Supported Features +================== + +The efm32pg_stk3402a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig` + +The default configuration when building for this EFM32JG12B SoC can be found in +:zephyr_file:`boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig` + +Other hardware features are currently not supported by the port. + +EFM32 Jade Gecko SoC +-------------------- + +The EFM32 Pearl Gecko Starter Kit EFM32PG-STK3402A can also be used to evaluate +the EFM32 Jade Gecko SoC (EFM32JG12B). The only difference between the Pearl +Gecko and the Jade Gecko is their core. The Pearl Gecko contains an ARM® +Cortex®-M4F core, and the Jade Gecko an ARM® Cortex®-M3 core. Other features +such as memory and peripherals are the same. + +Code that is built for the Jade Gecko also runs on an equivalent Pearl Gecko. + +To build firmware for the Jade Gecko and run it on the EFM32 Pearl Gecko Starter +Kit, use the board ``efm32pg_stk3402a/efm32pg12b500f1024gl125`` instead of ``efm32pg_stk3402a/efm32jg12b500f1024gl125``. + +Connections and IOs +=================== + +The EFM32PG12 SoC has twelve GPIO controllers (PORTA to PORTL), but only four +are currently enabled (PORTA, PORTB, PORTD and PORTF) for the EFM32PG-STK3402A +board. + +In the following table, the column **Name** contains pin names. For example, PE2 +means pin number 2 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PF4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PF5 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PF6 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PA5 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++-------+-------------+-------------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++-------+-------------+-------------------------------------+ +| PD10 | UART_TX | EXP12_UART_TX LEU0_TX #18 | ++-------+-------------+-------------------------------------+ +| PD11 | UART_RX | EXP14_UART_RX LEU0_RX #18 | ++-------+-------------+-------------------------------------+ +| PC10 | I2C_SDA | ENV_I2C_SDA I2C0_SDA #15 | ++-------+-------------+-------------------------------------+ +| PC11 | I2C_SCL | ENV_I2C_SCL I2C0_SCL #15 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32PG SoC is configured to use the 40 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32PG SoC has four USARTs and one Low Energy UART (LEUART). + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32PG-STK3402A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to EFM32PG-STK3402A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32pg_stk3402a/efm32pg12b500f1024gl125 + :goals: build + +Connect the EFM32PG-STK3402A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3402A). +Copy the generated zephyr.bin to the STK3402A drive. + +Use a USB-to-UART converter such as an FT232/CP2102 to connect to the UART on the +expansion header. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32PG-STK3402A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-pearl-gecko-pg12-starter-kit + +.. _EFM32PG-STK3402A User Guide: + https://www.silabs.com/documents/public/user-guides/ug257-stk3402-usersguide.pdf + +.. _EFM32PG-STK3402A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2501A-A01-schematic.pdf + +.. _EFM32PG Website: + https://www.silabs.com/products/mcu/32-bit/efm32-pearl-gecko + +.. _EFM32PG12 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32pg12-datasheet.pdf + +.. _EFM32PG12 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32pg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a-pinctrl.dtsi diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_common.dtsi diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.dts b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.dts similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a_jg.dts rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.dts diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml new file mode 100644 index 00000000000000..7373e65edb28db --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125.yaml @@ -0,0 +1,19 @@ +identifier: efm32pg_stk3402a/efm32jg12b500f1024gl125 +name: EFM32PG-STK3402A-JG +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - nvs +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig new file mode 100644 index 00000000000000..f220c60c9a879e --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32jg12b500f1024gl125_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 +CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.dts b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.dts similarity index 100% rename from boards/arm/efm32pg_stk3402a/efm32pg_stk3402a.dts rename to boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.dts diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml new file mode 100644 index 00000000000000..153ebae67ef919 --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125.yaml @@ -0,0 +1,20 @@ +identifier: efm32pg_stk3402a/efm32pg12b500f1024gl125 +name: EFM32PG-STK3402A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - i2c + - gpio + - nvs + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig new file mode 100644 index 00000000000000..f220c60c9a879e --- /dev/null +++ b/boards/silabs/efm32pg_stk3402a/efm32pg_stk3402a_efm32pg12b500f1024gl125_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=40000000 +CONFIG_CMU_HFCLK_HFXO=y diff --git a/boards/silabs/efm32wg_stk3800/Kconfig.defconfig b/boards/silabs/efm32wg_stk3800/Kconfig.defconfig new file mode 100644 index 00000000000000..12fb1b4f23684a --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFM32WG STK3800 board + +# Copyright (c) 2017, Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32WG_STK3800 + +config CMU_HFXO_FREQ + default 48000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFM32WG_STK3800 diff --git a/boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 b/boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 new file mode 100644 index 00000000000000..025ac1849f06e7 --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/Kconfig.efm32wg_stk3800 @@ -0,0 +1,7 @@ +# EFM32WG STK3800 board + +# Copyright (c) 2017, Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32WG_STK3800 + select SOC_PART_NUMBER_EFM32WG990F256 diff --git a/boards/arm/efm32wg_stk3800/board.cmake b/boards/silabs/efm32wg_stk3800/board.cmake similarity index 100% rename from boards/arm/efm32wg_stk3800/board.cmake rename to boards/silabs/efm32wg_stk3800/board.cmake diff --git a/boards/silabs/efm32wg_stk3800/board.yml b/boards/silabs/efm32wg_stk3800/board.yml new file mode 100644 index 00000000000000..034c623141b3e6 --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/board.yml @@ -0,0 +1,5 @@ +board: + name: efm32wg_stk3800 + vendor: silabs + socs: + - name: efm32wg990f256 diff --git a/boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.jpg b/boards/silabs/efm32wg_stk3800/doc/efm32wg_stk3800.jpg similarity index 100% rename from boards/arm/efm32wg_stk3800/doc/efm32wg_stk3800.jpg rename to boards/silabs/efm32wg_stk3800/doc/efm32wg_stk3800.jpg diff --git a/boards/silabs/efm32wg_stk3800/doc/index.rst b/boards/silabs/efm32wg_stk3800/doc/index.rst new file mode 100644 index 00000000000000..30810f0d71ec5d --- /dev/null +++ b/boards/silabs/efm32wg_stk3800/doc/index.rst @@ -0,0 +1,177 @@ +.. _efm32wg_stk3800: + +EFM32WG-STK3800 +############### + +Overview +******** + +The EFM32 Wonder Gecko Starter Kit EFM32WG-STK3800 contains a MCU from the +EFM32WG family built on ARM® Cortex®-M4F processor with excellent low +power capabilities. + +.. figure:: efm32wg_stk3800.jpg + :align: center + :alt: EFM32WG-STK3800 + + EFM32WG-STK3800 (image courtesy of Silicon Labs) + + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- 32MByte parallel NAND Flash +- 160 segment Energy Micro LCD +- 2 user buttons, 2 LEDs and a touch slider +- Ambient Light Sensor and Inductive-capacitive metal sensor +- On-board Segger J-Link USB debugger + +For more information about the EFM32WG SoC and EFM32WG-STK3800 board: + +- `EFM32WG Website`_ +- `EFM32WG Datasheet`_ +- `EFM32WG Reference Manual`_ +- `EFM32WG-STK3800 Website`_ +- `EFM32WG-STK3800 User Guide`_ +- `EFM32WG-STK3800 Schematics`_ + +Supported Features +================== + +The efm32wg_stk3800 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32WG SoC has six gpio controllers (PORTA to PORTF), but only three are +currently enabled (PORTB, PORTE and PORTF) for the EFM32WG-STK3800 board. + +In the following table, the column Name contains Pin names. For example, PE2 +means Pin number 2 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PE2 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PE3 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB9 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PB10 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PF7 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PE0 | UART0_TX | UART Console EFM_BC_TX U0_TX #1 | ++-------+-------------+-------------------------------------+ +| PE1 | UART0_RX | UART Console EFM_BC_RX U0_RX #1 | ++-------+-------------+-------------------------------------+ + +System Clock +============ + +The EFM32WG SoC is configured to use the 48 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32WG SoC has three USARTs, two UARTs and two Low Energy UARTs (LEUART). +UART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32WG-STK3800 includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFM32-STK3800 +---------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32wg_stk3800 + :goals: build + +Connect the EFM32WG-STK3800 to your host computer using the USB port and you +should see a USB connection which exposes a Mass Storage (STK3800) and a +USB Serial Port. Copy the generated zephyr.bin in the STK3800 drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! arm + + +.. _EFM32WG-STK3800 Website: + http://www.silabs.com/products/development-tools/mcu/32-bit/efm32-wonder-gecko-starter-kit + +.. _EFM32WG-STK3800 User Guide: + http://www.silabs.com/documents/public/user-guides/efm32wg-stk3800-ug.pdf + +.. _EFM32WG-STK3800 Schematics: + http://www.silabs.com/documents/public/schematic-files/BRD2400A_A00.pdf + +.. _EFM32WG Website: + http://www.silabs.com/products/mcu/32-bit/efm32-wonder-gecko + +.. _EFM32WG Datasheet: + http://www.silabs.com/documents/public/data-sheets/EFM32WG990.pdf + +.. _EFM32WG Reference Manual: + http://www.silabs.com/documents/public/reference-manuals/EFM32WG-RM.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800.dts similarity index 100% rename from boards/arm/efm32wg_stk3800/efm32wg_stk3800.dts rename to boards/silabs/efm32wg_stk3800/efm32wg_stk3800.dts diff --git a/boards/arm/efm32wg_stk3800/efm32wg_stk3800.yaml b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800.yaml similarity index 100% rename from boards/arm/efm32wg_stk3800/efm32wg_stk3800.yaml rename to boards/silabs/efm32wg_stk3800/efm32wg_stk3800.yaml diff --git a/boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig similarity index 76% rename from boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig rename to boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig index cda53788ee69ff..5563b773d7dbd9 100644 --- a/boards/arm/efm32wg_stk3800/efm32wg_stk3800_defconfig +++ b/boards/silabs/efm32wg_stk3800/efm32wg_stk3800_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFM32WG=y -CONFIG_BOARD_EFM32WG_STK3800=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/silabs/efr32_radio/Kconfig.defconfig b/boards/silabs/efr32_radio/Kconfig.defconfig new file mode 100644 index 00000000000000..ce20c2ef360b0d --- /dev/null +++ b/boards/silabs/efr32_radio/Kconfig.defconfig @@ -0,0 +1,51 @@ +# EFR32 radio board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFR32_RADIO + +config CMU_HFXO_FREQ + default 39000000 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x08000000 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 + default 0x0 + +config LOG_BACKEND_SWO_FREQ_HZ + default 875000 + depends on LOG_BACKEND_SWO + +if SOC_GECKO_USE_RAIL + +config FPU + default n if SOC_FAMILY_SILABS_S1 + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config MINIMAL_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +choice BT_HCI_BUS_TYPE + default BT_SILABS_HCI +endchoice + +endif # BT + +endif # BOARD_EFR32_RADIO diff --git a/boards/silabs/efr32_radio/Kconfig.efr32_radio b/boards/silabs/efr32_radio/Kconfig.efr32_radio new file mode 100644 index 00000000000000..1ebc6a94455fa3 --- /dev/null +++ b/boards/silabs/efr32_radio/Kconfig.efr32_radio @@ -0,0 +1,15 @@ +# EFR32BG13 BRD4104A / EFR32MG21 BRD4180A / +# EFR32FG1P BRD4250B / EFR32FG13P BRD4255A board + +# Copyright (c) 2020 Piotr Mienkowski +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32_RADIO + select SOC_PART_NUMBER_EFR32BG13P632F512GM48 if BOARD_EFR32_RADIO_EFR32BG13P632F512GM48 + select SOC_PART_NUMBER_EFR32MG12P433F1024GM68 if BOARD_EFR32_RADIO_EFR32MG12P433F1024GM68 + select SOC_PART_NUMBER_EFR32MG12P432F1024GL125 if BOARD_EFR32_RADIO_EFR32MG12P432F1024GL125 + select SOC_PART_NUMBER_EFR32FG1P133F256GM48 if BOARD_EFR32_RADIO_EFR32FG1P133F256GM48 + select SOC_PART_NUMBER_EFR32MG21A020F1024IM32 if BOARD_EFR32_RADIO_EFR32MG21A020F1024IM32 + select SOC_PART_NUMBER_EFR32MG24B220F1536IM48 if BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48 + select SOC_PART_NUMBER_EFR32FG13P233F512GM48 if BOARD_EFR32_RADIO_EFR32FG13P233F512GM48 diff --git a/boards/silabs/efr32_radio/board.cmake b/boards/silabs/efr32_radio/board.cmake new file mode 100644 index 00000000000000..142165be8c7949 --- /dev/null +++ b/boards/silabs/efr32_radio/board.cmake @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd) + +if(CONFIG_BOARD_EFR32_RADIO_EFR32BG13P632F512GM48) + board_runner_args(jlink "--device=EFR32BG13PxxxF512") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32FG1P133F256GM48) + board_runner_args(jlink "--device=EFR32FG1PxxxF256") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG12P433F1024GM68) + board_runner_args(jlink "--device=EFR32MG12PxxxF1024") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG12P432F1024GL125) + board_runner_args(jlink "--device=EFR32MG12PxxxF1024") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG21A020F1024IM32) + board_runner_args(jlink "--device=EFR32MG21AxxxF1024") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32MG24B220F1536IM48) + board_runner_args(jlink "--device=EFR32MG24BxxxF1536") +elseif(CONFIG_BOARD_EFR32_RADIO_EFR32FG13P233F512GM48) + board_runner_args(jlink "--device=EFR32FG13PxxxF512") +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/silabs/efr32_radio/board.yml b/boards/silabs/efr32_radio/board.yml new file mode 100644 index 00000000000000..5e68cef3826b40 --- /dev/null +++ b/boards/silabs/efr32_radio/board.yml @@ -0,0 +1,10 @@ +boards: + - name: efr32_radio + socs: + - name: efr32bg13p632f512gm48 + - name: efr32mg12p433f1024gm68 + - name: efr32mg12p432f1024gl125 + - name: efr32fg1p133f256gm48 + - name: efr32mg21a020f1024im32 + - name: efr32mg24b220f1536im48 + - name: efr32fg13p233f512gm48 diff --git a/boards/arm/efr32_radio/doc/brd4104a.rst b/boards/silabs/efr32_radio/doc/brd4104a.rst similarity index 93% rename from boards/arm/efr32_radio/doc/brd4104a.rst rename to boards/silabs/efr32_radio/doc/brd4104a.rst index e52f54d22c28b8..7fa1336345c550 100644 --- a/boards/arm/efr32_radio/doc/brd4104a.rst +++ b/boards/silabs/efr32_radio/doc/brd4104a.rst @@ -49,11 +49,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4104a board. +``efr32_radio/efr32bg13p632f512gm48`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4104a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig` System Clock ============ @@ -84,7 +83,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4104a + :board: efr32_radio/efr32bg13p632f512gm48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -98,7 +97,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4104a + Hello World! efr32_radio .. _EFR32BG13 Website: diff --git a/boards/arm/efr32_radio/doc/brd4161a.rst b/boards/silabs/efr32_radio/doc/brd4161a.rst similarity index 91% rename from boards/arm/efr32_radio/doc/brd4161a.rst rename to boards/silabs/efr32_radio/doc/brd4161a.rst index f51d54b5f3dbce..992d5f7a4acd36 100644 --- a/boards/arm/efr32_radio/doc/brd4161a.rst +++ b/boards/silabs/efr32_radio/doc/brd4161a.rst @@ -44,11 +44,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4161a board. +``efr32_radio/efr32mg12p432f1024gl125`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4161a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig` System Clock ============ @@ -79,7 +78,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4161a + :board: efr32_radio/efr32mg12p432f1024gl125 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -93,7 +92,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4161a + Hello World! efr32_radio .. _EFR32MG12 Website: diff --git a/boards/arm/efr32_radio/doc/brd4170a.rst b/boards/silabs/efr32_radio/doc/brd4170a.rst similarity index 91% rename from boards/arm/efr32_radio/doc/brd4170a.rst rename to boards/silabs/efr32_radio/doc/brd4170a.rst index 9924c2b1d1a848..a1751424f37c8c 100644 --- a/boards/arm/efr32_radio/doc/brd4170a.rst +++ b/boards/silabs/efr32_radio/doc/brd4170a.rst @@ -44,11 +44,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4170a board. +``efr32_radio/efr32mg12p433f1024gm68`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4170a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig` System Clock ============ @@ -79,7 +78,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4170a + :board: efr32_radio/efr32mg12p433f1024gm68 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -93,7 +92,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4170a + Hello World! efr32_radio .. _EFR32MG12 Website: diff --git a/boards/arm/efr32_radio/doc/brd4180a.rst b/boards/silabs/efr32_radio/doc/brd4180a.rst similarity index 96% rename from boards/arm/efr32_radio/doc/brd4180a.rst rename to boards/silabs/efr32_radio/doc/brd4180a.rst index 870b324a279956..4998122bbcdf5f 100644 --- a/boards/arm/efr32_radio/doc/brd4180a.rst +++ b/boards/silabs/efr32_radio/doc/brd4180a.rst @@ -95,9 +95,8 @@ means Pin number 2 on PORTA, as used in the board's datasheets and manuals. | PA6 | USART1_RX | UART Console EFM_BC_RX US1_RX | +-------+-------------+-------------------------------------+ -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4180a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig` System Clock ============ @@ -128,7 +127,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4180a + :board: efr32_radio/efr32mg21a020f1024im32 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -142,7 +141,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4180a + Hello World! efr32_radio .. _EFR32-SLWSTK6006A Website: diff --git a/boards/arm/efr32_radio/doc/brd4187c.rst b/boards/silabs/efr32_radio/doc/brd4187c.rst similarity index 96% rename from boards/arm/efr32_radio/doc/brd4187c.rst rename to boards/silabs/efr32_radio/doc/brd4187c.rst index 03ff14ad45cf21..63f106bd072f7a 100644 --- a/boards/arm/efr32_radio/doc/brd4187c.rst +++ b/boards/silabs/efr32_radio/doc/brd4187c.rst @@ -96,9 +96,8 @@ means Pin number 2 on PORTA, as used in the board's datasheets and manuals. | PA9 | USART0_RX | UART Console VCOM_RX US0_RX | +-------+-------------+-------------------------------------+ -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4187c_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig`` System Clock ============ @@ -129,7 +128,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4187c + :board: efr32_radio/efr32mg24b220f1536im48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -143,7 +142,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4187c + Hello World! efr32_radio .. _xG24-PK6010A Website: diff --git a/boards/arm/efr32_radio/doc/brd4250b.rst b/boards/silabs/efr32_radio/doc/brd4250b.rst similarity index 93% rename from boards/arm/efr32_radio/doc/brd4250b.rst rename to boards/silabs/efr32_radio/doc/brd4250b.rst index effac2a407eb9f..6ccb4ca22caa0f 100644 --- a/boards/arm/efr32_radio/doc/brd4250b.rst +++ b/boards/silabs/efr32_radio/doc/brd4250b.rst @@ -48,11 +48,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4250b board. +``efr32_radio/efr32fg1p133f256gm48`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4250b_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig` System Clock ============ @@ -83,7 +82,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4250b + :board: efr32_radio/efr32fg1p133f256gm48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -97,7 +96,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4250b + Hello World! efr32_radio .. _EFR32FG1 Website: diff --git a/boards/arm/efr32_radio/doc/brd4255a.rst b/boards/silabs/efr32_radio/doc/brd4255a.rst similarity index 92% rename from boards/arm/efr32_radio/doc/brd4255a.rst rename to boards/silabs/efr32_radio/doc/brd4255a.rst index ab81e513c90018..60138f08610c0c 100644 --- a/boards/arm/efr32_radio/doc/brd4255a.rst +++ b/boards/silabs/efr32_radio/doc/brd4255a.rst @@ -44,11 +44,10 @@ Supported Features Please refer to :ref:`EFR32 Radio Board Supported Features ` for details of the configuration and common features supported by the -efr32_radio_brd4255a board. +``efr32_radio/efr32fg13p233f512gm48`` board. -The default configuration can be found in the defconfig file: - - ``boards/arm/efr32_radio/efr32_radio_brd4255a_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig` System Clock ============ @@ -79,7 +78,7 @@ Here is an example for the :ref:`hello_world` application. .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: efr32_radio_brd4255a + :board: efr32_radio/efr32fg13p233f512gm48 :goals: flash Open a serial terminal (minicom, putty, etc.) with the following settings: @@ -93,7 +92,7 @@ Reset the board and you should see the following message in the terminal: .. code-block:: console - Hello World! efr32_radio_brd4255a + Hello World! efr32_radio .. _EFR32FG13 Website: diff --git a/boards/arm/efr32_radio/doc/efr32_slwstk6020b.jpg b/boards/silabs/efr32_radio/doc/efr32_slwstk6020b.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32_slwstk6020b.jpg rename to boards/silabs/efr32_radio/doc/efr32_slwstk6020b.jpg diff --git a/boards/arm/efr32_radio/doc/efr32bg13-slwrb4104a.jpg b/boards/silabs/efr32_radio/doc/efr32bg13-slwrb4104a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32bg13-slwrb4104a.jpg rename to boards/silabs/efr32_radio/doc/efr32bg13-slwrb4104a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32fg1-slwrb4250b.jpg b/boards/silabs/efr32_radio/doc/efr32fg1-slwrb4250b.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32fg1-slwrb4250b.jpg rename to boards/silabs/efr32_radio/doc/efr32fg1-slwrb4250b.jpg diff --git a/boards/arm/efr32_radio/doc/efr32fg13-slwrb4255a.jpg b/boards/silabs/efr32_radio/doc/efr32fg13-slwrb4255a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32fg13-slwrb4255a.jpg rename to boards/silabs/efr32_radio/doc/efr32fg13-slwrb4255a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg b/boards/silabs/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg rename to boards/silabs/efr32_radio/doc/efr32mg12-slwrb4161a.jpeg diff --git a/boards/arm/efr32_radio/doc/efr32mg12-slwrb4170a.jpg b/boards/silabs/efr32_radio/doc/efr32mg12-slwrb4170a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg12-slwrb4170a.jpg rename to boards/silabs/efr32_radio/doc/efr32mg12-slwrb4170a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32mg21-slwrb4180a.jpg b/boards/silabs/efr32_radio/doc/efr32mg21-slwrb4180a.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg21-slwrb4180a.jpg rename to boards/silabs/efr32_radio/doc/efr32mg21-slwrb4180a.jpg diff --git a/boards/arm/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg b/boards/silabs/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg similarity index 100% rename from boards/arm/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg rename to boards/silabs/efr32_radio/doc/efr32mg24-xg24-rb4187c.jpg diff --git a/boards/arm/efr32_radio/doc/index.rst b/boards/silabs/efr32_radio/doc/index.rst similarity index 100% rename from boards/arm/efr32_radio/doc/index.rst rename to boards/silabs/efr32_radio/doc/index.rst diff --git a/boards/arm/efr32_radio/efr32_radio-pinctrl.dtsi b/boards/silabs/efr32_radio/efr32_radio-pinctrl.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio-pinctrl.dtsi rename to boards/silabs/efr32_radio/efr32_radio-pinctrl.dtsi diff --git a/boards/arm/efr32_radio/efr32_radio.dtsi b/boards/silabs/efr32_radio/efr32_radio.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio.dtsi rename to boards/silabs/efr32_radio/efr32_radio.dtsi diff --git a/boards/arm/efr32_radio/efr32_radio_brd4104a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4104a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml new file mode 100644 index 00000000000000..8edaadbadf72ba --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48.yaml @@ -0,0 +1,22 @@ +identifier: efr32_radio/efr32bg13p632f512gm48 +name: BRD4104A +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig new file mode 100644 index 00000000000000..17eefb534ca224 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32bg13p632f512gm48_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4255a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4255a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml new file mode 100644 index 00000000000000..af096e1af9e281 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48.yaml @@ -0,0 +1,22 @@ +identifier: efr32_radio/efr32fg13p233f512gm48 +name: BRD4255A +type: mcu +arch: arm +ram: 64 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig new file mode 100644 index 00000000000000..17eefb534ca224 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg13p233f512gm48_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4250b.dts b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4250b.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml new file mode 100644 index 00000000000000..356d959514cafe --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48.yaml @@ -0,0 +1,22 @@ +identifier: efr32_radio/efr32fg1p133f256gm48 +name: BRD4250B +type: mcu +arch: arm +ram: 32 +flash: 256 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig new file mode 100644 index 00000000000000..17eefb534ca224 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32fg1p133f256gm48_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4161a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4161a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml new file mode 100644 index 00000000000000..8092040c672959 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg12p432f1024gl125 +name: BRD4161A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig new file mode 100644 index 00000000000000..17eefb534ca224 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p432f1024gl125_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4170a.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4170a.dts rename to boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.dts diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml new file mode 100644 index 00000000000000..ac0779d0d01768 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg12p433f1024gm68 +name: BRD4170A +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - nvs + - spi + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig new file mode 100644 index 00000000000000..17eefb534ca224 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg12p433f1024gm68_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4180a-pinctrl.dtsi b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4180a-pinctrl.dtsi rename to boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts new file mode 100644 index 00000000000000..379fd031e22dcf --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.dts @@ -0,0 +1,147 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "efr32_radio_efr32mg21a020f1024im32-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4180A (Mighty Gecko Radio Board)"; + compatible = "silabs,efr32mg21_brd4180a", "silabs,efr32mg21"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob 0 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiob 1 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpiod 2 GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpiod 3 GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <38400000>; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <4 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&wdog0 { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x0000c000>; + read-only; + }; + + /* Reserve 464 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x00074000>; + }; + + /* Reserve 464 kB for the application in slot 1 */ + slot1_partition: partition@80000 { + label = "image-1"; + reg = <0x00080000 0x00074000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@f4000 { + label = "image-scratch"; + reg = <0x000f4000 0x00008000>; + }; + + /* Set 16Kb of storage at the end of the 1024Kb of flash */ + storage_partition: partition@fc000 { + label = "storage"; + reg = <0x000fc000 0x00004000>; + }; + + }; +}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml new file mode 100644 index 00000000000000..c6103f5336b572 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg21a020f1024im32 +name: BRD4180A +type: mcu +arch: arm +ram: 96 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - nvs + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig new file mode 100644 index 00000000000000..053f12a36f4f21 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg21a020f1024im32_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=38400000 +CONFIG_CMU_HFCLK_HFXO=y +CONFIG_PINCTRL=y diff --git a/boards/arm/efr32_radio/efr32_radio_brd4187c-pinctrl.dtsi b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi similarity index 100% rename from boards/arm/efr32_radio/efr32_radio_brd4187c-pinctrl.dtsi rename to boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts new file mode 100644 index 00000000000000..0fb0b4becc3a0f --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.dts @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2023 Fr. Sauter AG + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "efr32_radio_efr32mg24b220f1536im48-pinctrl.dtsi" + +/ { + model = "Silicon Labs BRD4187C (Mighty Gecko Radio Board)"; + compatible = "silabs,efr32mg24_brd4187c", "silabs,efr32mg24"; + + chosen { + zephyr,console = &usart0; + zephyr,shell-uart = &usart0; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + watchdog0 = &wdog0; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpiob GECKO_PIN(2) GPIO_ACTIVE_HIGH>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpiob GECKO_PIN(4) GPIO_ACTIVE_HIGH>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpiob GECKO_PIN(1) GPIO_ACTIVE_LOW>; + label = "User Push Button 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpiob GECKO_PIN(3) GPIO_ACTIVE_LOW>; + label = "User Push Button 1"; + zephyr,code = ; + }; + }; + +}; + +&cpu0 { + clock-frequency = <39000000>; +}; + +&pstate_em3 { + status = "disabled"; +}; + +&usart0 { + current-speed = <115200>; + pinctrl-0 = <&usart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +&gpioa { + status = "okay"; +}; + +&gpiob { + status = "okay"; + + board-controller-enable { + gpio-hog; + gpios = <0 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&gpioc { + status = "okay"; +}; + +&gpiod { + status = "okay"; +}; + +&wdog0 { + status = "okay"; +}; + +&burtc0 { + status = "okay"; +}; + +&stimer0 { + status = "okay"; +}; + +&se { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 48 kB for the bootloader */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 DT_SIZE_K(48)>; + read-only; + }; + + /* Reserve 720 kB for the application in slot 0 */ + slot0_partition: partition@c000 { + label = "image-0"; + reg = <0x0000c000 0x000B4000>; + }; + + /* Reserve 720 kB for the application in slot 1 */ + slot1_partition: partition@C0000 { + label = "image-1"; + reg = <0x000C0000 0x000B4000>; + }; + + /* Reserve 32 kB for the scratch partition */ + scratch_partition: partition@174000 { + label = "image-scratch"; + reg = <0x00174000 DT_SIZE_K(32)>; + }; + + /* Set 16 kB of storage at the end of the 1536 kB of flash */ + storage_partition: partition@17c000 { + label = "storage"; + reg = <0x0017c000 DT_SIZE_K(16)>; + }; + }; +}; diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml new file mode 100644 index 00000000000000..278f40a4866f67 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48.yaml @@ -0,0 +1,21 @@ +identifier: efr32_radio/efr32mg24b220f1536im48 +name: BRD4187C +type: mcu +arch: arm +ram: 256 +flash: 1536 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - uart + - watchdog +testing: + ignore_tags: + - net + - bluetooth + - pm + - hwinfo +vendor: silabs diff --git a/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig new file mode 100644 index 00000000000000..7e41ebc6a13c01 --- /dev/null +++ b/boards/silabs/efr32_radio/efr32_radio_efr32mg24b220f1536im48_defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM_MPU=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=78000000 +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y +CONFIG_PINCTRL=y + +# Use BURTC as system clock source +CONFIG_GECKO_BURTC_TIMER=y +CONFIG_CMU_BURTCCLK_LFXO=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=1024 diff --git a/boards/arm/efr32_radio/pre_dt_board.cmake b/boards/silabs/efr32_radio/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32_radio/pre_dt_board.cmake rename to boards/silabs/efr32_radio/pre_dt_board.cmake diff --git a/boards/arm/efr32_radio/support/openocd.cfg b/boards/silabs/efr32_radio/support/openocd.cfg similarity index 100% rename from boards/arm/efr32_radio/support/openocd.cfg rename to boards/silabs/efr32_radio/support/openocd.cfg diff --git a/boards/arm/efr32_thunderboard/CMakeLists.txt b/boards/silabs/efr32_thunderboard/CMakeLists.txt similarity index 100% rename from boards/arm/efr32_thunderboard/CMakeLists.txt rename to boards/silabs/efr32_thunderboard/CMakeLists.txt diff --git a/boards/arm/efr32_thunderboard/Kconfig b/boards/silabs/efr32_thunderboard/Kconfig similarity index 100% rename from boards/arm/efr32_thunderboard/Kconfig rename to boards/silabs/efr32_thunderboard/Kconfig diff --git a/boards/silabs/efr32_thunderboard/Kconfig.defconfig b/boards/silabs/efr32_thunderboard/Kconfig.defconfig new file mode 100644 index 00000000000000..9c116263518955 --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.defconfig @@ -0,0 +1,38 @@ +# Thunderboard-style boards + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config CMU_HFXO_FREQ + default 38400000 + +config CMU_LFXO_FREQ + default 32768 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config COMMON_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 3072 if PM + default 2304 + +choice BT_HCI_BUS_TYPE + default BT_SILABS_HCI +endchoice + +endif # BT + +config REGULATOR + default y if SI7210 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a new file mode 100644 index 00000000000000..2cbcd4397614fb --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184a @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32BG22_BRD4184A + select SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b new file mode 100644 index 00000000000000..48a8915cf5ae44 --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg22_brd4184b @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32BG22_BRD4184B + select SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a new file mode 100644 index 00000000000000..7bf2e70d45533d --- /dev/null +++ b/boards/silabs/efr32_thunderboard/Kconfig.efr32bg27_brd2602a @@ -0,0 +1,7 @@ +# EFR32BG SLTB010A board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32BG27_BRD2602A + select SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/boards/arm/efr32_thunderboard/board.c b/boards/silabs/efr32_thunderboard/board.c similarity index 100% rename from boards/arm/efr32_thunderboard/board.c rename to boards/silabs/efr32_thunderboard/board.c diff --git a/boards/silabs/efr32_thunderboard/board.cmake b/boards/silabs/efr32_thunderboard/board.cmake new file mode 100644 index 00000000000000..d27a7983eb1dbe --- /dev/null +++ b/boards/silabs/efr32_thunderboard/board.cmake @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_BOARD_EFR32BG22_BRD4184A OR CONFIG_BOARD_EFR32BG22_BRD4184B) + board_runner_args(jlink "--device=EFR32BG22C224F512IM40" "--reset-after-load") + include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +elseif(CONFIG_BOARD_EFR32BG27_BRD2602A) + board_runner_args(silabs_commander "--device=EFR32BG27C140F768IM40") + include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake) +endif() diff --git a/boards/silabs/efr32_thunderboard/board.yml b/boards/silabs/efr32_thunderboard/board.yml new file mode 100644 index 00000000000000..ebfe25a104c0ce --- /dev/null +++ b/boards/silabs/efr32_thunderboard/board.yml @@ -0,0 +1,13 @@ +boards: + - name: efr32bg22_brd4184a + vendor: silabs + socs: + - name: efr32bg22c224f512im40 + - name: efr32bg22_brd4184b + vendor: silabs + socs: + - name: efr32bg22c224f512im40 + - name: efr32bg27_brd2602a + vendor: silabs + socs: + - name: efr32bg27c140f768im40 diff --git a/boards/arm/efr32_thunderboard/doc/brd2602.rst b/boards/silabs/efr32_thunderboard/doc/brd2602.rst similarity index 100% rename from boards/arm/efr32_thunderboard/doc/brd2602.rst rename to boards/silabs/efr32_thunderboard/doc/brd2602.rst diff --git a/boards/arm/efr32_thunderboard/doc/brd4184.rst b/boards/silabs/efr32_thunderboard/doc/brd4184.rst similarity index 96% rename from boards/arm/efr32_thunderboard/doc/brd4184.rst rename to boards/silabs/efr32_thunderboard/doc/brd4184.rst index 56685b31079922..a6f1c281d3c8e8 100644 --- a/boards/arm/efr32_thunderboard/doc/brd4184.rst +++ b/boards/silabs/efr32_thunderboard/doc/brd4184.rst @@ -79,9 +79,10 @@ The efr32bg22_brd4184a/b board configuration supports the following hardware fea | RADIO | on-chip | bluetooth | +-----------+------------+-------------------------------------+ -The default configuration can be found in the defconfig files: -- ``boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig`` -- ``boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig` +and +:zephyr_file:`boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig` Connections and IOs =================== @@ -168,17 +169,9 @@ Open a serial terminal (minicom, putty, etc.) with the following settings: Reset the board and you should be able to see on the corresponding Serial Port the following message: -BRD4184A: - -.. code-block:: console - - Hello World! efr32bg22_brd4184a - -BRD4184B: - .. code-block:: console - Hello World! efr32bg22_brd4184b + Hello World! efr32bg22_brd4184 Bluetooth ========= diff --git a/boards/arm/efr32_thunderboard/doc/efr32bg_sltb010a.jpg b/boards/silabs/efr32_thunderboard/doc/efr32bg_sltb010a.jpg similarity index 100% rename from boards/arm/efr32_thunderboard/doc/efr32bg_sltb010a.jpg rename to boards/silabs/efr32_thunderboard/doc/efr32bg_sltb010a.jpg diff --git a/boards/arm/efr32_thunderboard/doc/index.rst b/boards/silabs/efr32_thunderboard/doc/index.rst similarity index 100% rename from boards/arm/efr32_thunderboard/doc/index.rst rename to boards/silabs/efr32_thunderboard/doc/index.rst diff --git a/boards/arm/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml b/boards/silabs/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml rename to boards/silabs/efr32_thunderboard/dts/bindings/silabs,gecko-wake-up-triggers.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184.dtsi b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184.dtsi similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184.dtsi rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184.dtsi diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a.dts b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.dts similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184a.dts rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.dts diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a.yaml b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184a.yaml rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184a.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig similarity index 88% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig index cbef0c4a05c43b..50a14221ec99e9 100644 --- a/boards/arm/efr32_thunderboard/efr32bg22_brd4184a_defconfig +++ b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184a_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG22=y -CONFIG_BOARD_EFR32BG22_BRD4184A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b.dts b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.dts similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184b.dts rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.dts diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b.yaml b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184b.yaml rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184b.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig similarity index 88% rename from boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig rename to boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig index 2d2e5f1ad7e207..50a14221ec99e9 100644 --- a/boards/arm/efr32_thunderboard/efr32bg22_brd4184b_defconfig +++ b/boards/silabs/efr32_thunderboard/efr32bg22_brd4184b_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG22=y -CONFIG_BOARD_EFR32BG22_BRD4184B=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a.dts b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.dts similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg27_brd2602a.dts rename to boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.dts diff --git a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a.yaml b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.yaml similarity index 100% rename from boards/arm/efr32_thunderboard/efr32bg27_brd2602a.yaml rename to boards/silabs/efr32_thunderboard/efr32bg27_brd2602a.yaml diff --git a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a_defconfig b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig similarity index 88% rename from boards/arm/efr32_thunderboard/efr32bg27_brd2602a_defconfig rename to boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig index ecb0b7172ff201..50a14221ec99e9 100644 --- a/boards/arm/efr32_thunderboard/efr32bg27_brd2602a_defconfig +++ b/boards/silabs/efr32_thunderboard/efr32bg27_brd2602a_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32BG27=y -CONFIG_BOARD_EFR32BG27_BRD2602A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32_thunderboard/pre_dt_board.cmake b/boards/silabs/efr32_thunderboard/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32_thunderboard/pre_dt_board.cmake rename to boards/silabs/efr32_thunderboard/pre_dt_board.cmake diff --git a/boards/arm/efr32_thunderboard/thunderboard.dtsi b/boards/silabs/efr32_thunderboard/thunderboard.dtsi similarity index 100% rename from boards/arm/efr32_thunderboard/thunderboard.dtsi rename to boards/silabs/efr32_thunderboard/thunderboard.dtsi diff --git a/boards/arm/efr32mg_sltb004a/CMakeLists.txt b/boards/silabs/efr32mg_sltb004a/CMakeLists.txt similarity index 100% rename from boards/arm/efr32mg_sltb004a/CMakeLists.txt rename to boards/silabs/efr32mg_sltb004a/CMakeLists.txt diff --git a/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig b/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig new file mode 100644 index 00000000000000..5dd6c6417a7410 --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/Kconfig.defconfig @@ -0,0 +1,14 @@ +# EFR32MG SLTB004A board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFR32MG_SLTB004A + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +endif # BOARD_EFR32MG_SLTB004A diff --git a/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a b/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a new file mode 100644 index 00000000000000..3f2245d372e3c5 --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/Kconfig.efr32mg_sltb004a @@ -0,0 +1,7 @@ +# EFR32MG SLTB004A board + +# Copyright (c) 2018, Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32MG_SLTB004A + select SOC_PART_NUMBER_EFR32MG12P332F1024GL125 diff --git a/boards/arm/efr32mg_sltb004a/board.c b/boards/silabs/efr32mg_sltb004a/board.c similarity index 100% rename from boards/arm/efr32mg_sltb004a/board.c rename to boards/silabs/efr32mg_sltb004a/board.c diff --git a/boards/arm/efr32mg_sltb004a/board.cmake b/boards/silabs/efr32mg_sltb004a/board.cmake similarity index 100% rename from boards/arm/efr32mg_sltb004a/board.cmake rename to boards/silabs/efr32mg_sltb004a/board.cmake diff --git a/boards/silabs/efr32mg_sltb004a/board.yml b/boards/silabs/efr32mg_sltb004a/board.yml new file mode 100644 index 00000000000000..cef6207cf03c50 --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/board.yml @@ -0,0 +1,5 @@ +board: + name: efr32mg_sltb004a + vendor: silabs + socs: + - name: efr32mg12p332f1024gl125 diff --git a/boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg b/boards/silabs/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg similarity index 100% rename from boards/arm/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg rename to boards/silabs/efr32mg_sltb004a/doc/efr32mg_sltb004a.jpg diff --git a/boards/silabs/efr32mg_sltb004a/doc/index.rst b/boards/silabs/efr32mg_sltb004a/doc/index.rst new file mode 100644 index 00000000000000..fb595bbc7a850d --- /dev/null +++ b/boards/silabs/efr32mg_sltb004a/doc/index.rst @@ -0,0 +1,220 @@ +.. _efr32mg_sltb004a: + +EFR32MG-SLTB004A +################ + +Overview +******** + +The EFR32™ Mighty Gecko Starter Kit EFR32MG-SLTB004A (a.k.a Thunderboard +Sense 2) contains a MCU from the EFR32MG family built on ARM® Cortex®-M4F +processor with low power capabilities. + +.. image:: efr32mg_sltb004a.jpg + :align: center + :alt: EFR32MG-SLTB004A + +Hardware +******** + +- EFR32MG12 Mighty Gecko Wireless SoC with 38.4 MHz operating frequency +- ARM® Cortex® M4 core with 256 kB RAM and 1024 kB Flash +- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F) +- 2.4 GHz ceramic antenna for wireless transmission +- Silicon Labs Si7021 relative humidity and temperature sensor +- Silicon Labs Si1133 UV index and ambient light sensor +- Silicon Labs Si7210 hall effect sensor +- Bosch Sensortec BMP280 barometric pressure sensor +- ams CCS811 indoor air quality gas sensor +- TDK InvenSense ICM-20648 6-axis inertial sensor +- TDK InvenSense ICS-43434 MEMS microphone +- Four high brightness RGB LEDs from Broadcom Limited (ASMT-YTB7-0AA02) +- One bi-color LED and two push buttons +- Power enable signals for fine grained power-control +- On-board SEGGER J-Link debugger for easy programming and debugging, which + includes a USB virtual COM port +- Mini Simplicity connector for access to energy profiling and advanced wireless + network debugging +- Breakout pads for GPIO access and connection to external hardware +- Reset button +- Automatic switch-over between USB and battery power +- CR2032 coin cell holder and external battery connector + +For more information about the EFR32MG SoC and Thunderboard Sense 2 +(EFR32MG-SLTB004A) board: + +- `EFR32MG Website`_ +- `EFR32MG Datasheet`_ +- `EFR32MG Reference Manual`_ +- `EFR32MG-SLTB004A Website`_ +- `EFR32MG-SLTB004A User Guide`_ +- `EFR32MG-SLTB004A Schematics`_ + +Supported Features +================== + +The efr32mg_sltb004a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| SPI(M) | on-chip | spi port-polling | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig`` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFR32MG SoC has eight gpio controllers (PORTA, PORTB, PORTC, PORTD, +PORTF, PORTI, PORTJ and PORTK). + +In the following table, the column Name contains Pin names. For example, PE2 +means Pin number 2 on PORTE and #27 represents the location bitfield , as used +in the board's and microcontroller's datasheets and manuals. + ++------+-------------+-----------------------------------+ +| Name | Function | Usage | ++======+=============+===================================+ +| PD8 | GPIO | LED0 (RED) | ++------+-------------+-----------------------------------+ +| PD9 | GPIO | LED1 (GREEN) | ++------+-------------+-----------------------------------+ +| PD14 | GPIO | SW0 Push Button PB0 | ++------+-------------+-----------------------------------+ +| PD15 | GPIO | Push Button PB1 | ++------+-------------+-----------------------------------+ +| PA0 | UART_TX | UART TX Console VCOM_TX US0_TX #0 | ++------+-------------+-----------------------------------+ +| PA1 | UART_RX | UART RX Console VCOM_RX US0_RX #0 | ++------+-------------+-----------------------------------+ +| PF3 | UART_TX | EXP12_UART_TX LEU0_TX #27 | ++------+-------------+-----------------------------------+ +| PF4 | UART_RX | EXP14_UART_RX LEU0_RX #27 | ++------+-------------+-----------------------------------+ +| PC10 | I2C_SDA | EXP16_I2C_SDA I2C0_SDA #15 | ++------+-------------+-----------------------------------+ +| PC11 | I2C_SCL | EXP15_I2C_SCL I2C0_SCL #15 | ++------+-------------+-----------------------------------+ +| PB6 | I2C_SDA | CCS811_I2C_SDA I2C1_SDA #6 | ++------+-------------+-----------------------------------+ +| PB7 | I2C_SCL | CCS811_I2C_SCL I2C1_SCL #6 | ++------+-------------+-----------------------------------+ +| PK0 | SPI_MOSI | Flash MOSI US2_TX #29 | ++------+-------------+-----------------------------------+ +| PK2 | SPI_MISO | Flash MISO US2_RX #30 | ++------+-------------+-----------------------------------+ +| PF7 | SPI_SCLK | Flash SCLK US2_CLK #18 | ++------+-------------+-----------------------------------+ +| PK1 | SPI_CS | Flash Chip Select (GPIO) | ++------+-------------+-----------------------------------+ + +System Clock +============ + +The EFR32MG SoC is configured to use the 38.4 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG SoC has four USARTs and one Low Energy UARTs (LEUART with 9600 +maximum baudrate). USART0 is configured as the Zephyr console and is connected +to the On-Board J-Link Debugger that presents a virtual COM port for general +purpose application serial data transfer with this interface. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFR32MG-SLTB004A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a Mass Storage and a + USB Serial Port. +- A Serial Flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB Serial port. + +Flashing an application to EFR32-SLTB004A +----------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efr32mg_sltb004a + :goals: build + +Connect the EFR32MG-SLTB004A to your host computer using the USB port and you +should see a USB connection which exposes a Mass Storage (TB004) and a +USB Serial Port. Copy the generated zephyr.bin in the SLTB004A drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you should be able to see on the corresponding Serial Port +the following message: + +.. code-block:: console + + Hello World! arm + + +.. _EFR32MG-SLTB004A Website: + https://www.silabs.com/products/development-tools/thunderboard/thunderboard-sense-two-kit + +.. _EFR32MG-SLTB004A User Guide: + https://www.silabs.com/documents/public/user-guides/ug309-sltb004a-user-guide.pdf + +.. _EFR32MG-SLTB004A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD4166A-D00-schematic.pdf + +.. _EFR32MG Website: + https://www.silabs.com/products/wireless/mesh-networking/efr32mg-mighty-gecko-zigbee-thread-soc + +.. _EFR32MG Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg12-datasheet.pdf + +.. _EFR32MG Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg12-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.dts similarity index 100% rename from boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.dts rename to boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.dts diff --git a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.yaml b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.yaml similarity index 100% rename from boards/arm/efr32mg_sltb004a/efr32mg_sltb004a.yaml rename to boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a.yaml diff --git a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig similarity index 80% rename from boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig rename to boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig index 4182a0df8e4da8..17eefb534ca224 100644 --- a/boards/arm/efr32mg_sltb004a/efr32mg_sltb004a_defconfig +++ b/boards/silabs/efr32mg_sltb004a/efr32mg_sltb004a_defconfig @@ -1,8 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 CONFIG_ARM_MPU=y -CONFIG_SOC_SERIES_EFR32MG12P=y -CONFIG_BOARD_EFR32MG_SLTB004A=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y CONFIG_SERIAL=y diff --git a/boards/arm/efr32mg_sltb004a/pre_dt_board.cmake b/boards/silabs/efr32mg_sltb004a/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32mg_sltb004a/pre_dt_board.cmake rename to boards/silabs/efr32mg_sltb004a/pre_dt_board.cmake diff --git a/boards/arm/efr32xg24_dk2601b/Kconfig b/boards/silabs/efr32xg24_dk2601b/Kconfig similarity index 100% rename from boards/arm/efr32xg24_dk2601b/Kconfig rename to boards/silabs/efr32xg24_dk2601b/Kconfig diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig b/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig new file mode 100644 index 00000000000000..a63ff0ee6a76b8 --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/Kconfig.defconfig @@ -0,0 +1,42 @@ +# EFR32XG24 DK2601B board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFR32XG24_DK2601B + +config CMU_HFXO_FREQ + default 40000000 + +config CMU_LFXO_FREQ + default 32768 + +config FLASH_BASE_ADDRESS + hex + default 0x08000000 + +if SOC_GECKO_USE_RAIL + +config FPU + default y + +endif # SOC_GECKO_USE_RAIL + +if BT + +config FPU + default y + +config MINIMAL_LIBC_MALLOC_ARENA_SIZE + default 8192 + +config MAIN_STACK_SIZE + default 2304 + +choice BT_HCI_BUS_TYPE + default BT_SILABS_HCI +endchoice + +endif # BT + +endif # BOARD_EFR32XG24_DK2601B diff --git a/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b b/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b new file mode 100644 index 00000000000000..3826dc11b2a725 --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/Kconfig.efr32xg24_dk2601b @@ -0,0 +1,7 @@ +# EFR32XG24 DK2601B board + +# Copyright (c) 2021, Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFR32XG24_DK2601B + select SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/boards/arm/efr32xg24_dk2601b/board.c b/boards/silabs/efr32xg24_dk2601b/board.c similarity index 100% rename from boards/arm/efr32xg24_dk2601b/board.c rename to boards/silabs/efr32xg24_dk2601b/board.c diff --git a/boards/arm/efr32xg24_dk2601b/board.cmake b/boards/silabs/efr32xg24_dk2601b/board.cmake similarity index 100% rename from boards/arm/efr32xg24_dk2601b/board.cmake rename to boards/silabs/efr32xg24_dk2601b/board.cmake diff --git a/boards/silabs/efr32xg24_dk2601b/board.yml b/boards/silabs/efr32xg24_dk2601b/board.yml new file mode 100644 index 00000000000000..d4efb7ba178927 --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/board.yml @@ -0,0 +1,5 @@ +board: + name: efr32xg24_dk2601b + vendor: silabs + socs: + - name: efr32mg24b310f1536im48 diff --git a/boards/arm/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg b/boards/silabs/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg similarity index 100% rename from boards/arm/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg rename to boards/silabs/efr32xg24_dk2601b/doc/img/efr32xg24_dk2601b.jpg diff --git a/boards/silabs/efr32xg24_dk2601b/doc/index.rst b/boards/silabs/efr32xg24_dk2601b/doc/index.rst new file mode 100644 index 00000000000000..f6be0f828897d6 --- /dev/null +++ b/boards/silabs/efr32xg24_dk2601b/doc/index.rst @@ -0,0 +1,184 @@ +.. _efr32mg24_dk2601b: + +xG24-DK2601B +########################### + +Overview +******** + +The EFR32MG24 Mighty Gecko Board dev kit contains +a Wireless System-On-Chip from the EFR32MG24 family built on an +ARM Cortex®-M33F processor with excellent low power capabilities. + +.. figure:: ./img/efr32xg24_dk2601b.jpg + :height: 260px + :align: center + :alt: SLWRB4180A Mighty Gecko Radio Board + + xG24-DK2601B (image courtesy of Silicon Labs) + +Hardware +******** + +- EFR32MG24B310F1536IM48-B Mighty Gecko SoC +- CPU core: ARM Cortex®-M33 with FPU +- Flash memory: 1536 kB +- RAM: 256 kB +- Transmit power: up to +20 dBm +- Operation frequency: 2.4 GHz +- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz). +- On board sensors: + + - Silicon Labs Si7021 relative humidity & temperature sensor + - Silicon Labs Si7210 hall effect sensor + - 2x TDK InvenSense ICS-43434 MEMS microphones with I2S output + - TDK InvenSense ICM-20689 6-axis inertial measurement sensor + - Vishay VEML6035 ambient light sensor + - Bosch BMP384 pressure sensor with internal temperature sensor + +For more information about the EFR32MG24 SoC and BRD2601B board, refer to these +documents: + +- `EFR32MG24 Website`_ +- `EFR32MG24 Datasheet`_ +- `EFR32xG24 Reference Manual`_ +- `BRD2601B User Guide`_ + +Supported Features +================== + +The board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | stimer | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | semailbox | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | watchdog | ++-----------+------------+-------------------------------------+ +| I2C(M/S) | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| RADIO | on-chip | bluetooth | ++-----------+------------+-------------------------------------+ + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +In the following table, the column **Name** contains Pin names. For example, PA2 +means Pin number 2 on PORTA, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PA4 | GPIO | LED0 | ++-------+-------------+-------------------------------------+ +| PB0 | GPIO | LED1 | ++-------+-------------+-------------------------------------+ +| PB2 | GPIO | Push Button 0 | ++-------+-------------+-------------------------------------+ +| PB3 | GPIO | Push Button 1 | ++-------+-------------+-------------------------------------+ +| PA5 | USART0_TX | UART Console EFM_BC_TX US0_TX | ++-------+-------------+-------------------------------------+ +| PA6 | USART0_RX | UART Console EFM_BC_RX US0_RX | ++-------+-------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig` + +System Clock +============ + +The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFR32MG24 SoC has one USART and two EUSARTs. +USART0 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efr32xg24_dk2601b + :goals: build + +Connect the efr32xg24_dk2601b to your host computer using the USB port and you +should see a USB connection. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efr32xg24_dk2601b + +Bluetooth +========= + +To use the BLE function, run the command below to retrieve necessary binary +blobs from the SiLabs HAL repository. + +.. code-block:: console + + west blobs fetch silabs + +Then build the Zephyr kernel and a Bluetooth sample with the following +command. The :ref:`bluetooth-observer-sample` sample application is used in +this example. + +.. zephyr-app-commands:: + :zephyr-app: samples/bluetooth/observer + :board: efr32xg24_dk2601b + :goals: build + +.. _EFR32MG24 Website: + https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs# + +.. _EFR32MG24 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf + +.. _EFR32xG24 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efr32xg24-rm.pdf + +.. _BRD2601B User Guide: + https://www.silabs.com/documents/public/user-guides/ug524-brd2601b-user-guide.pdf + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml b/boards/silabs/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml similarity index 100% rename from boards/arm/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml rename to boards/silabs/efr32xg24_dk2601b/dts/bindings/silabs,gecko-wake-up-trigger.yaml diff --git a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.dts b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.dts similarity index 100% rename from boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.dts rename to boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.dts diff --git a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml similarity index 100% rename from boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml rename to boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b.yaml diff --git a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig similarity index 86% rename from boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig rename to boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig index e09abbd5482b6e..caadb4bb35b1e9 100644 --- a/boards/arm/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig +++ b/boards/silabs/efr32xg24_dk2601b/efr32xg24_dk2601b_defconfig @@ -1,8 +1,6 @@ # Copyright (c) 2022 Silicon Labs # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_EFR32MG24=y -CONFIG_BOARD_EFR32XG24_DK2601B=y CONFIG_ARM_MPU=y CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y @@ -11,9 +9,9 @@ CONFIG_CORTEX_M_SYSTICK=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=76800000 CONFIG_CMU_HFCLK_HFXO=y -CONFIG_SOC_GECKO_EMU_DCDC=y -CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y CONFIG_CMU_HFCLK_LFXO=y CONFIG_HW_STACK_PROTECTION=y CONFIG_PINCTRL=y CONFIG_REGULATOR=y +CONFIG_SOC_GECKO_EMU_DCDC=y +CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON=y diff --git a/boards/arm/efr32xg24_dk2601b/pre_dt_board.cmake b/boards/silabs/efr32xg24_dk2601b/pre_dt_board.cmake similarity index 100% rename from boards/arm/efr32xg24_dk2601b/pre_dt_board.cmake rename to boards/silabs/efr32xg24_dk2601b/pre_dt_board.cmake diff --git a/boards/silabs/index.rst b/boards/silabs/index.rst new file mode 100644 index 00000000000000..0b658035e63422 --- /dev/null +++ b/boards/silabs/index.rst @@ -0,0 +1,10 @@ +.. _boards-silabs: + +Silabgs +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sipeed/index.rst b/boards/sipeed/index.rst new file mode 100644 index 00000000000000..e84a42fc254eec --- /dev/null +++ b/boards/sipeed/index.rst @@ -0,0 +1,10 @@ +.. _boards-sipeed: + +Sipeed +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sipeed/longan_nano/Kconfig.defconfig b/boards/sipeed/longan_nano/Kconfig.defconfig new file mode 100644 index 00000000000000..2eef2edbc2fa12 --- /dev/null +++ b/boards/sipeed/longan_nano/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Sipeed longan nano Development Board Configuration + +# Copyright (c) 2021 Tokita, Hiroshi + +if BOARD_LONGAN_NANO + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_LONGAN_NANO diff --git a/boards/sipeed/longan_nano/Kconfig.longan_nano b/boards/sipeed/longan_nano/Kconfig.longan_nano new file mode 100644 index 00000000000000..2ac5424d6b7cb0 --- /dev/null +++ b/boards/sipeed/longan_nano/Kconfig.longan_nano @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_LONGAN_NANO + select SOC_GD32VF103 diff --git a/boards/riscv/longan_nano/board.cmake b/boards/sipeed/longan_nano/board.cmake similarity index 100% rename from boards/riscv/longan_nano/board.cmake rename to boards/sipeed/longan_nano/board.cmake diff --git a/boards/sipeed/longan_nano/board.yml b/boards/sipeed/longan_nano/board.yml new file mode 100644 index 00000000000000..035ea8f540dcb2 --- /dev/null +++ b/boards/sipeed/longan_nano/board.yml @@ -0,0 +1,7 @@ +board: + name: longan_nano + vendor: sipeed + socs: + - name: gd32vf103 + variants: + - name: lite diff --git a/boards/riscv/longan_nano/doc/img/longan_nano.jpg b/boards/sipeed/longan_nano/doc/img/longan_nano.jpg similarity index 100% rename from boards/riscv/longan_nano/doc/img/longan_nano.jpg rename to boards/sipeed/longan_nano/doc/img/longan_nano.jpg diff --git a/boards/riscv/longan_nano/doc/index.rst b/boards/sipeed/longan_nano/doc/index.rst similarity index 100% rename from boards/riscv/longan_nano/doc/index.rst rename to boards/sipeed/longan_nano/doc/index.rst diff --git a/boards/riscv/longan_nano/longan_nano-common.dtsi b/boards/sipeed/longan_nano/longan_nano-common.dtsi similarity index 100% rename from boards/riscv/longan_nano/longan_nano-common.dtsi rename to boards/sipeed/longan_nano/longan_nano-common.dtsi diff --git a/boards/riscv/longan_nano/longan_nano-pinctrl.dtsi b/boards/sipeed/longan_nano/longan_nano-pinctrl.dtsi similarity index 100% rename from boards/riscv/longan_nano/longan_nano-pinctrl.dtsi rename to boards/sipeed/longan_nano/longan_nano-pinctrl.dtsi diff --git a/boards/riscv/longan_nano/longan_nano.dts b/boards/sipeed/longan_nano/longan_nano.dts similarity index 100% rename from boards/riscv/longan_nano/longan_nano.dts rename to boards/sipeed/longan_nano/longan_nano.dts diff --git a/boards/riscv/longan_nano/longan_nano.yaml b/boards/sipeed/longan_nano/longan_nano.yaml similarity index 100% rename from boards/riscv/longan_nano/longan_nano.yaml rename to boards/sipeed/longan_nano/longan_nano.yaml diff --git a/boards/riscv/longan_nano/longan_nano_defconfig b/boards/sipeed/longan_nano/longan_nano_defconfig similarity index 78% rename from boards/riscv/longan_nano/longan_nano_defconfig rename to boards/sipeed/longan_nano/longan_nano_defconfig index fc2aa06f616f1e..353e533ef849b8 100644 --- a/boards/riscv/longan_nano/longan_nano_defconfig +++ b/boards/sipeed/longan_nano/longan_nano_defconfig @@ -4,10 +4,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_GD32VF103=y -CONFIG_SOC_GD32VF103=y -CONFIG_BOARD_LONGAN_NANO=y - CONFIG_GD32_HXTAL_8MHZ=y CONFIG_SERIAL=y diff --git a/boards/riscv/longan_nano/longan_nano_lite.dts b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.dts similarity index 100% rename from boards/riscv/longan_nano/longan_nano_lite.dts rename to boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.dts diff --git a/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml new file mode 100644 index 00000000000000..27636b6d47ec69 --- /dev/null +++ b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml @@ -0,0 +1,14 @@ +identifier: longan_nano/gd32vf103/lite +name: Sipeed Longan Nano Lite +type: mcu +arch: riscv +toolchain: + - zephyr + - xtools +flash: 64 +ram: 20 +supported: + - watchdog + - dma + - spi +vendor: sipeed diff --git a/boards/riscv/longan_nano/support/openocd.cfg b/boards/sipeed/longan_nano/support/openocd.cfg similarity index 100% rename from boards/riscv/longan_nano/support/openocd.cfg rename to boards/sipeed/longan_nano/support/openocd.cfg diff --git a/boards/sparc/generic_leon3/Kconfig.board b/boards/sparc/generic_leon3/Kconfig.board deleted file mode 100644 index 9ba65374a3cd8c..00000000000000 --- a/boards/sparc/generic_leon3/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GENERIC_LEON3 - bool "Generic LEON3 system" - depends on SOC_LEON3 diff --git a/boards/sparc/generic_leon3/Kconfig.defconfig b/boards/sparc/generic_leon3/Kconfig.defconfig deleted file mode 100644 index 97a92b57df5b30..00000000000000 --- a/boards/sparc/generic_leon3/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GENERIC_LEON3 - -config BOARD - default "generic_leon3" - -config SPARC_CASA - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -config UART_INTERRUPT_DRIVEN - default y - -endif diff --git a/boards/sparc/generic_leon3/generic_leon3_defconfig b/boards/sparc/generic_leon3/generic_leon3_defconfig deleted file mode 100644 index 8ec49d62baf059..00000000000000 --- a/boards/sparc/generic_leon3/generic_leon3_defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_LEON3=y -CONFIG_BOARD_GENERIC_LEON3=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_EXTRA_EXCEPTION_INFO=y diff --git a/boards/sparc/gr716a_mini/Kconfig.board b/boards/sparc/gr716a_mini/Kconfig.board deleted file mode 100644 index e200d6160c0cc0..00000000000000 --- a/boards/sparc/gr716a_mini/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_GR716A_MINI - bool "GR716-MINI Development Board" - depends on SOC_GR716A diff --git a/boards/sparc/gr716a_mini/Kconfig.defconfig b/boards/sparc/gr716a_mini/Kconfig.defconfig deleted file mode 100644 index 08132736348b4d..00000000000000 --- a/boards/sparc/gr716a_mini/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_GR716A_MINI - -config BOARD - default "gr716a_mini" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 20000000 - -config UART_INTERRUPT_DRIVEN - default y - -endif diff --git a/boards/sparc/gr716a_mini/gr716a_mini_defconfig b/boards/sparc/gr716a_mini/gr716a_mini_defconfig deleted file mode 100644 index 4f30129d3b28df..00000000000000 --- a/boards/sparc/gr716a_mini/gr716a_mini_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_GR716A=y -CONFIG_BOARD_GR716A_MINI=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/sparc/index.rst b/boards/sparc/index.rst deleted file mode 100644 index ef090183645d08..00000000000000 --- a/boards/sparc/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-sparc: - -SPARC Boards -############ - -.. toctree:: - :maxdepth: 1 - :glob: - - **/* diff --git a/boards/sparc/qemu_leon3/Kconfig.board b/boards/sparc/qemu_leon3/Kconfig.board deleted file mode 100644 index 6ba0234a17a452..00000000000000 --- a/boards/sparc/qemu_leon3/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_LEON3 - bool "QEMU LEON3 target" - depends on SOC_LEON3 - select QEMU_TARGET - select CPU_HAS_FPU diff --git a/boards/sparc/qemu_leon3/Kconfig.defconfig b/boards/sparc/qemu_leon3/Kconfig.defconfig deleted file mode 100644 index 0a48c2a4752f0c..00000000000000 --- a/boards/sparc/qemu_leon3/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_LEON3 - -config BOARD - default "qemu_leon3" - -config UART_INTERRUPT_DRIVEN - default y - -endif diff --git a/boards/sparkfun/index.rst b/boards/sparkfun/index.rst new file mode 100644 index 00000000000000..7f24ea105360f5 --- /dev/null +++ b/boards/sparkfun/index.rst @@ -0,0 +1,10 @@ +.. _boards-sparkfun-electronics: + +SparkFun Electronics +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig b/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig new file mode 100644 index 00000000000000..47d8a99ceca098 --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Sparkfun nRF52832 breakout board configuration + +# Copyright (c) 2017 Shawn Nock +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_SPARKFUN + +config BT_CTLR + default BT + +endif # BOARD_NRF52_SPARKFUN diff --git a/boards/sparkfun/nrf52_sparkfun/Kconfig.nrf52_sparkfun b/boards/sparkfun/nrf52_sparkfun/Kconfig.nrf52_sparkfun new file mode 100644 index 00000000000000..b2a3c575e35252 --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/Kconfig.nrf52_sparkfun @@ -0,0 +1,8 @@ +# Sparkfun nRF52832 breakout board configuration + +# Copyright (c) 2017 Shawn Nock +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_SPARKFUN + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_sparkfun/board.cmake b/boards/sparkfun/nrf52_sparkfun/board.cmake similarity index 100% rename from boards/arm/nrf52_sparkfun/board.cmake rename to boards/sparkfun/nrf52_sparkfun/board.cmake diff --git a/boards/sparkfun/nrf52_sparkfun/board.yml b/boards/sparkfun/nrf52_sparkfun/board.yml new file mode 100644 index 00000000000000..5e44e8a072b8a6 --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_sparkfun + vendor: sparkfun + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf b/boards/sparkfun/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf similarity index 100% rename from boards/arm/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf rename to boards/sparkfun/nrf52_sparkfun/doc/sparkfun-nrf52832-breakout-schematic-v10.pdf diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi rename to boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun-pinctrl.dtsi diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun.dts b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.dts similarity index 100% rename from boards/arm/nrf52_sparkfun/nrf52_sparkfun.dts rename to boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.dts diff --git a/boards/arm/nrf52_sparkfun/nrf52_sparkfun.yaml b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml similarity index 100% rename from boards/arm/nrf52_sparkfun/nrf52_sparkfun.yaml rename to boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml diff --git a/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun_defconfig b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/ruuvi_ruuvitag/pre_dt_board.cmake b/boards/sparkfun/nrf52_sparkfun/pre_dt_board.cmake similarity index 100% rename from boards/arm/ruuvi_ruuvitag/pre_dt_board.cmake rename to boards/sparkfun/nrf52_sparkfun/pre_dt_board.cmake diff --git a/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig b/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig new file mode 100644 index 00000000000000..57aecafff006de --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2021 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SPARKFUN_PRO_MICRO_RP2040 + +config RP2_FLASH_W25Q080 + default y + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_SPARKFUN_PRO_MICRO_RP2040 diff --git a/boards/sparkfun/pro_micro_rp2040/Kconfig.sparkfun_pro_micro_rp2040 b/boards/sparkfun/pro_micro_rp2040/Kconfig.sparkfun_pro_micro_rp2040 new file mode 100644 index 00000000000000..1bb3c7bf6e5e33 --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/Kconfig.sparkfun_pro_micro_rp2040 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Pete Johanson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_PRO_MICRO_RP2040 + select SOC_RP2040 diff --git a/boards/arm/sparkfun_pro_micro_rp2040/board.cmake b/boards/sparkfun/pro_micro_rp2040/board.cmake similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/board.cmake rename to boards/sparkfun/pro_micro_rp2040/board.cmake diff --git a/boards/sparkfun/pro_micro_rp2040/board.yml b/boards/sparkfun/pro_micro_rp2040/board.yml new file mode 100644 index 00000000000000..ed9e449e8aa235 --- /dev/null +++ b/boards/sparkfun/pro_micro_rp2040/board.yml @@ -0,0 +1,5 @@ +board: + name: sparkfun_pro_micro_rp2040 + vendor: sparkfun + socs: + - name: rp2040 diff --git a/boards/arm/sparkfun_pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg b/boards/sparkfun/pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg rename to boards/sparkfun/pro_micro_rp2040/doc/img/sparkfun_pro_micro_rp2040.jpg diff --git a/boards/arm/sparkfun_pro_micro_rp2040/doc/index.rst b/boards/sparkfun/pro_micro_rp2040/doc/index.rst similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/doc/index.rst rename to boards/sparkfun/pro_micro_rp2040/doc/index.rst diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_connector.dtsi diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040-pinctrl.dtsi diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.dts diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml similarity index 100% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml diff --git a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig similarity index 76% rename from boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig rename to boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig index 36aba349204086..ef4e863884ab57 100644 --- a/boards/arm/sparkfun_pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig +++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040_defconfig @@ -1,17 +1,13 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_SPARKFUN_PRO_MICRO_RP2040=y - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_RESET=y -# enable uart driver +# Enable UART driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y -# enable console +# Enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/sparkfun/red_v_things_plus/Kconfig.defconfig b/boards/sparkfun/red_v_things_plus/Kconfig.defconfig new file mode 100644 index 00000000000000..a67cae7efe3798 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2019 SiFive Inc. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SPARKFUN_RED_V_THINGS_PLUS + +config SYS_CLOCK_TICKS_PER_SEC + default 128 + +config HAS_FLASH_LOAD_OFFSET + default y + +config FLASH_LOAD_OFFSET + default 0x0 + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/spi@10014000,1) + +endif # BOARD_SPARKFUN_RED_V_THINGS_PLUS diff --git a/boards/sparkfun/red_v_things_plus/Kconfig.sparkfun_red_v_things_plus b/boards/sparkfun/red_v_things_plus/Kconfig.sparkfun_red_v_things_plus new file mode 100644 index 00000000000000..7118f8a3ce36d6 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/Kconfig.sparkfun_red_v_things_plus @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_RED_V_THINGS_PLUS + select SOC_SIFIVE_FREEDOM_FE310 diff --git a/boards/sparkfun/red_v_things_plus/board.cmake b/boards/sparkfun/red_v_things_plus/board.cmake new file mode 100644 index 00000000000000..134172931887bd --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/board.cmake @@ -0,0 +1,9 @@ +# Copyright (c) 2019 SiFive Inc. +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=FE310") +board_runner_args(jlink "--iface=JTAG") +board_runner_args(jlink "--speed=4000") +board_runner_args(jlink "--tool-opt=-jtagconf -1,-1") +board_runner_args(jlink "--tool-opt=-autoconnect 1") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/sparkfun/red_v_things_plus/board.yml b/boards/sparkfun/red_v_things_plus/board.yml new file mode 100644 index 00000000000000..6ef8e39c2f9207 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/board.yml @@ -0,0 +1,5 @@ +board: + name: sparkfun_red_v_things_plus + vendor: sparkfun + socs: + - name: fe310 diff --git a/boards/riscv/sparkfun_red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg b/boards/sparkfun/red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg rename to boards/sparkfun/red_v_things_plus/doc/img/sparkfun_red_v_things_plus.jpg diff --git a/boards/riscv/sparkfun_red_v_things_plus/doc/index.rst b/boards/sparkfun/red_v_things_plus/doc/index.rst similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/doc/index.rst rename to boards/sparkfun/red_v_things_plus/doc/index.rst diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi rename to boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus-pinctrl.dtsi diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.dts b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.dts similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.dts rename to boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.dts diff --git a/boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.yaml b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.yaml similarity index 100% rename from boards/riscv/sparkfun_red_v_things_plus/sparkfun_red_v_things_plus.yaml rename to boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus.yaml diff --git a/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig new file mode 100644 index 00000000000000..2085c58676a1d4 --- /dev/null +++ b/boards/sparkfun/red_v_things_plus/sparkfun_red_v_things_plus_defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019 SiFive Inc. +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_GPIO=y +CONFIG_PINCTRL=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_SIFIVE_PORT_0=y +CONFIG_UART_CONSOLE=y diff --git a/boards/sparkfun/thing_plus/Kconfig b/boards/sparkfun/thing_plus/Kconfig new file mode 100644 index 00000000000000..dec3626ba750be --- /dev/null +++ b/boards/sparkfun/thing_plus/Kconfig @@ -0,0 +1,11 @@ +# Sparkfun nRF9160 Thing Plus configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_THING_PLUS + # The GPIO driver is required by this board's initialization code + # (board.c), so it is forced here to be enabled always, not only + # enabled by default (in defconfig). + select GPIO diff --git a/boards/sparkfun/thing_plus/Kconfig.defconfig b/boards/sparkfun/thing_plus/Kconfig.defconfig new file mode 100644 index 00000000000000..5273768aa501fa --- /dev/null +++ b/boards/sparkfun/thing_plus/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Circuit Dojo nRF9160 Feather configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SPARKFUN_THING_PLUS + +# For the secure version of the board the firmware is linked at the beginning +# of the flash, or into the code-partition defined in DT if it is intended to +# be loaded by MCUboot. If the secure firmware is to be combined with a non- +# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always +# be restricted to the size of its code partition. +# For the non-secure version of the board, the firmware +# must be linked into the code-partition (non-secure) defined in DT, regardless. +# Apply this configuration below by setting the Kconfig symbols used by +# the linker according to the information extracted from DT partitions. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + depends on BOARD_SPARKFUN_THING_PLUS_NRF9160 && TRUSTED_EXECUTION_SECURE + +if BOARD_SPARKFUN_THING_PLUS_NRF9160_NS + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +config FLASH_LOAD_SIZE + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) + +endif # BOARD_SPARKFUN_THING_PLUS_NRF9160 + +endif # BOARD_SPARKFUN_THING_PLUS diff --git a/boards/sparkfun/thing_plus/Kconfig.sparkfun_thing_plus b/boards/sparkfun/thing_plus/Kconfig.sparkfun_thing_plus new file mode 100644 index 00000000000000..30710c008ee209 --- /dev/null +++ b/boards/sparkfun/thing_plus/Kconfig.sparkfun_thing_plus @@ -0,0 +1,8 @@ +# Sparkfun nRF9160 Thing Plus configuration + +# Copyright (c) 2018-2020 Nordic Semiconductor ASA +# Copyright (c) 2020 Circuit Dojo LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SPARKFUN_THING_PLUS + select SOC_NRF9160_SICA diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/board.cmake b/boards/sparkfun/thing_plus/board.cmake similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/board.cmake rename to boards/sparkfun/thing_plus/board.cmake diff --git a/boards/sparkfun/thing_plus/board.yml b/boards/sparkfun/thing_plus/board.yml new file mode 100644 index 00000000000000..18037dfd5b66f0 --- /dev/null +++ b/boards/sparkfun/thing_plus/board.yml @@ -0,0 +1,7 @@ +board: + name: sparkfun_thing_plus + vendor: sparkfun + socs: + - name: nrf9160 + variants: + - name: 'ns' diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/doc/img/sparkfun_thing_plus_nrf9160.jpg b/boards/sparkfun/thing_plus/doc/img/sparkfun_thing_plus_nrf9160.jpg similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/doc/img/sparkfun_thing_plus_nrf9160.jpg rename to boards/sparkfun/thing_plus/doc/img/sparkfun_thing_plus_nrf9160.jpg diff --git a/boards/sparkfun/thing_plus/doc/index.rst b/boards/sparkfun/thing_plus/doc/index.rst new file mode 100644 index 00000000000000..a6c7aee9742fb4 --- /dev/null +++ b/boards/sparkfun/thing_plus/doc/index.rst @@ -0,0 +1,153 @@ +.. _sparkfun_thing_plus_nrf9160: + +nRF9160 Thing Plus +################## + +.. figure:: img/sparkfun_thing_plus_nrf9160.jpg + :align: center + :alt: Sparkfun nRF9160 Thing Plus + + nRF9160 Thing Plus (Credit: Sparkfun) + +Overview +******** + +The nRF9160 Thing Plus designed by Circuit Dojo is a single-board development +for bringing your LTE-M and NB-IoT applications to life. The sparkfun_thing_plus_nrf9160 +board configuration leverages the pre-existing support for the Nordic Semiconductor +nRF9160. Supported nRF9160 peripherals include: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UARTE (Universal asynchronous receiver-transmitter with EasyDMA)` +* :abbr:`WDT (Watchdog Timer)` +* :abbr:`IDAU (Implementation Defined Attribution Unit)` + +More information about the board can be found at the +`nRF9160 Thing Plus Documentation`_. + + +Hardware +******** + +Connections and IOs +=================== + +The nRF9160 Thing Plus has everything you know and love about +the Feather platform. Here are some of the highlights: + +LED +--- + +* D7 (blue) = P0.03 + +Push buttons and Switches +------------------------- + +* MODE = P0.12 +* RESET + +USB +--- + +Contains a USB/UART connection for both debugging and loading new +code using a UART Enabled MCUBoot. + +Standard Battery Connection +---------------------------- + +The nRF9160 Thing Plus has a 2 pin battery connector on board. Lithium Polymer batteries > +300mA required. + +Nano SIM Holder +--------------- + +The nRF9160 Thing Plus has a built-in nano SIM (4FF) holder located +on the bottom side. + + +Programming and Debugging +************************* + +sparkfun_thing_plus_nrf9160 can be used with most programmers like: + +* J-Link (the nRF53-DK is recommended) +* CMSIS-DAP based programmers + +Check out `Getting Started`_ for more info. + +Building an application +======================= + +In most cases you'll want to use the ``ns`` target with any of the Zephyr +or Nordic based examples. + +Some of the examples do not use secure mode, so they do not required the ``ns`` suffix. +A great example of this is the `hello_world` below. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ screen /dev/ 115200 + +Replace :code:`` with the port where the nRF9160 Thing Plus +can be found. In most cases (On Linux/Mac) it will be: :code:`/dev/tty.SLAB_USBtoUART`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: sparkfun_thing_plus_nrf9160 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons on the nRF9160 Thing Plus +****************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +* :zephyr:code-sample:`blinky` +* :zephyr:code-sample:`button` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi`. + +References +********** + +.. target-notes:: + +**Side note** This page was based on the documentation for the nRF9160 DK. Thanks to Nordic for +developing a great platform! + +.. _nRF9160 Thing Plus Documentation: https://docs.jaredwolff.com/nrf9160-introduction.html +.. _Getting Started: https://docs.jaredwolff.com/nrf9160-getting-started.html diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.dts b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.dts similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.dts rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.dts diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.yaml b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml similarity index 82% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.yaml rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml index 8758b385c9d458..f9d59872c14906 100644 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160.yaml +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml @@ -1,4 +1,4 @@ -identifier: sparkfun_thing_plus_nrf9160 +identifier: sparkfun_thing_plus/nrf9160 name: Sparkfun-Thing-Plus-nRF9160 type: mcu arch: arm diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common-pinctrl.dtsi diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_common.dtsi rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_common.dtsi diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_defconfig b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_defconfig new file mode 100644 index 00000000000000..52852bb832c5fe --- /dev/null +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.dts b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.dts rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.dts diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.yaml b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml similarity index 81% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.yaml rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml index 65f9eaad326b81..6fbb1dfb13a7b9 100644 --- a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_ns.yaml +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml @@ -1,4 +1,4 @@ -identifier: sparkfun_thing_plus_nrf9160_ns +identifier: sparkfun_thing_plus/nrf9160/ns name: Sparkfun-Thing-Plus-nRF9160-Non-Secure type: mcu arch: arm diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns_defconfig b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns_defconfig new file mode 100644 index 00000000000000..2e8c7a1f9c891d --- /dev/null +++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns_defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable TrustZone-M +CONFIG_ARM_TRUSTZONE_M=y + +# This Board implies building Non-Secure firmware +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# Hardware stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +CONFIG_REGULATOR=y diff --git a/boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_partition_conf.dtsi b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_partition_conf.dtsi similarity index 100% rename from boards/arm/sparkfun_thing_plus_nrf9160/sparkfun_thing_plus_nrf9160_partition_conf.dtsi rename to boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_partition_conf.dtsi diff --git a/boards/st/b_g474e_dpow1/Kconfig.b_g474e_dpow1 b/boards/st/b_g474e_dpow1/Kconfig.b_g474e_dpow1 new file mode 100644 index 00000000000000..75a8d42b2ee668 --- /dev/null +++ b/boards/st/b_g474e_dpow1/Kconfig.b_g474e_dpow1 @@ -0,0 +1,5 @@ +# Copyright 2022 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_G474E_DPOW1 + select SOC_STM32G474XX diff --git a/boards/arm/b_g474e_dpow1/b_g474e_dpow1.dts b/boards/st/b_g474e_dpow1/b_g474e_dpow1.dts similarity index 100% rename from boards/arm/b_g474e_dpow1/b_g474e_dpow1.dts rename to boards/st/b_g474e_dpow1/b_g474e_dpow1.dts diff --git a/boards/arm/b_g474e_dpow1/b_g474e_dpow1.yaml b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml similarity index 100% rename from boards/arm/b_g474e_dpow1/b_g474e_dpow1.yaml rename to boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml diff --git a/boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig b/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig similarity index 88% rename from boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig rename to boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig index 6e0659f281d7c3..3da57c5589e14a 100644 --- a/boards/arm/b_g474e_dpow1/b_g474e_dpow1_defconfig +++ b/boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G474XX=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/b_g474e_dpow1/board.cmake b/boards/st/b_g474e_dpow1/board.cmake similarity index 100% rename from boards/arm/b_g474e_dpow1/board.cmake rename to boards/st/b_g474e_dpow1/board.cmake diff --git a/boards/st/b_g474e_dpow1/board.yml b/boards/st/b_g474e_dpow1/board.yml new file mode 100644 index 00000000000000..06d037f81a0f56 --- /dev/null +++ b/boards/st/b_g474e_dpow1/board.yml @@ -0,0 +1,5 @@ +board: + name: b_g474e_dpow1 + vendor: st + socs: + - name: stm32g474xx diff --git a/boards/arm/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg b/boards/st/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg similarity index 100% rename from boards/arm/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg rename to boards/st/b_g474e_dpow1/doc/img/b_g474e_dpow1.jpg diff --git a/boards/st/b_g474e_dpow1/doc/index.rst b/boards/st/b_g474e_dpow1/doc/index.rst new file mode 100644 index 00000000000000..afaa8d94f81c4b --- /dev/null +++ b/boards/st/b_g474e_dpow1/doc/index.rst @@ -0,0 +1,159 @@ +.. _b_g474e_dpow1_board: + +ST B-G474E-DPOW1 Discovery +########################## + +Overview +******** +The B-G474E-DPOW1 Discovery kit is a digital power solution and a complete +demonstration and development platform for the STMicroelectronics STM32G474RET6 +microcontroller. Leveraging the new HRTimer-oriented features, 96 Kbytes of +embedded RAM, math accelerator functions and USB-PD 3.0 offered by STM32G474RET6, +the B-G474E-DPOW1 Discovery kit, based on the USB 2.0 FS Type-C™ connector +interface, helps the user to prototype applications with digital power such as a +buck-boost converter, RGB power LED lighting or a class-D audio amplifier. The +B-G474E-DPOW1 Discovery kit does not require any separate probe, as it integrates +the STLINK-V3E debugger and programmer. + +- STM32G474RET6 Arm® Cortex®-M4 core-based microcontroller, featuring 512 Kbytes + of Flash memory and 128 Kbytes of SRAM, in LQFP64 package +- USB Type-C™ with USB 2.0 FS interface compatible with USB-PD 3.0 +- RGB power LED for a bright lighting +- Digital power buck-boost converter with internal or external Input voltage and + with onboard resistor loads +- Audio Class-D amplifier capable +- 4 user LEDs +- 3 LEDs for power and ST-LINK communication +- 4-direction joystick with a selection button +- Reset push-button +- Board connectors: + - USB Type-C™ + - USB Micro-B + - 2 x 32-pin header, 2.54 mm pitch, daughterboard extension connector for breadboard connection +- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS or external source +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: mass storage, + Virtual COM port, and debug port + +.. image:: img/b_g474e_dpow1.jpg + :align: center + :alt: B-G474E-DPOW1 + +More information about the board can be found at the `B-G474E-DPOW1 website`_. + + +More information about STM32G474RE can be found here: +- `G474RE on www.st.com`_ +- `STM32G4 reference manual`_ + + +Supported Features +================== + +The Zephyr b_g474e_dpow1 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| UCPD | on-chip | ucpd | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) +- BUTTON (JOY_SEL) : PC13 +- BUTTON (JOY_LEFT) : PC4 +- BUTTON (JOY_DOWN) : PC5 +- BUTTON (JOY_RIGHT) : PB2 +- BUTTON (JOY_UP) : PB10 +- LED (DOWN BLUE) : PA15 +- LED (LEFT ORANGE) : PB1 +- LED (UP RED) : PB5 +- LED (RIGHT GREEN) : PB7 +- USB DM : PA11 +- USB DP : PA12 +- UCPD CC2 : PB4 +- UCPD CC1 : PB6 + +For more details please refer to `B-G474E-DPOW1 Discovery board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``b_g474e_dpow1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface. + +.. code-block:: console + + $ west flash + +Flashing an application to the B_G474E_DPOW1 +-------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: b_g474e_dpow1 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_g474e_dpow1 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _B-G474E-DPOW1 website: + https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _B-G474E-DPOW1 Discovery board User Manual: + https://www.st.com/resource/en/user_manual/um2577-discovery-kit-with-stm32g474re-mcu-stmicroelectronics.pdf + +.. _G474RE on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32g474re.html diff --git a/boards/st/b_l072z_lrwan1/Kconfig.b_l072z_lrwan1 b/boards/st/b_l072z_lrwan1/Kconfig.b_l072z_lrwan1 new file mode 100644 index 00000000000000..6c1d12e2a80dfe --- /dev/null +++ b/boards/st/b_l072z_lrwan1/Kconfig.b_l072z_lrwan1 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Aleksandr Makarov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_L072Z_LRWAN1 + select SOC_STM32L072XX diff --git a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.dts b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.dts similarity index 100% rename from boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.dts rename to boards/st/b_l072z_lrwan1/b_l072z_lrwan1.dts diff --git a/boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.yaml b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml similarity index 100% rename from boards/arm/b_l072z_lrwan1/b_l072z_lrwan1.yaml rename to boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml diff --git a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig new file mode 100644 index 00000000000000..8accdc5b47c8ac --- /dev/null +++ b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/dragino_nbsn95/board.cmake b/boards/st/b_l072z_lrwan1/board.cmake similarity index 100% rename from boards/arm/dragino_nbsn95/board.cmake rename to boards/st/b_l072z_lrwan1/board.cmake diff --git a/boards/st/b_l072z_lrwan1/board.yml b/boards/st/b_l072z_lrwan1/board.yml new file mode 100644 index 00000000000000..1a7b494de19048 --- /dev/null +++ b/boards/st/b_l072z_lrwan1/board.yml @@ -0,0 +1,5 @@ +board: + name: b_l072z_lrwan1 + vendor: st + socs: + - name: stm32l072xx diff --git a/boards/arm/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg b/boards/st/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg similarity index 100% rename from boards/arm/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg rename to boards/st/b_l072z_lrwan1/doc/img/b_l072z_lrwan1.jpg diff --git a/boards/st/b_l072z_lrwan1/doc/index.rst b/boards/st/b_l072z_lrwan1/doc/index.rst new file mode 100644 index 00000000000000..5ea808478714a8 --- /dev/null +++ b/boards/st/b_l072z_lrwan1/doc/index.rst @@ -0,0 +1,250 @@ +.. _b_l072z_lrwan1_board: + +ST B-L072Z-LRWAN1 Discovery kit +############################### + +Overview +******** + +This Discovery kit features an all-in-one open module CMWX1ZZABZ-091 (by Murata). +The module is powered by an STM32L072CZ and an SX1276 transceiver. + +This kit provides: + +- CMWX1ZZABZ-091 LoRa* / Sigfox* module (Murata) + + - Embedded ultra-low-power STM32L072CZ Series MCUs, based on + Arm* Cortex* -M0+ core, with 192 Kbytes of Flash + memory, 20 Kbytes of RAM, 6 Kbytes of EEPROM + - Frequency range: 860 MHz - 930 MHz + - USB 2.0 FS + - 4-channel,12-bit ADC, 2xDAC + - 6-bit timers, LP-UART, I2C and SPI + - Embedded SX1276 transceiver + - LoRa* , FSK, GFSK, MSK, GMSK and OOK modulations (+ Sigfox* compatibility) + - +14 dBm or +20 dBm selectable output power + - 157 dB maximum link budget + - Programmable bit rate up to 300 kbit/s + - High sensitivity: down to -137 dBm + - Bullet-proof front end: IIP3 = -12.5 dBm + - 89 dB blocking immunity + - Low Rx current of 10 mA, 200 nA register retention + - Fully integrated synthesizer with a resolution of 61 Hz + - Built-in bit synchronizer for clock recovery + - Sync word recognition + - Preamble detection + - 127 dB+ dynamic range RSSI + +- SMA and U.FL RF interface connectors +- Including 50 ohm SMA RF antenna +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability + +- USB ST-LINK functions: +- Board power supply: + + - Through USB bus or external VIN/3.3 V supply voltage or batteries +- 3xAAA-type-battery holder for standalone operation +- 7 LEDs: + + - 4 general-purpose LEDs + - A 5 V-power LED + - An ST-LINK-communication LED + - A fault-power LED + - 2 push-buttons (user and reset) +- Arduino* Uno V3 connectors + +.. image:: img/b_l072z_lrwan1.jpg + :align: center + :alt: B-L072Z-LRWAN1 + +More information about the board can be found at the `B-L072Z-LRWAN1 website`_. + +Hardware +******** + +The STM32L072CZ SoC provides the following hardware IPs: + +- Ultra-low-power (down to 0.29 µA Standby mode and 93 uA/MHz run mode) +- Core: ARM* 32-bit Cortex*-M0+ CPU, frequency up to 32 MHz +- Clock Sources: + + - 1 to 32 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 37 kHz RC ( |plusminus| 5%) + - Internal multispeed low-power 65 kHz to 4.2 MHz RC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 2x 16-bit with up to 4 channels + - 2x 16-bit with up to 2 channels + - 1x 16-bit ultra-low-power timer + - 1x SysTick + - 1x RTC + - 2x 16-bit basic for DAC + - 2x watchdogs (independent/window) +- Up to 84 fast I/Os, most 5 V-tolerant. +- Memories + + - Up to 192 KB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 20 KB of SRAM + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 1.14 MSPS + - 2x 12-bit DAC + - 2x ultra-low-power comparators +- 11x communication interfaces + + - USB 2.0 full-speed device, LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 6x SPIs (4x SPIs with the Quad SPI) +- 7-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L072CZ can be found here: + +- `STM32L072CZ on www.st.com`_ +- `STM32L0x2 reference manual`_ + +Supported Features +================== + +The Zephyr B-L072Z-LRWAN1 Discovery board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| TRNG | on-chip | true random number generator | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++-----------+------------+-------------------------------------+ +| LoRa | on-module | sx1276 | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig` + + +Connections and IOs +=================== + +B-L072Z-LRWAN1 Discovery kit has GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `B-L072Z-LRWAN1 website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX/RX: PA9/PA10 (Arduino Serial) +- UART_2_TX/RX: PA2/PA3 (ST-Link Virtual COM Port) +- SPI1 NSS/SCK/MISO/MOSI: PA15/PB3/PA6/PA7 (Semtech SX1276 LoRa* Transceiver) +- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 (Arduino SPI) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) + +System Clock +------------ + +B-L072Z-LRWAN1 Discovery board System Clock is at 32MHz. + +Serial Port +----------- + +B-L072Z-LRWAN1 Discovery board has 2 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +USB device +---------- + +B-L072Z-LRWAN1 Discovery board has 1 USB device controller. However, +the USB data lines are not connected to the MCU by default. To connect +the USB data lines to the MCU, short solder bridges SB15 and SB16. + +Programming and Debugging +************************* + +Applications for the ``b_l072z_lrwan1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +B-L072Z-LRWAN1 Discovery board includes an ST-LINK/V2-1 embedded debug +tool interface. This interface is supported by the openocd version included +in the Zephyr SDK since v0.9.2. + + +Flashing an application to B-L072Z-LRWAN1 Discovery board +--------------------------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the B-L072Z-LRWAN1 Discovery board to a STLinkV2 to your host computer using the USB port, then +run a serial host program to connect with your board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l072z_lrwan1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l072z_lrwan1 + :maybe-skip-config: + :goals: debug + +.. _B-L072Z-LRWAN1 website: + https://www.st.com/en/evaluation-tools/b-l072z-lrwan1.html + +.. _STM32L072CZ on www.st.com: + https://www.st.com/en/microcontrollers/stm32l072cz.html + +.. _STM32L0x2 reference manual: + https://www.st.com/resource/en/reference_manual/DM00108281.pdf diff --git a/boards/arm/b_l072z_lrwan1/support/openocd.cfg b/boards/st/b_l072z_lrwan1/support/openocd.cfg similarity index 100% rename from boards/arm/b_l072z_lrwan1/support/openocd.cfg rename to boards/st/b_l072z_lrwan1/support/openocd.cfg diff --git a/boards/st/b_l4s5i_iot01a/Kconfig.b_l4s5i_iot01a b/boards/st/b_l4s5i_iot01a/Kconfig.b_l4s5i_iot01a new file mode 100644 index 00000000000000..e4c8a21a27aee0 --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/Kconfig.b_l4s5i_iot01a @@ -0,0 +1,5 @@ +# Copyright (c) 2020 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_L4S5I_IOT01A + select SOC_STM32L4S5XX diff --git a/boards/st/b_l4s5i_iot01a/Kconfig.defconfig b/boards/st/b_l4s5i_iot01a/Kconfig.defconfig new file mode 100644 index 00000000000000..36b722dbf38199 --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/Kconfig.defconfig @@ -0,0 +1,44 @@ +# B_L4S5I_IOT01A discovery kit board configuration + +# Copyright (c) 2020 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_B_L4S5I_IOT01A + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +choice LIS3MDL_TRIGGER_MODE + default LIS3MDL_TRIGGER_NONE +endchoice + +choice HTS221_TRIGGER_MODE + default HTS221_TRIGGER_NONE +endchoice + +choice LSM6DSL_TRIGGER_MODE + default LSM6DSL_TRIGGER_GLOBAL_THREAD + depends on LSM6DSL +endchoice + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n +config BT_HCI_VS_EXT + default n + +endif # BT + +endif # BOARD_B_L4S5I_IOT01A diff --git a/boards/arm/b_l4s5i_iot01a/arduino_r3_connector.dtsi b/boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/b_l4s5i_iot01a/arduino_r3_connector.dtsi rename to boards/st/b_l4s5i_iot01a/arduino_r3_connector.dtsi diff --git a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.dts b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts similarity index 100% rename from boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.dts rename to boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts diff --git a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml similarity index 100% rename from boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml rename to boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml diff --git a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig similarity index 81% rename from boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig rename to boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig index 981dd5f1670d9d..9e3dfce576e064 100644 --- a/boards/arm/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig +++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4S5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/b_l4s5i_iot01a/board.cmake b/boards/st/b_l4s5i_iot01a/board.cmake similarity index 100% rename from boards/arm/b_l4s5i_iot01a/board.cmake rename to boards/st/b_l4s5i_iot01a/board.cmake diff --git a/boards/st/b_l4s5i_iot01a/board.yml b/boards/st/b_l4s5i_iot01a/board.yml new file mode 100644 index 00000000000000..e41cb4b1002397 --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/board.yml @@ -0,0 +1,5 @@ +board: + name: b_l4s5i_iot01a + vendor: st + socs: + - name: stm32l4s5xx diff --git a/boards/arm/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg b/boards/st/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg similarity index 100% rename from boards/arm/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg rename to boards/st/b_l4s5i_iot01a/doc/img/b-l4s5i_iot01a.jpg diff --git a/boards/st/b_l4s5i_iot01a/doc/index.rst b/boards/st/b_l4s5i_iot01a/doc/index.rst new file mode 100644 index 00000000000000..17455c772dd0a1 --- /dev/null +++ b/boards/st/b_l4s5i_iot01a/doc/index.rst @@ -0,0 +1,233 @@ +.. _b_l4s5i_iot01a_board: + +ST B_L4S5I_IOT01A Discovery kit +############################### + +Overview +******** + +The B_L4S5I_IOT01A Discovery kit features an ARM Cortex-M4 based STM32L4S5VI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the B_L4S5I_IOT01A Discovery kit: + + +- STM32L4S5VIT6 microcontroller featuring 2 Mbyte of Flash memory, 640 Kbytes of RAM in LQFP100 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Three different interfaces supported on USB: + + - Virtual com port + - Mass storage + - Debug port + +- ARDUINO ® Uno V3 and Pmod TM expansion connector +- 4 LEDs (2 for user, wifi, BLE) +- 2 push-buttons (user and reset) +- USB OTG FS with micro-AB connector +- Dynamic NFC tag +- 2 digital omnidirectional microphones +- Capacitive digital sensor for relative humidity and temperature +- Time-of-flight and gesture-detection sensors +- High-performance 3-axis magnetometer +- 3D accelerometer and 3D gyroscope +- 64-Mbit Quad-SPI Flash memory +- Bluetooth ® 4.1 module +- 802.11 b/g/n compliant Wi‐Fi ® module +- MCU current ammeter with 4 ranges and auto-calibration + +- Flexible power supply options: + - ST-LINK/V2-1 + - USB FS connector + - External 5 V + + +.. image:: img/b-l4s5i_iot01a.jpg + :align: center + :alt: B_L4S5I_IOT01A Discovery kit + +More information about the board can be found at the `B L4S5I IOT01A Discovery kit website`_. + +Hardware +******** + +The STM32L4S5VI SoC provides the following hardware features: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 120 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + - 2x 16-bit advanced control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 83 fast I/Os, most 5 V-tolerant +- Memories + - Up to 2 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 640 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Octo SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SDMMC I/F + - DCMI camera interface +- 14-channel DMA controller with multiplex request router +- True random number generator +- CRC calculation unit, 96-bit unique ID +- AES and HASH hardware accelerators +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L4S5VI can be found here: + - `STM32L4S5VI on www.st.com`_ + - `STM32L4S5 reference manual`_ + + +Supported Features +================== + +The Zephyr b_l4s5i_iot01a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| BLE | module | bluetooth | ++-----------+------------+-------------------------------------+ +| WIFI | module | es-wifi | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig` + + +Connections and IOs +=================== + +B_L4S5I_IOT01A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `B L47S5I IOT01A board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) +- UART_4 TX/RX : PA0/PA1 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) +- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) +- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) +- PWM_2_CH1 : PA15 +- LD1 : PA5 +- LD2 : PB14 +- user button : PC13 + +System Clock +------------ + +B_L4S5I_IOT01A Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +B_L4S5I_IOT01A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +B_L4S5I_IOT01A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to B_L4S5I_IOT01A Discovery kit +------------------------------------------------------- + +Connect the B_L4S5I_IOT01A Discovery kit to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l4s5i_iot01a + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_l4s5i_iot01a + :maybe-skip-config: + :goals: debug + +.. _B L4S5I IOT01A Discovery kit website: + https://www.st.com/en/evaluation-tools/b-l4s5i-iot01a.html + +.. _B L47S5I IOT01A board User Manual: + https://www.st.com/resource/en/user_manual/dm00698410.pdf + +.. _STM32L4S5VI on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l4s5vi.html + +.. _STM32L4S5 reference manual: + https://www.st.com/resource/en/reference_manual/dm00310109.pdf diff --git a/boards/arm/b_l4s5i_iot01a/support/openocd.cfg b/boards/st/b_l4s5i_iot01a/support/openocd.cfg similarity index 100% rename from boards/arm/b_l4s5i_iot01a/support/openocd.cfg rename to boards/st/b_l4s5i_iot01a/support/openocd.cfg diff --git a/boards/arm/b_u585i_iot02a/CMakeLists.txt b/boards/st/b_u585i_iot02a/CMakeLists.txt similarity index 100% rename from boards/arm/b_u585i_iot02a/CMakeLists.txt rename to boards/st/b_u585i_iot02a/CMakeLists.txt diff --git a/boards/st/b_u585i_iot02a/Kconfig.b_u585i_iot02a b/boards/st/b_u585i_iot02a/Kconfig.b_u585i_iot02a new file mode 100644 index 00000000000000..0b544f0ae53c19 --- /dev/null +++ b/boards/st/b_u585i_iot02a/Kconfig.b_u585i_iot02a @@ -0,0 +1,5 @@ +# Copyright (c) 2021 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_B_U585I_IOT02A + select SOC_STM32U585XX diff --git a/boards/st/b_u585i_iot02a/Kconfig.defconfig b/boards/st/b_u585i_iot02a/Kconfig.defconfig new file mode 100644 index 00000000000000..b8b6eeb4e2c595 --- /dev/null +++ b/boards/st/b_u585i_iot02a/Kconfig.defconfig @@ -0,0 +1,31 @@ +# B_U585I_IOT02A discovery kit board configuration + +# Copyright (c) 2021 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_B_U585I_IOT02A + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if BUILD_WITH_TFM + +# Initial Attestation key provisioned by the BL1 bootloader +config TFM_INITIAL_ATTESTATION_KEY + default y + +config TFM_DUMMY_PROVISIONING + default n + +endif # BUILD_WITH_TFM + +# Disable Flow control +if BT + +config BT_HCI_ACL_FLOW_CONTROL + default n + +endif # BT + +endif # BOARD_B_U585I_IOT02A diff --git a/boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi b/boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/b_u585i_iot02a/arduino_r3_connector.dtsi rename to boards/st/b_u585i_iot02a/arduino_r3_connector.dtsi diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi b/boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a-common.dtsi rename to boards/st/b_u585i_iot02a/b_u585i_iot02a-common.dtsi diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a.dts similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a.dts rename to boards/st/b_u585i_iot02a/b_u585i_iot02a.dts diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml b/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a.yaml rename to boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig b/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig similarity index 81% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig rename to boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig index c034f717771cdf..9e3dfce576e064 100644 --- a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_defconfig +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U585XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.dts b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts similarity index 100% rename from boards/arm/b_u585i_iot02a/b_u585i_iot02a_ns.dts rename to boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.dts diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml new file mode 100644 index 00000000000000..662c6f18848073 --- /dev/null +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml @@ -0,0 +1,11 @@ +identifier: b_u585i_iot02a/stm32u585xx/ns +name: ST B_U585I_IOT02A Discovery kit non secure target +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 786 +flash: 512 +vendor: st diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig new file mode 100644 index 00000000000000..2141cc748f8a11 --- /dev/null +++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns_defconfig @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y diff --git a/boards/arm/b_u585i_iot02a/board.cmake b/boards/st/b_u585i_iot02a/board.cmake similarity index 100% rename from boards/arm/b_u585i_iot02a/board.cmake rename to boards/st/b_u585i_iot02a/board.cmake diff --git a/boards/st/b_u585i_iot02a/board.yml b/boards/st/b_u585i_iot02a/board.yml new file mode 100644 index 00000000000000..55e740ec45d324 --- /dev/null +++ b/boards/st/b_u585i_iot02a/board.yml @@ -0,0 +1,7 @@ +board: + name: b_u585i_iot02a + vendor: st + socs: + - name: stm32u585xx + variants: + - name: ns diff --git a/boards/arm/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg b/boards/st/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg similarity index 100% rename from boards/arm/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg rename to boards/st/b_u585i_iot02a/doc/img/b-u585i-iot02a.jpg diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst new file mode 100644 index 00000000000000..2d9b782c90aaf9 --- /dev/null +++ b/boards/st/b_u585i_iot02a/doc/index.rst @@ -0,0 +1,438 @@ +.. _b_u585i_iot02a_board: + +ST B_U585I_IOT02A Discovery kit +############################### + +Overview +******** + +The B_U585I_IOT02A Discovery kit features an ARM Cortex-M33 based STM32U585AI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the B_U585I_IOT02A Discovery kit: + + +- STM32U585AII6Q microcontroller featuring 2 Mbyte of Flash memory, 786 Kbytes of RAM in UFBGA169 package +- 512-Mbit octal-SPI Flash memory, 64-Mbit octal-SPI PSRAM, 256-Kbit I2C EEPROM +- USB FS, Sink and Source power, 2.5 W power capability +- 802.11 b/g/n compliant Wi-Fi® module from MXCHIP +- Bluetooth Low Energy from STMicroelectronics +- MEMS sensors from STMicroelectronics + + - 2 digital microphones + - Relative humidity and temperature sensor + - 3-axis magnetometer + - 3D accelerometer and 3D gyroscope + - Pressure sensor, 260-1260 hPa absolute digital output barometer + - Time-of-flight and gesture-detection sensor + - Ambient-light sensor + +- 2 push-buttons (user and reset) +- 2 user LEDs + +- Flexible power supply options: + - ST-LINK/V3 + - USB Vbus + - External sources + + +.. image:: img/b-u585i-iot02a.jpg + :align: center + :alt: B_U585I_IOT02A Discovery kit + +More information about the board can be found at the `B U585I IOT02A Discovery kit website`_. + +Hardware +******** + +The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security and cryptography + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure data storage with hardware unique key (HUK) + - Secure Firmware Update support with TF-M + - 2 AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + - Active tampers + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- True Random Number Generator (RNG) + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + + + +More information about STM32U585AI can be found here: + +- `STM32U585 on www.st.com`_ +- `STM32U585 reference manual`_ + + +Supported Features +================== + +The Zephyr b_u585i_iot02a board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| RADIO | STM32WB5MMG| Bluetooth Low Energy (BLE) | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig` + +Zephyr board options +==================== + +The STM32U585i is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for both Secure and Non-Secure firmware. + +The BOARD options are summarized below: + ++-------------------------------+-------------------------------------------+ +| BOARD | Description | ++===============================+===========================================+ +| b_u585i_iot02a | For building Trust Zone Disabled firmware | ++-------------------------------+-------------------------------------------+ +| b_u585i_iot02a/stm32u585xx/ns | For building Non-Secure firmware | ++-------------------------------+-------------------------------------------+ + +Here are the instructions to build Zephyr with a non-secure configuration, +using `tfm_ipc_` sample: + + .. code-block:: bash + + $ west build -b b_u585i_iot02a/stm32u585xx/ns samples/tfm_integration/tfm_ipc/ + +Once done, before flashing, you need to first run a generated script that +will set platform option bytes config and erase platform (among others, +option bit TZEN will be set). + + .. code-block:: bash + + $ ./build/tfm/regression.sh + $ west flash + +Please note that, after having run a TFM sample on the board, you will need to +run `./build/tfm/regression.sh` once more to clean up the board from secure +options and get back the platform back to a "normal" state and be able to run +usual, non-TFM, binaries. +Also note that, even then, TZEN will remain set, and you will need to use +STM32CubeProgrammer_ to disable it fully, if required. + +Connections and IOs +=================== + +B_U585I_IOT02A Discovery kit has 9 GPIO controllers (from A to I). These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `B U585I IOT02A board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- LD1 : PH7 +- LD2 : PH6 +- user button : PC13 +- SPI1 NSS/SCK/MISO/MOSI : PE12/P13/P14/P15 (Arduino SPI) +- I2C_1 SDA/SDL : PB9/PB8 (Arduino I2C) +- I2C_2 SDA/SDL : PH5/PH4 +- DAC1 CH1 : PA4 (STMOD+1) +- ADC1_IN15 : PB0 +- USB OTG : PA11/PA12 +- PWM4 : CN14 PB6 +- PWM3 : CN4 PE4 + +System Clock +------------ + +B_U585I_IOT02A Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +B_U585I_IOT02A Discovery kit has 4 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB6`` jumper on the back side of the board. + + +Programming and Debugging +************************* + +B_U585I_IOT02A Discovery kit includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be +used to flash and debug the board if west is told to use it as runner, +using ``-r openocd``. + +Connect the B_U585I_IOT02A Discovery kit to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: b_u585i_iot02a + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: b_u585i_iot02a + :goals: debug + +Building a secure/non-secure with Arm |reg| TrustZone |reg| +=========================================================== + +The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| +support. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``b_u585i_iot02a/stm32u585xx/ns`` as build target. + +.. code-block:: bash + + $ west build -b b_u585i_iot02a/stm32u585xx/ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/api_ns/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash + + +Disabling TrustZone |reg| on the board +====================================== + +If you have flashed a sample to the board that enables TrustZone, you will need +to disable it before you can flash and run a new non-TrustZone sample on the +board. + +To disable TrustZone, it's necessary to change AT THE SAME TIME the ``TZEN`` +and ``RDP`` bits. ``TZEN`` needs to get set from 1 to 0 and ``RDP``, +needs to be set from ``DC`` to ``AA`` (step 3 below). + +This is docummented in the `AN5347, in section 9`_, "TrustZone deactivation". + +However, it's possible that the ``RDP`` bit is not yet set to ``DC``, so you +first need to set it to ``DC`` (step 2). + +Finally you need to set the "Write Protection 1 & 2" bytes properly, otherwise +some memory regions won't be erasable and mass erase will fail (step 4). + +The following command sequence will fully deactivate TZ: + +Step 1: + +Ensure U23 BOOT0 switch is set to 1 (switch is on the left, assuming you read +"BOOT0" silkscreen label from left to right). You need to press "Reset" (B2 RST +switch) after changing the switch to make the change effective. + +Step 2: + +.. code-block:: console + + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob rdp=0xDC + +Step 3: + +.. code-block:: console + + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -tzenreg + +Step 4: + +.. code-block:: console + + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1a_pend=0x0 + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp1b_pend=0x0 + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2a_pend=0x0 + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pstrt=0x7f + $ STM32_Programmer_CLI -c port=/dev/ttyACM0 -ob wrp2b_pend=0x0 + + +.. _B U585I IOT02A Discovery kit website: + https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html + +.. _B U585I IOT02A board User Manual: + https://www.st.com/resource/en/user_manual/um2839-discovery-kit-for-iot-node-with-stm32u5-series-stmicroelectronics.pdf + +.. _STM32U585 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html + +.. _STM32U585 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD + +.. _AN5347, in section 9: + https://www.st.com/resource/en/application_note/dm00625692-stm32l5-series-trustzone-features-stmicroelectronics.pdf diff --git a/boards/arm/b_u585i_iot02a/pre_dt_board.cmake b/boards/st/b_u585i_iot02a/pre_dt_board.cmake similarity index 100% rename from boards/arm/b_u585i_iot02a/pre_dt_board.cmake rename to boards/st/b_u585i_iot02a/pre_dt_board.cmake diff --git a/boards/arm/b_u585i_iot02a/support/openocd.cfg b/boards/st/b_u585i_iot02a/support/openocd.cfg similarity index 100% rename from boards/arm/b_u585i_iot02a/support/openocd.cfg rename to boards/st/b_u585i_iot02a/support/openocd.cfg diff --git a/boards/st/disco_l475_iot1/Kconfig.defconfig b/boards/st/disco_l475_iot1/Kconfig.defconfig new file mode 100644 index 00000000000000..5679d2caff840d --- /dev/null +++ b/boards/st/disco_l475_iot1/Kconfig.defconfig @@ -0,0 +1,44 @@ +# Discovery IoT L475 board configuration + +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_DISCO_L475_IOT1 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +choice LIS3MDL_TRIGGER_MODE + default LIS3MDL_TRIGGER_NONE +endchoice + +choice HTS221_TRIGGER_MODE + default HTS221_TRIGGER_NONE +endchoice + +choice LSM6DSL_TRIGGER_MODE + default LSM6DSL_TRIGGER_GLOBAL_THREAD + depends on LSM6DSL +endchoice + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n +config BT_HCI_VS_EXT + default n + +endif # BT + +endif # BOARD_DISCO_L475_IOT1 diff --git a/boards/st/disco_l475_iot1/Kconfig.disco_l475_iot1 b/boards/st/disco_l475_iot1/Kconfig.disco_l475_iot1 new file mode 100644 index 00000000000000..ee5352391883ac --- /dev/null +++ b/boards/st/disco_l475_iot1/Kconfig.disco_l475_iot1 @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_DISCO_L475_IOT1 + select SOC_STM32L475XX diff --git a/boards/arm/disco_l475_iot1/arduino_r3_connector.dtsi b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/disco_l475_iot1/arduino_r3_connector.dtsi rename to boards/st/disco_l475_iot1/arduino_r3_connector.dtsi diff --git a/boards/arm/disco_l475_iot1/board.cmake b/boards/st/disco_l475_iot1/board.cmake similarity index 100% rename from boards/arm/disco_l475_iot1/board.cmake rename to boards/st/disco_l475_iot1/board.cmake diff --git a/boards/st/disco_l475_iot1/board.yml b/boards/st/disco_l475_iot1/board.yml new file mode 100644 index 00000000000000..c11f22591a5690 --- /dev/null +++ b/boards/st/disco_l475_iot1/board.yml @@ -0,0 +1,5 @@ +board: + name: disco_l475_iot1 + vendor: st + socs: + - name: stm32l475xx diff --git a/boards/arm/disco_l475_iot1/disco_l475_iot1.dts b/boards/st/disco_l475_iot1/disco_l475_iot1.dts similarity index 100% rename from boards/arm/disco_l475_iot1/disco_l475_iot1.dts rename to boards/st/disco_l475_iot1/disco_l475_iot1.dts diff --git a/boards/arm/disco_l475_iot1/disco_l475_iot1.yaml b/boards/st/disco_l475_iot1/disco_l475_iot1.yaml similarity index 100% rename from boards/arm/disco_l475_iot1/disco_l475_iot1.yaml rename to boards/st/disco_l475_iot1/disco_l475_iot1.yaml diff --git a/boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig b/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig similarity index 80% rename from boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig rename to boards/st/disco_l475_iot1/disco_l475_iot1_defconfig index a25b1eff6458ed..2ff706148f2956 100644 --- a/boards/arm/disco_l475_iot1/disco_l475_iot1_defconfig +++ b/boards/st/disco_l475_iot1/disco_l475_iot1_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_BOARD_DISCO_L475_IOT1=y -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L475XX=y - # enable uart driver CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg b/boards/st/disco_l475_iot1/doc/img/disco_l475_iot1.jpg similarity index 100% rename from boards/arm/disco_l475_iot1/doc/img/disco_l475_iot1.jpg rename to boards/st/disco_l475_iot1/doc/img/disco_l475_iot1.jpg diff --git a/boards/st/disco_l475_iot1/doc/index.rst b/boards/st/disco_l475_iot1/doc/index.rst new file mode 100644 index 00000000000000..dc49d4fcb2d68a --- /dev/null +++ b/boards/st/disco_l475_iot1/doc/index.rst @@ -0,0 +1,248 @@ +.. _disco_l475_iot1_board: + +ST Disco L475 IOT01 (B-L475E-IOT01A) +#################################### + +Overview +******** + +The B-L475E-IOT01A Discovery kit for IoT node allows users to develop +applications with direct connection to cloud servers. +The Discovery kit enables a wide diversity of applications by exploiting +low-power communication, multiway sensing and ARM |reg| Cortex |reg|-M4 core-based +STM32L4 Series features. + +This kit provides: + +- 64-Mbit Quad-SPI (Macronix) Flash memory +- Bluetooth |reg| V4.1 module (SPBTLE-RF) +- Sub-GHz (868 or 915 MHz) low-power-programmable RF module (SPSGRF-868 or SPSGRF-915) +- Wi-Fi |reg| module Inventek ISM43362-M3G-L44 (802.11 b/g/n compliant) +- Dynamic NFC tag based on M24SR with its printed NFC antenna +- 2 digital omni-directional microphones (MP34DT01) +- Capacitive digital sensor for relative humidity and temperature (HTS221) +- High-performance 3-axis magnetometer (LIS3MDL) +- 3D accelerometer and 3D gyroscope (LSM6DSL) +- 260-1260 hPa absolute digital output barometer (LPS22HB) +- Time-of-Flight and gesture-detection sensor (VL53L0X) +- 2 push-buttons (user and reset) +- USB OTG FS with Micro-AB connector +- Expansion connectors: + - Arduino |trade| Uno V3 + - PMOD +- Flexible power-supply options: + - ST LINK USB VBUS or external sources +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration capability: + - mass storage, virtual COM port and debug port + + +.. image:: img/disco_l475_iot1.jpg + :align: center + :alt: Disco L475 IoT1 + +More information about the board can be found at the `Disco L475 IoT1 website`_. + +Hardware +******** + +The STM32L475VG SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 120 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L475VG can be found here: + - `STM32L475VG on www.st.com`_ + - `STM32L475 reference manual`_ + +Supported Features +================== + +The Zephyr Disco L475 IoT board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/disco_l475_iot1/disco_l475_iot1_defconfig` + + +Connections and IOs +=================== + +Disco L475 IoT Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- + +For detailed information about available pins please refer to `STM32 Disco L475 IoT1 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 (ST-Link Virtual Port Com) +- UART_4 TX/RX : PA0/PA1 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 (Sensor I2C bus) +- I2C3 SCL/SDA : PC0/PC1 +- SPI1 NSS/SCK/MISO/MOSI : PA2/PA5/PA6/PA7 (Arduino SPI) +- SPI3 SCK/MISO/MOSI : PC10/PC11/PC12 (BT SPI bus) +- PWM_2_CH1 : PA15 +- USER_PB : PC13 +- LD2 : PA5 +- ADC12_IN5 : PA0 +- ADC123_IN3 : PC2 +- ADC123_IN4 : PC3 +- ADC12_IN13 : PC4 +- ADC12_IN14 : PC5 +- DAC1_OUT1 : PA4 + +System Clock +------------ + +Disco L475 IoT System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Disco L475 IoT board has 6 U(S)ARTs. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``disco_l475_iot1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Disco L475 IoT +----------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Connect the Disco L475 IoT to your host computer using the USB port, then +run a serial host program to connect with your Nucleo board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: disco_l475_iot1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: disco_l475_iot1 + :maybe-skip-config: + :goals: debug + +.. _Disco L475 IoT1 website: + https://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-discovery-kits/b-l475e-iot01a.html + +.. _STM32 Disco L475 IoT1 board User Manual: + https://www.st.com/resource/en/user_manual/dm00347848.pdf + +.. _STM32L475VG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l475vg.html + +.. _STM32L475 reference manual: + https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/disco_l475_iot1/support/openocd.cfg b/boards/st/disco_l475_iot1/support/openocd.cfg similarity index 100% rename from boards/arm/disco_l475_iot1/support/openocd.cfg rename to boards/st/disco_l475_iot1/support/openocd.cfg diff --git a/boards/st/index.rst b/boards/st/index.rst new file mode 100644 index 00000000000000..3cc804c72a8681 --- /dev/null +++ b/boards/st/index.rst @@ -0,0 +1,10 @@ +.. _boards-st: + +STMicroelectronics +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/st/nucleo_c031c6/Kconfig.nucleo_c031c6 b/boards/st/nucleo_c031c6/Kconfig.nucleo_c031c6 new file mode 100644 index 00000000000000..839f9916405a14 --- /dev/null +++ b/boards/st/nucleo_c031c6/Kconfig.nucleo_c031c6 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_C031C6 + select SOC_STM32C031XX diff --git a/boards/arm/nucleo_c031c6/arduino_r3_connector.dtsi b/boards/st/nucleo_c031c6/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_c031c6/arduino_r3_connector.dtsi rename to boards/st/nucleo_c031c6/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_c031c6/board.cmake b/boards/st/nucleo_c031c6/board.cmake similarity index 100% rename from boards/arm/nucleo_c031c6/board.cmake rename to boards/st/nucleo_c031c6/board.cmake diff --git a/boards/st/nucleo_c031c6/board.yml b/boards/st/nucleo_c031c6/board.yml new file mode 100644 index 00000000000000..37d48de4d52d55 --- /dev/null +++ b/boards/st/nucleo_c031c6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_c031c6 + vendor: st + socs: + - name: stm32c031xx diff --git a/boards/arm/nucleo_c031c6/doc/img/nucleo_c031c6.jpg b/boards/st/nucleo_c031c6/doc/img/nucleo_c031c6.jpg similarity index 100% rename from boards/arm/nucleo_c031c6/doc/img/nucleo_c031c6.jpg rename to boards/st/nucleo_c031c6/doc/img/nucleo_c031c6.jpg diff --git a/boards/st/nucleo_c031c6/doc/index.rst b/boards/st/nucleo_c031c6/doc/index.rst new file mode 100644 index 00000000000000..8ed5a7edfeae32 --- /dev/null +++ b/boards/st/nucleo_c031c6/doc/index.rst @@ -0,0 +1,151 @@ +.. _nucleo_c031c6_board: + +ST Nucleo C031C6 +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32C031C6 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_c031c6.jpg + :align: center + :alt: Nucleo C031C6 + +More information about the board can be found at the `Nucleo C031C6 website`_. + +Hardware +******** +Nucleo C031C6 provides the following hardware components: + +- STM32 microcontroller in 48-pin package featuring 32 Kbytes of Flash memory + and 12 Kbytes of SRAM. +- Extension resource: + + - Arduino* Uno V3 connectivity + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Current consumption measurement (IDD) + +- Four LEDs: + + - USB communication (LD1), USB power fault LED (LD2), power LED (LD3), + user LED (LD4) + +- Two push-button: USER and RESET + +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32C031C6 can be found here: +`STM32C0x1 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_c031c6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| IWDG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| WWDG | on-chip | window watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_c031c6/nucleo_c031c6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- LD4 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_c031c6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo C031C6 board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo C031C6 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_c031c6 + :goals: build flash + +You will see the LED blinking every second. + +References +********** + +.. target-notes:: + +.. _Nucleo C031C6 website: + https://www.st.com/en/evaluation-tools/nucleo-c031c6.html + +.. _STM32C0x1 reference manual: + https://www.st.com/resource/en/reference_manual/rm0490-stm32c0x1-advanced-armbased-64bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/um2953-stm32c0-nucleo64-board-mb1717-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_c031c6/nucleo_c031c6.dts b/boards/st/nucleo_c031c6/nucleo_c031c6.dts similarity index 100% rename from boards/arm/nucleo_c031c6/nucleo_c031c6.dts rename to boards/st/nucleo_c031c6/nucleo_c031c6.dts diff --git a/boards/arm/nucleo_c031c6/nucleo_c031c6.yaml b/boards/st/nucleo_c031c6/nucleo_c031c6.yaml similarity index 100% rename from boards/arm/nucleo_c031c6/nucleo_c031c6.yaml rename to boards/st/nucleo_c031c6/nucleo_c031c6.yaml diff --git a/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig b/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig new file mode 100644 index 00000000000000..1a570d28d13212 --- /dev/null +++ b/boards/st/nucleo_c031c6/nucleo_c031c6_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/st/nucleo_f030r8/Kconfig.nucleo_f030r8 b/boards/st/nucleo_f030r8/Kconfig.nucleo_f030r8 new file mode 100644 index 00000000000000..039a9e00c6ce25 --- /dev/null +++ b/boards/st/nucleo_f030r8/Kconfig.nucleo_f030r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F030R8 + select SOC_STM32F030X8 diff --git a/boards/arm/nucleo_f030r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f030r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f030r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_f030r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f030r8/board.cmake b/boards/st/nucleo_f030r8/board.cmake similarity index 100% rename from boards/arm/nucleo_f030r8/board.cmake rename to boards/st/nucleo_f030r8/board.cmake diff --git a/boards/st/nucleo_f030r8/board.yml b/boards/st/nucleo_f030r8/board.yml new file mode 100644 index 00000000000000..515aae8c5b09d6 --- /dev/null +++ b/boards/st/nucleo_f030r8/board.yml @@ -0,0 +1,11 @@ +board: + name: nucleo_f030r8 + vendor: st + revision: + format: number + default: "1" + revisions: + - name: "1" + - name: "2" + socs: + - name: stm32f030x8 diff --git a/boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8.jpg b/boards/st/nucleo_f030r8/doc/img/nucleo_f030r8.jpg similarity index 100% rename from boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8.jpg rename to boards/st/nucleo_f030r8/doc/img/nucleo_f030r8.jpg diff --git a/boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg b/boards/st/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg rename to boards/st/nucleo_f030r8/doc/img/nucleo_f030r8_connectors.jpg diff --git a/boards/st/nucleo_f030r8/doc/index.rst b/boards/st/nucleo_f030r8/doc/index.rst new file mode 100644 index 00000000000000..a7479859d099c2 --- /dev/null +++ b/boards/st/nucleo_f030r8/doc/index.rst @@ -0,0 +1,217 @@ +.. _nucleo_f030r8_board: + +ST Nucleo F030R8 +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F030R8 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f030r8.jpg + :align: center + :alt: Nucleo F030R8 + +More information about the board can be found at the `Nucleo F030R8 website`_. + +Hardware +******** +Nucleo F030R8 provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F030R8 can be found here: + +- `STM32F030 reference manual`_ +- `STM32F030 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f030r8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f030r8/nucleo_f030r8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f030r8_connectors.jpg + :align: center + :alt: Nucleo F030R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 +- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD1 : PA5 +- ADC : PA0 + + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f030r8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. _nucleo-f030r8-flashing: + +Flashing +======== + +Nucleo F030R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F030R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8 + :goals: build flash + +You will see the LED blinking every second. + +If using the C-01 board, select revision '1' that supports the board. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8@1 + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8 + :maybe-skip-config: + :goals: debug + +Again you have to use the adapted command for C-01. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f030r8@1 + :maybe-skip-config: + :goals: debug + +Board Revisions +*************** + +Nucleo F030R8 has some version of board variants. +`STM32 Nucleo-64 board User Manual`_ mentions to Nucleo board variants. + + | *The board version MB1136 C-01 or MB1136 C-02 is mentioned on the sticker, placed on the bottom side of the PCB.* + | *The board marking MB1136 C-01 corresponds to a board, configured as HSE not used.* + | *The board marking MB1136 C-02 (or higher) corresponds to a board, configured to use ST-LINK MCO as the clock input.* + +Using revision **2** adapted for C-02(or higher) as default when not explicitly selecting revisions. +If using the C-01 board, select revision **1**. +Please see :ref:`Flashing ` section. + +References +********** + +.. target-notes:: + +.. _Nucleo F030R8 website: + https://www.st.com/en/evaluation-tools/nucleo-f030r8.html + +.. _STM32F030 reference manual: + https://www.st.com/resource/en/reference_manual/dm00091010.pdf + +.. _STM32F030 data sheet: + https://www.st.com/resource/en/datasheet/stm32f030r8.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8.dts b/boards/st/nucleo_f030r8/nucleo_f030r8.dts similarity index 100% rename from boards/arm/nucleo_f030r8/nucleo_f030r8.dts rename to boards/st/nucleo_f030r8/nucleo_f030r8.dts diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8.yaml b/boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml similarity index 100% rename from boards/arm/nucleo_f030r8/nucleo_f030r8.yaml rename to boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml diff --git a/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml b/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml new file mode 100644 index 00000000000000..194e1b451993b6 --- /dev/null +++ b/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml @@ -0,0 +1,24 @@ +identifier: nucleo_f030r8@2 +name: ST Nucleo F030R8 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 8 +flash: 64 +supported: + - arduino_gpio + - arduino_i2c + - arduino_spi + - i2c + - spi + - gpio + - watchdog + - adc +testing: + ignore_tags: + - net + - bluetooth +vendor: st diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig b/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig similarity index 80% rename from boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig rename to boards/st/nucleo_f030r8/nucleo_f030r8_defconfig index 1ba94fff95d8ef..18ac599df259a0 100644 --- a/boards/arm/nucleo_f030r8/nucleo_f030r8_defconfig +++ b/boards/st/nucleo_f030r8/nucleo_f030r8_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F030X8=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/nucleo_f030r8/nucleo_f030r8_1.overlay b/boards/st/nucleo_f030r8/nucleo_f030r8_stm32f030x8_1.overlay similarity index 100% rename from boards/arm/nucleo_f030r8/nucleo_f030r8_1.overlay rename to boards/st/nucleo_f030r8/nucleo_f030r8_stm32f030x8_1.overlay diff --git a/boards/arm/nucleo_f030r8/st_morpho_connector.dtsi b/boards/st/nucleo_f030r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f030r8/st_morpho_connector.dtsi rename to boards/st/nucleo_f030r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f030r8/support/openocd.cfg b/boards/st/nucleo_f030r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f030r8/support/openocd.cfg rename to boards/st/nucleo_f030r8/support/openocd.cfg diff --git a/boards/st/nucleo_f031k6/Kconfig.nucleo_f031k6 b/boards/st/nucleo_f031k6/Kconfig.nucleo_f031k6 new file mode 100644 index 00000000000000..2e1f222fb0e20e --- /dev/null +++ b/boards/st/nucleo_f031k6/Kconfig.nucleo_f031k6 @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Sebastian Schwabe +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F031K6 + select SOC_STM32F031X6 diff --git a/boards/arm/nucleo_f031k6/board.cmake b/boards/st/nucleo_f031k6/board.cmake similarity index 100% rename from boards/arm/nucleo_f031k6/board.cmake rename to boards/st/nucleo_f031k6/board.cmake diff --git a/boards/st/nucleo_f031k6/board.yml b/boards/st/nucleo_f031k6/board.yml new file mode 100644 index 00000000000000..01fc79ac03391a --- /dev/null +++ b/boards/st/nucleo_f031k6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f031k6 + vendor: st + socs: + - name: stm32f031x6 diff --git a/boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6.jpg b/boards/st/nucleo_f031k6/doc/img/nucleo_f031k6.jpg similarity index 100% rename from boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6.jpg rename to boards/st/nucleo_f031k6/doc/img/nucleo_f031k6.jpg diff --git a/boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg b/boards/st/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg rename to boards/st/nucleo_f031k6/doc/img/nucleo_f031k6_connectors.jpg diff --git a/boards/st/nucleo_f031k6/doc/index.rst b/boards/st/nucleo_f031k6/doc/index.rst new file mode 100644 index 00000000000000..99ae997ce26c49 --- /dev/null +++ b/boards/st/nucleo_f031k6/doc/index.rst @@ -0,0 +1,155 @@ +.. _nucleo_f031k6_board: + +ST Nucleo F031K6 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32F031K6 MCU, supports Arduino nano connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f031k6.jpg + :align: center + :alt: Nucleo F031k6 + +More information about the board can be found at the `Nucleo F031K6 website`_. + +Hardware +******** +Nucleo F031K6 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- reset push button + +More information about STM32F031K6 can be found here: + +- `STM32F031 reference manual`_ +- `STM32F031 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f031k6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f031k6/nucleo_f031k6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. + +Board connectors: +----------------- +.. image:: img/nucleo_f031k6_connectors.jpg + :align: center + :alt: Nucleo F031K6 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f031k6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F030R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f031k6 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f031k6 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F031K6 website: + https://www.st.com/en/evaluation-tools/nucleo-f031k6.html + +.. _STM32F031 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32F031 data sheet: + https://www.st.com/resource/en/datasheet/stm32f031k6.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f031k6/nucleo_f031k6.dts b/boards/st/nucleo_f031k6/nucleo_f031k6.dts similarity index 100% rename from boards/arm/nucleo_f031k6/nucleo_f031k6.dts rename to boards/st/nucleo_f031k6/nucleo_f031k6.dts diff --git a/boards/arm/nucleo_f031k6/nucleo_f031k6.yaml b/boards/st/nucleo_f031k6/nucleo_f031k6.yaml similarity index 100% rename from boards/arm/nucleo_f031k6/nucleo_f031k6.yaml rename to boards/st/nucleo_f031k6/nucleo_f031k6.yaml diff --git a/boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig b/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig similarity index 86% rename from boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig rename to boards/st/nucleo_f031k6/nucleo_f031k6_defconfig index 87cb9a8114885e..62817c1ba47226 100644 --- a/boards/arm/nucleo_f031k6/nucleo_f031k6_defconfig +++ b/boards/st/nucleo_f031k6/nucleo_f031k6_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Platform Configuration -CONFIG_SOC_SERIES_STM32F0X=y -CONFIG_SOC_STM32F031X6=y # Kernel Options due to Low Memory (4k) CONFIG_MAIN_STACK_SIZE=512 diff --git a/boards/arm/nucleo_f031k6/support/openocd.cfg b/boards/st/nucleo_f031k6/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f031k6/support/openocd.cfg rename to boards/st/nucleo_f031k6/support/openocd.cfg diff --git a/boards/st/nucleo_f042k6/Kconfig.nucleo_f042k6 b/boards/st/nucleo_f042k6/Kconfig.nucleo_f042k6 new file mode 100644 index 00000000000000..ed5b7b1c303753 --- /dev/null +++ b/boards/st/nucleo_f042k6/Kconfig.nucleo_f042k6 @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F042K6 + select SOC_STM32F042X6 diff --git a/boards/arm/nucleo_f042k6/board.cmake b/boards/st/nucleo_f042k6/board.cmake similarity index 100% rename from boards/arm/nucleo_f042k6/board.cmake rename to boards/st/nucleo_f042k6/board.cmake diff --git a/boards/st/nucleo_f042k6/board.yml b/boards/st/nucleo_f042k6/board.yml new file mode 100644 index 00000000000000..89d8b050428195 --- /dev/null +++ b/boards/st/nucleo_f042k6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f042k6 + vendor: st + socs: + - name: stm32f042x6 diff --git a/boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6.jpg b/boards/st/nucleo_f042k6/doc/img/nucleo_f042k6.jpg similarity index 100% rename from boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6.jpg rename to boards/st/nucleo_f042k6/doc/img/nucleo_f042k6.jpg diff --git a/boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg b/boards/st/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg rename to boards/st/nucleo_f042k6/doc/img/nucleo_f042k6_connectors.jpg diff --git a/boards/st/nucleo_f042k6/doc/index.rst b/boards/st/nucleo_f042k6/doc/index.rst new file mode 100644 index 00000000000000..a1d90c8c4f3522 --- /dev/null +++ b/boards/st/nucleo_f042k6/doc/index.rst @@ -0,0 +1,155 @@ +.. _nucleo_f042k6_board: + +ST Nucleo F042K6 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32F042K6 MCU, supports Arduino nano connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f042k6.jpg + :align: center + :alt: Nucleo F042k6 + +More information about the board can be found at the `Nucleo F042K6 website`_. + +Hardware +******** +Nucleo F042K6 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- reset push button + +More information about STM32F042K6 can be found here: + +- `STM32F042 reference manual`_ +- `STM32F042 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f042k6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f042k6/nucleo_f042k6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. + +Board connectors: +----------------- +.. image:: img/nucleo_f042k6_connectors.jpg + :align: center + :alt: Nucleo F042K6 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA2/PA15 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB6/PB7 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f042k6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F042K6 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F042K6 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f042k6 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f042k6 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F042K6 website: + https://www.st.com/en/evaluation-tools/nucleo-f042k6.html + +.. _STM32F042 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1stm32f0x2stm32f0x8-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32F042 data sheet: + https://www.st.com/resource/en/datasheet/stm32f042k6.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_f042k6/nucleo_f042k6.dts b/boards/st/nucleo_f042k6/nucleo_f042k6.dts similarity index 100% rename from boards/arm/nucleo_f042k6/nucleo_f042k6.dts rename to boards/st/nucleo_f042k6/nucleo_f042k6.dts diff --git a/boards/arm/nucleo_f042k6/nucleo_f042k6.yaml b/boards/st/nucleo_f042k6/nucleo_f042k6.yaml similarity index 100% rename from boards/arm/nucleo_f042k6/nucleo_f042k6.yaml rename to boards/st/nucleo_f042k6/nucleo_f042k6.yaml diff --git a/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig b/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig new file mode 100644 index 00000000000000..06e8a32bb1f031 --- /dev/null +++ b/boards/st/nucleo_f042k6/nucleo_f042k6_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f042k6/support/openocd.cfg b/boards/st/nucleo_f042k6/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f042k6/support/openocd.cfg rename to boards/st/nucleo_f042k6/support/openocd.cfg diff --git a/boards/st/nucleo_f070rb/Kconfig.defconfig b/boards/st/nucleo_f070rb/Kconfig.defconfig new file mode 100644 index 00000000000000..49649c776a90e4 --- /dev/null +++ b/boards/st/nucleo_f070rb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# NUCLEO_F070RB board configuration + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F070RB + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F070RB diff --git a/boards/st/nucleo_f070rb/Kconfig.nucleo_f070rb b/boards/st/nucleo_f070rb/Kconfig.nucleo_f070rb new file mode 100644 index 00000000000000..0ebe4a837ba027 --- /dev/null +++ b/boards/st/nucleo_f070rb/Kconfig.nucleo_f070rb @@ -0,0 +1,5 @@ +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F070RB + select SOC_STM32F070XB diff --git a/boards/arm/nucleo_f070rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f070rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f070rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_f070rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f070rb/board.cmake b/boards/st/nucleo_f070rb/board.cmake similarity index 100% rename from boards/arm/nucleo_f070rb/board.cmake rename to boards/st/nucleo_f070rb/board.cmake diff --git a/boards/st/nucleo_f070rb/board.yml b/boards/st/nucleo_f070rb/board.yml new file mode 100644 index 00000000000000..8f3a6a49878032 --- /dev/null +++ b/boards/st/nucleo_f070rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f070rb + vendor: st + socs: + - name: stm32f070xb diff --git a/boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb.jpg b/boards/st/nucleo_f070rb/doc/img/nucleo_f070rb.jpg similarity index 100% rename from boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb.jpg rename to boards/st/nucleo_f070rb/doc/img/nucleo_f070rb.jpg diff --git a/boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg b/boards/st/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg rename to boards/st/nucleo_f070rb/doc/img/nucleo_f070rb_connectors.jpg diff --git a/boards/st/nucleo_f070rb/doc/index.rst b/boards/st/nucleo_f070rb/doc/index.rst new file mode 100644 index 00000000000000..5e6544e9cfb768 --- /dev/null +++ b/boards/st/nucleo_f070rb/doc/index.rst @@ -0,0 +1,180 @@ +.. _nucleo_f070rb_board: + +ST Nucleo F070RB +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F070RB MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f070rb.jpg + :align: center + :alt: Nucleo F070RB + +More information about the board can be found at the `Nucleo F070RB website`_. + +Hardware +******** +Nucleo F070RB provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F070RB can be found in +the `STM32F070 reference manual`_ . + + +Supported Features +================== + +The Zephyr nucleo_f070rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | SPI controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f070rb/nucleo_f070rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f070rb_connectors.jpg + :align: center + :alt: Nucleo F070RB connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB11 +- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 +- USER_PB : PC13 +- LD1 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f070rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F070RB board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F070RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f070rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f070rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F070RB website: + https://www.st.com/en/evaluation-tools/nucleo-f070rb.html + +.. _STM32F070 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb.dts b/boards/st/nucleo_f070rb/nucleo_f070rb.dts similarity index 100% rename from boards/arm/nucleo_f070rb/nucleo_f070rb.dts rename to boards/st/nucleo_f070rb/nucleo_f070rb.dts diff --git a/boards/arm/nucleo_f070rb/nucleo_f070rb.yaml b/boards/st/nucleo_f070rb/nucleo_f070rb.yaml similarity index 100% rename from boards/arm/nucleo_f070rb/nucleo_f070rb.yaml rename to boards/st/nucleo_f070rb/nucleo_f070rb.yaml diff --git a/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig b/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig new file mode 100644 index 00000000000000..bee511a28092a8 --- /dev/null +++ b/boards/st/nucleo_f070rb/nucleo_f070rb_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f070rb/st_morpho_connector.dtsi b/boards/st/nucleo_f070rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f070rb/st_morpho_connector.dtsi rename to boards/st/nucleo_f070rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f070rb/support/openocd.cfg b/boards/st/nucleo_f070rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f070rb/support/openocd.cfg rename to boards/st/nucleo_f070rb/support/openocd.cfg diff --git a/boards/st/nucleo_f091rc/Kconfig.defconfig b/boards/st/nucleo_f091rc/Kconfig.defconfig new file mode 100644 index 00000000000000..81a59cb529dbb7 --- /dev/null +++ b/boards/st/nucleo_f091rc/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32F091RC MCU + +# Copyright (c) 2017 Bobby Noelte +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F091RC + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F091RC diff --git a/boards/st/nucleo_f091rc/Kconfig.nucleo_f091rc b/boards/st/nucleo_f091rc/Kconfig.nucleo_f091rc new file mode 100644 index 00000000000000..8bb34456d832f1 --- /dev/null +++ b/boards/st/nucleo_f091rc/Kconfig.nucleo_f091rc @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Bobby Noelte +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F091RC + select SOC_STM32F091XC diff --git a/boards/arm/nucleo_f091rc/arduino_r3_connector.dtsi b/boards/st/nucleo_f091rc/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f091rc/arduino_r3_connector.dtsi rename to boards/st/nucleo_f091rc/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f091rc/board.cmake b/boards/st/nucleo_f091rc/board.cmake similarity index 100% rename from boards/arm/nucleo_f091rc/board.cmake rename to boards/st/nucleo_f091rc/board.cmake diff --git a/boards/st/nucleo_f091rc/board.yml b/boards/st/nucleo_f091rc/board.yml new file mode 100644 index 00000000000000..9f3fe67f8f69e6 --- /dev/null +++ b/boards/st/nucleo_f091rc/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f091rc + vendor: st + socs: + - name: stm32f091xc diff --git a/boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc.jpg b/boards/st/nucleo_f091rc/doc/img/nucleo_f091rc.jpg similarity index 100% rename from boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc.jpg rename to boards/st/nucleo_f091rc/doc/img/nucleo_f091rc.jpg diff --git a/boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg b/boards/st/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg rename to boards/st/nucleo_f091rc/doc/img/nucleo_f091rc_connectors.jpg diff --git a/boards/st/nucleo_f091rc/doc/index.rst b/boards/st/nucleo_f091rc/doc/index.rst new file mode 100644 index 00000000000000..eee47f79254e14 --- /dev/null +++ b/boards/st/nucleo_f091rc/doc/index.rst @@ -0,0 +1,197 @@ +.. _nucleo_f091rc_board: + +ST Nucleo F091RC +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F091RC MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f091rc.jpg + :align: center + :alt: Nucleo F091RC + +More information about the board can be found at the `Nucleo F091RC website`_. + +Hardware +******** +Nucleo F091RC provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F091RC can be found in the +`STM32F091 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_f091rc board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | SPI controller | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f091rc/nucleo_f091rc_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f091rc_connectors.jpg + :align: center + :alt: Nucleo F091RC connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 (disabled by default, uses same pins as CAN) +- CAN RX/TX : PA11/PA12 +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15 +- USER_PB : PC13 +- LD2 : PA5 +- DAC_OUT1 : PA4 +- PWM_2_CH1 : PA5 (might conflict with SPI1) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f091rc`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F091RC +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f091rc + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f091rc + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F091RC website: + https://www.st.com/en/evaluation-tools/nucleo-f091rc.html + +.. _STM32F091 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.dts b/boards/st/nucleo_f091rc/nucleo_f091rc.dts similarity index 100% rename from boards/arm/nucleo_f091rc/nucleo_f091rc.dts rename to boards/st/nucleo_f091rc/nucleo_f091rc.dts diff --git a/boards/arm/nucleo_f091rc/nucleo_f091rc.yaml b/boards/st/nucleo_f091rc/nucleo_f091rc.yaml similarity index 100% rename from boards/arm/nucleo_f091rc/nucleo_f091rc.yaml rename to boards/st/nucleo_f091rc/nucleo_f091rc.yaml diff --git a/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig b/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig new file mode 100644 index 00000000000000..06e8a32bb1f031 --- /dev/null +++ b/boards/st/nucleo_f091rc/nucleo_f091rc_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f091rc/st_morpho_connector.dtsi b/boards/st/nucleo_f091rc/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f091rc/st_morpho_connector.dtsi rename to boards/st/nucleo_f091rc/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f091rc/support/openocd.cfg b/boards/st/nucleo_f091rc/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f091rc/support/openocd.cfg rename to boards/st/nucleo_f091rc/support/openocd.cfg diff --git a/boards/st/nucleo_f103rb/Kconfig.nucleo_f103rb b/boards/st/nucleo_f103rb/Kconfig.nucleo_f103rb new file mode 100644 index 00000000000000..08cdc321800cf9 --- /dev/null +++ b/boards/st/nucleo_f103rb/Kconfig.nucleo_f103rb @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F103RB + select SOC_STM32F103XB diff --git a/boards/arm/nucleo_f103rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f103rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f103rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_f103rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f103rb/board.cmake b/boards/st/nucleo_f103rb/board.cmake similarity index 100% rename from boards/arm/nucleo_f103rb/board.cmake rename to boards/st/nucleo_f103rb/board.cmake diff --git a/boards/st/nucleo_f103rb/board.yml b/boards/st/nucleo_f103rb/board.yml new file mode 100644 index 00000000000000..57425f7832d689 --- /dev/null +++ b/boards/st/nucleo_f103rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f103rb + vendor: st + socs: + - name: stm32f103xb diff --git a/boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb.jpg b/boards/st/nucleo_f103rb/doc/img/nucleo_f103rb.jpg similarity index 100% rename from boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb.jpg rename to boards/st/nucleo_f103rb/doc/img/nucleo_f103rb.jpg diff --git a/boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg b/boards/st/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg rename to boards/st/nucleo_f103rb/doc/img/nucleo_f103rb_connectors.jpg diff --git a/boards/st/nucleo_f103rb/doc/index.rst b/boards/st/nucleo_f103rb/doc/index.rst new file mode 100644 index 00000000000000..0ff1a60ef85f11 --- /dev/null +++ b/boards/st/nucleo_f103rb/doc/index.rst @@ -0,0 +1,190 @@ +.. _nucleo_f103rb_board: + +ST Nucleo F103RB +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32F103RB MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f103rb.jpg + :align: center + :alt: Nucleo F103RB + +More information about the board can be found at the `Nucleo F103RB website`_. + +Hardware +******** +Nucleo F103RB provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F103RB can be found here: + +- `STM32F103 reference manual`_ +- `STM32F103 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_f103rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f103rb/nucleo_f103rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f103rb_connectors.jpg + :align: center + :alt: Nucleo F103RB connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI2 SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- I2C1 SDA/SCL: PB9/PB8 (Arduino I2C) +- PWM1_CH1: PA8 +- USER_PB : PC13 +- LD1 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f103rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F103RB board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F103RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f103rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f103rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F103RB website: + https://www.st.com/en/evaluation-tools/nucleo-f103rb.html + +.. _STM32F103 reference manual: + https://www.st.com/resource/en/reference_manual/cd00171190.pdf + +.. _STM32F103 data sheet: + https://www.st.com/resource/en/datasheet/stm32f103rb.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.dts b/boards/st/nucleo_f103rb/nucleo_f103rb.dts similarity index 100% rename from boards/arm/nucleo_f103rb/nucleo_f103rb.dts rename to boards/st/nucleo_f103rb/nucleo_f103rb.dts diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb.yaml b/boards/st/nucleo_f103rb/nucleo_f103rb.yaml similarity index 100% rename from boards/arm/nucleo_f103rb/nucleo_f103rb.yaml rename to boards/st/nucleo_f103rb/nucleo_f103rb.yaml diff --git a/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig b/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig similarity index 81% rename from boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig rename to boards/st/nucleo_f103rb/nucleo_f103rb_defconfig index b3d7a802a88427..d4828716f02444 100644 --- a/boards/arm/nucleo_f103rb/nucleo_f103rb_defconfig +++ b/boards/st/nucleo_f103rb/nucleo_f103rb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XB=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/arm/nucleo_f103rb/st_morpho_connector.dtsi b/boards/st/nucleo_f103rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f103rb/st_morpho_connector.dtsi rename to boards/st/nucleo_f103rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f103rb/support/openocd.cfg b/boards/st/nucleo_f103rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f103rb/support/openocd.cfg rename to boards/st/nucleo_f103rb/support/openocd.cfg diff --git a/boards/st/nucleo_f207zg/Kconfig.defconfig b/boards/st/nucleo_f207zg/Kconfig.defconfig new file mode 100644 index 00000000000000..c859796428d673 --- /dev/null +++ b/boards/st/nucleo_f207zg/Kconfig.defconfig @@ -0,0 +1,15 @@ +# NUCLEO-144 F207ZG board configuration + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F207ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F207ZG diff --git a/boards/st/nucleo_f207zg/Kconfig.nucleo_f207zg b/boards/st/nucleo_f207zg/Kconfig.nucleo_f207zg new file mode 100644 index 00000000000000..08d270ad23685b --- /dev/null +++ b/boards/st/nucleo_f207zg/Kconfig.nucleo_f207zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F207ZG + select SOC_STM32F207XX diff --git a/boards/arm/nucleo_f207zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f207zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f207zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f207zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f207zg/board.cmake b/boards/st/nucleo_f207zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f207zg/board.cmake rename to boards/st/nucleo_f207zg/board.cmake diff --git a/boards/st/nucleo_f207zg/board.yml b/boards/st/nucleo_f207zg/board.yml new file mode 100644 index 00000000000000..8b35f4457cd7af --- /dev/null +++ b/boards/st/nucleo_f207zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f207zg + vendor: st + socs: + - name: stm32f207xx diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_left.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_morpho_right.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_left.jpg diff --git a/boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg b/boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg similarity index 100% rename from boards/arm/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg rename to boards/st/nucleo_f207zg/doc/img/nucleo_f207zg_zio_right.jpg diff --git a/boards/st/nucleo_f207zg/doc/index.rst b/boards/st/nucleo_f207zg/doc/index.rst new file mode 100644 index 00000000000000..a801f0bc1e9a60 --- /dev/null +++ b/boards/st/nucleo_f207zg/doc/index.rst @@ -0,0 +1,206 @@ +.. _nucleo_f207zg_board: + +ST Nucleo F207ZG +################ + +Overview +******** + +The Nucleo F207ZG board features an ARM Cortex-M3 based STM32F207ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F207ZG board: + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f207zg.jpg + :align: center + :alt: Nucleo F207ZG + +More information about the board can be found at the `Nucleo F207ZG website`_. + +Hardware +******** + +Nucleo F207ZG provides the following hardware components: + +- STM32F207ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M3 CPU +- 120 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 24 channels +- RTC +- 17 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (6) +- I2C (3) +- SPI (3) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- 10/100 Ethernet MAC with dedicated DMA +- CRC calculation unit +- True random number generator + +More information about STM32F207ZG can be found here: + +- `STM32F207ZG on www.st.com`_ +- `STM32F207 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_207zg board configuration supports the following hardware features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | Random Number Generator | ++-------------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-------------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_f207zg/nucleo_f207zg_defconfig` + + +Connections and IOs +=================== + +Nucleo F207ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f207zg_zio_left.jpg + :align: center + :alt: Nucleo F207ZG ZIO connectors (left) +.. image:: img/nucleo_f207zg_zio_right.jpg + :align: center + :alt: Nucleo F207ZG ZIO connectors (right) +.. image:: img/nucleo_f207zg_morpho_left.jpg + :align: center + :alt: Nucleo F207ZG Morpho connectors (left) +.. image:: img/nucleo_f207zg_morpho_right.jpg + :align: center + :alt: Nucleo F207ZG Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB_DM : PA11 +- USB_DP : PA12 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- DAC: PA4 +- ADC: PA0 +- PWM_1_CH1 : PE9 + +System Clock +------------ + +Nucleo F207ZG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 120MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F207ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + +Network interface +----------------- + +Ethernet configured as the default network interface + +USB +--- +Nucleo F207ZG board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its micro USB connector +(USB USER). Only USB device function is supported in Zephyr at the moment. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +Programming and Debugging +************************* + +Nucleo F207ZG board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F207ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f207zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F207ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f207zg.html + +.. _STM32F207 reference manual: + https://www.st.com/resource/en/reference_manual/cd00225773.pdf diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.dts b/boards/st/nucleo_f207zg/nucleo_f207zg.dts similarity index 100% rename from boards/arm/nucleo_f207zg/nucleo_f207zg.dts rename to boards/st/nucleo_f207zg/nucleo_f207zg.dts diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg.yaml b/boards/st/nucleo_f207zg/nucleo_f207zg.yaml similarity index 100% rename from boards/arm/nucleo_f207zg/nucleo_f207zg.yaml rename to boards/st/nucleo_f207zg/nucleo_f207zg.yaml diff --git a/boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig b/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig similarity index 84% rename from boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig rename to boards/st/nucleo_f207zg/nucleo_f207zg_defconfig index b501adaa7ca601..2f2243e0a3b10d 100644 --- a/boards/arm/nucleo_f207zg/nucleo_f207zg_defconfig +++ b/boards/st/nucleo_f207zg/nucleo_f207zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F2X=y -CONFIG_SOC_STM32F207XX=y - CONFIG_SERIAL=y # Enable MPU diff --git a/boards/arm/nucleo_f207zg/support/openocd.cfg b/boards/st/nucleo_f207zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f207zg/support/openocd.cfg rename to boards/st/nucleo_f207zg/support/openocd.cfg diff --git a/boards/st/nucleo_f302r8/Kconfig.nucleo_f302r8 b/boards/st/nucleo_f302r8/Kconfig.nucleo_f302r8 new file mode 100644 index 00000000000000..060386906069a5 --- /dev/null +++ b/boards/st/nucleo_f302r8/Kconfig.nucleo_f302r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Seitz & Associates +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F302R8 + select SOC_STM32F302X8 diff --git a/boards/arm/nucleo_f302r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f302r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f302r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_f302r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f302r8/board.cmake b/boards/st/nucleo_f302r8/board.cmake similarity index 100% rename from boards/arm/nucleo_f302r8/board.cmake rename to boards/st/nucleo_f302r8/board.cmake diff --git a/boards/st/nucleo_f302r8/board.yml b/boards/st/nucleo_f302r8/board.yml new file mode 100644 index 00000000000000..a39ae3dc6d2e2a --- /dev/null +++ b/boards/st/nucleo_f302r8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f302r8 + vendor: st + socs: + - name: stm32f302x8 diff --git a/boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8.jpg b/boards/st/nucleo_f302r8/doc/img/nucleo_f302r8.jpg similarity index 100% rename from boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8.jpg rename to boards/st/nucleo_f302r8/doc/img/nucleo_f302r8.jpg diff --git a/boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg b/boards/st/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg rename to boards/st/nucleo_f302r8/doc/img/nucleo_f302r8_connectors.jpg diff --git a/boards/st/nucleo_f302r8/doc/index.rst b/boards/st/nucleo_f302r8/doc/index.rst new file mode 100644 index 00000000000000..88afebe40cb6b0 --- /dev/null +++ b/boards/st/nucleo_f302r8/doc/index.rst @@ -0,0 +1,168 @@ +.. _nucleo_f302r8_board: + +ST Nucleo F302R8 +################ + +Overview +******** + +The Nucleo F302R8 board features an ARM Cortex-M4 based STM32F302R8 +mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. +Here are some highlights of the Nucleo F302R8 board: + +- STM32 microcontroller in LQFP64 package +- LSE crystal: 32.768 kHz crystal oscillator +- Two types of extension resources: + + - Arduino* Uno V3 connectors + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- One user LED +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f302r8.jpg + :align: center + :alt: Nucleo F302R8 + +More information about the board can be found at the `Nucleo F302R8 website`_, +and in the `STM32 Nucleo-64 board User Manual`_. + +Hardware +******** + +The Nucleo F302R8 provides the following hardware components: + +- STM32F302R8T6 in QFP64 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 64 MB Flash +- 16 KB SRAM +- RTC +- Advanced-control Timer +- General Purpose Timers (4) +- Basic Timer +- Watchdog Timers (2) +- PWM channels (18) +- SPI/I2S (2) +- I2C (3) +- USART/UART (3/3) +- USB 2.0 FS with on-chip PHY +- CAN (2) +- GPIO with external interrupt capability +- DMA channels (7) +- Capacitive sensing channels (18) +- 12-bit ADC with 15 channels +- 12-bit D/A converter +- Analog comparator (3) +- Op amp + + +More information about the STM32F302R8 can be found here: + +- `STM32F302R8 on www.st.com`_ +- `STM32F302R8 reference manual`_ +- `STM32F302R8 datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f302r8 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f302r8/nucleo_f302r8_defconfig` + +Connections and IOs +=================== + +The Nucleo F302R8 Board has 5 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +Board connectors: +----------------- +.. image:: img/nucleo_f302r8_connectors.jpg + :align: center + :alt: Nucleo F302R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F302R8 board features an Arduino Uno V3 connector and a ST +morpho connector. Board is configured as follows: + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- UART_3 TX/RX : PC10/PC11 +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI2 CS/SCK/MISO/MOSI : PB6/PB13/PB14/P15 (Arduino SPI) +- PWM_2_CH2 : PA0 +- USER_PB : PC13 +- LD2 : PB13 + +System Clock +------------ + +The Nucleo F302R8 System Clock can be driven by an internal or +external oscillator, as well as by the main PLL clock. By default the +System Clock is driven by the PLL clock at 72 MHz. The input to the +PLL is an 8 MHz external clock supplied by the processor of the +on-board ST-LINK/V2-1 debugger/programmer. + +Serial Port +----------- + +The Nucleo F302R8 board has 3 UARTs. The Zephyr console output is assigned +to UART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +The Nucleo F302R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F302R8 website: + https://www.st.com/en/evaluation-tools/nucleo-f302r8.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F302R8 on www.st.com: + https://www.st.com/en/microcontrollers/stm32f302r8.html + +.. _STM32F302R8 reference manual: + https://www.st.com/resource/en/reference_manual/dm00094349.pdf + +.. _STM32F302R8 datasheet: + https://www.st.com/resource/en/datasheet/stm32f302r8.pdf diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8.dts b/boards/st/nucleo_f302r8/nucleo_f302r8.dts similarity index 100% rename from boards/arm/nucleo_f302r8/nucleo_f302r8.dts rename to boards/st/nucleo_f302r8/nucleo_f302r8.dts diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8.yaml b/boards/st/nucleo_f302r8/nucleo_f302r8.yaml similarity index 100% rename from boards/arm/nucleo_f302r8/nucleo_f302r8.yaml rename to boards/st/nucleo_f302r8/nucleo_f302r8.yaml diff --git a/boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig b/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig similarity index 79% rename from boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig rename to boards/st/nucleo_f302r8/nucleo_f302r8_defconfig index 8cb3b3a13adfa0..ed6630de61e2dc 100644 --- a/boards/arm/nucleo_f302r8/nucleo_f302r8_defconfig +++ b/boards/st/nucleo_f302r8/nucleo_f302r8_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F302X8=y - CONFIG_SERIAL=y # console diff --git a/boards/arm/nucleo_f302r8/st_morpho_connector.dtsi b/boards/st/nucleo_f302r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f302r8/st_morpho_connector.dtsi rename to boards/st/nucleo_f302r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f302r8/support/openocd.cfg b/boards/st/nucleo_f302r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f302r8/support/openocd.cfg rename to boards/st/nucleo_f302r8/support/openocd.cfg diff --git a/boards/st/nucleo_f303k8/Kconfig.nucleo_f303k8 b/boards/st/nucleo_f303k8/Kconfig.nucleo_f303k8 new file mode 100644 index 00000000000000..6da913d4a82152 --- /dev/null +++ b/boards/st/nucleo_f303k8/Kconfig.nucleo_f303k8 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Sebastian Schwabe +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F303K8 + select SOC_STM32F303X8 diff --git a/boards/arm/nucleo_f303k8/board.cmake b/boards/st/nucleo_f303k8/board.cmake similarity index 100% rename from boards/arm/nucleo_f303k8/board.cmake rename to boards/st/nucleo_f303k8/board.cmake diff --git a/boards/st/nucleo_f303k8/board.yml b/boards/st/nucleo_f303k8/board.yml new file mode 100644 index 00000000000000..ae44e2bbb550ba --- /dev/null +++ b/boards/st/nucleo_f303k8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f303k8 + vendor: st + socs: + - name: stm32f303x8 diff --git a/boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8.jpg b/boards/st/nucleo_f303k8/doc/img/nucleo_f303k8.jpg similarity index 100% rename from boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8.jpg rename to boards/st/nucleo_f303k8/doc/img/nucleo_f303k8.jpg diff --git a/boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg b/boards/st/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg similarity index 100% rename from boards/arm/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg rename to boards/st/nucleo_f303k8/doc/img/nucleo_f303k8_pinout.jpg diff --git a/boards/st/nucleo_f303k8/doc/index.rst b/boards/st/nucleo_f303k8/doc/index.rst new file mode 100644 index 00000000000000..1f8ff4a3250c49 --- /dev/null +++ b/boards/st/nucleo_f303k8/doc/index.rst @@ -0,0 +1,159 @@ +.. _nucleo_f303k8_board: + +ST Nucleo F303K8 +################ + +Overview +******** + +The Nucleo F303K8 board features an ARM Cortex-M4 based STM32F303K8 +mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. +Here are some highlights of the Nucleo F303K8 board: + +- STM32 microcontroller in LQFP32 package +- one type of extension resources: + +- Arduino™ Nano V3 connectivity support + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + +- 5 V from ST-LINK/V2-1 USB VBUS +- External power sources: 3.3 V, 5V and 7 - 12 V + +- One user LED +- One push-buttons: RESET + +.. image:: img/nucleo_f303k8.jpg + :align: center + :alt: Nucleo F303K8 + +More information about the board can be found at the `Nucleo F303K8 website`_, +and in the `STM32 Nucleo-32 board User Manual`_. + +Hardware +******** + +The Nucleo F303K8 provides the following hardware components: + +- STM32F303K8T6 in LQFP32 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 64 MB Flash +- 12 KB SRAM +- RTC +- Advanced-control Timer +- General Purpose Timers (5) +- Basic Timer (2) +- Watchdog Timers (2) +- PWM channels (12) +- SPI/I2S (1) +- I2C (1) +- USART/UART (2) +- CAN (1) +- GPIO with external interrupt capability +- DMA channels (7) +- Capacitive sensing channels (18) +- 12-bit ADC with 21 channels +- 12-bit D/A converter +- Analog comparator (3) +- Op amp + + +More information about the STM32F303K8 can be found here: + +- `STM32F303K8 on www.st.com`_ +- `STM32F303K8 reference manual`_ +- `STM32F303K8 datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f303k8 board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f303k8/nucleo_f303k8_defconfig` + +Connections and IOs +=================== + +The Nucleo F303K8 Board has 1 GPIO controller. This controllers is responsible +for input/output, pull-up, etc. + +Board connectors: +----------------- +.. image:: img/nucleo_f303k8_pinout.jpg + :align: center + :alt: Nucleo F303K8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F303K8 board features an Arduino Zero V3 connector. Board is configured as follows: + +- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB7/PB6 +- SPI1 CS/SCK/MISO/MOSI : PA_4/PA_5/PB_4/PA_7 +- LD2 : PB3 + +System Clock +------------ + +The Nucleo F303K8 System Clock can be driven by an internal or +external oscillator, as well as by the main PLL clock. By default the +System Clock is driven by the PLL clock at 72 MHz. The input to the +PLL is an 8 MHz internal clock supply. + +Serial Port +----------- + +The Nucleo F303K8 board has 2 UARTs. The Zephyr console output is assigned +to UART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +The Nucleo F303K8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F303K8 website: + https://www.st.com/en/evaluation-tools/nucleo-F303K8.html + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf + +.. _STM32F303K8 on www.st.com: + https://www.st.com/en/microcontrollers/stm32F303K8.html + +.. _STM32F303K8 reference manual: + https://www.st.com/resource/en/reference_manual/dm00043574-stm32f303xbcde-stm32f303x68-stm32f328x8-stm32f358xc-stm32f398xe-advanced-armbased-mcus-stmicroelectronics.pdf + +.. _STM32F303K8 datasheet: + https://www.st.com/resource/en/datasheet/stm32f303k8.pdf diff --git a/boards/arm/nucleo_f303k8/nucleo_f303k8.dts b/boards/st/nucleo_f303k8/nucleo_f303k8.dts similarity index 100% rename from boards/arm/nucleo_f303k8/nucleo_f303k8.dts rename to boards/st/nucleo_f303k8/nucleo_f303k8.dts diff --git a/boards/arm/nucleo_f303k8/nucleo_f303k8.yaml b/boards/st/nucleo_f303k8/nucleo_f303k8.yaml similarity index 100% rename from boards/arm/nucleo_f303k8/nucleo_f303k8.yaml rename to boards/st/nucleo_f303k8/nucleo_f303k8.yaml diff --git a/boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig b/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig similarity index 79% rename from boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig rename to boards/st/nucleo_f303k8/nucleo_f303k8_defconfig index 67f7f844b42ca2..ed6630de61e2dc 100644 --- a/boards/arm/nucleo_f303k8/nucleo_f303k8_defconfig +++ b/boards/st/nucleo_f303k8/nucleo_f303k8_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F303X8=y - CONFIG_SERIAL=y # console diff --git a/boards/arm/nucleo_f303k8/support/openocd.cfg b/boards/st/nucleo_f303k8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f303k8/support/openocd.cfg rename to boards/st/nucleo_f303k8/support/openocd.cfg diff --git a/boards/st/nucleo_f303re/Kconfig.nucleo_f303re b/boards/st/nucleo_f303re/Kconfig.nucleo_f303re new file mode 100644 index 00000000000000..7f2ad4639e3839 --- /dev/null +++ b/boards/st/nucleo_f303re/Kconfig.nucleo_f303re @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Paul M. Bendixen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F303RE + select SOC_STM32F303XE diff --git a/boards/arm/nucleo_f303re/arduino_r3_connector.dtsi b/boards/st/nucleo_f303re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f303re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f303re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f303re/board.cmake b/boards/st/nucleo_f303re/board.cmake similarity index 100% rename from boards/arm/nucleo_f303re/board.cmake rename to boards/st/nucleo_f303re/board.cmake diff --git a/boards/st/nucleo_f303re/board.yml b/boards/st/nucleo_f303re/board.yml new file mode 100644 index 00000000000000..dc99dcc1d6a235 --- /dev/null +++ b/boards/st/nucleo_f303re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f303re + vendor: st + socs: + - name: stm32f303xe diff --git a/boards/arm/nucleo_f303re/doc/img/nucleo_connectors.jpg b/boards/st/nucleo_f303re/doc/img/nucleo_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f303re/doc/img/nucleo_connectors.jpg rename to boards/st/nucleo_f303re/doc/img/nucleo_connectors.jpg diff --git a/boards/arm/nucleo_f303re/doc/img/nucleo_f303re.jpg b/boards/st/nucleo_f303re/doc/img/nucleo_f303re.jpg similarity index 100% rename from boards/arm/nucleo_f303re/doc/img/nucleo_f303re.jpg rename to boards/st/nucleo_f303re/doc/img/nucleo_f303re.jpg diff --git a/boards/st/nucleo_f303re/doc/index.rst b/boards/st/nucleo_f303re/doc/index.rst new file mode 100644 index 00000000000000..967079f1ff3c89 --- /dev/null +++ b/boards/st/nucleo_f303re/doc/index.rst @@ -0,0 +1,162 @@ +.. _nucleo_f303re_board: + +ST Nucleo F303RE +################ + +Overview +******** + +The Nucleo F303RE board features an ARM Cortex-M4 based STM32F303RE +mixed-signal MCU with FPU and DSP instructions capable of running at 72 MHz. +Here are some highlights of the Nucleo F303RE board: + +- STM32 microcontroller in LQFP64 package +- LSE crystal: 32.768 kHz crystal oscillator +- Two types of extension resources: + + - Arduino* Uno V3 connectors + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- One user LED +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f303re.jpg + :align: center + :alt: Nucleo F303RE + +More information about the board can be found at the `Nucleo F303RE website`_, +and in the `STM32 Nucleo-64 board User Manual`_. + +Hardware +******** + +The Nucleo F303RE provides the following hardware components: + +- STM32F303RET6 in QFP64 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 512 MB Flash +- 64 + 16 KB SRAM +- RTC +- Advanced-control Timer +- General Purpose Timers (4) +- Basic Timer +- Watchdog Timers (2) +- PWM channels (18) +- SPI/I2S (2) +- I2C (3) +- USART/UART (3/3) +- USB 2.0 FS with on-chip PHY +- CAN (2) +- GPIO with external interrupt capability +- DMA channels (12) +- Capacitive sensing channels (18) +- 12-bit ADC with 40 channels (4) +- 12-bit D/A converter with two channels +- Analog comparator (7) +- Op amp (4) +- Capacitive sensing 24 channels + + +More information about the STM32F303RE can be found here: + +- `STM32F303RE on www.st.com`_ +- `STM32F303RE reference manual`_ +- `STM32F303RE datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f303re board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f303re/nucleo_f303re_defconfig` + +Connections and IOs +=================== + +The Nucleo F303RE Board has 5 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +Board connectors: +----------------- +.. image:: img/nucleo_connectors.jpg + :align: center + :alt: Nucleo F303RE connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F303RE board features an Arduino Uno V3 connector and a ST +morpho connector. Board is configured as follows: + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD2 : PA5 + +System Clock +------------ + +The Nucleo F303RE System Clock can be driven by an internal or +external oscillator, as well as by the main PLL clock. By default the +System Clock is driven by the PLL clock at 72 MHz. The input to the +PLL is an 8 MHz external clock supplied by the processor of the +on-board ST-LINK/V2-1 debugger/programmer. + +Serial Port +----------- + +The Nucleo F303RE board has 2 UARTs. The Zephyr console output is assigned +to UART2. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +The Nucleo F303RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F303RE website: + https://www.st.com/en/evaluation-tools/nucleo-f303re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F303RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f303re.html + +.. _STM32F303RE reference manual: + https://www.st.com/resource/en/reference_manual/dm00043574.pdf + +.. _STM32F303RE datasheet: + https://www.st.com/resource/en/datasheet/stm32f303re.pdf diff --git a/boards/arm/nucleo_f303re/nucleo_f303re.dts b/boards/st/nucleo_f303re/nucleo_f303re.dts similarity index 100% rename from boards/arm/nucleo_f303re/nucleo_f303re.dts rename to boards/st/nucleo_f303re/nucleo_f303re.dts diff --git a/boards/arm/nucleo_f303re/nucleo_f303re.yaml b/boards/st/nucleo_f303re/nucleo_f303re.yaml similarity index 100% rename from boards/arm/nucleo_f303re/nucleo_f303re.yaml rename to boards/st/nucleo_f303re/nucleo_f303re.yaml diff --git a/boards/arm/nucleo_f303re/nucleo_f303re_defconfig b/boards/st/nucleo_f303re/nucleo_f303re_defconfig similarity index 84% rename from boards/arm/nucleo_f303re/nucleo_f303re_defconfig rename to boards/st/nucleo_f303re/nucleo_f303re_defconfig index c73a485b23936e..2f2243e0a3b10d 100644 --- a/boards/arm/nucleo_f303re/nucleo_f303re_defconfig +++ b/boards/st/nucleo_f303re/nucleo_f303re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F303XE=y - CONFIG_SERIAL=y # Enable MPU diff --git a/boards/arm/nucleo_f303re/st_morpho_connector.dtsi b/boards/st/nucleo_f303re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f303re/st_morpho_connector.dtsi rename to boards/st/nucleo_f303re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f303re/support/openocd.cfg b/boards/st/nucleo_f303re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f303re/support/openocd.cfg rename to boards/st/nucleo_f303re/support/openocd.cfg diff --git a/boards/st/nucleo_f334r8/Kconfig.defconfig b/boards/st/nucleo_f334r8/Kconfig.defconfig new file mode 100644 index 00000000000000..7a48abedd474c0 --- /dev/null +++ b/boards/st/nucleo_f334r8/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32F334R8 MCU + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F334R8 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F334R8 diff --git a/boards/st/nucleo_f334r8/Kconfig.nucleo_f334r8 b/boards/st/nucleo_f334r8/Kconfig.nucleo_f334r8 new file mode 100644 index 00000000000000..d605a67440e572 --- /dev/null +++ b/boards/st/nucleo_f334r8/Kconfig.nucleo_f334r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F334R8 + select SOC_STM32F334X8 diff --git a/boards/arm/nucleo_f334r8/arduino_r3_connector.dtsi b/boards/st/nucleo_f334r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f334r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_f334r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f334r8/board.cmake b/boards/st/nucleo_f334r8/board.cmake similarity index 100% rename from boards/arm/nucleo_f334r8/board.cmake rename to boards/st/nucleo_f334r8/board.cmake diff --git a/boards/st/nucleo_f334r8/board.yml b/boards/st/nucleo_f334r8/board.yml new file mode 100644 index 00000000000000..7a8a3e642d89f5 --- /dev/null +++ b/boards/st/nucleo_f334r8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f334r8 + vendor: st + socs: + - name: stm32f334x8 diff --git a/boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8.jpg b/boards/st/nucleo_f334r8/doc/img/nucleo_f334r8.jpg similarity index 100% rename from boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8.jpg rename to boards/st/nucleo_f334r8/doc/img/nucleo_f334r8.jpg diff --git a/boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg b/boards/st/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg rename to boards/st/nucleo_f334r8/doc/img/nucleo_f334r8_connectors.jpg diff --git a/boards/st/nucleo_f334r8/doc/index.rst b/boards/st/nucleo_f334r8/doc/index.rst new file mode 100644 index 00000000000000..10e312696248c9 --- /dev/null +++ b/boards/st/nucleo_f334r8/doc/index.rst @@ -0,0 +1,179 @@ +.. _nucleo_f334r8_board: + +ST Nucleo F334R8 +################ + +Overview +******** +STM32 Nucleo-64 development board with STM32F334R8 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board does not require any separate probe as it integrates the ST-LINK/V2-1 +debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_f334r8.jpg + :align: center + :alt: Nucleo F334R8 + +More information about the board can be found at the `Nucleo F334R8 website`_. + +Hardware +******** +Nucleo F334R8 provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32F334R8 can be found in the +`STM32F334 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_f334r8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f334r8/nucleo_f334r8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_f334r8_connectors.jpg + :align: center + :alt: Nucleo F334R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- UART_3 TX/RX : PB10/PB11 +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- PWM_1_CH1 : PA8 +- USER_PB : PC13 +- LD2 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f334r8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F334R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to Nucleo F334R8 +---------------------------------------- + +Connect the Nucleo F334R8 to your host computer using the USB port, +then build and flash an application. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f334r8 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for +the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_f334r8 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo F334R8 website: + https://www.st.com/en/evaluation-tools/nucleo-f334r8.html + +.. _STM32F334 reference manual: + https://www.st.com/resource/en/reference_manual/dm00093941.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8.dts b/boards/st/nucleo_f334r8/nucleo_f334r8.dts similarity index 100% rename from boards/arm/nucleo_f334r8/nucleo_f334r8.dts rename to boards/st/nucleo_f334r8/nucleo_f334r8.dts diff --git a/boards/arm/nucleo_f334r8/nucleo_f334r8.yaml b/boards/st/nucleo_f334r8/nucleo_f334r8.yaml similarity index 100% rename from boards/arm/nucleo_f334r8/nucleo_f334r8.yaml rename to boards/st/nucleo_f334r8/nucleo_f334r8.yaml diff --git a/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig b/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig new file mode 100644 index 00000000000000..d20d380241568a --- /dev/null +++ b/boards/st/nucleo_f334r8/nucleo_f334r8_defconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable clock +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_f334r8/st_morpho_connector.dtsi b/boards/st/nucleo_f334r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f334r8/st_morpho_connector.dtsi rename to boards/st/nucleo_f334r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f334r8/support/openocd.cfg b/boards/st/nucleo_f334r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f334r8/support/openocd.cfg rename to boards/st/nucleo_f334r8/support/openocd.cfg diff --git a/boards/st/nucleo_f401re/Kconfig.defconfig b/boards/st/nucleo_f401re/Kconfig.defconfig new file mode 100644 index 00000000000000..cfb78f3344214c --- /dev/null +++ b/boards/st/nucleo_f401re/Kconfig.defconfig @@ -0,0 +1,13 @@ +# NUCLEO-64 F401RE board configuration + +# Copyright (c) 2016 Linaro Limited. +# Copyright (c) 2019 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F401RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F401RE diff --git a/boards/st/nucleo_f401re/Kconfig.nucleo_f401re b/boards/st/nucleo_f401re/Kconfig.nucleo_f401re new file mode 100644 index 00000000000000..8b67befec4b348 --- /dev/null +++ b/boards/st/nucleo_f401re/Kconfig.nucleo_f401re @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F401RE + select SOC_STM32F401XE diff --git a/boards/arm/nucleo_f401re/arduino_r3_connector.dtsi b/boards/st/nucleo_f401re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f401re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f401re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f401re/board.cmake b/boards/st/nucleo_f401re/board.cmake similarity index 100% rename from boards/arm/nucleo_f401re/board.cmake rename to boards/st/nucleo_f401re/board.cmake diff --git a/boards/st/nucleo_f401re/board.yml b/boards/st/nucleo_f401re/board.yml new file mode 100644 index 00000000000000..4cb781427b514e --- /dev/null +++ b/boards/st/nucleo_f401re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f401re + vendor: st + socs: + - name: stm32f401xe diff --git a/boards/arm/nucleo_f401re/doc/img/nucleo_f401re.jpg b/boards/st/nucleo_f401re/doc/img/nucleo_f401re.jpg similarity index 100% rename from boards/arm/nucleo_f401re/doc/img/nucleo_f401re.jpg rename to boards/st/nucleo_f401re/doc/img/nucleo_f401re.jpg diff --git a/boards/arm/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg b/boards/st/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg similarity index 100% rename from boards/arm/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg rename to boards/st/nucleo_f401re/doc/img/nucleo_f401re_arduino.jpg diff --git a/boards/arm/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg b/boards/st/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg similarity index 100% rename from boards/arm/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg rename to boards/st/nucleo_f401re/doc/img/nucleo_f401re_morpho.jpg diff --git a/boards/st/nucleo_f401re/doc/index.rst b/boards/st/nucleo_f401re/doc/index.rst new file mode 100644 index 00000000000000..bd806a6378acea --- /dev/null +++ b/boards/st/nucleo_f401re/doc/index.rst @@ -0,0 +1,206 @@ +.. _nucleo_f401re_board: + +ST Nucleo F401RE +################ + +Overview +******** + +The Nucleo F401RE board features an ARM Cortex-M4 based STM32F401RE MCU +with a wide range of connectivity support and configurations Here are +some highlights of the Nucleo F401RE board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f401re.jpg + :align: center + :alt: Nucleo F401RE + +More information about the board can be found at the `Nucleo F401RE website`_. + +Hardware +******** + +Nucleo F401RE provides the following hardware components: + +- STM32F401RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 96 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (7) +- Watchdog Timers (2) +- USART/UART (3) +- I2C (3) +- SPI (4) +- SDIO +- USB 2.0 OTG FS +- DMA Controller + +More information about STM32F401RE can be found here: + +- `STM32F401RE on www.st.com`_ +- `STM32F401 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_401re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | System Window Watchdog | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re_defconfig` + + +Pin Mapping +=========== + +Nucleo F401RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f401re_arduino.jpg + :align: center + :alt: Nucleo F401RE Arduino connectors +.. image:: img/nucleo_f401re_morpho.jpg + :align: center + :alt: Nucleo F401RE Morpho connectors + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD2 : PA5 + +System Clock +============ + +Nucleo F401RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, +driven by 8MHz high speed external clock. + +Serial Port +=========== + +Nucleo F401RE board has 3 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +I2C +=== + +Nucleo F401RE board has up to 3 I2Cs. The default I2C mapping for Zephyr is: + +- I2C1_SCL : PB8 +- I2C1_SDA : PB9 + +Programming and Debugging +************************* + +Applications for the ``nucleo_f401re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to Nucleo F401RE +---------------------------------------- + +Connect the Nucleo F401RE to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f401re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f401re + :maybe-skip-config: + :goals: debug + +.. _Nucleo F401RE website: + https://www.st.com/en/evaluation-tools/nucleo-f401re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F401RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f401re.html + +.. _STM32F401 reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/nucleo_f401re/nucleo_f401re.dts b/boards/st/nucleo_f401re/nucleo_f401re.dts similarity index 100% rename from boards/arm/nucleo_f401re/nucleo_f401re.dts rename to boards/st/nucleo_f401re/nucleo_f401re.dts diff --git a/boards/arm/nucleo_f401re/nucleo_f401re.yaml b/boards/st/nucleo_f401re/nucleo_f401re.yaml similarity index 100% rename from boards/arm/nucleo_f401re/nucleo_f401re.yaml rename to boards/st/nucleo_f401re/nucleo_f401re.yaml diff --git a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig b/boards/st/nucleo_f401re/nucleo_f401re_defconfig similarity index 85% rename from boards/arm/nucleo_f401re/nucleo_f401re_defconfig rename to boards/st/nucleo_f401re/nucleo_f401re_defconfig index 637108b6d833eb..750f99bdff3b71 100644 --- a/boards/arm/nucleo_f401re/nucleo_f401re_defconfig +++ b/boards/st/nucleo_f401re/nucleo_f401re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f401re/st_morpho_connector.dtsi b/boards/st/nucleo_f401re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f401re/st_morpho_connector.dtsi rename to boards/st/nucleo_f401re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f401re/support/openocd.cfg b/boards/st/nucleo_f401re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f401re/support/openocd.cfg rename to boards/st/nucleo_f401re/support/openocd.cfg diff --git a/boards/st/nucleo_f410rb/Kconfig.defconfig b/boards/st/nucleo_f410rb/Kconfig.defconfig new file mode 100644 index 00000000000000..198018e7cc0031 --- /dev/null +++ b/boards/st/nucleo_f410rb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F410RB Nucleo board configuration + +# Copyright (c) 2020 Hans Unzner +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F410RB + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F410RB diff --git a/boards/st/nucleo_f410rb/Kconfig.nucleo_f410rb b/boards/st/nucleo_f410rb/Kconfig.nucleo_f410rb new file mode 100644 index 00000000000000..2a62a1eecc76e7 --- /dev/null +++ b/boards/st/nucleo_f410rb/Kconfig.nucleo_f410rb @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Hans Unzner +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F410RB + select SOC_STM32F410RX diff --git a/boards/arm/nucleo_f410rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f410rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f410rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_f410rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f410rb/board.cmake b/boards/st/nucleo_f410rb/board.cmake similarity index 100% rename from boards/arm/nucleo_f410rb/board.cmake rename to boards/st/nucleo_f410rb/board.cmake diff --git a/boards/st/nucleo_f410rb/board.yml b/boards/st/nucleo_f410rb/board.yml new file mode 100644 index 00000000000000..23c247e3bad904 --- /dev/null +++ b/boards/st/nucleo_f410rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f410rb + vendor: st + socs: + - name: stm32f410rx diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_left.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_arduino_top_right.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_left.jpg diff --git a/boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg b/boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg rename to boards/st/nucleo_f410rb/doc/img/nucleo_f410rb_morpho_top_right.jpg diff --git a/boards/st/nucleo_f410rb/doc/index.rst b/boards/st/nucleo_f410rb/doc/index.rst new file mode 100644 index 00000000000000..58579bce21cf77 --- /dev/null +++ b/boards/st/nucleo_f410rb/doc/index.rst @@ -0,0 +1,212 @@ +.. _nucleo_f410rb_board: + +ST Nucleo F410RB +################ + +Overview +******** + +The Nucleo F410RB board features an ARM Cortex-M4 based STM32F410RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F410RB board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f410rb.jpg + :align: center + :alt: Nucleo F410RB + +More information about the board can be found at the `Nucleo F410RB website`_. + +Hardware +******** + +Nucleo F410RB provides the following hardware components: + +- STM32F410RBT6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Adaptive real-time accelerator (ART Accelerator) +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 128 KB Flash +- 32 KB SRAM +- General purpose timer (4) +- Low-power timer (1) +- Advanced-control timer (1) +- Random number generator (TRNG for HW entropy) +- SPI/I2S (3) +- I2C (3) +- USART (3) +- GPIO (50) with external interrupt capability +- 12-bit ADC with 16 channels +- 12-bit DAC with 1 channel +- RTC + + +More information about STM32F410RB can be found here: + +- `STM32F410RB on www.st.com`_ +- `STM32F410 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f410rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | window & independent | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f410rb/nucleo_f410rb_defconfig` + + +Connections and IOs +=================== + +Nucleo F410RB Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f410rb_arduino_top_left.jpg + :align: center + :alt: Nucleo F410RB Arduino connectors (top left) +.. image:: img/nucleo_f410rb_arduino_top_right.jpg + :align: center + :alt: Nucleo F410RB Arduino connectors (top right) +.. image:: img/nucleo_f410rb_morpho_top_left.jpg + :align: center + :alt: Nucleo F410RB Morpho connectors (top left) +.. image:: img/nucleo_f410rb_morpho_top_right.jpg + :align: center + :alt: Nucleo F410RB Morpho connectors (top right) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PC13 +- LD2 : PA5 +- I2C1_SDA : PB9 +- I2C1_SCL : PB8 +- I2C2_SDA : PB3 +- I2C2_SCL : PB10 + +System Clock +------------ + +Nucleo F410RB System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, +driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F410RB board has 3 USARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f410rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F410RB board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F410RB +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f410rb + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f410rb + :maybe-skip-config: + :goals: debug + +.. _Nucleo F410RB website: + https://www.st.com/en/evaluation-tools/nucleo-F410RB.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F410RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32f410rb.html + +.. _STM32F410 reference manual: + https://www.st.com/resource/en/reference_manual/dm00180366.pdf diff --git a/boards/arm/nucleo_f410rb/nucleo_f410rb.dts b/boards/st/nucleo_f410rb/nucleo_f410rb.dts similarity index 100% rename from boards/arm/nucleo_f410rb/nucleo_f410rb.dts rename to boards/st/nucleo_f410rb/nucleo_f410rb.dts diff --git a/boards/arm/nucleo_f410rb/nucleo_f410rb.yaml b/boards/st/nucleo_f410rb/nucleo_f410rb.yaml similarity index 100% rename from boards/arm/nucleo_f410rb/nucleo_f410rb.yaml rename to boards/st/nucleo_f410rb/nucleo_f410rb.yaml diff --git a/boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig b/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig similarity index 84% rename from boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig rename to boards/st/nucleo_f410rb/nucleo_f410rb_defconfig index 4c7485eb6b36c2..c729b83e3d0506 100644 --- a/boards/arm/nucleo_f410rb/nucleo_f410rb_defconfig +++ b/boards/st/nucleo_f410rb/nucleo_f410rb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F410RX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f410rb/st_morpho_connector.dtsi b/boards/st/nucleo_f410rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f410rb/st_morpho_connector.dtsi rename to boards/st/nucleo_f410rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f410rb/support/openocd.cfg b/boards/st/nucleo_f410rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f410rb/support/openocd.cfg rename to boards/st/nucleo_f410rb/support/openocd.cfg diff --git a/boards/st/nucleo_f411re/Kconfig.defconfig b/boards/st/nucleo_f411re/Kconfig.defconfig new file mode 100644 index 00000000000000..43b605301eac93 --- /dev/null +++ b/boards/st/nucleo_f411re/Kconfig.defconfig @@ -0,0 +1,12 @@ +# NUCLEO-64 F411RE board configuration + +# Copyright (c) 2016 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F411RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F411RE diff --git a/boards/st/nucleo_f411re/Kconfig.nucleo_f411re b/boards/st/nucleo_f411re/Kconfig.nucleo_f411re new file mode 100644 index 00000000000000..9f61518746785e --- /dev/null +++ b/boards/st/nucleo_f411re/Kconfig.nucleo_f411re @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Matthias Boesl +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F411RE + select SOC_STM32F411XE diff --git a/boards/arm/nucleo_f411re/arduino_r3_connector.dtsi b/boards/st/nucleo_f411re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f411re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f411re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f411re/board.cmake b/boards/st/nucleo_f411re/board.cmake similarity index 100% rename from boards/arm/nucleo_f411re/board.cmake rename to boards/st/nucleo_f411re/board.cmake diff --git a/boards/st/nucleo_f411re/board.yml b/boards/st/nucleo_f411re/board.yml new file mode 100644 index 00000000000000..6ed17fdc2c4578 --- /dev/null +++ b/boards/st/nucleo_f411re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f411re + vendor: st + socs: + - name: stm32f411xe diff --git a/boards/arm/nucleo_f411re/doc/img/nucleo_f411re.jpg b/boards/st/nucleo_f411re/doc/img/nucleo_f411re.jpg similarity index 100% rename from boards/arm/nucleo_f411re/doc/img/nucleo_f411re.jpg rename to boards/st/nucleo_f411re/doc/img/nucleo_f411re.jpg diff --git a/boards/arm/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg b/boards/st/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg similarity index 100% rename from boards/arm/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg rename to boards/st/nucleo_f411re/doc/img/nucleo_f411re_arduino.jpg diff --git a/boards/arm/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg b/boards/st/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg similarity index 100% rename from boards/arm/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg rename to boards/st/nucleo_f411re/doc/img/nucleo_f411re_morpho.jpg diff --git a/boards/st/nucleo_f411re/doc/index.rst b/boards/st/nucleo_f411re/doc/index.rst new file mode 100644 index 00000000000000..77ca25184c6822 --- /dev/null +++ b/boards/st/nucleo_f411re/doc/index.rst @@ -0,0 +1,200 @@ +.. _nucleo_f411re_board: + +ST Nucleo F411RE +################ + +Overview +******** + +The Nucleo F411RE board features an ARM Cortex-M4 based STM32F411RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F411RE board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f411re.jpg + :align: center + :alt: Nucleo F411RE + +More information about the board can be found at the `Nucleo F411RE website`_. + +Hardware +******** + +Nucleo F411RE provides the following hardware components: + +- STM32F411RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels, with FIFO and burst support +- RTC +- 8 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- CRC calculation unit + +More information about STM32F411RE can be found here: + +- `STM32F411RE on www.st.com`_ +- `STM32F411 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f411re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| I2S | on-chip | i2s | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f411re/nucleo_f411re_defconfig` + + +Connections and IOs +=================== + +Nucleo F411RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f411re_arduino.jpg + :align: center + :alt: Nucleo F411RE Arduino connectors +.. image:: img/nucleo_f411re_morpho.jpg + :align: center + :alt: Nucleo F411RE Morpho connectors + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PB10/PB3 +- I2C1 SCL/SDA : PA8/B4 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Arduino SPI) +- I2S1 SCK/SD : PA5/PA7 (Arduino I2S) +- USER_PB : PC13 +- LD2 : PA5 + +.. note:: Please note that SPI1 and I2S1 are connected to the same mcu pins, as the h/w controller is the same one. + +System Clock +------------ + +Nucleo F411RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 84MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F411RE board has 3 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f411re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F411RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to Nucleo F411RE +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f411re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f411re + :maybe-skip-config: + :goals: debug + +.. _Nucleo F411RE website: + https://www.st.com/en/evaluation-tools/nucleo-f411re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F411RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f411re.html + +.. _STM32F411 reference manual: + https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/nucleo_f411re/nucleo_f411re.dts b/boards/st/nucleo_f411re/nucleo_f411re.dts similarity index 100% rename from boards/arm/nucleo_f411re/nucleo_f411re.dts rename to boards/st/nucleo_f411re/nucleo_f411re.dts diff --git a/boards/arm/nucleo_f411re/nucleo_f411re.yaml b/boards/st/nucleo_f411re/nucleo_f411re.yaml similarity index 100% rename from boards/arm/nucleo_f411re/nucleo_f411re.yaml rename to boards/st/nucleo_f411re/nucleo_f411re.yaml diff --git a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig b/boards/st/nucleo_f411re/nucleo_f411re_defconfig similarity index 85% rename from boards/arm/nucleo_f411re/nucleo_f411re_defconfig rename to boards/st/nucleo_f411re/nucleo_f411re_defconfig index cc07fdb2d8fc35..750f99bdff3b71 100644 --- a/boards/arm/nucleo_f411re/nucleo_f411re_defconfig +++ b/boards/st/nucleo_f411re/nucleo_f411re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f411re/st_morpho_connector.dtsi b/boards/st/nucleo_f411re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f411re/st_morpho_connector.dtsi rename to boards/st/nucleo_f411re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f411re/support/openocd.cfg b/boards/st/nucleo_f411re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f411re/support/openocd.cfg rename to boards/st/nucleo_f411re/support/openocd.cfg diff --git a/boards/st/nucleo_f412zg/Kconfig.defconfig b/boards/st/nucleo_f412zg/Kconfig.defconfig new file mode 100644 index 00000000000000..a2c9ec558818ca --- /dev/null +++ b/boards/st/nucleo_f412zg/Kconfig.defconfig @@ -0,0 +1,18 @@ +# NUCLEO-144 F412ZG board configuration + +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F412ZG + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_ECM + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F412ZG diff --git a/boards/st/nucleo_f412zg/Kconfig.nucleo_f412zg b/boards/st/nucleo_f412zg/Kconfig.nucleo_f412zg new file mode 100644 index 00000000000000..93a0b9f9a5b8c5 --- /dev/null +++ b/boards/st/nucleo_f412zg/Kconfig.nucleo_f412zg @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F412ZG + select SOC_STM32F412ZX diff --git a/boards/arm/nucleo_f412zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f412zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f412zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f412zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f412zg/board.cmake b/boards/st/nucleo_f412zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f412zg/board.cmake rename to boards/st/nucleo_f412zg/board.cmake diff --git a/boards/st/nucleo_f412zg/board.yml b/boards/st/nucleo_f412zg/board.yml new file mode 100644 index 00000000000000..b4bb8372f50b57 --- /dev/null +++ b/boards/st/nucleo_f412zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f412zg + vendor: st + socs: + - name: stm32f412zx diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_left.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_morpho_right.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_left.jpg diff --git a/boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg b/boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg similarity index 100% rename from boards/arm/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg rename to boards/st/nucleo_f412zg/doc/img/nucleo_f412zg_zio_right.jpg diff --git a/boards/st/nucleo_f412zg/doc/index.rst b/boards/st/nucleo_f412zg/doc/index.rst new file mode 100644 index 00000000000000..40039aed0897aa --- /dev/null +++ b/boards/st/nucleo_f412zg/doc/index.rst @@ -0,0 +1,172 @@ +.. _nucleo_f412zg_board: + +ST Nucleo F412ZG +################ + +Overview +******** + +The Nucleo F412ZG board features an ARM Cortex-M4 based STM32F412ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F412ZG board: + +- STM32 microcontroller in LQFP144 package +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f412zg.jpg + :align: center + :alt: Nucleo F412ZG + +More information about the board can be found at the `Nucleo F412ZG website`_. + +Hardware +******** + +Nucleo F412ZG provides the following hardware components: + +- STM32F412ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 256 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 16 channels, with FIFO and burst support +- RTC +- 14 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (4) +- I2C (4) +- SPI (5) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- CRC calculation unit + +More information about STM32F412ZG can be found here: + +- `STM32F412ZG on www.st.com`_ +- `STM32F412 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_412zg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f412zg/nucleo_f412zg_defconfig` + + +Connections and IOs +=================== + +Nucleo F412ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f412zg_zio_left.jpg + :align: center + :alt: Nucleo F412ZG ZIO connectors (left) +.. image:: img/nucleo_f412zg_zio_right.jpg + :align: center + :alt: Nucleo F412ZG ZIO connectors (right) +.. image:: img/nucleo_f412zg_morpho_left.jpg + :align: center + :alt: Nucleo F412ZG Morpho connectors (left) +.. image:: img/nucleo_f412zg_morpho_right.jpg + :align: center + :alt: Nucleo F412ZG Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- USB DM : PA11 +- USB DP : PA12 + +System Clock +------------ + +Nucleo F412ZG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F412ZG board has 4 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + +Network interface +----------------- + +Ethernet over USB is configured as the default network interface + +Programming and Debugging +************************* + +Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F412ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f412zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F412ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f412zg.html + +.. _STM32F412 reference manual: + https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/nucleo_f412zg/nucleo_f412zg.dts b/boards/st/nucleo_f412zg/nucleo_f412zg.dts similarity index 100% rename from boards/arm/nucleo_f412zg/nucleo_f412zg.dts rename to boards/st/nucleo_f412zg/nucleo_f412zg.dts diff --git a/boards/arm/nucleo_f412zg/nucleo_f412zg.yaml b/boards/st/nucleo_f412zg/nucleo_f412zg.yaml similarity index 100% rename from boards/arm/nucleo_f412zg/nucleo_f412zg.yaml rename to boards/st/nucleo_f412zg/nucleo_f412zg.yaml diff --git a/boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig b/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig similarity index 84% rename from boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig rename to boards/st/nucleo_f412zg/nucleo_f412zg_defconfig index d9ce153a46b810..c729b83e3d0506 100644 --- a/boards/arm/nucleo_f412zg/nucleo_f412zg_defconfig +++ b/boards/st/nucleo_f412zg/nucleo_f412zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412ZX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f412zg/support/openocd.cfg b/boards/st/nucleo_f412zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f412zg/support/openocd.cfg rename to boards/st/nucleo_f412zg/support/openocd.cfg diff --git a/boards/st/nucleo_f413zh/Kconfig.defconfig b/boards/st/nucleo_f413zh/Kconfig.defconfig new file mode 100644 index 00000000000000..34fb8d56961576 --- /dev/null +++ b/boards/st/nucleo_f413zh/Kconfig.defconfig @@ -0,0 +1,18 @@ +# NUCLEO-144 F413ZH board configuration + +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F413ZH + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_ECM + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F413ZH diff --git a/boards/st/nucleo_f413zh/Kconfig.nucleo_f413zh b/boards/st/nucleo_f413zh/Kconfig.nucleo_f413zh new file mode 100644 index 00000000000000..7ca7fe10894b8b --- /dev/null +++ b/boards/st/nucleo_f413zh/Kconfig.nucleo_f413zh @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Florian Vaussard, HEIG-VD +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F413ZH + select SOC_STM32F413XX diff --git a/boards/arm/nucleo_f413zh/arduino_r3_connector.dtsi b/boards/st/nucleo_f413zh/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f413zh/arduino_r3_connector.dtsi rename to boards/st/nucleo_f413zh/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f413zh/board.cmake b/boards/st/nucleo_f413zh/board.cmake similarity index 100% rename from boards/arm/nucleo_f413zh/board.cmake rename to boards/st/nucleo_f413zh/board.cmake diff --git a/boards/st/nucleo_f413zh/board.yml b/boards/st/nucleo_f413zh/board.yml new file mode 100644 index 00000000000000..a372cec4b8ac24 --- /dev/null +++ b/boards/st/nucleo_f413zh/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f413zh + vendor: st + socs: + - name: stm32f413xx diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_left.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_morpho_right.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_left.jpg diff --git a/boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg b/boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg similarity index 100% rename from boards/arm/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg rename to boards/st/nucleo_f413zh/doc/img/nucleo_f413zh_zio_right.jpg diff --git a/boards/st/nucleo_f413zh/doc/index.rst b/boards/st/nucleo_f413zh/doc/index.rst new file mode 100644 index 00000000000000..c6452fb4456575 --- /dev/null +++ b/boards/st/nucleo_f413zh/doc/index.rst @@ -0,0 +1,174 @@ +.. _nucleo_f413zh_board: + +ST Nucleo F413ZH +################ + +Overview +******** + +The Nucleo F413ZH board features an ARM Cortex-M4 based STM32F413ZH MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F413ZH board: + +- STM32 microcontroller in LQFP144 package +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f413zh.jpg + :align: center + :alt: Nucleo F413ZH + +More information about the board can be found at the `Nucleo F413ZH website`_. + +Hardware +******** + +Nucleo F413ZH provides the following hardware components: + +- STM32F413ZHT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1.5 MB Flash +- 320 KB SRAM +- GPIO with external interrupt capability +- 2 12-bit ADC with 16 channels, with FIFO and burst support +- RTC +- 14 General purpose timers +- 2 watchdog timers (independent and window) +- SysTick timer +- USART/UART (10) +- I2C (4) +- SPI (5) +- SDIO +- USB 2.0 OTG FS +- DMA Controller +- CRC calculation unit + +More information about STM32F413ZH can be found here: + +- `STM32F413ZH on www.st.com`_ +- `STM32F413/423 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_413zh board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f413zh/nucleo_f413zh_defconfig` + + +Connections and IOs +=================== + +Nucleo F413ZH Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f413zh_zio_left.jpg + :align: center + :alt: Nucleo F413ZH ZIO connectors (left) +.. image:: img/nucleo_f413zh_zio_right.jpg + :align: center + :alt: Nucleo F413ZH ZIO connectors (right) +.. image:: img/nucleo_f413zh_morpho_left.jpg + :align: center + :alt: Nucleo F413ZH Morpho connectors (left) +.. image:: img/nucleo_f413zh_morpho_right.jpg + :align: center + :alt: Nucleo F413ZH Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PA0 +- USB_DM : PA11 +- USB_DP : PA12 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 + +System Clock +------------ + +Nucleo F413ZH System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 96MHz, +driven by 8MHz high speed external clock. + +Serial Port +----------- + +Nucleo F413ZH board has 10 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + +USB +=== +Nucleo F413ZH board has a USB OTG dual-role device (DRD) controller that +supports both device and host functions through its micro USB connector +(USB USER). Only USB device function is supported in Zephyr at the moment. + + +Programming and Debugging +************************* + +Nucleo F413ZH board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + + +.. _Nucleo F413ZH website: + https://www.st.com/en/evaluation-tools/nucleo-f413zh.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F413ZH on www.st.com: + https://www.st.com/en/microcontrollers/stm32f413zh.html + +.. _STM32F413/423 reference manual: + https://www.st.com/resource/en/reference_manual/dm00305666.pdf diff --git a/boards/arm/nucleo_f413zh/nucleo_f413zh.dts b/boards/st/nucleo_f413zh/nucleo_f413zh.dts similarity index 100% rename from boards/arm/nucleo_f413zh/nucleo_f413zh.dts rename to boards/st/nucleo_f413zh/nucleo_f413zh.dts diff --git a/boards/arm/nucleo_f413zh/nucleo_f413zh.yaml b/boards/st/nucleo_f413zh/nucleo_f413zh.yaml similarity index 100% rename from boards/arm/nucleo_f413zh/nucleo_f413zh.yaml rename to boards/st/nucleo_f413zh/nucleo_f413zh.yaml diff --git a/boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig b/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig similarity index 84% rename from boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig rename to boards/st/nucleo_f413zh/nucleo_f413zh_defconfig index 1b7b52cb5b75fb..c729b83e3d0506 100644 --- a/boards/arm/nucleo_f413zh/nucleo_f413zh_defconfig +++ b/boards/st/nucleo_f413zh/nucleo_f413zh_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F413XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f413zh/support/openocd.cfg b/boards/st/nucleo_f413zh/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f413zh/support/openocd.cfg rename to boards/st/nucleo_f413zh/support/openocd.cfg diff --git a/boards/st/nucleo_f429zi/Kconfig.defconfig b/boards/st/nucleo_f429zi/Kconfig.defconfig new file mode 100644 index 00000000000000..2198e75674fca2 --- /dev/null +++ b/boards/st/nucleo_f429zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# NUCLEO-144 F429ZI board configuration + +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F429ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F429ZI diff --git a/boards/st/nucleo_f429zi/Kconfig.nucleo_f429zi b/boards/st/nucleo_f429zi/Kconfig.nucleo_f429zi new file mode 100644 index 00000000000000..baed70d72d71c1 --- /dev/null +++ b/boards/st/nucleo_f429zi/Kconfig.nucleo_f429zi @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F429ZI + select SOC_STM32F429XX diff --git a/boards/arm/nucleo_f429zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f429zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f429zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_f429zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f429zi/board.cmake b/boards/st/nucleo_f429zi/board.cmake similarity index 100% rename from boards/arm/nucleo_f429zi/board.cmake rename to boards/st/nucleo_f429zi/board.cmake diff --git a/boards/st/nucleo_f429zi/board.yml b/boards/st/nucleo_f429zi/board.yml new file mode 100644 index 00000000000000..ecf8e93828bfa2 --- /dev/null +++ b/boards/st/nucleo_f429zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f429zi + vendor: st + socs: + - name: stm32f429xx diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn11.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn12.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn7.jpg diff --git a/boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg b/boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg similarity index 100% rename from boards/arm/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg rename to boards/st/nucleo_f429zi/doc/img/nucleo_f429zi_cn8.jpg diff --git a/boards/st/nucleo_f429zi/doc/index.rst b/boards/st/nucleo_f429zi/doc/index.rst new file mode 100644 index 00000000000000..9e795649a4ebfa --- /dev/null +++ b/boards/st/nucleo_f429zi/doc/index.rst @@ -0,0 +1,217 @@ +.. _nucleo_f429zi_board: + +ST Nucleo F429ZI +################ + +Overview +******** + +The Nucleo F429ZI board features an ARM Cortex-M4 based STM32F429ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F429ZI board: + +- STM32 microcontroller in LQFP144 package +- LSE crystal: 32.768 kHz crystal oscillator +- USB OTG +- Ethernet compliant with IEEE-802.3-2002 +- Two types of extension resources: + + - ST Zio connector including: support for Arduino* Uno V3 connectivity + (A0 to A5, D0 to D15) and additional signals exposing a wide range of + peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5 V from ST-LINK/V2-1 USB VBUS + - External power sources: 3.3 V and 7 - 12 V on ST Zio or ST morpho + connectors, 5 V on ST morpho connector + +- Three user LEDs +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f429zi.jpg + :align: center + :alt: Nucleo F429ZI + +More information about the board can be found at the `Nucleo F429ZI website`_. + +Hardware +******** + +The Nucleo F429ZI provides the following hardware components: + +- STM32F429ZIT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 256+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (4/4) +- I2C (3) +- SPI (6) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F429ZI can be found here: + +- `STM32F429ZI on www.st.com`_ +- `STM32F429 reference manual`_ +- `STM32F429 datasheet`_ + +Supported Features +================== + +The Zephyr nucleo_f429zi board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f429zi/nucleo_f429zi_defconfig` + + +Connections and IOs +=================== + +The Nucleo F429ZI Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f429zi_cn8.jpg + :align: center + :alt: Nucleo F429ZI ZIO connectors (left) +.. image:: img/nucleo_f429zi_cn7.jpg + :align: center + :alt: Nucleo F429ZI ZIO connectors (right) +.. image:: img/nucleo_f429zi_cn11.jpg + :align: center + :alt: Nucleo F429ZI Morpho connectors (left) +.. image:: img/nucleo_f429zi_cn12.jpg + :align: center + :alt: Nucleo F429ZI Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F429ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PA7 (Arduino SPI) +- PWM_2_CH1 : PE13 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- USB DM : PA11 +- USB DP : PA12 +- ADC1 : PA0 + +System Clock +------------ + +The Nucleo F429ZI System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default System clock is driven by PLL clock at 180MHz, +driven by an 8MHz high speed external clock. + +Serial Port +----------- + +The Nucleo F429ZI board has 8 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +The Nucleo F429ZI board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flash partitions for MCUBoot bootloader +*************************************** + +The on-board STM32F429ZI MCU has 2MBs of internal flash memory. To use `MCUboot`_, +define a :ref:`Zephyr partition table ` for the flash memory in +its devicetree file ``nucleo_f429zi.dts``. As a reference, a partition table for +MCUBoot is already defined in the devicetree file, with these settings: + +- `MCUBoot`_ bootloader partition takes 64K bytes. +- Zephyr settings partition takes 64K bytes. +- Application image takes 256K bytes in Slot 0 partition. +- Updating image takes another 256K bytes in Slot 1 partition. +- A scratch partition with 128K is required for image swap. + +A specific application can adjust each partition size based on its needs. + + +.. _Nucleo F429ZI website: + https://www.st.com/en/evaluation-tools/nucleo-f429zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F429ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32f429zi.html + +.. _STM32F429 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031020.pdf + +.. _STM32F429 datasheet: + https://www.st.com/resource/en/datasheet/DM00071990.pdf + +.. _MCUBoot: + https://github.com/JuulLabs-OSS/mcuboot/blob/master/README.md diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi.dts b/boards/st/nucleo_f429zi/nucleo_f429zi.dts similarity index 100% rename from boards/arm/nucleo_f429zi/nucleo_f429zi.dts rename to boards/st/nucleo_f429zi/nucleo_f429zi.dts diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi.yaml b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml similarity index 100% rename from boards/arm/nucleo_f429zi/nucleo_f429zi.yaml rename to boards/st/nucleo_f429zi/nucleo_f429zi.yaml diff --git a/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig b/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig similarity index 85% rename from boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig rename to boards/st/nucleo_f429zi/nucleo_f429zi_defconfig index 478a485246cbf8..750f99bdff3b71 100644 --- a/boards/arm/nucleo_f429zi/nucleo_f429zi_defconfig +++ b/boards/st/nucleo_f429zi/nucleo_f429zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F429XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f429zi/support/openocd.cfg b/boards/st/nucleo_f429zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f429zi/support/openocd.cfg rename to boards/st/nucleo_f429zi/support/openocd.cfg diff --git a/boards/st/nucleo_f446re/Kconfig.defconfig b/boards/st/nucleo_f446re/Kconfig.defconfig new file mode 100644 index 00000000000000..4ccbf9d1580770 --- /dev/null +++ b/boards/st/nucleo_f446re/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F446RE Nucleo board configuration + +# Copyright (c) 2018 Philémon Jaermann +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F446RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F446RE diff --git a/boards/st/nucleo_f446re/Kconfig.nucleo_f446re b/boards/st/nucleo_f446re/Kconfig.nucleo_f446re new file mode 100644 index 00000000000000..72bfcd374593a1 --- /dev/null +++ b/boards/st/nucleo_f446re/Kconfig.nucleo_f446re @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Philémon Jaermann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F446RE + select SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446re/arduino_r3_connector.dtsi b/boards/st/nucleo_f446re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f446re/arduino_r3_connector.dtsi rename to boards/st/nucleo_f446re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f446re/board.cmake b/boards/st/nucleo_f446re/board.cmake similarity index 100% rename from boards/arm/nucleo_f446re/board.cmake rename to boards/st/nucleo_f446re/board.cmake diff --git a/boards/st/nucleo_f446re/board.yml b/boards/st/nucleo_f446re/board.yml new file mode 100644 index 00000000000000..d68a45990b84c0 --- /dev/null +++ b/boards/st/nucleo_f446re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f446re + vendor: st + socs: + - name: stm32f446xx diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_left.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_arduino_top_right.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_left.jpg diff --git a/boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg b/boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg similarity index 100% rename from boards/arm/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg rename to boards/st/nucleo_f446re/doc/img/nucleo_f446re_morpho_top_right.jpg diff --git a/boards/st/nucleo_f446re/doc/index.rst b/boards/st/nucleo_f446re/doc/index.rst new file mode 100644 index 00000000000000..28fe7699e608a6 --- /dev/null +++ b/boards/st/nucleo_f446re/doc/index.rst @@ -0,0 +1,226 @@ +.. _nucleo_f446re_board: + +ST Nucleo F446RE +################ + +Overview +******** + +The Nucleo F446RE board features an ARM Cortex-M4 based STM32F446RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F446RE board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f446re.jpg + :align: center + :alt: Nucleo F446RE + +More information about the board can be found at the `Nucleo F446RE website`_. + +Hardware +******** + +Nucleo F446RE provides the following hardware components: + +- STM32F446RET6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Adaptive real-time accelerator (ART Accelerator) +- 180 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- 10 General purpose timers +- 2 Advanced control timers +- 2 basic timers +- SPI(4) +- I2C(3) +- USART(4) +- UART(2) +- USB OTG Full Speed and High Speed +- CAN(2) +- SAI(2) +- SPDIF_Rx(1) +- HDMI_CEC(1) +- Quad SPI(1) +- Camera Interface +- GPIO(50) with external interrupt capability +- 12-bit ADC(3) with 16 channels +- 12-bit DAC with 2 channels + +More information about STM32F446RE can be found here: + +- `STM32F446RE on www.st.com`_ +- `STM32F446 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f446re board configuration supports the following hardware features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| CAN 1/2 | on-chip | Controller Area Network | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f446re/nucleo_f446re_defconfig` + + +Connections and IOs +=================== + +Nucleo F446RE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f446re_arduino_top_left.jpg + :align: center + :alt: Nucleo F446RE Arduino connectors (top left) +.. image:: img/nucleo_f446re_arduino_top_right.jpg + :align: center + :alt: Nucleo F446RE Arduino connectors (top right) +.. image:: img/nucleo_f446re_morpho_top_left.jpg + :align: center + :alt: Nucleo F446RE Morpho connectors (top left) +.. image:: img/nucleo_f446re_morpho_top_right.jpg + :align: center + :alt: Nucleo F446RE Morpho connectors (top right) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PC13 +- LD2 : PA5 +- I2C1_SDA : PB9 +- I2C1_SCL : PB8 +- I2C2_SDA : PB3 +- I2C2_SCL : PB10 +- I2C3_SDA : PB4 +- I2C3_SCL : PA8 + +System Clock +------------ + +Nucleo F446RE System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, +driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F446RE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB45`` jumper on the back side of the board. + +Controller Area Network +----------------------- + +The TX/RX wires connected with D14/D15 of CN5 connector. Thus the board can be +used with `RS485 CAN Shield`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f446re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F446RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F446RE +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446re + :maybe-skip-config: + :goals: debug + +.. _Nucleo F446RE website: + https://www.st.com/en/evaluation-tools/nucleo-f446re.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F446RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f446re.html + +.. _STM32F446 reference manual: + https://www.st.com/resource/en/reference_manual/dm00135183.pdf + +.. _RS485 CAN Shield: + https://www.waveshare.com/wiki/RS485_CAN_Shield diff --git a/boards/arm/nucleo_f446re/nucleo_f446re.dts b/boards/st/nucleo_f446re/nucleo_f446re.dts similarity index 100% rename from boards/arm/nucleo_f446re/nucleo_f446re.dts rename to boards/st/nucleo_f446re/nucleo_f446re.dts diff --git a/boards/arm/nucleo_f446re/nucleo_f446re.yaml b/boards/st/nucleo_f446re/nucleo_f446re.yaml similarity index 100% rename from boards/arm/nucleo_f446re/nucleo_f446re.yaml rename to boards/st/nucleo_f446re/nucleo_f446re.yaml diff --git a/boards/arm/nucleo_f446re/nucleo_f446re_defconfig b/boards/st/nucleo_f446re/nucleo_f446re_defconfig similarity index 84% rename from boards/arm/nucleo_f446re/nucleo_f446re_defconfig rename to boards/st/nucleo_f446re/nucleo_f446re_defconfig index a9e0141c1258c9..c729b83e3d0506 100644 --- a/boards/arm/nucleo_f446re/nucleo_f446re_defconfig +++ b/boards/st/nucleo_f446re/nucleo_f446re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F446XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f446re/st_morpho_connector.dtsi b/boards/st/nucleo_f446re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f446re/st_morpho_connector.dtsi rename to boards/st/nucleo_f446re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_f446re/support/openocd.cfg b/boards/st/nucleo_f446re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f446re/support/openocd.cfg rename to boards/st/nucleo_f446re/support/openocd.cfg diff --git a/boards/st/nucleo_f446ze/Kconfig.defconfig b/boards/st/nucleo_f446ze/Kconfig.defconfig new file mode 100644 index 00000000000000..0023ff8bde8e35 --- /dev/null +++ b/boards/st/nucleo_f446ze/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F446ZE Nucleo board configuration + +# Copyright (c) 2021 Tom Owen +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F446ZE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F446ZE diff --git a/boards/st/nucleo_f446ze/Kconfig.nucleo_f446ze b/boards/st/nucleo_f446ze/Kconfig.nucleo_f446ze new file mode 100644 index 00000000000000..13ff942a56762b --- /dev/null +++ b/boards/st/nucleo_f446ze/Kconfig.nucleo_f446ze @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Tom Owen +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F446ZE + select SOC_STM32F446XX diff --git a/boards/arm/nucleo_f446ze/arduino_r3_connector.dtsi b/boards/st/nucleo_f446ze/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f446ze/arduino_r3_connector.dtsi rename to boards/st/nucleo_f446ze/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f446ze/board.cmake b/boards/st/nucleo_f446ze/board.cmake similarity index 100% rename from boards/arm/nucleo_f446ze/board.cmake rename to boards/st/nucleo_f446ze/board.cmake diff --git a/boards/st/nucleo_f446ze/board.yml b/boards/st/nucleo_f446ze/board.yml new file mode 100644 index 00000000000000..eb577af456bd27 --- /dev/null +++ b/boards/st/nucleo_f446ze/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f446ze + vendor: st + socs: + - name: stm32f446xx diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_left_2019_8_29.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_morpho_right_2019_8_29.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_left_2019_8_29.jpg diff --git a/boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg b/boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg similarity index 100% rename from boards/arm/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg rename to boards/st/nucleo_f446ze/doc/img/nucleo_f446ze_zio_right_2019_8_29.jpg diff --git a/boards/st/nucleo_f446ze/doc/index.rst b/boards/st/nucleo_f446ze/doc/index.rst new file mode 100644 index 00000000000000..d99167db1596e3 --- /dev/null +++ b/boards/st/nucleo_f446ze/doc/index.rst @@ -0,0 +1,248 @@ +.. _nucleo_f446ze_board: + +ST Nucleo F446ZE +################ + + +Overview +******** + +The Nucleo F446ZE board features an ARM Cortex-M4 based STM32F446ZE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo F446ZE board: + +- STM32F446 microcontroller in QFP144 package +- Two types of extension resources: + + - ST zio support for Arduino™ Uno V3 connectivity (A0 to A5, D0 to D15) and additional signals exposing a wide range of peripherals + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- USB re-enumeration capability. Three different interfaces supported on USB: + - Virtual Com port + - Mass storage (USB Disk drive) for drag'n'drop programming + - Debug port +- Flexible board power supply: + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + - USB OTG + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_f446ze.jpg + :align: center + :alt: Nucleo F446ZE + +More information about the board can be found at the `Nucleo F446ZE website`_. + +Hardware +******** + +Nucleo F446ZE provides the following hardware components: + +- STM32F446ZET6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU +- Adaptive real-time accelerator (ART Accelerator) +- 180 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- 10 General purpose timers +- 2 Advanced control timers +- 2 basic timers +- SPI(4) +- I2C(4) +- USART(4) +- UART(2) +- USB OTG Full Speed and High Speed +- CAN(2) +- SAI(2) +- SPDIF_Rx(1) +- HDMI_CEC(1) +- Quad SPI(1) +- Camera Interface +- GPIO(50) with external interrupt capability +- 12-bit ADC(3) with 16 channels +- 12-bit DAC with 2 channels + +More information about STM32F446ZE can be found here: + +- `STM32F446ZE on www.st.com`_ +- `STM32F446 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_f446ze board configuration supports the following hardware features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| CAN 1/2 | on-chip | Controller Area Network | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | Analog Input | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | Analog Output | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f446ze/nucleo_f446ze_defconfig` + + +Connections and IOs +=================== + +Nucleo F446ZE Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_f446ze_zio_left_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Zio/Arduino connectors (left) +.. image:: img/nucleo_f446ze_zio_right_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Zio/Arduino connectors (right) +.. image:: img/nucleo_f446ze_morpho_left_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Morpho connectors (left) +.. image:: img/nucleo_f446ze_morpho_right_2019_8_29.jpg + :align: center + :alt: Nucleo F446ZE Morpho connectors (right) + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- UART_3_TX : PD8 +- UART_3_RX : PD9 +- USER_PB : PC13 +- LD0 : PB0 +- LD1 : PB7 +- LD2 : PB14 +- I2C1_SDA : PB9 +- I2C1_SCL : PB8 +- I2C2_SDA : PF0 +- I2C2_SCL : PF1 +- SPI1_CS : PD14 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- USB_DP : PA11 +- USB_DM : PA12 +- ADC1_IN0 : PA0 +- DAC_OUT1 : PA4 + + +System Clock +------------ + +Nucleo F446ZE System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default, the System clock is driven by the PLL clock at 84MHz, +driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F446ZE board has 2 UARTs and 4 USARTs. The Zephyr console output is assigned to USART3. +Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +Controller Area Network +----------------------- + +The TX/RX wires are connected with pins 25/27 of CN9 connector. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f446ze`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F446ZE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F446ZE +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446ze + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f446ze + :maybe-skip-config: + :goals: debug + +.. _Nucleo F446ZE website: + https://www.st.com/en/evaluation-tools/nucleo-f446ze.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um1974-stm32-nucleo144-boards-mb1137-stmicroelectronics.pdf + +.. _STM32F446ZE on www.st.com: + https://www.st.com/en/microcontrollers/stm32f446ze.html + +.. _STM32F446 reference manual: + https://www.st.com/resource/en/reference_manual/dm00135183.pdf diff --git a/boards/arm/nucleo_f446ze/nucleo_f446ze.dts b/boards/st/nucleo_f446ze/nucleo_f446ze.dts similarity index 100% rename from boards/arm/nucleo_f446ze/nucleo_f446ze.dts rename to boards/st/nucleo_f446ze/nucleo_f446ze.dts diff --git a/boards/arm/nucleo_f446ze/nucleo_f446ze.yaml b/boards/st/nucleo_f446ze/nucleo_f446ze.yaml similarity index 100% rename from boards/arm/nucleo_f446ze/nucleo_f446ze.yaml rename to boards/st/nucleo_f446ze/nucleo_f446ze.yaml diff --git a/boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig b/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig similarity index 84% rename from boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig rename to boards/st/nucleo_f446ze/nucleo_f446ze_defconfig index a9e0141c1258c9..c729b83e3d0506 100644 --- a/boards/arm/nucleo_f446ze/nucleo_f446ze_defconfig +++ b/boards/st/nucleo_f446ze/nucleo_f446ze_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F446XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f446ze/support/openocd.cfg b/boards/st/nucleo_f446ze/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f446ze/support/openocd.cfg rename to boards/st/nucleo_f446ze/support/openocd.cfg diff --git a/boards/st/nucleo_f722ze/Kconfig.defconfig b/boards/st/nucleo_f722ze/Kconfig.defconfig new file mode 100644 index 00000000000000..475a7e465f65f1 --- /dev/null +++ b/boards/st/nucleo_f722ze/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F722ZE Nucleo board configuration +# +# Copyright (c) 2023 Evan Perry Grove +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F722ZE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_F722ZE diff --git a/boards/st/nucleo_f722ze/Kconfig.nucleo_f722ze b/boards/st/nucleo_f722ze/Kconfig.nucleo_f722ze new file mode 100644 index 00000000000000..12cc5a5d418815 --- /dev/null +++ b/boards/st/nucleo_f722ze/Kconfig.nucleo_f722ze @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Evan Perry Grove +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F722ZE + select SOC_STM32F722XX diff --git a/boards/arm/nucleo_f722ze/arduino_r3_connector.dtsi b/boards/st/nucleo_f722ze/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f722ze/arduino_r3_connector.dtsi rename to boards/st/nucleo_f722ze/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f722ze/board.cmake b/boards/st/nucleo_f722ze/board.cmake similarity index 100% rename from boards/arm/nucleo_f722ze/board.cmake rename to boards/st/nucleo_f722ze/board.cmake diff --git a/boards/st/nucleo_f722ze/board.yml b/boards/st/nucleo_f722ze/board.yml new file mode 100644 index 00000000000000..793193bc2ca1a2 --- /dev/null +++ b/boards/st/nucleo_f722ze/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f722ze + vendor: st + socs: + - name: stm32f722xx diff --git a/boards/arm/nucleo_f722ze/doc/img/nucleo_f722ze.jpg b/boards/st/nucleo_f722ze/doc/img/nucleo_f722ze.jpg similarity index 100% rename from boards/arm/nucleo_f722ze/doc/img/nucleo_f722ze.jpg rename to boards/st/nucleo_f722ze/doc/img/nucleo_f722ze.jpg diff --git a/boards/arm/nucleo_f722ze/doc/index.rst b/boards/st/nucleo_f722ze/doc/index.rst similarity index 100% rename from boards/arm/nucleo_f722ze/doc/index.rst rename to boards/st/nucleo_f722ze/doc/index.rst diff --git a/boards/arm/nucleo_f722ze/nucleo_f722ze.dts b/boards/st/nucleo_f722ze/nucleo_f722ze.dts similarity index 100% rename from boards/arm/nucleo_f722ze/nucleo_f722ze.dts rename to boards/st/nucleo_f722ze/nucleo_f722ze.dts diff --git a/boards/arm/nucleo_f722ze/nucleo_f722ze.yaml b/boards/st/nucleo_f722ze/nucleo_f722ze.yaml similarity index 100% rename from boards/arm/nucleo_f722ze/nucleo_f722ze.yaml rename to boards/st/nucleo_f722ze/nucleo_f722ze.yaml diff --git a/boards/arm/nucleo_f722ze/nucleo_f722ze_defconfig b/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig similarity index 86% rename from boards/arm/nucleo_f722ze/nucleo_f722ze_defconfig rename to boards/st/nucleo_f722ze/nucleo_f722ze_defconfig index 345694efd8088b..86e44f22e552ee 100644 --- a/boards/arm/nucleo_f722ze/nucleo_f722ze_defconfig +++ b/boards/st/nucleo_f722ze/nucleo_f722ze_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F722XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f722ze/support/openocd.cfg b/boards/st/nucleo_f722ze/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f722ze/support/openocd.cfg rename to boards/st/nucleo_f722ze/support/openocd.cfg diff --git a/boards/st/nucleo_f746zg/Kconfig.defconfig b/boards/st/nucleo_f746zg/Kconfig.defconfig new file mode 100644 index 00000000000000..7cf77f7d6f0a35 --- /dev/null +++ b/boards/st/nucleo_f746zg/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32F746ZG Nucleo board configuration + +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F746ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F746ZG diff --git a/boards/st/nucleo_f746zg/Kconfig.nucleo_f746zg b/boards/st/nucleo_f746zg/Kconfig.nucleo_f746zg new file mode 100644 index 00000000000000..89bf9f55bbecb3 --- /dev/null +++ b/boards/st/nucleo_f746zg/Kconfig.nucleo_f746zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F746ZG + select SOC_STM32F746XX diff --git a/boards/arm/nucleo_f746zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f746zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f746zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f746zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f746zg/board.cmake b/boards/st/nucleo_f746zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f746zg/board.cmake rename to boards/st/nucleo_f746zg/board.cmake diff --git a/boards/st/nucleo_f746zg/board.yml b/boards/st/nucleo_f746zg/board.yml new file mode 100644 index 00000000000000..1df68107ece55d --- /dev/null +++ b/boards/st/nucleo_f746zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f746zg + vendor: st + socs: + - name: stm32f746xx diff --git a/boards/arm/nucleo_f746zg/doc/img/nucleo_f746zg.jpg b/boards/st/nucleo_f746zg/doc/img/nucleo_f746zg.jpg similarity index 100% rename from boards/arm/nucleo_f746zg/doc/img/nucleo_f746zg.jpg rename to boards/st/nucleo_f746zg/doc/img/nucleo_f746zg.jpg diff --git a/boards/st/nucleo_f746zg/doc/index.rst b/boards/st/nucleo_f746zg/doc/index.rst new file mode 100644 index 00000000000000..cc1ca6d95ed714 --- /dev/null +++ b/boards/st/nucleo_f746zg/doc/index.rst @@ -0,0 +1,235 @@ +.. _nucleo_f746zg_board: + +ST Nucleo F746ZG +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS significantly reduces power +consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_f746zg.jpg + :align: center + :alt: Nucleo F746ZG + +More information about the board can be found at the `Nucleo F746ZG website`_. + +Hardware +******** + +Nucleo F746ZG provides the following hardware components: + +- STM32F746ZG in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- ART Accelerator +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 320 KB SRAM +- 16-bit timers(10) +- 32-bit timers(2) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO(up to 168) with external interrupt capability +- 12-bit ADC(3) with 24 channels / 2.4 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_f746zg board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-------------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f746zg/nucleo_f746zg_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F746ZG board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino UART) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB DM : PA11 +- USB DP : PA12 +- I2C : PB8, PB9 +- PWM : PE13 +- SPI : PD14, PA5, PA6, PA7 +- ADC1_IN0 : PA0 +- DAC1_OUT1 : PA4 + +Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH +device on pin PA7. + +System Clock +------------ + +Nucleo F746ZG System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F746ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +Programming and Debugging +************************* + +Applications for the ``nucleo_f746zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo F746ZG +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f746zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_f746zg + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f746zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo F746ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f746zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32F746ZG on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746zg.html + +.. _STM32F746 reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg.dts b/boards/st/nucleo_f746zg/nucleo_f746zg.dts similarity index 100% rename from boards/arm/nucleo_f746zg/nucleo_f746zg.dts rename to boards/st/nucleo_f746zg/nucleo_f746zg.dts diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg.yaml b/boards/st/nucleo_f746zg/nucleo_f746zg.yaml similarity index 100% rename from boards/arm/nucleo_f746zg/nucleo_f746zg.yaml rename to boards/st/nucleo_f746zg/nucleo_f746zg.yaml diff --git a/boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig b/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig similarity index 85% rename from boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig rename to boards/st/nucleo_f746zg/nucleo_f746zg_defconfig index e1eb901f61c9cc..261e47c2d53c4a 100644 --- a/boards/arm/nucleo_f746zg/nucleo_f746zg_defconfig +++ b/boards/st/nucleo_f746zg/nucleo_f746zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F746XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f746zg/support/openocd.cfg b/boards/st/nucleo_f746zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f746zg/support/openocd.cfg rename to boards/st/nucleo_f746zg/support/openocd.cfg diff --git a/boards/st/nucleo_f756zg/Kconfig.defconfig b/boards/st/nucleo_f756zg/Kconfig.defconfig new file mode 100644 index 00000000000000..4ca0a6ee3a0964 --- /dev/null +++ b/boards/st/nucleo_f756zg/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32F756ZG Nucleo board configuration + +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F756ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F756ZG diff --git a/boards/st/nucleo_f756zg/Kconfig.nucleo_f756zg b/boards/st/nucleo_f756zg/Kconfig.nucleo_f756zg new file mode 100644 index 00000000000000..3f8154cdebc382 --- /dev/null +++ b/boards/st/nucleo_f756zg/Kconfig.nucleo_f756zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018 AJ Palmer +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F756ZG + select SOC_STM32F756XX diff --git a/boards/arm/nucleo_f756zg/arduino_r3_connector.dtsi b/boards/st/nucleo_f756zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f756zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_f756zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f756zg/board.cmake b/boards/st/nucleo_f756zg/board.cmake similarity index 100% rename from boards/arm/nucleo_f756zg/board.cmake rename to boards/st/nucleo_f756zg/board.cmake diff --git a/boards/st/nucleo_f756zg/board.yml b/boards/st/nucleo_f756zg/board.yml new file mode 100644 index 00000000000000..791d7601754497 --- /dev/null +++ b/boards/st/nucleo_f756zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f756zg + vendor: st + socs: + - name: stm32f756xx diff --git a/boards/arm/nucleo_f756zg/doc/img/nucleo_f756zg.jpg b/boards/st/nucleo_f756zg/doc/img/nucleo_f756zg.jpg similarity index 100% rename from boards/arm/nucleo_f756zg/doc/img/nucleo_f756zg.jpg rename to boards/st/nucleo_f756zg/doc/img/nucleo_f756zg.jpg diff --git a/boards/st/nucleo_f756zg/doc/index.rst b/boards/st/nucleo_f756zg/doc/index.rst new file mode 100644 index 00000000000000..fd8b5f259c3062 --- /dev/null +++ b/boards/st/nucleo_f756zg/doc/index.rst @@ -0,0 +1,218 @@ +.. _nucleo_f756zg_board: + +ST Nucleo F756ZG +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS significantly reduces power +consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration + capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the +- STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_f756zg.jpg + :align: center + :alt: Nucleo F756ZG + +More information about the board can be found at the `Nucleo F756ZG website`_. + +Hardware +******** + +Nucleo F756ZG provides the following hardware components: + +- STM32F756ZG in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- ART Accelerator +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 320 KB SRAM +- 16-bit timers(10) +- 32-bit timers(2) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO(up to 168) with external interrupt capability +- 12-bit ADC(3) with 24 channels / 2.4 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_f756zg board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f756zg/nucleo_f756zg_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F756ZG board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino UART) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB DM : PA11 +- USB DP : PA12 +- I2C : PB8, PB9 +- PWM : PE13 +- SPI : PD14, PA5, PA6, PA7 + +Note. The Arduino Uno v3 specified SPI device conflicts with the on-board ETH +device on pin PA7. + +System Clock +------------ + +Nucleo F756ZG System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F756ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f756zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo F756ZG +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f756zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_f756zg + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f756zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo F756ZG website: + https://www.st.com/en/evaluation-tools/nucleo-f756zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32F756ZG on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f756zg.html + +.. _STM32F756 reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/nucleo_f756zg/nucleo_f756zg.dts b/boards/st/nucleo_f756zg/nucleo_f756zg.dts similarity index 100% rename from boards/arm/nucleo_f756zg/nucleo_f756zg.dts rename to boards/st/nucleo_f756zg/nucleo_f756zg.dts diff --git a/boards/arm/nucleo_f756zg/nucleo_f756zg.yaml b/boards/st/nucleo_f756zg/nucleo_f756zg.yaml similarity index 100% rename from boards/arm/nucleo_f756zg/nucleo_f756zg.yaml rename to boards/st/nucleo_f756zg/nucleo_f756zg.yaml diff --git a/boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig b/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig similarity index 85% rename from boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig rename to boards/st/nucleo_f756zg/nucleo_f756zg_defconfig index 6f89a9784b9ed7..261e47c2d53c4a 100644 --- a/boards/arm/nucleo_f756zg/nucleo_f756zg_defconfig +++ b/boards/st/nucleo_f756zg/nucleo_f756zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F756XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f756zg/support/openocd.cfg b/boards/st/nucleo_f756zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f756zg/support/openocd.cfg rename to boards/st/nucleo_f756zg/support/openocd.cfg diff --git a/boards/st/nucleo_f767zi/Kconfig.defconfig b/boards/st/nucleo_f767zi/Kconfig.defconfig new file mode 100644 index 00000000000000..45850f2d06d817 --- /dev/null +++ b/boards/st/nucleo_f767zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32F767ZI Nucleo board configuration + +# Copyright (c) 2019 Roland Ma +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_F767ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_F767ZI diff --git a/boards/st/nucleo_f767zi/Kconfig.nucleo_f767zi b/boards/st/nucleo_f767zi/Kconfig.nucleo_f767zi new file mode 100644 index 00000000000000..e14bf165a8f132 --- /dev/null +++ b/boards/st/nucleo_f767zi/Kconfig.nucleo_f767zi @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Roland Ma +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_F767ZI + select SOC_STM32F767XX diff --git a/boards/arm/nucleo_f767zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f767zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_f767zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_f767zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_f767zi/board.cmake b/boards/st/nucleo_f767zi/board.cmake similarity index 100% rename from boards/arm/nucleo_f767zi/board.cmake rename to boards/st/nucleo_f767zi/board.cmake diff --git a/boards/st/nucleo_f767zi/board.yml b/boards/st/nucleo_f767zi/board.yml new file mode 100644 index 00000000000000..810b80a5fdcbcb --- /dev/null +++ b/boards/st/nucleo_f767zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_f767zi + vendor: st + socs: + - name: stm32f767xx diff --git a/boards/arm/nucleo_f767zi/doc/img/nucleo_f767zi.jpg b/boards/st/nucleo_f767zi/doc/img/nucleo_f767zi.jpg similarity index 100% rename from boards/arm/nucleo_f767zi/doc/img/nucleo_f767zi.jpg rename to boards/st/nucleo_f767zi/doc/img/nucleo_f767zi.jpg diff --git a/boards/st/nucleo_f767zi/doc/index.rst b/boards/st/nucleo_f767zi/doc/index.rst new file mode 100644 index 00000000000000..8500f7fd3f17af --- /dev/null +++ b/boards/st/nucleo_f767zi/doc/index.rst @@ -0,0 +1,236 @@ +.. _nucleo_f767zi_board: + +ST Nucleo F767ZI +################ + +Overview +******** + +The STM32 Nucleo-144 F767ZI boards offer combinations of performance and +power that provide an affordable and flexible way for users to build +prototypes and try out new concepts. For compatible boards, the SMPS +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_f767zi.jpg + :align: center + :alt: Nucleo F767ZI + +More information about the board can be found at the `Nucleo F767ZI website`_. + +Hardware +******** + +Nucleo F767ZI provides the following hardware components: + +- STM32F767ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- ART Accelerator +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 2 MB Flash +- 512 KB SRAM +- 16-bit timers(10) +- 32-bit timers(2) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO(up to 168) with external interrupt capability +- 12-bit ADC(3) with 24 channels / 2.4 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_f767zi board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet (*) | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ + + +(*) nucleo_f767zi with soc cut-A (Device marking A) has some ethernet + instability (:github:`26519`). + Use of cut-Z is advised. + see restrictions errata: + https://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/23/a6/11/0b/30/24/46/a5/DM00257543/files/DM00257543.pdf/jcr:content/translations/en.DM00257543.pdf + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_f767zi/nucleo_f767zi_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo F767ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_2 TX/RX/RTS/CTS : PD5/PD6/PD4/PD3 +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino UART) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- USB DM : PA11 +- USB DP : PA12 +- I2C : PB8, PB9 +- PWM : PE13 +- SPI : PD14, PA5, PA6, PA7 + +.. note:: + The Arduino Uno v3 specified SPI device conflicts with the on-board ETH + device on pin PA7. + +System Clock +------------ + +Nucleo F767ZI System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 72MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo F767ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_f767zi`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo F767ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo F767ZI +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f767zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_f767zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_f767zi + :maybe-skip-config: + :goals: debug + +.. _Nucleo f767zi website: + https://www.st.com/en/evaluation-tools/nucleo-f767zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32f767zi on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x&/stm32f767zi.html + +.. _STM32F767 reference manual: + https://www.st.com/resource/en/reference_manual/DM00224583.pdf diff --git a/boards/arm/nucleo_f767zi/nucleo_f767zi.dts b/boards/st/nucleo_f767zi/nucleo_f767zi.dts similarity index 100% rename from boards/arm/nucleo_f767zi/nucleo_f767zi.dts rename to boards/st/nucleo_f767zi/nucleo_f767zi.dts diff --git a/boards/arm/nucleo_f767zi/nucleo_f767zi.yaml b/boards/st/nucleo_f767zi/nucleo_f767zi.yaml similarity index 100% rename from boards/arm/nucleo_f767zi/nucleo_f767zi.yaml rename to boards/st/nucleo_f767zi/nucleo_f767zi.yaml diff --git a/boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig b/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig similarity index 85% rename from boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig rename to boards/st/nucleo_f767zi/nucleo_f767zi_defconfig index df549434139acf..261e47c2d53c4a 100644 --- a/boards/arm/nucleo_f767zi/nucleo_f767zi_defconfig +++ b/boards/st/nucleo_f767zi/nucleo_f767zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F767XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_f767zi/support/openocd.cfg b/boards/st/nucleo_f767zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_f767zi/support/openocd.cfg rename to boards/st/nucleo_f767zi/support/openocd.cfg diff --git a/boards/st/nucleo_g031k8/Kconfig.defconfig b/boards/st/nucleo_g031k8/Kconfig.defconfig new file mode 100644 index 00000000000000..2c6c84ed50d9eb --- /dev/null +++ b/boards/st/nucleo_g031k8/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-32 development board with STM32G031K8 MCU + +# Copyright (c) 2022 Joylab AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_G031K8 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_G031K8 diff --git a/boards/st/nucleo_g031k8/Kconfig.nucleo_g031k8 b/boards/st/nucleo_g031k8/Kconfig.nucleo_g031k8 new file mode 100644 index 00000000000000..b748af9991d980 --- /dev/null +++ b/boards/st/nucleo_g031k8/Kconfig.nucleo_g031k8 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Joylab AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G031K8 + select SOC_STM32G031XX diff --git a/boards/arm/nucleo_g031k8/arduino_nano_r3_connector.dtsi b/boards/st/nucleo_g031k8/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g031k8/arduino_nano_r3_connector.dtsi rename to boards/st/nucleo_g031k8/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/nucleo_g031k8/board.cmake b/boards/st/nucleo_g031k8/board.cmake similarity index 100% rename from boards/arm/nucleo_g031k8/board.cmake rename to boards/st/nucleo_g031k8/board.cmake diff --git a/boards/st/nucleo_g031k8/board.yml b/boards/st/nucleo_g031k8/board.yml new file mode 100644 index 00000000000000..690afd52fb0dd4 --- /dev/null +++ b/boards/st/nucleo_g031k8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g031k8 + vendor: st + socs: + - name: stm32g031xx diff --git a/boards/arm/nucleo_g031k8/doc/img/nucleo_g031k8.jpg b/boards/st/nucleo_g031k8/doc/img/nucleo_g031k8.jpg similarity index 100% rename from boards/arm/nucleo_g031k8/doc/img/nucleo_g031k8.jpg rename to boards/st/nucleo_g031k8/doc/img/nucleo_g031k8.jpg diff --git a/boards/st/nucleo_g031k8/doc/index.rst b/boards/st/nucleo_g031k8/doc/index.rst new file mode 100644 index 00000000000000..e140ac74040040 --- /dev/null +++ b/boards/st/nucleo_g031k8/doc/index.rst @@ -0,0 +1,168 @@ +.. _nucleo_g031k8_board: + +ST Nucleo G031K8 +################ + +Overview +******** +The STM32 Nucleo-32 board provides an affordable and flexible way for users to try +out new concepts and build prototypes by choosing from the various combinations of +performance and power consumption features, provided by the STM32 +microcontroller. + +The Arduino™ Nano V3 connectivity support allows the easy expansion of the +functionality of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo-32 board does not require any separate probe as it integrates the +ST-LINK debugger/programmer. + +The STM32 Nucleo-32 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + + +.. image:: img/nucleo_g031k8.jpg + :align: center + :alt: Nucleo G031K8 + +More information about the board can be found at the `Nucleo G031K8 website`_. + +Hardware +******** +Nucleo G031K8 provides the following hardware components: + +- STM32 microcontroller in 32-pin package featuring 64 Kbytes of Flash memory + and 8 Kbytes of SRAM. +- Extension resource: + + - Arduino* Nano V3 connectivity + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Current consumption measurement (IDD) + +- Four LEDs: + + - USB communication (LD1), power LED (LD2), user LED (LD3), + USB power fault LED (LD4) + +- One push-button: RESET + +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32G031K8 can be found in the +`STM32G0x1 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_g031k8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g031k8/nucleo_g031k8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C2 SCL/SDA : PA9/PA10 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PB3/PB4/PB5 (Arduino SPI) +- LD3 : PC6 + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g031k8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G031K8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo G031K8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g031k8 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g031k8 + :maybe-skip-config: + :goals: debug + +Restriction +*********** + +On some boards, the board reset line is not used by the controller. +Therefore the reset button, reset-pin and the ST-Link reset have no effect. +To enable those functionalities, the option byte NRST_mode in the User +Configuration needs to be changed from 2 to 1 or 3 - depending on the +requirements. + +References +********** + +.. target-notes:: + +.. _Nucleo G031K8 website: + https://www.st.com/en/evaluation-tools/nucleo-g031k8.html + +.. _STM32G0x1 reference manual: + https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/um2591-stm32g0-nucleo32-board-mb1455-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_g031k8/nucleo_g031k8.dts b/boards/st/nucleo_g031k8/nucleo_g031k8.dts similarity index 100% rename from boards/arm/nucleo_g031k8/nucleo_g031k8.dts rename to boards/st/nucleo_g031k8/nucleo_g031k8.dts diff --git a/boards/arm/nucleo_g031k8/nucleo_g031k8.yaml b/boards/st/nucleo_g031k8/nucleo_g031k8.yaml similarity index 100% rename from boards/arm/nucleo_g031k8/nucleo_g031k8.yaml rename to boards/st/nucleo_g031k8/nucleo_g031k8.yaml diff --git a/boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig b/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig similarity index 78% rename from boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig rename to boards/st/nucleo_g031k8/nucleo_g031k8_defconfig index e4a8706b596ea2..06484e88bea72c 100644 --- a/boards/arm/nucleo_g031k8/nucleo_g031k8_defconfig +++ b/boards/st/nucleo_g031k8/nucleo_g031k8_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y - -# Platform Configuration -CONFIG_SOC_STM32G031XX=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/nucleo_g031k8/support/openocd.cfg b/boards/st/nucleo_g031k8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g031k8/support/openocd.cfg rename to boards/st/nucleo_g031k8/support/openocd.cfg diff --git a/boards/st/nucleo_g070rb/Kconfig.nucleo_g070rb b/boards/st/nucleo_g070rb/Kconfig.nucleo_g070rb new file mode 100644 index 00000000000000..0465a3f42736c9 --- /dev/null +++ b/boards/st/nucleo_g070rb/Kconfig.nucleo_g070rb @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Marin Jurjević +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G070RB + select SOC_STM32G070XX diff --git a/boards/arm/nucleo_g070rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g070rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g070rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_g070rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g070rb/board.cmake b/boards/st/nucleo_g070rb/board.cmake similarity index 100% rename from boards/arm/nucleo_g070rb/board.cmake rename to boards/st/nucleo_g070rb/board.cmake diff --git a/boards/st/nucleo_g070rb/board.yml b/boards/st/nucleo_g070rb/board.yml new file mode 100644 index 00000000000000..88306b0d7f08cb --- /dev/null +++ b/boards/st/nucleo_g070rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g070rb + vendor: st + socs: + - name: stm32g070xx diff --git a/boards/arm/nucleo_g070rb/doc/img/nucleo_g070rb.jpg b/boards/st/nucleo_g070rb/doc/img/nucleo_g070rb.jpg similarity index 100% rename from boards/arm/nucleo_g070rb/doc/img/nucleo_g070rb.jpg rename to boards/st/nucleo_g070rb/doc/img/nucleo_g070rb.jpg diff --git a/boards/st/nucleo_g070rb/doc/index.rst b/boards/st/nucleo_g070rb/doc/index.rst new file mode 100644 index 00000000000000..b18525ee0ebf5d --- /dev/null +++ b/boards/st/nucleo_g070rb/doc/index.rst @@ -0,0 +1,191 @@ +.. _nucleo_g070rb_board: + +ST Nucleo G070RB +################ + +Overview +******** +The Nucleo G070RB board features an ARM Cortex-M0+ based STM32G070RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G070RB board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_g070rb.jpg + :align: center + :alt: Nucleo G070RB + +More information about the board can be found at the `Nucleo G070RB website`_. + +Hardware +******** +Nucleo G070RB provides the following hardware components: + +- STM32 microcontroller in LQFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD4), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32G070RB can be found here: + +- `G070RB on www.st.com`_ + +Supported Features +================== + +The Zephyr nucleo_g070rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arm memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g070rb/nucleo_g070rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PC4/PC5 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 +- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD4 : PA5 +- PWM : PA6 +- ADC1 IN0 : PA0 +- ADC1 IN1 : PA1 +- DAC1_OUT1 : PA4 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g070rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G070RB board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo G070RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g070rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g070rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo G070RB website: + https://www.st.com/en/evaluation-tools/nucleo-g070rb.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00452640.pdf + +.. _G070RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g070rb.html diff --git a/boards/arm/nucleo_g070rb/nucleo_g070rb.dts b/boards/st/nucleo_g070rb/nucleo_g070rb.dts similarity index 100% rename from boards/arm/nucleo_g070rb/nucleo_g070rb.dts rename to boards/st/nucleo_g070rb/nucleo_g070rb.dts diff --git a/boards/arm/nucleo_g070rb/nucleo_g070rb.yaml b/boards/st/nucleo_g070rb/nucleo_g070rb.yaml similarity index 100% rename from boards/arm/nucleo_g070rb/nucleo_g070rb.yaml rename to boards/st/nucleo_g070rb/nucleo_g070rb.yaml diff --git a/boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig b/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig similarity index 75% rename from boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig rename to boards/st/nucleo_g070rb/nucleo_g070rb_defconfig index cf5cff7fe61a24..0055481a2e8f4a 100644 --- a/boards/arm/nucleo_g070rb/nucleo_g070rb_defconfig +++ b/boards/st/nucleo_g070rb/nucleo_g070rb_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G070XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_g070rb/support/openocd.cfg b/boards/st/nucleo_g070rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g070rb/support/openocd.cfg rename to boards/st/nucleo_g070rb/support/openocd.cfg diff --git a/boards/st/nucleo_g071rb/Kconfig.nucleo_g071rb b/boards/st/nucleo_g071rb/Kconfig.nucleo_g071rb new file mode 100644 index 00000000000000..4237b458f47640 --- /dev/null +++ b/boards/st/nucleo_g071rb/Kconfig.nucleo_g071rb @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G071RB + select SOC_STM32G071XX diff --git a/boards/arm/nucleo_g071rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g071rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g071rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_g071rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g071rb/board.cmake b/boards/st/nucleo_g071rb/board.cmake similarity index 100% rename from boards/arm/nucleo_g071rb/board.cmake rename to boards/st/nucleo_g071rb/board.cmake diff --git a/boards/st/nucleo_g071rb/board.yml b/boards/st/nucleo_g071rb/board.yml new file mode 100644 index 00000000000000..05e948a2f36bea --- /dev/null +++ b/boards/st/nucleo_g071rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g071rb + vendor: st + socs: + - name: stm32g071xx diff --git a/boards/arm/nucleo_g071rb/doc/img/nucleo_g071rb.jpg b/boards/st/nucleo_g071rb/doc/img/nucleo_g071rb.jpg similarity index 100% rename from boards/arm/nucleo_g071rb/doc/img/nucleo_g071rb.jpg rename to boards/st/nucleo_g071rb/doc/img/nucleo_g071rb.jpg diff --git a/boards/st/nucleo_g071rb/doc/index.rst b/boards/st/nucleo_g071rb/doc/index.rst new file mode 100644 index 00000000000000..9cc78b0f4c823d --- /dev/null +++ b/boards/st/nucleo_g071rb/doc/index.rst @@ -0,0 +1,198 @@ +.. _nucleo_g071rb_board: + +ST Nucleo G071RB +################ + +Overview +******** +The Nucleo G071RB board features an ARM Cortex-M0+ based STM32G071RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G071RB board: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_g071rb.jpg + :align: center + :alt: Nucleo G071RB + +More information about the board can be found at the `Nucleo G071RB website`_. + +Hardware +******** +Nucleo G071RB provides the following hardware components: + +- STM32 microcontroller in LQFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD4), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32G071RB can be found here: + +- `G071RB on www.st.com`_ +- `STM32G071 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_g071rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arm memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g071rb/nucleo_g071rb_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PC4/PC5 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 +- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD4 : PA5 +- PWM : PA6 +- ADC1 IN0 : PA0 +- ADC1 IN1 : PA1 +- DAC1_OUT1 : PA4 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g071rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface. + +Flashing an application to Nucleo G071RB +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g071rb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g071rb + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo G071RB website: + https://www.st.com/en/evaluation-tools/nucleo-g071rb.html + +.. _STM32G071 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00452640.pdf + +.. _G071RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb.dts b/boards/st/nucleo_g071rb/nucleo_g071rb.dts similarity index 100% rename from boards/arm/nucleo_g071rb/nucleo_g071rb.dts rename to boards/st/nucleo_g071rb/nucleo_g071rb.dts diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb.yaml b/boards/st/nucleo_g071rb/nucleo_g071rb.yaml similarity index 100% rename from boards/arm/nucleo_g071rb/nucleo_g071rb.yaml rename to boards/st/nucleo_g071rb/nucleo_g071rb.yaml diff --git a/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig b/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig similarity index 75% rename from boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig rename to boards/st/nucleo_g071rb/nucleo_g071rb_defconfig index 71cc51e4ffcf8f..0055481a2e8f4a 100644 --- a/boards/arm/nucleo_g071rb/nucleo_g071rb_defconfig +++ b/boards/st/nucleo_g071rb/nucleo_g071rb_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G071XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_g071rb/support/openocd.cfg b/boards/st/nucleo_g071rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g071rb/support/openocd.cfg rename to boards/st/nucleo_g071rb/support/openocd.cfg diff --git a/boards/st/nucleo_g0b1re/Kconfig.nucleo_g0b1re b/boards/st/nucleo_g0b1re/Kconfig.nucleo_g0b1re new file mode 100644 index 00000000000000..05d7b4b18622b3 --- /dev/null +++ b/boards/st/nucleo_g0b1re/Kconfig.nucleo_g0b1re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G0B1RE + select SOC_STM32G0B1XX diff --git a/boards/arm/nucleo_g0b1re/arduino_r3_connector.dtsi b/boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g0b1re/arduino_r3_connector.dtsi rename to boards/st/nucleo_g0b1re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g0b1re/board.cmake b/boards/st/nucleo_g0b1re/board.cmake similarity index 100% rename from boards/arm/nucleo_g0b1re/board.cmake rename to boards/st/nucleo_g0b1re/board.cmake diff --git a/boards/st/nucleo_g0b1re/board.yml b/boards/st/nucleo_g0b1re/board.yml new file mode 100644 index 00000000000000..b9d0f93261f70a --- /dev/null +++ b/boards/st/nucleo_g0b1re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g0b1re + vendor: st + socs: + - name: stm32g0b1xx diff --git a/boards/arm/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg b/boards/st/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg similarity index 100% rename from boards/arm/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg rename to boards/st/nucleo_g0b1re/doc/img/nucleo_g0b1re.jpg diff --git a/boards/st/nucleo_g0b1re/doc/index.rst b/boards/st/nucleo_g0b1re/doc/index.rst new file mode 100644 index 00000000000000..b283d6d3d1f207 --- /dev/null +++ b/boards/st/nucleo_g0b1re/doc/index.rst @@ -0,0 +1,211 @@ +.. _nucleo_g0b1re_board: + +ST Nucleo G0B1RE +################ + +Overview +******** +The Nucleo G0B1RE board features an ARM Cortex-M0+ based STM32G0B1RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G0B1RE board: + +- STM32 microcontroller in QFP64 package +- Board connectors: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - 5V_USB_STLK from ST-Link USB connector + - VIN (7 - 12V) from ARDUINO connector or ST morpho connector + - E5V from ST morpho connector + - 5V_USB_CHG from ST-LINK USB connector + - 3.3V on ARDUINO connector or ST morpho connector + +- Three LEDs: USB communication (LD1), user LED (LD4), power LED (LD3) +- Two push-buttons: USER and RESET +- 32.768 kHz crystal oscillator + +.. image:: img/nucleo_g0b1re.jpg + :align: center + :alt: Nucleo G0B1RE + +More information about the board can be found at the `Nucleo G0B1RE website`_. + +Hardware +******** +Nucleo G0B1RE provides the following hardware components: + +- STM32G0B1RE in LQFP64 package +- ARM 32-bit Cortex-M0+ CPU +- 64 MHz max CPU frequency +- Voltage range from 1.7 V to 3.6 V +- 512 KB Flash +- 144 kB SRAM +- 32-bit timers(1) +- 16-bit timers(11) +- watchdogs(2) +- systick(1) +- Calendar RTC with alarm and periodic wakeup +- I2C(3) +- USART(6) +- LPUART(2) +- 32 Mbit/s SPI(3) multiplexed with I2S(2) +- HDMI_CEC(1) +- USB 2.0 FS device (crystal-less) and host controller(1) +- USB Type-C Power Delivery controller +- CAN FD(2) +- GPIO (up to 94) with external interrupt capability +- Tamper Pins(3) +- 12-bit ADC with 16 channels +- 12-bit DAC with 2 channels(2) +- Analog Comparator(3) +- 12-channel DMA + + +More information about STM32G0B1RE can be found here: + +- `G0B1RE on www.st.com`_ +- `STM32G0B1 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_g0b1re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| MPU | on-chip | arm memory protection unit | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| FDCAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PC4/PC5 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C2 SCL/SDA : PA11/PA12 +- SPI1 NSS/SCK/MISO/MOSI : PB0/PA5/PA6/PA7 (Arduino SPI) +- SPI2 NSS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- USER_PB : PC13 +- LD4 : PA5 +- PWM : PA6 +- ADC1 IN0 : PA0 +- ADC1 IN1 : PA1 +- DAC1_OUT1 : PA4 +- FDCAN1 RX/TX: PA11/PA12 +- FDCAN2 RX/TX: PB0/PB1 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g0b1re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface. + +This interface is not yet supported by the openocd version included in the Zephyr SDK. +But JLink, STM32CubeProgrammer and Pyocd interfaces are supported. +Pyocd support is currently limited: As the stm32g0b1 target causes issues, +the stm32g071 target is used. For STM32G0 support pyocd needs additional target +information, which can be installed by adding "pack" support with the +following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32g0 + + +Flashing an application to Nucleo G0B1RE +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_g0b1re + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g0b1re + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo G0B1RE website: + https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html + +.. _STM32G0B1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00452640.pdf + +.. _G0B1RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32g0b1re.html diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts b/boards/st/nucleo_g0b1re/nucleo_g0b1re.dts similarity index 100% rename from boards/arm/nucleo_g0b1re/nucleo_g0b1re.dts rename to boards/st/nucleo_g0b1re/nucleo_g0b1re.dts diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml b/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml similarity index 100% rename from boards/arm/nucleo_g0b1re/nucleo_g0b1re.yaml rename to boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml diff --git a/boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig b/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig similarity index 75% rename from boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig rename to boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig index c57537f7c31071..84d7129fd51728 100644 --- a/boards/arm/nucleo_g0b1re/nucleo_g0b1re_defconfig +++ b/boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G0B1XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_g0b1re/support/openocd.cfg b/boards/st/nucleo_g0b1re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g0b1re/support/openocd.cfg rename to boards/st/nucleo_g0b1re/support/openocd.cfg diff --git a/boards/st/nucleo_g431rb/Kconfig.defconfig b/boards/st/nucleo_g431rb/Kconfig.defconfig new file mode 100644 index 00000000000000..9d0323049ba805 --- /dev/null +++ b/boards/st/nucleo_g431rb/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32G431RB Nucleo board configuration + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_G431RB + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_G431RB diff --git a/boards/st/nucleo_g431rb/Kconfig.nucleo_g431rb b/boards/st/nucleo_g431rb/Kconfig.nucleo_g431rb new file mode 100644 index 00000000000000..304e9cc08881a7 --- /dev/null +++ b/boards/st/nucleo_g431rb/Kconfig.nucleo_g431rb @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G431RB + select SOC_STM32G431XX diff --git a/boards/arm/nucleo_g431rb/arduino_r3_connector.dtsi b/boards/st/nucleo_g431rb/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g431rb/arduino_r3_connector.dtsi rename to boards/st/nucleo_g431rb/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g431rb/board.cmake b/boards/st/nucleo_g431rb/board.cmake similarity index 100% rename from boards/arm/nucleo_g431rb/board.cmake rename to boards/st/nucleo_g431rb/board.cmake diff --git a/boards/st/nucleo_g431rb/board.yml b/boards/st/nucleo_g431rb/board.yml new file mode 100644 index 00000000000000..460dcf740e85fb --- /dev/null +++ b/boards/st/nucleo_g431rb/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g431rb + vendor: st + socs: + - name: stm32g431xx diff --git a/boards/arm/nucleo_g431rb/doc/img/nucleo_g431rb.jpg b/boards/st/nucleo_g431rb/doc/img/nucleo_g431rb.jpg similarity index 100% rename from boards/arm/nucleo_g431rb/doc/img/nucleo_g431rb.jpg rename to boards/st/nucleo_g431rb/doc/img/nucleo_g431rb.jpg diff --git a/boards/st/nucleo_g431rb/doc/index.rst b/boards/st/nucleo_g431rb/doc/index.rst new file mode 100644 index 00000000000000..08d660a0c7d58c --- /dev/null +++ b/boards/st/nucleo_g431rb/doc/index.rst @@ -0,0 +1,263 @@ +.. _nucleo_g431rb_board: + +ST Nucleo G431RB +################ + +Overview +******** + +The Nucleo G431RB board features an ARM Cortex-M4 based STM32G431RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G431RB board: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V3E debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) +- Two push-buttons: RESET and USER + +.. image:: img/nucleo_g431rb.jpg + :align: center + :alt: Nucleo G431RB + +More information about the board can be found at the `Nucleo G431RB website`_. + +Hardware +******** + +The STM32G431RB SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz +- Clock Sources: + + - 4 to 48 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- 14x timers: + + - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop + - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop + - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop + - 2x watchdog timers (independent, window) + - 2x 16-bit basic timers + - SysTick timer + - 1x low-power timer + +- Up to 86 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 128 KB single bank Flash, proprietary code readout protection + - Up to 22 KB of SRAM including 16 KB with hardware parity check + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 4x 12-bit DAC, low-power sample and hold + - 3x operational amplifiers with built-in PGA + - 4x ultra-fast rail-to-rail analog comparators + +- 16x communication interfaces + + - 1 x FDCAN controller supporting flexible data rate + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (2x with multiplexed half duplex I2S interface) + - 1x SAI (serial audio interface) + - USB 2.0 full-speed interface with LPM and BCD support + - IRTIM (Infrared interface) + - USB Type-C™ /USB power delivery controller (UCPD) + +- 12-channel DMA controller +- True random number generator (RNG) +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32G431RB can be found here: + +- `STM32G431RB on www.st.com`_ +- `STM32G4 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_g431rb board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | rng | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g431rb/nucleo_g431rb_defconfig` + + +Connections and IOs +=================== + +Nucleo G431RB Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PC4 +- UART_1_RX : PC5 +- LPUART_1_TX : PA2 +- LPUART_1_RX : PA3 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- SPI_1_NSS : PB6 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PB12 +- SPI_2_SCK : PB13 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PA15 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_3_CH1 : PB4 +- USER_PB : PC13 +- LD2 : PA5 +- DAC1_OUT1 : PA4 + +System Clock +------------ + +Nucleo G431RB System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, +driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode +is selected. + +Serial Port +----------- + +Nucleo G431RB board has 3 U(S)ARTs and one LPUART. The Zephyr console output is assigned to LPUART1. +Default settings are 115200 8N1. + +Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in +low power mode. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g431rb`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G431RB board includes an ST-LINK/V3E embedded debug tool interface. + +This interface is not yet supported by the openocd version included in the Zephyr SDK. + +Instead, support can be enabled on pyocd by adding "pack" support with +the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32g431rb + +Note: +To manually enable the openocd interface, You can still update, compile and install +a 'local' openocd from the official openocd repo http://openocd.zylin.com . +Then run the following openocd command where the '/usr/local/bin/openocd'is your path +for the freshly installed openocd, given by "$ which openocd" : + +.. code-block:: console + + $ west flash --openocd /usr/local/bin/openocd + +Flashing an application to Nucleo G431RB +---------------------------------------- + +Connect the Nucleo G431RB to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g431rb + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g431rb + :maybe-skip-config: + :goals: debug + +.. _Nucleo G431RB website: + https://www.st.com/en/evaluation-tools/nucleo-g431rb.html + +.. _STM32G4 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00556337.pdf + +.. _STM32G431RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g431rb.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb.dts b/boards/st/nucleo_g431rb/nucleo_g431rb.dts similarity index 100% rename from boards/arm/nucleo_g431rb/nucleo_g431rb.dts rename to boards/st/nucleo_g431rb/nucleo_g431rb.dts diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb.yaml b/boards/st/nucleo_g431rb/nucleo_g431rb.yaml similarity index 100% rename from boards/arm/nucleo_g431rb/nucleo_g431rb.yaml rename to boards/st/nucleo_g431rb/nucleo_g431rb.yaml diff --git a/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig b/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig similarity index 85% rename from boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig rename to boards/st/nucleo_g431rb/nucleo_g431rb_defconfig index 92c2363d2d8ffb..5bd145ba76ca38 100644 --- a/boards/arm/nucleo_g431rb/nucleo_g431rb_defconfig +++ b/boards/st/nucleo_g431rb/nucleo_g431rb_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G431XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_g431rb/st_morpho_connector.dtsi b/boards/st/nucleo_g431rb/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g431rb/st_morpho_connector.dtsi rename to boards/st/nucleo_g431rb/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_g431rb/support/openocd.cfg b/boards/st/nucleo_g431rb/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g431rb/support/openocd.cfg rename to boards/st/nucleo_g431rb/support/openocd.cfg diff --git a/boards/st/nucleo_g474re/Kconfig.defconfig b/boards/st/nucleo_g474re/Kconfig.defconfig new file mode 100644 index 00000000000000..fb93e1098d1aca --- /dev/null +++ b/boards/st/nucleo_g474re/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32G474RE Nucleo board configuration + +# Copyright (c) 2019 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_G474RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_G431RB diff --git a/boards/st/nucleo_g474re/Kconfig.nucleo_g474re b/boards/st/nucleo_g474re/Kconfig.nucleo_g474re new file mode 100644 index 00000000000000..bf6ef1999713ec --- /dev/null +++ b/boards/st/nucleo_g474re/Kconfig.nucleo_g474re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_G474RE + select SOC_STM32G474XX diff --git a/boards/arm/nucleo_g474re/arduino_r3_connector.dtsi b/boards/st/nucleo_g474re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_g474re/arduino_r3_connector.dtsi rename to boards/st/nucleo_g474re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_g474re/board.cmake b/boards/st/nucleo_g474re/board.cmake similarity index 100% rename from boards/arm/nucleo_g474re/board.cmake rename to boards/st/nucleo_g474re/board.cmake diff --git a/boards/st/nucleo_g474re/board.yml b/boards/st/nucleo_g474re/board.yml new file mode 100644 index 00000000000000..7cf7857f527041 --- /dev/null +++ b/boards/st/nucleo_g474re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_g474re + vendor: st + socs: + - name: stm32g474xx diff --git a/boards/arm/nucleo_g474re/doc/img/nucleo_g474re.jpg b/boards/st/nucleo_g474re/doc/img/nucleo_g474re.jpg similarity index 100% rename from boards/arm/nucleo_g474re/doc/img/nucleo_g474re.jpg rename to boards/st/nucleo_g474re/doc/img/nucleo_g474re.jpg diff --git a/boards/st/nucleo_g474re/doc/index.rst b/boards/st/nucleo_g474re/doc/index.rst new file mode 100644 index 00000000000000..9d23c072b75979 --- /dev/null +++ b/boards/st/nucleo_g474re/doc/index.rst @@ -0,0 +1,255 @@ +.. _nucleo_g474re_board: + +ST Nucleo G474RE +################ + +Overview +******** + +The Nucleo G474RE board features an ARM Cortex-M4 based STM32G474RE MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo G474RE board: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V3E debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD2) +- Two push-buttons: RESET and USER + +.. image:: img/nucleo_g474re.jpg + :align: center + :alt: Nucleo G474RE + +More information about the board can be found at the `Nucleo G474RE website`_. + +Hardware +******** + +The STM32G474RE SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 170 MHz +- Clock Sources: + + - 4 to 48 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- 14x timers: + + - 1x 32-bit timer and 2x 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 2x 16-bit 8-channel advanced motor control timers, with up to 8x PWM channels, dead time generation and emergency stop + - 1x 16-bit timer with 2x IC/OCs, one OCN/PWM, dead time generation and emergency stop + - 2x 16-bit timers with IC/OC/OCN/PWM, dead time generation and emergency stop + - 2x watchdog timers (independent, window) + - 2x 16-bit basic timers + - SysTick timer + - 1x low-power timer + +- Up to 86 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 128 KB single bank Flash, proprietary code readout protection + - Up to 22 KB of SRAM including 16 KB with hardware parity check + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 4x 12-bit DAC, low-power sample and hold + - 3x operational amplifiers with built-in PGA + - 4x ultra-fast rail-to-rail analog comparators + +- 16x communication interfaces + + - 1 x FDCAN controller supporting flexible data rate + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (2x with multiplexed half duplex I2S interface) + - 1x SAI (serial audio interface) + - USB 2.0 full-speed interface with LPM and BCD support + - IRTIM (Infrared interface) + - USB Type-C™ /USB power delivery controller (UCPD) + +- 12-channel DMA controller +- True random number generator (RNG) +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32G474RE can be found here: + +- `STM32G474RE on www.st.com`_ +- `STM32G4 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_g474re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ +| FDCAN1 | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_g474re/nucleo_g474re_defconfig` + + +Connections and IOs +=================== + +Nucleo G474RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32G4 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PC4 +- UART_1_RX : PC5 +- LPUART_1_TX : PA2 +- LPUART_1_RX : PA3 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- SPI_1_NSS : PB6 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PB12 +- SPI_2_SCK : PB13 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PA15 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_2_CH1 : PA5 (might conflict with SPI1) +- PWM_3_CH1 : PB4 +- USER_PB : PC13 +- LD2 : PA5 +- ADC1_IN1 : PA0 +- DAC1_OUT1 : PA4 +- FDCAN1_RX: PA11 +- FDCAN1_TX: PA12 + +System Clock +------------ + +Nucleo G474RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 150MHz, +driven by 16MHz high speed internal oscillator. The clock can be boosted to 170MHz if boost mode +is selected. + +Serial Port +----------- + +Nucleo G474RE board has 3 U(S)ARTs. The Zephyr console output is assigned to LPUART1. +Default settings are 115200 8N1. + +Please note that LPUART1 baudrate is limited to 9600 if the MCU is clocked by LSE (32.768 kHz) in +low power mode. + +Programming and Debugging +************************* + +Applications for the ``nucleo_g474re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface. + +Flashing an application to Nucleo G474RE +---------------------------------------- + +Connect the Nucleo G474RE to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g474re + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_g474re + :maybe-skip-config: + :goals: debug + +.. _Nucleo G474RE website: + https://www.st.com/en/evaluation-tools/nucleo-g474re.html + +.. _STM32G4 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00556337.pdf + +.. _STM32G474RE on www.st.com: + https://www.st.com/en/microcontrollers/stm32g474re.html + +.. _STM32G4 reference manual: + https://www.st.com/resource/en/reference_manual/dm00355726.pdf diff --git a/boards/arm/nucleo_g474re/nucleo_g474re.dts b/boards/st/nucleo_g474re/nucleo_g474re.dts similarity index 100% rename from boards/arm/nucleo_g474re/nucleo_g474re.dts rename to boards/st/nucleo_g474re/nucleo_g474re.dts diff --git a/boards/arm/nucleo_g474re/nucleo_g474re.yaml b/boards/st/nucleo_g474re/nucleo_g474re.yaml similarity index 100% rename from boards/arm/nucleo_g474re/nucleo_g474re.yaml rename to boards/st/nucleo_g474re/nucleo_g474re.yaml diff --git a/boards/arm/nucleo_g474re/nucleo_g474re_defconfig b/boards/st/nucleo_g474re/nucleo_g474re_defconfig similarity index 85% rename from boards/arm/nucleo_g474re/nucleo_g474re_defconfig rename to boards/st/nucleo_g474re/nucleo_g474re_defconfig index 15b382fefaec00..b22a31b2f2018c 100644 --- a/boards/arm/nucleo_g474re/nucleo_g474re_defconfig +++ b/boards/st/nucleo_g474re/nucleo_g474re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G474XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_g474re/support/openocd.cfg b/boards/st/nucleo_g474re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_g474re/support/openocd.cfg rename to boards/st/nucleo_g474re/support/openocd.cfg diff --git a/boards/st/nucleo_h563zi/Kconfig.defconfig b/boards/st/nucleo_h563zi/Kconfig.defconfig new file mode 100644 index 00000000000000..54426df3945540 --- /dev/null +++ b/boards/st/nucleo_h563zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H563ZI Nucleo board configuration + +# Copyright (c) 2023 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H563ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H563ZI diff --git a/boards/st/nucleo_h563zi/Kconfig.nucleo_h563zi b/boards/st/nucleo_h563zi/Kconfig.nucleo_h563zi new file mode 100644 index 00000000000000..49209ab6a161e5 --- /dev/null +++ b/boards/st/nucleo_h563zi/Kconfig.nucleo_h563zi @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H563ZI + select SOC_STM32H563XX diff --git a/boards/arm/nucleo_h563zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h563zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h563zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_h563zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h563zi/board.cmake b/boards/st/nucleo_h563zi/board.cmake similarity index 100% rename from boards/arm/nucleo_h563zi/board.cmake rename to boards/st/nucleo_h563zi/board.cmake diff --git a/boards/st/nucleo_h563zi/board.yml b/boards/st/nucleo_h563zi/board.yml new file mode 100644 index 00000000000000..42319f55755d9b --- /dev/null +++ b/boards/st/nucleo_h563zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h563zi + vendor: st + socs: + - name: stm32h563xx diff --git a/boards/arm/nucleo_h563zi/doc/img/nucleo_h563zi.jpg b/boards/st/nucleo_h563zi/doc/img/nucleo_h563zi.jpg similarity index 100% rename from boards/arm/nucleo_h563zi/doc/img/nucleo_h563zi.jpg rename to boards/st/nucleo_h563zi/doc/img/nucleo_h563zi.jpg diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst new file mode 100644 index 00000000000000..9be058043300fa --- /dev/null +++ b/boards/st/nucleo_h563zi/doc/index.rst @@ -0,0 +1,317 @@ +.. _nucleo_h563zi_board: + +ST Nucleo H563ZI +################ + +Overview +******** + +The Nucleo H563ZI board is designed as an affordable development platform for +STMicroelectronics ARM |reg| Cortex |reg|-M33 core-based STM32H563ZIT6 +microcontroller with TrustZone |reg|. +Here are some highlights of the Nucleo H563ZI board: + +- STM32H563ZI microcontroller featuring 2 Mbytes of Flash memory and 640Kbyte of + SRAM in LQFP144 package +- Board connectors: + + - USB Type-C |trade| Sink device FS + - Ethernet RJ45 connector compliant with IEEE-802.3-2002 (depending on STM32 support) + - ST Zio expansion connector including Arduino Uno V3 connectivity (CN7, CN8, CN9, CN10) + - ST morpho extension connector (CN11, CN12) + +- Flexible board power supply: + + - 5V_USB_STLK from ST-Link USB connector + - VIN (7 - 12V, 0.8A) supplied via pin header CN8 pin 15 or CN11 pin 24 + - 5V_EXT on the ST morpho connector CN11 Pin 6 (5V, 1.3) + - CHGR from a USB charger via the ST-LINK USB connector + - USB_USER from the USB user connector (5V, 3A) + - 3V3_EXT supplied via a pin header CN8 pin 7 or CN11 pin 16 (3.3V, 1.3A) + +- On-board ST-LINK/V3EC debugger/programmer + + - mass storage + - Virtual COM port + - debug port + +- Three users LEDs +- Two push-buttons: USER and RESET +- 32.789 kHz crystal oscillator + +More information about the board can be found at the `NUCLEO_H563ZI website`_. + +.. image:: img/nucleo_h563zi.jpg + :align: center + :alt: NUCLEO H563ZI + +Hardware +******** + +The STM32H563xx devices are high-performance microcontrollers from the STM32H5 +Series based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. +They operate at a frequency of up to 250 MHz. + +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 375 DMPIS/MHz (Dhrystone 2.1) + +- Security + + - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension + - Up to 8 configurable SAU regions + - TrustZone |reg| aware and securable peripherals + - Flexible lifecycle scheme with secure debug authentication + - SFI (secure firmware installation) + - Secure firmware upgrade support with TF-M + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + +- Clock management: + + - 25 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 64 MHz (HSI) trimmable by software + - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) + - Internal 4 MHz oscillator (CSI), trimmable by software + - Internal 48 MHz (HSI48) with recovery system + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + +- RTC with HW calendar, alarms and calibration +- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V +- Up to 16 timers and 2 watchdogs + + - 12x 16-bit + - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 6x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- Memories + + - Up to 2 MB Flash, 2 banks read-while-write + - 1 Kbyte OTP (one-time programmable) + - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC + - 4 Kbytes of backup SRAM available in the lowest power modes + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories + - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 2x SD/SDIO/MMC interfaces + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC with up to 5 MSPS in 12-bit + - 1x 12-bit D/A with 2 channels + - 1x Digital temperature sensor + +- 34x communication interfaces + + - 1x USB Type-C / USB power-delivery controller + - 1x USB 2.0 full-speed host and device + - 4x I2C FM+ interfaces (SMBus/PMBus) + - 1x I3C interface + - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) + - 1x LP UART + - 6x SPIs including 3 muxed with full-duplex I2S + - 5x additional SPI from 5x USART when configured in Synchronous mode + - 2x SAI + - 2x FDCAN + - 1x SDMMC interface + - 2x 16 channel DMA controllers + - 1x 8- to 14- bit camera interface + - 1x HDMI-CEC + - 1x Ethernel MAC interface with DMA controller + - 1x 16-bit parallel slave synchronous-interface + +- CORDIC for trigonometric functions acceleration +- FMAC (filter mathematical accelerator) +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + +More information about STM32H563ZI can be found here: + +- `STM32H563ZI on www.st.com`_ +- `STM32H563 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_h563zi board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi bus | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB full-speed host/device bus | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Secure target: + + - :zephyr_file:`boards/st/nucleo_h563zi/nucleo_h563zi_defconfig` + - :zephyr_file:`boards/st/nucleo_h563zi/nucleo_h563zi.dts` + +Zephyr board options +==================== + +The STM32H563 is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| nucleo_h563zi | For building Secure firmware | ++----------------------+-----------------------------------------------+ + +Connections and IOs +=================== + +Nucleo H563ZI Board has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H5 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- ADC1 channel 3 input: PA6 +- ADC1 channel 15 input: PA3 +- DAC1 channel 2 output: PA5 +- LD1 (green): PB0 +- LD2 (yellow): PF4 +- LD3 (red): PG4 +- LPUART1 TX/RX : PB6/PB7 (Arduino LPUART1) +- SPI1 SCK/MISO/MOSI/CS: PA5/PG9/PB5/PD14 +- UART3 TX/RX : PD8/PD9 (VCP) +- USER_PB : PC13 + +System Clock +------------ + +Nucleo H563ZI System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +240MHz, driven by 8MHz external clock provided from the STLINK-V3EC. + +Serial Port +----------- + +Nucleo H563ZI board has up to 12 U(S)ARTs. The Zephyr console output is assigned +to USART3. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h563zi`` board can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo H563ZI board includes an ST-LINK/V3EC embedded debug tool interface. +This probe allows to flash the board using various tools. + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, pyocd or jlink via an external probe can also be used to flash +and debug the board if west is told to use it as runner, which can be done by +passing either or ``-r pyocd``, or ``-r jlink``. + +For pyocd additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32h5 + + +Flashing an application to Nucleo H563ZI +------------------------------------------ + +Connect the Nucleo H563ZI to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h563zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_h563zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h563zi + :goals: debug + +.. _NUCLEO_H563ZI website: + https://www.st.com/en/evaluation-tools/nucleo-h563zi + +.. _STM32H5 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um3115-stm32h5-nucleo144-board-mb1404-stmicroelectronics.pdf + +.. _STM32H563ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32h563zi.html + +.. _STM32H563 reference manual: + https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi-common.dtsi b/boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi similarity index 100% rename from boards/arm/nucleo_h563zi/nucleo_h563zi-common.dtsi rename to boards/st/nucleo_h563zi/nucleo_h563zi-common.dtsi diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi.dts b/boards/st/nucleo_h563zi/nucleo_h563zi.dts similarity index 100% rename from boards/arm/nucleo_h563zi/nucleo_h563zi.dts rename to boards/st/nucleo_h563zi/nucleo_h563zi.dts diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi.yaml b/boards/st/nucleo_h563zi/nucleo_h563zi.yaml similarity index 100% rename from boards/arm/nucleo_h563zi/nucleo_h563zi.yaml rename to boards/st/nucleo_h563zi/nucleo_h563zi.yaml diff --git a/boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig b/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig similarity index 85% rename from boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig rename to boards/st/nucleo_h563zi/nucleo_h563zi_defconfig index a14e2d48eec045..d751abf075b76e 100644 --- a/boards/arm/nucleo_h563zi/nucleo_h563zi_defconfig +++ b/boards/st/nucleo_h563zi/nucleo_h563zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H5X=y -CONFIG_SOC_STM32H563XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_h563zi/st_morpho_connector.dtsi b/boards/st/nucleo_h563zi/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h563zi/st_morpho_connector.dtsi rename to boards/st/nucleo_h563zi/st_morpho_connector.dtsi diff --git a/boards/st/nucleo_h723zg/Kconfig.defconfig b/boards/st/nucleo_h723zg/Kconfig.defconfig new file mode 100644 index 00000000000000..2e205cf96c4199 --- /dev/null +++ b/boards/st/nucleo_h723zg/Kconfig.defconfig @@ -0,0 +1,19 @@ +# STM32H723ZG Nucleo board configuration + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H723ZG + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config USB_DC_HAS_HS_SUPPORT + default y + depends on USB_DC_STM32 + +endif # BOARD_NUCLEO_H723ZG diff --git a/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg b/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg new file mode 100644 index 00000000000000..a8ff99320e6fb9 --- /dev/null +++ b/boards/st/nucleo_h723zg/Kconfig.nucleo_h723zg @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H723ZG + select SOC_STM32H723XX diff --git a/boards/arm/nucleo_h723zg/arduino_r3_connector.dtsi b/boards/st/nucleo_h723zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h723zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_h723zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h723zg/board.cmake b/boards/st/nucleo_h723zg/board.cmake similarity index 100% rename from boards/arm/nucleo_h723zg/board.cmake rename to boards/st/nucleo_h723zg/board.cmake diff --git a/boards/st/nucleo_h723zg/board.yml b/boards/st/nucleo_h723zg/board.yml new file mode 100644 index 00000000000000..56a6d5cfb52e90 --- /dev/null +++ b/boards/st/nucleo_h723zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h723zg + vendor: st + socs: + - name: stm32h723xx diff --git a/boards/arm/nucleo_h723zg/doc/img/nucleo_h723zg.jpg b/boards/st/nucleo_h723zg/doc/img/nucleo_h723zg.jpg similarity index 100% rename from boards/arm/nucleo_h723zg/doc/img/nucleo_h723zg.jpg rename to boards/st/nucleo_h723zg/doc/img/nucleo_h723zg.jpg diff --git a/boards/st/nucleo_h723zg/doc/index.rst b/boards/st/nucleo_h723zg/doc/index.rst new file mode 100644 index 00000000000000..cce94294255cb5 --- /dev/null +++ b/boards/st/nucleo_h723zg/doc/index.rst @@ -0,0 +1,248 @@ +.. _nucleo_h723zg_board: + +ST Nucleo H723ZG +################ + +Overview +******** + +The STM32 Nucleo-144 board provides an affordable and flexible way for users +to try out new concepts and build prototypes by choosing from the various combinations +of performance and power consumption features, provided by the STM32 microcontroller. +For the compatible boards, the internal or external SMPS significantly reduces power +consumption in Run mode. + +The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and +the ST morpho headers provide an easy means of expanding the functionality of the Nucleo +open development platform with a wide choice of specialized shields. +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK V3 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - Ethernet RJ45 (depending on STM32 support) + - SWDST Zio connector including Arduino* Uno V3ST + - ST morpho expansion + +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- External or internal SMPS to generate Vcore logic supply +- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port +- USB OTG full speed or device only + +.. image:: img/nucleo_h723zg.jpg + :align: center + :alt: Nucleo H723ZG + +More information about the board can be found at the `Nucleo H723ZG website`_. + +Hardware +******** + +Nucleo H723ZG provides the following hardware components: + +- STM32H723ZG in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 550 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 1 MB Flash +- 562 kB SRAM max (376 kb used currently) +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h723zg board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig files: +:zephyr_file:`boards/st/nucleo_h723zg/nucleo_h723zg_defconfig`` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H723ZG board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 +- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) + +System Clock +------------ + +Nucleo H723ZG System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 550MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H723ZG board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB52`` jumper on the back side of the board. + +Programming and Debugging +************************* + +Currently the ``nucleo_h723zg`` board supports stm32cubeprogrammer (default), OpenOCD and J-Link debuggers. + +.. note:: + + Official OpenOCD support for this board was added on October '20. + Make sure your openocd version is older than that. + Following links may be helpful: `OpenOCD installing Debug Version`_ + and `OpenOCD installing with ST-LINK V3 support`_ + +.. note:: + + Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ + +Flashing +======== + +Nucleo H723ZG board includes an ST-LINK/V3 embedded debug tool interface. + +First, connect the NUCLEO-H723ZG to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your NUCLEO-H723ZG board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +or use screen: + +.. code-block:: console + + $ screen /dev/ttyACM0 115200 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h723zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h723zg + +Blinky example can also be used: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h723zg + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h723zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo H723ZG website: + https://www.st.com/en/evaluation-tools/nucleo-h723zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00499160-stm32h7-nucleo144-boards-mb1364-stmicroelectronics.pdf + +.. _STM32H723ZG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h723zg.html + +.. _STM32H723 reference manual: + https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _OpenOCD installing Debug Version: + https://github.com/zephyrproject-rtos/openocd + +.. _OpenOCD installing with ST-LINK V3 support: + https://mbd.kleier.net/integrating-st-link-v3.html + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg.dts b/boards/st/nucleo_h723zg/nucleo_h723zg.dts similarity index 100% rename from boards/arm/nucleo_h723zg/nucleo_h723zg.dts rename to boards/st/nucleo_h723zg/nucleo_h723zg.dts diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg.yaml b/boards/st/nucleo_h723zg/nucleo_h723zg.yaml similarity index 100% rename from boards/arm/nucleo_h723zg/nucleo_h723zg.yaml rename to boards/st/nucleo_h723zg/nucleo_h723zg.yaml diff --git a/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig b/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig similarity index 78% rename from boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig rename to boards/st/nucleo_h723zg/nucleo_h723zg_defconfig index 676bfa4533f2ae..96a37909f6b3f6 100644 --- a/boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig +++ b/boards/st/nucleo_h723zg/nucleo_h723zg_defconfig @@ -1,10 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H723XX=y - -CONFIG_BOARD_NUCLEO_H723ZG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h723zg/support/openocd.cfg b/boards/st/nucleo_h723zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h723zg/support/openocd.cfg rename to boards/st/nucleo_h723zg/support/openocd.cfg diff --git a/boards/st/nucleo_h743zi/Kconfig.defconfig b/boards/st/nucleo_h743zi/Kconfig.defconfig new file mode 100644 index 00000000000000..b893c798c116c7 --- /dev/null +++ b/boards/st/nucleo_h743zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H743ZI Nucleo board configuration + +# Copyright (c) 2020 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H743ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H743ZI diff --git a/boards/st/nucleo_h743zi/Kconfig.nucleo_h743zi b/boards/st/nucleo_h743zi/Kconfig.nucleo_h743zi new file mode 100644 index 00000000000000..f1f89927f01971 --- /dev/null +++ b/boards/st/nucleo_h743zi/Kconfig.nucleo_h743zi @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H743ZI + select SOC_STM32H743XX diff --git a/boards/arm/nucleo_h743zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h743zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h743zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_h743zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h743zi/board.cmake b/boards/st/nucleo_h743zi/board.cmake similarity index 100% rename from boards/arm/nucleo_h743zi/board.cmake rename to boards/st/nucleo_h743zi/board.cmake diff --git a/boards/st/nucleo_h743zi/board.yml b/boards/st/nucleo_h743zi/board.yml new file mode 100644 index 00000000000000..e133a6fc034ead --- /dev/null +++ b/boards/st/nucleo_h743zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h743zi + vendor: st + socs: + - name: stm32h743xx diff --git a/boards/arm/nucleo_h743zi/doc/img/nucleo_h743zi.jpg b/boards/st/nucleo_h743zi/doc/img/nucleo_h743zi.jpg similarity index 100% rename from boards/arm/nucleo_h743zi/doc/img/nucleo_h743zi.jpg rename to boards/st/nucleo_h743zi/doc/img/nucleo_h743zi.jpg diff --git a/boards/st/nucleo_h743zi/doc/index.rst b/boards/st/nucleo_h743zi/doc/index.rst new file mode 100644 index 00000000000000..d5d1ee596b62a0 --- /dev/null +++ b/boards/st/nucleo_h743zi/doc/index.rst @@ -0,0 +1,246 @@ +.. _nucleo_h743zi_board: + +ST Nucleo H743ZI +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h743zi.jpg + :align: center + :alt: Nucleo H743ZI + +More information about the board can be found at the `Nucleo H743ZI website`_. + +Hardware +******** + +Nucleo H743ZI provides the following hardware components: + +- STM32H743ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- 1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h743zi board configuration supports the following hardware +features: + ++-------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-------------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-------------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-------------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-------------+------------+-------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-------------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-------------+------------+-------------------------------------+ +| CAN/CANFD | on-chip | canbus | ++-------------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-------------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_h743zi/nucleo_h743zi_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H743ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 +- ADC1_INP15 : PA3 +- DAC1_OUT1 : PA4 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- SPI1 NSS/SCK/MISO/MOSI : PD14/PA5/PA6/PB5 (Arduino SPI) +- CAN/CANFD : PD0, PD1 + +System Clock +------------ + +Nucleo H743ZI System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H743ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB156`` jumper on the back side of the board. + +CAN, CANFD +---------- + +Requires an external CAN or CANFD transceiver. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h743zi`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 series yet. You can also choose the + ``stm32cubeprogrammer`` runner. + +Flashing +======== + +Nucleo H743ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo H743ZI +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h743zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h743zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h743zi + :maybe-skip-config: + :goals: debug + +.. _Nucleo H743ZI website: + https://www.st.com/en/evaluation-tools/nucleo-h743zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32H743ZI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h743zi.html + +.. _STM32H743 reference manual: + https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.dts b/boards/st/nucleo_h743zi/nucleo_h743zi.dts similarity index 100% rename from boards/arm/nucleo_h743zi/nucleo_h743zi.dts rename to boards/st/nucleo_h743zi/nucleo_h743zi.dts diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi.yaml b/boards/st/nucleo_h743zi/nucleo_h743zi.yaml similarity index 100% rename from boards/arm/nucleo_h743zi/nucleo_h743zi.yaml rename to boards/st/nucleo_h743zi/nucleo_h743zi.yaml diff --git a/boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig b/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig similarity index 85% rename from boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig rename to boards/st/nucleo_h743zi/nucleo_h743zi_defconfig index c06c8d34406827..8dcaab60f611ae 100644 --- a/boards/arm/nucleo_h743zi/nucleo_h743zi_defconfig +++ b/boards/st/nucleo_h743zi/nucleo_h743zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H743XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h743zi/support/openocd.cfg b/boards/st/nucleo_h743zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h743zi/support/openocd.cfg rename to boards/st/nucleo_h743zi/support/openocd.cfg diff --git a/boards/st/nucleo_h745zi_q/Kconfig.defconfig b/boards/st/nucleo_h745zi_q/Kconfig.defconfig new file mode 100644 index 00000000000000..9ad83aa96d108f --- /dev/null +++ b/boards/st/nucleo_h745zi_q/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H745ZI Nucleo board configuration + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H745ZI_Q + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H745ZI_Q diff --git a/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q b/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q new file mode 100644 index 00000000000000..6d19d1592ae58b --- /dev/null +++ b/boards/st/nucleo_h745zi_q/Kconfig.nucleo_h745zi_q @@ -0,0 +1,8 @@ +# STM32H745ZI Nucleo board configuration + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H745ZI_Q + select SOC_STM32H745XX_M7 if BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M7 + select SOC_STM32H745XX_M4 if BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M4 diff --git a/boards/arm/nucleo_h745zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h745zi_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_h745zi_q/arduino_r3_connector.dtsi diff --git a/boards/st/nucleo_h745zi_q/board.cmake b/boards/st/nucleo_h745zi_q/board.cmake new file mode 100644 index 00000000000000..677c748de358b0 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/board.cmake @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2020 Alexander Kozhinov + +board_runner_args(jlink "--device=STM32H745ZI" "--speed=4000") +if(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M7) +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_NUCLEO_H745ZI_Q_STM32H745XX_M4) +board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/nucleo_h745zi_q/board.yml b/boards/st/nucleo_h745zi_q/board.yml new file mode 100644 index 00000000000000..7ba025f5bb78b5 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h745zi_q + vendor: st + socs: + - name: stm32h745xx diff --git a/boards/arm/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg b/boards/st/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg similarity index 100% rename from boards/arm/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg rename to boards/st/nucleo_h745zi_q/doc/img/nucleo_h745zi_q.jpg diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst new file mode 100644 index 00000000000000..265d3385be8a91 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/doc/index.rst @@ -0,0 +1,290 @@ +.. _nucleo_h745zi_q_board: + +ST Nucleo H745ZI-Q +################### + +Overview +******** + +The STM32 Nucleo-144 board provides an affordable and flexible way for users +to try out new concepts and build prototypes by choosing from the various combinations +of performance and power consumption features, provided by the STM32 microcontroller. +For the compatible boards, the internal or external SMPS significantly reduces power +consumption in Run mode. + +The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and +the ST morpho headers provide an easy means of expanding the functionality of the Nucleo +open development platform with a wide choice of specialized shields. +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK V3 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - Ethernet RJ45 (depending on STM32 support) + - SWDST Zio connector including Arduino* Uno V3ST + - ST morpho expansion + +- Flexible power-supply options: ST-LINK USB VBUS or external sources +- External or internal SMPS to generate Vcore logic supply +- On-board ST-LINK/V3 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port +- USB OTG full speed or device only +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h745zi_q.jpg + :align: center + :alt: Nucleo H745ZI-Q + +More information about the board can be found at the `Nucleo H745ZI-Q website`_. + +Hardware +******** + +Nucleo H745ZI-Q provides the following hardware components: + +- STM32H745ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- ARM 32-bit Cortex-M4 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- 1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h745zi_q board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration per core can be found in the defconfig files: +:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig`` and +:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H745ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 + +System Clock +------------ + +Nucleo H745ZI-Q System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 480MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H745ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +Resources sharing +----------------- + +The dual core nature of STM32H745 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h745zi_q`` board should be built per core target, +using either ``nucleo_h745zi_q_m7`` or ```nucleo_h745zi_q_m4`` as the target +(see :ref:`build_an_application` and :ref:`application_run` for more details). + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 series and ST-LINK V3 yet. + Following links may be helpful: `OpenOCD installing Debug Version`_ + and `OpenOCD installing with ST-LINK V3 support`_ + +.. note:: + + Check if your ST-LINK V3 has newest FW version. It can be done with `STM32CubeIDE`_ + +Flashing +======== + +Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. + +By default: + + - CPU0 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) + - CPU1 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) + +Also, default out of the box board configuration enables CM7 and CM4 boot when +board is powered (Option bytes BCM7 and BCM4 are checked). +In that configuration, Kconfig boot option ``STM32H7_BOOT_CM4_CM7`` should be selected. +Zephyr flash configuration has been set to meet these default settings. + +Flashing an application to STM32H745ZI M7 Core +---------------------------------------------- +First, connect the NUCLEO-H745ZI-Q to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your NUCLEO-H745ZI-Q board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +or use screen: + +.. code-block:: console + + $ screen /dev/ttyACM0 115200 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h745zi_q_m7 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h745zi_q_m7 + +.. note:: + Sometimes, flashing is not working. It is necessary to erase the flash + (with STM32CubeProgrammer for example) to make it work again. + +Similarly, you can build and flash samples on the M4 target. For this, please +take care of the resource sharing (UART port used for console for instance). + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_h745zi_q_m4 + :goals: build flash + +.. note:: + + Flashing both M4 and M7 and pushing RESTART button on the board leads + to LD1 and LD2 flashing simultaneously. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h745zi_q_m7 + :maybe-skip-config: + :goals: debug + +Debugging with west is currently not available on Cortex M4 side. +In order to debug a Zephyr application on Cortex M4 side, you can use +`STM32CubeIDE`_. + +.. _Nucleo H745ZI-Q website: + https://www.st.com/en/evaluation-tools/nucleo-h745zi-q.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00499171-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf + +.. _STM32H745ZI on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h745zi.html + +.. _STM32H745 reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _OpenOCD installing Debug Version: + https://github.com/zephyrproject-rtos/openocd + +.. _OpenOCD installing with ST-LINK V3 support: + https://mbd.kleier.net/integrating-st-link-v3.html + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q.dtsi b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q.dtsi similarity index 100% rename from boards/arm/nucleo_h745zi_q/nucleo_h745zi_q.dtsi rename to boards/st/nucleo_h745zi_q/nucleo_h745zi_q.dtsi diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts similarity index 100% rename from boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.dts rename to boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.dts diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml new file mode 100644 index 00000000000000..19c2a5a1f1c510 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml @@ -0,0 +1,19 @@ +identifier: nucleo_h745zi_q/stm32h745xx/m4 +name: ST Nucleo H745ZI-Q (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - arduino_gpio + - gpio + - netif:eth +testing: + ignore_tags: + - mpu + - nfc +vendor: st diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig new file mode 100644 index 00000000000000..2eb7224edabefe --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2020 Alexander Kozhinov + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clock +CONFIG_CLOCK_CONTROL=y + +# By default SERIAL peripherals are assigned to m7 + +# Enable uart driver +#CONFIG_SERIAL=y + +# Console +#CONFIG_CONSOLE=y +#CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts similarity index 100% rename from boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts rename to boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml new file mode 100644 index 00000000000000..c480b150189838 --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml @@ -0,0 +1,20 @@ +identifier: nucleo_h745zi_q/stm32h745xx/m7 +name: ST Nucleo H745ZI-Q (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - arduino_gpio + - arduino_i2c + - uart + - gpio + - counter + - i2c + - pwm + - netif:eth +vendor: st diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig new file mode 100644 index 00000000000000..a38b7cad80ebfc --- /dev/null +++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2020 Alexander Kozhinov + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART ( disable to assign to M4 core) +CONFIG_SERIAL=y + +# Console ( disable to assign to M4 core) +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable Clock +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_h745zi_q/support/openocd.cfg b/boards/st/nucleo_h745zi_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h745zi_q/support/openocd.cfg rename to boards/st/nucleo_h745zi_q/support/openocd.cfg diff --git a/boards/st/nucleo_h753zi/Kconfig.defconfig b/boards/st/nucleo_h753zi/Kconfig.defconfig new file mode 100644 index 00000000000000..57c83698109706 --- /dev/null +++ b/boards/st/nucleo_h753zi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32H753ZI Nucleo board configuration + +# Copyright (c) 2021 Blue Clover Devices +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H753ZI + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_H753ZI diff --git a/boards/st/nucleo_h753zi/Kconfig.nucleo_h753zi b/boards/st/nucleo_h753zi/Kconfig.nucleo_h753zi new file mode 100644 index 00000000000000..2ca1de7fd9343d --- /dev/null +++ b/boards/st/nucleo_h753zi/Kconfig.nucleo_h753zi @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Blue Clover Devices +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H753ZI + select SOC_STM32H753XX diff --git a/boards/arm/nucleo_h753zi/arduino_r3_connector.dtsi b/boards/st/nucleo_h753zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h753zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_h753zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h753zi/board.cmake b/boards/st/nucleo_h753zi/board.cmake similarity index 100% rename from boards/arm/nucleo_h753zi/board.cmake rename to boards/st/nucleo_h753zi/board.cmake diff --git a/boards/st/nucleo_h753zi/board.yml b/boards/st/nucleo_h753zi/board.yml new file mode 100644 index 00000000000000..12dc4b5a501dec --- /dev/null +++ b/boards/st/nucleo_h753zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h753zi + vendor: st + socs: + - name: stm32h753xx diff --git a/boards/arm/nucleo_h753zi/doc/img/nucleo_h753zi.jpg b/boards/st/nucleo_h753zi/doc/img/nucleo_h753zi.jpg similarity index 100% rename from boards/arm/nucleo_h753zi/doc/img/nucleo_h753zi.jpg rename to boards/st/nucleo_h753zi/doc/img/nucleo_h753zi.jpg diff --git a/boards/st/nucleo_h753zi/doc/index.rst b/boards/st/nucleo_h753zi/doc/index.rst new file mode 100644 index 00000000000000..536d90d63105b4 --- /dev/null +++ b/boards/st/nucleo_h753zi/doc/index.rst @@ -0,0 +1,233 @@ +.. _nucleo_h753zi_board: + +ST Nucleo H753ZI +################ + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V2-1 debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- Ethernet compliant with IEEE-802.3-2002 (depending on STM32 support) +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - Ethernet RJ45 (depending on STM32 support) + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h753zi.jpg + :align: center + :alt: Nucleo H753ZI + +More information about the board can be found at the `Nucleo H753ZI website`_. + +Hardware +******** + +Nucleo H753ZI provides the following hardware components: + +- STM32H753ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 480 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- 1 MB SRAM +- High-resolution timer (2.1 ns) +- 32-bit timers(2) +- 16-bit timers(12) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(4) +- UART(4) +- USB OTG Full Speed and High Speed(1) +- USB OTG Full Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(3) with 36 channels / 3.6 MSPS +- 12-bit DAC with 2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution +- Cryptographic acceleration: AES 128, 192, 256, TDES, HASH (MD5, SHA-1, SHA-2), HMAC +- Secure firmware upgrade support, Secure access mode + +Supported Features +================== + +The Zephyr nucleo_h753zi board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | counter | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ +| CAN/CANFD | on-chip | canbus | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_h753zi/nucleo_h753zi_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H753ZI board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PB7 +- LD3 : PB14 +- I2C : PB8, PB9 +- ADC1_INP15 : PA3 +- ETH : PA1, PA2, PA7, PB13, PC1, PC4, PC5, PG11, PG13 +- SPI1 NSS/SCK/MISO/MOSI : PD14PA5/PA6/PB5 (Arduino SPI) +- CAN/CANFD : PD0, PD1 + +System Clock +------------ + +Nucleo H753ZI System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H753ZI board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to UART3. Default settings are 115200 8N1. + +CAN, CANFD +---------- + +Requires an external CAN or CANFD transceiver. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h753zi`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 series yet. You can also choose the + ``stm32cubeprogrammer`` runner. + +Flashing +======== + +Nucleo H753ZI board includes an ST-LINK/V2-1 embedded debug tool interface. + +Flashing an application to Nucleo H753ZI +---------------------------------------- + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h753zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h753zi + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h753zi + :maybe-skip-config: + :goals: debug + +.. _Nucleo H753ZI website: + https://www.st.com/en/evaluation-tools/nucleo-h753zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00244518.pdf + +.. _STM32H753ZI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h743-753/stm32h753zi.html + +.. _STM32H753 reference manual: + https://www.st.com/resource/en/reference_manual/dm00314099.pdf diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi.dts b/boards/st/nucleo_h753zi/nucleo_h753zi.dts similarity index 100% rename from boards/arm/nucleo_h753zi/nucleo_h753zi.dts rename to boards/st/nucleo_h753zi/nucleo_h753zi.dts diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi.yaml b/boards/st/nucleo_h753zi/nucleo_h753zi.yaml similarity index 100% rename from boards/arm/nucleo_h753zi/nucleo_h753zi.yaml rename to boards/st/nucleo_h753zi/nucleo_h753zi.yaml diff --git a/boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig b/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig similarity index 85% rename from boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig rename to boards/st/nucleo_h753zi/nucleo_h753zi_defconfig index 42eb8fd0f12157..8dcaab60f611ae 100644 --- a/boards/arm/nucleo_h753zi/nucleo_h753zi_defconfig +++ b/boards/st/nucleo_h753zi/nucleo_h753zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H753XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h753zi/support/openocd.cfg b/boards/st/nucleo_h753zi/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h753zi/support/openocd.cfg rename to boards/st/nucleo_h753zi/support/openocd.cfg diff --git a/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig b/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig new file mode 100644 index 00000000000000..e8fd3484ea7288 --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32H7A3ZI-Q Nucleo board configuration + +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_H7A3ZI_Q + +config USB_DC_HAS_HS_SUPPORT + default y + depends on USB_DC_STM32 + +endif # BOARD_NUCLEO_H7A3ZI_Q diff --git a/boards/st/nucleo_h7a3zi_q/Kconfig.nucleo_h7a3zi_q b/boards/st/nucleo_h7a3zi_q/Kconfig.nucleo_h7a3zi_q new file mode 100644 index 00000000000000..7a00b2bd8fed91 --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/Kconfig.nucleo_h7a3zi_q @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_H7A3ZI_Q + select SOC_STM32H7A3XXQ diff --git a/boards/arm/nucleo_h7a3zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_h7a3zi_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_h7a3zi_q/board.cmake b/boards/st/nucleo_h7a3zi_q/board.cmake similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/board.cmake rename to boards/st/nucleo_h7a3zi_q/board.cmake diff --git a/boards/st/nucleo_h7a3zi_q/board.yml b/boards/st/nucleo_h7a3zi_q/board.yml new file mode 100644 index 00000000000000..0c64ac88228268 --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_h7a3zi_q + vendor: st + socs: + - name: stm32h7a3xx diff --git a/boards/arm/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg b/boards/st/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg rename to boards/st/nucleo_h7a3zi_q/doc/img/nucleo_h7a3zi_q.jpg diff --git a/boards/st/nucleo_h7a3zi_q/doc/index.rst b/boards/st/nucleo_h7a3zi_q/doc/index.rst new file mode 100644 index 00000000000000..484c7e8219649f --- /dev/null +++ b/boards/st/nucleo_h7a3zi_q/doc/index.rst @@ -0,0 +1,206 @@ +.. _nucleo_h7a3zi_q_board: + +ST Nucleo H7A3ZI-Q +################## + +Overview +******** + +The STM32 Nucleo-144 boards offer combinations of performance and power that +provide an affordable and flexible way for users to build prototypes and try +out new concepts. For compatible boards, the SMPS (Switched-Mode Power Supply) +significantly reduces power consumption in Run mode. + +The Arduino-compatible ST Zio connector expands functionality of the Nucleo +open development platform, with a wide choice of specialized Arduino* Uno V3 +shields. + +The STM32 Nucleo-144 board does not require any separate probe as it integrates +the ST-LINK/V3E debugger/programmer. + +The STM32 Nucleo-144 board comes with the STM32 comprehensive free software +libraries and examples available with the STM32Cube MCU Package. + +Key Features + +- STM32 microcontroller in LQFP144 package +- USB OTG or full-speed device (depending on STM32 support) +- 3 user LEDs +- 2 user and reset push-buttons +- 32.768 kHz crystal oscillator +- Board connectors: + + - USB with Micro-AB + - SWD + - ST Zio connector including Arduino* Uno V3 + - ST morpho + +- Flexible power-supply options: ST-LINK USB VBUS or external sources. +- On-board ST-LINK/V3E debugger/programmer with USB re-enumeration +- capability: mass storage, virtual COM port and debug port. +- Comprehensive free software libraries and examples available with the + STM32Cube MCU package. +- Arm* Mbed Enabled* compliant (only for some Nucleo part numbers) + +.. image:: img/nucleo_h7a3zi_q.jpg + :align: center + :alt: Nucleo H7A3ZI-Q + +More information about the board can be found at the `Nucleo H7A3ZI-Q website`_. + +Hardware +******** + +Nucleo H7A3ZI-Q provides the following hardware components: + +- STM32H7A3ZI in LQFP144 package +- ARM 32-bit Cortex-M7 CPU with FPU +- Chrom-ART Accelerator +- Hardware JPEG Codec +- 280 MHz max CPU frequency +- VDD from 1.62 V to 3.6 V +- 2 MB Flash +- ~1.4 Mbytes SRAM +- 32-bit timers(2) +- 16-bit timers(15) +- SPI(6) +- I2C(4) +- I2S (3) +- USART(5) +- UART(5) +- USB OTG Full Speed and High Speed(1) +- CAN FD(2) +- SAI(2) +- SPDIF_Rx(4) +- HDMI_CEC(1) +- Dual Mode Quad SPI(1) +- Camera Interface +- GPIO (up to 114) with external interrupt capability +- 16-bit ADC(2) with 24 channels / 3.6 MSPS +- 12-bit DAC with 1/2 channels(2) +- True Random Number Generator (RNG) +- 16-channel DMA +- LCD-TFT Controller with XGA resolution + +Supported Features +================== + +The Zephyr nucleo_h7a3zi_q board configuration supports the following hardware +features: + ++-------------+------------+------------------------------------+ +| Interface | Controller | Driver/Component | ++=============+============+====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-------------+------------+------------------------------------+ +| UART | on-chip | serial port | ++-------------+------------+------------------------------------+ +| PINMUX | on-chip | pinmux | ++-------------+------------+------------------------------------+ +| GPIO | on-chip | gpio | ++-------------+------------+------------------------------------+ +| PWM | on-chip | pwm | ++-------------+------------+------------------------------------+ +| ADC | on-chip | adc | ++-------------+------------+------------------------------------+ +| Backup SRAM | on-chip | Backup SRAM | ++-------------+------------+------------------------------------+ +| USB OTG HS | on-chip | USB device | ++-------------+------------+------------------------------------+ +| RNG | on-chip | True Random number generator | ++-------------+------------+------------------------------------+ + + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig` + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The Nucleo H7A3ZI-Q board features a ST Zio connector (extended Arduino Uno V3) +and a ST morpho connector. Board is configured as follows: + +- USART3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- USER_PB : PC13 +- LD1 : PB0 +- LD2 : PE1 +- LD3 : PB14 +- ADC1_INP15 : PA3 (Arduino analog, A0) + +System Clock +------------ + +Nucleo H7A3ZI-Q System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock. + +Serial Port +----------- + +Nucleo H7A3ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is +assigned to USART3. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``nucleo_h7a3zi_q`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo H7A3ZI-Q board includes an ST-LINK/V3E embedded debug tool interface. + +Flashing an application to Nucleo H7A3ZI-Q +------------------------------------------ + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h7a3zi_q + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_h7a3zi_q + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_h7a3zi_q + :maybe-skip-config: + :goals: debug + +.. _Nucleo H7A3ZI-Q website: + https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html#overview + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um2408-stm32h7-nucleo144-boards-mb1363-stmicroelectronics.pdf + +.. _STM32H7A3ZI-Q on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3zi.html + +.. _STM32H7A3ZI-Q reference manual: + https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts rename to boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.dts diff --git a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml rename to boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml diff --git a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig similarity index 87% rename from boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig rename to boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig index 86ed02f8045a17..5490e9f1fc7572 100644 --- a/boards/arm/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig +++ b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2021 Electrolance Solutions # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H7A3XXQ=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_h7a3zi_q/support/openocd.cfg b/boards/st/nucleo_h7a3zi_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_h7a3zi_q/support/openocd.cfg rename to boards/st/nucleo_h7a3zi_q/support/openocd.cfg diff --git a/boards/st/nucleo_l011k4/Kconfig.defconfig b/boards/st/nucleo_l011k4/Kconfig.defconfig new file mode 100644 index 00000000000000..f05a90ff9b2111 --- /dev/null +++ b/boards/st/nucleo_l011k4/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-32 development board with STM32L011K4 MCU + +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L011K4 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L011K4 diff --git a/boards/st/nucleo_l011k4/Kconfig.nucleo_l011k4 b/boards/st/nucleo_l011k4/Kconfig.nucleo_l011k4 new file mode 100644 index 00000000000000..e83f4b27968692 --- /dev/null +++ b/boards/st/nucleo_l011k4/Kconfig.nucleo_l011k4 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L011K4 + select SOC_STM32L011XX diff --git a/boards/arm/nucleo_l011k4/board.cmake b/boards/st/nucleo_l011k4/board.cmake similarity index 100% rename from boards/arm/nucleo_l011k4/board.cmake rename to boards/st/nucleo_l011k4/board.cmake diff --git a/boards/st/nucleo_l011k4/board.yml b/boards/st/nucleo_l011k4/board.yml new file mode 100644 index 00000000000000..be64789e75477a --- /dev/null +++ b/boards/st/nucleo_l011k4/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l011k4 + vendor: st + socs: + - name: stm32l011xx diff --git a/boards/arm/nucleo_l011k4/doc/img/nucleo_l011k4.jpg b/boards/st/nucleo_l011k4/doc/img/nucleo_l011k4.jpg similarity index 100% rename from boards/arm/nucleo_l011k4/doc/img/nucleo_l011k4.jpg rename to boards/st/nucleo_l011k4/doc/img/nucleo_l011k4.jpg diff --git a/boards/st/nucleo_l011k4/doc/index.rst b/boards/st/nucleo_l011k4/doc/index.rst new file mode 100644 index 00000000000000..7344ed734adf55 --- /dev/null +++ b/boards/st/nucleo_l011k4/doc/index.rst @@ -0,0 +1,167 @@ +.. _nucleo_l011k4_board: + +ST Nucleo L011K4 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32L011K4 MCU, supports Arduino Nano V3 connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Nano V3 connectivity support allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l011k4.jpg + :align: center + :alt: Nucleo L011K4 + +More information about the board can be found at the `Nucleo L011K4 website`_. + +Hardware +******** +Nucleo L011K4 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package +- Extension resource: + + - Arduino* Nano V3 connectivity + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- One push-button: RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32L011K4 can be found in the +`STM32L0x1 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_l011k4 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l011k4/nucleo_l011k4_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PA4/PA10 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l011k4`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L011K4 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L011K4 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l011k4 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l011k4 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L011K4 website: + https://www.st.com/en/evaluation-tools/nucleo-l011k4.html + +.. _STM32L0x1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l011k4/nucleo_l011k4.dts b/boards/st/nucleo_l011k4/nucleo_l011k4.dts similarity index 100% rename from boards/arm/nucleo_l011k4/nucleo_l011k4.dts rename to boards/st/nucleo_l011k4/nucleo_l011k4.dts diff --git a/boards/arm/nucleo_l011k4/nucleo_l011k4.yaml b/boards/st/nucleo_l011k4/nucleo_l011k4.yaml similarity index 100% rename from boards/arm/nucleo_l011k4/nucleo_l011k4.yaml rename to boards/st/nucleo_l011k4/nucleo_l011k4.yaml diff --git a/boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig b/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig similarity index 78% rename from boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig rename to boards/st/nucleo_l011k4/nucleo_l011k4_defconfig index 62de04f9b1a906..255389258c4804 100644 --- a/boards/arm/nucleo_l011k4/nucleo_l011k4_defconfig +++ b/boards/st/nucleo_l011k4/nucleo_l011k4_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L011XX=y - # Kernel Options due to Low Memory (2k) CONFIG_MAIN_STACK_SIZE=320 CONFIG_IDLE_STACK_SIZE=100 diff --git a/boards/arm/nucleo_l011k4/support/openocd.cfg b/boards/st/nucleo_l011k4/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l011k4/support/openocd.cfg rename to boards/st/nucleo_l011k4/support/openocd.cfg diff --git a/boards/st/nucleo_l031k6/Kconfig.defconfig b/boards/st/nucleo_l031k6/Kconfig.defconfig new file mode 100644 index 00000000000000..335784c41510ee --- /dev/null +++ b/boards/st/nucleo_l031k6/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-32 development board with STM32L031K6 MCU + +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L031K6 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L031K6 diff --git a/boards/st/nucleo_l031k6/Kconfig.nucleo_l031k6 b/boards/st/nucleo_l031k6/Kconfig.nucleo_l031k6 new file mode 100644 index 00000000000000..8e2c0345fc0999 --- /dev/null +++ b/boards/st/nucleo_l031k6/Kconfig.nucleo_l031k6 @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Steven Daglish +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L031K6 + select SOC_STM32L031XX diff --git a/boards/arm/nucleo_l031k6/arduino_nano_r3_connector.dtsi b/boards/st/nucleo_l031k6/arduino_nano_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l031k6/arduino_nano_r3_connector.dtsi rename to boards/st/nucleo_l031k6/arduino_nano_r3_connector.dtsi diff --git a/boards/arm/nucleo_l031k6/board.cmake b/boards/st/nucleo_l031k6/board.cmake similarity index 100% rename from boards/arm/nucleo_l031k6/board.cmake rename to boards/st/nucleo_l031k6/board.cmake diff --git a/boards/st/nucleo_l031k6/board.yml b/boards/st/nucleo_l031k6/board.yml new file mode 100644 index 00000000000000..7fc334c0c2da69 --- /dev/null +++ b/boards/st/nucleo_l031k6/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l031k6 + vendor: st + socs: + - name: stm32l031xx diff --git a/boards/arm/nucleo_l031k6/doc/img/nucleo_l031k6.jpg b/boards/st/nucleo_l031k6/doc/img/nucleo_l031k6.jpg similarity index 100% rename from boards/arm/nucleo_l031k6/doc/img/nucleo_l031k6.jpg rename to boards/st/nucleo_l031k6/doc/img/nucleo_l031k6.jpg diff --git a/boards/st/nucleo_l031k6/doc/index.rst b/boards/st/nucleo_l031k6/doc/index.rst new file mode 100644 index 00000000000000..543d0cc01f892a --- /dev/null +++ b/boards/st/nucleo_l031k6/doc/index.rst @@ -0,0 +1,160 @@ +.. _nucleo_l031k6_board: + +ST Nucleo L031K6 +################ + +Overview +******** +The STM32 Nucleo-32 development board with STM32L031K6 MCU, supports Arduino Nano V3 connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Nano V3 connectivity support allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l031k6.jpg + :align: center + :alt: Nucleo L031K6 + +More information about the board can be found at the `Nucleo L031K6 website`_. + +Hardware +******** +Nucleo L031K6 provides the following hardware components: + +- STM32 microcontroller in LQFP32 package +- Extension resource: + + - Arduino* Nano V3 connectivity + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- One push-button: RESET + +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32L031K6 can be found in the +`STM32L0x1 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l031k6 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l031k6/nucleo_l031k6_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA15 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PA9/PA10 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- LD2 : PB3 + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l031k6`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L031K6 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L031K6 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l031k6 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l031k6 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L031K6 website: + https://www.st.com/en/evaluation-tools/nucleo-l031k6.html + +.. _STM32L0x1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00108282-ultralowpower-stm32l0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744-stm32-nucleo32-boards-mb1180-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l031k6/nucleo_l031k6.dts b/boards/st/nucleo_l031k6/nucleo_l031k6.dts similarity index 100% rename from boards/arm/nucleo_l031k6/nucleo_l031k6.dts rename to boards/st/nucleo_l031k6/nucleo_l031k6.dts diff --git a/boards/arm/nucleo_l031k6/nucleo_l031k6.yaml b/boards/st/nucleo_l031k6/nucleo_l031k6.yaml similarity index 100% rename from boards/arm/nucleo_l031k6/nucleo_l031k6.yaml rename to boards/st/nucleo_l031k6/nucleo_l031k6.yaml diff --git a/boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig b/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig similarity index 78% rename from boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig rename to boards/st/nucleo_l031k6/nucleo_l031k6_defconfig index 83745ca36aff09..06484e88bea72c 100644 --- a/boards/arm/nucleo_l031k6/nucleo_l031k6_defconfig +++ b/boards/st/nucleo_l031k6/nucleo_l031k6_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L031XX=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/nucleo_l031k6/support/openocd.cfg b/boards/st/nucleo_l031k6/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l031k6/support/openocd.cfg rename to boards/st/nucleo_l031k6/support/openocd.cfg diff --git a/boards/st/nucleo_l053r8/Kconfig.defconfig b/boards/st/nucleo_l053r8/Kconfig.defconfig new file mode 100644 index 00000000000000..1e7c587a040ec5 --- /dev/null +++ b/boards/st/nucleo_l053r8/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32L053R8 MCU + +# Copyright (c) 2018 Anthony Kreft +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L053R8 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L053R8 diff --git a/boards/st/nucleo_l053r8/Kconfig.nucleo_l053r8 b/boards/st/nucleo_l053r8/Kconfig.nucleo_l053r8 new file mode 100644 index 00000000000000..69194b81d03c7e --- /dev/null +++ b/boards/st/nucleo_l053r8/Kconfig.nucleo_l053r8 @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Anthony Kreft +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L053R8 + select SOC_STM32L053XX diff --git a/boards/arm/nucleo_l053r8/arduino_r3_connector.dtsi b/boards/st/nucleo_l053r8/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l053r8/arduino_r3_connector.dtsi rename to boards/st/nucleo_l053r8/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l053r8/board.cmake b/boards/st/nucleo_l053r8/board.cmake similarity index 100% rename from boards/arm/nucleo_l053r8/board.cmake rename to boards/st/nucleo_l053r8/board.cmake diff --git a/boards/st/nucleo_l053r8/board.yml b/boards/st/nucleo_l053r8/board.yml new file mode 100644 index 00000000000000..a31629d64436d9 --- /dev/null +++ b/boards/st/nucleo_l053r8/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l053r8 + vendor: st + socs: + - name: stm32l053xx diff --git a/boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8.jpg b/boards/st/nucleo_l053r8/doc/img/nucleo_l053r8.jpg similarity index 100% rename from boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8.jpg rename to boards/st/nucleo_l053r8/doc/img/nucleo_l053r8.jpg diff --git a/boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg b/boards/st/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg similarity index 100% rename from boards/arm/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg rename to boards/st/nucleo_l053r8/doc/img/nucleo_l053r8_connectors.jpg diff --git a/boards/st/nucleo_l053r8/doc/index.rst b/boards/st/nucleo_l053r8/doc/index.rst new file mode 100644 index 00000000000000..e8fdac96751352 --- /dev/null +++ b/boards/st/nucleo_l053r8/doc/index.rst @@ -0,0 +1,176 @@ +.. _nucleo_l053r8_board: + +ST Nucleo L053R8 +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32L053R8 MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l053r8.jpg + :align: center + :alt: Nucleo L053R8 + +More information about the board can be found at the `Nucleo L053R8 website`_. + +Hardware +******** +Nucleo L053R8 provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32L053R8 can be found in the +`STM32L0x3 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_l053r8 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l053r8/nucleo_l053r8_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_l053r8_connectors.jpg + :align: center + :alt: Nucleo L053R8 connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- USER_PB : PC13 +- LD2 : PA5 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l053r8`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L053R8 board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L053R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l053r8 + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l053r8 + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L053R8 website: + https://www.st.com/en/evaluation-tools/nucleo-l053r8.html + +.. _STM32L0x3 reference manual: + https://www.st.com/resource/en/reference_manual/dm00095744.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l053r8/nucleo_l053r8.dts b/boards/st/nucleo_l053r8/nucleo_l053r8.dts similarity index 100% rename from boards/arm/nucleo_l053r8/nucleo_l053r8.dts rename to boards/st/nucleo_l053r8/nucleo_l053r8.dts diff --git a/boards/arm/nucleo_l053r8/nucleo_l053r8.yaml b/boards/st/nucleo_l053r8/nucleo_l053r8.yaml similarity index 100% rename from boards/arm/nucleo_l053r8/nucleo_l053r8.yaml rename to boards/st/nucleo_l053r8/nucleo_l053r8.yaml diff --git a/boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig b/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig similarity index 79% rename from boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig rename to boards/st/nucleo_l053r8/nucleo_l053r8_defconfig index 154565653dafa2..7742224e030f73 100644 --- a/boards/arm/nucleo_l053r8/nucleo_l053r8_defconfig +++ b/boards/st/nucleo_l053r8/nucleo_l053r8_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32L0X=y - -# Platform Configuration -CONFIG_SOC_STM32L053XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l053r8/st_morpho_connector.dtsi b/boards/st/nucleo_l053r8/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l053r8/st_morpho_connector.dtsi rename to boards/st/nucleo_l053r8/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l053r8/support/openocd.cfg b/boards/st/nucleo_l053r8/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l053r8/support/openocd.cfg rename to boards/st/nucleo_l053r8/support/openocd.cfg diff --git a/boards/st/nucleo_l073rz/Kconfig.defconfig b/boards/st/nucleo_l073rz/Kconfig.defconfig new file mode 100644 index 00000000000000..5d5c910151fa9d --- /dev/null +++ b/boards/st/nucleo_l073rz/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32 Nucleo-64 development board with STM32L073RZ MCU + +# Copyright (c) 2018 Ilya Tagunov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L073RZ + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L073RZ diff --git a/boards/st/nucleo_l073rz/Kconfig.nucleo_l073rz b/boards/st/nucleo_l073rz/Kconfig.nucleo_l073rz new file mode 100644 index 00000000000000..06e54aa03c4dbb --- /dev/null +++ b/boards/st/nucleo_l073rz/Kconfig.nucleo_l073rz @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Ilya Tagunov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L073RZ + select SOC_STM32L073XX diff --git a/boards/arm/nucleo_l073rz/arduino_r3_connector.dtsi b/boards/st/nucleo_l073rz/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l073rz/arduino_r3_connector.dtsi rename to boards/st/nucleo_l073rz/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l073rz/board.cmake b/boards/st/nucleo_l073rz/board.cmake similarity index 100% rename from boards/arm/nucleo_l073rz/board.cmake rename to boards/st/nucleo_l073rz/board.cmake diff --git a/boards/st/nucleo_l073rz/board.yml b/boards/st/nucleo_l073rz/board.yml new file mode 100644 index 00000000000000..232170aa06d5d6 --- /dev/null +++ b/boards/st/nucleo_l073rz/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l073rz + vendor: st + socs: + - name: stm32l073xx diff --git a/boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz.jpg b/boards/st/nucleo_l073rz/doc/img/nucleo_l073rz.jpg similarity index 100% rename from boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz.jpg rename to boards/st/nucleo_l073rz/doc/img/nucleo_l073rz.jpg diff --git a/boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg b/boards/st/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg similarity index 100% rename from boards/arm/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg rename to boards/st/nucleo_l073rz/doc/img/nucleo_l073rz_connectors.jpg diff --git a/boards/st/nucleo_l073rz/doc/index.rst b/boards/st/nucleo_l073rz/doc/index.rst new file mode 100644 index 00000000000000..4c4ca788ddd0be --- /dev/null +++ b/boards/st/nucleo_l073rz/doc/index.rst @@ -0,0 +1,190 @@ +.. _nucleo_l073rz_board: + +ST Nucleo L073RZ +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32L073RZ MCU, supports Arduino and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption, and features. + +The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l073rz.jpg + :align: center + :alt: Nucleo L073RZ + +More information about the board can be found at the `Nucleo L073RZ website`_. + +Hardware +******** +Nucleo L073RZ provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino* Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- ARM* mbed* +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: USER and RESET +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +- Support of wide choice of Integrated Development Environments (IDEs) including: + + - IAR + - ARM Keil + - GCC-based IDEs + +More information about STM32L073RZ can be found in the +`STM32L0x3 reference manual`_ + + +Supported Features +================== + +The Zephyr nucleo_l073rz board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi controller | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | Random Number Generator | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l073rz/nucleo_l073rz_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_l073rz_connectors.jpg + :align: center + :alt: Nucleo L073RZ connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PB7 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI1 SCK/MISO/MOSI : PA5/PA6/PA7 (Arduino SPI) +- USER_PB : PC13 +- LD2 : PA5 +- DAC : PA4 +- PWM_2_CH1 : PA5 (might conflict with SPI1) + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l073rz`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L073RZ board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L073RZ +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l073rz + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l073rz + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L073RZ website: + https://www.st.com/en/evaluation-tools/nucleo-l073rz.html + +.. _STM32L0x3 reference manual: + https://www.st.com/resource/en/reference_manual/dm00095744.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz.dts b/boards/st/nucleo_l073rz/nucleo_l073rz.dts similarity index 100% rename from boards/arm/nucleo_l073rz/nucleo_l073rz.dts rename to boards/st/nucleo_l073rz/nucleo_l073rz.dts diff --git a/boards/arm/nucleo_l073rz/nucleo_l073rz.yaml b/boards/st/nucleo_l073rz/nucleo_l073rz.yaml similarity index 100% rename from boards/arm/nucleo_l073rz/nucleo_l073rz.yaml rename to boards/st/nucleo_l073rz/nucleo_l073rz.yaml diff --git a/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig b/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig new file mode 100644 index 00000000000000..f877d5b620a3bc --- /dev/null +++ b/boards/st/nucleo_l073rz/nucleo_l073rz_defconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l073rz/st_morpho_connector.dtsi b/boards/st/nucleo_l073rz/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l073rz/st_morpho_connector.dtsi rename to boards/st/nucleo_l073rz/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l073rz/support/openocd.cfg b/boards/st/nucleo_l073rz/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l073rz/support/openocd.cfg rename to boards/st/nucleo_l073rz/support/openocd.cfg diff --git a/boards/st/nucleo_l152re/Kconfig.nucleo_l152re b/boards/st/nucleo_l152re/Kconfig.nucleo_l152re new file mode 100644 index 00000000000000..04252bf55d470f --- /dev/null +++ b/boards/st/nucleo_l152re/Kconfig.nucleo_l152re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L152RE + select SOC_STM32L152XE diff --git a/boards/arm/nucleo_l152re/arduino_r3_connector.dtsi b/boards/st/nucleo_l152re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l152re/arduino_r3_connector.dtsi rename to boards/st/nucleo_l152re/arduino_r3_connector.dtsi diff --git a/boards/arm/cc3220sf_launchxl/board.cmake b/boards/st/nucleo_l152re/board.cmake similarity index 100% rename from boards/arm/cc3220sf_launchxl/board.cmake rename to boards/st/nucleo_l152re/board.cmake diff --git a/boards/st/nucleo_l152re/board.yml b/boards/st/nucleo_l152re/board.yml new file mode 100644 index 00000000000000..2838a81f7b0bde --- /dev/null +++ b/boards/st/nucleo_l152re/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l152re + vendor: st + socs: + - name: stm32l152xe diff --git a/boards/arm/nucleo_l152re/doc/img/nucleo_l152re.jpg b/boards/st/nucleo_l152re/doc/img/nucleo_l152re.jpg similarity index 100% rename from boards/arm/nucleo_l152re/doc/img/nucleo_l152re.jpg rename to boards/st/nucleo_l152re/doc/img/nucleo_l152re.jpg diff --git a/boards/arm/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg b/boards/st/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg similarity index 100% rename from boards/arm/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg rename to boards/st/nucleo_l152re/doc/img/nucleo_l152re_connectors.jpg diff --git a/boards/st/nucleo_l152re/doc/index.rst b/boards/st/nucleo_l152re/doc/index.rst new file mode 100644 index 00000000000000..9d8e31a6a6e3a8 --- /dev/null +++ b/boards/st/nucleo_l152re/doc/index.rst @@ -0,0 +1,187 @@ +.. _nucleo_l152re_board: + +ST Nucleo L152RE +################ + +Overview +******** +The STM32 Nucleo-64 development board with STM32L152RE MCU, supports Arduino™ and ST morpho connectivity. + +The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts, +and build prototypes with the STM32 microcontroller, choosing from the various +combinations of performance, power consumption and features. + +The Arduino Uno V3 connectivity support and the ST morpho headers allow easy functionality +expansion of the STM32 Nucleo open development platform with a wide choice of +specialized shields. + +The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer. + +The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together +with various packaged software examples. + +.. image:: img/nucleo_l152re.jpg + :align: center + :alt: NUCLEO-L152RE + +More information about the board can be found at the `Nucleo L152RE website`_. + +Hardware +******** +Nucleo L152RE provides the following hardware components: + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector: + + - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1 + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: + + - USB communication (LD1), user LED (LD2), power LED (LD3) + +- Two push-buttons: B1 (USER/blue) and B2 (RESET/black) +- USB re-enumeration capability. Three different interfaces supported on USB: + + - Virtual COM port + - Mass storage + - Debug port + +More information about STM32L152RE can be found here: + +- `STM32L152 reference manual`_ +- `STM32L152 data sheet`_ + +Supported Features +================== + +The Zephyr nucleo_l152re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| EEPROM | on-chip | eeprom | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/nucleo_l152re/nucleo_l152re_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/nucleo_l152re_connectors.jpg + :align: center + :alt: Nucleo L152RE connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- B1 (USER/blue) : PC13 +- LD1 : PA5 +- DAC : PA4 +- PWM_3_CH1 : PA6 + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``nucleo_l152re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L152RE board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo L152RE +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_l152re + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l152re + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _Nucleo L152RE website: + https://www.st.com/en/evaluation-tools/nucleo-l152re.html + +.. _STM32L152 reference manual: + https://www.st.com/resource/en/reference_manual/cd00240193.pdf + +.. _STM32L152 data sheet: + https://www.st.com/resource/en/datasheet/stm32l152re.pdf + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf diff --git a/boards/arm/nucleo_l152re/nucleo_l152re.dts b/boards/st/nucleo_l152re/nucleo_l152re.dts similarity index 100% rename from boards/arm/nucleo_l152re/nucleo_l152re.dts rename to boards/st/nucleo_l152re/nucleo_l152re.dts diff --git a/boards/arm/nucleo_l152re/nucleo_l152re.yaml b/boards/st/nucleo_l152re/nucleo_l152re.yaml similarity index 100% rename from boards/arm/nucleo_l152re/nucleo_l152re.yaml rename to boards/st/nucleo_l152re/nucleo_l152re.yaml diff --git a/boards/arm/nucleo_l152re/nucleo_l152re_defconfig b/boards/st/nucleo_l152re/nucleo_l152re_defconfig similarity index 85% rename from boards/arm/nucleo_l152re/nucleo_l152re_defconfig rename to boards/st/nucleo_l152re/nucleo_l152re_defconfig index b8045bd70a5ea0..02fb0a26c54889 100644 --- a/boards/arm/nucleo_l152re/nucleo_l152re_defconfig +++ b/boards/st/nucleo_l152re/nucleo_l152re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L1X=y -CONFIG_SOC_STM32L152XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l152re/st_morpho_connector.dtsi b/boards/st/nucleo_l152re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l152re/st_morpho_connector.dtsi rename to boards/st/nucleo_l152re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l152re/support/openocd.cfg b/boards/st/nucleo_l152re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l152re/support/openocd.cfg rename to boards/st/nucleo_l152re/support/openocd.cfg diff --git a/boards/st/nucleo_l412rb_p/Kconfig.defconfig b/boards/st/nucleo_l412rb_p/Kconfig.defconfig new file mode 100644 index 00000000000000..1ea0e9a194a12e --- /dev/null +++ b/boards/st/nucleo_l412rb_p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L412RB Nucleo board configuration + +# Copyright (c) 2021 Guðni Már Gilbert +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L412RB_P + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L412RB_P diff --git a/boards/st/nucleo_l412rb_p/Kconfig.nucleo_l412rb_p b/boards/st/nucleo_l412rb_p/Kconfig.nucleo_l412rb_p new file mode 100644 index 00000000000000..9faaea408546a4 --- /dev/null +++ b/boards/st/nucleo_l412rb_p/Kconfig.nucleo_l412rb_p @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Guðni Már Gilbert +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L412RB_P + select SOC_STM32L412XX diff --git a/boards/arm/nucleo_l412rb_p/arduino_r3_connector.dtsi b/boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l412rb_p/arduino_r3_connector.dtsi rename to boards/st/nucleo_l412rb_p/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l412rb_p/board.cmake b/boards/st/nucleo_l412rb_p/board.cmake similarity index 100% rename from boards/arm/nucleo_l412rb_p/board.cmake rename to boards/st/nucleo_l412rb_p/board.cmake diff --git a/boards/st/nucleo_l412rb_p/board.yml b/boards/st/nucleo_l412rb_p/board.yml new file mode 100644 index 00000000000000..92ab56d2df399f --- /dev/null +++ b/boards/st/nucleo_l412rb_p/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l412rb_p + vendor: st + socs: + - name: stm32l412xx diff --git a/boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg b/boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg similarity index 100% rename from boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg rename to boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p.jpg diff --git a/boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg b/boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg rename to boards/st/nucleo_l412rb_p/doc/img/nucleo_l412rb_p_pinout.jpg diff --git a/boards/st/nucleo_l412rb_p/doc/index.rst b/boards/st/nucleo_l412rb_p/doc/index.rst new file mode 100644 index 00000000000000..b423f06c17489c --- /dev/null +++ b/boards/st/nucleo_l412rb_p/doc/index.rst @@ -0,0 +1,269 @@ +.. _nucleo_l412rb_p_board: + +ST Nucleo L412RB-P +################## + +Overview +******** + +The Nucleo L412RB board features an ARM Cortex-M4 based STM32L412RB MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L412RB board: + +- STM32 microcontroller in LQFP64 package +- 1 user LED shared with ARDUINO |reg| +- 1 user and 1 reset push-buttons +- 32.768 kHz crystal oscillator +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK debugger/programmer with USB re-enumeration capability: mass storage, Virtual COM port and debug port +- Flexible power-supply options: ST-LINK, USB VBUS, or external sources + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Board specific features + + - External SMPS to generate Vcore logic supply + - 24 MHz HSE + - Board connectors: + + - External SMPS experimentation dedicated connector + - Micro-AB or Mini-AB USB connector for the ST-LINK + - MIPI® debug connector + + - Arm® Mbed Enabled |trade| compliant + +.. image:: img/nucleo_l412rb_p.jpg + :align: center + :alt: Nucleo L412RB + +More information about the board can be found at the `Nucleo L412RB-P website`_. + +Hardware +******** + +Nucleo L412RB-P provides the following hardware components: + +- STM32L412RBT6 in LQFP64 package +- Ultra-low-power with FlexPowerControl + + - 1.71 V to 3.6 V power supply + - -40 °C to 85/125 °C temperature range + - 300 nA in VBAT mode: supply for RTC and 32x32-bit backup registers + - 16 nA Shutdown mode (4 wakeup pins) + - 32 nA Standby mode (4 wakeup pins) + - 245 nA Standby mode with RTC + - 0.7 |micro| A Stop 2 mode, 0.95 |micro| A with RTC + - 79 |micro| A/MHz run mode (LDO Mode) + - 28 |micro| A/MHz run mode (@3.3 V SMPS Mode) + - Batch acquisition mode (BAM) + - 4 |micro| s wakeup from Stop mode + - Brown out reset (BOR) + - Interconnect matrix + +- Core: Arm |reg| 32-bit Cortex |reg| -M4 CPU with FPU, Adaptive real-time accelerator (ART Accelerator |trade| ) allowing 0-wait-state execution from Flash memory, frequency up to 80 MHz, MPU, 100DMIPS and DSP instructions +- Performance benchmark + + - 1.25 DMIPS/MHz (Drystone 2.1) + - 273.55 CoreMark |reg| (3.42 CoreMark/MHz @ 80 MHz) + +- Energy benchmark + + - 442 ULPMark-CP® + - 165 ULPMark-PP® + +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by LSE (better than |plusminus| 0.25 % accuracy) + - Internal 48 MHz with clock recovery + - PLL for system clock + +- Up to 52 fast I/Os, most 5 V-tolerant +- RTC with HW calendar, alarms and calibration +- Up to 12 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 10x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 2x 16-bit general purpose + - 1x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Memories + + - 128 KB single bank Flash, proprietary code readout protection + - 40 KB of SRAM including 8 KB with hardware parity check + - Quad SPI memory interface with XIP capability + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 |micro| A/Msps + - 2x operational amplifiers with built-in PGA + - 1x ultra-low-power comparator + - Accurate 2.5 V or 2.048 V reference voltage buffered output + +- 12x communication interfaces + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 3x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 2x SPIs (and 1x Quad SPI) + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- All packages are ECOPACK2 compliant + +Note: the current board revision is C. (MB1319C) + +More information about STM32L412RB can be found here: + +- `STM32L412RB on www.st.com`_ +- `STM32L412 reference manual`_ + +Supported Features +================== + +The Zephyr ``nucleo_l412rb_p`` board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig` + + +Connections and IOs +=================== + +Nucleo L412RB-P Board has 5 GPIO controllers (Ports A, B, C, D and H). These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l412rb_p_pinout.jpg + :align: center + :alt: Nucleo L412RB-P + +For more details please refer to `ST Nucleo L412RB-P User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- LPUART1 TX/RX : PA2/PA3 +- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) +- SPI2 CS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) +- UART1 TX/RX : PA9/PA10 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD4 : PB13 + +Note: SPI2 CS pin (PB12) is not located on the Arduino connector. + +System Clock +------------ + +Nucleo L412RB-P System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L412RB-P board has 3 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned to LPUART1. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l412rb_p`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L412RB-P board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L412RB-P +------------------------------------------ + +Connect the Nucleo L412RB-P to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l412rb_p + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_l412rb_p + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l412rb_p + :maybe-skip-config: + :goals: debug + +.. _Nucleo L412RB-P website: + https://www.st.com/en/evaluation-tools/nucleo-l412rb-p.html + +.. _ST Nucleo L412RB-P User Manual: + https://www.st.com/resource/en/user_manual/dm00387966-stm32-nucleo-64-p-boards-stmicroelectronics.pdf + +.. _STM32L412RB on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l412rb.html + +.. _STM32L412 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940-stm32l41xxx42xxx43xxx44xxx45xxx46xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.dts b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts similarity index 100% rename from boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.dts rename to boards/st/nucleo_l412rb_p/nucleo_l412rb_p.dts diff --git a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.yaml b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml similarity index 100% rename from boards/arm/nucleo_l412rb_p/nucleo_l412rb_p.yaml rename to boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml diff --git a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig similarity index 85% rename from boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig rename to boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig index a3541daa6f6ab7..349e958591e43c 100644 --- a/boards/arm/nucleo_l412rb_p/nucleo_l412rb_p_defconfig +++ b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L412XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l412rb_p/support/openocd.cfg b/boards/st/nucleo_l412rb_p/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l412rb_p/support/openocd.cfg rename to boards/st/nucleo_l412rb_p/support/openocd.cfg diff --git a/boards/st/nucleo_l432kc/Kconfig.defconfig b/boards/st/nucleo_l432kc/Kconfig.defconfig new file mode 100644 index 00000000000000..2820946d23a7ed --- /dev/null +++ b/boards/st/nucleo_l432kc/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32L432KC Nucleo board configuration + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L432KC + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L432KC diff --git a/boards/st/nucleo_l432kc/Kconfig.nucleo_l432kc b/boards/st/nucleo_l432kc/Kconfig.nucleo_l432kc new file mode 100644 index 00000000000000..800f96f6c013e6 --- /dev/null +++ b/boards/st/nucleo_l432kc/Kconfig.nucleo_l432kc @@ -0,0 +1,5 @@ +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L432KC + select SOC_STM32L432XX diff --git a/boards/arm/nucleo_l432kc/board.cmake b/boards/st/nucleo_l432kc/board.cmake similarity index 100% rename from boards/arm/nucleo_l432kc/board.cmake rename to boards/st/nucleo_l432kc/board.cmake diff --git a/boards/st/nucleo_l432kc/board.yml b/boards/st/nucleo_l432kc/board.yml new file mode 100644 index 00000000000000..25ccfc0ddf9c4f --- /dev/null +++ b/boards/st/nucleo_l432kc/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l432kc + vendor: st + socs: + - name: stm32l432xx diff --git a/boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc.jpg b/boards/st/nucleo_l432kc/doc/img/nucleo_l432kc.jpg similarity index 100% rename from boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc.jpg rename to boards/st/nucleo_l432kc/doc/img/nucleo_l432kc.jpg diff --git a/boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg b/boards/st/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg similarity index 100% rename from boards/arm/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg rename to boards/st/nucleo_l432kc/doc/img/nucleo_l432kc_arduino_nano.jpg diff --git a/boards/st/nucleo_l432kc/doc/index.rst b/boards/st/nucleo_l432kc/doc/index.rst new file mode 100644 index 00000000000000..ddbfaec6a805ee --- /dev/null +++ b/boards/st/nucleo_l432kc/doc/index.rst @@ -0,0 +1,229 @@ +.. _nucleo_l432kc_board: + +ST Nucleo L432KC +################ + +Overview +******** + +The Nucleo L432KC board features an ARM Cortex-M4 based STM32L432KC MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L432KC board: + +- STM32 microcontroller in UFQFPN32 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD2), user LED (LD3) +- One push-button: RESET + +.. image:: img/nucleo_l432kc.jpg + :align: center + :alt: Nucleo L432KC + +More information about the board can be found at the `Nucleo L432KC website`_. + +Hardware +******** + +The STM32L432KC SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 2x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 26 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 256 KB single bank Flash, proprietary code readout protection + - Up to 64 KB of SRAM including 16 KB with hardware parity check + - Quad SPI memory interface + +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 1x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 13x communication interfaces + + - USB OTG 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAIs (serial audio interface) + - 2x I2C FM+(1 Mbit/s), SMBus/PMBus + - 3x USARTs (ISO 7816, LIN, IrDA, modem) + - 2x SPIs (3x SPIs with the Quad SPI) + - CAN (2.0B Active) + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L432KC can be found here: + +- `STM32L432KC on www.st.com`_ +- `STM32L432 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l432kc board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l432kc/nucleo_l432kc_defconfig` + + +Connections and IOs +=================== + +Nucleo L432KC Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l432kc_arduino_nano.jpg + :align: center + :alt: Nucleo L432KC Arduino connectors + +For more details please refer to `STM32 Nucleo-32 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- LD3 : PB3 + +System Clock +------------ + +Nucleo L432KC System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L432KC board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l432kc`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L432KC +---------------------------------------- + +Connect the Nucleo L432KC to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l432kc + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l432kc + :maybe-skip-config: + :goals: debug + +.. _Nucleo L432KC website: + https://www.st.com/en/evaluation-tools/nucleo-l432kc.html + +.. _STM32 Nucleo-32 board User Manual: + https://www.st.com/resource/en/user_manual/dm00231744.pdf + +.. _STM32L432KC on www.st.com: + https://www.st.com/en/microcontrollers/stm32l432kc.html + +.. _STM32L432 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l432kc/nucleo_l432kc.dts b/boards/st/nucleo_l432kc/nucleo_l432kc.dts similarity index 100% rename from boards/arm/nucleo_l432kc/nucleo_l432kc.dts rename to boards/st/nucleo_l432kc/nucleo_l432kc.dts diff --git a/boards/arm/nucleo_l432kc/nucleo_l432kc.yaml b/boards/st/nucleo_l432kc/nucleo_l432kc.yaml similarity index 100% rename from boards/arm/nucleo_l432kc/nucleo_l432kc.yaml rename to boards/st/nucleo_l432kc/nucleo_l432kc.yaml diff --git a/boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig b/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig similarity index 85% rename from boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig rename to boards/st/nucleo_l432kc/nucleo_l432kc_defconfig index d4bf42213f4b2f..82ee7285d52d8a 100644 --- a/boards/arm/nucleo_l432kc/nucleo_l432kc_defconfig +++ b/boards/st/nucleo_l432kc/nucleo_l432kc_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L432XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l432kc/support/openocd.cfg b/boards/st/nucleo_l432kc/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l432kc/support/openocd.cfg rename to boards/st/nucleo_l432kc/support/openocd.cfg diff --git a/boards/st/nucleo_l433rc_p/Kconfig.defconfig b/boards/st/nucleo_l433rc_p/Kconfig.defconfig new file mode 100644 index 00000000000000..5db4cd8f6d3d27 --- /dev/null +++ b/boards/st/nucleo_l433rc_p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L433RC Nucleo board configuration + +# Copyright (c) 2021 Matija Tudan +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L433RC_P + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L433RC_P diff --git a/boards/st/nucleo_l433rc_p/Kconfig.nucleo_l433rc_p b/boards/st/nucleo_l433rc_p/Kconfig.nucleo_l433rc_p new file mode 100644 index 00000000000000..e2e57e6890b524 --- /dev/null +++ b/boards/st/nucleo_l433rc_p/Kconfig.nucleo_l433rc_p @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Matija Tudan +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L433RC_P + select SOC_STM32L433XX diff --git a/boards/arm/nucleo_l433rc_p/arduino_r3_connector.dtsi b/boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l433rc_p/arduino_r3_connector.dtsi rename to boards/st/nucleo_l433rc_p/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l433rc_p/board.cmake b/boards/st/nucleo_l433rc_p/board.cmake similarity index 100% rename from boards/arm/nucleo_l433rc_p/board.cmake rename to boards/st/nucleo_l433rc_p/board.cmake diff --git a/boards/st/nucleo_l433rc_p/board.yml b/boards/st/nucleo_l433rc_p/board.yml new file mode 100644 index 00000000000000..03c1f3c6f6fb6d --- /dev/null +++ b/boards/st/nucleo_l433rc_p/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l433rc_p + vendor: st + socs: + - name: stm32l433xx diff --git a/boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg b/boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg similarity index 100% rename from boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg rename to boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p.jpg diff --git a/boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg b/boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg rename to boards/st/nucleo_l433rc_p/doc/img/nucleo_l433rc_p_pinout.jpg diff --git a/boards/st/nucleo_l433rc_p/doc/index.rst b/boards/st/nucleo_l433rc_p/doc/index.rst new file mode 100644 index 00000000000000..8981c68b2361ff --- /dev/null +++ b/boards/st/nucleo_l433rc_p/doc/index.rst @@ -0,0 +1,234 @@ +.. _nucleo_l433rc_board: + +ST Nucleo L433RC +################ + +Overview +******** + +The Nucleo L433RC board features an ARM Cortex-M4 based STM32L433RC MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L433RC board: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), power LED (LD3), user LED (LD4) +- One push-button: RESET + +.. image:: img/nucleo_l433rc_p.jpg + :align: center + :alt: Nucleo L433RC + +More information about the board can be found at the `Nucleo L433RC-P website`_. + +Hardware +******** + +The STM32L433RC SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 21 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 11x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 2x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 83 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 256 KB single bank Flash, proprietary code readout protection + - 64 KB of SRAM including 16 KB with hardware parity check + - Quad SPI memory interface + +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC output channels, low-power sample and hold + - 1x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 17x communication interfaces + + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAI (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 4x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 3x SPIs (and 1x Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L433RC can be found here: + +- `STM32L433RC on www.st.com`_ +- `STM32L432 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l433rc_p board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig` + + +Connections and IOs +=================== + +Nucleo L433RC-P Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l433rc_p_pinout.jpg + :align: center + :alt: Nucleo L433RC-P + +For more details please refer to `ST Nucleo L433RC-P User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- LPUART_1_TX : PA2 +- LPUART_1_RX : PA3 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- LD4 : PB13 +- SPI_1: NSS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 +- SPI_2: NSS/SCK/MISO/MOSI : PA11/PB13/PB14/PB15 (Arduino SPI) + +System Clock +------------ + +Nucleo L433RC-P System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L433RC-P board has 4 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned +to LPUART1. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l433rc_p`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L433RC-P board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L433RC-P +------------------------------------------ + +Connect the Nucleo L433RC-P to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ picocom /dev/ttyACM0 -b 115200 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l433rc_p + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! nucleo_l433rc_p + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l433rc_p + :maybe-skip-config: + :goals: debug + +.. _Nucleo L433RC-P website: + https://www.st.com/en/evaluation-tools/nucleo-l433rc-p.html + +.. _ST Nucleo L433RC-P User Manual: + https://www.st.com/resource/en/user_manual/dm00387966.pdf + +.. _STM32L433RC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l433rc.html + +.. _STM32L432 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.dts b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.dts similarity index 100% rename from boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.dts rename to boards/st/nucleo_l433rc_p/nucleo_l433rc_p.dts diff --git a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.yaml b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml similarity index 100% rename from boards/arm/nucleo_l433rc_p/nucleo_l433rc_p.yaml rename to boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml diff --git a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig similarity index 85% rename from boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig rename to boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig index 72a116e3fec1e4..82ee7285d52d8a 100644 --- a/boards/arm/nucleo_l433rc_p/nucleo_l433rc_p_defconfig +++ b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L433XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/nucleo_l433rc_p/support/openocd.cfg b/boards/st/nucleo_l433rc_p/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l433rc_p/support/openocd.cfg rename to boards/st/nucleo_l433rc_p/support/openocd.cfg diff --git a/boards/st/nucleo_l452re/Kconfig.defconfig b/boards/st/nucleo_l452re/Kconfig.defconfig new file mode 100644 index 00000000000000..1758af6e18caab --- /dev/null +++ b/boards/st/nucleo_l452re/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32L452RE Nucleo board configuration +# +# Copyright (c) 2019 Libre Solar Technologies GmbH +# +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L452RE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L452RE diff --git a/boards/st/nucleo_l452re/Kconfig.nucleo_l452re b/boards/st/nucleo_l452re/Kconfig.nucleo_l452re new file mode 100644 index 00000000000000..08df2bfc05fef7 --- /dev/null +++ b/boards/st/nucleo_l452re/Kconfig.nucleo_l452re @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Libre Solar Technologies GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L452RE + select SOC_STM32L452XX diff --git a/boards/arm/nucleo_l452re/arduino_r3_connector.dtsi b/boards/st/nucleo_l452re/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l452re/arduino_r3_connector.dtsi rename to boards/st/nucleo_l452re/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l452re/board.cmake b/boards/st/nucleo_l452re/board.cmake similarity index 100% rename from boards/arm/nucleo_l452re/board.cmake rename to boards/st/nucleo_l452re/board.cmake diff --git a/boards/st/nucleo_l452re/board.yml b/boards/st/nucleo_l452re/board.yml new file mode 100644 index 00000000000000..9bbf96304971ed --- /dev/null +++ b/boards/st/nucleo_l452re/board.yml @@ -0,0 +1,7 @@ +board: + name: nucleo_l452re + vendor: st + socs: + - name: stm32l452xx + variants: + - name: p diff --git a/boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p.jpg b/boards/st/nucleo_l452re/doc/img/nucleo_l452re_p.jpg similarity index 100% rename from boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p.jpg rename to boards/st/nucleo_l452re/doc/img/nucleo_l452re_p.jpg diff --git a/boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg b/boards/st/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg rename to boards/st/nucleo_l452re/doc/img/nucleo_l452re_p_pinout.jpg diff --git a/boards/arm/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg b/boards/st/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg similarity index 100% rename from boards/arm/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg rename to boards/st/nucleo_l452re/doc/img/nucleo_l452re_pinout.jpg diff --git a/boards/st/nucleo_l452re/doc/index.rst b/boards/st/nucleo_l452re/doc/index.rst new file mode 100644 index 00000000000000..57839f931c5d2d --- /dev/null +++ b/boards/st/nucleo_l452re/doc/index.rst @@ -0,0 +1,266 @@ +.. _nucleo_l452re_board: + +ST Nucleo L452RE +################ + +Overview +******** + +The Nucleo L452RE(-P) boards feature an ARM Cortex-M4 based STM32L452RE MCU +with a wide range of connectivity support and configurations. There are two variants: + +- ST Nucleo L452RE +- ST Nucleo L452RE-P + +Here some highlights of these boards: + +- STM32 microcontroller in LQFP64 package +- Arduino Uno V3 connectivity +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- One push-button: RESET + +.. image:: img/nucleo_l452re_p.jpg + :align: center + :alt: Nucleo L452RE-P + +The main difference between the ST Nucleo L452RE and the L452RE-P (note the missing +"-P" at the end) lays in the External Switched Mode Power Supply (SMPS) included in +the P series. + +More information about the boards can be found at the `Nucleo L452RE website`_ and +the `Nucleo L452RE-P website`_. + +Hardware +******** + +The STM32L452RE SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 2 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 3 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 12x timers: + + - 1x 16-bit advanced motor-control + - 1x 32-bit and 3x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 26 fast I/Os, most 5 V-tolerant +- Memories + + - Up to 512 KB single bank Flash, proprietary code readout protection + - 160 KB of SRAM including 32 KB with hardware parity check + - Quad SPI memory interface + +- Rich analog peripherals (independent supply) + + - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 1x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 17x communication interfaces + - USB 2.0 full-speed crystal less solution with LPM and BCD + - 1x SAI (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 3x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x UART (LIN, IrDA, modem) + - 1x LPUART (Stop 2 wake-up) + - 3x SPIs (and 1x Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L452RE can be found here: + +- `STM32L452RE on www.st.com`_ +- `STM32L452 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l452re board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_defconfig` + +And for Nucleo L452RE-P in this defconfig file: +:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig` + + +Connections and IOs +=================== + +Nucleo L452RE Board has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l452re_pinout.jpg + :align: center + :alt: Nucleo L452RE Pinout + +.. image:: img/nucleo_l452re_p_pinout.jpg + :align: center + :alt: Nucleo L452RE-P Pinout + +For more details please refer to `ST Nucleo L452RE User Manual`_ or +`ST Nucleo L452RE-P User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- SPI_NSS : PB6 +- SPI_SCK : PA5 +- SPI_MISO : PA6 +- SPI_MOSI : PA7 +- CAN_TX : PA11 +- CAN_RX : PA12 +- LD2 : PA5 + +System Clock +------------ + +Nucleo L452RE System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L452RE board has 3 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l452re`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L452RE +---------------------------------------- + +Connect the Nucleo L452RE to your host computer using the USB port, +then run a serial host program to connect with your Nucleo board. + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Now build and flash an application. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l452re + :goals: build flash + +For Nucleo L452RE-P, use this command instead: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l452re/stm32l452xx/p + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + $ Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l452re + :maybe-skip-config: + :goals: debug + +.. _Nucleo L452RE website: + https://www.st.com/en/evaluation-tools/nucleo-l452re.html + +.. _Nucleo L452RE-P website: + https://www.st.com/en/evaluation-tools/nucleo-l452re-p.html + +.. _ST Nucleo L452RE User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _ST Nucleo L452RE-P User Manual: + https://www.st.com/resource/en/user_manual/dm00387966.pdf + +.. _STM32L452RE on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l452re.html + +.. _STM32L452 reference manual: + https://www.st.com/resource/en/reference_manual/dm00151940.pdf diff --git a/boards/arm/nucleo_l452re/nucleo_l452re.dts b/boards/st/nucleo_l452re/nucleo_l452re.dts similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re.dts rename to boards/st/nucleo_l452re/nucleo_l452re.dts diff --git a/boards/arm/nucleo_l452re/nucleo_l452re.yaml b/boards/st/nucleo_l452re/nucleo_l452re.yaml similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re.yaml rename to boards/st/nucleo_l452re/nucleo_l452re.yaml diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_common.dtsi b/boards/st/nucleo_l452re/nucleo_l452re_common.dtsi similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re_common.dtsi rename to boards/st/nucleo_l452re/nucleo_l452re_common.dtsi diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_defconfig b/boards/st/nucleo_l452re/nucleo_l452re_defconfig similarity index 85% rename from boards/arm/nucleo_l452re/nucleo_l452re_defconfig rename to boards/st/nucleo_l452re/nucleo_l452re_defconfig index 14b7ffdd20928b..94950b2862fcaa 100644 --- a/boards/arm/nucleo_l452re/nucleo_l452re_defconfig +++ b/boards/st/nucleo_l452re/nucleo_l452re_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L452XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l452re/nucleo_l452re_p.dts b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.dts similarity index 100% rename from boards/arm/nucleo_l452re/nucleo_l452re_p.dts rename to boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.dts diff --git a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml new file mode 100644 index 00000000000000..86e8a58034f761 --- /dev/null +++ b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml @@ -0,0 +1,17 @@ +identifier: nucleo_l452re/stm32l452xx/p +name: ST Nucleo L452RE-P +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 160 +flash: 512 +supported: + - nvs + - pwm + - can + - counter + - spi +vendor: st diff --git a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig new file mode 100644 index 00000000000000..94950b2862fcaa --- /dev/null +++ b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l452re/st_morpho_connector.dtsi b/boards/st/nucleo_l452re/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l452re/st_morpho_connector.dtsi rename to boards/st/nucleo_l452re/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l452re/support/openocd.cfg b/boards/st/nucleo_l452re/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l452re/support/openocd.cfg rename to boards/st/nucleo_l452re/support/openocd.cfg diff --git a/boards/st/nucleo_l476rg/Kconfig.defconfig b/boards/st/nucleo_l476rg/Kconfig.defconfig new file mode 100644 index 00000000000000..276fdc47b58095 --- /dev/null +++ b/boards/st/nucleo_l476rg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32L476RG Nucleo board configuration + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L476RG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L476RG diff --git a/boards/st/nucleo_l476rg/Kconfig.nucleo_l476rg b/boards/st/nucleo_l476rg/Kconfig.nucleo_l476rg new file mode 100644 index 00000000000000..dd3608327d185e --- /dev/null +++ b/boards/st/nucleo_l476rg/Kconfig.nucleo_l476rg @@ -0,0 +1,5 @@ +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L476RG + select SOC_STM32L476XX diff --git a/boards/arm/nucleo_l476rg/arduino_r3_connector.dtsi b/boards/st/nucleo_l476rg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l476rg/arduino_r3_connector.dtsi rename to boards/st/nucleo_l476rg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l476rg/board.cmake b/boards/st/nucleo_l476rg/board.cmake similarity index 100% rename from boards/arm/nucleo_l476rg/board.cmake rename to boards/st/nucleo_l476rg/board.cmake diff --git a/boards/st/nucleo_l476rg/board.yml b/boards/st/nucleo_l476rg/board.yml new file mode 100644 index 00000000000000..c6b21713e34ec1 --- /dev/null +++ b/boards/st/nucleo_l476rg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l476rg + vendor: st + socs: + - name: stm32l476xx diff --git a/boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg.jpg b/boards/st/nucleo_l476rg/doc/img/nucleo_l476rg.jpg similarity index 100% rename from boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg.jpg rename to boards/st/nucleo_l476rg/doc/img/nucleo_l476rg.jpg diff --git a/boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg b/boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg similarity index 100% rename from boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg rename to boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_arduino.jpg diff --git a/boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg b/boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg similarity index 100% rename from boards/arm/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg rename to boards/st/nucleo_l476rg/doc/img/nucleo_l476rg_morpho.jpg diff --git a/boards/st/nucleo_l476rg/doc/index.rst b/boards/st/nucleo_l476rg/doc/index.rst new file mode 100644 index 00000000000000..a45b18b339e189 --- /dev/null +++ b/boards/st/nucleo_l476rg/doc/index.rst @@ -0,0 +1,243 @@ +.. _nucleo_l476rg_board: + +ST Nucleo L476RG +################ + +Overview +******** + +The Nucleo L476RG board features an ARM Cortex-M4 based STM32L476RG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L476RG board: + + +- STM32 microcontroller in QFP64 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three LEDs: USB communication (LD1), user LED (LD2), power LED (LD3) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_l476rg.jpg + :align: center + :alt: Nucleo L476RG + +More information about the board can be found at the `Nucleo L476RG website`_. + +Hardware +******** + +The STM32L476RG SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 18x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L476RG can be found here: + +- `STM32L476RG on www.st.com`_ +- `STM32L476 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l476rg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l476rg/nucleo_l476rg_defconfig` + + +Connections and IOs +=================== + +Nucleo L476RG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo_l476rg_arduino.jpg + :align: center + :alt: Nucleo L476RG Arduino connectors +.. image:: img/nucleo_l476rg_morpho.jpg + :align: center + :alt: Nucleo L476RG Morpho connectors + +For more details please refer to `STM32 Nucleo-64 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1 TX/RX : PA9/PA10 +- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual Port Com) +- UART_3 TX/RX : PB10/PB11 +- I2C_1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C_3 SCL/SDA : PC0/PC1 +- SPI_1 CS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI) +- SPI_2 CS/SCK/MISO/MOSI : PB12/PB13/PB14/PB15 +- SPI_3 CS/SCK/MISO/MOSI : PA15/PC10/PC11/PC12 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD2 : PA5 + +System Clock +------------ + +Nucleo L476RG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L476RG board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l476rg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.2. + +Flashing an application to Nucleo L476RG +---------------------------------------- + +Connect the Nucleo L476RG to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l476rg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l476rg + :maybe-skip-config: + :goals: debug + +.. _Nucleo L476RG website: + https://www.st.com/en/evaluation-tools/nucleo-l476rg.html + +.. _STM32 Nucleo-64 board User Manual: + https://www.st.com/resource/en/user_manual/dm00105823.pdf + +.. _STM32L476RG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l476rg.html + +.. _STM32L476 reference manual: + https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg.dts b/boards/st/nucleo_l476rg/nucleo_l476rg.dts similarity index 100% rename from boards/arm/nucleo_l476rg/nucleo_l476rg.dts rename to boards/st/nucleo_l476rg/nucleo_l476rg.dts diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg.yaml b/boards/st/nucleo_l476rg/nucleo_l476rg.yaml similarity index 100% rename from boards/arm/nucleo_l476rg/nucleo_l476rg.yaml rename to boards/st/nucleo_l476rg/nucleo_l476rg.yaml diff --git a/boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig b/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig similarity index 85% rename from boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig rename to boards/st/nucleo_l476rg/nucleo_l476rg_defconfig index 0ba22d7b6c432f..76e7e50d1fac52 100644 --- a/boards/arm/nucleo_l476rg/nucleo_l476rg_defconfig +++ b/boards/st/nucleo_l476rg/nucleo_l476rg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L476XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l476rg/st_morpho_connector.dtsi b/boards/st/nucleo_l476rg/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l476rg/st_morpho_connector.dtsi rename to boards/st/nucleo_l476rg/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_l496zg/support/openocd.cfg b/boards/st/nucleo_l476rg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l496zg/support/openocd.cfg rename to boards/st/nucleo_l476rg/support/openocd.cfg diff --git a/boards/st/nucleo_l496zg/Kconfig.defconfig b/boards/st/nucleo_l496zg/Kconfig.defconfig new file mode 100644 index 00000000000000..f15b6d411eca88 --- /dev/null +++ b/boards/st/nucleo_l496zg/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L496ZG Nucleo board configuration + +# Copyright (c) 2018 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L496ZG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L496ZG diff --git a/boards/st/nucleo_l496zg/Kconfig.nucleo_l496zg b/boards/st/nucleo_l496zg/Kconfig.nucleo_l496zg new file mode 100644 index 00000000000000..79dc7f4b042d16 --- /dev/null +++ b/boards/st/nucleo_l496zg/Kconfig.nucleo_l496zg @@ -0,0 +1,5 @@ +# Copyright (c) 2018-2019 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L496ZG + select SOC_STM32L496XX diff --git a/boards/arm/nucleo_l496zg/arduino_r3_connector.dtsi b/boards/st/nucleo_l496zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l496zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_l496zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l496zg/board.cmake b/boards/st/nucleo_l496zg/board.cmake similarity index 100% rename from boards/arm/nucleo_l496zg/board.cmake rename to boards/st/nucleo_l496zg/board.cmake diff --git a/boards/st/nucleo_l496zg/board.yml b/boards/st/nucleo_l496zg/board.yml new file mode 100644 index 00000000000000..3d1c909cffc790 --- /dev/null +++ b/boards/st/nucleo_l496zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l496zg + vendor: st + socs: + - name: stm32l496xx diff --git a/boards/arm/nucleo_l496zg/doc/img/nucleo_l496zg.jpg b/boards/st/nucleo_l496zg/doc/img/nucleo_l496zg.jpg similarity index 100% rename from boards/arm/nucleo_l496zg/doc/img/nucleo_l496zg.jpg rename to boards/st/nucleo_l496zg/doc/img/nucleo_l496zg.jpg diff --git a/boards/st/nucleo_l496zg/doc/index.rst b/boards/st/nucleo_l496zg/doc/index.rst new file mode 100644 index 00000000000000..da208a4c8d931f --- /dev/null +++ b/boards/st/nucleo_l496zg/doc/index.rst @@ -0,0 +1,244 @@ +.. _nucleo_l496zg_board: + +ST Nucleo L496ZG +################ + +Overview +******** + +The Nucleo L496ZG board features an ARM Cortex-M4 based STM32L496ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L476ZG board: + + +- STM32 microcontroller in QFP144 package +- USB OTG FS with Micro-AB connector +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB + power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) +- 2 push buttons: USER and RESET + +.. image:: img/nucleo_l496zg.jpg + :align: center + :alt: Nucleo L496ZG + +More information about the board can be found at the `Nucleo L496ZG website`_. + +Hardware +******** + +The STM32L496ZG SoC provides the following hardware capabilities: + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 320 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (4x SPIs with the Quad SPI) + - 2x CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L496ZG can be found here: + +- `STM32L496ZG on www.st.com`_ +- `STM32L496 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l496zg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | System Window Watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l496zg/nucleo_l496zg_defconfig` + + +Connections and IOs +=================== + +Nucleo L496ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PD5/PD6 +- UART_3 TX/RX : PD8/PD9 +- LPUART_1 TX/RX : PG7/PG8 +- PWM_1_CH1: PE9 +- PWM_1_CH2: PE11 +- PWM_1_CH3: PE13 +- PWM_2_CH1: PA0 +- I2C_1_SCL: PB8 +- I2C_1_SDA: PB7 +- SPI_1_NSS: PD14 +- SPI_1_SCK: PA5 +- SPI_1_MISO: PA6 +- SPI_1_MOSI: PA7 +- USER_PB : PC13 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PB14 + +System Clock +------------ + +Nucleo L496ZG System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +Nucleo L496ZG board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l496zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the openocd version +included in the Zephyr SDK since v0.9.5. + +Flashing an application to Nucleo L496ZG +---------------------------------------- + +Connect the Nucleo L496ZG to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l496zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l496zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo L496ZG website: + https://www.st.com/en/evaluation-tools/nucleo-l496zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00368330.pdf + +.. _STM32L496ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l496zg.html + +.. _STM32L496 reference manual: + https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l496zg/nucleo_l496zg.dts b/boards/st/nucleo_l496zg/nucleo_l496zg.dts similarity index 100% rename from boards/arm/nucleo_l496zg/nucleo_l496zg.dts rename to boards/st/nucleo_l496zg/nucleo_l496zg.dts diff --git a/boards/arm/nucleo_l496zg/nucleo_l496zg.yaml b/boards/st/nucleo_l496zg/nucleo_l496zg.yaml similarity index 100% rename from boards/arm/nucleo_l496zg/nucleo_l496zg.yaml rename to boards/st/nucleo_l496zg/nucleo_l496zg.yaml diff --git a/boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig b/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig similarity index 85% rename from boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig rename to boards/st/nucleo_l496zg/nucleo_l496zg_defconfig index e195230eb20829..5ef11a3cb3ff67 100644 --- a/boards/arm/nucleo_l496zg/nucleo_l496zg_defconfig +++ b/boards/st/nucleo_l496zg/nucleo_l496zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L496XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l4a6zg/support/openocd.cfg b/boards/st/nucleo_l496zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l4a6zg/support/openocd.cfg rename to boards/st/nucleo_l496zg/support/openocd.cfg diff --git a/boards/st/nucleo_l4a6zg/Kconfig.defconfig b/boards/st/nucleo_l4a6zg/Kconfig.defconfig new file mode 100644 index 00000000000000..a7e0339c369b90 --- /dev/null +++ b/boards/st/nucleo_l4a6zg/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32L4A6ZG Nucleo board configuration + +# Copyright (c) 2022 Tomislav Milkovic +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L4A6ZG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_L4A6ZG diff --git a/boards/st/nucleo_l4a6zg/Kconfig.nucleo_l4a6zg b/boards/st/nucleo_l4a6zg/Kconfig.nucleo_l4a6zg new file mode 100644 index 00000000000000..fb33c9a9a23d16 --- /dev/null +++ b/boards/st/nucleo_l4a6zg/Kconfig.nucleo_l4a6zg @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Tomislav Milkovic +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L4A6ZG + select SOC_STM32L4A6XX diff --git a/boards/arm/nucleo_l4a6zg/arduino_r3_connector.dtsi b/boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l4a6zg/arduino_r3_connector.dtsi rename to boards/st/nucleo_l4a6zg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l4a6zg/board.cmake b/boards/st/nucleo_l4a6zg/board.cmake similarity index 100% rename from boards/arm/nucleo_l4a6zg/board.cmake rename to boards/st/nucleo_l4a6zg/board.cmake diff --git a/boards/st/nucleo_l4a6zg/board.yml b/boards/st/nucleo_l4a6zg/board.yml new file mode 100644 index 00000000000000..6e935c5d0826ae --- /dev/null +++ b/boards/st/nucleo_l4a6zg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l4a6zg + vendor: st + socs: + - name: stm32l4a6xx diff --git a/boards/st/nucleo_l4a6zg/doc/index.rst b/boards/st/nucleo_l4a6zg/doc/index.rst new file mode 100644 index 00000000000000..30cac697ddee3d --- /dev/null +++ b/boards/st/nucleo_l4a6zg/doc/index.rst @@ -0,0 +1,243 @@ +.. _nucleo_l4a6zg_board: + +ST Nucleo L4A6ZG +################ + +Overview +******** + +The Nucleo L4A6ZG board features an ARM Cortex-M4 based STM32L4A6ZG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L4A6ZG board: + + +- STM32 microcontroller in QFP144 package +- USB OTG FS with Micro-AB connector +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- 8 LEDs: user LEDs (LD1, LD2, LD3), communication LED (LD4), USB + power fault(LD5), power LED (LD6), USB FS OTG (LD7, LD8) +- 2 push buttons: USER and RESET + +.. image:: ../../nucleo_l496zg/doc/img/nucleo_l496zg.jpg + :align: center + :alt: Nucleo L4A6ZG + +More information about the board can be found at the `Nucleo L4A6ZG website`_. + +Hardware +******** + +The STM32L4A6ZG SoC provides the following hardware capabilities: + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 320 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5x U(S)ARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (4x SPIs with the Quad SPI) + - 2x CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- AES and HASH hardware accelerators +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L4A6ZG can be found here: + +- `STM32L4A6ZG on www.st.com`_ +- `STM32L4A6 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l4a6zg board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | System Window Watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig` + + +Connections and IOs +=================== + +Nucleo L4A6ZG Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- LPUART_1 TX/RX : PG7/PG8 (ST-Link Virtual COM Port) +- UART_3 TX/RX : PD8/PD9 (Arduino Serial) +- I2C_1 SCL/SDA : PB8/PB7 (Arduino I2C) +- SPI_1 SCK/MISO/MOSI/NSS : PA5/PA6/PA7/PD14 (Arduino SPI) +- USER_PB : PC13 +- PWM_15_CH1 : PB14 (Red LED) +- LD1 : PC7 (Green LED) +- LD2 : PB7 (Blue LED) +- LD3 : PB14 (Red LED) + +System Clock +------------ + +Nucleo L4A6ZG system clock could be driven by internal or external oscillator, +as well as main PLL clock. By default, system clock is driven by PLL at 80MHz, which is +driven by 16MHz high speed internal oscillator (HSI). High speed external oscillator +(HSE) is not soldered on the board, so it cannot be used to drive the PLL. + +Serial Port +----------- + +Nucleo L4A6ZG board has 5 UARTs. The Zephyr console output is assigned to LPUART1, +which is connected to the onboard ST-LINK/V2-1. Virtual COM port interface. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``nucleo_l4a6zg`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Nucleo L4A6ZG board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is supported by the OpenOCD version +included in the Zephyr SDK since v0.9.5. + +Flashing an application to Nucleo L4A6ZG +---------------------------------------- + +Connect the Nucleo L4A6ZG to your host computer using the ST-LINK USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l4a6zg + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! nucleo_l4a6zg + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l4a6zg + :maybe-skip-config: + :goals: debug + +.. _Nucleo L4A6ZG website: + https://www.st.com/en/evaluation-tools/nucleo-l4a6zg.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00368330.pdf + +.. _STM32L4A6ZG on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l4a6zg.html + +.. _STM32L4A6 reference manual: + https://www.st.com/resource/en/reference_manual/dm00083560.pdf diff --git a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.dts b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts similarity index 100% rename from boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.dts rename to boards/st/nucleo_l4a6zg/nucleo_l4a6zg.dts diff --git a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.yaml b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml similarity index 100% rename from boards/arm/nucleo_l4a6zg/nucleo_l4a6zg.yaml rename to boards/st/nucleo_l4a6zg/nucleo_l4a6zg.yaml diff --git a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig similarity index 85% rename from boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig rename to boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig index a2e8b6eb212c5b..5ef11a3cb3ff67 100644 --- a/boards/arm/nucleo_l4a6zg/nucleo_l4a6zg_defconfig +++ b/boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4A6XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l4r5zi/support/openocd.cfg b/boards/st/nucleo_l4a6zg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l4r5zi/support/openocd.cfg rename to boards/st/nucleo_l4a6zg/support/openocd.cfg diff --git a/boards/st/nucleo_l4r5zi/Kconfig.defconfig b/boards/st/nucleo_l4r5zi/Kconfig.defconfig new file mode 100644 index 00000000000000..31b375e87d2d9e --- /dev/null +++ b/boards/st/nucleo_l4r5zi/Kconfig.defconfig @@ -0,0 +1,22 @@ +# STM32L4R5ZI Nucleo board configuration + +# Copyright (c) 2018 Pushpal Sidhu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_L4R5ZI + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if NETWORKING + +config USB_DEVICE_STACK + default y + +config USB_DEVICE_NETWORK_EEM + default y + +endif # NETWORKING + +endif # BOARD_NUCLEO_L4R5ZI diff --git a/boards/st/nucleo_l4r5zi/Kconfig.nucleo_l4r5zi b/boards/st/nucleo_l4r5zi/Kconfig.nucleo_l4r5zi new file mode 100644 index 00000000000000..06fe55dc6b5bb6 --- /dev/null +++ b/boards/st/nucleo_l4r5zi/Kconfig.nucleo_l4r5zi @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Pushpal Sidhu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L4R5ZI + select SOC_STM32L4R5XX diff --git a/boards/arm/nucleo_l4r5zi/arduino_r3_connector.dtsi b/boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l4r5zi/arduino_r3_connector.dtsi rename to boards/st/nucleo_l4r5zi/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l4r5zi/board.cmake b/boards/st/nucleo_l4r5zi/board.cmake similarity index 100% rename from boards/arm/nucleo_l4r5zi/board.cmake rename to boards/st/nucleo_l4r5zi/board.cmake diff --git a/boards/st/nucleo_l4r5zi/board.yml b/boards/st/nucleo_l4r5zi/board.yml new file mode 100644 index 00000000000000..46ead4d88316c3 --- /dev/null +++ b/boards/st/nucleo_l4r5zi/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_l4r5zi + vendor: st + socs: + - name: stm32l4r5xx diff --git a/boards/arm/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg b/boards/st/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg similarity index 100% rename from boards/arm/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg rename to boards/st/nucleo_l4r5zi/doc/img/nucleo144_layout.jpg diff --git a/boards/arm/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg b/boards/st/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg similarity index 100% rename from boards/arm/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg rename to boards/st/nucleo_l4r5zi/doc/img/nucleo_l4r5zi.jpg diff --git a/boards/st/nucleo_l4r5zi/doc/index.rst b/boards/st/nucleo_l4r5zi/doc/index.rst new file mode 100644 index 00000000000000..f449c985a83600 --- /dev/null +++ b/boards/st/nucleo_l4r5zi/doc/index.rst @@ -0,0 +1,275 @@ +.. _nucleo_l4r5zi_board: + +ST Nucleo L4R5ZI +################ + +Overview +******** + +The Nucleo L4R5ZI board features an ARM Cortex-M4 based STM32L4R5ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the Nucleo L4R5ZI board: + + +- STM32 microcontroller in LQFP144 package +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Three User LEDs: LD1 (Green), LD2 (Blue), LD3 (Red) +- Two push-buttons: USER and RESET + +.. image:: img/nucleo_l4r5zi.jpg + :align: center + :alt: Nucleo L4R5ZI + +More information about the board can be found at the `Nucleo L4R5ZI website`_. + +Hardware +******** + +The STM32L4R5ZI SoC provides the following hardware IPs: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode + and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, adaptive + real-time accelerator (ART Accelerator) allowing 0-wait-state + execution from Flash memory, frequency up to 120 MHz, MPU, 150 + DMIPS/1.25 DMIPS/MHz (Dhrystone 2.1), and DSP instructions +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - Internal 48 MHz with clock recovery + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- Up to 24 capacitive sensing channels: support touchkey, linear and + rotary touch sensors +- Advanced graphics features + + - Chrom-ART Accelerator™ (DMA2D) for enhanced graphic content creation + - Chrom-GRC™ (GFXMMU) allowing up to 20% of graphic resources optimization + - MIPI® DSI Host controller with two DSI lanes running at up to 500 + Mbits/s each + - LCD-TFT controller + +- 16x timers + + - 2 x 16-bit advanced motor-control + - 2 x 32-bit and 5 x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with + independent supply down to 1.08 V +- Memories + + - 2-Mbyte Flash, 2 banks read-while-write, proprietary code readout protection + - 640 Kbytes of SRAM including 64 Kbytes with hardware parity check + - External memory interface for static memories supporting SRAM, + PSRAM, NOR, NAND and FRAM memories + - 2 x OctoSPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 12-bit ADC 5 Msps, up to 16-bit with hardware oversampling, 200 μA/Msps + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with the dual OctoSPI) + - CAN (2.0B Active) and SDMMC + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- 8- to 14-bit camera interface up to 32 MHz (black and white) or 10 MHz (color) +- Development support: serial wire debug (SWD), JTAG, Embedded Trace + Macrocell (ETM) + +More information about STM32L4R5ZI can be found here: + +- `STM32L4R5ZI on www.st.com`_ +- `STM32L4R5 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_l4r5zi board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig` + + +Connections and IOs +=================== + +Nucleo L4R5ZI Board has 8 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +Available pins: +--------------- +.. image:: img/nucleo144_layout.jpg + :align: center + :alt: Nucleo L4R5ZI Arduino connectors + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- UART_3_TX : PB10 +- UART_3_RX : PB11 +- I2C_1_SCL : PB6 +- I2C_1_SDA : PB7 +- SPI_1_NSS : PD14 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- SPI_2_NSS : PB12 +- SPI_2_SCK : PB13 +- SPI_2_MISO : PB14 +- SPI_2_MOSI : PB15 +- SPI_3_NSS : PB12 +- SPI_3_SCK : PC10 +- SPI_3_MISO : PC11 +- SPI_3_MOSI : PC12 +- PWM_2_CH1 : PA0 +- USER_PB : PC13 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PB14 +- USB DM : PA11 +- USB DP : PA12 +- ADC1 : PC0 + +System Clock +------------ + +Nucleo L4R5ZI System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default, the System clock is +driven by the PLL clock at 80MHz, driven by a 16MHz high speed +internal oscillator. The clock can be boosted to 120MHz if boost mode +is selected. + +Serial Port +----------- + +Nucleo L4R5ZI board has 5 U(S)ARTs. The Zephyr console output is +assigned to UART2. Default settings are 115200 8N1. + +Network interface +----------------- + +Ethernet over USB is configured as the default network interface (EEM) + +Programming and Debugging +************************* + +The NUCLEO-L4R5ZI board includes a ST-LINK/V2 embedded debug tool interface. + +The board is configured to be flashed using west `STM32CubeProgrammer`_ runner, +so its installation is required to be able to flash the board. + +Alternatively, openocd (provided in Zephyr SDK) or JLink can also be used to +flash the board using the ``--runner`` (or ``-r``) option: + +.. code-block:: console + + $ west flash --runner openocd + $ west flash --runner jlink + +Connect the Nucleo L4R5ZI to your host computer using the USB port. +Then build and flash an application. + +Here is an example for the :ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_l4r5zi + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +.. _Nucleo L4R5ZI website: + https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00368330.pdf + +.. _STM32L4R5ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32l4r5zi.html + +.. _STM32L4R5 reference manual: + https://www.st.com/resource/en/reference_manual/DM00310109.pdf + +.. _STM32 ST-LINK utility: + https://www.st.com/content/st_com/en/products/development-tools/software-development-tools/stm32-software-development-tools/stm32-programmers/stsw-link004.html + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts similarity index 100% rename from boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.dts rename to boards/st/nucleo_l4r5zi/nucleo_l4r5zi.dts diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.yaml b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml similarity index 100% rename from boards/arm/nucleo_l4r5zi/nucleo_l4r5zi.yaml rename to boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml diff --git a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig similarity index 85% rename from boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig rename to boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig index 0efb42f55a9f67..4ba8077edd667c 100644 --- a/boards/arm/nucleo_l4r5zi/nucleo_l4r5zi_defconfig +++ b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/sensortile_box/support/openocd.cfg b/boards/st/nucleo_l4r5zi/support/openocd.cfg similarity index 100% rename from boards/arm/sensortile_box/support/openocd.cfg rename to boards/st/nucleo_l4r5zi/support/openocd.cfg diff --git a/boards/arm/nucleo_l552ze_q/CMakeLists.txt b/boards/st/nucleo_l552ze_q/CMakeLists.txt similarity index 100% rename from boards/arm/nucleo_l552ze_q/CMakeLists.txt rename to boards/st/nucleo_l552ze_q/CMakeLists.txt diff --git a/boards/st/nucleo_l552ze_q/Kconfig.nucleo_l552ze_q b/boards/st/nucleo_l552ze_q/Kconfig.nucleo_l552ze_q new file mode 100644 index 00000000000000..22104ed027dee1 --- /dev/null +++ b/boards/st/nucleo_l552ze_q/Kconfig.nucleo_l552ze_q @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_L552ZE_Q + select SOC_STM32L552XX diff --git a/boards/arm/nucleo_l552ze_q/arduino_r3_connector.dtsi b/boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_l552ze_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_l552ze_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_l552ze_q/board.cmake b/boards/st/nucleo_l552ze_q/board.cmake similarity index 100% rename from boards/arm/nucleo_l552ze_q/board.cmake rename to boards/st/nucleo_l552ze_q/board.cmake diff --git a/boards/st/nucleo_l552ze_q/board.yml b/boards/st/nucleo_l552ze_q/board.yml new file mode 100644 index 00000000000000..713b695aeba0bb --- /dev/null +++ b/boards/st/nucleo_l552ze_q/board.yml @@ -0,0 +1,7 @@ +board: + name: nucleo_l552ze_q + vendor: st + socs: + - name: stm32l552xx + variants: + - name: ns diff --git a/boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg b/boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg similarity index 100% rename from boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg rename to boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q.jpg diff --git a/boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg b/boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg similarity index 100% rename from boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg rename to boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_left_2020_2_11.jpg diff --git a/boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg b/boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg similarity index 100% rename from boards/arm/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg rename to boards/st/nucleo_l552ze_q/doc/img/nucleo_l552ze_q_zio_right_2020_2_11.jpg diff --git a/boards/arm/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst similarity index 91% rename from boards/arm/nucleo_l552ze_q/doc/nucleol552ze_q.rst rename to boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst index 65a2df527a9caa..d4b8f5996734dd 100644 --- a/boards/arm/nucleo_l552ze_q/doc/nucleol552ze_q.rst +++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst @@ -168,17 +168,17 @@ The default configuration can be found in the defconfig and dts files: - Common: - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi` - Secure target: - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig` - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.dts` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts` - Non-Secure target: - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns_defconfig` - - :zephyr_file:`boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.dts` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig` + - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts` Zephyr board options ==================== @@ -188,20 +188,20 @@ for building for both Secure and Non-Secure firmware. The BOARD options are summarized below: -+----------------------+-----------------------------------------------+ -| BOARD | Description | -+======================+===============================================+ -| nucleo_l552ze_q | For building Secure (or Secure-only) firmware | -+----------------------+-----------------------------------------------+ -| nucleo_l552ze_q_ns | For building Non-Secure firmware | -+----------------------+-----------------------------------------------+ ++--------------------------------+-------------------------------------------+ +| BOARD | Description | ++================================+===========================================+ +| nucleo_l552ze_q | For building Trust Zone Disabled firmware | ++--------------------------------+-------------------------------------------+ +| nucleo_l552ze_q/stm32l552xx/ns | For building Non-Secure firmware | ++--------------------------------+-------------------------------------------+ Here are the instructions to build Zephyr with a non-secure configuration, using `tfm_ipc_` sample: .. code-block:: bash - $ west build -b nucleo_l552ze_q_ns samples/tfm_integration/tfm_ipc/ + $ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/ Once done, before flashing, you need to first run a generated script that will set platform option bytes config and erase platform (among others, @@ -332,11 +332,11 @@ Building a secure/non-secure with Arm |reg| TrustZone |reg| The TF-M integration sample :ref:`tfm_ipc` can be run on a ST Nucleo L552ZE Q. In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image -can be generated using ``nucleo_l552ze_q_ns`` as build target. +can be generated using ``nucleo_l552ze_q/stm32l552xx/ns`` as build target. .. code-block:: bash - $ west build -b nucleo_l552ze_q_ns path/to/source/directory + $ west build -b nucleo_l552ze_q/stm32l552xx/ns path/to/source/directory Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script is run automatically in a post-build step to make some required flash layout changes. diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.dts b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.dts rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.yaml b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q.yaml similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q.yaml rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q.yaml diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig similarity index 85% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig index aa132c44b32af3..08e076454708fc 100644 --- a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_defconfig +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L552XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.dts b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts similarity index 100% rename from boards/arm/nucleo_l552ze_q/nucleo_l552ze_q_ns.dts rename to boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts diff --git a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.yaml b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.yaml new file mode 100644 index 00000000000000..186f873ff83e35 --- /dev/null +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.yaml @@ -0,0 +1,13 @@ +identifier: nucleo_l552ze_q/stm32l552xx/ns +name: ST Nucleo L552ZE Q non secure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - gpio + - dac +ram: 192 +flash: 328 +vendor: st diff --git a/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig new file mode 100644 index 00000000000000..540ddddfc4e574 --- /dev/null +++ b/boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable clock +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/nucleo_l552ze_q/support/openocd.cfg b/boards/st/nucleo_l552ze_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_l552ze_q/support/openocd.cfg rename to boards/st/nucleo_l552ze_q/support/openocd.cfg diff --git a/boards/arm/nucleo_u575zi_q/CMakeLists.txt b/boards/st/nucleo_u575zi_q/CMakeLists.txt similarity index 100% rename from boards/arm/nucleo_u575zi_q/CMakeLists.txt rename to boards/st/nucleo_u575zi_q/CMakeLists.txt diff --git a/boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q b/boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q new file mode 100644 index 00000000000000..0093ddbe95d030 --- /dev/null +++ b/boards/st/nucleo_u575zi_q/Kconfig.nucleo_u575zi_q @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_U575ZI_Q + select SOC_STM32U575XX diff --git a/boards/arm/nucleo_u575zi_q/arduino_r3_connector.dtsi b/boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_u575zi_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_u575zi_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_u575zi_q/board.cmake b/boards/st/nucleo_u575zi_q/board.cmake similarity index 100% rename from boards/arm/nucleo_u575zi_q/board.cmake rename to boards/st/nucleo_u575zi_q/board.cmake diff --git a/boards/st/nucleo_u575zi_q/board.yml b/boards/st/nucleo_u575zi_q/board.yml new file mode 100644 index 00000000000000..ced9ac720b3247 --- /dev/null +++ b/boards/st/nucleo_u575zi_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_u575zi_q + vendor: st + socs: + - name: stm32u575xx diff --git a/boards/st/nucleo_u575zi_q/doc/index.rst b/boards/st/nucleo_u575zi_q/doc/index.rst new file mode 100644 index 00000000000000..9a7222cb18a3ce --- /dev/null +++ b/boards/st/nucleo_u575zi_q/doc/index.rst @@ -0,0 +1,343 @@ +.. _nucleo_u575zi_q_board: + +ST Nucleo U575ZI Q +################## + +Overview +******** + +The Nucleo U575ZI Q board, featuring an ARM Cortex-M33 based STM32U575ZI MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the Nucleo U575ZI Q +board: + + +- STM32U575ZI microcontroller in LQFP144 package +- Internal SMPS to generate V core logic supply +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V3E debugger/programmer +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - ST-Link V3E + +- Three users LEDs +- Two push-buttons: USER and RESET +- USB Type-C |trade| Sink device FS + +Hardware +******** + +The STM32U575xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure Firmware Update support with TF-M + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 2 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- True Random Number Generator (RNG) + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + +More information about STM32U575ZI can be found here: + +- `STM32U575ZI on www.st.com`_ +- `STM32U575 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_u575zi_q board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CAN/CANFD | on-chip | canbus | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig` + + +Connections and IOs +=================== + +Nucleo U575ZI Q Board has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + + +- CAN/CANFD_TX: PD1 +- CAN/CANFD_RX: PD0 +- DAC1_OUT1 : PA4 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- I2C_2_SCL : PF1 +- I2C_2_SDA : PF0 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PG2 +- LPUART_1_TX : PG7 +- LPUART_1_RX : PG8 +- SPI_1_NSS : PA4 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PC13 + +System Clock +------------ + +Nucleo U575ZI Q System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +160MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +Nucleo U575ZI Q board has 6 U(S)ARTs. The Zephyr console output is assigned to +USART1. Default settings are 115200 8N1. + + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB50`` jumper on the back side of the board. + + +Programming and Debugging +************************* + +Nucleo U575ZI-Q board includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be +used to flash and debug the board if west is told to use it as runner, +which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. + +For pyocd additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32u5 + + +Flashing an application to Nucleo U575ZI Q +------------------------------------------ + +Connect the Nucleo U575ZI Q to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_u575zi_q + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u575zi_q + :goals: debug + +Building a secure/non-secure with Arm |reg| TrustZone |reg| +=========================================================== + +The TF-M applications can be run on this board, thanks to its Arm |reg| TrustZone |reg| +support. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``nucleo_u575zi_q_ns`` as build target. + +.. code-block:: bash + + $ west build -b nucleo_u575zi_q_ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/dm00615305.pdf + +.. _STM32U575ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32u575zi.html + +.. _STM32U575 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi similarity index 100% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q-common.dtsi diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts similarity index 100% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.dts rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q.dts diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.yaml b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q.yaml similarity index 100% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q.yaml rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q.yaml diff --git a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig similarity index 85% rename from boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig rename to boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig index 23eebae7ef0793..08e076454708fc 100644 --- a/boards/arm/nucleo_u575zi_q/nucleo_u575zi_q_defconfig +++ b/boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U575XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_u575zi_q/support/openocd.cfg b/boards/st/nucleo_u575zi_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_u575zi_q/support/openocd.cfg rename to boards/st/nucleo_u575zi_q/support/openocd.cfg diff --git a/boards/arm/nucleo_u5a5zj_q/CMakeLists.txt b/boards/st/nucleo_u5a5zj_q/CMakeLists.txt similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/CMakeLists.txt rename to boards/st/nucleo_u5a5zj_q/CMakeLists.txt diff --git a/boards/st/nucleo_u5a5zj_q/Kconfig.nucleo_u5a5zj_q b/boards/st/nucleo_u5a5zj_q/Kconfig.nucleo_u5a5zj_q new file mode 100644 index 00000000000000..58256af223f383 --- /dev/null +++ b/boards/st/nucleo_u5a5zj_q/Kconfig.nucleo_u5a5zj_q @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_U5A5ZJ_Q + select SOC_STM32U5A5XX diff --git a/boards/arm/nucleo_u5a5zj_q/arduino_r3_connector.dtsi b/boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/arduino_r3_connector.dtsi rename to boards/st/nucleo_u5a5zj_q/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_u5a5zj_q/board.cmake b/boards/st/nucleo_u5a5zj_q/board.cmake similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/board.cmake rename to boards/st/nucleo_u5a5zj_q/board.cmake diff --git a/boards/st/nucleo_u5a5zj_q/board.yml b/boards/st/nucleo_u5a5zj_q/board.yml new file mode 100644 index 00000000000000..9e594c30fb1376 --- /dev/null +++ b/boards/st/nucleo_u5a5zj_q/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_u5a5zj_q + vendor: st + socs: + - name: stm32u5a5xx diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst new file mode 100644 index 00000000000000..9b76919db33f71 --- /dev/null +++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst @@ -0,0 +1,377 @@ +.. _nucleo_u5a5zj_q_board: + +ST Nucleo U5A5ZJ Q +################## + +Overview +******** + +The Nucleo U5A5ZJ Q board, featuring an ARM Cortex-M33 based STM32U5A5ZJ MCU, +provides an affordable and flexible way for users to try out new concepts and +build prototypes by choosing from the various combinations of performance and +power consumption features. Here are some highlights of the Nucleo U5A5ZJ Q +board: + + +- STM32U5A5ZJ microcontroller in LQFP144 package +- Internal SMPS to generate V core logic supply +- Two types of extension resources: + + - Arduino Uno V3 connectivity + - ST morpho extension pin headers for full access to all STM32 I/Os + +- On-board ST-LINK/V3E debugger/programmer +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - ST-Link V3E + +- Three users LEDs +- Two push-buttons: USER and RESET +- USB Type-C ™ Sink device FS + +Hardware +******** + +The STM32U5A5xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm® Cortex®-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Includes ST state-of-the-art patented technology +- Ultra-low-power with FlexPowerControl: + + - 1.71 V to 3.6 V power supply + - -40 °C to +85/125 °C temperature range + - Low-power background autonomous mode (LPBAM): autonomous peripherals with + DMA, functional down to Stop 2 mode + - VBAT mode: supply for RTC, 32 x 32-bit backup registers and 2-Kbyte backup SRAM + - 150 nA Shutdown mode (24 wake-up pins) + - 195 nA Standby mode (24 wake-up pins) + - 480 nA Standby mode with RTC + - 2 µA Stop 3 mode with 40-Kbyte SRAM + - 8.2 µA Stop 3 mode with 2.5-Mbyte SRAM + - 4.65 µA Stop 2 mode with 40-Kbyte SRAM + - 17.5 µA Stop 2 mode with 2.5-Mbyte SRAM + - 18.5 µA/MHz Run mode at 3.3 V + +- Core: + + - Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, + and FPU ART Accelerator + - 32-Kbyte ICACHE allowing 0-wait-state execution from flash and external + memories: frequency up to 160 MHz, 240 DMIPS + - 16-Kbyte DCACHE1 for external memories + +- Power management: + + - Embedded regulator (LDO) and SMPSstep-down converter supporting switch + on-the-fly and voltage scaling + +- Benchmarks: + + - 1.5 DMIPS/MHz (Drystone 2.1) + - 655 CoreMark® (4.09 CoreMark®/MHz) + - 369 ULPMark™-CP + - 89 ULPMark™-PP + - 47.2 ULPMark™-CM + - 120000 SecureMark™-TLS + +- Memories: + + - 4-Mbyte flash memory with ECC, 2 banks readwhile-write, including 512 Kbytes + with 100 kcycles + - With SRAM3 ECC off: 2514-Kbyte RAM including 66 Kbytes with ECC + - With SRAM3 ECC on: 2450-Kbyte RAMincluding 322 Kbytes with ECC + - External memory interface supporting SRAM,PSRAM, NOR, NAND, and FRAM memories + - 2 Octo-SPI memory interfaces + - 16-bit HSPI memory interface up to 160 MHz + +- Rich graphic features: + + - Neo-Chrom GPU (GPU2D) accelerating any angle rotation, scaling, and + perspective correct texture mapping + - 16-Kbyte DCACHE2 + - Chrom-ART Accelerator (DMA2D) for smoothmotion and transparency effects + - Chrom-GRC (GFXMMU) allowing up to 20 % of graphic resources optimization + - MIPI® DSI host controller with two DSI lanes running at up to 500 Mbit/s each + - LCD-TFT controller (LTDC) + - Digital camera interface + +- General-purpose input/outputs: + + - Up to 156 fast I/Os with interrupt capability most 5V-tolerant and + up to 14 I/Os with independent supply down to 1.08 V + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC (± 1 %) + - Internal low-power 32 kHz RC (± 5 %) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one + autotrimmed by LSE (better than ± 0.25 % accuracy) + - Internal 48 MHz + - 5 PLLs for system clock, USB, audio, ADC, DSI + +- Security and cryptography: + + - SESIP3 and PSA Level 3 Certified Assurance Target + - Arm® TrustZone® and securable I/Os, memories, and peripherals + - Flexible life cycle scheme with RDP andpassword-protected debug + - Root of trust thanks to unique boot entry and secure hide-protection area (HDP) + - Secure firmware installation (SFI) thanks to embedded root secure services (RSS) + - Secure data storage with hardware unique key (HUK) + - Secure firmware upgrade support with TF-M + - 2 AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte OTP (one-time programmable) + - Active tampers + +- Up to 17 timers, 2 watchdogs and RTC: + + - 19 timers: 2 16-bit advanced motor-control, 4 32-bit, 3 16-bit general + purpose, 2 16-bit basic, 4 low-power 16-bit (available in Stop mode), + 2 SysTick timers, and 2 watchdogs + - RTC with hardware calendar, alarms, and calibration + +- Up to 25 communication peripherals: + + - 1 USB Type-C®/USB power delivery controller + - 1 USB OTG high-speed with embedded PHY + - 2 SAIs (serial audio interface) + - 6 I2C FM+(1 Mbit/s), SMBus/PMBus™ + - 7 USARTs (ISO 7816, LIN, IrDA, modem) + - 3 SPIs (6x SPIs with OCTOSPI/HSPI) + - 1 CAN FD controller + - 2 SDMMC interfaces + - 1 multifunction digital filter (6 filters) + 1 audio digital filter + with sound-activity detection + - Parallel synchronous slave interface + +- Mathematical coprocessor: + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + +- Rich analog peripherals (independent supply): + + - 2 14-bit ADC 2.5-Msps with hardware oversampling + - 1 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 12-bit DAC (2 channels), low-power sample, and hold, autonomous in Stop 2 mode + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- ECOPACK2 compliant packages + +More information about STM32U5A5ZJ can be found here: + +- `STM32U5A5ZJ on www.st.com`_ +- `STM32U5A5 reference manual`_ + +Supported Features +================== + +The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CAN/CANFD | on-chip | canbus | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| BKP SRAM | on-chip | Backup SRAM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig` + + +Connections and IOs +=================== + +Nucleo U5A5ZJ Q Board has 10 GPIO controllers. These controllers are responsible +for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32 Nucleo-144 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + + +- CAN/CANFD_TX: PD1 +- CAN/CANFD_RX: PD0 +- DAC1_OUT1 : PA4 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- I2C_2_SCL : PF1 +- I2C_2_SDA : PF0 +- LD1 : PC7 +- LD2 : PB7 +- LD3 : PG2 +- LPUART_1_TX : PG7 +- LPUART_1_RX : PG8 +- SPI_1_NSS : PA4 +- SPI_1_SCK : PA5 +- SPI_1_MISO : PA6 +- SPI_1_MOSI : PA7 +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PC13 + +System Clock +------------ + +Nucleo U5A5ZJ Q System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +160MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +Nucleo U5A5ZJ Q board has 6 U(S)ARTs. The Zephyr console output is assigned to +USART1. Default settings are 115200 8N1. + + +Backup SRAM +----------- + +In order to test backup SRAM you may want to disconnect VBAT from VDD. You can +do it by removing ``SB50`` jumper on the back side of the board. + + +Programming and Debugging +************************* + +Nucleo U5A5ZJ-Q board includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash the board using various tools. + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board. + +Alternatively, openocd (provided in Zephyr SDK), JLink and pyocd can also be +used to flash and debug the board if west is told to use it as runner, +which can be done by passing either ``-r openocd``, ``-r jlink`` or ``-r pyocd``. + +For pyocd additional target information needs to be installed. +This can be done by executing the following commands. + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32u5 + + +Flashing an application to Nucleo U5A5ZJ Q +------------------------------------------ + +Connect the Nucleo U5A5ZJ Q to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nucleo_u5a5zj_q + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +Default flasher for this board is openocd. It could be used in the usual way. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: nucleo_u5a5zj_q + :goals: debug + +Building a secure/non-secure with Arm ® TrustZone ® +=========================================================== + +The TF-M applications can be run on this board, thanks to its Arm ® TrustZone ® +support. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``nucleo_u5a5zj_q_ns`` as build target. + +.. code-block:: bash + + $ west build -b nucleo_u5a5zj_q_ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +.. _STM32 Nucleo-144 board User Manual: + https://www.st.com/resource/en/user_manual/um2861-stm32u5-nucleo144-board-mb1549-stmicroelectronics.pdf + +.. _STM32U5A5ZJ on www.st.com: + https://www.st.com/en/microcontrollers/stm32u5a5zj.html + +.. _STM32U5A5 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STMicroelectronics customized version of OpenOCD: + https://github.com/STMicroelectronics/OpenOCD diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q-common.dtsi diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.dts diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q.yaml diff --git a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig similarity index 85% rename from boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig rename to boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig index 3134af0b6a7573..08e076454708fc 100644 --- a/boards/arm/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig +++ b/boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U5A5XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_u5a5zj_q/support/openocd.cfg b/boards/st/nucleo_u5a5zj_q/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_u5a5zj_q/support/openocd.cfg rename to boards/st/nucleo_u5a5zj_q/support/openocd.cfg diff --git a/boards/st/nucleo_wb55rg/Kconfig.defconfig b/boards/st/nucleo_wb55rg/Kconfig.defconfig new file mode 100644 index 00000000000000..a4822901739803 --- /dev/null +++ b/boards/st/nucleo_wb55rg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WB55RG Nucleo board configuration + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_WB55RG + +choice BT_HCI_BUS_TYPE + default BT_STM32_IPM + depends on BT +endchoice + +endif diff --git a/boards/st/nucleo_wb55rg/Kconfig.nucleo_wb55rg b/boards/st/nucleo_wb55rg/Kconfig.nucleo_wb55rg new file mode 100644 index 00000000000000..8ed5f79787275f --- /dev/null +++ b/boards/st/nucleo_wb55rg/Kconfig.nucleo_wb55rg @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WB55RG + select SOC_STM32WB55XX diff --git a/boards/arm/nucleo_wb55rg/arduino_r3_connector.dtsi b/boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wb55rg/arduino_r3_connector.dtsi rename to boards/st/nucleo_wb55rg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wb55rg/board.cmake b/boards/st/nucleo_wb55rg/board.cmake similarity index 100% rename from boards/arm/nucleo_wb55rg/board.cmake rename to boards/st/nucleo_wb55rg/board.cmake diff --git a/boards/st/nucleo_wb55rg/board.yml b/boards/st/nucleo_wb55rg/board.yml new file mode 100644 index 00000000000000..49366ba9e62bb9 --- /dev/null +++ b/boards/st/nucleo_wb55rg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wb55rg + vendor: st + socs: + - name: stm32wb55xx diff --git a/boards/arm/nucleo_wb55rg/doc/img/nucleowb55rg.jpg b/boards/st/nucleo_wb55rg/doc/img/nucleowb55rg.jpg similarity index 100% rename from boards/arm/nucleo_wb55rg/doc/img/nucleowb55rg.jpg rename to boards/st/nucleo_wb55rg/doc/img/nucleowb55rg.jpg diff --git a/boards/arm/nucleo_wb55rg/doc/nucleo_wb55rg.rst b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst similarity index 99% rename from boards/arm/nucleo_wb55rg/doc/nucleo_wb55rg.rst rename to boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst index 835b99f227f7db..04bdc9d45ec719 100644 --- a/boards/arm/nucleo_wb55rg/doc/nucleo_wb55rg.rst +++ b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst @@ -177,7 +177,7 @@ The Zephyr nucleo_wb55rg board configuration supports the following hardware fea Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig`` +:zephyr_file:`boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig` Bluetooth and compatibility with STM32WB Copro Wireless Binaries ================================================================ diff --git a/boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts b/boards/st/nucleo_wb55rg/nucleo_wb55rg.dts similarity index 100% rename from boards/arm/nucleo_wb55rg/nucleo_wb55rg.dts rename to boards/st/nucleo_wb55rg/nucleo_wb55rg.dts diff --git a/boards/arm/nucleo_wb55rg/nucleo_wb55rg.yaml b/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml similarity index 100% rename from boards/arm/nucleo_wb55rg/nucleo_wb55rg.yaml rename to boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml diff --git a/boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig b/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig similarity index 83% rename from boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig rename to boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig index 9fdd732848efc4..75373aa997cfc4 100644 --- a/boards/arm/nucleo_wb55rg/nucleo_wb55rg_defconfig +++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WBX=y -CONFIG_SOC_STM32WB55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wb55rg/support/openocd.cfg b/boards/st/nucleo_wb55rg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wb55rg/support/openocd.cfg rename to boards/st/nucleo_wb55rg/support/openocd.cfg diff --git a/boards/st/nucleo_wba52cg/Kconfig.defconfig b/boards/st/nucleo_wba52cg/Kconfig.defconfig new file mode 100644 index 00000000000000..6bf6d3f610f0d5 --- /dev/null +++ b/boards/st/nucleo_wba52cg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WBA52CG Nucleo board configuration + +# Copyright (c) 2023 STMicroelectronics + +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_WBA52CG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_WBA52CG diff --git a/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg b/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg new file mode 100644 index 00000000000000..515685e5715ab1 --- /dev/null +++ b/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WBA52CG + select SOC_STM32WBA52XX diff --git a/boards/arm/nucleo_wba52cg/arduino_r3_connector.dtsi b/boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wba52cg/arduino_r3_connector.dtsi rename to boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wba52cg/board.cmake b/boards/st/nucleo_wba52cg/board.cmake similarity index 100% rename from boards/arm/nucleo_wba52cg/board.cmake rename to boards/st/nucleo_wba52cg/board.cmake diff --git a/boards/st/nucleo_wba52cg/board.yml b/boards/st/nucleo_wba52cg/board.yml new file mode 100644 index 00000000000000..70950acf34db82 --- /dev/null +++ b/boards/st/nucleo_wba52cg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wba52cg + vendor: st + socs: + - name: stm32wba52xx diff --git a/boards/arm/nucleo_wba52cg/doc/img/nucleowba52cg.jpg b/boards/st/nucleo_wba52cg/doc/img/nucleowba52cg.jpg similarity index 100% rename from boards/arm/nucleo_wba52cg/doc/img/nucleowba52cg.jpg rename to boards/st/nucleo_wba52cg/doc/img/nucleowba52cg.jpg diff --git a/boards/arm/nucleo_wba52cg/doc/nucleo_wba52cg.rst b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst similarity index 98% rename from boards/arm/nucleo_wba52cg/doc/nucleo_wba52cg.rst rename to boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst index db45d48a7fa72d..cb72fdfb8311aa 100644 --- a/boards/arm/nucleo_wba52cg/doc/nucleo_wba52cg.rst +++ b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst @@ -183,7 +183,7 @@ The Zephyr nucleo_wba52cg board configuration supports the following hardware fe Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig`` +:zephyr_file:`boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig` Connections and IOs =================== @@ -233,7 +233,7 @@ For now, openocd support is available only on upstream OpenOCD. You can check In order to use it, you should clone and compile it following usual README guidelines. Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in -:zephyr_file:`boards/arm/nucleo_wba52cg/board.cmake` to point the build +:zephyr_file:`boards/st/nucleo_wba52cg/board.cmake` to point the build to the paths of the OpenOCD binary and its scripts, before including the common openocd.board.cmake file: diff --git a/boards/arm/nucleo_wba52cg/nucleo_wba52cg.dts b/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts similarity index 100% rename from boards/arm/nucleo_wba52cg/nucleo_wba52cg.dts rename to boards/st/nucleo_wba52cg/nucleo_wba52cg.dts diff --git a/boards/arm/nucleo_wba52cg/nucleo_wba52cg.yaml b/boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml similarity index 100% rename from boards/arm/nucleo_wba52cg/nucleo_wba52cg.yaml rename to boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml diff --git a/boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig b/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig similarity index 85% rename from boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig rename to boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig index 9b917b0fc69c1c..08e076454708fc 100644 --- a/boards/arm/nucleo_wba52cg/nucleo_wba52cg_defconfig +++ b/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32WBAX=y -CONFIG_SOC_STM32WBA52XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wba52cg/support/openocd.cfg b/boards/st/nucleo_wba52cg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wba52cg/support/openocd.cfg rename to boards/st/nucleo_wba52cg/support/openocd.cfg diff --git a/boards/st/nucleo_wba55cg/Kconfig.defconfig b/boards/st/nucleo_wba55cg/Kconfig.defconfig new file mode 100644 index 00000000000000..4a4717a5659148 --- /dev/null +++ b/boards/st/nucleo_wba55cg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WBA52CG Nucleo board configuration + +# Copyright (c) 2023 STMicroelectronics + +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NUCLEO_WBA55CG + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_NUCLEO_WBA55CG diff --git a/boards/st/nucleo_wba55cg/Kconfig.nucleo_wba55cg b/boards/st/nucleo_wba55cg/Kconfig.nucleo_wba55cg new file mode 100644 index 00000000000000..83289b3635b7df --- /dev/null +++ b/boards/st/nucleo_wba55cg/Kconfig.nucleo_wba55cg @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WBA55CG + select SOC_STM32WBA55XX diff --git a/boards/arm/nucleo_wba55cg/arduino_r3_connector.dtsi b/boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wba55cg/arduino_r3_connector.dtsi rename to boards/st/nucleo_wba55cg/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wba55cg/board.cmake b/boards/st/nucleo_wba55cg/board.cmake similarity index 100% rename from boards/arm/nucleo_wba55cg/board.cmake rename to boards/st/nucleo_wba55cg/board.cmake diff --git a/boards/st/nucleo_wba55cg/board.yml b/boards/st/nucleo_wba55cg/board.yml new file mode 100644 index 00000000000000..2fbe6b2bca49d6 --- /dev/null +++ b/boards/st/nucleo_wba55cg/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wba55cg + vendor: st + socs: + - name: stm32wba55xx diff --git a/boards/arm/nucleo_wba55cg/doc/img/nucleowba55cg.jpg b/boards/st/nucleo_wba55cg/doc/img/nucleowba55cg.jpg similarity index 100% rename from boards/arm/nucleo_wba55cg/doc/img/nucleowba55cg.jpg rename to boards/st/nucleo_wba55cg/doc/img/nucleowba55cg.jpg diff --git a/boards/arm/nucleo_wba55cg/doc/nucleo_wba55cg.rst b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst similarity index 98% rename from boards/arm/nucleo_wba55cg/doc/nucleo_wba55cg.rst rename to boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst index 2ea660da1f16f8..362d74f0e91067 100644 --- a/boards/arm/nucleo_wba55cg/doc/nucleo_wba55cg.rst +++ b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst @@ -181,7 +181,7 @@ The Zephyr nucleo_wba55cg board configuration supports the following hardware fe Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig`` +:zephyr_file:`boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig` Bluetooh support ---------------- @@ -244,7 +244,7 @@ For now, openocd support is available only on upstream OpenOCD. You can check In order to use it, you should clone and compile it following usual README guidelines. Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in -:zephyr_file:`boards/arm/nucleo_wba55cg/board.cmake` to point the build +:zephyr_file:`boards/st/nucleo_wba55cg/board.cmake` to point the build to the paths of the OpenOCD binary and its scripts, before including the common openocd.board.cmake file: diff --git a/boards/arm/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts similarity index 100% rename from boards/arm/nucleo_wba55cg/nucleo_wba55cg.dts rename to boards/st/nucleo_wba55cg/nucleo_wba55cg.dts diff --git a/boards/arm/nucleo_wba55cg/nucleo_wba55cg.yaml b/boards/st/nucleo_wba55cg/nucleo_wba55cg.yaml similarity index 100% rename from boards/arm/nucleo_wba55cg/nucleo_wba55cg.yaml rename to boards/st/nucleo_wba55cg/nucleo_wba55cg.yaml diff --git a/boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig b/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig similarity index 88% rename from boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig rename to boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig index 2c523d8801957a..98bb440f4abf28 100644 --- a/boards/arm/nucleo_wba55cg/nucleo_wba55cg_defconfig +++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig @@ -1,9 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 # Copyright (c) 2023 STMicroelectronics -CONFIG_SOC_SERIES_STM32WBAX=y -CONFIG_SOC_STM32WBA55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wba55cg/support/openocd.cfg b/boards/st/nucleo_wba55cg/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wba55cg/support/openocd.cfg rename to boards/st/nucleo_wba55cg/support/openocd.cfg diff --git a/boards/st/nucleo_wl55jc/Kconfig.nucleo_wl55jc b/boards/st/nucleo_wl55jc/Kconfig.nucleo_wl55jc new file mode 100644 index 00000000000000..365b200dee6406 --- /dev/null +++ b/boards/st/nucleo_wl55jc/Kconfig.nucleo_wl55jc @@ -0,0 +1,5 @@ +# Copyright (c) 2020 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NUCLEO_WL55JC + select SOC_STM32WL55XX diff --git a/boards/arm/nucleo_wl55jc/arduino_r3_connector.dtsi b/boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wl55jc/arduino_r3_connector.dtsi rename to boards/st/nucleo_wl55jc/arduino_r3_connector.dtsi diff --git a/boards/arm/nucleo_wl55jc/board.cmake b/boards/st/nucleo_wl55jc/board.cmake similarity index 100% rename from boards/arm/nucleo_wl55jc/board.cmake rename to boards/st/nucleo_wl55jc/board.cmake diff --git a/boards/st/nucleo_wl55jc/board.yml b/boards/st/nucleo_wl55jc/board.yml new file mode 100644 index 00000000000000..930da79b19925f --- /dev/null +++ b/boards/st/nucleo_wl55jc/board.yml @@ -0,0 +1,5 @@ +board: + name: nucleo_wl55jc + vendor: st + socs: + - name: stm32wl55xx diff --git a/boards/arm/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg b/boards/st/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg similarity index 100% rename from boards/arm/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg rename to boards/st/nucleo_wl55jc/doc/img/nucleo_wl55jc.jpg diff --git a/boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst similarity index 98% rename from boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst rename to boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst index 3d569753f15257..df32bbc07c071d 100644 --- a/boards/arm/nucleo_wl55jc/doc/nucleo_wl55jc.rst +++ b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst @@ -211,10 +211,10 @@ features: Other hardware features are not yet supported on this Zephyr port. -The default configuration can be found in the defconfig and dts files: +The default configuration can be found in: -- :zephyr_file:`boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig` -- :zephyr_file:`boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts` +- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig` +- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc.dts` Connections and IOs diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts b/boards/st/nucleo_wl55jc/nucleo_wl55jc.dts similarity index 100% rename from boards/arm/nucleo_wl55jc/nucleo_wl55jc.dts rename to boards/st/nucleo_wl55jc/nucleo_wl55jc.dts diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc.yaml b/boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml similarity index 100% rename from boards/arm/nucleo_wl55jc/nucleo_wl55jc.yaml rename to boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml diff --git a/boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig b/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig similarity index 83% rename from boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig rename to boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig index 813ba6643ccc89..0d6dc9f80d3dd9 100644 --- a/boards/arm/nucleo_wl55jc/nucleo_wl55jc_defconfig +++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WLX=y -CONFIG_SOC_STM32WL55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/nucleo_wl55jc/st_morpho_connector.dtsi b/boards/st/nucleo_wl55jc/st_morpho_connector.dtsi similarity index 100% rename from boards/arm/nucleo_wl55jc/st_morpho_connector.dtsi rename to boards/st/nucleo_wl55jc/st_morpho_connector.dtsi diff --git a/boards/arm/nucleo_wl55jc/support/openocd.cfg b/boards/st/nucleo_wl55jc/support/openocd.cfg similarity index 100% rename from boards/arm/nucleo_wl55jc/support/openocd.cfg rename to boards/st/nucleo_wl55jc/support/openocd.cfg diff --git a/boards/st/sensortile_box/Kconfig.defconfig b/boards/st/sensortile_box/Kconfig.defconfig new file mode 100644 index 00000000000000..29aa7598ef81b0 --- /dev/null +++ b/boards/st/sensortile_box/Kconfig.defconfig @@ -0,0 +1,31 @@ +# SensorTile.box board configuration + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SENSORTILE_BOX + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n +config BT_HCI_VS_EXT + default n + +endif # BT + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_SENSORTILE_BOX diff --git a/boards/st/sensortile_box/Kconfig.sensortile_box b/boards/st/sensortile_box/Kconfig.sensortile_box new file mode 100644 index 00000000000000..0d7ec6b82af5f5 --- /dev/null +++ b/boards/st/sensortile_box/Kconfig.sensortile_box @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SENSORTILE_BOX + select SOC_STM32L4R9XX diff --git a/boards/arm/96b_carbon/board.cmake b/boards/st/sensortile_box/board.cmake similarity index 100% rename from boards/arm/96b_carbon/board.cmake rename to boards/st/sensortile_box/board.cmake diff --git a/boards/st/sensortile_box/board.yml b/boards/st/sensortile_box/board.yml new file mode 100644 index 00000000000000..4ac086b2cb7c97 --- /dev/null +++ b/boards/st/sensortile_box/board.yml @@ -0,0 +1,5 @@ +board: + name: sensortile_box + vendor: st + socs: + - name: stm32l4r9xx diff --git a/boards/arm/sensortile_box/doc/img/sensortile_box.jpg b/boards/st/sensortile_box/doc/img/sensortile_box.jpg similarity index 100% rename from boards/arm/sensortile_box/doc/img/sensortile_box.jpg rename to boards/st/sensortile_box/doc/img/sensortile_box.jpg diff --git a/boards/arm/sensortile_box/doc/index.rst b/boards/st/sensortile_box/doc/index.rst similarity index 100% rename from boards/arm/sensortile_box/doc/index.rst rename to boards/st/sensortile_box/doc/index.rst diff --git a/boards/arm/sensortile_box/sensortile_box.dts b/boards/st/sensortile_box/sensortile_box.dts similarity index 100% rename from boards/arm/sensortile_box/sensortile_box.dts rename to boards/st/sensortile_box/sensortile_box.dts diff --git a/boards/arm/sensortile_box/sensortile_box.yaml b/boards/st/sensortile_box/sensortile_box.yaml similarity index 100% rename from boards/arm/sensortile_box/sensortile_box.yaml rename to boards/st/sensortile_box/sensortile_box.yaml diff --git a/boards/arm/sensortile_box/sensortile_box_defconfig b/boards/st/sensortile_box/sensortile_box_defconfig similarity index 85% rename from boards/arm/sensortile_box/sensortile_box_defconfig rename to boards/st/sensortile_box/sensortile_box_defconfig index 2970c68d6c9e7a..4ba8077edd667c 100644 --- a/boards/arm/sensortile_box/sensortile_box_defconfig +++ b/boards/st/sensortile_box/sensortile_box_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R9XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/swan_r5/support/openocd.cfg b/boards/st/sensortile_box/support/openocd.cfg similarity index 100% rename from boards/arm/swan_r5/support/openocd.cfg rename to boards/st/sensortile_box/support/openocd.cfg diff --git a/boards/arm/sensortile_box_pro/CMakeLists.txt b/boards/st/sensortile_box_pro/CMakeLists.txt similarity index 100% rename from boards/arm/sensortile_box_pro/CMakeLists.txt rename to boards/st/sensortile_box_pro/CMakeLists.txt diff --git a/boards/st/sensortile_box_pro/Kconfig.defconfig b/boards/st/sensortile_box_pro/Kconfig.defconfig new file mode 100644 index 00000000000000..f0271728a9a3e3 --- /dev/null +++ b/boards/st/sensortile_box_pro/Kconfig.defconfig @@ -0,0 +1,39 @@ +# SENSORTILE_BOX_PRO board configuration + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_SENSORTILE_BOX_PRO + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y + +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n + +endif # BT + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +if LOG + +# Logger cannot use itself to log +choice USB_CDC_ACM_LOG_LEVEL_CHOICE + default USB_CDC_ACM_LOG_LEVEL_OFF +endchoice + +endif # LOG + +endif # BOARD_SENSORTILE_BOX_PRO diff --git a/boards/st/sensortile_box_pro/Kconfig.sensortile_box_pro b/boards/st/sensortile_box_pro/Kconfig.sensortile_box_pro new file mode 100644 index 00000000000000..b0928107887329 --- /dev/null +++ b/boards/st/sensortile_box_pro/Kconfig.sensortile_box_pro @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SENSORTILE_BOX_PRO + select SOC_STM32U585XX diff --git a/boards/arm/sensortile_box_pro/board.c b/boards/st/sensortile_box_pro/board.c similarity index 100% rename from boards/arm/sensortile_box_pro/board.c rename to boards/st/sensortile_box_pro/board.c diff --git a/boards/arm/sensortile_box_pro/board.cmake b/boards/st/sensortile_box_pro/board.cmake similarity index 100% rename from boards/arm/sensortile_box_pro/board.cmake rename to boards/st/sensortile_box_pro/board.cmake diff --git a/boards/st/sensortile_box_pro/board.yml b/boards/st/sensortile_box_pro/board.yml new file mode 100644 index 00000000000000..d3bb8ca9ee93d6 --- /dev/null +++ b/boards/st/sensortile_box_pro/board.yml @@ -0,0 +1,5 @@ +board: + name: sensortile_box_pro + vendor: st + socs: + - name: stm32u585xx diff --git a/boards/arm/sensortile_box_pro/doc/img/sensortile_box_pro.jpg b/boards/st/sensortile_box_pro/doc/img/sensortile_box_pro.jpg similarity index 100% rename from boards/arm/sensortile_box_pro/doc/img/sensortile_box_pro.jpg rename to boards/st/sensortile_box_pro/doc/img/sensortile_box_pro.jpg diff --git a/boards/st/sensortile_box_pro/doc/index.rst b/boards/st/sensortile_box_pro/doc/index.rst new file mode 100644 index 00000000000000..e98ddace1bbf8a --- /dev/null +++ b/boards/st/sensortile_box_pro/doc/index.rst @@ -0,0 +1,386 @@ +.. _sensortile_box_pro_board: + +ST SensorTile.box PRO +##################### + +Overview +******** + +The STEVAL-MKBOXPRO (SensorTile.box PRO) features an ARM Cortex-M33 based STM32U585AI MCU +and is a ready-to-use box kit for wireless IoT and wearable sensor platforms to help using +and developing apps based on remote motion and environmental sensor data. + +The SensorTile.box PRO board fits into a small plastic box with a long-life rechargeable +battery, and communicates with a standard smartphone through its Bluetooth interface, +providing data coming from the sensors. + +.. image:: img/sensortile_box_pro.jpg + :align: center + :alt: SensorTile.box PRO + +More information about the board can be found at the `SensorTile.box PRO website`_. + +Supported Features +****************** + +The SensorTile.box PRO provides motion, environmental, and audio +sensor data through either the BLE or USB protocols to a host application running +on a smartphone/PC to implement applications such as: + +- Pedometer optimized for belt positioning +- Baby crying detection with Cloud AI learning +- Barometer / environmental monitoring +- Vehicle / goods tracking +- Vibration monitoring +- Compass and inclinometer +- Sensor data logger + +(see `Motion and environmental sensors`_ section for the complete lists of available +sensors on board) + +Hardware +******** + +The STM32U585xx devices are an ultra-low-power microcontrollers family (STM32U5 +Series) based on the high-performance Arm|reg| Cortex|reg|-M33 32-bit RISC core. +They operate at a frequency of up to 160 MHz. + +- Ultra-low-power with FlexPowerControl (down to 300 nA Standby mode and 19.5 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 651 CoreMark |reg| (4.07 CoreMark |reg| /MHZ) + +- Security and cryptography + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) and password protected debug + - Root of trust thanks to unique boot entry and secure hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure data storage with hardware unique key (HUK) + - Secure Firmware Update support with TF-M + - 2 AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - Active tampers + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + - Active tampers + +- Clock management: + + - 4 to 50 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - 2 internal multispeed 100 kHz to 48 MHz oscillators, including one auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + - Internal 48 MHz with clock recovery + +- Power management + + - Embedded regulator (LDO) + - Embedded SMPS step-down converter supporting switch on-the-fly and voltage scaling + +- RTC with HW calendar and calibration +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 17 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5 x 16-bit general purpose + - 4x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- ART accelerator + + - 8-Kbyte instruction cache allowing 0-wait-state execution from Flash and + external memories: up to 160 MHz, MPU, 240 DMIPS and DSP + - 4-Kbyte data cache for external memories + +- Memories + + - 2-Mbyte Flash memory with ECC, 2 banks read-while-write, including 512 Kbytes with 100 kcycles + - 786-Kbyte SRAM with ECC OFF or 722-Kbyte SRAM including up to 322-Kbyte SRAM with ECC ON + - External memory interface supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - 2 Octo-SPI memory interfaces + +- Rich analog peripherals (independent supply) + + - 14-bit ADC 2.5-Msps, resolution up to 16 bits with hardware oversampling + - 12-bit ADC 2.5-Msps, with hardware oversampling, autonomous in Stop 2 mode + - 12-bit DAC, low-power sample and hold + - 2 operational amplifiers with built-in PGA + - 2 ultra-low-power comparators + +- Up to 22 communication interfaces + + - USB Type-C / USB power delivery controller + - USB OTG 2.0 full-speed controller + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (5x SPIs with dual OCTOSPI in SPI mode) + - 1x FDCAN + - 2x SDMMC interface + - 16- and 4-channel DMA controllers, functional in Stop mode + - 1 multi-function digital filter (6 filters)+ 1 audio digital filter with + sound-activity detection + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| +- True Random Number Generator (RNG) + +- Graphic features + + - Chrom-ART Accelerator (DMA2D) for enhanced graphic content creation + - 1 digital camera interface + +- Mathematical co-processor + + - CORDIC for trigonometric functions acceleration + - FMAC (filter mathematical accelerator) + + +More information about STM32U585AI can be found here: + +- `STM32U585 on www.st.com`_ +- `STM32U585 reference manual`_ + +Motion and environmental sensors +================================ + + - **LSM6DSV16X** 6-axis inertial measurement unit + (`lsm6dsv16x datasheet`_) + - **LIS2MDL** 3-axis magnetometer + (`lis2mdl datasheet`_) + - **LPS22DF** Altimeter / pressure sensor + (`lps22df datasheet`_) + - **LIS2DU12** 3-axis accelerometer + (`lis2du12 datasheet`_) + - **HTS221** Humidity sensor + (`hts221 datasheet`_) + - **STTS22H** Digital temperature sensor + (`stts22hh datasheet`_) + - **MP23db01HP** Microphone / audio sensor + (`mp23db01hp datasheet`_) + +Connections and IOs +=================== + +- 4x user LEDs + + - **led0** (Green) + - **led1** (Red - shared with BLE) + - **led2** (Yellow) + - **led3** (Blue) + + +- 4x buttons/switch + + - **User BT1** button, available to user application + - **User BT2** / **boot0** button, available to user application + but useful to let the SensorTile.box PRO enter DFU mode + if found pressed after h/w reset (see **rst** button and + `Programming and Debugging`_ section) + - **rst** button, used to reset the board (not available on case) + - **power** switch, used to Power on/off the board + +System Clock +============ + +SensorTile.box PRO System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default, the System clock is +driven by the PLL clock at 80MHz, driven by the 16MHz external oscillator. +The system clock can be boosted to 120MHz. +The internal AHB/APB1/APB2 AMBA buses are all clocked at 80MHz. + +Serial Port +=========== + +The SensorTile.box PRO has 4 U(S)ARTs. The UART4 is connected to JTAG/SWD connector +and may be used as console. + +USB interface +============= + +SensorTile.box PRO can be connected as a USB device to a PC host through its USB-C connector. +The final application may use it to declare SensorTile.box PRO device as belonging to a +certain standard or vendor class, e.g. a CDC, a mass storage or a composite device with both +functions. + +Console +======= + +There are two possible options for Zephyr console output: + +- through UART4 which is available on SWD connector (JP2). In this case a JTAG adapter + can be used to connect SensorTile.box PRO and have both SWD and console lines available. + + To enable console and shell over UART + + - switch the console lines from cdc_acm to uart4 + (:file:`boards/st/sensortile_box_pro/sensortile_box_pro.dts`) + + - comment out the USB configuration macros + (:file:`boards/st/sensortile_box_pro/sensortile_box_pro_defconfig`) + +.. code-block:: dts + :caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts + + / { + chosen { + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + //zephyr,console = &cdc_acm_uart0; + //zephyr,shell-uart = &cdc_acm_uart0; + }; + }; + +.. code-block:: Kconfig + :caption: boards/st/sensortile_box_pro/sensortile_box_pro_defconfig + + # Comment out following USB config lines when + # switching console to UART + #CONFIG_USB_DEVICE_STACK=y + #CONFIG_USB_DEVICE_VID=0x0483 + #CONFIG_USB_DEVICE_PID=0x1235 + #CONFIG_USB_DEVICE_PRODUCT="Zephyr CDC SensorTile.box PRO" + #CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y + #CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n + + +- through USB as USB CDC/ACM class. This is the default case present in the board dts file. + +.. code-block:: dts + :caption: boards/st/sensortile_box_pro/sensortile_box_pro.dts + + / { + chosen { + zephyr,console = &cdc_acm_uart0; + }; + }; + + &zephyr_udc0 { + cdc_acm_uart0: cdc_acm_uart0 { + compatible = "zephyr,cdc-acm-uart"; + }; + }; + + + +Console default settings are 115200 8N1. + +Programming and Debugging +************************* + +There are two alternative methods of flashing ST Sensortile.box Pro board: + +1. Using DFU software tools + + This method requires to enter STM32U585 ROM bootloader DFU mode + by powering up (or reset) the board while keeping the BOOT0 button pressed. + No additional hardware is required except a USB-C cable. This method is fully + supported by :ref:`flash-debug-host-tools`. + You can read more about how to enable and use the ROM bootloader by checking + the application note `AN2606`_ (STM32U585xx section). + +2. Using SWD hardware tools + + This method requires to connect additional hardware, like a ST-LINK/V3 + embedded debug tool, to the board SWD connector. + +DFU flashing +============ + +Install dfu-util +---------------- + +It is recommended to use at least v0.9 of dfu-util. The package available in +Debian and Ubuntu can be quite old, so you might have to build dfu-util from source. +Information about how to get the source code and how to build it can be found +at the `DFU-UTIL website`_ + +Flash an Application to SensorTile.box PRO +------------------------------------------ + +While pressing the BOOT0 button, connect the USB-C cable to the USB OTG SensorTile.box PRO +port and to your computer. The board should be forced to enter DFU mode. + +Check that the board is indeed in DFU mode: + +.. code-block:: console + + $ sudo dfu-util -l + dfu-util 0.9 + + Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc. + Copyright 2010-2019 Tormod Volden and Stefan Schmidt + This program is Free Software and has ABSOLUTELY NO WARRANTY + Please report bugs to http://sourceforge.net/p/dfu-util/tickets/ + + Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=2, name="@OTP Memory /0x1FFF7000/01*0001Ke", serial="204A325D574D" + Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=1, name="@Option Bytes /0x1FF00000/01*040 e/0x1FF01000/01*040 e", serial="204A325D574D" + Found DFU: [0483:df11] ver=2200, devnum=74, cfg=1, intf=0, path="2-2", alt=0, name="@Internal Flash /0x08000000/512*0004Kg", serial="204A325D574D" + +You should see following confirmation on your Linux host: + +.. code-block:: console + + $ dmesg + usb 2-2: new full-speed USB device number 74 using xhci_hcd + usb 2-2: New USB device found, idVendor=0483, idProduct=df11 + usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + usb 2-2: Product: STM32 BOOTLOADER + usb 2-2: Manufacturer: STMicroelectronics + usb 2-2: SerialNumber: 204A325D574D + +You can build and flash the provided sample application +(:ref:`sensortile_box_pro_sample_sensors`) that reads sensors data and outputs +values on the console. + +References +********** + +.. target-notes:: + +.. _SensorTile.box PRO website: + https://www.st.com/en/evaluation-tools/steval-mkboxpro.html + +.. _STM32U585 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u575-585.html + +.. _STM32U585 reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u575585-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _lsm6dsv16x datasheet: + https://www.st.com/en/mems-and-sensors/lsm6dsv16x.html + +.. _lis2mdl datasheet: + https://www.st.com/en/mems-and-sensors/lis2mdl.html + +.. _lps22df datasheet: + https://www.st.com/en/mems-and-sensors/lps22df.html + +.. _lis2du12 datasheet: + https://www.st.com/en/mems-and-sensors/lis2du12.html + +.. _hts221 datasheet: + https://www.st.com/en/mems-and-sensors/hts221.html + +.. _stts22hh datasheet: + https://www.st.com/en/mems-and-sensors/stts22h.html + +.. _mp23db01hp datasheet: + https://www.st.com/en/mems-and-sensors/mp23db01hp.html + +.. _AN2606: + http://www.st.com/content/ccc/resource/technical/document/application_note/b9/9b/16/3a/12/1e/40/0c/CD00167594.pdf/files/CD00167594.pdf/jcr:content/translations/en.CD00167594.pdf + +.. _DFU-UTIL website: + http://dfu-util.sourceforge.net/ diff --git a/boards/arm/sensortile_box_pro/sensortile_box_pro.dts b/boards/st/sensortile_box_pro/sensortile_box_pro.dts similarity index 100% rename from boards/arm/sensortile_box_pro/sensortile_box_pro.dts rename to boards/st/sensortile_box_pro/sensortile_box_pro.dts diff --git a/boards/arm/sensortile_box_pro/sensortile_box_pro.yaml b/boards/st/sensortile_box_pro/sensortile_box_pro.yaml similarity index 100% rename from boards/arm/sensortile_box_pro/sensortile_box_pro.yaml rename to boards/st/sensortile_box_pro/sensortile_box_pro.yaml diff --git a/boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig b/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig similarity index 92% rename from boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig rename to boards/st/sensortile_box_pro/sensortile_box_pro_defconfig index 7a91dc1c19581d..a47f372d784715 100644 --- a/boards/arm/sensortile_box_pro/sensortile_box_pro_defconfig +++ b/boards/st/sensortile_box_pro/sensortile_box_pro_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U585XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/sensortile_box_pro/support/openocd.cfg b/boards/st/sensortile_box_pro/support/openocd.cfg similarity index 100% rename from boards/arm/sensortile_box_pro/support/openocd.cfg rename to boards/st/sensortile_box_pro/support/openocd.cfg diff --git a/boards/st/steval_fcu001v1/Kconfig.steval_fcu001v1 b/boards/st/steval_fcu001v1/Kconfig.steval_fcu001v1 new file mode 100644 index 00000000000000..d726c3f0e9267a --- /dev/null +++ b/boards/st/steval_fcu001v1/Kconfig.steval_fcu001v1 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STEVAL_FCU001V1 + select SOC_STM32F401XC diff --git a/boards/arm/steval_fcu001v1/board.cmake b/boards/st/steval_fcu001v1/board.cmake similarity index 100% rename from boards/arm/steval_fcu001v1/board.cmake rename to boards/st/steval_fcu001v1/board.cmake diff --git a/boards/st/steval_fcu001v1/board.yml b/boards/st/steval_fcu001v1/board.yml new file mode 100644 index 00000000000000..16357770fa4a1e --- /dev/null +++ b/boards/st/steval_fcu001v1/board.yml @@ -0,0 +1,5 @@ +board: + name: steval_fcu001v1 + vendor: st + socs: + - name: stm32f401xc diff --git a/boards/arm/steval_fcu001v1/doc/img/steval_fcu001v1.jpg b/boards/st/steval_fcu001v1/doc/img/steval_fcu001v1.jpg similarity index 100% rename from boards/arm/steval_fcu001v1/doc/img/steval_fcu001v1.jpg rename to boards/st/steval_fcu001v1/doc/img/steval_fcu001v1.jpg diff --git a/boards/st/steval_fcu001v1/doc/index.rst b/boards/st/steval_fcu001v1/doc/index.rst new file mode 100644 index 00000000000000..a76f99c6e01cd7 --- /dev/null +++ b/boards/st/steval_fcu001v1/doc/index.rst @@ -0,0 +1,158 @@ +.. _steval_fcu001v1: + +ST STM32 Flight Controller Unit +############################### + +Overview +******** + +The STEVAL-FCU001V1 is a Cortex M4 MCU-based flight controller unit for toy quad-copter drones. + +.. figure:: img/steval_fcu001v1.jpg + :align: center + :alt: STM32 Flight Controller Unit + +Hardware +******** + +STM32 Flight Controller Unit provides the following hardware components: + +- STM32F401CC in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg|-M4 MCU with FPU +- 84MHz max MCU frequency +- VDD from 1.7 V to 3.6 V +- 256 KB FLASH +- 64 KB SRAM +- General Purpose Timers +- Watchdog Timers (2) +- On board sensors: + + - 3D Accelerometer and 3D Gyroscope: LSM6DSL + - 3D Magnetometer: LIS2MDL + - MEMS Pressure sensor: LPS22HD + +- 2 User LEDS +- USART/UART (1) +- I2C (1) +- Bluetooth LE over SPI + +More information about the STM32 Flight Controller Unit +can be found in these documents: + +- `STEVAL_FCU001V1 website`_ +- `STM32F401 reference manual`_ +- `STM32F401CC on www.st.com`_ + +Supported Features +================== + +The Zephyr steval_fcu001v1 board configuration supports the following hardware features: + ++-----------+------------+------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+------------------------------------+ + + +The default configuration can be found in +:zephyr_file:`boards/st/steval_fcu001v1/steval_fcu001v1_defconfig` + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C2 SCL/SDA : PB10/PB3 +- PWM_2_CH1 : PA0 +- LD1 : PB5 +- LD2 : PB4 + +System Clock +============ + +The steval_fcu001v1 system clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the system clock is driven by the PLL clock at 84MHz, +driven by a 16MHz high-speed external clock. + +Serial Port +=========== + +The steval_fcu001v1 board has one UART. The Zephyr console output is assigned to UART1. +Default settings are 115200 8N1. + +I2C +=== + +The steval_fcu001v1 board has one I2C. The default I2C mapping for Zephyr is: + +- I2C2_SCL : PB10 +- I2C2_SDA : PB3 + +Programming and Debugging +************************* + +Applications for the ``steval_fcu001v1`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +Flashing Zephyr onto the steval_fcu001v1 board requires an external ST-LINK/V2-1 programmer. +The programmer is attached to the P8 programming header with ARM-JTAG-20-10-Plug-in Adapter. + +Flashing an application to STEVAL_FCU001V1 +------------------------------------------ + +Connect the FT232-to-USB port to host system, and RX, TX, Gnd pins to +the P7 header of the steval_fcu001v1 board. Then run a serial host +program to connect with your steval_fcu001v1 via the FT232 board: + +.. code-block:: console + + $ minicom -D /dev/ttyUSB0 + +Now build and flash an application. Here is an example for :ref:`hello_world` + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: steval_fcu001v1 + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! steval_fcu001v1 + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: steval_fcu001v1 + :maybe-skip-config: + :goals: debug + +.. _STEVAL_FCU001V1 website: + https://www.st.com/en/evaluation-tools/steval-fcu001v1.html + +.. _STM32F401CC on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32f401cc.html + +.. _STM32F401 reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/steval_fcu001v1/steval_fcu001v1.dts b/boards/st/steval_fcu001v1/steval_fcu001v1.dts similarity index 100% rename from boards/arm/steval_fcu001v1/steval_fcu001v1.dts rename to boards/st/steval_fcu001v1/steval_fcu001v1.dts diff --git a/boards/arm/steval_fcu001v1/steval_fcu001v1.yaml b/boards/st/steval_fcu001v1/steval_fcu001v1.yaml similarity index 100% rename from boards/arm/steval_fcu001v1/steval_fcu001v1.yaml rename to boards/st/steval_fcu001v1/steval_fcu001v1.yaml diff --git a/boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig b/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig similarity index 81% rename from boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig rename to boards/st/steval_fcu001v1/steval_fcu001v1_defconfig index 53be30e3c52d0b..e4d07bf318455d 100644 --- a/boards/arm/steval_fcu001v1/steval_fcu001v1_defconfig +++ b/boards/st/steval_fcu001v1/steval_fcu001v1_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/steval_fcu001v1/support/openocd.cfg b/boards/st/steval_fcu001v1/support/openocd.cfg similarity index 100% rename from boards/arm/steval_fcu001v1/support/openocd.cfg rename to boards/st/steval_fcu001v1/support/openocd.cfg diff --git a/boards/st/stm3210c_eval/Kconfig.stm3210c_eval b/boards/st/stm3210c_eval/Kconfig.stm3210c_eval new file mode 100644 index 00000000000000..40baeecc6722e1 --- /dev/null +++ b/boards/st/stm3210c_eval/Kconfig.stm3210c_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM3210C_EVAL + select SOC_STM32F107XC diff --git a/boards/arm/stm3210c_eval/board.cmake b/boards/st/stm3210c_eval/board.cmake similarity index 100% rename from boards/arm/stm3210c_eval/board.cmake rename to boards/st/stm3210c_eval/board.cmake diff --git a/boards/st/stm3210c_eval/board.yml b/boards/st/stm3210c_eval/board.yml new file mode 100644 index 00000000000000..bb8003f01ab96c --- /dev/null +++ b/boards/st/stm3210c_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm3210c_eval + vendor: st + socs: + - name: stm32f107xc diff --git a/boards/arm/stm3210c_eval/doc/img/stm3210c_eval.jpg b/boards/st/stm3210c_eval/doc/img/stm3210c_eval.jpg similarity index 100% rename from boards/arm/stm3210c_eval/doc/img/stm3210c_eval.jpg rename to boards/st/stm3210c_eval/doc/img/stm3210c_eval.jpg diff --git a/boards/arm/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg b/boards/st/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg similarity index 100% rename from boards/arm/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg rename to boards/st/stm3210c_eval/doc/img/stm3210c_eval_connectors.jpg diff --git a/boards/st/stm3210c_eval/doc/index.rst b/boards/st/stm3210c_eval/doc/index.rst new file mode 100644 index 00000000000000..383a0e2f5fbde8 --- /dev/null +++ b/boards/st/stm3210c_eval/doc/index.rst @@ -0,0 +1,165 @@ +.. _stm3210c_eval_board: + +ST STM3210C Evaluation +###################### + +Overview +******** +The STM3210C-EVAL evaluation board is a complete development platform for STMicroelectronic's +ARM Cortex-M3 core-based STM32F107VCT microcontroller. + +The range of hardware features on the board help you to evaluate all peripherals +(USB-OTG FS, ethernet, motor control, CAN, microSD CardTM, smartcard, USART, +audio DAC, MEMS, EEPROM and more) and develop your own applications. + +Extension headers make it easy to connect a daughterboard or wrapping board for your specific +application. + +.. image:: img/stm3210c_eval.jpg + :align: center + :alt: STM3210C-EVAL + +More information about the board can be found at the `STM3210C-EVAL website`_. + +Hardware +******** + +STM3210C-EVAL provides the following hardware components: + +- Three 5 V power supply options: + - Power jack + - USB connector + - daughterboard +- Boot from user Flash, system memory or SRAM. +- I2S audio DAC, stereo audio jack. +- 2 GByte (or more) microSD CardTM. +- Both type A and B smartcard support. +- I2C compatible serial interface 64 Kbit EEPROM, MEMS and I/O expander. +- RS-232 communication. +- IrDA transceiver. +- USB-OTG full speed, USB microAB connector. +- IEEE-802.3-2002 compliant ethernet connector. +- Two channels of CAN2.0A/B compliant connection. +- Inductor motor control connector. +- JTAG and trace debug support. +- 3.2" 240x320 TFT color LCD with touch screen. +- Joystick with 4-direction control and selector. +- Reset, Wakeup, Tamper and User button. +- 4 color LEDs. +- RTC with backup battery. +- MCU consumption measurement circuit. +- Extension connector for daughterboard or wrapping board. + +More information about STM32F107VCT can be found here: + - `STM32F107VCT reference manual`_ + + +Supported Features +================== + +The Zephyr stm3210c_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm3210c_eval/stm3210c_eval_defconfig`. + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/stm3210c_eval_connectors.jpg + :align: center + :alt: STM3210C_EVAL connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PB9 +- LED2 : PD13 + +Programming and Debugging +************************* + +Flashing +======== + +STM3210C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. +At power-on, the board is in firmware-upgrade mode (also called DFU for +"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. +This interface is supported by the openocd version included in Zephyr SDK. + +Applications for the ``stm3210c_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing an application to STM3210C-EVAL +---------------------------------------- + +Connect the STM3210C-EVAL to your host computer using the USB port, then build +and flash an application in the usual way. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm3210c_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can run a serial host program to connect with your STM3210C-EVAL board. For +example, on Linux: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm3210c_eval + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM3210C-EVAL website: + https://www.st.com/en/evaluation-tools/stm3210c-eval.html + +.. _STM32F107VCT reference manual: + https://www.st.com/resource/en/reference_manual/CD00171190.pdf diff --git a/boards/arm/stm3210c_eval/stm3210c_eval.dts b/boards/st/stm3210c_eval/stm3210c_eval.dts similarity index 100% rename from boards/arm/stm3210c_eval/stm3210c_eval.dts rename to boards/st/stm3210c_eval/stm3210c_eval.dts diff --git a/boards/arm/stm3210c_eval/stm3210c_eval.yaml b/boards/st/stm3210c_eval/stm3210c_eval.yaml similarity index 100% rename from boards/arm/stm3210c_eval/stm3210c_eval.yaml rename to boards/st/stm3210c_eval/stm3210c_eval.yaml diff --git a/boards/st/stm3210c_eval/stm3210c_eval_defconfig b/boards/st/stm3210c_eval/stm3210c_eval_defconfig new file mode 100644 index 00000000000000..5af8b611205e3d --- /dev/null +++ b/boards/st/stm3210c_eval/stm3210c_eval_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# RCC Controller +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm3210c_eval/support/openocd.cfg b/boards/st/stm3210c_eval/support/openocd.cfg similarity index 100% rename from boards/arm/stm3210c_eval/support/openocd.cfg rename to boards/st/stm3210c_eval/support/openocd.cfg diff --git a/boards/st/stm32373c_eval/Kconfig.stm32373c_eval b/boards/st/stm32373c_eval/Kconfig.stm32373c_eval new file mode 100644 index 00000000000000..fc8baa062de4e9 --- /dev/null +++ b/boards/st/stm32373c_eval/Kconfig.stm32373c_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32373C_EVAL + select SOC_STM32F373XC diff --git a/boards/arm/stm32373c_eval/board.cmake b/boards/st/stm32373c_eval/board.cmake similarity index 100% rename from boards/arm/stm32373c_eval/board.cmake rename to boards/st/stm32373c_eval/board.cmake diff --git a/boards/st/stm32373c_eval/board.yml b/boards/st/stm32373c_eval/board.yml new file mode 100644 index 00000000000000..32da748e9a75a4 --- /dev/null +++ b/boards/st/stm32373c_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32373c_eval + vendor: st + socs: + - name: stm32f373xc diff --git a/boards/arm/stm32373c_eval/doc/img/stm32373c_eval.jpg b/boards/st/stm32373c_eval/doc/img/stm32373c_eval.jpg similarity index 100% rename from boards/arm/stm32373c_eval/doc/img/stm32373c_eval.jpg rename to boards/st/stm32373c_eval/doc/img/stm32373c_eval.jpg diff --git a/boards/arm/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg b/boards/st/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg similarity index 100% rename from boards/arm/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg rename to boards/st/stm32373c_eval/doc/img/stm32373c_eval_connectors.jpg diff --git a/boards/st/stm32373c_eval/doc/index.rst b/boards/st/stm32373c_eval/doc/index.rst new file mode 100644 index 00000000000000..b6895a4bca221c --- /dev/null +++ b/boards/st/stm32373c_eval/doc/index.rst @@ -0,0 +1,159 @@ +.. _stm32373c_eval_board: + +ST STM32373C Evaluation +####################### + +Overview +******** +The STM32373C-EVAL evaluation board is designed as a complete demonstration and development platform for STMicroelectronics ARM Cortex-M4 core-based STM32F373VCT6 microcontroller. + +The full range of hardware features on the board can help the user evaluate all peripherals (USB FS, USART, audio DAC, microphone ADC, dot-matrix LCD, IrDA, LDR, MicroSD card, HDMI CEC, ECG, pressure sensor, CAN, IR transmitter and receiver, EEPROM, touch slider, temperature sensor, etc.) and develop their own applications. + +Extension headers make it possible to easily connect a daughter board or wrapping board for a specific application. + +.. image:: img/stm32373c_eval.jpg + :align: center + :alt: STM32373C-EVAL + +More information about the board can be found at the `STM32373C-EVAL website`_. + +Hardware +******** + +STM32373C-EVAL provides the following hardware components: + +- STM32F373VCT6 microcontroller +- Four 5 V power supply options: + - Power jack + - ST-LINK/V2 USB connector + - User USB connector + - Daughter board +- Audio jack connected to I2 S DAC +- Microphone connected to ADC through an amplifier +- 2-GByte (or more) MicroSD card on SPI +- Three components on I2 C bus: temperature sensor, EEPROM and dual interface RF EEPROM +- RS-232 communication configurable for communication of Flash loader +- IrDA transceiver +- 240x320 TFT color LCD connected to SPI interface +- Joystick with 4-direction control and selector +- Reset, Wakeup or Tamper, and Key buttons +- 4 color user LEDs +- 2 LEDs for MCU power range indicator +- ECG, pressure sensor and PT100 temperature sensor connected to the 16-bit Sigma Delta ADC of STM32F373VCT6 +- Extension connectors for daughter board or wrapping board +- MCU voltage: 3.3 V or adjustable 2.0 V - 3.6 V +- USB FS connector +- Touch slider +- RTC with backup battery +- CAN 2.0 A/B compliant connection +- Light dependent resistor (LDR) +- Two HDMI connectors with DDC and CEC +- IR transmitter and receiver +- Two ADC & DAC input and output signal connectors and one Sigma Delta ADC input signal connector +- Potentiometer +- JTAG/SWD and ETM trace debug support +- Embedded ST-LINK/V2 + +More information about STM32F373VCT6 can be found here: + - `STM32F373VCT6 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32373c_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32373c_eval/stm32373c_eval_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/stm32373c_eval_connectors.jpg + :align: center + :alt: STM32373C_EVAL connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- USER_PB : PA2 +- LED2 : PC1 + +Programming and Debugging +************************* + +Applications for the ``stm32373c_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32373C-EVAL board includes an ST-LINK/V2-1 embedded debug tool interface. +At power-on, the board is in firmware-upgrade mode (also called DFU for +"Device Firmware Upgrade"), allowing the firmware to be updated through the USB. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32373C-EVAL +----------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32373c_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32373c_eval + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32373C-EVAL website: + https://www.st.com/en/evaluation-tools/stm32373c-eval.html + +.. _STM32F373VCT6 reference manual: + https://www.st.com/resource/en/reference_manual/dm00041563.pdf diff --git a/boards/arm/stm32373c_eval/stm32373c_eval.dts b/boards/st/stm32373c_eval/stm32373c_eval.dts similarity index 100% rename from boards/arm/stm32373c_eval/stm32373c_eval.dts rename to boards/st/stm32373c_eval/stm32373c_eval.dts diff --git a/boards/arm/stm32373c_eval/stm32373c_eval.yaml b/boards/st/stm32373c_eval/stm32373c_eval.yaml similarity index 100% rename from boards/arm/stm32373c_eval/stm32373c_eval.yaml rename to boards/st/stm32373c_eval/stm32373c_eval.yaml diff --git a/boards/arm/stm32373c_eval/stm32373c_eval_defconfig b/boards/st/stm32373c_eval/stm32373c_eval_defconfig similarity index 76% rename from boards/arm/stm32373c_eval/stm32373c_eval_defconfig rename to boards/st/stm32373c_eval/stm32373c_eval_defconfig index e61cabb061b70c..579a5c3fc4ef31 100644 --- a/boards/arm/stm32373c_eval/stm32373c_eval_defconfig +++ b/boards/st/stm32373c_eval/stm32373c_eval_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F3X=y - -# Platform Configuration -CONFIG_SOC_STM32F373XC=y - # Enable MPU CONFIG_ARM_MPU=y @@ -15,6 +9,7 @@ CONFIG_HW_STACK_PROTECTION=y # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y + # enable console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y diff --git a/boards/arm/stm32373c_eval/support/openocd.cfg b/boards/st/stm32373c_eval/support/openocd.cfg similarity index 100% rename from boards/arm/stm32373c_eval/support/openocd.cfg rename to boards/st/stm32373c_eval/support/openocd.cfg diff --git a/boards/st/stm32f072_eval/Kconfig.stm32f072_eval b/boards/st/stm32f072_eval/Kconfig.stm32f072_eval new file mode 100644 index 00000000000000..b21c49de795064 --- /dev/null +++ b/boards/st/stm32f072_eval/Kconfig.stm32f072_eval @@ -0,0 +1,5 @@ +# Copyright (c) 2017 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F072_EVAL + select SOC_STM32F072XB diff --git a/boards/arm/stm32f072_eval/board.cmake b/boards/st/stm32f072_eval/board.cmake similarity index 100% rename from boards/arm/stm32f072_eval/board.cmake rename to boards/st/stm32f072_eval/board.cmake diff --git a/boards/st/stm32f072_eval/board.yml b/boards/st/stm32f072_eval/board.yml new file mode 100644 index 00000000000000..43e4ec82854d75 --- /dev/null +++ b/boards/st/stm32f072_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f072_eval + vendor: st + socs: + - name: stm32f072xb diff --git a/boards/arm/stm32f072_eval/doc/img/stm32f072_eval.jpg b/boards/st/stm32f072_eval/doc/img/stm32f072_eval.jpg similarity index 100% rename from boards/arm/stm32f072_eval/doc/img/stm32f072_eval.jpg rename to boards/st/stm32f072_eval/doc/img/stm32f072_eval.jpg diff --git a/boards/st/stm32f072_eval/doc/index.rst b/boards/st/stm32f072_eval/doc/index.rst new file mode 100644 index 00000000000000..998670d4cf2e90 --- /dev/null +++ b/boards/st/stm32f072_eval/doc/index.rst @@ -0,0 +1,184 @@ +.. _stm32f072_eval_board: + +ST STM32F072 Evaluation +####################### + +Overview +******** + +The STM32F072-EVAL Discovery kit features an ARM Cortex-M0 based STM32F072VBT6 MCU +with a wide range of connectivity support and configurations. +Here are some highlights of the STM32F072-EVAL board: + +- Four 5 V power supply options: power jack, ST-LINK/V2 USB connector, user USB connector, or daughter board +- Stereo audio jack, which supports a headset with microphone connected to DAC and ADC of STM32F072VBT6. +- 2G Byte (or more) SPI interface MicroSD card +- I2C compatible serial interface temperature sensor +- RF E2PROM +- RS232 and RS485 communication +- IrDA transceiver +- IR LED and IR receiver +- SWD debug support, ST-LINK/V2 embedded +- 240x320 TFT color LCD connected to SPI interface of STM32F072VBT6 +- Joystick with 4-direction control and selector +- Reset and tamper buttons +- Four color user LEDs and two LEDs as MCU low power alarm +- Extension connector for daughter board or wrapping board +- MCU voltage choice: fixed 3.3 V or adjustable from 1.65 V to 3.6 V +- USB full-speed connector +- Touch sensing buttons +- RTC with backup battery +- CAN2.0A/B compliant connector +- Light Dependent Resistor (LDR) +- Potentiometer +- Two HDMI connectors with DDC and CEC +- Smart Card slot +- Motor control connector + + +.. image:: img/stm32f072_eval.jpg + :align: center + :alt: STM32F072-EVAL + +Hardware +******** + +STM32F072-EVAL Discovery kit provides the following hardware components: + +- STM32F072VBT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M0 CPU +- 48 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 128 KB Flash +- 16 KB SRAM with HW parity +- GPIO with external interrupt capability +- one 12-bit ADC with 16 channels +- one 12-bit D/A converters with 2 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (8) +- Watchdog Timers (2) +- USART (4) +- I2C (2) +- SPI (2) +- CAN +- USB 2.0 OTG FS with on-chip PHY +- CRC calculation unit +- DMA Controller +- HDMI CEC Controller +- 24 capacitive sensing channels for touchkey, linear, and rotary touch sensors +- Up to 87 fast I/Os: 68 I/Os with 5V tolerant capability and 19 with independent supply + +More information about STM32F072VB can be found here: + - `STM32F072VB on www.st.com`_ + - `STM32F072 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f072_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f072_eval/stm32f072_eval_defconfig` + + +Pin Mapping +=========== + +STM32F072-EVAL Discovery kit has 6 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to STM32F072-EVAL board User Manual. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- TAMPER_PB : PC13 +- JOYSTICK_RIGHT_PB : PE3 +- JOYSTICK_LEFT_PB : PF2 +- JOYSTICK_UP_PB : PF9 +- JOYSTICK_DOWN_PB : PF10 +- JOYSTICK_SEL_PB : PA0 +- LD1 : PD8 +- LD2 : PD9 +- LD3 : PD10 +- LD4 : PD11 + +System Clock +============ + +STM32F072-EVAL System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 48MHz, +driven by an 8MHz high speed internal clock. + +Serial Port +=========== + +STM32F072-EVAL Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f072_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F072-EVAL Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F072-EVAL +------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f072_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f072_eval + :maybe-skip-config: + :goals: debug + + +.. _STM32F072VB on www.st.com: + https://www.st.com/en/microcontrollers/stm32f072vb.html + +.. _STM32F072 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf diff --git a/boards/arm/stm32f072_eval/stm32f072_eval.dts b/boards/st/stm32f072_eval/stm32f072_eval.dts similarity index 100% rename from boards/arm/stm32f072_eval/stm32f072_eval.dts rename to boards/st/stm32f072_eval/stm32f072_eval.dts diff --git a/boards/arm/stm32f072_eval/stm32f072_eval.yaml b/boards/st/stm32f072_eval/stm32f072_eval.yaml similarity index 100% rename from boards/arm/stm32f072_eval/stm32f072_eval.yaml rename to boards/st/stm32f072_eval/stm32f072_eval.yaml diff --git a/boards/st/stm32f072_eval/stm32f072_eval_defconfig b/boards/st/stm32f072_eval/stm32f072_eval_defconfig new file mode 100644 index 00000000000000..06e8a32bb1f031 --- /dev/null +++ b/boards/st/stm32f072_eval/stm32f072_eval_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f072_eval/support/openocd.cfg b/boards/st/stm32f072_eval/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f072_eval/support/openocd.cfg rename to boards/st/stm32f072_eval/support/openocd.cfg diff --git a/boards/st/stm32f072b_disco/Kconfig.defconfig b/boards/st/stm32f072b_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..06d17064665f33 --- /dev/null +++ b/boards/st/stm32f072b_disco/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STM32F072B-DISCO board configuration + +# Copyright (c) 2017 Clage GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F072B_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_STM32F072B_DISCO diff --git a/boards/st/stm32f072b_disco/Kconfig.stm32f072b_disco b/boards/st/stm32f072b_disco/Kconfig.stm32f072b_disco new file mode 100644 index 00000000000000..817caf5d7c4f24 --- /dev/null +++ b/boards/st/stm32f072b_disco/Kconfig.stm32f072b_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Clage GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F072B_DISCO + select SOC_STM32F072XB diff --git a/boards/arm/stm32f072b_disco/board.cmake b/boards/st/stm32f072b_disco/board.cmake similarity index 100% rename from boards/arm/stm32f072b_disco/board.cmake rename to boards/st/stm32f072b_disco/board.cmake diff --git a/boards/st/stm32f072b_disco/board.yml b/boards/st/stm32f072b_disco/board.yml new file mode 100644 index 00000000000000..ca3e636655f509 --- /dev/null +++ b/boards/st/stm32f072b_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f072b_disco + vendor: st + socs: + - name: stm32f072xb diff --git a/boards/arm/stm32f072b_disco/doc/img/stm32f072b_disco.jpg b/boards/st/stm32f072b_disco/doc/img/stm32f072b_disco.jpg similarity index 100% rename from boards/arm/stm32f072b_disco/doc/img/stm32f072b_disco.jpg rename to boards/st/stm32f072b_disco/doc/img/stm32f072b_disco.jpg diff --git a/boards/st/stm32f072b_disco/doc/index.rst b/boards/st/stm32f072b_disco/doc/index.rst new file mode 100644 index 00000000000000..d09a8fc47dfafb --- /dev/null +++ b/boards/st/stm32f072b_disco/doc/index.rst @@ -0,0 +1,218 @@ +.. _stm32f072b_disco_board: + +ST STM32F072B Discovery +####################### + +Overview +******** + +The STM32F072B-DISCO Discovery kit features an ARM Cortex-M0 based STM32F072RB +MCU with everything required for beginners and experienced users to get +started quickly. Here are some highlights of the STM32F072B-DISCO board: + +- STM32 microcontroller in LQFP64 package +- Extension header for LQFP64 I/Os for a quick connection to the prototyping + board and easy probing +- On-board ST-LINK/V2, debugger/programmer with SWD connector +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V + +- Six LEDs: + + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power on + - Four user LEDs: LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) + +- Two push-buttons: USER and RESET +- USB USER with Mini-B connector +- L3GD20, ST MEMS motion sensor, 3-axis digital output gyroscope +- One linear touch sensor or four touch keys +- RF EEprom daughter board connector + +.. image:: img/stm32f072b_disco.jpg + :align: center + :alt: STM32F072B-DISCO + +More information about the board can be found at the +`STM32F072B-DISCO website`_. + +Hardware +******** + +STM32F072B-DISCO Discovery kit provides the following hardware components: + +- STM32F072RBTT6 in LQFP64 package +- ARM |reg| 32-bit Cortex |reg| -M0 CPU +- 48 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 128 KB Flash +- 16 KB SRAM +- GPIO with external interrupt capability +- 12-bit ADC with 39 channels +- 12-bit D/A converters +- RTC +- General Purpose Timers (12) +- USART/UART (4) +- I2C (2) +- SPI (2) +- CAN +- USB 2.0 full speed interface +- DMA Controller +- 24 capacitive sensing channels for touchkey, linear and rotary touch sensors + +More information about STM32F072RB can be found here: + - `STM32F072RB on www.st.com`_ + - `STM32F072xB reference manual`_ + +Supported Features +================== + +The Zephyr stm32f072b_disco board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c controller | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | SPI controller | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f072b_disco/stm32f072b_disco_defconfig` + + +Pin Mapping +=========== + +STM32F072B-DISCO Discovery kit has 6 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32F072B-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- I2C1_SCL : PB8 +- I2C1_SDA : PB9 +- I2C2_SCL : PB10 +- I2C2_SDA : PB11 +- SPI1_SCK : PB3 +- SPI1_MISO : PB4 +- SPI1_MOSI : PB5 +- USER_PB : PA0 +- LD3 : PC6 +- LD4 : PC8 +- LD5 : PC9 +- LD6 : PC7 +- CAN_RX : PB8 +- CAN_TX : PB9 + +System Clock +============ + +STM32F072B-DISCO System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default System clock is driven +by PLL clock at 72 MHz, driven by internal 8 MHz oscillator. + +Serial Port +=========== + +STM32F072B-DISCO Discovery kit has up to 4 UARTs. The Zephyr console output +is assigned to UART 1. Default settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f072b_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + + +Flashing an application to STM32F072B-DISCO +------------------------------------------- + +First, connect the STM32F072B-DISCO Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f072b_disco + :goals: build flash + +Run a serial host program to connect with your board. A TTL(3.3V) serial +adapter is required. + +.. code-block:: console + + $ minicom -D /dev/ + +Replace with the port where the serial adapter can be found. +For example, under Linux, /dev/ttyUSB0. + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f072b_disco + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32F072B-DISCO website: + https://www.st.com/en/evaluation-tools/32f072bdiscovery.html + + +.. _STM32F072B-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00099401.pdf + +.. _STM32F072RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32f072rb.html + +.. _STM32F072xB reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _SK Pang CAN breakout board: + https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-5v-logic diff --git a/boards/arm/stm32f072b_disco/stm32f072b_disco.dts b/boards/st/stm32f072b_disco/stm32f072b_disco.dts similarity index 100% rename from boards/arm/stm32f072b_disco/stm32f072b_disco.dts rename to boards/st/stm32f072b_disco/stm32f072b_disco.dts diff --git a/boards/arm/stm32f072b_disco/stm32f072b_disco.yaml b/boards/st/stm32f072b_disco/stm32f072b_disco.yaml similarity index 100% rename from boards/arm/stm32f072b_disco/stm32f072b_disco.yaml rename to boards/st/stm32f072b_disco/stm32f072b_disco.yaml diff --git a/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig b/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig new file mode 100644 index 00000000000000..06e8a32bb1f031 --- /dev/null +++ b/boards/st/stm32f072b_disco/stm32f072b_disco_defconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Serial Drivers +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# GPIO Controller +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32f072b_disco/support/openocd.cfg b/boards/st/stm32f072b_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f072b_disco/support/openocd.cfg rename to boards/st/stm32f072b_disco/support/openocd.cfg diff --git a/boards/st/stm32f0_disco/Kconfig.stm32f0_disco b/boards/st/stm32f0_disco/Kconfig.stm32f0_disco new file mode 100644 index 00000000000000..f3ae1b0177282f --- /dev/null +++ b/boards/st/stm32f0_disco/Kconfig.stm32f0_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Nathan Tsoi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F0_DISCO + select SOC_STM32F051X8 diff --git a/boards/arm/stm32f0_disco/board.cmake b/boards/st/stm32f0_disco/board.cmake similarity index 100% rename from boards/arm/stm32f0_disco/board.cmake rename to boards/st/stm32f0_disco/board.cmake diff --git a/boards/st/stm32f0_disco/board.yml b/boards/st/stm32f0_disco/board.yml new file mode 100644 index 00000000000000..a195ae98ae7d64 --- /dev/null +++ b/boards/st/stm32f0_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f0_disco + vendor: st + socs: + - name: stm32f051x8 diff --git a/boards/arm/stm32f0_disco/doc/img/stm32f0_disco.jpg b/boards/st/stm32f0_disco/doc/img/stm32f0_disco.jpg similarity index 100% rename from boards/arm/stm32f0_disco/doc/img/stm32f0_disco.jpg rename to boards/st/stm32f0_disco/doc/img/stm32f0_disco.jpg diff --git a/boards/st/stm32f0_disco/doc/index.rst b/boards/st/stm32f0_disco/doc/index.rst new file mode 100644 index 00000000000000..3947600d8370ff --- /dev/null +++ b/boards/st/stm32f0_disco/doc/index.rst @@ -0,0 +1,143 @@ +.. _stm32f0_disco_board: + +ST STM32F0 Discovery +#################### + +Overview +******** + +The STM32F0 Discovery development board uses an STM32F051R8T6 MCU and +integrates the ST-LINK/V2-1 debugger and programmer. It also comes with a +comprehensive STM32 software HAL library and various packaged software +examples. + +.. image:: img/stm32f0_disco.jpg + :align: center + :alt: STM32F0DISCOVERY + +More information about the board can be found at the `STM32F0DISCOVERY website`_. + +Hardware +******** + +The STM32 Discovery board features: + +- STM32F051R8T6 microcontroller featuring 64 KB Flash memory, 8 KB RAM in an + LQFP64 package +- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone + ST-LINK/V2 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- Four LEDs: + + - LD1 (red) for 3.3 V power on + - LD2 (red/green) for USB communication + - LD3 (green) for PC9 output + - LD4 (blue) for PC8 output +- Two push buttons (user and reset) +- Extension header for all LQFP64 I/Os for quick connection to prototyping board + and easy probing +- An additional board is provided which can be connected to the extension + connector for even easier prototyping and probing. +- Comprehensive free software including a variety of examples, part of + STM32CubeF0 package or STSW-STM32049 for legacy Standard Libraries usage + +More information about STM32F051R8 can be found in the `STM32F0x8 reference manual`_. + +Supported Features +================== + +The Zephyr stm32f0_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f0_disco/stm32f0_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 + +For more details please refer to `STM32F0DISCOVERY board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32f0_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F0DISCOVERY board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to Nucleo F030R8 +---------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f0_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f0_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32F0DISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32f0discovery.html + +.. _STM32F0x8 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031936.pdf + +.. _STM32F0DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00050135.pdf diff --git a/boards/arm/stm32f0_disco/stm32f0_disco.dts b/boards/st/stm32f0_disco/stm32f0_disco.dts similarity index 100% rename from boards/arm/stm32f0_disco/stm32f0_disco.dts rename to boards/st/stm32f0_disco/stm32f0_disco.dts diff --git a/boards/arm/stm32f0_disco/stm32f0_disco.yaml b/boards/st/stm32f0_disco/stm32f0_disco.yaml similarity index 100% rename from boards/arm/stm32f0_disco/stm32f0_disco.yaml rename to boards/st/stm32f0_disco/stm32f0_disco.yaml diff --git a/boards/arm/stm32f0_disco/stm32f0_disco_defconfig b/boards/st/stm32f0_disco/stm32f0_disco_defconfig similarity index 80% rename from boards/arm/stm32f0_disco/stm32f0_disco_defconfig rename to boards/st/stm32f0_disco/stm32f0_disco_defconfig index f1fd239fa3b29d..18ac599df259a0 100644 --- a/boards/arm/stm32f0_disco/stm32f0_disco_defconfig +++ b/boards/st/stm32f0_disco/stm32f0_disco_defconfig @@ -1,11 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32F0X=y - -# Platform Configuration -CONFIG_SOC_STM32F051X8=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/arm/stm32f0_disco/support/openocd.cfg b/boards/st/stm32f0_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f0_disco/support/openocd.cfg rename to boards/st/stm32f0_disco/support/openocd.cfg diff --git a/boards/st/stm32f103_mini/Kconfig.stm32f103_mini b/boards/st/stm32f103_mini/Kconfig.stm32f103_mini new file mode 100644 index 00000000000000..7a9d990870b6d5 --- /dev/null +++ b/boards/st/stm32f103_mini/Kconfig.stm32f103_mini @@ -0,0 +1,5 @@ +# Copyright (c) 2020 WuhanStudio +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F103_MINI + select SOC_STM32F103XE diff --git a/boards/arm/stm32f103_mini/board.cmake b/boards/st/stm32f103_mini/board.cmake similarity index 100% rename from boards/arm/stm32f103_mini/board.cmake rename to boards/st/stm32f103_mini/board.cmake diff --git a/boards/st/stm32f103_mini/board.yml b/boards/st/stm32f103_mini/board.yml new file mode 100644 index 00000000000000..4ea8f6fbb2d014 --- /dev/null +++ b/boards/st/stm32f103_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f103_mini + vendor: st + socs: + - name: stm32f103xe diff --git a/boards/arm/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg b/boards/st/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg similarity index 100% rename from boards/arm/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg rename to boards/st/stm32f103_mini/doc/img/stm32f103_mini_blue.jpg diff --git a/boards/arm/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg b/boards/st/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg similarity index 100% rename from boards/arm/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg rename to boards/st/stm32f103_mini/doc/img/stm32f103_mini_pin.jpg diff --git a/boards/arm/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg b/boards/st/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg similarity index 100% rename from boards/arm/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg rename to boards/st/stm32f103_mini/doc/img/stm32f103_mini_yellow.jpg diff --git a/boards/st/stm32f103_mini/doc/index.rst b/boards/st/stm32f103_mini/doc/index.rst new file mode 100644 index 00000000000000..63d2199e4d03ff --- /dev/null +++ b/boards/st/stm32f103_mini/doc/index.rst @@ -0,0 +1,166 @@ +.. _stm32f103_mini_board: + +STM32F103 Mini +################ + +Overview +******** + +The STM32F103_MINI board features an ARM Cortex-M3 based STM32F103RC MCU +with a wide range of connectivity support and configurations. There are +multiple version of this board like ``stm32f103_mini``. + +.. image:: img/stm32f103_mini_yellow.jpg + :align: center + :alt: STM32F103 Mini Yellow + +.. image:: img/stm32f103_mini_blue.jpg + :align: center + :alt: STM32F103 Mini Blue + +Hardware +******** +STM32F103 Mini provides the following hardware components: + +- STM32 microcontroller in QFP64 package + +- Flexible board power supply: + + - USB VBUS or external source (3.3V, 5V, 7 - 12V) + - Power management access point + +- Two LEDs: + + - User LED (LD1), power LED (LD2) + +- USB re-enumeration capability: + + - Mass storage + +More information about STM32F103RC can be found here: + +- `STM32F103 reference manual`_ +- `STM32F103 data sheet`_ + +Supported Features +================== + +The Zephyr stm32f103_mini board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | rtc | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | rtc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f103_mini/stm32f103_mini_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Board connectors: +----------------- +.. image:: img/stm32f103_mini_pin.jpg + :align: center + :alt: Nucleo F103RB connectors + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX: PA9/PA10 +- UART_2 TX/RX: PA2/PA3 (ST-Link Virtual COM Port) +- SPI1 NSS/SCK/MISO/MOSI: PA4/PA5/PA6/PA7 +- SPI2 NSS/SCK/MISO/MOSI: PB12/PB13/PB14/PB15 +- I2C1 SDA/SCL: PB9/PB8 +- PWM1_CH1: PA8 +- USER_PB: PC13 +- LD1: PA5 +- USB_DC DM/DP: PA11/PA12 + +System Clock +------------ + +The on-board 8MHz crystal is used to produce a 72MHz system clock with PLL. + +Programming and Debugging +************************* + +Applications for the ``stm32f103_mini`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +There are 2 main entry points for flashing STM32F1X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing an application to stm32f103 mini +----------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f103_mini + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f103_mini + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32F103 reference manual: + https://www.st.com/resource/en/reference_manual/cd00171190.pdf + +.. _STM32F103 data sheet: + https://www.st.com/resource/en/datasheet/stm32f103rc.pdf diff --git a/boards/arm/stm32f103_mini/stm32f103_mini.dts b/boards/st/stm32f103_mini/stm32f103_mini.dts similarity index 100% rename from boards/arm/stm32f103_mini/stm32f103_mini.dts rename to boards/st/stm32f103_mini/stm32f103_mini.dts diff --git a/boards/arm/stm32f103_mini/stm32f103_mini.yaml b/boards/st/stm32f103_mini/stm32f103_mini.yaml similarity index 100% rename from boards/arm/stm32f103_mini/stm32f103_mini.yaml rename to boards/st/stm32f103_mini/stm32f103_mini.yaml diff --git a/boards/arm/stm32f103_mini/stm32f103_mini_defconfig b/boards/st/stm32f103_mini/stm32f103_mini_defconfig similarity index 81% rename from boards/arm/stm32f103_mini/stm32f103_mini_defconfig rename to boards/st/stm32f103_mini/stm32f103_mini_defconfig index 765fc062bd7db7..9fd4400ac206eb 100644 --- a/boards/arm/stm32f103_mini/stm32f103_mini_defconfig +++ b/boards/st/stm32f103_mini/stm32f103_mini_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XE=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/arm/stm32f103_mini/support/openocd.cfg b/boards/st/stm32f103_mini/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f103_mini/support/openocd.cfg rename to boards/st/stm32f103_mini/support/openocd.cfg diff --git a/boards/st/stm32f3_disco/Kconfig.stm32f3_disco b/boards/st/stm32f3_disco/Kconfig.stm32f3_disco new file mode 100644 index 00000000000000..0bddbf557190f1 --- /dev/null +++ b/boards/st/stm32f3_disco/Kconfig.stm32f3_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F3_DISCO + select SOC_STM32F303XC diff --git a/boards/arm/stm32f3_disco/board.cmake b/boards/st/stm32f3_disco/board.cmake similarity index 100% rename from boards/arm/stm32f3_disco/board.cmake rename to boards/st/stm32f3_disco/board.cmake diff --git a/boards/st/stm32f3_disco/board.yml b/boards/st/stm32f3_disco/board.yml new file mode 100644 index 00000000000000..ae48f138fa5d83 --- /dev/null +++ b/boards/st/stm32f3_disco/board.yml @@ -0,0 +1,11 @@ +board: + name: stm32f3_disco + vendor: st + revision: + format: letter + default: "B" + revisions: + - name: "B" + - name: "E" + socs: + - name: stm32f303xc diff --git a/boards/arm/stm32f3_disco/doc/img/stm32f3_disco.jpg b/boards/st/stm32f3_disco/doc/img/stm32f3_disco.jpg similarity index 100% rename from boards/arm/stm32f3_disco/doc/img/stm32f3_disco.jpg rename to boards/st/stm32f3_disco/doc/img/stm32f3_disco.jpg diff --git a/boards/st/stm32f3_disco/doc/index.rst b/boards/st/stm32f3_disco/doc/index.rst new file mode 100644 index 00000000000000..8862d754fbbd1d --- /dev/null +++ b/boards/st/stm32f3_disco/doc/index.rst @@ -0,0 +1,280 @@ +.. _stm32f3_disco_board: + +ST STM32F3 Discovery +#################### + +Overview +******** + +The STM32F3DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F303VC +MCU with everything required for beginners and experienced users to get +started quickly. Here are some highlights of the STM32F3DISCOVERY board: + +- STM32 microcontroller in LQFP100 package +- Extension header for all LQFP100 I/Os for quick connection to prototyping + board and easy probing +- On-board, ST-LINK/V2 for PCB version A or B or ST-LINK/V2-B for PCB version + C and newer, debugger/programmer with SWD connector +- Board power supply: through USB bus or from an external 3 V or 5 V supply + voltage +- External application power supply: 3 V and 5 V + +- Ten LEDs: + + - 3.3 V power on (LD1) + - USB communication (LD2) + - Eight user LEDs: red (LD3/LD10), blue (LD4/LD9), orange (LD5/LD9) + and green (LD6/LD7) + +- Two push-buttons: USER and RESET +- USB USER with Mini-B connector +- L3GD20 or I3G4250D, ST MEMS motion sensor, 3-axis digital output gyroscope +- LSM303DLHC or LSM303AGR, ST MEMS system-in-package featuring a 3D digital linear + acceleration sensor and a 3D digital magnetic sensor; + +.. HINT:: + Recent PCB revisions (E and newer) are shipped with I3G4250D and LSM303AGR. + +.. image:: img/stm32f3_disco.jpg + :align: center + :alt: STM32F3DISCOVERY + +More information about the board can be found at the +`STM32F3DISCOVERY website`_. + +Hardware +******** + +STM32F3DISCOVERY Discovery kit provides the following hardware components: + +- STM32F303VCT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 72 MHz max CPU frequency +- VDD from 2.0 V to 3.6 V +- 256 KB Flash +- 40 KB SRAM +- Routine booster: 8 Kbytes of SRAM on instruction and data bus +- GPIO with external interrupt capability +- 4x12-bit ADC with 39 channels +- 2x12-bit D/A converters +- RTC +- General Purpose Timers (13) +- USART/UART (5) +- I2C (2) +- SPI (3) +- CAN +- USB 2.0 full speed interface +- Infrared transmitter +- DMA Controller + +More information about STM32F303VC can be found here: + - `STM32F303VC on www.st.com`_ + - `STM32F303xC reference manual`_ + +Supported Features +================== + +The Zephyr stm32f3_disco board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN | ++-----------+------------+-------------------------------------+ +| IWDG | on-chip | Independent WatchDoG | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| die-temp | on-chip | die temperature sensor | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f3_disco/stm32f3_disco_defconfig` + + +Pin Mapping +=========== + +STM32F3DISCOVERY Discovery kit has 6 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `STM32F3DISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PC4 +- UART_1_RX : PC5 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- UART_4_TX : PC10 +- UART_4_RX : PC11 +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PA9 +- I2C2_SDA : PA10 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- CAN1_RX : PD0 +- CAN1_TX : PD1 +- USB_DM : PA11 +- USB_DP : PA12 +- USER_PB : PA0 +- LD3 : PE9 +- LD4 : PE8 +- LD5 : PE10 +- LD6 : PE15 +- LD7 : PE11 +- LD8 : PE14 +- LD9 : PE12 +- LD10 : PE13 +- PWM : PA8 +- ADC1 : PA0 +- DAC1 : PA4 + +System Clock +============ + +STM32F3DISCOVERY System Clock could be driven by internal or external +oscillator, as well as main PLL clock. By default System clock is driven +by PLL clock at 72 MHz, driven by 8 MHz MCO from the ST Link. + +Serial Port +=========== + +STM32F3DISCOVERY Discovery kit has up to 5 UARTs. The Zephyr console output +is assigned to UART1. Default settings are 115200 8N1. + +I2C +=== + +STM32F3DISCOVERY has up to 2 I2Cs. I2C1 is connected to the LSM303DLHC and is +an ultra-compact low-power system-in-package featuring a 3D digital linear +acceleration sensor and a 3D digital magnetic sensor. + +USB +=== +STM32F3DISCOVERY has a USB 2.0 full-speed device interface available through +its mini USB connector (USB USER). + +CAN +=== +The STM32F3DISCOVERY does not have an onboard CAN transceiver. In +order to use the CAN bus on the this board, an external CAN bus +transceiver must be connected to ``PD0`` (``CAN1_RX``) and ``PD1`` +(``CAN1_TX``). + +Programming and Debugging +************************* + +Flashing +======== + +STM32F3DISCOVERY Discovery kit includes a ST-LINK/V2 or ST-LINK/V2-B embedded +debug tool interface. + +Applications for the ``stm32f3_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing an application to STM32F3DISCOVERY +------------------------------------------- + +First, connect the STM32F3DISCOVERY Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco + :goals: build flash + + +In case you are using a recent PCB revision (E or newer), you have to use an +adapted board definition: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco@E + :goals: build flash + +Run a serial host program to connect with your board. For PCB version A or B a +TTL(3.3V) serial adapter is required. For PCB version C and newer a Virtual Com +Port (VCP) is available on the USB ST-LINK port. + +.. code-block:: console + + $ minicom -D /dev/ + +Replace with the port where the STM32F3DISCOVERY board can be +found. For example, under Linux, /dev/ttyUSB0. + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco + :goals: debug + +Again you have to use the adapted command for newer PCB revisions (E and newer): + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f3_disco@E + :goals: debug + +.. _STM32F3DISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32f3discovery.html + +.. _STM32F3DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00063382.pdf + +.. _STM32F303VC on www.st.com: + https://www.st.com/en/microcontrollers/stm32f303vc.html + +.. _STM32F303xC reference manual: + https://www.st.com/resource/en/reference_manual/dm00043574.pdf diff --git a/boards/arm/stm32f3_disco/stm32f3_disco.dts b/boards/st/stm32f3_disco/stm32f3_disco.dts similarity index 100% rename from boards/arm/stm32f3_disco/stm32f3_disco.dts rename to boards/st/stm32f3_disco/stm32f3_disco.dts diff --git a/boards/st/stm32f3_disco/stm32f3_disco_B.yaml b/boards/st/stm32f3_disco/stm32f3_disco_B.yaml new file mode 100644 index 00000000000000..1c87cb7fd36bfb --- /dev/null +++ b/boards/st/stm32f3_disco/stm32f3_disco_B.yaml @@ -0,0 +1,24 @@ +identifier: stm32f3_disco +name: ST STM32F3 Discovery rev B +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 40 +supported: + - gpio + - i2c + - counter + - spi + - watchdog + - usb_device + - lsm303dlhc + - nvs + - can + - pwm + - adc + - dac + - dma +vendor: st diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_defconfig b/boards/st/stm32f3_disco/stm32f3_disco_defconfig similarity index 85% rename from boards/arm/stm32f3_disco/stm32f3_disco_defconfig rename to boards/st/stm32f3_disco/stm32f3_disco_defconfig index fae0909e8403f5..ed90d066c5a3f3 100644 --- a/boards/arm/stm32f3_disco/stm32f3_disco_defconfig +++ b/boards/st/stm32f3_disco/stm32f3_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F3X=y -CONFIG_SOC_STM32F303XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f3_disco/stm32f3_disco_E.overlay b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.overlay similarity index 100% rename from boards/arm/stm32f3_disco/stm32f3_disco_E.overlay rename to boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.overlay diff --git a/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml new file mode 100644 index 00000000000000..13e6b0bf1431fb --- /dev/null +++ b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml @@ -0,0 +1,23 @@ +identifier: stm32f3_disco@E +name: ST STM32F3 Discovery rev E +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 40 +supported: + - gpio + - i2c + - counter + - spi + - watchdog + - usb_device + - i3g4250d + - nvs + - can + - pwm + - adc + - dac +vendor: st diff --git a/boards/arm/stm32f3_disco/support/openocd.cfg b/boards/st/stm32f3_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f3_disco/support/openocd.cfg rename to boards/st/stm32f3_disco/support/openocd.cfg diff --git a/boards/st/stm32f411e_disco/Kconfig.stm32f411e_disco b/boards/st/stm32f411e_disco/Kconfig.stm32f411e_disco new file mode 100644 index 00000000000000..8ef325c580b586 --- /dev/null +++ b/boards/st/stm32f411e_disco/Kconfig.stm32f411e_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Fenix Engineering Solutions +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F411E_DISCO + select SOC_STM32F411XE diff --git a/boards/arm/stm32f411e_disco/board.cmake b/boards/st/stm32f411e_disco/board.cmake similarity index 100% rename from boards/arm/stm32f411e_disco/board.cmake rename to boards/st/stm32f411e_disco/board.cmake diff --git a/boards/st/stm32f411e_disco/board.yml b/boards/st/stm32f411e_disco/board.yml new file mode 100644 index 00000000000000..f42b1ada4a44e5 --- /dev/null +++ b/boards/st/stm32f411e_disco/board.yml @@ -0,0 +1,11 @@ +board: + name: stm32f411e_disco + vendor: st + revision: + format: letter + default: "D" + revisions: + - name: "B" + - name: "D" + socs: + - name: stm32f411xe diff --git a/boards/arm/stm32f411e_disco/doc/img/stm32f411e_disco.jpg b/boards/st/stm32f411e_disco/doc/img/stm32f411e_disco.jpg similarity index 100% rename from boards/arm/stm32f411e_disco/doc/img/stm32f411e_disco.jpg rename to boards/st/stm32f411e_disco/doc/img/stm32f411e_disco.jpg diff --git a/boards/st/stm32f411e_disco/doc/index.rst b/boards/st/stm32f411e_disco/doc/index.rst new file mode 100644 index 00000000000000..a2e6f02619b7d0 --- /dev/null +++ b/boards/st/stm32f411e_disco/doc/index.rst @@ -0,0 +1,188 @@ +.. _stm32f411e_disco_board: + +ST STM32F411E Discovery +####################### + +Overview +******** + +The STM32F411E Discovery kit features an ARM Cortex-M4 based STM32F411VE MCU +with a wide range of connectivity support and configurations. +Here are some highlights of the STM32F411E-DISCO board: + +- STM32F411VET6 microcontroller featuring 512 KB of Flash memory, 128 KB of RAM in an LQFP100 package +- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone STLINK/V2 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- L3GD20(rev B) or I3G4250D(rev D): ST MEMS motion sensor, 3-axis digital output gyroscope. +- LSM303DLHC(rev B) or LSM303AGR(rev D): ST MEMS system-in-package featuring a 3D digital linear acceleration sensor and a 3D digital magnetic sensor. +- MP45DT02(rev B) or IMP34DT05(rev D), ST MEMS audio sensor, omnidirectional digital microphone +- CS43L22, audio DAC with integrated class D speaker driver +- Eight LEDs: + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power on + - Four user LEDs: + LD3 (orange), LD4 (green), LD5 (red) and LD6 (blue) + - Two USB OTG LEDs: + LD7 (green) VBus and LD8 (red) over-current +- Two pushbuttons (user and reset) +- USB OTG with micro-AB connector +- Extension header for LQFP100 I/Os for a quick connection to the prototyping board and an easy probing + +.. image:: img/stm32f411e_disco.jpg + :align: center + :alt: STM32F411E-DISCO + +More information about the board can be found at the `32F411EDISCOVERY website`_. + +Hardware +******** + +STM32F411E-DISCO Discovery kit provides the following hardware components: + +- STM32F411VET6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +More information about STM32F411VE can be found here: + - `STM32F411VE website`_ + - `STM32F411x reference manual`_ + +Supported Features +================== + +The Zephyr stm32f411e_disco board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f411e_disco/stm32f411e_disco_defconfig` + + +Pin Mapping +=========== + +STM32F411E-DISCO Discovery kit has 5 GPIO controllers. These controllers are +responsible for pin muxing, input/output, pull-up, etc. + +For more details please refer to `32F411EDISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- LD3 : PD13 (PWM4 CH2) +- LD4 : PD12 (PWM4 CH1) +- LD5 : PD14 (PWM4 CH3) +- LD6 : PD15 (PWM4 CH4) + +System Clock +============ + +STM32F411E-DISCO System Clock could be driven by an internal or external +oscillator, as well as the main PLL clock. By default, the System clock is +driven by the PLL clock at 100MHz, driven by the internal oscillator. + +Serial Port +=========== + +The STM32F411G Discovery kit has up to 3 UARTs. The Zephyr console output is +assigned to UART2. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32f411e_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F411E-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool +interface. This interface is supported by the openocd version included in +Zephyr SDK. + +Flashing an application to STM32F411E-DISCO +------------------------------------------- + +Connect the STM32F411E-DISCO Discovery kit to your host computer using the +USB port. Then build and flash an application. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f411e_disco + :goals: build flash + +In case you are using PCB revision B, you have to use an +adapted board definition as the default PCB rev here is D: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f411e_disco@B + :goals: build flash + +You should see the orange led (LD3) blinking every second. + +Debugging +========= + +You can debug applications in the usual way. Here is an example for +the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f411e_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _32F411EDISCOVERY website: + https://www.st.com/en/evaluation-tools/32f411ediscovery.html + +.. _32F411EDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00148985.pdf + +.. _STM32F411VE website: + https://www.st.com/en/microcontrollers/stm32f411ve.html + +.. _STM32F411x reference manual: + https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco.dts b/boards/st/stm32f411e_disco/stm32f411e_disco.dts similarity index 100% rename from boards/arm/stm32f411e_disco/stm32f411e_disco.dts rename to boards/st/stm32f411e_disco/stm32f411e_disco.dts diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig b/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig similarity index 86% rename from boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig rename to boards/st/stm32f411e_disco/stm32f411e_disco_defconfig index 30784f3514d63d..67896885dac614 100644 --- a/boards/arm/stm32f411e_disco/stm32f411e_disco_defconfig +++ b/boards/st/stm32f411e_disco/stm32f411e_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco_B.overlay b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay similarity index 100% rename from boards/arm/stm32f411e_disco/stm32f411e_disco_B.overlay rename to boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.overlay diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml new file mode 100644 index 00000000000000..05f3c979f7f0c0 --- /dev/null +++ b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml @@ -0,0 +1,11 @@ +identifier: stm32f411e_disco@B +name: ST STM32F411E Discovery +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter +vendor: st diff --git a/boards/arm/stm32f411e_disco/stm32f411e_disco.yaml b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml similarity index 100% rename from boards/arm/stm32f411e_disco/stm32f411e_disco.yaml rename to boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml diff --git a/boards/arm/stm32f411e_disco/support/openocd.cfg b/boards/st/stm32f411e_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f411e_disco/support/openocd.cfg rename to boards/st/stm32f411e_disco/support/openocd.cfg diff --git a/boards/st/stm32f412g_disco/Kconfig.stm32f412g_disco b/boards/st/stm32f412g_disco/Kconfig.stm32f412g_disco new file mode 100644 index 00000000000000..ec0581a33dfbd8 --- /dev/null +++ b/boards/st/stm32f412g_disco/Kconfig.stm32f412g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Powersoft +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F412G_DISCO + select SOC_STM32F412ZX diff --git a/boards/arm/stm32f412g_disco/arduino_r3_connector.dtsi b/boards/st/stm32f412g_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f412g_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f412g_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f412g_disco/board.cmake b/boards/st/stm32f412g_disco/board.cmake similarity index 100% rename from boards/arm/stm32f412g_disco/board.cmake rename to boards/st/stm32f412g_disco/board.cmake diff --git a/boards/st/stm32f412g_disco/board.yml b/boards/st/stm32f412g_disco/board.yml new file mode 100644 index 00000000000000..836972823ada12 --- /dev/null +++ b/boards/st/stm32f412g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f412g_disco + vendor: st + socs: + - name: stm32f412zx diff --git a/boards/arm/stm32f412g_disco/doc/img/stm32f412g_disco.jpg b/boards/st/stm32f412g_disco/doc/img/stm32f412g_disco.jpg similarity index 100% rename from boards/arm/stm32f412g_disco/doc/img/stm32f412g_disco.jpg rename to boards/st/stm32f412g_disco/doc/img/stm32f412g_disco.jpg diff --git a/boards/st/stm32f412g_disco/doc/index.rst b/boards/st/stm32f412g_disco/doc/index.rst new file mode 100644 index 00000000000000..0443d00b483212 --- /dev/null +++ b/boards/st/stm32f412g_disco/doc/index.rst @@ -0,0 +1,201 @@ +.. _stm32f412g_disco_board: + +ST STM32F412G Discovery +####################### + +Overview +******** + +The STM32F412 Discovery kit features an ARM Cortex-M4 based STM32F412ZG MCU +with a wide range of connectivity support and configurations Here are +some highlights of the STM32F412G-DISCO board: + + +- STM32F412ZGT6 microcontroller featuring 1 Mbyte of Flash memory and 256 Kbytes of RAM in an LQFP144 package +- On-board ST-LINK/V2-1 SWD debugger supporting USB re-enumeration capability: + + - USB virtual COM port + - mass storage + - debug port + +- 1.54 inch 240x240 pixel TFT color LCD with parallel interface and capacitive touchscreen +- I2S Audio CODEC, with a stereo headset jack, including analog microphone input and a loudspeaker output +- Stereo digital MEMS microphones +- MicroSD card connector extension +- I2C extension connector +- 128 Mbit Quad-SPI Nor Flash +- Reset button and Joystick +- Four color user LEDs. +- USB OTG FS with Micro-AB connector +- Four power supply options: + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino* connectors + - + 5 V from Arduino* connectors + +- Two power supplies for MCU: 2.0 V and 3.3 V +- Compatible with Arduino(tm) Uno revision 3 connectors +- Extension connector for direct access to various features of STM32F412ZGT6 MCU +- Comprehensive free software including a variety of examples, part of STM32Cube package + +.. image:: img/stm32f412g_disco.jpg + :align: center + :alt: STM32F412G-DISCO + +More information about the board can be found at the `32F412GDISCOVERY website`_. + +Hardware +******** + +STM32F469I-DISCO Discovery kit provides the following hardware components: + +- STM32F412ZGT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 1 MB Flash +- 256 KB SRAM +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- 1x12-bit ADC with 16 channels +- RTC +- Advanced-control Timer +- General Purpose Timers (12) +- Watchdog Timers (2) +- USART/UART (4) +- I2C (4) +- SPI (5) +- SDIO +- 2xCAN +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F412ZG can be found here: + - `STM32F412ZG on www.st.com`_ + - `STM32F412 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f412g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f412g_disco/stm32f412g_disco_defconfig` + + +Pin Mapping +=========== + +STM32F412G-DISCO Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F412GDISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- LD1 : PE0 +- LD2 : PE1 +- LD3 : PE2 +- LD4 : PE3 + +System Clock +============ + +STM32F412G-DISCO System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 100MHz, +driven internal oscillator. + +Serial Port +=========== + +The STM32F412G Discovery kit has up to 4 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32f412g_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F412G-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F412G-DISCO +------------------------------------------- + +Connect the STM32F412G-DISCO Discovery kit to your host computer using +the USB port, then run a serial host program to connect with your +board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f412g_disco + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f412g_disco + :maybe-skip-config: + :goals: debug + +.. _32F412GDISCOVERY website: + https://www.st.com/en/evaluation-tools/32f412gdiscovery.html + +.. _32F412GDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00275919.pdf + +.. _STM32F412ZG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f412zg.html + +.. _STM32F412 reference manual: + https://www.st.com/resource/en/reference_manual/dm00180369.pdf diff --git a/boards/arm/stm32f412g_disco/stm32f412g_disco.dts b/boards/st/stm32f412g_disco/stm32f412g_disco.dts similarity index 100% rename from boards/arm/stm32f412g_disco/stm32f412g_disco.dts rename to boards/st/stm32f412g_disco/stm32f412g_disco.dts diff --git a/boards/arm/stm32f412g_disco/stm32f412g_disco.yaml b/boards/st/stm32f412g_disco/stm32f412g_disco.yaml similarity index 100% rename from boards/arm/stm32f412g_disco/stm32f412g_disco.yaml rename to boards/st/stm32f412g_disco/stm32f412g_disco.yaml diff --git a/boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig b/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig similarity index 85% rename from boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig rename to boards/st/stm32f412g_disco/stm32f412g_disco_defconfig index 1992a4de58c964..0efcd3c8c7eb30 100644 --- a/boards/arm/stm32f412g_disco/stm32f412g_disco_defconfig +++ b/boards/st/stm32f412g_disco/stm32f412g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F412ZX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f412g_disco/support/openocd.cfg b/boards/st/stm32f412g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f412g_disco/support/openocd.cfg rename to boards/st/stm32f412g_disco/support/openocd.cfg diff --git a/boards/st/stm32f429i_disc1/Kconfig.defconfig b/boards/st/stm32f429i_disc1/Kconfig.defconfig new file mode 100644 index 00000000000000..1d783097dad4c0 --- /dev/null +++ b/boards/st/stm32f429i_disc1/Kconfig.defconfig @@ -0,0 +1,14 @@ +# STM32F4DISCOVERY board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F429I_DISC1 + +config INPUT + default y if DISPLAY + +config MEMC + default y if DISPLAY + +endif # BOARD_STM32F429I_DISC1 diff --git a/boards/st/stm32f429i_disc1/Kconfig.stm32f429i_disc1 b/boards/st/stm32f429i_disc1/Kconfig.stm32f429i_disc1 new file mode 100644 index 00000000000000..5af24073ad2edc --- /dev/null +++ b/boards/st/stm32f429i_disc1/Kconfig.stm32f429i_disc1 @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F429I_DISC1 + select SOC_STM32F429XX diff --git a/boards/arm/stm32f429i_disc1/board.cmake b/boards/st/stm32f429i_disc1/board.cmake similarity index 100% rename from boards/arm/stm32f429i_disc1/board.cmake rename to boards/st/stm32f429i_disc1/board.cmake diff --git a/boards/st/stm32f429i_disc1/board.yml b/boards/st/stm32f429i_disc1/board.yml new file mode 100644 index 00000000000000..e8e332283072bb --- /dev/null +++ b/boards/st/stm32f429i_disc1/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f429i_disc1 + vendor: st + socs: + - name: stm32f429xx diff --git a/boards/arm/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg b/boards/st/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg similarity index 100% rename from boards/arm/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg rename to boards/st/stm32f429i_disc1/doc/img/stm32f429i_disc1.jpg diff --git a/boards/st/stm32f429i_disc1/doc/index.rst b/boards/st/stm32f429i_disc1/doc/index.rst new file mode 100644 index 00000000000000..c61cfcaa739855 --- /dev/null +++ b/boards/st/stm32f429i_disc1/doc/index.rst @@ -0,0 +1,229 @@ +.. _stm32f429i_disc1_board: + +ST STM32F429I Discovery +####################### + +Overview +******** + +The STM32F429I-DISC1 Discovery kit features an ARM Cortex-M4 based STM32F429ZI MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32F429I-DISC1 board: + +- STM32 microcontroller in LQFP144 package +- Extension header for all LQFP144 I/Os for quick connection to prototyping board and easy probing +- On-board ST-LINK/V2-B debugger/programmer with SWD connector +- Flexible board power supply: + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino* compatible connectors + +- Two push-buttons: USER and RESET +- USB OTG FS with micro-AB connector +- 2.4-inch QVGA LCD with MIPI DSI interface and capacitive touch screen +- 64Mbit SDRAM +- L3GD20, ST-MEMS motion sensor 3-axis digital output gyroscope +- Six LEDs + + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power-on + - Two user LEDs: LD3 (green), LD4 (red) + - Two USB OTG LEDs: LD5 (green) VBUS and LD6 (red) OC (over-current) + +.. image:: img/stm32f429i_disc1.jpg + :align: center + :alt: STM32F429I-DISC1 + +More information about the board can be found at the `STM32F429I-DISC1 website`_. + +Hardware +******** + +The STM32F429I-DISC1 Discovery kit provides the following hardware components: + +- STM32F429ZIT6 in LQFP144 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 256+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (4/4) +- I2C (3) +- SPI (6) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F429ZI can be found here: + - `STM32F429ZI on www.st.com`_ + - `STM32F429 Reference Manual`_ + +Supported Features +================== + +The Zephyr stm32f429i_disc1 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| OTG_HS | on-chip | usbotg_hs | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig` + + +Pin Mapping +=========== + +The STM32F429I-DISC1 Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32F429I-DISC1 board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- USER_PB : PA0 +- LD3 : PG13 +- LD4 : PG12 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB9 +- I2C_2_SCL : PB10 +- I2C_2_SDA : PB11 +- I2C_3_SCL : PA8 +- I2C_3_SDA : PC9 +- SPI_5_CS : PF6 +- SPI_5_SCK : PF7 +- SPI_5_MISO : PF8 +- SPI_5_MOSI : PF9 +- OTG_HS_ID : PB12 +- OTG_HS_DM : PB14 +- OTG_HS_DP : PB15 + +System Clock +============ + +The STM32F429I-DISC1 System Clock could be driven by an internal or external oscillator, +as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 168MHz, +driven by an 8MHz high speed external clock. + +Serial Port +=========== + +The STM32F429I-DISC1 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1. +The default communication settings are 115200 8N1. + +USB Port +=========== + +The STM32F429I-DISC1 Discovery kit has a USB FS capable Micro-B port. It is connected to the on-chip +OTG_HS peripheral, but operates in FS mode only since no HS PHY is present. The board supports device +and host OTG operation, but only device mode has been tested with Zephyr at this time. + +Programming and Debugging +************************* + +Applications for the ``stm32f429i_disc1`` board configuration can be built +and flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The STM32F429I-DISC1 Discovery kit includes a ST-LINK/V2-B embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F429I-DISC1 +------------------------------------------- + +The board is configured to be flashed using west OpenOCD runner. +Alternatively, you can use `STM32CubeProgrammer`_ (after installing it) using the ``--runner`` +(or ``-r``) option: + +.. code-block:: console + + $ west flash --runner stm32cubeprogrammer + +First, connect the STM32F429I-DISC1 Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f429i_disc1 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, press the RESET button (The black one), you should see the following message: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f429i_disc1 + :goals: debug + +.. _STM32F429I-DISC1 website: + https://www.st.com/en/evaluation-tools/32f429idiscovery.html + +.. _STM32F429I-DISC1 board User Manual: + https://www.st.com/web/en/resource/technical/document/user_manual/DM00097320.pdf + +.. _STM32F429ZI on www.st.com: + https://www.st.com/en/microcontrollers/stm32f429-439.html + +.. _STM32F429 Reference Manual: + https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts b/boards/st/stm32f429i_disc1/stm32f429i_disc1.dts similarity index 100% rename from boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts rename to boards/st/stm32f429i_disc1/stm32f429i_disc1.dts diff --git a/boards/arm/stm32f429i_disc1/stm32f429i_disc1.yaml b/boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml similarity index 100% rename from boards/arm/stm32f429i_disc1/stm32f429i_disc1.yaml rename to boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml diff --git a/boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig b/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig similarity index 84% rename from boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig rename to boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig index 0e2f562dc03773..c729b83e3d0506 100644 --- a/boards/arm/stm32f429i_disc1/stm32f429i_disc1_defconfig +++ b/boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F429XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f429i_disc1/support/openocd.cfg b/boards/st/stm32f429i_disc1/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f429i_disc1/support/openocd.cfg rename to boards/st/stm32f429i_disc1/support/openocd.cfg diff --git a/boards/st/stm32f469i_disco/Kconfig.defconfig b/boards/st/stm32f469i_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..e8f2fd5b6c97fb --- /dev/null +++ b/boards/st/stm32f469i_disco/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32F469I-DISCO board configuration + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F469I_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + + +endif # BOARD_STM32F469I_DISCO diff --git a/boards/st/stm32f469i_disco/Kconfig.stm32f469i_disco b/boards/st/stm32f469i_disco/Kconfig.stm32f469i_disco new file mode 100644 index 00000000000000..e63e8858c478cf --- /dev/null +++ b/boards/st/stm32f469i_disco/Kconfig.stm32f469i_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F469I_DISCO + select SOC_STM32F469XX diff --git a/boards/arm/stm32f469i_disco/arduino_r3_connector.dtsi b/boards/st/stm32f469i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f469i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f469i_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f469i_disco/board.cmake b/boards/st/stm32f469i_disco/board.cmake similarity index 100% rename from boards/arm/stm32f469i_disco/board.cmake rename to boards/st/stm32f469i_disco/board.cmake diff --git a/boards/st/stm32f469i_disco/board.yml b/boards/st/stm32f469i_disco/board.yml new file mode 100644 index 00000000000000..2f7407bbc381d6 --- /dev/null +++ b/boards/st/stm32f469i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f469i_disco + vendor: st + socs: + - name: stm32f469xx diff --git a/boards/arm/stm32f469i_disco/doc/img/stm32f469i_disco.jpg b/boards/st/stm32f469i_disco/doc/img/stm32f469i_disco.jpg similarity index 100% rename from boards/arm/stm32f469i_disco/doc/img/stm32f469i_disco.jpg rename to boards/st/stm32f469i_disco/doc/img/stm32f469i_disco.jpg diff --git a/boards/st/stm32f469i_disco/doc/index.rst b/boards/st/stm32f469i_disco/doc/index.rst new file mode 100644 index 00000000000000..85ebec3778fbee --- /dev/null +++ b/boards/st/stm32f469i_disco/doc/index.rst @@ -0,0 +1,207 @@ +.. _stm32f469i_disco_board: + +ST STM32F469I Discovery +####################### + +Overview +******** + +The STM32F469 Discovery kit features an ARM Cortex-M4 based STM32F469NI MCU +with a wide range of connectivity support and configurations Here are +some highlights of the STM32F469I-DISCO board: + + +- STM32 microcontroller in BGA216 package +- On-board ST-LINK/V2-1 debugger/programmer, supporting USB reenumeration capability +- Flexible board power supply: + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino* compatible connectors + +- Four user LEDs +- Two push-buttons: USER and RESET +- USB OTG FS with micro-AB connector +- 4-inch 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive touch screen +- SAI Audio DAC, with a stereo headphone output jack +- Three MEMS microphones +- MicroSD card connector +- I2C extension connector +- 4Mx32bit SDRAM +- 128-Mbit Quad-SPI NOR Flash +- Expansion connectors and Arduino UNO V3 connectors + +.. image:: img/stm32f469i_disco.jpg + :align: center + :alt: STM32F469I-DISCO + +More information about the board can be found at the `32F469IDISCOVERY website`_. + +Hardware +******** + +STM32F469I-DISCO Discovery kit provides the following hardware components: + +- STM32F469NIH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 180 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 384+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- LCD TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (6) +- 1xSAI (serial audio interface) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F469NI can be found here: + - `STM32F469NI on www.st.com`_ + - `STM32F469 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f469i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| SDIO | on-chip | SD-card controller | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f469i_disco/stm32f469i_disco_defconfig` + + +Pin Mapping +=========== + +STM32F469I-DISCO Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F469IDISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PG14/PG9 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SPI2 NSS/SCK/MISO/MOSI : PH6/PD3/PB14/PB15 (Arduino SPI) +- SDIO D0/D1/D2/D3/CLK/Detect : PC8/PC9/PC10/PC11/PC12/PG2 +- USB DM : PA11 +- USB DP : PA12 +- USER_PB : PA0 +- LD1 : PG6 +- LD2 : PD4 +- LD3 : PD5 +- LD4 : PK3 + +System Clock +============ + +STM32F469I-DISCO System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 180MHz, +driven by 8MHz high speed external clock. + +Serial Port +=========== + +The STM32F469 Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART3. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32f469i_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F469I-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F469I-DISCO +------------------------------------------- + +First, connect the STM32F469I-DISCO Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f469i_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f469i_disco + :goals: debug + + +.. _32F469IDISCOVERY website: + https://www.st.com/en/evaluation-tools/32f469idiscovery.html + +.. _32F469IDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00218846.pdf + +.. _STM32F469NI on www.st.com: + https://www.st.com/en/microcontrollers/stm32f469ni.html + +.. _STM32F469 reference manual: + https://www.st.com/resource/en/reference_manual/dm00127514.pdf diff --git a/boards/arm/stm32f469i_disco/stm32f469i_disco.dts b/boards/st/stm32f469i_disco/stm32f469i_disco.dts similarity index 100% rename from boards/arm/stm32f469i_disco/stm32f469i_disco.dts rename to boards/st/stm32f469i_disco/stm32f469i_disco.dts diff --git a/boards/arm/stm32f469i_disco/stm32f469i_disco.yaml b/boards/st/stm32f469i_disco/stm32f469i_disco.yaml similarity index 100% rename from boards/arm/stm32f469i_disco/stm32f469i_disco.yaml rename to boards/st/stm32f469i_disco/stm32f469i_disco.yaml diff --git a/boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig b/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig similarity index 84% rename from boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig rename to boards/st/stm32f469i_disco/stm32f469i_disco_defconfig index 94a8f52809e7ec..c729b83e3d0506 100644 --- a/boards/arm/stm32f469i_disco/stm32f469i_disco_defconfig +++ b/boards/st/stm32f469i_disco/stm32f469i_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F469XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f469i_disco/support/openocd.cfg b/boards/st/stm32f469i_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f469i_disco/support/openocd.cfg rename to boards/st/stm32f469i_disco/support/openocd.cfg diff --git a/boards/st/stm32f4_disco/Kconfig.stm32f4_disco b/boards/st/stm32f4_disco/Kconfig.stm32f4_disco new file mode 100644 index 00000000000000..88d7525c640ab1 --- /dev/null +++ b/boards/st/stm32f4_disco/Kconfig.stm32f4_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F4_DISCO + select SOC_STM32F407XG diff --git a/boards/arm/stm32f4_disco/board.cmake b/boards/st/stm32f4_disco/board.cmake similarity index 100% rename from boards/arm/stm32f4_disco/board.cmake rename to boards/st/stm32f4_disco/board.cmake diff --git a/boards/st/stm32f4_disco/board.yml b/boards/st/stm32f4_disco/board.yml new file mode 100644 index 00000000000000..663f8613eec3b3 --- /dev/null +++ b/boards/st/stm32f4_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f4_disco + vendor: st + socs: + - name: stm32f407xx diff --git a/boards/arm/stm32f4_disco/doc/img/stm32f4_disco.jpg b/boards/st/stm32f4_disco/doc/img/stm32f4_disco.jpg similarity index 100% rename from boards/arm/stm32f4_disco/doc/img/stm32f4_disco.jpg rename to boards/st/stm32f4_disco/doc/img/stm32f4_disco.jpg diff --git a/boards/st/stm32f4_disco/doc/index.rst b/boards/st/stm32f4_disco/doc/index.rst new file mode 100644 index 00000000000000..8839759a3ab3ca --- /dev/null +++ b/boards/st/stm32f4_disco/doc/index.rst @@ -0,0 +1,213 @@ +.. _stm32f4_disco_board: + +ST STM32F4 Discovery +#################### + +Overview +******** + +The STM32F4DISCOVERY Discovery kit features an ARM Cortex-M4 based STM32F407VG MCU +with a wide range of connectivity support and configurations Here are +some highlights of the STM32F4DISCOVERY board: + + +- STM32 microcontroller in LQFP100 package +- Extension header for all LQFP100 I/Os for quick connection to prototyping board and easy probing +- On-board ST-LINK/V2 debugger/programmer with SWD connector +- Flexible board power supply: + + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- Eight LEDs: + + - USB communication (LD1) + - 3.3 V power on (LD2) + - Four user LEDs: orange (LD3), green (LD4), red (LD5), and blue (LD6) + - 2 USB OTG LEDs for VBUS (LD7) and over-current (LD8) + +- Two push-buttons: USER and RESET +- USB OTG FS with micro-AB connector +- LIS302DL or LIS3DSH ST MEMS 3-axis accelerometer +- MP45DT02 ST-MEMS audio sensor omni-directional digital microphone +- CS43L22 audio DAC with integrated class D speaker driver + +.. image:: img/stm32f4_disco.jpg + :align: center + :alt: STM32F4DISCOVERY + +More information about the board can be found at the `STM32F4DISCOVERY website`_. + +Hardware +******** + +STM32F4DISCOVERY Discovery kit provides the following hardware components: + +- STM32F407VGT6 in LQFP100 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 168 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 1 MB Flash +- 192+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (6) +- I2C (3) +- SPI (3) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F407VG can be found here: + - `STM32F407VG on www.st.com`_ + - `STM32F407 reference manual`_ + +Supported Features +================== + +The Zephyr stm32f4_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | CAN controller | ++-----------+------------+-------------------------------------+ + +.. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_. + Zephyr default configuration uses CAN_2 exclusively, as simultaneous use + of CAN_1 and CAN_2 is not yet supported. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f4_disco/stm32f4_disco_defconfig` + + +Pin Mapping +=========== + +STM32F4DISCOVERY Discovery kit has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32F4DISCOVERY board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PB6 +- UART_1_RX : PB7 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- USER_PB : PA0 +- LD3 : PD13 +- LD4 : PD12 +- LD5 : PD14 +- LD6 : PD15 +- USB DM : PA11 +- USB DP : PA12 +- CAN1_RX : PB8 +- CAN1_TX : PB9 +- CAN2_RX : PB5 +- CAN2_TX : PB13 + +System Clock +============ + +STM32F4DISCOVERY System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at 168MHz, +driven by 8MHz high speed external clock. + +Serial Port +=========== + +STM32F4DISCOVERY Discovery kit has up to 6 UARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. +Please note that ST-Link Virtual Com Port is not wired to chip serial port. In order to +enable console output you should use a serial cable and connect it to UART2 pins (PA2/PA3). + + +Programming and Debugging +************************* + +Applications for the ``stm32f4_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F4DISCOVERY Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32F4DISCOVERY +------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Build and flash the application: + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32f4_disco + :goals: build flash + +You should see user led "LD4" blinking. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f4_disco + :maybe-skip-config: + :goals: debug + +.. _STM32F4DISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32f4discovery.html + +.. _STM32F4DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00039084.pdf + +.. _STM32F407VG on www.st.com: + https://www.st.com/en/microcontrollers/stm32f407vg.html + +.. _STM32F407 reference manual: + https://www.st.com/resource/en/reference_manual/dm00031020.pdf + +.. _SK Pang CAN breakout board: + https://www.skpang.co.uk/products/can-bus-can-fd-breakout-board-5v-supply-and-3-3v-logic diff --git a/boards/arm/stm32f4_disco/stm32f4_disco.dts b/boards/st/stm32f4_disco/stm32f4_disco.dts similarity index 100% rename from boards/arm/stm32f4_disco/stm32f4_disco.dts rename to boards/st/stm32f4_disco/stm32f4_disco.dts diff --git a/boards/arm/stm32f4_disco/stm32f4_disco.yaml b/boards/st/stm32f4_disco/stm32f4_disco.yaml similarity index 100% rename from boards/arm/stm32f4_disco/stm32f4_disco.yaml rename to boards/st/stm32f4_disco/stm32f4_disco.yaml diff --git a/boards/arm/stm32f4_disco/stm32f4_disco_defconfig b/boards/st/stm32f4_disco/stm32f4_disco_defconfig similarity index 84% rename from boards/arm/stm32f4_disco/stm32f4_disco_defconfig rename to boards/st/stm32f4_disco/stm32f4_disco_defconfig index ad325266c72c97..c729b83e3d0506 100644 --- a/boards/arm/stm32f4_disco/stm32f4_disco_defconfig +++ b/boards/st/stm32f4_disco/stm32f4_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F407XG=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f4_disco/support/openocd.cfg b/boards/st/stm32f4_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f4_disco/support/openocd.cfg rename to boards/st/stm32f4_disco/support/openocd.cfg diff --git a/boards/st/stm32f723e_disco/Kconfig.defconfig b/boards/st/stm32f723e_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..607dc58ca369d3 --- /dev/null +++ b/boards/st/stm32f723e_disco/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32F723E DISCOVERY board configuration + +# Copyright (c) 2018 Aurelien Jarno +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F723E_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + + +endif # BOARD_STM32F723E_DISCO diff --git a/boards/st/stm32f723e_disco/Kconfig.stm32f723e_disco b/boards/st/stm32f723e_disco/Kconfig.stm32f723e_disco new file mode 100644 index 00000000000000..a8caec5cf6f31f --- /dev/null +++ b/boards/st/stm32f723e_disco/Kconfig.stm32f723e_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Aurelien Jarno +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F723E_DISCO + select SOC_STM32F723XX diff --git a/boards/arm/stm32f723e_disco/arduino_r3_connector.dtsi b/boards/st/stm32f723e_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f723e_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f723e_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f723e_disco/board.cmake b/boards/st/stm32f723e_disco/board.cmake similarity index 100% rename from boards/arm/stm32f723e_disco/board.cmake rename to boards/st/stm32f723e_disco/board.cmake diff --git a/boards/st/stm32f723e_disco/board.yml b/boards/st/stm32f723e_disco/board.yml new file mode 100644 index 00000000000000..652487052342f2 --- /dev/null +++ b/boards/st/stm32f723e_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f723e_disco + vendor: st + socs: + - name: stm32f723xx diff --git a/boards/arm/stm32f723e_disco/doc/img/stm32f723e_disco.jpg b/boards/st/stm32f723e_disco/doc/img/stm32f723e_disco.jpg similarity index 100% rename from boards/arm/stm32f723e_disco/doc/img/stm32f723e_disco.jpg rename to boards/st/stm32f723e_disco/doc/img/stm32f723e_disco.jpg diff --git a/boards/st/stm32f723e_disco/doc/index.rst b/boards/st/stm32f723e_disco/doc/index.rst new file mode 100644 index 00000000000000..554c329db81e4a --- /dev/null +++ b/boards/st/stm32f723e_disco/doc/index.rst @@ -0,0 +1,192 @@ +.. _stm32f723e_disco_board: + +ST STM32F723E Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F723IEK6 microcontroller featuring 512 Kbytes of Flash memory and 256+16+4 Kbytes of RAM, in BGA176 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- TFT LCD 240x240 pixels with touch panel +- SAI audio codec +- Audio line in and line out jack +- Stereo speaker outputs +- Four ST MEMS microphones +- Two pushbuttons (user and reset) +- 512-Mbit Quad-SPI Flash memory +- 8-Mbit external PSRAM +- USB OTG HS with Micro-AB connectors +- USB OTG FS with Micro-AB connectors + +.. image:: img/stm32f723e_disco.jpg + :align: center + :alt: STM32F723E-DISCO + +More information about the board can be found at the `32F723E-DISCO website`_. + +Hardware +******** + +The STM32F723E Discovery kit provides the following hardware components: + +- STM32F723IEK6 in BGA176 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 1 MB Flash +- 256+16+4 KB SRAM including 64KB of tightly coupled memory +- GPIO with external interrupt capability +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer (2) +- General Purpose Timers (13) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (5) +- 2xSAI (serial audio interface) +- SDIO (2) +- CAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and on-chip hi-speed PHY +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F723IEK6 can be found here: + +- `STM32F723IEK6 on www.st.com`_ +- `STM32F72xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f723e_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f723e_disco/stm32f723e_disco_defconfig` + +Pin Mapping +=========== + +STM32F723E Discovery kit has 7 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F723E-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- +- UART_2 TX/RX : PA2/PA3 (Arduino Serial) +- UART_6 TX/RX : PC6/PC7 (ST-Link Virtual Port Com) +- I2C1 SCL/SDA : PB8/PB9 +- I2C2 SCL/SDA : PH4/PH5 (Arduino I2C) +- I2C3 SCL/SDA : PA8/PH8 +- SPI1 SCK/MISO/MOSI : PA5/PB4/PB5 (Arduino SPI) +- LD1 : PA5 +- LD5 : PA7 +- LD6 : PB1 +- OTG_FS_DM : PA11 +- OTG_FS_DP : PA12 + +System Clock +============ + +The STM32F723E System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F723E Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART6 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f723e_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F723E Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F723E-DISCO +------------------------------------------- + +First, connect the STM32F723E Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f723e_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f723e_disco + :goals: debug + + +.. _32F723E-DISCO website: + https://www.st.com/en/evaluation-tools/32f723ediscovery.html + +.. _32F723E-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00342318.pdf + +.. _STM32F723IEK6 on www.st.com: + https://www.st.com/en/microcontrollers/stm32f723ie.html + +.. _STM32F72xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00305990.pdf diff --git a/boards/arm/stm32f723e_disco/stm32f723e_disco.dts b/boards/st/stm32f723e_disco/stm32f723e_disco.dts similarity index 100% rename from boards/arm/stm32f723e_disco/stm32f723e_disco.dts rename to boards/st/stm32f723e_disco/stm32f723e_disco.dts diff --git a/boards/arm/stm32f723e_disco/stm32f723e_disco.yaml b/boards/st/stm32f723e_disco/stm32f723e_disco.yaml similarity index 100% rename from boards/arm/stm32f723e_disco/stm32f723e_disco.yaml rename to boards/st/stm32f723e_disco/stm32f723e_disco.yaml diff --git a/boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig b/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig similarity index 84% rename from boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig rename to boards/st/stm32f723e_disco/stm32f723e_disco_defconfig index 404cd5c1bb15f6..c729b83e3d0506 100644 --- a/boards/arm/stm32f723e_disco/stm32f723e_disco_defconfig +++ b/boards/st/stm32f723e_disco/stm32f723e_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F723XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f723e_disco/support/openocd.cfg b/boards/st/stm32f723e_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f723e_disco/support/openocd.cfg rename to boards/st/stm32f723e_disco/support/openocd.cfg diff --git a/boards/st/stm32f746g_disco/Kconfig.defconfig b/boards/st/stm32f746g_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..e617f92308bd77 --- /dev/null +++ b/boards/st/stm32f746g_disco/Kconfig.defconfig @@ -0,0 +1,37 @@ +# STM32F746G DISCOVERY board configuration + +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F746G_DISCO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config INPUT + default y if LVGL + +if DISPLAY + +# MEMC needs to be enabled in order to store +# display buffer to external SDRAM connected to FMC +config MEMC + default y + +endif # DISPLAY + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32F746G_DISCO diff --git a/boards/st/stm32f746g_disco/Kconfig.stm32f746g_disco b/boards/st/stm32f746g_disco/Kconfig.stm32f746g_disco new file mode 100644 index 00000000000000..3e29d5e0747435 --- /dev/null +++ b/boards/st/stm32f746g_disco/Kconfig.stm32f746g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F746G_DISCO + select SOC_STM32F746XX diff --git a/boards/arm/stm32f746g_disco/arduino_r3_connector.dtsi b/boards/st/stm32f746g_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f746g_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f746g_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f746g_disco/board.cmake b/boards/st/stm32f746g_disco/board.cmake similarity index 100% rename from boards/arm/stm32f746g_disco/board.cmake rename to boards/st/stm32f746g_disco/board.cmake diff --git a/boards/st/stm32f746g_disco/board.yml b/boards/st/stm32f746g_disco/board.yml new file mode 100644 index 00000000000000..3522ea40ac3af1 --- /dev/null +++ b/boards/st/stm32f746g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f746g_disco + vendor: st + socs: + - name: stm32f746xx diff --git a/boards/arm/stm32f746g_disco/doc/img/stm32f746g_disco.jpg b/boards/st/stm32f746g_disco/doc/img/stm32f746g_disco.jpg similarity index 100% rename from boards/arm/stm32f746g_disco/doc/img/stm32f746g_disco.jpg rename to boards/st/stm32f746g_disco/doc/img/stm32f746g_disco.jpg diff --git a/boards/st/stm32f746g_disco/doc/index.rst b/boards/st/stm32f746g_disco/doc/index.rst new file mode 100644 index 00000000000000..03e71c20b90ea7 --- /dev/null +++ b/boards/st/stm32f746g_disco/doc/index.rst @@ -0,0 +1,243 @@ +.. _stm32f746g_disco_board: + +ST STM32F746G Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F746NGH6 microcontroller featuring 1 Mbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Five power supply options: + + - ST LINK/V2-1 + - USB FS connector + - USB HS connector + - VIN from Arduino connector + - External 5 V from connector + +- Two pushbuttons (user and reset) +- USB functions: virtual COM port, mass storage, debug port +- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen +- SAI audio codec +- Audio line in and line out jack +- Stereo speaker outputs +- Two ST MEMS microphones +- SPDIF RCA input connector +- 128-Mbit Quad-SPI Flash memory +- 128-Mbit SDRAM (64 Mbits accessible) +- Connector for microSD card +- USB OTG HS with Micro-AB connectors +- USB OTG FS with Micro-AB connectors +- Ethernet connector compliant with IEEE-802.3-2002 + +.. image:: img/stm32f746g_disco.jpg + :align: center + :alt: STM32F746G-DISCO + +More information about the board can be found at the `32F746G-DISCO website`_. + +Hardware +******** + +The STM32F746G Discovery kit provides the following hardware components: + +- STM32F746NGH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- VDD from 1.8 V to 3.6 V +- 2 MB Flash +- 384+4 KB SRAM including 64-Kbyte of core coupled memory +- GPIO with external interrupt capability +- LCD parallel interface, 8080/6800 modes +- LCD TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (3) +- SPI (6) +- 1xSAI (serial audio interface) +- SDIO +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F746NGH6 can be found here: + +- `STM32F746NGH6 on www.st.com`_ +- `STM32F74xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f746g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f746g_disco/stm32f746g_disco_defconfig` + +Pin Mapping +=========== + +STM32F746G Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F746G-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The STM32F746G Discovery kit features an Arduino Uno V3 connector. Board is +configured as follows + +- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PC6/PC7 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 +- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) +- PWM_3_CH1 : PB4 +- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 +- USER_PB : PI11 +- LD1 : PI1 +- USB DM : PA11 +- USB DP : PA12 +- FMC SDRAM : + + - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 + - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 + - A14/A15 : PG4/PG5 + - SDNRAS/SDNCAS : PF11/PG15 + - NBL0/NBL1 : PE0/PE1 + - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 + +- LTDC : + + - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 + - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 + - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 + - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 + + +System Clock +============ + +The STM32F746G System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F746G Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f746g_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F746G +------------------------------------------- + +First, connect the STM32F746G Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f746g_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f746g_disco + :goals: debug + + +.. _32F746G-DISCO website: + https://www.st.com/en/evaluation-tools/32f746gdiscovery.html + +.. _32F746G-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00190424.pdf + +.. _STM32F746NGH6 on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html + +.. _STM32F74xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.dts b/boards/st/stm32f746g_disco/stm32f746g_disco.dts similarity index 100% rename from boards/arm/stm32f746g_disco/stm32f746g_disco.dts rename to boards/st/stm32f746g_disco/stm32f746g_disco.dts diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco.yaml b/boards/st/stm32f746g_disco/stm32f746g_disco.yaml similarity index 100% rename from boards/arm/stm32f746g_disco/stm32f746g_disco.yaml rename to boards/st/stm32f746g_disco/stm32f746g_disco.yaml diff --git a/boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig b/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig similarity index 84% rename from boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig rename to boards/st/stm32f746g_disco/stm32f746g_disco_defconfig index fff57f6d5e40ba..c729b83e3d0506 100644 --- a/boards/arm/stm32f746g_disco/stm32f746g_disco_defconfig +++ b/boards/st/stm32f746g_disco/stm32f746g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F746XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f746g_disco/support/openocd.cfg b/boards/st/stm32f746g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f746g_disco/support/openocd.cfg rename to boards/st/stm32f746g_disco/support/openocd.cfg diff --git a/boards/st/stm32f7508_dk/Kconfig.defconfig b/boards/st/stm32f7508_dk/Kconfig.defconfig new file mode 100644 index 00000000000000..c43b749d79b915 --- /dev/null +++ b/boards/st/stm32f7508_dk/Kconfig.defconfig @@ -0,0 +1,37 @@ +# STM32F7508-DK Discovery board configuration + +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F7508_DK + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +if DISPLAY + +# MEMC needs to be enabled in order to store +# display buffer to external SDRAM connected to FMC +config MEMC + default y + +endif # DISPLAY + +config INPUT + default y if LVGL + +if INPUT + +config INPUT_FT5336_INTERRUPT + default y + +endif # INPUT + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32F7508_DK diff --git a/boards/st/stm32f7508_dk/Kconfig.stm32f7508_dk b/boards/st/stm32f7508_dk/Kconfig.stm32f7508_dk new file mode 100644 index 00000000000000..8da75f6864a935 --- /dev/null +++ b/boards/st/stm32f7508_dk/Kconfig.stm32f7508_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F7508_DK + select SOC_STM32F750XX diff --git a/boards/arm/stm32f7508_dk/arduino_r3_connector.dtsi b/boards/st/stm32f7508_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f7508_dk/arduino_r3_connector.dtsi rename to boards/st/stm32f7508_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f7508_dk/board.cmake b/boards/st/stm32f7508_dk/board.cmake similarity index 100% rename from boards/arm/stm32f7508_dk/board.cmake rename to boards/st/stm32f7508_dk/board.cmake diff --git a/boards/st/stm32f7508_dk/board.yml b/boards/st/stm32f7508_dk/board.yml new file mode 100644 index 00000000000000..46e12e5a6f0f82 --- /dev/null +++ b/boards/st/stm32f7508_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f7508_dk + vendor: st + socs: + - name: stm32f750xx diff --git a/boards/arm/stm32f7508_dk/doc/img/stm32f7508_dk.jpg b/boards/st/stm32f7508_dk/doc/img/stm32f7508_dk.jpg similarity index 100% rename from boards/arm/stm32f7508_dk/doc/img/stm32f7508_dk.jpg rename to boards/st/stm32f7508_dk/doc/img/stm32f7508_dk.jpg diff --git a/boards/st/stm32f7508_dk/doc/index.rst b/boards/st/stm32f7508_dk/doc/index.rst new file mode 100644 index 00000000000000..0b3737a87614f2 --- /dev/null +++ b/boards/st/stm32f7508_dk/doc/index.rst @@ -0,0 +1,238 @@ +.. _stm32f7508_dk_board: + +ST STM32F7508-DK Discovery Kit +############################## + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F750N8H6 microcontroller featuring 64 Kbytes of Flash memory and 340 Kbytes of RAM, in BGA216 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Five power supply options: + + - ST LINK/V2-1 + - USB FS connector + - USB HS connector + - VIN from Arduino connector + - External 5 V from connector + +- Two pushbuttons (user and reset) +- USB functions: virtual COM port, mass storage, debug port +- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen +- SAI audio codec +- Audio line in and line out jack +- Two ST MEMS microphones +- SPDIF RCA input connector +- 128-Mbit Quad-SPI Flash memory +- 128-Mbit SDRAM (64 Mbits accessible) +- Connector for microSD card +- USB OTG HS with Micro-AB connectors +- USB OTG FS with Micro-AB connectors +- Ethernet connector compliant with IEEE-802.3-2002 + +.. image:: img/stm32f7508_dk.jpg + :align: center + :alt: STM32F7508-DK + +More information about the board can be found at the `32F7508-DK website`_. + +Hardware +******** + +The STM32F7508-DK Discovery kit provides the following hardware components: + +- STM32F750N8H6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- 64 KB Flash +- 320+16+4 KB SRAM +- GPIO with external interrupt capability +- 4.3-inch 480x272 color LCD-TFT with capacitive touch screen +- 3x12-bit ADC +- 2x12-bit D/A converters +- RTC +- Advanced-control Timer +- General Purpose Timers (17) +- Watchdog Timers (2) +- USART/UART (8) +- I2C (4) +- SPI (6) +- 2xSAI (serial audio interface) +- 2xCAN +- USB 2.0 OTG FS with on-chip PHY +- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA +- 8- to 14-bit parallel camera +- CRC calculation unit +- True random number generator +- DMA Controller + +More information about STM32F750x8 can be found here: + +- `STM32F750x8 on www.st.com`_ +- `STM32F74xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f7508_dk board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f7508_dk/stm32f7508_dk_defconfig` + +Pin Mapping +=========== + +STM32F7508-DK Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F7508-DK board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +The STM32F7508 Discovery kit features an Arduino Uno V3 connector. Board is +configured as follows + +- UART_1 TX/RX : PA9/PB7 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PC6/PC7 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- SDMMC_1 D0/D1/D2/D3/CK/CD/CMD: PC8/PC9/PC10/PC11/PC12/PC13/PD2 +- SPI2 NSS/SCK/MISO/MOSI : PA8/PI1/PB14/PB15 (Arduino SPI) +- PWM_3_CH1 : PB4 +- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 +- USER_PB : PI11 +- LD1 : PI1 +- USB DM : PA11 +- USB DP : PA12 +- FMC SDRAM : + + - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 + - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 + - A14/A15 : PG4/PG5 + - SDNRAS/SDNCAS : PF11/PG15 + - NBL0/NBL1 : PE0/PE1 + - SDCLK/SDNWE/SDCKE0/SDNE0 : PG8/PH5/PC3/PH3 + +- LTDC : + + - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 + - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 + - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 + - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 + + +System Clock +============ + +The STM32F7508 System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F7508-DK Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f7508_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F7508-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F7508-DK +------------------------------------------- + +First, connect the STM32F746G Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f7508_dk + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f7508_dk + :goals: debug + + +.. _32F7508-DK website: + https://www.st.com/en/evaluation-tools/stm32f7508-dk.html + +.. _32F7508-DK board User Manual: + https://www.st.com/resource/en/user_manual/dm00537062-discovery-kit-for-stm32f7-series-with-stm32f750n8-mcu-stmicroelectronics.pdf + +.. _STM32F750x8 on www.st.com: + https://www.st.com/resource/en/datasheet/stm32f750z8.pdf + +.. _STM32F74xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00124865.pdf diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk.dts b/boards/st/stm32f7508_dk/stm32f7508_dk.dts similarity index 100% rename from boards/arm/stm32f7508_dk/stm32f7508_dk.dts rename to boards/st/stm32f7508_dk/stm32f7508_dk.dts diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk.yaml b/boards/st/stm32f7508_dk/stm32f7508_dk.yaml similarity index 100% rename from boards/arm/stm32f7508_dk/stm32f7508_dk.yaml rename to boards/st/stm32f7508_dk/stm32f7508_dk.yaml diff --git a/boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig b/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig similarity index 85% rename from boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig rename to boards/st/stm32f7508_dk/stm32f7508_dk_defconfig index b78ebb9d3a3c44..18159201a573a6 100644 --- a/boards/arm/stm32f7508_dk/stm32f7508_dk_defconfig +++ b/boards/st/stm32f7508_dk/stm32f7508_dk_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2022, Rtone. # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F750XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f7508_dk/support/openocd.cfg b/boards/st/stm32f7508_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f7508_dk/support/openocd.cfg rename to boards/st/stm32f7508_dk/support/openocd.cfg diff --git a/boards/st/stm32f769i_disco/Kconfig.defconfig b/boards/st/stm32f769i_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..be174cce67f0bf --- /dev/null +++ b/boards/st/stm32f769i_disco/Kconfig.defconfig @@ -0,0 +1,22 @@ +# STM32F769I DISCOVERY board configuration + +# Copyright (c) 2018 Yong Jin +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32F769I_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config INPUT + default y if LVGL + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_STM32F769I_DISCO diff --git a/boards/st/stm32f769i_disco/Kconfig.stm32f769i_disco b/boards/st/stm32f769i_disco/Kconfig.stm32f769i_disco new file mode 100644 index 00000000000000..0041a7a9b69459 --- /dev/null +++ b/boards/st/stm32f769i_disco/Kconfig.stm32f769i_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2018 Yong Jin +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32F769I_DISCO + select SOC_STM32F769XX diff --git a/boards/arm/stm32f769i_disco/arduino_r3_connector.dtsi b/boards/st/stm32f769i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32f769i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32f769i_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32f769i_disco/board.cmake b/boards/st/stm32f769i_disco/board.cmake similarity index 100% rename from boards/arm/stm32f769i_disco/board.cmake rename to boards/st/stm32f769i_disco/board.cmake diff --git a/boards/st/stm32f769i_disco/board.yml b/boards/st/stm32f769i_disco/board.yml new file mode 100644 index 00000000000000..de83c60be993bd --- /dev/null +++ b/boards/st/stm32f769i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32f769i_disco + vendor: st + socs: + - name: stm32f769xx diff --git a/boards/arm/stm32f769i_disco/doc/img/stm32f769i_disco.jpg b/boards/st/stm32f769i_disco/doc/img/stm32f769i_disco.jpg similarity index 100% rename from boards/arm/stm32f769i_disco/doc/img/stm32f769i_disco.jpg rename to boards/st/stm32f769i_disco/doc/img/stm32f769i_disco.jpg diff --git a/boards/st/stm32f769i_disco/doc/index.rst b/boards/st/stm32f769i_disco/doc/index.rst new file mode 100644 index 00000000000000..223c48a9dbe284 --- /dev/null +++ b/boards/st/stm32f769i_disco/doc/index.rst @@ -0,0 +1,225 @@ +.. _stm32f769i_disco_board: + +ST STM32F769I Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, security, video, +and high-speed connectivity features. Important board features include: + +- STM32F769NIH6 microcontroller featuring 2 Mbytes of Flash memory and 512 Kbytes of RAM, in BGA216 package +- On-board ST-LINK/V2-1 supporting USB reenumeration capability +- USB ST-LINK functions: virtual COM port, mass storage, debug port +- Five power supply options: + + - ST LINK/V2-1 + - USB HS connector + - 5 V from RJ45 (Power Over Ethernet) + - 5 V from Arduino™ or external connector + - USB charger + +- 4-inch capacitive touch LCD display with MIPI-DSI connector +- SAI audio codec +- Two audio line jacks, one for input and one for output +- Stereo speaker outputs +- Four ST MEMS microphones on DFSDM inputs +- Two SPDIF RCA input and output connectors +- Two push-buttons (user and reset) +- 512-Mbit Quad-SPI Flash memory +- 128-Mbit SDRAM +- Connector for microSD card +- Wi-Fi or Ext-EEP daughterboard connector +- USB OTG HS with Micro-AB connector +- Ethernet connector compliant with IEEE-802.3-2002 +- Power Over Ethernet based on IEEE 802.3af (Powered Device, 48 V to 5 V, 3 W) +- Power supply output for external applications: 3.3 V or 5 V +- Arduino Uno V3 connectors +- Comprehensive free software including a variety of examples, part of the STM32Cube package +- Supported by a wide choice of integrated development environments + +.. image:: img/stm32f769i_disco.jpg + :align: center + :alt: STM32F769I-DISCO + +More information about the board can be found at the `32F769I-DISCO website`_. + +Hardware +******** + +The STM32F769I Discovery kit provides the following hardware components: + +- STM32F769NIH6 in BGA216 package +- ARM |reg| 32-bit Cortex |reg| -M7 CPU with FPU +- 216 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 2 MB Flash +- 512 + 16 + 4 KB SRAM +- Flexible external memory controller with up to 32-bit data bus +- Dual mode Quad-SPI +- Chrom-ART Accelerator(DMA2D), graphical hardware accelerator enabling enhanced graphical user interface +- Hardware JPEG codec +- LCD-TFT controller supporting up to XGA resolution +- MIPI |reg| DSI host controller supporting up to 720p 30Hz resolution +- 3x12-bit ADC with 24 channels +- 2x12-bit D/A converters +- DMA Controller +- General Purpose Timers (15) +- Watchdog Timers (2) +- I2C (4) +- USART/UART (8) +- SPI (6) +- SAI (2) +- CAN (3) +- SDMMC (2) +- SPDIFRX interface +- HDMI-CEC +- MDIO slave interface +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- USB 2.0 high-speed/full-speed device/host/OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI +- 10/100 Ethernet MAC with dedicated DMA: supports IEEE 1588v2 hardware, MII/RMII +- 8- to 14-bit camera interface up to 54 Mbyte/s +- True random number generator +- CRC calculation unit +- RTC: sub-second accuracy, hardware calendar +- 96-bit unique ID + +More information about STM32F769NIH6 can be found here: + +- `STM32F769NIH6 on www.st.com`_ +- `STM32F76xxx reference manual`_ + +Supported Features +================== + +The Zephyr stm32f769i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | Ethernet | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | flash | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| TOUCH | off-chip | ft5336(FT6202) | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32f769i_disco/stm32f769i_disco_defconfig` + +Pin Mapping +=========== + +STM32F769I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `32F769I-DISCO board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- UART_6 TX/RX : PC6/PC7 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C) +- I2C4 SCL/SDA : PD12/PB7 (Touchscreen FT6202, PI13 Interrupt Pin) +- SPI2 SCK/MISO/MOSI : PA12/PB14/PB15 (Arduino SPI) +- ETH : PA1, PA2, PA7, PC1, PC4, PC5, PG11, PG13, PG14 +- LD1 : PJ13 +- LD2 : PJ5 +- LD3 : PA12 +- LD4 : PD4 + +System Clock +============ + +The STM32F769I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by the PLL +clock at 216MHz, driven by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32F769I Discovery kit has up to 8 UARTs. The Zephyr console output is assigned to UART1 +which connected to the onboard ST-LINK/V2 Virtual COM port interface. Default communication +settings are 115200 8N1. + +Programming and Debugging +************************* + +Applications for the ``stm32f769i_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32F769I Discovery kit includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application to STM32F769I +------------------------------------------- + +First, connect the STM32F769I Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f769i_disco + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32f769i_disco + :goals: debug + + +.. _32F769I-DISCO website: + https://www.st.com/en/evaluation-tools/32f769idiscovery.html + +.. _32F769I-DISCO board User Manual: + https://www.st.com/resource/en/user_manual/dm00276557.pdf + +.. _STM32F769NIH6 on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32f7-series/stm32f7x9/stm32f769ni.html + +.. _STM32F76xxx reference manual: + https://www.st.com/resource/en/reference_manual/dm00224583.pdf diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts similarity index 100% rename from boards/arm/stm32f769i_disco/stm32f769i_disco.dts rename to boards/st/stm32f769i_disco/stm32f769i_disco.dts diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco.yaml b/boards/st/stm32f769i_disco/stm32f769i_disco.yaml similarity index 100% rename from boards/arm/stm32f769i_disco/stm32f769i_disco.yaml rename to boards/st/stm32f769i_disco/stm32f769i_disco.yaml diff --git a/boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig b/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig similarity index 84% rename from boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig rename to boards/st/stm32f769i_disco/stm32f769i_disco_defconfig index 3a6c65f14b6929..c729b83e3d0506 100644 --- a/boards/arm/stm32f769i_disco/stm32f769i_disco_defconfig +++ b/boards/st/stm32f769i_disco/stm32f769i_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F7X=y -CONFIG_SOC_STM32F769XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32f769i_disco/support/openocd.cfg b/boards/st/stm32f769i_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f769i_disco/support/openocd.cfg rename to boards/st/stm32f769i_disco/support/openocd.cfg diff --git a/boards/st/stm32g0316_disco/Kconfig.stm32g0316_disco b/boards/st/stm32g0316_disco/Kconfig.stm32g0316_disco new file mode 100644 index 00000000000000..b0f55e7bba7022 --- /dev/null +++ b/boards/st/stm32g0316_disco/Kconfig.stm32g0316_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2019 SEAL AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32G0316_DISCO + select SOC_STM32G031XX diff --git a/boards/arm/stm32g0316_disco/board.cmake b/boards/st/stm32g0316_disco/board.cmake similarity index 100% rename from boards/arm/stm32g0316_disco/board.cmake rename to boards/st/stm32g0316_disco/board.cmake diff --git a/boards/st/stm32g0316_disco/board.yml b/boards/st/stm32g0316_disco/board.yml new file mode 100644 index 00000000000000..5a67daf81d6bb6 --- /dev/null +++ b/boards/st/stm32g0316_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32g0316_disco + vendor: st + socs: + - name: stm32g031xx diff --git a/boards/arm/stm32g0316_disco/doc/img/stm32g0316_disco.jpg b/boards/st/stm32g0316_disco/doc/img/stm32g0316_disco.jpg similarity index 100% rename from boards/arm/stm32g0316_disco/doc/img/stm32g0316_disco.jpg rename to boards/st/stm32g0316_disco/doc/img/stm32g0316_disco.jpg diff --git a/boards/st/stm32g0316_disco/doc/index.rst b/boards/st/stm32g0316_disco/doc/index.rst new file mode 100644 index 00000000000000..6767a115416428 --- /dev/null +++ b/boards/st/stm32g0316_disco/doc/index.rst @@ -0,0 +1,134 @@ +.. _stm32g0316_disco_board: + +ST STM32G0316 Discovery +####################### + +Overview +******** + +The STM32G0316-DISCO Discovery kit helps to discover features of STM32G0 in SO8 package. +This discovery kit offers an SO8 to DIL8 module designed with the STM32G031J6 microcontroller +and allows the user to develop applications. It includes an on-board ST-LINK/V2-1 to debug +and program the embedded STM32 microcontroller. + +.. image:: img/stm32g0316_disco.jpg + :align: center + :alt: STM32G0316-DISCO + +Hardware +******** + +- STM32G031J6 Arm |reg| Cortex |reg|-M0+ core-based microcontroller, + featuring 32 Kbytes of Flash memory and 8 Kbytes of SRAM, in an SO8 package +- 1 user LED +- 1 reset/user push-button +- Individual and breakable STM32 SO8 to DIL8 module +- ST-LINK Micro-B USB connector +- DIL8 socket to ease programming of the STM32 MCU +- On-board ST-LINK/V2-1 debugger/programmer + +For more information about the STM32G03x SoC and the STM32G0316-DISCO board, see these ST reference documents: + +- `STM32G031J6 website`_ +- `STM32G031 datasheet`_ +- `STM32G0x1 reference manual`_ +- `STM32G0316-DISCO website`_ + +Supported Features +================== + +The Zephyr stm32g0316_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32g0316_disco/stm32g0316_disco_defconfig` + +Connections and IOs +=================== + +Due to the small number of I/O pins on the SO8 package, multiple die I/Os are bonded +to the same package pins to maximize the number of peripherals which can be used. +Care must be taken not to set two I/Os which are connected together to conflicting +states (e.g. both as outputs, one low, the other high). + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1 TX/RX : PA9/PB7 (pins 5/1) +- USER_PB : PA0 (pin 4) +- LD2 : PA12 (pin 6) + +Programming and Debugging +************************* + +Applications for the ``stm32g0316_disco`` board configuration can be built the +usual way (see :ref:`build_an_application` and :ref:`application_run` for more details). + +Flashing +======== + +The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool +interface. This interface is not yet supported by the openocd version included in +the Zephyr SDK. Instead, support can be enabled on pyocd by adding "pack" support with +the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32g031j6 + +Flashing an application to the STM32G0316-DISCO +----------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32g0316_disco + :goals: build flash + +You should see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32g0316_disco + :maybe-skip-config: + :goals: debug + +.. _STM32G031J6 website: + https://www.st.com/en/microcontrollers-microprocessors/stm32g031j6.html + +.. _STM32G031 datasheet: + https://www.st.com/resource/en/datasheet/stm32g031j6.pdf + +.. _STM32G0x1 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32G0316-DISCO website: + https://www.st.com/en/evaluation-tools/stm32g0316-disco.html diff --git a/boards/arm/stm32g0316_disco/stm32g0316_disco.dts b/boards/st/stm32g0316_disco/stm32g0316_disco.dts similarity index 100% rename from boards/arm/stm32g0316_disco/stm32g0316_disco.dts rename to boards/st/stm32g0316_disco/stm32g0316_disco.dts diff --git a/boards/arm/stm32g0316_disco/stm32g0316_disco.yaml b/boards/st/stm32g0316_disco/stm32g0316_disco.yaml similarity index 100% rename from boards/arm/stm32g0316_disco/stm32g0316_disco.yaml rename to boards/st/stm32g0316_disco/stm32g0316_disco.yaml diff --git a/boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig b/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig similarity index 80% rename from boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig rename to boards/st/stm32g0316_disco/stm32g0316_disco_defconfig index a790e064bf6c14..f846f1d12a72e3 100644 --- a/boards/arm/stm32g0316_disco/stm32g0316_disco_defconfig +++ b/boards/st/stm32g0316_disco/stm32g0316_disco_defconfig @@ -1,7 +1,3 @@ -# Zephyr Kernel Configuration -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G031XX=y - # Kernel Options due to Low Memory (8k) CONFIG_MAIN_STACK_SIZE=640 CONFIG_IDLE_STACK_SIZE=200 diff --git a/boards/st/stm32g071b_disco/Kconfig.stm32g071b_disco b/boards/st/stm32g071b_disco/Kconfig.stm32g071b_disco new file mode 100644 index 00000000000000..78241c936dc340 --- /dev/null +++ b/boards/st/stm32g071b_disco/Kconfig.stm32g071b_disco @@ -0,0 +1,5 @@ +# Copyright 2021 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32G071B_DISCO + select SOC_STM32G071XX diff --git a/boards/arm/stm32g071b_disco/board.cmake b/boards/st/stm32g071b_disco/board.cmake similarity index 100% rename from boards/arm/stm32g071b_disco/board.cmake rename to boards/st/stm32g071b_disco/board.cmake diff --git a/boards/st/stm32g071b_disco/board.yml b/boards/st/stm32g071b_disco/board.yml new file mode 100644 index 00000000000000..5445391255f9c7 --- /dev/null +++ b/boards/st/stm32g071b_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32g071b_disco + vendor: st + socs: + - name: stm32g071xx diff --git a/boards/arm/stm32g071b_disco/doc/img/stm32g071b_disco.jpg b/boards/st/stm32g071b_disco/doc/img/stm32g071b_disco.jpg similarity index 100% rename from boards/arm/stm32g071b_disco/doc/img/stm32g071b_disco.jpg rename to boards/st/stm32g071b_disco/doc/img/stm32g071b_disco.jpg diff --git a/boards/st/stm32g071b_disco/doc/index.rst b/boards/st/stm32g071b_disco/doc/index.rst new file mode 100644 index 00000000000000..6047f6d298a8a6 --- /dev/null +++ b/boards/st/stm32g071b_disco/doc/index.rst @@ -0,0 +1,169 @@ +.. _stm32g071b_disco_board: + +ST STM32G071B Discovery +####################### + +Overview +******** +The STM32G071B-DISCO Discovery board is a demonstration and development platform +for the STMicroelectronics Arm® Cortex® -M0+ core-based STM32G071RB USB Type-C™ +and Power Delivery microcontroller. The STM32G071B-DISCO Discovery board is +presented with all necessary interfaces for easy connection and +interoperability with other USB Type-C™ devices. The STM32G071B-DISCO Discovery +board is intended for discovery and display of USB Type-C™ port characteristics +such as data role, power role, VBUS and IBUS monitoring. It offers an advanced +user mode when associated with the STM32CubeMonUCPD software GUI and can be used +as a USB Type-C™ and Power Delivery analyzer. + +- STM32G071RBT6 microcontroller featuring 128 Kbytes of Flash memory and + 32 Kbytes of RAM in LQFP64 package +- Plastic case +- 1” 128 x 64 pixels OLED LCD module with SPI interface +- USB Type-C™ interface plug cable and receptacle connector accessible by door + with reed sensor detection +- 3 bidirectional current and power monitors with I2C interface to measure VBUS, + CC1 and CC2 protected and isolated lines +- On-board DC/DC converter to sustain power supply with VBUS varying from 3 V to + 20 V (+/- 5 %) +- 4 user status LEDs about USB Type-C™ configuration +- 3 LEDs for power and ST-LINK communication +- 4-way joystick with selection button +- 1 reset push-button +- Board external connectors: + - USB Type-C™ plug cable + - USB Type-C™ receptacle connector + - 8-pin user extension connector including ADC, SPI, USART and + I2C communication signals + - USB with Micro-AB (ST-LINK) +- Board internal connectors: + - 2 x 8-pin GPIOs free pins from microcontroller + (accessible internally when case is removed) + - USB Type-C™ test points for main signals +- Flexible power-supply options: ST-LINK USB VBUS or USB Type-C™ VBUS +- On-board ST-LINK/V2-1 debugger/programmer with USB enumeration capability: + mass storage, Virtual COM port and debug port + +.. image:: img/stm32g071b_disco.jpg + :align: center + :alt: STM32G071B-DISCO + +More information about the board can be found at the `STM32G071B-DISCO website`_. + + +More information about STM32G071RB can be found here: +- `G071RB on www.st.com`_ +- `STM32G071 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32g071b_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UCPD | on-chip | ucpd | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32g071b_disco/stm32g071b_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) +- UCPD1 : PA8/PB15 +- BUTTON (JOY_SEL) : PC0 +- BUTTON (JOY_LEFT) : PC1 +- BUTTON (JOY_DOWN) : PC2 +- BUTTON (JOY_RIGHT) : PC3 +- BUTTON (JOY_UP) : PC4 +- LED (TO_REC) : PD9 +- LED (TO_PLUG) : PD8 +- LED (SINK_SPY) : PD5 +- LED (SOURCE) : PC12 +- ENCC1 : PB10 (Enable CC1) +- ENCC2 : PB11 (Enable CC2) +- RDCC1 : PB12 (Enable Door Sense on CC1) + + +For more details please refer to `STM32G0 Discovery board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32g071b_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The STM32G071B Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. + +.. code-block:: console + + $ west flash + +Flashing an application to the STM32G071B_DISCO +----------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32g071b_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32g071b_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32G071B-DISCO website: + https://www.st.com/en/evaluation-tools/stm32g071b-disco.html + +.. _STM32G071 reference manual: + https://www.st.com/resource/en/reference_manual/dm00371828.pdf + +.. _STM32G0 Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00496511.pdf + +.. _G071RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g071rb.html diff --git a/boards/arm/stm32g071b_disco/stm32g071b_disco.dts b/boards/st/stm32g071b_disco/stm32g071b_disco.dts similarity index 100% rename from boards/arm/stm32g071b_disco/stm32g071b_disco.dts rename to boards/st/stm32g071b_disco/stm32g071b_disco.dts diff --git a/boards/arm/stm32g071b_disco/stm32g071b_disco.yaml b/boards/st/stm32g071b_disco/stm32g071b_disco.yaml similarity index 100% rename from boards/arm/stm32g071b_disco/stm32g071b_disco.yaml rename to boards/st/stm32g071b_disco/stm32g071b_disco.yaml diff --git a/boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig b/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig similarity index 85% rename from boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig rename to boards/st/stm32g071b_disco/stm32g071b_disco_defconfig index c4129b26a7fb38..2554c25669715e 100644 --- a/boards/arm/stm32g071b_disco/stm32g071b_disco_defconfig +++ b/boards/st/stm32g071b_disco/stm32g071b_disco_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G071XX=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/st/stm32g081b_eval/Kconfig.stm32g081b_eval b/boards/st/stm32g081b_eval/Kconfig.stm32g081b_eval new file mode 100644 index 00000000000000..0448edcd135d92 --- /dev/null +++ b/boards/st/stm32g081b_eval/Kconfig.stm32g081b_eval @@ -0,0 +1,5 @@ +# Copyright 2021 The Chromium OS Authors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32G081B_EVAL + select SOC_STM32G081XX diff --git a/boards/arm/stm32g081b_eval/board.cmake b/boards/st/stm32g081b_eval/board.cmake similarity index 100% rename from boards/arm/stm32g081b_eval/board.cmake rename to boards/st/stm32g081b_eval/board.cmake diff --git a/boards/st/stm32g081b_eval/board.yml b/boards/st/stm32g081b_eval/board.yml new file mode 100644 index 00000000000000..5cdb22ef9b8754 --- /dev/null +++ b/boards/st/stm32g081b_eval/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32g081b_eval + vendor: st + socs: + - name: stm32g081xx diff --git a/boards/arm/stm32g081b_eval/doc/img/stm32g081b_eval.jpg b/boards/st/stm32g081b_eval/doc/img/stm32g081b_eval.jpg similarity index 100% rename from boards/arm/stm32g081b_eval/doc/img/stm32g081b_eval.jpg rename to boards/st/stm32g081b_eval/doc/img/stm32g081b_eval.jpg diff --git a/boards/st/stm32g081b_eval/doc/index.rst b/boards/st/stm32g081b_eval/doc/index.rst new file mode 100644 index 00000000000000..5363a2c230a409 --- /dev/null +++ b/boards/st/stm32g081b_eval/doc/index.rst @@ -0,0 +1,207 @@ +.. _stm32g081b_eval_board: + +ST STM32G081B Evaluation +######################## + +Overview +******** +The STM32G081B-EVAL Evaluation board is a high-end development platform, for +Arm Cortex-M0+ core-based STM32G081RBT6 microcontroller, with USB Type-C and +power delivery controller interfaces (UCPD), compliant with USB type-C r1.2 +and USB PD specification r3.0, two I2Cs, two SPIs, five USARTs, one LP UART, +one 12-bit ADC, two 12-bit DACs, two GP comparators, two LP timers, internal +32 KB SRAM and 128 KB Flash, CEC, SWD debugging support. The full range of +hardware features on the STM32G081B-EVAL Evaluation board includes a mother +board, a legacy peripheral daughterboard and a USB-C and Power Delivery +daughterboard, which help to evaluate all peripherals (USB Type-C connector +with USB PD, motor control connector, RS232, RS485, Audio DAC, microphone ADC, +TFT LCD, IrDA, IR LED, IR receiver, LDR, MicroSD card, CEC on two HDMI +connectors, smart card slot, RF E2PROM & Temperature sensor…), and to develop +applications. + +The board integrates an ST-LINK/V2-1 as an embedded in-circuit debugger and +programmer for the STM32 MCU. The daughterboard and extension connectors +provide an easy way to connect a daughterboard or wrapping board for the +user's specific applications. + +The USB-C and Power Delivery daughterboard +features two independent USB-C ports controlled by an STM32G0. USB-C port 1 +is dual role power (DRP) and can provide up-to 45 W. USB-C Port 2 is sink +only. Both support USB PD protocol and alternate mode functionality. + +Application firmware examples are provided to evaluate the USB-C technology +through various use cases. + + + +- Mother board + - STM32G081RBT6 microcontroller with 128 Kbytes of Flash memory and + 32 Kbytes of RAM in LQFP64 package + - MCU voltage choice fixed 3.3 V or adjustable from 1.65 V to 3.6 V + - I2C compatible serial interface + - RTC with backup battery + - 8-Gbyte or more SPI interface microSD card + - Potentiometer + - 4 color user LEDs and one LED as MCU low-power alarm + - Reset, Tamper and User buttons + - 4-direction control and selection joystick + - Board connectors: + - 5 V power jack + - RS-232 and RS485 communications + - Stereo audio jack including analog microphone input + - microSD card + - Extension I2C connector + - Motor-control connector + - Board extension connectors: + - Daughterboard connectors for legacy peripheral daughter board or + USB-C daughterboard + - Extension connectors for daughterboard or wire-wrap board + - Flexible power-supply options: + - 5 V power jack + - ST-LINK/V2-1 USB connector + - Daughterboard + - On-board ST-LINK/V2-1 debugger/programmer with USB re-enumeration + capability: mass storage, virtual COM port and debug port + - Legacy peripheral daughterboard + - IrDA transceiver + - IR LED and IR receiver + - Light dependent resistor (LDR) + - Temperature Sensor + - Board connectors: + - Two HDMI connectors with DDC and CEC + - Smart card slot + - USB-C and Power Delivery daughterboard + - Mux for USB3.1 Gen1 / DisplayPort input and Type-C port1 output + - Mux for Type-C port2 input and DisplayPort output / USB2.0 + - VCONN on Type-C port1 + - USB PD on Type-C port1 + - Board connectors: + - Type-C port1 DRP (dual-role port) + - Type-C port2 Sink + - DisplayPort input + - DisplayPort output + - USB 3.1 Gen1 Type-B receptacle + - USB2.0 Type-A receptacle + - 19 V power jack for USB PD + +.. image:: img/stm32g081b_eval.jpg + :align: center + :alt: STM32G081B-EVAL + +More information about the board can be found at the `STM32G081B-EVAL website`_. + + +More information about STM32G081RB can be found here: +- `G081RB on www.st.com`_ +- `STM32G081 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32g081b_eval board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| UCPD | on-chip + ucpd | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32g081b_eval/stm32g081b_eval_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PC10/PC11 (ST-Link Virtual Port Com) +- UCPD2 : PD0/PD2 +- BUTTON (JOY_SEL) : PA0 +- BUTTON (JOY_LEFT) : PC8 +- BUTTON (JOY_DOWN) : PC3 +- BUTTON (JOY_RIGHT) : PC7 +- BUTTON (JOY_UP) : PC2 +- VBUS DISCHARGE : PB14 +- LED1 : PD5 +- LED2 : PD6 +- LED3 : PD8 +- LED4 : PD9 + +For more details please refer to `STM32G0 Evaluation board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32g081b_eval`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +The STM32G081B Evaluation board includes an ST-LINK/V2-1 embedded debug tool interface. + +.. code-block:: console + + $ west flash + +Flashing an application to the STM32G081B_EVAL +---------------------------------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32g081b_eval + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32g081b_eval + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32G081B-EVAL website: + https://www.st.com/en/evaluation-tools/stm32g081b-eval.html + +.. _STM32G081 reference manual: + https://www.st.com/resource/en/reference_manual/rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32G0 Evaluation board User Manual: + https://www.st.com/resource/en/user_manual/um2403-evaluation-board-with-stm32g081rb-mcu-stmicroelectronics.pdf + +.. _G081RB on www.st.com: + https://www.st.com/en/microcontrollers/stm32g081rb.html diff --git a/boards/arm/stm32g081b_eval/stm32g081b_eval.dts b/boards/st/stm32g081b_eval/stm32g081b_eval.dts similarity index 100% rename from boards/arm/stm32g081b_eval/stm32g081b_eval.dts rename to boards/st/stm32g081b_eval/stm32g081b_eval.dts diff --git a/boards/arm/stm32g081b_eval/stm32g081b_eval.yaml b/boards/st/stm32g081b_eval/stm32g081b_eval.yaml similarity index 100% rename from boards/arm/stm32g081b_eval/stm32g081b_eval.yaml rename to boards/st/stm32g081b_eval/stm32g081b_eval.yaml diff --git a/boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig b/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig similarity index 85% rename from boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig rename to boards/st/stm32g081b_eval/stm32g081b_eval_defconfig index cccb164bbcde7f..2554c25669715e 100644 --- a/boards/arm/stm32g081b_eval/stm32g081b_eval_defconfig +++ b/boards/st/stm32g081b_eval/stm32g081b_eval_defconfig @@ -2,9 +2,6 @@ # # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32G0X=y -CONFIG_SOC_STM32G081XX=y - # Serial Drivers CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y diff --git a/boards/st/stm32h573i_dk/Kconfig.defconfig b/boards/st/stm32h573i_dk/Kconfig.defconfig new file mode 100644 index 00000000000000..b3a733436a9ec9 --- /dev/null +++ b/boards/st/stm32h573i_dk/Kconfig.defconfig @@ -0,0 +1,17 @@ +# STM32H573I DISCOVERY KIT board configuration +# +# Copyright (c) 2023 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if BOARD_STM32H573I_DK + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +endif # BOARD_STM32H573I_DK diff --git a/boards/st/stm32h573i_dk/Kconfig.stm32h573i_dk b/boards/st/stm32h573i_dk/Kconfig.stm32h573i_dk new file mode 100644 index 00000000000000..633e537e078f56 --- /dev/null +++ b/boards/st/stm32h573i_dk/Kconfig.stm32h573i_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H573I_DK + select SOC_STM32H573XX diff --git a/boards/arm/stm32h573i_dk/arduino_r3_connector.dtsi b/boards/st/stm32h573i_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h573i_dk/arduino_r3_connector.dtsi rename to boards/st/stm32h573i_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32h573i_dk/board.cmake b/boards/st/stm32h573i_dk/board.cmake similarity index 100% rename from boards/arm/stm32h573i_dk/board.cmake rename to boards/st/stm32h573i_dk/board.cmake diff --git a/boards/st/stm32h573i_dk/board.yml b/boards/st/stm32h573i_dk/board.yml new file mode 100644 index 00000000000000..e6a08a9197f31b --- /dev/null +++ b/boards/st/stm32h573i_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h573i_dk + vendor: st + socs: + - name: stm32h573xx diff --git a/boards/arm/stm32h573i_dk/doc/img/stm32h573i_dk.jpg b/boards/st/stm32h573i_dk/doc/img/stm32h573i_dk.jpg similarity index 100% rename from boards/arm/stm32h573i_dk/doc/img/stm32h573i_dk.jpg rename to boards/st/stm32h573i_dk/doc/img/stm32h573i_dk.jpg diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst new file mode 100644 index 00000000000000..f7e0a7adbbe056 --- /dev/null +++ b/boards/st/stm32h573i_dk/doc/index.rst @@ -0,0 +1,326 @@ +.. _stm32h573i_dk_board: + +ST STM32H573I-DK Discovery +########################## + +Overview +******** + +The STM32H573I-DK Discovery kit is designed as a complete demonstration and +development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based +STM32H573IIK3Q microcontroller with TrustZone |reg|. Here are some highlights of +the STM32H573I-DK Discovery board: + + +- STM32H573IIK3Q microcontroller featuring 2 Mbytes of Flash memory and 640 Kbytes of SRAM in 176-pin BGA package +- 1.54-inch 240x240 pixels TFT-LCD with LED backlight and touch panel +- USB Type-C |trade| Host and device with USB power-delivery controller +- SAI Audio DAC stereo with one audio jacks for input/output, +- ST MEMS digital microphone with PDM interface +- Octo-SPI interface connected to 512Mbit Octo-SPI NORFlash memory device (MX25LM51245GXDI00 from MACRONIX) +- 10/100-Mbit Ethernet, +- microSD |trade| +- A Wi‑Fi® add-on board +- Board connectors + + - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors + - Pmod |trade| expansion connector + - Audio MEMS daughterboard expansion connector + - ARDUINO |reg| Uno V3 expansion connector + +- Flexible power-supply options + + - ST-LINK + - USB VBUS + - external sources + +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: + + - mass storage + - Virtual COM port + - debug port + +- 4 user LEDs +- User and reset push-buttons + +.. image:: img/stm32h573i_dk.jpg + :align: center + :alt: STM32H573I-DK Discovery + +More information about the board can be found at the `STM32H573I-DK Discovery website`_. + +Hardware +******** + +The STM32H573xx devices are an high-performance microcontrollers family (STM32H5 +Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. +They operate at a frequency of up to 250 MHz. + +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 375 DMPIS/MHz (Dhrystone 2.1) + +- Security + + - Arm |reg| TrustZone |reg| with ARMv8-M mainline security extension + - Up to 8 configurable SAU regions + - TrustZone |reg| aware and securable peripherals + - Flexible lifecycle scheme with secure debug authentication + - Preconfigured immutable root of trust (ST-iROT) + - SFI (secure firmware installation) + - Secure data storage with hardware unique key (HUK) + - Secure firmware upgrade support with TF-M + - 2x AES coprocessors including one with DPA resistance + - Public key accelerator, DPA resistant + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - True random number generator, NIST SP800-90B compliant + - 96-bit unique ID + - Active tampers + - True Random Number Generator (RNG) NIST SP800-90B compliant + +- Clock management: + + - 25 MHz crystal oscillator (HSE) + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 64 MHz (HSI) trimmable by software + - Internal low-power 32 kHz RC (LSI)( |plusminus| 5%) + - Internal 4 MHz oscillator (CSI), trimmable by software + - Internal 48 MHz (HSI48) with recovery system + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + +- RTC with HW calendar, alarms and calibration +- Up to 139 fast I/Os, most 5 V-tolerant, up to 10 I/Os with independent supply down to 1.08 V +- Up to 16 timers and 2 watchdogs + + - 12x 16-bit + - 2x 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input + - 6x 16-bit low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- Memories + + - Up to 2 MB Flash, 2 banks read-while-write + - 1 Kbyte OTP (one-time programmable) + - 640 KB of SRAM including 64 KB with hardware parity check and 320 Kbytes with flexible ECC + - 4 Kbytes of backup SRAM available in the lowest power modes + - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories + - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats + - 2x SD/SDIO/MMC interfaces + +- Rich analog peripherals (independent supply) + + - 2x 12-bit ADC with up to 5 MSPS in 12-bit + - 2x 12-bit D/A converters + - 1x Digital temperature sensor + +- 34x communication interfaces + + - 1x USB Type-C / USB power-delivery controller + - 1x USB 2.0 full-speed host and device + - 4x I2C FM+ interfaces (SMBus/PMBus) + - 1x I3C interface + - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control) + - 1x LP UART + - 6x SPIs including 3 muxed with full-duplex I2S + - 5x additional SPI from 5x USART when configured in Synchronous mode + - 2x SAI + - 2x FDCAN + - 1x SDMMC interface + - 2x 16 channel DMA controllers + - 1x 8- to 14- bit camera interface + - 1x HDMI-CEC + - 1x Ethernel MAC interface with DMA controller + - 1x 16-bit parallel slave synchronous-interface + +- CORDIC for trigonometric functions acceleration +- FMAC (filter mathematical accelerator) +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32H573 can be found here: + +- `STM32H573 on www.st.com`_ +- `STM32H573 reference manual`_ + +Supported Features +================== + +The Zephyr STM32H573I_DK board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi bus | ++-----------+------------+-------------------------------------+ +| OCTOSPI | on-chip | octospi | ++-----------+------------+-------------------------------------+ +| CAN | on-chip | can bus | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| USB | on-chip | USB full-speed host/device bus | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Secure target: + + - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk_defconfig` + - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk.dts` + +Zephyr board options +==================== + +The STM32H573 is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for Secure firmware. + +The BOARD options are summarized below: + ++----------------------+-----------------------------------------------+ +| BOARD | Description | ++======================+===============================================+ +| stm32h573i_dk | For building Secure firmware | ++----------------------+-----------------------------------------------+ + +Connections and IOs +=================== + +STM32H573I-DK Discovery Board has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H573I-DK Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX/RX : PA9/PA10 (VCP) +- USART_3 TX/RX : PB11/PB10 (Arduino USART3) +- USER_PB : PC13 +- LD1 (green) : PI9 +- DAC1 channel 1 output : PA4 +- ADC1 channel 6 input : PF12 + +System Clock +------------ + +STM32H573I-DK System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +240MHz, driven by 25MHz external oscillator (HSE). + +Serial Port +----------- + +STM32H573I-DK Discovery board has 3 U(S)ARTs. The Zephyr console output is +assigned to USART1. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32h573i_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool +interface. Support is available on STM32CubeProgrammer V2.13.0. + +Alternatively, this interface will be supported by a next openocd version. + +Flashing an application to STM32H573I-DK Discovery +-------------------------------------------------- + +Connect the STM32H573I-DK Discovery to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h573i_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32h573i_dk + +Debugging +========= + +Waiting for openocd support, debugging could be performed with pyocd which +requires to enable "pack" support with the following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32h5 + +Once installed, you can debug an application in the usual way. Here is an +example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h573i_dk + :maybe-skip-config: + :goals: debug + +.. _STM32H573I-DK Discovery website: + https://www.st.com/en/evaluation-tools/stm32h573i-dk.html + +.. _STM32H573I-DK Discovery board User Manual: + https://www.st.com/en/evaluation-tools/stm32h573i-dk.html + +.. _STM32H573 on www.st.com: + https://www.st.com/en/microcontrollers/stm32h573ii.html + +.. _STM32H573 reference manual: + https://www.st.com/resource/en/reference_manual/rm0481-stm32h563h573-and-stm32h562-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts similarity index 100% rename from boards/arm/stm32h573i_dk/stm32h573i_dk.dts rename to boards/st/stm32h573i_dk/stm32h573i_dk.dts diff --git a/boards/arm/stm32h573i_dk/stm32h573i_dk.yaml b/boards/st/stm32h573i_dk/stm32h573i_dk.yaml similarity index 100% rename from boards/arm/stm32h573i_dk/stm32h573i_dk.yaml rename to boards/st/stm32h573i_dk/stm32h573i_dk.yaml diff --git a/boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig b/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig similarity index 87% rename from boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig rename to boards/st/stm32h573i_dk/stm32h573i_dk_defconfig index a8050bc4e82167..c112d04baa0fc9 100644 --- a/boards/arm/stm32h573i_dk/stm32h573i_dk_defconfig +++ b/boards/st/stm32h573i_dk/stm32h573i_dk_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2023 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H5X=y -CONFIG_SOC_STM32H573XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/st/stm32h735g_disco/Kconfig.defconfig b/boards/st/stm32h735g_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..9c3777487a37cc --- /dev/null +++ b/boards/st/stm32h735g_disco/Kconfig.defconfig @@ -0,0 +1,19 @@ +# STM32H735G DISCOVERY board configuration + +# Copyright (c) 2021 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H735G_DISCO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_STM32H735G_DISCO diff --git a/boards/st/stm32h735g_disco/Kconfig.stm32h735g_disco b/boards/st/stm32h735g_disco/Kconfig.stm32h735g_disco new file mode 100644 index 00000000000000..f2284afee88e34 --- /dev/null +++ b/boards/st/stm32h735g_disco/Kconfig.stm32h735g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2021 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H735G_DISCO + select SOC_STM32H735XX diff --git a/boards/st/stm32h735g_disco/board.cmake b/boards/st/stm32h735g_disco/board.cmake new file mode 100644 index 00000000000000..b4beb22525d63c --- /dev/null +++ b/boards/st/stm32h735g_disco/board.cmake @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2021 SILA Embedded Solutions GmbH + +board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h735g_disco/board.yml b/boards/st/stm32h735g_disco/board.yml new file mode 100644 index 00000000000000..146a622647e0ab --- /dev/null +++ b/boards/st/stm32h735g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h735g_disco + vendor: st + socs: + - name: stm32h735xx diff --git a/boards/arm/stm32h735g_disco/doc/img/stm32h735g_disco.jpg b/boards/st/stm32h735g_disco/doc/img/stm32h735g_disco.jpg similarity index 100% rename from boards/arm/stm32h735g_disco/doc/img/stm32h735g_disco.jpg rename to boards/st/stm32h735g_disco/doc/img/stm32h735g_disco.jpg diff --git a/boards/st/stm32h735g_disco/doc/index.rst b/boards/st/stm32h735g_disco/doc/index.rst new file mode 100644 index 00000000000000..bf7605d77668b6 --- /dev/null +++ b/boards/st/stm32h735g_disco/doc/index.rst @@ -0,0 +1,152 @@ +.. _stm32h735g_disco_board: + +ST STM32H735G Discovery +####################### + +Overview +******** + +The STM32H735G-DK Discovery kit is a complete demonstration and development +platform for Arm® Cortex®-M7 core-based STM32H735IGK6U microcontroller, with +1 Mbyte of Flash memory and 564 Kbytes of SRAM. + +The STM32H735G-DK Discovery kit is used as a reference design for user +application development before porting to the final product, thus simplifying +the application development. + +The full range of hardware features available on the board helps users to enhance +their application development by an evaluation of all the peripherals (such as +USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with +audio jack input and output, MEMS digital microphone, HyperRAM™, +Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). +ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension +shields or daughterboards for specific applications. + +STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and +programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H735G-DK board +comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive +software HAL library as well as various software examples. + +.. image:: img/stm32h735g_disco.jpg + :align: center + :alt: STM32H735G-DISCO + +More information about the board can be found at the `STM32H735G-DISCO website`_. +More information about STM32H735 can be found here: + +- `STM32H725/735 on www.st.com`_ +- `STM32H735xx reference manual`_ +- `STM32H735xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h735g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| FDCAN1 | on-chip | CAN-FD Controller | ++-----------+------------+-------------------------------------+ +| FDCAN2 | on-chip | CAN-FD Controller | ++-----------+------------+-------------------------------------+ +| FDCAN2 | on-chip | CAN-FD Controller (disabled by | +| | | default. Solder bridges SB29 and | +| | | SB30 need to be closed for FDCAN3 | +| | | to work) | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32h735g_disco/stm32h735g_disco_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32H735G-DISCO website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PD8/PD9 (ST-Link Virtual Port Com) +- UART_7 TX/RX : PF7/PF6 (Arduino Serial) +- LD1 : PC2 +- LD2 : PC3 +- FDCAN1 : CAN + +System Clock +============ + +The STM32H735G System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock +is driven by the PLL clock at 550MHz. PLL clock is feed by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32H735G Discovery kit has up to 6 UARTs. +The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual +COM port interface. Default communication settings are 115200 8N1. + + +Programming and Debugging +************************* + +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration and flash the ``stm32h735g_disco`` target. + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h735g_disco + :goals: debug + + +.. _STM32H735G-DISCO website: + https://www.st.com/en/evaluation-tools/stm32h735g-dk.html + +.. _STM32H725/735 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h725-735.html + +.. _STM32H735xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00603761-stm32h723733-stm32h725735-and-stm32h730-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H735xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h735ag.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32h735g_disco/pmod_connector.dtsi b/boards/st/stm32h735g_disco/pmod_connector.dtsi similarity index 100% rename from boards/arm/stm32h735g_disco/pmod_connector.dtsi rename to boards/st/stm32h735g_disco/pmod_connector.dtsi diff --git a/boards/arm/stm32h735g_disco/stm32h735g_disco.dts b/boards/st/stm32h735g_disco/stm32h735g_disco.dts similarity index 100% rename from boards/arm/stm32h735g_disco/stm32h735g_disco.dts rename to boards/st/stm32h735g_disco/stm32h735g_disco.dts diff --git a/boards/arm/stm32h735g_disco/stm32h735g_disco.yaml b/boards/st/stm32h735g_disco/stm32h735g_disco.yaml similarity index 100% rename from boards/arm/stm32h735g_disco/stm32h735g_disco.yaml rename to boards/st/stm32h735g_disco/stm32h735g_disco.yaml diff --git a/boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig b/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig similarity index 76% rename from boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig rename to boards/st/stm32h735g_disco/stm32h735g_disco_defconfig index d8c7d4e78d0616..fe5e10927298a4 100644 --- a/boards/arm/stm32h735g_disco/stm32h735g_disco_defconfig +++ b/boards/st/stm32h735g_disco/stm32h735g_disco_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H735XX=y +# Copyright (c) 2021 SILA Embedded Solutions GmbH # Enable the internal SMPS regulator CONFIG_POWER_SUPPLY_DIRECT_SMPS=y @@ -14,15 +12,15 @@ CONFIG_HW_STACK_PROTECTION=y CONFIG_SERIAL=y -# console +# Console CONFIG_CONSOLE=y CONFIG_UART_CONSOLE=y -# enable GPIO +# Enable GPIO CONFIG_GPIO=y # Enable Clocks CONFIG_CLOCK_CONTROL=y -# enable pin controller +# Enable pin controller CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h735g_disco/support/openocd.cfg b/boards/st/stm32h735g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32h735g_disco/support/openocd.cfg rename to boards/st/stm32h735g_disco/support/openocd.cfg diff --git a/boards/arm/stm32h747i_disco/CMakeLists.txt b/boards/st/stm32h747i_disco/CMakeLists.txt similarity index 100% rename from boards/arm/stm32h747i_disco/CMakeLists.txt rename to boards/st/stm32h747i_disco/CMakeLists.txt diff --git a/boards/st/stm32h747i_disco/Kconfig.defconfig b/boards/st/stm32h747i_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..68e0fc0b4a01ee --- /dev/null +++ b/boards/st/stm32h747i_disco/Kconfig.defconfig @@ -0,0 +1,18 @@ +# STM32H747I DISCOVERY board configuration + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H747I_DISCO + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32H747I_DISCO diff --git a/boards/st/stm32h747i_disco/Kconfig.stm32h747i_disco b/boards/st/stm32h747i_disco/Kconfig.stm32h747i_disco new file mode 100644 index 00000000000000..8c6309f909a02d --- /dev/null +++ b/boards/st/stm32h747i_disco/Kconfig.stm32h747i_disco @@ -0,0 +1,8 @@ +# STM32H747I DISCOVERY board configuration + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H747I_DISCO + select SOC_STM32H747XX_M7 if BOARD_STM32H747I_DISCO_STM32H747XX_M7 + select SOC_STM32H747XX_M4 if BOARD_STM32H747I_DISCO_STM32H747XX_M4 diff --git a/boards/arm/stm32h747i_disco/arduino_r3_connector.dtsi b/boards/st/stm32h747i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h747i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32h747i_disco/arduino_r3_connector.dtsi diff --git a/boards/st/stm32h747i_disco/board.cmake b/boards/st/stm32h747i_disco/board.cmake new file mode 100644 index 00000000000000..93b40d3634d376 --- /dev/null +++ b/boards/st/stm32h747i_disco/board.cmake @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 STMicroelectronics + +if(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7) + board_runner_args(jlink "--device=STM32H747ZI_M7") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m7.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +elseif(CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4) + board_runner_args(jlink "--device=STM32H747ZI_M4") + board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h747i_disco_m4.cfg") + board_runner_args(openocd --target-handle=_CHIPNAME.cpu1) +endif() +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/st/stm32h747i_disco/board.yml b/boards/st/stm32h747i_disco/board.yml new file mode 100644 index 00000000000000..431d3e4f486202 --- /dev/null +++ b/boards/st/stm32h747i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h747i_disco + vendor: st + socs: + - name: stm32h747xx diff --git a/boards/arm/stm32h747i_disco/dc_ram.ld b/boards/st/stm32h747i_disco/dc_ram.ld similarity index 100% rename from boards/arm/stm32h747i_disco/dc_ram.ld rename to boards/st/stm32h747i_disco/dc_ram.ld diff --git a/boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg b/boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg similarity index 100% rename from boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg rename to boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_1.jpg diff --git a/boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg b/boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg similarity index 100% rename from boards/arm/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg rename to boards/st/stm32h747i_disco/doc/img/disco_h747i_ethernet_modification_2.jpg diff --git a/boards/arm/stm32h747i_disco/doc/img/stm32h747i_disco.jpg b/boards/st/stm32h747i_disco/doc/img/stm32h747i_disco.jpg similarity index 100% rename from boards/arm/stm32h747i_disco/doc/img/stm32h747i_disco.jpg rename to boards/st/stm32h747i_disco/doc/img/stm32h747i_disco.jpg diff --git a/boards/st/stm32h747i_disco/doc/index.rst b/boards/st/stm32h747i_disco/doc/index.rst new file mode 100644 index 00000000000000..1f6846d6815bc4 --- /dev/null +++ b/boards/st/stm32h747i_disco/doc/index.rst @@ -0,0 +1,314 @@ +.. _stm32h747i_disco_board: + +ST STM32H747I Discovery +####################### + +Overview +******** + +The discovery kit enables a wide diversity of applications taking benefit +from audio, multi-sensor support, graphics, security, video, +and high-speed connectivity features. + +The board includes an STM32H747XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU, +with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface, +large set of peripherals, SMPS, and MIPI-DSI. + +Additionally, the board features: + +- On-board ST-LINK/V3E supporting USB reenumeration capability +- USB ST-LINK functions: virtual COM port, mass storage, debug port +- Flexible power-supply options: + + - ST-LINK USB VBUS, USB OTG HS connector, or external sources + +- 4” capacitive touch LCD display module with MIPI® DSI interface +- Ethernet compliant with IEEE802.3-2002 +- USB OTG HS +- Stereo speaker outputs +- ST-MEMS digital microphones +- 2 x 512-Mbit QUAD-SPI NOR Flash memory +- 256-Mbit SDRAM +- 4 color user LEDs +- 1 user and reset push-button +- 4-direction joystick with selection button +- Arduino Uno V3 connectors + +.. image:: img/stm32h747i_disco.jpg + :align: center + :alt: STM32H747I-DISCO + +More information about the board can be found at the `STM32H747I-DISCO website`_. +More information about STM32H747XIH6 can be found here: + +- `STM32H747XI on www.st.com`_ +- `STM32H747xx reference manual`_ +- `STM32H747xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h747i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet (*) | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| IPM | on-chip | virtual mailbox based on HSEM | ++-----------+------------+-------------------------------------+ +| DISPLAY | on-chip | MIPI DSI Host with shield (MP1166) | +| | | st_b_lcd40_dsi1_mb1166 | ++-----------+------------+-------------------------------------+ + +(*) From UM2411 Rev 4: + With the default setting, the Ethernet feature is not working because of + a conflict between ETH_MDC and SAI4_D1 of the MEMs digital microphone. + Make sure you have SB8 closed and SB21 open to get Ethernet working. + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration per core can be found in the defconfig files: +:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig` and +:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig` + +Pin Mapping +=========== + +STM32H747I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32H747I-DISCO website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- UART_8 TX/RX : PJ8/PJ9 (Arduino Serial) +- SPI_5 NSS/SCK/MISO/MOSI : PK1/PK0/PJ11/PJ10 (Arduino SPI) +- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 +- LD1 : PI12 +- LD2 : PI13 +- LD3 : PI14 +- LD4 : PI15 +- W-UP : PC13 +- J-CENTER : PK2 +- J-DOWN : PK3 +- J-LEFT : PK4 +- J-RIGHT : PK5 +- J-UP : PK6 + +System Clock +============ + +The STM32H747I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock +is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock +is driven at 200MHz. PLL clock is feed by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32H747I Discovery kit has up to 8 UARTs. +Default configuration assigns USART1 and UART8 to the CPU1. The Zephyr console +output is assigned to UART1 which connected to the onboard ST-LINK/V3.0. Virtual +COM port interface. Default communication settings are 115200 8N1. + +Ethernet +======== + +**Disclaimer:** This section is mostly copy-paste of corresponding +`DISCO_H747I modifications for Ethernet`_ mbed blog post. The author of this +article sincerely allowed to use the images and his knowledge about necessary +HW modifications to get Ethernet working with this board. + +To get Ethernet working following HW modifications are required: + +- **SB21**, **SB45** and **R87** should be opened +- **SB22**, **SB44**, **SB17** and **SB8** should be closed + +Following two images shows necessary changes on the board marked: + +.. image:: img/disco_h747i_ethernet_modification_1.jpg + :align: center + :alt: STM32H747I-DISCO - Ethernet modification 1 (**SB44**, **SB45**) + +.. image:: img/disco_h747i_ethernet_modification_2.jpg + :align: center + :alt: STM32H747I-DISCO - Ethernet modification 2 (**SB21**, **R87**, **SB22**, **SB17** and **SB8**) + +Display +======= + +The STM32H747I Discovery kit has a dedicated DSI LCD connector **CN15**, where +the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display +support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` to your build +command, for example: + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/display + :board: stm32h747i_disco/stm32h747xx/m7 + :shield: st_b_lcd40_dsi1_mb1166 + :goals: build flash + +.. note:: + Currently only the older version MB1166-A03 is supported by Zephyr. + The newer version MB1166-A09 does not get initialized correctly (see :github:`60888`). + +Resources sharing +================= + +The dual core nature of STM32H747 SoC requires sharing HW resources between the +two cores. This is done in 3 ways: + +- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only + has access to bus clock activation and deactivation. +- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in + devicetree before compilation. The user must ensure peripherals are not assigned + to both cores at the same time. +- **Run time protection**: Interrupt-controller and GPIO configurations could be + accessed by both cores at run time. Accesses are protected by a hardware semaphore + to avoid potential concurrent access issues. + +Programming and Debugging +************************* + +Applications for the ``stm32h747i_disco`` board should be built per core target, +using either ``stm32h747i_disco/stm32h747xx/m7`` or ```stm32h747i_disco/stm32h747xx/m4`` as the target. +See :ref:`build_an_application` for more information about application builds. + +.. note:: + + If using OpenOCD you will need a recent development version as the last + official release does not support H7 dualcore yet. + Also, with OpenOCD, sometimes, flashing is not working. It is necessary to + erase the flash (with STM32CubeProgrammer for example) to make it work again. + Debugging with OpenOCD is currently working for this board only with Cortex M7, + not Cortex M4. + + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration and flash ``stm32h747i_disco/stm32h747xx/m7`` and +``stm32h747i_disco/stm32h747xx/m7`` targets. + +By default: + + - CPU1 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0) + - CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0) + +Also, default out of the box board configuration enables CM7 and CM4 boot when +board is powered (Option bytes BCM7 and BCM4 are checked). +It is possible to change Option Bytes so that CM7 boots first in stand alone, +and CM7 will wakeup CM4 after clock initialization. +Drivers are able to take into account both Option Bytes configurations +automatically. + +Zephyr flash configuration has been set to meet these default settings. + +Alternatively, west `STM32CubeProgrammer`_ runner can be used, after installing +it, to flash applications for both cores. The target core is detected automatically. + +.. code-block:: console + + $ west flash --runner stm32cubeprogrammer + +Flashing an application to STM32H747I M7 Core +--------------------------------------------- + +First, connect the STM32H747I Discovery kit to your host computer using +the USB port to prepare it for flashing. Then build and flash your application. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h747i_disco/stm32h747xx/m7 + :goals: build flash + +Run a serial host program to connect with your board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32h747i_disco + +.. note:: + Sometimes, flashing is not working. It is necessary to erase the flash + (with STM32CubeProgrammer for example) to make it work again. + +Similarly, you can build and flash samples on the M4 target. For this, please +take care of the resource sharing (UART port used for console for instance). + +Here is an example for the :zephyr:code-sample:`blinky` application on M4 core. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32h747i_disco/stm32h747xx/m7 + :goals: build flash + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h747i_disco/stm32h747xx/m7 + :goals: debug + +Debugging with west is currently not available on Cortex M4 side. +In order to debug a Zephyr application on Cortex M4 side, you can use +`STM32CubeIDE`_. + +.. _STM32H747I-DISCO website: + https://www.st.com/en/evaluation-tools/stm32h747i-disco.html + +.. _STM32H747XI on www.st.com: + https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus/stm32-high-performance-mcus/stm32h7-series/stm32h747-757/stm32h747xi.html + +.. _STM32H747xx reference manual: + https://www.st.com/resource/en/reference_manual/dm00176879.pdf + +.. _STM32H747xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h747xi.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _DISCO_H747I modifications for Ethernet: + https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet + +.. _STM32CubeIDE: + https://www.st.com/en/development-tools/stm32cubeide.html diff --git a/boards/arm/stm32h747i_disco/pmod_connector.dtsi b/boards/st/stm32h747i_disco/pmod_connector.dtsi similarity index 100% rename from boards/arm/stm32h747i_disco/pmod_connector.dtsi rename to boards/st/stm32h747i_disco/pmod_connector.dtsi diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco.dtsi b/boards/st/stm32h747i_disco/stm32h747i_disco.dtsi similarity index 100% rename from boards/arm/stm32h747i_disco/stm32h747i_disco.dtsi rename to boards/st/stm32h747i_disco/stm32h747i_disco.dtsi diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m4.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.dts similarity index 100% rename from boards/arm/stm32h747i_disco/stm32h747i_disco_m4.dts rename to boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.dts diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml new file mode 100644 index 00000000000000..2a544e167013a3 --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml @@ -0,0 +1,19 @@ +identifier: stm32h747i_disco/stm32h747xx/m4 +name: ST STM32H747I Discovery (M4) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 288 +flash: 1024 +supported: + - arduino_gpio + - gpio +testing: + ignore_tags: + - mpu + - nfc + - net +vendor: st diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig new file mode 100644 index 00000000000000..9b540e01f63a82 --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 STMicroelectronics + +# Enable GPIO +CONFIG_GPIO=y + +# Clock configuration +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Enable UART driver +CONFIG_SERIAL=y + +# By default CONSOLE is assigned to m7 +#CONFIG_CONSOLE=y +#CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts similarity index 100% rename from boards/arm/stm32h747i_disco/stm32h747i_disco_m7.dts rename to boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml new file mode 100644 index 00000000000000..e4b7d1b33345ab --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml @@ -0,0 +1,21 @@ +identifier: stm32h747i_disco/stm32h747xx/m7 +name: ST STM32H747I Discovery (M7) +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 512 +flash: 1024 +supported: + - arduino_gpio + - gpio + - arduino_spi + - spi + - netif:eth + - qspi + - memc + - usb_cdc + - usb_device +vendor: st diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig new file mode 100644 index 00000000000000..69659b1c01ebd3 --- /dev/null +++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig @@ -0,0 +1,28 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2019 STMicroelectronics + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_DIRECT_SMPS=y + +# Enable GPIO +CONFIG_GPIO=y + +# Enable clocks +CONFIG_CLOCK_CONTROL=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +# Disable following to assign serial ports to m4 core + +# Enable uart driver +CONFIG_SERIAL=y +# Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg b/boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg similarity index 100% rename from boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg rename to boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m4.cfg diff --git a/boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg b/boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg similarity index 100% rename from boards/arm/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg rename to boards/st/stm32h747i_disco/support/openocd_stm32h747i_disco_m7.cfg diff --git a/boards/st/stm32h750b_dk/Kconfig.stm32h750b_dk b/boards/st/stm32h750b_dk/Kconfig.stm32h750b_dk new file mode 100644 index 00000000000000..b141d9d1b9d658 --- /dev/null +++ b/boards/st/stm32h750b_dk/Kconfig.stm32h750b_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H750B_DK + select SOC_STM32H750XX diff --git a/boards/arm/stm32h750b_dk/arduino_r3_connector.dtsi b/boards/st/stm32h750b_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h750b_dk/arduino_r3_connector.dtsi rename to boards/st/stm32h750b_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32h735g_disco/board.cmake b/boards/st/stm32h750b_dk/board.cmake similarity index 100% rename from boards/arm/stm32h735g_disco/board.cmake rename to boards/st/stm32h750b_dk/board.cmake diff --git a/boards/st/stm32h750b_dk/board.yml b/boards/st/stm32h750b_dk/board.yml new file mode 100644 index 00000000000000..95275ee2e426e1 --- /dev/null +++ b/boards/st/stm32h750b_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h750b_dk + vendor: st + socs: + - name: stm32h750xx diff --git a/boards/arm/stm32h750b_dk/doc/img/stm32h750b_dk.png b/boards/st/stm32h750b_dk/doc/img/stm32h750b_dk.png similarity index 100% rename from boards/arm/stm32h750b_dk/doc/img/stm32h750b_dk.png rename to boards/st/stm32h750b_dk/doc/img/stm32h750b_dk.png diff --git a/boards/st/stm32h750b_dk/doc/index.rst b/boards/st/stm32h750b_dk/doc/index.rst new file mode 100644 index 00000000000000..f295947a334451 --- /dev/null +++ b/boards/st/stm32h750b_dk/doc/index.rst @@ -0,0 +1,145 @@ +.. _stm32h750b_dk_board: + +ST STM32H750B Discovery Kit +########################### + +Overview +******** + +The STM32H750B-DK Discovery kit is a complete demonstration and development +platform for Arm® Cortex®-M7 core-based STM32H750XBH6 microcontroller, with +128Kbytes of Flash memory and 1 Mbytes of SRAM. + +The STM32H750B-DK Discovery kit is used as a reference design for user +application development before porting to the final product, thus simplifying +the application development. + +The full range of hardware features available on the board helps users to enhance +their application development by an evaluation of all the peripherals (such as +USB OTG FS, Ethernet, microSD™ card, USART, CAN FD, SAI audio DAC stereo with +audio jack input and output, MEMS digital microphone, HyperRAM™, +Octo-SPI Flash memory, RGB interface LCD with capacitive touch panel, and others). +ARDUINO® Uno V3, Pmod™ and STMod+ connectors provide easy connection to extension +shields or daughterboards for specific applications. + +STLINK-V3E is integrated into the board, as the embedded in-circuit debugger and +programmer for the STM32 MCU and USB Virtual COM port bridge. STM32H750B-DK board +comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive +software HAL library as well as various software examples. + +.. image:: img/stm32h750b_dk.png + :align: center + :alt: STM32H750B-DK + +More information about the board can be found at the `STM32H750B-DK website`_. +More information about STM32H750 can be found here: + +- `STM32H750 on www.st.com`_ +- `STM32H750xx reference manual`_ +- `STM32H750xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h750b_dk board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32h750b_dk/stm32h750b_dk_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32H750B-DK website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_3 TX/RX : PB10/PB11 (ST-Link Virtual Port Com) +- LD1 : PJ2 +- LD2 : PI13 + +System Clock +============ + +The STM32H750B System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock +is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock. + +Serial Port +=========== + +The STM32H750B Discovery kit has up to 6 UARTs. +The Zephyr console output is assigned to UART3 which connected to the onboard ST-LINK/V3.0. Virtual +COM port interface. Default communication settings are 115200 8N1. + + +Programming and Debugging +************************* + +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Connect the STM32H750B-DK to your host computer using the ST-LINK +USB port, then run a serial host program to connect with the board. For example: + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +You can then build and flash applications in the usual way. +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h750b_dk + :goals: build flash + +You should see the following message in the serial host program: + +.. code-block:: console + + $ Hello World! stm32h750b_dk + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h750b_dk + :goals: debug + + +.. _STM32H750B-DK website: + https://www.st.com/en/evaluation-tools/stm32h750b-dk.html + +.. _STM32H750 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html + +.. _STM32H750xx reference manual: + https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H750xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h750ib.pdf diff --git a/boards/arm/stm32h750b_dk/stm32h750b_dk.dts b/boards/st/stm32h750b_dk/stm32h750b_dk.dts similarity index 100% rename from boards/arm/stm32h750b_dk/stm32h750b_dk.dts rename to boards/st/stm32h750b_dk/stm32h750b_dk.dts diff --git a/boards/arm/stm32h750b_dk/stm32h750b_dk.yaml b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml similarity index 100% rename from boards/arm/stm32h750b_dk/stm32h750b_dk.yaml rename to boards/st/stm32h750b_dk/stm32h750b_dk.yaml diff --git a/boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig b/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig similarity index 88% rename from boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig rename to boards/st/stm32h750b_dk/stm32h750b_dk_defconfig index 64cab9ff714377..08add3eb2c6bca 100644 --- a/boards/arm/stm32h750b_dk/stm32h750b_dk_defconfig +++ b/boards/st/stm32h750b_dk/stm32h750b_dk_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2023 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H750XX=y - # Enable the internal SMPS regulator CONFIG_POWER_SUPPLY_LDO=y diff --git a/boards/arm/stm32h750b_dk/support/openocd.cfg b/boards/st/stm32h750b_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32h750b_dk/support/openocd.cfg rename to boards/st/stm32h750b_dk/support/openocd.cfg diff --git a/boards/st/stm32h7b3i_dk/Kconfig.defconfig b/boards/st/stm32h7b3i_dk/Kconfig.defconfig new file mode 100644 index 00000000000000..39101c47f7b6b3 --- /dev/null +++ b/boards/st/stm32h7b3i_dk/Kconfig.defconfig @@ -0,0 +1,19 @@ +# STM32H7B3I DISCOVERY KIT board configuration + +# Copyright (c) 2022 Byte-Lab d.o.o. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32H7B3I_DK + +config INPUT + default y if LVGL + +config INPUT_FT5336_INTERRUPT + default y if INPUT_FT5336 + +# MEMC needs to be enabled in order to store +# display buffer to external SDRAM connected to FMC +config MEMC + default y if DISPLAY + +endif # BOARD_STM32H7B3I_DK diff --git a/boards/st/stm32h7b3i_dk/Kconfig.stm32h7b3i_dk b/boards/st/stm32h7b3i_dk/Kconfig.stm32h7b3i_dk new file mode 100644 index 00000000000000..c243bf05acd7bd --- /dev/null +++ b/boards/st/stm32h7b3i_dk/Kconfig.stm32h7b3i_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Byte-Lab d.o.o. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32H7B3I_DK + select SOC_STM32H7B3XXQ diff --git a/boards/arm/stm32h7b3i_dk/arduino_r3_connector.dtsi b/boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32h7b3i_dk/arduino_r3_connector.dtsi rename to boards/st/stm32h7b3i_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32h7b3i_dk/board.cmake b/boards/st/stm32h7b3i_dk/board.cmake similarity index 100% rename from boards/arm/stm32h7b3i_dk/board.cmake rename to boards/st/stm32h7b3i_dk/board.cmake diff --git a/boards/st/stm32h7b3i_dk/board.yml b/boards/st/stm32h7b3i_dk/board.yml new file mode 100644 index 00000000000000..5516412eac9342 --- /dev/null +++ b/boards/st/stm32h7b3i_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32h7b3i_dk + vendor: st + socs: + - name: stm32h7b3xx diff --git a/boards/arm/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg b/boards/st/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg similarity index 100% rename from boards/arm/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg rename to boards/st/stm32h7b3i_dk/doc/img/stm32h7b3i_dk.jpg diff --git a/boards/st/stm32h7b3i_dk/doc/index.rst b/boards/st/stm32h7b3i_dk/doc/index.rst new file mode 100644 index 00000000000000..98f00c342348c6 --- /dev/null +++ b/boards/st/stm32h7b3i_dk/doc/index.rst @@ -0,0 +1,171 @@ +.. _stm32h7b3i_dk_board: + +ST STM32H7B3I Discovery Kit +########################### + +Overview +******** + +The STM32H7B3I-DK Discovery kit is a complete demonstration and development +platform for STMicroelectronics Arm® Cortex®-M7 core-based STM32H7B3LIH6QU +microcontroller. + +The STM32H7B3I-DK Discovery kit is used as a reference design for user +application development before porting to the final product, thus simplifying +the application development. + +The full range of hardware features available on the board helps users enhance +their application development by an evaluation of almost all peripherals (such as +USB OTG_HS, microSD, USART, FDCAN, audio DAC stereo with audio jack input and output, +camera, SDRAM, Octo-SPI Flash memory and RGB interface LCD with capacitive touch +panel). ARDUINO® Uno V3 connectors provide easy connection to extension shields or +daughterboards for specific applications. + +STLINK-V3E is integrated into the board, as an embedded in-circuit debugger and +programmer for the STM32 MCU and the USB Virtual COM port bridge. The STM32H7B3I-DK +board comes with the STM32CubeH7 MCU Package, which provides an STM32 comprehensive +software HAL library as well as various software examples. + +.. image:: img/stm32h7b3i_dk.jpg + :align: center + :alt: STM32H7B3I-DK + +More information about the board can be found at the `STM32H7B3I-DK website`_. +More information about STM32H7B3 can be found here: + +- `STM32H7A3/7B3 on www.st.com`_ +- `STM32H7A3/7B3/7B0 reference manual`_ +- `STM32H7B3xI datasheet`_ + +Supported Features +================== + +The current Zephyr stm32h7b3i_dk board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| FMC | on-chip | memc (SDRAM) | ++-----------+------------+-------------------------------------+ +| LTDC | on-chip | display | ++-----------+------------+-------------------------------------+ +| CANFD | on-chip | can | ++-----------+------------+-------------------------------------+ + + +Other hardware features have not been enabled yet for this board. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32H7B3I-DK website`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- UART_4 TX/RX : PH13/PH14 (Arduino Serial) +- I2C4 SCL/SDA : PD12/PD13 (Arduino I2C, Touchscreen FT5336 with PH2 Interrupt Pin) +- SPI2 SCK/MISO/MOSI/NSS : PA12/PB14/PB15/PI0 (Arduino SPI) +- LD1 : PG11 +- LD2 : PG2 +- USER_PB : PC13 +- SDMMC D0/D1/D2/D3/CK/CMD/CD : PC8/PC9/PC10/PC11/PC12/PD2/PI8 +- CANFD RX/TX/WAKE [#]_ : PA11/PA12/PH8 +- FMC SDRAM : + + - D0-D15 : PD14/PD15/PD0/PD1/PE7/PE8/PE9/PE10/PE11/PE12/PE13/PE14/PE15/PD8/PD9/PD10 + - A0-A11 : PF0/PF1/PF2/PF3/PF4/PF5/PF12/PF13/PF14/PF15/PG0/PG1 + - A14/A15 : PG4/PG5 + - SDNRAS/SDNCAS : PF11/PG15 + - NBL0/NBL1 : PE0/PE1 + - SDCLK/SDNWE/SDCKE1/SDNE1 : PG8/PH5/PH7/PH6 + +- LTDC : + + - R0-R7 : PI15/PJ0/PJ1/PJ2/PJ3/PJ4/PJ5/PJ6 + - G0-G7 : PJ7/PJ8/PJ9/PJ10/PJ11/PK0/PK1/PK2 + - B0-B7 : PJ12/PK13/PJ14/PJ15/PK3/PK4/PK5/PK6 + - DE/CLK/HSYNC/VSYNC : PK7/PI14/PI12/PI13 + + +System Clock +============ + +The STM32H7B3I System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven +by the PLL clock at 280MHz. PLL clock is fed by a 24MHz high speed external clock. + +Serial Port +=========== + +The STM32H7B3I Discovery kit has up to 8 UARTs. +The Zephyr console output is assigned to UART1 which connected to the onboard +ST-LINK/V3.0. Virtual COM port interface. Default communication settings are +115200 8N1. + + +Programming and Debugging +************************* + +See :ref:`build_an_application` for more information about application builds. + + +Flashing +======== + +Flashing operation will depend on the target to be flashed and the SoC +option bytes configuration. +It is advised to use `STM32CubeProgrammer`_ to check and update option bytes +configuration and flash the ``stm32h7b3i_dk`` target. + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32h7b3i_dk + :goals: debug + + +.. _STM32H7B3I-DK website: + https://www.st.com/en/evaluation-tools/stm32h7b3i-dk.html + +.. _STM32H7A3/7B3 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3-7b3.html + +.. _STM32H7A3/7B3/7B0 reference manual: + https://www.st.com/resource/en/reference_manual/rm0455-stm32h7a37b3-and-stm32h7b0-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H7B3xI datasheet: + https://www.st.com/resource/en/datasheet/stm32h7b3ai.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STM32H7B3I_DK board schematics: + https://www.st.com/resource/en/schematic_pack/mb1332-h7b3i-c02_schematic.pdf + +.. [#] To use CAN, solder bridges SB3, SB4 and SB5 need to be connected. + Take note that CANFD pins are shared with STMOD+ connector (P1), so please check + `STM32H7B3I_DK board schematics`_ for possible collisions if using that connector. diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts similarity index 100% rename from boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.dts rename to boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.yaml b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml similarity index 100% rename from boards/arm/stm32h7b3i_dk/stm32h7b3i_dk.yaml rename to boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml diff --git a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig similarity index 89% rename from boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig rename to boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig index 913a1ed5dbd6ef..bb3b8c0178c6a8 100644 --- a/boards/arm/stm32h7b3i_dk/stm32h7b3i_dk_defconfig +++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig @@ -2,9 +2,6 @@ # SPDX-License-Identifier: Apache-2.0 # Set SoC present on the board -CONFIG_SOC_SERIES_STM32H7X=y -CONFIG_SOC_STM32H7B3XXQ=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32h7b3i_dk/support/openocd.cfg b/boards/st/stm32h7b3i_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32h7b3i_dk/support/openocd.cfg rename to boards/st/stm32h7b3i_dk/support/openocd.cfg diff --git a/boards/st/stm32l1_disco/Kconfig.stm32l1_disco b/boards/st/stm32l1_disco/Kconfig.stm32l1_disco new file mode 100644 index 00000000000000..9e1e0bb01a45a8 --- /dev/null +++ b/boards/st/stm32l1_disco/Kconfig.stm32l1_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2019 eTactica ehf +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L1_DISCO + select SOC_STM32L151XB diff --git a/boards/arm/stm32l1_disco/board.cmake b/boards/st/stm32l1_disco/board.cmake similarity index 100% rename from boards/arm/stm32l1_disco/board.cmake rename to boards/st/stm32l1_disco/board.cmake diff --git a/boards/st/stm32l1_disco/board.yml b/boards/st/stm32l1_disco/board.yml new file mode 100644 index 00000000000000..bdca72bf548187 --- /dev/null +++ b/boards/st/stm32l1_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l1_disco + vendor: st + socs: + - name: stm32l151xb diff --git a/boards/arm/stm32l1_disco/doc/img/stm32l1_disco.jpg b/boards/st/stm32l1_disco/doc/img/stm32l1_disco.jpg similarity index 100% rename from boards/arm/stm32l1_disco/doc/img/stm32l1_disco.jpg rename to boards/st/stm32l1_disco/doc/img/stm32l1_disco.jpg diff --git a/boards/st/stm32l1_disco/doc/index.rst b/boards/st/stm32l1_disco/doc/index.rst new file mode 100644 index 00000000000000..a3b4a30bdfa007 --- /dev/null +++ b/boards/st/stm32l1_disco/doc/index.rst @@ -0,0 +1,179 @@ +.. _stm32l1_disco_board: + +ST STM32L1 Discovery +#################### + +Overview +******** + +The two generations of the STM32L1 Discovery development boards come with +an integrated ST-LINK/V2 debugger and programmer. The boards have a +24-segment LCD and a touch slider, along with two user LEDs and a user button. +Support circuitry for measuring power consumption is also available. +It also comes with a comprehensive STM32 software HAL library and various +packaged software examples. + +There +are two variants of the board: + +- STM32LDISCOVERY targets STM32L152RBT6, with 128K flash, 16K RAM +- 32L152CDISCOVERY targets STM32L152RCT6, with 256K flash, 32K RAM + +The STM32LDISCOVERY is no longer sold, but was widely available. The current +configuration assumes only 128K flash and 16K RAM, so it builds and runs +on both variants out of the box. + +.. image:: img/stm32l1_disco.jpg + :align: center + :alt: STM32LDISCOVERY + +More information about the board can be found at the `STM32LDISCOVERY website`_. + +Hardware +******** + +The STM32 Discovery board features: + +- On-board ST-LINK/V2 with selection mode switch to use the kit as a standalone + ST-LINK/V2 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- Four LEDs: + + - LD1 (red) for 3.3 V power on + - LD2 (red/green) for USB communication + - LD3 (green) for PC9 output + - LD4 (blue) for PC8 output +- Two push buttons (user and reset) +- Extension header for all LQFP64 I/Os for quick connection to prototyping board + and easy probing + +More information about STM32L151x can be found in the `STM32L1x reference manual`_. + +Supported Features +================== + +The Zephyr stm32l1_disco board configuration supports the following hardware features: + +.. list-table:: Supported hardware + :header-rows: 1 + + * - Interface + - Controller + - Driver/component + * - NVIC + - on-chip + - nested vector interrupt controller + * - UART + - on-chip + - serial port-polling + serial port-interrupt + * - PINMUX + - on-chip + - pinmux + * - GPIO + - on-chip + - gpio + * - CLOCK + - on-chip + - reset and clock control + * - FLASH + - on-chip + - flash memory + * - WATCHDOG + - on-chip + - window watchdog + * - I2C + - on-chip + - i2c + * - SPI + - on-chip + - spi + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32l1_disco/stm32l1_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB11 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 + +For more details please refer to `STM32L1DISCOVERY board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32l1_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32L1DISCOVERY board includes an ST-LINK/V2 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application +----------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32l1_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32l1_disco + :maybe-skip-config: + :goals: debug + +References +********** + +.. target-notes:: + +.. _STM32LDISCOVERY website: + https://www.st.com/en/evaluation-tools/32l152cdiscovery.html + +.. _STM32L1x reference manual: + https://www.st.com/resource/en/reference_manual/cd00240193.pdf + +.. _STM32L1DISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/dm00027954.pdf diff --git a/boards/arm/stm32l1_disco/stm32l1_disco.dts b/boards/st/stm32l1_disco/stm32l1_disco.dts similarity index 100% rename from boards/arm/stm32l1_disco/stm32l1_disco.dts rename to boards/st/stm32l1_disco/stm32l1_disco.dts diff --git a/boards/arm/stm32l1_disco/stm32l1_disco.yaml b/boards/st/stm32l1_disco/stm32l1_disco.yaml similarity index 100% rename from boards/arm/stm32l1_disco/stm32l1_disco.yaml rename to boards/st/stm32l1_disco/stm32l1_disco.yaml diff --git a/boards/arm/stm32l1_disco/stm32l1_disco_defconfig b/boards/st/stm32l1_disco/stm32l1_disco_defconfig similarity index 81% rename from boards/arm/stm32l1_disco/stm32l1_disco_defconfig rename to boards/st/stm32l1_disco/stm32l1_disco_defconfig index dfbf82011e57fe..fd0afcb9d74ce4 100644 --- a/boards/arm/stm32l1_disco/stm32l1_disco_defconfig +++ b/boards/st/stm32l1_disco/stm32l1_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L1X=y -CONFIG_SOC_STM32L151XB=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32l1_disco/support/openocd.cfg b/boards/st/stm32l1_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l1_disco/support/openocd.cfg rename to boards/st/stm32l1_disco/support/openocd.cfg diff --git a/boards/st/stm32l476g_disco/Kconfig.stm32l476g_disco b/boards/st/stm32l476g_disco/Kconfig.stm32l476g_disco new file mode 100644 index 00000000000000..7c062054f4480f --- /dev/null +++ b/boards/st/stm32l476g_disco/Kconfig.stm32l476g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2017 Arthur Sfez +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L476G_DISCO + select SOC_STM32L476XX diff --git a/boards/arm/stm32l476g_disco/board.cmake b/boards/st/stm32l476g_disco/board.cmake similarity index 100% rename from boards/arm/stm32l476g_disco/board.cmake rename to boards/st/stm32l476g_disco/board.cmake diff --git a/boards/st/stm32l476g_disco/board.yml b/boards/st/stm32l476g_disco/board.yml new file mode 100644 index 00000000000000..c82c2c618430e1 --- /dev/null +++ b/boards/st/stm32l476g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l476g_disco + vendor: st + socs: + - name: stm32l476xx diff --git a/boards/arm/stm32l476g_disco/doc/img/stm32l476g_disco.jpg b/boards/st/stm32l476g_disco/doc/img/stm32l476g_disco.jpg similarity index 100% rename from boards/arm/stm32l476g_disco/doc/img/stm32l476g_disco.jpg rename to boards/st/stm32l476g_disco/doc/img/stm32l476g_disco.jpg diff --git a/boards/st/stm32l476g_disco/doc/index.rst b/boards/st/stm32l476g_disco/doc/index.rst new file mode 100644 index 00000000000000..ef40802a709aa9 --- /dev/null +++ b/boards/st/stm32l476g_disco/doc/index.rst @@ -0,0 +1,218 @@ +.. _stm32l476g_disco_board: + +ST STM32L476G Discovery +####################### + +Overview +******** + +The STM32L476G Discovery board features an ARM Cortex-M4 based STM32L476VG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32L476G Discovery board: + + +- STM32L476VGT6 microcontroller featuring 1 Mbyte of Flash memory, 128 Kbytes of RAM in LQFP100 package +- On-board ST-LINK/V2-1 supporting USB re-enumeration capability +- Three different interfaces supported on USB: + + - Virtual com port + - Mass storage + - Debug port + +- LCD 24 segments, 4 commons in DIP 28 package +- Seven LEDs: + + - LD1 (red/green) for USB communication + - LD2 (red) for 3.3 V power on + - LD3 Over current (red) + - LD4 (red), LD5 (green) two user LEDs + - LD6 (green), LD7 (red) USB OTG FS LEDs + +- Pushbutton (reset) +- Four directions Joystick with selection +- USB OTG FS with micro-AB connector +- SAI Audio DAC, Stereo with output jack +- Digital microphone, accelerometer, magnetometer and gyroscope MEMS +- 128-Mbit Quad-SPI Flash memory +- MCU current ammeter with 4 ranges and auto-calibration +- Connector for external board or RF-EEPROM +- Four power supply options: + - ST-LINK/V2-1 + - USB FS connector + - External 5 V + - CR2032 battery (not provided) + +.. image:: img/stm32l476g_disco.jpg + :align: center + :alt: STM32L476G Discovery + +More information about the board can be found at the `STM32L476G Discovery website`_. + +Hardware +******** + +The STM32L476VG SoC provides the following hardware features: + +- Ultra-low-power with FlexPowerControl (down to 130 nA Standby mode and 100 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg|-M4 CPU with FPU, frequency up to 80 MHz, 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - Up to 128 KB of SRAM including 32 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR and NAND memories + - Quad SPI memory interface +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators +- 18x communication interfaces + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 3x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (4x SPIs with the Quad SPI) + - CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L476VG can be found here: + - `STM32L476VG on www.st.com`_ + - `STM32L476 reference manual`_ + + +Supported Features +================== + +The Zephyr stm32l476g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/stm32l476g_disco/stm32l476g_disco_defconfig` + + +Connections and IOs +=================== + +STM32L476G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L476G Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2_TX : PD5 +- UART_2_RX : PD6 +- LD4 : PB2 +- LD5 : PE8 + +System Clock +------------ + +STM32L476G Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +STM32L476G Discovery board has 6 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +STM32L476G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface. +This interface is supported by the openocd version included in Zephyr SDK. + +Flashing an application to STM32L476G Discovery +----------------------------------------------- + +Connect the STM32L476G Discovery to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l476g_disco + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l476g_disco + :maybe-skip-config: + :goals: debug + +.. _STM32L476G Discovery website: + https://www.st.com/en/evaluation-tools/32l476gdiscovery.html + +.. _STM32L476G Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00172179.pdf + +.. _STM32L476VG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l476vg.html + +.. _STM32L476 reference manual: + https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l476g_disco/stm32l476g_disco.dts b/boards/st/stm32l476g_disco/stm32l476g_disco.dts similarity index 100% rename from boards/arm/stm32l476g_disco/stm32l476g_disco.dts rename to boards/st/stm32l476g_disco/stm32l476g_disco.dts diff --git a/boards/arm/stm32l476g_disco/stm32l476g_disco.yaml b/boards/st/stm32l476g_disco/stm32l476g_disco.yaml similarity index 100% rename from boards/arm/stm32l476g_disco/stm32l476g_disco.yaml rename to boards/st/stm32l476g_disco/stm32l476g_disco.yaml diff --git a/boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig b/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig similarity index 85% rename from boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig rename to boards/st/stm32l476g_disco/stm32l476g_disco_defconfig index 0f0f47059fe071..82ee7285d52d8a 100644 --- a/boards/arm/stm32l476g_disco/stm32l476g_disco_defconfig +++ b/boards/st/stm32l476g_disco/stm32l476g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L476XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32l476g_disco/support/openocd.cfg b/boards/st/stm32l476g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l476g_disco/support/openocd.cfg rename to boards/st/stm32l476g_disco/support/openocd.cfg diff --git a/boards/arm/stm32l496g_disco/CMakeLists.txt b/boards/st/stm32l496g_disco/CMakeLists.txt similarity index 100% rename from boards/arm/stm32l496g_disco/CMakeLists.txt rename to boards/st/stm32l496g_disco/CMakeLists.txt diff --git a/boards/st/stm32l496g_disco/Kconfig.defconfig b/boards/st/stm32l496g_disco/Kconfig.defconfig new file mode 100644 index 00000000000000..604ea42983c33f --- /dev/null +++ b/boards/st/stm32l496g_disco/Kconfig.defconfig @@ -0,0 +1,16 @@ +# STM32L476G Nucleo board configuration + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32L496G_DISCO + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_STM32L496G_DISCO diff --git a/boards/st/stm32l496g_disco/Kconfig.stm32l496g_disco b/boards/st/stm32l496g_disco/Kconfig.stm32l496g_disco new file mode 100644 index 00000000000000..43f50ffced9f0d --- /dev/null +++ b/boards/st/stm32l496g_disco/Kconfig.stm32l496g_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2019 Centaur Analytics, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L496G_DISCO + select SOC_STM32L496XX diff --git a/boards/arm/stm32l496g_disco/arduino_r3_connector.dtsi b/boards/st/stm32l496g_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32l496g_disco/arduino_r3_connector.dtsi rename to boards/st/stm32l496g_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32l496g_disco/board.cmake b/boards/st/stm32l496g_disco/board.cmake similarity index 100% rename from boards/arm/stm32l496g_disco/board.cmake rename to boards/st/stm32l496g_disco/board.cmake diff --git a/boards/st/stm32l496g_disco/board.yml b/boards/st/stm32l496g_disco/board.yml new file mode 100644 index 00000000000000..9d6b18a598d7b4 --- /dev/null +++ b/boards/st/stm32l496g_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l496g_disco + vendor: st + socs: + - name: stm32l496xx diff --git a/boards/arm/stm32l496g_disco/board_adc_vref.c b/boards/st/stm32l496g_disco/board_adc_vref.c similarity index 100% rename from boards/arm/stm32l496g_disco/board_adc_vref.c rename to boards/st/stm32l496g_disco/board_adc_vref.c diff --git a/boards/arm/stm32l496g_disco/doc/img/stm32l496g_disco.jpg b/boards/st/stm32l496g_disco/doc/img/stm32l496g_disco.jpg similarity index 100% rename from boards/arm/stm32l496g_disco/doc/img/stm32l496g_disco.jpg rename to boards/st/stm32l496g_disco/doc/img/stm32l496g_disco.jpg diff --git a/boards/st/stm32l496g_disco/doc/index.rst b/boards/st/stm32l496g_disco/doc/index.rst new file mode 100644 index 00000000000000..576c07bc2cc9ac --- /dev/null +++ b/boards/st/stm32l496g_disco/doc/index.rst @@ -0,0 +1,259 @@ +.. _stm32l496g_disco_board: + +ST STM32L496G Discovery +####################### + +Overview +******** + +The STM32L496G Discovery board features an ARM Cortex-M4 based STM32L496AG MCU +with a wide range of connectivity support and configurations. Here are +some highlights of the STM32L496G Discovery board: + + +- STM32L496AGI6 microcontroller featuring 1 Mbyte of Flash memory and 320 Kbytes of RAM in an UFBGA169 package +- 1.54 inch 240 x 240 pixel-TFT color LCD with parallel interface +- SAI Audio CODEC, with a stereo headset jack, including analog microphone input +- Stereo digital MEMS microphones +- microSD card connector (card included) +- Camera 8 bit-connector +- 8 Mbit-PSRAM +- IDD measurement +- 64 Mbit-Quad-SPI Flash +- USB OTG FS with Micro-AB connector +- Two types of extension resources: + + - STMod+ and PMOD connectors + - Compatible Arduino* Uno V3 connectors + +- On-board ST-LINK/V2-1 debugger/programmer with SWD connector +- 5 source options for power supply + + - ST-LINK/V2-1 USB connector + - User USB FS connector + - VIN from Arduino connector + - 5 V from Arduino connector + - USB charger + - USB VBUS or external source(3.3V, 5V, 7 - 12V) + - Power management access point + +- 8 LEDs +- Reset push button +- 4 direction-joystick with selection + +.. image:: img/stm32l496g_disco.jpg + :align: center + :alt: STM32L496G Discovery + +More information about the board can be found at the `STM32L496G Discovery website`_. + +Hardware +******** + +The STM32L496AG SoC provides the following hardware capabilities: + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 91 + |micro| A/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz, + 100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) +- Clock Sources: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - Internal 48 MHz with clock recovery + - 3 PLLs for system clock, USB, audio, ADC + +- RTC with HW calendar, alarms and calibration +- LCD 8 x 40 or 4 x 44 with step-up converter +- Up to 24 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- 16x timers: + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 2x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - SysTick timer + +- Up to 136 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Memories + + - Up to 1 MB Flash, 2 banks read-while-write, proprietary code readout protection + - 320 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR, and NAND memories + - Quad SPI memory interface + +- 4x digital filters for sigma delta modulator +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 + |micro| A/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + +- 20x communication interfaces + + - USB OTG 2.0 full-speed, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 5x USARTs (ISO 7816, LIN, IrDA, modem) + - 1x LPUART + - 3x SPIs (4x SPIs with the Quad SPI) + - 2x CAN (2.0B Active) and SDMMC interface + - SWPMI single wire protocol master I/F + - IRTIM (Infrared interface) + +- 14-channel DMA controller +- True random number generator +- CRC calculation unit, 96-bit unique ID +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell* + + +More information about STM32L496AG can be found in: + +- `STM32L496AG on www.st.com`_ +- `STM32L496 reference manual`_ + +Supported Features +================== + +The Zephyr stm32l496g_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | disk access | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| QSPI NOR | on-chip | off-chip flash | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb_device | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/stm32l496g_disco/stm32l496g_disco_defconfig` + + +Connections and IOs +=================== + +STM32L496G Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L496G Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PB6/PG10 +- UART_2 TX/RX : PA2/PD6 (ST-Link Virtual Port Com) +- LPUART_1 TX/RX : PG7/PG8 (Arduino Serial) +- I2C1 SCL/SDA : PB8/PB7 (Arduino I2C) +- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2 +- SPI1 NSS/SCK/MISO/MOSI : PA15/PA5/PB4/PB5 (Arduino SPI) +- USB DM/DP/ID : PA11/PA12/PA10 +- I2C_1_SCL : PB8 +- I2C_1_SDA : PB7 +- PWM_2_CH1 : PA0 +- LD2 : PB13 + +System Clock +------------ + +STM32L496G Discovery System Clock could be driven by an internal or external oscillator, +as well as the main PLL clock. By default the System clock is driven by the PLL clock at 80MHz, +driven by 16MHz high speed internal oscillator. + +Serial Port +----------- + +STM32L496G Discovery board has 5 U(S)ARTs. The Zephyr console output is assigned to UART2. +Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug +tool interface. This interface is supported by openocd version +v0.10.0, which has been available since Zephyr SDK v0.9.2. + +Applications for the ``stm32l496g_disco`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + +Flashing an application to STM32L496G Discovery +----------------------------------------------- + +Connect the STM32L496G Discovery to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l496g_disco + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! arm + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l496g_disco + :maybe-skip-config: + :goals: debug + +.. _STM32L496G Discovery website: + https://www.st.com/en/evaluation-tools/32l496gdiscovery.html + +.. _STM32L496G Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00353127.pdf + +.. _STM32L496AG on www.st.com: + https://www.st.com/en/microcontrollers/stm32l496ag.html + +.. _STM32L496 reference manual: + https://www.st.com/resource/en/reference_manual/DM00083560.pdf diff --git a/boards/arm/stm32l496g_disco/stm32l496g_disco.dts b/boards/st/stm32l496g_disco/stm32l496g_disco.dts similarity index 100% rename from boards/arm/stm32l496g_disco/stm32l496g_disco.dts rename to boards/st/stm32l496g_disco/stm32l496g_disco.dts diff --git a/boards/arm/stm32l496g_disco/stm32l496g_disco.yaml b/boards/st/stm32l496g_disco/stm32l496g_disco.yaml similarity index 100% rename from boards/arm/stm32l496g_disco/stm32l496g_disco.yaml rename to boards/st/stm32l496g_disco/stm32l496g_disco.yaml diff --git a/boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig b/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig similarity index 85% rename from boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig rename to boards/st/stm32l496g_disco/stm32l496g_disco_defconfig index d2d940208b5ce4..c7582ad0d95389 100644 --- a/boards/arm/stm32l496g_disco/stm32l496g_disco_defconfig +++ b/boards/st/stm32l496g_disco/stm32l496g_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L496XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32l496g_disco/support/openocd.cfg b/boards/st/stm32l496g_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l496g_disco/support/openocd.cfg rename to boards/st/stm32l496g_disco/support/openocd.cfg diff --git a/boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco b/boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco new file mode 100644 index 00000000000000..680643035711e0 --- /dev/null +++ b/boards/st/stm32l4r9i_disco/Kconfig.stm32l4r9i_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L4R9I_DISCO + select SOC_STM32L4R9XX diff --git a/boards/arm/stm32l4r9i_disco/arduino_r3_connector.dtsi b/boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32l4r9i_disco/arduino_r3_connector.dtsi rename to boards/st/stm32l4r9i_disco/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32l4r9i_disco/board.cmake b/boards/st/stm32l4r9i_disco/board.cmake similarity index 100% rename from boards/arm/stm32l4r9i_disco/board.cmake rename to boards/st/stm32l4r9i_disco/board.cmake diff --git a/boards/st/stm32l4r9i_disco/board.yml b/boards/st/stm32l4r9i_disco/board.yml new file mode 100644 index 00000000000000..267fd87932da75 --- /dev/null +++ b/boards/st/stm32l4r9i_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32l4r9i_disco + vendor: st + socs: + - name: stm32l4r9xx diff --git a/boards/arm/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg b/boards/st/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg similarity index 100% rename from boards/arm/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg rename to boards/st/stm32l4r9i_disco/doc/img/stm32l4r9i_disco.jpg diff --git a/boards/st/stm32l4r9i_disco/doc/index.rst b/boards/st/stm32l4r9i_disco/doc/index.rst new file mode 100644 index 00000000000000..e2053313122bf5 --- /dev/null +++ b/boards/st/stm32l4r9i_disco/doc/index.rst @@ -0,0 +1,150 @@ +.. _stm32l4r9i_disco_board: + +ST STM32L4R9I Discovery +####################### + +Overview +******** + +The 32L4R9IDISCOVERY Discovery kit is a complete demonstration and development platform +for STMicroelectronics Arm® Cortex®-M4 core-based STM32L4R9AI microcontroller. + +Leveraging the innovative ultra-low-power oriented features, 640 Kbytes of embedded RAM, +graphics performance (Chrom-ART Accelerator), and DSI controller offered by the STM32L4R9AI, +the 32L4R9IDISCOVERY Discovery kit enables users to easily prototype applications with +state-of-the-art energy efficiency, as well as stunning audio and graphics rendering with direct +support for AMOLED DSI round LCD display. + +For even more user-friendliness, the on-board ST-LINK/V2-1 debugger provides out-of-the-box +programming and debugging capabilities. + +.. image:: img/stm32l4r9i_disco.jpg + :align: center + :alt: STM32L4R9I-DISCO + +More information about the board can be found at the `STM32L4R9I-DISCOVERY website`_. +More information about STM32L4R9 can be found here: + +- `STM32L4R9/S9 on www.st.com`_ +- `STM32L4+ Series reference manual`_ +- `STM32L4R5xx/R7xx/R9xx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32l4r9i_disco board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | on-chip flash memory; | +| | | external OctoSPI memory | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| RTC | on-chip | Real Time Clock | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | sd/mmc | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig` + + +Pin Mapping +=========== + +For more details, please refer to `STM32L4R9I-DISCOVERY website`_. + +System Clock +============ + +The STM32L4R9AI System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock is driven by +the PLL clock at 120MHz. PLL clock is driven by a 4MHz medium speed internal clock. + +Serial Port +=========== + +The STM32L4R9I Discovery board has up to 6 U(S)ARTs. +The Zephyr console output is assigned to UART2, which is connected to the onboard +ST-LINK Virtual COM port interface. Default communication settings are 115200 8N1. + + +Programming and Debugging +************************* + +Flashing +======== + +The STM32L4R9I Discovery board includes an ST-LINK/V2-1 debug tool. + +Applications for the ``stm32l4r9i_disco`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details). + + +Flashing an application to STM32L4R9I Discovery +----------------------------------------------- + +Connect the STM32L4R9I Discovery to your host computer using the ST-LINK +USB port, then run a serial host program to connect with the board. For example: + +.. code-block:: console + + $ minicom -b 115200 -D /dev/ttyACM0 + +You can then build and flash applications in the usual way. +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l4r9i_disco + :goals: build flash + +You should see the following message in the serial host program: + +.. code-block:: console + + $ Hello World! stm32l4r9i_disco + + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l4r9i_disco + :goals: debug + +.. _STM32L4R9I-DISCOVERY website: + https://www.st.com/en/evaluation-tools/32l4r9idiscovery.html + +.. _STM32L4R9/S9 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32l4r9-s9.html + +.. _STM32L4+ Series reference manual: + https://www.st.com/resource/en/reference_manual/rm0432-stm32l4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32L4R5xx/R7xx/R9xx datasheet: + https://www.st.com/resource/en/datasheet/stm32l4r5vi.pdf diff --git a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.dts b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts similarity index 100% rename from boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.dts rename to boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts diff --git a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.yaml b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml similarity index 100% rename from boards/arm/stm32l4r9i_disco/stm32l4r9i_disco.yaml rename to boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml diff --git a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig similarity index 85% rename from boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig rename to boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig index 546bd3379a8547..ac681be2af064e 100644 --- a/boards/arm/stm32l4r9i_disco/stm32l4r9i_disco_defconfig +++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L4X=y -CONFIG_SOC_STM32L4R9XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32l4r9i_disco/support/openocd.cfg b/boards/st/stm32l4r9i_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l4r9i_disco/support/openocd.cfg rename to boards/st/stm32l4r9i_disco/support/openocd.cfg diff --git a/boards/arm/stm32l562e_dk/CMakeLists.txt b/boards/st/stm32l562e_dk/CMakeLists.txt similarity index 100% rename from boards/arm/stm32l562e_dk/CMakeLists.txt rename to boards/st/stm32l562e_dk/CMakeLists.txt diff --git a/boards/st/stm32l562e_dk/Kconfig.defconfig b/boards/st/stm32l562e_dk/Kconfig.defconfig new file mode 100644 index 00000000000000..3f15027bb35d63 --- /dev/null +++ b/boards/st/stm32l562e_dk/Kconfig.defconfig @@ -0,0 +1,29 @@ +# STM32L562E-DK Discovery board configuration + +# Copyright (c) 2020 Yestin Sun +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32L562E_DK + +if BT + +config SPI + default y + +choice BT_HCI_BUS_TYPE + default BT_SPI +endchoice + +config BT_BLUENRG_ACI + default y + +# Disable Flow control +config BT_HCI_ACL_FLOW_CONTROL + default n + +config BT_HCI_VS_EXT + default n + +endif # BT + +endif # BOARD_STM32L562E_DK diff --git a/boards/st/stm32l562e_dk/Kconfig.stm32l562e_dk b/boards/st/stm32l562e_dk/Kconfig.stm32l562e_dk new file mode 100644 index 00000000000000..f5b901a2bce068 --- /dev/null +++ b/boards/st/stm32l562e_dk/Kconfig.stm32l562e_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Yestin Sun +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32L562E_DK + select SOC_STM32L562XX diff --git a/boards/arm/stm32l562e_dk/arduino_r3_connector.dtsi b/boards/st/stm32l562e_dk/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32l562e_dk/arduino_r3_connector.dtsi rename to boards/st/stm32l562e_dk/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32l562e_dk/board.cmake b/boards/st/stm32l562e_dk/board.cmake similarity index 100% rename from boards/arm/stm32l562e_dk/board.cmake rename to boards/st/stm32l562e_dk/board.cmake diff --git a/boards/st/stm32l562e_dk/board.yml b/boards/st/stm32l562e_dk/board.yml new file mode 100644 index 00000000000000..225f25adc2e8cf --- /dev/null +++ b/boards/st/stm32l562e_dk/board.yml @@ -0,0 +1,7 @@ +board: + name: stm32l562e_dk + vendor: st + socs: + - name: stm32l562xx + variants: + - name: ns diff --git a/boards/arm/stm32l562e_dk/doc/img/stm32l562e_dk.jpg b/boards/st/stm32l562e_dk/doc/img/stm32l562e_dk.jpg similarity index 100% rename from boards/arm/stm32l562e_dk/doc/img/stm32l562e_dk.jpg rename to boards/st/stm32l562e_dk/doc/img/stm32l562e_dk.jpg diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst new file mode 100644 index 00000000000000..889f0b8d593a40 --- /dev/null +++ b/boards/st/stm32l562e_dk/doc/index.rst @@ -0,0 +1,387 @@ +.. _stm32l562e_dk_board: + +ST STM32L562E-DK Discovery +########################## + +Overview +******** + +The STM32L562E-DK Discovery kit is designed as a complete demonstration and +development platform for STMicroelectronics Arm |reg| Cortex |reg|-M33 core-based +STM32L562QEI6QU microcontroller with TrustZone |reg|. Here are some highlights of +the STM32L562E-DK Discovery board: + + +- STM32L562QEI6QU microcontroller featuring 512 Kbytes of Flash memory and 256 Kbytes of SRAM in BGA132 package +- 1.54" 240 x 240 pixel-262K color TFT LCD module with parallel interface and touch-control panel +- USB Type-C |trade| Sink device FS +- On-board energy meter: 300 nA to 150 mA measurement range with a dedicated USB interface +- SAI Audio CODEC +- MEMS digital microphones +- 512-Mbit Octal-SPI Flash memory +- Bluetooth |reg| V4.1 Low Energy module +- iNEMO 3D accelerometer and 3D gyroscope +- Board connectors + + - STMod+ expansion connector with fan-out expansion board for Wi‑Fi |reg|, Grove and mikroBUS |trade| compatible connectors + - Pmod |trade| expansion connector + - Audio MEMS daughterboard expansion connector + - ARDUINO |reg| Uno V3 expansion connector + +- Flexible power-supply options + + - ST-LINK + - USB VBUS + - external sources + +- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability: + + - mass storage + - Virtual COM port + - debug port + +- 2 user LEDs +- User and reset push-buttons + +.. image:: img/stm32l562e_dk.jpg + :align: center + :alt: STM32L562E-DK Discovery + +More information about the board can be found at the `STM32L562E-DK Discovery website`_. + +Hardware +******** + +The STM32L562xx devices are an ultra-low-power microcontrollers family (STM32L5 +Series) based on the high-performance Arm |reg| Cortex |reg|-M33 32-bit RISC core. +They operate at a frequency of up to 110 MHz. + +- Ultra-low-power with FlexPowerControl (down to 108 nA Standby mode and 62 uA/MHz run mode) +- Core: ARM |reg| 32-bit Cortex |reg| -M33 CPU with TrustZone |reg| and FPU. +- Performance benchmark: + + - 1.5 DMPIS/MHz (Drystone 2.1) + - 442 CoreMark |reg| (4.02 CoreMark |reg| /MHZ) + +- Security + + - Arm |reg| TrustZone |reg| and securable I/Os memories and peripherals + - Flexible life cycle scheme with RDP (readout protection) + - Root of trust thanks to unique boot entry and hide protection area (HDP) + - Secure Firmware Installation thanks to embedded Root Secure Services + - Secure Firmware Update support with TF-M + - AES coprocessor + - Public key accelerator + - On-the-fly decryption of Octo-SPI external memories + - HASH hardware accelerator + - Active tamper and protection temperature, voltage and frequency attacks + - True Random Number Generator NIST SP800-90B compliant + - 96-bit unique ID + - 512-byte One-Time Programmable for user data + +- Clock management: + + - 4 to 48 MHz crystal oscillator + - 32 kHz crystal oscillator for RTC (LSE) + - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%) + - Internal low-power 32 kHz RC ( |plusminus| 5%) + - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by + LSE (better than |plusminus| 0.25 % accuracy) + - 3 PLLs for system clock, USB, audio, ADC + +- Power management + + - Embedded regulator (LDO) with three configurable range output to supply the digital circuitry + - Embedded SMPS step-down converter + - External SMPS support + +- RTC with HW calendar, alarms and calibration +- Up to 114 fast I/Os, most 5 V-tolerant, up to 14 I/Os with independent supply down to 1.08 V +- Up to 22 capacitive sensing channels: support touchkey, linear and rotary touch sensors +- Up to 16 timers and 2 watchdogs + + - 2x 16-bit advanced motor-control + - 2x 32-bit and 5x 16-bit general purpose + - 2x 16-bit basic + - 3x low-power 16-bit timers (available in Stop mode) + - 2x watchdogs + - 2x SysTick timer + +- Memories + + - Up to 512 MB Flash, 2 banks read-while-write + - 512 KB of SRAM including 64 KB with hardware parity check + - External memory interface for static memories supporting SRAM, PSRAM, NOR, NAND and FRAM memories + - OCTOSPI memory interface + +- Rich analog peripherals (independent supply) + + - 3x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200 uA/MSPS + - 2x 12-bit DAC, low-power sample and hold + - 2x operational amplifiers with built-in PGA + - 2x ultra-low-power comparators + - 4x digital filters for sigma delta modulator + +- 19x communication interfaces + + - USB Type-C / USB power delivery controller + - 2.0 full-speed crystal less solution, LPM and BCD + - 2x SAIs (serial audio interface) + - 4x I2C FM+(1 Mbit/s), SMBus/PMBus + - 6x USARTs (ISO 7816, LIN, IrDA, modem) + - 3x SPIs (7x SPIs with USART and OCTOSPI in SPI mode) + - 1xFDCAN + - 1xSDMMC interface + - 2x 14 channel DMA controllers + +- CRC calculation unit +- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell |trade| + + +More information about STM32L562QE can be found here: + +- `STM32L562QE on www.st.com`_ +- `STM32L562 reference manual`_ + +Supported Features +================== + +The Zephyr stm32l562e_dk board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| ADC | on-chip | ADC Controller | ++-----------+------------+-------------------------------------+ +| AES | on-chip | crypto | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| DAC | on-chip | DAC Controller | ++-----------+------------+-------------------------------------+ +| DMA | on-chip | Direct Memory Access | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | PWM | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | entropy | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | sd/mmc | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| TrustZone | on-chip | Trusted Firmware-M | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| USB | on-chip | usb | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on this Zephyr port. + +The default configuration can be found in the defconfig and dts files: + +- Common: + + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi` + +- Secure target: + + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_defconfig` + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk.dts` + +- Non-Secure target: + + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig` + - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts` + +Zephyr board options +==================== + +The STM32L562e is an SoC with Cortex-M33 architecture. Zephyr provides support +for building for both Secure and Non-Secure firmware. + +The BOARD options are summarized below: + ++------------------------------+-------------------------------------------+ +| BOARD | Description | ++==============================+===========================================+ +| stm32l562e_dk | For building Trust Zone Disabled firmware | ++------------------------------+-------------------------------------------+ +| stm32l562e_dk/stm32l562xx/ns | For building Non-Secure firmware | ++------------------------------+-------------------------------------------+ + +Here are the instructions to build Zephyr with a non-secure configuration, +using `tfm_ipc_` sample: + + .. code-block:: bash + + $ west build -b stm32l562e_dk/stm32l562xx/ns samples/tfm_integration/tfm_ipc/ + +Once done, before flashing, you need to first run a generated script that +will set platform option bytes config and erase platform (among others, +option bit TZEN will be set). + + .. code-block:: bash + + $ ./build/tfm/regression.sh + $ west flash + +Please note that, after having run a TFM sample on the board, you will need to +run `./build/tfm/regression.sh` once more to clean up the board from secure +options and get back the platform back to a "normal" state and be able to run +usual, non-TFM, binaries. +Also note that, even then, TZEN will remain set, and you will need to use +STM32CubeProgrammer_ to disable it fully, if required. + +Connections and IOs +=================== + +STM32L562E-DK Discovery Board has 8 GPIO controllers. These controllers are responsible for pin muxing, +input/output, pull-up, etc. + +For more details please refer to `STM32L562E-DK Discovery board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX/RX : PA9/PA10 +- USART_3 TX/RX : PC10/PC11 +- I2C_1 SCL/SDA : PB6/PB7 +- SPI_1 SCK/MISO/MOSI : PG2/PG3/PG4 (BT SPI bus) +- SPI_3 NSS/SCK/MISO/MOSI : PE0/PG9/PB4/PB5 (Arduino SPI) +- USER_PB : PC13 +- LD10 : PG12 +- PWM_2_CH1 : PA0 +- DAC1 : PA4 +- ADC1 : PC4 + +System Clock +------------ + +STM32L562E-DK System Clock could be driven by internal or external oscillator, +as well as main PLL clock. By default System clock is driven by PLL clock at +110MHz, driven by 4MHz medium speed internal oscillator. + +Serial Port +----------- + +STM32L562E-DK Discovery board has 6 U(S)ARTs. The Zephyr console output is +assigned to USART1. Default settings are 115200 8N1. + + +Programming and Debugging +************************* + +Applications for the ``stm32l562e_dk`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool +interface. Support can be enabled on pyocd by adding "pack" support with the +following pyocd command: + +.. code-block:: console + + $ pyocd pack --update + $ pyocd pack --install stm32l562qe + +Alternatively, this interface is supported by the openocd version +included in the Zephyr SDK since v0.13.1. + +Flashing an application to STM32L562E-DK Discovery +-------------------------------------------------- + +Connect the STM32L562E-DK Discovery to your host computer using the USB port. +Then build and flash an application. Here is an example for the +:ref:`hello_world` application. + +Run a serial host program to connect with your Nucleo board: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 + +Then build and flash the application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l562e_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32l562e_dk + +Building Secure/Non-Secure Zephyr applications with Arm |reg| TrustZone |reg| +----------------------------------------------------------------------------- + +The TF-M integration sample :ref:`tfm_ipc` can be run on a ST STM32L562E-DK Discovery. +In TF-M configuration, Zephyr is run on the non-secure domain. A non-secure image +can be generated using ``stm32l562e_dk/stm32l562xx/ns`` as build target. + +.. code-block:: bash + + $ west build -b stm32l562e_dk/stm32l562xx/ns path/to/source/directory + +Note: When building the ``*_ns`` image with TF-M, ``build/tfm/api_ns/postbuild.sh`` bash script +is run automatically in a post-build step to make some required flash layout changes. + +Once the build is completed, run the following script to initialize the option bytes. + +.. code-block:: bash + + $ build/tfm/regression.sh + +Finally, to flash the board, run: + +.. code-block:: bash + + $ west flash --hex-file build/tfm_merged.hex + +Note: Check the ``build/tfm`` directory to ensure that the commands required by these scripts +(``readlink``, etc.) are available on your system. Please also check ``STM32_Programmer_CLI`` +(which is used for initialization) is available in the PATH. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32l562e_dk + :maybe-skip-config: + :goals: debug + +.. _STM32L562E-DK Discovery website: + https://www.st.com/en/evaluation-tools/stm32l562e-dk.html + +.. _STM32L562E-DK Discovery board User Manual: + https://www.st.com/resource/en/user_manual/dm00635554.pdf + +.. _STM32L562QE on www.st.com: + https://www.st.com/en/microcontrollers/stm32l562qe.html + +.. _STM32L562 reference manual: + https://www.st.com/resource/en/reference_manual/DM00346336.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk.dts b/boards/st/stm32l562e_dk/stm32l562e_dk.dts similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk.dts rename to boards/st/stm32l562e_dk/stm32l562e_dk.dts diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk.yaml b/boards/st/stm32l562e_dk/stm32l562e_dk.yaml similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk.yaml rename to boards/st/stm32l562e_dk/stm32l562e_dk.yaml diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi b/boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk_common.dtsi rename to boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig b/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig similarity index 85% rename from boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig rename to boards/st/stm32l562e_dk/stm32l562e_dk_defconfig index 6646832e7ef7e8..cf7483088e502a 100644 --- a/boards/arm/stm32l562e_dk/stm32l562e_dk_defconfig +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32L5X=y -CONFIG_SOC_STM32L562XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32l562e_dk/stm32l562e_dk_ns.dts b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts similarity index 100% rename from boards/arm/stm32l562e_dk/stm32l562e_dk_ns.dts rename to boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml new file mode 100644 index 00000000000000..c092f8da95d82e --- /dev/null +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.yaml @@ -0,0 +1,21 @@ +identifier: stm32l562e_dk/stm32l562xx/ns +name: ST STM32L562E-DK Discovery non secure +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb +supported: + - counter + - gpio + - i2c + - lptim + - dac + - spi + - arduino_spi + - sdhc + - usb + - usb_device +ram: 192 +flash: 512 +vendor: st diff --git a/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig new file mode 100644 index 00000000000000..d2035929200df4 --- /dev/null +++ b/boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable uart driver +CONFIG_SERIAL=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# Enable MPU +CONFIG_ARM_MPU=y + +CONFIG_ARM_TRUSTZONE_M=y +CONFIG_RUNTIME_NMI=y +CONFIG_TRUSTED_EXECUTION_NONSECURE=y + +# enable pin controller +CONFIG_PINCTRL=y diff --git a/boards/arm/stm32l562e_dk/support/openocd.cfg b/boards/st/stm32l562e_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32l562e_dk/support/openocd.cfg rename to boards/st/stm32l562e_dk/support/openocd.cfg diff --git a/boards/st/stm32mp157c_dk2/Kconfig.defconfig b/boards/st/stm32mp157c_dk2/Kconfig.defconfig new file mode 100644 index 00000000000000..40490cb49c3f9d --- /dev/null +++ b/boards/st/stm32mp157c_dk2/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STM32MP157 discovery board configuration + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32MP157C_DK2 + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +config CLOCK_STM32_HSE_CLOCK + default 24000000 + +endif # BOARD_STM32MP157_Dk2 diff --git a/boards/st/stm32mp157c_dk2/Kconfig.stm32mp157c_dk2 b/boards/st/stm32mp157c_dk2/Kconfig.stm32mp157c_dk2 new file mode 100644 index 00000000000000..f3befe5bc83b27 --- /dev/null +++ b/boards/st/stm32mp157c_dk2/Kconfig.stm32mp157c_dk2 @@ -0,0 +1,5 @@ +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32MP157C_DK2 + select SOC_STM32MP15_M4 diff --git a/boards/arm/stm32mp157c_dk2/arduino_r3_connector.dtsi b/boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi similarity index 100% rename from boards/arm/stm32mp157c_dk2/arduino_r3_connector.dtsi rename to boards/st/stm32mp157c_dk2/arduino_r3_connector.dtsi diff --git a/boards/arm/stm32mp157c_dk2/board.cmake b/boards/st/stm32mp157c_dk2/board.cmake similarity index 100% rename from boards/arm/stm32mp157c_dk2/board.cmake rename to boards/st/stm32mp157c_dk2/board.cmake diff --git a/boards/st/stm32mp157c_dk2/board.yml b/boards/st/stm32mp157c_dk2/board.yml new file mode 100644 index 00000000000000..d8ffb9a66b5628 --- /dev/null +++ b/boards/st/stm32mp157c_dk2/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32mp157c_dk2 + vendor: st + socs: + - name: stm32mp157cxx diff --git a/boards/arm/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg b/boards/st/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg similarity index 100% rename from boards/arm/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg rename to boards/st/stm32mp157c_dk2/doc/img/en.stm32mp157c-dk2.jpg diff --git a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst similarity index 98% rename from boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst rename to boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst index 0b92de76c9af40..f8f9a4869e291c 100644 --- a/boards/arm/stm32mp157c_dk2/doc/stm32mp157_dk2.rst +++ b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst @@ -178,8 +178,8 @@ features: | SPI | on-chip | spi | +-----------+------------+-------------------------------------+ -The default configuration can be found in the defconfig file: -``boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig`` +The default configuration can be found in +:zephyr_file:`boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig` Connections and IOs diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.dts b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.dts similarity index 100% rename from boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.dts rename to boards/st/stm32mp157c_dk2/stm32mp157c_dk2.dts diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml similarity index 100% rename from boards/arm/stm32mp157c_dk2/stm32mp157c_dk2.yaml rename to boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml diff --git a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig similarity index 89% rename from boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig rename to boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig index 66503dc2406738..056ce7eddc026b 100644 --- a/boards/arm/stm32mp157c_dk2/stm32mp157c_dk2_defconfig +++ b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32MP1X=y -CONFIG_SOC_STM32MP15_M4=y - # enable GPIO CONFIG_GPIO=y diff --git a/boards/arm/stm32mp157c_dk2/support/openocd.cfg b/boards/st/stm32mp157c_dk2/support/openocd.cfg similarity index 100% rename from boards/arm/stm32mp157c_dk2/support/openocd.cfg rename to boards/st/stm32mp157c_dk2/support/openocd.cfg diff --git a/boards/st/stm32u5a9j_dk/Kconfig.stm32u5a9j_dk b/boards/st/stm32u5a9j_dk/Kconfig.stm32u5a9j_dk new file mode 100644 index 00000000000000..2609400aa9ea19 --- /dev/null +++ b/boards/st/stm32u5a9j_dk/Kconfig.stm32u5a9j_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32U5A9J_DK + select SOC_STM32U5A9XX diff --git a/boards/arm/stm32u5a9j_dk/board.cmake b/boards/st/stm32u5a9j_dk/board.cmake similarity index 100% rename from boards/arm/stm32u5a9j_dk/board.cmake rename to boards/st/stm32u5a9j_dk/board.cmake diff --git a/boards/st/stm32u5a9j_dk/board.yml b/boards/st/stm32u5a9j_dk/board.yml new file mode 100644 index 00000000000000..93bcec39743df7 --- /dev/null +++ b/boards/st/stm32u5a9j_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32u5a9j_dk + vendor: st + socs: + - name: stm32u5a9xx diff --git a/boards/arm/stm32u5a9j_dk/doc/img/bottom_view.jpg b/boards/st/stm32u5a9j_dk/doc/img/bottom_view.jpg similarity index 100% rename from boards/arm/stm32u5a9j_dk/doc/img/bottom_view.jpg rename to boards/st/stm32u5a9j_dk/doc/img/bottom_view.jpg diff --git a/boards/arm/stm32u5a9j_dk/doc/img/top_view.jpg b/boards/st/stm32u5a9j_dk/doc/img/top_view.jpg similarity index 100% rename from boards/arm/stm32u5a9j_dk/doc/img/top_view.jpg rename to boards/st/stm32u5a9j_dk/doc/img/top_view.jpg diff --git a/boards/st/stm32u5a9j_dk/doc/index.rst b/boards/st/stm32u5a9j_dk/doc/index.rst new file mode 100644 index 00000000000000..aed555a40575fb --- /dev/null +++ b/boards/st/stm32u5a9j_dk/doc/index.rst @@ -0,0 +1,198 @@ +.. _stm32u5a9j_dk_board: + +ST STM32U5A9J Discovery Kit +########################### + +Overview +******** + +The STM32U5A9J-DK Discovery kit is a complete demonstration and development +platform for the STM32U5A9NJH6Q microcontroller, featuring an Arm® Cortex®-M33 +core with Arm® TrustZone®. + +Leveraging the innovative ultra-low-power oriented features, 2.5 Mbytes of +embedded SRAM, 4 Mbytes of embedded flash memory, and rich graphics features, +the STM32U5A9J-DK Discovery kit enables users to easily prototype applications +with state-of-the-art energy efficiency, as well as providing stunning and +optimized graphics rendering with the support of the 2.5D NeoChrom Accelerator, +Chrom-ART Accelerator, and Chrom-GRC™ MMU. + +The full range of hardware features available on the board helps users to +enhance their application development by an evaluation of all the peripherals +such as a 2.47-inch RGB 480x480 pixels TFT round LCD module with MIPI DSI® +interface and capacitive touch panel, USB Type-C® HS, Octo-SPI flash memory +device, Hexadeca-SPI PSRAM memory device, eMMC flash memory device, +Time-of-Flight and gesture detection sensor, temperature sensor, and two 2.54 mm +pitch double-row flexible expansion connectors for easy prototyping with +daughterboards for specific applications (USART, LPUART, two SPIs, SAI, three +I2C, SDMMC, ADCs, timers, and GPIOs). + +The STM32U5A9J-DK Discovery kit integrates an STLINK-V3E embedded in-circuit +debugger and programmer for the STM32 microcontroller with a USB Virtual COM +port bridge and comes with the STM32CubeU5 MCU Package, which provides an STM32 +comprehensive software HAL library as well as various software examples. + +.. image:: img/top_view.jpg + :align: center + :alt: STM32U5A9J-DK Top View + +.. image:: img/bottom_view.jpg + :align: center + :alt: STM32U5A9J-DK Bottom View + +More information about the board can be found at the `STM32U5A9J-DK website`_. +More information about STM32U5A9NJH6Q can be found here: + +- `STM32U5A9NJ on www.st.com`_ +- `STM32U5 Series reference manual`_ +- `STM32U5Axxx datasheet`_ + +Supported Features +================== + +The current Zephyr stm32u5a9j_dk board configuration supports the following +hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| LPUART | on-chip | low power uart | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| RNG | on-chip | True Random number generator | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++-----------+------------+-------------------------------------+ +| SDMMC | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| WATCHDOG | on-chip | independent watchdog | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ + +Other hardware features have not been enabled yet for this board. + +The default configuration per core can be found in the defconfig file: +:zephyr_file:`boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig` + +Pin Mapping +=========== + +For more details please refer to `STM32U5A9J-DK board User Manual`_. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- USART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com) +- LD3 : PE0 +- LD4 : PE1 +- User Button: PC13 +- USART_3 TX/RX : PB10/PB11 +- LPUART_1 TX/RX : PG7/PG8 +- I2C1 SCL/SDA : PG14/PG13 +- I2C2 SCL/SDA : PF1/PF0 +- I2C6 SCL/SDA : PD1/PD0 +- SPI2 SCK/MISO/MOSI/CS : PB13/PD3/PD4/PB12 +- SPI3 SCK/MISO/MOSI/CS : PG9/PG10/PG11/PG15 +- ADC1 : channel5 PA0, channel14 PC5 +- ADC2 : channel9 PA4 +- ADC4 : channel5 PF14 + +System Clock +============ + +The STM32U5A9J-DK Discovery kit relies on an HSE oscillator (16 MHz crystal) +and an LSE oscillator (32.768 kHz crystal) as clock references. +Using the HSE (instead of HSI) is mandatory to manage the DSI interface for +the LCD module and the USB high‑speed interface. + +Serial Port +=========== + +The STM32U5A9J Discovery kit has up to 4 USARTs, 2 UARTs, and 1 LPUART. +The Zephyr console output is assigned to USART1 which connected to the onboard +ST-LINK/V3.0. Virtual COM port interface. Default communication settings are +115200 8N1. + + +Programming and Debugging +************************* + +STM32U5A9J Discovery kit includes an ST-LINK/V3 embedded debug tool interface. +This probe allows to flash and debug the board using various tools. + +Flashing +======== + +Board is configured to be flashed using west STM32CubeProgrammer runner. +Installation of `STM32CubeProgrammer`_ is then required to flash the board., + +Connect the STM32U5A9J Discovery board to your host computer using the USB +port, then run a serial host program to connect with your Discovery +board. For example: + +.. code-block:: console + + $ minicom -D /dev/ttyACM0 -b 115200 + +Then, build and flash in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: stm32u5a9j_dk + :goals: build flash + +You should see the following message on the console: + +.. code-block:: console + + Hello World! stm32u5a9j_dk + +Debugging +========= + +Default debugger for this board is openocd. It could be used in the usual way +with "west debug" command. +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32u5a9j_dk + :goals: debug + + +.. _STM32U5A9J-DK website: + https://www.st.com/en/evaluation-tools/stm32u5a9j-dk.html + +.. _STM32U5A9J-DK board User Manual: + https://www.st.com/resource/en/user_manual/um2967-discovery-kit-with-stm32u5a9nj-mcu-stmicroelectronics.pdf + +.. _STM32U5A9NJ on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32u5a9nj.html + +.. _STM32U5 Series reference manual: + https://www.st.com/resource/en/reference_manual/rm0456-stm32u5-series-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32U5Axxx datasheet: + https://www.st.com/resource/en/datasheet/stm32u5a9nj.pdf + +.. _STM32CubeProgrammer: + https://www.st.com/en/development-tools/stm32cubeprog.html + +.. _STM32U5A9J_DK board schematics: + https://www.st.com/resource/en/schematic_pack/mb1829-u5a9njq-b01-schematic.pdf diff --git a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.dts b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts similarity index 100% rename from boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.dts rename to boards/st/stm32u5a9j_dk/stm32u5a9j_dk.dts diff --git a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.yaml b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk.yaml similarity index 100% rename from boards/arm/stm32u5a9j_dk/stm32u5a9j_dk.yaml rename to boards/st/stm32u5a9j_dk/stm32u5a9j_dk.yaml diff --git a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig similarity index 80% rename from boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig rename to boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig index 71e92cf0450d6a..93c31903765ad7 100644 --- a/boards/arm/stm32u5a9j_dk/stm32u5a9j_dk_defconfig +++ b/boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2023 STMicroelectronics # SPDX-License-Identifier: Apache-2.0 -# Set SoC present on the board -CONFIG_SOC_SERIES_STM32U5X=y -CONFIG_SOC_STM32U5A9XX=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32u5a9j_dk/support/openocd.cfg b/boards/st/stm32u5a9j_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32u5a9j_dk/support/openocd.cfg rename to boards/st/stm32u5a9j_dk/support/openocd.cfg diff --git a/boards/st/stm32vl_disco/Kconfig.stm32vl_disco b/boards/st/stm32vl_disco/Kconfig.stm32vl_disco new file mode 100644 index 00000000000000..d14fa18d468d11 --- /dev/null +++ b/boards/st/stm32vl_disco/Kconfig.stm32vl_disco @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Jonas Eriksson, Up to Code AB +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32VL_DISCO + select SOC_STM32F100XB diff --git a/boards/arm/stm32vl_disco/board.cmake b/boards/st/stm32vl_disco/board.cmake similarity index 100% rename from boards/arm/stm32vl_disco/board.cmake rename to boards/st/stm32vl_disco/board.cmake diff --git a/boards/st/stm32vl_disco/board.yml b/boards/st/stm32vl_disco/board.yml new file mode 100644 index 00000000000000..15c8b5b3caca7c --- /dev/null +++ b/boards/st/stm32vl_disco/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32vl_disco + vendor: st + socs: + - name: stm32f100xb diff --git a/boards/arm/stm32vl_disco/doc/img/stm32vl_disco.jpg b/boards/st/stm32vl_disco/doc/img/stm32vl_disco.jpg similarity index 100% rename from boards/arm/stm32vl_disco/doc/img/stm32vl_disco.jpg rename to boards/st/stm32vl_disco/doc/img/stm32vl_disco.jpg diff --git a/boards/st/stm32vl_disco/doc/index.rst b/boards/st/stm32vl_disco/doc/index.rst new file mode 100644 index 00000000000000..e676e4ab426709 --- /dev/null +++ b/boards/st/stm32vl_disco/doc/index.rst @@ -0,0 +1,188 @@ +.. _stm32vl_disco_board: + +ST STM32VL Discovery +#################### + +Overview +******** + +The STM32 Discovery series comes in many varieties, in this case the "Value +Line" STM32F100x SoC series is showcased. Like other Discovery board, an +integrated ST-LINK debugger and programmer is included (V1), but the only +included I/O devices are two user LEDs and one user button. + +.. image:: img/stm32vl_disco.jpg + :align: center + :alt: STM32VLDISCOVERY + +More information about the board can be found at the `STM32VLDISCOVERY website`_. + +Hardware +******** + +The STM32 Discovery board features: + +- On-board ST-LINK/V1 with selection mode switch to use the kit as a standalone + ST-LINK/V1 (with SWD connector for programming and debugging) +- Board power supply: through USB bus or from an external 5 V supply voltage +- External application power supply: 3 V and 5 V +- Four LEDs: + + - LD1 (red) for 3.3 V power on + - LD2 (red/green) for USB communication + - LD3 (green) for PC9 output + - LD4 (blue) for PC8 output +- Two push buttons (user and reset) +- Extension header for all LQFP64 I/Os for quick connection to prototyping board + and easy probing + +More information about the STM32F100x can be found in the +`STM32F100x reference manual`_ and the `STM32F100x data sheet`_. + +Supported Features +================== + +The Zephyr stm32vl_disco board configuration supports the following hardware features: + +.. list-table:: Supported hardware + :header-rows: 1 + + * - Interface + - Controller + - Driver/component + * - NVIC + - on-chip + - nested vector interrupt controller + * - UART + - on-chip + - serial port-polling + serial port-interrupt + * - PINMUX + - on-chip + - pinmux + * - GPIO + - on-chip + - gpio + * - CLOCK + - on-chip + - reset and clock control + * - FLASH + - on-chip + - flash memory + * - WATCHDOG + - on-chip + - window watchdog + * - I2C + - on-chip + - i2c + * - SPI + - on-chip + - spi + * - ADC + - on-chip + - adc + +Other hardware features are not yet supported in this Zephyr port. + +The default configuration can be found in +:zephyr_file:`boards/st/stm32vl_disco/stm32vl_disco_defconfig` + +Connections and IOs +=================== + +Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as +input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the +GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current +capable except for analog inputs. + +Default Zephyr Peripheral Mapping: +---------------------------------- + +.. rst-class:: rst-columns + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- UART_2_TX : PA2 +- UART_2_RX : PA3 +- UART_3_TX : PB10 +- UART_3_RX : PB11 +- SPI1_NSS : PA4 +- SPI1_SCK : PA5 +- SPI1_MISO : PA6 +- SPI1_MOSI : PA7 +- SPI2_NSS : PB12 +- SPI2_SCK : PB13 +- SPI2_MISO : PB14 +- SPI2_MOSI : PB15 +- I2C1_SCL : PB6 +- I2C1_SDA : PB7 +- I2C2_SCL : PB10 +- I2C2_SDA : PB11 + +For more details please refer to `STM32VLDISCOVERY board User Manual`_. + +Programming and Debugging +************************* + +Applications for the ``stm32vl_disco`` board configuration can be built and +flashed in the usual way (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Flashing +======== + +STM32VLDISCOVERY board includes an ST-LINK/V1 embedded debug tool interface. +This interface is supported by the openocd version included in the Zephyr SDK. + +Flashing an application +----------------------- + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32vl_disco + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: stm32vl_disco + :maybe-skip-config: + :goals: debug + +USB mass storage issues +======================= + +The ST-LINK/V1 includes a buggy USB mass storage gadget. To connect to the +ST-LINK from Linux, you might need to ignore the device using modprobe +configuration parameters: + +.. code-block:: shell + + $ echo "options usb-storage quirks=483:3744:i" | sudo tee /etc/modprobe.d/local.conf + $ sudo modprobe -r usb-storage + +References +********** + +.. target-notes:: + +.. _STM32VLDISCOVERY website: + https://www.st.com/en/evaluation-tools/stm32vldiscovery.html + +.. _STM32F100x reference manual: + https://www.st.com/resource/en/reference_manual/cd00246267.pdf + +.. _STM32F100x data sheet: + https://www.st.com/resource/en/datasheet/stm32f100cb.pdf + +.. _STM32VLDISCOVERY board User Manual: + https://www.st.com/resource/en/user_manual/cd00267113.pdf diff --git a/boards/arm/stm32vl_disco/stm32vl_disco.dts b/boards/st/stm32vl_disco/stm32vl_disco.dts similarity index 100% rename from boards/arm/stm32vl_disco/stm32vl_disco.dts rename to boards/st/stm32vl_disco/stm32vl_disco.dts diff --git a/boards/arm/stm32vl_disco/stm32vl_disco.yaml b/boards/st/stm32vl_disco/stm32vl_disco.yaml similarity index 100% rename from boards/arm/stm32vl_disco/stm32vl_disco.yaml rename to boards/st/stm32vl_disco/stm32vl_disco.yaml diff --git a/boards/arm/stm32vl_disco/stm32vl_disco_defconfig b/boards/st/stm32vl_disco/stm32vl_disco_defconfig similarity index 80% rename from boards/arm/stm32vl_disco/stm32vl_disco_defconfig rename to boards/st/stm32vl_disco/stm32vl_disco_defconfig index ee2e8b8462ac5b..9472e788675c1f 100644 --- a/boards/arm/stm32vl_disco/stm32vl_disco_defconfig +++ b/boards/st/stm32vl_disco/stm32vl_disco_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -# Platform Configuration -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F100XB=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/stm32vl_disco/support/openocd.cfg b/boards/st/stm32vl_disco/support/openocd.cfg similarity index 100% rename from boards/arm/stm32vl_disco/support/openocd.cfg rename to boards/st/stm32vl_disco/support/openocd.cfg diff --git a/boards/st/stm32wb5mm_dk/Kconfig.defconfig b/boards/st/stm32wb5mm_dk/Kconfig.defconfig new file mode 100644 index 00000000000000..37be19b4d1c657 --- /dev/null +++ b/boards/st/stm32wb5mm_dk/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WB5MM-DK Discovery Development board configuration + +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32WB5MM_DK + +choice BT_HCI_BUS_TYPE + default BT_STM32_IPM + depends on BT +endchoice + +endif diff --git a/boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk b/boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk new file mode 100644 index 00000000000000..209ab102ba51f4 --- /dev/null +++ b/boards/st/stm32wb5mm_dk/Kconfig.stm32wb5mm_dk @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32WB5MM_DK + select SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mm_dk/board.cmake b/boards/st/stm32wb5mm_dk/board.cmake similarity index 100% rename from boards/arm/stm32wb5mm_dk/board.cmake rename to boards/st/stm32wb5mm_dk/board.cmake diff --git a/boards/st/stm32wb5mm_dk/board.yml b/boards/st/stm32wb5mm_dk/board.yml new file mode 100644 index 00000000000000..5df998d28c1152 --- /dev/null +++ b/boards/st/stm32wb5mm_dk/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32wb5mm_dk + vendor: st + socs: + - name: stm32wb55xx diff --git a/boards/arm/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg b/boards/st/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg similarity index 100% rename from boards/arm/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg rename to boards/st/stm32wb5mm_dk/doc/img/STM32WB5MM_DK.jpg diff --git a/boards/arm/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst similarity index 99% rename from boards/arm/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst rename to boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst index 61b701066014d5..a149ea79a3679e 100644 --- a/boards/arm/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst +++ b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst @@ -126,7 +126,7 @@ The Zephyr STM32WB5MM-DK board configuration supports the following hardware fea Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig`` +:zephyr_file:`boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig` Bluetooth and compatibility with STM32WB Copro Wireless Binaries ================================================================ diff --git a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.dts b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts similarity index 100% rename from boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.dts rename to boards/st/stm32wb5mm_dk/stm32wb5mm_dk.dts diff --git a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.yaml b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml similarity index 100% rename from boards/arm/stm32wb5mm_dk/stm32wb5mm_dk.yaml rename to boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml diff --git a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig similarity index 83% rename from boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig rename to boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig index 9fdd732848efc4..75373aa997cfc4 100644 --- a/boards/arm/stm32wb5mm_dk/stm32wb5mm_dk_defconfig +++ b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WBX=y -CONFIG_SOC_STM32WB55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32wb5mm_dk/support/openocd.cfg b/boards/st/stm32wb5mm_dk/support/openocd.cfg similarity index 100% rename from boards/arm/stm32wb5mm_dk/support/openocd.cfg rename to boards/st/stm32wb5mm_dk/support/openocd.cfg diff --git a/boards/st/stm32wb5mmg/Kconfig.defconfig b/boards/st/stm32wb5mmg/Kconfig.defconfig new file mode 100644 index 00000000000000..e63531f897bac2 --- /dev/null +++ b/boards/st/stm32wb5mmg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# STM32WB5MMG Bluetooth module board configuration + +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_STM32WB5MMG + +choice BT_HCI_BUS_TYPE + default BT_STM32_IPM + depends on BT +endchoice + +endif diff --git a/boards/st/stm32wb5mmg/Kconfig.stm32wb5mmg b/boards/st/stm32wb5mmg/Kconfig.stm32wb5mmg new file mode 100644 index 00000000000000..7e755aa1505d80 --- /dev/null +++ b/boards/st/stm32wb5mmg/Kconfig.stm32wb5mmg @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Javad Rahimipetroudi +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_STM32WB5MMG + select SOC_STM32WB55XX diff --git a/boards/arm/stm32wb5mmg/board.cmake b/boards/st/stm32wb5mmg/board.cmake similarity index 100% rename from boards/arm/stm32wb5mmg/board.cmake rename to boards/st/stm32wb5mmg/board.cmake diff --git a/boards/st/stm32wb5mmg/board.yml b/boards/st/stm32wb5mmg/board.yml new file mode 100644 index 00000000000000..dc90a918930fe9 --- /dev/null +++ b/boards/st/stm32wb5mmg/board.yml @@ -0,0 +1,5 @@ +board: + name: stm32wb5mmg + vendor: st + socs: + - name: stm32wb55xx diff --git a/boards/arm/stm32wb5mmg/doc/img/STM32WB5MMG.jpg b/boards/st/stm32wb5mmg/doc/img/STM32WB5MMG.jpg similarity index 100% rename from boards/arm/stm32wb5mmg/doc/img/STM32WB5MMG.jpg rename to boards/st/stm32wb5mmg/doc/img/STM32WB5MMG.jpg diff --git a/boards/arm/stm32wb5mmg/doc/stm32wb5mmg.rst b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst similarity index 99% rename from boards/arm/stm32wb5mmg/doc/stm32wb5mmg.rst rename to boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst index 90561ee1275336..13446524535a73 100644 --- a/boards/arm/stm32wb5mmg/doc/stm32wb5mmg.rst +++ b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst @@ -179,7 +179,7 @@ The Zephyr STM32WB5MMG board configuration supports the following hardware featu Other hardware features are not yet supported on this Zephyr port. The default configuration can be found in the defconfig file: -``boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig`` +:zephyr_file:`boards/st/stm32wb5mmg/stm32wb5mmg_defconfig` Bluetooth and compatibility with STM32WB Copro Wireless Binaries ================================================================ diff --git a/boards/arm/stm32wb5mmg/stm32wb5mmg.dts b/boards/st/stm32wb5mmg/stm32wb5mmg.dts similarity index 100% rename from boards/arm/stm32wb5mmg/stm32wb5mmg.dts rename to boards/st/stm32wb5mmg/stm32wb5mmg.dts diff --git a/boards/arm/stm32wb5mmg/stm32wb5mmg.yaml b/boards/st/stm32wb5mmg/stm32wb5mmg.yaml similarity index 100% rename from boards/arm/stm32wb5mmg/stm32wb5mmg.yaml rename to boards/st/stm32wb5mmg/stm32wb5mmg.yaml diff --git a/boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig b/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig similarity index 83% rename from boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig rename to boards/st/stm32wb5mmg/stm32wb5mmg_defconfig index 9fdd732848efc4..75373aa997cfc4 100644 --- a/boards/arm/stm32wb5mmg/stm32wb5mmg_defconfig +++ b/boards/st/stm32wb5mmg/stm32wb5mmg_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_STM32WBX=y -CONFIG_SOC_STM32WB55XX=y - # enable uart driver CONFIG_SERIAL=y diff --git a/boards/arm/stm32wb5mmg/support/openocd.cfg b/boards/st/stm32wb5mmg/support/openocd.cfg similarity index 100% rename from boards/arm/stm32wb5mmg/support/openocd.cfg rename to boards/st/stm32wb5mmg/support/openocd.cfg diff --git a/boards/synopsys/em_starterkit/CMakeLists.txt b/boards/synopsys/em_starterkit/CMakeLists.txt new file mode 100644 index 00000000000000..b936308cb37df6 --- /dev/null +++ b/boards/synopsys/em_starterkit/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +if((CONFIG_BOARD_EM_STARTERKIT_EMSK_EM9D OR CONFIG_BOARD_EM_STARTERKIT_EMSK_EM11D) AND "${BOARD_REVISION}" STREQUAL "2.2") + message(FATAL_ERROR "Board revision 2.2 is not supported for this SoC") +endif() + +zephyr_sources(pmodmux.c) +zephyr_sources_ifdef(CONFIG_ARC_MPU_ENABLE arc_mpu_regions.c) diff --git a/boards/synopsys/em_starterkit/Kconfig.defconfig b/boards/synopsys/em_starterkit/Kconfig.defconfig new file mode 100644 index 00000000000000..7713228ddb8416 --- /dev/null +++ b/boards/synopsys/em_starterkit/Kconfig.defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +if BOARD_EM_STARTERKIT + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 100 + +endif # I2C_DW + +endif # BOARD_EM_STARTERKIT diff --git a/boards/synopsys/em_starterkit/Kconfig.em_starterkit b/boards/synopsys/em_starterkit/Kconfig.em_starterkit new file mode 100644 index 00000000000000..33967621ddef47 --- /dev/null +++ b/boards/synopsys/em_starterkit/Kconfig.em_starterkit @@ -0,0 +1,17 @@ +# DesignWare ARC EM Starter Kit board configuration + +# Copyright (c) 2016 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EM_STARTERKIT + select SOC_EMSK + select SOC_EMSK_EM7D if BOARD_EM_STARTERKIT_EMSK_EM7D + select SOC_EMSK_EM9D if BOARD_EM_STARTERKIT_EMSK_EM9D + select SOC_EMSK_EM11D if BOARD_EM_STARTERKIT_EMSK_EM11D + help + The DesignWare ARC EM Starter Kit board is a board + that can host up to 3 different SOC FPGA bit files. + Both version 2.2 and 2.3 firmware have EM7D, EM9D and EM11D configurations. + EM9D using CCM memories and is a Harvard Architecture. + EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache. + EM7D of EMSK 2.3 supports secure mode. diff --git a/boards/arc/em_starterkit/arc_mpu_regions.c b/boards/synopsys/em_starterkit/arc_mpu_regions.c similarity index 100% rename from boards/arc/em_starterkit/arc_mpu_regions.c rename to boards/synopsys/em_starterkit/arc_mpu_regions.c diff --git a/boards/synopsys/em_starterkit/board.cmake b/boards/synopsys/em_starterkit/board.cmake new file mode 100644 index 00000000000000..48fa1722e4df61 --- /dev/null +++ b/boards/synopsys/em_starterkit/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +board_runner_args(openocd "--use-elf") +board_runner_args(mdb-hw "--jtag=digilent") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/synopsys/em_starterkit/board.dtsi b/boards/synopsys/em_starterkit/board.dtsi new file mode 100644 index 00000000000000..f447d53e2fc7cc --- /dev/null +++ b/boards/synopsys/em_starterkit/board.dtsi @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2017 Synopsys */ + +#include + +/ { + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + led4 = &led4; + led5 = &led5; + led6 = &led6; + led7 = &led7; + led8 = &led8; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio1 0 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpio1 1 0>; + label = "LED 1"; + }; + led2: led_2 { + gpios = <&gpio1 2 0>; + label = "LED 2"; + }; + led3: led_3 { + gpios = <&gpio1 3 0>; + label = "LED 3"; + }; + led4: led_4 { + gpios = <&gpio1 4 0>; + label = "LED 4"; + }; + led5: led_5 { + gpios = <&gpio1 5 0>; + label = "LED 5"; + }; + led6: led_6 { + gpios = <&gpio1 6 0>; + label = "LED 6"; + }; + led7: led_7 { + gpios = <&gpio1 7 0>; + label = "LED 7"; + }; + led8: led_8 { + gpios = <&gpio1 8 0>; + label = "LED 8"; + }; + + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + label = "Push button switch 0"; + zephyr,code = ; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button2: button_2 { + /* gpio flags need validation */ + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + label = "Push button switch 2"; + zephyr,code = ; + }; + switch0: switch_0 { + /* gpio flags need validation */ + gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 1"; + zephyr,code = ; + }; + switch1: switch_1 { + /* gpio flags need validation */ + gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 2"; + zephyr,code = ; + }; + switch2: switch_2 { + /* gpio flags need validation */ + gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 3"; + zephyr,code = ; + }; + switch3: switch_3 { + /* gpio flags need validation */ + gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; + label = "DIP SW1 - Switch 4"; + zephyr,code = ; + }; + }; + +}; diff --git a/boards/synopsys/em_starterkit/board.yml b/boards/synopsys/em_starterkit/board.yml new file mode 100644 index 00000000000000..b5c30f1ba9d67c --- /dev/null +++ b/boards/synopsys/em_starterkit/board.yml @@ -0,0 +1,13 @@ +board: + name: em_starterkit + vendor: snps + socs: + - name: emsk_em7d + - name: emsk_em9d + - name: emsk_em11d + revision: + format: major.minor.patch + default: "2.3" + revisions: + - name: "2.2" + - name: "2.3" diff --git a/boards/arc/em_starterkit/doc/em_starterkit.jpg b/boards/synopsys/em_starterkit/doc/em_starterkit.jpg similarity index 100% rename from boards/arc/em_starterkit/doc/em_starterkit.jpg rename to boards/synopsys/em_starterkit/doc/em_starterkit.jpg diff --git a/boards/synopsys/em_starterkit/doc/index.rst b/boards/synopsys/em_starterkit/doc/index.rst new file mode 100644 index 00000000000000..9d71b4f7678808 --- /dev/null +++ b/boards/synopsys/em_starterkit/doc/index.rst @@ -0,0 +1,318 @@ +.. _em_starterkit: + +DesignWare(R) ARC(R) EM Starter Kit +################################### + +Overview +******** + +The DesignWare(R) ARC(R) EM Starter Kit is a low-cost, versatile solution +enabling rapid software development and software debugging, and profiling +for the ARC EM Family of processors. The EM Family includes the EM4, EM6, +EM5D, EM7D, EM9D, and EM11D cores. The Zephyr RTOS can be used with the +EM Starter Kit. + +.. image:: em_starterkit.jpg + :align: center + :alt: DesignWare(R) ARC(R) EM Starter Kit (synopsys.com) + +The ARC EM Starter Kit consists of a hardware platform, including pre-installed +FPGA images of different ARC EM processor configurations with peripherals. +Documentation for this board can be found at `embARC website`_. + +See also this URL for details about the board: +`Designware ARC EM Starter Kit website`_ . + +The latest version of EM Starter Kit is 2.3, developer can upgrade from +2.0/2.1/2.2 to 2.3 using latest firmware. +The default configuration for EM Starter Kit boards can be found in +:zephyr_file:`boards/synopsys/em_starterkit/em_starterkit_defconfig`. + +The default SoC for this board supported in Zephyr is the EM9D. +This configuration is a Harvard Architecture, with a separate +instruction bus and data bus. Instruction memory is called ICCM +and data memory is called DCCM. The configuration file for EM9D +is found in :zephyr_file:`soc/synopsys/emsk/Kconfig.defconfig.em9d`. + +If you have a larger program, you can select the EM7D or EM11D, which gives +access to 128KB DRAM with i-cache and d-cache. The configuration file for EM7D +is found in :zephyr_file:`soc/synopsys/emsk/Kconfig.defconfig.em7d` and EM11D is +found in :zephyr_file:`soc/synopsys/emsk/Kconfig.defconfig.em11d`. + + +Hardware +******** +Board Layout +============ + +The ARC EM Starter Kit main board has 6 Pmod connectors. These can be configured +to support attachment of GPIO, I2C, UART or SPI devices. + +The board also has a 16MB SPI-FLASH and an SDCard for storage. There are 9 LEDs, +3 buttons, and 4 dip switches that can be used with GPIO. + +The Xilinx Spartan(R)-6 LX150 FPGA can auto-load one of 3 FPGA SoC bit files +which have the EM7D, EM9D, or EM11D SoC. + +Documentation and general information for the board can be found at the +`embARC website`_, which also includes some free sample software. + + +Supported Firmware Versions +=========================== + +The EM Starter Kit has different versions, such as 1.0, 1.1, 2.0, 2.1, +2.2 and 2.3. +In Zephyr, only firmware versions 2.2 and 2.3 are supported. + +Supported Features +================== + +The Zephyr kernel supports multiple hardware features on the EM Starter Kit +through the use of device drivers. + +The EM Starter Kit supports 6 Digilent Pmod(TM) Interfaces, which enables the +use of a large variety of pluggable modules for storage, communications, +sensors, displays, etc. With the Pmod interface, you can prototype your +applications using the Zephyr RTOS. + +The table below shows which drivers are supported and which functionality can +be found on which architectures: + ++-----------+------------+-----+-------+-----------------------+ +| Interface | Controller |EM9D | EM11D | Driver/Component | ++===========+============+=====+=======+=======================+ +| INT | on-chip | Y | Y | interrupt_controller | ++-----------+------------+-----+-------+-----------------------+ +| UART | usb + | Y | Y | serial port-polling; | +| | 2 Pmods | | | serial port-interrupt | ++-----------+------------+-----+-------+-----------------------+ +| SPI | 2 Pmods | Y | Y | spi | ++-----------+------------+-----+-------+-----------------------+ +| ADC | n/a | N | N | adc (can add via Pmod)| ++-----------+------------+-----+-------+-----------------------+ +| I2C | 2 Pmods | Y | Y | i2c | ++-----------+------------+-----+-------+-----------------------+ +| GPIO | 6 Pmods | Y | Y | gpio | ++-----------+------------+-----+-------+-----------------------+ +| PWM | n/a | N | N | pwm | ++-----------+------------+-----+-------+-----------------------+ + +The board has 3 (debounced and interrupting) buttons for use with GPIO, 4 dip +switches, 9 LEDs, SDCard on SPI, and a 16MB SPI-Flash memory. + +The SPI-FLASH driver is supported with sample, which can be found in +``samples/drivers/spi_flash``. + +The SPI-Flash also holds 3 (or 4) separate FPGA CPU bit files, selectable via +dip switch. + +The SPI-Flash is also programmed with a bootloader. The bootloader can copy a +program image from SPI-Flash into executable memory. Zephyr initialization will +copy the initialized data section to the data memory if CONFIG_XIP is used. + + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the EM Starter Kit board, a few additional +pieces of hardware are required. + +* USB Cable (delivered as part of the ARC EM Starter Kit) + +* The USB cable provides power to the board; however, if the board is to run + standalone, the universal switching power adaptor (110-240V AC to 5V DC), + provided in the package, can be used to power the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the ARC EM Starter Kit +============================= + +To run Zephyr application on correct arc core of EM Starter Kit, you need to +setup the board correctly. + +* Connect the digilent usb cable from your host to the board. + +* Connect the 5V DC power supply to your board. + +* Select the core configuration of the board by choosing correct dip switch + SW1 settings, then press then FPGA configure button located above the letter + 'C' of the ARC logo on the board. + +* Then the board will be reconfigured with selected core configuration, you + can download and debug Zephyr application now. + +* If you want to know more about how to use this board, you can take a look + at the `ARC EM Starter Kit User Guide`_. + +Set up Zephyr Software +====================== + +Since there are different firmware versions of EM Starter Kit, you need to +choose the proper firmware version supported in Zephyr. + +Three different configurations exist for this board: + +* EM7D: em_starterkit_em7d_defconfig +* EM9D: em_starterkit_defconfig +* EM11D: em_starterkit_em11d_defconfig + + +Building Sample Applications +============================== + +You can try many of the sample applications or tests, but let us discuss +the one called :ref:`hello_world`. +It is found in :zephyr_file:`samples/hello_world`. + +Configuring +----------- + +You may need to write a prj_arc.conf file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By +specifying ``em_starterkit`` as the board configuration, you can select the ARC +EM Starter Kit board support for Zephyr. + +.. zephyr-app-commands:: + :board: em_starterkit + :zephyr-app: samples/hello_world + :goals: menuconfig + +On this board you will also need to consider the "ARC SoC Selection" and set +it either to EM9D or EM11D. To boot up the EM9D on the board, all dip +switches should be UP except for switch 1. Other configuration choices +are made in the normal way. To boot up the EM11D on the board, +all dip switches should be UP except for switch 2. Next press the button +above the letter C in the "ARC" logo on the silkscreen. + +Building +-------- + +You can build application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: em_starterkit + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's EM Starter Kit images support +serial output via the UART1 on the board. To enable serial output: + +On your development environment, you will need to: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) +* Specify the tty driver name, for example, on Linux this may be :file:`/dev/ttyUSB1` +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.9), you can debug and flash +EM Starterkit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands. + +.. zephyr-app-commands:: + :board: em_starterkit + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +'c' to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: em_starterkit + :app: + :goals: debugserver + +Then connect to the debug server at the EM Starter Kit from a second +console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/bin/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the EM Starter Kit's CCM +or DDR and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: em_starterkit + :goals: flash + +This command still uses openocd and gdb to load application elf file +to EM Starter Kit, but it will load application and then run immediately. +If power is lost, the application will also lost due to power loss. + +Most of the time you will not be flashing your program but will instead +debug it using openocd and gdb. The program can be download via the USB +cable into the code and data memories. + +When you are ready to deploy the program so that it boots up automatically +on reset or power-up, you can follow the steps to place the program on +SPI-FLASH. + +For instructions on how to write your program to SPI-FLASH, +refer to the documentation on the ARC EM Starter Kit at the +`embARC website`_, which includes instructions for how to place an +executable image onto the SPI-FLASH in such a way that it is understood +by the bootloader. + +Release Notes +************* + +The following is a list of TODO items: + +* ``GH-2647``: Zephyr needs i-cache API (all targets) +* ``GH-2230``: Zephyr ARC port doesn't yet support nested regular interrupts. +* pinmux driver: Possibly it can be written to configure PMods too. + +References +********** + +.. _embARC website: https://www.embarc.org + +.. _Designware ARC EM Starter Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit + +.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules + +.. _Putty website: http://www.putty.org + +.. _ARC EM Starter Kit User Guide: https://www.synopsys.com/dw/ipdir.php?ds=arc_em_starter_kit diff --git a/boards/synopsys/em_starterkit/em_starterkit_defconfig b/boards/synopsys/em_starterkit/em_starterkit_defconfig new file mode 100644 index 00000000000000..38979ec4912dbb --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_XIP=n +CONFIG_BUILD_NO_GAP_FILL=y +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.dts new file mode 100644 index 00000000000000..75a23beda8a398 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "em_starterkit_r23.dtsi" +#include "board.dtsi" + +/ { + model = "em_starterkit-em11d"; + compatible = "snps,em_starterkit-em11d", "snps,em_starterkit"; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + }; + + chosen { + zephyr,sram = &ddr0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + iccm0: iccm@0 { + compatible = "arc,iccm"; + reg = <0x0 DT_SIZE_K(64)>; + }; + + dccm0: dccm@80000000 { + compatible = "arc,dccm"; + reg = <0x80000000 DT_SIZE_K(64)>; + }; + + xccm@c0000000 { + compatible = "arc,xccm"; + reg = <0xc0000000 DT_SIZE_K(8)>; + }; + + yccm@e0000000 { + compatible = "arc,yccm"; + reg = <0xe0000000 DT_SIZE_K(8)>; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.yaml new file mode 100644 index 00000000000000..3189656c78f7a8 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em11d.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit/emsk_em11d +name: EM Starterkit EM11D +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.dts new file mode 100644 index 00000000000000..e170df7dd9590b --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.dts @@ -0,0 +1,5 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.yaml new file mode 100644 index 00000000000000..fe2276e2d738f2 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit/emsk_em7d +name: EM Starterkit EM7D +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d_v22.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.overlay similarity index 100% rename from boards/arc/em_starterkit/em_starterkit_em7d_v22.dts rename to boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.overlay diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml new file mode 100644 index 00000000000000..498333044249e3 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit@2.2/emsk_em7d +name: EM Starterkit EM7D +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_em7d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay similarity index 100% rename from boards/arc/em_starterkit/em_starterkit_em7d.dts rename to boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3.overlay diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig new file mode 100644 index 00000000000000..5ce90449df84a6 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_2_3_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +CONFIG_ARC_HAS_SECURE=y +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_INIT_ARCH_HW_AT_BOOT=y diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_defconfig b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_defconfig new file mode 100644 index 00000000000000..6685d5f940d866 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em7d_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Synopsys + +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.dts b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.dts new file mode 100644 index 00000000000000..63f97a132795ee --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.dts @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2018, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "em_starterkit_r23.dtsi" +#include "board.dtsi" + +/ { + model = "em_starterkit-em9d"; + compatible = "snps,em_starterkit-em9d", "snps,em_starterkit"; + + aliases { + uart-0 = &uart0; + uart-1 = &uart1; + uart-2 = &uart2; + }; + + chosen { + zephyr,sram = &dccm0; + zephyr,console = &uart1; + zephyr,shell-uart = &uart1; + }; + + iccm0: iccm@0 { + compatible = "arc,iccm"; + reg = <0x0 DT_SIZE_K(256)>; + }; + + dccm0: dccm@80000000 { + compatible = "arc,dccm"; + reg = <0x80000000 DT_SIZE_K(128)>; + }; + + xccm@c0000000 { + compatible = "arc,xccm"; + reg = <0xc0000000 DT_SIZE_K(8)>; + }; + + yccm@e0000000 { + compatible = "arc,yccm"; + reg = <0xe0000000 DT_SIZE_K(8)>; + }; +}; + +&uart1 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.yaml b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.yaml new file mode 100644 index 00000000000000..34b10ca6d7b270 --- /dev/null +++ b/boards/synopsys/em_starterkit/em_starterkit_emsk_em9d.yaml @@ -0,0 +1,17 @@ +identifier: em_starterkit/emsk_em9d +name: EM Starterkit +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +supported: + - i2c + - spi + - gpio +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/em_starterkit/em_starterkit_r22.dtsi b/boards/synopsys/em_starterkit/em_starterkit_r22.dtsi similarity index 100% rename from boards/arc/em_starterkit/em_starterkit_r22.dtsi rename to boards/synopsys/em_starterkit/em_starterkit_r22.dtsi diff --git a/boards/arc/em_starterkit/em_starterkit_r23.dtsi b/boards/synopsys/em_starterkit/em_starterkit_r23.dtsi similarity index 96% rename from boards/arc/em_starterkit/em_starterkit_r23.dtsi rename to boards/synopsys/em_starterkit/em_starterkit_r23.dtsi index ef93abcfd46d33..3de7425d975015 100644 --- a/boards/arc/em_starterkit/em_starterkit_r23.dtsi +++ b/boards/synopsys/em_starterkit/em_starterkit_r23.dtsi @@ -5,6 +5,10 @@ */ / { + aliases { + spi-flash0 = &w25q128bv; + }; + soc { i2c@f0004000 { interrupts = <25 1>; diff --git a/boards/arc/em_starterkit/pmodmux.c b/boards/synopsys/em_starterkit/pmodmux.c similarity index 100% rename from boards/arc/em_starterkit/pmodmux.c rename to boards/synopsys/em_starterkit/pmodmux.c diff --git a/boards/arc/em_starterkit/support/openocd.cfg b/boards/synopsys/em_starterkit/support/openocd.cfg similarity index 100% rename from boards/arc/em_starterkit/support/openocd.cfg rename to boards/synopsys/em_starterkit/support/openocd.cfg diff --git a/boards/arc/emsdp/CMakeLists.txt b/boards/synopsys/emsdp/CMakeLists.txt similarity index 100% rename from boards/arc/emsdp/CMakeLists.txt rename to boards/synopsys/emsdp/CMakeLists.txt diff --git a/boards/synopsys/emsdp/Kconfig.defconfig b/boards/synopsys/emsdp/Kconfig.defconfig new file mode 100644 index 00000000000000..cfe387e3f25817 --- /dev/null +++ b/boards/synopsys/emsdp/Kconfig.defconfig @@ -0,0 +1,15 @@ +# DesignWare ARC EM Software Development Platform board configuration + +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EMSDP + +if SPI + +config SPI_DW + default y + +endif # SPI + +endif # BOARD_EMSDP diff --git a/boards/synopsys/emsdp/Kconfig.emsdp b/boards/synopsys/emsdp/Kconfig.emsdp new file mode 100644 index 00000000000000..55afa1582b6979 --- /dev/null +++ b/boards/synopsys/emsdp/Kconfig.emsdp @@ -0,0 +1,21 @@ +# DesignWare ARC EM Software Development Platform board configuration + +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EMSDP + select SOC_ARC_EMSDP + select SOC_EMSDP_EM4 if BOARD_EMSDP_EMSDP_EM4 + select SOC_EMSDP_EM5D if BOARD_EMSDP_EMSDP_EM5D + select SOC_EMSDP_EM6 if BOARD_EMSDP_EMSDP_EM6 + select SOC_EMSDP_EM7D if BOARD_EMSDP_EMSDP_EM7D + select SOC_EMSDP_EM7D_ESP if BOARD_EMSDP_EMSDP_EM7D_ESP + select SOC_EMSDP_EM9D if BOARD_EMSDP_EMSDP_EM9D + select SOC_EMSDP_EM11D if BOARD_EMSDP_EMSDP_EM11D + help + The ARC EM Software Development Platform (emsdp) is an FPGA based + development platform intended to support ARC licenses in developing + their software for the ARC EM processor family and ARC EM Subsystems. + It has the support for ARC EM4, EM5D, EM6, EM7D, EM9D and EM11D + processors. ARC EM Enhanced Security Package (ESP) and ARC EM + Subsystems (DFSS, SCSS, DSS) are also supported. diff --git a/boards/arc/emsdp/arc_mpu_regions.c b/boards/synopsys/emsdp/arc_mpu_regions.c similarity index 100% rename from boards/arc/emsdp/arc_mpu_regions.c rename to boards/synopsys/emsdp/arc_mpu_regions.c diff --git a/boards/arc/em_starterkit/board.cmake b/boards/synopsys/emsdp/board.cmake similarity index 100% rename from boards/arc/em_starterkit/board.cmake rename to boards/synopsys/emsdp/board.cmake diff --git a/boards/arc/emsdp/board.dtsi b/boards/synopsys/emsdp/board.dtsi similarity index 100% rename from boards/arc/emsdp/board.dtsi rename to boards/synopsys/emsdp/board.dtsi diff --git a/boards/synopsys/emsdp/board.yml b/boards/synopsys/emsdp/board.yml new file mode 100644 index 00000000000000..463c30bc2fc1fb --- /dev/null +++ b/boards/synopsys/emsdp/board.yml @@ -0,0 +1,11 @@ +board: + name: emsdp + vendor: snps + socs: + - name: emsdp_em4 + - name: emsdp_em5d + - name: emsdp_em6 + - name: emsdp_em7d + - name: emsdp_em7d_esp + - name: emsdp_em9d + - name: emsdp_em11d diff --git a/boards/arc/emsdp/doc/emsdp.jpg b/boards/synopsys/emsdp/doc/emsdp.jpg similarity index 100% rename from boards/arc/emsdp/doc/emsdp.jpg rename to boards/synopsys/emsdp/doc/emsdp.jpg diff --git a/boards/synopsys/emsdp/doc/index.rst b/boards/synopsys/emsdp/doc/index.rst new file mode 100644 index 00000000000000..fa4606d98f89e1 --- /dev/null +++ b/boards/synopsys/emsdp/doc/index.rst @@ -0,0 +1,286 @@ +.. _emsdp: + +DesignWare(R) ARC(R) EM Software Development Platform +##################################################### + +Overview +******** + +The DesignWare® ARC® EM Software Development Platform (SDP) is a flexible platform +for rapid software development on ARC EM processor-based subsystems. It is intended +to accelerate software development and debug of ARC EM processors and subsystems for +a wide range of ultra-low power embedded applications such as IoT, sensor fusion, +and voice applications. + +.. image:: emsdp.jpg + :align: center + :alt: DesignWare(R) ARC(R) EM Software Development Platform (synopsys.com) + +For details about the board, see: `DesignWare ARC EM Software Development Platform +(EM SDP) `__ + + +Hardware +******** + +The EM Software Development Platform supports different core configurations, such as EM4, +EM5D, EM6, EM7D, EM7D+ESP, EM9D, EM11D. The core must be supplied as the variant of the base +board which takes the form ``emsdp/`` whereby core is ``emsdp_em4`` for EM4, +``emsdp_em5D`` for EM5D, ``emsdp_em6`` for EM6, ``emsdp_em7d`` for EM7D, ``emsdp_em7d_esp`` +for EM7D+ESP, ``emsdp_em9d`` for EM9D and ``emsdp_em11d`` for EM11D. + +The following table shows the hardware features supported for different core configuration: + ++-----------+-----+-----+------+------+----------+------+-------+ +| Features | EM4 | EM6 | EM5D | EM7D | EM7D_ESP | EM9D | EM11D | ++===========+=====+=====+======+======+==========+======+=======+ +| Caches | N | Y | N | Y | Y | N | Y | ++-----------+-----+-----+------+------+----------+------+-------+ +| DSP | N | N | Y | Y | Y | Y | Y | ++-----------+-----+-----+------+------+----------+------+-------+ +| XY Memory | N | N | N | N | N | Y | Y | ++-----------+-----+-----+------+------+----------+------+-------+ +| Secure | N | N | N | N | Y | N | N | ++-----------+-----+-----+------+------+----------+------+-------+ + +The table below shows which drivers are currently available in Zephyr. + ++-----------+------------+-------+-----------------------+ +| Interface | Controller | EMSDP | Driver/Component | ++===========+============+=======+=======================+ +| SDIO | on-chip | N | SD-card controller | ++-----------+------------+-------+-----------------------+ +| UART | Arduino + | Y | serial port-polling; | +| | 3 Pmods | | serial port-interrupt | ++-----------+------------+-------+-----------------------+ +| SPI | Arduino + | Y | spi | +| | Pmod + adc | | | ++-----------+------------+-------+-----------------------+ +| ADC | 1 Pmod | N | adc (via spi) | ++-----------+------------+-------+-----------------------+ +| I2C | Arduino + | N | i2c | +| | Pmod | | | ++-----------+------------+-------+-----------------------+ +| GPIO | Arduino + | Y | gpio | +| | Pmod + Pin | | | ++-----------+------------+-------+-----------------------+ +| PWM | Arduino + | N | pwm | +| | Pmod | | | ++-----------+------------+-------+-----------------------+ +| I2S | on-chip | N | Audio interface | ++-----------+------------+-------+-----------------------+ + +Support two 32 MByte Quad-SPI Flash memory, one only contains FPGA image, the other +one is user SPI-FLASH, which is connected via SPI bus and its sample can be found in +``samples/drivers/spi_flash``. + +To configure the FPGA, The ARC EM SDP offers a single USB 2.0 host port, which is +both used to access the FPGAs configuration memory and as a DEBUG/ UART port. + +When connected using the USB cable to a PC, the ARC EM SDP presents itself as a mass +storage device. This allows an FPGA configuration bitstream to be dragged and dropped into +the configuration memory. The FPGA bitstream is automatically loaded into the FPGA device +upon power-on reset, or when the configuration button is pressed. + +For hardware feature details, refer to : `ARC EM Software Development Platform +`__ + +Peripheral driver test and sample +================================= + +``tests/drivers/spi/spi_loopback``: verify DesignWare SPI driver. No need to connect +MISO with MOSI, DW SPI register is configured to internally connect them. This test +use two different speed to verify data transfer with asynchronous functionality. +Note: DW SPI only available on SPI0 and SPI1. + +``samples/drivers/spi_flash``: Verfiy DW SPI and SPI-FLASH on SPI1. First erase the +whole flash then write 4 byte data to the flash. Read from the flash and compare the +result with buffer to check functionality. + +Pinmux interface +================ + +The following pinmux peripheral module standards are supported: + +* Digilent Pmod (3x) + +The ARC EM SDP features three 12-pin Pmod connectors: Pmod_A, Pmod_B, and Pmod_C. +The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, +I2C, and PWM (Note: support two type UART Pmod interface: UARTA is newer version). +Multiplexing is controlled by software using the PMOD_MUX_CTRL register. + +* Arduino (1x) + +The ARC EM SDP provides an Arduino shield interface. Multiplexing is controlled by software +using the ARDUINO_MUX_CTRL register. Note: some IO must be programmed in group and can't be +set individually, for details see Table 9 in `EM Software Development Platform user guide`_. + +* MikroBUS (1x) + +Note that since the controllers that are mapped to the MikroBUS are shared with the Arduino +controllers, and therefore the MikroBUS functions are only available when the Arduino +multiplexer ARDUINO_MUX_CTRL is in the default mode (GPIO). + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the EM Software Development Platform board, +a few additional pieces of hardware are required. + +* A micro USB cable to connect the computer. + +* A universal switching power adaptor (110-240V AC to 12 DC), + provided in the package, which used to power the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods, Arduino modules, or Mikro modules. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the EM Software Development Platform +=========================================== + +To run Zephyr application on EM Software Development Platform, you need to +setup the board correctly. + +* Connect the 12V DC power supply to your board. + +* Connect the digilent usb cable from your host to the board. + +Set up Zephyr Software +====================== + +Building Sample Applications +============================== + +You can try many of the sample applications or tests, but let us discuss +the one called :ref:`hello_world`. +It is found in :zephyr_file:`samples/hello_world`. + +Configuring +----------- + +You may need to write a prj_arc.conf file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By specifying +``emsdp`` as the board configuration, you can select the ARC EM Software +Development Platform board support for Zephyr, note that the core also need to +be supplied, for example for the em7d: + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em7d + :zephyr-app: samples/hello_world + :goals: menuconfig + + +Building +-------- + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world` for the em4. + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em4 + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's EM Software Development Platform images +support serial output via the USB-UART on the board. To enable serial output: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) + +* Specify the tty driver name, for example, on Linux this may be + :file:`/dev/ttyUSB0` + +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.9), you can debug and flash IoT +Development Kit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands, for example for the em6 + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em6 + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +'c' to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em6 + :app: + :goals: debugserver + +Then connect to the debug server at the EM Software Development Platform from a +second console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/ \ + arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the EM Software Development +Platform's CCM and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: emsdp/emsdp_em6 + :app: + :goals: flash + +This command still uses openocd and gdb to load the application elf file to EM +Software Development Platform, but it will load the application and immediately run. +If power is removed, the application will be lost since it wasn't written to flash. + +Most of the time you will not be flashing your program but will instead debug +it using openocd and gdb. The program can be download via the USB cable into +the code and data memories. + +References +********** + +.. target-notes:: + +.. _EM Software Development Platform user guide: + https://www.synopsys.com/dw/ipdir.php?ds=arc-em-software-development-platform + +.. _Digilent Pmod Modules: + http://store.digilentinc.com/pmod-modules + +.. _Putty website: + http://www.putty.org diff --git a/boards/arc/emsdp/emsdp-pinctrl.dtsi b/boards/synopsys/emsdp/emsdp-pinctrl.dtsi similarity index 100% rename from boards/arc/emsdp/emsdp-pinctrl.dtsi rename to boards/synopsys/emsdp/emsdp-pinctrl.dtsi diff --git a/boards/arc/emsdp/emsdp_defconfig b/boards/synopsys/emsdp/emsdp_defconfig similarity index 76% rename from boards/arc/emsdp/emsdp_defconfig rename to boards/synopsys/emsdp/emsdp_defconfig index 2480ef52f3bac4..d8581e40fabcaa 100644 --- a/boards/arc/emsdp/emsdp_defconfig +++ b/boards/synopsys/emsdp/emsdp_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_EMSDP=y -CONFIG_SOC_EMSDP_EM11D=y -CONFIG_BOARD_EMSDP=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y @@ -15,5 +12,3 @@ CONFIG_SERIAL=y CONFIG_UART_INTERRUPT_DRIVEN=y CONFIG_ARC_MPU_ENABLE=y CONFIG_GPIO=y -CONFIG_SPI=y -CONFIG_PINCTRL=y diff --git a/boards/arc/emsdp/emsdp.dts b/boards/synopsys/emsdp/emsdp_emsdp_em11d.dts similarity index 100% rename from boards/arc/emsdp/emsdp.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em11d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em11d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em11d.yaml new file mode 100644 index 00000000000000..b9c1868a133a00 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em11d.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em11d +name: EM Software Development Platform (EM11D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em11d_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em11d_defconfig new file mode 100644 index 00000000000000..ac2ac3efaaa635 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em11d_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y +CONFIG_PINCTRL=y diff --git a/boards/arc/emsdp/emsdp_em4.dts b/boards/synopsys/emsdp/emsdp_emsdp_em4.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em4.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em4.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em4.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em4.yaml new file mode 100644 index 00000000000000..96f05b3251ff0e --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em4.yaml @@ -0,0 +1,14 @@ +identifier: emsdp/emsdp_em4 +name: EM Software Development Platform (EM4) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/emsdp/emsdp_em5d.dts b/boards/synopsys/emsdp/emsdp_emsdp_em5d.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em5d.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em5d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em5d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em5d.yaml new file mode 100644 index 00000000000000..91f3c1d1c4e56f --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em5d.yaml @@ -0,0 +1,14 @@ +identifier: emsdp/emsdp_em5d +name: EM Software Development Platform (EM5D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em5d_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em5d_defconfig new file mode 100644 index 00000000000000..e3abf3f96b6bc3 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em5d_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em6.dts b/boards/synopsys/emsdp/emsdp_emsdp_em6.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em6.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em6.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em6.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em6.yaml new file mode 100644 index 00000000000000..0c74c5b7c2144b --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em6.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em6 +name: EM Software Development Platform (EM6) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em6_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em6_defconfig new file mode 100644 index 00000000000000..e3abf3f96b6bc3 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em6_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em7d.dts b/boards/synopsys/emsdp/emsdp_emsdp_em7d.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em7d.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em7d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em7d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em7d.yaml new file mode 100644 index 00000000000000..94dfbdd2af055b --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em7d.yaml @@ -0,0 +1,14 @@ +identifier: emsdp/emsdp_em7d +name: EM Software Development Platform (EM7D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/emsdp/emsdp_em7d_esp.dts b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em7d_esp.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.yaml new file mode 100644 index 00000000000000..fcbc5e24c74cd7 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em7d_esp +name: EM Software Development Platform (EM7D_ESP) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp_defconfig new file mode 100644 index 00000000000000..a0da795360adce --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em7d_esp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARC_HAS_SECURE=y +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_SPI=y diff --git a/boards/arc/emsdp/emsdp_em9d.dts b/boards/synopsys/emsdp/emsdp_emsdp_em9d.dts similarity index 100% rename from boards/arc/emsdp/emsdp_em9d.dts rename to boards/synopsys/emsdp/emsdp_emsdp_em9d.dts diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em9d.yaml b/boards/synopsys/emsdp/emsdp_emsdp_em9d.yaml new file mode 100644 index 00000000000000..e22e8d3709214e --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em9d.yaml @@ -0,0 +1,16 @@ +identifier: emsdp/emsdp_em9d +name: EM Software Development Platform (EM9D) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools +ram: 128 +supported: + - spi +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/emsdp/emsdp_emsdp_em9d_defconfig b/boards/synopsys/emsdp/emsdp_emsdp_em9d_defconfig new file mode 100644 index 00000000000000..e3abf3f96b6bc3 --- /dev/null +++ b/boards/synopsys/emsdp/emsdp_emsdp_em9d_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SPI=y diff --git a/boards/arc/emsdp/platform.c b/boards/synopsys/emsdp/platform.c similarity index 100% rename from boards/arc/emsdp/platform.c rename to boards/synopsys/emsdp/platform.c diff --git a/boards/arc/emsdp/support/openocd.cfg b/boards/synopsys/emsdp/support/openocd.cfg similarity index 100% rename from boards/arc/emsdp/support/openocd.cfg rename to boards/synopsys/emsdp/support/openocd.cfg diff --git a/boards/arc/hsdk/CMakeLists.txt b/boards/synopsys/hsdk/CMakeLists.txt similarity index 100% rename from boards/arc/hsdk/CMakeLists.txt rename to boards/synopsys/hsdk/CMakeLists.txt diff --git a/boards/synopsys/hsdk/Kconfig.defconfig b/boards/synopsys/hsdk/Kconfig.defconfig new file mode 100644 index 00000000000000..65a4731bf53883 --- /dev/null +++ b/boards/synopsys/hsdk/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_HSDK + +if SPI_DW + +config SPI_DW_ACCESS_WORD_ONLY + default y + +endif # SPI_DW + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 200 + +endif # I2C_DW + +endif # BOARD_HSDK diff --git a/boards/synopsys/hsdk/Kconfig.hsdk b/boards/synopsys/hsdk/Kconfig.hsdk new file mode 100644 index 00000000000000..17631e1defbd49 --- /dev/null +++ b/boards/synopsys/hsdk/Kconfig.hsdk @@ -0,0 +1,12 @@ +# DesignWare ARC HS Development Kit board configuration + +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HSDK + select SOC_ARC_HSDK + help + The DesignWare ARC HS Development Kit is a ready-to-use platform for + rapid software development on the ARC HS3x family of processors. It + supports single- and multi-core ARC HS34, HS36 and HS38 processors + and offers a wide range of interfaces diff --git a/boards/synopsys/hsdk/board.cmake b/boards/synopsys/hsdk/board.cmake new file mode 100644 index 00000000000000..be0105913d44ed --- /dev/null +++ b/boards/synopsys/hsdk/board.cmake @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +board_runner_args(openocd "--use-elf") + +if(${CONFIG_MP_MAX_NUM_CPUS} EQUAL 2) + board_runner_args(openocd "--config=${CMAKE_CURRENT_LIST_DIR}/support/openocd-2-cores.cfg") +endif() + +board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/synopsys/hsdk/board.yml b/boards/synopsys/hsdk/board.yml new file mode 100644 index 00000000000000..44363f8a9b8a08 --- /dev/null +++ b/boards/synopsys/hsdk/board.yml @@ -0,0 +1,7 @@ +board: + name: hsdk + vendor: snps + socs: + - name: arc_hsdk + variants: + - name: 2cores diff --git a/boards/arc/hsdk/doc/arduino_shield_interface.jpg b/boards/synopsys/hsdk/doc/arduino_shield_interface.jpg similarity index 100% rename from boards/arc/hsdk/doc/arduino_shield_interface.jpg rename to boards/synopsys/hsdk/doc/arduino_shield_interface.jpg diff --git a/boards/arc/hsdk/doc/hsdk.jpg b/boards/synopsys/hsdk/doc/hsdk.jpg similarity index 100% rename from boards/arc/hsdk/doc/hsdk.jpg rename to boards/synopsys/hsdk/doc/hsdk.jpg diff --git a/boards/arc/hsdk/doc/index.rst b/boards/synopsys/hsdk/doc/index.rst similarity index 100% rename from boards/arc/hsdk/doc/index.rst rename to boards/synopsys/hsdk/doc/index.rst diff --git a/boards/arc/hsdk/doc/mikrobus_header.jpg b/boards/synopsys/hsdk/doc/mikrobus_header.jpg similarity index 100% rename from boards/arc/hsdk/doc/mikrobus_header.jpg rename to boards/synopsys/hsdk/doc/mikrobus_header.jpg diff --git a/boards/arc/hsdk/doc/pinout_diagram_of_the_pmod.jpg b/boards/synopsys/hsdk/doc/pinout_diagram_of_the_pmod.jpg similarity index 100% rename from boards/arc/hsdk/doc/pinout_diagram_of_the_pmod.jpg rename to boards/synopsys/hsdk/doc/pinout_diagram_of_the_pmod.jpg diff --git a/boards/arc/hsdk/hsdk.dts b/boards/synopsys/hsdk/hsdk.dts similarity index 100% rename from boards/arc/hsdk/hsdk.dts rename to boards/synopsys/hsdk/hsdk.dts diff --git a/boards/arc/hsdk/hsdk.dtsi b/boards/synopsys/hsdk/hsdk.dtsi similarity index 100% rename from boards/arc/hsdk/hsdk.dtsi rename to boards/synopsys/hsdk/hsdk.dtsi diff --git a/boards/arc/hsdk/hsdk.yaml b/boards/synopsys/hsdk/hsdk.yaml similarity index 100% rename from boards/arc/hsdk/hsdk.yaml rename to boards/synopsys/hsdk/hsdk.yaml diff --git a/boards/arc/hsdk/hsdk_2cores.dts b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.dts similarity index 100% rename from boards/arc/hsdk/hsdk_2cores.dts rename to boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.dts diff --git a/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.yaml b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.yaml new file mode 100644 index 00000000000000..24c50b0b918289 --- /dev/null +++ b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores.yaml @@ -0,0 +1,16 @@ +identifier: hsdk/arc_hsdk/2cores +name: HS Development Kit(2 cores) +type: mcu +arch: arc +toolchain: + - zephyr + - cross-compile + - xtools + - arcmwdt +supported: + - smp +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores_defconfig b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores_defconfig new file mode 100644 index 00000000000000..af283689b38996 --- /dev/null +++ b/boards/synopsys/hsdk/hsdk_arc_hsdk_2cores_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MP_MAX_NUM_CPUS=2 diff --git a/boards/arc/hsdk/hsdk_defconfig b/boards/synopsys/hsdk/hsdk_defconfig similarity index 87% rename from boards/arc/hsdk/hsdk_defconfig rename to boards/synopsys/hsdk/hsdk_defconfig index 1e6b459fc37b49..0d17f50041bc10 100644 --- a/boards/arc/hsdk/hsdk_defconfig +++ b/boards/synopsys/hsdk/hsdk_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_HSDK=y -CONFIG_BOARD_HSDK=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y diff --git a/boards/arc/hsdk/platform.c b/boards/synopsys/hsdk/platform.c similarity index 100% rename from boards/arc/hsdk/platform.c rename to boards/synopsys/hsdk/platform.c diff --git a/boards/arc/hsdk/support/openocd-2-cores.cfg b/boards/synopsys/hsdk/support/openocd-2-cores.cfg similarity index 100% rename from boards/arc/hsdk/support/openocd-2-cores.cfg rename to boards/synopsys/hsdk/support/openocd-2-cores.cfg diff --git a/boards/arc/hsdk/support/openocd.cfg b/boards/synopsys/hsdk/support/openocd.cfg similarity index 100% rename from boards/arc/hsdk/support/openocd.cfg rename to boards/synopsys/hsdk/support/openocd.cfg diff --git a/boards/arc/hsdk4xd/CMakeLists.txt b/boards/synopsys/hsdk4xd/CMakeLists.txt similarity index 100% rename from boards/arc/hsdk4xd/CMakeLists.txt rename to boards/synopsys/hsdk4xd/CMakeLists.txt diff --git a/boards/synopsys/hsdk4xd/Kconfig.hsdk4xd b/boards/synopsys/hsdk4xd/Kconfig.hsdk4xd new file mode 100644 index 00000000000000..23c57baf0e9c27 --- /dev/null +++ b/boards/synopsys/hsdk4xd/Kconfig.hsdk4xd @@ -0,0 +1,12 @@ +# DesignWare ARC HSDK4XD Development Kit board configuration + +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_HSDK4XD + select SOC_ARC_HSDK4XD + help + The ARC HS4x/4xD Development Kit is a ready-to-use software development + platform for the ARC HS4x/4xD family of processor IP. It includes + a multicore ARC HS4x/HS4xD-based chip and integrates a wide range + of interfaces. diff --git a/boards/synopsys/hsdk4xd/board.cmake b/boards/synopsys/hsdk4xd/board.cmake new file mode 100644 index 00000000000000..dd49a483a39048 --- /dev/null +++ b/boards/synopsys/hsdk4xd/board.cmake @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(openocd "--use-elf") +board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake) diff --git a/boards/synopsys/hsdk4xd/board.yml b/boards/synopsys/hsdk4xd/board.yml new file mode 100644 index 00000000000000..70e04fa7e80eca --- /dev/null +++ b/boards/synopsys/hsdk4xd/board.yml @@ -0,0 +1,5 @@ +board: + name: hsdk4xd + vendor: snps + socs: + - name: arc_hsdk4xd diff --git a/boards/arc/hsdk4xd/doc/arduino_shield_interface.jpg b/boards/synopsys/hsdk4xd/doc/arduino_shield_interface.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/arduino_shield_interface.jpg rename to boards/synopsys/hsdk4xd/doc/arduino_shield_interface.jpg diff --git a/boards/arc/hsdk4xd/doc/hsdk4xd.jpg b/boards/synopsys/hsdk4xd/doc/hsdk4xd.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/hsdk4xd.jpg rename to boards/synopsys/hsdk4xd/doc/hsdk4xd.jpg diff --git a/boards/synopsys/hsdk4xd/doc/index.rst b/boards/synopsys/hsdk4xd/doc/index.rst new file mode 100644 index 00000000000000..b373f22cee319e --- /dev/null +++ b/boards/synopsys/hsdk4xd/doc/index.rst @@ -0,0 +1,557 @@ +.. _hsdk4xd: + +DesignWare(R) ARC(R) HS4x/HS4xD Development Kit +############################################### + +Overview +******** + +The ARC HS4x/HS4xD Development Kit is the next revision of :ref:`Synopsys HSDK board `. +It includes a multicore ARC HS4xD-based chip that integrates a wide range of interfaces +including Ethernet, HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and GPIO, +as well as a Think Silicon GPU. + +.. image:: hsdk4xd.jpg + :align: center + :alt: DesignWare(R) ARC(R) HS4x/HS4xD Development Kit (synopsys.com) + +For details about the board, see: `ARC HS4x/HS4xD Development Kit +(HSDK4xD) `__ + +Hardware +******** + +The ARC HSDK4xD has 24 general GPIOs, which divided into 8 groups named from ``GPIO_SEL_0`` to ``GPIO_SEL_7``. +Each sel can configured for different functions, such as: GPIO, UART, SPI, I2C and PWM. We can program +``CREG_GPIO_MUX`` register to do configuration for each sel. Tables below show the bit definition for +``CREG_GPIO_MUX`` register and the details configuration for each pin. + ++--------+-------------+---------+--------------+---------------------------------+ +| Bit | Name | Access | Reset value | Description | ++--------+-------------+---------+--------------+---------------------------------+ +| 2:0 | GPIO_SEL_0 | RW | 0x0 | GPIO mux select for gpio[3:0] | ++--------+-------------+---------+--------------+---------------------------------+ +| 5:3 | GPIO_SEL_1 | RW | 0x0 | GPIO mux select for gpio[7:4] | ++--------+-------------+---------+--------------+---------------------------------+ +| 8:6 | GPIO_SEL_2 | RW | 0x0 | GPIO mux select for gpio[11:8] | ++--------+-------------+---------+--------------+---------------------------------+ +| 11:9 | GPIO_SEL_3 | RW | 0x0 | GPIO mux select for gpio[15:12] | ++--------+-------------+---------+--------------+---------------------------------+ +| 14:12 | GPIO_SEL_4 | RW | 0x0 | GPIO mux select for gpio[17:16] | ++--------+-------------+---------+--------------+---------------------------------+ +| 17:15 | GPIO_SEL_5 | RW | 0x0 | GPIO mux select for gpio[19:18] | ++--------+-------------+---------+--------------+---------------------------------+ +| 20:18 | GPIO_SEL_6 | RW | 0x0 | GPIO mux select for gpio[21:20] | ++--------+-------------+---------+--------------+---------------------------------+ +| 23:21 | GPIO_SEL_7 | RW | 0x0 | GPIO mux select for gpio[23:22] | ++--------+-------------+---------+--------------+---------------------------------+ + ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SELS | GPIO PINS | FUN0 | FUN1 | FUN2 | FUN3 | FUN4 | FUN5 | FUN6 | FUN7 | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL0 | 0 | gpio[0] | uart0_cts | spi1_cs[0] | gpio[0] | gpio[0] | pwm_ch[6] | pwm_ch[6] | pwm_ch[1] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 1 | gpio[1] | uart0_txd | spi1_mosi | gpio[1] | pwm_ch[0] | gpio[1] | pwm_ch[0] | pwm_ch[0] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 2 | gpio[2] | uart0_rxd | spi1 _miso | i2c1_scl | gpio[2] | gpio[2] | gpio[2] | gpio[2] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 3 | gpio[3] | uart0_rts | spi1_clk | i2c1_sda | gpio[3] | gpio[3] | gpio[3] | gpio[3] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL1 | 4 | gpio[4] | uart1_cts | spi2_cs[0] | gpio[4] | gpio[4] | pwm_ch[4] | pwm_ch[4] | pwm_ch[3] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 5 | gpio[5] | uart1_txd | spi2_mosi | gpio[5] | pwm_ch[2] | gpio[5] | pwm_ch[2] | pwm_ch[2] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 6 | gpio[6] | uart1_rxd | spi2_miso | i2c2_scl | gpio[6] | gpio[6] | gpio[6] | gpio[6] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 7 | gpio[7] | uart1_rts | spi2_clk | i2c2_sda | gpio[7] | gpio[7] | gpio[7] | gpio[7] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL2 | 8 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | pwm_ch[2] | pwm_ch[5] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 9 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | pwm_ch[4] | pwm_ch[4] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 10 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | gpio[10] | gpio[10] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 11 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | gpio[11] | gpio[11] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL3 | 12 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | pwm_ch[0] | pwm_ch[7] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 13 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | pwm_ch[6] | pwm_ch[6] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 14 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | gpio[14] | gpio[14] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 15 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | gpio[15] | gpio[15] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL4 | 16 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | pwm_fault_0 | gpio[16] | pwm_fault_0 | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 17 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | pwm_ch[0] | pwm_ch[5] | pwm_ch[5] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL5 | 18 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | gpio[18] | gpio[18] | gpio[18] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 19 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | gpio[19] | gpio[19] | gpio[19] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL6 | 20 | gpio[20] | uart0_txd | spi2_cs[2] | i2c1_scl | gpio[20] | pwm_fault_1 | gpio[20] | pwm_fault_1 | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 21 | gpio[21] | uart0_rxd | spi2_mosi | i2c1_sda | pwm_ch[6] | pwm_ch[6] | pwm_ch[3] | pwm_ch[3] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| SEL7 | 22 | gpio[22] | uart2_txd | spi2_miso | i2c2_scl | gpio[22] | gpio[22] | gpio[22] | gpio[22] | +| +-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ +| | 23 | gpio[23] | uart2_rxd | spi2_clk | i2c2_sda | gpio[23] | gpio[23] | gpio[23] | gpio[23] | ++------+-----------+----------+-----------+------------+----------+-----------+-------------+-----------+-------------+ + +Digilent Pmod +============= + +The ARC HSDK4xD features two 12-pin Pmod connectors ``Pmod_A`` and ``Pmod_B`` and one 6-pin Pmod connector ``Pmod_C``. +The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI, I2C and PWM. +The location of the pins on the Pmod connectors is shown in Figure below. Detailed pin descriptions +depending on the pin multiplexer settings are provided in the subsequent sections. + +.. image:: pinout_diagram_of_the_pmod.jpg + :align: center + :alt: Pinout Diagram of the Pmod + +Pmod_A Connector +---------------- + +Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_A`` +connector. The GPIO column is the default assignment after Reset. + ++------+-----------+------------+-------------+-----------+------------+-----------+ +| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A1 | gpio[8] | uart2_cts | spi1_cs[1] | gpio[8] | gpio[8] | pwm_ch[2] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A2 | gpio[9] | uart2_txd | spi1_mosi | gpio[9] | pwm_ch[4] | gpio[9] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A3 | gpio[10] | uart2_rxd | spi1_miso | i2c1_scl | gpio[10] | gpio[10] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A4 | gpio[11] | uart2_rts | spi1_clk | i2c1_sda | gpio[11] | gpio[11] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A5 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A7 | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | gpio[20] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A8 | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | gpio[21] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A11 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| A12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ + +Pmod_B Connector +---------------- + +Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_B`` +connector. The GPIO column is the default assignment after Reset. + ++------+-----------+------------+-------------+-----------+------------+-----------+ +| Pin | GPIO | UART | SPI | I2C | PWM_1 | PWM_2 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B1 | gpio[12] | uart0_cts | spi2_cs[1] | gpio[12] | gpio[12] | pwm_ch[0] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B2 | gpio[13] | uart0_txd | spi2_mosi | gpio[13] | pwm_ch[6] | gpio[13] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B3 | gpio[14] | uart0_rxd | spi2_miso | i2c2_scl | gpio[14] | gpio[14] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B4 | gpio[15] | uart0_rts | spi2_clk | i2c2_sda | gpio[15] | gpio[15] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B5 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B7 | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | gpio[22] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B8 | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | gpio[23] | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B9 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B10 | n.c. | n.c. | n.c. | n.c. | n.c. | n.c. | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B11 | GND | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+------------+-----------+ +| B12 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+------------+-----------+ + +Pmod_C Connector +---------------- + +Table below lists the pin assignment of valid protocols that can be multiplexed on the ``Pmod_C`` +connector. The GPIO column is the default assignment after Reset. + ++------+-----------+------------+-------------+-----------+-----------+ +| Pin | GPIO | UART | SPI | I2C | PWM | ++------+-----------+------------+-------------+-----------+-----------+ +| C1 | gpio[16] | uart1_txd | spi1_cs[2] | i2c1_scl | gpio[16] | ++------+-----------+------------+-------------+-----------+-----------+ +| C2 | gpio[17] | uart1_rxd | spi1_mosi | i2c1_sda | pwm_ch[0] | ++------+-----------+------------+-------------+-----------+-----------+ +| C3 | gpio[18] | uart2_txd | spi1_miso | i2c2_scl | gpio[18] | ++------+-----------+------------+-------------+-----------+-----------+ +| C4 | gpio[19] | uart2_rxd | spi1_clk | i2c2_sda | gpio[19] | ++------+-----------+------------+-------------+-----------+-----------+ +| C5 | GND | GND | GND | GND | GND | ++------+-----------+------------+-------------+-----------+-----------+ +| C6 | 3V3 | 3V3 | 3V3 | 3V3 | 3V3 | ++------+-----------+------------+-------------+-----------+-----------+ + +Mikrobus +======== + +The ARC HSDK4xD features a set of MikroBUS headers. Figure below shows the relevant function assignments, +fully compatible with the MikroBUS standard. Table below shows the pin assignment on the I/O Multiplexer. + +.. image:: mikrobus_header.jpg + :align: center + :alt: mikrobus header + ++-------+-----------------+------+-----------+ +| Pin | I/O | Pin | I/O | ++-------+-----------------+------+-----------+ +| AN | ADC VIN6* | PWM | pwm_ch[0] | ++-------+-----------------+------+-----------+ +| RST | GPX_Port0_bit1 | INT | gpio[16] | ++-------+-----------------+------+-----------+ +| CS | spi2_cs[1] | RX | uart2_rxd | ++-------+-----------------+------+-----------+ +| SCK | spi2_clk | TX | uart2_txd | ++-------+-----------------+------+-----------+ +| MISO | spi2_miso | SCL | i2c2_scl | ++-------+-----------------+------+-----------+ +| MOSI | spi2_mosi | SDA | i2c2_sda | ++-------+-----------------+------+-----------+ + +.. note:: + ADC VIN6 is available through the on-board ADC and is + read though SPI0 using SPI chip select 1. + +Arduino +======= + +The ARC HSDK4xD provides an Arduino shield interface. Figure below shows the relevant +function assignments. The Arduino shield interface is compatible with the Arduino UNO +R3 with the following exceptions: 5 Volt shields are not supported, the IOREF voltage on +the ARC HSDK4xD board is fixed to 3V3. Note that the ICSP header is also not available. Most +shields do not require this ICSP header as the SPI master interface on this ICSP header +is also available on the ``IO10`` to ``IO13`` pins. + +.. image:: arduino_shield_interface.jpg + :align: center + :alt: arduino shield interface + +Table below shows the pin assignment on the I/O Multiplexer. Multiplexing is controlled by software +using the ``CREG_GPIO_MUX`` register (see Pinmux ). After a reset, all ports are configured as GPIO inputs. + ++-------+------------+-----------------+------------+ +| Pin | I/O-1 | I/O-2 | I/O-3 | ++-------+------------+-----------------+------------+ +| AD0 | ADC VIN0* | GPX_port0_bit2 | - | ++-------+------------+-----------------+------------+ +| AD1 | ADC VIN1* | GPX_port0_bit3 | - | ++-------+------------+-----------------+------------+ +| AD2 | ADC VIN2* | GPX_port0_bit4 | - | ++-------+------------+-----------------+------------+ +| AD3 | ADC VIN3* | GPX_port0_bit5 | - | ++-------+------------+-----------------+------------+ +| AD4 | ADC VIN4* | gpio[18] | i2c2_sda | ++-------+------------+-----------------+------------+ +| AD5 | ADC VIN5* | gpio[19] | i2c2_scl | ++-------+------------+-----------------+------------+ +| IO0 | gpio[23] | uart2_rxd | - | ++-------+------------+-----------------+------------+ +| IO1 | gpio[22] | uart2_txd | - | ++-------+------------+-----------------+------------+ +| IO2 | gpio[16] | - | - | ++-------+------------+-----------------+------------+ +| IO3 | gpio[17] | pwm_ch[5] | - | ++-------+------------+-----------------+------------+ +| IO4 | gpio[11] | - | | ++-------+------------+-----------------+------------+ +| IO5 | gpio[9] | pwm_ch[4] | - | ++-------+------------+-----------------+------------+ +| IO6 | gpio[21] | pwm_ch[3] | - | ++-------+------------+-----------------+------------+ +| IO7 | gpio[20] | - | - | ++-------+------------+-----------------+------------+ +| IO8 | gpio[10] | - | - | ++-------+------------+-----------------+------------+ +| IO9 | gpio[8] | pwm_ch[2] | - | ++-------+------------+-----------------+------------+ +| IO10 | gpio[12] | pwm_ch[0] | spi2_cs[1] | ++-------+------------+-----------------+------------+ +| IO11 | gpio[13] | pwm_ch[6] | spi2_mosi | ++-------+------------+-----------------+------------+ +| IO12 | gpio[14] | - | spi2_miso | ++-------+------------+-----------------+------------+ +| IO13 | gpio[15] | - | spi2_clk | ++-------+------------+-----------------+------------+ + +I/O expander +============ + +The ARC HSDK4xD board includes a CY8C9520A I/O expander from `Cypress CY8C9520A +`__. The I/O +expander offers additional GPIO signals and board control signals and can be accessed +through the on-board I2C bus, we have implemented a basic driver for it. +Tables below shows an overview of relevant I/O signals. + ++------------+---------------------------------------------+ +| Pins | Usage | ++------------+---------------------------------------------+ +| port0_bit0 | RS9113 Bluetooth I2S RX enable (active low) | ++------------+---------------------------------------------+ +| port0_bit1 | mikroBUS Reset (active low) | ++------------+---------------------------------------------+ +| port0_bit2 | GPIO for Arduino AD0 | ++------------+---------------------------------------------+ +| port0_bit3 | GPIO for Arduino AD1 | ++------------+---------------------------------------------+ +| port0_bit4 | GPIO for Arduino AD2 | ++------------+---------------------------------------------+ +| port0_bit5 | GPIO for Arduino AD3 | ++------------+---------------------------------------------+ +| port1_bit4 | On-board user LED0 | ++------------+---------------------------------------------+ +| port1_bit5 | On-board user LED1 | ++------------+---------------------------------------------+ +| port1_bit6 | On-board user LED2 | ++------------+---------------------------------------------+ +| port1_bit7 | On-board user LED3 | ++------------+---------------------------------------------+ + +On-board user LEDS +================== + +The ARC HSDK4xD includes 4 user LEDs(active high), which can be controlled through the I/O expander pins. + ++-------+-----------------+ +| LEDs | PINs | ++-------+-----------------+ +| LED0 | GPX_port1_bit4 | ++-------+-----------------+ +| LED1 | GPX_port1_bit5 | ++-------+-----------------+ +| LED2 | GPX_port1_bit6 | ++-------+-----------------+ +| LED3 | GPX_port1_bit7 | ++-------+-----------------+ + +For hardware feature details, refer to : `Designware HS4x/HS4xD Development Kit website +`__. + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To use Zephyr RTOS applications on the HS4x/HS4xD Development Kit board, a few +additional pieces of hardware are required. + +* A micro USB cable provides USB-JTAG debug and USB-UART communication + to the board + +* A universal switching power adaptor (110-240V + AC to 12V DC), provided in the package, provides power to the board. + +* :ref:`The Zephyr SDK ` + +* Terminal emulator software for use with the USB-UART. Suggestion: + `Putty Website`_. + +* (optional) A collection of Pmods, Arduino modules, or Mikro modules. + See `Digilent Pmod Modules`_ or develop your custom interfaces to attach + to the Pmod connector. + +Set up the ARC HS4x/HS4xD Development Kit +========================================= + +To run Zephyr application on ARC HS4x/HS4xD Development Kit, you need to +set up the board correctly. + +* Connect the digilent USB cable from your host to the board. + +* Connect the 12V DC power supply to your board + +Set up Zephyr Software +====================== + +Building Sample Applications +============================== + +You can try many of the :ref:`sample applications and demos +`. We'll use :ref:`hello_world`, found in +:zephyr_file:`samples/hello_world` as an example. + +Configuring +----------- + +You may need to write a ``prj.conf`` file if the sample doesn't have one. +Next, you can use the menuconfig rule to configure the target. By specifying +``hsdk4xd`` as the board configuration, you can select the ARC HS4x/HS4xD Development +Kit board support for Zephyr. + +.. zephyr-app-commands:: + :board: hsdk4xd + :zephyr-app: samples/hello_world + :goals: menuconfig + + +Building +-------- + +You can build an application in the usual way. Refer to +:ref:`build_an_application` for more details. Here is an example for +:ref:`hello_world`. + +.. zephyr-app-commands:: + :board: hsdk4xd + :zephyr-app: samples/hello_world + :maybe-skip-config: + :goals: build + + +Connecting Serial Output +========================= + +In the default configuration, Zephyr's HS4x/HS4xD Development Kit images support +serial output via the USB-UART on the board. To enable serial output: + +* Open a serial port emulator (i.e. on Linux minicom, putty, screen, etc) + +* Specify the tty driver name, for example, on Linux this may be + :file:`/dev/ttyUSB0` + +* Set the communication settings to: + + +========= ===== +Parameter Value +========= ===== +Baud: 115200 +Data: 8 bits +Parity: None +Stopbits: 1 +========= ===== + +Debugging +========== + +Using the latest version of Zephyr SDK(>=0.15.2), you can debug and +flash (run) HS4x/HS4xD Development Kit directly. + +One option is to build and debug the application using the usual +Zephyr build system commands. + +.. zephyr-app-commands:: + :board: hsdk4xd + :app: + :goals: debug + +At this point you can do your normal debug session. Set breakpoints and then +:kbd:`c` to continue into the program. + +The other option is to launch a debug server, as follows. + +.. zephyr-app-commands:: + :board: hsdk4xd + :app: + :goals: debugserver + +Then connect to the debug server at the HS4x/HS4xD Development Kit from a second +console, from the build directory containing the output :file:`zephyr.elf`. + +.. code-block:: console + + $ cd + $ $ZEPHYR_SDK_INSTALL_DIR/arc-zephyr-elf/arc-zephyr-elf-gdb zephyr.elf + (gdb) target remote localhost:3333 + (gdb) load + (gdb) b main + (gdb) c + +Flashing +======== + +If you just want to download the application to the HS4x/HS4xD Development Kit's DDR +and run, you can do so in the usual way. + +.. zephyr-app-commands:: + :board: hsdk4xd + :app: + :goals: flash + +This command still uses openocd and gdb to load the application elf file to +HS4x/HS4xD Development Kit, but it will load the application and immediately run. If +power is removed, the application will be lost since it wasn't written to flash. + +Most of the time you will not be flashing your program but will instead debug +it using openocd and gdb. The program can be download via the USB cable into +the code and data memories. + +The HS4x/HS4xD Development Kit also supports flashing the Zephyr application +with the U-Boot bootloader, a powerful and flexible tool for loading +an executable from different sources and running it on the target platform. + +The U-Boot implementation for the HS4x/HS4xD Development Kit was further extended with +additional functionality that allows users to better manage the broad +configurability of the HS4x/HS4xD Development Kit + +When you are ready to deploy the program so that it boots up automatically on +reset or power-up, you can follow the steps to place the program on SD card. + +For details, see: `Uboot-HS4x/HS4xD-Command-Reference +`__ + +Supported peripheral +==================== + +The following list indicates the state of HS4x/HS4xD Development Kit peripherals’ support + ++------------+---------+ +| Peripheral | Support | ++------------+---------+ +| ADC | No | ++------------+---------+ +| Bluetooth | No | ++------------+---------+ +| Ethernet | No | ++------------+---------+ +| GPIO | No | ++------------+---------+ +| GPU | No | ++------------+---------+ +| HDMI | No | ++------------+---------+ +| I2C | No | ++------------+---------+ +| I2S | No | ++------------+---------+ +| PWM | No | ++------------+---------+ +| SDIO | No | ++------------+---------+ +| SPI | No | ++------------+---------+ +| UART | Yes | ++------------+---------+ +| USB | No | ++------------+---------+ +| WiFi | No | ++------------+---------+ + +References +********** + +.. _embARC website: https://www.embarc.org + +.. _Designware HS Development Kit website: https://www.synopsys.com/dw/ipdir.php?ds=arc-hs-development-kit + +.. _Digilent Pmod Modules: http://store.digilentinc.com/pmod-modules + +.. _Putty website: http://www.putty.org diff --git a/boards/arc/hsdk4xd/doc/mikrobus_header.jpg b/boards/synopsys/hsdk4xd/doc/mikrobus_header.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/mikrobus_header.jpg rename to boards/synopsys/hsdk4xd/doc/mikrobus_header.jpg diff --git a/boards/arc/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg b/boards/synopsys/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg similarity index 100% rename from boards/arc/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg rename to boards/synopsys/hsdk4xd/doc/pinout_diagram_of_the_pmod.jpg diff --git a/boards/synopsys/hsdk4xd/hsdk4xd.dts b/boards/synopsys/hsdk4xd/hsdk4xd.dts new file mode 100644 index 00000000000000..59792f4d487f5c --- /dev/null +++ b/boards/synopsys/hsdk4xd/hsdk4xd.dts @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2023, Synopsys, Inc. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/ { + model = "hsdk4xd"; + compatible = "snps,hsdk4xd"; + + aliases { + uart-dbg = &uart_dbg; + }; + + chosen { + zephyr,sram = &ddr0; + zephyr,console = &uart_dbg; + zephyr,shell-uart = &uart_dbg; + }; + +}; + +arduino_spi: &spi2 {}; + +&uart_dbg { + status = "okay"; + current-speed = <115200>; +}; + +&creg_gpio { + status = "okay"; +}; diff --git a/boards/arc/hsdk4xd/hsdk4xd.yaml b/boards/synopsys/hsdk4xd/hsdk4xd.yaml similarity index 100% rename from boards/arc/hsdk4xd/hsdk4xd.yaml rename to boards/synopsys/hsdk4xd/hsdk4xd.yaml diff --git a/boards/arc/hsdk4xd/hsdk4xd_defconfig b/boards/synopsys/hsdk4xd/hsdk4xd_defconfig similarity index 86% rename from boards/arc/hsdk4xd/hsdk4xd_defconfig rename to boards/synopsys/hsdk4xd/hsdk4xd_defconfig index 24f79598815e45..00d8ba6ff0df75 100644 --- a/boards/arc/hsdk4xd/hsdk4xd_defconfig +++ b/boards/synopsys/hsdk4xd/hsdk4xd_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_HSDK4XD=y -CONFIG_BOARD_HSDK4XD=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/arc/hsdk4xd/support/openocd.cfg b/boards/synopsys/hsdk4xd/support/openocd.cfg similarity index 100% rename from boards/arc/hsdk4xd/support/openocd.cfg rename to boards/synopsys/hsdk4xd/support/openocd.cfg diff --git a/boards/synopsys/index.rst b/boards/synopsys/index.rst new file mode 100644 index 00000000000000..00ef0d70564a19 --- /dev/null +++ b/boards/synopsys/index.rst @@ -0,0 +1,10 @@ +.. _boards-synopsys: + +Synopsys +######## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/arc/qemu_arc/CMakeLists.txt b/boards/synopsys/iotdk/CMakeLists.txt similarity index 100% rename from boards/arc/qemu_arc/CMakeLists.txt rename to boards/synopsys/iotdk/CMakeLists.txt diff --git a/boards/synopsys/iotdk/Kconfig.iotdk b/boards/synopsys/iotdk/Kconfig.iotdk new file mode 100644 index 00000000000000..192759678b7b00 --- /dev/null +++ b/boards/synopsys/iotdk/Kconfig.iotdk @@ -0,0 +1,14 @@ +# DesignWare ARC IoT Development Kit board configuration + +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_IOTDK + select SOC_ARC_IOT + help + The DesignWare ARC IoT Development Kit board is a versatile platform that includes the + necessary hardware and software to accelerate software development and debugging of + sensor fusion, voice recognition and face detection designs. It includes a silicon + implementation of the ARC Data Fusion IP Subsystem running at 144 MHz on SMIC's 55-nm + ultra-low power process, and a rich set of peripherals commonly used in IoT designs + such as USB, UART, SPI, I2C, PWM, SDIO and ADCs. diff --git a/boards/arc/iotdk/arc_mpu_regions.c b/boards/synopsys/iotdk/arc_mpu_regions.c similarity index 100% rename from boards/arc/iotdk/arc_mpu_regions.c rename to boards/synopsys/iotdk/arc_mpu_regions.c diff --git a/boards/arc/emsdp/board.cmake b/boards/synopsys/iotdk/board.cmake similarity index 100% rename from boards/arc/emsdp/board.cmake rename to boards/synopsys/iotdk/board.cmake diff --git a/boards/synopsys/iotdk/board.yml b/boards/synopsys/iotdk/board.yml new file mode 100644 index 00000000000000..5222ad815cf849 --- /dev/null +++ b/boards/synopsys/iotdk/board.yml @@ -0,0 +1,5 @@ +board: + name: iotdk + vendor: snps + socs: + - name: arc_iot diff --git a/boards/arc/iotdk/doc/index.rst b/boards/synopsys/iotdk/doc/index.rst similarity index 100% rename from boards/arc/iotdk/doc/index.rst rename to boards/synopsys/iotdk/doc/index.rst diff --git a/boards/arc/iotdk/doc/iotdk.jpg b/boards/synopsys/iotdk/doc/iotdk.jpg similarity index 100% rename from boards/arc/iotdk/doc/iotdk.jpg rename to boards/synopsys/iotdk/doc/iotdk.jpg diff --git a/boards/arc/iotdk/iotdk.dts b/boards/synopsys/iotdk/iotdk.dts similarity index 96% rename from boards/arc/iotdk/iotdk.dts rename to boards/synopsys/iotdk/iotdk.dts index e1bd41db5b63be..8a9837d1b2a416 100644 --- a/boards/arc/iotdk/iotdk.dts +++ b/boards/synopsys/iotdk/iotdk.dts @@ -8,7 +8,6 @@ #include #include -#include "board.dtsi" / { model = "iotdk"; diff --git a/boards/arc/iotdk/iotdk.yaml b/boards/synopsys/iotdk/iotdk.yaml similarity index 100% rename from boards/arc/iotdk/iotdk.yaml rename to boards/synopsys/iotdk/iotdk.yaml diff --git a/boards/arc/iotdk/iotdk_defconfig b/boards/synopsys/iotdk/iotdk_defconfig similarity index 86% rename from boards/arc/iotdk/iotdk_defconfig rename to boards/synopsys/iotdk/iotdk_defconfig index afb2569dadd648..d95ae777729835 100644 --- a/boards/arc/iotdk/iotdk_defconfig +++ b/boards/synopsys/iotdk/iotdk_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ARC_IOT=y -CONFIG_BOARD_IOTDK=y CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y CONFIG_BUILD_OUTPUT_BIN=n diff --git a/boards/arc/iotdk/support/openocd.cfg b/boards/synopsys/iotdk/support/openocd.cfg similarity index 100% rename from boards/arc/iotdk/support/openocd.cfg rename to boards/synopsys/iotdk/support/openocd.cfg diff --git a/boards/arc/nsim/CMakeLists.txt b/boards/synopsys/nsim/CMakeLists.txt similarity index 100% rename from boards/arc/nsim/CMakeLists.txt rename to boards/synopsys/nsim/CMakeLists.txt diff --git a/boards/synopsys/nsim/Kconfig b/boards/synopsys/nsim/Kconfig new file mode 100644 index 00000000000000..5fefd2b3877a7f --- /dev/null +++ b/boards/synopsys/nsim/Kconfig @@ -0,0 +1,7 @@ +# DesignWare ARC nSIM simulated platform configuration + +# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NSIM + select HAS_COVERAGE_SUPPORT diff --git a/boards/synopsys/nsim/Kconfig.nsim b/boards/synopsys/nsim/Kconfig.nsim new file mode 100644 index 00000000000000..88601b8e48a918 --- /dev/null +++ b/boards/synopsys/nsim/Kconfig.nsim @@ -0,0 +1,28 @@ +# DesignWare ARC nSIM simulated platform configuration + +# Copyright (c) 2016, 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NSIM + select SOC_NSIM_EM if BOARD_NSIM_NSIM_EM + select SOC_NSIM_EM7D_V22 if BOARD_NSIM_NSIM_EM7D_V22 + select SOC_NSIM_EM11D if BOARD_NSIM_NSIM_EM11D + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_SRAM + select SOC_NSIM_HS_SMP if BOARD_NSIM_NSIM_HS_SMP + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_FLASH_XIP + select SOC_NSIM_HS_MPUV6 if BOARD_NSIM_NSIM_HS_MPUV6 + select SOC_NSIM_HS if BOARD_NSIM_NSIM_HS_HOSTLINK + select SOC_NSIM_HS5X if BOARD_NSIM_NSIM_HS5X + select SOC_NSIM_HS5X_SMP if BOARD_NSIM_NSIM_HS5X_SMP + select SOC_NSIM_HS5X_SMP if BOARD_NSIM_NSIM_HS5X_SMP_12CORES + select SOC_NSIM_HS6X if BOARD_NSIM_NSIM_HS6X + select SOC_NSIM_HS6X_SMP if BOARD_NSIM_NSIM_HS6X_SMP + select SOC_NSIM_HS6X_SMP if BOARD_NSIM_NSIM_HS6X_SMP_12CORES + select SOC_NSIM_SEM if BOARD_NSIM_NSIM_SEM + select SOC_NSIM_SEM if BOARD_NSIM_NSIM_SEM_MPU_STACK_GUARD + select SOC_NSIM_VPX5 if BOARD_NSIM_NSIM_VPX5 + help + The DesignWare ARC nSIM board is a virtual board based on + the ARC nSIM simulator. It demonstrates the ARC core features + and a console based on the ns16550 UART model. diff --git a/boards/arc/nsim/arc_mpu_regions.c b/boards/synopsys/nsim/arc_mpu_regions.c similarity index 100% rename from boards/arc/nsim/arc_mpu_regions.c rename to boards/synopsys/nsim/arc_mpu_regions.c diff --git a/boards/arc/nsim/board.cmake b/boards/synopsys/nsim/board.cmake similarity index 100% rename from boards/arc/nsim/board.cmake rename to boards/synopsys/nsim/board.cmake diff --git a/boards/synopsys/nsim/board.yml b/boards/synopsys/nsim/board.yml new file mode 100644 index 00000000000000..a5089774c473e2 --- /dev/null +++ b/boards/synopsys/nsim/board.yml @@ -0,0 +1,28 @@ +board: + name: nsim + vendor: snps + socs: + - name: nsim_em + - name: nsim_em7d_v22 + - name: nsim_em11d + - name: nsim_hs + variants: + - name: sram + - name: smp + - name: flash_xip + - name: mpuv6 + - name: hostlink + - name: nsim_hs5x + variants: + - name: smp + variants: + - name: 12cores + - name: nsim_hs6x + variants: + - name: smp + variants: + - name: 12cores + - name: nsim_sem + variants: + - name: mpu_stack_guard + - name: nsim_vpx5 diff --git a/boards/synopsys/nsim/doc/index.rst b/boards/synopsys/nsim/doc/index.rst new file mode 100644 index 00000000000000..3f4a250993a3ac --- /dev/null +++ b/boards/synopsys/nsim/doc/index.rst @@ -0,0 +1,339 @@ +.. _nsim: + +DesignWare ARC nSIM and HAPS FPGA boards +######################################## + +Overview +******** + +This platform can be used to run Zephyr RTOS on the widest possible range of ARC processors in +simulation with `Designware ARC nSIM`_ or run same images on FPGA prototyping platform `HAPS`_. The +platform includes the following features: + +* ARC processor core, which implements ARCv2 or ARCv3 ISA, please refer to + :ref:`here ` for a complete list of ARC processor families which + currently supported +* Virtual serial console (a standard ``ns16550`` UART model) + +ARC processors are known for being highly customizable and some but not all of the configurations +are currently supported in the Zephyr RTOS for ARC, again please refer to +:ref:`here ` for a complete list of supported features. + +There are multiple supported sub-configurations for that platform. Some but not all of currently +available configurations are listed below: + +* ``nsim/nsim_em`` - ARC EM core v4.0 with two register banks, FastIRQ's, MPUv2, DSP options and + XY-memory +* ``nsim/nsim_em7d_v22`` - ARC EM core v3.0 with one register bank and FastIRQ's +* ``nsim/nsim_em11d`` - ARC EM core v4.0 with one register bank, no FastIRQ's, MPUv2, DSP options and + XY-memory +* ``nsim/nsim_sem`` - ARC EM core v4.0 with secure features (thus "SEM", i.e. Secure EM) and MPUv4 +* ``nsim/nsim_hs`` - ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 +* ``nsim/nsim_hs/smp`` - Dual-core ARCv2 HS core v2.1 with two register banks, FastIRQ's and MPUv3 +* ``nsim/nsim_vpx5`` - ARCv2 VPX5 core, close to vpx5_integer_full template +* ``nsim/nsim_hs5x`` - 32-bit ARCv3 HS core with rich set of options +* ``nsim/nsim_hs6x`` - 64-bit ARCv3 HS core with rich set of options +* ``nsim/nsim_hs5x/smp/12cores`` - SMP 12 cores 32-bit ARCv3 HS platform +* ``nsim/nsim_hs6x/smp/12cores`` - SMP 12 cores 64-bit ARCv3 HS platform + +.. _board_arc_nsim_prop_args_files: + +It is recommended to look at precise description of a particular sub-configuration in either +``.props`` or ``.args`` files in :zephyr_file:`boards/synopsys/nsim/support/` directory to understand +which options are configured and so will be used on invocation of the simulator. + +In case of single-core configurations it would be ``.props`` file which contains configuration +for nSIM simulator and ``.args`` file which contains configuration for MetaWare debugger (MDB). +Note that these files contain identical HW configuration and meant to be used with the corresponding +tool: ``.props`` file for nSIM simulator and ``.args`` file for MDB (which internally uses nSIM for +simulation anyway). + +.. hint:: + If different behavior is observed during execution or debugging of a particular application + (especially after creation of a new board or modification of the existing one) make sure features + defined in ``.props`` and ``.args`` are semantically identical (unfortunately options of + nSIM & MDB don't exactly match, so care should be taken). + +I.e. for the single-core ``nsim/nsim_hs5x`` platform there are +:zephyr_file:`boards/synopsys/nsim/support/nsim_hs5x.props` and +:zephyr_file:`boards/synopsys/nsim/support/mdb_hs5x.args`. + +For the multi-core configurations there is only ``.args`` file as the multi-core configuration +can only be instantiated with help of MDB. + +I.e. for the multi-core ``nsim/nsim_hs5x/smp`` platform there is only +:zephyr_file:`boards/synopsys/nsim/support/mdb_hs5x_smp.args`. + +.. warning:: + All nSIM/MDB configurations are used for demo and testing purposes. They are not meant to + represent any real system and so might be renamed, removed or modified at any point. + +Programming and Debugging +************************* + +Required Hardware and Software +============================== + +To run single-core Zephyr RTOS applications in simulation on this board, +either `DesignWare ARC nSIM`_ or `DesignWare ARC Free nSIM`_ is required. + +To run multi-core Zephyr RTOS applications in simulation on this board, +`DesignWare ARC nSIM`_ and MetaWare Debugger from `ARC MWDT`_ are required. + +To run Zephyr RTOS applications on FPGA-based `HAPS`_ platform, +MetaWare Debugger from `ARC MWDT`_ is required as well as the HAPS platform itself. + +Building & Running Sample Applications +====================================== + +Most board sub-configurations support building with both GNU and ARC MWDT toolchains, however +there might be exceptions from that, especially for newly added targets. You can check supported +toolchains for the sub-configurations in the corresponding ``.yaml`` file. + +I.e. for the ``nsim/nsim_hs5x`` board we can check :zephyr_file:`boards/synopsys/nsim/nsim_nsim_hs5x.yaml` + +The supported toolchains are listed in ``toolchain:`` array in ``.yaml`` file, where we can find: + +* **zephyr** - implies ARC GNU toolchain from Zephyr SDK. You can find more information about + Zephyr SDK :ref:`here `. +* **cross-compile** - implies ARC GNU cross toolchain, which is not a part of Zephyr SDK. Note that + some (especially new) sub-configurations may declare ``cross-compile`` toolchain support without + ``zephyr`` toolchain support because corresponding target CPU support hasn't been added to Zephyr + SDK yet. You can find more information about its usage here: :ref:`here `. +* **arcmwdt** - implies proprietary ARC MWDT toolchain. You can find more information about its + usage here: :ref:`here `. + +.. note:: + Note that even if both GNU and MWDT toolchain support is declared for the target some tests or + samples can be only built with either GNU or MWDT toolchain due to some features limited to a + particular toolchain. + +Use this configuration to run basic Zephyr applications and kernel tests in +nSIM, for example, with the :zephyr:code-sample:`synchronization` sample: + +.. zephyr-app-commands:: + :zephyr-app: samples/synchronization + :host-os: unix + :board: nsim_em + :goals: flash + +This will build an image with the synchronization sample app, boot it using +nSIM, and display the following console output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.2.0-3948-gd351a024dc87 *** + thread_a: Hello World from cpu 0 on nsim! + thread_b: Hello World from cpu 0 on nsim! + thread_a: Hello World from cpu 0 on nsim! + thread_b: Hello World from cpu 0 on nsim! + thread_a: Hello World from cpu 0 on nsim! + + +.. note:: + To exit the simulator, use :kbd:`Ctrl+]`, then :kbd:`Ctrl+c` + +.. _board_arc_nsim_verbose_build: + +.. tip:: + You can get more details about the building process by running build in verbose mode. It can be + done by passing ``-v`` flag to the west: ``west -v build -b nsim_hs samples/synchronization`` + +You can run applications built for ``nsim`` board not only on nSIM simulation itself, but also on +FPGA based HW platform `HAPS`_. To run previously built application on HAPS do: + +.. code-block:: console + + west flash --runner mdb-hw + +.. note:: + To run on HAPS, in addition to proper build and flash Zephyr image, you need setup HAPS itself + as well as flash proper built FPGA image (aka .bit-file). This instruction doesn't cover those + steps, so you need to follow HAPS manual. + +Debugging +========= + +.. _board_arc_nsim_debugging_mwdt: + +Debugging with MDB +------------------ + +.. note:: + We strongly recommend to debug with MetaWare debugger (MDB) because it: + + * Supports wider range of ARC hardware features + * Allows to debug both single-core and multi-core ``nsim`` targets. + * Allows to debug on `HAPS`_ platform. + +You can use the following command to start GUI debugging when running application on nSIM simulator +(regardless if single- or multi-core configuration is used): + +.. code-block:: console + + west debug --runner mdb-nsim + +You can use the following command to start GUI debugging when running application on `HAPS`_ +platform: + +.. code-block:: console + + west debug --runner mdb-hw + +.. tip:: + The ``west debug`` (as well as ``west flash``) is just a wrapper script and so it's possible to + extract the exact commands which are called in it by running it in verbose mode. For that you + need to pass ``-v`` flag to the wrapper. For example, if you run the following command: + + .. code-block:: console + + west -v debug --runner mdb-nsim + + it will produce the following output (the ``nsim/nsim_hs5x/smp`` configuration was used for that + example): + + .. code-block:: console + + < *snip* > + -- west debug: using runner mdb-nsim + runners.mdb-nsim: mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + runners.mdb-nsim: mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + runners.mdb-nsim: mdb -multifiles=core1,core0 -OKN + + From that output it's possible to extract MDB commands used for setting-up the GUI debugging + session: + + .. code-block:: console + + mdb -pset=1 -psetname=core0 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + mdb -pset=2 -psetname=core1 -prop=download=2 -nooptions -nogoifmain -toggle=include_local_symbols=1 -nsim @/path/zephyr/boards/synopsys/nsim/support/mdb_hs5x_smp.args /path/zephyr/build/zephyr/zephyr.elf + mdb -multifiles=core1,core0 -OKN + + Then it's possible to use them directly or in some machinery if required. + + .. warning:: + It is strongly recommended to not rely on the mdb command line options listed above but + extract it yourself for your configuration. + + .. note:: + In case of execution or debugging with MDB on multi-core configuration on nSIM + simulator without ``west flash`` and ``west debug`` wrappers it's necessary to + set :envvar:`NSIM_MULTICORE` environment variable to ``1``. If you are using ``west flash`` or + ``west debug`` it's done automatically by wrappers. + + Without :envvar:`NSIM_MULTICORE` environment variable set to 1, MDB will simulate 2 separate + ARC cores which don't share any memory regions with each other and so SMP-enabled code won't + work as expected. + +Debugging with GDB +------------------ + +.. note:: + Debugging on nSIM via GDB is only supported on single-core configurations (which use standalone + nSIM). However if it's possible to launch application on multi-core nsim target that means you + can simply :ref:`debug with MDB debugger `. + It's the nSIM with ARC GDB restriction, real HW multi-core ARC targets can be debugged with ARC + GDB. + +.. note:: + Currently debugging with GDB is not supported on `HAPS`_ platform. + +.. note:: + The normal ``west debug`` command won't work for debugging applications using nsim boards + because both the nSIM simulator and the debugger (either GDB or MDB) use the same console for + input / output. + In case of GDB debugger it's possible to use a separate terminal windows for GDB and nSIM to + avoid intermixing their output. For the MDB debugger simply use GUI mode. + +After building your application, open two terminal windows. In terminal one, use nSIM to start a GDB +server and wait for a remote connection with following command: + +.. code-block:: console + + west debugserver --runner arc-nsim + +In terminal two, connect to the GDB server using ARC GDB. You can find it in Zephyr SDK: + +* for the ARCv2 targets you should use :file:`arc-zephyr-elf-gdb` +* for the ARCv3 targets you should use :file:`arc64-zephyr-elf-gdb` + +This command loads the symbol table from the elf binary file, for example the +:file:`build/zephyr/zephyr.elf` file: + +.. code-block:: console + + arc-zephyr-elf-gdb -ex 'target remote localhost:3333' -ex load build/zephyr/zephyr.elf + +Now the debug environment has been set up, and it's possible to debug the application with gdb +commands. + +Modifying the configuration +*************************** + +If modification of existing nsim configuration is required or even there's a need in creation of a +new one it's required to maintain alignment between + +* Zephyr OS configuration +* nSIM & MDB configuration +* GNU & MWDT toolchain compiler options + +.. note:: + The ``.tcf`` configuration files are not supported by Zephyr directly. There are multiple + reasons for that. ``.tcf`` perfectly suits building of bare-metal single-thread application - + in that case all the compiler options from ``.tcf`` are passed to the compiler, so all the HW + features are used by the application and optimal code is being generated. + The situation is completely different when multi-thread feature-rich operation system is + considered. Of course it is still possible to build all the code with all the + options from ``.tcf`` - but that may be far from optimal solution. For example, such approach + require so save & restore full register context for all tasks (and sometimes even for + interrupts). And for DSP-enabled or for FPU-enabled systems that leads to dozens of extra + registers save and restore even if the most of the user and kernel tasks don't actually use + DSP or FPU. Instead we prefer to fine-tune the HW features usage which (with all its pros) + require us to maintain them separately from ``.tcf`` configuration. + + +Zephyr OS configuration +======================= + +Zephyr OS configuration is defined via Kconfig and Device tree. These are non ARC-specific +mechanisms which are described in :ref:`board porting guide `. + +It is advised to look for ``_defconfig``, ``.dts`` and +``.yaml`` as an entry point for board configuration. + +nSIM configuration +================== + +nSIM configuration is defined in :ref:`props and args files `. +Generally they are identical to the values from corresponding ``.tcf`` configuration with few +exceptions: + +* The UART model is added (to both ``.props`` and ``.args`` files). +* Options to fine-tuned MDB behavior are added (to ``.args`` files only) to disable MDB profiling + and fine-tune MDB behavior on multi-core systems. + +GNU & MWDT toolchain compiler options +===================================== + +The hardware-specific compiler options are set in corresponding SoC cmake file. For ``nsim`` board +it is :zephyr_file:`soc/synopsys/nsim/CMakeLists.txt`. + +For the GNU toolchain the basic configuration is set via ``-mcpu`` which is defined in generic code +and based on the selected CPU model via Kconfig. It still can be forcefully set to required value +on SoC level. + +For the MWDT toolchain all hardware-specific compiler options are set directly in SoC +``CMakeLists.txt``. + +.. note:: + The non hardware-specific compiler options like optimizations, library selections, C / C++ + language options are still set in Zephyr generic code. It could be observed by + :ref:`running build in verbose mode `. + +References +********** + +.. _Designware ARC nSIM: https://www.synopsys.com/dw/ipdir.php?ds=sim_nsim +.. _DesignWare ARC Free nSIM: https://www.synopsys.com/cgi-bin/dwarcnsim/req1.cgi +.. _HAPS: https://www.synopsys.com/verification/prototyping/haps.html +.. _ARC MWDT: https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware diff --git a/boards/arc/nsim/haps_arcv3_init.c b/boards/synopsys/nsim/haps_arcv3_init.c similarity index 100% rename from boards/arc/nsim/haps_arcv3_init.c rename to boards/synopsys/nsim/haps_arcv3_init.c diff --git a/boards/arc/nsim/nsim-ccm-mem.dtsi b/boards/synopsys/nsim/nsim-ccm-mem.dtsi similarity index 100% rename from boards/arc/nsim/nsim-ccm-mem.dtsi rename to boards/synopsys/nsim/nsim-ccm-mem.dtsi diff --git a/boards/arc/nsim/nsim-flash-sram-mem.dtsi b/boards/synopsys/nsim/nsim-flash-sram-mem.dtsi similarity index 100% rename from boards/arc/nsim/nsim-flash-sram-mem.dtsi rename to boards/synopsys/nsim/nsim-flash-sram-mem.dtsi diff --git a/boards/arc/nsim/nsim-flat-mem.dtsi b/boards/synopsys/nsim/nsim-flat-mem.dtsi similarity index 100% rename from boards/arc/nsim/nsim-flat-mem.dtsi rename to boards/synopsys/nsim/nsim-flat-mem.dtsi diff --git a/boards/arc/nsim/nsim-smp.dtsi b/boards/synopsys/nsim/nsim-smp.dtsi similarity index 100% rename from boards/arc/nsim/nsim-smp.dtsi rename to boards/synopsys/nsim/nsim-smp.dtsi diff --git a/boards/arc/nsim/nsim-uart-hostlink.dtsi b/boards/synopsys/nsim/nsim-uart-hostlink.dtsi similarity index 100% rename from boards/arc/nsim/nsim-uart-hostlink.dtsi rename to boards/synopsys/nsim/nsim-uart-hostlink.dtsi diff --git a/boards/arc/nsim/nsim-uart-ns16550.dtsi b/boards/synopsys/nsim/nsim-uart-ns16550.dtsi similarity index 100% rename from boards/arc/nsim/nsim-uart-ns16550.dtsi rename to boards/synopsys/nsim/nsim-uart-ns16550.dtsi diff --git a/boards/arc/nsim/nsim.dtsi b/boards/synopsys/nsim/nsim.dtsi similarity index 100% rename from boards/arc/nsim/nsim.dtsi rename to boards/synopsys/nsim/nsim.dtsi diff --git a/boards/arc/nsim/nsim_em-sec.dtsi b/boards/synopsys/nsim/nsim_em-sec.dtsi similarity index 100% rename from boards/arc/nsim/nsim_em-sec.dtsi rename to boards/synopsys/nsim/nsim_em-sec.dtsi diff --git a/boards/arc/nsim/nsim_em.dtsi b/boards/synopsys/nsim/nsim_em.dtsi similarity index 100% rename from boards/arc/nsim/nsim_em.dtsi rename to boards/synopsys/nsim/nsim_em.dtsi diff --git a/boards/arc/nsim/nsim_em.dts b/boards/synopsys/nsim/nsim_nsim_em.dts similarity index 100% rename from boards/arc/nsim/nsim_em.dts rename to boards/synopsys/nsim/nsim_nsim_em.dts diff --git a/boards/synopsys/nsim/nsim_nsim_em.yaml b/boards/synopsys/nsim/nsim_nsim_em.yaml new file mode 100644 index 00000000000000..7fd973932eb046 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_em +name: EM Nsim simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_em11d.dts b/boards/synopsys/nsim/nsim_nsim_em11d.dts similarity index 100% rename from boards/arc/nsim/nsim_em11d.dts rename to boards/synopsys/nsim/nsim_nsim_em11d.dts diff --git a/boards/synopsys/nsim/nsim_nsim_em11d.yaml b/boards/synopsys/nsim/nsim_nsim_em11d.yaml new file mode 100644 index 00000000000000..e37aeb2f442559 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em11d.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_em11d +name: EM11D Nsim simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_em11d_defconfig b/boards/synopsys/nsim/nsim_nsim_em11d_defconfig new file mode 100644 index 00000000000000..1cdf8a0b67ebd8 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em11d_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_em7d_v22.dts b/boards/synopsys/nsim/nsim_nsim_em7d_v22.dts similarity index 100% rename from boards/arc/nsim/nsim_em7d_v22.dts rename to boards/synopsys/nsim/nsim_nsim_em7d_v22.dts diff --git a/boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml b/boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml new file mode 100644 index 00000000000000..c77c883ccc8d1a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em7d_v22.yaml @@ -0,0 +1,14 @@ +identifier: nsim/nsim_em7d_v22 +name: EM nSIM simulator (EM7D_v22) +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig b/boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig new file mode 100644 index 00000000000000..1cdf8a0b67ebd8 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em7d_v22_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/synopsys/nsim/nsim_nsim_em_defconfig b/boards/synopsys/nsim/nsim_nsim_em_defconfig new file mode 100644 index 00000000000000..1cdf8a0b67ebd8 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_em_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y diff --git a/boards/arc/nsim/nsim_hs.dts b/boards/synopsys/nsim/nsim_nsim_hs.dts similarity index 100% rename from boards/arc/nsim/nsim_hs.dts rename to boards/synopsys/nsim/nsim_nsim_hs.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs.yaml b/boards/synopsys/nsim/nsim_nsim_hs.yaml new file mode 100644 index 00000000000000..2f02bf5c85a43f --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs +name: HS nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x.dts b/boards/synopsys/nsim/nsim_nsim_hs5x.dts similarity index 100% rename from boards/arc/nsim/nsim_hs5x.dts rename to boards/synopsys/nsim/nsim_nsim_hs5x.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x.yaml b/boards/synopsys/nsim/nsim_nsim_hs5x.yaml new file mode 100644 index 00000000000000..a20ad79a34a21e --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs5x +name: HS5x nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - arcmwdt + - cross-compile +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_defconfig b/boards/synopsys/nsim/nsim_nsim_hs5x_defconfig new file mode 100644 index 00000000000000..5a48971e06d4fa --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs5x_smp.dts b/boards/synopsys/nsim/nsim_nsim_hs5x_smp.dts similarity index 100% rename from boards/arc/nsim/nsim_hs5x_smp.dts rename to boards/synopsys/nsim/nsim_nsim_hs5x_smp.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml b/boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml new file mode 100644 index 00000000000000..09dcfd014efa25 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp.yaml @@ -0,0 +1,18 @@ +identifier: nsim/nsim_hs5x/smp +name: Multi-core HS5x nSIM simulator +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - zephyr + - arcmwdt + - cross-compile +supported: + - smp +testing: + timeout_multiplier: 1.5 + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs5x_smp_12cores.dts b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.dts similarity index 100% rename from boards/arc/nsim/nsim_hs5x_smp_12cores.dts rename to boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml new file mode 100644 index 00000000000000..63a60a3423aca6 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores.yaml @@ -0,0 +1,17 @@ +identifier: nsim/nsim_hs5x/smp/12cores +name: Multi-core HS5x nSIM simulator (12 cores) +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - zephyr + - arcmwdt + - cross-compile +supported: + - smp +testing: + timeout_multiplier: 4 + ignore_tags: + - net + - bluetooth diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig new file mode 100644 index 00000000000000..cea98ef287a099 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_12cores_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MP_MAX_NUM_CPUS=12 diff --git a/boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig new file mode 100644 index 00000000000000..112ba7f1bd0896 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs5x_smp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs6x.dts b/boards/synopsys/nsim/nsim_nsim_hs6x.dts similarity index 100% rename from boards/arc/nsim/nsim_hs6x.dts rename to boards/synopsys/nsim/nsim_nsim_hs6x.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x.yaml b/boards/synopsys/nsim/nsim_nsim_hs6x.yaml new file mode 100644 index 00000000000000..08d1fecc9c235a --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs6x +name: HS6x nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - arcmwdt + - cross-compile + - zephyr +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_defconfig b/boards/synopsys/nsim/nsim_nsim_hs6x_defconfig new file mode 100644 index 00000000000000..5a48971e06d4fa --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ISA_ARCV3=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arc/nsim/nsim_hs6x_smp.dts b/boards/synopsys/nsim/nsim_nsim_hs6x_smp.dts similarity index 100% rename from boards/arc/nsim/nsim_hs6x_smp.dts rename to boards/synopsys/nsim/nsim_nsim_hs6x_smp.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml b/boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml new file mode 100644 index 00000000000000..5db80b6afa1d12 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp.yaml @@ -0,0 +1,18 @@ +identifier: nsim/nsim_hs6x/smp +name: Multi-core HS6x nSIM simulator +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - cross-compile + - zephyr + - arcmwdt +supported: + - smp +testing: + timeout_multiplier: 1.5 + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs6x_smp_12cores.dts b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.dts similarity index 100% rename from boards/arc/nsim/nsim_hs6x_smp_12cores.dts rename to boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml new file mode 100644 index 00000000000000..085f4bb93d53de --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores.yaml @@ -0,0 +1,17 @@ +identifier: nsim/nsim_hs6x/smp/12cores +name: Multi-core HS6x nSIM simulator (12 cores) +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - cross-compile + - zephyr + - arcmwdt +supported: + - smp +testing: + timeout_multiplier: 4 + ignore_tags: + - net + - bluetooth diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig new file mode 100644 index 00000000000000..cea98ef287a099 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_12cores_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MP_MAX_NUM_CPUS=12 diff --git a/boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig new file mode 100644 index 00000000000000..112ba7f1bd0896 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs6x_smp_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/synopsys/nsim/nsim_nsim_hs_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_defconfig new file mode 100644 index 00000000000000..123983e3241579 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_ARC_MPU_ENABLE=y diff --git a/boards/arc/nsim/nsim_hs_flash_xip.dts b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_flash_xip.dts rename to boards/synopsys/nsim/nsim_nsim_hs_flash_xip.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml new file mode 100644 index 00000000000000..e39cfe00f9af05 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs/flash_xip +name: HS nSIM simulator (FLASH XIP) +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig new file mode 100644 index 00000000000000..4c4786d7291633 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_flash_xip_defconfig @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_XIP=y +CONFIG_HARVARD=n diff --git a/boards/arc/nsim/nsim_hs3x_hostlink.dts b/boards/synopsys/nsim/nsim_nsim_hs_hostlink.dts similarity index 100% rename from boards/arc/nsim/nsim_hs3x_hostlink.dts rename to boards/synopsys/nsim/nsim_nsim_hs_hostlink.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml b/boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml new file mode 100644 index 00000000000000..6a2a224d2e69fb --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_hostlink.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs/hostlink +name: HS3x nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs_mpuv6.dts b/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_mpuv6.dts rename to boards/synopsys/nsim/nsim_nsim_hs_mpuv6.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml b/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml new file mode 100644 index 00000000000000..03e5609e7033d8 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_mpuv6.yaml @@ -0,0 +1,16 @@ +identifier: nsim/nsim_hs/mpuv6 +name: HS (with MPU v6) nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/arc/nsim/nsim_hs_smp.dts b/boards/synopsys/nsim/nsim_nsim_hs_smp.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_smp.dts rename to boards/synopsys/nsim/nsim_nsim_hs_smp.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_smp.yaml b/boards/synopsys/nsim/nsim_nsim_hs_smp.yaml new file mode 100644 index 00000000000000..50f910e3f8cba2 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_smp.yaml @@ -0,0 +1,19 @@ +identifier: nsim/nsim_hs/smp +name: Multi-core HS nSIM simulator +type: sim +simulation: mdb-nsim +simulation_exec: mdb +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +supported: + - smp +testing: + timeout_multiplier: 1.5 + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig new file mode 100644 index 00000000000000..f681801471837e --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_smp_defconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARC_MPU_ENABLE=n +CONFIG_SMP=y +CONFIG_MP_MAX_NUM_CPUS=2 +CONFIG_TICKET_SPINLOCKS=y diff --git a/boards/arc/nsim/nsim_hs_sram.dts b/boards/synopsys/nsim/nsim_nsim_hs_sram.dts similarity index 100% rename from boards/arc/nsim/nsim_hs_sram.dts rename to boards/synopsys/nsim/nsim_nsim_hs_sram.dts diff --git a/boards/synopsys/nsim/nsim_nsim_hs_sram.yaml b/boards/synopsys/nsim/nsim_nsim_hs_sram.yaml new file mode 100644 index 00000000000000..f2d8a0e8bd9255 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_sram.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_hs/sram +name: HS nSIM simulator (SRAM) +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig b/boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig new file mode 100644 index 00000000000000..fec69adbb50a27 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_hs_sram_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_HARVARD=n diff --git a/boards/arc/nsim/nsim_sem.dts b/boards/synopsys/nsim/nsim_nsim_sem.dts similarity index 100% rename from boards/arc/nsim/nsim_sem.dts rename to boards/synopsys/nsim/nsim_nsim_sem.dts diff --git a/boards/synopsys/nsim/nsim_nsim_sem.yaml b/boards/synopsys/nsim/nsim_nsim_sem.yaml new file mode 100644 index 00000000000000..fadc0783f72eac --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem.yaml @@ -0,0 +1,16 @@ +identifier: nsim/nsim_sem +name: SEM Nsim simulator +type: sim +arch: arc +simulation: nsim +simulation_exec: nsimdrv +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + default: true + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_sem_defconfig b/boards/synopsys/nsim/nsim_nsim_sem_defconfig new file mode 100644 index 00000000000000..deb2c9c05711e5 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_ARC_MPU_ENABLE=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/arc/nsim/nsim_sem_mpu_stack_guard.dts b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.dts similarity index 100% rename from boards/arc/nsim/nsim_sem_mpu_stack_guard.dts rename to boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.dts diff --git a/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml new file mode 100644 index 00000000000000..986345ab8e0dc8 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard.yaml @@ -0,0 +1,15 @@ +identifier: nsim/nsim_sem/mpu_stack_guard +name: SEM nSIM simulator (stack guard) +type: sim +arch: arc +simulation: nsim +simulation_exec: nsimdrv +toolchain: + - zephyr + - cross-compile + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig new file mode 100644 index 00000000000000..8fe546e4302138 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_sem_mpu_stack_guard_defconfig @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARC_HAS_STACK_CHECKING=n diff --git a/boards/arc/nsim/nsim_vpx5.dts b/boards/synopsys/nsim/nsim_nsim_vpx5.dts similarity index 100% rename from boards/arc/nsim/nsim_vpx5.dts rename to boards/synopsys/nsim/nsim_nsim_vpx5.dts diff --git a/boards/synopsys/nsim/nsim_nsim_vpx5.yaml b/boards/synopsys/nsim/nsim_nsim_vpx5.yaml new file mode 100644 index 00000000000000..b1169acd111773 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_vpx5.yaml @@ -0,0 +1,13 @@ +identifier: nsim/nsim_vpx5 +name: VPX5 nSIM simulator +type: sim +simulation: nsim +simulation_exec: nsimdrv +arch: arc +toolchain: + - arcmwdt +testing: + ignore_tags: + - net + - bluetooth +vendor: snps diff --git a/boards/synopsys/nsim/nsim_nsim_vpx5_defconfig b/boards/synopsys/nsim/nsim_nsim_vpx5_defconfig new file mode 100644 index 00000000000000..8ba152d9d36664 --- /dev/null +++ b/boards/synopsys/nsim/nsim_nsim_vpx5_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 +CONFIG_BUILD_OUTPUT_BIN=n +CONFIG_ARCV2_INTERRUPT_UNIT=y +CONFIG_ARCV2_TIMER=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arc/nsim/support/mdb_em.args b/boards/synopsys/nsim/support/mdb_em.args similarity index 100% rename from boards/arc/nsim/support/mdb_em.args rename to boards/synopsys/nsim/support/mdb_em.args diff --git a/boards/arc/nsim/support/mdb_em11d.args b/boards/synopsys/nsim/support/mdb_em11d.args similarity index 100% rename from boards/arc/nsim/support/mdb_em11d.args rename to boards/synopsys/nsim/support/mdb_em11d.args diff --git a/boards/arc/nsim/support/mdb_em7d_v22.args b/boards/synopsys/nsim/support/mdb_em7d_v22.args similarity index 100% rename from boards/arc/nsim/support/mdb_em7d_v22.args rename to boards/synopsys/nsim/support/mdb_em7d_v22.args diff --git a/boards/arc/nsim/support/mdb_hs.args b/boards/synopsys/nsim/support/mdb_hs.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs.args rename to boards/synopsys/nsim/support/mdb_hs.args diff --git a/boards/arc/nsim/support/mdb_hs3x_hostlink.args b/boards/synopsys/nsim/support/mdb_hs3x_hostlink.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs3x_hostlink.args rename to boards/synopsys/nsim/support/mdb_hs3x_hostlink.args diff --git a/boards/arc/nsim/support/mdb_hs5x.args b/boards/synopsys/nsim/support/mdb_hs5x.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs5x.args rename to boards/synopsys/nsim/support/mdb_hs5x.args diff --git a/boards/arc/nsim/support/mdb_hs5x_smp.args b/boards/synopsys/nsim/support/mdb_hs5x_smp.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs5x_smp.args rename to boards/synopsys/nsim/support/mdb_hs5x_smp.args diff --git a/boards/arc/nsim/support/mdb_hs5x_smp_12cores.args b/boards/synopsys/nsim/support/mdb_hs5x_smp_12cores.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs5x_smp_12cores.args rename to boards/synopsys/nsim/support/mdb_hs5x_smp_12cores.args diff --git a/boards/arc/nsim/support/mdb_hs6x.args b/boards/synopsys/nsim/support/mdb_hs6x.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs6x.args rename to boards/synopsys/nsim/support/mdb_hs6x.args diff --git a/boards/arc/nsim/support/mdb_hs6x_smp.args b/boards/synopsys/nsim/support/mdb_hs6x_smp.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs6x_smp.args rename to boards/synopsys/nsim/support/mdb_hs6x_smp.args diff --git a/boards/arc/nsim/support/mdb_hs6x_smp_12cores.args b/boards/synopsys/nsim/support/mdb_hs6x_smp_12cores.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs6x_smp_12cores.args rename to boards/synopsys/nsim/support/mdb_hs6x_smp_12cores.args diff --git a/boards/arc/nsim/support/mdb_hs_flash_xip.args b/boards/synopsys/nsim/support/mdb_hs_flash_xip.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_flash_xip.args rename to boards/synopsys/nsim/support/mdb_hs_flash_xip.args diff --git a/boards/arc/nsim/support/mdb_hs_mpuv6.args b/boards/synopsys/nsim/support/mdb_hs_mpuv6.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_mpuv6.args rename to boards/synopsys/nsim/support/mdb_hs_mpuv6.args diff --git a/boards/arc/nsim/support/mdb_hs_smp.args b/boards/synopsys/nsim/support/mdb_hs_smp.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_smp.args rename to boards/synopsys/nsim/support/mdb_hs_smp.args diff --git a/boards/arc/nsim/support/mdb_hs_sram.args b/boards/synopsys/nsim/support/mdb_hs_sram.args similarity index 100% rename from boards/arc/nsim/support/mdb_hs_sram.args rename to boards/synopsys/nsim/support/mdb_hs_sram.args diff --git a/boards/arc/nsim/support/mdb_sem.args b/boards/synopsys/nsim/support/mdb_sem.args similarity index 100% rename from boards/arc/nsim/support/mdb_sem.args rename to boards/synopsys/nsim/support/mdb_sem.args diff --git a/boards/arc/nsim/support/mdb_vpx5.args b/boards/synopsys/nsim/support/mdb_vpx5.args similarity index 100% rename from boards/arc/nsim/support/mdb_vpx5.args rename to boards/synopsys/nsim/support/mdb_vpx5.args diff --git a/boards/arc/nsim/support/nsim_em.props b/boards/synopsys/nsim/support/nsim_em.props similarity index 100% rename from boards/arc/nsim/support/nsim_em.props rename to boards/synopsys/nsim/support/nsim_em.props diff --git a/boards/arc/nsim/support/nsim_em11d.props b/boards/synopsys/nsim/support/nsim_em11d.props similarity index 100% rename from boards/arc/nsim/support/nsim_em11d.props rename to boards/synopsys/nsim/support/nsim_em11d.props diff --git a/boards/arc/nsim/support/nsim_em7d_v22.props b/boards/synopsys/nsim/support/nsim_em7d_v22.props similarity index 100% rename from boards/arc/nsim/support/nsim_em7d_v22.props rename to boards/synopsys/nsim/support/nsim_em7d_v22.props diff --git a/boards/arc/nsim/support/nsim_hs.props b/boards/synopsys/nsim/support/nsim_hs.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs.props rename to boards/synopsys/nsim/support/nsim_hs.props diff --git a/boards/arc/nsim/support/nsim_hs3x_hostlink.props b/boards/synopsys/nsim/support/nsim_hs3x_hostlink.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs3x_hostlink.props rename to boards/synopsys/nsim/support/nsim_hs3x_hostlink.props diff --git a/boards/arc/nsim/support/nsim_hs5x.props b/boards/synopsys/nsim/support/nsim_hs5x.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs5x.props rename to boards/synopsys/nsim/support/nsim_hs5x.props diff --git a/boards/arc/nsim/support/nsim_hs6x.props b/boards/synopsys/nsim/support/nsim_hs6x.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs6x.props rename to boards/synopsys/nsim/support/nsim_hs6x.props diff --git a/boards/arc/nsim/support/nsim_hs_flash_xip.props b/boards/synopsys/nsim/support/nsim_hs_flash_xip.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs_flash_xip.props rename to boards/synopsys/nsim/support/nsim_hs_flash_xip.props diff --git a/boards/arc/nsim/support/nsim_hs_mpuv6.props b/boards/synopsys/nsim/support/nsim_hs_mpuv6.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs_mpuv6.props rename to boards/synopsys/nsim/support/nsim_hs_mpuv6.props diff --git a/boards/arc/nsim/support/nsim_hs_sram.props b/boards/synopsys/nsim/support/nsim_hs_sram.props similarity index 100% rename from boards/arc/nsim/support/nsim_hs_sram.props rename to boards/synopsys/nsim/support/nsim_hs_sram.props diff --git a/boards/arc/nsim/support/nsim_sem.props b/boards/synopsys/nsim/support/nsim_sem.props similarity index 100% rename from boards/arc/nsim/support/nsim_sem.props rename to boards/synopsys/nsim/support/nsim_sem.props diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args b/boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.args similarity index 100% rename from boards/arc/nsim/support/nsim_sem_mpu_stack_guard.args rename to boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.args diff --git a/boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props b/boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.props similarity index 100% rename from boards/arc/nsim/support/nsim_sem_mpu_stack_guard.props rename to boards/synopsys/nsim/support/nsim_sem_mpu_stack_guard.props diff --git a/boards/arc/nsim/support/nsim_vpx5.props b/boards/synopsys/nsim/support/nsim_vpx5.props similarity index 100% rename from boards/arc/nsim/support/nsim_vpx5.props rename to boards/synopsys/nsim/support/nsim_vpx5.props diff --git a/boards/tdk/index.rst b/boards/tdk/index.rst new file mode 100644 index 00000000000000..fe11070b5bc13d --- /dev/null +++ b/boards/tdk/index.rst @@ -0,0 +1,10 @@ +.. _boards-tdk: + +TDK +### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/tdk/robokit1/Kconfig.robokit1 b/boards/tdk/robokit1/Kconfig.robokit1 new file mode 100644 index 00000000000000..136a9fe8df1f04 --- /dev/null +++ b/boards/tdk/robokit1/Kconfig.robokit1 @@ -0,0 +1,6 @@ +# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ROBOKIT1 + select SOC_SAME70Q21B diff --git a/boards/tdk/robokit1/board.cmake b/boards/tdk/robokit1/board.cmake new file mode 100644 index 00000000000000..391006d62de358 --- /dev/null +++ b/boards/tdk/robokit1/board.cmake @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=ATSAME70Q21") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) + +board_runner_args(openocd --cmd-post-verify "atsamv gpnvm set 1") +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/tdk/robokit1/board.yml b/boards/tdk/robokit1/board.yml new file mode 100644 index 00000000000000..c97c2a0c940214 --- /dev/null +++ b/boards/tdk/robokit1/board.yml @@ -0,0 +1,5 @@ +board: + name: robokit1 + vendor: tdk + socs: + - name: same70q21b diff --git a/boards/arm/tdk_robokit1/doc/img/tdk_robokit1.jpg b/boards/tdk/robokit1/doc/img/tdk_robokit1.jpg similarity index 100% rename from boards/arm/tdk_robokit1/doc/img/tdk_robokit1.jpg rename to boards/tdk/robokit1/doc/img/tdk_robokit1.jpg diff --git a/boards/tdk/robokit1/doc/index.rst b/boards/tdk/robokit1/doc/index.rst new file mode 100644 index 00000000000000..ef65431b7e5a96 --- /dev/null +++ b/boards/tdk/robokit1/doc/index.rst @@ -0,0 +1,184 @@ +.. _robokit1: + +TDK RoboKit 1 +############# + +Overview +******** + +The TDK RoboKit1 is a development board for use primarily with ROS2 and provides a large +number of small ground robotics useful sensors including chirp sensors for time of flight +(e.g. ultrasonic obstacle detection). + +It pairs a 300MHz Cortex-M7 ATSAME70Q21 with an array of TDK sensors and pin headers useful for robotics. + +.. image:: img/tdk_robokit1.jpg + :align: center + :alt: TDK RoboKit1 + +Hardware +******** + +- ATSAME70Q21 ARM Cortex-M7 Processor +- 12 MHz crystal oscillator (Pres) +- 32.768 kHz crystal oscillator +- Micro-AB USB device +- Micro-AB USB debug (Microchip EDBG) interface supporting CMSIS-DAP, Virtual COM Port and Data +- JTAG interface connector +- One reset pushbutton +- One red user LED +- TDK ICM 42688-P 6-Axis 32KHz IMU +- TDK ICP-10111 Pressure Sensor +- TDK NTC Thermistor for Temperature +- AKM AK09918C Magnetometer +- 2 TDK HVCi-4223 Cortex-M3 Dedicated Motor Controller +- 3 TDK ICS-43434 Stereo Microphones +- Connector for Industrial Dual IMU (TDK IIM-46230) +- TDK CH101 Ultrasonic Range Sensor Array (9 Connectors, comes with 3) + +Supported Features +================== + +The TDK RoboKit1 board supports the following hardware +features: + +.. list-table:: + : header-rows: 1 + + * - Peripheral + - Kconfig option + - Devicetree compatible + * - GPIO + - :kconfig:option:`CONFIG_GPIO_SAM` + - :dtcompatible:`atmel,sam-gpio` + * - USART + - :kconfig:option:`CONFIG_USART_SAM` + - :dtcompatible:`atmel,sam-usart` + * - UART + - :kconfig:option:`CONFIG_UART_SAM` + - :dtcompatible:`atmel,sam-uart` + * - SPI + - :kconfig:option:`CONFIG_SPI_SAM` + - :dtcompatible:`atmel,sam-spi` + * - I2C + - :kconfig:option:`CONFIG_I2C_SAM_TWIHS` + - :dtcompatible:`atmel,sam-i2c-twihs` + * - I2S + - :kconfig:option:`CONFIG_I2S_SAM_SSC` + - :dtcompatible:`atmel,sam-ssc` + * - ADC + - :kconfig:option:`CONFIG_ADC_SAM_AFEC` + - :dtcompatible:`atmel,sam-afec` + * - DAC + - :kconfig:option:`CONFIG_DAC_SAM` + - :dtcompatible:`atmel,sam-dac` + * - PWM + - :kconfig:option:`CONFIG_PWM_SAM` + - :dtcompatible:`atmel,sam-pwm` + * - CAN + - :kconfig:option:`CONFIG_CAN_SAM` + - :dtcompatible:`atmel,sam-can` + * - USB + - :kconfig:option:`CONFIG_USB_DC_SAM_USBHS` + - :dtcompatible:`atmel,sam-usbhs` + * - WATCHDOG + - :kconfig:option:`CONFIG_WDT_SAM` + - :dtcompatible:`atmel,sam-watchdog` + * - NVIC + - N/A + - :dtcompatible:`arm,v7m-nvic` + * - SYSTICK + - N/A + - N/A + * - COUNTER + - :kconfig:option:`CONFIG_COUNTER_SAM_TC` + - :dtcompatible:`atmel,sam-tc` + * - DMA + - :kconfig:option:`CONFIG_DMA_SAM_XDMAC` + - :dtcompatible:`atmel,sam-xdmac` + * - ENTROPY + - :kconfig:option:`CONFIG_ENTROPY_SAM_RNG` + - :dtcompatible:`atmel,sam-trng` + * - HWINFO (reset cause) + - :kconfig:option:`CONFIG_HWINFO_SAM_RSTC` + - :dtcompatible:`atmel,sam-rstc` + * - HWINFO (device id) + - :kconfig:option:`CONFIG_HWINFO_SAM` + - N/A + +The default configuration can be found in the Kconfig +:zephyr_file:`boards/tdk/robokit1/robokit1_defconfig`. + +Connections and IOs +=================== + +The TDK RoboKit Hardware Guide has detailed information about board connections. + +System Clock +============ + +The SAM E70 MCU is configured to use the 12 MHz external oscillator on the board +with the on-chip PLL to generate a 300 MHz system clock. + +Serial Port +=========== + +The ATSAME70Q21 MCU has five UARTs and three USARTs. One of the UARTs is +configured for the console and is available as a Virtual COM Port via the USB2 connector. + +Programming and Debugging +************************* + +Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_. +Both west flash and west debug commands should correctly work with both USB0 and USB1 +connected and the board powered. + +Flashing +======== + +#. Run your favorite terminal program to listen for output. Under Linux the + terminal should be :code:`/dev/ttyACM0`. For example: + + .. code-block:: console + + $ minicom -D /dev/ttyUSB0 -o + + The -o option tells minicom not to send the modem initialization + string. Connection should be configured as follows: + + - Speed: 115200 + - Data: 8 bits + - Parity: None + - Stop bits: 1 + +#. Connect the TDK RoboKit1 board to your host computer using the + USB debug port (USB1), USB2 for a serial console, and remaining micro USB for + power. Then build and flash the :ref:`hello_world` application. + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: robokit1 + :goals: build flash + + You should see "Hello World! robokit1" in your terminal. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: robokit1 + :maybe-skip-config: + :goals: debug + +References +********** + +TDK RoboKit1 Product Page: + https://invensense.tdk.com/products/robokit1-dk/ + +.. _OpenOCD tool: + http://openocd.org/ diff --git a/boards/tdk/robokit1/robokit1-common.dtsi b/boards/tdk/robokit1/robokit1-common.dtsi new file mode 100644 index 00000000000000..40fa35366a2b3f --- /dev/null +++ b/boards/tdk/robokit1/robokit1-common.dtsi @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2022 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "robokit1-pinctrl.dtsi" + +/ { + aliases { + led0 = &led_0; + magn0 = &akm09918c; + accel0 = &icm42688; + die-temp0 = &icm42688; + ambient-temp0 = &temp_sensor; + }; + + chosen { + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; + + leds { + compatible = "gpio-leds"; + led_0: led_0 { + gpios = <&pioa 11 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + led_1: led_1 { + gpios = <&pioa 12 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + led_2: led_2 { + gpios = <&pioa 13 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + led_3: led_3 { + gpios = <&pioa 14 GPIO_ACTIVE_HIGH>; + label = "User LED"; + }; + }; + + temp_sensor: ambient_temp_sensor { + compatible = "epcos,b57861s0103a039"; + io-channels = <&spi_adc 0>; + pullup-uv = <3300000>; + pullup-ohm = <0>; + pulldown-ohm = <10000>; + connected-positive; + }; +}; + +&cpu0 { + clock-frequency = <300000000>; +}; + +&afec0 { + pinctrl-0 = <&afec0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&dacc { + status = "okay"; +}; + +&twihs0 { + pinctrl-0 = <&twihs0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&twihs1 { + pinctrl-0 = <&twihs1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&twihs2 { + pinctrl-0 = <&twihs2_default>; + pinctrl-names = "default"; + status = "okay"; + akm09918c: akm09918c@c { + compatible = "asahi-kasei,akm09918c"; + reg = <0xc>; + }; +}; + +&spi0 { + pinctrl-0 = <&spi0_default>; + pinctrl-names = "default"; + dmas = <&xdmac 0 DMA_PERID_SPI0_TX>, <&xdmac 1 DMA_PERID_SPI0_RX>; + dma-names = "tx", "rx"; + cs-gpios =<&pioa 31 GPIO_ACTIVE_LOW>, + <&pioc 31 GPIO_ACTIVE_LOW>; + status = "okay"; + + icm42688: icm42688p@0 { + compatible = "invensense,icm42688"; + reg = <0>; + int-gpios = <&pioc 5 GPIO_ACTIVE_HIGH>; + spi-max-frequency = <24000000>; + accel-hz = <32000>; + accel-fs = <16>; + gyro-hz = <32000>; + gyro-fs = <2000>; + }; + spi_adc: adc@1 { + compatible = "ti,ads7052"; + reg = <1>; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <24000000>; + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_VDD_1"; + zephyr,vref-mv = <3300>; + zephyr,acquisition-time = ; + zephyr,resolution = <14>; + }; + }; +}; + +&spi1 { + pinctrl-0 = <&spi1_default>; + pinctrl-names = "default"; + cs-gpios = <&pioc 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart0 { + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usart2 { + current-speed = <115200>; + pinctrl-0 = <&usart2_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +zephyr_udc0: &usbhs { + status = "okay"; +}; + +&mdio { + pinctrl-0 = <&mdio_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm0 { + pinctrl-0 = <&pwm_default>; + pinctrl-names = "default"; + status = "okay"; +}; + + +&xdmac { + status = "okay"; +}; + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* + * The first half of sector 0 (64 kbytes) + * is reserved for the bootloader + */ + boot_partition: partition@0 { + label = "mcuboot"; + reg = <0x0 0x00010000>; + read-only; + }; + + /* From sector 1 to sector 7 (included): slot0 (896 kbytes) */ + slot0_partition: partition@20000 { + label = "image-0"; + reg = <0x00020000 0x000e0000>; + }; + + /* From sector 8 to sector 14 (included): slot1 (896 kbytes) */ + slot1_partition: partition@100000 { + label = "image-1"; + reg = <0x00100000 0x000e0000>; + }; + + /* Sector 15: scratch (128 kbytes) */ + scratch_partition: partition@1e0000 { + label = "image-scratch"; + reg = <0x001e0000 0x00020000>; + }; + }; +}; diff --git a/boards/arm/tdk_robokit1/tdk_robokit1-pinctrl.dtsi b/boards/tdk/robokit1/robokit1-pinctrl.dtsi similarity index 100% rename from boards/arm/tdk_robokit1/tdk_robokit1-pinctrl.dtsi rename to boards/tdk/robokit1/robokit1-pinctrl.dtsi diff --git a/boards/tdk/robokit1/robokit1.dts b/boards/tdk/robokit1/robokit1.dts new file mode 100644 index 00000000000000..46d160b20741f7 --- /dev/null +++ b/boards/tdk/robokit1/robokit1.dts @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2022 Intel Corporation + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#include "robokit1-common.dtsi" + +/ { + model = "TDK RoboKit1"; + compatible = "tdk,robokit1", "atmel,same70q21b", "atmel,same70"; +}; diff --git a/boards/tdk/robokit1/robokit1.yaml b/boards/tdk/robokit1/robokit1.yaml new file mode 100644 index 00000000000000..8cbd19f73a6f05 --- /dev/null +++ b/boards/tdk/robokit1/robokit1.yaml @@ -0,0 +1,21 @@ +identifier: robokit1 +name: TDK RoboKit1 +type: mcu +arch: arm +flash: 2048 +ram: 384 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - can + - dma + - hwinfo + - gpio + - i2c + - pwm + - spi + - usb_device + - watchdog +vendor: tdk diff --git a/boards/tdk/robokit1/robokit1_defconfig b/boards/tdk/robokit1/robokit1_defconfig new file mode 100644 index 00000000000000..0f48eff3adf680 --- /dev/null +++ b/boards/tdk/robokit1/robokit1_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_WDT_DISABLE_AT_BOOT=y + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y diff --git a/boards/arm/tdk_robokit1/support/openocd.cfg b/boards/tdk/robokit1/support/openocd.cfg similarity index 100% rename from boards/arm/tdk_robokit1/support/openocd.cfg rename to boards/tdk/robokit1/support/openocd.cfg diff --git a/boards/technexion/index.rst b/boards/technexion/index.rst new file mode 100644 index 00000000000000..31b1d47e448b6f --- /dev/null +++ b/boards/technexion/index.rst @@ -0,0 +1,10 @@ +.. _boards-technexion: + +TECHNEXION +########## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/technexion/pico_pi/Kconfig.defconfig b/boards/technexion/pico_pi/Kconfig.defconfig new file mode 100644 index 00000000000000..aebd510fe618d8 --- /dev/null +++ b/boards/technexion/pico_pi/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Pico-Pi iMX7D M4 board + +# Copyright (c) 2019, Joris Offouga +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_PICO_PI + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_PICO_PI diff --git a/boards/technexion/pico_pi/Kconfig.pico_pi b/boards/technexion/pico_pi/Kconfig.pico_pi new file mode 100644 index 00000000000000..02def5fdc0e33e --- /dev/null +++ b/boards/technexion/pico_pi/Kconfig.pico_pi @@ -0,0 +1,7 @@ +# Copyright (c) 2019, Joris Offouga +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PICO_PI + select SOC_PART_NUMBER_MCIMX7D7DVM10SC + select SOC_MCIMX7D_M4 if BOARD_PICO_PI_MCIMX7D_M4 diff --git a/boards/technexion/pico_pi/board.yml b/boards/technexion/pico_pi/board.yml new file mode 100644 index 00000000000000..61c6713a925b6b --- /dev/null +++ b/boards/technexion/pico_pi/board.yml @@ -0,0 +1,5 @@ +board: + name: pico_pi + vendor: technexion + socs: + - name: mcimx7d diff --git a/boards/technexion/pico_pi/doc/index.rst b/boards/technexion/pico_pi/doc/index.rst new file mode 100644 index 00000000000000..3b651729227bd7 --- /dev/null +++ b/boards/technexion/pico_pi/doc/index.rst @@ -0,0 +1,239 @@ +.. _pico_pi: + +Pico-Pi i.MX7D - Android Things IoT Development Platform +############################################################# + +Overview +******** + +The i.MX7D SoC is a Hybrid multi-core processor composed of Single Cortex A7 +core and Single Cortex M4 core. +Zephyr was ported to run on the M4 core. In a later release, it will also +communicate with the A7 core (running Linux) via RPmsg. + + +.. image:: pico_pi.jpg + :align: center + :alt: Pico-Pi i.MX7D + +Hardware +******** + +The Pico-Pi Platform is composed of a CPU and IO board. + +Pico-Pi IO Board +================ +- S1 - On/Off (MX7_ONOFF signal) +- Board to board connector : Edison compatible connector (70 configurable pins) +- mikroBUS expansion connector ADC, GPIO, I²C, PWM, SPI, UART) +- 10-pin needle JTAG Connector +- Debug USB exposing One UART +- MIPI DSI 1 lane Connector +- LCD Touch Connector +- Audio Jack: Mic and Stereo Headphone + +Pico-Pi CPU Board +================= + +- CPU i.MX7 Dual with a Single Cortex A7 (1 GHz) core and + Single Cortex M4 (200MHz) core +- Memory + + - RAM -> A7: 4GB + - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A7: 8GB eMMC + +For more information about the i.MX7 SoC and Pico-Pi i.MX7D, see these references: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Dual Datasheet`_ +- `i.MX 7 Dual Reference Manual`_ + +Supported Features +================== + +The Pico-Pi i.MX7D configuration supports the following hardware features on the +Cortex M4 Core: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The Pico-Pi board Board was tested with the following pinmux controller +configuration. + ++---------------+---------------------+--------------------------------+ +| Board Name | SoC Name | Usage | ++===============+=====================+================================+ +| UART_TX232 | UART1_TX | UART Console | ++---------------+---------------------+--------------------------------+ +| UART_RX232 | UART1_RX | UART Console | ++---------------+---------------------+--------------------------------+ +| RX_E | UART6_TX | UART (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ +| TX_E | UART6_RX | UART (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ +| I2CX_SDA_3V | I2C1_SDA | I2C (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ +| I2CX_SCL_3V | I2C1_SCL | I2C (mikroBUS and Edison) | ++---------------+---------------------+--------------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7D SoC has seven UARTs. The number 6 is configured for the console and +the number 2 is used in the mikroBUS connector. + +Programming and Debugging +************************* + +The Pico-Pi i.MX7D doesn't have QSPI flash for the M4 and it needs to be started by +the A7 core. The A7 core is responsible to load the M4 binary application into +the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and +get the M4 out of reset. +The A7 can perform these steps at bootloader level or after the Linux system +has booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and +M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + +References +========== + +- `i.MX 7 Dual Reference Manual`_ from page 182 (section 2.1.2 and 2.1.3) +- `Toradex Wiki`_ + + +At compilation time you have to choose which RAM will be used. This +configuration is done in the file :zephyr_file:`boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts` with +"zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties. The available +configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from A7 using +u-boot. + +Connect both micro USB interfaces into the PC. This is the A7 console and the +UART6 in the Edison connector is M4 console for Zephyr with both configured to work at 115200 8N1. +The USB interface is used to power the CPU and IO boards and is connected +to the USB OTG interface of the i.MX7D. + +After powering up the platform stop the u-boot execution on the A7 core and +expose the eMMC as mass storage with the following command in the u-boot +prompt: ``ums 0 mmc 0``. Copy the compiled zephyr.bin to the first FAT +partition and remove the mounted device on the PC by issuing a "Ctrl+C" in the +u-boot prompt. +Set the u-boot environment variables and run the zephyr.bin from the +appropriated memory configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'fatload mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Dual Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf + +.. _i.MX 7 Dual Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7DRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/arm/pico_pi_m4/doc/pico_pi_m4.jpg b/boards/technexion/pico_pi/doc/pico_pi.jpg similarity index 100% rename from boards/arm/pico_pi_m4/doc/pico_pi_m4.jpg rename to boards/technexion/pico_pi/doc/pico_pi.jpg diff --git a/boards/arm/pico_pi_m4/pico_pi_m4-pinctrl.dtsi b/boards/technexion/pico_pi/pico_pi-pinctrl.dtsi similarity index 100% rename from boards/arm/pico_pi_m4/pico_pi_m4-pinctrl.dtsi rename to boards/technexion/pico_pi/pico_pi-pinctrl.dtsi diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts new file mode 100644 index 00000000000000..988d5c2e39880c --- /dev/null +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.dts @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2019, Joris Offouga + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "pico_pi-pinctrl.dtsi" + +/ { + model = "Pico-Pi IMX7D board"; + compatible = "nxp,mcimx7d_m4"; + + aliases { + uart-6 = &uart6; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; + }; +}; + +&uart2 { + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&uart5 { + pinctrl-0 = <&uart5_default>; + pinctrl-names = "default"; +}; + +&uart6 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart6_default>; + pinctrl-names = "default"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml new file mode 100644 index 00000000000000..7baa570c548825 --- /dev/null +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2019, Joris Offouga +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: pico_pi/mcimx7d/m4 +name: Pico-Pi IMX7D +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +vendor: nxp diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig new file mode 100644 index 00000000000000..a9f1db5c8a767e --- /dev/null +++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2019, Joris Offouga +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_GPIO=n +CONFIG_PINCTRL=y diff --git a/boards/telink/index.rst b/boards/telink/index.rst new file mode 100644 index 00000000000000..52bece46290277 --- /dev/null +++ b/boards/telink/index.rst @@ -0,0 +1,10 @@ +.. _boards-telink: + +Telink Semiconductor +#################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/telink/tlsr9518adk80d/Kconfig.defconfig b/boards/telink/tlsr9518adk80d/Kconfig.defconfig new file mode 100644 index 00000000000000..001ad28758607e --- /dev/null +++ b/boards/telink/tlsr9518adk80d/Kconfig.defconfig @@ -0,0 +1,38 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_TLSR9518ADK80D + +config SOC_FLASH_TELINK_B91 + default y if FLASH + +if BT + +# BLE Controller SDK from hal_telink requires +# Telink's toolchain with FPU support +config FPU + default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" + +config BT_HCI_ACL_FLOW_CONTROL + default n + +choice BT_HCI_BUS_TYPE + default BT_B91 +endchoice + +endif # BT + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition + +config FLASH_LOAD_OFFSET + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION)) if USE_DT_CODE_PARTITION + +# Buffer for image writter shall be less(multiple of access alignment) or +# equal to flash page. tlsr9518adk80d boards use external P25Q16 IC as +# flesh memory. Flash page size of the IC is 256 bytes. So that, it is +# maximum image writer buffer size for such kind of boards. +config IMG_BLOCK_BUF_SIZE + default 256 if MCUBOOT_IMG_MANAGER + +endif diff --git a/boards/telink/tlsr9518adk80d/Kconfig.tlsr9518adk80d b/boards/telink/tlsr9518adk80d/Kconfig.tlsr9518adk80d new file mode 100644 index 00000000000000..5c88071e686c82 --- /dev/null +++ b/boards/telink/tlsr9518adk80d/Kconfig.tlsr9518adk80d @@ -0,0 +1,5 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_TLSR9518ADK80D + select SOC_TLSR9518 diff --git a/boards/riscv/tlsr9518adk80d/board.cmake b/boards/telink/tlsr9518adk80d/board.cmake similarity index 100% rename from boards/riscv/tlsr9518adk80d/board.cmake rename to boards/telink/tlsr9518adk80d/board.cmake diff --git a/boards/telink/tlsr9518adk80d/board.yml b/boards/telink/tlsr9518adk80d/board.yml new file mode 100644 index 00000000000000..b4d45ba665dcec --- /dev/null +++ b/boards/telink/tlsr9518adk80d/board.yml @@ -0,0 +1,5 @@ +board: + name: tlsr9518adk80d + vendor: telink + socs: + - name: tlsr9518 diff --git a/boards/riscv/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg b/boards/telink/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg similarity index 100% rename from boards/riscv/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg rename to boards/telink/tlsr9518adk80d/doc/img/tlsr9518_block_diagram.jpg diff --git a/boards/riscv/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg b/boards/telink/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg similarity index 100% rename from boards/riscv/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg rename to boards/telink/tlsr9518adk80d/doc/img/tlsr9518adk80d.jpg diff --git a/boards/telink/tlsr9518adk80d/doc/index.rst b/boards/telink/tlsr9518adk80d/doc/index.rst new file mode 100644 index 00000000000000..e80db259a77d8c --- /dev/null +++ b/boards/telink/tlsr9518adk80d/doc/index.rst @@ -0,0 +1,267 @@ +.. _tlsr9518adk80d: + +Telink TLSR9518ADK80D +##################### + +Overview +******** + +The TLSR9518A Generic Starter Kit is a hardware platform which +can be used to verify the `Telink TLSR951x series chipset`_ and develop applications +for several 2.4 GHz air interface standards including Bluetooth 5.2 (Basic data +rate, Enhanced data rate, LE, Indoor positioning and BLE Mesh), +Zigbee 3.0, Homekit, 6LoWPAN, Thread and 2.4 Ghz proprietary. + +.. figure:: img/tlsr9518adk80d.jpg + :align: center + :alt: TLSR9518ADK80D + +More information about the board can be found at the `Telink B91 Generic Starter Kit Hardware Guide`_ website. + +Hardware +******** + +The TLSR9518A SoC integrates a powerful 32-bit RISC-V MCU, DSP, AI Engine, 2.4 GHz ISM Radio, 256 +KB SRAM (128 KB of Data Local Memory and 128 KB of Instruction Local Memory), external Flash memory, +stereo audio codec, 14 bit AUX ADC, analog and digital Microphone input, PWM, flexible IO interfaces, +and other peripheral blocks required for advanced IoT, hearable, and wearable devices. + +.. figure:: img/tlsr9518_block_diagram.jpg + :align: center + :alt: TLSR9518ADK80D_SOC + +The TLSR9518ADK80D default board configuration provides the following hardware components: + +- RF conducted antenna +- 1 MB External Flash memory with reset button +- Chip reset button +- Mini USB interface +- 4-wire JTAG +- 4 LEDs, Key matrix up to 4 keys +- 2 line-in function (Dual Analog microphone supported when switching jumper from microphone path) +- Dual Digital microphone +- Stereo line-out + +Supported Features +================== + +The Zephyr TLSR9518ADK80D board configuration supports the following hardware features: + ++----------------+------------+------------------------------+ +| Interface | Controller | Driver/Component | ++================+============+==============================+ +| PLIC | on-chip | interrupt_controller | ++----------------+------------+------------------------------+ +| RISC-V Machine | on-chip | timer | +| Timer (32 KHz) | | | ++----------------+------------+------------------------------+ +| PINCTRL | on-chip | pinctrl | ++----------------+------------+------------------------------+ +| GPIO | on-chip | gpio | ++----------------+------------+------------------------------+ +| UART | on-chip | serial | ++----------------+------------+------------------------------+ +| PWM | on-chip | pwm | ++----------------+------------+------------------------------+ +| TRNG | on-chip | entropy | ++----------------+------------+------------------------------+ +| FLASH (MSPI) | on-chip | flash | ++----------------+------------+------------------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154, OpenThread | ++----------------+------------+------------------------------+ +| SPI (Master) | on-chip | spi | ++----------------+------------+------------------------------+ +| I2C (Master) | on-chip | i2c | ++----------------+------------+------------------------------+ +| ADC | on-chip | adc | ++----------------+------------+------------------------------+ + +.. note:: + To support "button" example project PC3-KEY3 (J20-19, J20-20) jumper needs to be removed and KEY3 (J20-19) should be connected to VDD3_DCDC (J51-13) externally. + + For the rest example projects use the default jumpers configuration. + +Other hardware features and example projects are not supported yet. + +Limitations +----------- + +- Maximum 3 GPIO pins could be configured to generate interrupts simultaneously. All pins must be related to different ports and use different IRQ numbers. +- DMA mode is not supported by I2C, SPI and Serial Port. +- UART hardware flow control is not implemented. +- SPI Slave mode is not implemented. +- I2C Slave mode is not implemented. + +Default configuration and IOs +============================= + +System Clock +------------ + +The TLSR9518ADK80D board is configured to use the 24 MHz external crystal oscillator +with the on-chip PLL/DIV generating the 48 MHz system clock. +The following values also could be assigned to the system clock in the board DTS file +:zephyr_file:`boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts`: + +- 16000000 +- 24000000 +- 32000000 +- 48000000 +- 64000000 +- 96000000 + +.. code-block:: + + &cpu0 { + clock-frequency = <48000000>; + }; + +PINs Configuration +------------------ + +The TLSR9518A SoC has five GPIO controllers (PORT_A to PORT_E), but only two are +currently enabled (PORT_B for LEDs control and PORT_C for buttons) in the board DTS file: + +- LED0 (blue): PB4, LED1 (green): PB5, LED2 (white): PB6, LED3 (red): PB7 +- Key Matrix SW0: PC2_PC3, SW1: PC2_PC1, SW2: PC0_PC3, SW3: PC0_PC1 + +Peripheral's pins on the SoC are mapped to the following GPIO pins in the +:zephyr_file:`boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts` file: + +- UART0 TX: PB2, RX: PB3 +- UART1 TX: PC6, RX: PC7 +- PWM Channel 0: PB4 +- PSPI CS0: PC4, CLK: PC5, MISO: PC6, MOSI: PC7 +- HSPI CS0: PA1, CLK: PA2, MISO: PA3, MOSI: PA4 +- I2C SCL: PE1, SDA: PE3 + +Serial Port +----------- + +The TLSR9518A SoC has 2 UARTs. The Zephyr console output is assigned to UART0. +The default settings are 115200 8N1. + +Programming and debugging +************************* + +Building +======== + +.. important:: + + These instructions assume you've set up a development environment as + described in the :ref:`getting_started`. + +To build applications using the default RISC-V toolchain from Zephyr SDK, just run the west build command. +Here is an example for the "hello_world" application. + +.. code-block:: console + + # From the root of the zephyr repository + west build -b tlsr9518adk80d samples/hello_world + +To use `Telink RISC-V Linux Toolchain`_, ``ZEPHYR_TOOLCHAIN_VARIANT`` and ``CROSS_COMPILE`` variables need to be set. +In addition ``CONFIG_FPU=y`` must be selected in :zephyr_file:`boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig` file since this +toolchain is compatible only with the float point unit usage. + +.. code-block:: console + + # Set Zephyr toolchain variant to cross-compile + export ZEPHYR_TOOLCHAIN_VARIANT=cross-compile + # Specify the Telink RISC-V Toolchain location + export CROSS_COMPILE=~/toolchains/nds32le-elf-mculib-v5f/bin/riscv32-elf- + # From the root of the zephyr repository + west build -b tlsr9518adk80d samples/hello_world + +`Telink RISC-V Linux Toolchain`_ is available on the `Burning and Debugging Tools for TLSR9 Series in Linux`_ page. + +Open a serial terminal with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flash the board, reset and observe the following messages on the selected +serial port: + +.. code-block:: console + + *** Booting Zephyr OS version 2.5.0 *** + Hello World! tlsr9518adk80d + + +Flashing +======== + +To flash the TLSR9518ADK80D board see the sources below: + +- `Burning and Debugging Tools for all Series`_ +- `Burning and Debugging Tools for TLSR9 Series`_ +- `Burning and Debugging Tools for TLSR9 Series in Linux`_ + +It is also possible to use the west flash command, but additional steps are required to set it up: + +- Download `Telink RISC-V Linux Toolchain`_. The toolchain contains tools for the board flashing as well. +- Since the ICEman tool is created for the 32-bit OS version it is necessary to install additional packages in case of the 64-bit OS version. + +.. code-block:: console + + sudo dpkg --add-architecture i386 + sudo apt-get update + sudo apt-get install -y libc6:i386 libncurses5:i386 libstdc++6:i386 + +- Run the "ICEman.sh" script. + +.. code-block:: console + + # From the root of the {path to the Telink RISC-V Linux Toolchain}/ice repository + sudo ./ICEman.sh + +- Now you should be able to run the west flash command with the toolchain path specified (TELINK_TOOLCHAIN_PATH). + +.. code-block:: console + + west flash --telink-tools-path=$TELINK_TOOLCHAIN_PATH + +- You can also run the west flash command without toolchain path specification if add SPI_burn and ICEman to PATH. + +.. code-block:: console + + export PATH=$TELINK_TOOLCHAIN_PATH/flash/bin:"$PATH" + export PATH=$TELINK_TOOLCHAIN_PATH/ice:"$PATH" + +Debugging +========= + +This port supports UART debug and OpenOCD+GDB. The `west debug` command also supported. You may run +it in a simple way, like: + +.. code-block:: console + + west debug + +Or with additional arguments, like: + +.. code-block:: console + + west debug --gdb-port= --gdb-ex= + +Example: + +.. code-block:: console + + west debug --gdb-port=1111 --gdb-ex="-ex monitor reset halt -ex b main -ex continue" + +References +********** + +.. target-notes:: + +.. _Telink TLSR951x series chipset: https://wiki.telink-semi.cn/wiki/chip-series/TLSR951x-Series/ +.. _Telink B91 Generic Starter Kit Hardware Guide: https://wiki.telink-semi.cn/wiki/Hardware/B91_Generic_Starter_Kit_Hardware_Guide/ +.. _Telink RISC-V Linux Toolchain: https://wiki.telink-semi.cn/tools_and_sdk/Tools/IDE/telink_riscv_linux_toolchain.zip +.. _Burning and Debugging Tools for all Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-all-Series/ +.. _Burning and Debugging Tools for TLSR9 Series: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/Burning-and-Debugging-Tools-for-TLSR9-Series/ +.. _Burning and Debugging Tools for TLSR9 Series in Linux: https://wiki.telink-semi.cn/wiki/IDE-and-Tools/BDT_for_TLSR9_Series_in_Linux/ diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi b/boards/telink/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi similarity index 100% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d-pinctrl.dtsi diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts b/boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts similarity index 100% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d.dts rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d.dts diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml b/boards/telink/tlsr9518adk80d/tlsr9518adk80d.yaml similarity index 100% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d.yaml rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d.yaml diff --git a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig similarity index 75% rename from boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig rename to boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig index c4cfdfea718e4e..881ec1fdbefc06 100644 --- a/boards/riscv/tlsr9518adk80d/tlsr9518adk80d_defconfig +++ b/boards/telink/tlsr9518adk80d/tlsr9518adk80d_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2021 Telink Semiconductor # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_TELINK_TLSR951X=y -CONFIG_SOC_TELINK_TLSR9518=y -CONFIG_BOARD_TLSR9518ADK80D=y CONFIG_GPIO=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000 CONFIG_HEAP_MEM_POOL_SIZE=4096 diff --git a/boards/ti/cc1352p1_launchxl/CMakeLists.txt b/boards/ti/cc1352p1_launchxl/CMakeLists.txt new file mode 100644 index 00000000000000..cdf4f19c873e1a --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() +zephyr_library_sources(board_antenna.c) diff --git a/boards/ti/cc1352p1_launchxl/Kconfig b/boards/ti/cc1352p1_launchxl/Kconfig new file mode 100644 index 00000000000000..6981f6fdf8bec8 --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/Kconfig @@ -0,0 +1,16 @@ +# TI CC1352R LaunchXL board + +# Copyright (c) 2021 Florin Stancu +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CC1352P1_LAUNCHXL + +config BOARD_ANTENNA_INIT_PRIO + int "Board antenna switch initialization priority" + default 70 + help + Set the priority for board init, must be greater than + KERNEL_INIT_PRIORITY_DEVICE but smaller than + IEEE802154_CC13XX_CC26XX_SUB_GHZ_INIT_PRIO. + +endif # BOARD_CC1352P1_LAUNCHXL diff --git a/boards/ti/cc1352p1_launchxl/Kconfig.cc1352p1_launchxl b/boards/ti/cc1352p1_launchxl/Kconfig.cc1352p1_launchxl new file mode 100644 index 00000000000000..3701bf6e19e944 --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/Kconfig.cc1352p1_launchxl @@ -0,0 +1,7 @@ +# TI CC1352R LaunchXL board + +# Copyright (c) 2021 Florin Stancu +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352P1_LAUNCHXL + select SOC_CC1352P diff --git a/boards/arm/cc1352p1_launchxl/board.cmake b/boards/ti/cc1352p1_launchxl/board.cmake similarity index 100% rename from boards/arm/cc1352p1_launchxl/board.cmake rename to boards/ti/cc1352p1_launchxl/board.cmake diff --git a/boards/ti/cc1352p1_launchxl/board.yml b/boards/ti/cc1352p1_launchxl/board.yml new file mode 100644 index 00000000000000..5d9b234947db6b --- /dev/null +++ b/boards/ti/cc1352p1_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc1352p1_launchxl + vendor: ti + socs: + - name: cc1352p diff --git a/boards/arm/cc1352p1_launchxl/board_antenna.c b/boards/ti/cc1352p1_launchxl/board_antenna.c similarity index 100% rename from boards/arm/cc1352p1_launchxl/board_antenna.c rename to boards/ti/cc1352p1_launchxl/board_antenna.c diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.dts b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts similarity index 100% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.dts rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.dts diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.yaml b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml similarity index 100% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl.yaml rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml diff --git a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl_defconfig b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig similarity index 85% rename from boards/arm/cc1352p1_launchxl/cc1352p1_launchxl_defconfig rename to boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig index 45a87b265cc48b..42ca455ed33026 100644 --- a/boards/arm/cc1352p1_launchxl/cc1352p1_launchxl_defconfig +++ b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC1352P=y -CONFIG_BOARD_CC1352P1_LAUNCHXL=y CONFIG_BUILD_OUTPUT_HEX=y # custom callback for the antenna switch CONFIG_CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS=y diff --git a/boards/arm/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg b/boards/ti/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg similarity index 100% rename from boards/arm/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg rename to boards/ti/cc1352p1_launchxl/doc/img/cc1352p1_launchxl.jpg diff --git a/boards/arm/cc1352p1_launchxl/doc/index.rst b/boards/ti/cc1352p1_launchxl/doc/index.rst similarity index 100% rename from boards/arm/cc1352p1_launchxl/doc/index.rst rename to boards/ti/cc1352p1_launchxl/doc/index.rst diff --git a/boards/arm/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml b/boards/ti/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml similarity index 100% rename from boards/arm/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml rename to boards/ti/cc1352p1_launchxl/dts/bindings/skyworks,sky13317.yaml diff --git a/boards/arm/cc1352p1_launchxl/support/openocd.cfg b/boards/ti/cc1352p1_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc1352p1_launchxl/support/openocd.cfg rename to boards/ti/cc1352p1_launchxl/support/openocd.cfg diff --git a/boards/ti/cc1352r1_launchxl/Kconfig.cc1352r1_launchxl b/boards/ti/cc1352r1_launchxl/Kconfig.cc1352r1_launchxl new file mode 100644 index 00000000000000..609bde5814f0a9 --- /dev/null +++ b/boards/ti/cc1352r1_launchxl/Kconfig.cc1352r1_launchxl @@ -0,0 +1,7 @@ +# TI CC1352R LaunchXL board + +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352R1_LAUNCHXL + select SOC_CC1352R diff --git a/boards/arm/cc1352r1_launchxl/board.cmake b/boards/ti/cc1352r1_launchxl/board.cmake similarity index 100% rename from boards/arm/cc1352r1_launchxl/board.cmake rename to boards/ti/cc1352r1_launchxl/board.cmake diff --git a/boards/ti/cc1352r1_launchxl/board.yml b/boards/ti/cc1352r1_launchxl/board.yml new file mode 100644 index 00000000000000..a96d6d89a10cca --- /dev/null +++ b/boards/ti/cc1352r1_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc1352r1_launchxl + vendor: ti + socs: + - name: cc1352r diff --git a/boards/arm/cc1352r1_launchxl/boosterpack_connector.dtsi b/boards/ti/cc1352r1_launchxl/boosterpack_connector.dtsi similarity index 100% rename from boards/arm/cc1352r1_launchxl/boosterpack_connector.dtsi rename to boards/ti/cc1352r1_launchxl/boosterpack_connector.dtsi diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts similarity index 100% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.dts rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.dts diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.yaml b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml similarity index 100% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl.yaml rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml diff --git a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl_defconfig b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig similarity index 82% rename from boards/arm/cc1352r1_launchxl/cc1352r1_launchxl_defconfig rename to boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig index 30e755d99f114c..872843de16d29b 100644 --- a/boards/arm/cc1352r1_launchxl/cc1352r1_launchxl_defconfig +++ b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC1352R=y -CONFIG_BOARD_CC1352R1_LAUNCHXL=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y diff --git a/boards/arm/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg b/boards/ti/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg similarity index 100% rename from boards/arm/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg rename to boards/ti/cc1352r1_launchxl/doc/img/cc1352r1_launchxl.jpg diff --git a/boards/arm/cc1352r1_launchxl/doc/index.rst b/boards/ti/cc1352r1_launchxl/doc/index.rst similarity index 100% rename from boards/arm/cc1352r1_launchxl/doc/index.rst rename to boards/ti/cc1352r1_launchxl/doc/index.rst diff --git a/boards/arm/cc1352r1_launchxl/support/openocd.cfg b/boards/ti/cc1352r1_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc1352r1_launchxl/support/openocd.cfg rename to boards/ti/cc1352r1_launchxl/support/openocd.cfg diff --git a/boards/ti/cc1352r_sensortag/Kconfig.cc1352r_sensortag b/boards/ti/cc1352r_sensortag/Kconfig.cc1352r_sensortag new file mode 100644 index 00000000000000..49506bd20ba231 --- /dev/null +++ b/boards/ti/cc1352r_sensortag/Kconfig.cc1352r_sensortag @@ -0,0 +1,8 @@ +# TI CC1352R SensorTag board + +# Copyright (c) 2019 Brett Witherspoon +# Copyright (c) 2020 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC1352R_SENSORTAG + select SOC_CC1352R diff --git a/boards/ti/cc1352r_sensortag/Kconfig.defconfig b/boards/ti/cc1352r_sensortag/Kconfig.defconfig new file mode 100644 index 00000000000000..4396ce0fbd3106 --- /dev/null +++ b/boards/ti/cc1352r_sensortag/Kconfig.defconfig @@ -0,0 +1,12 @@ +# TI CC1352R SensorTag board + +# Copyright (c) 2019 Brett Witherspoon +# Copyright (c) 2020 Friedt Professional Engineering Services, Inc +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_CC1352R_SENSORTAG + +config SPI + default SENSOR + +endif # BOARD_CC1352R_SENSORTAG diff --git a/boards/arm/cc1352r_sensortag/board.cmake b/boards/ti/cc1352r_sensortag/board.cmake similarity index 100% rename from boards/arm/cc1352r_sensortag/board.cmake rename to boards/ti/cc1352r_sensortag/board.cmake diff --git a/boards/ti/cc1352r_sensortag/board.yml b/boards/ti/cc1352r_sensortag/board.yml new file mode 100644 index 00000000000000..b359f530fa2330 --- /dev/null +++ b/boards/ti/cc1352r_sensortag/board.yml @@ -0,0 +1,5 @@ +board: + name: cc1352r_sensortag + vendor: ti + socs: + - name: cc1352r diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi b/boards/ti/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi similarity index 100% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag-pinctrl.dtsi diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts similarity index 100% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag.dts rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag.dts diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag.yaml b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml similarity index 100% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag.yaml rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml diff --git a/boards/arm/cc1352r_sensortag/cc1352r_sensortag_defconfig b/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig similarity index 84% rename from boards/arm/cc1352r_sensortag/cc1352r_sensortag_defconfig rename to boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig index 6345d1584962df..2cddbd5af73e24 100644 --- a/boards/arm/cc1352r_sensortag/cc1352r_sensortag_defconfig +++ b/boards/ti/cc1352r_sensortag/cc1352r_sensortag_defconfig @@ -5,10 +5,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC1352R=y -CONFIG_BOARD_CC1352R_SENSORTAG=y - CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE=y CONFIG_CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN=15 diff --git a/boards/arm/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg b/boards/ti/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg similarity index 100% rename from boards/arm/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg rename to boards/ti/cc1352r_sensortag/doc/img/cc1352r_sensortag.jpg diff --git a/boards/arm/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg b/boards/ti/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg similarity index 100% rename from boards/arm/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg rename to boards/ti/cc1352r_sensortag/doc/img/launchpad-lpstk-debug.jpg diff --git a/boards/arm/cc1352r_sensortag/doc/index.rst b/boards/ti/cc1352r_sensortag/doc/index.rst similarity index 100% rename from boards/arm/cc1352r_sensortag/doc/index.rst rename to boards/ti/cc1352r_sensortag/doc/index.rst diff --git a/boards/arm/cc1352r_sensortag/support/openocd.cfg b/boards/ti/cc1352r_sensortag/support/openocd.cfg similarity index 100% rename from boards/arm/cc1352r_sensortag/support/openocd.cfg rename to boards/ti/cc1352r_sensortag/support/openocd.cfg diff --git a/boards/ti/cc26x2r1_launchxl/Kconfig.cc26x2r1_launchxl b/boards/ti/cc26x2r1_launchxl/Kconfig.cc26x2r1_launchxl new file mode 100644 index 00000000000000..6ad560d1fef40f --- /dev/null +++ b/boards/ti/cc26x2r1_launchxl/Kconfig.cc26x2r1_launchxl @@ -0,0 +1,7 @@ +# TI CC26x2R1 LaunchXL board + +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC26X2R1_LAUNCHXL + select SOC_CC2652R diff --git a/boards/arm/cc26x2r1_launchxl/board.cmake b/boards/ti/cc26x2r1_launchxl/board.cmake similarity index 100% rename from boards/arm/cc26x2r1_launchxl/board.cmake rename to boards/ti/cc26x2r1_launchxl/board.cmake diff --git a/boards/ti/cc26x2r1_launchxl/board.yml b/boards/ti/cc26x2r1_launchxl/board.yml new file mode 100644 index 00000000000000..3361b2ccff7150 --- /dev/null +++ b/boards/ti/cc26x2r1_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc26x2r1_launchxl + vendor: ti + socs: + - name: cc2652r diff --git a/boards/arm/cc26x2r1_launchxl/boosterpack_connector.dtsi b/boards/ti/cc26x2r1_launchxl/boosterpack_connector.dtsi similarity index 100% rename from boards/arm/cc26x2r1_launchxl/boosterpack_connector.dtsi rename to boards/ti/cc26x2r1_launchxl/boosterpack_connector.dtsi diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts similarity index 100% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.dts rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.dts diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml similarity index 100% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml diff --git a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig similarity index 82% rename from boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig rename to boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig index 0906e953e163a5..d10e7a152e52d2 100644 --- a/boards/arm/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig +++ b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_CC13X2_CC26X2=y -CONFIG_SOC_CC2652R=y -CONFIG_BOARD_CC26X2R1_LAUNCHXL=y CONFIG_BUILD_OUTPUT_HEX=y CONFIG_CC13X2_CC26X2_BOOTLOADER_ENABLE=y diff --git a/boards/arm/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg b/boards/ti/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg similarity index 100% rename from boards/arm/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg rename to boards/ti/cc26x2r1_launchxl/doc/img/cc26x2r1_launchxl.jpg diff --git a/boards/arm/cc26x2r1_launchxl/doc/index.rst b/boards/ti/cc26x2r1_launchxl/doc/index.rst similarity index 100% rename from boards/arm/cc26x2r1_launchxl/doc/index.rst rename to boards/ti/cc26x2r1_launchxl/doc/index.rst diff --git a/boards/arm/cc26x2r1_launchxl/support/openocd.cfg b/boards/ti/cc26x2r1_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc26x2r1_launchxl/support/openocd.cfg rename to boards/ti/cc26x2r1_launchxl/support/openocd.cfg diff --git a/boards/ti/cc3220sf_launchxl/CMakeLists.txt b/boards/ti/cc3220sf_launchxl/CMakeLists.txt new file mode 100644 index 00000000000000..8bbc4cf2f34a6c --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +zephyr_library() +zephyr_library_sources(dbghdr.c) diff --git a/boards/ti/cc3220sf_launchxl/Kconfig.cc3220sf_launchxl b/boards/ti/cc3220sf_launchxl/Kconfig.cc3220sf_launchxl new file mode 100644 index 00000000000000..36564cdd16f74c --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/Kconfig.cc3220sf_launchxl @@ -0,0 +1,6 @@ +# TI SimpleLink CC3220SF LaunchXL Board +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +config BOARD_CC3220SF_LAUNCHXL + select SOC_CC3220SF diff --git a/boards/ti/cc3220sf_launchxl/board.cmake b/boards/ti/cc3220sf_launchxl/board.cmake new file mode 100644 index 00000000000000..9f0a0bef65e7ad --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/ti/cc3220sf_launchxl/board.yml b/boards/ti/cc3220sf_launchxl/board.yml new file mode 100644 index 00000000000000..f902db4d3928db --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc3220sf_launchxl + vendor: ti + socs: + - name: cc3220sf diff --git a/boards/arm/cc3220sf_launchxl/boosterpack_connector.dtsi b/boards/ti/cc3220sf_launchxl/boosterpack_connector.dtsi similarity index 100% rename from boards/arm/cc3220sf_launchxl/boosterpack_connector.dtsi rename to boards/ti/cc3220sf_launchxl/boosterpack_connector.dtsi diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi rename to boards/ti/cc3220sf_launchxl/cc3220sf_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.dts similarity index 100% rename from boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.dts rename to boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.dts diff --git a/boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.yaml b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml similarity index 100% rename from boards/arm/cc3220sf_launchxl/cc3220sf_launchxl.yaml rename to boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml diff --git a/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl_defconfig b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl_defconfig new file mode 100644 index 00000000000000..8f107f24a0b697 --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2022 Dhruva Gole + +CONFIG_BUILD_OUTPUT_HEX=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3220sf_launchxl/dbghdr.c b/boards/ti/cc3220sf_launchxl/dbghdr.c similarity index 100% rename from boards/arm/cc3220sf_launchxl/dbghdr.c rename to boards/ti/cc3220sf_launchxl/dbghdr.c diff --git a/boards/ti/cc3220sf_launchxl/doc/index.rst b/boards/ti/cc3220sf_launchxl/doc/index.rst new file mode 100644 index 00000000000000..dd58c203daa768 --- /dev/null +++ b/boards/ti/cc3220sf_launchxl/doc/index.rst @@ -0,0 +1,297 @@ +.. _cc3220sf_launchxl: + +CC3220SF LaunchXL +################# + +Overview +******** +The SimpleLink Wi-Fi CC3220SF LaunchPad development kit (CC3220SF-LAUNCHXL) +highlights CC3220SF, a single-chip wireless microcontroller (MCU) with +1MB internal flash, 4MB external serial flash, 256KB of RAM and enhanced +security features. + +See the `TI CC3220 Product Page`_ for details. + +Features: +========= + +* Two separate execution environments: a user application dedicated ARM + Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and + internet logical layers +* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem +* On-board accelerometer and temperature sensor +* Two buttons and three LEDs for user interaction +* UART through USB to PC +* BoosterPack plug-in module for adding graphical displays, audio + codecs, antenna selection, environmental sensing, and more +* Power from USB for the LaunchPad and optional external BoosterPack +* XDS110-based JTAG emulation with serial port for flash programming + +Details on the CC3220SF LaunchXL development board can be found in the +`CC3220SF LaunchPad Dev Kit Hardware User's Guide`_. + +Hardware +******** + +The CC3220SF SoC has two MCUs: + +#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, + and access to external serial 4MB flash with bootloader and peripheral + drivers in ROM. + +#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely + offloads Wi-Fi and internet protocols from the application MCU. + +Complete details of the CC3220SF SoC can be found in the `CC3220 TRM`_. + +Supported Features +================== + +Zephyr has been ported to the Applications MCU, with basic peripheral +driver support. + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| UART | on-chip | serial port-interrupt | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-----------------------+ +| SPI_0 | on-chip | Wi-Fi host driver | ++-----------+------------+-----------------------+ + +.. note:: + + For consistency with TI SimpleLink SDK and BoosterPack examples, + the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed + on bootup. + +The accelerometer, temperature sensors, or other peripherals +accessible through the BoosterPack, are not currently supported. + +Programming and Debugging +************************* + +TI officially supports development on the CC3220SF using the TI +`CC3220 SDK`_ on Windows and Linux using TI tools: Code Composer +Studio for debugging and `UniFlash`_ for flashing. + +For Windows developers, see the `CC3220 Getting Started Guide`_ for +instructions on installation of tools, and how to flash the board using +UniFlash. + +Note that zephyr.bin produced by the Zephyr SDK may not load via +UniFlash tool. If encountering difficulties, use the zephyr.elf +file and openocd instead (see below). + +The following instructions are geared towards Linux developers who +prefer command line tools to an IDE. + +Before flashing and debugging the board, there are a few one-time board +setup steps to follow. + +Prerequisites: +============== + +#. Download and install the latest version of `UniFlash`_. +#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. + + This should result in a new device "Texas Instruments XDS110 Embed + with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. + +#. Update the service pack, and place the board in "Development Mode". + + Setting "Development Mode" enables the JTAG interface, necessary + for subsequent use of OpenOCD and updating XDS110 firmware. + + Follow the instructions in Section 2.4 "Download the Application", + in the `CC3220 Getting Started Guide`_, except for steps 5 and 6 in + Section 2.4.1 which select an MCU image. + +#. Ensure the XDS-110 emulation firmware is updated. + + Download and install the latest `XDS-110 emulation package`_. + + Follow these `xds110 firmware update directions + `_ + + Note that the emulation package install may place the xdsdfu utility + in ``/ccs_base/common/uscif/xds110/``. + +#. Switch Jumper SOP[2..0] (J15) back to [001]. + + Remove power from the board (disconnect USB cable) before switching jumpers. + +#. Install OpenOCD + + You can obtain OpenOCD by following these + :ref:`installing the latest Zephyr SDK instructions `. + + After the installation, add the directory containing the OpenOCD executable + to your environment's PATH variable. For example, use this command in Linux: + + .. code-block:: console + + export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH + + If you had previously installed TI OpenOCD, you can simply switch to use + the one in the Zephyr SDK. If for some reason you wish to continue to use + your TI OpenOCD installation, you can set the OPENOCD and + OPENOCD_DEFAULT_PATH variables in + :zephyr_file:`boards/ti/cc3220sf_launchxl/board.cmake` to point the build + to the paths of the OpenOCD binary and its scripts, before + including the common openocd.board.cmake file: + + .. code-block:: cmake + + set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +#. Ensure CONFIG_XIP=y (default) is set. + + This locates the program into flash, and sets CONFIG_CC3220SF_DEBUG=y, + which prepends a debug header enabling the flash to persist over + subsequent reboots, bypassing the bootloader flash signature + verification. + + See Section 21.10 "Debugging Flash User Application Using JTAG" of the + `CC3220 TRM`_ for details on the secure flash boot process. + + +Once the above prerequisites are met, applications for the ``_cc3220sf_launchxl`` +board can be built, flashed, and debugged with openocd and gdb per the Zephyr +Application Development Primer (see :ref:`build_an_application` and +:ref:`application_run`). + +Flashing +======== + +To build and flash an application, execute the following commands for : + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3220sf_launchxl + :goals: flash + +This will load the image into flash. + +To see program output from UART0, connect a separate terminal window: + +.. code-block:: console + + % screen /dev/ttyACM0 115200 8N1 + +Then press the reset button (SW1) on the board to run the program. + +When using OpenOCD from Zephyr SDK to flash the device, you may notice +the program hangs when starting the network processor on the device, if the +program uses it. There is a known issue with how that version of OpenOCD +resets the network processor. You would need to manually hit the reset button +on the board to properly reset the device after flashing. + +Debugging +========= + +To debug a previously flashed image, after resetting the board, use the 'debug' +build target: + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3220sf_launchxl + :maybe-skip-config: + :goals: debug + + +Wi-Fi Support +************* + +The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported +to Zephyr, and communicates over a dedicated SPI to the network co-processor. +It is available as a Zephyr Wi-Fi device driver in +:zephyr_file:`drivers/wifi/simplelink`. + +Usage: +====== + +Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` +to enable Wi-Fi. +See :zephyr_file:`samples/net/wifi/boards/cc3220sf_launchxl.conf`. + +Provisioning: +============= + +SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. +To keep it simple for Zephyr development and demos, the SimpleLink +"Fast Connect" policy is enabled, with one-shot scanning. +This enables the cc3220sf_launchxl to automatically reconnect to the last +good known access point (AP), without having to restart a scan, and +re-specify the SSID and password. + +To connect to an AP, first run the Zephyr Wi-Fi shell sample application, +and connect to a known AP with SSID and password. + +See :zephyr:code-sample:`wifi-shell` + +Once the connection succeeds, the network co-processor keeps the AP identity in +its persistent memory. Newly loaded Wi-Fi applications then need not explicitly +execute any Wi-Fi scan or connect operations, until the need to change to a new AP. + +Secure Socket Offload +********************* + +The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket +offload point, enabling Zephyr BSD socket API calls to be directed to the +SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` +to ``y``. + +Secure socket (TLS) communication is handled as part of the socket APIs, +and enabled by: + +- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` + and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, +- using the TI Uniflash tool to program the required certificates and + keys to the secure flash filesystem, and enabling the TI Trusted + Root-Certificate Catalog. + +See :zephyr:code-sample:`sockets-http-get` and +:zephyr_file:`samples/net/sockets/http_get/boards/cc3220sf_launchxl.conf` for an +example. + +See the document `Simplelink Wi-Fi Certificates Handling`_ for details on +using the TI UniFlash tool for certificate programming. + +References +********** + +CC32xx Wiki: + http://processors.wiki.ti.com/index.php/CC31xx_%26_CC32xx + +.. _TI CC3220 Product Page: + http://www.ti.com/product/cc3220 + +.. _CC3220 TRM: + http://www.ti.com/lit/pdf/swru465 + +.. _CC3220 Programmer's Guide: + http://www.ti.com/lit/pdf/swru464 + +.. _CC3220 Getting Started Guide: + http://www.ti.com/lit/pdf/swru461 + +.. _UniFlash: + http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash + +.. _CC3220 SDK: + http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK + +.. _CC3220SF LaunchPad Dev Kit Hardware User's Guide: + http://www.ti.com/lit/pdf/swru463 + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download + +.. _Simplelink Wi-Fi Certificates Handling: + http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/cc3220sf_launchxl/support/openocd.cfg b/boards/ti/cc3220sf_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc3220sf_launchxl/support/openocd.cfg rename to boards/ti/cc3220sf_launchxl/support/openocd.cfg diff --git a/boards/arm/cc3220sf_launchxl/CMakeLists.txt b/boards/ti/cc3235sf_launchxl/CMakeLists.txt similarity index 100% rename from boards/arm/cc3220sf_launchxl/CMakeLists.txt rename to boards/ti/cc3235sf_launchxl/CMakeLists.txt diff --git a/boards/ti/cc3235sf_launchxl/Kconfig.cc3235sf_launchxl b/boards/ti/cc3235sf_launchxl/Kconfig.cc3235sf_launchxl new file mode 100644 index 00000000000000..c4a04b2d293a16 --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/Kconfig.cc3235sf_launchxl @@ -0,0 +1,6 @@ +# TI SimpleLink CC3235SF LaunchXL Board +# Copyright (c) 2019, Texas Instruments Incorporated +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_CC3235SF_LAUNCHXL + select SOC_CC3235SF diff --git a/boards/arm/cc3235sf_launchxl/board.cmake b/boards/ti/cc3235sf_launchxl/board.cmake similarity index 100% rename from boards/arm/cc3235sf_launchxl/board.cmake rename to boards/ti/cc3235sf_launchxl/board.cmake diff --git a/boards/ti/cc3235sf_launchxl/board.yml b/boards/ti/cc3235sf_launchxl/board.yml new file mode 100644 index 00000000000000..6cf8104545a466 --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: cc3235sf_launchxl + vendor: ti + socs: + - name: cc3235sf diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi similarity index 100% rename from boards/arm/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi rename to boards/ti/cc3235sf_launchxl/cc3235sf_launchxl-pinctrl.dtsi diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.dts similarity index 100% rename from boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.dts rename to boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.dts diff --git a/boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.yaml b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml similarity index 100% rename from boards/arm/cc3235sf_launchxl/cc3235sf_launchxl.yaml rename to boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml diff --git a/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl_defconfig b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl_defconfig new file mode 100644 index 00000000000000..acbb196bc4eb6f --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl_defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_BUILD_OUTPUT_HEX=y + +# Enable GPIO driver +CONFIG_GPIO=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/cc3235sf_launchxl/dbghdr.c b/boards/ti/cc3235sf_launchxl/dbghdr.c similarity index 100% rename from boards/arm/cc3235sf_launchxl/dbghdr.c rename to boards/ti/cc3235sf_launchxl/dbghdr.c diff --git a/boards/ti/cc3235sf_launchxl/doc/index.rst b/boards/ti/cc3235sf_launchxl/doc/index.rst new file mode 100644 index 00000000000000..cf865b8902883e --- /dev/null +++ b/boards/ti/cc3235sf_launchxl/doc/index.rst @@ -0,0 +1,297 @@ +.. _cc3235sf_launchxl: + +CC3235SF LaunchXL +################# + +Overview +******** +The SimpleLink Wi-Fi CC3235SF LaunchPad development kit (CC3235SF-LAUNCHXL) +highlights CC3235SF, a single-chip wireless microcontroller (MCU) with +1MB internal flash, 4MB external serial flash, 256KB of RAM, and enhanced +security features. It supports 802.11 a/b/g/n, both 2.4 GHz and 5 GHz. + +See the `TI CC3235 Product Page`_ for details. + +Features: +========= + +* Two separate execution environments: a user application dedicated ARM + Cortex-M4 MCU and a network processor MCU to run all Wi-Fi and + internet logical layers +* 40-pin LaunchPad standard leveraging the BoosterPack ecosystem +* On-board accelerometer and temperature sensor +* Two buttons and a RGB LED for user interaction +* UART through USB to PC +* BoosterPack plug-in module for adding graphical displays, audio + codecs, antenna selection, environmental sensing, and more +* Power from USB for the LaunchPad and optional external BoosterPack +* XDS110-based JTAG emulation with serial port for flash programming + +Details on the CC3235SF LaunchXL development board can be found in the +`CC3235SF LaunchPad Dev Kit Hardware User's Guide`_. + +Hardware +******** + +The CC3235SF SoC has two MCUs: + +#. Applications MCU - an ARM |reg| Cortex |reg|-M4 Core at 80 MHz, with 256Kb RAM, + and access to external serial 4MB flash with bootloader and peripheral + drivers in ROM. + +#. Network Coprocessor (NWP) - a dedicated ARM MCU, which completely + offloads Wi-Fi and internet protocols from the application MCU. + +Complete details of the CC3235SF SoC can be found in the `CC3235 TRM`_. + +Supported Features +================== + +Zephyr has been ported to the Applications MCU, with basic peripheral +driver support. + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| UART | on-chip | serial port-interrupt | ++-----------+------------+-----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-----------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-----------------------+ +| SPI_0 | on-chip | Wi-Fi host driver | ++-----------+------------+-----------------------+ + +.. note:: + + For consistency with TI SimpleLink SDK and BoosterPack examples, + the I2C driver defaults to I2C_BITRATE_FAST mode (400 kHz) bus speed + on bootup. + +The accelerometer, temperature sensors, or other peripherals +accessible through the BoosterPack, are not currently supported. + +Programming and Debugging +************************* + +TI officially supports development on the CC3235SF using the TI +`CC32xx SDK`_ on Windows and Linux using TI tools: Code Composer +Studio for debugging and `UniFlash`_ for flashing. + +For Windows developers, see the `CC32xx Quick Start Guide`_ for +instructions on installation of tools, and how to flash the board using +UniFlash. + +Note that ``zephyr.bin`` produced by the Zephyr SDK may not load via +UniFlash tool. If encountering difficulties, use the ``zephyr.elf`` +file and openocd instead (see below). + +The following instructions are geared towards Linux developers who +prefer command line tools to an IDE. + +Before flashing and debugging the board, there are a few one-time board +setup steps to follow. + +Prerequisites: +============== + +#. Download and install the latest version of `UniFlash`_. +#. Jumper SOP[2..0] (J15) to [010], and connect the USB cable to the PC. + + This should result in a new device "Texas Instruments XDS110 Embed + with CMSIS-DAP" appearing at /dev/ttyACM1 and /dev/ttyACM0. + +#. Update the service pack, and place the board in "Development Mode". + + Setting "Development Mode" enables the JTAG interface, necessary + for subsequent use of OpenOCD and updating XDS110 firmware. + + Follow the instructions in Section 2.4 "Download the Application", + in the `CC32xx Quick Start Guide`_, except for steps 5 and 6 in + Section 2.4.1 which select an MCU image. + +#. Ensure the XDS-110 emulation firmware is updated. + + Download and install the latest `XDS-110 emulation package`_. + + Follow these `xds110 firmware update directions + `_ + + Note that the emulation package install may place the xdsdfu utility + in ``/ccs_base/common/uscif/xds110/``. + +#. Switch Jumper SOP[2..0] (J15) back to [001]. + + Remove power from the board (disconnect USB cable) before switching jumpers. + +#. Install OpenOCD + + You can obtain OpenOCD by following these + :ref:`installing the latest Zephyr SDK instructions `. + + After the installation, add the directory containing the OpenOCD executable + to your environment's PATH variable. For example, use this command in Linux: + + .. code-block:: console + + export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH + + If you had previously installed TI OpenOCD, you can simply switch to use + the one in the Zephyr SDK. If for some reason you wish to continue to use + your TI OpenOCD installation, you can set the OPENOCD and + OPENOCD_DEFAULT_PATH variables in + :zephyr_file:`boards/ti/cc3220sf_launchxl/board.cmake` to point the build + to the paths of the OpenOCD binary and its scripts, before + including the common openocd.board.cmake file: + + .. code-block:: cmake + + set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +#. Ensure CONFIG_XIP=y (default) is set. + + This locates the program into flash, and sets CONFIG_CC3235SF_DEBUG=y, + which prepends a debug header enabling the flash to persist over + subsequent reboots, bypassing the bootloader flash signature + verification. + + See Section 21.10 "Debugging Flash User Application Using JTAG" of the + `CC3235 TRM`_ for details on the secure flash boot process. + + +Once the above prerequisites are met, applications for the ``_cc3235sf_launchxl`` +board can be built, flashed, and debugged with openocd and gdb per the Zephyr +Application Development Primer (see :ref:`build_an_application` and +:ref:`application_run`). + +Flashing +======== + +To build and flash an application, execute the following commands for : + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3235sf_launchxl + :goals: flash + +This will load the image into flash. + +To see program output from UART0, connect a separate terminal window: + +.. code-block:: console + + % screen /dev/ttyACM0 115200 8N1 + +Then press the reset button (SW1) on the board to run the program. + +When using OpenOCD from Zephyr SDK to flash the device, you may notice +the program hangs when starting the network processor on the device, if the +program uses it. There is a known issue with how that version of OpenOCD +resets the network processor. You would need to manually hit the reset button +on the board to properly reset the device after flashing. + +Debugging +========= + +To debug a previously flashed image, after resetting the board, use the 'debug' +build target: + +.. zephyr-app-commands:: + :zephyr-app: + :board: cc3235sf_launchxl + :maybe-skip-config: + :goals: debug + + +Wi-Fi Support +************* + +The SimpleLink Host Driver, imported from the SimpleLink SDK, has been ported +to Zephyr, and communicates over a dedicated SPI to the network co-processor. +It is available as a Zephyr Wi-Fi device driver in +:zephyr_file:`drivers/wifi/simplelink`. + +Usage: +====== + +Set :kconfig:option:`CONFIG_WIFI_SIMPLELINK` and :kconfig:option:`CONFIG_WIFI` to ``y`` +to enable Wi-Fi. +See :zephyr_file:`samples/net/wifi/boards/cc3235sf_launchxl.conf`. + +Provisioning: +============= + +SimpleLink provides a few rather sophisticated Wi-Fi provisioning methods. +To keep it simple for Zephyr development and demos, the SimpleLink +"Fast Connect" policy is enabled, with one-shot scanning. +This enables the cc3235sf_launchxl to automatically reconnect to the last +good known access point (AP), without having to restart a scan, and +re-specify the SSID and password. + +To connect to an AP, first run the Zephyr Wi-Fi shell sample application, +and connect to a known AP with SSID and password. + +See :zephyr:code-sample:`wifi-shell` + +Once the connection succeeds, the network co-processor keeps the AP identity in +its persistent memory. Newly loaded Wi-Fi applications then need not explicitly +execute any Wi-Fi scan or connect operations, until the need to change to a new AP. + +Secure Socket Offload +********************* + +The SimpleLink Wi-Fi driver provides socket operations to the Zephyr socket +offload point, enabling Zephyr BSD socket API calls to be directed to the +SimpleLink Wi-Fi driver, by setting :kconfig:option:`CONFIG_NET_SOCKETS_OFFLOAD` +to ``y``. + +Secure socket (TLS) communication is handled as part of the socket APIs, +and enabled by: + +- setting both :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` + and :kconfig:option:`CONFIG_TLS_CREDENTIAL_FILENAMES` to ``y``, +- using the TI Uniflash tool to program the required certificates and + keys to the secure flash filesystem, and enabling the TI Trusted + Root-Certificate Catalog. + +See :zephyr:code-sample:`sockets-http-get` and +:zephyr_file:`samples/net/sockets/http_get/boards/cc3235sf_launchxl.conf` for an +example. + +See the document `Simplelink Wi-Fi Certificates Handling`_ for details on +using the TI UniFlash tool for certificate programming. + +References +********** + +TI SimpleLink MCUs: + http://www.ti.com/microcontrollers/simplelink-mcus/overview.html + +.. _TI CC3235 Product Page: + http://www.ti.com/product/cc3235SF + +.. _CC3235 TRM: + http://www.ti.com/lit/pdf/swru543 + +.. _CC3x20/CC3x35 SimpleLink Wi-Fi and IoT Network Processor Programmer's Guide: + http://www.ti.com/lit/pdf/swru455 + +.. _CC32xx Quick Start Guide: + http://dev.ti.com/tirex/content/simplelink_cc32xx_sdk_2_40_01_01/docs/simplelink_mcu_sdk/Quick_Start_Guide.html + +.. _UniFlash: + http://processors.wiki.ti.com/index.php/Category:CCS_UniFlash + +.. _CC32xx SDK: + http://www.ti.com/tool/download/SIMPLELINK-CC32xx-SDK/2.40.01.01 + +.. _CC3235SF LaunchPad Dev Kit Hardware User's Guide: + http://www.ti.com/lit/pdf/swru539 + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download + +.. _Simplelink Wi-Fi Certificates Handling: + http://www.ti.com/lit/pdf/swpu332 diff --git a/boards/arm/cc3235sf_launchxl/support/openocd.cfg b/boards/ti/cc3235sf_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/cc3235sf_launchxl/support/openocd.cfg rename to boards/ti/cc3235sf_launchxl/support/openocd.cfg diff --git a/boards/ti/index.rst b/boards/ti/index.rst new file mode 100644 index 00000000000000..0d78a6e4827905 --- /dev/null +++ b/boards/ti/index.rst @@ -0,0 +1,10 @@ +.. _boards-ti: + +Texas Instruments +################# + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/ti/msp_exp432p401r_launchxl/Kconfig.msp_exp432p401r_launchxl b/boards/ti/msp_exp432p401r_launchxl/Kconfig.msp_exp432p401r_launchxl new file mode 100644 index 00000000000000..270cc9be561e54 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/Kconfig.msp_exp432p401r_launchxl @@ -0,0 +1,6 @@ +# TI SimpleLink MSP-EXP432P401R LaunchXL Development Board +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Linaro + +config BOARD_MSP_EXP432P401R_LAUNCHXL + select SOC_MSP432P401R diff --git a/boards/ti/msp_exp432p401r_launchxl/board.cmake b/boards/ti/msp_exp432p401r_launchxl/board.cmake new file mode 100644 index 00000000000000..ca103200fd057f --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Linaro + +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) diff --git a/boards/ti/msp_exp432p401r_launchxl/board.yml b/boards/ti/msp_exp432p401r_launchxl/board.yml new file mode 100644 index 00000000000000..1e9ed0b7ed3e2f --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/board.yml @@ -0,0 +1,5 @@ +board: + name: msp_exp432p401r_launchxl + vendor: ti + socs: + - name: msp432p401r diff --git a/boards/arm/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg b/boards/ti/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg similarity index 100% rename from boards/arm/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg rename to boards/ti/msp_exp432p401r_launchxl/doc/img/msp_exp432p401r_launchxl.jpg diff --git a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst new file mode 100644 index 00000000000000..e24d8140a253b7 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst @@ -0,0 +1,152 @@ +.. _msp_exp432p401r_launchxl: + +MSP-EXP432P401R LaunchXL +######################## + +Overview +******** + +The SimpleLink MSP‐EXP432P401R LaunchPad development kit is an easy-to-use evaluation +module for the SimpleLink MSP432P401R microcontroller. It contains everything needed to start +developing on the SimpleLink MSP432 low-power + performance ARM |reg| 32-bit Cortex |reg|-M4F +microcontroller (MCU). + +.. figure:: img/msp_exp432p401r_launchxl.jpg + :align: center + :alt: MSP-EXP432P401R LaunchXL development board + +Features: +========= + +* Low-power ARM Cortex-M4F MSP432P401R +* 40-pin LaunchPad development kit standard that leverages the BoosterPack plug-in module ecosystem +* XDS110-ET, an open-source onboard debug probe featuring EnergyTrace+ technology and application + UART +* Two buttons and two LEDs for user interaction +* Backchannel UART through USB to PC + +Details on the MSP-EXP432P401R LaunchXL development board can be found in the +MSP-EXP432P401R LaunchXL User's Guide. + +Supported Features +================== + +* The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the + default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low- + power modes to be used. +* The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK. + +The MSP-EXP432P401R LaunchXL development board configuration supports the following hardware features: + ++-----------+------------+-----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=======================+ +| NVIC | on-chip | nested vectored | +| | | interrupt controller | ++-----------+------------+-----------------------+ +| SYSTICK | on-chip | system clock | ++-----------+------------+-----------------------+ +| UART | on-chip | serial port | ++-----------+------------+-----------------------+ + +More details about the supported peripherals are available in MSP432P4XX TRM +Other hardware features are not currently supported by the Zephyr kernel. + +Building and Flashing +********************* + +Prerequisites: +============== + +#. Ensure the XDS-110 emulation firmware is updated. + + Download and install the latest `XDS-110 emulation package`_. + + Follow these `xds110 firmware update directions + `_ + + Note that the emulation package install may place the xdsdfu utility + in ``/ccs_base/common/uscif/xds110/``. + +#. Install OpenOCD + + You can obtain OpenOCD by following these + :ref:`installing the latest Zephyr SDK instructions `. + + After the installation, add the directory containing the OpenOCD executable + to your environment's PATH variable. For example, use this command in Linux: + + .. code-block:: console + + export PATH=$ZEPHYR_SDK_INSTALL_DIR/sysroots/x86_64-pokysdk-linux/usr/bin/openocd:$PATH + + If you had previously installed TI OpenOCD, you can simply switch to use + the one in the Zephyr SDK. If for some reason you wish to continue to use + your TI OpenOCD installation, you can set the OPENOCD and + OPENOCD_DEFAULT_PATH variables in + :zephyr_file:`boards/ti/msp_exp432p401r_launchxl/board.cmake` to point the build + to the paths of the OpenOCD binary and its scripts, before + including the common openocd.board.cmake file: + + .. code-block:: cmake + + set(OPENOCD "/usr/local/bin/openocd" CACHE FILEPATH "" FORCE) + set(OPENOCD_DEFAULT_PATH /usr/local/share/openocd/scripts) + include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) + +Flashing +======== + +Follow the :ref:`getting_started` instructions for Zephyr application +development. + +For example, to build and flash the :ref:`hello_world` application for the +MSP-EXP432P401R LaunchXL: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: msp_exp432p401r_launchxl + :goals: flash + +This will load the image into flash. + +To see program output from UART0, connect a separate terminal window: + +.. code-block:: console + + % screen /dev/ttyACM0 115200 8N1 + +Then press the reset button (S3) on the board to run the program. + +Debugging +========= + +To debug a previously flashed image, after resetting the board, use the 'debug' +build target: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: msp_exp432p401r_launchxl + :maybe-skip-config: + :goals: debug + +References +********** + +TI MSP432 Wiki: + https://en.wikipedia.org/wiki/TI_MSP432 + +TI MSP432P401R Product Page: + http://www.ti.com/product/msp432p401r + +TI MSP432 SDK: + http://www.ti.com/tool/SIMPLELINK-MSP432-SDK + +.. _UniFlash: + http://processors.wiki.ti.com/index.php/UniFlash_v4_Quick_Guide#Command_Line_Interface + +.. _CCS IDE: + http://www.ti.com/tool/ccstudio + +.. _XDS-110 emulation package: + http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS_Emulation_Software_.28emupack.29_Download diff --git a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts similarity index 93% rename from boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts rename to boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts index c9172dc0db9013..d7af9e0e5cbdda 100644 --- a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts +++ b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.dts @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: Apache-2.0 */ +/* Copyright (c) 2017 Linaro */ /dts-v1/; diff --git a/boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml similarity index 100% rename from boards/arm/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml rename to boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml diff --git a/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig new file mode 100644 index 00000000000000..b1a19a007d0563 --- /dev/null +++ b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Linaro + +CONFIG_BUILD_OUTPUT_HEX=y + +# Floating point options +CONFIG_FPU=y + +# Enable UART driver +CONFIG_SERIAL=y + +# Enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/msp_exp432p401r_launchxl/support/openocd.cfg b/boards/ti/msp_exp432p401r_launchxl/support/openocd.cfg similarity index 100% rename from boards/arm/msp_exp432p401r_launchxl/support/openocd.cfg rename to boards/ti/msp_exp432p401r_launchxl/support/openocd.cfg diff --git a/boards/ti/sk_am62/Kconfig.sk_am62 b/boards/ti/sk_am62/Kconfig.sk_am62 new file mode 100644 index 00000000000000..d7e83cba87ac76 --- /dev/null +++ b/boards/ti/sk_am62/Kconfig.sk_am62 @@ -0,0 +1,11 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2023 Texas Instruments Incorporated +# Copyright (c) 2023 L Lakshmanan +# +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_SK_AM62_AM6234_M4 + select SOC_AM6234_M4 + help + TI AM62x M4 Starter Kit (SK) Evaluation Module (EVM) diff --git a/boards/ti/sk_am62/board.yml b/boards/ti/sk_am62/board.yml new file mode 100644 index 00000000000000..da6e946fe02c54 --- /dev/null +++ b/boards/ti/sk_am62/board.yml @@ -0,0 +1,5 @@ +board: + name: sk_am62 + vendor: ti + socs: + - name: am6234 diff --git a/boards/arm/am62x_m4/doc/img/sk_am62_angled.webp b/boards/ti/sk_am62/doc/img/sk_am62_angled.webp similarity index 100% rename from boards/arm/am62x_m4/doc/img/sk_am62_angled.webp rename to boards/ti/sk_am62/doc/img/sk_am62_angled.webp diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst new file mode 100644 index 00000000000000..0a93edd1367a04 --- /dev/null +++ b/boards/ti/sk_am62/doc/index.rst @@ -0,0 +1,138 @@ +.. _sk_am62: + +SK-AM62 M4F Core +################ + +Overview +******** + +The SK-AM62 board configuration is used by Zephyr applications that run on +the TI AM62x platform. The board configuration provides support for the ARM +Cortex-M4F MCU core and the following features: + +- Nested Vector Interrupt Controller (NVIC) +- System Tick System Clock (SYSTICK) + +The board configuration also enables support for the semihosting debugging console. + +See the `TI AM62X Product Page`_ for details. + +.. figure:: img/sk_am62_angled.webp + :align: center + :alt: TI SK-AM62 EVM + + Texas Instruments SK-AM62 EVM + +Hardware +******** +The SK-AM62 EVM features the AM62x SoC, which is composed of a quad Cortex-A53 +cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on +the M4F core and the following listed hardware specifications are used: + +- Low-power ARM Cortex-M4F +- Memory + + - 256KB of SRAM + - 2GB of DDR4 + +- Debug + + - XDS110 based JTAG + +Supported Features +================== + +The sk_am62 configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| PINCTRL | on-chip | pinctrl | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial | ++-----------+------------+-------------------------------------+ + +Other hardware features are not currently supported by the port. + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 400 MHz. + +DDR RAM +------- + +The board has 2GB of DDR RAM available. This board configuration +allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400). + +Serial Port +----------- + +This board configuration uses a single serial communication channel with the +MCU domain UART (MCU_UART0). + +SD Card +******* + +Download TI's official `WIC`_ and flash the WIC file with an etching software +onto an SD-card. This will boot Linux on the A53 application cores of the EVM. +These cores will then load the zephyr binary on the M4 core using remoteproc. + +The default configuration can be found in +:zephyr_file:`boards/ti/sk_am62/sk_am62_am6234_m4_defconfig` + +Flashing +******** + +The board can using remoteproc, and uses the OpenAMP resource table to accomplish this. + +The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc. + +To test the M4F core, we build the `hello_world` sample with the following command. + +.. code-block:: console + + # From the root of the Zephyr repository + west build -p -b sk_am62/am6234/m4 samples/hello_world + +This builds the program and the binary is present in the `build/zephyr` directory as `zephyr.elf`. + +We now copy this binary onto the SD card in the `/lib/firmware` directory and name it as `am62-mcu-m4f0_0-fw`. + +.. code-block:: console + + # Mount the SD card at sdcard for example + sudo mount /dev/sdX sdcard + # copy the elf to the /lib/firmware directory + sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw + +The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot. + +To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `EVM Setup Page`_. + +After changing the boot mode, the board should go through the boot sequence on powering up. +The binary will run and print Hello world to the MCU_UART0 port. + +References +********** + +AM62x SK EVM TRM: + https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf + +.. _TI AM62X Product Page: + https://www.ti.com/product/AM625 + +.. _WIC: + https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-PvdSyIiioq/08.06.00.42/tisdk-default-image-am62xx-evm.wic.xz + +.. _AM62x SK EVM TRM: + https://www.ti.com/lit/ug/spruiv7/spruiv7.pdf + +.. _EVM Setup Page: + https://software-dl.ti.com/mcu-plus-sdk/esd/AM62X/08_06_00_18/exports/docs/api_guide_am62x/EVM_SETUP_PAGE.html diff --git a/boards/arm/am62x_m4/am62x_m4_sk.dts b/boards/ti/sk_am62/sk_am62_am6234_m4.dts similarity index 100% rename from boards/arm/am62x_m4/am62x_m4_sk.dts rename to boards/ti/sk_am62/sk_am62_am6234_m4.dts diff --git a/boards/ti/sk_am62/sk_am62_am6234_m4.yaml b/boards/ti/sk_am62/sk_am62_am6234_m4.yaml new file mode 100644 index 00000000000000..d257c6dc98d816 --- /dev/null +++ b/boards/ti/sk_am62/sk_am62_am6234_m4.yaml @@ -0,0 +1,8 @@ +identifier: sk_am62/am6234/m4 +name: TI AM62X M4 Starter Kit (SK) +type: mcu +arch: arm +toolchain: + - zephyr +ram: 192 +vendor: ti diff --git a/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig b/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig new file mode 100644 index 00000000000000..8ed54c6554e03f --- /dev/null +++ b/boards/ti/sk_am62/sk_am62_am6234_m4_defconfig @@ -0,0 +1,22 @@ +# Texas Instruments Sitara AM62x-SK-M4 EVM +# +# Copyright (c) 2023 Texas Instruments Incorporated +# Copyright (c) 2023 L Lakshmanan +# +# SPDX-License-Identifier: Apache-2.0 + +# Platform Configuration +CONFIG_CORTEX_M_SYSTICK=y + +# Zephyr Kernel Configuration +CONFIG_XIP=n + +# Enable Pinctrl +CONFIG_PINCTRL=y + +# Serial Driver +CONFIG_SERIAL=y + +# Enable Console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d b/boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d new file mode 100644 index 00000000000000..d17d33cfdf87b6 --- /dev/null +++ b/boards/toradex/colibri_imx7d/Kconfig.colibri_imx7d @@ -0,0 +1,6 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_COLIBRI_IMX7D + select SOC_PART_NUMBER_MCIMX7D5EVM10SC + select SOC_MCIMX7D_M4 if BOARD_COLIBRI_IMX7D_MCIMX7D_M4 diff --git a/boards/toradex/colibri_imx7d/Kconfig.defconfig b/boards/toradex/colibri_imx7d/Kconfig.defconfig new file mode 100644 index 00000000000000..4f108737fd2aac --- /dev/null +++ b/boards/toradex/colibri_imx7d/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Colibri iMX7D M4 board + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_COLIBRI_IMX7D_MCIMX7D_M4 + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + + +endif # BOARD_COLIBRI_IMX7D_MCIMX7D_M4 diff --git a/boards/toradex/colibri_imx7d/board.yml b/boards/toradex/colibri_imx7d/board.yml new file mode 100644 index 00000000000000..7a6ffe6249510d --- /dev/null +++ b/boards/toradex/colibri_imx7d/board.yml @@ -0,0 +1,5 @@ +board: + name: colibri_imx7d + vendor: toradex + socs: + - name: mcimx7d diff --git a/boards/arm/colibri_imx7d_m4/colibri_imx7d_m4-pinctrl.dtsi b/boards/toradex/colibri_imx7d/colibri_imx7d-pinctrl.dtsi similarity index 100% rename from boards/arm/colibri_imx7d_m4/colibri_imx7d_m4-pinctrl.dtsi rename to boards/toradex/colibri_imx7d/colibri_imx7d-pinctrl.dtsi diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts new file mode 100644 index 00000000000000..c59fac1a0a450d --- /dev/null +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2017,2019 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "colibri_imx7d-pinctrl.dtsi" +#include + +/ { + model = "TORADEX Colibri IMX7D board"; + compatible = "nxp,mcimx7d_m4"; + + aliases { + led0 = &green_led; + sw0 = &user_switch_1; + }; + + chosen { + zephyr,flash = &tcml_code; + zephyr,sram = &tcmu_sys; + zephyr,console = &uart2; + zephyr,shell-uart = &uart2; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_0 { + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + label = "User LED1"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_switch_1: user_sw_1 { + gpios = <&gpio2 26 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + label = "User SW1"; + zephyr,code = ; + }; + }; +}; + +&uart2 { + status = "okay"; + current-speed = <115200>; + modem-mode = <64>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_default>; + pinctrl-names = "default"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_default>; + pinctrl-names = "default"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_default>; + pinctrl-names = "default"; +}; + +&i2c4 { + pinctrl-0 = <&i2c4_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm1 { + pinctrl-0 = <&pwm1_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_default>; + pinctrl-names = "default"; +}; + +&pwm3 { + pinctrl-0 = <&pwm3_default>; + pinctrl-names = "default"; +}; + +&pwm4 { + pinctrl-0 = <&pwm4_default>; + pinctrl-names = "default"; +}; + +&mub { + status = "okay"; +}; diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml new file mode 100644 index 00000000000000..d28eccc9d2b8c2 --- /dev/null +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml @@ -0,0 +1,23 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: colibri_imx7d/mcimx7d/m4 +name: TORADEX Colibri IMX7D +type: mcu +arch: arm +ram: 32 +flash: 32 +toolchain: + - zephyr + - gnuarmemb + - xtools +testing: + ignore_tags: + - net + - bluetooth +supported: + - pwm +vendor: nxp diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig new file mode 100644 index 00000000000000..a55e01a9fa748d --- /dev/null +++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2017, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_PINCTRL=y diff --git a/boards/arm/colibri_imx7d_m4/doc/colibri_imx7d_m4.jpg b/boards/toradex/colibri_imx7d/doc/colibri_imx7d.jpg similarity index 100% rename from boards/arm/colibri_imx7d_m4/doc/colibri_imx7d_m4.jpg rename to boards/toradex/colibri_imx7d/doc/colibri_imx7d.jpg diff --git a/boards/toradex/colibri_imx7d/doc/index.rst b/boards/toradex/colibri_imx7d/doc/index.rst new file mode 100644 index 00000000000000..22b356fc1c6259 --- /dev/null +++ b/boards/toradex/colibri_imx7d/doc/index.rst @@ -0,0 +1,325 @@ +.. _colibri_imx7d: + +NXP i.MX 7 Computer on Module - Colibri iMX7 +############################################ + +Overview +******** + +The i.MX7 SoC is a Hybrid multi-core processor composed by Single/Dual Cortex A7 +core and Single Cortex M4 core. +Zephyr was ported to run on the M4 core. In a later release, it will also +communicate with the A7 core (running Linux) via RPmsg. + + +.. image:: colibri_imx7d.jpg + :align: center + :alt: Colibri-iMX7 + +Hardware +******** + +- i.MX7 Single/Dual Cortex A7 (800MHz/1.0GHz) core and Single Cortex M4 (200MHz) core + +- Memory + + - RAM -> A7: 256MB, 512MB and 1GB + - RAM -> M4: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A7: 4Gb eMMC and 512Mb NAND + +- Display + + - RGB 1920x1080x24bpp + - 4-wire Resistive touch + +- Multimedia + + - 1x Camera Parallel Interface + - 1x Analog Audio Line in (Stereo) + - 1x Analog Audio Mic in (Mono) + - 1x Analog Audio Headphone out (Stereo) + +- Connectivity + + - USB 2.0 OTG (High Speed) + - USB 2.0 host (High Speed) + - 10/100 Mbit/s Ethernet PHY + - 4x I2C + - 4x SPI + - 7x UART + - 1x IrDA + - 20x PWM + - Up to 125 GPIO + - 4x Analog Input (12 Bit) + - 2x SDIO/SD/MMC (8 Bit) + - 2x CAN + +For more information about the i.MX 7 SoC, Colibri iMX7 Computer on Module +and Colibri Evaluation Board, see these references: + +- `i.MX 7 Series Website`_ +- `i.MX 7 Dual Datasheet`_ +- `i.MX 7 Dual Reference Manual`_ +- `Colibri iMX7 Website`_ +- `Colibri iMX7 User Guide`_ +- `Colibri iMX7 Datasheet`_ +- `Colibri Evaluation Board Website`_ +- `Colibri Evaluation Board Datasheet`_ + +Supported Features +================== + +The Colibri iMX7D Computer on Module with Colibri Evaluation Board configuration +supports the following hardware features on the Cortex M4 Core: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++-----------+------------+-------------------------------------+ +| PWM | on-chip | pwm | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The Colibri iMX7D Computer on Module with Colibri Evaluation Board +was tested with the following pinmux controller configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART_B RXD | UART2_TXD | UART Console | ++---------------+-----------------+---------------------------+ +| UART_B TXD | UART2_RXD | UART Console | ++---------------+-----------------+---------------------------+ +| SODIMM_135 | GPIO1_IO02 | LED0 | ++---------------+-----------------+---------------------------+ +| SODIMM_133 | GPIO2_IO26 | SW0 | ++---------------+-----------------+---------------------------+ +| SODIMM_194 | I2C4_SDA | I2C_SDA | ++---------------+-----------------+---------------------------+ +| SODIMM_196 | I2C4_SCL | I2C_SCL | ++---------------+-----------------+---------------------------+ +| SODIMM_59 | PWM1/GPIO1_IO08 | PWM | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The M4 Core is configured to run at a 200 MHz clock speed. + +Serial Port +=========== + +The iMX7D SoC has seven UARTs. The number 2 is configured for the console and +the remaining are not used/tested. + +Programming and Debugging +************************* + +The Colibri iMX7D doesn't have QSPI flash for the M4 and it needs to be started by +the A7 core. The A7 core is responsible to load the M4 binary application into the +RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get +the M4 out of reset. +The A7 can perform these steps at bootloader level or after the Linux system has +booted. + +The M4 can use up to 5 different RAMs. These are the memory mapping for A7 and M4: + ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A7 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size | ++============+=======================+========================+=======================+======================+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 0x10000000-0x1FFEFFFF | 2048MB (less for M4) | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| TCML | 0x007F8000-0x007FFFFF | | 0x1FFF8000-0x1FFFFFFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00000000-0x00007FFF | 32KB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ +| QSPI Flash | | | 0x08000000-0x0BFFFFFF | 64MB | ++------------+-----------------------+------------------------+-----------------------+----------------------+ + + +References +========== + +- `i.MX 7 Dual Reference Manual`_ from page 190 (section 2.1.2 and 2.1.3) +- `Toradex Wiki`_ + + +At compilation time you have to choose which RAM will be used. This configuration is +done in the file :zephyr_file:`boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.dts` +with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" +properties. The available configurations are: + +.. code-block:: none + + "zephyr,flash" + - &ddr_code + - &tcml_code + - &ocram_code + - &ocram_s_code + - &ocram_pxp_code + - &ocram_epdc_code + + "zephyr,sram" + - &ddr_sys + - &tcmu_sys + - &ocram_sys + - &ocram_s_sys + - &ocram_pxp_sys + - &ocram_epdc_sys + + +Below you will find the instructions to load and run Zephyr on M4 from A7 using u-boot. + +Copy the compiled zephyr.bin to the first EXT partition of the SD card and plug into the +board. Power it up and stop the u-boot execution. +Set the u-boot environment variables and run the zephyr.bin from the appropriated memory +configured in the Zephyr compilation: + +.. code-block:: console + + setenv bootm4 'ext4load mmc 0:1 $m4addr $m4fw && dcache flush && bootaux $m4addr' + # TCML + setenv m4tcml 'setenv m4fw zephyr.bin; setenv m4addr 0x007F8000' + setenv bootm4tcml 'run m4tcml && run bootm4' + run bootm4tcml + # TCMU + setenv m4tcmu 'setenv m4fw zephyr.bin; setenv m4addr 0x00800000' + setenv bootm4tcmu 'run m4tcmu && run bootm4' + run bootm4tcmu + # OCRAM + setenv m4ocram 'setenv m4fw zephyr.bin; setenv m4addr 0x00900000' + setenv bootm4ocram 'run m4ocram && run bootm4' + run bootm4ocram + # OCRAM_S + setenv m4ocrams 'setenv m4fw zephyr.bin; setenv m4addr 0x00180000' + setenv bootm4ocrams 'run m4ocrams && run bootm4' + run bootm4ocrams + # DDR + setenv m4ddr 'setenv m4fw zephyr.bin; setenv m4addr 0x80000000' + setenv bootm4ddr 'run m4ddr && run bootm4' + run bootm4ddr + + +Debugging +========= + +Download and install `J-Link Tools`_ and `NXP iMX7D Connect CortexM4.JLinkScript`_. + +To run Zephyr Binary using J-Link create the following script in order to +get the Program Counter and Stack Pointer from zephyr.bin. + +get-pc-sp.sh: + +.. code-block:: console + + #!/bin/sh + + firmware=$1 + + pc=$(od -An -N 8 -t x4 $firmware | awk '{print $2;}') + sp=$(od -An -N 8 -t x4 $firmware | awk '{print $1;}') + + echo pc=$pc + echo sp=$sp + + +Get the SP and PC from firmware binary: ``./get-pc-sp.sh zephyr.bin`` + +.. code-block:: console + + pc=00900f01 + sp=00905020 + +Plug in the J-Link into the board and PC and run the J-Link command line tool: + +.. code-block:: console + + /usr/bin/JLinkExe -device Cortex-M4 -if JTAG -speed 4000 -autoconnect 1 -jtagconf -1,-1 -jlinkscriptfile iMX7D_Connect_CortexM4.JLinkScript + +The following steps are necessary to run the zephyr.bin: +1. Put the M4 core in reset +2. Load the binary in the appropriate addr (TMCL, TCMU, OCRAM, OCRAM_S or DDR) +3. Set PC (Program Counter) +4. Set SP (Stack Pointer) +5. Get the M4 core out of reset + +Issue the following commands inside J-Link commander: + +.. code-block:: console + + w4 0x3039000C 0xAC + loadfile zephyr.bin,0x00900000 + w4 0x00180000 00900f01 + w4 0x00180004 00905020 + w4 0x3039000C 0xAA + +With these mechanisms, applications for the ``colibri_imx7d/imx7d/m4`` board +configuration can be built and debugged in the usual way (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +References +========== + +- `Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors`_ +- `J-Link iMX7D Instructions`_ + +.. _Colibri Evaluation Board Website: + https://www.toradex.com/products/carrier-board/colibri-evaluation-carrier-board + +.. _Colibri Evaluation Board Datasheet: + https://docs.toradex.com/102284-colibri-evaluation-board-datasheet.pdf + +.. _Colibri iMX7 Website: + https://www.toradex.com/computer-on-modules/colibri-arm-family/nxp-freescale-imx7 + +.. _Colibri iMX7 User Guide: + https://developer.toradex.com/products/colibri-imx7 + +.. _Colibri iMX7 Datasheet: + https://docs.toradex.com/103125-colibri-arm-som-imx7-datasheet.pdf + +.. _i.MX 7 Series Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors:IMX7-SERIES?fsrch=1&sr=1&pageNum=1 + +.. _i.MX 7 Dual Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX7DCEC.pdf + +.. _i.MX 7 Dual Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX7DRM + +.. _J-Link Tools: + https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack + +.. _NXP iMX7D Connect CortexM4.JLinkScript: + https://wiki.segger.com/images/8/86/NXP_iMX7D_Connect_CortexM4.JLinkScript + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf + +.. _J-Link iMX7D Instructions: + https://wiki.segger.com/IMX7D + +.. _Toradex Wiki: + https://developer.toradex.com/knowledge-base/freertos-on-the-cortex-m4-of-a-colibri-imx7#Memory_areas diff --git a/boards/toradex/index.rst b/boards/toradex/index.rst new file mode 100644 index 00000000000000..1be6d87105a77b --- /dev/null +++ b/boards/toradex/index.rst @@ -0,0 +1,10 @@ +.. _boards-toradex: + +Toradex +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/toradex/verdin_imx8mp/Kconfig.defconfig b/boards/toradex/verdin_imx8mp/Kconfig.defconfig new file mode 100644 index 00000000000000..76903f1d2e1cc7 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/Kconfig.defconfig @@ -0,0 +1,15 @@ +# VERDIN_IMX8MP board defconfig + +# Copyright (c) 2023 Toradex +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_VERDIN_IMX8MP + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +endif # BOARD_VERDIN_IMX8MP diff --git a/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp b/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp new file mode 100644 index 00000000000000..41c84eb369005f --- /dev/null +++ b/boards/toradex/verdin_imx8mp/Kconfig.verdin_imx8mp @@ -0,0 +1,9 @@ +# VERDIN_IMX8MP board + +# Copyright (c) 2023 Toradex +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_VERDIN_IMX8MP + select SOC_MIMX8MP_M7 if BOARD_VERDIN_IMX8MP_MIMX8ML8_M7 || BOARD_VERDIN_IMX8MP_MIMX8ML8_M7_DDR + select SOC_PART_NUMBER_MIMX8ML8DVNLZ diff --git a/boards/arm/verdin_imx8mp_m7/board.cmake b/boards/toradex/verdin_imx8mp/board.cmake similarity index 100% rename from boards/arm/verdin_imx8mp_m7/board.cmake rename to boards/toradex/verdin_imx8mp/board.cmake diff --git a/boards/toradex/verdin_imx8mp/board.yml b/boards/toradex/verdin_imx8mp/board.yml new file mode 100644 index 00000000000000..6ffbf4561a2805 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/board.yml @@ -0,0 +1,8 @@ +board: + name: verdin_imx8mp + vendor: toradex + socs: + - name: mimx8ml8 + variants: + - name: ddr + cpucluster: m7 diff --git a/boards/toradex/verdin_imx8mp/doc/index.rst b/boards/toradex/verdin_imx8mp/doc/index.rst new file mode 100644 index 00000000000000..de7751ff0e6843 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/doc/index.rst @@ -0,0 +1,304 @@ +.. _verdin_imx8mp: + +Toradex Verdin iMX8M Plus SoM +############################# + +Overview +******** + +The Verdin iMX8M Plus is a Computer on Module (CoM) developed by Toradex. It is based on the NXP® +i.MX 8M Plus family of processors (or System on Chips - SoCs). + +The Verdin iMX8M Plus family consists of: + ++-------------------------------------------------+-----------------------+ +| CoM | SoC | ++=================================================+=======================+ +| Verdin iMX8M Plus Quad 8GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus Quad 4GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus Quad 4GB IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus Quad 2GB Wi-Fi / Bluetooth IT | i.MX 8M Plus Quad | ++-------------------------------------------------+-----------------------+ +| Verdin iMX8M Plus QuadLite 1GB IT | i.MX 8M Plus QuadLite | ++-------------------------------------------------+-----------------------+ + +Quoting NXP: + + The i.MX 8M Plus family focuses on machine learning and vision, advanced multimedia, and + industrial automation with high reliability. It is built to meet the needs of Smart Home, + Building, City and Industry 4.0 applications. + +The Verdin iMX8M Plus integrates a total of 4 Arm Cortex™-A53 CPUs, operating at 1.6 GHz, alongside +a single Arm Cortex™-M7F microcontroller operating at 800 MHz. + +.. figure:: verdin_imx8mp_front.jpg + :align: center + :alt: Toradex Verdin iMX8M Plus + + Toradex Verdin iMX8M Plus (Credit: Toradex) + +Regarding the Cortex-A53 cluster, it employs the ARMv8-A architecture as a mid-range and +energy-efficient processor. With four cores in this cluster, each core is equipped with its own L1 +memory system. Moreover, the cluster incorporates a unified L2 cache that offers supplementary +functions. This cache is housed within a single APR region. Facilitating debugging processes, the +cores support both real-time trace through the ETM system and static debugging via JTAG. +Furthermore, the platform features support for real-time trace capabilities, achieved through ARM's +CoreSight ETM modules, and also enables cross-triggering by utilizing CTI and CTM modules. + +The Arm® Cortex®-M7 microcontroller is indicated for Real-time control, combining high-performance +with a minimal interrupt latency. It stands out for its compatibility with existing Cortex-M profile +processors. The microcontroller employs an efficient in-order super-scalar pipeline, allowing +dual-issued instructions such as load/load and load/store pairs, thanks to its multiple memory +interfaces. These interfaces encompass Tightly-Coupled Memory (TCM), Harvard caches, and an AXI +master interface. The Arm Cortex-M7 Platform boasts features like a 32 KB L1 Instruction Cache, 32 +KB L1 Data Cache, Floating Point Unit (FPU) with FPv5 architecture support, and an Internal Trace +(TRC) mechanism. Furthermore, the chip supports 160 IRQs, and integrates crucial Arm CoreSight +components including ETM and CTI, dedicated to facilitating debug and trace functions. + +Hardware +******** + +- SoC name: NXP® i.MX 8M Plus +- CPU Type: 4x Arm Cortex™-A53 (1.6 GHz) +- Microcontroller: 1x Arm Cortex™-M7F (800 MHz) + +- Memory: + + - RAM -> A53: 1GB, 2GB, 4GB or 8GB + - RAM -> M7: 3x32KB (TCML, TCMU, OCRAM_S), 1x128KB (OCRAM) and 1x256MB (DDR) + - Flash -> A53: Up to 32GB eMMC + +- Connectivity: + + - USB 3.1: 1x Host / 1x OTG (Gen 1) + - USB 2.0: 1x Host / 1x OTG + - Ethernet Gigabit with TSN (+2nd RGMII) + - Wi-Fi Dual-band 802.11ac 2x2 MU-MIMO + - Bluetooth 5 + - 5x I2C + - 3x SPI + - 1 QSPI + - 4x UART + - Up to 92 GPIO + - 4x Analog Input + - 2x CAN (FlexCAN) + +- Multimedia: + + - Neural Processing Unit (NPU) + - Image Signal Processor (ISP) + - 2D and 3D acceleration + - HDMI, MIPI-DSI and MIPI-CSI interface + +For more information about the Verdin iMX8M Plus and the i.MX 8M Plus SoC refer to these links: + +- `i.MX 8M Plus Applications Processor page`_ +- `Verdin iMX8M Plus homepage`_ +- `Verdin iMX8M Plus developer page`_ +- `Verdin Development Board developer page`_ +- `Verdin iMX8M Plus Datasheet`_ +- `Verdin Development Board Datasheet`_ + +Supported Features +================== + +The Zephyr verdin_imx8mp_m7 board configuration supports the following hardware features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | GPIO output | +| | | GPIO input | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + +- :zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig`, if you choose to use + the ITCM memory. + +- :zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig`, if you choose to use + the DDR memory. + +It is recommended to disable peripherals used by the M7 core on the Linux host. + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +UART +---- + +Zephyr is configured to use the UART4 by default, which is connected to the FTDI USB converter on +most Toradex carrier boards. + +This is also the UART connected to WiFi/BT chip in modules that have the WiFi/BT chip. Therefore, if +UART4 is used, WiFI/BT will not work properly. + +If the WiFi/BT is needed, then another UART should be used for Zephyr (UART1 for example). You can +change the UART by changing the ``zephyr,console`` and ``zephyr,shell-uart`` in the +:zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts` or +:zephyr_file:`boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts` file. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| UART_1 | UART1 | General purpose UART | ++---------------+-----------------+---------------------------+ +| UART_4 | UART4 | Cortex-M4 debug UART | ++---------------+-----------------+---------------------------+ + +GPIO +---- + +All the GPIO banks available are enabled in the :zephyr_file:`dts/arm/nxp/nxp_imx8ml_m7.dtsi`. + +System Clock +============ + +The M7 Core is configured to run at a 800 MHz clock speed. + +Serial Port +=========== + +The i.MX8M Plus SoC has four UARTs. UART_4 is configured for the console and the remaining are not +used/tested. + +Programming and Debugging +************************* + +The Verdin iMX8M Plus board doesn't have QSPI flash for the M7, and it needs to be started by the +A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in +reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can +perform these steps at bootloader level or after the Linux system has booted. + +The M7 can use up to 3 different RAMs (currently, only two configurations are supported: ITCM and +DDR). These are the memory mapping for A53 and M7: + ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| Region | Cortex-A53 | Cortex-M7 (System Bus) | Cortex-M7 (Code Bus) | Size | ++============+=========================+========================+=======================+======================+ +| OCRAM | 0x00900000-0x0098FFFF | 0x20200000-0x2028FFFF | 0x00900000-0x0098FFFF | 576KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DTCM | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| ITCM | 0x007E0000-0x007FFFFF | | 0x00000000-0x0001FFFF | 128KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| OCRAM_S | 0x00180000-0x00188FFF | 0x20180000-0x20188FFF | 0x00180000-0x00188FFF | 36KB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ +| DDR | 0x80000000-0x803FFFFF | 0x80200000-0x803FFFFF | 0x80000000-0x801FFFFF | 2MB | ++------------+-------------------------+------------------------+-----------------------+----------------------+ + +For more information about memory mapping see the `i.MX 8M Plus Applications Processor Reference +Manual`_ (section 2.1 to 2.3) + +At compilation time you have to choose which RAM will be used. To facilitate this process, there are +two targets available: + +- ``verdin_imx8mp/mimx8ml8/m7``, which uses the ITCM configuration. +- ``verdin_imx8mp/mimx8ml8/m7/ddr``, which uses the DDR configuration. + + +Starting the Cortex-M7 via U-Boot +================================= + +Load and run Zephyr on M7 from A53 using u-boot by copying the compiled ``zephyr.bin`` to the first +FAT partition of the SD card and plug the SD card into the board. Power it up and stop the u-boot +execution at prompt. + +Load the M7 binary onto the desired memory and start its execution using: + +ITCM +==== + +Loading the binary from an EXT4 partition: + +.. code-block:: shell + + ext4load mmc 2:2 ${loadaddr} //zephyr.bin + cp.b ${loadaddr} 0x7e0000 + bootaux 0x7e0000 + +DDR +=== + +Loading the binary from an EXT4 partition: + +.. code-block:: shell + + ext4load mmc 2:2 ${loadaddr} //zephyr.bin + cp.b ${loadaddr} 0x80000000 + bootaux 0x80000000 + +Debugging +========= + +Toradex Verdin iMX8M Plus SoM can be debugged by connecting an external JLink JTAG debugger to the +X56 debug connector and to the PC, or simply connecting a USB-C to X66 on the Verdin Development +Board. Then, the application can be debugged using the usual way. + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: verdin_imx8mp/mimx8ml8/m7/ddr + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v3.4.0-2300-g03905f7e55d2 *** + Hello World! verdin_imx8mp + +References +========== + +- `How to Load Compiled Binaries into Cortex-M`_ +- `Cortex-M JTAG Debugging`_ +- `NXP website`_ + +.. _NXP website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK + +.. _i.MX 8M Plus Applications Processor Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMX8MPRM + +.. _How to Load Compiled Binaries into Cortex-M: + https://developer.toradex.com/software/real-time/cortex-m/how-to-load-binaries + +.. _Cortex-M JTAG Debugging: + https://developer.toradex.com/software/real-time/cortex-m/cortexm-jtag-debugging/ + +.. _i.MX 8M Plus Applications Processor page: + https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-applications-processors/i-mx-8m-plus-arm-cortex-a53-machine-learning-vision-multimedia-and-industrial-iot:IMX8MPLUS + +.. _Verdin iMX8M Plus homepage: + https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus + +.. _Verdin iMX8M Plus developer page: + https://developer.toradex.com/hardware/verdin-som-family/modules/verdin-imx8m-plus + +.. _Verdin Development Board developer page: + https://developer.toradex.com/hardware/verdin-som-family/carrier-boards/verdin-development-board/ + +.. _Verdin iMX8M Plus Datasheet: + https://docs.toradex.com/110977-verdin_imx8m_plus_v1.1_datasheet.pdf + +.. _Verdin Development Board Datasheet: + https://docs.toradex.com/109463-verdin_development_board_datasheet_v1.1.pdf diff --git a/boards/arm/verdin_imx8mp_m7/doc/verdin_imx8mp_front.jpg b/boards/toradex/verdin_imx8mp/doc/verdin_imx8mp_front.jpg similarity index 100% rename from boards/arm/verdin_imx8mp_m7/doc/verdin_imx8mp_front.jpg rename to boards/toradex/verdin_imx8mp/doc/verdin_imx8mp_front.jpg diff --git a/boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7-pinctrl.dtsi b/boards/toradex/verdin_imx8mp/verdin_imx8mp-pinctrl.dtsi similarity index 100% rename from boards/arm/verdin_imx8mp_m7/verdin_imx8mp_m7-pinctrl.dtsi rename to boards/toradex/verdin_imx8mp/verdin_imx8mp-pinctrl.dtsi diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts new file mode 100644 index 00000000000000..ad9b0fa7b696de --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.dts @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2023 Toradex + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "verdin_imx8mp-pinctrl.dtsi" +#include + +/ { + model = "Toradex Verdin iMX8M Plus M7"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* TCM */ + zephyr,flash = &itcm; + zephyr,sram = &dtcm; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml new file mode 100644 index 00000000000000..e4e77056bc0fcd --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2023 Toradex +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: verdin_imx8mp/mimx8ml8/m7 +name: Toradex Verdin iMX8M Plus (ITCM) +type: mcu +arch: arm +ram: 128 +flash: 128 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts new file mode 100644 index 00000000000000..43db40248cad0d --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.dts @@ -0,0 +1,46 @@ +/* + * Copyright (c) 2023 Toradex + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "verdin_imx8mp-pinctrl.dtsi" +#include + +/ { + model = "Toradex Verdin iMX8M Plus M7"; + compatible = "nxp,mimx8mp_evk"; + + chosen { + /* DDR */ + zephyr,flash = &ddr_code; + zephyr,sram = &ddr_sys; + + zephyr,console = &uart4; + zephyr,shell-uart = &uart4; + }; +}; + +&gpio3 { + status = "okay"; +}; + +&mailbox0 { + status = "okay"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart4 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart4_default>; + pinctrl-names = "default"; +}; diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml new file mode 100644 index 00000000000000..979dbfa498d24b --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml @@ -0,0 +1,18 @@ +# +# Copyright (c) 2023 Toradex +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: verdin_imx8mp/mimx8ml8/m7/ddr +name: Toradex Verdin iMX8M Plus (DDR) +type: mcu +arch: arm +ram: 2048 +flash: 2048 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - uart diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig new file mode 100644 index 00000000000000..0f2a48bcc79c12 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2023 Toradex +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_DDR=y +CONFIG_PINCTRL=y diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig new file mode 100644 index 00000000000000..c7f1110e266cd5 --- /dev/null +++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2023 Toradex +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CLOCK_CONTROL=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CONSOLE=y +CONFIG_XIP=y +CONFIG_CODE_ITCM=y +CONFIG_PINCTRL=y diff --git a/boards/u-blox/index.rst b/boards/u-blox/index.rst new file mode 100644 index 00000000000000..d1fe5fc4f4b8ba --- /dev/null +++ b/boards/u-blox/index.rst @@ -0,0 +1,10 @@ +.. _boards-u-blox: + +u-blox +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig b/boards/u-blox/ubx_bmd300eval/Kconfig new file mode 100644 index 00000000000000..361d81b0fed011 --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/Kconfig @@ -0,0 +1,10 @@ +# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD300EVAL diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig new file mode 100644 index 00000000000000..8ba8ca2d640fa2 --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD300EVAL + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD300EVAL diff --git a/boards/u-blox/ubx_bmd300eval/Kconfig.ubx_bmd300eval b/boards/u-blox/ubx_bmd300eval/Kconfig.ubx_bmd300eval new file mode 100644 index 00000000000000..1efa727323b06a --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/Kconfig.ubx_bmd300eval @@ -0,0 +1,7 @@ +# BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD300EVAL + select SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_bmd300eval_nrf52832/board.cmake b/boards/u-blox/ubx_bmd300eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/board.cmake rename to boards/u-blox/ubx_bmd300eval/board.cmake diff --git a/boards/u-blox/ubx_bmd300eval/board.yml b/boards/u-blox/ubx_bmd300eval/board.yml new file mode 100644 index 00000000000000..522c0808eed9ad --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd300eval + vendor: u-blox + socs: + - name: nrf52832 diff --git a/boards/arm/ubx_bmd300eval_nrf52832/doc/img/BMD-30-33-35-36-EVAL.jpg b/boards/u-blox/ubx_bmd300eval/doc/img/BMD-30-33-35-36-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/doc/img/BMD-30-33-35-36-EVAL.jpg rename to boards/u-blox/ubx_bmd300eval/doc/img/BMD-30-33-35-36-EVAL.jpg diff --git a/boards/arm/ubx_bmd300eval_nrf52832/doc/img/bmd-300-eval_pin_out.jpg b/boards/u-blox/ubx_bmd300eval/doc/img/bmd-300-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/doc/img/bmd-300-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd300eval/doc/img/bmd-300-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd300eval/doc/index.rst b/boards/u-blox/ubx_bmd300eval/doc/index.rst new file mode 100644 index 00000000000000..43e8d1d9fe9c8d --- /dev/null +++ b/boards/u-blox/ubx_bmd300eval/doc/index.rst @@ -0,0 +1,397 @@ +.. _ubx_bmd300eval_nrf52832: + +u-blox EVK-BMD-30/35: BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL +################################################################## + +Overview +******** + +The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL hardware provides +support for the u-blox BMD-300, BMD-301, and BMD-350 Bluetooth 5 +modules, based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F +CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-30-33-35-36-EVAL.jpg + :align: center + :alt: BMD-300-EVAL + + BMD-300-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share the same + pin headers and assignments. The boards are different only in + the module used on the board. The BMD-300 and BMD-301 modules + share the same footprint and differ only in the antenna. The + BMD-350 module utilizes the nRF52832 CIAA WLCSP package. + +More information about the BMD-300-EVAL, BMD-301-EVAL, and +BMD-350-EVAL and the respective modules can be found at the +`u-blox website`_. All of the Nordic Semiconductor examples for +the nRF52 DK (nrf52dk_nrf52832) may be used without modification. + +Hardware +******** + +The BMD-300/301/350 module on the board contains an internal +high-frequency oscillator at 32MHz. There is also a low frequency +(slow) oscillator of 32.768kHz. The module itself does not include +the slow crystal; however, the EVAL boards do. + +.. note:: + When targeting a custom design without a slow crystal, + be sure to modify code to utilize the internal RC + oscillator for the slow clock. + +Supported Features +================== + +The BMD-300/301/350-EVAL configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of +BMD-300/301/350-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.17 +* LED2 (red) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-300-eval_pin_out.jpg + :align: center + :alt: BMD-300-EVAL pin-out + + BMD-300-EVAL pin-out (Credit: u-blox AG) + +.. note:: + The BMD-300-EVAL, BMD-301-EVAL, and BMD-350-EVAL share + the same pin headers and assignments. + The BMD-300-EVAL is shown here. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-300/301/350-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 | ++-------+----------------+ +| 2 | P0.09 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.21 / RESET | ++-------+----------------+ +| 8 | P0.01 / XL2 | ++-------+----------------+ +| 9 | P0.00 / XL1 | ++-------+----------------+ +| 10 | GND | ++-------+----------------+ + + +Arduino Headers +--------------- + + +Power (J5) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | VSHLD | N/A | ++-------+--------------+---------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+---------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+---------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+---------------------------+ +| 5 | V5V | N/A | ++-------+--------------+---------------------------+ +| 6 | GND | N/A | ++-------+--------------+---------------------------+ +| 7 | GND | N/A | ++-------+--------------+---------------------------+ +| 8 | N/C | N/A | ++-------+--------------+---------------------------+ + + +Analog in (J8) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+---------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+---------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+---------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+---------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+---------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+---------------------------+ + + +Digital I/O (J7) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | D7 | P0.18/TRACEDATA[0]/SWO | ++-------+--------------+---------------------------+ +| 2 | D6 | P0.17 | ++-------+--------------+---------------------------+ +| 3 | D5 | P0.16/TRACEDATA[1] | ++-------+--------------+---------------------------+ +| 4 | D4 | P0.15/TRACEDATA[2] | ++-------+--------------+---------------------------+ +| 5 | D3 | P0.14/TRACEDATA[3] | ++-------+--------------+---------------------------+ +| 6 | D2 | P0.13 | ++-------+--------------+---------------------------+ +| 7 | D1 (TX) | P0.12 | ++-------+--------------+---------------------------+ +| 8 | D0 (RX) | P0.11 | ++-------+--------------+---------------------------+ + + +Digital I/O (J6) + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | SCL | P0.27 | ++-------+--------------+---------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+---------------------------+ +| 3 | AREF | P0.02/AIN0 | ++-------+--------------+---------------------------+ +| 4 | GND | N/A | ++-------+--------------+---------------------------+ +| 5 | D13 (SCK) | P0.25 | ++-------+--------------+---------------------------+ +| 6 | D12 (MISO) | P0.24 | ++-------+--------------+---------------------------+ +| 7 | D11 (MOSI) | P0.23 | ++-------+--------------+---------------------------+ +| 8 | D10 (SS) | P0.22 | ++-------+--------------+---------------------------+ +| 9 | D9 | P0.20/TRACECLK | ++-------+--------------+---------------------------+ +| 10 | D8 | P0.19 | ++-------+--------------+---------------------------+ + + +J11 + ++-------+--------------+---------------------------+ +| PIN # | Signal Name | BMD-300/301/350 Functions | ++=======+==============+===========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+---------------------------+ +| 2 | V5V | N/A | ++-------+--------------+---------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+---------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+---------------------------+ +| 5 | RESET | N/A | ++-------+--------------+---------------------------+ +| 6 | N/A | N/A | ++-------+--------------+---------------------------+ + + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the +BMD-300/301/350-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd300eval/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-330-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is +running correctly on your board. The button and LED definitions +can be found in :zephyr_file:`boards/ublox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-3035-series-open-cpu diff --git a/boards/arm/thingy52_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_bmd300eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/thingy52_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd300eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832-pinctrl.dtsi b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832-pinctrl.dtsi rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.dts b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.dts rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.dts diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.yaml b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml similarity index 88% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.yaml rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml index 09d6a50ed74723..910642809d6cc0 100644 --- a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832.yaml +++ b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd300eval_nrf52832 +identifier: ubx_bmd300eval/nrf52832 name: UBX_BMD300EVAL_NRF52832 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832_defconfig b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832_defconfig similarity index 75% rename from boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832_defconfig rename to boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832_defconfig index 0ac55829154b6b..8daa29dc47326f 100644 --- a/boards/arm/ubx_bmd300eval_nrf52832/ubx_bmd300eval_nrf52832_defconfig +++ b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832_defconfig @@ -1,9 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_UBX_BMD300EVAL_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig b/boards/u-blox/ubx_bmd330eval/Kconfig new file mode 100644 index 00000000000000..af68ffe247b660 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/Kconfig @@ -0,0 +1,15 @@ +# BMD-330-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD330EVAL + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd330eval/Kconfig.defconfig new file mode 100644 index 00000000000000..3f43013dd27820 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/Kconfig.defconfig @@ -0,0 +1,8 @@ +# BMD-330-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD330EVAL + +endif # BOARD_UBX_BMD330EVAL diff --git a/boards/u-blox/ubx_bmd330eval/Kconfig.ubx_bmd330eval b/boards/u-blox/ubx_bmd330eval/Kconfig.ubx_bmd330eval new file mode 100644 index 00000000000000..4c556d7927744f --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/Kconfig.ubx_bmd330eval @@ -0,0 +1,7 @@ +# BMD-330-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD330EVAL + select SOC_NRF52810_QFAA diff --git a/boards/arm/ubx_bmd330eval_nrf52810/board.cmake b/boards/u-blox/ubx_bmd330eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/board.cmake rename to boards/u-blox/ubx_bmd330eval/board.cmake diff --git a/boards/u-blox/ubx_bmd330eval/board.yml b/boards/u-blox/ubx_bmd330eval/board.yml new file mode 100644 index 00000000000000..d50ce8816f77ec --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd330eval + vendor: u-blox + socs: + - name: nrf52810 diff --git a/boards/arm/ubx_bmd330eval_nrf52810/doc/img/BMD-30-33-35-36-EVAL.jpg b/boards/u-blox/ubx_bmd330eval/doc/img/BMD-30-33-35-36-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/doc/img/BMD-30-33-35-36-EVAL.jpg rename to boards/u-blox/ubx_bmd330eval/doc/img/BMD-30-33-35-36-EVAL.jpg diff --git a/boards/arm/ubx_bmd330eval_nrf52810/doc/img/bmd-300-eval_pin_out.jpg b/boards/u-blox/ubx_bmd330eval/doc/img/bmd-300-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/doc/img/bmd-300-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd330eval/doc/img/bmd-300-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd330eval/doc/index.rst b/boards/u-blox/ubx_bmd330eval/doc/index.rst new file mode 100644 index 00000000000000..d23b576f8f5a70 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/doc/index.rst @@ -0,0 +1,388 @@ +.. _ubx_bmd330eval_nrf52810: + +u-blox EVK-BMD-330: BMD-330-EVAL +################################ + +Overview +******** + +The BMD-330-EVAL hardware provides support for the +u-blox BMD-330 Bluetooth 5 module, based on The +Nordic Semiconductor nRF52810 ARM Cortex-M4 CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-30-33-35-36-EVAL.jpg + :align: center + :alt: BMD-300-EVAL + + BMD-300-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-330-EVAL shares the same pin headers and assignments as the + BMD-300-EVAL. The BMD-300-EVAL is shown here. + +More information about the BMD-330-EVAL and the BMD-330 module +can be found at the `u-blox website`_. All of the Nordic +Semiconductor examples for the nRF52 DK (nrf52dk_nrf52810) +may be used without modification. + +Hardware +******** + +The BMD-330 on the BMD-330-EVAL contains an internal +high-frequency oscillator at 32MHz. There is also a low frequency +(slow) oscillator of 32.768kHz. The BMD-330 itself does not include +the slow crystal; however, the BMD-330-EVAL does. + +.. note:: + When targeting a custom design without a slow crystal, + be sure to modify code to utilize the internal RC + oscillator for the slow clock. + +Supported Features +================== + +The BMD-330-EVAL configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of +BMD-330-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.17 +* LED2 (red) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-300-eval_pin_out.jpg + :align: center + :alt: BMD-300-EVAL pin-out + + BMD-300-EVAL pin-out (Credit: u-blox AG) + +.. note:: + The BMD-330-EVAL shares the same pin headers and assignments + as the BMD-300-EVAL. The BMD-300-EVAL is shown here. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-330-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 | ++-------+----------------+ +| 2 | P0.09 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.21 / RESET | ++-------+----------------+ +| 8 | P0.01 / XL2 | ++-------+----------------+ +| 9 | P0.00 / XL1 | ++-------+----------------+ +| 10 | GND | ++-------+----------------+ + + +Arduino Headers +--------------- + + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+----------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+============================+ +| 1 | D7 | P0.18 | ++-------+--------------+----------------------------+ +| 2 | D6 | P0.17 | ++-------+--------------+----------------------------+ +| 3 | D5 | P0.16 | ++-------+--------------+----------------------------+ +| 4 | D4 | P0.15 | ++-------+--------------+----------------------------+ +| 5 | D3 | P0.14 | ++-------+--------------+----------------------------+ +| 6 | D2 | P0.13 | ++-------+--------------+----------------------------+ +| 7 | D1 (TX) | P0.12 | ++-------+--------------+----------------------------+ +| 8 | D0 (RX) | P0.11 | ++-------+--------------+----------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P0.22 | ++-------+--------------+-------------------------+ +| 9 | D9 | P0.20 | ++-------+--------------+-------------------------+ +| 10 | D8 | P0.19 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-330 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the +BMD-330-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd330eval/nrf52810 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-330-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is +running correctly on your board. The button and LED definitions +can be found in :zephyr_file:`boards/ublox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts`. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-330-open-cpu diff --git a/boards/arm/ubx_bmd300eval_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_bmd330eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd300eval_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd330eval/pre_dt_board.cmake diff --git a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml new file mode 100644 index 00000000000000..50d337f1c35b32 --- /dev/null +++ b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml @@ -0,0 +1,23 @@ +identifier: ubx_bmd330eval/nrf52810 +name: UBX_BMD330EVAL_NRF52810 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 24 +flash: 192 +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_spi + - gpio + - counter + - nvs + - i2c + - pwm + - spi + - watchdog +vendor: u-blox diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810-pinctrl.dtsi b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810-pinctrl.dtsi rename to boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.dts b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810.dts rename to boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810.dts diff --git a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810_defconfig b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810_defconfig similarity index 79% rename from boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810_defconfig rename to boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810_defconfig index edfe56e0a15528..7107ff3f634def 100644 --- a/boards/arm/ubx_bmd330eval_nrf52810/ubx_bmd330eval_nrf52810_defconfig +++ b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval_nrf52810_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52810_QFAA=y -CONFIG_BOARD_UBX_BMD330EVAL_NRF52810=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig b/boards/u-blox/ubx_bmd340eval/Kconfig new file mode 100644 index 00000000000000..6cc0ace7c6e136 --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/Kconfig @@ -0,0 +1,10 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD340EVAL diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig new file mode 100644 index 00000000000000..37b10951309cfb --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD340EVAL + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD340EVAL diff --git a/boards/u-blox/ubx_bmd340eval/Kconfig.ubx_bmd340eval b/boards/u-blox/ubx_bmd340eval/Kconfig.ubx_bmd340eval new file mode 100644 index 00000000000000..715be2a855baea --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/Kconfig.ubx_bmd340eval @@ -0,0 +1,7 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD340EVAL + select SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd340eval_nrf52840/board.cmake b/boards/u-blox/ubx_bmd340eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/board.cmake rename to boards/u-blox/ubx_bmd340eval/board.cmake diff --git a/boards/u-blox/ubx_bmd340eval/board.yml b/boards/u-blox/ubx_bmd340eval/board.yml new file mode 100644 index 00000000000000..2440541fc45be6 --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd340eval + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_bmd340eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg b/boards/u-blox/ubx_bmd340eval/doc/img/BMD-34-38-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg rename to boards/u-blox/ubx_bmd340eval/doc/img/BMD-34-38-EVAL.jpg diff --git a/boards/arm/ubx_bmd340eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg b/boards/u-blox/ubx_bmd340eval/doc/img/bmd-340-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd340eval/doc/img/bmd-340-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd340eval/doc/index.rst b/boards/u-blox/ubx_bmd340eval/doc/index.rst new file mode 100644 index 00000000000000..bb1afcfa7fae0b --- /dev/null +++ b/boards/u-blox/ubx_bmd340eval/doc/index.rst @@ -0,0 +1,521 @@ +.. _ubx_bmd340eval_nrf52840: + +u-blox EVK-BMD-34/38: BMD-340-EVAL and BMD-341-EVAL +################################################### + +Overview +******** + +The BMD-340-EVAL and BMD-341-EVAL hardware provides support for the +u-blox BMD-340 and BMD-341 Bluetooth 5.0 modules, based on the +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU. the BMD-340 and +BMD-341 are identical in operation except for the antenna. The +BMD-340 has a PCB antenna while the BMD-341 has a U.FL connector. +Both support the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-34-38-EVAL.jpg + :align: center + :alt: BMD-340-EVAL + + BMD-340-EVAL (Credit: u-blox AG) + +More information about the BMD-340-EVAL, BMD-340 module, BMD-341-EVAL, +and BMD-341 module can be found at the `u-blox website`_. +All of the Nordic Semiconductor examples for the nRF52840 DK +(nrf52840dk_nrf52840) may be used without modification. + +..note:: + The BMD-340 and BMD-341 are identical except for the antenna. + Throughout this board support package, the filenames utilize + the ubx_bmd340eval_nrf52840. + +Hardware +******** + +The BMD-340 on the BMD-340-EVAL (or BMD-341 on the BMD-341-EVAL) +contains an internal high-frequency oscillator at 32MHz. +There is also a low frequency (slow) oscillator of 32.768kHz. +The BMD-340 and BMD-341 do not include the slow crystal; +however, the BMD-340-EVAL and BMD-341-EVAL do. + +.. note:: + + When targeting a custom design without a slow crystal, be sure + to modify code to utilize the internal RC oscillator for the + slow clock. + +Supported Features +================== + +The BMD-340-EVAL and BMD-341-EVAL board configuration supports +the following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of BMD-340-EVAL +and BMD-341-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.13 +* LED2 (red) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-340-eval_pin_out.jpg + :align: center + :alt: BMD-340-EVAL pin-out + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-340-EVAL or + BMD-341-EVAL for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Debug IN (J26) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | BMD-340_VCC | ++-------+----------------+ +| 2 | BMD-340_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | BMD-340_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | BMD-340_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | GND | ++-------+----------------+ +| 10 | BMD-340_RESET | ++-------+----------------+ + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 / NFC2 | ++-------+----------------+ +| 2 | P0.09 / NFC1 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.01 / XL2 | ++-------+----------------+ +| 8 | P0.00 / XL1 | ++-------+----------------+ + +Auxiliary (J10) + ++-------+-------------------+ +| PIN # | Signal Name | ++=======+===================+ +| 1 | P0.11 / TRACED[2] | ++-------+-------------------+ +| 2 | P0.12 / TRACED[1] | ++-------+-------------------+ +| 3 | P0.13 | ++-------+-------------------+ +| 4 | P0.14 | ++-------+-------------------+ +| 5 | P0.15 | ++-------+-------------------+ +| 6 | P0.16 | ++-------+-------------------+ +| 7 | P0.17 / QSPI_CS | ++-------+-------------------+ +| 8 | P0.18 / RESET | ++-------+-------------------+ +| 9 | P0.19 / QSPI_CLK | ++-------+-------------------+ +| 10 | P0.20 / QSPI_D0 | ++-------+-------------------+ +| 11 | P0.21 / QSPI_D1 | ++-------+-------------------+ +| 12 | P0.22 / QSPI_D2 | ++-------+-------------------+ +| 13 | P0.23 / QSPI_D3 | ++-------+-------------------+ +| 14 | P0.24 | ++-------+-------------------+ +| 15 | P0.25 | ++-------+-------------------+ +| 16 | P1.00 / TRACED[0] | ++-------+-------------------+ +| 17 | P1.09 / TRACED[3] | ++-------+-------------------+ +| 18 | No connection | ++-------+-------------------+ + +Arduino Headers +--------------- + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | D7 | P1.08 | ++-------+--------------+-------------------------+ +| 2 | D6 | P1.07 | ++-------+--------------+-------------------------+ +| 3 | D5 | P1.06 | ++-------+--------------+-------------------------+ +| 4 | D4 | P1.05 | ++-------+--------------+-------------------------+ +| 5 | D3 | P1.04 | ++-------+--------------+-------------------------+ +| 6 | D2 | P1.03 | ++-------+--------------+-------------------------+ +| 7 | D1 (TX) | P1.02 | ++-------+--------------+-------------------------+ +| 8 | D0 (RX) | P1.01 | ++-------+--------------+-------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P1.15 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P1.14 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P1.13 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P1.12 | ++-------+--------------+-------------------------+ +| 9 | D9 | P1.11 | ++-------+--------------+-------------------------+ +| 10 | D8 | P1.10 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-34x Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.15 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.13 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Applications for the BMD-340-EVAL and BMD-341-EVAL board +configurations can be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` +for more details); however, the standard debugging targets +are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BMD-340-EVAL +or BMD-341-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd340eval/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-340-EVAL and BMD-341-EVAL +***************************************************************** + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found +in +:zephyr_file:`boards/ublox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your + application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is + used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app +main directory to be picked up automatically by the device tree +compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the BMD-340 at the `u-blox website`_, Section 2 +'Pin definition'. In the table 3 select the pins marked 'GPIO'. +Note that pins marked as 'Standard drive, low frequency I/O only +(<10 kH' can only be used in under-10KHz applications. +They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module + pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/docs/UBX-19033353 diff --git a/boards/arm/ubx_bmd330eval_nrf52810/pre_dt_board.cmake b/boards/u-blox/ubx_bmd340eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd330eval_nrf52810/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd340eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.dts rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.yaml b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml similarity index 90% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.yaml rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml index dbe7c648911fb2..be6ccd190a8037 100644 --- a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd340eval_nrf52840 +identifier: ubx_bmd340eval/nrf52840 name: UBX_BMD340EVAL_NRF52840 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840_defconfig b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840_defconfig similarity index 79% rename from boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840_defconfig rename to boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840_defconfig index f1fd8825b8c3d9..78510eb0204610 100644 --- a/boards/arm/ubx_bmd340eval_nrf52840/ubx_bmd340eval_nrf52840_defconfig +++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_BMD340EVAL_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig new file mode 100644 index 00000000000000..21e8ac9b5caf49 --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/Kconfig.defconfig @@ -0,0 +1,12 @@ +# BMD-345-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# Copyright (c) 2021 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD345EVAL_NRF52840 + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD345EVAL_NRF52840 diff --git a/boards/u-blox/ubx_bmd345eval/Kconfig.ubx_bmd345eval b/boards/u-blox/ubx_bmd345eval/Kconfig.ubx_bmd345eval new file mode 100644 index 00000000000000..01858fd7dcf405 --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/Kconfig.ubx_bmd345eval @@ -0,0 +1,8 @@ +# BMD-340-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# Copyright (c) 2021 Linumiz +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD345EVAL + select SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_bmd345eval_nrf52840/board.cmake b/boards/u-blox/ubx_bmd345eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/board.cmake rename to boards/u-blox/ubx_bmd345eval/board.cmake diff --git a/boards/u-blox/ubx_bmd345eval/board.yml b/boards/u-blox/ubx_bmd345eval/board.yml new file mode 100644 index 00000000000000..eec2be0b7d9711 --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd345eval + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_features.jpg b/boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_features.jpg similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_features.jpg rename to boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_features.jpg diff --git a/boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_pin_out.jpg b/boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/doc/img/bmd-345-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd345eval/doc/img/bmd-345-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd345eval/doc/index.rst b/boards/u-blox/ubx_bmd345eval/doc/index.rst new file mode 100644 index 00000000000000..e63507eb4fce48 --- /dev/null +++ b/boards/u-blox/ubx_bmd345eval/doc/index.rst @@ -0,0 +1,533 @@ +.. _ubx_bmd345eval_nrf52840: + +u-blox EVK-BMD-34/38: BMD-345-EVAL +################################## + +Overview +******** + +The BMD-345-EVALhardware provides support for the u-blox BMD-345 +Bluetooth 5.0 modules, based on the Nordic Semiconductor nRF52840 +ARM Cortex-M4F CPU and Skyworks RFX2411 Front End Module (FEM), +also known as a Power Amplifier / Low Noise Amplifier (PA/LNA). +Both support the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/bmd-345-eval_features.jpg + :align: center + :alt: BMD 345 EVAL + + BMD-345-EVAL (Credit: ublox AG) + +More information about the BMD-345-EVAL and BMD-345 module can be +found at the `u-blox website`_. + + +Hardware +******** + +The BMD-345 on the BMD-345-EVAL contains an internal high-frequency +oscillator at 32MHz. There is also a low frequency (slow) +oscillator of 32.768kHz. The BMD-345 does not include the slow +crystal; however, the BMD-345-EVAL does. + +.. note:: + + When targeting a custom design without a slow crystal, be sure + to modify code to utilize the internal RC oscillator for the + slow clock. + +Front End Module +================ + +BMD-345 utilizes the Skyworks RFX2411 front end module (FEM). +The FEM provides higher output power and better sensitivity. + +FEM pin assignments +------------------- + ++-------------+--------------+----------+--------+----------+---------+ +| GPIO Number | Signal Name | Shutdown | Bypass | Transmit | Receive | ++=============+==============+==========+========+==========+=========+ +| P1.05 | TX_EN | Low | Low | High | Low | ++-------------+--------------+----------+--------+----------+---------+ +| P1.06 | RX_EN | Low | Low | Low | High | ++-------------+--------------+----------+--------+----------+---------+ +| P1.04 | MODE | Low | High | Low | Low | ++-------------+--------------+----------+--------+----------+---------+ +| P1.02 | A_SEL | Low | Low | Low | Low | ++-------------+--------------+----------+--------+----------+---------+ + +Supported Features +================== + +The BMD-345-EVAL board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of BMD-345-EVAL +hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.13 +* LED2 (red) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-345-eval_pin_out.jpg + :align: center + :alt: BMD-345-EVAL pin-out + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-340-EVAL or + BMD-341-EVAL for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Debug IN (J26) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | BMD-340_VCC | ++-------+----------------+ +| 2 | BMD-340_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | BMD-340_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | BMD-340_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | GND | ++-------+----------------+ +| 10 | BMD-340_RESET | ++-------+----------------+ + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 / NFC2 | ++-------+----------------+ +| 2 | P0.09 / NFC1 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.01 / XL2 | ++-------+----------------+ +| 8 | P0.00 / XL1 | ++-------+----------------+ + +Auxiliary (J10) + ++-------+-------------------+ +| PIN # | Signal Name | ++=======+===================+ +| 1 | P0.11 / TRACED[2] | ++-------+-------------------+ +| 2 | P0.12 / TRACED[1] | ++-------+-------------------+ +| 3 | P0.13 | ++-------+-------------------+ +| 4 | P0.14 | ++-------+-------------------+ +| 5 | P0.15 | ++-------+-------------------+ +| 6 | P0.16 | ++-------+-------------------+ +| 7 | P0.17 / QSPI_CS | ++-------+-------------------+ +| 8 | P0.18 / RESET | ++-------+-------------------+ +| 9 | P0.19 / QSPI_CLK | ++-------+-------------------+ +| 10 | P0.20 / QSPI_D0 | ++-------+-------------------+ +| 11 | P0.21 / QSPI_D1 | ++-------+-------------------+ +| 12 | P0.22 / QSPI_D2 | ++-------+-------------------+ +| 13 | P0.23 / QSPI_D3 | ++-------+-------------------+ +| 14 | P0.24 | ++-------+-------------------+ +| 15 | P0.25 | ++-------+-------------------+ +| 16 | P1.00 / TRACED[0] | ++-------+-------------------+ +| 17 | P1.09 / TRACED[3] | ++-------+-------------------+ +| 18 | No connection | ++-------+-------------------+ + +Arduino Headers +--------------- + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | D7 | P1.08 | ++-------+--------------+-------------------------+ +| 2 | D6 | P1.07 | ++-------+--------------+-------------------------+ +| 3 | N/C | N/A | ++-------+--------------+-------------------------+ +| 4 | N/C | N/A | ++-------+--------------+-------------------------+ +| 5 | N/C | N/A | ++-------+--------------+-------------------------+ +| 6 | D2 | P1.03 | ++-------+--------------+-------------------------+ +| 7 | N/C | N/A | ++-------+--------------+-------------------------+ +| 8 | D0 (RX) | P1.01 | ++-------+--------------+-------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P1.15 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P1.14 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P1.13 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P1.12 | ++-------+--------------+-------------------------+ +| 9 | D9 | P1.11 | ++-------+--------------+-------------------------+ +| 10 | D8 | P1.10 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-345 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.15 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.13 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Applications for the BMD-345-EVAL board +configurations can be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` +for more details); however, the standard debugging targets +are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BMD-345-EVAL +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd345eval/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-345-EVAL +***************************************************************** + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found +in +:zephyr_file:`boards/ublox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your + application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is + used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app +main directory to be picked up automatically by the device tree +compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the BMD-345 at the `u-blox website`_, Section 2 +'Pin definition'. In the table 3 select the pins marked 'GPIO'. +Note that pins marked as 'Standard drive, low frequency I/O only +(<10 kH' can only be used in under-10KHz applications. +They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module + pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-34-series-open-cpu diff --git a/boards/arm/ubx_bmd340eval_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_bmd345eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd340eval_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd345eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.dts rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.dts diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.yaml b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml similarity index 89% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.yaml rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml index 7d8201f2093e06..fa53f794f09fa0 100644 --- a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd345eval_nrf52840 +identifier: ubx_bmd345eval/nrf52840 name: BMD-345-EVAL type: mcu arch: arm diff --git a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840_defconfig b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840_defconfig similarity index 79% rename from boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840_defconfig rename to boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840_defconfig index 97872745a6df3a..71e6c0a6d60de1 100644 --- a/boards/arm/ubx_bmd345eval_nrf52840/ubx_bmd345eval_nrf52840_defconfig +++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_BMD345EVAL_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig b/boards/u-blox/ubx_bmd360eval/Kconfig new file mode 100644 index 00000000000000..89f886d08e43c3 --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/Kconfig @@ -0,0 +1,15 @@ +# BMD-360-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD360EVAL + +# BT_CTLR depends on BT. When BT is enabled we should default to also +# enabling the controller. +config BT_CTLR + default y if BT diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd360eval/Kconfig.defconfig new file mode 100644 index 00000000000000..eb35b4bb15213f --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/Kconfig.defconfig @@ -0,0 +1,8 @@ +# BMD-360-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD360EVAL + +endif # BOARD_UBX_BMD360EVAL diff --git a/boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval b/boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval new file mode 100644 index 00000000000000..6661cadd9faa5c --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/Kconfig.ubx_bmd360eval @@ -0,0 +1,7 @@ +# BMD-360-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD360EVAL + select SOC_NRF52811_QFAA diff --git a/boards/arm/ubx_bmd360eval_nrf52811/board.cmake b/boards/u-blox/ubx_bmd360eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/board.cmake rename to boards/u-blox/ubx_bmd360eval/board.cmake diff --git a/boards/u-blox/ubx_bmd360eval/board.yml b/boards/u-blox/ubx_bmd360eval/board.yml new file mode 100644 index 00000000000000..a06d24dd008178 --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd360eval + vendor: u-blox + socs: + - name: nrf52811 diff --git a/boards/arm/ubx_bmd360eval_nrf52811/doc/img/BMD-30-33-35-36-EVAL.jpg b/boards/u-blox/ubx_bmd360eval/doc/img/BMD-30-33-35-36-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/doc/img/BMD-30-33-35-36-EVAL.jpg rename to boards/u-blox/ubx_bmd360eval/doc/img/BMD-30-33-35-36-EVAL.jpg diff --git a/boards/arm/ubx_bmd360eval_nrf52811/doc/img/bmd-300-eval_pin_out.jpg b/boards/u-blox/ubx_bmd360eval/doc/img/bmd-300-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/doc/img/bmd-300-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd360eval/doc/img/bmd-300-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd360eval/doc/index.rst b/boards/u-blox/ubx_bmd360eval/doc/index.rst new file mode 100644 index 00000000000000..9ce29132c131ff --- /dev/null +++ b/boards/u-blox/ubx_bmd360eval/doc/index.rst @@ -0,0 +1,386 @@ +.. _ubx_bmd360eval_nrf52811: + +u-blox EVK-BMD-360: BMD-360-EVAL +################################ + +Overview +******** + +The BMD-360-EVAL hardware provides support for the +u-blox BMD-360 Bluetooth 5 module, based on The +Nordic Semiconductor nRF52811 ARM Cortex-M4 CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-30-33-35-36-EVAL.jpg + :align: center + :alt: BMD-300-EVAL + + BMD-300-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-360-EVAL shares the same pin headers and assignments as the + BMD-300-EVAL. The BMD-300-EVAL is shown here. + +More information about the BMD-360-EVAL and the BMD-360 module +can be found at the `u-blox website`_. + +Hardware +******** + +The BMD-360 on the BMD-360-EVAL contains an internal +high-frequency oscillator at 32MHz. There is also a low frequency +(slow) oscillator of 32.768kHz. The BMD-360 itself does not include +the slow crystal; however, the BMD-360-EVAL does. + +.. note:: + When targeting a custom design without a slow crystal, + be sure to modify code to utilize the internal RC + oscillator for the slow clock. + +Supported Features +================== + +The BMD-360-EVAL configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of +BMD-360-EVAL hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.17 +* LED2 (red) = P0.18 +* LED3 (green) = P0.19 +* LED4 (green) = P0.20 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.13 +* BUTTON2 = SW2 = P0.14 +* BUTTON3 = SW3 = P0.15 +* BUTTON4 = SW4 = P0.16 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-300-eval_pin_out.jpg + :align: center + :alt: BMD-300-EVAL pin-out + + BMD-300-EVAL pin-out (Credit: u-blox AG) + +.. note:: + The BMD-360-EVAL shares the same pin headers and assignments + as the BMD-300-EVAL. The BMD-300-EVAL is shown here. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-360-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 | ++-------+----------------+ +| 2 | P0.09 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.21 / RESET | ++-------+----------------+ +| 8 | P0.01 / XL2 | ++-------+----------------+ +| 9 | P0.00 / XL1 | ++-------+----------------+ +| 10 | GND | ++-------+----------------+ + + +Arduino Headers +--------------- + + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.21 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+----------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+============================+ +| 1 | D7 | P0.18 | ++-------+--------------+----------------------------+ +| 2 | D6 | P0.17 | ++-------+--------------+----------------------------+ +| 3 | D5 | P0.16 | ++-------+--------------+----------------------------+ +| 4 | D4 | P0.15 | ++-------+--------------+----------------------------+ +| 5 | D3 | P0.14 | ++-------+--------------+----------------------------+ +| 6 | D2 | P0.13 | ++-------+--------------+----------------------------+ +| 7 | D1 (TX) | P0.12 | ++-------+--------------+----------------------------+ +| 8 | D0 (RX) | P0.11 | ++-------+--------------+----------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P0.22 | ++-------+--------------+-------------------------+ +| 9 | D9 | P0.20 | ++-------+--------------+-------------------------+ +| 10 | D8 | P0.19 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-360 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.24 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.25 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.23 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the +BMD-360-EVAL can be found. For example, under Linux, +:code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd360eval/nrf52811 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-360-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is +running correctly on your board. The button and LED definitions +can be found in :zephyr_file:`boards/ublox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts`. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/bmd-360-open-cpu diff --git a/boards/arm/ubx_bmd345eval_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_bmd360eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd345eval_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd360eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811-pinctrl.dtsi b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811-pinctrl.dtsi rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.dts b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.dts rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.dts diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.yaml b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml similarity index 88% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.yaml rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml index 3da084eb1ac474..4df9c1172f0137 100644 --- a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811.yaml +++ b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd360eval_nrf52811 +identifier: ubx_bmd360eval/nrf52811 name: UBX_BMD360EVAL_NRF52811 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811_defconfig b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811_defconfig similarity index 79% rename from boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811_defconfig rename to boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811_defconfig index 6cc16653c7419f..b2f60844ace0a7 100644 --- a/boards/arm/ubx_bmd360eval_nrf52811/ubx_bmd360eval_nrf52811_defconfig +++ b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52811_QFAA=y -CONFIG_BOARD_UBX_BMD360EVAL_NRF52811=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig b/boards/u-blox/ubx_bmd380eval/Kconfig new file mode 100644 index 00000000000000..def5144ceef543 --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/Kconfig @@ -0,0 +1,10 @@ +# BMD-380-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_BMD380EVAL diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig b/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig new file mode 100644 index 00000000000000..58afb83796fcd3 --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/Kconfig.defconfig @@ -0,0 +1,11 @@ +# BMD-380-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_BMD380EVAL + +config BT_CTLR + default BT + +endif # BOARD_UBX_BMD380EVAL diff --git a/boards/u-blox/ubx_bmd380eval/Kconfig.ubx_bmd380eval b/boards/u-blox/ubx_bmd380eval/Kconfig.ubx_bmd380eval new file mode 100644 index 00000000000000..a6c9334537956b --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/Kconfig.ubx_bmd380eval @@ -0,0 +1,10 @@ +# BMD-380-EVAL board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_BMD380EVAL + select SOC_NRF52840_QIAA + +# should be CKAA, +# but SOC file not yet available from Nordic Semiconductor diff --git a/boards/arm/ubx_bmd380eval_nrf52840/board.cmake b/boards/u-blox/ubx_bmd380eval/board.cmake similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/board.cmake rename to boards/u-blox/ubx_bmd380eval/board.cmake diff --git a/boards/u-blox/ubx_bmd380eval/board.yml b/boards/u-blox/ubx_bmd380eval/board.yml new file mode 100644 index 00000000000000..0f7ec7263e7b90 --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_bmd380eval + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg b/boards/u-blox/ubx_bmd380eval/doc/img/BMD-34-38-EVAL.jpg similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/doc/img/BMD-34-38-EVAL.jpg rename to boards/u-blox/ubx_bmd380eval/doc/img/BMD-34-38-EVAL.jpg diff --git a/boards/arm/ubx_bmd380eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg b/boards/u-blox/ubx_bmd380eval/doc/img/bmd-340-eval_pin_out.jpg similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/doc/img/bmd-340-eval_pin_out.jpg rename to boards/u-blox/ubx_bmd380eval/doc/img/bmd-340-eval_pin_out.jpg diff --git a/boards/u-blox/ubx_bmd380eval/doc/index.rst b/boards/u-blox/ubx_bmd380eval/doc/index.rst new file mode 100644 index 00000000000000..1c89222536e9fd --- /dev/null +++ b/boards/u-blox/ubx_bmd380eval/doc/index.rst @@ -0,0 +1,518 @@ +.. _ubx_bmd380eval_nrf52840: + +u-blox EVK-BMD-34/48: BMD-380-EVAL +################################## + +Overview +******** + +The BMD-380-EVAL hardware provides support for the +u-blox BMD-380 Bluetooth 5.0 module, based on The +Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/BMD-34-38-EVAL.jpg + :align: center + :alt: BMD-340-EVAL + + BMD-340-EVAL (Credit: u-blox AG) + +.. note:: + The BMD-380-EVAL shares the same pin headers and assignments as the + BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. + See the pin tables below for the exceptions. + +More information about the BMD-340-EVAL and the BMD-340 module +can be found at the `u-blox website`_. All of the Nordic Semiconductor +examples for the nRF52840 DK (nrf52840dk_nrf52840) may be used without +modification. + +Hardware +******** + +The BMD-380 on the BMD-380-EVAL contains an internal high-frequency +oscillator at 32MHz. There is also a low frequency (slow) oscillator +of 32.768kHz. The BMD-380 itself does not include the slow crystal; +however, the BMD-380-eval does. + +.. note:: + + When targeting a custom design without a slow crystal, be sure + to modify code to utilize the internal RC oscillator for the + slow clock. + +Supported Features +================== + +The BMD-380-EVAL board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of BMD-380-EVAL +hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED1 (red) = P0.13 +* LED2 (red) = P0.14 +* LED3 (green) = P0.15 +* LED4 (green) = P0.16 +* D5 (red) = OB LED 1 +* D6 (green) = OB LED 2 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.11 +* BUTTON2 = SW2 = P0.12 +* BUTTON3 = SW3 = P0.24 +* BUTTON4 = SW4 = P0.25 +* BOOT = SW5 = boot/reset + +External Connectors +------------------- + +.. figure:: img/bmd-340-eval_pin_out.jpg + :align: center + :alt: BMD-340-EVAL pin-out + +.. note:: + The BMD-380-EVAL shares the same pin headers and assignments as the + BMD-340-EVAL with four exceptions. The BMD-340-EVAL is shown here. + See the pin tables below for the exceptions. + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the BMD-380-EVAL + for each header + +J-Link Prog Connector (J2) + ++-------+--------------+ +| PIN # | Signal Name | ++=======+==============+ +| 1 | VDD | ++-------+--------------+ +| 2 | IMCU_TMSS | ++-------+--------------+ +| 3 | GND | ++-------+--------------+ +| 4 | IMCU_TCKS | ++-------+--------------+ +| 5 | V5V | ++-------+--------------+ +| 6 | IMCU_TDOS | ++-------+--------------+ +| 7 | Cut off | ++-------+--------------+ +| 8 | IMCU_TDIS | ++-------+--------------+ +| 9 | Cut off | ++-------+--------------+ +| 10 | IMCU_RESET | ++-------+--------------+ + +Debug OUT (J3) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | EXT_VTG | ++-------+----------------+ +| 2 | EXT_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | EXT_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | EXT_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | EXT_GND_DETECT | ++-------+----------------+ +| 10 | EXT_RESET | ++-------+----------------+ + +Debug IN (J26) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | BMD-340_VCC | ++-------+----------------+ +| 2 | BMD-340_SWDIO | ++-------+----------------+ +| 3 | GND | ++-------+----------------+ +| 4 | BMD-340_SWDCLK | ++-------+----------------+ +| 5 | GND | ++-------+----------------+ +| 6 | BMD-340_SWO | ++-------+----------------+ +| 7 | N/C | ++-------+----------------+ +| 8 | N/C | ++-------+----------------+ +| 9 | GND | ++-------+----------------+ +| 10 | BMD-340_RESET | ++-------+----------------+ + +Auxiliary (J9) + ++-------+----------------+ +| PIN # | Signal Name | ++=======+================+ +| 1 | P0.10 / NFC2 | ++-------+----------------+ +| 2 | P0.09 / NFC1 | ++-------+----------------+ +| 3 | P0.08 | ++-------+----------------+ +| 4 | P0.07 | ++-------+----------------+ +| 5 | P0.06 | ++-------+----------------+ +| 6 | P0.05 / AIN3 | ++-------+----------------+ +| 7 | P0.01 / XL2 | ++-------+----------------+ +| 8 | P0.00 / XL1 | ++-------+----------------+ + +Auxiliary (J10) + ++-------+-------------------+ +| PIN # | Signal Name | ++=======+===================+ +| 1 | P0.11 / TRACED[2] | ++-------+-------------------+ +| 2 | P0.12 / TRACED[1] | ++-------+-------------------+ +| 3 | P0.13 | ++-------+-------------------+ +| 4 | P0.14 | ++-------+-------------------+ +| 5 | P0.15 | ++-------+-------------------+ +| 6 | P0.16 | ++-------+-------------------+ +| 7 | P0.17 / QSPI_CS | ++-------+-------------------+ +| 8 | P0.18 / RESET | ++-------+-------------------+ +| 9 | P0.19 / QSPI_CLK | ++-------+-------------------+ +| 10 | P0.20 / QSPI_D0 | ++-------+-------------------+ +| 11 | P0.21 / QSPI_D1 | ++-------+-------------------+ +| 12 | P0.22 / QSPI_D2 | ++-------+-------------------+ +| 13 | P0.23 / QSPI_D3 | ++-------+-------------------+ +| 14 | P0.24 | ++-------+-------------------+ +| 15 | P0.25 | ++-------+-------------------+ +| 16 | P1.00 / TRACED[0] | ++-------+-------------------+ +| 17 | P1.09 / TRACED[3] | ++-------+-------------------+ +| 18 | No connection | ++-------+-------------------+ + +Power (J5) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 2 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | VSHLD | N/A | ++-------+--------------+-------------------------+ +| 5 | V5V | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ + +Analog in (J8) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.29 / AIN5 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.31 / AIN7 | ++-------+--------------+-------------------------+ + +Digital I/O (J7) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | D7 | P1.08 | ++-------+--------------+-------------------------+ +| 2 | - | No connection | ++-------+--------------+-------------------------+ +| 3 | D5 | P1.06 | ++-------+--------------+-------------------------+ +| 4 | D4 | No connection | ++-------+--------------+-------------------------+ +| 5 | - | No connection | ++-------+--------------+-------------------------+ +| 6 | - | No connection | ++-------+--------------+-------------------------+ +| 7 | D1 (TX) | P1.02 | ++-------+--------------+-------------------------+ +| 8 | - | No connection | ++-------+--------------+-------------------------+ + +Digital I/O (J6) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | SCL | P0.27 | ++-------+--------------+-------------------------+ +| 2 | SDA | P0.26 | ++-------+--------------+-------------------------+ +| 3 | AREF | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 4 | GND | N/A | ++-------+--------------+-------------------------+ +| 5 | D13 (SCK) | P1.15 | ++-------+--------------+-------------------------+ +| 6 | D12 (MISO) | P1.14 | ++-------+--------------+-------------------------+ +| 7 | D11 (MOSI) | P1.13 | ++-------+--------------+-------------------------+ +| 8 | D10 (SS) | P1.12 | ++-------+--------------+-------------------------+ +| 9 | D9 | P1.11 | ++-------+--------------+-------------------------+ +| 10 | D8 | P1.10 | ++-------+--------------+-------------------------+ + +J11 + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | BMD-380 Functions | ++=======+==============+=========================+ +| 1 | D12 (MISO) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | V5V | N/A | ++-------+--------------+-------------------------+ +| 3 | D13 (SCK) | P0.15 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.13 | ++-------+--------------+-------------------------+ +| 5 | RESET | N/A | ++-------+--------------+-------------------------+ +| 6 | N/A | N/A | ++-------+--------------+-------------------------+ + +Programming and Debugging +************************* + +Applications for the BMD-380-EVAL board configurations can +be built and flashed in the usual way +(see :ref:`build_an_application` and :ref:`application_run` +for more details); however, the standard debugging targets +are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the BMD-380-EVAL +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_bmd380eval/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the BMD-380-EVAL +************************************************ + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your + application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is + used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app +main directory to be picked up automatically by the device tree +compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the BMD-380 at the `u-blox website`_, Section 2 +'Pin definition'. In the table 3 select the pins marked 'GPIO'. +Note that pins marked as 'Standard drive, low frequency I/O only +(<10 kH' can only be used in under-10KHz applications. +They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module + pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/docs/UBX-19039467 diff --git a/boards/arm/ubx_bmd360eval_nrf52811/pre_dt_board.cmake b/boards/u-blox/ubx_bmd380eval/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd360eval_nrf52811/pre_dt_board.cmake rename to boards/u-blox/ubx_bmd380eval/pre_dt_board.cmake diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.dts rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.dts diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.yaml b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml similarity index 88% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.yaml rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml index afd074165c1c0d..15bb236585d4e0 100644 --- a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840.yaml +++ b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_bmd380eval_nrf52840 +identifier: ubx_bmd380eval/nrf52840 name: UBX_BMD380EVAL_NRF52840 type: mcu arch: arm diff --git a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840_defconfig b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840_defconfig similarity index 82% rename from boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840_defconfig rename to boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840_defconfig index 79826cc9974251..7d36d059a41afa 100644 --- a/boards/arm/ubx_bmd380eval_nrf52840/ubx_bmd380eval_nrf52840_defconfig +++ b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840_defconfig @@ -3,10 +3,7 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y # should be CKAA, but not available yet from Nordic Semiconductor -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_BMD380EVAL_NRF52840=y # Enable hardware stack protection CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/u-blox/ubx_evkannab1/Kconfig b/boards/u-blox/ubx_evkannab1/Kconfig new file mode 100644 index 00000000000000..cba82a1d0b28b4 --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/Kconfig @@ -0,0 +1,10 @@ +# u-blox EVK-ANNA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKANNAB1 diff --git a/boards/u-blox/ubx_evkannab1/Kconfig.defconfig b/boards/u-blox/ubx_evkannab1/Kconfig.defconfig new file mode 100644 index 00000000000000..e12e7d4ebaccd5 --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/Kconfig.defconfig @@ -0,0 +1,11 @@ +# u-blox EVK-ANNA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKANNAB1 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKANNAB1 diff --git a/boards/u-blox/ubx_evkannab1/Kconfig.ubx_evkannab1 b/boards/u-blox/ubx_evkannab1/Kconfig.ubx_evkannab1 new file mode 100644 index 00000000000000..cb43df23647f83 --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/Kconfig.ubx_evkannab1 @@ -0,0 +1,7 @@ +# u-blox EVK-ANNA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKANNAB1 + select SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkannab1_nrf52832/board.cmake b/boards/u-blox/ubx_evkannab1/board.cmake similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/board.cmake rename to boards/u-blox/ubx_evkannab1/board.cmake diff --git a/boards/u-blox/ubx_evkannab1/board.yml b/boards/u-blox/ubx_evkannab1/board.yml new file mode 100644 index 00000000000000..3aeac881aba6f2 --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkannab1 + vendor: u-blox + socs: + - name: nrf52832 diff --git a/boards/arm/ubx_evkannab1_nrf52832/doc/img/EVK-ANNA-B112.jpg b/boards/u-blox/ubx_evkannab1/doc/img/EVK-ANNA-B112.jpg similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/doc/img/EVK-ANNA-B112.jpg rename to boards/u-blox/ubx_evkannab1/doc/img/EVK-ANNA-B112.jpg diff --git a/boards/u-blox/ubx_evkannab1/doc/index.rst b/boards/u-blox/ubx_evkannab1/doc/index.rst new file mode 100644 index 00000000000000..88ed4f5511359d --- /dev/null +++ b/boards/u-blox/ubx_evkannab1/doc/index.rst @@ -0,0 +1,169 @@ +.. _ubx_evkannab1_nrf52832: + +u-blox EVK-ANNA-B11x +#################### + +Overview +******** + +The u-blox ANNA-B1 Evaluation Kit hardware is a Bluetooth low energy +module based on the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU +and has support for the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-ANNA-B112.jpg + + EVK ANNA-B1 + +More information about the ANNA-B1 module and the EVK-ANNA-B1 +can be found at `ANNA-B1 product page`_ and +`EVK-ANNA-B1 product page`_. + +Supported Features +================== + +The ubx_evkannab1_nrf52832 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth Low Energy | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `EVK-ANNA-B1 product page`_ and `ANNA-B1 Data Sheet`_ +for a complete list of EVK ANNA-B1 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.27 +* LED1 (green) = P0.25 +* LED2 (blue) = P0.26 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.25 +* BUTTON2 = SW2 = P0.24 + +General information on module pin numbering +------------------------------------------- + +The numbering of the pins on the module and EVK do not follow the GPIO +numbering on the nRF52832 SoC. Please see the `ANNA-B1 Data Sheet`_ for +information on how to map ANNA-B1 pins to the pin numbering on the +nRF52832 SoC. + +The reason for this is the u-blox module family concept where different +modules share the same pinout and can be interchanged. + +Programming and Debugging +************************* + +Applications for the ``ubx_evkannab1/nrf52832`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Build and flash applications as usual (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Open a terminal program to the USB Serial Port installed when connecting +the board and listen for output. + +Settings: 115200, 8N1, no flow control. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkannab1/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging boards +containing a Nordic Semiconductor chip with a Segger IC. + + +Testing the LEDs and buttons in the EVK NINA-B11x +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) +and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts`. + +Note that the buttons on the EVK-ANNA-B1 are marked SW1 and SW2, which +are named sw0 and sw1 in the dts file. +Also note that the SW1 button and the green LED are connected on HW level. + + +References +********** + +.. target-notes:: + +.. _ANNA-B1 product page: https://www.u-blox.com/en/product/anna-b112-open-cpu +.. _EVK-ANNA-B1 product page: https://www.u-blox.com/en/product/evk-anna-b112 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _ANNA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-18011707 diff --git a/boards/arm/ubx_bmd380eval_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_evkannab1/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_bmd380eval_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_evkannab1/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832-pinctrl.dtsi b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832-pinctrl.dtsi rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.dts b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.dts rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.dts diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.yaml b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml similarity index 88% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.yaml rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml index 39de6903d449f3..54af92298d8f53 100644 --- a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832.yaml +++ b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkannab1_nrf52832 +identifier: ubx_evkannab1/nrf52832 name: UBX-EVKANNAB1-NRF52832 type: mcu arch: arm diff --git a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832_defconfig b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832_defconfig similarity index 79% rename from boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832_defconfig rename to boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832_defconfig index 95f9f59739f9e8..5b7bfe0d28c2da 100644 --- a/boards/arm/ubx_evkannab1_nrf52832/ubx_evkannab1_nrf52832_defconfig +++ b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_UBX_EVKANNAB1_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_evkninab1/Kconfig b/boards/u-blox/ubx_evkninab1/Kconfig new file mode 100644 index 00000000000000..280d583f721798 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/Kconfig @@ -0,0 +1,10 @@ +# u-blox EVK NINA-B1 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKNINAB1 diff --git a/boards/u-blox/ubx_evkninab1/Kconfig.defconfig b/boards/u-blox/ubx_evkninab1/Kconfig.defconfig new file mode 100644 index 00000000000000..5f897eb6bb1b74 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/Kconfig.defconfig @@ -0,0 +1,11 @@ +# u-blox EVK-NINA-B1 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKNINAB1 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKNINAB1 diff --git a/boards/u-blox/ubx_evkninab1/Kconfig.ubx_evkninab1 b/boards/u-blox/ubx_evkninab1/Kconfig.ubx_evkninab1 new file mode 100644 index 00000000000000..b221d0a7d22330 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/Kconfig.ubx_evkninab1 @@ -0,0 +1,7 @@ +# u-blox EVK-NINA-B1 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKNINAB1 + select SOC_NRF52832_QFAA diff --git a/boards/arm/ubx_evkninab1_nrf52832/board.cmake b/boards/u-blox/ubx_evkninab1/board.cmake similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/board.cmake rename to boards/u-blox/ubx_evkninab1/board.cmake diff --git a/boards/u-blox/ubx_evkninab1/board.yml b/boards/u-blox/ubx_evkninab1/board.yml new file mode 100644 index 00000000000000..3073c5833d24ab --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkninab1 + vendor: u-blox + socs: + - name: nrf52832 diff --git a/boards/arm/ubx_evkninab1_nrf52832/doc/img/EVK-NINA-B1.jpg b/boards/u-blox/ubx_evkninab1/doc/img/EVK-NINA-B1.jpg similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/doc/img/EVK-NINA-B1.jpg rename to boards/u-blox/ubx_evkninab1/doc/img/EVK-NINA-B1.jpg diff --git a/boards/u-blox/ubx_evkninab1/doc/index.rst b/boards/u-blox/ubx_evkninab1/doc/index.rst new file mode 100644 index 00000000000000..9b296624ad8f40 --- /dev/null +++ b/boards/u-blox/ubx_evkninab1/doc/index.rst @@ -0,0 +1,178 @@ +.. _ubx_evkninab1_nrf52832: + +u-blox EVK NINA-B11x +#################### + +Overview +******** + +The u-blox NINA-B1 Evaluation Kit hardware is a Bluetooth +low energy module based on the Nordic Semiconductor nRF52832 +ARM Cortex-M4F CPU and has support for the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-NINA-B1.jpg + + EVK NINA-B1 + +More information about the NINA-B1 module and the EVK NINA-B1 +can be found at `NINA-B1 product page`_ and +`EVK-NINA-B1 product page`_. + +Supported Features +================== + +The ubx_evkninab1/nrf52832 board configuration supports the +following hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth Low Energy | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +.. note:: + Most Arduino interfaces are supported. Arduino pins + D5 and D8 are not available, so arduino_gpio is + disabled. On the EVK-NINA-B1, these pins are + assigned to SWDIO and SWDCLK, respectively. + +Other hardware features have not been enabled yet for this board. +See `EVK-NINA-B1 product page`_ and `NINA-B1 Data Sheet`_ +for a complete list of EVK NINA-B1 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.08 +* LED1 (green) = P0.16 +* LED2 (blue) = P0.18 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.16 +* BUTTON2 = SW2 = P0.30 + + +General information on module pin numbering +------------------------------------------- + +The numbering of the pins on the module and EVK do not follow the GPIO +numbering on the nRF52832 SoC. Please see the `NINA-B1 Data Sheet`_ for +information on how to map NINA-B1 pins to the pin numbering on the +nRF52832 SoC. + +The reason for this is the u-blox module family concept where different +modules share the same pinout and can be interchanged, see +`NINA module family Nested design`_. + +Programming and Debugging +************************* + +Applications for the ``ubx_evkninab1/nrf52832`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Build and flash applications as usual (see +:ref:`build_an_application` and :ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +Open a terminal program to the USB Serial Port installed when connecting +the board and listen for output. + +Settings: 115200, 8N1, no flow control. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkninab1/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging boards +containing a Nordic Semiconductor chip with a Segger IC. + + +Testing the LEDs and buttons in the EVK NINA-B11x +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) +and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts`. + +Note that the buttons on the EVK-NINA-B1 are marked SW1 and SW2, which +are named sw0 and sw1 in the dts file. +Also note that the SW1 button and the green LED are connected on HW level. + + +References +********** + +.. target-notes:: + +.. _NINA-B1 product page: https://www.u-blox.com/en/product/nina-b1-series-open-cpu +.. _EVK-NINA-B1 product page: https://www.u-blox.com/en/product/evk-nina-b1 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _NINA-B1 Data Sheet: https://www.u-blox.com/en/docs/UBX-15019243 +.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ubx_evkannab1_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_evkninab1/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkannab1_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_evkninab1/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832-pinctrl.dtsi b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832-pinctrl.dtsi rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832-pinctrl.dtsi diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.dts b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.dts rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.dts diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.yaml b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml similarity index 87% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.yaml rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml index 125efd94a1c19d..286e66b97cbad7 100644 --- a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832.yaml +++ b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkninab1_nrf52832 +identifier: ubx_evkninab1/nrf52832 name: UBX-EVKNINAB1-NRF52832 type: mcu arch: arm diff --git a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832_defconfig b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832_defconfig similarity index 79% rename from boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832_defconfig rename to boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832_defconfig index c23f9eb78331f3..9696c89e3d73f9 100644 --- a/boards/arm/ubx_evkninab1_nrf52832/ubx_evkninab1_nrf52832_defconfig +++ b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_QFAA=y -CONFIG_BOARD_UBX_EVKNINAB1_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_evkninab3/Kconfig b/boards/u-blox/ubx_evkninab3/Kconfig new file mode 100644 index 00000000000000..acf0948c5d5c9c --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/Kconfig @@ -0,0 +1,10 @@ +# EVK-NINA-B3 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKNINAB3 diff --git a/boards/u-blox/ubx_evkninab3/Kconfig.defconfig b/boards/u-blox/ubx_evkninab3/Kconfig.defconfig new file mode 100644 index 00000000000000..2579b835428384 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/Kconfig.defconfig @@ -0,0 +1,11 @@ +# EVK-NINA-B3 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKNINAB3 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKNINAB3 diff --git a/boards/u-blox/ubx_evkninab3/Kconfig.ubx_evkninab3 b/boards/u-blox/ubx_evkninab3/Kconfig.ubx_evkninab3 new file mode 100644 index 00000000000000..a978020479452c --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/Kconfig.ubx_evkninab3 @@ -0,0 +1,7 @@ +# EVK-NINA-B3 board configuration + +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKNINAB3 + select SOC_NRF52840_QIAA diff --git a/boards/arm/ubx_evkninab3_nrf52840/board.cmake b/boards/u-blox/ubx_evkninab3/board.cmake similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/board.cmake rename to boards/u-blox/ubx_evkninab3/board.cmake diff --git a/boards/u-blox/ubx_evkninab3/board.yml b/boards/u-blox/ubx_evkninab3/board.yml new file mode 100644 index 00000000000000..3914fd281495c0 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkninab3 + vendor: u-blox + socs: + - name: nrf52840 diff --git a/boards/arm/ubx_evkninab3_nrf52840/doc/img/EVK-NINA-B3.jpg b/boards/u-blox/ubx_evkninab3/doc/img/EVK-NINA-B3.jpg similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/doc/img/EVK-NINA-B3.jpg rename to boards/u-blox/ubx_evkninab3/doc/img/EVK-NINA-B3.jpg diff --git a/boards/u-blox/ubx_evkninab3/doc/index.rst b/boards/u-blox/ubx_evkninab3/doc/index.rst new file mode 100644 index 00000000000000..941c58eccd0933 --- /dev/null +++ b/boards/u-blox/ubx_evkninab3/doc/index.rst @@ -0,0 +1,328 @@ +.. _ubx_ninab3_nrf52840: + +u-blox EVK-NINA-B3 +################## + +Overview +******** + +The u-blox EVK-NINA-B30 Development Kit hardware provides support for the +u-blox NINA-B30x Bluetooth 5.0 module, based on the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-NINA-B3.jpg + :align: center + :alt: EVK-NINA-B3 + + EVK-NINA-B3 (Credit: u-blox AG) + +More information about the EVK-NINA-B3 and the NINA-B30x modules +can be found at the `u-blox website`_. + +Hardware +******** + +The NINA-B30x on the EVK-NINA-B30x contains an internal high-frequency +oscillator at 32MHz as well as a low frequency (slow) oscillator +of 32.768kHz. + + +Supported Features +================== + +The ubx_evkninab3/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | IEEE 802.15.4 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See the `u-blox website`_ for a complete list of EVK-NINA-B30x +hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.13 +* LED1 (green) = P0.25 +* LED2 (blue) = P1.00 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.25 +* BUTTON2 = SW2 = P0.2 +* BOOT = SW0 = boot/reset + +External Connectors +------------------- + +.. note:: + The pin numbers noted below are referenced to + the pin 1 markings on the EVK-NINA-B30x + for each header + + +Arduino Headers +--------------- + +Power (J1) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 1 | N/C | N/A | ++-------+--------------+-------------------------+ +| 2 | VDD_IO | N/A | ++-------+--------------+-------------------------+ +| 3 | RESET | P0.18 / RESET | ++-------+--------------+-------------------------+ +| 4 | 3V3 | N/A | ++-------+--------------+-------------------------+ +| 5 | 5V0 | N/A | ++-------+--------------+-------------------------+ +| 6 | GND | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 8 | VIN | N/A | ++-------+--------------+-------------------------+ + +Analog in (J2) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 1 | A0 | P0.04 / AIN2 | ++-------+--------------+-------------------------+ +| 2 | A1 | P0.30 / AIN6 | ++-------+--------------+-------------------------+ +| 3 | A2 | P0.05 / AIN3 | ++-------+--------------+-------------------------+ +| 4 | A3 | P0.02 / AIN0 | ++-------+--------------+-------------------------+ +| 5 | A4 | P0.28 / AIN4 | ++-------+--------------+-------------------------+ +| 6 | A5 | P0.03 / AIN1 | ++-------+--------------+-------------------------+ + +Digital I/O (J3) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 8 | D7 | P0.10 | ++-------+--------------+-------------------------+ +| 7 | D6 | P0.09 | ++-------+--------------+-------------------------+ +| 6 | D5 | P0.11 | ++-------+--------------+-------------------------+ +| 5 | D4 | P0.13 | ++-------+--------------+-------------------------+ +| 4 | D3 | P0.31 | ++-------+--------------+-------------------------+ +| 3 | D2 | P1.12 | ++-------+--------------+-------------------------+ +| 2 | D1 (TX) | P1.13 | ++-------+--------------+-------------------------+ +| 1 | D0 (RX) | P0.29 | ++-------+--------------+-------------------------+ + +Digital I/O (J4) + ++-------+--------------+-------------------------+ +| PIN # | Signal Name | NINA-B30x Functions | ++=======+==============+=========================+ +| 10 | SCL | P0.24 | ++-------+--------------+-------------------------+ +| 9 | SDA | P0.16 | ++-------+--------------+-------------------------+ +| 8 | N/C | N/A | ++-------+--------------+-------------------------+ +| 7 | GND | N/A | ++-------+--------------+-------------------------+ +| 6 | D13 (SCK) | P0.07 | ++-------+--------------+-------------------------+ +| 5 | D12 (MISO) | P1.00 | ++-------+--------------+-------------------------+ +| 4 | D11 (MOSI) | P0.15 | ++-------+--------------+-------------------------+ +| 3 | D10 (SS) | P0.14 | ++-------+--------------+-------------------------+ +| 2 | D9 | P0.12 | ++-------+--------------+-------------------------+ +| 1 | D8 | P1.09 | ++-------+--------------+-------------------------+ + + +Programming and Debugging +************************* + +Applications for the ``ubx_evkninab3/nrf52840`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the EVK-NINA-B30x +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkninab3/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging +u-blox boards with a Segger J-LINK-OB IC. + + +Testing the LEDs and buttons in the EVK-NINA-B30x +************************************************* + +There are 2 samples that allow you to test that the buttons +(switches) and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts`. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app main directory to be +picked up automatically by the device tree compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the NINA-B3 at `u-blox website`_, Section 3 'Pin definition'. +In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' +can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module pad number. + +References +********** + +.. target-notes:: + +.. _u-blox website: https://www.u-blox.com/en/product/nina-b3-series-open-cpu diff --git a/boards/arm/ubx_evkninab1_nrf52832/pre_dt_board.cmake b/boards/u-blox/ubx_evkninab3/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkninab1_nrf52832/pre_dt_board.cmake rename to boards/u-blox/ubx_evkninab3/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840-pinctrl.dtsi b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840-pinctrl.dtsi rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840-pinctrl.dtsi diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.dts rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.dts diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.yaml b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml similarity index 89% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.yaml rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml index 34590896e55f87..90d292bc049e83 100644 --- a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840.yaml +++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkninab3_nrf52840 +identifier: ubx_evkninab3/nrf52840 name: UBX-EVKNINAB3-NRF52840 type: mcu arch: arm diff --git a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840_defconfig b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840_defconfig similarity index 79% rename from boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840_defconfig rename to boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840_defconfig index 9ccc843efb0eae..aec93a8b1bc883 100644 --- a/boards/arm/ubx_evkninab3_nrf52840/ubx_evkninab3_nrf52840_defconfig +++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_UBX_EVKNINAB3_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/u-blox/ubx_evkninab4/Kconfig b/boards/u-blox/ubx_evkninab4/Kconfig new file mode 100644 index 00000000000000..b9ef2c7aea6e0e --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/Kconfig @@ -0,0 +1,10 @@ +# NINA-B4 EVK board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_UBX_EVKNINAB4 diff --git a/boards/u-blox/ubx_evkninab4/Kconfig.defconfig b/boards/u-blox/ubx_evkninab4/Kconfig.defconfig new file mode 100644 index 00000000000000..c9e958708bfbfc --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/Kconfig.defconfig @@ -0,0 +1,11 @@ +# EVK-NINA-B4 board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UBX_EVKNINAB4 + +config BT_CTLR + default BT + +endif # BOARD_UBX_EVKNINAB4 diff --git a/boards/u-blox/ubx_evkninab4/Kconfig.ubx_evkninab4 b/boards/u-blox/ubx_evkninab4/Kconfig.ubx_evkninab4 new file mode 100644 index 00000000000000..f93b20c48dccef --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/Kconfig.ubx_evkninab4 @@ -0,0 +1,7 @@ +# NINA-B4 EVK board configuration +# +# Copyright (c) 2021 u-blox AG +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UBX_EVKNINAB4 + select SOC_NRF52833_QIAA diff --git a/boards/arm/ubx_evkninab4_nrf52833/board.cmake b/boards/u-blox/ubx_evkninab4/board.cmake similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/board.cmake rename to boards/u-blox/ubx_evkninab4/board.cmake diff --git a/boards/u-blox/ubx_evkninab4/board.yml b/boards/u-blox/ubx_evkninab4/board.yml new file mode 100644 index 00000000000000..787ae9c4cdfe57 --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/board.yml @@ -0,0 +1,5 @@ +board: + name: ubx_evkninab4 + vendor: u-blox + socs: + - name: nrf52833 diff --git a/boards/arm/ubx_evkninab4_nrf52833/doc/img/EVK-NINA-B406_Top_web.jpg b/boards/u-blox/ubx_evkninab4/doc/img/EVK-NINA-B406_Top_web.jpg similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/doc/img/EVK-NINA-B406_Top_web.jpg rename to boards/u-blox/ubx_evkninab4/doc/img/EVK-NINA-B406_Top_web.jpg diff --git a/boards/u-blox/ubx_evkninab4/doc/index.rst b/boards/u-blox/ubx_evkninab4/doc/index.rst new file mode 100644 index 00000000000000..872b778b7e30ac --- /dev/null +++ b/boards/u-blox/ubx_evkninab4/doc/index.rst @@ -0,0 +1,230 @@ +.. _ubx_ninab4_nrf52833: + +u-blox EVK NINA-B40x +#################### + +Overview +******** + +The u-blox NINA-B4 Evaluation Kit hardware is a Bluetooth low energy +module based on the Nordic Semiconductor nRF52833 ARM Cortex-M4F CPU +and has support for the following features: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`USB (Universal Serial Bus)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/EVK-NINA-B406_Top_web.jpg + + EVK NINA-B4 + +More information about the NINA-B4 module and the EVK-NINA-B4 can be +found at `NINA-B40 product page`_ and `EVK-NINA-B4 product page`_. + +Supported Features +================== + +The ubx_evkninab4/nrf52833 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth low energy | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| USB | on-chip | usb | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features have not been enabled yet for this board. +See `EVK-NINA-B4 product page`_ and `NINA-B40 Data Sheet`_ +for a complete list of EVK NINA-B4 hardware features. + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.13 +* LED1 (green) = P1.01 +* LED2 (blue) = P1.00 + +Push buttons +------------ + +* BUTTON1 = SW1 = P1.01 (Shared with green LED) +* BUTTON2 = SW2 = P0.02 + +General information on module pin numbering +------------------------------------------- + +The numbering of the pins on the module and EVK do not follow the GPIO +numbering on the nRF52833 SoC. Please see the `NINA-B40 Data Sheet`_ for +information on how to map NINA-B40 pins to the pin numbering on the +nRF52833 SoC. + +The reason for this is the u-blox module family concept where different +modules share the same pinout and can be interchanged, see +`NINA module family Nested design`_. + +Programming and Debugging +************************* + +Applications for the ``ubx_evkninab4/nrf52833`` board configuration can be +built and flashed in the usual way (see :ref:`build_an_application` +and :ref:`application_run` for more details); however, the standard +debugging targets are not currently available. + +Flashing +======== + +Build and flash applications as usual (see +:ref:`build_an_application` and :ref:`application_run` for more details) + +Here is an example for the :ref:`hello_world` application. + +Open a terminal program to the USB Serial Port installed when connecting +the board and listen for output. + +Settings: 115200, 8N1, no flow control. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: ubx_evkninab4/nrf52833 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging boards +containing a Nordic Semiconductor chip with a Segger IC. + + +Testing the LEDs and buttons in the EVK NINA-B40x +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) +and LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running +correctly on your board. The button and LED definitions can be found in +:zephyr_file:`boards/ublox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts`. + +Note that the buttons on the EVK-NINA-B4 are marked SW1 and SW2, which +are named sw0 and sw1 in the dts file. +Also note that the SW1 button and the green LED are connected on HW level. + +Using UART1 +*********** + +The following approach can be used when an application needs to use +more than one UART for connecting peripheral devices: + +1. Add device tree overlay file to the main directory of your application: + + .. code-block:: devicetree + + &pinctrl { + uart1_default: uart1_default { + group1 { + psels = , + ; + }; + }; + /* required if CONFIG_PM_DEVICE=y */ + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + }; + + &uart1 { + compatible = "nordic,nrf-uarte"; + current-speed = <115200>; + status = "okay"; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; + }; + + In the overlay file above, pin P0.16 is used for RX and P0.14 is used for TX + +2. Use the UART1 as ``DEVICE_DT_GET(DT_NODELABEL(uart1))`` + +Overlay file naming +=================== + +The file has to be named ``.overlay`` and placed in the app main directory to be +picked up automatically by the device tree compiler. + +Selecting the pins +================== + +Pins can be configured in the board pinctrl file. To see the available mappings, +open the data sheet for the NINA-B4 at `NINA-B40 Data Sheet`_, Section 3 'Pin definition'. +In the table 7 select the pins marked 'GPIO_xx'. Note that pins marked as 'Radio sensitive pin' +can only be used in under-10KHz applications. They are not suitable for 115200 speed of UART. + +.. note: + Pins are defined according to the "nRF52" pin number, not the module pad number. + + +References +********** + +.. target-notes:: + +.. _NINA-B40 product page: https://www.u-blox.com/en/product/nina-b40-series-open-cpu +.. _EVK-NINA-B4 product page: https://www.u-blox.com/en/product/evk-nina-b4 +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _NINA-B40 Data Sheet: https://www.u-blox.com/en/docs/UBX-19049405 +.. _NINA module family Nested design: https://www.u-blox.com/en/docs/UBX-17065600 diff --git a/boards/arm/ubx_evkninab3_nrf52840/pre_dt_board.cmake b/boards/u-blox/ubx_evkninab4/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkninab3_nrf52840/pre_dt_board.cmake rename to boards/u-blox/ubx_evkninab4/pre_dt_board.cmake diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833-pinctrl.dtsi b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833-pinctrl.dtsi similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833-pinctrl.dtsi rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833-pinctrl.dtsi diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.dts rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.dts diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.yaml b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml similarity index 87% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.yaml rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml index 4134fe918c8210..f7f8cb355a93d0 100644 --- a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833.yaml +++ b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml @@ -1,4 +1,4 @@ -identifier: ubx_evkninab4_nrf52833 +identifier: ubx_evkninab4/nrf52833 name: EVK-NINA-B4-NRF52833 type: mcu arch: arm diff --git a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833_defconfig b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833_defconfig similarity index 79% rename from boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833_defconfig rename to boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833_defconfig index 80995445718d82..b1318ad37dc18e 100644 --- a/boards/arm/ubx_evkninab4_nrf52833/ubx_evkninab4_nrf52833_defconfig +++ b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833_defconfig @@ -3,10 +3,6 @@ # Copyright (c) 2021 u-blox AG # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52833_QIAA=y -CONFIG_BOARD_UBX_EVKNINAB4_NRF52833=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/udoo/index.rst b/boards/udoo/index.rst new file mode 100644 index 00000000000000..aac4e7f711af75 --- /dev/null +++ b/boards/udoo/index.rst @@ -0,0 +1,10 @@ +.. _boards-udoo: + +UDOO +#### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/udoo/udoo_neo_full/Kconfig.udoo_neo_full b/boards/udoo/udoo_neo_full/Kconfig.udoo_neo_full new file mode 100644 index 00000000000000..e0e9d50bd17739 --- /dev/null +++ b/boards/udoo/udoo_neo_full/Kconfig.udoo_neo_full @@ -0,0 +1,6 @@ +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UDOO_NEO_FULL + select SOC_PART_NUMBER_MCIMX6X4EVM10AB + select SOC_MCIMX6X_M4 if BOARD_UDOO_NEO_FULL_MCIMX6X_M4 diff --git a/boards/arm/udoo_neo_full_m4/board.cmake b/boards/udoo/udoo_neo_full/board.cmake similarity index 100% rename from boards/arm/udoo_neo_full_m4/board.cmake rename to boards/udoo/udoo_neo_full/board.cmake diff --git a/boards/udoo/udoo_neo_full/board.yml b/boards/udoo/udoo_neo_full/board.yml new file mode 100644 index 00000000000000..1c20ebdc15f951 --- /dev/null +++ b/boards/udoo/udoo_neo_full/board.yml @@ -0,0 +1,5 @@ +board: + name: udoo_neo_full + vendor: udoo + socs: + - name: mcimx6x diff --git a/boards/udoo/udoo_neo_full/doc/index.rst b/boards/udoo/udoo_neo_full/doc/index.rst new file mode 100644 index 00000000000000..945c1dcee4af01 --- /dev/null +++ b/boards/udoo/udoo_neo_full/doc/index.rst @@ -0,0 +1,368 @@ +.. _udoo_neo_full: + +UDOO Neo Full +############# + +Overview +******** + +UDOO Neo Full is an open source Arduino Uno compatible single board computer. +It is equipped with an NXP |reg| i.MX 6SoloX hybrid multicore processor +composed of one ARM |reg| Cortex-A9 core running up to 1 GHz and one Cortex-M4 +core running up to 227 MHz for high CPU performance and real-time response. +Zephyr was ported to run on the Cortex-M4 core only. In a future release, it +will also communicate with the Cortex-A9 core (running Linux) via OpenAMP. + +.. figure:: udoo_neo_full_mcimx6x_m4.jpg + :align: center + :alt: UDOO-Neo-Full + + UDOO Neo Full (Credit: udoo.org) + +Hardware +******** + +- MCIMX6X MCU with a single Cortex-A9 (1 GHz) core and single Cortex-M4 (227 MHz) core + +- Memory + + - 1 GB RAM + - 128 KB OCRAM + - 256 KB L2 cache (can be switched into OCRAM instead) + - 16 KB OCRAM_S + - 32 KB TCML + - 32 KB TCMU + - 32 KB CAAM (secure RAM) + +- A9 Boot Devices + + - NOR flash + - NAND flash + - OneNAND flash + - SD/MMC + - Serial (I2C/SPI) NOR flash and EEPROM + - QuadSPI (QSPI) flash + +- Display + + - Micro HDMI connector + - LVDS display connector + - Touch (I2C signals) + +- Multimedia + + - Integrated 2d/3d graphics controller + - 8-bit parallel interface for analog camera supporting NTSC and PAL + - HDMI audio transmitter + - S/PDIF + - I2S + +- Connectivity + + - USB 2.0 Type A port + - USB OTG (micro-AB connector) + - 10/100 Mbit/s Ethernet PHY + - Wi-Fi 802.11 b/g/n + - Bluetooth 4.0 Low Energy + - 3x UART ports + - 2x CAN Bus interfaces + - 8x PWM signals + - 3x I2C interface + - 1x SPI interface + - 6x multiplexable signals + - 32x GPIO (A9) + - 22x GPIO (M4) + +- Other + + - MicroSD card slot (8-bit SDIO interface) + - Power status LED (green) + - 2x user LED (red and orange) + +- Power + + - 5 V DC Micro USB + - 6-15 V DC jack + - RTC battery connector + +- Debug + + - pads for soldering of JTAG 14-pin connector + +- Sensor + + - 3-Axis Accelerometer + - 3-Axis Magnetometer + - 3-Axis Digital Gyroscope + - 1x Sensor Snap-In I2C connector + +- Expansion port + + - Arduino interface + +For more information about the MCIMX6X SoC and UDOO Neo Full board, +see these references: + +- `NXP i.MX 6SoloX Website`_ +- `NXP i.MX 6SoloX Datasheet`_ +- `NXP i.MX 6SoloX Reference Manual`_ +- `UDOO Neo Website`_ +- `UDOO Neo Getting Started`_ +- `UDOO Neo Documentation`_ +- `UDOO Neo Datasheet`_ +- `UDOO Neo Schematics`_ + +Supported Features +================== + +The UDOO Neo Full board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | general purpose input/output | ++-----------+------------+-------------------------------------+ +| COUNTER | on-chip | counter | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The UDOO Neo Full board was tested with the following pinmux +controller configuration. + ++---------------+-----------------+---------------------------+ +| Board Name | SoC Name | Usage | ++===============+=================+===========================+ +| J4 RX | UART5_RX_DATA | UART Console | ++---------------+-----------------+---------------------------+ +| J4 TX | UART5_TX_DATA | UART Console | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The MCIMX6X SoC is configured to use the 24 MHz external oscillator +on the board with the on-chip PLL to generate core clock. +PLL settings for M4 core are set via code running on the A9 core. + +Serial Port +=========== + +The MCIMX6X SoC has six UARTs. UART5 is configured for the M4 core and the +remaining are used by the A9 core or not used. + +Programming and Debugging +************************* + +The M4 core does not have a flash memory and is not provided a clock +at power-on-reset. Therefore it needs to be started by the A9 core. +The A9 core is responsible to load the M4 binary application into the RAM, +put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get +the M4 out of reset. The A9 can perform these steps at the bootloader level +or after the Linux system has booted. + +The M4 core can use up to 5 different RAMs (some other types of memory like +a secure RAM are not currently implemented in Zephyr). +These are the memory mappings for A9 and M4: + ++------------+-----------------------+-----------------------+-----------------------+ +| Region | Cortex-A9 | Cortex-M4 | Size | ++============+=======================+=======================+=======================+ +| TCML | 0x007F8000-0x007FFFFF | 0x1FFF8000-0x1FFFFFFF | 32 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| TCMU | 0x00800000-0x00807FFF | 0x20000000-0x20007FFF | 32 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| OCRAM_S | 0x008F8000-0x008FBFFF | 0x208F8000-0x208FBFFF | 16 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| OCRAM | 0x00900000-0x0091FFFF | 0x20900000-0x2091FFFF | 128 KB | ++------------+-----------------------+-----------------------+-----------------------+ +| DDR | 0x80000000-0xFFFFFFFF | 0x80000000-0xDFFFFFFF | 2048 MB (1536 for M4) | ++------------+-----------------------+-----------------------+-----------------------+ + +References +========== + +- `NXP i.MX 6SoloX Reference Manual`_ Chapter 2 - Memory Maps + +You have to choose which RAM will be used at compilation time. This configuration +is done in the file :zephyr_file:`boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts`. + +If you want to have the code placed in the subregion of a memory, which will +likely be the case when using DDR, select "zephyr,flash=&flash" and set the +DT_FLASH_SIZE macro to determine the region size and DT_FLASH_ADDR to determine +the address where the region begins. + +If you want to have the data placed in the subregion of a memory, which will +likely be the case when using DDR, select "zephyr,sram = &sram", which sets the +CONFIG_SRAM_SIZE macro to determine the region size and +CONFIG_SRAM_BASE_ADDRESS to determine the address where the region begins. + +Otherwise set "zephyr,flash" and/or "zephyr,sram" to one of the predefined +regions: + +.. code-block:: none + + "zephyr,flash" + - &tcml + - &ocram_s + - &ocram + - &ddr + + "zephyr,sram" + - &tcmu + - &ocram_s + - &ocram + - &ddr + +Below you will find the instructions how a Linux user space application running +on the A9 core can be used to load and run Zephyr application on the M4 core. + +The UDOOBuntu Linux distribution contains a `udooneo-m4uploader`_ utility, +but its purpose is to load UDOO Neo "Arduino-like" sketches, so it doesn't +work with Zephyr applications in most cases. The reason is that there is +an exchange of information between this utility and the program running on the +M4 core using hardcoded shared memory locations. The utility writes a flag which +is read by the program running on the M4 core. The program is then supposed to +end safely and write the status to the shared memory location for the main core. +The utility then loads the new application and reads its status from the shared +memory location to determine if it has successfully launched. Since this +functionality is specific for the UDOO Neo "Arduino-like" sketches, it is not +implemented in Zephyr. However Zephyr applications can support it on their own +if planned to be used along with the UDOOBuntu Linux running on the A9 core. +The udooneo-uploader utility calls another executable named +mqx_upload_on_m4SoloX which can be called directly to load Zephyr applications. +Copy the Zephyr binary image into the Linux filesystem and invoke the utility +as a root user: + +.. code-block:: console + + mqx_upload_on_m4SoloX zephyr.bin + +If the output looks like below, the mqx_upload_on_m4SoloX could not read +the status of the stopped application. This is expected if the previously +loaded application is not a UDOO Neo "Arduino-like" sketch and ignores the +shared memory communication: + +.. code-block:: console + + UDOONeo - mqx_upload_on_m4SoloX 1.1.0 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Stop, m4TraceFlags: 00000000 + UDOONeo - Failed to Stop M4 sketch: reboot system ! + +In such situation, the mqx_upload_on_m4SoloX utility has reset the trace flags, +so it will succeed when called again. Then it can have this output below: + +.. code-block:: console + + UDOONeo - mqx_upload_on_m4SoloX 1.1.0 + UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 + UDOONeo - start - end (0x84000000 - 0x84080000) + UDOONeo - Waiting M4 Run, m4TraceFlags: 000001E0 + UDOONeo - M4 sketch is running + +Or the one below, if the utility cannot read the status flag that the M4 core +applications has started. It can be ignored as the application should be +running, the utility just doesn't know it: + +.. code-block:: console + + UDOONeo - mqx_upload_on_m4SoloX 1.1.0 + UDOONeo - FILENAME = zephyr.bin; loadaddr = 0x84000000 + UDOONeo - start - end (0x84000000 - 0x84080000) + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Waiting M4 Run, m4TraceFlags: 00000000 + UDOONeo - Failed to Start M4 sketch: reboot system ! + +The stack pointer and the program counter values are read from the binary. +The memory address where binary will be placed is calculated from the program +counter as its value aligned to 64 KB down, or it can be provided as a second +command line argument: + +.. code-block:: console + + mqx_upload_on_m4SoloX zephyr.bin 0x84000000 + +It is necessary to provide the address if the binary is copied into a memory +region which has different mapping between the A9 and the M4 core. The address +calculated from the stack pointer value in the binary file would be wrong. + +It is possible to modify the mqx_upload_on_m4SoloX utility source code +to not exchange the information with the M4 core application using shared +memory. + +It is also possible to use the `imx-m4fwloader`_ utility to load the M4 core +application. + +One option applicable in UDOOBuntu Linux is to copy the binary file into the +file /var/opt/m4/m4last.fw in the Linux filesystem. The next time the system is +booted, Das U-Boot will load it from there. + +Another option is to directly use Das U-Boot to load the code. + +Debugging +========= + +The UDOO Neo Full board includes pads for soldering the 14-pin JTAG +connector. Zephyr applications running on the M4 core have only been +tested by observing UART console output. + +References +========== + +.. target-notes:: + +.. _UDOO Neo Website: + https://www.udoo.org/udoo-neo/ + +.. _UDOO Neo Getting Started: + https://www.udoo.org/get-started-neo/ + +.. _UDOO Neo Documentation: + https://www.udoo.org/docs-neo + +.. _UDOO Neo Datasheet: + https://www.udoo.org/download/files/datasheets/datasheet_udoo_neo.pdf + +.. _UDOO Neo Schematics: + https://www.udoo.org/download/files/schematics/UDOO_NEO_schematics.pdf + +.. _Udoo Neo Linux or Android Images for the A9 Core: + https://www.udoo.org/downloads/ + +.. _udooneo-m4uploader: + https://github.com/ektor5/udooneo-m4uploader + +.. _imx-m4fwloader: + https://github.com/codeauroraforum/imx-m4fwloader + +.. _NXP i.MX 6SoloX Website: + https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6solox-processors-heterogeneous-processing-with-arm-cortex-a9-and-cortex-m4-cores:i.MX6SX + +.. _NXP i.MX 6SoloX Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMX6SXCEC.pdf + +.. _NXP i.MX 6SoloX Reference Manual: + https://www.nxp.com/docs/en/reference-manual/IMX6SXRM.pdf + +.. _Loading Code on Cortex-M4 from Linux for the i.MX 6SoloX and i.MX 7Dual/7Solo Application Processors: + https://www.nxp.com/docs/en/application-note/AN5317.pdf diff --git a/boards/arm/udoo_neo_full_m4/doc/udoo_neo_full_m4.jpg b/boards/udoo/udoo_neo_full/doc/udoo_neo_full_mcimx6x_m4.jpg similarity index 100% rename from boards/arm/udoo_neo_full_m4/doc/udoo_neo_full_m4.jpg rename to boards/udoo/udoo_neo_full/doc/udoo_neo_full_mcimx6x_m4.jpg diff --git a/boards/arm/udoo_neo_full_m4/udoo_neo_full_m4-pinctrl.dtsi b/boards/udoo/udoo_neo_full/udoo_neo_full-pinctrl.dtsi similarity index 100% rename from boards/arm/udoo_neo_full_m4/udoo_neo_full_m4-pinctrl.dtsi rename to boards/udoo/udoo_neo_full/udoo_neo_full-pinctrl.dtsi diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts new file mode 100644 index 00000000000000..f54b88102cdc9c --- /dev/null +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.dts @@ -0,0 +1,84 @@ +/* + * Copyright 2018,2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +/* + * Determines the address and size for code memory which will be applied + * when "zephyr,flash = &flash". Use this to select a custom region, + * usually within DDR. + */ +#define DT_FLASH_SIZE DT_SIZE_K(512) +#define DT_FLASH_ADDR 84000000 /* DT_ADDR will add leading 0x where needed */ + +/* + * Determines the address and size for data memory which will be applied + * when "zephyr,sram = &sram". Use this to select a custom region, + * usually within DDR. + */ +#define DT_SRAM_SIZE DT_SIZE_K(128) +#define DT_SRAM_ADDR 84080000 /* DT_ADDR will add leading 0x where needed */ + +#include +#include "udoo_neo_full-pinctrl.dtsi" + +/ { + model = "UDOO Neo Full board"; + compatible = "nxp,mcmcimx6x_m4"; + + aliases { + led0 = &red_led; + }; + + chosen { + zephyr,flash = &flash; + zephyr,sram = &tcmu; + zephyr,console = &uart5; + zephyr,shell-uart = &uart5; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + gpios = <&gpio4 6 0>; + label = "User LD1"; + }; + }; +}; + +&uart5 { + status = "okay"; + current-speed = <115200>; + modem-mode = <0>; + pinctrl-0 = <&uart5_default>; + pinctrl-names = "default"; +}; + +&gpio4 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&gpio6 { + status = "okay"; +}; + +&mub { + status = "okay"; +}; + +&epit1 { + status = "okay"; +}; + +&epit2 { + status = "okay"; +}; diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml new file mode 100644 index 00000000000000..4fdd64933092ac --- /dev/null +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml @@ -0,0 +1,21 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: udoo_neo_full/mcimx6x/m4 +name: UDOO Neo Full +type: mcu +arch: arm +ram: 32 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - counter + - gpio + - uart +vendor: nxp diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig new file mode 100644 index 00000000000000..140679e50c3f51 --- /dev/null +++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig @@ -0,0 +1,13 @@ +# +# Copyright (c) 2018, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=227000000 +CONFIG_PINCTRL=y diff --git a/boards/up/index.rst b/boards/up/index.rst new file mode 100644 index 00000000000000..e9397ae50108e7 --- /dev/null +++ b/boards/up/index.rst @@ -0,0 +1,10 @@ +.. _boards-up: + +UP Bridge the Gap. +################## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/up/up_squared/CMakeLists.txt b/boards/up/up_squared/CMakeLists.txt new file mode 100644 index 00000000000000..ddfd93807ffd18 --- /dev/null +++ b/boards/up/up_squared/CMakeLists.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation + +zephyr_include_directories(.) + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/up/up_squared/Kconfig.defconfig b/boards/up/up_squared/Kconfig.defconfig new file mode 100644 index 00000000000000..78d041976f1abc --- /dev/null +++ b/boards/up/up_squared/Kconfig.defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation + +if BOARD_UP_SQUARED + +config MP_MAX_NUM_CPUS + default 2 if BOARD_UP_SQUARED + +config BUILD_OUTPUT_STRIPPED + default y + +# TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1593600000 if APIC_TSC_DEADLINE_TIMER + default 1593600000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +endif # BOARD_UP_SQUARED diff --git a/boards/up/up_squared/Kconfig.up_squared b/boards/up/up_squared/Kconfig.up_squared new file mode 100644 index 00000000000000..b6a1427cec71e9 --- /dev/null +++ b/boards/up/up_squared/Kconfig.up_squared @@ -0,0 +1,5 @@ +# Copyright (c) 2018-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UP_SQUARED + select SOC_APOLLO_LAKE diff --git a/boards/up/up_squared/board.cmake b/boards/up/up_squared/board.cmake new file mode 100644 index 00000000000000..896bd4967f0498 --- /dev/null +++ b/boards/up/up_squared/board.cmake @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation + +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) diff --git a/boards/x86/up_squared/board.h b/boards/up/up_squared/board.h similarity index 100% rename from boards/x86/up_squared/board.h rename to boards/up/up_squared/board.h diff --git a/boards/up/up_squared/board.yml b/boards/up/up_squared/board.yml new file mode 100644 index 00000000000000..0955b6967af10e --- /dev/null +++ b/boards/up/up_squared/board.yml @@ -0,0 +1,4 @@ +board: + name: up_squared + socs: + - name: apollo_lake diff --git a/boards/x86/up_squared/doc/img/up_squared.jpg b/boards/up/up_squared/doc/img/up_squared.jpg similarity index 100% rename from boards/x86/up_squared/doc/img/up_squared.jpg rename to boards/up/up_squared/doc/img/up_squared.jpg diff --git a/boards/up/up_squared/doc/index.rst b/boards/up/up_squared/doc/index.rst new file mode 100644 index 00000000000000..62166f2ef38034 --- /dev/null +++ b/boards/up/up_squared/doc/index.rst @@ -0,0 +1,125 @@ +.. _up_squared: + +UP Squared +########## + +Overview +******** + +UP |sup2| (UP Squared) is an ultra compact single board computer with high +performance and low power consumption. It features the latest Intel |reg| Apollo +Lake Celeron |trade| and Pentium |trade| Processors with only 4W of Scenario Design Power and +a powerful and flexible Intel |reg| FPGA Altera MAX 10 onboard. + +.. figure:: img/up_squared.jpg + :align: center + :alt: UP Squared + + Up Squared (Credit: https://up-board.org) + +This board configuration enables kernel support for the `UP Squared`_ board. + +.. note:: + This board configuration works on all three variants of `UP Squared`_ + boards containing Intel |reg| Pentium |trade| SoC, + Intel |reg| Celeron |trade| SoC, or Intel |reg| Atom |trade| SoC. + +Hardware +******** + +General information about the board can be found at the `UP Squared`_ website. + +.. include:: ../../../../soc/intel/apollo_lake/doc/supported_features.txt + +GPIO +---- + +GPIOs are exposed through the HAT header, and can be referred using +predefined macros such as ``UP2_HAT_PIN3``. The physical pins are +connected to the on-board FPGA acting as level shifter. Therefore, +to actually utilize these GPIO pins, the function of the pins and +directions (input/output) must be set in the BIOS. This can be +accomplished in BIOS, under menu ``Advanced``, and option +``HAT Configurations``. When a corresponding pin is set to act as +GPIO, there is an option to set the direction of the pin. This needs +to be set accordingly for the GPIO to function properly. + +Connections and IOs +=================== + +Refer to the `UP Squared`_ website and `UP Squared Pinout`_ website +for connection diagrams. + +Programming and Debugging +************************* + +Use the following procedures for booting an image on a UP Squared board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application on UP Squared: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: up_squared + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +Booting the UP Squared Board using UEFI +======================================= + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. note:: + Refer to the `UP Squared Serial Console Wiki page + `_ for instructions on how to + connect serial console. + +.. note:: + You can safely ignore this message if it appears: + + .. code-block:: console + + WARNING: no console will be available to OS + +Booting the UP Squared Board over network +========================================= + +.. include:: ../../../intel/common/net_boot.rst + :start-after: start_include_here + +.. note:: + Refer to the `UP Squared Serial Console Wiki page + `_ for instructions on how to + connect serial console. + +.. note:: + To enable PXE boot for Up Squared board do the following: + + #. Enable network from BIOS settings. + + .. code-block:: console + + Advanced -> Network Stack Configuration -> Enable Network Stack -> Enable Ipv4 PXE Support + + #. Make network boot as the first boot option. + + .. code-block:: console + + Boot -> Boot Option #1 : [Network] + +.. _UP Squared: https://www.up-board.org/upsquared/specifications + +.. _UP Squared Pinout: https://wiki.up-community.org/Pinout diff --git a/boards/x86/up_squared/up_squared.dts b/boards/up/up_squared/up_squared.dts similarity index 100% rename from boards/x86/up_squared/up_squared.dts rename to boards/up/up_squared/up_squared.dts diff --git a/boards/x86/up_squared/up_squared.yaml b/boards/up/up_squared/up_squared.yaml similarity index 100% rename from boards/x86/up_squared/up_squared.yaml rename to boards/up/up_squared/up_squared.yaml diff --git a/boards/x86/up_squared/up_squared_defconfig b/boards/up/up_squared/up_squared_defconfig similarity index 83% rename from boards/x86/up_squared/up_squared_defconfig rename to boards/up/up_squared/up_squared_defconfig index d76a6404fab686..608e32cdef02b2 100644 --- a/boards/x86/up_squared/up_squared_defconfig +++ b/boards/up/up_squared/up_squared_defconfig @@ -1,7 +1,6 @@ # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Intel Corporation -CONFIG_SOC_APOLLO_LAKE=y -CONFIG_BOARD_UP_SQUARED=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/up/up_squared_pro_7000/CMakeLists.txt b/boards/up/up_squared_pro_7000/CMakeLists.txt new file mode 100644 index 00000000000000..36ddcdf9d1392b --- /dev/null +++ b/boards/up/up_squared_pro_7000/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/up/up_squared_pro_7000/Kconfig.defconfig b/boards/up/up_squared_pro_7000/Kconfig.defconfig new file mode 100644 index 00000000000000..84744a7ea3af41 --- /dev/null +++ b/boards/up/up_squared_pro_7000/Kconfig.defconfig @@ -0,0 +1,64 @@ +# Copyright (c) 2023-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_UP_SQUARED_PRO_7000 + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1900000000 if APIC_TSC_DEADLINE_TIMER + default 1900000000 if APIC_TIMER_TSC + default 19200000 + +if APIC_TIMER + +config APIC_TIMER_IRQ + default 24 +config APIC_TIMER_TSC_M + default 3 +config APIC_TIMER_TSC_N + default 249 +endif + +config ACPI + default y + +if ACPI + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 +config MAIN_STACK_SIZE + default 320000 + +if SHELL + +config SHELL_STACK_SIZE + default 320000 +endif # SHELL +endif # ACPI + +if DMA + +config DMA_64BIT + default y + +config DMA_DW_HW_LLI + default n + +config DMA_DW_CHANNEL_COUNT + default 2 + +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y + +config HAS_COVERAGE_SUPPORT + default y + +endif # BOARD_UP_SQUARED_PRO_7000 diff --git a/boards/up/up_squared_pro_7000/Kconfig.up_squared_pro_7000 b/boards/up/up_squared_pro_7000/Kconfig.up_squared_pro_7000 new file mode 100644 index 00000000000000..035cc0f888d148 --- /dev/null +++ b/boards/up/up_squared_pro_7000/Kconfig.up_squared_pro_7000 @@ -0,0 +1,5 @@ +# Copyright (c) 2018-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_UP_SQUARED_PRO_7000 + select SOC_ALDER_LAKE diff --git a/boards/x86/up_squared/board.cmake b/boards/up/up_squared_pro_7000/board.cmake similarity index 100% rename from boards/x86/up_squared/board.cmake rename to boards/up/up_squared_pro_7000/board.cmake diff --git a/boards/up/up_squared_pro_7000/board.yml b/boards/up/up_squared_pro_7000/board.yml new file mode 100644 index 00000000000000..b929cca9967d19 --- /dev/null +++ b/boards/up/up_squared_pro_7000/board.yml @@ -0,0 +1,4 @@ +board: + name: up_squared_pro_7000 + socs: + - name: alder_lake diff --git a/boards/x86/intel_adl/doc/up_squared_pro_7000.rst b/boards/up/up_squared_pro_7000/doc/up_squared_pro_7000.rst similarity index 95% rename from boards/x86/intel_adl/doc/up_squared_pro_7000.rst rename to boards/up/up_squared_pro_7000/doc/up_squared_pro_7000.rst index 762340e10495a8..1b2d6bace7bce3 100644 --- a/boards/x86/intel_adl/doc/up_squared_pro_7000.rst +++ b/boards/up/up_squared_pro_7000/doc/up_squared_pro_7000.rst @@ -66,13 +66,13 @@ connection setup. Booting the UP Squared Pro 7000 Board using UEFI ================================================ -.. include:: ../../common/efi_boot.rst +.. include:: ../../../intel/common/efi_boot.rst :start-after: start_include_here Booting the UP Squared Pro 7000 Board over network ================================================== -.. include:: ../../common/net_boot.rst +.. include:: ../../../intel/common/net_boot.rst :start-after: start_include_here References diff --git a/boards/x86/intel_adl/up_squared_pro_7000.dts b/boards/up/up_squared_pro_7000/up_squared_pro_7000.dts similarity index 87% rename from boards/x86/intel_adl/up_squared_pro_7000.dts rename to boards/up/up_squared_pro_7000/up_squared_pro_7000.dts index 06d6f8e2330757..2b155e22adea0f 100644 --- a/boards/x86/intel_adl/up_squared_pro_7000.dts +++ b/boards/up/up_squared_pro_7000/up_squared_pro_7000.dts @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include "intel_adl.dts" +#include "../../intel/adl/intel_adl.dts" / { model = "UP Squared Pro 7000 board"; diff --git a/boards/x86/intel_adl/up_squared_pro_7000.yaml b/boards/up/up_squared_pro_7000/up_squared_pro_7000.yaml similarity index 100% rename from boards/x86/intel_adl/up_squared_pro_7000.yaml rename to boards/up/up_squared_pro_7000/up_squared_pro_7000.yaml diff --git a/boards/x86/intel_adl/up_squared_pro_7000_defconfig b/boards/up/up_squared_pro_7000/up_squared_pro_7000_defconfig similarity index 79% rename from boards/x86/intel_adl/up_squared_pro_7000_defconfig rename to boards/up/up_squared_pro_7000/up_squared_pro_7000_defconfig index 4c228677a70c53..fb9be2a4994a30 100644 --- a/boards/x86/intel_adl/up_squared_pro_7000_defconfig +++ b/boards/up/up_squared_pro_7000/up_squared_pro_7000_defconfig @@ -1,7 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_ALDER_LAKE=y -CONFIG_BOARD_UP_SQUARED_PRO_7000=y CONFIG_PIC_DISABLE=y CONFIG_LOAPIC=y CONFIG_CONSOLE=y diff --git a/boards/vcc-gnd/index.rst b/boards/vcc-gnd/index.rst new file mode 100644 index 00000000000000..5a70a862cb9faf --- /dev/null +++ b/boards/vcc-gnd/index.rst @@ -0,0 +1,10 @@ +.. _boards-vcc-gnd: + +VCC-GND +####### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/vcc-gnd/yd_esp32/Kconfig b/boards/vcc-gnd/yd_esp32/Kconfig new file mode 100644 index 00000000000000..901933061242cb --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_YD_ESP32 + select SOC_ESP32_PROCPU if BOARD_YD_ESP32_ESP32_PROCPU + select SOC_ESP32_APPCPU if BOARD_YD_ESP32_ESP32_APPCPU diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.defconfig b/boards/vcc-gnd/yd_esp32/Kconfig.defconfig new file mode 100644 index 00000000000000..9b7b408dbef2dd --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig.defconfig @@ -0,0 +1,26 @@ +# YD-ESP32 board configuration + +# Copyright (c) 2023 Julio Cesar +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_YD_ESP32_ESP32_PROCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 65535 if WIFI && BT + default 51200 if WIFI + default 40960 if BT + default 4096 + +choice BT_HCI_BUS_TYPE + default BT_ESP32 if BT +endchoice + +endif # BOARD_YD_ESP32_ESP32_PROCPU + +if BOARD_YD_ESP32_ESP32_APPCPU + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + default 256 + +endif # BOARD_YD_ESP32_ESP32_PROCPU diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.sysbuild b/boards/vcc-gnd/yd_esp32/Kconfig.sysbuild new file mode 100644 index 00000000000000..3a2d17ac5cfd06 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig.sysbuild @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +choice BOOTLOADER + default BOOTLOADER_MCUBOOT +endchoice + +choice BOOT_SIGNATURE_TYPE + default BOOT_SIGNATURE_TYPE_NONE +endchoice diff --git a/boards/vcc-gnd/yd_esp32/Kconfig.yd_esp32 b/boards/vcc-gnd/yd_esp32/Kconfig.yd_esp32 new file mode 100644 index 00000000000000..981d728d09f961 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/Kconfig.yd_esp32 @@ -0,0 +1,7 @@ +# YD-ESP32 board configuration + +# Copyright (c) 2023 Julio Cesar +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_YD_ESP32 + select SOC_ESP32_WROOM_32UE_N4 diff --git a/boards/xtensa/xiao_esp32s3/board.cmake b/boards/vcc-gnd/yd_esp32/board.cmake similarity index 100% rename from boards/xtensa/xiao_esp32s3/board.cmake rename to boards/vcc-gnd/yd_esp32/board.cmake diff --git a/boards/vcc-gnd/yd_esp32/board.yml b/boards/vcc-gnd/yd_esp32/board.yml new file mode 100644 index 00000000000000..a930386ed8448c --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/board.yml @@ -0,0 +1,5 @@ +board: + name: yd_esp32 + vendor: vcc-gnd + socs: + - name: esp32 diff --git a/boards/xtensa/yd_esp32/doc/img/yd_esp32.png b/boards/vcc-gnd/yd_esp32/doc/img/yd_esp32.png similarity index 100% rename from boards/xtensa/yd_esp32/doc/img/yd_esp32.png rename to boards/vcc-gnd/yd_esp32/doc/img/yd_esp32.png diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst new file mode 100644 index 00000000000000..e69f7d07704509 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/doc/index.rst @@ -0,0 +1,310 @@ +.. _yd_esp32: + +YD-ESP32 +######## + +Overview +******** + +The YD-ESP32 development board is one of VCC-GND® Studio’s official boards. +This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core. + +.. figure:: img/yd_esp32.png + :align: center + :alt: YD-ESP32 + + YD-ESP32 DevKit with ESP32-WROOM-32E Module + +ESP32 +===== + +ESP32 is a series of low cost, low power system on a chip microcontrollers +with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a +Tensilica Xtensa LX6 microprocessor in both dual-core and single-core +variations. ESP32 is created and developed by Espressif Systems, a +Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm +process. [1]_ + +The features include the following: + +- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz +- 520KB of SRAM +- 802.11b/g/n/e/i +- Bluetooth v4.2 BR/EDR and BLE +- Various peripherals: + + - 12-bit ADC with up to 18 channels + - 2x 8-bit DACs + - 10x touch sensors + - Temperature sensor + - 4x SPI + - 2x I2S + - 2x I2C + - 3x UART + - SD/SDIO/MMC host + - Slave (SDIO/SPI) + - Ethernet MAC + - CAN bus 2.0 + - IR (RX/TX) + - Motor PWM + - LED PWM with up to 16 channels + - Hall effect sensor + +- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) +- 5uA deep sleep current + +Supported Features +================== + +Current Zephyr's YD-ESP32 board supports the following features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| USB-JTAG | on-chip | hardware interface | ++------------+------------+-------------------------------------+ +| SPI Master | on-chip | spi | ++------------+------------+-------------------------------------+ +| Timers | on-chip | counter | ++------------+------------+-------------------------------------+ +| Watchdog | on-chip | watchdog | ++------------+------------+-------------------------------------+ +| TRNG | on-chip | entropy | ++------------+------------+-------------------------------------+ +| LEDC | on-chip | pwm | ++------------+------------+-------------------------------------+ +| MCPWM | on-chip | pwm | ++------------+------------+-------------------------------------+ +| PCNT | on-chip | qdec | ++------------+------------+-------------------------------------+ +| SPI DMA | on-chip | spi | ++------------+------------+-------------------------------------+ +| TWAI | on-chip | can | ++------------+------------+-------------------------------------+ +| ADC | on-chip | adc | ++------------+------------+-------------------------------------+ +| DAC | on-chip | dac | ++------------+------------+-------------------------------------+ +| Wi-Fi | on-chip | | ++------------+------------+-------------------------------------+ +| Bluetooth | on-chip | | ++------------+------------+-------------------------------------+ + +System requirements +=================== + +Prerequisites +------------- + +Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command +below to retrieve those files. + +.. code-block:: console + + west blobs fetch hal_espressif + +.. note:: + + It is recommended running the command above after :file:`west update`. + +Building & Flashing +******************* + +ESP-IDF bootloader +================== + +The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. +It is build as a subproject at each application build. No further attention +is expected from the user. + +MCUboot bootloader +================== + +User may choose to use MCUboot bootloader instead. In that case the bootloader +must be build (and flash) at least once. + +There are two options to be used when building an application: + +1. Sysbuild +2. Manual build + +.. note:: + + User can select the MCUboot bootloader by adding the following line + to the board default configuration file. + ``` + CONFIG_BOOTLOADER_MCUBOOT=y + ``` + +Sysbuild +======== + +The sysbuild makes possible to build and flash all necessary images needed to +bootstrap the board with the ESP32 SoC. + +To build the sample application using sysbuild use the command: + +.. zephyr-app-commands:: + :tool: west + :app: samples/hello_world + :board: yd_esp32 + :goals: build + :west-args: --sysbuild + :compact: + +By default, the ESP32 sysbuild creates bootloader (MCUboot) and application +images. But it can be configured to create other kind of images. + +Build directory structure created by sysbuild is different from traditional +Zephyr build. Output is structured by the domain subdirectories: + +.. code-block:: + + build/ + ├── hello_world + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + ├── mcuboot + │ └── zephyr + │ ├── zephyr.elf + │ └── zephyr.bin + └── domains.yaml + +.. note:: + + With ``--sysbuild`` option the bootloader will be re-build and re-flash + every time the pristine build is used. + +For more information about the system build please read the :ref:`sysbuild` documentation. + +Manual build +============ + +During the development cycle, it is intended to build & flash as quickly possible. +For that reason, images can be build one at a time using traditional build. + +The instructions following are relevant for both manual build and sysbuild. +The only difference is the structure of the build directory. + +.. note:: + + Remember that bootloader (MCUboot) needs to be flash at least once. + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: build + +The usual ``flash`` target will work with the ``yd_esp32`` board +configuration. Here is an example for the :ref:`hello_world` +application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: flash + +Open the serial monitor using the following command: + +.. code-block:: shell + + west espressif monitor + +After the board has automatically reset and booted, you should see the following +message in the monitor: + +.. code-block:: console + + ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** + Hello World! yd_esp32 + +RGB LED +======= + +The board contains an addressable RGB LED (`XL-5050RGBC-WS2812B`_), driven by GPIO16. +Here is an example of how to test it using the :zephyr:code-sample:`led-ws2812` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/drivers/led_ws2812 + :board: yd_esp32/esp32/procpu + :goals: flash + + +.. _`XL-5050RGBC-WS2812B`: http://www.xinglight.cn/index.php?c=show&id=947 + +Debugging +********* + +ESP32 support on OpenOCD is available upstream as of version 0.12.0. +Download and install OpenOCD from `OpenOCD`_. + +On the YD-ESP32 board, the JTAG pins are not run to a +standard connector (e.g. ARM 20-pin) and need to be manually connected +to the external programmer (e.g. a Flyswatter2): + ++------------+-----------+ +| ESP32 pin | JTAG pin | ++============+===========+ +| 3V3 | VTRef | ++------------+-----------+ +| EN | nTRST | ++------------+-----------+ +| IO14 | TMS | ++------------+-----------+ +| IO12 | TDI | ++------------+-----------+ +| GND | GND | ++------------+-----------+ +| IO13 | TCK | ++------------+-----------+ +| IO15 | TDO | ++------------+-----------+ + +Further documentation can be obtained from the SoC vendor in `JTAG debugging +for ESP32`_. + +Here is an example for building the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: build flash + +You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_esp32/esp32/procpu + :goals: debug + +Note on Debugging with GDB Stub +=============================== + +GDB stub is enabled on ESP32. + +* When adding breakpoints, please use hardware breakpoints with command + ``hbreak``. Command ``break`` uses software breakpoints which requires + modifying memory content to insert break/trap instructions. + This does not work as the code is on flash which cannot be randomly + accessed for modification. + +.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html +.. _`OpenOCD`: https://github.com/openocd-org/openocd + +References +********** + +.. [1] https://en.wikipedia.org/wiki/ESP32 +.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf +.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/yd_esp32/support/openocd.cfg b/boards/vcc-gnd/yd_esp32/support/openocd.cfg similarity index 100% rename from boards/xtensa/yd_esp32/support/openocd.cfg rename to boards/vcc-gnd/yd_esp32/support/openocd.cfg diff --git a/boards/xtensa/yd_esp32/yd_esp32-pinctrl.dtsi b/boards/vcc-gnd/yd_esp32/yd_esp32-pinctrl.dtsi similarity index 100% rename from boards/xtensa/yd_esp32/yd_esp32-pinctrl.dtsi rename to boards/vcc-gnd/yd_esp32/yd_esp32-pinctrl.dtsi diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.dts new file mode 100644 index 00000000000000..6bed6d38402940 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.dts @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include + +/ { + model = "VCC-GND Studio YD-ESP32 APPCPU"; + compatible = "espressif,esp32"; + + chosen { + zephyr,sram = &sram0; + zephyr,ipc_shm = &shm0; + zephyr,ipc = &ipm0; + }; +}; + +&cpu0 { + clock-frequency = ; +}; + +&cpu1 { + clock-frequency = ; +}; + +&ipm0 { + status = "okay"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.yaml b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.yaml new file mode 100644 index 00000000000000..018b3c2b727323 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu.yaml @@ -0,0 +1,27 @@ +identifier: yd_esp32/esp32/appcpu +name: ESP32 DEVKITC WROVER APPCPU +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - uart +testing: + ignore_tags: + - net + - bluetooth + - flash + - cpp + - posix + - watchdog + - logging + - kernel + - pm + - gpio + - crypto + - eeprom + - heap + - cmsis_rtos + - jwt + - zdsp +vendor: espressif diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig new file mode 100644 index 00000000000000..100bb882567619 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_appcpu_defconfig @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_CLOCK_CONTROL=y +CONFIG_MINIMAL_LIBC=y diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.dts new file mode 100644 index 00000000000000..2e748af71b98d5 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.dts @@ -0,0 +1,184 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ +/dts-v1/; + +#include +#include +#include "yd_esp32-pinctrl.dtsi" +#include + +/ { + model = "VCC-GND Studio YD-ESP32 PROCPU"; + compatible = "espressif,esp32"; + + aliases { + uart-0 = &uart0; + i2c-0 = &i2c0; + sw0 = &button0; + watchdog0 = &wdt0; + led-strip = &rgb_led; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "BOOT Button"; + zephyr,code = ; + }; + }; + + chosen { + zephyr,sram = &sram0; + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,flash = &flash0; + zephyr,code-partition = &slot0_partition; + }; +}; + +&pinctrl { + spim2_default: spim2_default { + group2 { + pinmux = ; + output-low; + }; + }; +}; + +&cpu0 { + clock-frequency = ; + cpu-power-states = <&light_sleep &deep_sleep>; +}; + +&cpu1 { + clock-frequency = ; +}; + +&uart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-names = "default"; +}; + +&uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-names = "default"; +}; + +&uart2 { + current-speed = <115200>; + pinctrl-0 = <&uart2_default>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = ; + sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; + scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; + pinctrl-0 = <&i2c0_default>; + pinctrl-names = "default"; +}; + +&spi2 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim2_default>; + pinctrl-names = "default"; + + rgb_led: ws2812@0 { + compatible = "worldsemi,ws2812-spi"; + + /* SPI */ + reg = <0>; /* ignored, but necessary for SPI bindings */ + spi-max-frequency = <6400000>; + + /* XL-5050RGBC-WS2812B */ + chain-length = <1>; + spi-one-frame = <0xfc>; /* 11111100: 0.937 us high and 0.313 us low */ + spi-zero-frame = <0xc0>; /* 11000000: 0.313 us high and 0.937 us low */ + color-mapping = ; + }; +}; + +&spi3 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + pinctrl-0 = <&spim3_default>; + pinctrl-names = "default"; +}; + +&timer0 { + status = "disabled"; +}; + +&timer1 { + status = "disabled"; +}; + +&timer2 { + status = "disabled"; +}; + +&timer3 { + status = "disabled"; +}; + +&trng0 { + status = "okay"; +}; + +&flash0 { + status = "okay"; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Reserve 60kB for the bootloader */ + boot_partition: partition@1000 { + label = "mcuboot"; + reg = <0x00001000 0x0000F000>; + read-only; + }; + + /* Reserve 1024kB for the application in slot 0 */ + slot0_partition: partition@10000 { + label = "image-0"; + reg = <0x00010000 0x00100000>; + }; + + /* Reserve 1024kB for the application in slot 1 */ + slot1_partition: partition@110000 { + label = "image-1"; + reg = <0x00110000 0x00100000>; + }; + + /* Reserve 256kB for the scratch partition */ + scratch_partition: partition@210000 { + label = "image-scratch"; + reg = <0x00210000 0x00040000>; + }; + + storage_partition: partition@250000 { + label = "storage"; + reg = <0x00250000 0x00006000>; + }; + }; +}; diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.yaml b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.yaml new file mode 100644 index 00000000000000..b3fc0cdf97d1a7 --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu.yaml @@ -0,0 +1,24 @@ +identifier: yd_esp32/esp32/procpu +name: YD-ESP32 +type: mcu +arch: xtensa +toolchain: + - zephyr +supported: + - adc + - dac + - gpio + - i2c + - watchdog + - uart + - nvs + - pwm + - dac + - spi + - counter + - entropy +testing: + ignore_tags: + - net + - bluetooth +vendor: vcc-gnd diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu_defconfig b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu_defconfig new file mode 100644 index 00000000000000..4fc7d44e0852af --- /dev/null +++ b/boards/vcc-gnd/yd_esp32/yd_esp32_esp32_procpu_defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Julio Cesar +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/vng/index.rst b/boards/vng/index.rst new file mode 100644 index 00000000000000..5d4ab1cecd97d2 --- /dev/null +++ b/boards/vng/index.rst @@ -0,0 +1,10 @@ +.. _boards-vng: + +VNG Corporation +############### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/vng/nrf51_vbluno51/Kconfig.defconfig b/boards/vng/nrf51_vbluno51/Kconfig.defconfig new file mode 100644 index 00000000000000..4957faeb05c018 --- /dev/null +++ b/boards/vng/nrf51_vbluno51/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 VBLUno51 board configuration + +# Copyright (c) 2017 VNG IoT Lab Limited. +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51_VBLUNO51 + +config BT_CTLR + default BT + +endif # BOARD_NRF51_VBLUNO51 diff --git a/boards/vng/nrf51_vbluno51/Kconfig.nrf51_vbluno51 b/boards/vng/nrf51_vbluno51/Kconfig.nrf51_vbluno51 new file mode 100644 index 00000000000000..69400c2344c3dc --- /dev/null +++ b/boards/vng/nrf51_vbluno51/Kconfig.nrf51_vbluno51 @@ -0,0 +1,7 @@ +# nRF51-VBLUNO51 board configuration + +# Copyright (c) 2017 VNG IoT Lab Limited. +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51_VBLUNO51 + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_vbluno51/board.cmake b/boards/vng/nrf51_vbluno51/board.cmake similarity index 100% rename from boards/arm/nrf51_vbluno51/board.cmake rename to boards/vng/nrf51_vbluno51/board.cmake diff --git a/boards/vng/nrf51_vbluno51/board.yml b/boards/vng/nrf51_vbluno51/board.yml new file mode 100644 index 00000000000000..8e3a9bf948830d --- /dev/null +++ b/boards/vng/nrf51_vbluno51/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51_vbluno51 + vendor: vngiotlab + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg b/boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg rename to boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg b/boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg rename to boards/vng/nrf51_vbluno51/doc/img/nrf51_vbluno51_bot.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg b/boards/vng/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg rename to boards/vng/nrf51_vbluno51/doc/img/vbluno51_frizting.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg b/boards/vng/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg rename to boards/vng/nrf51_vbluno51/doc/img/vbluno51_nordic_pinout.jpg diff --git a/boards/arm/nrf51_vbluno51/doc/index.rst b/boards/vng/nrf51_vbluno51/doc/index.rst similarity index 100% rename from boards/arm/nrf51_vbluno51/doc/index.rst rename to boards/vng/nrf51_vbluno51/doc/index.rst diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi b/boards/vng/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi rename to boards/vng/nrf51_vbluno51/nrf51_vbluno51-pinctrl.dtsi diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51.dts b/boards/vng/nrf51_vbluno51/nrf51_vbluno51.dts similarity index 100% rename from boards/arm/nrf51_vbluno51/nrf51_vbluno51.dts rename to boards/vng/nrf51_vbluno51/nrf51_vbluno51.dts diff --git a/boards/arm/nrf51_vbluno51/nrf51_vbluno51.yaml b/boards/vng/nrf51_vbluno51/nrf51_vbluno51.yaml similarity index 100% rename from boards/arm/nrf51_vbluno51/nrf51_vbluno51.yaml rename to boards/vng/nrf51_vbluno51/nrf51_vbluno51.yaml diff --git a/boards/vng/nrf51_vbluno51/nrf51_vbluno51_defconfig b/boards/vng/nrf51_vbluno51/nrf51_vbluno51_defconfig new file mode 100644 index 00000000000000..1289685e1e806e --- /dev/null +++ b/boards/vng/nrf51_vbluno51/nrf51_vbluno51_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/nrf51dongle_nrf51422/pre_dt_board.cmake b/boards/vng/nrf51_vbluno51/pre_dt_board.cmake similarity index 100% rename from boards/arm/nrf51dongle_nrf51422/pre_dt_board.cmake rename to boards/vng/nrf51_vbluno51/pre_dt_board.cmake diff --git a/boards/vng/nrf52_vbluno52/Kconfig.defconfig b/boards/vng/nrf52_vbluno52/Kconfig.defconfig new file mode 100644 index 00000000000000..700df41dfc6c92 --- /dev/null +++ b/boards/vng/nrf52_vbluno52/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF52 VBLUno52 board configuration + +# Copyright (c) 2017 VNG IoT Lab +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF52_VBLUNO52 + +config BT_CTLR + default BT + +endif # BOARD_NRF52_VBLUNO52 diff --git a/boards/vng/nrf52_vbluno52/Kconfig.nrf52_vbluno52 b/boards/vng/nrf52_vbluno52/Kconfig.nrf52_vbluno52 new file mode 100644 index 00000000000000..e2d9bec6517a8c --- /dev/null +++ b/boards/vng/nrf52_vbluno52/Kconfig.nrf52_vbluno52 @@ -0,0 +1,7 @@ +# nRF52 VBLUno52 board configuration +# Copyright (c) 2017 VNG IoT Lab + +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF52_VBLUNO52 + select SOC_NRF52832_QFAA diff --git a/boards/arm/nrf52_vbluno52/board.cmake b/boards/vng/nrf52_vbluno52/board.cmake similarity index 100% rename from boards/arm/nrf52_vbluno52/board.cmake rename to boards/vng/nrf52_vbluno52/board.cmake diff --git a/boards/vng/nrf52_vbluno52/board.yml b/boards/vng/nrf52_vbluno52/board.yml new file mode 100644 index 00000000000000..be59c421baa573 --- /dev/null +++ b/boards/vng/nrf52_vbluno52/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf52_vbluno52 + vendor: vngiotlab + socs: + - name: nrf52832 diff --git a/boards/arm/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg b/boards/vng/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg similarity index 100% rename from boards/arm/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg rename to boards/vng/nrf52_vbluno52/doc/img/nrf52_vbluno52.jpg diff --git a/boards/arm/nrf52_vbluno52/doc/index.rst b/boards/vng/nrf52_vbluno52/doc/index.rst similarity index 100% rename from boards/arm/nrf52_vbluno52/doc/index.rst rename to boards/vng/nrf52_vbluno52/doc/index.rst diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi b/boards/vng/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi rename to boards/vng/nrf52_vbluno52/nrf52_vbluno52-pinctrl.dtsi diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52.dts b/boards/vng/nrf52_vbluno52/nrf52_vbluno52.dts similarity index 100% rename from boards/arm/nrf52_vbluno52/nrf52_vbluno52.dts rename to boards/vng/nrf52_vbluno52/nrf52_vbluno52.dts diff --git a/boards/arm/nrf52_vbluno52/nrf52_vbluno52.yaml b/boards/vng/nrf52_vbluno52/nrf52_vbluno52.yaml similarity index 100% rename from boards/arm/nrf52_vbluno52/nrf52_vbluno52.yaml rename to boards/vng/nrf52_vbluno52/nrf52_vbluno52.yaml diff --git a/boards/vng/nrf52_vbluno52/nrf52_vbluno52_defconfig b/boards/vng/nrf52_vbluno52/nrf52_vbluno52_defconfig new file mode 100644 index 00000000000000..7167aca850a04d --- /dev/null +++ b/boards/vng/nrf52_vbluno52/nrf52_vbluno52_defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Enable MPU +CONFIG_ARM_MPU=y + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/ubx_evkninab4_nrf52833/pre_dt_board.cmake b/boards/vng/nrf52_vbluno52/pre_dt_board.cmake similarity index 100% rename from boards/arm/ubx_evkninab4_nrf52833/pre_dt_board.cmake rename to boards/vng/nrf52_vbluno52/pre_dt_board.cmake diff --git a/boards/waveshare/index.rst b/boards/waveshare/index.rst new file mode 100644 index 00000000000000..6acd377cab94c1 --- /dev/null +++ b/boards/waveshare/index.rst @@ -0,0 +1,10 @@ +.. _boards-waveshare: + +Waveshare Electronics +##################### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/waveshare/nrf51_ble400/Kconfig.defconfig b/boards/waveshare/nrf51_ble400/Kconfig.defconfig new file mode 100644 index 00000000000000..65d41b852d32a7 --- /dev/null +++ b/boards/waveshare/nrf51_ble400/Kconfig.defconfig @@ -0,0 +1,11 @@ +# nRF51 BLE400 board configuration + +# Copyright (c) 2018 Roman Tataurov +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_NRF51_BLE400 + +config BT_CTLR + default BT + +endif # BOARD_NRF51_BLE400 diff --git a/boards/waveshare/nrf51_ble400/Kconfig.nrf51_ble400 b/boards/waveshare/nrf51_ble400/Kconfig.nrf51_ble400 new file mode 100644 index 00000000000000..48bb3e49e096cb --- /dev/null +++ b/boards/waveshare/nrf51_ble400/Kconfig.nrf51_ble400 @@ -0,0 +1,7 @@ +# nRF51 BLE400 board configuration + +# Copyright (c) 2018 Roman Tataurov +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_NRF51_BLE400 + select SOC_NRF51822_QFAC diff --git a/boards/arm/nrf51_ble400/board.cmake b/boards/waveshare/nrf51_ble400/board.cmake similarity index 100% rename from boards/arm/nrf51_ble400/board.cmake rename to boards/waveshare/nrf51_ble400/board.cmake diff --git a/boards/waveshare/nrf51_ble400/board.yml b/boards/waveshare/nrf51_ble400/board.yml new file mode 100644 index 00000000000000..d2c7da1f732aec --- /dev/null +++ b/boards/waveshare/nrf51_ble400/board.yml @@ -0,0 +1,5 @@ +board: + name: nrf51_ble400 + vendor: waveshare + socs: + - name: nrf51822 diff --git a/boards/arm/nrf51_ble400/doc/img/BLE400-size.jpg b/boards/waveshare/nrf51_ble400/doc/img/BLE400-size.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/BLE400-size.jpg rename to boards/waveshare/nrf51_ble400/doc/img/BLE400-size.jpg diff --git a/boards/arm/nrf51_ble400/doc/img/Core51822-Compare.jpg b/boards/waveshare/nrf51_ble400/doc/img/Core51822-Compare.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/Core51822-Compare.jpg rename to boards/waveshare/nrf51_ble400/doc/img/Core51822-Compare.jpg diff --git a/boards/arm/nrf51_ble400/doc/img/Core51822-pin.jpg b/boards/waveshare/nrf51_ble400/doc/img/Core51822-pin.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/Core51822-pin.jpg rename to boards/waveshare/nrf51_ble400/doc/img/Core51822-pin.jpg diff --git a/boards/arm/nrf51_ble400/doc/img/nrf51_ble400.jpg b/boards/waveshare/nrf51_ble400/doc/img/nrf51_ble400.jpg similarity index 100% rename from boards/arm/nrf51_ble400/doc/img/nrf51_ble400.jpg rename to boards/waveshare/nrf51_ble400/doc/img/nrf51_ble400.jpg diff --git a/boards/waveshare/nrf51_ble400/doc/index.rst b/boards/waveshare/nrf51_ble400/doc/index.rst new file mode 100644 index 00000000000000..3bfe06aa204257 --- /dev/null +++ b/boards/waveshare/nrf51_ble400/doc/index.rst @@ -0,0 +1,223 @@ +.. _nrf51_ble400: + +Waveshare BLE400 +################# + +Overview +******** + +BLE400 is a motherboard designed for BLE Bluetooth 2.4G Wireless Module. Used together with core board -- Core51822. + +Supported Features +================== + +Motherboard +------------ + +- Onboard battery holder, multi power supplies are available +- All the IOs are accessible for easy expansion +- Integrates CP2102 for debugging +- LEDs and user keys, compatible with other official boards, easy to use + +Core board +---------- + +- Onboard chip: nRF51822 +- Communication distance (open outdoor 1M data rate): 30m +- Frequency range: 2.4GHz +- Operating voltage: 2.0V ~ 3.6V +- Operating temperature: -40℃ ~ 85℃ +- Expansion pinheader: all the I/Os except P0.26 and P0.27 +- Pinheader pitch: 2.00mm +- Antenna: onboard antenna + +Features +======== + +- 2.4 GHz multiprotocol RF transceiver +- ARM® Cortex™-M0 32 bit processor +- 128 bit AES HW encryption +- 256kB flash & 32kB RAM +- Programmable Peripheral Interconnect (PPI) +- Digital interfaces: SPI, I2C, UART +- 10 bit ADC +- Programmable output power: -20 to +4 dBm +- Independent application development and protocol stack +- Fully compatible with NRF24L series +- Pinout compatible with NRF51xxx series +- Global separate power management +- Operating voltage: 1.8 V ~ 3.6 V + +Revision History +================ + +Core board +---------- + +In June of 2015, Core51822 and its variant, Core51822 (B), upgraded the onboard chip to Rev3 (nRF51822_QFAC) that features 32kB RAM. + +.. image:: img/Core51822-Compare.jpg + :align: center + :alt: Compare + +Top: Core51822 +Bottom: Core51822 (B) + +Connections and IOs +==================== + +Motherboard +------------ + +.. image:: img/nrf51_ble400.jpg + :align: center + :alt: BLE400 + +1. Wireless module connector: for easily connecting modules like Core51822 +2. MCU pins expansion connector +3. I2C interface +4. SPI interface +5. 5V/3.3V power input/output: usually used as power output, also common-grounding with other user board +6. USB connector: USB TO UART via onboard converter CP2102 +7. Debugging interface +8. UART interface +9. Battery holder +10. User LEDs +11. User keys +12. Reset button +13. CP2102 +14. USB TO UART jumper +15. LEDs & Keys jumper + +Core board +---------- + +.. image:: img/Core51822-pin.jpg + :align: center + :alt: Core board pinout + +BLE400 dimensions +================= + +.. image:: img/BLE400-size.jpg + :align: center + :alt: BLE400 size + +Connections and IOs +=================== + +LED +--- + +* LED0 (red) = P0.18 +* LED1 (red) = P0.19 +* LED2 (red) = P0.20 +* LED3 (red) = P0.21 +* LED4 (red) = P0.22 +* SUSPEND = SUSPEND +* RXD1 = P0.9 +* TXD1 = P0.11 + +Push buttons +------------ + +* KEY1 = P0.16 +* KEY2 = P0.17 +* RESET = SWDIO + +I2C +--- + +* SMBA = P0.02 +* SCL = P0.01 +* SDA = P0.00 + +SPI +--- + +* NSS = P0.30 +* SCK = P0.25 +* MOSI = P0.24 +* MISO = P0.23 + +USART1 +------ + +* RX = P0.05 +* TX = P0.06 +* CTS = P0.07 +* RTS = P0.12 + +UART (USB) +---------- + +* RX = P0.9 +* TX = P0.11 +* CTS = P0.8 +* RTS = P0.10 + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF51 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: nrf51_ble400 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the nRF51 DK +******************************************** + +There are samples below that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +- :zephyr:code-sample:`blinky` +- :zephyr:code-sample:`button` +- :zephyr:code-sample:`fade-led` +- :zephyr:code-sample:`multi-thread-blinky` + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/waveshare/nrf51_ble400/nrf51_ble400.dts`. + +References +********** + +.. target-notes:: + +.. _nRF51 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF51-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _Waveshare Wiki BLE400: https://www.waveshare.com/wiki/BLE400 +.. _Waveshare WiKi Core51822: https://www.waveshare.com/wiki/Core51822 +.. _User manual: https://www.waveshare.com/w/upload/b/b7/NRF51822-Eval-Kit-UserManual-EN.pdf +.. _Schematic: https://www.waveshare.com/w/upload/1/1b/BLE400-Schematic.pdf +.. _Code samples: https://www.waveshare.com/w/upload/5/53/NRF51822-Code.7z +.. _Core board schematics: https://www.waveshare.com/w/upload/5/57/Core51822-Schematic.pdf diff --git a/boards/arm/nrf51_ble400/nrf51_ble400-pinctrl.dtsi b/boards/waveshare/nrf51_ble400/nrf51_ble400-pinctrl.dtsi similarity index 100% rename from boards/arm/nrf51_ble400/nrf51_ble400-pinctrl.dtsi rename to boards/waveshare/nrf51_ble400/nrf51_ble400-pinctrl.dtsi diff --git a/boards/arm/nrf51_ble400/nrf51_ble400.dts b/boards/waveshare/nrf51_ble400/nrf51_ble400.dts similarity index 100% rename from boards/arm/nrf51_ble400/nrf51_ble400.dts rename to boards/waveshare/nrf51_ble400/nrf51_ble400.dts diff --git a/boards/arm/nrf51_ble400/nrf51_ble400.yaml b/boards/waveshare/nrf51_ble400/nrf51_ble400.yaml similarity index 100% rename from boards/arm/nrf51_ble400/nrf51_ble400.yaml rename to boards/waveshare/nrf51_ble400/nrf51_ble400.yaml diff --git a/boards/waveshare/nrf51_ble400/nrf51_ble400_defconfig b/boards/waveshare/nrf51_ble400/nrf51_ble400_defconfig new file mode 100644 index 00000000000000..1289685e1e806e --- /dev/null +++ b/boards/waveshare/nrf51_ble400/nrf51_ble400_defconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +# enable GPIO +CONFIG_GPIO=y + +# enable uart driver +CONFIG_SERIAL=y + +# enable console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y diff --git a/boards/arm/qemu_cortex_m0/pre_dt_board.cmake b/boards/waveshare/nrf51_ble400/pre_dt_board.cmake similarity index 100% rename from boards/arm/qemu_cortex_m0/pre_dt_board.cmake rename to boards/waveshare/nrf51_ble400/pre_dt_board.cmake diff --git a/boards/waveshare/open103z/Kconfig.waveshare_open103z b/boards/waveshare/open103z/Kconfig.waveshare_open103z new file mode 100644 index 00000000000000..ae0e3f3b4b30d6 --- /dev/null +++ b/boards/waveshare/open103z/Kconfig.waveshare_open103z @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Stefano Manni +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WAVESHARE_OPEN103Z + select SOC_STM32F103XE diff --git a/boards/arm/waveshare_open103z/board.cmake b/boards/waveshare/open103z/board.cmake similarity index 100% rename from boards/arm/waveshare_open103z/board.cmake rename to boards/waveshare/open103z/board.cmake diff --git a/boards/waveshare/open103z/board.yml b/boards/waveshare/open103z/board.yml new file mode 100644 index 00000000000000..7504feebf9f342 --- /dev/null +++ b/boards/waveshare/open103z/board.yml @@ -0,0 +1,5 @@ +board: + name: waveshare_open103z + vendor: waveshare + socs: + - name: stm32f103xe diff --git a/boards/arm/waveshare_open103z/doc/img/waveshare_connector.PNG b/boards/waveshare/open103z/doc/img/waveshare_connector.PNG similarity index 100% rename from boards/arm/waveshare_open103z/doc/img/waveshare_connector.PNG rename to boards/waveshare/open103z/doc/img/waveshare_connector.PNG diff --git a/boards/arm/waveshare_open103z/doc/img/waveshare_connector_list.PNG b/boards/waveshare/open103z/doc/img/waveshare_connector_list.PNG similarity index 100% rename from boards/arm/waveshare_open103z/doc/img/waveshare_connector_list.PNG rename to boards/waveshare/open103z/doc/img/waveshare_connector_list.PNG diff --git a/boards/arm/waveshare_open103z/doc/img/waveshare_open103z.jpg b/boards/waveshare/open103z/doc/img/waveshare_open103z.jpg similarity index 100% rename from boards/arm/waveshare_open103z/doc/img/waveshare_open103z.jpg rename to boards/waveshare/open103z/doc/img/waveshare_open103z.jpg diff --git a/boards/arm/waveshare_open103z/doc/index.rst b/boards/waveshare/open103z/doc/index.rst similarity index 100% rename from boards/arm/waveshare_open103z/doc/index.rst rename to boards/waveshare/open103z/doc/index.rst diff --git a/boards/arm/waveshare_open103z/support/openocd.cfg b/boards/waveshare/open103z/support/openocd.cfg similarity index 100% rename from boards/arm/waveshare_open103z/support/openocd.cfg rename to boards/waveshare/open103z/support/openocd.cfg diff --git a/boards/arm/waveshare_open103z/waveshare_open103z.dts b/boards/waveshare/open103z/waveshare_open103z.dts similarity index 100% rename from boards/arm/waveshare_open103z/waveshare_open103z.dts rename to boards/waveshare/open103z/waveshare_open103z.dts diff --git a/boards/arm/waveshare_open103z/waveshare_open103z.yaml b/boards/waveshare/open103z/waveshare_open103z.yaml similarity index 100% rename from boards/arm/waveshare_open103z/waveshare_open103z.yaml rename to boards/waveshare/open103z/waveshare_open103z.yaml diff --git a/boards/arm/waveshare_open103z/waveshare_open103z_defconfig b/boards/waveshare/open103z/waveshare_open103z_defconfig similarity index 81% rename from boards/arm/waveshare_open103z/waveshare_open103z_defconfig rename to boards/waveshare/open103z/waveshare_open103z_defconfig index 765fc062bd7db7..9fd4400ac206eb 100644 --- a/boards/arm/waveshare_open103z/waveshare_open103z_defconfig +++ b/boards/waveshare/open103z/waveshare_open103z_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F1X=y -CONFIG_SOC_STM32F103XE=y - # enable uart driver CONFIG_SERIAL=y # enable console diff --git a/boards/we/index.rst b/boards/we/index.rst new file mode 100644 index 00000000000000..b7c7b2e468a153 --- /dev/null +++ b/boards/we/index.rst @@ -0,0 +1,10 @@ +.. _boards-wurth-elektronik: + +Würth Elektronik +################ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/we/ophelia1ev/Kconfig b/boards/we/ophelia1ev/Kconfig new file mode 100644 index 00000000000000..2b36398f590d8e --- /dev/null +++ b/boards/we/ophelia1ev/Kconfig @@ -0,0 +1,10 @@ +# Ophelia-I EV nRF52805 board configuration + +# Copyright (c) 2020 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + depends on BOARD_WE_OPHELIA1EV diff --git a/boards/we/ophelia1ev/Kconfig.defconfig b/boards/we/ophelia1ev/Kconfig.defconfig new file mode 100644 index 00000000000000..c148d6771835ce --- /dev/null +++ b/boards/we/ophelia1ev/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_OPHELIA1EV + +config BT_CTLR + default BT + +endif diff --git a/boards/we/ophelia1ev/Kconfig.we_ophelia1ev b/boards/we/ophelia1ev/Kconfig.we_ophelia1ev new file mode 100644 index 00000000000000..d732cd54cb37e8 --- /dev/null +++ b/boards/we/ophelia1ev/Kconfig.we_ophelia1ev @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WE_OPHELIA1EV + select SOC_NRF52805_CAAA diff --git a/boards/arm/we_ophelia1ev_nrf52805/board.cmake b/boards/we/ophelia1ev/board.cmake similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/board.cmake rename to boards/we/ophelia1ev/board.cmake diff --git a/boards/we/ophelia1ev/board.yml b/boards/we/ophelia1ev/board.yml new file mode 100644 index 00000000000000..ac80e1ed6e4de6 --- /dev/null +++ b/boards/we/ophelia1ev/board.yml @@ -0,0 +1,5 @@ +board: + name: we_ophelia1ev + vendor: wurth + socs: + - name: nrf52805 diff --git a/boards/arm/we_ophelia1ev_nrf52805/doc/img/we_ophelia1ev_nrf52805.jpg b/boards/we/ophelia1ev/doc/img/we_ophelia1ev_nrf52805.jpg similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/doc/img/we_ophelia1ev_nrf52805.jpg rename to boards/we/ophelia1ev/doc/img/we_ophelia1ev_nrf52805.jpg diff --git a/boards/we/ophelia1ev/doc/index.rst b/boards/we/ophelia1ev/doc/index.rst new file mode 100644 index 00000000000000..d64c32579a5431 --- /dev/null +++ b/boards/we/ophelia1ev/doc/index.rst @@ -0,0 +1,115 @@ +.. _we_ophelia1ev_nrf52805: + +Ophelia-I EV NRF52805 +##################### + +Overview +******** + +The we_ophelia1ev_nrf52805 board is an evaluation board of the Ophelia-I radio module. +It provides support for the Nordic Semiconductor nRF52805 ARM CPU and +the following devices: + +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/we_ophelia1ev_nrf52805.jpg + :align: center + :alt: Ophelia-I EV + + Ophelia-I EV (Credit: Würth Elektronik) + +Hardware +******** + +The Ophelia-I uses the internal low frequency RC oscillator +and provides the so called smart antenna connection, that allows +to choose between the module's integrated PCB antenna and an external +antenna that can be connected to the available SMA connector. + +Supported Features +================== + +The we_ophelia1ev_nrf52805 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Programming and Debugging +************************* + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board nRF52 DK +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: we_ophelia1ev/nrf52805 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + +References +********** + +.. target-notes:: + +.. _Ophelia-I radio module website: https://www.we-online.com/katalog/de/OPHELIA-I +.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805 diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805-pinctrl.dtsi b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805-pinctrl.dtsi similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805-pinctrl.dtsi rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805-pinctrl.dtsi diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.dts b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts similarity index 100% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.dts rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805.dts diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.yaml b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml similarity index 88% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.yaml rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml index b069727893196e..5b55a854a0d99f 100644 --- a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805.yaml +++ b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: we_ophelia1ev_nrf52805 +identifier: we_ophelia1ev/nrf52805 name: we_ophelia1ev_nrf52805 type: mcu arch: arm diff --git a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805_defconfig b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805_defconfig similarity index 79% rename from boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805_defconfig rename to boards/we/ophelia1ev/we_ophelia1ev_nrf52805_defconfig index b81a1a35e4eada..b2e4d39984b5f1 100644 --- a/boards/arm/we_ophelia1ev_nrf52805/we_ophelia1ev_nrf52805_defconfig +++ b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52805_CAAA=y -CONFIG_BOARD_WE_OPHELIA1EV_NRF52805=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/we_proteus2ev_nrf52832/Kconfig b/boards/we/proteus2ev/Kconfig similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/Kconfig rename to boards/we/proteus2ev/Kconfig diff --git a/boards/we/proteus2ev/Kconfig.defconfig b/boards/we/proteus2ev/Kconfig.defconfig new file mode 100644 index 00000000000000..dcdfd0a06e0b8f --- /dev/null +++ b/boards/we/proteus2ev/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_PROTEUS2EV_NRF52832 + +config BT_CTLR + default BT + +endif diff --git a/boards/we/proteus2ev/Kconfig.we_proteus2ev b/boards/we/proteus2ev/Kconfig.we_proteus2ev new file mode 100644 index 00000000000000..60aa73fb142c77 --- /dev/null +++ b/boards/we/proteus2ev/Kconfig.we_proteus2ev @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WE_PROTEUS2EV_NRF52832 + select SOC_NRF52832_CIAA diff --git a/boards/arm/we_proteus2ev_nrf52832/board.cmake b/boards/we/proteus2ev/board.cmake similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/board.cmake rename to boards/we/proteus2ev/board.cmake diff --git a/boards/we/proteus2ev/board.yml b/boards/we/proteus2ev/board.yml new file mode 100644 index 00000000000000..38cc08204e5981 --- /dev/null +++ b/boards/we/proteus2ev/board.yml @@ -0,0 +1,5 @@ +board: + name: we_proteus2ev + vendor: wurth + socs: + - name: nrf52832 diff --git a/boards/arm/we_proteus2ev_nrf52832/doc/img/we_proteus2ev_nrf52832.jpg b/boards/we/proteus2ev/doc/img/we_proteus2ev_nrf52832.jpg similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/doc/img/we_proteus2ev_nrf52832.jpg rename to boards/we/proteus2ev/doc/img/we_proteus2ev_nrf52832.jpg diff --git a/boards/we/proteus2ev/doc/index.rst b/boards/we/proteus2ev/doc/index.rst new file mode 100644 index 00000000000000..7bdd621fd90727 --- /dev/null +++ b/boards/we/proteus2ev/doc/index.rst @@ -0,0 +1,162 @@ +.. _we_proteus2ev_nrf52832: + +Würth Elektronik Proteus-II-EV +############################## + +Overview +******** + +The Proteus-II-EV hardware provides +support for the Proteus-II radio module that uses the Nordic Semiconductor nRF52832 ARM Cortex-M4F CPU and +the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/we_proteus2ev_nrf52832.jpg + :align: center + :alt: Proteus-II EV + + Proteus-II-EV (Credit: Würth Elektronik) + +More information about the radio module can be found the Würth Elektronik web page https://www.we-online.com/katalog/de/PROTEUS-II . + + +Hardware +******** + +Proteus-II radio module provides only the internal oscillators. The frequency of the slow clock +is 32.768 kHz. The frequency of the main clock is 32 MHz. + +Supported Features +================== + +The we_proteus2ev/nrf52832 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not supported by the Zephyr kernel. + +Connections and IOs +=================== + +LED +--- + +* LED1 = P0.00 +* LED2 = P0.01 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.29 + + +Programming and Debugging +************************* + +Applications for the ``we_proteus2ev/nrf52832`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board Proteus-II-EV +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: we_proteus2ev/nrf52832 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic boards with a +Segger IC. + + +Testing the LEDs and buttons in the Proteus-II-EV +************************************************* + +There are 2 samples that allow you to test that the buttons (switches) and LEDs on +the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly on +your board. The button and LED definitions can be found in +:zephyr_file:`boards/wurth_elektronik/proteus2ev/we_proteus2ev_nrf52832.dts`. + +References +********** + +.. target-notes:: + +.. _Proteus-II radio module website: https://www.we-online.com/katalog/de/PROTEUS-II +.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com diff --git a/boards/arm/we_proteus2ev_nrf52832/pre_dt_board.cmake b/boards/we/proteus2ev/pre_dt_board.cmake similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/pre_dt_board.cmake rename to boards/we/proteus2ev/pre_dt_board.cmake diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832-pinctrl.dtsi b/boards/we/proteus2ev/we_proteus2ev_nrf52832-pinctrl.dtsi similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832-pinctrl.dtsi rename to boards/we/proteus2ev/we_proteus2ev_nrf52832-pinctrl.dtsi diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.dts b/boards/we/proteus2ev/we_proteus2ev_nrf52832.dts similarity index 100% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.dts rename to boards/we/proteus2ev/we_proteus2ev_nrf52832.dts diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.yaml b/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml similarity index 88% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.yaml rename to boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml index 4cc87992655895..e30510176d0dbe 100644 --- a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832.yaml +++ b/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: we_proteus2ev_nrf52832 +identifier: we_proteus2ev/nrf52832 name: we_proteus2ev_nrf52832 type: mcu arch: arm diff --git a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832_defconfig b/boards/we/proteus2ev/we_proteus2ev_nrf52832_defconfig similarity index 81% rename from boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832_defconfig rename to boards/we/proteus2ev/we_proteus2ev_nrf52832_defconfig index 0b4e298d05aa88..62452ad517ef6c 100644 --- a/boards/arm/we_proteus2ev_nrf52832/we_proteus2ev_nrf52832_defconfig +++ b/boards/we/proteus2ev/we_proteus2ev_nrf52832_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52832_CIAA=y -CONFIG_BOARD_WE_PROTEUS2EV_NRF52832=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/we/proteus3ev/Kconfig b/boards/we/proteus3ev/Kconfig new file mode 100644 index 00000000000000..06a2c989d8adc0 --- /dev/null +++ b/boards/we/proteus3ev/Kconfig @@ -0,0 +1,18 @@ +# Proteus-III-EV board configuration + +# Copyright (c) 2016 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_PROTEUS3EV + +config BOARD_ENABLE_DCDC + bool "DCDC mode" + select SOC_DCDC_NRF52X + default y + +config BOARD_ENABLE_DCDC_HV + bool "High Voltage DCDC converter" + select SOC_DCDC_NRF52X_HV + default y + +endif # BOARD_WE_PROTEUS3EV diff --git a/boards/we/proteus3ev/Kconfig.defconfig b/boards/we/proteus3ev/Kconfig.defconfig new file mode 100644 index 00000000000000..ef564abbcbc5ed --- /dev/null +++ b/boards/we/proteus3ev/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_WE_PROTEUS3EV + +config BT_CTLR + default BT + +endif # BOARD_WE_PROTEUS3EV diff --git a/boards/we/proteus3ev/Kconfig.we_proteus3ev b/boards/we/proteus3ev/Kconfig.we_proteus3ev new file mode 100644 index 00000000000000..bdc3245f14a26a --- /dev/null +++ b/boards/we/proteus3ev/Kconfig.we_proteus3ev @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WE_PROTEUS3EV + select SOC_NRF52840_QIAA diff --git a/boards/arm/we_proteus3ev_nrf52840/board.cmake b/boards/we/proteus3ev/board.cmake similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/board.cmake rename to boards/we/proteus3ev/board.cmake diff --git a/boards/we/proteus3ev/board.yml b/boards/we/proteus3ev/board.yml new file mode 100644 index 00000000000000..6def880d7a5b40 --- /dev/null +++ b/boards/we/proteus3ev/board.yml @@ -0,0 +1,5 @@ +board: + name: we_proteus3ev + vendor: wurth + socs: + - name: nrf52840 diff --git a/boards/arm/we_proteus3ev_nrf52840/doc/img/we_proteus3ev_nrf52840.jpg b/boards/we/proteus3ev/doc/img/we_proteus3ev_nrf52840.jpg similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/doc/img/we_proteus3ev_nrf52840.jpg rename to boards/we/proteus3ev/doc/img/we_proteus3ev_nrf52840.jpg diff --git a/boards/we/proteus3ev/doc/index.rst b/boards/we/proteus3ev/doc/index.rst new file mode 100644 index 00000000000000..59c5116d50940d --- /dev/null +++ b/boards/we/proteus3ev/doc/index.rst @@ -0,0 +1,164 @@ +.. _we_proteus3ev_nrf52840: + +Würth Elektronik Proteus-III-EV +############################### + +Overview +******** + +The Proteus-III-EV (evaluation board) hardware provides support +for the Proteus-III radio module that uses the Nordic Semiconductor +nRF52840 ARM Cortex-M4F CPU and the following devices: + +* :abbr:`ADC (Analog to Digital Converter)` +* CLOCK +* FLASH +* :abbr:`GPIO (General Purpose Input Output)` +* :abbr:`I2C (Inter-Integrated Circuit)` +* :abbr:`MPU (Memory Protection Unit)` +* :abbr:`NVIC (Nested Vectored Interrupt Controller)` +* :abbr:`PWM (Pulse Width Modulation)` +* RADIO (Bluetooth Low Energy and 802.15.4) +* :abbr:`RTC (nRF RTC System Clock)` +* Segger RTT (RTT Console) +* :abbr:`SPI (Serial Peripheral Interface)` +* :abbr:`UART (Universal asynchronous receiver-transmitter)` +* :abbr:`WDT (Watchdog Timer)` + +.. figure:: img/we_proteus3ev_nrf52840.jpg + :align: center + :alt: Proteus-III EV + + Proteus-III EV (Credit: Würth Elektronik) + +More information about the radio module can be found the Würth Elektronik +web page https://www.we-online.com/katalog/de/PROTEUS-III . + + +Hardware +******** + +Proteus-III radio module provides only the internal oscillators. The +frequency of the slow clock is 32.768 kHz. The frequency of the main +clock is 32 MHz. + +Supported Features +================== + +The we_proteus3ev/nrf52840 board configuration supports the following +hardware features: + ++-----------+------------+----------------------+ +| Interface | Controller | Driver/Component | ++===========+============+======================+ +| ADC | on-chip | adc | ++-----------+------------+----------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+----------------------+ +| FLASH | on-chip | flash | ++-----------+------------+----------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+----------------------+ +| I2C(M) | on-chip | i2c | ++-----------+------------+----------------------+ +| MPU | on-chip | arch/arm | ++-----------+------------+----------------------+ +| NVIC | on-chip | arch/arm | ++-----------+------------+----------------------+ +| PWM | on-chip | pwm | ++-----------+------------+----------------------+ +| RADIO | on-chip | Bluetooth, | +| | | ieee802154 | ++-----------+------------+----------------------+ +| RTC | on-chip | system clock | ++-----------+------------+----------------------+ +| RTT | Segger | console | ++-----------+------------+----------------------+ +| SPI(M/S) | on-chip | spi | ++-----------+------------+----------------------+ +| UART | on-chip | serial | ++-----------+------------+----------------------+ +| WDT | on-chip | watchdog | ++-----------+------------+----------------------+ + +Other hardware features are not supported by the Zephyr kernel. + +Connections and IOs +=================== + +LED +--- + +* LED1 = P0.00 +* LED2 = P0.01 + +Push buttons +------------ + +* BUTTON1 = SW1 = P0.03 + +Programming and Debugging +************************* + +Applications for the ``we_proteus3ev/nrf52840`` board configuration can be +built, flashed, and debugged in the usual way. See +:ref:`build_an_application` and :ref:`application_run` for more details on +building and running. + +Flashing +======== + +Follow the instructions in the :ref:`nordic_segger` page to install +and configure all the necessary software. Further information can be +found in :ref:`nordic_segger_flashing`. Then build and flash +applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Here is an example for the :ref:`hello_world` application. + +First, run your favorite terminal program to listen for output. + +.. code-block:: console + + $ minicom -D -b 115200 + +Replace :code:`` with the port where the board Proteus-III-EV +can be found. For example, under Linux, :code:`/dev/ttyACM0`. + +Then build and flash the application in the usual way. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: we_proteus3ev/nrf52840 + :goals: build flash + +Debugging +========= + +Refer to the :ref:`nordic_segger` page to learn about debugging Nordic +boards with a Segger IC. + +Testing the LEDs and buttons in the Proteus-III-EV +************************************************** + +There are 2 samples that allow you to test that the buttons (switches) and +LEDs on the board are working properly with Zephyr: + +.. code-block:: console + + samples/basic/blinky + samples/basic/button + +You can build and flash the examples to make sure Zephyr is running correctly +on your board. The button and LED definitions can be found in +:zephyr_file:`boards/wurth_elektronik/proteus3ev/we_proteus3ev_nrf52840.dts`. + +References +********** + +.. target-notes:: + +.. _Proteus-III radio module website: https://www.we-online.com/katalog/de/PROTEUS-III +.. _Nordic Semiconductor Infocenter: https://infocenter.nordicsemi.com +.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html +.. _nRF52840 Product Specification: http://infocenter.nordicsemi.com/pdf/nRF52840_PS_v1.0.pdf diff --git a/boards/arm/we_proteus3ev_nrf52840/pre_dt_board.cmake b/boards/we/proteus3ev/pre_dt_board.cmake similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/pre_dt_board.cmake rename to boards/we/proteus3ev/pre_dt_board.cmake diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840-pinctrl.dtsi b/boards/we/proteus3ev/we_proteus3ev_nrf52840-pinctrl.dtsi similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840-pinctrl.dtsi rename to boards/we/proteus3ev/we_proteus3ev_nrf52840-pinctrl.dtsi diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.dts b/boards/we/proteus3ev/we_proteus3ev_nrf52840.dts similarity index 100% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.dts rename to boards/we/proteus3ev/we_proteus3ev_nrf52840.dts diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.yaml b/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml similarity index 88% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.yaml rename to boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml index 544029d3d9cd78..5a771ca28b386c 100644 --- a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840.yaml +++ b/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml @@ -1,7 +1,7 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -identifier: we_proteus3ev_nrf52840 +identifier: we_proteus3ev/nrf52840 name: we_proteus3ev_nrf52840 type: mcu arch: arm diff --git a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840_defconfig b/boards/we/proteus3ev/we_proteus3ev_nrf52840_defconfig similarity index 81% rename from boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840_defconfig rename to boards/we/proteus3ev/we_proteus3ev_nrf52840_defconfig index a7687b6b541ceb..62452ad517ef6c 100644 --- a/boards/arm/we_proteus3ev_nrf52840/we_proteus3ev_nrf52840_defconfig +++ b/boards/we/proteus3ev/we_proteus3ev_nrf52840_defconfig @@ -1,10 +1,6 @@ # Copyright (c) 2022 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_NRF52X=y -CONFIG_SOC_NRF52840_QIAA=y -CONFIG_BOARD_WE_PROTEUS3EV_NRF52840=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/weact/blackpill_f401cc/Kconfig.blackpill_f401cc b/boards/weact/blackpill_f401cc/Kconfig.blackpill_f401cc new file mode 100644 index 00000000000000..10068a79a76f7e --- /dev/null +++ b/boards/weact/blackpill_f401cc/Kconfig.blackpill_f401cc @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACKPILL_F401CC + select SOC_STM32F401XC diff --git a/boards/weact/blackpill_f401cc/Kconfig.defconfig b/boards/weact/blackpill_f401cc/Kconfig.defconfig new file mode 100644 index 00000000000000..dff0982bd8bddd --- /dev/null +++ b/boards/weact/blackpill_f401cc/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2022 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# F401CE based Black Pill V3.0+ board board configuration + +if BOARD_BLACKPILL_F401CC + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACKPILL_F401CC diff --git a/boards/arm/blackpill_f401cc/blackpill_f401cc.dts b/boards/weact/blackpill_f401cc/blackpill_f401cc.dts similarity index 100% rename from boards/arm/blackpill_f401cc/blackpill_f401cc.dts rename to boards/weact/blackpill_f401cc/blackpill_f401cc.dts diff --git a/boards/arm/blackpill_f401cc/blackpill_f401cc.yaml b/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml similarity index 100% rename from boards/arm/blackpill_f401cc/blackpill_f401cc.yaml rename to boards/weact/blackpill_f401cc/blackpill_f401cc.yaml diff --git a/boards/arm/blackpill_f401cc/blackpill_f401cc_defconfig b/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig similarity index 87% rename from boards/arm/blackpill_f401cc/blackpill_f401cc_defconfig rename to boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig index 416cdff51e6ff9..180ea77ffc986e 100644 --- a/boards/arm/blackpill_f401cc/blackpill_f401cc_defconfig +++ b/boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig @@ -1,9 +1,6 @@ # Copyright (c) 2022 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XC=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f401cc/board.cmake b/boards/weact/blackpill_f401cc/board.cmake similarity index 100% rename from boards/arm/blackpill_f401cc/board.cmake rename to boards/weact/blackpill_f401cc/board.cmake diff --git a/boards/weact/blackpill_f401cc/board.yml b/boards/weact/blackpill_f401cc/board.yml new file mode 100644 index 00000000000000..e72de492ef869d --- /dev/null +++ b/boards/weact/blackpill_f401cc/board.yml @@ -0,0 +1,5 @@ +board: + name: blackpill_f401cc + vendor: weact + socs: + - name: stm32f401xc diff --git a/boards/arm/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg b/boards/weact/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg similarity index 100% rename from boards/arm/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg rename to boards/weact/blackpill_f401cc/doc/img/Blackpill_Pinout.jpg diff --git a/boards/arm/blackpill_f401cc/doc/img/blackpill-v3.jpg b/boards/weact/blackpill_f401cc/doc/img/blackpill-v3.jpg similarity index 100% rename from boards/arm/blackpill_f401cc/doc/img/blackpill-v3.jpg rename to boards/weact/blackpill_f401cc/doc/img/blackpill-v3.jpg diff --git a/boards/weact/blackpill_f401cc/doc/index.rst b/boards/weact/blackpill_f401cc/doc/index.rst new file mode 100644 index 00000000000000..79e30862e87ad5 --- /dev/null +++ b/boards/weact/blackpill_f401cc/doc/index.rst @@ -0,0 +1,173 @@ +.. _blackpill_f401cc: + +WeAct Studio Black Pill V1.2 +############################ + +Overview +******** + +The WeAct Black Pill V1.2 Board is an extremely low cost and bare-bones +development board featuring the STM32F401CC, see `STM32F401CC website`_. +This is the 48-pin variant of the STM32F401x series, +see `STM32F401x reference manual`_. More info about the board available +`here `_ and on `WeAct Github`_. + +.. image:: img/blackpill-v3.jpg + :align: center + :alt: Black Pill V3.0+ + +Hardware +******** + +The STM32F401CC based Black Pill V3.0+ Board provides the following +hardware components: + +- STM32F401CCU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 256 KB Flash +- 64 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr blackpill_f401ce board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig` + +Pin Mapping +=========== + +Available pins: +--------------- +.. image:: img/Blackpill_Pinout.jpg + :align: center + :alt: Black Pill V1.2 Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- USER_PB : PA0 +- USER_LED : PC13 + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 84MHz, which is the maximum possible frequency +to achieve a stable USB clock (42MHz). + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: blackpill_f401cc + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F401CC website: + https://www.st.com/en/microcontrollers/stm32f401cc.html + +.. _STM32F401x reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f401ce/support/openocd.cfg b/boards/weact/blackpill_f401cc/support/openocd.cfg similarity index 100% rename from boards/arm/blackpill_f401ce/support/openocd.cfg rename to boards/weact/blackpill_f401cc/support/openocd.cfg diff --git a/boards/weact/blackpill_f401ce/Kconfig.blackpill_f401ce b/boards/weact/blackpill_f401ce/Kconfig.blackpill_f401ce new file mode 100644 index 00000000000000..9b638f3cd2b121 --- /dev/null +++ b/boards/weact/blackpill_f401ce/Kconfig.blackpill_f401ce @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Kalyan Sriram +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACKPILL_F401CE + select SOC_STM32F401XE diff --git a/boards/weact/blackpill_f401ce/Kconfig.defconfig b/boards/weact/blackpill_f401ce/Kconfig.defconfig new file mode 100644 index 00000000000000..57ff4a7736981e --- /dev/null +++ b/boards/weact/blackpill_f401ce/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 Kalyan Sriram +# SPDX-License-Identifier: Apache-2.0 + +# F401CE based Black Pill V3.0+ board board configuration + +if BOARD_BLACKPILL_F401CE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACKPILL_F401CE diff --git a/boards/arm/blackpill_f401ce/blackpill_f401ce.dts b/boards/weact/blackpill_f401ce/blackpill_f401ce.dts similarity index 100% rename from boards/arm/blackpill_f401ce/blackpill_f401ce.dts rename to boards/weact/blackpill_f401ce/blackpill_f401ce.dts diff --git a/boards/arm/blackpill_f401ce/blackpill_f401ce.yaml b/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml similarity index 100% rename from boards/arm/blackpill_f401ce/blackpill_f401ce.yaml rename to boards/weact/blackpill_f401ce/blackpill_f401ce.yaml diff --git a/boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig b/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig similarity index 86% rename from boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig rename to boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig index e2fdc023a5ba7c..8f08a2bfe96c87 100644 --- a/boards/arm/blackpill_f401ce/blackpill_f401ce_defconfig +++ b/boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F401XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f401ce/board.cmake b/boards/weact/blackpill_f401ce/board.cmake similarity index 100% rename from boards/arm/blackpill_f401ce/board.cmake rename to boards/weact/blackpill_f401ce/board.cmake diff --git a/boards/weact/blackpill_f401ce/board.yml b/boards/weact/blackpill_f401ce/board.yml new file mode 100644 index 00000000000000..83d26820943cf5 --- /dev/null +++ b/boards/weact/blackpill_f401ce/board.yml @@ -0,0 +1,5 @@ +board: + name: blackpill_f401ce + vendor: weact + socs: + - name: stm32f401xe diff --git a/boards/arm/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg b/boards/weact/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg similarity index 100% rename from boards/arm/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg rename to boards/weact/blackpill_f401ce/doc/img/Blackpill_Pinout.jpg diff --git a/boards/arm/blackpill_f401ce/doc/img/blackpill-v3.jpg b/boards/weact/blackpill_f401ce/doc/img/blackpill-v3.jpg similarity index 100% rename from boards/arm/blackpill_f401ce/doc/img/blackpill-v3.jpg rename to boards/weact/blackpill_f401ce/doc/img/blackpill-v3.jpg diff --git a/boards/weact/blackpill_f401ce/doc/index.rst b/boards/weact/blackpill_f401ce/doc/index.rst new file mode 100644 index 00000000000000..eb4983577ae13f --- /dev/null +++ b/boards/weact/blackpill_f401ce/doc/index.rst @@ -0,0 +1,178 @@ +.. _blackpill_f401ce: + +WeAct Studio Black Pill V3.0 +############################ + +Overview +******** + +The WeAct Black Pill V3.0 Board is an extremely low cost and bare-bones +development board featuring the STM32F401CE, see `STM32F401CE website`_. +This is the 48-pin variant of the STM32F401x series, +see `STM32F401x reference manual`_. More info about the board available +`here `_ and on `WeAct Github`_. + +.. image:: img/blackpill-v3.jpg + :align: center + :alt: Black Pill V3.0+ + +Hardware +******** + +The STM32F401CE based Black Pill V3.0+ Board provides the following +hardware components: + +- STM32F401CEU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 84 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 96 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr blackpill_f401ce board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig` + +Pin Mapping +=========== + +Available pins: +--------------- +.. image:: img/Blackpill_Pinout.jpg + :align: center + :alt: Black Pill V3.0+ Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- USER_PB : PA0 +- USER_LED : PC13 + +Note on SPI pin mapping: According to the `board release notes`_, there was a brief +change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. +This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using +V2.0 and en external flash, the pinmux will need to be modified accordingly. + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 84MHz, which is the maximum possible frequency +to achieve a stable USB clock (42MHz). + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: blackpill_f401ce + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F401CEU6-WeAct-Black-Pill-V3.0.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F401CE website: + https://www.st.com/en/microcontrollers/stm32f401ce.html + +.. _STM32F401x reference manual: + https://www.st.com/resource/en/reference_manual/dm00096844.pdf diff --git a/boards/arm/blackpill_f411ce/support/openocd.cfg b/boards/weact/blackpill_f401ce/support/openocd.cfg similarity index 100% rename from boards/arm/blackpill_f411ce/support/openocd.cfg rename to boards/weact/blackpill_f401ce/support/openocd.cfg diff --git a/boards/weact/blackpill_f411ce/Kconfig.blackpill_f411ce b/boards/weact/blackpill_f411ce/Kconfig.blackpill_f411ce new file mode 100644 index 00000000000000..c6d1b632da19c5 --- /dev/null +++ b/boards/weact/blackpill_f411ce/Kconfig.blackpill_f411ce @@ -0,0 +1,5 @@ +# Copyright (c) 2020 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_BLACKPILL_F411CE + select SOC_STM32F411XE diff --git a/boards/weact/blackpill_f411ce/Kconfig.defconfig b/boards/weact/blackpill_f411ce/Kconfig.defconfig new file mode 100644 index 00000000000000..a14284ed4c5fb3 --- /dev/null +++ b/boards/weact/blackpill_f411ce/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 Brian Bradley +# SPDX-License-Identifier: Apache-2.0 + +# F411CE based Black Pill V2.0+ board board configuration + +if BOARD_BLACKPILL_F411CE + +config SPI_STM32_INTERRUPT + default y + depends on SPI + +endif # BOARD_BLACKPILL_F411CE diff --git a/boards/arm/blackpill_f411ce/blackpill_f411ce.dts b/boards/weact/blackpill_f411ce/blackpill_f411ce.dts similarity index 100% rename from boards/arm/blackpill_f411ce/blackpill_f411ce.dts rename to boards/weact/blackpill_f411ce/blackpill_f411ce.dts diff --git a/boards/arm/blackpill_f411ce/blackpill_f411ce.yaml b/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml similarity index 100% rename from boards/arm/blackpill_f411ce/blackpill_f411ce.yaml rename to boards/weact/blackpill_f411ce/blackpill_f411ce.yaml diff --git a/boards/arm/blackpill_f411ce/blackpill_f411ce_defconfig b/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig similarity index 86% rename from boards/arm/blackpill_f411ce/blackpill_f411ce_defconfig rename to boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig index 1c1d2d9692591b..8f08a2bfe96c87 100644 --- a/boards/arm/blackpill_f411ce/blackpill_f411ce_defconfig +++ b/boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig @@ -1,8 +1,5 @@ # SPDX-License-Identifier: Apache-2.0 -CONFIG_SOC_SERIES_STM32F4X=y -CONFIG_SOC_STM32F411XE=y - # Enable MPU CONFIG_ARM_MPU=y diff --git a/boards/arm/blackpill_f411ce/board.cmake b/boards/weact/blackpill_f411ce/board.cmake similarity index 100% rename from boards/arm/blackpill_f411ce/board.cmake rename to boards/weact/blackpill_f411ce/board.cmake diff --git a/boards/weact/blackpill_f411ce/board.yml b/boards/weact/blackpill_f411ce/board.yml new file mode 100644 index 00000000000000..b145c5e7f019ef --- /dev/null +++ b/boards/weact/blackpill_f411ce/board.yml @@ -0,0 +1,5 @@ +board: + name: blackpill_f411ce + vendor: weact + socs: + - name: stm32f411xe diff --git a/boards/arm/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg b/boards/weact/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg similarity index 100% rename from boards/arm/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg rename to boards/weact/blackpill_f411ce/doc/img/Blackpill_Pinout.jpg diff --git a/boards/arm/blackpill_f411ce/doc/img/blackpill-v2.jpg b/boards/weact/blackpill_f411ce/doc/img/blackpill-v2.jpg similarity index 100% rename from boards/arm/blackpill_f411ce/doc/img/blackpill-v2.jpg rename to boards/weact/blackpill_f411ce/doc/img/blackpill-v2.jpg diff --git a/boards/weact/blackpill_f411ce/doc/index.rst b/boards/weact/blackpill_f411ce/doc/index.rst new file mode 100644 index 00000000000000..f190d7ea64a0df --- /dev/null +++ b/boards/weact/blackpill_f411ce/doc/index.rst @@ -0,0 +1,178 @@ +.. _blackpill_f411ce: + +WeAct Studio Black Pill V2.0 +############################ + +Overview +******** + +The WeAct Black Pill V2.0 Board is an extremely low cost and bare-bones +development board featuring the STM32F411CE, see `STM32F411CE website`_. +This is the 48-pin variant of the STM32F411x series, +see `STM32F411x reference manual`_. More info about the board available +`here `_ and on `WeAct Github`_. + +.. image:: img/blackpill-v2.jpg + :align: center + :alt: Black Pill V2.0+ + +Hardware +******** + +The STM32F411CE based Black Pill V2.0+ Board provides the following +hardware components: + +- STM32F411CEU6 in UFQFPN48 package +- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU +- 100 MHz max CPU frequency +- VDD from 1.7 V to 3.6 V +- 512 KB Flash +- 128 KB SRAM +- GPIO with external interrupt capability +- 1x12-bit, 2.4 MSPS ADC with 16 channels +- DMA Controller +- Up to 11 Timers (six 16-bit, two 32-bit, two watchdog timers and a SysTick timer) +- USART/UART (3) +- I2C (3) +- SPI/I2S (5) +- SDIO +- USB 2.0 full-speed device/host/OTG controller with on-chip PHY +- CRC calculation unit +- 96-bit unique ID +- RTC + +Supported Features +================== + +The Zephyr blackpill_f411ce board configuration supports the following +hardware features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| SYSTICK | on-chip | system clock | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++------------+------------+-------------------------------------+ +| FLASH | on-chip | flash | ++------------+------------+-------------------------------------+ +| SPI | on-chip | spi | ++------------+------------+-------------------------------------+ +| I2C | on-chip | i2c | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB OTG FS | on-chip | USB device | ++------------+------------+-------------------------------------+ + +The default configuration can be found in +:zephyr_file:`boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig` + +Pin Mapping +=========== + +Available pins: +--------------- +.. image:: img/Blackpill_Pinout.jpg + :align: center + :alt: Black Pill V2.0+ Pinout + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1 TX/RX : PA9/PA10 +- I2C1 SCL/SDA : PB8/PB9 +- SPI1 CS/SCK/MISO/MOSI : PA4/PA5/PA6/PA7 (Routed to footprint for external flash) +- PWM_4_CH1 : PB6 +- PWM_4_CH2 : PB7 +- ADC_1 : PA1 +- USER_PB : PA0 +- USER_LED : PC13 + +Note on SPI pin mapping: According to the `board release notes`_, there was a brief +change for V2.0 specifically where MISO was routed to PB4 for the flash footprint. +This was reverted for V2.1+ so that the flash DO pin was routed back to PA6. If using +V2.0 and en external flash, the pinmux will need to be modified accordingly. + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is +32.768 kHz. The frequency of the main clock (HSE) is 25 MHz. + +The default configuration sources the system clock from the PLL, which is +derived from HSE, and is set at 96MHz, which is the maximum possible frequency +to achieve a stable USB clock (48MHz). + +Programming and Debugging +************************* + +There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 pin. + +Flashing +======== + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an Application +----------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: blackpill_f411ce + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, +and attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO +pins on that header. + +References +********** + +.. target-notes:: + +.. _board release notes: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1/blob/master/HDK/README.md + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _WeAct Github: + https://github.com/WeActStudio/WeActStudio.MiniSTM32F4x1 + +.. _stm32-base-board-page: + https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0.html + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32F411CE website: + https://www.st.com/en/microcontrollers/stm32f411ce.html + +.. _STM32F411x reference manual: + https://www.st.com/resource/en/reference_manual/dm00119316.pdf diff --git a/boards/arm/stm32f401_mini/support/openocd.cfg b/boards/weact/blackpill_f411ce/support/openocd.cfg similarity index 100% rename from boards/arm/stm32f401_mini/support/openocd.cfg rename to boards/weact/blackpill_f411ce/support/openocd.cfg diff --git a/boards/weact/index.rst b/boards/weact/index.rst new file mode 100644 index 00000000000000..21a31a003129a0 --- /dev/null +++ b/boards/weact/index.rst @@ -0,0 +1,10 @@ +.. _boards-weact: + +WeAct Studio +############ + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/weact/stm32g431_core/Kconfig.weact_stm32g431_core b/boards/weact/stm32g431_core/Kconfig.weact_stm32g431_core new file mode 100644 index 00000000000000..2bd370e9311d2a --- /dev/null +++ b/boards/weact/stm32g431_core/Kconfig.weact_stm32g431_core @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Andreas Sandberg +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_WEACT_STM32G431_CORE + select SOC_STM32G431XX diff --git a/boards/arm/weact_stm32g431_core/board.cmake b/boards/weact/stm32g431_core/board.cmake similarity index 100% rename from boards/arm/weact_stm32g431_core/board.cmake rename to boards/weact/stm32g431_core/board.cmake diff --git a/boards/weact/stm32g431_core/board.yml b/boards/weact/stm32g431_core/board.yml new file mode 100644 index 00000000000000..359e74ed0d757e --- /dev/null +++ b/boards/weact/stm32g431_core/board.yml @@ -0,0 +1,5 @@ +board: + name: weact_stm32g431_core + vendor: weact + socs: + - name: stm32g431xx diff --git a/boards/weact/stm32g431_core/doc/index.rst b/boards/weact/stm32g431_core/doc/index.rst new file mode 100644 index 00000000000000..7ebfbd02b29192 --- /dev/null +++ b/boards/weact/stm32g431_core/doc/index.rst @@ -0,0 +1,147 @@ +.. _weact_stm32g431_core: + +WeAct Studio STM32G431 Core Board +################################# + +The WeAct STM32G431 Core Board is a low-cost bare-bones STM32G431-based development +board. See the `STM32G431CB website`_ for more information about the MCU. More information +about the board, including schematics, is available from the `WeAct GitHub`_. + +Modifications USB-C Power Delivery +********************************** + +The board does not support USB-C PD in its standard configuration. To enable USB-C PD, CC1 +and CC2 need to be disconnected from their pull-down resistors and be connected to PB6 and +PB4 respectively. Dead battery support requires PA9 and PA10 to be routed to CC1 and +CC2. VBUS also needs to be connected to the MCU through a voltage divider. + +The pull-downs are disconnected by removing the zero-Ohm resistors on SB8 and SB9 next to +the USB-C connector. SB3, SB5, SB6, and SB7 then need to be closed to connect the CCx +lines to the MCU. The voltage divider is connected to PB2 by closing SB4. + +After these modifications have been made, PA9, PA10, PB2, PB4, and PB6 should be +considered reserved for USB-C and not available for other applications. + +.. warning:: + The internal USB DFU boot loader may not work correctly with machines that respect USB + PD signaling unless dead battery support has been enabled. A USB-C to USB-A adapter or + programming using the SWD port can be used as a workaround. + + +Supported Features +================== + +The Zephyr weact_stm32g431_core board configuration supports the following hardware +features: + ++------------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++============+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++------------+------------+-------------------------------------+ +| UART | on-chip | serial port | ++------------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++------------+------------+-------------------------------------+ +| ADC | on-chip | ADC Controller | ++------------+------------+-------------------------------------+ +| USB | on-chip | USB device | ++------------+------------+-------------------------------------+ +| UCPD | on-chip | ucpd | ++------------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + +:zephyr_file:`boards/weact/stm32g431_core/weact_stm32g431_core_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_2 TX/RX : PA2/PA3 +- UCPD1 CCx : PB6/PB4 (not connected by default) +- UCPD1 DBCCx : PA9/PA10 (not connected by default) +- BUTTON (User) : PC13 +- BUTTON (BOOT0) : PB8 +- LED0 : PC6 +- ADC (VBUS) : PB2 + +The ADC is disabled by default since the VBUS voltage divider is not connected in the +board's standard configuration. + + +Hardware Configuration +---------------------- ++---------------+---------+-----------------------------------------------+ +| Solder bridge | Default | Description | ++===============+=========+===============================================+ +| SB1/SB2 | Open | Route PC14/PC15 (LSE) to header | ++---------------+---------+-----------------------------------------------+ +| SB6/SB7 | Open | Connect PB4/PB6 (UCPD1_CCx) to USB-C CCx pins | ++---------------+---------+-----------------------------------------------+ +| SB3/SB5 | Open | Connect PA9/PA10 (UCPD1_DBCCx) to to PB6/PB4 | ++---------------+---------+-----------------------------------------------+ +| SB4 | Open | Connect PB2 to VBUS voltage divider | ++---------------+---------+-----------------------------------------------+ +| SB8/SB9 | Closed | Connect USB-CCx to pull-down resistors | ++---------------+---------+-----------------------------------------------+ +| SB10 | Open | VBUS protection diode bypass | ++---------------+---------+-----------------------------------------------+ + + +Clock Sources +------------- + +The board has two external oscillators. The frequency of the slow clock (LSE) is 32.768 +kHz. The frequency of the main clock (HSE) is 8 MHz. + +The default configuration sources the system clock from the PLL, which is derived from +HSE, and is set at 144 MHz. The 48 MHz clock used by the USB interface is derived from the +PLL instead of the internal 48 MHz oscillator. + +Programming and Debugging +************************* + +The MCU is normally programmed using the ROM bootloader or the exposed SWD port. + +Please note that some laptops may not detect the ROM bootloader correctly if the CCx +pull-downs have been disconnected by opening SB8 and SB9 unless dead battery support has +been enabled by closing SB3 and SB5. A USB-C to USB-A adapter can be used as a workaround +if this is a problem. + +Flashing an Application +======================= + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode by +keeping the BOOT0 switch pressed while pressing and releasing the NRST switch. + +The dfu-util runner is supported on this board and so a sample can be built and tested +easily. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: weact_stm32g431_core + :goals: build flash + +Debugging +========= + +The board can be debugged by installing the included 100 mil (0.1 inch) header, and +attaching an SWD debugger to the 3V3 (3.3V), GND, SCK, and DIO pins on that header. + + +References +********** + +.. target-notes:: + +.. _WeAct GitHub: + https://github.com/WeActStudio/WeActStudio.STM32G431CoreBoard + +.. _STM32G431CB website: + https://www.st.com/en/microcontrollers-microprocessors/stm32g431cb.html + +.. _STM32F401x reference manual: + https://www.st.com/resource/en/reference_manual/rm0440-stm32g4-series-advanced-armbased-32bit-mcus-stmicroelectronics.pdf diff --git a/boards/arm/weact_stm32g431_core/support/openocd.cfg b/boards/weact/stm32g431_core/support/openocd.cfg similarity index 100% rename from boards/arm/weact_stm32g431_core/support/openocd.cfg rename to boards/weact/stm32g431_core/support/openocd.cfg diff --git a/boards/arm/weact_stm32g431_core/weact_stm32g431_core.dts b/boards/weact/stm32g431_core/weact_stm32g431_core.dts similarity index 100% rename from boards/arm/weact_stm32g431_core/weact_stm32g431_core.dts rename to boards/weact/stm32g431_core/weact_stm32g431_core.dts diff --git a/boards/arm/weact_stm32g431_core/weact_stm32g431_core.yaml b/boards/weact/stm32g431_core/weact_stm32g431_core.yaml similarity index 100% rename from boards/arm/weact_stm32g431_core/weact_stm32g431_core.yaml rename to boards/weact/stm32g431_core/weact_stm32g431_core.yaml diff --git a/boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig b/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig similarity index 83% rename from boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig rename to boards/weact/stm32g431_core/weact_stm32g431_core_defconfig index 0c9d0e2a185683..19919b198ca2b8 100644 --- a/boards/arm/weact_stm32g431_core/weact_stm32g431_core_defconfig +++ b/boards/weact/stm32g431_core/weact_stm32g431_core_defconfig @@ -4,9 +4,6 @@ # SPDX-License-Identifier: Apache-2.0 # -CONFIG_SOC_SERIES_STM32G4X=y -CONFIG_SOC_STM32G431XX=y - CONFIG_CLOCK_CONTROL=y CONFIG_PINCTRL=y diff --git a/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig b/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig new file mode 100644 index 00000000000000..85fdb26695695a --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ESP32S2 LOLIN S2 MINI board configuration + +# Copyright (c) 2023 Google, LLC +# SPDX-License-Identifier: Apache-2.0 + +config ENTROPY_GENERATOR + default y + +config HEAP_MEM_POOL_ADD_SIZE_BOARD + int + default 32768 if WIFI + default 4096 diff --git a/boards/wemos/esp32s2_lolin_mini/Kconfig.esp32s2_lolin_mini b/boards/wemos/esp32s2_lolin_mini/Kconfig.esp32s2_lolin_mini new file mode 100644 index 00000000000000..fe7f72a138ba0b --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/Kconfig.esp32s2_lolin_mini @@ -0,0 +1,7 @@ +# ESP32S2 LOLIN S2 MINI board configuration + +# Copyright (c) 2023 Google, LLC +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_ESP32S2_LOLIN_MINI + select SOC_ESP32S2_FN4R2 diff --git a/boards/xtensa/yd_esp32/board.cmake b/boards/wemos/esp32s2_lolin_mini/board.cmake similarity index 100% rename from boards/xtensa/yd_esp32/board.cmake rename to boards/wemos/esp32s2_lolin_mini/board.cmake diff --git a/boards/wemos/esp32s2_lolin_mini/board.yml b/boards/wemos/esp32s2_lolin_mini/board.yml new file mode 100644 index 00000000000000..7df1267c2146f8 --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/board.yml @@ -0,0 +1,5 @@ +board: + name: esp32s2_lolin_mini + vendor: wemos + socs: + - name: esp32s2 diff --git a/boards/xtensa/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg b/boards/wemos/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg rename to boards/wemos/esp32s2_lolin_mini/doc/img/esp32_s2_lolin_mini.jpg diff --git a/boards/xtensa/esp32s2_lolin_mini/doc/index.rst b/boards/wemos/esp32s2_lolin_mini/doc/index.rst similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/doc/index.rst rename to boards/wemos/esp32s2_lolin_mini/doc/index.rst diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi similarity index 100% rename from boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi rename to boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini-pinctrl.dtsi diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.dts b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts similarity index 98% rename from boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.dts rename to boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts index 3ce00f8bdb8c22..53a598ad0ded66 100644 --- a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.dts +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts @@ -11,7 +11,7 @@ #include "esp32s2_lolin_mini-pinctrl.dtsi" / { - model = "esp32s2_lolin_mini"; + model = "Wemos ESP32S2-Lolin Mini"; compatible = "espressif,esp32s2"; aliases { diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml similarity index 93% rename from boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml rename to boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml index 3764f5eddd74f7..763b8c838f492c 100644 --- a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.yaml @@ -12,3 +12,4 @@ testing: ignore_tags: - net - bluetooth +vendor: wemos diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig new file mode 100644 index 00000000000000..f029cac9e9e77b --- /dev/null +++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_MAIN_STACK_SIZE=2048 + +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_CONSOLE=y + +CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_saola/support/openocd.cfg b/boards/wemos/esp32s2_lolin_mini/support/openocd.cfg similarity index 100% rename from boards/xtensa/esp32s2_saola/support/openocd.cfg rename to boards/wemos/esp32s2_lolin_mini/support/openocd.cfg diff --git a/boards/wemos/index.rst b/boards/wemos/index.rst new file mode 100644 index 00000000000000..200fbcae8a76da --- /dev/null +++ b/boards/wemos/index.rst @@ -0,0 +1,10 @@ +.. _boards-wemos: + +Wemos +##### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/wiznet/index.rst b/boards/wiznet/index.rst new file mode 100644 index 00000000000000..6fe6eeac028b8e --- /dev/null +++ b/boards/wiznet/index.rst @@ -0,0 +1,10 @@ +.. _boards-wiznet: + +WIZnet +###### + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/wiznet/w5500_evb_pico/Kconfig.defconfig b/boards/wiznet/w5500_evb_pico/Kconfig.defconfig new file mode 100644 index 00000000000000..a159b56f52ab2e --- /dev/null +++ b/boards/wiznet/w5500_evb_pico/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2021 Yonatan Schachter +# Copyright (c) 2023 Ian Wakely +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_W5500_EVB_PICO + +config RP2_FLASH_W25Q080 + default y + +if NETWORKING + +config NET_L2_ETHERNET + default y + +endif # NETWORKING + +if I2C_DW + +config I2C_DW_CLOCK_SPEED + default 125 + +endif # I2C_DW + +config USB_SELF_POWERED + default n + +endif # BOARD_W5500_EVB_PICO diff --git a/boards/wiznet/w5500_evb_pico/Kconfig.w5500_evb_pico b/boards/wiznet/w5500_evb_pico/Kconfig.w5500_evb_pico new file mode 100644 index 00000000000000..d6326dffedbd53 --- /dev/null +++ b/boards/wiznet/w5500_evb_pico/Kconfig.w5500_evb_pico @@ -0,0 +1,6 @@ +# Copyright (c) 2021 Yonatan Schachter +# Copyright (c) 2023 Ian Wakely +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_W5500_EVB_PICO + select SOC_RP2040 diff --git a/boards/arm/w5500_evb_pico/board.cmake b/boards/wiznet/w5500_evb_pico/board.cmake similarity index 100% rename from boards/arm/w5500_evb_pico/board.cmake rename to boards/wiznet/w5500_evb_pico/board.cmake diff --git a/boards/wiznet/w5500_evb_pico/board.yml b/boards/wiznet/w5500_evb_pico/board.yml new file mode 100644 index 00000000000000..17ce17eea15038 --- /dev/null +++ b/boards/wiznet/w5500_evb_pico/board.yml @@ -0,0 +1,5 @@ +board: + name: w5500_evb_pico + vendor: wiznet + socs: + - name: rp2040 diff --git a/boards/arm/w5500_evb_pico/doc/img/w5500_evb_pico_side.png b/boards/wiznet/w5500_evb_pico/doc/img/w5500_evb_pico_side.png similarity index 100% rename from boards/arm/w5500_evb_pico/doc/img/w5500_evb_pico_side.png rename to boards/wiznet/w5500_evb_pico/doc/img/w5500_evb_pico_side.png diff --git a/boards/arm/w5500_evb_pico/doc/index.rst b/boards/wiznet/w5500_evb_pico/doc/index.rst similarity index 100% rename from boards/arm/w5500_evb_pico/doc/index.rst rename to boards/wiznet/w5500_evb_pico/doc/index.rst diff --git a/boards/arm/w5500_evb_pico/support/openocd.cfg b/boards/wiznet/w5500_evb_pico/support/openocd.cfg similarity index 100% rename from boards/arm/w5500_evb_pico/support/openocd.cfg rename to boards/wiznet/w5500_evb_pico/support/openocd.cfg diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi b/boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi similarity index 100% rename from boards/arm/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico-pinctrl.dtsi diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico.dts b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts similarity index 100% rename from boards/arm/w5500_evb_pico/w5500_evb_pico.dts rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico.dts diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico.yaml b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml similarity index 100% rename from boards/arm/w5500_evb_pico/w5500_evb_pico.yaml rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml diff --git a/boards/arm/w5500_evb_pico/w5500_evb_pico_defconfig b/boards/wiznet/w5500_evb_pico/w5500_evb_pico_defconfig similarity index 77% rename from boards/arm/w5500_evb_pico/w5500_evb_pico_defconfig rename to boards/wiznet/w5500_evb_pico/w5500_evb_pico_defconfig index ec36f85040cf66..df003531af9c87 100644 --- a/boards/arm/w5500_evb_pico/w5500_evb_pico_defconfig +++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico_defconfig @@ -1,6 +1,3 @@ -CONFIG_SOC_SERIES_RP2XXX=y -CONFIG_SOC_RP2040=y -CONFIG_BOARD_W5500_EVB_PICO=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000 CONFIG_SERIAL=y CONFIG_CONSOLE=y diff --git a/boards/x86/acrn/Kconfig.board b/boards/x86/acrn/Kconfig.board deleted file mode 100644 index e8fa3f429877ac..00000000000000 --- a/boards/x86/acrn/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ACRN - bool "ACRN User OS" - depends on SOC_IA32 - select CPU_HAS_FPU - select X86_64 diff --git a/boards/x86/acrn/Kconfig.defconfig b/boards/x86/acrn/Kconfig.defconfig deleted file mode 100644 index a1a8936e38b003..00000000000000 --- a/boards/x86/acrn/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ACRN - -config BOARD - default "acrn" - depends on BOARD_ACRN - -config MP_MAX_NUM_CPUS - default 2 - -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 32768 - depends on ACPI - -endif diff --git a/boards/x86/acrn/doc/index.rst b/boards/x86/acrn/doc/index.rst deleted file mode 100644 index 2bdaa96a817884..00000000000000 --- a/boards/x86/acrn/doc/index.rst +++ /dev/null @@ -1,302 +0,0 @@ -Building and Running Zephyr with ACRN -##################################### - -Zephyr's is capable of running as a guest under the x86 ACRN -hypervisor (see https://projectacrn.org/). The process for getting -this to work is somewhat involved, however. - -ACRN hypervisor supports a hybrid scenario where Zephyr runs in a so- -called "pre-launched" mode. This means Zephyr will access the ACRN -hypervisor directly without involving the SOS VM. This is the most -practical user scenario in the real world because Zephyr's real-time -and safety capability can be assured without influence from other -VMs. The following figure from ACRN's official documentation shows -how a hybrid scenario works: - -.. figure:: ACRN-Hybrid.jpg - :align: center - :alt: ACRN Hybrid User Scenario - :figclass: align-center - - ACRN Hybrid User Scenario - -In this tutorial, we will show you how to build a minimal running instance of Zephyr -and ACRN hypervisor to demonstrate that it works successfully. To learn more about -other features of ACRN, such as building and using the SOS VM or other guest VMs, -please refer to the Getting Started Guide for ACRN: -https://projectacrn.github.io/latest/tutorials/using_hybrid_mode_on_nuc.html - -Build your Zephyr App -********************* - -First, build the Zephyr application you want to run in ACRN as you -normally would, selecting an appropriate board: - - .. code-block:: console - - west build -b acrn_ehl_crb samples/hello_world - -In this tutorial, we will use the Intel Elkhart Lake Reference Board -(`EHL`_ CRB) since it is one of the suggested platforms for this -type of scenario. Use ``acrn_ehl_crb`` as the target board parameter. - -Note the kconfig output in ``build/zephyr/.config``, you will need to -reference that to configure ACRN later. - -The Zephyr build artifact you will need is ``build/zephyr/zephyr.bin``, -which is a raw memory image. Unlike other x86 targets, you do not -want to use ``zephyr.elf``! - -Configure and build ACRN -************************ - -First you need the source code, clone from: - - .. code-block:: console - - git clone https://github.com/projectacrn/acrn-hypervisor - -We suggest that you use versions v2.5.1 or later of the ACRN hypervisor -as they have better support for SMP in Zephyr. - -Like Zephyr, ACRN favors build-time configuration management instead -of runtime probing or control. Unlike Zephyr, ACRN has single large -configuration files instead of small easily-merged configuration -elements like kconfig defconfig files or devicetree includes. You -have to edit a big XML file to match your Zephyr configuration. -Choose an ACRN host config that matches your hardware ("ehl-crb-b" in -this case). Then find the relevant file in -``misc/config_tools/data//hybrid.xml``. - -First, find the list of ```` declarations. Each has an ``id=`` -attribute. For testing Zephyr, you will want to make sure that the -Zephyr image is ID zero. This allows you to launch ACRN with just one -VM image and avoids the need to needlessly copy large Linux blobs into -the boot filesystem. Under currently tested configurations, Zephyr -will always have a "vm_type" tag of "SAFETY_VM". - -Configure Zephyr Memory Layout -============================== - -Next, locate the load address of the Zephyr image and its entry point -address. These have to be configured manually in ACRN. Traditionally -Zephyr distributes itself as an ELF image where these addresses can be -automatically extracted, but ACRN does not know how to do that, it -only knows how to load a single contiguous region of data into memory -and jump to a specific address. - -Find the "..." tag that will look something like this: - - .. code-block:: xml - - - Zephyr - KERNEL_ZEPHYR - Zephyr_RawImage - - - 0x1000 - 0x1000 - - -The ``kern_load_addr`` tag must match the Zephyr LOCORE_BASE symbol -found in include/arch/x86/memory.ld. This is currently 0x1000 and -matches the default ACRN config. - -The ``kern_entry_addr`` tag must match the entry point in the built -``zephyr.elf`` file. You can find this with binutils, for example: - - .. code-block:: console - - $ objdump -f build/zephyr/zephyr.elf - - build/zephyr/zephyr.elf: file format elf64-x86-64 - architecture: i386:x86-64, flags 0x00000012: - EXEC_P, HAS_SYMS - start address 0x0000000000001000 - -By default this entry address is the same, at 0x1000. This has not -always been true of all configurations, however, and will likely -change in the future. - -Configure Zephyr CPUs -===================== - -Now you need to configure the CPU environment ACRN presents to the -guest. By default Zephyr builds in SMP mode, but ACRN's default -configuration gives it only one CPU. Find the value of -``CONFIG_MP_MAX_NUM_CPUS`` in the Zephyr .config file give the guest that -many CPUs in the ```` tag. For example: - - .. code-block:: xml - - - SAFETY_VM - ACRN PRE-LAUNCHED VM0 - - 0 - - - 0 - 1 - - ... - - 0 - 0 - - ... - - -To use SMP, we have to change the pcpu_id of VM0 to 0 and 1. -This configures ACRN to run Zephyr on CPU0 and CPU1. The ACRN hypervisor -and Zephyr application will not boot successfully without this change. -If you plan to run Zephyr with one CPU only, you can skip it. - -Since Zephyr is using CPU0 and CPU1, we also have to change -VM1's configuration so it runs on CPU2 and CPU3. If your ACRN setup has -additional VMs, you should change their configurations as well. - - .. code-block:: xml - - - SOS_VM - ACRN SOS VM - - 0 - - - 2 - 3 - - - 0 - 0 - - ... - - -Note that these indexes are physical CPUs on the host. When -configuring multiple guests, you probably don't want to overlap these -assignments with other guests. But for testing Zephyr simply using -CPUs 0 and 1 works fine. (Note that ehl-crb-b has four physical CPUs, -so configuring all of 0-3 will work fine too, but leave no space for -other guests to have dedicated CPUs). - -Build ACRN -========== - -Once configuration is complete, ACRN builds fairly cleanly: - - .. code-block:: console - - $ make -j BOARD=ehl-crb-b SCENARIO=hybrid - -The only build artifact you need is the ACRN multiboot image in -``build/hypervisor/acrn.bin`` - -Assemble EFI Boot Media -*********************** - -ACRN will boot on the hardware via the GNU GRUB bootloader, which is -itself launched from the EFI firmware. These need to be configured -correctly. - -Locate GRUB -=========== - -First, you will need a GRUB EFI binary that corresponds to your -hardware. In many cases, a simple upstream build from source or a -copy from a friendly Linux distribution will work. In some cases it -will not, however, and GRUB will need to be specially patched for -specific hardware. Contact your hardware support team (pause for -laughter) for clear instructions for how to build a working GRUB. In -practice you may just need to ask around and copy a binary from the -last test that worked for someone. - -Create EFI Boot Filesystem -========================== - -Now attach your boot media (e.g. a USB stick on /dev/sdb, your -hardware may differ!) to a Linux system and create an EFI boot -partition (type code 0xEF) large enough to store your boot artifacts. -This command feeds the relevant commands to fdisk directly, but you -can type them yourself if you like: - - .. code-block:: console - - # for i in n p 1 "" "" t ef w; do echo $i; done | fdisk /dev/sdb - ... - - -Now create a FAT filesystem in the new partition and mount it: - - .. code-block:: console - - # mkfs.vfat -n ACRN_ZEPHYR /dev/sdb1 - # mkdir -p /mnt/acrn - # mount /dev/sdb1 /mnt/acrn - -Copy Images and Configure GRUB -============================== - -ACRN does not have access to a runtime filesystem of its own. It -receives its guest VMs (i.e. zephyr.bin) as GRUB "multiboot" modules. -This means that we must rely on GRUB's filesystem driver. The three -files (GRUB, ACRN and Zephyr) all need to be copied into the -"/efi/boot" directory of the boot media. Note that GRUB must be named -"bootx64.efi" for the firmware to recognize it as the bootloader: - - .. code-block:: console - - # mkdir -p /mnt/acrn/efi/boot - # cp $PATH_TO_GRUB_BINARY /mnt/acrn/efi/boot/bootx64.efi - # cp $ZEPHYR_BASE/build/zephyr/zephyr.bin /mnt/acrn/efi/boot/ - # cp $PATH_TO_ACRN/build/hypervisor/acrn.bin /mnt/acrn/efi/boot/ - -At boot, GRUB will load a "efi/boot/grub.cfg" file for its runtime -configuration instructions (a feature, ironically, that both ACRN and -Zephyr lack!). This needs to load acrn.bin as the boot target and -pass it the zephyr.bin file as its first module (because Zephyr was -configured as ```` above). This minimal configuration will -work fine for all but the weirdest hardware (i.e. "hd0" is virtually -always the boot filesystem from which grub loaded), no need to fiddle -with GRUB plugins or menus or timeouts: - - .. code-block:: console - - # cat > /mnt/acrn/efi/boot/grub.cfg<vm_console 0 - - ----- Entering VM 0 Shell ----- - *** Booting Zephyr OS build v2.6.0-rc1-324-g1a03783861ad *** - Hello World! acrn - - -.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/x86/index.rst b/boards/x86/index.rst deleted file mode 100644 index f7321566591af1..00000000000000 --- a/boards/x86/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-x86: - -x86 Boards -########## - -.. toctree:: - :maxdepth: 1 - :glob: - - [!common]*/**/* diff --git a/boards/x86/intel_adl/CMakeLists.txt b/boards/x86/intel_adl/CMakeLists.txt deleted file mode 100644 index 2dc5afcc3232ad..00000000000000 --- a/boards/x86/intel_adl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/intel_adl/Kconfig.board b/boards/x86/intel_adl/Kconfig.board deleted file mode 100644 index 591da3261f27f4..00000000000000 --- a/boards/x86/intel_adl/Kconfig.board +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADL_CRB - bool "Alder Lake CRB" - depends on SOC_ALDER_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_INTEL_ADL_RVP - bool "Alder Lake RVP" - depends on SOC_ALDER_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_UP_SQUARED_PRO_7000 - bool "UP SQUARED PRO 7000 board" - depends on SOC_ALDER_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT diff --git a/boards/x86/intel_adl/Kconfig.defconfig b/boards/x86/intel_adl/Kconfig.defconfig deleted file mode 100644 index 5a61d2f552eaae..00000000000000 --- a/boards/x86/intel_adl/Kconfig.defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP || BOARD_UP_SQUARED_PRO_7000 - -config BOARD - default "intel_adl_crb" if BOARD_INTEL_ADL_CRB - default "intel_adl_rvp" if BOARD_INTEL_ADL_RVP - default "up_squared_pro_7000" if BOARD_UP_SQUARED_PRO_7000 - -config BUILD_OUTPUT_STRIPPED - default y - -config MP_MAX_NUM_CPUS - default 2 - -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -config ACPI - default y - -if ACPI -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 64000000 -config MAIN_STACK_SIZE - default 320000 - -if SHELL -config SHELL_STACK_SIZE - default 320000 -endif # SHELL -endif # ACPI - -if DMA -config DMA_64BIT - default y -config DMA_DW_HW_LLI - default n -config DMA_DW_CHANNEL_COUNT - default 2 -endif - -config UART_NS16550_INTEL_LPSS_DMA - default y - -endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP || BOARD_UP_SQUARED_PRO_7000 diff --git a/boards/x86/intel_adl/doc/index.rst b/boards/x86/intel_adl/doc/index.rst deleted file mode 100644 index 63a518248b88ec..00000000000000 --- a/boards/x86/intel_adl/doc/index.rst +++ /dev/null @@ -1,65 +0,0 @@ -.. _intel_adl_n: - -Alder Lake N -############ - -Overview -******** -Alder Lake processor is a 64-bit multi-core processor built on 10-nanometer -technology process. - -Currently supported is N-processor line, Single Chip Platform that consists of -the Processor Die and Alder Lake N Platform Controller Hub (ADL-N PCH) Die on -the same package as Multi-Chip Package (MCP). - -Proposed branding for Adler Lake N is Intel Processor (N100,N200) and -Intel Core i3 (N300, N305). - -Alder Lake N Customer Reference Board (ADL-N CRB) and Alder Lake Reference -Validation Platform (ADL-N RVP) are example implementations of compact single -board computer with high performance for IoT edge devices. - -This board configuration enables kernel support for the Alder Lake N boards. - -Hardware -******** - -General information about the board can be found at the `INTEL_ADL`_ website. - -Connections and IOs -=================== - -Refer to the `INTEL_ADL`_ website for more information. - -Programming and Debugging -************************* -Use the following procedures for booting an image for an Alder Lake N CRB board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application for Alder Lake N CRB: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_adl_crb - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the Alder Lake N CRB Board using UEFI -============================================= - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -.. _INTEL_ADL: https://edc.intel.com/content/www/us/en/design/products/platforms/processor-and-core-i3-n-series-datasheet-volume-1-of-2/ diff --git a/boards/x86/intel_ehl/CMakeLists.txt b/boards/x86/intel_ehl/CMakeLists.txt deleted file mode 100644 index 2dc5afcc3232ad..00000000000000 --- a/boards/x86/intel_ehl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/intel_ehl/Kconfig.board b/boards/x86/intel_ehl/Kconfig.board deleted file mode 100644 index a04a9973eb002f..00000000000000 --- a/boards/x86/intel_ehl/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_EHL_CRB - bool "Elkhart Lake CRB" - depends on SOC_ELKHART_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_INTEL_EHL_CRB_SBL - bool "Elkhart Lake CRB (with Slim Bootloader)" - depends on SOC_ELKHART_LAKE - select X86_64 diff --git a/boards/x86/intel_ehl/Kconfig.defconfig b/boards/x86/intel_ehl/Kconfig.defconfig deleted file mode 100644 index ae8270faa64578..00000000000000 --- a/boards/x86/intel_ehl/Kconfig.defconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_EHL_CRB || BOARD_INTEL_EHL_CRB_SBL - -config BOARD - default "intel_ehl_crb_sbl" if BOARD_INTEL_EHL_CRB_SBL - default "intel_ehl_crb" - -config BUILD_OUTPUT_STRIPPED - default y - -config MP_MAX_NUM_CPUS - default 2 - -if BOARD_INTEL_EHL_CRB_SBL -config SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN - depends on SHELL_BACKEND_SERIAL - default n -endif - -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 2097152 - depends on ACPI - -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -endif # BOARD_INTEL_EHL_CRB || BOARD_INTEL_EHL_CRB_SBL diff --git a/boards/x86/intel_ehl/doc/index.rst b/boards/x86/intel_ehl/doc/index.rst deleted file mode 100644 index 1aa8f530155046..00000000000000 --- a/boards/x86/intel_ehl/doc/index.rst +++ /dev/null @@ -1,89 +0,0 @@ -.. _intel_ehl_crb: - -Elkhart Lake CRB -################ - -Overview -******** -Elkhart Lake Reference Board (EHL CRB) is an example implementation of a -compact single board computer with high performance for IoT edge devices. - -This board configuration enables kernel support for the `EHL`_ board. - -.. note:: - This board configuration works on the variant of `EHL`_ - boards containing Intel |reg| Atom |trade| SoC. - -Hardware -******** - -General information about the board can be found at the `EHL`_ website. - -.. include:: ../../../../soc/x86/elkhart_lake/doc/supported_features.txt - - -Connections and IOs -=================== - -Refer to the `EHL`_ website for more information. - -Programming and Debugging -************************* -Use the following procedures for booting an image on a EHL CRB board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application on Elkhart Lake CRB: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_ehl_crb - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the Elkhart Lake CRB Board using UEFI -============================================= - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -Booting the Elkhart Lake CRB Board over network -=============================================== - -.. include:: ../../common/net_boot.rst - :start-after: start_include_here - -.. note:: - To enable PXE boot for Elkhart Lake CRB board do the following: - - #. Enable boot from PXE. Go to EFI shell and make sure that the first boot - option is ``UEFI PXEv4``. - - .. code-block:: console - - Shell> bcfg boot dump - Option: 00. Variable: Boot0007 - Desc - UEFI PXEv4 (MAC:6805CABC1997) - DevPath - PciRoot(0x0)/Pci(0x1C,0x0)/Pci(0x0,0x0)/MAC(6805CABC1997,0x0)/IPv4(0.0.0.0) - Optional- Y - ... - - #. If UEFI PXEv4 is not the first boot option use ``bcfg boot mv`` command to - change boot order - - .. code-block:: console - - Shell> bcfg boot mv 7 0 - -.. _EHL: https://www.intel.com/content/www/us/en/products/docs/processors/embedded/enhanced-for-iot-platform-brief.html diff --git a/boards/x86/intel_ish/Kconfig.board b/boards/x86/intel_ish/Kconfig.board deleted file mode 100644 index 77962495a12e7e..00000000000000 --- a/boards/x86/intel_ish/Kconfig.board +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -config BOARD_INTEL_ISH_5_4_1 - bool "Intel ISH 5.4.1 board" - depends on SOC_INTEL_ISH_5_4_1 - -config BOARD_INTEL_ISH_5_6_0 - bool "Intel ISH 5.6.0 board" - depends on SOC_INTEL_ISH_5_6_0 - -config BOARD_INTEL_ISH_5_8_0 - bool "Intel ISH 5.8.0 board" - depends on SOC_INTEL_ISH_5_8_0 diff --git a/boards/x86/intel_ish/Kconfig.defconfig b/boards/x86/intel_ish/Kconfig.defconfig deleted file mode 100644 index 1f3d68096437a2..00000000000000 --- a/boards/x86/intel_ish/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if BOARD_INTEL_ISH_5_4_1 || BOARD_INTEL_ISH_5_6_0 || BOARD_INTEL_ISH_5_8_0 - -config BOARD - default "intel_ish_5_4_1" if BOARD_INTEL_ISH_5_4_1 - default "intel_ish_5_6_0" if BOARD_INTEL_ISH_5_6_0 - default "intel_ish_5_8_0" if BOARD_INTEL_ISH_5_8_0 - -if TEST -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # TEST - -config SYS_CLOCK_TICKS_PER_SEC - default 2048 if HPET_TIMER # HPET is 32768 HZ - -endif # BOARD_INTEL_ISH_5_4_1 || BOARD_INTEL_ISH_5_6_0 || BOARD_INTEL_ISH_5_8_0 diff --git a/boards/x86/intel_ish/doc/index.rst b/boards/x86/intel_ish/doc/index.rst deleted file mode 100644 index a3fc6f540dc8eb..00000000000000 --- a/boards/x86/intel_ish/doc/index.rst +++ /dev/null @@ -1,79 +0,0 @@ -.. _intel_ish: - -Intel Integrated Sensor Hub (ISH) -################################# - -Overview -******** -Intel Integrated Sensor Hub (ISH) is a lower-power/always-on co-processor -inside many Intel Processors. It helps offload sensor processing tasks from -the core processor for better power saving. - -Hardware -******** - -- LMT MinuteIA Core: - - - 16KB instruction cache and 16KB data cache. - - 640KB SRAM space for code and data - implemented as L2 SRAM. - - 8KB AON RF space for code resident during deep D0i2/3 PG states. - -- Interface-to-Sensor peripherals (I2C, SPI, UART, I3C, GPIO, DMA). -- Inter Process Communications (IPC) to core processor and other IP processors. - -.. include:: ../../../../soc/x86/intel_ish/doc/supported_features.txt - -Programming and Debugging -************************* -Use the following procedures for booting an ISH image on a ADL RVP board -for Chrome. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application for ISH 5.4.1 on Intel ADL Processor: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_ish_5_4_1 - :goals: build - - .. note:: - - A Zephyr image file named :file:`ish_fw.bin` is automatically - created in the build directory after the application is built. - -Run ish_fw.bin on ADL RVP board for Chrome -========================================== - -- Power on the ADL RVP board. -- Log in Chrome OS. (Note: the user must have root access right, see `Developer Mode`_) -- Re-mount the root filesystem as read-write: - -.. code-block:: console - - $ mount -o remount,rw / - -- If re-mount fails, execute below commands to Remove rootfs verification: - -.. code-block:: console - - $ /usr/share/vboot/bin/make_dev_ssd.sh --remove_rootfs_verification --partitions - $ reboot - -- Go to the ISH firmware direcoty: - -.. code-block:: console - - $ cd /lib/firmware/intel - -- Relace the file adlrvp_ish.bin with zephyr image built out, ish_fw.bin. -- Reboot, then observe Zephyr log output via ISH UART0. - -.. _Developer Mode: https://chromium.googlesource.com/chromiumos/docs/+/HEAD/developer_mode.md diff --git a/boards/x86/intel_ish/intel_ish_5_4_1_defconfig b/boards/x86/intel_ish/intel_ish_5_4_1_defconfig deleted file mode 100644 index 527466ad337b6b..00000000000000 --- a/boards/x86/intel_ish/intel_ish_5_4_1_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_FAMILY_INTEL_ISH=y -CONFIG_SOC_SERIES_INTEL_ISH5=y -CONFIG_SOC_INTEL_ISH_5_4_1=y -CONFIG_BOARD_INTEL_ISH_5_4_1=y - -# uart & console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_6_0_defconfig b/boards/x86/intel_ish/intel_ish_5_6_0_defconfig deleted file mode 100644 index 74b00676d39977..00000000000000 --- a/boards/x86/intel_ish/intel_ish_5_6_0_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_FAMILY_INTEL_ISH=y -CONFIG_SOC_SERIES_INTEL_ISH5=y -CONFIG_SOC_INTEL_ISH_5_6_0=y -CONFIG_BOARD_INTEL_ISH_5_6_0=y - -# uart & console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/x86/intel_ish/intel_ish_5_8_0_defconfig b/boards/x86/intel_ish/intel_ish_5_8_0_defconfig deleted file mode 100644 index ee319557f761b4..00000000000000 --- a/boards/x86/intel_ish/intel_ish_5_8_0_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -CONFIG_SOC_FAMILY_INTEL_ISH=y -CONFIG_SOC_SERIES_INTEL_ISH5=y -CONFIG_SOC_INTEL_ISH_5_8_0=y -CONFIG_BOARD_INTEL_ISH_5_8_0=y - -# uart & console -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y -CONFIG_SERIAL=y diff --git a/boards/x86/intel_rpl/CMakeLists.txt b/boards/x86/intel_rpl/CMakeLists.txt deleted file mode 100644 index 2dc5afcc3232ad..00000000000000 --- a/boards/x86/intel_rpl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/intel_rpl/Kconfig.board b/boards/x86/intel_rpl/Kconfig.board deleted file mode 100644 index 0424004d10b0fa..00000000000000 --- a/boards/x86/intel_rpl/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022-2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_RPL_S_CRB - bool "Raptor Lake S CRB" - depends on SOC_RAPTOR_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_INTEL_RPL_P_CRB - bool "Raptor Lake P CRB" - depends on SOC_RAPTOR_LAKE - select X86_64 - select HAS_COVERAGE_SUPPORT diff --git a/boards/x86/intel_rpl/Kconfig.defconfig b/boards/x86/intel_rpl/Kconfig.defconfig deleted file mode 100644 index 0458aef89be4ec..00000000000000 --- a/boards/x86/intel_rpl/Kconfig.defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# Copyright (c) 2022-2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_RPL_S_CRB || BOARD_INTEL_RPL_P_CRB - -config BOARD - default "intel_rpl_p_crb" if BOARD_INTEL_RPL_P_CRB - default "intel_rpl_s_crb" if BOARD_INTEL_RPL_S_CRB - -config BUILD_OUTPUT_STRIPPED - default y - -config MP_MAX_NUM_CPUS - default 2 - -# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1900000000 if APIC_TSC_DEADLINE_TIMER - default 1900000000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -config ACPI - default y - -if ACPI -config HEAP_MEM_POOL_ADD_SIZE_ACPI - default 64000000 -config MAIN_STACK_SIZE - default 320000 - -if SHELL -config SHELL_STACK_SIZE - default 320000 -endif # SHELL -endif # ACPI - -if DMA -config DMA_64BIT - default y -config DMA_DW_HW_LLI - default n -config DMA_DW_CHANNEL_COUNT - default 2 -endif - -config UART_NS16550_INTEL_LPSS_DMA - default y if BOARD_INTEL_RPL_S_CRB - -if SHELL -config SHELL_STACK_SIZE - default 320000 -endif - -endif # BOARD_INTEL_RPL_S_CRB || BOARD_INTEL_RPL_P_CRB diff --git a/boards/x86/intel_rpl/doc/index.rst b/boards/x86/intel_rpl/doc/index.rst deleted file mode 100644 index 7c3d7758484eca..00000000000000 --- a/boards/x86/intel_rpl/doc/index.rst +++ /dev/null @@ -1,75 +0,0 @@ -.. _intel_rpl_crb: - -Raptor Lake CRB -############### - -Overview -******** -Raptor Lake processor is a 13th generation 64-bit multi-core processor built -on a 10-nanometer technology process. Raptor Lake is based on a Hybrid -architecture, utilizing P-cores for performance and E-Cores for efficiency. - -Raptor Lake S and Raptor Lake P processor lines are supported. - -The S-Processor line is a 2-Chip Platform that includes the Processor Die and -Platform Controller Hub (PCH-S) Die in the Package. - -The P-Processor line is a 2-Die Multi Chip Package (MCP) that includes the -Processor Die and Platform Controller Hub (PCH-P) Die on the same package as -the Processor Die. - -For more information about Raptor Lake Processor lines, P-cores, and E-cores -please refer to `RPL`_. - -Raptor Lake Customer Reference Board (RPL CRB) is an example implementation of a -compact single board computer with high performance for IoT edge devices. The -supported boards are `intel_rpl_s_crb` and `intel_rpl_p_crb`. - -These board configurations enable kernel support for the supported Raptor Lake -boards. - -Hardware -******** - -General information about the board can be found at the `RPL`_. - -.. include:: ../../../../soc/x86/raptor_lake/doc/supported_features.txt - - -Connections and IOs -=================== - -Refer to the `RPL`_ for more information. - -Programming and Debugging -************************* -Use the following procedures for booting an image on an RPL CRB board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application on Raptor Lake S CRB: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: intel_rpl_s_crb - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the Raptor Lake S CRB Board using UEFI -============================================== - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -.. _RPL: https://edc.intel.com/content/www/us/en/design/products/platforms/details/raptor-lake-s/13th-generation-core-processors-datasheet-volume-1-of-2/ diff --git a/boards/x86/qemu_x86/CMakeLists.txt b/boards/x86/qemu_x86/CMakeLists.txt deleted file mode 100644 index de31c25a82ed8f..00000000000000 --- a/boards/x86/qemu_x86/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -if(CONFIG_BOARD_QEMU_X86_64 AND CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -i ${ZEPHYR_BASE}/include - -o ${CMAKE_OBJCOPY} - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/qemu_x86/Kconfig.board b/boards/x86/qemu_x86/Kconfig.board deleted file mode 100644 index 275d1c69757e84..00000000000000 --- a/boards/x86/qemu_x86/Kconfig.board +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_X86 - bool "QEMU x86" - depends on SOC_IA32 - select QEMU_TARGET - select CPU_HAS_FPU - select HAS_COVERAGE_SUPPORT - -config BOARD_QEMU_X86_64 - bool "QEMU x86_64" - depends on SOC_IA32 - select QEMU_TARGET - select X86_64 - select HAS_COVERAGE_SUPPORT - -config BOARD_QEMU_X86_LAKEMONT - bool "QEMU x86 (Lakemont)" - depends on SOC_LAKEMONT - select QEMU_TARGET - select CPU_HAS_FPU - select HAS_COVERAGE_SUPPORT - -config BOARD_QEMU_X86_TINY - bool "QEMU x86 (tiny memory)" - depends on SOC_IA32 - select QEMU_TARGET - select CPU_HAS_FPU - select HAS_COVERAGE_SUPPORT diff --git a/boards/x86/qemu_x86/Kconfig.defconfig b/boards/x86/qemu_x86/Kconfig.defconfig deleted file mode 100644 index 1e2b7af0a4d941..00000000000000 --- a/boards/x86/qemu_x86/Kconfig.defconfig +++ /dev/null @@ -1,114 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY - -# The EEPROM emulator must be initialized after the flash simulator -config EEPROM_INIT_PRIORITY - default 60 - depends on EEPROM - -config BUILD_OUTPUT_BIN - default n - -endif # BOARD_QEMU_X86 || BOARD_QEMU_X86_64 || BOARD_QEMU_X86_LAKEMONT || BOARD_QEMU_X86_TINY - -if BOARD_QEMU_X86 - -config BOARD - default "qemu_x86" - -config FLASH_SIMULATOR - default y - depends on FLASH - -config KERNEL_VM_SIZE - default 0x10000000 if ACPI - -config MULTIBOOT - default y - -config MULTIBOOT_INFO - default y if MULTIBOOT - -config MULTIBOOT_MEMMAP - default y if MULTIBOOT - -config QEMU_ICOUNT - default n if HPET_TIMER && SHELL - -config QEMU_ICOUNT_SHIFT - default 5 - -endif # BOARD_QEMU_X86 - -if BOARD_QEMU_X86_64 - -config BOARD - default "qemu_x86_64" - -config KERNEL_VM_SIZE - default 0x10000000 if ACPI - -endif # BOARD_QEMU_X86_64 - -if BOARD_QEMU_X86_LAKEMONT - -config BOARD - default "qemu_x86_lakemont" - -config KERNEL_VM_SIZE - default 0x400000 - -config MULTIBOOT - # This is needed for QEMU to load the ELF image - default y - -config X86_PC_COMPATIBLE - # QEMU presents a PC-compatible machine - default y - -config QEMU_ICOUNT - default n if HPET_TIMER && SHELL - -config QEMU_ICOUNT_SHIFT - default 5 - -endif # BOARD_QEMU_X86_LAKEMONT - -if BOARD_QEMU_X86_TINY - -config BOARD - default "qemu_x86_tiny" - -config KERNEL_VM_SIZE - default 0x400000 - -config MULTIBOOT - # This is needed for QEMU to load the ELF image - default y - -config X86_PC_COMPATIBLE - # QEMU presents a PC-compatible machine - default y - -config QEMU_ICOUNT - default n if HPET_TIMER && SHELL - -config QEMU_ICOUNT_SHIFT - default 5 - -config HAVE_CUSTOM_LINKER_SCRIPT - default y - -config CUSTOM_LINKER_SCRIPT - default "${ZEPHYR_BASE}/boards/x86/qemu_x86/qemu_x86_tiny.ld" - -config X86_EXTRA_PAGE_TABLE_PAGES - # This is needed for gen_mmu.py to map the flash into memory - default 2 if DEMAND_PAGING && !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT - -config DEMAND_PAGING_PAGE_FRAMES_RESERVE - # Need to accommodate the heap for newlib or common malloc in libc-hook.c - default 6 if NEWLIB_LIBC || (COMMON_LIBC_MALLOC && COMMON_LIBC_MALLOC_ARENA_SIZE != 0) - -endif # BOARD_QEMU_X86_TINY diff --git a/boards/x86/qemu_x86/board.cmake b/boards/x86/qemu_x86/board.cmake deleted file mode 100644 index 97a56a92770db8..00000000000000 --- a/boards/x86/qemu_x86/board.cmake +++ /dev/null @@ -1,87 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -if(NOT CONFIG_REBOOT) - set(REBOOT_FLAG -no-reboot) -endif() - -if(CONFIG_X86_64) - set(QEMU_binary_suffix x86_64) - set(QEMU_CPU_TYPE_${ARCH} qemu64,+x2apic) - if("${CONFIG_MP_MAX_NUM_CPUS}" STREQUAL "1") - # icount works with 1 CPU so we can enable it here. - # FIXME: once this works across configs, remove this line and set - # CONFIG_QEMU_ICOUNT_SHIFT in defconfig instead. - list(APPEND QEMU_EXTRA_FLAGS -icount shift=5,align=off,sleep=off -rtc clock=vm) - endif() -else() - set(QEMU_CPU_TYPE_${ARCH} qemu32,+nx,+pae) -endif() - -if(CONFIG_XIP) - # Extra 4MB to emulate flash area - math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024 + 4") -elseif(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING - AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) - # Flash is at 4MB-8MB, so need this to be large enough - math(EXPR QEMU_MEMORY_SIZE_MB "8") -else() - math(EXPR QEMU_MEMORY_SIZE_MB "${CONFIG_SRAM_SIZE} / 1024") -endif() - -set(QEMU_CPU_FLAGS "") -if(CONFIG_X86_MMX) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmx") - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "mmxext") -endif() -if(CONFIG_X86_SSE) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse") -endif() -if(CONFIG_X86_SSE2) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse2") -endif() -if(CONFIG_X86_SSE3) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "pni") -endif() -if(CONFIG_X86_SSSE3) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "ssse3") -endif() -if(CONFIG_X86_SSE41) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.1") -endif() -if(CONFIG_X86_SSE42) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4.2") -endif() -if(CONFIG_X86_SSE4A) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "sse4a") -endif() -if(NOT CONFIG_X86_64 AND CONFIG_CACHE_MANAGEMENT) - string(JOIN "," QEMU_CPU_FLAGS "${QEMU_CPU_FLAGS}" "clflush") -endif() - -set(QEMU_FLAGS_${ARCH} - -m ${QEMU_MEMORY_SIZE_MB} - -cpu ${QEMU_CPU_TYPE_${ARCH}}${QEMU_CPU_FLAGS} - -machine q35 - -device isa-debug-exit,iobase=0xf4,iosize=0x04 - ${REBOOT_FLAG} - -nographic - ) - -if(NOT CONFIG_ACPI) - list(APPEND QEMU_FLAGS_${ARCH} -no-acpi) -endif() - -# TODO: Support debug -# board_set_debugger_ifnset(qemu) -# debugserver: QEMU_EXTRA_FLAGS += -s -S -# debugserver: qemu - -if(CONFIG_BOARD_QEMU_X86_TINY AND CONFIG_DEMAND_PAGING - AND NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT) - # This is to map the flash so it is accessible. - math(EXPR QEMU_FLASH_SIZE_KB "${CONFIG_FLASH_SIZE} * 1024") - set(X86_EXTRA_GEN_MMU_ARGUMENTS - --map ${CONFIG_FLASH_BASE_ADDRESS},${QEMU_FLASH_SIZE_KB},W) -endif() diff --git a/boards/x86/qemu_x86/qemu_x86_64_nokpti.yaml b/boards/x86/qemu_x86/qemu_x86_64_nokpti.yaml deleted file mode 100644 index 531ebd4d3e1aab..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_64_nokpti.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: qemu_x86_64_nokpti -name: QEMU Emulation for X86_64 (KPTI disabled) -type: qemu -arch: x86 -toolchain: - - zephyr - - xtools -supported: - - smp -simulation: qemu -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_64_nokpti_defconfig b/boards/x86/qemu_x86/qemu_x86_64_nokpti_defconfig deleted file mode 100644 index 1ca8daa5fa1e8d..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_64_nokpti_defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86_64=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y -CONFIG_SMP=y -CONFIG_MP_MAX_NUM_CPUS=2 -CONFIG_X86_MMU=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_QEMU_ICOUNT=n -CONFIG_X86_KPTI=n diff --git a/boards/x86/qemu_x86/qemu_x86_nokpti.yaml b/boards/x86/qemu_x86/qemu_x86_nokpti.yaml deleted file mode 100644 index 75ab0d13d5fffa..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_nokpti.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_x86_nokpti -name: QEMU Emulation for X86 (KPTI disabled) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig b/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig deleted file mode 100644 index 5423b62b679277..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_nokpti_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_X86_KPTI=n diff --git a/boards/x86/qemu_x86/qemu_x86_nommu.dts b/boards/x86/qemu_x86/qemu_x86_nommu.dts deleted file mode 100644 index cac68cd695e1b3..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_nommu.dts +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: Apache-2.0 */ - -#include "qemu_x86.dts" diff --git a/boards/x86/qemu_x86/qemu_x86_nommu.yaml b/boards/x86/qemu_x86/qemu_x86_nommu.yaml deleted file mode 100644 index 8d7aee97b7e811..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_nommu.yaml +++ /dev/null @@ -1,14 +0,0 @@ -identifier: qemu_x86_nommu -name: QEMU Emulation for X86 (MMU disabled) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_nommu_defconfig b/boards/x86/qemu_x86/qemu_x86_nommu_defconfig deleted file mode 100644 index d485369c6cb1b5..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_nommu_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y diff --git a/boards/x86/qemu_x86/qemu_x86_nopae.yaml b/boards/x86/qemu_x86/qemu_x86_nopae.yaml deleted file mode 100644 index 7dbd449cebcf4d..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_nopae.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_x86_nopae -name: QEMU Emulation for X86 (32-bit page tables) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_nopae_defconfig b/boards/x86/qemu_x86/qemu_x86_nopae_defconfig deleted file mode 100644 index 15a109c056f310..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_nopae_defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_X86_PAE=n diff --git a/boards/x86/qemu_x86/qemu_x86_tiny_768.conf b/boards/x86/qemu_x86/qemu_x86_tiny_768.conf deleted file mode 100644 index 583d6a85451ed1..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_tiny_768.conf +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# Enable coverage regardless since this config for coverage only. -CONFIG_COVERAGE=y - -# Need more stack space due to coverage being enabled. -CONFIG_MAIN_STACK_SIZE=4096 -CONFIG_IDLE_STACK_SIZE=1024 diff --git a/boards/x86/qemu_x86/qemu_x86_tiny_768.overlay b/boards/x86/qemu_x86/qemu_x86_tiny_768.overlay deleted file mode 100644 index bb92000cb41bbc..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_tiny_768.overlay +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2022 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Override with 768KB DRAM */ -&dram0 { - reg = < 0x100000 DT_SIZE_K(768) >; -}; diff --git a/boards/x86/qemu_x86/qemu_x86_virt.yaml b/boards/x86/qemu_x86/qemu_x86_virt.yaml deleted file mode 100644 index 1f3eb2fb18b32b..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_virt.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: qemu_x86_virt -name: QEMU Emulation for X86 (Run in Virtual Address Space) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - kernel - - userspace - ignore_tags: - - benchmark -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_virt_defconfig b/boards/x86/qemu_x86/qemu_x86_virt_defconfig deleted file mode 100644 index eabfab7a591caf..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_virt_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_X86_MMU=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y - -CONFIG_SRAM_OFFSET=0x100000 -CONFIG_KERNEL_VM_SIZE=0x400000 -CONFIG_KERNEL_VM_BASE=0x40000000 -CONFIG_KERNEL_VM_OFFSET=0 - -CONFIG_LINKER_USE_BOOT_SECTION=y -CONFIG_LINKER_USE_PINNED_SECTION=y diff --git a/boards/x86/qemu_x86/qemu_x86_xip.yaml b/boards/x86/qemu_x86/qemu_x86_xip.yaml deleted file mode 100644 index c33acd4db16d4f..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_xip.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: qemu_x86_xip -name: QEMU Emulation for X86 (XIP enabled) -type: qemu -arch: x86 -simulation: qemu -toolchain: - - zephyr - - xtools -testing: - default: true - only_tags: - - xip -vendor: qemu diff --git a/boards/x86/qemu_x86/qemu_x86_xip_defconfig b/boards/x86/qemu_x86/qemu_x86_xip_defconfig deleted file mode 100644 index 42fd2677785f33..00000000000000 --- a/boards/x86/qemu_x86/qemu_x86_xip_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_IA32=y -CONFIG_BOARD_QEMU_X86=y -CONFIG_PIC_DISABLE=y -CONFIG_LOAPIC=y -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=25000000 -CONFIG_TEST_RANDOM_GENERATOR=y -CONFIG_DEBUG_INFO=y -CONFIG_SCHED_SCALABLE=y -CONFIG_WAITQ_SCALABLE=y -CONFIG_X86_VERY_EARLY_CONSOLE=y -CONFIG_XIP=y diff --git a/boards/x86/qemu_x86/revision.cmake b/boards/x86/qemu_x86/revision.cmake deleted file mode 100644 index 96fc09545a19f7..00000000000000 --- a/boards/x86/qemu_x86/revision.cmake +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2022 Intel Corporation. -# SPDX-License-Identifier: Apache-2.0 - -# We can't really do board_check_revision() here -# as it will apply to all qemu_x86* boards. diff --git a/boards/x86/up_squared/CMakeLists.txt b/boards/x86/up_squared/CMakeLists.txt deleted file mode 100644 index 2dc5afcc3232ad..00000000000000 --- a/boards/x86/up_squared/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# Create an EFI image -if(CONFIG_BUILD_OUTPUT_EFI) -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py - -c ${CMAKE_C_COMPILER} - -o ${CMAKE_OBJCOPY} - -i ${ZEPHYR_BASE}/include - -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf - $<$:--verbose> - WORKING_DIRECTORY ${PROJECT_BINARY_DIR} -) -endif() diff --git a/boards/x86/up_squared/Kconfig.board b/boards/x86/up_squared/Kconfig.board deleted file mode 100644 index c25c3e2857d46a..00000000000000 --- a/boards/x86/up_squared/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_UP_SQUARED - bool "UP Squared (x86_64)" - depends on SOC_APOLLO_LAKE - select X86_64 diff --git a/boards/x86/up_squared/Kconfig.defconfig b/boards/x86/up_squared/Kconfig.defconfig deleted file mode 100644 index e8eecbcc5087fd..00000000000000 --- a/boards/x86/up_squared/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_UP_SQUARED - -config BOARD - default "up_squared" - -config MP_MAX_NUM_CPUS - default 2 if BOARD_UP_SQUARED - -config BUILD_OUTPUT_STRIPPED - default y - -# TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1593600000 if APIC_TSC_DEADLINE_TIMER - default 1593600000 if APIC_TIMER_TSC - default 19200000 - -if APIC_TIMER -config APIC_TIMER_IRQ - default 24 -config APIC_TIMER_TSC_M - default 3 -config APIC_TIMER_TSC_N - default 249 -endif - -endif # BOARD_UP_SQUARED diff --git a/boards/x86/up_squared/doc/index.rst b/boards/x86/up_squared/doc/index.rst deleted file mode 100644 index bf40fa16ba2ce6..00000000000000 --- a/boards/x86/up_squared/doc/index.rst +++ /dev/null @@ -1,125 +0,0 @@ -.. _up_squared: - -UP Squared -########## - -Overview -******** - -UP |sup2| (UP Squared) is an ultra compact single board computer with high -performance and low power consumption. It features the latest Intel |reg| Apollo -Lake Celeron |trade| and Pentium |trade| Processors with only 4W of Scenario Design Power and -a powerful and flexible Intel |reg| FPGA Altera MAX 10 onboard. - -.. figure:: img/up_squared.jpg - :align: center - :alt: UP Squared - - Up Squared (Credit: https://up-board.org) - -This board configuration enables kernel support for the `UP Squared`_ board. - -.. note:: - This board configuration works on all three variants of `UP Squared`_ - boards containing Intel |reg| Pentium |trade| SoC, - Intel |reg| Celeron |trade| SoC, or Intel |reg| Atom |trade| SoC. - -Hardware -******** - -General information about the board can be found at the `UP Squared`_ website. - -.. include:: ../../../../soc/x86/apollo_lake/doc/supported_features.txt - -GPIO ----- - -GPIOs are exposed through the HAT header, and can be referred using -predefined macros such as ``UP2_HAT_PIN3``. The physical pins are -connected to the on-board FPGA acting as level shifter. Therefore, -to actually utilize these GPIO pins, the function of the pins and -directions (input/output) must be set in the BIOS. This can be -accomplished in BIOS, under menu ``Advanced``, and option -``HAT Configurations``. When a corresponding pin is set to act as -GPIO, there is an option to set the direction of the pin. This needs -to be set accordingly for the GPIO to function properly. - -Connections and IOs -=================== - -Refer to the `UP Squared`_ website and `UP Squared Pinout`_ website -for connection diagrams. - -Programming and Debugging -************************* - -Use the following procedures for booting an image on a UP Squared board. - -.. contents:: - :depth: 1 - :local: - :backlinks: top - -Build Zephyr application -======================== - -#. Build a Zephyr application; for instance, to build the ``hello_world`` - application on UP Squared: - - .. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: up_squared - :goals: build - - .. note:: - - A Zephyr EFI image file named :file:`zephyr.efi` is automatically - created in the build directory after the application is built. - -Booting the UP Squared Board using UEFI -======================================= - -.. include:: ../../common/efi_boot.rst - :start-after: start_include_here - -.. note:: - Refer to the `UP Squared Serial Console Wiki page - `_ for instructions on how to - connect serial console. - -.. note:: - You can safely ignore this message if it appears: - - .. code-block:: console - - WARNING: no console will be available to OS - -Booting the UP Squared Board over network -========================================= - -.. include:: ../../common/net_boot.rst - :start-after: start_include_here - -.. note:: - Refer to the `UP Squared Serial Console Wiki page - `_ for instructions on how to - connect serial console. - -.. note:: - To enable PXE boot for Up Squared board do the following: - - #. Enable network from BIOS settings. - - .. code-block:: console - - Advanced -> Network Stack Configuration -> Enable Network Stack -> Enable Ipv4 PXE Support - - #. Make network boot as the first boot option. - - .. code-block:: console - - Boot -> Boot Option #1 : [Network] - -.. _UP Squared: https://www.up-board.org/upsquared/specifications - -.. _UP Squared Pinout: https://wiki.up-community.org/Pinout diff --git a/boards/xen/index.rst b/boards/xen/index.rst new file mode 100644 index 00000000000000..4f760a22fbe1bf --- /dev/null +++ b/boards/xen/index.rst @@ -0,0 +1,10 @@ +.. _boards-xen: + +Xen Hypervisor +############## + +.. toctree:: + :maxdepth: 1 + :glob: + + **/* diff --git a/boards/xen/xenvm/Kconfig.defconfig b/boards/xen/xenvm/Kconfig.defconfig new file mode 100644 index 00000000000000..965dc9cda33bd8 --- /dev/null +++ b/boards/xen/xenvm/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_XENVM + +config BUILD_OUTPUT_BIN + default y + +config HEAP_MEM_POOL_SIZE + default 16384 if BOARD_XENVM_XENVM + +endif # BOARD_XENVM diff --git a/boards/xen/xenvm/Kconfig.xenvm b/boards/xen/xenvm/Kconfig.xenvm new file mode 100644 index 00000000000000..e5393bbf957acb --- /dev/null +++ b/boards/xen/xenvm/Kconfig.xenvm @@ -0,0 +1,5 @@ +# Copyright (c) 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_XENVM + select SOC_XENVM diff --git a/boards/xen/xenvm/board.yml b/boards/xen/xenvm/board.yml new file mode 100644 index 00000000000000..5b5aec44c55ba5 --- /dev/null +++ b/boards/xen/xenvm/board.yml @@ -0,0 +1,7 @@ +board: + name: xenvm + vendor: xen + socs: + - name: xenvm + variants: + - name: gicv3 diff --git a/boards/xen/xenvm/doc/index.rst b/boards/xen/xenvm/doc/index.rst new file mode 100644 index 00000000000000..88221b582e7963 --- /dev/null +++ b/boards/xen/xenvm/doc/index.rst @@ -0,0 +1,187 @@ +.. xenvm: + +ARMv8 Xen Virtual Machine Example +################################# + +Overview +******** + +This board allows to run Zephyr as Xen guest on any ARMv8 board that supports +ARM Virtualization Extensions. This is example configuration, as almost any VM +configuration is unique in many aspects. + +It provides minimal set of devices: + +* ARM Generic timer +* GICv2/GICv3 + +Hardware +******** +Supported Features +================== + +The following hardware features are supported: + ++--------------+-------------+----------------------+ +| Interface | Controller | Driver/Component | ++==============+=============+======================+ +| GIC | virtualized | interrupt controller | ++--------------+-------------+----------------------+ +| ARM TIMER | virtualized | system clock | ++--------------+-------------+----------------------+ + +The kernel currently does not support other hardware features on this platform. + +The default configuration for this board can be found in these files: + +- :zephyr_file:`boards/xen/xenvm/Kconfig.defconfig` +- :zephyr_file:`boards/xen/xenvm/xenvm_defconfig` + +Devices +======== +System Clock +------------ + +This board configuration uses a system clock frequency of 8.32 MHz. This is the +default value, which should be corrected for user's actual hardware. + +You can determine clock frequency of your ARM Generic Timer by inspecting Xen +boot log: + +:: + + (XEN) [ 0.147541] Generic Timer IRQ: phys=30 hyp=26 virt=27 Freq: 8320 KHz + +Interrupt Controller +-------------------- + +Depending on the version of the GIC on your hardware, you may choose one of the +following board configuration variants: + +- ``xenvm`` selects GICv2 +- ``xenvm//gicv3`` selects GICv3 + +CPU Core type +------------- + +Default core in this configuration is Cortex A72. Depending on yours actual +hardware you might want to change this option in the same way as Interrupt +Controller configuration. + +Known Problems or Limitations +============================== + +Xen configures guests in runtime by providing device tree that describes guest +environment. On other hand, Zephyr uses static configuration that should be know +at build time. So there are chances, that Zephyr image created with default +configuration would not boot on your hardware. In this case you need to update +configuration by altering device tree and Kconfig options. This will be covered +in detail in next section. + +Most of Xen-specific features are not supported at the moment. This includes: +* XenBus (under development) +* Xen PV drivers + +Now only following features are supported: +* Xen Enlighten memory page +* Xen event channels +* Xen PV console (2 versions: regular ring buffer based for DomU and consoleio for Dom0) +* Xen early console_io interface (mainly for debug purposes - requires debug version of Xen) +* Xen grant tables (granting access for own grants and map/unmap foreign grants) + +Building and Running +******************** + +Use this configuration to run basic Zephyr applications and kernel tests as Xen +guest, for example, with the :zephyr:code-sample:`synchronization` sample: + +- if your hardware is based on GICv2: + +.. code-block:: + + $ west build -b xenvm samples/synchronization + +- if your hardware is based on GICv3: + +.. code-block:: + + $ west build -b xenvm//gicv3 samples/synchronization + +This will build an image with the synchronization sample app. Next, you need to +create guest configuration file :code:`zephyr.conf`. There is example: + +.. code-block:: + + kernel="zephyr.bin" + name="zephyr" + vcpus=1 + memory=16 + gic_version="v2" + on_crash="preserve" + +When using ``xenvm//gicv3`` configuration, you need to remove the ``gic_version`` +parameter or set it to ``"v3"``. + +You need to upload both :code:`zephyr.bin` and :code:`zephyr.conf` to your Dom0 +and then you can run Zephyr by issuing + +.. code-block:: + + $ xl create zephyr.conf + +Next you need to attach to PV console: + +.. code-block:: + + $ xl console zephyr + +Also this can be performed via single command: + +.. code-block:: + + $ xl create -c zephyr.conf + +You will see Zephyr output: + +.. code-block:: console + + *** Booting Zephyr OS build zephyr-v2.4.0-1137-g5803ee1e8183 *** + thread_a: Hello World from cpu 0 on xenvm! + thread_b: Hello World from cpu 0 on xenvm! + thread_a: Hello World from cpu 0 on xenvm! + thread_b: Hello World from cpu 0 on xenvm! + thread_a: Hello World from cpu 0 on xenvm! + +Exit xen virtual console by pressing :kbd:`CTRL+]` + +Updating configuration +********************** + +As was said earlier, Xen describes hardware using device tree and expects that +guest will parse device tree in runtime. On other hand, Zephyr supports only +static, build time configuration. While provided configuration should work on +almost any ARMv8 host running in aarch64 mode, there is no guarantee, that Xen +will not change some values (like RAM base address) in the future. + +Also, frequency of system timer is board specific and should be updated when running +Zephyr xenvm image on new hardware. + +One can make Xen to dump generated DTB by using :code:`LIBXL_DEBUG_DUMP_DTB` +environment variable, like so: + +.. code-block:: + + $ LIBXL_DEBUG_DUMP_DTB=domu-libxl.dtb xl create zephyr.conf + +Then, generated "domu-libxl.dtb" file can be de-compiled using "dtc" tool. + +Use information from de-compiled DTB file to update all related entries in +provided "xenvm.dts" file. If memory layout is also changed, you may need to +update :code:`CONFIG_SRAM_BASE_ADDRESS` as well. + +References +********** + +`Xen ARM with Virtualization Extensions `_ + +`xl.conf (guest configuration file) manual `_ diff --git a/boards/arm64/xenvm/xenvm.dts b/boards/xen/xenvm/xenvm.dts similarity index 100% rename from boards/arm64/xenvm/xenvm.dts rename to boards/xen/xenvm/xenvm.dts diff --git a/boards/arm64/xenvm/xenvm.yaml b/boards/xen/xenvm/xenvm.yaml similarity index 100% rename from boards/arm64/xenvm/xenvm.yaml rename to boards/xen/xenvm/xenvm.yaml diff --git a/boards/arm64/xenvm/xenvm_defconfig b/boards/xen/xenvm/xenvm_defconfig similarity index 77% rename from boards/arm64/xenvm/xenvm_defconfig rename to boards/xen/xenvm/xenvm_defconfig index 39e8a20767cb27..38885a73413100 100644 --- a/boards/arm64/xenvm/xenvm_defconfig +++ b/boards/xen/xenvm/xenvm_defconfig @@ -1,11 +1,7 @@ -CONFIG_SOC_XENVM=y -CONFIG_BOARD_XENVM=y - # Enable UART driver CONFIG_SERIAL=y CONFIG_MAX_XLAT_TABLES=24 -CONFIG_HEAP_MEM_POOL_SIZE=16384 # Enable console CONFIG_CONSOLE=y diff --git a/boards/arm64/xenvm/xenvm_gicv3.dts b/boards/xen/xenvm/xenvm_xenvm_gicv3.dts similarity index 100% rename from boards/arm64/xenvm/xenvm_gicv3.dts rename to boards/xen/xenvm/xenvm_xenvm_gicv3.dts diff --git a/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml new file mode 100644 index 00000000000000..a680dd6d0cf25e --- /dev/null +++ b/boards/xen/xenvm/xenvm_xenvm_gicv3.yaml @@ -0,0 +1,9 @@ +identifier: xenvm/xenvm/gicv3 +name: ARMv8 Xen Virtual Machine With GICv3 +type: mcu +arch: arm64 +toolchain: + - zephyr + - cross-compile +ram: 16384 +vendor: xen diff --git a/boards/xtensa/esp32_devkitc_wroom/Kconfig.board b/boards/xtensa/esp32_devkitc_wroom/Kconfig.board deleted file mode 100644 index a295f3bfc50edc..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROOM - bool "ESP32-DEVKITC-WROOM Development Board" - depends on SOC_SERIES_ESP32 - -config BOARD_ESP32_DEVKITC_WROOM_APPCPU - bool "ESP32 Board configuration for APPCPU (core 1)." - depends on SOC_SERIES_ESP32 && SOC_ESP32_APPCPU - -choice SOC_PART_NUMBER - default SOC_ESP32_WROOM_32UE_N4 -endchoice diff --git a/boards/xtensa/esp32_devkitc_wroom/Kconfig.defconfig b/boards/xtensa/esp32_devkitc_wroom/Kconfig.defconfig deleted file mode 100644 index aadb2d833f8dcf..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# ESP32 board configuration - -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32_DEVKITC_WROOM - -config BOARD - default "esp32_devkitc_wroom" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_ESP32_DEVKITC_WROOM - -if BOARD_ESP32_DEVKITC_WROOM_APPCPU - -config BOARD - default "esp32_devkitc_wroom_appcpu" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -config KERNEL_BIN_NAME - default "esp32_appcpu_firmware" - -endif # BOARD_ESP32_DEVKITC_WROOM_APPCPU - -config ENTROPY_GENERATOR - default y diff --git a/boards/xtensa/esp32_devkitc_wroom/doc/index.rst b/boards/xtensa/esp32_devkitc_wroom/doc/index.rst deleted file mode 100644 index ceeb7d38ba9c3f..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/doc/index.rst +++ /dev/null @@ -1,215 +0,0 @@ -.. _esp32_devkitc_wroom: - -ESP32-DEVKITC-WROOM -################### - -Overview -******** - -ESP32-DEVKITC-WROOM is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32-WROOM is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -.. figure:: img/esp32_devkitc_wroom.jpg - :align: center - :alt: ESP32-DEVKITC-WROOM - - ESP32-DevKitC-WROOM-32D DK - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DEVKITC-WROOM allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. - -Supported Features -================== - -Current Zephyr's ESP32-WROOM board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wroom`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wroom - -Debugging ---------- - -ESP32-DEVKITC-WROOM support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wroom - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.dts b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.dts deleted file mode 100644 index a33384c2a5ce59..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.dts +++ /dev/null @@ -1,176 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wroom-pinctrl.dtsi" -#include -#include - -/ { - model = "Espressif ESP32-DEVKITC-WROOM-32D"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&psram0 { - status = "disabled"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.yaml b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.yaml deleted file mode 100644 index 19155f8a0d1299..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom.yaml +++ /dev/null @@ -1,25 +0,0 @@ -identifier: esp32_devkitc_wroom -name: ESP32-DevkitC-WROOM-32D -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts deleted file mode 100644 index c58f39cd444bf4..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include - -/ { - model = "esp32_wroom_appcpu"; - compatible = "espressif,esp32_appcpu"; - - chosen { - zephyr,sram = &sram0; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml deleted file mode 100644 index 02f9916ef9013f..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wroom_appcpu -name: ESP32 DEVKITC WROOM APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig deleted file mode 100644 index 81406ae4c49218..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_appcpu_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ESP32=y -CONFIG_SOC_ESP32_APPCPU=y -CONFIG_BOARD_ESP32_DEVKITC_WROOM_APPCPU=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig b/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig deleted file mode 100644 index ead6203b86e595..00000000000000 --- a/boards/xtensa/esp32_devkitc_wroom/esp32_devkitc_wroom_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32_DEVKITC_WROOM=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_devkitc_wrover/Kconfig.board b/boards/xtensa/esp32_devkitc_wrover/Kconfig.board deleted file mode 100644 index 20e59ac10fea69..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/Kconfig.board +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_DEVKITC_WROVER - bool "ESP32-DEVKITC-WROVER-E Development board" - depends on SOC_SERIES_ESP32 - -config BOARD_ESP32_DEVKITC_WROVER_APPCPU - bool "ESP32 Board configuration for APPCPU (core 1)." - depends on SOC_SERIES_ESP32 && SOC_ESP32_APPCPU - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N4R8 -endchoice diff --git a/boards/xtensa/esp32_devkitc_wrover/Kconfig.defconfig b/boards/xtensa/esp32_devkitc_wrover/Kconfig.defconfig deleted file mode 100644 index 84b365c2b77a7c..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/Kconfig.defconfig +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32_DEVKITC_WROVER - -config BOARD - default "esp32_devkitc_wrover" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_ESP32_DEVKITC_WROVER - -if BOARD_ESP32_DEVKITC_WROVER_APPCPU - -config BOARD - default "esp32_devkitc_wrover_appcpu" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - default 4096 - -config KERNEL_BIN_NAME - default "esp32_appcpu_firmware" -endif - -config ENTROPY_GENERATOR - default y diff --git a/boards/xtensa/esp32_devkitc_wrover/doc/index.rst b/boards/xtensa/esp32_devkitc_wrover/doc/index.rst deleted file mode 100644 index ec59ab5c640745..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/doc/index.rst +++ /dev/null @@ -1,296 +0,0 @@ -.. _esp32_devkitc_wrover: - -ESP32-DEVKITC-WROVER -#################### - -Overview -******** - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -.. figure:: img/esp32_devkitc_wrover.jpg - :align: center - :alt: ESP32-DEVKITC-WROVER - - ESP32-DevKitC-WROVER-IE - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32-DEVKITC-WROVER allows 2 different applications to be executed in ESP32 SoC. Due to its dual-core architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. - -Supported Features -================== - -Current Zephyr's ESP32-devkitc board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build - -The usual ``flash`` target will work with the ``esp32_devkitc_wrover`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_devkitc_wrover - -Debugging -********* - -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the ESP-WROOM-32 DevKitC board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_devkitc_wrover - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.dts b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.dts deleted file mode 100644 index d62fe5ccfb8609..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.dts +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_devkitc_wrover-pinctrl.dtsi" -#include -#include - -/ { - model = "Espressif ESP32-DEVKITC-WROVER-E"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.yaml b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.yaml deleted file mode 100644 index df56a1dbc553c5..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover.yaml +++ /dev/null @@ -1,25 +0,0 @@ -identifier: esp32_devkitc_wrover -name: ESP32-DevkitC-WROVER-E -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy - - input -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts deleted file mode 100644 index 2b6f06263563b0..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.dts +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include - -/ { - model = "esp32_wrover_appcpu"; - compatible = "espressif,esp32_appcpu"; - - chosen { - zephyr,sram = &sram0; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&trng0 { - status = "okay"; -}; diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml deleted file mode 100644 index 03fe6a111a65f9..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu.yaml +++ /dev/null @@ -1,27 +0,0 @@ -identifier: esp32_devkitc_wrover_appcpu -name: ESP32 DEVKITC WROVER APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp -vendor: espressif diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig deleted file mode 100644 index 5363f49388288c..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ESP32=y -CONFIG_SOC_ESP32_APPCPU=y -CONFIG_BOARD_ESP32_DEVKITC_WROVER_APPCPU=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig b/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig deleted file mode 100644 index ad08ccede28bd3..00000000000000 --- a/boards/xtensa/esp32_devkitc_wrover/esp32_devkitc_wrover_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32_DEVKITC_WROVER=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32_ethernet_kit/Kconfig.board b/boards/xtensa/esp32_ethernet_kit/Kconfig.board deleted file mode 100644 index 28a8995bbdf287..00000000000000 --- a/boards/xtensa/esp32_ethernet_kit/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32-ETHERNET-KIT board configuration - -# Copyright (c) 2022 Grant Ramsay -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32_ETHERNET_KIT - bool "ESP32-ETHERNET-KIT Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N4R8 -endchoice diff --git a/boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig b/boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig deleted file mode 100644 index 8797780b74ea01..00000000000000 --- a/boards/xtensa/esp32_ethernet_kit/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# ESP32-ETHERNET-KIT board configuration - -# Copyright (c) 2022 Grant Ramsay -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32_ethernet_kit" - depends on BOARD_ESP32_ETHERNET_KIT - -config ESP_SPIRAM - default y - -choice SPIRAM_TYPE - default SPIRAM_TYPE_ESPPSRAM64 -endchoice - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/esp32_ethernet_kit/doc/index.rst b/boards/xtensa/esp32_ethernet_kit/doc/index.rst deleted file mode 100644 index 7159681dccdfcd..00000000000000 --- a/boards/xtensa/esp32_ethernet_kit/doc/index.rst +++ /dev/null @@ -1,623 +0,0 @@ -.. _esp32_ethernet_kit: - -ESP32-ETHERNET-KIT -################## - -The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables -Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide -more flexible power supply options, the ESP32-Ethernet-Kit also supports power -over Ethernet (PoE). - -.. _get-started-esp32-ethernet-kit-v1.2-overview: - -.. figure:: img/esp32-ethernet-kit-v1.2-overview.jpg - :align: center - :alt: ESP32-Ethernet-Kit V1.2 - :figclass: align-center - - ESP32-Ethernet-Kit V1.2 Overview - -Overview -******** - -ESP32-Ethernet-Kit is an ESP32-based development board produced by -`Espressif `_. - -It consists of two development boards, the Ethernet board A and the PoE -board B. The `Ethernet board (A)`_ contains Bluetooth/Wi-Fi dual-mode -ESP32-WROVER-E module and IP101GRI, a Single Port 10/100 Fast Ethernet -Transceiver (PHY). The `PoE board (B)`_ provides power over Ethernet -functionality. The A board can work independently, without the board B -installed. - -.. _get-started-esp32-ethernet-kit-v1.2: - -.. figure:: img/esp32-ethernet-kit-v1.2.jpg - :align: center - :alt: ESP32-Ethernet-Kit V1.2 - :figclass: align-center - - ESP32-Ethernet-Kit V1.2 - -For the application loading and monitoring, the Ethernet board (A) also -features FTDI FT2232H chip - an advanced multi-interface USB bridge. -This chip enables to use JTAG for direct debugging of ESP32 through the -USB interface without a separate JTAG debugger. - - -Functionality Overview -====================== - -The block diagram below shows the main components of ESP32-Ethernet-Kit -and their interconnections. - -.. figure:: img/esp32-ethernet-kit-v1.1-block-diagram.jpg - :align: center - :alt: ESP32-Ethernet-Kit block diagram - :figclass: align-center - - ESP32-Ethernet-Kit block diagram - - -Functional Description ----------------------- - -The following figures and tables describe the key components, interfaces, -and controls of the ESP32-Ethernet-Kit. - -.. _get-started-esp32-ethernet-kit-a-v1.2-layout: - - -Ethernet Board (A) -^^^^^^^^^^^^^^^^^^ - -.. figure:: img/esp32-ethernet-kit-a-v1.2-layout.jpg - :align: center - :alt: ESP32-Ethernet-Kit V1.2 - :figclass: align-center - - ESP32-Ethernet-Kit - Ethernet board (A) layout - -The table below provides description starting from the picture's top right -corner and going clockwise. - -.. list-table:: Table 1 Component Description - :widths: 40 150 - :header-rows: 1 - - * - Key Component - - Description - * - ESP32-WROVER-E - - This ESP32 module features 64-Mbit PSRAM for flexible extended storage - and data processing capabilities. - * - GPIO Header 2 - - Five unpopulated through-hole solder pads to provide access to selected - GPIOs of ESP32. For details, see `GPIO Header 2`_. - * - Function Switch - - A 4-bit DIP switch used to configure the functionality of selected GPIOs - of ESP32. For details see `Function Switch`_. - * - Tx/Rx LEDs - - Two LEDs to show the status of UART transmission. - * - FT2232H - - The FT2232H chip serves as a multi-protocol USB-to-serial bridge which - can be programmed and controlled via USB to provide communication with - ESP32. FT2232H also features USB-to-JTAG interface which is available - on channel A of the chip, while USB-to-serial is on channel B. - The FT2232H chip enhances user-friendliness in terms of application - development and debugging. See - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. - * - USB Port - - USB interface. Power supply for the board as well as the communication - interface between a computer and the board. - * - Power Switch - - Power On/Off Switch. Toggling the switch to **5V0** position powers the - board on, toggling to **GND** position powers the board off. - * - 5V Input - - The 5 V power supply interface can be more convenient when the board is - operating autonomously (not connected to a computer). - * - 5V Power On LED - - This red LED turns on when power is supplied to the board, either from - USB or 5 V Input. - * - DC/DC Converter - - Provided DC 5 V to 3.3 V conversion, output current up to 2 A. - * - Board B Connectors - - A pair male and female header pins for mounting the `PoE board (B)`_ - * - IP101GRI (PHY) - - The physical layer (PHY) connection to the Ethernet cable is - implemented using the - `IP101GRI `_ - chip. The connection between PHY and ESP32 is done through the reduced - media-independent interface (RMII), a variant of the media-independent - interface `(MII) `_ - standard. The PHY supports the IEEE 802.3/802.3u standard of 10/100 - Mbps. - * - RJ45 Port - - Ethernet network data transmission port. - * - Magnetics Module - - The Magnetics are part of the Ethernet specification to protect against - faults and transients, including rejection of common mode signals - between the transceiver IC and the cable. The magnetics also provide - galvanic isolation between the transceiver and the Ethernet device. - * - Link/Activity LEDs - - Two LEDs (green and red) that respectively indicate the "Link" and - "Activity" statuses of the PHY. - * - BOOT Button - - Download button. Holding down **BOOT** and then pressing **EN** - initiates Firmware Download mode for downloading firmware through the - serial port. - * - EN Button - - Reset button. - * - GPIO Header 1 - - This header provides six unpopulated through-hole solder pads connected - to spare GPIOs of ESP32. For details, see `GPIO Header 1`_. - -PoE Board (B) -^^^^^^^^^^^^^ - -This board coverts power delivered over the Ethernet cable (PoE) to provide a -power supply for the Ethernet board (A). The main components of the PoE board -(B) are shown on the block diagram under `Functionality Overview`_. - -The PoE board (B) has the following features: - -* Support for IEEE 802.3at -* Power output: 5 V, 1.4 A - -To take advantage of the PoE functionality the **RJ45 Port** of the Ethernet -board (A) should be connected with an Ethernet cable to a switch that supports -PoE. When the Ethernet board (A) detects 5 V power output from the PoE board -(B), the USB power will be automatically cut off. - -.. figure:: img/esp32-ethernet-kit-b-v1.0-layout.jpg - :align: center - :alt: ESP32-Ethernet-Kit - PoE board (B) - :figclass: align-center - - ESP32-Ethernet-Kit - PoE board (B) layout - -.. list-table:: Table PoE board (B) - :widths: 40 150 - :header-rows: 1 - - * - Key Component - - Description - * - Board A Connector - - Four female (left) and four male (right) header pins for connecting the - PoE board (B) to `Ethernet board (A)`_. The pins on the left accept - power coming from a PoE switch. The pins on the right deliver 5 V power - supply to the Ethernet board (A). - * - External Power Terminals - - Optional power supply (26.6 ~ 54 V) to the PoE board (B). - -.. _get-started-esp32-ethernet-kit-v1.2-setup-options: - - -Setup Options -============= - -This section describes options to configure the ESP32-Ethernet-Kit hardware. - - -Function Switch ---------------- - -When in On position, this DIP switch is routing listed GPIOs to FT2232H to -provide JTAG functionality. When in Off position, the GPIOs may be used for -other purposes. - -======= ================ -DIP SW GPIO Pin -======= ================ - 1 GPIO13 - 2 GPIO12 - 3 GPIO15 - 4 GPIO14 -======= ================ - - -RMII Clock Selection --------------------- - -The ethernet MAC and PHY under RMII working mode need a common 50 MHz -reference clock (i.e. RMII clock) that can be provided either externally, -or generated from internal ESP32 APLL (not recommended). - -.. note:: - - For additional information on the RMII clock selection, please refer to - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, - sheet 2, location D2. - - -RMII Clock Sourced Externally by PHY -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -By default, the ESP32-Ethernet-Kit is configured to provide RMII clock for the -IP101GRI PHY's 50M_CLKO output. The clock signal is generated by the frequency -multiplication of 25 MHz crystal connected to the PHY. For details, please see -the figure below. - -.. figure:: img/esp32-ethernet-kit-rmii-clk-from-phy.jpg - :align: center - :alt: RMII Clock from IP101GRI PHY - :figclass: align-center - - RMII Clock from IP101GRI PHY - -Please note that the PHY is reset on power up by pulling the RESET_N signal -down with a resistor. ESP32 should assert RESET_N high with GPIO5 to enable -PHY. Only this can ensure the power-up of system. Otherwise ESP32 may enter -download mode (when the clock signal of REF_CLK_50M is at a high logic level -during the GPIO0 power-up sampling phase). - - -RMII Clock Sourced Internally from ESP32's APLL -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Another option is to source the RMII Clock from internal ESP32 APLL, see -figure below. The clock signal coming from GPIO0 is first inverted, to account -for transmission line delay, and then supplied to the PHY. - -.. figure:: img/esp32-ethernet-kit-rmii-clk-to-phy.jpg - :align: center - :alt: RMII Clock from ESP Internal APLL - :figclass: align-center - - RMII Clock from ESP Internal APLL - -To implement this option, users need to remove or add some RC components on -the board. For details please refer to -`ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_, -sheet 2, location D2. Please note that if the APLL is already used for other -purposes (e.g. I2S peripheral), then you have no choice but use an external -RMII clock. - - -GPIO Allocation ---------------- - -This section describes allocation of ESP32 GPIOs to specific interfaces or -functions of the ESP32-Ethernet-Kit. - - -IP101GRI (PHY) Interface -^^^^^^^^^^^^^^^^^^^^^^^^ - -The allocation of the ESP32 (MAC) pins to IP101GRI (PHY) is shown in the table -below. Implementation of ESP32-Ethernet-Kit defaults to Reduced -Media-Independent Interface (RMII). - -==== ================ =============== -No. ESP32 Pin (MAC) IP101GRI (PHY) -==== ================ =============== -*RMII Interface* ---------------------------------------- - 1 GPIO21 TX_EN - 2 GPIO19 TXD[0] - 3 GPIO22 TXD[1] - 4 GPIO25 RXD[0] - 5 GPIO26 RXD[1] - 6 GPIO27 CRS_DV - 7 GPIO0 REF_CLK ----- ---------------- --------------- -*Serial Management Interface* ---------------------------------------- - 8 GPIO23 MDC - 9 GPIO18 MDIO ----- ---------------- --------------- -*PHY Reset* ---------------------------------------- -10 GPIO5 Reset_N -==== ================ =============== - -.. note:: - - The allocation of all pins under the ESP32's *RMII Interface* is fixed and - cannot be changed either through IO MUX or GPIO Matrix. REF_CLK can only - be selected from GPIO0, GPIO16 or GPIO17 and it can not be changed through - GPIO Matrix. - - -GPIO Header 1 -^^^^^^^^^^^^^ - -This header exposes some GPIOs that are not used elsewhere on the -ESP32-Ethernet-Kit. - -==== ================ -No. ESP32 Pin -==== ================ - 1 GPIO32 - 2 GPIO33 - 3 GPIO34 - 4 GPIO35 - 5 GPIO36 - 6 GPIO39 -==== ================ - - -GPIO Header 2 -^^^^^^^^^^^^^ - -This header contains GPIOs that may be used for other purposes depending on -scenarios described in column "Comments". - -==== ========== ==================== -No. ESP32 Pin Comments -==== ========== ==================== - 1 GPIO17 See note 1 - 2 GPIO16 See note 1 - 3 GPIO4 - 4 GPIO2 - 5 GPIO13 See note 2 - 6 GPIO12 See note 2 - 7 GPIO15 See note 2 - 8 GPIO14 See note 2 - 9 GND Ground -10 3V3 3.3 V power supply -==== ========== ==================== - -.. note:: - - 1. The ESP32 pins GPIO16 and GPIO17 are not broken out to the - ESP32-WROVER-E module and therefore not available for use. If you need - to use these pins, please solder a module without PSRAM memory inside, - e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. - - 2. Functionality depends on the settings of the `Function Switch`_. - - -GPIO Allocation Summary -^^^^^^^^^^^^^^^^^^^^^^^ - -.. csv-table:: - :header: ESP32-WROVER-E,IP101GRI,UART,JTAG,GPIO,Comments - - S_VP,,,,IO36, - S_VN,,,,IO39, - IO34,,,,IO34, - IO35,,,,IO35, - IO32,,,,IO32, - IO33,,,,IO33, - IO25,RXD[0],,,, - IO26,RXD[1],,,, - IO27,CRS_DV,,,, - IO14,,,TMS,IO14, - IO12,,,TDI,IO12, - IO13,,,TCK,IO13, - IO15,,,TDO,IO15, - IO2,,,,IO2, - IO0,REF_CLK,,,,See note 1 - IO4,,,,IO4, - IO16,,,,IO16 (NC),See note 2 - IO17,,,,IO17 (NC),See note 2 - IO5,Reset_N,,,,See note 1 - IO18,MDIO,,,, - IO19,TXD[0],,,, - IO21,TX_EN,,,, - RXD0,,RXD,,, - TXD0,,TXD,,, - IO22,TXD[1],,,, - IO23,MDC,,,, - -.. note:: - - 1. To prevent the power-on state of the GPIO0 from being affected by the - clock output on the PHY side, the RESET_N signal to PHY defaults to - low, turning the clock output off. After power-on you can control - RESET_N with GPIO5 to turn the clock output on. See also - `RMII Clock Sourced Externally by PHY`_. For PHYs that cannot turn off - the clock output through RESET_N, it is recommended to use a crystal - module that can be disabled/enabled externally. Similarly like when - using RESET_N, the oscillator module should be disabled by default and - turned on by ESP32 after power-up. For a reference design please see - `ESP32-Ethernet-Kit V1.2 Ethernet board (A) Schematic `_. - - 2. The ESP32 pins GPIO16 and GPIO17 are not broken out to the - ESP32-WROVER-E module and therefore not available for use. If you need - to use these pins, please solder a module without PSRAM memory inside, - e.g. the ESP32-WROOM-32D or ESP32-SOLO-1. - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32_ethernet_kit - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: build - -The usual ``flash`` target will work with the ``esp32_ethernet_kit`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32_ethernet_kit - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32_ethernet_kit - :goals: debug - - -Enabling Ethernet -***************** - -Enable Ethernet MAC, PHY and MDIO; add these to your device tree overlay: - -.. code-block:: devicetree - - ð { - status = "okay"; - }; - - &phy { - status = "okay"; - }; - - &mdio { - status = "okay"; - }; - -Enable Ethernet in KConfig: - -.. code-block:: cfg - - CONFIG_ETH_ESP32=y - CONFIG_NETWORKING=y - CONFIG_NET_L2_ETHERNET=y - -Board Init -========== - -RESET_N (GPIO5) is automatically set high to enable the Ethernet PHY -during board initialization (board_init.c) - -Related Documents -***************** - -* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) Schematic `_ (PDF) -* `ESP32-Ethernet-Kit PoE Board (B) Schematic `_ (PDF) -* `ESP32-Ethernet-Kit V1.2 Ethernet Board (A) PCB Layout `_ (PDF) -* `ESP32-Ethernet-Kit PoE Board (B) PCB Layout `_ (PDF) -* `ESP32 Datasheet `_ (PDF) -* `ESP32-WROVER-E Datasheet `_ (PDF) -* `OpenOCD ESP32 `_ diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts deleted file mode 100644 index 50b01b88b2f58f..00000000000000 --- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.dts +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2022 Grant Ramsay - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32_ethernet_kit-pinctrl.dtsi" - -/ { - model = "esp32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - - phy: ethernet-phy@1 { - compatible = "ethernet-phy"; - status = "disabled"; - reg = <1>; - }; -}; - -ð { - phy-handle = <&phy>; -}; diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml deleted file mode 100644 index 8f1167e1facaf7..00000000000000 --- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: esp32_ethernet_kit -name: ESP32 ETHERNET KIT -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - watchdog - - uart - - nvs - - pwm -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig b/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig deleted file mode 100644 index a9c99bec06b74c..00000000000000 --- a/boards/xtensa/esp32_ethernet_kit/esp32_ethernet_kit_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32_ETHERNET_KIT=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_franzininho/Kconfig.board b/boards/xtensa/esp32s2_franzininho/Kconfig.board deleted file mode 100644 index 7b52b4d88b12e1..00000000000000 --- a/boards/xtensa/esp32s2_franzininho/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 Franzininho board configuration - -# Copyright (c) 2022 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S2_FRANZININHO - bool "ESP32S2 Franzininho Board" - depends on SOC_SERIES_ESP32S2 - -choice SOC_PART_NUMBER - default SOC_ESP32S2_WROOM -endchoice diff --git a/boards/xtensa/esp32s2_franzininho/Kconfig.defconfig b/boards/xtensa/esp32s2_franzininho/Kconfig.defconfig deleted file mode 100644 index 2319c0061e4f3e..00000000000000 --- a/boards/xtensa/esp32s2_franzininho/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ESP32S2 Franzininho board configuration - -# Copyright (c) 2022 Felipe Neves -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s2_franzininho" - depends on BOARD_ESP32S2_FRANZININHO - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/xtensa/esp32s2_franzininho/doc/index.rst b/boards/xtensa/esp32s2_franzininho/doc/index.rst deleted file mode 100644 index 684fbf5dd5c303..00000000000000 --- a/boards/xtensa/esp32s2_franzininho/doc/index.rst +++ /dev/null @@ -1,174 +0,0 @@ -.. _esp32s2_franzininho: - -ESP32-S2 Franzininho -#################### - -Overview -******** - -Franzininho is an educational development board based on ESP32-S2 which is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, -designed to be secure and cost-effective, with a high performance and a rich set of IO capabilities. [1]_ - -The features include the following: - -- RSA-3072-based secure boot -- AES-XTS-256-based flash encryption -- Protected private key and device secrets from software access -- Cryptographic accelerators for enhanced performance -- Protection against physical fault injection attacks -- Various peripherals: - - - 43x programmable GPIOs - - 14x configurable capacitive touch GPIOs - - USB OTG - - LCD interface - - camera interface - - SPI - - I2S - - UART - - ADC - - DAC - - LED PWM with up to 8 channels - -.. figure:: img/esp32_s2_franzininho.jpg - :align: center - :alt: ESP32-S2 FRANZININHO - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s2_franzininho - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_franzininho - :goals: build - -The usual ``flash`` target will work with the ``esp32s2_franzininho`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_franzininho - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s2_franzininho - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-s2 -.. _`ESP32S2 Technical Reference Manual`: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf -.. _`ESP32S2 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig b/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig deleted file mode 100644 index 6d95a2f5567bf4..00000000000000 --- a/boards/xtensa/esp32s2_franzininho/esp32s2_franzininho_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - - -CONFIG_BOARD_ESP32S2_FRANZININHO=y -CONFIG_SOC_SERIES_ESP32S2=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_lolin_mini/Kconfig.board b/boards/xtensa/esp32s2_lolin_mini/Kconfig.board deleted file mode 100644 index 1f567f3f42b559..00000000000000 --- a/boards/xtensa/esp32s2_lolin_mini/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP32S2 LOLIN S2 MINI board configuration - -# Copyright (c) 2023 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S2_LOLIN_MINI - bool "ESP32S2 Lolin Mini Board" - depends on SOC_SERIES_ESP32S2 - -choice SOC_PART_NUMBER - default SOC_ESP32S2_FN4R2 -endchoice diff --git a/boards/xtensa/esp32s2_lolin_mini/Kconfig.defconfig b/boards/xtensa/esp32s2_lolin_mini/Kconfig.defconfig deleted file mode 100644 index 709b0d5b53b94f..00000000000000 --- a/boards/xtensa/esp32s2_lolin_mini/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ESP32S2 LOLIN S2 MINI board configuration - -# Copyright (c) 2023 Google, LLC -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s2_lolin_mini" - depends on BOARD_ESP32S2_LOLIN_MINI - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig b/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig deleted file mode 100644 index c8c04460dbe461..00000000000000 --- a/boards/xtensa/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S2_LOLIN_MINI=y -CONFIG_SOC_SERIES_ESP32S2=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s2_saola/Kconfig.board b/boards/xtensa/esp32s2_saola/Kconfig.board deleted file mode 100644 index 7d9e3a717ae2ed..00000000000000 --- a/boards/xtensa/esp32s2_saola/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP32S2_SAOLA - bool "ESP32S2 Saola Board" - depends on SOC_SERIES_ESP32S2 - -choice SOC_PART_NUMBER - default SOC_ESP32S2_WROVER_N4R2 -endchoice diff --git a/boards/xtensa/esp32s2_saola/Kconfig.defconfig b/boards/xtensa/esp32s2_saola/Kconfig.defconfig deleted file mode 100644 index 8b160c0293591b..00000000000000 --- a/boards/xtensa/esp32s2_saola/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ESP32S2 Saola board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s2_saola" - depends on BOARD_ESP32S2_SAOLA - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 32768 if WIFI - default 4096 diff --git a/boards/xtensa/esp32s2_saola/doc/index.rst b/boards/xtensa/esp32s2_saola/doc/index.rst deleted file mode 100644 index f52594c664953b..00000000000000 --- a/boards/xtensa/esp32s2_saola/doc/index.rst +++ /dev/null @@ -1,249 +0,0 @@ -.. _esp32s2_saola: - -ESP32-S2 -######## - -Overview -******** - -ESP32-S2 is a highly integrated, low-power, single-core Wi-Fi Microcontroller SoC, designed to be secure and -cost-effective, with a high performance and a rich set of IO capabilities. [1]_ - -The features include the following: - -- RSA-3072-based secure boot -- AES-XTS-256-based flash encryption -- Protected private key and device secrets from software access -- Cryptographic accelerators for enhanced performance -- Protection against physical fault injection attacks -- Various peripherals: - - - 43x programmable GPIOs - - 14x configurable capacitive touch GPIOs - - USB OTG - - LCD interface - - camera interface - - SPI - - I2S - - UART - - ADC - - DAC - - LED PWM with up to 8 channels - -Supported Features -================== - -Current Zephyr's ESP32-S2-saola board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s2_saola - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: build - -The usual ``flash`` target will work with the ``esp32s2_saola`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s2_saola - -Debugging -********* - -ESP32-S2 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -The following table shows the pin mapping between ESP32-S2 board and JTAG interface. - -+---------------+-----------+ -| ESP32 pin | JTAG pin | -+===============+===========+ -| MTDO / GPIO40 | TDO | -+---------------+-----------+ -| MTDI / GPIO41 | TDI | -+---------------+-----------+ -| MTCK / GPIO39 | TCK | -+---------------+-----------+ -| MTMS / GPIO42 | TMS | -+---------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging for ESP32-S2`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s2_saola - :goals: debug - -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/api-guides/jtag-debugging/index.html - - -References -********** - -.. [1] https://www.espressif.com/en/products/socs/esp32-s2 -.. _ESP32-S2 Saola User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s2/hw-reference/esp32s2/user-guide-saola-1-v1.2.html -.. _ESP32S2 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf -.. _ESP32S2 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s2_datasheet_en.pdf diff --git a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig b/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig deleted file mode 100644 index c7bacdd2ec6219..00000000000000 --- a/boards/xtensa/esp32s2_saola/esp32s2_saola_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S2_SAOLA=y -CONFIG_SOC_SERIES_ESP32S2=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.board b/boards/xtensa/esp32s3_devkitm/Kconfig.board deleted file mode 100644 index 3f899740c0dea9..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -# ESP32S3 DevKitM board configuration -config BOARD_ESP32S3_DEVKITM - bool "ESP32S3 DevKitM Board" - depends on SOC_SERIES_ESP32S3 - -config BOARD_ESP32S3_DEVKITM_APPCPU - bool "ESP32S3 Board configuration for APPCPU (core 1)." - depends on SOC_SERIES_ESP32S3 && SOC_ESP32S3_APPCPU - -choice SOC_PART_NUMBER - default SOC_ESP32S3_MINI_N8 -endchoice diff --git a/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig b/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig deleted file mode 100644 index 54a01595721103..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/Kconfig.defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# ESP32S3 DevKitM board configuration - -# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_ESP32S3_DEVKITM - -config BOARD - default "esp32s3_devkitm" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif - -if BOARD_ESP32S3_DEVKITM_APPCPU - -config BOARD - default "esp32s3_devkitm_appcpu" - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - def_int 4096 - -config KERNEL_BIN_NAME - default "esp32_appcpu_firmware" -endif - -config ENTROPY_GENERATOR - default y diff --git a/boards/xtensa/esp32s3_devkitm/doc/index.rst b/boards/xtensa/esp32s3_devkitm/doc/index.rst deleted file mode 100644 index 851246a75d4bcb..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/doc/index.rst +++ /dev/null @@ -1,286 +0,0 @@ -.. _esp32s3_devkitm: - -ESP32S3-DevKitM -############### - -Overview -******** - -The ESP32-S3-DevKitM is an entry-level development board equipped with either ESP32-S3-MINI-1 -or ESP32-S3-MINI-1U, a module named for its small size. This board integrates complete Wi-Fi -and Bluetooth Low Energy functions. For more information, check `ESP32-S3 DevKitM`_ - -Hardware -******** - -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. - -ESP32-S3 DevKitM includes the following features: - -- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz -- Additional vector instructions support for AI acceleration -- 512KB of SRAM -- 384KB of ROM -- Wi-Fi 802.11b/g/n -- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate - -Digital interfaces: - -- 45 programmable GPIOs -- 4x SPI -- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 -- 1x DVP 8-bit ~16-bit camera interface -- 3x UART -- 2x I2C -- 2x I2S -- 1x RMT (TX/RX) -- 1x pulse counter -- LED PWM controller, up to 8 channels -- 1x full-speed USB OTG -- 1x USB Serial/JTAG controller -- 2x MCPWM -- 1x SDIO host controller with 2 slots -- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels -- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) -- Addressable RGB LED, driven by GPIO48. - -Analog interfaces: - -- 2x 12-bit SAR ADCs, up to 20 channels -- 1x temperature sensor -- 14x touch sensing IOs - -Timers: - -- 4x 54-bit general-purpose timers -- 1x 52-bit system timer -- 3x watchdog timers - -Low Power: - -- Power Management Unit with five power modes -- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) - -Asymmetric Multiprocessing (AMP) -******************************** - -ESP32S3-DevKitM allows 2 different applications to be executed in ESP32-S3 SoC. Due to its dual-core -architecture, each core can be enabled to execute customized tasks in stand-alone mode -and/or exchanging data over OpenAMP framework. See :ref:`ipc_samples` folder as code reference. - -For more information, check the datasheet at `ESP32-S3 Datasheet`_. - -Supported Features -================== - -Current Zephyr's ESP32-S3-DevKitM board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s3_devkitm - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: build - -The usual ``flash`` target will work with the ``esp32s3_devkitm`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s3_devkitm - -Debugging -********* - -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_devkitm - :goals: debug - -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP32-S3 DevKitM`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html - -References -********** - -.. _ESP32-S3 DevKitM User Guide: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/hw-reference/esp32s3/user-guide-devkitm-1.html -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts deleted file mode 100644 index 640304ee00fa5a..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.dts +++ /dev/null @@ -1,183 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp32s3_devkitm-pinctrl.dtsi" -#include -#include - -/ { - model = "esp32s3_devkitm"; - compatible = "espressif,esp32s3"; - - aliases { - i2c-0 = &i2c0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - uart-0 = &uart0; - sw0 = &button0; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&touch { - debounce-interval-ms = <30>; - href-microvolt = <2700000>; - lref-microvolt = <500000>; - href-atten-microvolt = <1000000>; - filter-mode = ; - filter-debounce-cnt = <1>; - filter-noise-thr = ; - filter-jitter-step = <4>; - filter-smooth-level = ; -}; - -&i2c0 { - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; - bus-speed = <125000>; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&wdt0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&usb_serial { - status = "disabled"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml deleted file mode 100644 index cce4cb8b82e9ad..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: esp32s3_devkitm -name: ESP32-S3 DevKitM -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma - - input -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts deleted file mode 100644 index ae68f094e14c66..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.dts +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -/ { - model = "esp32s3_appcpu"; - compatible = "espressif,esp32s3_appcpu"; - - chosen { - zephyr,sram = &sram0; - zephyr,ipc_shm = &shm0; - zephyr,ipc = &ipm0; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&trng0 { - status = "okay"; -}; - -&ipm0 { - status = "okay"; -}; diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml deleted file mode 100644 index b6145d0f9651c3..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu.yaml +++ /dev/null @@ -1,26 +0,0 @@ -identifier: esp32s3_devkitm_appcpu -name: ESP32S3 DEVKITM APPCPU -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - flash - - cpp - - posix - - watchdog - - logging - - kernel - - pm - - gpio - - crypto - - eeprom - - heap - - cmsis_rtos - - jwt - - zdsp diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig deleted file mode 100644 index e554a9512635cc..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_ESP32S3=y -CONFIG_SOC_ESP32S3_APPCPU=y -CONFIG_BOARD_ESP32S3_DEVKITM_APPCPU=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CLOCK_CONTROL=y -CONFIG_MINIMAL_LIBC=y diff --git a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig b/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig deleted file mode 100644 index 1f8b52aa3604bc..00000000000000 --- a/boards/xtensa/esp32s3_devkitm/esp32s3_devkitm_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S3_DEVKITM=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_luatos_core/Kconfig.board b/boards/xtensa/esp32s3_luatos_core/Kconfig.board deleted file mode 100644 index 05e726bb4a0546..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/Kconfig.board +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -# ESP32S3 Core board configuration -config BOARD_ESP32S3_LUATOS_CORE - bool "ESP32S3 LuatOS Core Board with ch343 enabled" - depends on SOC_SERIES_ESP32S3 - -config BOARD_ESP32S3_LUATOS_CORE_USB - bool "ESP32S3 LuatOS Core Board with ch343 disabled" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_MINI_N8 -endchoice diff --git a/boards/xtensa/esp32s3_luatos_core/Kconfig.defconfig b/boards/xtensa/esp32s3_luatos_core/Kconfig.defconfig deleted file mode 100644 index 35d4a9bc3fc417..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP32S3 Core board configuration - -# Copyright (c) 2023 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp32s3_luatos_core" - depends on BOARD_ESP32S3_LUATOS_CORE || BOARD_ESP32S3_LUATOS_CORE_USB - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/esp32s3_luatos_core/doc/index.rst b/boards/xtensa/esp32s3_luatos_core/doc/index.rst deleted file mode 100644 index 9160a20fcf4743..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/doc/index.rst +++ /dev/null @@ -1,292 +0,0 @@ -.. _esp32s3_luatos_core: - -ESP32S3-Luatos-Core -################### - -Overview -******** - -The ESP32S3-LUATOS-CORE development board is a compact board based on Espressif ESP32-S3. -The board comes equipped with a 2.4GHz antenna and supports both Wi-Fi and Bluetooth functionalities. -For more information, check `ESP32S3-LUATOS-CORE`_ (chinese) - -.. image:: img/esp32s3_luatos_core.jpg - :align: center - :alt: esp32s3_luatos_core - -Hardware -******** - -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. - -ESP32S3-LUATOS-CORE includes the following features: - -- Dual core 32-bit Xtensa Microprocessor (Tensilica LX7), running up to 240MHz -- Additional vector instructions support for AI acceleration -- 512KB of SRAM -- 384KB of ROM -- 8MB of PSRAM -- 16MB of FLASH -- Wi-Fi 802.11b/g/n -- Bluetooth LE 5.0 with long-range support and up to 2Mbps data rate - -Digital interfaces: - -- 4x SPI -- 1x LCD interface (8-bit ~16-bit parallel RGB, I8080 and MOTO6800), supporting conversion between RGB565, YUV422, YUV420 and YUV411 -- 1x DVP 8-bit ~16-bit camera interface -- 3x UART -- 2x I2C -- 2x I2S -- 1x RMT (TX/RX) -- 1x pulse counter -- LED PWM controller, up to 8 channels -- 1x USB Port with USB switcher, supporting following modes: - - 1x full-speed USB OTG or 1x USB Serial/JTAG controller - - USB to serial chip CH343 -- 2x MCPWM -- 1x SDIO host controller with 2 slots -- General DMA controller (GDMA), with 5 transmit channels and 5 receive channels -- 1x TWAI® controller, compatible with ISO 11898-1 (CAN Specification 2.0) -- 2x Blue LED - -Analog interfaces: - -- 2x 12-bit SAR ADCs, up to 20 channels - -Timers: - -- 4x 54-bit general-purpose timers -- 1x 52-bit system timer -- 3x watchdog timers - -Low Power: - -- Power Management Unit with five power modes -- Ultra-Low-Power (ULP) coprocessors: ULP-RISC-V and ULP-FSM - -Security: - -- Secure boot -- Flash encryption -- 4-Kbit OTP, up to 1792 bits for users -- Cryptographic hardware acceleration: (AES-128/256, Hash, RSA, RNG, HMAC, Digital signature) - -For more information, check the datasheet at `ESP32-S3 Datasheet`_. - -.. image:: img/esp32s3_luatos_core_pinout.jpg - :align: center - :alt: esp32s3_luatos_core_pinout - -Supported Features -================== - -Current Zephyr's ESP32S3-LUATOS-Core board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ -| USB-CDC | on-chip | serial | -+------------+------------+-------------------------------------+ - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp32s3_luatos_core - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: build - -If CH343 chip is disabled, You need use the following command to build: - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core_usb - :goals: build - -The usual ``flash`` target will work with the ``esp32s3_luatos_core`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp32s3_luatos_core - -Debugging -********* - -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp32s3_luatos_core - :goals: debug - -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP32S3-LUATOS-CORE`: https://wiki.luatos.com/chips/esp32s3/board.html - -References -********** - -.. _ESP32S3-LUATOS-CORE User Guide: https://wiki.luatos.com/chips/esp32s3/board.html -.. _ESP32-S3 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-s3-mini-1_mini-1u_datasheet_en.pdf -.. _ESP32 Technical Reference Manual: https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dts b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dts deleted file mode 100644 index fea76fca3b7a01..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.dts +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2023 YuLong Yao - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include "esp32s3_luatos_core.dtsi" - -/ { - model = "esp32s3_luatos_core"; - compatible = "espressif,esp32s3"; - - aliases { - led0 = &led0; - led1 = &led1; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - uart-0 = &uart0; - sw0 = &button0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.yaml b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.yaml deleted file mode 100644 index eb850a58f95306..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32s3_luatos_core -name: ESP32-S3 Core -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_defconfig b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_defconfig deleted file mode 100644 index 59a3ecc3c4d004..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S3_LUATOS_CORE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.dts b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.dts deleted file mode 100644 index 686c977e36fc13..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.dts +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2023 YuLong Yao - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include "esp32s3_luatos_core.dtsi" - -/ { - model = "esp32s3_luatos_core"; - compatible = "espressif,esp32s3"; - - aliases { - led0 = &led0; - led1 = &led1; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - uart-0 = &usb_serial; - sw0 = &button0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - }; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "disabled"; -}; diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.yaml b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.yaml deleted file mode 100644 index a8680bb6544096..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: esp32s3_luatos_core_usb -name: ESP32-S3 Core USB -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb_defconfig b/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb_defconfig deleted file mode 100644 index 59a3ecc3c4d004..00000000000000 --- a/boards/xtensa/esp32s3_luatos_core/esp32s3_luatos_core_usb_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP32S3_LUATOS_CORE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/esp_wrover_kit/Kconfig.board b/boards/xtensa/esp_wrover_kit/Kconfig.board deleted file mode 100644 index eb255c7ec55f06..00000000000000 --- a/boards/xtensa/esp_wrover_kit/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ESP-WROVER-KIT board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ESP_WROVER_KIT - bool "ESP-WROVER-KIT Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N4R8 -endchoice diff --git a/boards/xtensa/esp_wrover_kit/Kconfig.defconfig b/boards/xtensa/esp_wrover_kit/Kconfig.defconfig deleted file mode 100644 index 378b557eb7f4fd..00000000000000 --- a/boards/xtensa/esp_wrover_kit/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# ESP-WROVER-KIT board configuration - -# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "esp_wrover_kit" - depends on BOARD_ESP_WROVER_KIT - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -config DISK_DRIVER_SDMMC - default y diff --git a/boards/xtensa/esp_wrover_kit/doc/index.rst b/boards/xtensa/esp_wrover_kit/doc/index.rst deleted file mode 100644 index 0154f2c9ad9f3d..00000000000000 --- a/boards/xtensa/esp_wrover_kit/doc/index.rst +++ /dev/null @@ -1,658 +0,0 @@ -.. _esp_wrover_kit: - -ESP-WROVER-KIT -############## - -Overview -******** - -ESP-WROVER-KIT is an ESP32-based development board produced by `Espressif `_. - -ESP-WROVER-KIT features the following integrated components: - -- ESP32-WROVER-E module -- LCD screen -- MicroSD card slot - -Its another distinguishing feature is the embedded FTDI FT2232HL chip - an advanced multi-interface -USB bridge. This chip enables to use JTAG for direct debugging of ESP32 through the USB interface -without a separate JTAG debugger. ESP-WROVER-KIT makes development convenient, easy, and -cost-effective. - -Most of the ESP32 I/O pins are broken out to the board's pin headers for easy access. - -.. note:: - - ESP32's GPIO16 and GPIO17 are used as chip select and clock signals for PSRAM. By default, the two - GPIOs are not broken out to the board's pin headers in order to ensure reliable performance. - -Functionality Overview -********************** - -The block diagram below shows the main components of ESP-WROVER-KIT and their interconnections. - -.. image:: img/esp-wrover-kit-block-diagram.jpg - :align: center - :alt: ESP-WROVER-KIT - -Functional Description -********************** - -The following two figures and the table below describe the key components, interfaces, and controls -of the ESP-WROVER-KIT board. - -.. figure:: img/esp-wrover-kit-v4.1-layout-front.jpg - :align: center - :alt: esp wrover front - - ESP-WROVER-KIT board layout - front - -.. _esp wrover back: - -.. figure:: img/esp-wrover-kit-v4.1-layout-back.jpg - :align: center - :alt: esp wrover back - - ESP-WROVER-KIT board layout - back - -The table below provides description in the following manner: -- Starting from the first picture’s top right corner and going clockwise -- Then moving on to the second picture - -+------------------+-------------------------------------------------------------------------+ -| Key Component | Description | -+==================+=========================================================================+ -| FT2232 | The FT2232 chip serves as a multi-protocol USB-to-serial bridge | -| | which can be programmed and controlled via USB to provide | -| | communication with ESP32. FT2232 also features USB-to-JTAG | -| | interface which is available on channel A of the chip, while USB-to- | -| | serial is on channel B. The FT2232 chip enhances user-friendliness in | -| | terms of application development and debugging. See `ESP-WROVER-KIT | -| | V4.1 schematic | -| | `_. | -+------------------+-------------------------------------------------------------------------+ -| 32.768 kHz | External precision 32.768 kHz crystal oscillator serves as a clock with | -| | low-power consumption while the chip is in Deep-sleep mode. | -+------------------+-------------------------------------------------------------------------+ -| 0R | Zero-ohm resistor intended as a placeholder for a current shunt, can | -| | be desoldered or replaced with a current shunt to facilitate the | -| | measurement of ESP32’s current consumption in different modes. | -+------------------+-------------------------------------------------------------------------+ -| ESP32-WROVER-E | This ESP32 module features 64-Mbit PSRAM for flexible extended | -| module | storage and data processing capabilities. | -+------------------+-------------------------------------------------------------------------+ -| Diagnostic LEDs | Four red LEDs connected to the GPIO pins of FT2232. Intended for | -| | future use. | -+------------------+-------------------------------------------------------------------------+ -| UART | Serial port. The serial TX/RX signals of FT2232 and ESP32 are broken | -| | out to the inward and outward sides of JP2 respectively. By default, | -| | these pairs of pins are connected with jumpers. To use ESP32’s serial | -| | interface, remove the jumpers and connect another external serial | -| | device to the respective pins. | -+------------------+-------------------------------------------------------------------------+ -| SPI | By default, ESP32 uses its SPI interface to access flash and PSRAM | -| | memory inside the module. Use these pins to connect ESP32 to | -| | another SPI device. In this case, an extra chip select (CS) signal is | -| | needed. Please note that the voltage of this interface is 3.3 V. | -+------------------+-------------------------------------------------------------------------+ -| CTS/RTS | Serial port flow control signals: the pins are not connected to the | -| | circuitry by default. To enable them, short the respective pins of JP14 | -| | with jumpers. | -+------------------+-------------------------------------------------------------------------+ -| JTAG | JTAG interface. JTAG signals of FT2232 and ESP32 are broken out to | -| | the inward and outward sides of JP2 respectively. By default, these | -| | pairs of pins are disconnected. To enable JTAG, short the respective | -| | pins with jumpers as shown in Section | -| | :ref:`Setup Options` | -+------------------+-------------------------------------------------------------------------+ -| USB Port | USB interface. Power supply for the board as well as the | -| | communication interface between a computer and the board. | -+------------------+-------------------------------------------------------------------------+ -| EN Button | Reset button. | -+------------------+-------------------------------------------------------------------------+ -| BOOT Button | Download button. Holding down Boot and then pressing EN initiates | -| | Firmware Download mode for downloading firmware through the | -+------------------+-------------------------------------------------------------------------+ -| Power Switch | Power On/Off Switch. Toggling toward the Boot button powers the | -| | board on, toggling away from Boot powers the board off. | -+------------------+-------------------------------------------------------------------------+ -| Power Selector | Power supply selector interface. The board can be powered either via | -| | USB or via the 5V Input interface. Select the power source with a | -| | jumper. For more details, see Section Setup Options, jumper header | -| | JP7. | -+------------------+-------------------------------------------------------------------------+ -| 5V input | 5V power supply interface for a standard coaxial power connector, | -| | 5.5 x 2.1 mm, center positive. This interface can be more convenient | -| | when the board is operating autonomously (not connected to a | -| | computer). | -+------------------+-------------------------------------------------------------------------+ -| 5V Power On LED | This red LED turns on when power is supplied to the board, either | -| | from USB or 5V Input. | -+------------------+-------------------------------------------------------------------------+ -| LDO | NCP1117(1A). 5V-to-3.3V LDO. NCP1117 can provide a maximum | -| | current of 1A. The LDO on the board has a fixed output voltage. | -| | Although, the user can install an LDO with adjustable output voltage. | -| | For details, please refer to `ESP-WROVER-KIT V4.1 schematic | -| | `_. | -+------------------+-------------------------------------------------------------------------+ -| Camera Connector | Camera interface, a standard OV7670 camera module. | -+------------------+-------------------------------------------------------------------------+ -| RGB LED | Red, green and blue (RGB) light emitting diodes (LEDs), can be | -| | controlled by pulse width modulation (PWM). | -+------------------+-------------------------------------------------------------------------+ -| I/O Connector | All the pins on the ESP32 module are broken out to pin headers. You | -| | can program ESP32 to enable multiple functions, such as PWM, ADC, | -| | DAC, I2C, I2S, SPI, etc. | -+------------------+-------------------------------------------------------------------------+ -| MicroSD Card | Useful for developing applications that access MicroSD card for data | -| Slot | storage and retrieval. | -+------------------+-------------------------------------------------------------------------+ -| LCD | Support for mounting and interfacing a 3.2” SPI (standard 4-wire | -| | Serial Peripheral Interface) LCD, as shown on figure | -| | :ref:`ESP-WROVER-KIT board layout - back` | -+------------------+-------------------------------------------------------------------------+ - -.. _setup options: - -Setup Options -************* - -There are three jumper blocks available to set up the board functionality. The most frequently -required options are listed in the table below. - -.. |jmpextpwr| image:: img/esp-wrover-kit-v4.1-jp7-ext_5v.jpg - -.. |jmpusbpwr| image:: img/esp-wrover-kit-v4.1-jp7-usb_5v.jpg - -.. |jmpjtag| image:: img/esp-wrover-kit-v4.1-jp2-jtag.jpg - -.. |jmpuart| image:: img/esp-wrover-kit-v4.1-jp2-tx-rx.jpg - -.. |jmpctrl| image:: img/esp-wrover-kit-v4.1-jp14.jpg - -+------------------+--------------------------------------------------------------+ -| Header | Jumper Setting | Description of Functionality | -+========+================+=======================================================+ -| JP7 | |jmpextpwr| | Power ESP-WROVER-KIT via an external power supply | -+--------+----------------+-------------------------------------------------------+ -| JP7 | |jmpusbpwr| | Power ESP-WROVER-KIT via USB | -+--------+----------------+-------------------------------------------------------+ -| JP2 | |jmpjtag| | Enable JTAG functionality | -+--------+----------------+-------------------------------------------------------+ -| JP2 | |jmpuart| | Enable UART communication | -+--------+----------------+-------------------------------------------------------+ -| JP14 | |jmpctrl| | Enable RTS/CTS flow control for serial communication | -+--------+----------------+-------------------------------------------------------+ - -Allocation of ESP32 Pins -************************ - -Some pins / terminals of ESP32 are allocated for use with the onboard or external hardware. If -that hardware is not used, e.g., nothing is plugged into the Camera (JP4) header, then these -GPIOs can be used for other purposes. - -Some of the pins, such as GPIO0 or GPIO2, have multiple functions and some of them are shared -among onboard and external peripheral devices. Certain combinations of peripherals cannot work -together. For example, it is not possible to do JTAG debugging of an application that is using -SD card, because several pins are shared by JTAG and the SD card slot. - -In other cases, peripherals can coexist under certain conditions. This is applicable to, for -example, LCD screen and SD card that share only a single pin GPIO21. This pin is used to provide -D/C (Data / Control) signal for the LCD as well as the Card Detect signal read from the SD card -slot. If the card detect functionality is not essential, then it may be disabled by removing R167, -so both LCD and SD may operate together. - -For more details on which pins are shared among which peripherals, please refer to the table in -the next section. - -Main I/O Connector / JP1 -************************ - -The JP1 connector consists of 14x2 male pins whose functions are shown in the middle two “I/O” -columns of the table below. The two “Shared With” columns on both sides describe where else on -the board a certain GPIO is used. - -+-------------------+------+------+----------------------+ -| Shared With | I/O | I/O | Shared With | -+===================+======+======+======================+ -| n/a | 3.3V | GND | n/a | -+-------------------+------+------+----------------------+ -| NC/XTAL | IO32 | IO33 | NC/XTAL | -+-------------------+------+------+----------------------+ -| JTAG, MicroSD | IO12 | IO13 | JTAG, MicroSD | -+-------------------+------+------+----------------------+ -| JTAG, MicroSD | IO14 | IO27 | Camera | -+-------------------+------+------+----------------------+ -| Camera | IO26 | IO25 | Camera, LCD | -+-------------------+------+------+----------------------+ -| Camera | IO35 | IO34 | Camera | -+-------------------+------+------+----------------------+ -| Camera | IO39 | IO36 | Camera | -+-------------------+------+------+----------------------+ -| JTAG | EN | IO23 | Camera, LCD | -+-------------------+------+------+----------------------+ -| Camera, LCD | IO22 | IO21 | Camera, LCD, MicroSD | -+-------------------+------+------+----------------------+ -| Camera, LCD | IO19 | IO18 | Camera, LCD | -+-------------------+------+------+----------------------+ -| Camera, LCD | IO5 | IO17 | PSRAM | -+-------------------+------+------+----------------------+ -| PSRAM | IO16 | IO4 | LED, Camera, MicroSD | -+-------------------+------+------+----------------------+ -| Camera, LED, Boot | IO0 | IO2 | LED, MicroSD | -+-------------------+------+------+----------------------+ -| JTAG, MicroSD | IO15 | 5V | | -+-------------------+------+------+----------------------+ - -Legend: - - - NC/XTAL - 32.768 kHz Oscillator - - JTAG - JTAG / JP2 - - Boot - Boot button / SW2 - - Camera - Camera / JP4 - - LED - RGB LED - - MicroSD - MicroSD Card / J4 - - LCD - LCD / U5 - - PSRAM - ESP32-WROVER-E’s PSRAM - -32.768 kHz Oscillator -********************* - -+---+-----------+ -| . | ESP32 Pin | -+===+===========+ -| 1 | GPIO32 | -+---+-----------+ -| 2 | GPIO33 | -+---+-----------+ - -.. note:: - - Since GPIO32 and GPIO33 are connected to the oscillator by default, they are not connected to - the JP1 I/O connector to maintain signal integrity. This allocation may be changed from the - oscillator to JP1 by desoldering the zero-ohm resistors from positions R11 / R23 and re- - soldering them to positions R12 / R24. - -SPI Flash / JP2 -*************** - -+---+--------------+ -| . | ESP32 Pin | -+===+==============+ -| 1 | CLK / GPIO6 | -+---+--------------+ -| 2 | SD0 / GPIO7 | -+---+--------------+ -| 3 | SD1 / GPIO8 | -+---+--------------+ -| 4 | SD2 / GPIO9 | -+---+--------------+ -| 5 | SD3 / GPIO10 | -+---+--------------+ -| 6 | CDM / GPIO11 | -+---+--------------+ - -.. important:: - The module’s flash bus is connected to the jumper block JP2 through zero-ohm resistors R140 ~ - R145. If the flash memory needs to operate at the frequency of 80 MHz, for reasons such as - improving the integrity of bus signals, you can desolder these resistors to disconnect the - module’s flash bus from the pin header JP2. - -JTAG / JP2 -********** - -+---+---------------+-------------+ -| . | ESP32 Pin | JTAG Signal | -+===+===============+=============+ -| 1 | EN | TRST_N | -+---+---------------+-------------+ -| 2 | MTMS / GPIO14 | TMS | -+---+---------------+-------------+ -| 3 | MTDO / GPIO15 | TDO | -+---+---------------+-------------+ -| 4 | MTDI / GPIO12 | TDI | -+---+---------------+-------------+ -| 5 | MTCK / GPIO13 | TCK | -+---+---------------+-------------+ - -Camera / JP4 -************ - -+----+-----------+-----------------------------+ -| . | ESP32 Pin | Camera Signal | -+====+===========+=============================+ -| 1 | n/a | 3.3V | -+----+-----------+-----------------------------+ -| 2 | n/a | Ground | -+----+-----------+-----------------------------+ -| 3 | GPIO27 | SIO_C / SCCB Clock | -+----+-----------+-----------------------------+ -| 4 | GPIO26 | SIO_D / SCCB Data | -+----+-----------+-----------------------------+ -| 5 | GPIO25 | VSYNC / Vertical Sync | -+----+-----------+-----------------------------+ -| 6 | GPIO23 | HREF / Horizontal Reference | -+----+-----------+-----------------------------+ -| 7 | GPIO22 | PCLK / Pixel Clock | -+----+-----------+-----------------------------+ -| 8 | GPIO21 | XCLK / System Clock | -+----+-----------+-----------------------------+ -| 9 | GPIO35 | D7 / Pixel Data Bit 7 | -+----+-----------+-----------------------------+ -| 10 | GPIO34 | D6 / Pixel Data Bit 6 | -+----+-----------+-----------------------------+ -| 11 | GPIO39 | D5 / Pixel Data Bit 5 | -+----+-----------+-----------------------------+ -| 12 | GPIO36 | D4 / Pixel Data Bit 4 | -+----+-----------+-----------------------------+ -| 13 | GPIO19 | D3 / Pixel Data Bit 3 | -+----+-----------+-----------------------------+ -| 14 | GPIO18 | D2 / Pixel Data Bit 2 | -+----+-----------+-----------------------------+ -| 15 | GPIO5 | D1 / Pixel Data Bit 1 | -+----+-----------+-----------------------------+ -| 16 | GPIO4 | D0 / Pixel Data Bit 0 | -+----+-----------+-----------------------------+ -| 17 | GPIO0 | RESET / Camera Reset | -+----+-----------+-----------------------------+ -| 18 | n/a | PWDN / Camera Power Down | -+----+-----------+-----------------------------+ - -- Signals D0 .. D7 denote camera data bus - -RGB LED -******* - -+----+-----------+---------+ -| . | ESP32 Pin | RGB LED | -+====+===========+=========+ -| 1 | GPIO0 | Red | -+----+-----------+---------+ -| 2 | GPIO2 | Green | -+----+-----------+---------+ -| 3 | GPIO4 | Blue | -+----+-----------+---------+ - -MicroSD Card -************ - -+---+---------------+----------------+ -| . | ESP32 Pin | MicroSD Signal | -+===+===============+================+ -| 1 | MTDI / GPIO12 | DATA2 | -+---+---------------+----------------+ -| 2 | MTCK / GPIO13 | CD / DATA3 | -+---+---------------+----------------+ -| 3 | MTDO / GPIO15 | CMD | -+---+---------------+----------------+ -| 4 | MTMS / GPIO14 | CLK | -+---+---------------+----------------+ -| 5 | GPIO2 | DATA0 | -+---+---------------+----------------+ -| 6 | GPIO4 | DATA1 | -+---+---------------+----------------+ -| 7 | GPIO21 | Card Detect | -+---+---------------+----------------+ - -LCD / U5 -******** - -+---+-----------+------------+ -| . | ESP32 Pin | LCD Signal | -+===+===========+============+ -| 1 | GPIO18 | RESET | -+---+-----------+------------+ -| 2 | GPIO19 | SCL | -+---+-----------+------------+ -| 3 | GPIO21 | D/C | -+---+-----------+------------+ -| 4 | GPIO22 | CS | -+---+-----------+------------+ -| 5 | GPIO23 | SDA | -+---+-----------+------------+ -| 6 | GPIO25 | SDO | -+---+-----------+------------+ -| 7 | GPIO5 | Backlight | -+---+-----------+------------+ - -Start Application Development -***************************** - -Before powering up your ESP-WROVER-KIT, please make sure that the board is in good -condition with no obvious signs of damage. - -Initial Setup -************* - -Please set only the following jumpers shown in the pictures below: - -- Select USB as the power source using the jumper block JP7. -- Enable UART communication using the jumper block JP2. - -+------------------------+---------------------------+ -| Power up from USB port | Enable UART communication | -+========+===============+===========================+ -| |jmpusbpwr| | |jmpuart| | -+------------------------+---------------------------+ - -Do not install any other jumpers. - -Turn the Power Switch to ON, the 5V Power On LED should light up. - -Supported Features -================== - -Current Zephyr's ESP32-Wrover-Kit board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: esp_wrover_kit - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: build - -The usual ``flash`` target will work with the ``esp_wrover_kit`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! esp_wrover_kit - -Debugging -********* - -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the ESP-WROVER-KIT board, the JTAG pins are connected internally to -a USB serial port on the same device as the console. These boards -require no external hardware and are debuggable as-is. The JTAG -signals, however, must be jumpered closed to connect the internal -controller (the default is to leave them disconnected). The jumper -headers are on the right side of the board as viewed from the power -switch, next to similar headers for SPI and UART. See -`ESP-WROVER-32 V3 Getting Started Guide`_ for details. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: esp_wrover_kit - :goals: debug - -.. _`OpenOCD`: https://github.com/openocd-org/openocd -.. _`ESP-WROVER-32 V3 Getting Started Guide`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/esp32/get-started-wrover-kit.html - -Related Documents -***************** - -.. _ESP-WROVER-KIT V4.1 schematics: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4_1.pdf (PDF) -.. _ESP-WROVER-KIT V4.1 layout: https://dl.espressif.com/dl/schematics/ESP-WROVER-KIT_V4.1.dxf (DXF) -.. _ESP32 Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf (PDF) -.. _ESP32-WROVER-E Datasheet: https://www.espressif.com/sites/default/files/documentation/esp32-wrover-e_esp32-wrover-ie_datasheet_en.pdf (PDF) -.. _ESP32 Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.dts b/boards/xtensa/esp_wrover_kit/esp_wrover_kit.dts deleted file mode 100644 index 3a31d745d63172..00000000000000 --- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.dts +++ /dev/null @@ -1,227 +0,0 @@ -/* - * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "esp_wrover_kit-pinctrl.dtsi" - -/ { - model = "esp32"; - compatible = "espressif,esp32"; - - aliases { - led0 = &blue_led; - led1 = &green_led; - led2 = &red_led; - pwm-led0 = &pwm_led_red; - pwm-led1 = &pwm_led_green; - pwm-led2 = &pwm_led_blue; - red-pwm-led = &pwm_led_red; - green-pwm-led = &pwm_led_green; - blue-pwm-led = &pwm_led_blue; - uart-0 = &uart0; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &ili9341; - }; - - leds { - compatible = "gpio-leds"; - - blue_led: led_0 { - gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; - label = "Blue - LED0"; - }; - - green_led: led_1 { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - label = "Green - LED1"; - }; - - red_led: led_2 { - gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; - label = "Red - LED2"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led_red: pwm_led_0 { - label = "Red PWM LED"; - pwms = <&ledc0 0 PWM_HZ(100) PWM_POLARITY_NORMAL>; - }; - pwm_led_green: pwm_led_1 { - label = "Green PWM LED"; - pwms = <&ledc0 1 PWM_HZ(100) PWM_POLARITY_NORMAL>; - }; - pwm_led_blue: pwm_led_2 { - label = "Blue PWM LED"; - pwms = <&ledc0 2 PWM_HZ(100) PWM_POLARITY_NORMAL>; - }; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - spi-dev = <&spi3>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9341: ili9341@0 { - compatible = "ilitek,ili9341"; - mipi-max-frequency = <25000000>; - reg = <0>; - pixel-format = <0>; - rotation = <0>; - width = <240>; - height = <320>; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; - - /* FIXME: should be part of the display node */ - lcd-backlight { - gpio-hog; - gpios = <5 GPIO_ACTIVE_HIGH>; - output-low; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&ledc0 { - pinctrl-0 = <&ledc0_default>; - pinctrl-names = "default"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - channel0@0 { - reg = <0x0>; - timer = <0>; - }; - channel1@1 { - reg = <0x1>; - timer = <1>; - }; - channel2@2 { - reg = <0x2>; - timer = <2>; - }; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.yaml b/boards/xtensa/esp_wrover_kit/esp_wrover_kit.yaml deleted file mode 100644 index 3d1b9921904dc5..00000000000000 --- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: esp_wrover_kit -name: ESP WROVER KIT -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - spi - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig b/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig deleted file mode 100644 index f2b8f7b663c22d..00000000000000 --- a/boards/xtensa/esp_wrover_kit/esp_wrover_kit_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ESP_WROVER_KIT=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board b/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board deleted file mode 100644 index b364fad83fdf06..00000000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# HELTEC ESP32 board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HELTEC_WIFI_LORA32 - bool "HELTEC WiFi LoRa 32 (V2) Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_D0WD_V3 -endchoice diff --git a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.defconfig b/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.defconfig deleted file mode 100644 index eaf538cd28127c..00000000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# HELTEC board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "heltec_wifi_lora32" - depends on BOARD_HELTEC_WIFI_LORA32 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/heltec_wifi_lora32_v2/doc/index.rst b/boards/xtensa/heltec_wifi_lora32_v2/doc/index.rst deleted file mode 100644 index 1029b21dd6049e..00000000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/doc/index.rst +++ /dev/null @@ -1,208 +0,0 @@ -.. _heltec_wifi_lora32_v2: - -Heltec WiFi LoRa 32 (V2) -######################## - -Overview -******** - -Heltec WiFi LoRa 32 is a classic IoT dev-board designed & produced by Heltec Automation(TM), it's a highly -integrated product based on ESP32 + SX127x, it has Wi-Fi, BLE, LoRa functions, also Li-Po battery management -system, 0.96" OLED are also included. [1]_ - -The features include the following: - -- Microprocessor: ESP32 (dual-core 32-bit MCU + ULP core) -- LoRa node chip SX1276/SX1278 -- Micro USB interface with a complete voltage regulator, ESD protection, short circuit protection, - RF shielding, and other protection measures -- Onboard SH1.25-2 battery interface, integrated lithium battery management system -- Integrated WiFi, LoRa, Bluetooth three network connections, onboard Wi-Fi, Bluetooth dedicated 2.4GHz - metal 3D antenna, reserved IPEX (U.FL) interface for LoRa use -- Onboard 0.96-inch 128*64 dot matrix OLED display -- Integrated CP2102 USB to serial port chip - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: build - -The usual ``flash`` target will work with the ``heltec_wifi_lora32_v2`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! heltec_wifi_lora32_v2 - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wifi_lora32_v2 - :goals: debug - -Utilizing Hardware Features -*************************** - -Onboard OLED display -==================== - -The onboard OLED display is of type ``ssd1306``, has 128*64 pixels and is -connected via I2C. It can therefore be used by enabling the -:ref:`ssd1306_128_shield` as shown in the following for the :zephyr:code-sample:`lvgl` sample: - -.. zephyr-app-commands:: - :zephyr-app: samples/subsys/display/lvgl - :board: heltec_wifi_lora32_v2 - :shield: ssd1306_128x64 - :goals: flash - -References -********** - -- `Heltec WiFi LoRa (v2) Pinout Diagram `_ -- `Heltec WiFi LoRa (v2) Schematic Diagrams `_ -- `ESP32 Toolchain `_ -- `esptool documentation `_ -- `OpenOCD ESP32 `_ - -.. [1] https://heltec.org/project/wifi-lora-32/ diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.dts b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.dts deleted file mode 100644 index 636f1afd354317..00000000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.dts +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "heltec_wifi_lora32_v2-pinctrl.dtsi" -#include - -/ { - model = "heltec_wifi_lora32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - led0 = &led0; - sw0 = &button0; - watchdog0 = &wdt0; - lora0 = &lora0; - }; - - leds { - compatible = "gpio-leds"; - led0: led { - gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; - label = "White LED"; - }; - - vext: vext { - gpios = <&gpio0 21 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "External VCC"; - }; - - oledrst: oledrst { - gpios = <&gpio0 16 (GPIO_PULL_UP | GPIO_ACTIVE_HIGH)>; - label = "OLED Reset"; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "PRG Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; - lora0: lora@0 { - compatible = "semtech,sx1276"; - reg = <0>; - reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - dio-gpios = - /* SX1276 D0 -> GPIO26 */ - <&gpio0 26 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D1 -> GPIO35 */ - <&gpio1 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>, - /* SX1276 D1 -> GPIO34 */ - <&gpio1 2 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>; - spi-max-frequency = <1000000>; - power-amplifier-output = "pa-boost"; - }; -}; - -&flash0 { - /* the board is using plain d0wd SoC part without the flash - * so any additional flash size should be defined at the board level - */ - reg = <0x0 DT_SIZE_M(8)>; - - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; - -/* Required by the ssd1306_128x64 shield which enables the OLED display */ -arduino_i2c: &i2c0 {}; diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.yaml b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.yaml deleted file mode 100644 index 740755b5e6a407..00000000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2.yaml +++ /dev/null @@ -1,17 +0,0 @@ -identifier: heltec_wifi_lora32_v2 -name: HELTEC WiFi LoRa 32 (V2) Board -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - watchdog - - uart - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig b/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig deleted file mode 100644 index ac8cf88d749446..00000000000000 --- a/boards/xtensa/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_HELTEC_WIFI_LORA32=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.board b/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.board deleted file mode 100644 index a590916109dc30..00000000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.board +++ /dev/null @@ -1,13 +0,0 @@ -# Heltec Wireless Stick Lite (V3) board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# Copyright (c) 2023 The Zephyr Project Contributors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_HELTEC_WIRELESS_STICK_LITE - bool "Heltec Wireless Stick Lite (V3) Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.defconfig b/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.defconfig deleted file mode 100644 index ea79f62e2fae94..00000000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Heltec Wireless Stick Lite (V3) board configuration - -# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) -# Copyright (c) 2023 The Zephyr Project Contributors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "heltec_wireless_stick_lite_v3" - depends on BOARD_HELTEC_WIRELESS_STICK_LITE - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/xtensa/heltec_wireless_stick_lite_v3/doc/index.rst deleted file mode 100644 index 24170d4cb1b7ff..00000000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/doc/index.rst +++ /dev/null @@ -1,306 +0,0 @@ -.. heltec_wireless_stick_lite_v3: - -HelTec Wireless Stick Lite (V3) -############################### - -Overview -******** - -HelTec Wireless Stick Lite (V3) is a development board with Wi-Fi, Bluetooth and LoRa support. It is designed and produced by HelTec Automation(TM). [1]_ - -.. figure:: heltec_wireless_stick_lite_v3.webp - :width: 400px - :align: center - :alt: HelTec Wireless Stick Lite (V3) - - HelTec Wireless Stick Lite (V3) (Credit: Chengdu HelTec Automation Technology Co., Ltd.) - -Hardware -******** - -The main hardware features are: - -- ESP32-S3FN8 low-power MCU-based SoC (dual-core Xtensa® 32-bit LX7 microprocessor, five stage pipeline rack Structure, main frequency up to 240 MHz). -- Semtech SX1262 LoRa node chip -- Type-C USB interface with a complete voltage regulator, ESD protection, short circuit protection, RF shielding, and other protection measures (note: you need an USB-A to USB-C cable if you want to power-up the board from USB). -- Onboard SH1.25-2 battery interface, integrated lithium battery management system (charge and discharge management, overcharge protection, battery power detection, USB / battery power automatic switching). -- Integrated WiFi and Bluetooth interfaces with 2.4GHz metal spring antenna and reserved IPEX (U.FL) interface for LoRa use. -- Integrated CP2102 USB to serial port chip, convenient for program downloading, debugging information printing. -- Good RF circuit design and low-power design. - -Supported Features -================== -- LoRa via SPI -- UART0 (USB Serial via CP2102) -- UART1 -- I2C -- CAN (optional, need to enable) -- PWM LED -- User Switch / Button - -Connections and IOs -=================== - -.. figure:: heltec_wireless_stick_lite_v3_pinout.webp - :width: 600px - :align: center - :alt: HelTec Wireless Stick Lite (V3) Pinout - - Pinout (Credit: Chengdu HelTec Automation Technology Co., Ltd.) - -.. table:: HelTec Wireless Stick Lite (V3) Pinout - :widths: auto - - +--------+---------+-----------------------------+ - | Header | Function| Description | - +========+=========+=============================+ - | J2.1 | Ve | | - +--------+---------+-----------------------------+ - | J2.2 | GND | | - +--------+---------+-----------------------------+ - | J2.3 | | | - +--------+---------+-----------------------------+ - | J2.4 | U0RXD | Zephyr Console+Shell | - +--------+---------+-----------------------------+ - | J2.5 | U0TXD | Zephyr Console+Shell | - +--------+---------+-----------------------------+ - | J2.6 | | | - +--------+---------+-----------------------------+ - | J2.7 | | | - +--------+---------+-----------------------------+ - | J2.8 | GPIO35 | PWM LED Control | - +--------+---------+-----------------------------+ - | J2.9 | GPIO36 | Vext Control | - +--------+---------+-----------------------------+ - | J2.10 | GPIO37 | ADC Control | - +--------+---------+-----------------------------+ - | J2.11 | | | - +--------+---------+-----------------------------+ - | J2.12 | GPIO39 | | - +--------+---------+-----------------------------+ - | J2.13 | GPIO40 | | - +--------+---------+-----------------------------+ - | J2.14 | GPIO41 | | - +--------+---------+-----------------------------+ - | J2.15 | GPIO42 | | - +--------+---------+-----------------------------+ - | J2.16 | GPIO45 | | - +--------+---------+-----------------------------+ - | J2.17 | GPIO46 | | - +--------+---------+-----------------------------+ - | J2.18 | ADC1_CH0| Battery Voltage Measurement | - +--------+---------+-----------------------------+ - | J2.19 | | | - +--------+---------+-----------------------------+ - | J2.20 | | | - +--------+---------+-----------------------------+ - | J3.1 | 5V | | - +--------+---------+-----------------------------+ - | J3.2 | 3V3 | | - +--------+---------+-----------------------------+ - | J3.3 | GND | | - +--------+---------+-----------------------------+ - | J3.4 | GPIO47 | | - +--------+---------+-----------------------------+ - | J3.5 | GPIO48 | | - +--------+---------+-----------------------------+ - | J3.6 | GPIO0 | User Switch | - +--------+---------+-----------------------------+ - | J3.7 | | | - +--------+---------+-----------------------------+ - | J3.8 | | | - +--------+---------+-----------------------------+ - | J3.9 | U1RXD | UART 1 | - +--------+---------+-----------------------------+ - | J3.10 | GPIO21 | | - +--------+---------+-----------------------------+ - | J3.11 | | | - +--------+---------+-----------------------------+ - | J3.12 | U1TXD | UART 1 | - +--------+---------+-----------------------------+ - | J3.13 | | | - +--------+---------+-----------------------------+ - | J3.14 | NC | Reset Switch | - +--------+---------+-----------------------------+ - | J3.15 | | | - +--------+---------+-----------------------------+ - | J3.16 | | | - +--------+---------+-----------------------------+ - | J3.17 | | | - +--------+---------+-----------------------------+ - | J3.18 | | | - +--------+---------+-----------------------------+ - | J3.19 | TWAI_TX | CAN (optional) | - +--------+---------+-----------------------------+ - | J3.20 | TWAI_RX | CAN (optional) | - +--------+---------+-----------------------------+ - - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Programming and Debugging -************************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the EPS32-S3 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32S3 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: build - -The usual ``flash`` target will work with the ``heltec_wireless_stick_lite_v3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! heltec_wireless_stick_lite_v3 - -Debugging -========= - -As with much custom hardware, the ESP32S3 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: heltec_wireless_stick_lite_v3 - :goals: debug - -References -********** - -- `Heltec Wireless Stick Lite (v3) Pinout Diagram `_ -- `Heltec Wireless Stick Lite (v3) Schematic Diagrams `_ -- `ESP-IDF Programming Guide `_ -- `esptool documentation `_ -- `OpenOCD ESP32 `_ - -.. [1] https://heltec.org/project/wireless-stick-lite-v2/ diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.dts b/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.dts deleted file mode 100644 index 9a23a008c2f245..00000000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.dts +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * Copyright (c) 2023 The Zephyr Project Contributors - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "heltec_wireless_stick_lite_v3-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "heltec_wireless_stick_lite_v3"; - compatible = "espressif,esp32s3"; - - aliases { - pwm-0 = &ledc0; - pwm-led0 = &pwm_led_white; - uart-0 = &uart0; - uart-1 = &uart1; - i2c-0 = &i2c0; - lora0 = &lora0; - sw0 = &button0; - watchdog0 = &wdt0; - }; - - leds { - compatible = "gpio-leds"; - - vext: vext { - gpios = <&gpio0 36 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Vext Control"; - }; - - adc: adc { - gpios = <&gpio0 37 GPIO_ACTIVE_LOW>; - label = "ADC Control"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led_white: pwm_led_gpio0_35 { - label = "White PWM LED"; - pwms = <&ledc0 0 PWM_MSEC(10) PWM_POLARITY_NORMAL>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "USER SW"; - zephyr,code = ; - }; - }; - - vbatt { - compatible = "voltage-divider"; - io-channels = <&adc1 0>; - output-ohms = <100000>; - full-ohms = <(100000 + 390000)>; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&adc1 { - status ="okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&ledc0 { - pinctrl-0 = <&ledc0_default>; - pinctrl-names = "default"; - status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - channel0@0 { - reg = <0x0>; - timer = <0>; - }; -}; - -&i2c0 { - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; - lora0: lora@0 { - compatible = "semtech,sx1262"; - reg = <0>; - reset-gpios = <&gpio0 12 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - busy-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; - dio1-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - dio2-tx-enable; - dio3-tcxo-voltage = ; - tcxo-power-startup-delay-ms = <5>; - spi-max-frequency = <16000000>; - }; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; - bus-speed = <125000>; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 64kB for the bootloader */ - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x00010000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.yaml b/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.yaml deleted file mode 100644 index 05c89b6d984257..00000000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: heltec_wireless_stick_lite_v3 -name: Heltec Wireless Stick Lite (V3) -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma - - lora -testing: - ignore_tags: - - net - - bluetooth diff --git a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_defconfig b/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_defconfig deleted file mode 100644 index a32ddde0422cdf..00000000000000 --- a/boards/xtensa/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_HELTEC_WIRELESS_STICK_LITE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CLOCK_CONTROL=y -CONFIG_CONSOLE=y -CONFIG_GPIO=y -CONFIG_PWM=y -CONFIG_SERIAL=y -CONFIG_SPI=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/index.rst b/boards/xtensa/index.rst deleted file mode 100644 index efe46624acf70f..00000000000000 --- a/boards/xtensa/index.rst +++ /dev/null @@ -1,10 +0,0 @@ -.. _boards-xtensa: - -Xtensa Boards -############# - -.. toctree:: - :maxdepth: 1 - :glob: - - **/index diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.board b/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.board deleted file mode 100644 index d51735c9caa0b6..00000000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADSP_ACE15_MTPM - bool "Intel ADSP ACE 1.5 Meteor PCH M" - depends on SOC_SERIES_INTEL_ACE diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.defconfig b/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.defconfig deleted file mode 100644 index ca7aa07cd95e28..00000000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADSP_ACE15_MTPM - -config BOARD - default "intel_adsp_ace15_mtpm" - -if DAI_INTEL_SSP - -config DAI_SSP_HAS_POWER_CONTROL - def_bool y - -endif - -endif # BOARD_INTEL_ADSP_ACE15_MTPM diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/board.cmake b/boards/xtensa/intel_adsp_ace15_mtpm/board.cmake deleted file mode 100644 index e9778da4d8449f..00000000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/board.cmake +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -board_set_rimage_target(mtl) - -set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace15_mtpm/board.cmake") - -board_finalize_runner_args(intel_adsp) diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm_defconfig b/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm_defconfig deleted file mode 100644 index b544d3db403c19..00000000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/intel_adsp_ace15_mtpm_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_SOC_SERIES_INTEL_ACE=y -CONFIG_SOC_INTEL_ACE15_MTPM=y -CONFIG_BOARD_INTEL_ADSP_ACE15_MTPM=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_MM_DRV=y -CONFIG_CRYPTO=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_ace15_mtpm/pre_dt_board.cmake b/boards/xtensa/intel_adsp_ace15_mtpm/pre_dt_board.cmake deleted file mode 100644 index 7a471ca8758f02..00000000000000 --- a/boards/xtensa/intel_adsp_ace15_mtpm/pre_dt_board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - dmic0: dmic0@10000 & dmic1: dmic1@10000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board deleted file mode 100644 index 26994dfb6c5f0c..00000000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADSP_ACE20_LNL - bool "Intel ADSP ACE 2.0 Lunar Lake PCH" - depends on SOC_SERIES_INTEL_ACE diff --git a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig b/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig deleted file mode 100644 index 756481eba01fb4..00000000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADSP_ACE20_LNL - -config BOARD - default "intel_adsp_ace20_lnl" - -endif # BOARD_INTEL_ADSP_ACE20_LNL diff --git a/boards/xtensa/intel_adsp_ace20_lnl/board.cmake b/boards/xtensa/intel_adsp_ace20_lnl/board.cmake deleted file mode 100644 index 04d679fba023c0..00000000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/board.cmake +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS acesim) - -board_set_rimage_target(lnl) - -set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in ace20_lnl/board.cmake") diff --git a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig b/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig deleted file mode 100644 index 9be759e2e9ab46..00000000000000 --- a/boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl_defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_SOC_SERIES_INTEL_ACE=y -CONFIG_SOC_INTEL_ACE20_LNL=y -CONFIG_BOARD_INTEL_ADSP_ACE20_LNL=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_BUILD_OUTPUT_BIN=n -CONFIG_MM_DRV=y -CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.board b/boards/xtensa/intel_adsp_cavs25/Kconfig.board deleted file mode 100644 index 275d43b3c778a6..00000000000000 --- a/boards/xtensa/intel_adsp_cavs25/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_INTEL_ADSP_CAVS25 - bool "Intel ADSP CAVS 2.5" - depends on SOC_SERIES_INTEL_ADSP_CAVS - -config BOARD_INTEL_ADSP_CAVS25_TGPH - bool "Intel ADSP CAVS 2.5 for Tiger Lake H PCH" - depends on SOC_SERIES_INTEL_ADSP_CAVS diff --git a/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig b/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig deleted file mode 100644 index 03d5c7a1ad359d..00000000000000 --- a/boards/xtensa/intel_adsp_cavs25/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_INTEL_ADSP_CAVS25 || BOARD_INTEL_ADSP_CAVS25_TGPH - -config BOARD - default "intel_adsp_cavs25" if BOARD_INTEL_ADSP_CAVS25 - default "intel_adsp_cavs25_tgph" if BOARD_INTEL_ADSP_CAVS25_TGPH - - - -if DAI_INTEL_SSP - -config DAI_SSP_HAS_POWER_CONTROL - def_bool y - -endif - -endif # BOARD_INTEL_ADSP_CAVS25 || BOARD_INTEL_ADSP_CAVS25_TGPH diff --git a/boards/xtensa/intel_adsp_cavs25/board.cmake b/boards/xtensa/intel_adsp_cavs25/board.cmake deleted file mode 100644 index 1bdb2698c12feb..00000000000000 --- a/boards/xtensa/intel_adsp_cavs25/board.cmake +++ /dev/null @@ -1,20 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if($ENV{CAVS_OLD_FLASHER}) - board_set_flasher_ifnset(misc-flasher) - board_finalize_runner_args(misc-flasher) -endif() - -board_set_flasher_ifnset(intel_adsp) - -set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default in cavs25/board.cmake") - -if(CONFIG_BOARD_INTEL_ADSP_CAVS25) -board_set_rimage_target(tgl) -endif() - -if(CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH) -board_set_rimage_target(tgl-h) -endif() - -board_finalize_runner_args(intel_adsp) diff --git a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig b/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig deleted file mode 100644 index 2787e3649f9d0e..00000000000000 --- a/boards/xtensa/intel_adsp_cavs25/intel_adsp_cavs25_tgph_defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_SOC_INTEL_CAVS_V25=y -CONFIG_BOARD_INTEL_ADSP_CAVS25_TGPH=y -CONFIG_SOC_SERIES_INTEL_ADSP_CAVS=y - - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n - -CONFIG_XTENSA_RESET_VECTOR=y - -CONFIG_XTENSA_USE_CORE_CRT1=y - -CONFIG_MULTI_LEVEL_INTERRUPTS=y -CONFIG_2ND_LEVEL_INTERRUPTS=y - -CONFIG_BUILD_OUTPUT_BIN=n - -CONFIG_DAI_SSP_HAS_POWER_CONTROL=y - -CONFIG_DCACHE_LINE_SIZE=64 diff --git a/boards/xtensa/intel_adsp_cavs25/pre_dt_board.cmake b/boards/xtensa/intel_adsp_cavs25/pre_dt_board.cmake deleted file mode 100644 index 7a471ca8758f02..00000000000000 --- a/boards/xtensa/intel_adsp_cavs25/pre_dt_board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Suppress "unique_unit_address_if_enabled" to handle the following overlaps: -# - dmic0: dmic0@10000 & dmic1: dmic1@10000 -list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/boards/xtensa/kincony_kc868_a32/Kconfig.board b/boards/xtensa/kincony_kc868_a32/Kconfig.board deleted file mode 100644 index 098f377092bcec..00000000000000 --- a/boards/xtensa/kincony_kc868_a32/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Bartosz Bilas -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_KINCONY_KC868_A32 - bool "KINCONY KC868-A32 Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROOM_32UE_N4 -endchoice diff --git a/boards/xtensa/kincony_kc868_a32/Kconfig.defconfig b/boards/xtensa/kincony_kc868_a32/Kconfig.defconfig deleted file mode 100644 index 85e02264b5a85a..00000000000000 --- a/boards/xtensa/kincony_kc868_a32/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Bartosz Bilas -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "kincony_kc868_a32" - depends on BOARD_KINCONY_KC868_A32 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_SIZE - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 diff --git a/boards/xtensa/kincony_kc868_a32/doc/index.rst b/boards/xtensa/kincony_kc868_a32/doc/index.rst deleted file mode 100644 index dfd4797701bdd6..00000000000000 --- a/boards/xtensa/kincony_kc868_a32/doc/index.rst +++ /dev/null @@ -1,97 +0,0 @@ -.. _kincony_kc868_a32: - -KINCONY KC868-A32 -################# - -Overview -******** - -Kincony KC868-A32 is a home automation relay module based on the -Espressif ESP-WROOM-32 module with all its inherent capabilities -(Wi-Fi, Bluetooth, etc.) - -The features include the following: - -- 32 digital optoisolated inputs “dry contact” -- 4 analog inputs 0-5 V -- 32 relays 220 V, 10 A (COM, NO, NC) -- RS485 interface -- I2C connector -- Connector GSM/HMI -- Ethernet LAN8270A -- USB Type-B connector for programming and filling firmware -- RESET and DOWNLOAD buttons -- Powered by 12V DC - -.. figure:: img/kincony_kc868_a32.jpg - :align: center - :alt: KINCONCY-KC868-A32 - - KINCONCY-KC868-A32 - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: kincony_kc868_a32 - :goals: build - -The usual ``flash`` target will work with the ``kincony_kc868_a32`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: kincony_kc868_a32 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! kincony_kc868_a32 - -Enabling Ethernet -***************** - -Enable Ethernet in KConfig: - -.. code-block:: cfg - - CONFIG_NETWORKING=y - CONFIG_NET_L2_ETHERNET=y - CONFIG_MDIO=y - -References -********** - -.. _KINCONY KC868-A32 User Guide: https://www.kincony.com/arduino-esp32-32-channel-relay-module-kc868-a32.html diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.dts b/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.dts deleted file mode 100644 index 2690ae75b24644..00000000000000 --- a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.dts +++ /dev/null @@ -1,214 +0,0 @@ -/* - * Copyright (c) 2023 Bartosz Bilas - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "kincony_kc868_a32-pinctrl.dtsi" - -/ { - model = "Kincony KC868-A32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 13 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - - i2c0_pcf8574@21 { - compatible = "nxp,pcf857x"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c0_pcf8574@22 { - compatible = "nxp,pcf857x"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c0_pcf8574@24 { - compatible = "nxp,pcf857x"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c0_pcf8574@25 { - compatible = "nxp,pcf857x"; - reg = <0x25>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 5 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; - - i2c1_pcf8574@21 { - compatible = "nxp,pcf857x"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c1_pcf8574@22 { - compatible = "nxp,pcf857x"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c1_pcf8574@24 { - compatible = "nxp,pcf857x"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; - - i2c1_pcf8574@25 { - compatible = "nxp,pcf857x"; - reg = <0x25>; - gpio-controller; - #gpio-cells = <2>; - ngpios = <8>; - }; -}; - -&mdio { - pinctrl-0 = <&mdio_default>; - pinctrl-names = "default"; - status = "okay"; - - phy: ethernet-phy@0 { - compatible = "ethernet-phy"; - status = "okay"; - reg = <0>; - }; -}; - -ð { - status = "okay"; - phy-handle = <&phy>; - ref-clk-output-gpios = <&gpio0 17 0>; -}; - -&psram0 { - status = "disabled"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.yaml b/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.yaml deleted file mode 100644 index 72577b2572a2e1..00000000000000 --- a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: kincony_kc868_a32 -name: KINCONY-KC868-A32 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - watchdog - - uart - - nvs - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: kincony diff --git a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32_defconfig b/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32_defconfig deleted file mode 100644 index 7bb4a23e7949b1..00000000000000 --- a/boards/xtensa/kincony_kc868_a32/kincony_kc868_a32_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) Bartosz Bilas -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_KINCONY_KC868_A32=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y -CONFIG_I2C=y diff --git a/boards/xtensa/m5stack_atoms3/Kconfig.board b/boards/xtensa/m5stack_atoms3/Kconfig.board deleted file mode 100644 index 726e31773e223f..00000000000000 --- a/boards/xtensa/m5stack_atoms3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack AtomS3 board configuration - -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STACK_ATOMS3 - bool "M5Stack AtomS3 Development Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/m5stack_atoms3/Kconfig.defconfig b/boards/xtensa/m5stack_atoms3/Kconfig.defconfig deleted file mode 100644 index 94f209758eb73a..00000000000000 --- a/boards/xtensa/m5stack_atoms3/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# M5Stack AtomS3 board configuration -# Copyright (c) 2023 Benjamin Cabé -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_ATOMS3 - -config BOARD - default "m5stack_atoms3" - depends on BOARD_M5STACK_ATOMS3 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -config LV_COLOR_16_SWAP - default y if LVGL - -endif # BOARD_M5STACK_ATOMS3 diff --git a/boards/xtensa/m5stack_atoms3/doc/index.rst b/boards/xtensa/m5stack_atoms3/doc/index.rst deleted file mode 100644 index 2dd229be436455..00000000000000 --- a/boards/xtensa/m5stack_atoms3/doc/index.rst +++ /dev/null @@ -1,136 +0,0 @@ -.. _m5stack_atoms3: - -M5Stack AtomS3 -############## - -Overview -******** - -M5Stack AtomS3 is an ESP32-based development board from M5Stack. - -It features the following integrated components: - -- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) -- 512KB of SRAM -- 384KB of ROM -- 8MB of Flash -- LCD IPS TFT 0.85", 128x128 px screen (ST7789 compatible) -- 6-axis IMU MPU6886 -- Infrared emitter - - -.. figure:: img/m5stack_atoms3.webp - :align: center - :alt: M5Stack AtomS3 - - M5Stack AtomS3 - - -Supported Features -================== - -The Zephyr m5stack_atoms3 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5Stack AtomS3, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: shell - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3 - :goals: build - -The usual ``flash`` target will work with the ``m5stack_atoms3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3 - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_atoms3 - -Debugging ---------- - -M5Stack AtomS3 debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5Stack AtomS3 schematic `_ -- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.dts b/boards/xtensa/m5stack_atoms3/m5stack_atoms3.dts deleted file mode 100644 index 72ebd81b42fe94..00000000000000 --- a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.dts +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2023 Benjamin Cabé - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_atoms3-pinctrl.dtsi" -#include "grove_connectors.dtsi" -#include - -/ { - model = "M5Stack AtomS3"; - compatible = "m5stack,atoms3"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &st7789v; - }; - - aliases { - sw0 = &user_button_0; - watchdog0 = &wdt0; - accel0 = &mpu6886; - }; - - gpio_keys { - compatible = "gpio-keys"; - - /* This is the button that's underneath the LCD display */ - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; // G42 - zephyr,code = ; - }; - }; - - /* Regulators */ - lcd_backlight_en { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_enable"; - enable-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; - - mpu6886: mpu6886@68 { - compatible = "invensense,mpu6050"; - reg = <0x68>; - status = "okay"; - }; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; - - st7789v: st7789v@0 { - compatible = "sitronix,st7789v"; - reg = <0>; - spi-max-frequency = <27000000>; - cmd-data-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; /* G33 */ - reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; /* G34 */ - - width = <128>; - height = <128>; - x-offset = <2>; - y-offset = <1>; - - vcom = <0x28>; - gctrl = <0x35>; - vrhs = <0x10>; - vdvs = <0x20>; - mdac = <0x00>; - gamma = <0x01>; - colmod = <0x55>; - lcm = <0x0c>; - porch-param = [0c 0c 00 33 33]; - cmd2en-param = [5a 69 02 00]; - pwctrl1-param = [a4 a1]; - pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17]; - nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e]; - ram-param = [00 E0]; - rgb-param = [40 02 14]; - }; - -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.yaml b/boards/xtensa/m5stack_atoms3/m5stack_atoms3.yaml deleted file mode 100644 index ed34b2f551d7d6..00000000000000 --- a/boards/xtensa/m5stack_atoms3/m5stack_atoms3.yaml +++ /dev/null @@ -1,21 +0,0 @@ -identifier: m5stack_atoms3 -name: M5Stack AtomS3 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - regulator - - uart - - pinmux - - nvs - - display -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_atoms3/m5stack_atoms3_defconfig b/boards/xtensa/m5stack_atoms3/m5stack_atoms3_defconfig deleted file mode 100644 index 1000271dbe584b..00000000000000 --- a/boards/xtensa/m5stack_atoms3/m5stack_atoms3_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_ATOMS3=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_GPIO=y -CONFIG_REGULATOR=y # for LCD backlight - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/m5stack_atoms3_lite/Kconfig.board b/boards/xtensa/m5stack_atoms3_lite/Kconfig.board deleted file mode 100644 index 2c77718895e0e5..00000000000000 --- a/boards/xtensa/m5stack_atoms3_lite/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack AtomS3 Lite board configuration -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -# M5Stack AtomS3 Lite -config BOARD_M5STACK_ATOMS3_LITE - bool "M5Stack AtomS3 Lite Development Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/m5stack_atoms3_lite/Kconfig.defconfig b/boards/xtensa/m5stack_atoms3_lite/Kconfig.defconfig deleted file mode 100644 index 8f982cec80b7e4..00000000000000 --- a/boards/xtensa/m5stack_atoms3_lite/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# M5Stack AtomS3 Lite board configuration -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_ATOMS3_LITE - -config BOARD - default "m5stack_atoms3_lite" - depends on BOARD_M5STACK_ATOMS3_LITE - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 98304 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice -endif # BOARD_M5STACK_ATOMS3_LITE diff --git a/boards/xtensa/m5stack_atoms3_lite/doc/index.rst b/boards/xtensa/m5stack_atoms3_lite/doc/index.rst deleted file mode 100644 index c51f580aa623bb..00000000000000 --- a/boards/xtensa/m5stack_atoms3_lite/doc/index.rst +++ /dev/null @@ -1,134 +0,0 @@ -.. _m5stack_atoms3_lite: - -M5Stack AtomS3 Lite -################### - -Overview -******** - -M5Stack AtomS3 Lite is an ESP32-based development board from M5Stack. - -It features the following integrated components: - -- ESP32-S3FN8 chip (240MHz dual core, Wi-Fi/BLE 5.0) -- 512KB of SRAM -- 384KB of ROM -- 8MB of Flash -- RGB Status-LED - - -.. figure:: img/m5stack_atoms3_lite.webp - :align: center - :alt: M5Stack AtomS3 Lite - - M5Stack AtomS3 Lite - - -Supported Features -================== - -The Zephyr m5stack_atoms3_lite board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5Stack AtomS3 Lite, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: shell - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3_lite - :goals: build - -The usual ``flash`` target will work with the ``m5stack_atoms3_lite`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_atoms3_lite - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_atoms3_lite - -Debugging ---------- - -M5Stack AtomS3 Lite debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5Stack AtomS3 Lite schematic `_ -- `ESP32S3 Datasheet `_ diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.dts b/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.dts deleted file mode 100644 index 51b65cfba0cfa1..00000000000000 --- a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.dts +++ /dev/null @@ -1,155 +0,0 @@ -/* - * Copyright (c) 2023 Benjamin Cabé - * Copyright (c) 2023 Martin Kiepfer - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_atoms3_lite-pinctrl.dtsi" -#include -#include -#include - -/ { - model = "M5Stack AtomS3 Lite"; - compatible = "m5stack,atoms3_lite"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - sw0 = &user_button_0; - watchdog0 = &wdt0; - i2c-0 = &i2c0; - led-strip = &status_rgb_led; - }; - - buttons { - compatible = "gpio-keys"; - debounce-interval-ms = <100>; - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - line-idle-low; - pinctrl-0 = <&spim3_ws2812_led>; - pinctrl-names = "default"; - - status_rgb_led: ws2812@0 { - compatible = "worldsemi,ws2812-spi"; - reg = <0>; - spi-max-frequency = ; - - chain-length = <1>; - color-mapping = , - , - ; - spi-one-frame = ; - spi-zero-frame = ; - }; -}; -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.yaml b/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.yaml deleted file mode 100644 index 82426e35fe68ad..00000000000000 --- a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite.yaml +++ /dev/null @@ -1,23 +0,0 @@ -identifier: m5stack_atoms3_lite -name: M5Stack AtomS3-Lite -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - counter - - watchdog - - entropy - - pwm - - pinmux - - nvs - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite_defconfig b/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite_defconfig deleted file mode 100644 index 18468290e06d99..00000000000000 --- a/boards/xtensa/m5stack_atoms3_lite/m5stack_atoms3_lite_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_ATOMS3_LITE=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/m5stack_core2/Kconfig.board b/boards/xtensa/m5stack_core2/Kconfig.board deleted file mode 100644 index 9b48a15c24d084..00000000000000 --- a/boards/xtensa/m5stack_core2/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack Core2 board configuration - -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STACK_CORE2 - bool "M5Stack Core2 Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_D0WD_V3 -endchoice diff --git a/boards/xtensa/m5stack_core2/Kconfig.defconfig b/boards/xtensa/m5stack_core2/Kconfig.defconfig deleted file mode 100644 index 15dfc61483abaf..00000000000000 --- a/boards/xtensa/m5stack_core2/Kconfig.defconfig +++ /dev/null @@ -1,53 +0,0 @@ -# M5Stack Core2 board configuration -# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_CORE2 - -config BOARD - default "m5stack_core2" - depends on BOARD_M5STACK_CORE2 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -config REGULATOR_AXP192_INIT_PRIORITY - default 81 - -config GPIO_HOGS_INIT_PRIORITY - default 82 - -config INPUT_FT5336_INTERRUPT - default y if INPUT - -config INPUT - default y - -config LV_COLOR_16_SWAP - default y if LVGL - -# Increase initialization priority of MIPI DBI device, so that it initializes -# after the GPIO controller -if MIPI_DBI - -config MIPI_DBI_INIT_PRIORITY - default 82 - -endif # MIPI_DBI - -endif # BOARD_M5STACK_CORE2 diff --git a/boards/xtensa/m5stack_core2/doc/index.rst b/boards/xtensa/m5stack_core2/doc/index.rst deleted file mode 100644 index 11fd9b9826e224..00000000000000 --- a/boards/xtensa/m5stack_core2/doc/index.rst +++ /dev/null @@ -1,197 +0,0 @@ -.. _m5stack_core2: - -M5Stack Core2 -############# - -Overview -******** - -M5Stack Core2 is an ESP32-based development board from M5Stack. It is the successor for the Core module. - -M5Stack Core2 features the following integrated components: - -- ESP32-D0WDQ6-V3 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) -- PSRAM 8MB -- Flash 16MB -- LCD IPS TFT 2", 320x240 px screen (ILI9342C) -- Touch screen (FT6336U) -- PMU AXP192 -- Audio NS4168 amplifier (1W-092 speaker) -- Vibration motor -- RTC BM8563 -- USB CP2104 -- SD-Card slot -- IMO 6-axis IMU MPU6886 -- MIC SPM1423 -- Battery 390mAh 3,7V - -.. figure:: img/m5stack_core2.webp - :align: center - :alt: M5Stack-Core2 - :width: 400 px - - M5Stack-Core2 module - -Functional Description -********************** - -The following table below describes the key components, interfaces, and controls -of the M5Stack Core2 board. - -.. _M5Core2 Schematic: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/schematic/Core/CORE2_V1.0_SCH.pdf -.. _MPU-ESP32: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32_datasheet_en_v3.9.pdf -.. _TOUCH-FT6336U: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/Ft6336GU_Firmware%20外部寄存器_20151112-%20EN.xlsx -.. _SND-NS4168: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/NS4168_CN_datasheet.pdf -.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf -.. _LCD-ILI9342C: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ILI9342C-ILITEK.pdf -.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf -.. _RTC-BM8563: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/BM8563_V1.1_cn.pdf -.. _SY7088: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SY7088-Silergy.pdf -.. _PMU-AXP192: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/AXP192_datasheet_en.pdf -.. _VIB-1072_RFN01: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/1027RFN01-33d.pdf - -+------------------+--------------------------------------------------------------------------+------------+ -| Key Component | Description | Status | -+==================+==========================================================================+============+ -|| ESP32-D0WDQ6-V2 || This `MPU-ESP32`_ module provides complete Wi-Fi and Bluetooth || supported | -|| module || functionalities and integrates a 16-MB SPI flash. || | -+------------------+--------------------------------------------------------------------------+------------+ -|| 32.768 kHz RTC || External precision 32.768 kHz crystal oscillator serves as a clock with || supported | -|| || low-power consumption while the chip is in Deep-sleep mode. || | -+------------------+--------------------------------------------------------------------------+------------+ -| Status LED | One user LED connected to the GPIO pin. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| USB Port || USB interface. Power supply for the board as well as the || supported | -|| || communication interface between a computer and the board. || | -|| || Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 || | -+------------------+--------------------------------------------------------------------------+------------+ -| Reset button | Reset button | supported | -+------------------+--------------------------------------------------------------------------+------------+ -| Power Switch | Power on/off button. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| LCD screen || Built-in LCD TFT display \(`LCD-ILI9342C`_, 2", 320x240 px\) || supported | -|| || controlled via SPI interface || | -+------------------+--------------------------------------------------------------------------+------------+ -| SD-Card slot | SD-Card connection via SPI-mode. | supported | -+------------------+--------------------------------------------------------------------------+------------+ -|| 6-axis IMU || The `MPU-6886`_ is a 6-axis motion tracker (6DOF IMU) device that || todo | -|| MPU6886 || combines a 3-axis gyroscope and a 3-axis accelerometer. || | -|| || For details please refer to :ref:`m5stack_core2_ext` || | -+------------------+--------------------------------------------------------------------------+------------+ -|| Built-in || The `SPM-1423`_ I2S driven microphone. || todo | -|| microphone || || | -+------------------+--------------------------------------------------------------------------+------------+ -| Built-in speaker | 1W speaker for audio output via I2S interface. | todo | -+------------------+--------------------------------------------------------------------------+------------+ - -Supported Features -================== - -The Zephyr m5stack_core2 board configuration supports the following hardware features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| NVIC | on-chip | nested vector interrupt controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | serial port-polling; | -| | | serial port-interrupt | -+-----------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| CLOCK | on-chip | reset and clock control | -+-----------+------------+-------------------------------------+ -| COUNTER | on-chip | rtc | -+-----------+------------+-------------------------------------+ -| WATCHDOG | on-chip | independent watchdog | -+-----------+------------+-------------------------------------+ -| PWM | on-chip | pwm | -+-----------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+-----------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+-----------+------------+-------------------------------------+ -| die-temp | on-chip | die temperature sensor | -+-----------+------------+-------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5Stack Core2, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_core2 - :goals: build - -The usual ``flash`` target will work with the ``m5stack_core2`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_core2 - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_core2 - -Debugging ---------- - -M5Stack Core2 debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5StickC PLUS schematic `_ (WEBP) -- `ESP32-PICO-D4 Datasheet `_ (PDF) -- `M5StickC PLUS docs `_ -- `ESP32 Datasheet `_ (PDF) -- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.dts b/boards/xtensa/m5stack_core2/m5stack_core2.dts deleted file mode 100644 index 17cbe3fe638b17..00000000000000 --- a/boards/xtensa/m5stack_core2/m5stack_core2.dts +++ /dev/null @@ -1,285 +0,0 @@ -/* - * Copyright (c) 2023 Martin Kiepfer - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_core2-pinctrl.dtsi" -#include "grove_connectors.dtsi" -#include "m5stack_mbus_connectors.dtsi" -#include -#include - -/ { - model = "M5Stack Core2"; - compatible = "m5stack,core2"; - - aliases { - pwr-led = &pwr_led; - uart-0 = &uart0; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - rtc = &pfc8563_rtc; - led0 = &led_pwr; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,display = &ili9342c; - zephyr,code-partition = &slot0_partition; - zephyr,rtc = &pfc8563_rtc; - }; - - leds { - compatible = "gpio-leds"; - led_pwr: led_pwr { - gpios = <&axp192_gpio 1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - label = "Power LED"; - }; - }; - - lvgl_pointer { - compatible = "zephyr,lvgl-pointer-input"; - input = <&ft5336_touch>; - swap-xy; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; - reset-gpios = <&axp192_gpio 4 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - spi-dev = <&spi3>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9342c: ili9342c@0 { - compatible = "ilitek,ili9342c"; - mipi-max-frequency = <30000000>; - reg = <0>; - vin-supply = <&lcd_bg>; - pixel-format = ; - display-inversion; - width = <320>; - height = <240>; - rotation = <0>; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&psram0 { - reg = <0x3f800000 DT_SIZE_M(8)>; - status = "disabled"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; - pinctrl-names = "default"; -}; - -&uart1 { - status = "disabled"; - current-speed = <115200>; - pinctrl-0 = <&uart1_rx_gpio33 &uart1_tx_gpio32>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - scl-timeout-us = <0>; - pinctrl-names = "default"; - - pfc8563_rtc: pfc8563@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - status = "okay"; - }; - - axp192_pmic: axp192@34 { - compatible = "x-powers,axp192"; - reg = <0x34>; - status = "okay"; - - axp192_regulator: axp192_regulator { - compatible = "x-powers,axp192-regulator"; - status = "okay"; - - vdd_mcu: DCDC1 { - regulator-init-microvolt = <3350000>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3400000>; - regulator-initial-mode = ; - regulator-boot-on; - regulator-always-on; - }; - - lcd_bg: DCDC3 { - regulator-init-microvolt = <2800000>; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - v_peri: LDO2 { - regulator-init-microvolt = <3300000>; - regulator-min-microvolt = <3200000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - vib_motor: LDO3 { - regulator-init-microvolt = <2800000>; - }; - }; - - axp192_gpio: axp192_gpio { - compatible = "x-powers,axp192-gpio"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <5>; - status = "okay"; - - pwr_led: axp192_gpio1 { - gpio-hog; - gpios = <1 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>; - output-high; - line-name = "pwr-led"; - }; - - bus_pwr_en: axp192_gpio0 { - gpio-hog; - gpios = <0 0>; - input; - }; - }; - }; - - ft5336_touch: ft5336@38 { - compatible = "focaltech,ft5336"; - reg = <0x38>; - int-gpios = <&gpio1 7 0>; - }; -}; - -&i2c1 { - status = "disabled"; - clock-frequency = ; - sda-gpios = <&gpio1 0 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio1 1 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - dma-enabled; - clock-frequency = <20000000>; - cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>, - <&gpio0 4 GPIO_ACTIVE_LOW>; - - sdhc0: sdhc@1 { - compatible = "zephyr,sdhc-spi-slot"; - reg = <1>; - status = "okay"; - spi-max-frequency = <20000000>; - mmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - - }; -}; - - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - reg = <0 DT_SIZE_M(16)>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - /* 14MB storage */ - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00db0000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_core2/m5stack_core2.yaml b/boards/xtensa/m5stack_core2/m5stack_core2.yaml deleted file mode 100644 index 78b361e8834205..00000000000000 --- a/boards/xtensa/m5stack_core2/m5stack_core2.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: m5stack_core2 -name: M5Stack Core2 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - regulator - - uart - - pinmux - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_core2/m5stack_core2_defconfig b/boards/xtensa/m5stack_core2/m5stack_core2_defconfig deleted file mode 100644 index 10fde73b47755c..00000000000000 --- a/boards/xtensa/m5stack_core2/m5stack_core2_defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_CORE2=y - -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0 - -CONFIG_GPIO=y - -CONFIG_REGULATOR=y - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -# for debugging -CONFIG_SHELL=y diff --git a/boards/xtensa/m5stack_stamps3/Kconfig.board b/boards/xtensa/m5stack_stamps3/Kconfig.board deleted file mode 100644 index 1f22500830e864..00000000000000 --- a/boards/xtensa/m5stack_stamps3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5Stack StampS3 board configuration - -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STACK_STAMPS3 - bool "M5Stack StampS3 Development Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_FN8 -endchoice diff --git a/boards/xtensa/m5stack_stamps3/Kconfig.defconfig b/boards/xtensa/m5stack_stamps3/Kconfig.defconfig deleted file mode 100644 index f451db3e231c35..00000000000000 --- a/boards/xtensa/m5stack_stamps3/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# M5Stack StampS3 board configuration -# Copyright (c) 2023 Martin Kiepfer -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_M5STACK_STAMPS3 - -config BOARD - default "m5stack_stamps3" - depends on BOARD_M5STACK_STAMPS3 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 98304 if WIFI - default 65536 if BT - default 4096 - -config KERNEL_MEM_POOL - default y - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_M5STACK_STAMPS3 diff --git a/boards/xtensa/m5stack_stamps3/doc/index.rst b/boards/xtensa/m5stack_stamps3/doc/index.rst deleted file mode 100644 index 75c660de8033e8..00000000000000 --- a/boards/xtensa/m5stack_stamps3/doc/index.rst +++ /dev/null @@ -1,199 +0,0 @@ -.. _m5stack_stamps3: - -M5Stack StampS3 -############### - -Overview -******** - -M5Stack StampS3 is an ESP32-based development board from M5Stack. -It features the following integrated components: - -- ESP32-S3FN8 chip (240MHz dual core) -- 512KB SRAM -- 384KB ROM -- 8MB Flash -- Wi-Fi -- Bluetooth -- User-Button - -.. figure:: img/m5stack_stamps3.webp - :align: center - :alt: M5Stack StampS3 - :width: 400 px - - M5Stack StampS3 module - -Functional Description -********************** - -The following table below describes the key components, interfaces, and controls -of the M5Stack StampS3 module. - -+---------------+-----------------------------------------------------------------+-----------+ -| Key Component | Description | Status | -+===============+=================================================================+===========+ -| ESP32-S3FN8 | This MPU-ESP32S3 module provides complete Wi-Fi and Bluetooth | supported | -| module | functionalities and integrates a 8MB flash. | | -+---------------+-----------------------------------------------------------------+-----------+ -| Status LED | One user LED connected via :dtcompatible:`worldsemi,ws2812-spi` | supported | -| | interface (``led-strip``). | | -+---------------+-----------------------------------------------------------------+-----------+ -| USB Port | USB interface. Power supply for the board as well as the | supported | -| | communication interface between a computer and the board. | | -+---------------+-----------------------------------------------------------------+-----------+ -| User button | User button (``sw0``) | supported | -+---------------+-----------------------------------------------------------------+-----------+ - -Main connector header -===================== - -The Zephyr m5stack_stamps3 board can be used on various applications. It -therefore publishes a header definition to be used in different shields: -:dtcompatible:`m5stack,stamps3-header`. - -.. figure:: img/m5stack_stamps3_header.webp - :align: center - :alt: M5Stack StampS3 Header - :width: 400 px - - M5Stack StampS3 connector header - -Following interfaces are being exported for this header: - -- ``m5stack_stamps3_clkout0``: PWM output with 2 channels (0 and 2). -- ``m5stack_stamps3_spilcd``: SPI interface for interfacing LCDs. Consists of a - CLK, MOSI and CS signal. -- ``m5stack_stamps3_i2c0`` and ``m5stack_stamps3_i2c1``: I2C interfaces (SDA, SCL). -- ``m5stack_stamps3_uart0``: UART interface (RXD, TXD). -- ``m5stack_stamps3_header``: All GPIOs are of course accessible via main header - definition. - -+-----+-----------------------------------------+-----+---------------------------------+ -| Pin | Functions | Pin | Functions | -+=====+=========================================+=====+=================================+ -| 1 | | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 2 | | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 3 | ``m5stack_stamps3_clkout0`` - Channel 0 | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 4 | | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 5 | ``m5stack_stamps3_spilcd`` - MOSI | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 6 | ``m5stack_stamps3_spilcd`` - CLK | | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 7 | ``m5stack_stamps3_spilcd`` - CS | 28 | **3V3** | -+-----+-----------------------------------------+-----+---------------------------------+ -| 8 | | 27 | ``m5stack_stamps3_uart0`` - TXD | -+-----+-----------------------------------------+-----+---------------------------------+ -| 9 | ``m5stack_stamps3_clkout0`` - Channel 2 | 26 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 10 | | 25 | ``m5stack_stamps3_uart0`` - RXD | -+-----+-----------------------------------------+-----+---------------------------------+ -| 11 | **GND** | 24 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 12 | ``m5stack_stamps3_i2c1`` - SDA | 23 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 13 | **5V** | 22 | **EN** | -+-----+-----------------------------------------+-----+---------------------------------+ -| 14 | ``m5stack_stamps3_i2c1`` - SCL | 21 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 15 | ``m5stack_stamps3_i2c0`` - SDA | 20 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 16 | | 19 | | -+-----+-----------------------------------------+-----+---------------------------------+ -| 17 | ``m5stack_stamps3_i2c0`` - SCL | 18 | **GND** | -+-----+-----------------------------------------+-----+---------------------------------+ - -Power supply -============ - -M5Stack StampS3 requires a single 5V input power supply. The module internally -features a DCDC (MUN3CAD01-SC) to generate the 3.3V needed for the MCU. - -The **EN** signal (Pin 22) is an active low signal to enable the **3V3** power -supply. If this pin is pulled low this main 3.3V power supply for the MCU will be -deactivated. It is internally equipped with a pull-up and can hence be left open -if unused. - -Start Application Development -***************************** - -Before powering up your M5Stack StampS3, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -------------------- - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_stamps3 - :goals: build - -The usual ``flash`` target will work with the ``m5stack_stamps3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stack_stamps3 - :goals: flash - -The baud rate of 921600bps is set by default. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stack_stamps3 - -Debugging ---------- - -M5Stack StampS3 exports a JTAG-interface via Pins 19 (MTCK), 21 (MTDO), 23 -(MTDI), 25 (MTMS). - -.. note:: - - Please note that additional JTAG equipment is needed to utilize JTAG. Refer to - the ESP32S3 datasheet and the M5Stack StampS3 documentation for details. - -Related Documents -***************** - -- `M5Stack StampS3 schematic `_ -- `M5Stack StampS3 `_ -- `ESP32 Datasheet `_ (PDF) -- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.dts b/boards/xtensa/m5stack_stamps3/m5stack_stamps3.dts deleted file mode 100644 index b4087e31bd9edd..00000000000000 --- a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.dts +++ /dev/null @@ -1,195 +0,0 @@ -/* - * Copyright (c) 2023 Martin Kiepfer - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stack_stamps3-pinctrl.dtsi" -#include "m5stack_stamps3_connectors.dtsi" -#include -#include -#include -#include - -/ { - model = "M5Stack StampS3"; - compatible = "m5stack,stamps3"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - sw0 = &user_button_0; - watchdog0 = &wdt0; - //pwm-0 = &ledc0; - i2c-0 = &i2c0; - led-strip = &status_rgb_led; - }; - - gpio_keys { - compatible = "gpio-keys"; - - /* This is the button that's underneath the LCD display */ - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&i2c1 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c1_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&mcpwm0 { - status = "okay"; - pinctrl-0 = <&mcpwm0_default>; - pinctrl-names = "default"; - prescale = <255>; - prescale-timer0 = <100>; - prescale-timer1 = <100>; -}; - -&ledc0 { - pinctrl-0 = <&ledc0_default>; - pinctrl-names = "default"; - status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; - channel0@0 { - reg = <0x0>; - timer = <0>; - }; - channel0@1 { - reg = <0x1>; - timer = <0>; - }; -}; - - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - line-idle-low; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - - status_rgb_led: ws2812@0 { - compatible = "worldsemi,ws2812-spi"; - reg = <0x0>; - spi-max-frequency = ; - - chain-length = <1>; - color-mapping = , - , - ; - spi-one-frame = ; - spi-zero-frame = ; - reset-delay = <250>; - }; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.yaml b/boards/xtensa/m5stack_stamps3/m5stack_stamps3.yaml deleted file mode 100644 index f5275cabe05ad8..00000000000000 --- a/boards/xtensa/m5stack_stamps3/m5stack_stamps3.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: m5stack_stamps3 -name: M5Stack StampS3 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - uart - - pwm - - pinmux - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stack_stamps3/m5stack_stamps3_defconfig b/boards/xtensa/m5stack_stamps3/m5stack_stamps3_defconfig deleted file mode 100644 index 34f489623bc874..00000000000000 --- a/boards/xtensa/m5stack_stamps3/m5stack_stamps3_defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STACK_STAMPS3=y -CONFIG_SOC_SERIES_ESP32S3=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_GPIO=y - -CONFIG_CONSOLE=y -CONFIG_PWM=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_CLOCK_CONTROL=y diff --git a/boards/xtensa/m5stickc_plus/Kconfig.board b/boards/xtensa/m5stickc_plus/Kconfig.board deleted file mode 100644 index 91e31bc959521c..00000000000000 --- a/boards/xtensa/m5stickc_plus/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# M5StickC PLUS board configuration - -# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_M5STICKC_PLUS - bool "M5StickC PLUS Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_PICO_D4 -endchoice diff --git a/boards/xtensa/m5stickc_plus/Kconfig.defconfig b/boards/xtensa/m5stickc_plus/Kconfig.defconfig deleted file mode 100644 index a9e73202781111..00000000000000 --- a/boards/xtensa/m5stickc_plus/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# M5StickC PLUS board configuration - -# Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "m5stickc_plus" - depends on BOARD_M5STICKC_PLUS - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/m5stickc_plus/doc/index.rst b/boards/xtensa/m5stickc_plus/doc/index.rst deleted file mode 100644 index 1b042f4f30f4dc..00000000000000 --- a/boards/xtensa/m5stickc_plus/doc/index.rst +++ /dev/null @@ -1,218 +0,0 @@ -.. _m5stickc_plus: - -M5StickC PLUS -############# - -Overview -******** - -M5StickC PLUS, one of the core devices in M5Stacks product series, is an ESP32-based development board. - -M5StickC PLUS features the following integrated components: - -- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi) -- ST7789v2, LCD TFT 1.14", 135x240 px screen -- IMU MPU-6886 -- SPM-1423 microphone -- RTC BM8563 -- PMU AXP192 -- 120 mAh 3,7 V battery - -Some of the ESP32 I/O pins are broken out to the board's pin headers for easy access. - -Functional Description -********************** - -The following table below describes the key components, interfaces, and controls -of the M5StickC PLUS board. - -.. _ST7789v2: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/ST7789V.pdf -.. _MPU-6886: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/MPU-6886-000193%2Bv1.1_GHIC_en.pdf -.. _ESP32-PICO-D4: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/esp32-pico-d4_datasheet_en.pdf -.. _SPM-1423: https://m5stack.oss-cn-shenzhen.aliyuncs.com/resource/docs/datasheet/core/SPM1423HM4H-B_datasheet_en.pdf - -+------------------+-------------------------------------------------------------------------+ -| Key Component | Description | -+==================+=========================================================================+ -| 32.768 kHz RTC | External precision 32.768 kHz crystal oscillator serves as a clock with | -| | low-power consumption while the chip is in Deep-sleep mode. | -+------------------+-------------------------------------------------------------------------+ -| ESP32-PICO-D4 | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth | -| module | functionalities and integrates a 4-MB SPI flash. | -+------------------+-------------------------------------------------------------------------+ -| Diagnostic LED | One user LED connected to the GPIO pin. | -+------------------+-------------------------------------------------------------------------+ -| USB Port | USB interface. Power supply for the board as well as the | -| | communication interface between a computer and the board. | -| | Contains: TypeC x 1, GROVE(I2C+I/O+UART) x 1 | -+------------------+-------------------------------------------------------------------------+ -| Power Switch | Power on/off button. | -+------------------+-------------------------------------------------------------------------+ -| A/B user buttons | Two push buttons intended for any user use. | -+------------------+-------------------------------------------------------------------------+ -| LCD screen | Built-in LCD TFT display \(`ST7789v2`_, 1.14", 135x240 px\) controlled | -| | by the SPI interface | -+------------------+-------------------------------------------------------------------------+ -| MPU-6886 | The `MPU-6886`_ is a 6-axis MotionTracking device that combines a | -| | 3-axis gyroscope and a 3-axis accelerometer. | -+------------------+-------------------------------------------------------------------------+ -| Built-in | The `SPM-1423`_ I2S driven microphone. | -| microphone | | -+------------------+-------------------------------------------------------------------------+ - - -Start Application Development -***************************** - -Before powering up your M5StickC PLUS, please make sure that the board is in good -condition with no obvious signs of damage. - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: m5stickc_plus - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stickc_plus - :goals: build - -The usual ``flash`` target will work with the ``m5stickc_plus`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: m5stickc_plus - :goals: flash - -The default baud rate for the M5StickC PLUS is set to 1500000bps. If experiencing issues when flashing, -try using different values by using ``--esp-baud-rate `` option during -``west flash`` (e.g. ``west flash --esp-baud-rate 115200``). - -You can also open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! m5stickc_plus - -Debugging -********* - -M5StickC PLUS debugging is not supported due to pinout limitations. - -Related Documents -***************** - -- `M5StickC PLUS schematic `_ (WEBP) -- `ESP32-PICO-D4 Datasheet `_ (PDF) -- `M5StickC PLUS docs `_ -- `ESP32 Datasheet `_ (PDF) -- `ESP32 Hardware Reference `_ diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus.dts b/boards/xtensa/m5stickc_plus/m5stickc_plus.dts deleted file mode 100644 index 6737973adae510..00000000000000 --- a/boards/xtensa/m5stickc_plus/m5stickc_plus.dts +++ /dev/null @@ -1,167 +0,0 @@ -/* - * Copyright (c) 2022 AVSystem Sławomir Wolf Sp.j. (AVSystem) - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "m5stickc_plus-pinctrl.dtsi" -#include - -/ { - model = "M5StickC Plus"; - compatible = "m5stack,m5stickc-plus"; - - aliases { - led0 = &red_led; - sw0 = &user_button_0; - sw1 = &user_button_1; - uart-0 = &uart0; - i2c-0 = &i2c0; - watchdog0 = &wdt0; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - leds { - compatible = "gpio-leds"; - - red_led: led_0 { - gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>; - label = "Red - LED0"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - - user_button_0: button_0 { - label = "User button 0"; - gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - user_button_1: button_1 { - label = "User button 1"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_tx_gpio1 &uart0_rx_gpio3>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -/* IMU MPU-6886, RTC BM8563, PMU AXP192 */ -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_sda_gpio21 &i2c0_scl_gpio22>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_miso_gpio12 &spim2_mosi_gpio11 - &spim2_sclk_gpio14 &spim2_csel_gpio16>; - pinctrl-names = "default"; -}; - -/* LCD TFT 1.14", 135x240 px, ST7789v2 */ -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_miso_gpio25 &spim3_mosi_gpio15 - &spim3_sclk_gpio13 &spim3_csel_gpio5>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus.yaml b/boards/xtensa/m5stickc_plus/m5stickc_plus.yaml deleted file mode 100644 index 821770c2be4410..00000000000000 --- a/boards/xtensa/m5stickc_plus/m5stickc_plus.yaml +++ /dev/null @@ -1,19 +0,0 @@ -identifier: m5stickc_plus -name: M5StickC PLUS -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - uart - - pinmux - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: m5stack diff --git a/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig b/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig deleted file mode 100644 index cc30c956bafd17..00000000000000 --- a/boards/xtensa/m5stickc_plus/m5stickc_plus_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_M5STICKC_PLUS=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y -CONFIG_I2C=y diff --git a/boards/xtensa/nxp_adsp_imx8/Kconfig.board b/boards/xtensa/nxp_adsp_imx8/Kconfig.board deleted file mode 100644 index 4bb4f56404043f..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8 - bool "NXP ADSP i.MX8" - depends on SOC_SERIES_NXP_IMX8 - select SOC_PART_NUMBER_MIMX8QM6AVUFF diff --git a/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig deleted file mode 100644 index 04aa0aa6ed30e5..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8 - -config BOARD - default "nxp_adsp_imx8" - -endif # BOARD_NXP_ADSP_IMX8 diff --git a/boards/xtensa/nxp_adsp_imx8/board.cmake b/boards/xtensa/nxp_adsp_imx8/board.cmake deleted file mode 100644 index 7ae22465082ced..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8) diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts deleted file mode 100644 index a17690109eca59..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nxp_adsp_imx8-pinctrl.dtsi" - -/ { - model = "nxp_adsp_imx8"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - }; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&lpuart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml deleted file mode 100644 index b2ab9b227a9dc9..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: nxp_adsp_imx8 -name: i.MX8 DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel - - sof -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig b/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig deleted file mode 100644 index a16d8be5e2e36e..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8/nxp_adsp_imx8_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=3072 - -# board/soc-related configurations -CONFIG_SOC_SERIES_NXP_IMX8=y -CONFIG_SOC_MIMX8QM_ADSP=y -CONFIG_BOARD_NXP_ADSP_IMX8=y - -CONFIG_LOG=y - -# TODO: maybe move this to SOF? -CONFIG_DYNAMIC_INTERRUPTS=y -CONFIG_BUILD_OUTPUT_BIN=n - -# clock-related configurations -CONFIG_CLOCK_CONTROL=y - -# serial-related configurations -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/nxp_adsp_imx8m/Kconfig.board b/boards/xtensa/nxp_adsp_imx8m/Kconfig.board deleted file mode 100644 index b84a08cc12feb5..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8m/Kconfig.board +++ /dev/null @@ -1,10 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8M - bool "NXP i.MX8M Plus EVK Audio DSP" - depends on SOC_SERIES_NXP_IMX8M - select SOC_PART_NUMBER_MIMX8ML8DVNLZ - select SOC_PART_NUMBER_MIMX8ML8CVNKZ diff --git a/boards/xtensa/nxp_adsp_imx8m/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8m/Kconfig.defconfig deleted file mode 100644 index 344449dd74436b..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8m/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2021, 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8M - -config BOARD - default "nxp_adsp_imx8m" - -endif # BOARD_NXP_ADSP_IMX8M diff --git a/boards/xtensa/nxp_adsp_imx8m/board.cmake b/boards/xtensa/nxp_adsp_imx8m/board.cmake deleted file mode 100644 index 4fb52dc2d292fb..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8m/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8m) diff --git a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.dts b/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.dts deleted file mode 100644 index 6a0d7508deb2a7..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.dts +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2021, 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include - -/ { - model = "nxp_adsp_imx8m"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - - zephyr,console = &uart4; - zephyr,shell-uart = &uart4; - }; -}; - -&pinctrl { - uart4_default: uart4_default { - group0 { - pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>, - <&iomuxc_uart4_txd_uart_tx_uart4_tx>; - bias-pull-up; - slew-rate = "slow"; - drive-strength = "x1"; - }; - }; -}; - -&uart4 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart4_default>; - pinctrl-names = "default"; -}; diff --git a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.yaml b/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.yaml deleted file mode 100644 index ef0bbdfe0ff04f..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m.yaml +++ /dev/null @@ -1,16 +0,0 @@ -identifier: nxp_adsp_imx8m -name: NXP i.MX8M Plus EVK Audio DSP -type: mcu -arch: xtensa -toolchain: - - xcc - - xt-clang - - zephyr -supported: - - uart -testing: - ignore_tags: - - net - - bluetooth - - mcumgr -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig b/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig deleted file mode 100644 index 72ccd09f55a47c..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8m/nxp_adsp_imx8m_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NXP_IMX8M=y -CONFIG_SOC_MIMX8M_ADSP=y -CONFIG_BOARD_NXP_ADSP_IMX8M=y - -# size of stack for initialization and main thread -CONFIG_MAIN_STACK_SIZE=3072 - -# enable logger -CONFIG_LOG=y - -# no need for a "raw" binary zephyr/zephyr.bin in the build directory -CONFIG_BUILD_OUTPUT_BIN=n - -# enable uart driver -CONFIG_SERIAL=y - -# clock configuration -CONFIG_CLOCK_CONTROL=y - -# console (remote proc console by default) -CONFIG_CONSOLE=y - -# uart console (overrides remote proc console) -CONFIG_UART_CONSOLE=y - -# enable pin controller -CONFIG_PINCTRL=y diff --git a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board b/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board deleted file mode 100644 index d9a1ff65953286..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.board +++ /dev/null @@ -1,7 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8ULP - bool "NXP ADSP i.MX8ULP" diff --git a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig deleted file mode 100644 index 431515d5961428..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8ULP - -config BOARD - default "nxp_adsp_imx8ulp" - -endif # BOARD_NXP_ADSP_IMX8ULP diff --git a/boards/xtensa/nxp_adsp_imx8ulp/board.cmake b/boards/xtensa/nxp_adsp_imx8ulp/board.cmake deleted file mode 100644 index e05fbc891e5202..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8ulp) diff --git a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts b/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts deleted file mode 100644 index d584097cb0306e..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.dts +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include - -/ { - model = "nxp_adsp_imx8ulp"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - }; -}; diff --git a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml b/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml deleted file mode 100644 index e71105631da6f9..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp.yaml +++ /dev/null @@ -1,10 +0,0 @@ -identifier: nxp_adsp_imx8ulp -name: i.MX8ULP DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel - - sof diff --git a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp_defconfig b/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp_defconfig deleted file mode 100644 index cc1911c615cfce..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8ulp/nxp_adsp_imx8ulp_defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_SOC_SERIES_NXP_IMX8ULP=y -CONFIG_SOC_NXP_IMX8ULP=y -CONFIG_BOARD_NXP_ADSP_IMX8ULP=y - -CONFIG_BUILD_OUTPUT_BIN=n - -CONFIG_DYNAMIC_INTERRUPTS=y - -CONFIG_LOG=y diff --git a/boards/xtensa/nxp_adsp_imx8x/Kconfig.board b/boards/xtensa/nxp_adsp_imx8x/Kconfig.board deleted file mode 100644 index 7d5336ce7a790c..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8x/Kconfig.board +++ /dev/null @@ -1,9 +0,0 @@ -# Xtensa board configuration - -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_IMX8X - bool "NXP ADSP i.MX8X" - depends on SOC_SERIES_NXP_IMX8 - select SOC_PART_NUMBER_MIMX8QX6AVLFZ diff --git a/boards/xtensa/nxp_adsp_imx8x/Kconfig.defconfig b/boards/xtensa/nxp_adsp_imx8x/Kconfig.defconfig deleted file mode 100644 index a985696286afb9..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8x/Kconfig.defconfig +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_IMX8X - -config BOARD - default "nxp_adsp_imx8x" - -endif # BOARD_NXP_ADSP_IMX8X diff --git a/boards/xtensa/nxp_adsp_imx8x/board.cmake b/boards/xtensa/nxp_adsp_imx8x/board.cmake deleted file mode 100644 index 7ae22465082ced..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8x/board.cmake +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -board_set_flasher_ifnset(misc-flasher) -board_finalize_runner_args(misc-flasher) - -board_set_rimage_target(imx8) diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts b/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts deleted file mode 100644 index 5aa0e59ebdd078..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.dts +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2021 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "nxp_adsp_imx8x-pinctrl.dtsi" - -/ { - model = "nxp_adsp_imx8x"; - compatible = "nxp"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &lpuart2; - zephyr,shell-uart = &lpuart2; - }; -}; - -&lpuart2 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&lpuart2_default>; - pinctrl-names = "default"; -}; diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.yaml b/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.yaml deleted file mode 100644 index a343b8843c8dcc..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x.yaml +++ /dev/null @@ -1,11 +0,0 @@ -identifier: nxp_adsp_imx8x -name: i.MX8X DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel - - sof -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig b/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig deleted file mode 100644 index 0635e78adf88f6..00000000000000 --- a/boards/xtensa/nxp_adsp_imx8x/nxp_adsp_imx8x_defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=3072 - -# board/soc-related configurations -CONFIG_SOC_SERIES_NXP_IMX8=y -CONFIG_SOC_MIMX8QXP_ADSP=y -CONFIG_BOARD_NXP_ADSP_IMX8X=y - -CONFIG_LOG=y - -# TODO: maybe move this to SOF? -CONFIG_DYNAMIC_INTERRUPTS=y -CONFIG_BUILD_OUTPUT_BIN=n - -# clock-related configurations -CONFIG_CLOCK_CONTROL=y - -# serial-related configurations -CONFIG_SERIAL=y -CONFIG_CONSOLE=y -CONFIG_UART_CONSOLE=y diff --git a/boards/xtensa/nxp_adsp_rt595/Kconfig b/boards/xtensa/nxp_adsp_rt595/Kconfig deleted file mode 100644 index 3c787188a9b017..00000000000000 --- a/boards/xtensa/nxp_adsp_rt595/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset) -DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data) -DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text) - -if BOARD_NXP_ADSP_RT595 - -config RT595_ADSP_STACK_SIZE - hex "Boot time stack size" - default 0x1000 - help - Stack space is reserved at the end of the RT595_ADSP_DATA_MEM - region, starting at RT595_ADSP_DATA_MEM_ADDR - RT595_ADSP_STACK_SIZE - -config RT595_ADSP_RESET_MEM_ADDR - hex - default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM)) - -config RT595_ADSP_RESET_MEM_SIZE - hex - default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM)) - -config RT595_ADSP_DATA_MEM_ADDR - hex - default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM)) - -config RT595_ADSP_DATA_MEM_SIZE - hex - default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM)) - -config RT595_ADSP_TEXT_MEM_ADDR - hex - default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM)) - -config RT595_ADSP_TEXT_MEM_SIZE - hex - default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM)) - -endif # BOARD_NXP_ADSP_RT595 diff --git a/boards/xtensa/nxp_adsp_rt595/Kconfig.board b/boards/xtensa/nxp_adsp_rt595/Kconfig.board deleted file mode 100644 index a88eb58638fe61..00000000000000 --- a/boards/xtensa/nxp_adsp_rt595/Kconfig.board +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_NXP_ADSP_RT595 - bool "NXP ADSP RT595" - depends on SOC_SERIES_NXP_RT5XX diff --git a/boards/xtensa/nxp_adsp_rt595/Kconfig.defconfig b/boards/xtensa/nxp_adsp_rt595/Kconfig.defconfig deleted file mode 100644 index 7ffe782d28b288..00000000000000 --- a/boards/xtensa/nxp_adsp_rt595/Kconfig.defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_NXP_ADSP_RT595 - -config BOARD - default "nxp_adsp_rt595" - -endif # BOARD_NXP_ADSP_RT595 diff --git a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.yaml b/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.yaml deleted file mode 100644 index 09f61405d94bab..00000000000000 --- a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595.yaml +++ /dev/null @@ -1,10 +0,0 @@ -identifier: nxp_adsp_rt595 -name: i.MXRT595 DSP -type: mcu -arch: xtensa -toolchain: - - zephyr -testing: - only_tags: - - kernel -vendor: nxp diff --git a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595_defconfig b/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595_defconfig deleted file mode 100644 index 0e80f8a41a66ec..00000000000000 --- a/boards/xtensa/nxp_adsp_rt595/nxp_adsp_rt595_defconfig +++ /dev/null @@ -1,7 +0,0 @@ -CONFIG_SOC_SERIES_NXP_RT5XX=y -CONFIG_SOC_NXP_RT595=y -CONFIG_BOARD_NXP_ADSP_RT595=y - -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_XTENSA_SMALL_VECTOR_TABLE_ENTRY=y diff --git a/boards/xtensa/odroid_go/Kconfig.board b/boards/xtensa/odroid_go/Kconfig.board deleted file mode 100644 index f815a4e7e8823d..00000000000000 --- a/boards/xtensa/odroid_go/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# ODROID-GO Game Kit configuration - -# Copyright (c) 2019 Yannis Damigos -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_ODROID_GO - bool "ODROID-GO Game Kit" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N16R2 -endchoice diff --git a/boards/xtensa/odroid_go/Kconfig.defconfig b/boards/xtensa/odroid_go/Kconfig.defconfig deleted file mode 100644 index 1827d83a0411b7..00000000000000 --- a/boards/xtensa/odroid_go/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# ODROID-GO Game Kit configuration - -# Copyright (c) 2019 Yannis Damigos -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "odroid_go" - depends on BOARD_ODROID_GO - -config DISK_DRIVER_SDMMC - default y if DISK_ACCESS - -config SPI - default y if DISK_DRIVER_SDMMC - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/odroid_go/doc/index.rst b/boards/xtensa/odroid_go/doc/index.rst deleted file mode 100644 index 933c167f535972..00000000000000 --- a/boards/xtensa/odroid_go/doc/index.rst +++ /dev/null @@ -1,245 +0,0 @@ -.. _odroid_go: - -ODROID-GO -######### - -Overview -******** - -ODROID-GO Game Kit is a "Do it yourself" ("DIY") portable game console by -HardKernel. It features a custom ESP32-WROVER with 16 MB flash and it operates -from 80 MHz - 240 MHz [1]_. - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 80 - 240MHz -- 4 MB of PSRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- 2.4 inch 320x240 TFT LCD -- Speaker -- Micro SD card slot -- Micro USB port (battery charging and USB_UART data communication -- Input Buttons (Menu, Volume, Select, Start, A, B, Direction Pad) -- Expansion port (I2C, GPIO, SPI) -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) - -.. figure:: img/odroid_go.jpg - :align: center - :alt: ODROID-GO - - ODROID-Go Game Kit - -External Connector -================== - -+-------+------------------+-------------------------+ -| PIN # | Signal Name | ESP32-WROVER Functions | -+=======+==================+=========================+ -| 1 | GND | GND | -+-------+------------------+-------------------------+ -| 2 | VSPI.SCK (IO18) | GPIO18, VSPICLK | -+-------+------------------+-------------------------+ -| 3 | IO12 | GPIO12 | -+-------+------------------+-------------------------+ -| 4 | IO15 | GPIO15, ADC2_CH3 | -+-------+------------------+-------------------------+ -| 5 | IO4 | GPIO4, ADC2_CH0 | -+-------+------------------+-------------------------+ -| 6 | P3V3 | 3.3 V | -+-------+------------------+-------------------------+ -| 7 | VSPI.MISO (IO19) | GPIO19, VSPIQ | -+-------+------------------+-------------------------+ -| 8 | VSPI.MOSI (IO23) | GPIO23, VSPID | -+-------+------------------+-------------------------+ -| 9 | N.C | N/A | -+-------+------------------+-------------------------+ -| 10 | VBUS | USB VBUS (5V) | -+-------+------------------+-------------------------+ - -Supported Features -================== - -The Zephyr odroid_go board configuration supports the following hardware -features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| I2C | on-chip | i2c | -+------------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+------------+------------+-------------------------------------+ - - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: odroid_go - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: build - -The usual ``flash`` target will work with the ``odroid_go`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! odroid_go - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: odroid_go - :goals: debug - -References -********** - -.. target-notes:: - -.. [1] https://wiki.odroid.com/odroid_go/odroid_go -.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/odroid_go/odroid_go.dts b/boards/xtensa/odroid_go/odroid_go.dts deleted file mode 100644 index 31ceee79d3cf6e..00000000000000 --- a/boards/xtensa/odroid_go/odroid_go.dts +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2019 Yannis Damigos - * - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include "odroid_go-pinctrl.dtsi" -#include - -/ { - model = "ODROID-GO Game Kit"; - compatible = "hardkernel,odroid_go", "espressif,esp32"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - zephyr,display = &ili9341; - }; - - leds { - compatible = "gpio-leds"; - blue_led: led { - gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; - label = "Status Led"; - }; - }; - - gpio_keys { - compatible = "gpio-keys"; - menu_button: menu_button { - label = "Menu"; - gpios = <&gpio0 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - volume_button: volume_button { - label = "Volume"; - gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - select_button: select_button { - label = "Select"; - gpios = <&gpio0 27 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - a_button: a_button { - label = "A"; - gpios = <&gpio1 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - b_button: b_button { - label = "B"; - gpios = <&gpio1 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - zephyr,code = ; - }; - start_button: start_button { - label = "Start"; - gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; - zephyr,code = ; - }; - }; - - lcd_backlight_en { - compatible = "regulator-fixed"; - regulator-name = "lcd_backlight_enable"; - enable-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - regulator-boot-on; - }; - - aliases { - uart-0 = &uart0; - led0 = &blue_led; - sw0 = &menu_button; - watchdog0 = &wdt0; - }; - - mipi_dbi { - compatible = "zephyr,mipi-dbi-spi"; - dc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; - spi-dev = <&spi3>; - write-only; - #address-cells = <1>; - #size-cells = <0>; - - ili9341: ili9341@0 { - compatible = "ilitek,ili9341"; - mipi-max-frequency = <25000000>; - pixel-format = <0>; - reg = <0>; - rotation = <270>; - width = <320>; - height = <240>; - }; - }; -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; - - blue-led-disable { - gpio-hog; - gpios = <2 GPIO_ACTIVE_HIGH>; - output-low; - }; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 4 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 15 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; - - sdhc0: sdhc@1 { - compatible = "zephyr,sdhc-spi-slot"; - reg = <1>; - status = "okay"; - mmc { - compatible = "zephyr,sdmmc-disk"; - status = "okay"; - }; - spi-max-frequency = <20000000>; - }; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&timer2 { - status = "okay"; -}; - -&timer3 { - status = "okay"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/odroid_go/odroid_go.yaml b/boards/xtensa/odroid_go/odroid_go.yaml deleted file mode 100644 index 8a487018654804..00000000000000 --- a/boards/xtensa/odroid_go/odroid_go.yaml +++ /dev/null @@ -1,18 +0,0 @@ -identifier: odroid_go -name: ODROID-GO -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - i2c - - spi - - watchdog - - uart - - nvs -testing: - ignore_tags: - - net - - bluetooth -vendor: hardkernel diff --git a/boards/xtensa/odroid_go/odroid_go_defconfig b/boards/xtensa/odroid_go/odroid_go_defconfig deleted file mode 100644 index 3bda04a1ed3a71..00000000000000 --- a/boards/xtensa/odroid_go/odroid_go_defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_ODROID_GO=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y - -# required to enable LCD backlight -CONFIG_REGULATOR=y diff --git a/boards/xtensa/olimex_esp32_evb/Kconfig.board b/boards/xtensa/olimex_esp32_evb/Kconfig.board deleted file mode 100644 index 7bb6c2295b7983..00000000000000 --- a/boards/xtensa/olimex_esp32_evb/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# Olimex ESP32-EVB board configuration - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_OLIMEX_ESP32_EVB - bool "Olimex ESP32-EVB" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROVER_E_N8R2 -endchoice diff --git a/boards/xtensa/olimex_esp32_evb/Kconfig.defconfig b/boards/xtensa/olimex_esp32_evb/Kconfig.defconfig deleted file mode 100644 index 6aca00ecad505f..00000000000000 --- a/boards/xtensa/olimex_esp32_evb/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Olimex ESP32-EVB board configuration - -# Copyright (c) 2022 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_OLIMEX_ESP32_EVB - -config BOARD - default "olimex_esp32_evb" - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice - -endif # BOARD_OLIMEX_ESP32_EVB diff --git a/boards/xtensa/olimex_esp32_evb/doc/index.rst b/boards/xtensa/olimex_esp32_evb/doc/index.rst deleted file mode 100644 index 3bc02a82295677..00000000000000 --- a/boards/xtensa/olimex_esp32_evb/doc/index.rst +++ /dev/null @@ -1,265 +0,0 @@ -.. _olimex_esp32_evb: - -Olimex ESP32-EVB -################ - -Overview -******** - -The Olimex ESP32-EVB is an OSHW certified, open-source IoT board based on the -Espressif ESP32-WROOM-32E/UE module. It has a wired 100Mbit/s Ethernet Interface, -Bluetooth LE, WiFi, infrared remote control, and CAN connectivity. Two relays -allows switching power appliances on and off. - -The board can operate from a single LiPo backup battery as it has an internal -LiPo battery charger. There is no step-up converter, so relays, CAN, and USB -power does not work when running off battery. - -.. figure:: ESP32-EVB.jpg - :align: center - :alt: ESP32-EVB - - ESP32-EVB (Credit: Olimex) - -Hardware -******** - -- ESP32-WROOM-32E/UE module with 4MB flash. -- On-board programmer, CH340T USB-to-UART -- WiFi, Bluetooth LE connectivity. -- 100Mbit/s Ethernet interface, Microchip LAN8710A PHY. -- MicroSD card slot. -- 2 x 10A/250VAC (15A/120VAC 15A/24VDC) relays with connectors and status LEDs. -- CAN interface, Microchip MCP2562-E high-speed CAN transceiver. -- IR receiver and transmitter, up to 5 meters distance. -- BL4054B LiPo battery charger with status LEDs for stand-alone operation during - power outages. -- Power jack for external 5VDC power supply. -- Univeral EXTension (UEXT) connector for connecting UEXT modules. -- User push button. -- 40 pin GPIO connector with all ESP32 pins. - -For more information about the ESP32-EVB and the ESP32-WROOM-32E/UE module, see -these reference documents: - -- `ESP32-EVB Website`_ -- `ESP32-EVB Schematic`_ -- `ESP32-EVB GitHub Repository`_ -- `ESP32-WROOM32-E/UE Datasheet`_ - -Supported Features -****************** - -The olimex_esp32_evb board configuration supports the following hardware -features: - -+-----------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+===========+============+=====================================+ -| EFUSE | on-chip | hwinfo, device ID | -+-----------+------------+-------------------------------------+ -| FLASH | module | External flash | -+-----------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+-----------+------------+-------------------------------------+ -| I2C | on-chip | I2C | -+-----------+------------+-------------------------------------+ -| INTERRUPT | on-chip | interrupt controller | -+-----------+------------+-------------------------------------+ -| IO_MUX | on-chip | pinctrl | -+-----------+------------+-------------------------------------+ -| SPI | on-chip | spi | -+-----------+------------+-------------------------------------+ -| TIMG | on-chip | counter | -+-----------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+-----------+------------+-------------------------------------+ -| TWAI | on-chip | CAN controller | -+-----------+------------+-------------------------------------+ -| UART | on-chip | uart | -+-----------+------------+-------------------------------------+ -| WDT | on-chip | watchdog | -+-----------+------------+-------------------------------------+ -| WiFi | on-chip | WiFi | -+-----------+------------+-------------------------------------+ - -The default configuration can be found in the defconfig file: -``boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig``. - -Other hardware features are not currently supported by the port. - -System requirements -******************* - -Prerequisites -============= - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: olimex_esp32_evb - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: build - -The usual ``flash`` target will work with the ``olimex_esp32_evb`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! olimex_esp32_evb - -Debugging -********* - -As with much custom hardware, the ESP32 modules require patches to -OpenOCD that are not upstreamed yet. Espressif maintains their own fork of -the project. The custom OpenOCD can be obtained at `OpenOCD ESP32`_ - -The Zephyr SDK uses a bundled version of OpenOCD by default. You can overwrite that behavior by adding the -``-DOPENOCD= -DOPENOCD_DEFAULT_PATH=`` -parameter when building. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: build flash - :gen-args: -DOPENOCD= -DOPENOCD_DEFAULT_PATH= - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: olimex_esp32_evb - :goals: debug - -References -********** - -.. _ESP32-EVB Website: - https://www.olimex.com/Products/IoT/ESP32/ESP32-EVB/open-source-hardware - -.. _ESP32-EVB Schematic: - https://github.com/OLIMEX/ESP32-EVB/raw/master/HARDWARE/REV-I/ESP32-EVB_Rev_I.pdf - -.. _ESP32-EVB GitHub Repository: - https://github.com/OLIMEX/ESP32-EVB - -.. _ESP32-WROOM32-E/UE Datasheet: - https://www.espressif.com/sites/default/files/documentation/esp32-wroom-32e_esp32-wroom-32ue_datasheet_en.pdf - -.. _OpenOCD ESP32: - https://github.com/espressif/openocd-esp32/releases diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.yaml b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.yaml deleted file mode 100644 index 83320db1529f2c..00000000000000 --- a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb.yaml +++ /dev/null @@ -1,20 +0,0 @@ -identifier: olimex_esp32_evb -name: Olimex ESP32-EVB -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - can - - counter - - gpio - - hwinfo - - i2c - - spi - - uart - - watchdog -testing: - ignore_tags: - - net - - bluetooth -vendor: olimex diff --git a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig b/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig deleted file mode 100644 index a89b387d08441e..00000000000000 --- a/boards/xtensa/olimex_esp32_evb/olimex_esp32_evb_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_OLIMEX_ESP32_EVB=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/boards/xtensa/qemu_xtensa/Kconfig b/boards/xtensa/qemu_xtensa/Kconfig deleted file mode 100644 index 2ecdedbd716de3..00000000000000 --- a/boards/xtensa/qemu_xtensa/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Xtensa Qemu board configuration - -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 diff --git a/boards/xtensa/qemu_xtensa/Kconfig.board b/boards/xtensa/qemu_xtensa/Kconfig.board deleted file mode 100644 index 34cdf44a15c46b..00000000000000 --- a/boards/xtensa/qemu_xtensa/Kconfig.board +++ /dev/null @@ -1,17 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2017, 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_QEMU_XTENSA - bool "Xtensa emulation using QEMU" - depends on SOC_XTENSA_DC233C - select QEMU_TARGET - select ARCH_SUPPORTS_COREDUMP - -config BOARD_QEMU_XTENSA_MMU - bool "Xtensa emulation using QEMU with MMU" - depends on SOC_XTENSA_DC233C - select QEMU_TARGET - select ARCH_SUPPORTS_COREDUMP - select XTENSA_MMU diff --git a/boards/xtensa/qemu_xtensa/Kconfig.defconfig b/boards/xtensa/qemu_xtensa/Kconfig.defconfig deleted file mode 100644 index a6beed9151c540..00000000000000 --- a/boards/xtensa/qemu_xtensa/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2017, 2023 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if BOARD_QEMU_XTENSA - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_xtensa" - -config IPM_CONSOLE_STACK_SIZE - default 2048 if IPM_CONSOLE_RECEIVER - -endif # BOARD_QEMU_XTENSA - -if BOARD_QEMU_XTENSA_MMU - -config BUILD_OUTPUT_BIN - default n - -config BOARD - default "qemu_xtensa_mmu" - -config IPM_CONSOLE_STACK_SIZE - default 2048 if IPM_CONSOLE_RECEIVER - -endif # BOARD_QEMU_XTENSA diff --git a/boards/xtensa/qemu_xtensa/board.cmake b/boards/xtensa/qemu_xtensa/board.cmake deleted file mode 100644 index 56a6c358be47ca..00000000000000 --- a/boards/xtensa/qemu_xtensa/board.cmake +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SUPPORTED_EMU_PLATFORMS qemu) - -if(CONFIG_BOARD_QEMU_XTENSA OR CONFIG_BOARD_QEMU_XTENSA_MMU) - set(QEMU_CPU_TYPE_${ARCH} dc233c) - - set(QEMU_FLAGS_${ARCH} - -machine sim -semihosting -nographic -cpu dc233c - ) -endif() - -# TODO: Support debug -# board_set_debugger_ifnset(qemu) -# debugserver: QEMU_EXTRA_FLAGS += -s -S -# debugserver: qemu diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.yaml b/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.yaml deleted file mode 100644 index aa2ef7692d45cb..00000000000000 --- a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu.yaml +++ /dev/null @@ -1,13 +0,0 @@ -identifier: qemu_xtensa_mmu -name: QEMU Emulation for Xtensa with MMU -type: qemu -simulation: qemu -arch: xtensa -toolchain: - - zephyr - - xtools -testing: - default: true - ignore_tags: - - net - - bluetooth diff --git a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu_defconfig b/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu_defconfig deleted file mode 100644 index 6587737bd88535..00000000000000 --- a/boards/xtensa/qemu_xtensa/qemu_xtensa_mmu_defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_BOARD_QEMU_XTENSA_MMU=y -CONFIG_CONSOLE=y -CONFIG_SOC_XTENSA_DC233C=y -CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=10000000 -CONFIG_STACK_SENTINEL=y -CONFIG_GEN_ISR_TABLES=y -CONFIG_GEN_IRQ_VECTOR_TABLE=n -CONFIG_SIMULATOR_XTENSA=y -CONFIG_QEMU_ICOUNT_SHIFT=6 diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.board b/boards/xtensa/xiao_esp32s3/Kconfig.board deleted file mode 100644 index 99669d929e3f3a..00000000000000 --- a/boards/xtensa/xiao_esp32s3/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# XIAO ESP32S3 board configuration - -# Copyright (c) 2023 Seeed Studio inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XIAO_ESP32S3 - bool "XIAO ESP32S3 Board" - depends on SOC_SERIES_ESP32S3 - -choice SOC_PART_NUMBER - default SOC_ESP32S3_WROOM_N8R8 -endchoice diff --git a/boards/xtensa/xiao_esp32s3/Kconfig.defconfig b/boards/xtensa/xiao_esp32s3/Kconfig.defconfig deleted file mode 100644 index 3bc3e999189ca2..00000000000000 --- a/boards/xtensa/xiao_esp32s3/Kconfig.defconfig +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Seeed Studio inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "xiao_esp32s3" - depends on BOARD_XIAO_ESP32S3 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/xiao_esp32s3/doc/index.rst b/boards/xtensa/xiao_esp32s3/doc/index.rst deleted file mode 100644 index 62a5eb69ebaf15..00000000000000 --- a/boards/xtensa/xiao_esp32s3/doc/index.rst +++ /dev/null @@ -1,243 +0,0 @@ -.. _xiao_esp32s3: - -XIAO ESP32S3 -############ - -Overview -******** - -Seeed Studio XIAO ESP32S3 is an IoT mini development board based on the -Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip. - -For more details see the `Seeed Studio XIAO ESP32S3`_ wiki page. - -.. figure:: img/xiao_esp32s3.jpg - :align: center - :alt: XIAO ESP32S3 - - XIAO ESP32S3 - -Hardware -******** - -This board is based on the ESP32-S3 with 8MB of flash, WiFi and BLE support. It -has an USB-C port for programming and debugging, integrated battery charging -and an U.FL external antenna connector. It is based on a standard XIAO 14 pin -pinout. - -ESP32-S3 is a low-power MCU-based system on a chip (SoC) with integrated 2.4 GHz Wi-Fi -and Bluetooth® Low Energy (Bluetooth LE). It consists of high-performance dual-core microprocessor -(Xtensa® 32-bit LX7), a low power coprocessor, a Wi-Fi baseband, a Bluetooth LE baseband, -RF module, and numerous peripherals. - -Supported Features -================== - -Current Zephyr's XIAO ESP32S3 board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI/CAN | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| GDMA | on-chip | dma | -+------------+------------+-------------------------------------+ - -Connections and IOs -=================== - -The board uses a standard XIAO pinout, the default pin mapping is the following: - -.. figure:: img/xiao_esp32s3_pinout.jpg - :align: center - :alt: XIAO ESP32S3 Pinout - - XIAO ESP32S3 Pinout - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: xiao_esp32s3 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: build - -The usual ``flash`` target will work with the ``xiao_esp32s3`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! xiao_esp32s3 - -Debugging -********* - -ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -ESP32-S3 has a built-in JTAG circuitry and can be debugged without any additional chip. Only an USB cable connected to the D+/D- pins is necessary. - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32-S3`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: xiao_esp32s3 - :goals: debug -.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/ -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. target-notes:: - -.. _`Seeed Studio XIAO ESP32S3`: https://wiki.seeedstudio.com/xiao_esp32s3_getting_started/ diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts deleted file mode 100644 index a4592b26bce2a9..00000000000000 --- a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.dts +++ /dev/null @@ -1,138 +0,0 @@ -/* - * Copyright (c) 2023 Seeed Studio inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; - -#include -#include "xiao_esp32s3-pinctrl.dtsi" -#include "seeed_xiao_connector.dtsi" - -/ { - model = "Seeed XIAO ESP32S3"; - compatible = "seeed,xiao-esp32s3"; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &usb_serial; - zephyr,shell-uart = &usb_serial; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; - - aliases { - i2c-0 = &i2c0; - watchdog0 = &wdt0; - led0 = &led0; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; - label = "BUILTIN LED"; - }; - }; - -}; - -&cpu0 { - clock-frequency = ; -}; - -&cpu1 { - clock-frequency = ; -}; - -&usb_serial { - status = "okay"; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&trng0 { - status = "okay"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&wdt0 { - status = "okay"; -}; - -&twai { - pinctrl-0 = <&twai_default>; - pinctrl-names = "default"; - bus-speed = <125000>; -}; - -&timer0 { - status = "okay"; -}; - -&timer1 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot_partition: partition@0 { - label = "mcuboot"; - reg = <0x00000000 0x0000F000>; - read-only; - }; - - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml b/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml deleted file mode 100644 index 59ddcaec1e1f96..00000000000000 --- a/boards/xtensa/xiao_esp32s3/xiao_esp32s3.yaml +++ /dev/null @@ -1,22 +0,0 @@ -identifier: xiao_esp32s3 -name: XIAO ESP32S3 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - gpio - - uart - - i2c - - spi - - can - - counter - - watchdog - - entropy - - pwm - - dma -testing: - ignore_tags: - - net - - bluetooth -vendor: seeed diff --git a/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig b/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig deleted file mode 100644 index 978da251a5897b..00000000000000 --- a/boards/xtensa/xiao_esp32s3/xiao_esp32s3_defconfig +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_XIAO_ESP32S3=y -CONFIG_SOC_SERIES_ESP32S3=y -CONFIG_MAIN_STACK_SIZE=2048 -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y -CONFIG_GPIO=y diff --git a/boards/xtensa/xt-sim/Kconfig.board b/boards/xtensa/xt-sim/Kconfig.board deleted file mode 100644 index d67c68417a92a8..00000000000000 --- a/boards/xtensa/xt-sim/Kconfig.board +++ /dev/null @@ -1,8 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_XT_SIM - bool "Xtensa Development ISS" - depends on SIMULATOR_XTENSA diff --git a/boards/xtensa/xt-sim/Kconfig.defconfig b/boards/xtensa/xt-sim/Kconfig.defconfig deleted file mode 100644 index ab2d5e9f13bf33..00000000000000 --- a/boards/xtensa/xt-sim/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "xt-sim" - -config IPM_CONSOLE_STACK_SIZE - default 2048 if IPM_CONSOLE_RECEIVER diff --git a/boards/xtensa/yd_esp32/Kconfig.board b/boards/xtensa/yd_esp32/Kconfig.board deleted file mode 100644 index 843b2b38627c7e..00000000000000 --- a/boards/xtensa/yd_esp32/Kconfig.board +++ /dev/null @@ -1,12 +0,0 @@ -# YD-ESP32 board configuration - -# Copyright (c) 2023 Julio Cesar -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_YD_ESP32 - bool "YD-ESP32 Development Board" - depends on SOC_SERIES_ESP32 - -choice SOC_PART_NUMBER - default SOC_ESP32_WROOM_32UE_N4 -endchoice diff --git a/boards/xtensa/yd_esp32/Kconfig.defconfig b/boards/xtensa/yd_esp32/Kconfig.defconfig deleted file mode 100644 index 4807671ca7917f..00000000000000 --- a/boards/xtensa/yd_esp32/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# YD-ESP32 board configuration - -# Copyright (c) 2023 Julio Cesar -# SPDX-License-Identifier: Apache-2.0 - -config BOARD - default "yd_esp32" - depends on BOARD_YD_ESP32 - -config ENTROPY_GENERATOR - default y - -config HEAP_MEM_POOL_ADD_SIZE_BOARD - int - default 65535 if WIFI && BT - default 51200 if WIFI - default 40960 if BT - default 4096 - -choice BT_HCI_BUS_TYPE - default BT_ESP32 if BT -endchoice diff --git a/boards/xtensa/yd_esp32/doc/index.rst b/boards/xtensa/yd_esp32/doc/index.rst deleted file mode 100644 index c49bdc0cb60835..00000000000000 --- a/boards/xtensa/yd_esp32/doc/index.rst +++ /dev/null @@ -1,310 +0,0 @@ -.. _yd_esp32: - -YD-ESP32 -######## - -Overview -******** - -The YD-ESP32 development board is one of VCC-GND® Studio’s official boards. -This board is based on the ESP32-WROOM-32E module, with the ESP32 as the core. - -.. figure:: img/yd_esp32.png - :align: center - :alt: YD-ESP32 - - YD-ESP32 DevKit with ESP32-WROOM-32E Module - -ESP32 -===== - -ESP32 is a series of low cost, low power system on a chip microcontrollers -with integrated Wi-Fi & dual-mode Bluetooth. The ESP32 series employs a -Tensilica Xtensa LX6 microprocessor in both dual-core and single-core -variations. ESP32 is created and developed by Espressif Systems, a -Shanghai-based Chinese company, and is manufactured by TSMC using their 40nm -process. [1]_ - -The features include the following: - -- Dual core Xtensa microprocessor (LX6), running at 160 or 240MHz -- 520KB of SRAM -- 802.11b/g/n/e/i -- Bluetooth v4.2 BR/EDR and BLE -- Various peripherals: - - - 12-bit ADC with up to 18 channels - - 2x 8-bit DACs - - 10x touch sensors - - Temperature sensor - - 4x SPI - - 2x I2S - - 2x I2C - - 3x UART - - SD/SDIO/MMC host - - Slave (SDIO/SPI) - - Ethernet MAC - - CAN bus 2.0 - - IR (RX/TX) - - Motor PWM - - LED PWM with up to 16 channels - - Hall effect sensor - -- Cryptographic hardware acceleration (RNG, ECC, RSA, SHA-2, AES) -- 5uA deep sleep current - -Supported Features -================== - -Current Zephyr's YD-ESP32 board supports the following features: - -+------------+------------+-------------------------------------+ -| Interface | Controller | Driver/Component | -+============+============+=====================================+ -+------------+------------+-------------------------------------+ -| UART | on-chip | serial port | -+------------+------------+-------------------------------------+ -| GPIO | on-chip | gpio | -+------------+------------+-------------------------------------+ -| PINMUX | on-chip | pinmux | -+------------+------------+-------------------------------------+ -| USB-JTAG | on-chip | hardware interface | -+------------+------------+-------------------------------------+ -| SPI Master | on-chip | spi | -+------------+------------+-------------------------------------+ -| Timers | on-chip | counter | -+------------+------------+-------------------------------------+ -| Watchdog | on-chip | watchdog | -+------------+------------+-------------------------------------+ -| TRNG | on-chip | entropy | -+------------+------------+-------------------------------------+ -| LEDC | on-chip | pwm | -+------------+------------+-------------------------------------+ -| MCPWM | on-chip | pwm | -+------------+------------+-------------------------------------+ -| PCNT | on-chip | qdec | -+------------+------------+-------------------------------------+ -| SPI DMA | on-chip | spi | -+------------+------------+-------------------------------------+ -| TWAI | on-chip | can | -+------------+------------+-------------------------------------+ -| ADC | on-chip | adc | -+------------+------------+-------------------------------------+ -| DAC | on-chip | dac | -+------------+------------+-------------------------------------+ -| Wi-Fi | on-chip | | -+------------+------------+-------------------------------------+ -| Bluetooth | on-chip | | -+------------+------------+-------------------------------------+ - -System requirements -=================== - -Prerequisites -------------- - -Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command -below to retrieve those files. - -.. code-block:: console - - west blobs fetch hal_espressif - -.. note:: - - It is recommended running the command above after :file:`west update`. - -Building & Flashing -******************* - -ESP-IDF bootloader -================== - -The board is using the ESP-IDF bootloader as the default 2nd stage bootloader. -It is build as a subproject at each application build. No further attention -is expected from the user. - -MCUboot bootloader -================== - -User may choose to use MCUboot bootloader instead. In that case the bootloader -must be build (and flash) at least once. - -There are two options to be used when building an application: - -1. Sysbuild -2. Manual build - -.. note:: - - User can select the MCUboot bootloader by adding the following line - to the board default configuration file. - ``` - CONFIG_BOOTLOADER_MCUBOOT=y - ``` - -Sysbuild -======== - -The sysbuild makes possible to build and flash all necessary images needed to -bootstrap the board with the ESP32 SoC. - -To build the sample application using sysbuild use the command: - -.. zephyr-app-commands:: - :tool: west - :app: samples/hello_world - :board: yd_esp32 - :goals: build - :west-args: --sysbuild - :compact: - -By default, the ESP32 sysbuild creates bootloader (MCUboot) and application -images. But it can be configured to create other kind of images. - -Build directory structure created by sysbuild is different from traditional -Zephyr build. Output is structured by the domain subdirectories: - -.. code-block:: - - build/ - ├── hello_world - │   └── zephyr - │   ├── zephyr.elf - │   └── zephyr.bin - ├── mcuboot - │ └── zephyr - │ ├── zephyr.elf - │ └── zephyr.bin - └── domains.yaml - -.. note:: - - With ``--sysbuild`` option the bootloader will be re-build and re-flash - every time the pristine build is used. - -For more information about the system build please read the :ref:`sysbuild` documentation. - -Manual build -============ - -During the development cycle, it is intended to build & flash as quickly possible. -For that reason, images can be build one at a time using traditional build. - -The instructions following are relevant for both manual build and sysbuild. -The only difference is the structure of the build directory. - -.. note:: - - Remember that bootloader (MCUboot) needs to be flash at least once. - -Build and flash applications as usual (see :ref:`build_an_application` and -:ref:`application_run` for more details). - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: build - -The usual ``flash`` target will work with the ``yd_esp32`` board -configuration. Here is an example for the :ref:`hello_world` -application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: flash - -Open the serial monitor using the following command: - -.. code-block:: shell - - west espressif monitor - -After the board has automatically reset and booted, you should see the following -message in the monitor: - -.. code-block:: console - - ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx ***** - Hello World! yd_esp32 - -RGB LED -======= - -The board contains an addressable RGB LED (`XL-5050RGBC-WS2812B`_), driven by GPIO16. -Here is an example of how to test it using the :zephyr:code-sample:`led-ws2812` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/drivers/led_ws2812 - :board: yd_esp32 - :goals: flash - - -.. _`XL-5050RGBC-WS2812B`: http://www.xinglight.cn/index.php?c=show&id=947 - -Debugging -********* - -ESP32 support on OpenOCD is available upstream as of version 0.12.0. -Download and install OpenOCD from `OpenOCD`_. - -On the YD-ESP32 board, the JTAG pins are not run to a -standard connector (e.g. ARM 20-pin) and need to be manually connected -to the external programmer (e.g. a Flyswatter2): - -+------------+-----------+ -| ESP32 pin | JTAG pin | -+============+===========+ -| 3V3 | VTRef | -+------------+-----------+ -| EN | nTRST | -+------------+-----------+ -| IO14 | TMS | -+------------+-----------+ -| IO12 | TDI | -+------------+-----------+ -| GND | GND | -+------------+-----------+ -| IO13 | TCK | -+------------+-----------+ -| IO15 | TDO | -+------------+-----------+ - -Further documentation can be obtained from the SoC vendor in `JTAG debugging -for ESP32`_. - -Here is an example for building the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: build flash - -You can debug an application in the usual way. Here is an example for the :ref:`hello_world` application. - -.. zephyr-app-commands:: - :zephyr-app: samples/hello_world - :board: yd_esp32 - :goals: debug - -Note on Debugging with GDB Stub -=============================== - -GDB stub is enabled on ESP32. - -* When adding breakpoints, please use hardware breakpoints with command - ``hbreak``. Command ``break`` uses software breakpoints which requires - modifying memory content to insert break/trap instructions. - This does not work as the code is on flash which cannot be randomly - accessed for modification. - -.. _`JTAG debugging for ESP32`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/api-guides/jtag-debugging/index.html -.. _`OpenOCD`: https://github.com/openocd-org/openocd - -References -********** - -.. [1] https://en.wikipedia.org/wiki/ESP32 -.. _ESP32 Technical Reference Manual: https://espressif.com/sites/default/files/documentation/esp32_technical_reference_manual_en.pdf -.. _Hardware Reference: https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html diff --git a/boards/xtensa/yd_esp32/yd_esp32.dts b/boards/xtensa/yd_esp32/yd_esp32.dts deleted file mode 100644 index 9442e5009e45cf..00000000000000 --- a/boards/xtensa/yd_esp32/yd_esp32.dts +++ /dev/null @@ -1,184 +0,0 @@ -/* - * SPDX-License-Identifier: Apache-2.0 - */ -/dts-v1/; - -#include -#include -#include "yd_esp32-pinctrl.dtsi" -#include - -/ { - model = "VCC-GND Studio YD-ESP32"; - compatible = "espressif,esp32"; - - aliases { - uart-0 = &uart0; - i2c-0 = &i2c0; - sw0 = &button0; - watchdog0 = &wdt0; - led-strip = &rgb_led; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "BOOT Button"; - zephyr,code = ; - }; - }; - - chosen { - zephyr,sram = &sram0; - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,flash = &flash0; - zephyr,code-partition = &slot0_partition; - }; -}; - -&pinctrl { - spim2_default: spim2_default { - group2 { - pinmux = ; - output-low; - }; - }; -}; - -&cpu0 { - clock-frequency = ; - cpu-power-states = <&light_sleep &deep_sleep>; -}; - -&cpu1 { - clock-frequency = ; -}; - -&uart0 { - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-names = "default"; -}; - -&uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-names = "default"; -}; - -&uart2 { - current-speed = <115200>; - pinctrl-0 = <&uart2_default>; - pinctrl-names = "default"; -}; - -&gpio0 { - status = "okay"; -}; - -&gpio1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = ; - sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>; - scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>; - pinctrl-0 = <&i2c0_default>; - pinctrl-names = "default"; -}; - -&spi2 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim2_default>; - pinctrl-names = "default"; - - rgb_led: ws2812@0 { - compatible = "worldsemi,ws2812-spi"; - - /* SPI */ - reg = <0>; /* ignored, but necessary for SPI bindings */ - spi-max-frequency = <6400000>; - - /* XL-5050RGBC-WS2812B */ - chain-length = <1>; - spi-one-frame = <0xfc>; /* 11111100: 0.937 us high and 0.313 us low */ - spi-zero-frame = <0xc0>; /* 11000000: 0.313 us high and 0.937 us low */ - color-mapping = ; - }; -}; - -&spi3 { - #address-cells = <1>; - #size-cells = <0>; - status = "okay"; - pinctrl-0 = <&spim3_default>; - pinctrl-names = "default"; -}; - -&timer0 { - status = "disabled"; -}; - -&timer1 { - status = "disabled"; -}; - -&timer2 { - status = "disabled"; -}; - -&timer3 { - status = "disabled"; -}; - -&trng0 { - status = "okay"; -}; - -&flash0 { - status = "okay"; - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - /* Reserve 60kB for the bootloader */ - boot_partition: partition@1000 { - label = "mcuboot"; - reg = <0x00001000 0x0000F000>; - read-only; - }; - - /* Reserve 1024kB for the application in slot 0 */ - slot0_partition: partition@10000 { - label = "image-0"; - reg = <0x00010000 0x00100000>; - }; - - /* Reserve 1024kB for the application in slot 1 */ - slot1_partition: partition@110000 { - label = "image-1"; - reg = <0x00110000 0x00100000>; - }; - - /* Reserve 256kB for the scratch partition */ - scratch_partition: partition@210000 { - label = "image-scratch"; - reg = <0x00210000 0x00040000>; - }; - - storage_partition: partition@250000 { - label = "storage"; - reg = <0x00250000 0x00006000>; - }; - }; -}; diff --git a/boards/xtensa/yd_esp32/yd_esp32.yaml b/boards/xtensa/yd_esp32/yd_esp32.yaml deleted file mode 100644 index 2a73436066b835..00000000000000 --- a/boards/xtensa/yd_esp32/yd_esp32.yaml +++ /dev/null @@ -1,24 +0,0 @@ -identifier: yd_esp32 -name: YD-ESP32 -type: mcu -arch: xtensa -toolchain: - - zephyr -supported: - - adc - - dac - - gpio - - i2c - - watchdog - - uart - - nvs - - pwm - - dac - - spi - - counter - - entropy -testing: - ignore_tags: - - net - - bluetooth -vendor: espressif diff --git a/boards/xtensa/yd_esp32/yd_esp32_defconfig b/boards/xtensa/yd_esp32/yd_esp32_defconfig deleted file mode 100644 index c90b1c17d15705..00000000000000 --- a/boards/xtensa/yd_esp32/yd_esp32_defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Julio Cesar -# SPDX-License-Identifier: Apache-2.0 - -CONFIG_BOARD_YD_ESP32=y -CONFIG_SOC_SERIES_ESP32=y - -CONFIG_MAIN_STACK_SIZE=2048 - -CONFIG_CONSOLE=y -CONFIG_SERIAL=y -CONFIG_UART_CONSOLE=y - -CONFIG_GPIO=y diff --git a/cmake/compiler/gcc/target_arc.cmake b/cmake/compiler/gcc/target_arc.cmake index cf3d090991782c..e18fa468f1600c 100644 --- a/cmake/compiler/gcc/target_arc.cmake +++ b/cmake/compiler/gcc/target_arc.cmake @@ -1,7 +1,7 @@ # SPDX-License-Identifier: Apache-2.0 -if(EXISTS ${SOC_DIR}/${ARCH}/${SOC_PATH}/tune_build_ops.cmake) - include(${SOC_DIR}/${ARCH}/${SOC_PATH}/tune_build_ops.cmake) +if(EXISTS ${SOC_FULL_DIR}/tune_build_ops.cmake) + include(${SOC_FULL_DIR}/tune_build_ops.cmake) endif() if(NOT DEFINED GCC_ARC_TUNED_CPU) diff --git a/cmake/modules/FindDeprecated.cmake b/cmake/modules/FindDeprecated.cmake index 875f243b0344cf..bad0ab6ffe74a1 100644 --- a/cmake/modules/FindDeprecated.cmake +++ b/cmake/modules/FindDeprecated.cmake @@ -112,7 +112,7 @@ if("SEARCHED_LINKER_SCRIPT" IN_LIST Deprecated_FIND_COMPONENTS) set(LINKER_SCRIPT ${BOARD_DIR}/linker.ld) if(NOT EXISTS ${LINKER_SCRIPT}) # If not available, try an SoC specific linker file - set(LINKER_SCRIPT ${SOC_DIR}/${ARCH}/${SOC_PATH}/linker.ld) + set(LINKER_SCRIPT ${SOC_FULL_DIR}/linker.ld) endif() message(DEPRECATION "Pre-defined `linker.ld` script is deprecated. Please set " diff --git a/cmake/modules/FindHostTools.cmake b/cmake/modules/FindHostTools.cmake index b2d5257642daa5..8d3c9eccaaf373 100644 --- a/cmake/modules/FindHostTools.cmake +++ b/cmake/modules/FindHostTools.cmake @@ -65,8 +65,9 @@ find_program(BOSSAC bossac) # in the mcuboot repository if that's present in some cases) find_program(IMGTOOL imgtool) -# Pick host system's toolchain if we are targeting posix -if("${ARCH}" STREQUAL "posix" OR "${ARCH}" STREQUAL "unit_testing") +# Default to the host system's toolchain if we are targeting a host based target +if((${BOARD_DIR} MATCHES "boards\/native") OR ("${ARCH}" STREQUAL "posix") + OR ("${BOARD}" STREQUAL "unit_testing")) if(NOT "${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "llvm") set(ZEPHYR_TOOLCHAIN_VARIANT "host") endif() diff --git a/cmake/modules/arch.cmake b/cmake/modules/arch.cmake deleted file mode 100644 index 806b5c12b58c62..00000000000000 --- a/cmake/modules/arch.cmake +++ /dev/null @@ -1,48 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2022, Nordic Semiconductor ASA - -# Configure ARCH settings based on board directory and arch root. -# -# This CMake module will set the following variables in the build system based -# on board directory and arch root. -# -# If no implementation is available for the current arch an error will be raised. -# -# Outcome: -# The following variables will be defined when this CMake module completes: -# -# - ARCH: Name of the arch in use. -# - ARCH_DIR: Directory containing the arch implementation. -# - ARCH_ROOT: ARCH_ROOT with ZEPHYR_BASE appended -# -# Variable dependencies: -# - ARCH_ROOT: CMake list of arch roots containing arch implementations -# - BOARD_DIR: CMake variable specifying the directory of the selected BOARD -# -# Variables set by this module and not mentioned above are considered internal -# use only and may be removed, renamed, or re-purposed without prior notice. - -include_guard(GLOBAL) - -# 'ARCH_ROOT' is a prioritized list of directories where archs may be -# found. It always includes ${ZEPHYR_BASE} at the lowest priority (except for unittesting). -if(NOT unittest IN_LIST Zephyr_FIND_COMPONENTS) - list(APPEND ARCH_ROOT ${ZEPHYR_BASE}) -endif() - -cmake_path(GET BOARD_DIR PARENT_PATH board_arch_dir) -cmake_path(GET board_arch_dir FILENAME ARCH) - -foreach(root ${ARCH_ROOT}) - if(EXISTS ${root}/arch/${ARCH}/CMakeLists.txt) - set(ARCH_DIR ${root}/arch) - break() - endif() -endforeach() - -if(NOT ARCH_DIR) - message(FATAL_ERROR "Could not find ARCH=${ARCH} for BOARD=${BOARD}, \ -please check your installation. ARCH roots searched: \n\ -${ARCH_ROOT}") -endif() diff --git a/cmake/modules/arch_v1.cmake b/cmake/modules/arch_v1.cmake new file mode 100644 index 00000000000000..613182f0723f90 --- /dev/null +++ b/cmake/modules/arch_v1.cmake @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2022, Nordic Semiconductor ASA + +# +# This CMake module is only valid for hw model v1. +# In hw model v1, then arch is determined by the board folder structure. +# +# Configure ARCH settings based on board directory and arch root. +# +# This CMake module will set the following variables in the build system based +# on board directory and arch root. +# +# If no implementation is available for the current arch an error will be raised. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - ARCH: Name of the arch in use. +# - ARCH_DIR: Directory containing the arch implementation. +# - ARCH_ROOT: ARCH_ROOT with ZEPHYR_BASE appended +# +# Variable dependencies: +# - ARCH_ROOT: CMake list of arch roots containing arch implementations +# - BOARD_DIR: CMake variable specifying the directory of the selected BOARD +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +if(HWMv1) + # 'ARCH_ROOT' is a prioritized list of directories where archs may be + # found. It always includes ${ZEPHYR_BASE} at the lowest priority (except for unittesting). + if(NOT unittest IN_LIST Zephyr_FIND_COMPONENTS) + list(APPEND ARCH_ROOT ${ZEPHYR_BASE}) + endif() + + cmake_path(GET BOARD_DIR PARENT_PATH board_arch_dir) + cmake_path(GET board_arch_dir FILENAME ARCH) + + foreach(root ${ARCH_ROOT}) + if(EXISTS ${root}/arch/${ARCH}/CMakeLists.txt) + set(ARCH_DIR ${root}/arch) + break() + endif() + endforeach() + + if(NOT ARCH_DIR) + message(FATAL_ERROR "Could not find ARCH=${ARCH} for BOARD=${BOARD}, \ +please check your installation. ARCH roots searched: \n\ +${ARCH_ROOT}") + endif() +endif() diff --git a/cmake/modules/arch_v2.cmake b/cmake/modules/arch_v2.cmake new file mode 100644 index 00000000000000..8ad0372474511f --- /dev/null +++ b/cmake/modules/arch_v2.cmake @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +# +# Configure ARCH settings based on KConfig settings and arch root. +# +# This CMake module will set the following variables in the build system based +# on board directory and arch root. +# +# If no implementation is available for the current arch an error will be raised. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - ARCH: Name of the arch in use. +# - ARCH_DIR: Directory containing the arch implementation. +# - ARCH_ROOT: ARCH_ROOT with ZEPHYR_BASE appended +# +# Variable dependencies: +# - ARCH_ROOT: CMake list of arch roots containing arch implementations +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +if(HWMv2) + # HWMv2 obtains arch from Kconfig for the given Board / SoC variant because + # the Board / SoC path is no longer sufficient for determine the arch + # (read: multi-core and multi-arch SoC). + set(ARCH ${CONFIG_ARCH}) + string(TOUPPER "${ARCH}" arch_upper) + + if(NOT ARCH) + message(FATAL_ERROR "ARCH not defined. Check that BOARD=${BOARD}, is selecting " + "an appropriate SoC in Kconfig, SoC=${CONFIG_SOC}, and that the SoC " + "is selecting the correct architecture." + ) + endif() + + cmake_path(GET ARCH_V2_${arch_upper}_DIR PARENT_PATH ARCH_DIR) + if(NOT ARCH_DIR) + message(FATAL_ERROR "Could not find ARCH=${ARCH} for BOARD=${BOARD}, \ +please check your installation. ARCH roots searched: \n\ +${ARCH_ROOT}") + endif() +endif() diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake index 77f61c32f7b51b..1cc649326ff254 100644 --- a/cmake/modules/boards.cmake +++ b/cmake/modules/boards.cmake @@ -61,27 +61,66 @@ if(NOT unittest IN_LIST Zephyr_FIND_COMPONENTS) list(APPEND BOARD_ROOT ${ZEPHYR_BASE}) endif() -string(FIND "${BOARD}" "@" REVISION_SEPARATOR_INDEX) -if(NOT (REVISION_SEPARATOR_INDEX EQUAL -1)) - math(EXPR BOARD_REVISION_INDEX "${REVISION_SEPARATOR_INDEX} + 1") - string(SUBSTRING ${BOARD} ${BOARD_REVISION_INDEX} -1 BOARD_REVISION) - string(SUBSTRING ${BOARD} 0 ${REVISION_SEPARATOR_INDEX} BOARD) -endif() +# Helper function for parsing a board's name, revision, and identifier, +# from one input variable to three separate output variables. +function(parse_board_components board_in name_out revision_out identifier_out) + if(NOT "${${board_in}}" MATCHES "^([^@/]+)(@[^@/]+)?(/[^@]+)?$") + message(FATAL_ERROR + "Invalid revision / identifier format for ${board_in} (${${board_in}}). " + "Valid format is: @/" + ) + endif() + string(REPLACE "@" "" board_revision "${CMAKE_MATCH_2}") + + set(${name_out} ${CMAKE_MATCH_1} PARENT_SCOPE) + set(${revision_out} ${board_revision} PARENT_SCOPE) + set(${identifier_out} ${CMAKE_MATCH_3} PARENT_SCOPE) +endfunction() + +parse_board_components( + BOARD + BOARD BOARD_REVISION BOARD_IDENTIFIER +) zephyr_get(ZEPHYR_BOARD_ALIASES) if(DEFINED ZEPHYR_BOARD_ALIASES) include(${ZEPHYR_BOARD_ALIASES}) if(${BOARD}_BOARD_ALIAS) set(BOARD_ALIAS ${BOARD} CACHE STRING "Board alias, provided by user") - set(BOARD ${${BOARD}_BOARD_ALIAS}) + parse_board_components( + ${BOARD}_BOARD_ALIAS + BOARD BOARD_ALIAS_REVISION BOARD_ALIAS_IDENTIFIER + ) message(STATUS "Aliased BOARD=${BOARD_ALIAS} changed to ${BOARD}") + if(NOT DEFINED BOARD_REVISION) + set(BOARD_REVISION ${BOARD_ALIAS_REVISION}) + endif() + set(BOARD_IDENTIFIER ${BOARD_ALIAS_IDENTIFIER}${BOARD_IDENTIFIER}) endif() endif() + include(${ZEPHYR_BASE}/boards/deprecated.cmake) -if(${BOARD}_DEPRECATED) - set(BOARD_DEPRECATED ${BOARD} CACHE STRING "Deprecated board name, provided by user") - set(BOARD ${${BOARD}_DEPRECATED}) - message(WARNING "Deprecated BOARD=${BOARD_DEPRECATED} name specified, board automatically changed to: ${BOARD}.") +if(${BOARD}${BOARD_IDENTIFIER}_DEPRECATED) + set(BOARD_DEPRECATED ${BOARD}${BOARD_IDENTIFIER} CACHE STRING "Deprecated BOARD, provided by user") + message(WARNING + "Deprecated BOARD=${BOARD_DEPRECATED} specified, " + "board automatically changed to: ${${BOARD}${BOARD_IDENTIFIER}_DEPRECATED}." + ) + parse_board_components( + ${BOARD}${BOARD_IDENTIFIER}_DEPRECATED + BOARD BOARD_DEPRECATED_REVISION BOARD_IDENTIFIER + ) + if(DEFINED BOARD_DEPRECATED_REVISION) + if(DEFINED BOARD_REVISION) + message(FATAL_ERROR + "Invalid board revision: ${BOARD_REVISION}\n" + "Deprecated board '${BOARD_DEPRECATED}' is now implemented as a revision of another board " + "(${BOARD}@${BOARD_DEPRECATED_REVISION}), so the specified revision does not apply. " + "Please consult the documentation for '${BOARD}' to see how to build for the new board." + ) + endif() + set(BOARD_REVISION ${BOARD_DEPRECATED_REVISION}) + endif() endif() zephyr_boilerplate_watch(BOARD) @@ -95,41 +134,166 @@ Hints: - if your board directory is '/foo/bar/boards//my_board' then add '/foo/bar' to BOARD_ROOT, not the entire board directory - if in doubt, use absolute paths") endif() +endforeach() + +if((HWMv1 AND NOT EXISTS ${BOARD_DIR}/${BOARD}_defconfig) + OR (HWMv2 AND NOT EXISTS ${BOARD_DIR}/board.yml)) + message(WARNING "BOARD_DIR: ${BOARD_DIR} has been moved or deleted. " + "Trying to find new location." + ) + set(BOARD_DIR BOARD_DIR-NOTFOUND CACHE PATH "Path to a file." FORCE) +endif() + +# Prepare list boards command. +# This command is used for locating the board dir as well as printing all boards +# in the system in the following cases: +# - User specifies an invalid BOARD +# - User invokes ' boards' target +list(TRANSFORM ARCH_ROOT PREPEND "--arch-root=" OUTPUT_VARIABLE arch_root_args) +list(TRANSFORM BOARD_ROOT PREPEND "--board-root=" OUTPUT_VARIABLE board_root_args) +list(TRANSFORM SOC_ROOT PREPEND "--soc-root=" OUTPUT_VARIABLE soc_root_args) + +set(list_boards_commands + COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/list_boards.py + ${arch_root_args} ${board_root_args} --arch-root=${ZEPHYR_BASE} + ${soc_root_args} --soc-root=${ZEPHYR_BASE} +) + +if(NOT BOARD_DIR) + if(BOARD_ALIAS) + execute_process(${list_boards_commands} --board=${BOARD_ALIAS} --cmakeformat={DIR} + OUTPUT_VARIABLE ret_board + ERROR_VARIABLE err_board + RESULT_VARIABLE ret_val + ) + string(STRIP "${ret_board}" ret_board) + cmake_parse_arguments(BOARD_HIDDEN "" "DIR" "" ${ret_board}) + set(BOARD_HIDDEN_DIR ${BOARD_HIDDEN_DIR} CACHE PATH "Path to a folder." FORCE) - # NB: find_path will return immediately if the output variable is - # already set - if (BOARD_ALIAS) - find_path(BOARD_HIDDEN_DIR - NAMES ${BOARD_ALIAS}_defconfig - PATHS ${root}/boards/*/* - NO_DEFAULT_PATH - ) if(BOARD_HIDDEN_DIR) message("Board alias ${BOARD_ALIAS} is hiding the real board of same name") endif() endif() - if(BOARD_DIR AND NOT EXISTS ${BOARD_DIR}/${BOARD}_defconfig) - message(WARNING "BOARD_DIR: ${BOARD_DIR} has been moved or deleted. " - "Trying to find new location." - ) - set(BOARD_DIR BOARD_DIR-NOTFOUND CACHE PATH "Path to a file." FORCE) +endif() + +set(format_str "{NAME}\;{DIR}\;{HWM}\;") +set(format_str "${format_str}{REVISION_FORMAT}\;{REVISION_DEFAULT}\;{REVISION_EXACT}\;") +set(format_str "${format_str}{REVISIONS}\;{SOCS}\;{IDENTIFIERS}") + +if(BOARD_DIR) + set(board_dir_arg "--board-dir=${BOARD_DIR}") +endif() +execute_process(${list_boards_commands} --board=${BOARD} ${board_dir_arg} + --cmakeformat=${format_str} + OUTPUT_VARIABLE ret_board + ERROR_VARIABLE err_board + RESULT_VARIABLE ret_val +) +if(ret_val) + message(FATAL_ERROR "Error finding board: ${BOARD}\nError message: ${err_board}") +endif() + +if(NOT "${ret_board}" STREQUAL "") + string(STRIP "${ret_board}" ret_board) + set(single_val "NAME;DIR;HWM;REVISION_FORMAT;REVISION_DEFAULT;REVISION_EXACT") + set(multi_val "REVISIONS;SOCS;IDENTIFIERS") + cmake_parse_arguments(BOARD "" "${single_val}" "${multi_val}" ${ret_board}) + set(BOARD_DIR ${BOARD_DIR} CACHE PATH "Board directory for board (${BOARD})" FORCE) + + # Create two CMake variables identifying the hw model. + # CMake variable: HWM=[v1,v2] + # CMake variable: HWMv1=True, when HWMv1 is in use. + # CMake variable: HWMv2=True, when HWMv2 is in use. + set(HWM ${BOARD_HWM} CACHE INTERNAL "Zephyr hardware model version") + set(HWM${HWM} True CACHE INTERNAL "Zephyr hardware model") +elseif(BOARD_DIR) + message(FATAL_ERROR "Error finding board: ${BOARD} in ${BOARD_DIR}.\n" + "This indicates the board has been removed, renamed, or placed at a new location.\n" + "Please run a pristine build." + ) +else() + message("No board named '${BOARD}' found.\n\n" + "Please choose one of the following boards:\n" + ) + execute_process(${list_boards_commands}) + unset(CACHED_BOARD CACHE) + message(FATAL_ERROR "Invalid BOARD; see above.") +endif() + +if(HWMv1 AND DEFINED BOARD_IDENTIFIER) + message(FATAL_ERROR + "Board '${BOARD}' does not support board identifiers, ${BOARD}${BOARD_IDENTIFIER}.\n" + "Please specify board without an identifier.\n" + ) +endif() + +cmake_path(IS_PREFIX ZEPHYR_BASE "${BOARD_DIR}" NORMALIZE in_zephyr_tree) +if(NOT in_zephyr_tree) + set(USING_OUT_OF_TREE_BOARD 1) +endif() + +if(HWMv1) + if(EXISTS ${BOARD_DIR}/revision.cmake) + # Board provides revision handling. + include(${BOARD_DIR}/revision.cmake) + elseif(BOARD_REVISION) + message(WARNING "Board revision ${BOARD_REVISION} specified for ${BOARD}, \ + but board has no revision so revision will be ignored.") endif() - find_path(BOARD_DIR - NAMES ${BOARD}_defconfig - PATHS ${root}/boards/*/* - NO_DEFAULT_PATH +elseif(HWMv2) + if(BOARD_REVISION_FORMAT) + if(BOARD_REVISION_FORMAT STREQUAL "custom") + include(${BOARD_DIR}/revision.cmake) + else() + if(EXISTS ${BOARD_DIR}/revision.cmake) + message(WARNING + "revision.cmake ignored, revision.cmake is only used for revision format: 'custom'" + ) + endif() + + string(TOUPPER "${BOARD_REVISION_FORMAT}" rev_format) + if(BOARD_REVISION_EXACT) + set(rev_exact EXACT) + endif() + + board_check_revision( + FORMAT ${rev_format} + DEFAULT_REVISION ${BOARD_REVISION_DEFAULT} + VALID_REVISIONS ${BOARD_REVISIONS} + ${rev_exact} + ) + endif() + elseif(DEFINED BOARD_REVISION) + if(EXISTS ${BOARD_DIR}/revision.cmake) + message(WARNING + "revision.cmake is not used, revisions must be defined in '${BOARD_DIR}/board.yml'" + ) + endif() + + message(FATAL_ERROR "Invalid board revision: ${BOARD_REVISION}\n" + "Board '${BOARD}' does not define any revisions." ) - if(BOARD_DIR AND NOT (${root} STREQUAL ${ZEPHYR_BASE})) - set(USING_OUT_OF_TREE_BOARD 1) endif() -endforeach() -if(EXISTS ${BOARD_DIR}/revision.cmake) - # Board provides revision handling. - include(${BOARD_DIR}/revision.cmake) -elseif(BOARD_REVISION) - message(WARNING "Board revision ${BOARD_REVISION} specified for ${BOARD}, \ - but board has no revision so revision will be ignored.") + if(BOARD_IDENTIFIERS) + # Allow users to omit the SoC when building for a board with a single SoC. + list(LENGTH BOARD_SOCS socs_length) + if(NOT DEFINED BOARD_IDENTIFIER AND socs_length EQUAL 1) + set(BOARD_IDENTIFIER "/${BOARD_SOCS}") + elseif("${BOARD_IDENTIFIER}" MATCHES "^//.*" AND socs_length EQUAL 1) + string(REGEX REPLACE "^//" "/${BOARD_SOCS}/" BOARD_IDENTIFIER "${BOARD_IDENTIFIER}") + endif() + + if(NOT ("${BOARD}${BOARD_IDENTIFIER}" IN_LIST BOARD_IDENTIFIERS)) + string(REPLACE ";" "\n" BOARD_IDENTIFIERS "${BOARD_IDENTIFIERS}") + unset(CACHED_BOARD CACHE) + message(FATAL_ERROR "Board identifier `${BOARD_IDENTIFIER}` for board \ + `${BOARD}` not found. Please specify a valid board.\n" + "Valid board identifiers for ${BOARD_NAME} are:\n${BOARD_IDENTIFIERS}\n") + endif() + endif() +else() + message(FATAL_ERROR "Unknown hw model (${HWM}) for board: ${BOARD}.") endif() set(board_message "Board: ${BOARD}") @@ -144,29 +308,13 @@ if(DEFINED BOARD_REVISION) string(REPLACE "." "_" BOARD_REVISION_STRING ${BOARD_REVISION}) endif() -message(STATUS "${board_message}") - -# Prepare boards usage command printing. -# This command prints all boards in the system in the following cases: -# - User specifies an invalid BOARD -# - User invokes ' boards' target -list(TRANSFORM ARCH_ROOT PREPEND "--arch-root=" OUTPUT_VARIABLE arch_root_args) -list(TRANSFORM BOARD_ROOT PREPEND "--board-root=" OUTPUT_VARIABLE board_root_args) - -set(list_boards_commands - COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/list_boards.py - ${arch_root_args} ${board_root_args} --arch-root=${ZEPHYR_BASE} -) - -if(NOT BOARD_DIR) - message("No board named '${BOARD}' found.\n\n" - "Please choose one of the following boards:\n" - ) - execute_process(${list_boards_commands}) - unset(CACHED_BOARD CACHE) - message(FATAL_ERROR "Invalid BOARD; see above.") +if(DEFINED BOARD_IDENTIFIER) + string(REGEX REPLACE "^/" "identifier: " board_message_identifier "${BOARD_IDENTIFIER}") + set(board_message "${board_message}, ${board_message_identifier}") endif() +message(STATUS "${board_message}") + add_custom_target(boards ${list_boards_commands} USES_TERMINAL) # Board extensions are enabled by default diff --git a/cmake/modules/configuration_files.cmake b/cmake/modules/configuration_files.cmake index 4f2e469ab79065..e23110b88b7d41 100644 --- a/cmake/modules/configuration_files.cmake +++ b/cmake/modules/configuration_files.cmake @@ -77,8 +77,15 @@ zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR}/boards DTS APP_BOARD_DTS SUFFIX zephyr_get(DTC_OVERLAY_FILE SYSBUILD LOCAL) if(NOT DEFINED DTC_OVERLAY_FILE) + zephyr_build_string(board_overlay_strings + BOARD ${BOARD} + BOARD_IDENTIFIER ${BOARD_IDENTIFIER} + MERGE + ) + list(TRANSFORM board_overlay_strings APPEND ".overlay") + zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR} DTS DTC_OVERLAY_FILE - NAMES "${APP_BOARD_DTS};${BOARD}.overlay;app.overlay" SUFFIX ${FILE_SUFFIX}) + NAMES "${APP_BOARD_DTS};${board_overlay_strings};app.overlay" SUFFIX ${FILE_SUFFIX}) endif() set(DTC_OVERLAY_FILE ${DTC_OVERLAY_FILE} CACHE STRING "If desired, you can \ diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake index 23659c18692447..bf19e602f6d1ec 100644 --- a/cmake/modules/dts.cmake +++ b/cmake/modules/dts.cmake @@ -122,11 +122,26 @@ set(DTS_CMAKE ${PROJECT_BINARY_DIR}/dts.cmake) # modules. set(VENDOR_PREFIXES dts/bindings/vendor-prefixes.txt) -set_ifndef(DTS_SOURCE ${BOARD_DIR}/${BOARD}.dts) +if(NOT DEFINED DTS_SOURCE) + zephyr_build_string(dts_board_string BOARD ${BOARD} BOARD_IDENTIFIER ${BOARD_IDENTIFIER} MERGE) + foreach(str ${dts_board_string}) + if(EXISTS ${BOARD_DIR}/${str}.dts) + set(DTS_SOURCE ${BOARD_DIR}/${str}.dts) + break() + endif() + endforeach() +endif() + if(EXISTS ${DTS_SOURCE}) # We found a devicetree. Check for a board revision overlay. - if(DEFINED BOARD_REVISION AND EXISTS ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay) - list(APPEND DTS_SOURCE ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.overlay) + if(DEFINED BOARD_REVISION) + zephyr_build_string(dts_board_string BOARD ${BOARD} + BOARD_IDENTIFIER ${BOARD_IDENTIFIER} + BOARD_REVISION ${BOARD_REVISION} + ) + if(EXISTS ${BOARD_DIR}/${dts_board_string}.overlay) + list(APPEND DTS_SOURCE ${BOARD_DIR}/${dts_board_string}.overlay) + endif() endif() else() # If we don't have a devicetree, provide an empty stub diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake index e636a2cb473493..4e8f454711bf99 100644 --- a/cmake/modules/extensions.cmake +++ b/cmake/modules/extensions.cmake @@ -1510,18 +1510,38 @@ endfunction() # # This is a common function to ensure that build strings are always created # in a uniform way. +# A single string is returned containing the full build string constructed from +# all arguments. +# +# When MERGE is supplied a list of build strings will be returned with the full +# build string as first item in the list. +# The full order of build strings returned in the list will be: +# - Full build string, including identifier and revision +# - Build string with board variants removed in addition +# - Build string with cpuset removed in addition +# - Build string with soc removed in addition +# +# If BUILD is supplied, then build type will be appended to each entry in the +# list above. +# If REVISION is supplied or obtained as system wide setting a build string +# with the sanitized revision string will be added in addition to the +# non-revisioned entry for each entry. # # Usage: # zephyr_build_string( # BOARD +# [BOARD_IDENTIFIER ] # [BOARD_REVISION ] # [BUILD ] +# [MERGE [REVERSE]] # ) # # : Output variable where the build string will be returned. # BOARD : Board name to use when creating the build string. # BOARD_REVISION : Board revision to use when creating the build string. # BUILD : Build type to use when creating the build string. +# MERGE: Return a list of build identifiers instead of a single build string. +# REVERSE: Reverse the list before returning it. # # Examples # calling @@ -1532,10 +1552,20 @@ endfunction() # zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0 BUILD debug) # will return the string `alpha_1_0_0_debug` in `build_string` parameter. # +# calling +# zephyr_build_string(build_string BOARD alpha BOARD_IDENTIFIER /soc/bar) +# will return the string `alpha_soc_bar` in `build_string` parameter. +# +# calling +# zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0 BOARD_IDENTIFIER /soc/bar MERGE) +# will return a list of the following strings +# `alpha_soc_bar_1_0_0;alpha_soc_bar;alpha_soc_1_0_0;alpha_soc;alpha_1_0_0;alpha` in `build_string` parameter. +# function(zephyr_build_string outvar) - set(single_args BOARD BOARD_REVISION BUILD) + set(options MERGE REVERSE) + set(single_args BOARD BOARD_IDENTIFIER BOARD_REVISION BUILD) - cmake_parse_arguments(BUILD_STR "" "${single_args}" "" ${ARGN}) + cmake_parse_arguments(BUILD_STR "${options}" "${single_args}" "" ${ARGN}) if(BUILD_STR_UNPARSED_ARGUMENTS) message(FATAL_ERROR "zephyr_build_string(${ARGV0} ...) given unknown arguments:" @@ -1550,15 +1580,37 @@ function(zephyr_build_string outvar) ) endif() - set(${outvar} ${BUILD_STR_BOARD}) + if(DEFINED BUILD_STR_BOARD_IDENTIFIER AND NOT BUILD_STR_BOARD) + message(FATAL_ERROR + "zephyr_build_string(${ARGV0} BOARD_IDENTIFIER ${BUILD_STR_BOARD_IDENTIFIER} ...)" + " given without BOARD argument, please specify BOARD" + ) + endif() + + string(REPLACE "/" ";" str_segment_list "${BUILD_STR_BOARD}${BUILD_STR_BOARD_IDENTIFIER}") + string(REPLACE "." "_" revision_string "${BUILD_STR_BOARD_REVISION}") + + string(JOIN "_" ${outvar} ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) - if(DEFINED BUILD_STR_BOARD_REVISION) - string(REPLACE "." "_" revision_string ${BUILD_STR_BOARD_REVISION}) - set(${outvar} "${${outvar}}_${revision_string}") + if(BUILD_STR_MERGE) + if(DEFINED BUILD_STR_BOARD_REVISION) + string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) + list(APPEND ${outvar} "${variant_string}") + endif() + list(POP_BACK str_segment_list) + while(NOT str_segment_list STREQUAL "") + if(DEFINED BUILD_STR_BOARD_REVISION) + string(JOIN "_" variant_string ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD}) + list(APPEND ${outvar} "${variant_string}") + endif() + string(JOIN "_" variant_string ${str_segment_list} ${BUILD_STR_BUILD}) + list(APPEND ${outvar} "${variant_string}") + list(POP_BACK str_segment_list) + endwhile() endif() - if(BUILD_STR_BUILD) - set(${outvar} "${${outvar}}_${BUILD_STR_BUILD}") + if(BUILD_STR_REVERSE) + list(REVERSE ${outvar}) endif() # This updates the provided outvar in parent scope (callers scope) @@ -2362,7 +2414,7 @@ endfunction() # Usage: # print(BOARD) # -# will print: "BOARD: nrf52dk_nrf52832" +# will print: "BOARD: nrf52dk" function(print arg) message(STATUS "${arg}: ${${arg}}") endfunction() @@ -2436,6 +2488,7 @@ endfunction() # files are returned. Configuration files will be: # - DTS: Overlay files (.overlay) # - Kconfig: Config fragments (.conf) +# - defconfig: defconfig files (_defconfig) # The conf file search will return existing configuration # files for the current board. # CONF_FILES takes the following additional arguments: @@ -2454,6 +2507,7 @@ endfunction() # # DTS : List to append DTS overlay files in to # KCONF : List to append Kconfig fragment files in to +# DEFCONF : List to append _defconfig files in to # BUILD : Build type to include for search. # For example: # BUILD debug, will look for _debug.conf @@ -2477,7 +2531,7 @@ Please provide one of following: APPLICATION_ROOT, CONF_FILES") set(single_args APPLICATION_ROOT) elseif(${ARGV0} STREQUAL CONF_FILES) set(options REQUIRED) - set(single_args BOARD BOARD_REVISION DTS KCONF BUILD SUFFIX) + set(single_args BOARD BOARD_REVISION BOARD_IDENTIFIER DTS KCONF DEFCONFIG BUILD SUFFIX) set(multi_args CONF_FILES NAMES) endif() @@ -2535,24 +2589,23 @@ Relative paths are only allowed with `-D${ARGV1}=`") if(DEFINED BOARD_REVISION) set(FILE_BOARD_REVISION ${BOARD_REVISION}) endif() + + if(DEFINED BOARD_IDENTIFIER) + set(FILE_BOARD_IDENTIFIER ${BOARD_IDENTIFIER}) + endif() endif() if(FILE_NAMES) set(dts_filename_list ${FILE_NAMES}) set(kconf_filename_list ${FILE_NAMES}) else() - zephyr_build_string(filename - BOARD ${FILE_BOARD} - BUILD ${FILE_BUILD} - ) - set(filename_list ${filename}) - - zephyr_build_string(filename + zephyr_build_string(filename_list BOARD ${FILE_BOARD} BOARD_REVISION ${FILE_BOARD_REVISION} + BOARD_IDENTIFIER ${FILE_BOARD_IDENTIFIER} BUILD ${FILE_BUILD} + MERGE REVERSE ) - list(APPEND filename_list ${filename}) list(REMOVE_DUPLICATES filename_list) set(dts_filename_list ${filename_list}) list(TRANSFORM dts_filename_list APPEND ".overlay") @@ -2636,6 +2689,19 @@ Relative paths are only allowed with `-D${ARGV1}=`") message(DEPRECATION "prj_.conf was deprecated after Zephyr 3.5," " you should switch to using -DFILE_SUFFIX instead") endif() + + if(FILE_DEFCONFIG) + foreach(path ${FILE_CONF_FILES}) + foreach(filename ${filename_list}) + if(EXISTS ${path}/${filename}_defconfig) + list(APPEND ${FILE_DEFCONFIG} ${path}/${filename}_defconfig) + endif() + endforeach() + endforeach() + + # This updates the provided list in parent scope (callers scope) + set(${FILE_DEFCONFIG} ${${FILE_DEFCONFIG}} PARENT_SCOPE) + endif() endif() endfunction() diff --git a/cmake/modules/hwm_v2.cmake b/cmake/modules/hwm_v2.cmake new file mode 100644 index 00000000000000..38af4083fb1a92 --- /dev/null +++ b/cmake/modules/hwm_v2.cmake @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +# This CMake module works together with the list_hardware.py script to obtain +# all archs and SoC implementations defined in the Zephyr build system. +# +# The result from list_hardware.py is then used to generate Kconfig files for +# the build system. +# +# The following files are generated in '/soc' +# - Kconfig.defconfig: Contains references to SoC defconfig files for Zephyr integration. +# - Kconfig: Contains references to regular SoC Kconfig files for Zephyr integration. +# - Kconfig.soc: Contains references to generic SoC Kconfig files. +# +# The following file is generated in '/arch' +# - Kconfig: Contains references to regular arch Kconfig files for Zephyr integration. + +include_guard(GLOBAL) + +if(NOT HWMv2) + return() +endif() + +# Internal helper function for creation of Kconfig files. +function(kconfig_gen bin_dir file dirs) + file(MAKE_DIRECTORY "${bin_dir}") + set(kconfig_file ${bin_dir}/${file}) + foreach(dir ${dirs}) + cmake_path(CONVERT "${dir}" TO_CMAKE_PATH_LIST dir) + file(APPEND ${kconfig_file} "osource \"${dir}/${file}\"\n") + endforeach() +endfunction() + +# 'SOC_ROOT' and 'ARCH_ROOT' are prioritized lists of directories where their +# implementations may be found. It always includes ${ZEPHYR_BASE}/[arch|soc] +# at the lowest priority. +list(APPEND SOC_ROOT ${ZEPHYR_BASE}) +list(APPEND ARCH_ROOT ${ZEPHYR_BASE}) + +list(TRANSFORM ARCH_ROOT PREPEND "--arch-root=" OUTPUT_VARIABLE arch_root_args) +list(TRANSFORM SOC_ROOT PREPEND "--soc-root=" OUTPUT_VARIABLE soc_root_args) + +execute_process(COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/list_hardware.py + ${arch_root_args} ${soc_root_args} + --archs --socs + --cmakeformat={TYPE}\;{NAME}\;{DIR}\;{HWM} + OUTPUT_VARIABLE ret_hw + ERROR_VARIABLE err_hw + RESULT_VARIABLE ret_val +) +if(ret_val) + message(FATAL_ERROR "Error listing hardware.\nError message: ${err_hw}") +endif() + +set(kconfig_soc_source_dir) + +while(TRUE) + string(FIND "${ret_hw}" "\n" idx REVERSE) + math(EXPR start "${idx} + 1") + string(SUBSTRING "${ret_hw}" ${start} -1 line) + string(SUBSTRING "${ret_hw}" 0 ${idx} ret_hw) + + cmake_parse_arguments(HWM "" "TYPE" "" ${line}) + if(HWM_TYPE STREQUAL "arch") + cmake_parse_arguments(ARCH_V2 "" "NAME;DIR" "" ${line}) + + list(APPEND kconfig_arch_source_dir "${ARCH_V2_DIR}") + list(APPEND ARCH_V2_NAME_LIST ${ARCH_V2_NAME}) + string(TOUPPER "${ARCH_V2_NAME}" ARCH_V2_NAME_UPPER) + set(ARCH_V2_${ARCH_V2_NAME_UPPER}_DIR ${ARCH_V2_DIR}) + elseif(HWM_TYPE MATCHES "^soc|^series|^family") + cmake_parse_arguments(SOC_V2 "" "NAME;DIR;HWM" "" ${line}) + + list(APPEND kconfig_soc_source_dir "${SOC_V2_DIR}") + + if(HWM_TYPE STREQUAL "soc") + set(setting_name SOC_${SOC_V2_NAME}_DIR) + else() + set(setting_name SOC_${HWM_TYPE}_${SOC_V2_NAME}_DIR) + endif() + # We support both SOC_foo_DIR and SOC_FOO_DIR. + set(${setting_name} ${SOC_V2_DIR}) + string(TOUPPER ${setting_name} setting_name) + set(${setting_name} ${SOC_V2_DIR}) + endif() + + if(idx EQUAL -1) + break() + endif() +endwhile() +list(REMOVE_DUPLICATES kconfig_soc_source_dir) + +# Support multiple ARCH_ROOT and SOC_ROOT +set(arch_kconfig_file Kconfig) +set(soc_defconfig_file Kconfig.defconfig) +set(soc_zephyr_file Kconfig) +set(soc_kconfig_file Kconfig.soc) +set(arch_kconfig_header "# Load arch Kconfig descriptions.\n") +set(defconfig_header "# Load Zephyr SoC Kconfig defconfig.\n") +set(soc_zephyr_header "# Load Zephyr SoC Kconfig descriptions.\n") +set(soc_kconfig_header "# Load SoC Kconfig descriptions.\n") +file(WRITE ${KCONFIG_BINARY_DIR}/arch/${arch_kconfig_file} "${arch_kconfig_header}") +file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_defconfig_file} "${defconfig_header}") +file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_zephyr_file} "${soc_zephyr_header}") +file(WRITE ${KCONFIG_BINARY_DIR}/soc/${soc_kconfig_file} "${soc_kconfig_header}") + +kconfig_gen("${KCONFIG_BINARY_DIR}/arch" "${arch_kconfig_file}" "${kconfig_arch_source_dir}") +kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_defconfig_file}" "${kconfig_soc_source_dir}") +kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_zephyr_file}" "${kconfig_soc_source_dir}") +kconfig_gen("${KCONFIG_BINARY_DIR}/soc" "${soc_kconfig_file}" "${kconfig_soc_source_dir}") + +# Clear variables created by cmake_parse_arguments +unset(SOC_V2_NAME) +unset(SOC_V2_DIR) +unset(SOC_V2_HWM) +unset(ARCH_V2_NAME) +unset(ARCH_V2_DIR) diff --git a/cmake/modules/kconfig.cmake b/cmake/modules/kconfig.cmake index f355bf2beb5318..ae11892750a42a 100644 --- a/cmake/modules/kconfig.cmake +++ b/cmake/modules/kconfig.cmake @@ -22,23 +22,30 @@ set_ifndef(KCONFIG_NAMESPACE "CONFIG") set_ifndef(KCONFIG_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/Kconfig) file(MAKE_DIRECTORY ${KCONFIG_BINARY_DIR}) -# Support multiple SOC_ROOT, remove ZEPHYR_BASE as that is always sourced. -set(kconfig_soc_root ${SOC_ROOT}) -list(REMOVE_ITEM kconfig_soc_root ${ZEPHYR_BASE}) -set(OPERATION WRITE) -foreach(root ${kconfig_soc_root}) - file(${OPERATION} ${KCONFIG_BINARY_DIR}/Kconfig.soc.defconfig - "osource \"${root}/soc/$(ARCH)/*/Kconfig.defconfig\"\n" - ) - file(${OPERATION} ${KCONFIG_BINARY_DIR}/Kconfig.soc - "osource \"${root}/soc/$(ARCH)/*/Kconfig.soc\"\n" - ) - file(${OPERATION} ${KCONFIG_BINARY_DIR}/Kconfig.soc.arch - "osource \"${root}/soc/$(ARCH)/Kconfig\"\n" - "osource \"${root}/soc/$(ARCH)/*/Kconfig\"\n" - ) - set(OPERATION APPEND) -endforeach() +if(HWMv1) + # Support multiple SOC_ROOT + file(MAKE_DIRECTORY ${KCONFIG_BINARY_DIR}/soc) + set(kconfig_soc_root ${BOARD_ROOT}) + list(REMOVE_ITEM kconfig_soc_root ${ZEPHYR_BASE}) + set(soc_defconfig_file ${KCONFIG_BINARY_DIR}/soc/Kconfig.defconfig) + + # This loads Zephyr base SoC root defconfigs + file(WRITE ${soc_defconfig_file} "osource \"soc/soc_legacy/$(ARCH)/*/Kconfig.defconfig\"\n") + + set(OPERATION WRITE) + foreach(root ${kconfig_soc_root}) + file(APPEND ${soc_defconfig_file} + "osource \"${root}/soc/soc_legacy/$(ARCH)/*/Kconfig.defconfig\"\n") + file(${OPERATION} ${KCONFIG_BINARY_DIR}/soc/Kconfig.soc.choice + "osource \"${root}/soc/soc_legacy/$(ARCH)/*/Kconfig.soc\"\n" + ) + file(${OPERATION} ${KCONFIG_BINARY_DIR}/soc/Kconfig.soc.arch + "osource \"${root}/soc/soc_legacy/$(ARCH)/Kconfig\"\n" + "osource \"${root}/soc/soc_legacy/$(ARCH)/*/Kconfig\"\n" + ) + set(OPERATION APPEND) + endforeach() +endif() # Support multiple shields in BOARD_ROOT, remove ZEPHYR_BASE as that is always sourced. set(kconfig_board_root ${BOARD_ROOT}) @@ -67,10 +74,23 @@ else() set(KCONFIG_ROOT ${ZEPHYR_BASE}/Kconfig) endif() -set_ifndef(BOARD_DEFCONFIG ${BOARD_DIR}/${BOARD}_defconfig) -if((DEFINED BOARD_REVISION) AND EXISTS ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.conf) - set_ifndef(BOARD_REVISION_CONFIG ${BOARD_DIR}/${BOARD}_${BOARD_REVISION_STRING}.conf) +if(NOT DEFINED BOARD_DEFCONFIG) + zephyr_file(CONF_FILES ${BOARD_DIR} DEFCONFIG BOARD_DEFCONFIG) endif() + +if(DEFINED BOARD_REVISION) + zephyr_build_string(config_board_string + BOARD ${BOARD} + BOARD_IDENTIFIER ${BOARD_IDENTIFIER} + BOARD_REVISION ${BOARD_REVISION} + ) + set(board_rev_file ${config_board_string}) + if(EXISTS ${BOARD_DIR}/${board_rev_file}.conf) + message(DEPRECATION "Use of '${board_rev_file}.conf' is deprecated, please switch to '${board_rev_file}_defconfig'") + set_ifndef(BOARD_REVISION_CONFIG ${BOARD_DIR}/${board_rev_file}.conf) + endif() +endif() + set(DOTCONFIG ${PROJECT_BINARY_DIR}/.config) set(PARSED_KCONFIG_SOURCES_TXT ${PROJECT_BINARY_DIR}/kconfig/sources.txt) @@ -137,12 +157,11 @@ set(COMMON_KCONFIG_ENV_SETTINGS APP_VERSION_TWEAK_STRING=${APP_VERSION_TWEAK_STRING} CONFIG_=${KCONFIG_NAMESPACE}_ KCONFIG_CONFIG=${DOTCONFIG} - # Set environment variables so that Kconfig can prune Kconfig source - # files for other architectures - ARCH=${ARCH} - ARCH_DIR=${ARCH_DIR} BOARD_DIR=${BOARD_DIR} + BOARD=${BOARD} BOARD_REVISION=${BOARD_REVISION} + BOARD_IDENTIFIER=${BOARD_IDENTIFIER} + HWM_SCHEME=${HWM} KCONFIG_BINARY_DIR=${KCONFIG_BINARY_DIR} APPLICATION_SOURCE_DIR=${APPLICATION_SOURCE_DIR} ZEPHYR_TOOLCHAIN_VARIANT=${ZEPHYR_TOOLCHAIN_VARIANT} @@ -154,6 +173,21 @@ set(COMMON_KCONFIG_ENV_SETTINGS ${ZEPHYR_KCONFIG_MODULES_DIR} ) +if(HWMv1) + list(APPEND COMMON_KCONFIG_ENV_SETTINGS + ARCH=${ARCH} + ARCH_DIR=${ARCH_DIR} + ) +else() + # For HWMv2 we should in future generate a Kconfig.arch.v2 which instead + # glob-sources all arch roots, but for Zephyr itself, the current approach is + # sufficient. + list(APPEND COMMON_KCONFIG_ENV_SETTINGS + ARCH=* + ARCH_DIR=${ZEPHYR_BASE}/arch + ) +endif() + # Allow out-of-tree users to add their own Kconfig python frontend # targets by appending targets to the CMake list # 'EXTRA_KCONFIG_TARGETS' and setting variables named diff --git a/cmake/modules/pre_dt.cmake b/cmake/modules/pre_dt.cmake index b19fd7f7fb57e8..4e062b2b97069e 100644 --- a/cmake/modules/pre_dt.cmake +++ b/cmake/modules/pre_dt.cmake @@ -62,6 +62,14 @@ function(pre_dt_module_run) # Finalize DTS_ROOT. list(REMOVE_DUPLICATES DTS_ROOT) + if(HWMv1) + set(arch_include dts/${ARCH}) + else() + foreach(arch ${ARCH_V2_NAME_LIST}) + list(APPEND arch_include dts/${arch}) + endforeach() + endif() + # Finalize DTS_ROOT_SYSTEM_INCLUDE_DIRS. set(DTS_ROOT_SYSTEM_INCLUDE_DIRS) foreach(dts_root ${DTS_ROOT}) @@ -69,7 +77,7 @@ function(pre_dt_module_run) include include/zephyr dts/common - dts/${ARCH} + ${arch_include} dts ) get_filename_component(full_path ${dts_root}/${dts_root_path} REALPATH) diff --git a/cmake/modules/soc.cmake b/cmake/modules/soc.cmake deleted file mode 100644 index 5253620b6b9af7..00000000000000 --- a/cmake/modules/soc.cmake +++ /dev/null @@ -1,71 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021, Nordic Semiconductor ASA - -# Configure SoC settings based on Kconfig settings and SoC root. -# -# This CMake module will set the following variables in the build system based -# on Kconfig settings and selected SoC. -# -# If no implementation is available for the selected SoC an error will be raised. -# -# Outcome: -# The following variables will be defined when this CMake module completes: -# -# - SOC_NAME: Name of the SoC in use, identical to CONFIG_SOC -# - SOC_SERIES: Name of the SoC series in use, identical to CONFIG_SOC_SERIES -# - SOC_FAMILY: Name of the SoC family, identical to CONFIG_SOC_FAMILY -# - SOC_PATH: Path fragment defined by either SOC_NAME or SOC_FAMILY/SOC_SERIES. -# - SOC_DIR: Directory containing the SoC implementation -# - SOC_ROOT: SOC_ROOT with ZEPHYR_BASE appended -# -# Variable dependencies: -# - SOC_ROOT: CMake list of SoC roots containing SoC implementations -# -# Variables set by this module and not mentioned above are considered internal -# use only and may be removed, renamed, or re-purposed without prior notice. - -include_guard(GLOBAL) - -include(kconfig) - -# 'SOC_ROOT' is a prioritized list of directories where socs may be -# found. It always includes ${ZEPHYR_BASE}/soc at the lowest priority. -list(APPEND SOC_ROOT ${ZEPHYR_BASE}) - -set(SOC_NAME ${CONFIG_SOC}) -set(SOC_SERIES ${CONFIG_SOC_SERIES}) -set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME}) -set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) - -if("${SOC_SERIES}" STREQUAL "") - set(SOC_PATH ${SOC_NAME}) -else() - set(SOC_PATH ${SOC_FAMILY}/${SOC_SERIES}) -endif() - -# Use SOC to search for a 'CMakeLists.txt' file. -# e.g. zephyr/soc/xtensa/intel_adsp/CMakeLists.txt. -foreach(root ${SOC_ROOT}) - # Check that the root looks reasonable. - if(NOT IS_DIRECTORY "${root}/soc") - message(WARNING "\nSOC_ROOT element(s) without a 'soc' subdirectory: -${root} -Hints: - - if your SoC family directory is '/foo/bar/soc//my_soc_family', then add '/foo/bar' to SOC_ROOT, not the entire SoC family path - - if in doubt, use absolute paths\n") - endif() - - if(EXISTS ${root}/soc/${ARCH}/${SOC_PATH}) - set(SOC_DIR ${root}/soc) - break() - endif() -endforeach() - -if(NOT SOC_DIR) - message(FATAL_ERROR "Could not find SOC=${SOC_NAME} for BOARD=${BOARD},\n" - "please check your installation.\n" - "SOC roots searched:\n" - "${SOC_ROOT}\n" - ) -endif() diff --git a/cmake/modules/soc_v1.cmake b/cmake/modules/soc_v1.cmake new file mode 100644 index 00000000000000..1bba9536c0c217 --- /dev/null +++ b/cmake/modules/soc_v1.cmake @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021, Nordic Semiconductor ASA + +# Configure SoC settings based on Kconfig settings and SoC root. +# +# This CMake module will set the following variables in the build system based +# on Kconfig settings and selected SoC. +# +# If no implementation is available for the selected SoC an error will be raised. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - SOC_NAME: Name of the SoC in use, identical to CONFIG_SOC +# - SOC_SERIES: Name of the SoC series in use, identical to CONFIG_SOC_SERIES +# - SOC_FAMILY: Name of the SoC family, identical to CONFIG_SOC_FAMILY +# - SOC_PATH: Path fragment defined by either SOC_NAME or SOC_FAMILY/SOC_SERIES. +# - SOC_DIR: Directory containing the SoC implementation +# - SOC_ROOT: SOC_ROOT with ZEPHYR_BASE appended +# +# Variable dependencies: +# - SOC_ROOT: CMake list of SoC roots containing SoC implementations +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +include(kconfig) + +if(HWMv1) + # 'SOC_ROOT' is a prioritized list of directories where socs may be + # found. It always includes ${ZEPHYR_BASE}/soc at the lowest priority. + list(APPEND SOC_ROOT ${ZEPHYR_BASE}) + + set(SOC_NAME ${CONFIG_SOC}) + set(SOC_SERIES ${CONFIG_SOC_SERIES}) + set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME}) + set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) + + if("${SOC_SERIES}" STREQUAL "") + set(SOC_PATH ${SOC_NAME}) + else() + set(SOC_PATH ${SOC_FAMILY}/${SOC_SERIES}) + endif() + + # Use SOC to search for a 'CMakeLists.txt' file. + # e.g. zephyr/soc/xtensa/intel_adsp/CMakeLists.txt. + foreach(root ${SOC_ROOT}) + # Check that the root looks reasonable. + if(NOT IS_DIRECTORY "${root}/soc") + message(WARNING "\nSOC_ROOT element(s) without a 'soc' subdirectory: + ${root} + Hints: + - if your SoC family directory is '/foo/bar/soc//my_soc_family', then add '/foo/bar' to SOC_ROOT, not the entire SoC family path + - if in doubt, use absolute paths\n") + endif() + + if(EXISTS ${root}/soc/${ARCH}/${SOC_PATH}) + set(SOC_DIR ${root}/soc) + break() + elseif(EXISTS ${root}/soc/soc_legacy/${ARCH}/${SOC_PATH}) + set(SOC_DIR ${root}/soc/soc_legacy) + break() + endif() + endforeach() + + if(NOT SOC_DIR) + message(FATAL_ERROR "Could not find SOC=${SOC_NAME} for BOARD=${BOARD},\n" + "please check your installation.\n" + "SOC roots searched:\n" + "${SOC_ROOT}\n" + ) + endif() + + set(SOC_FULL_DIR ${SOC_DIR}/${ARCH}/${SOC_PATH}) +endif() diff --git a/cmake/modules/soc_v2.cmake b/cmake/modules/soc_v2.cmake new file mode 100644 index 00000000000000..866958e1f808bb --- /dev/null +++ b/cmake/modules/soc_v2.cmake @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021, Nordic Semiconductor ASA + +# Configure SoC settings based on Kconfig settings. +# +# This CMake module will set the following variables in the build system based +# on Kconfig settings for the selected SoC. +# +# Outcome: +# The following variables will be defined when this CMake module completes: +# +# - SOC_NAME: Name of the SoC in use, identical to CONFIG_SOC +# - SOC_SERIES: Name of the SoC series in use, identical to CONFIG_SOC_SERIES +# - SOC_FAMILY: Name of the SoC family, identical to CONFIG_SOC_FAMILY +# +# Variables set by this module and not mentioned above are considered internal +# use only and may be removed, renamed, or re-purposed without prior notice. + +include_guard(GLOBAL) + +include(kconfig) + +if(HWMv2) + set(SOC_NAME ${CONFIG_SOC}) + set(SOC_SERIES ${CONFIG_SOC_SERIES}) + set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME}) + set(SOC_FAMILY ${CONFIG_SOC_FAMILY}) + set(SOC_V2_DIR ${SOC_${SOC_NAME}_DIR}) + set(SOC_FULL_DIR ${SOC_V2_DIR}) +endif() diff --git a/cmake/modules/unittest.cmake b/cmake/modules/unittest.cmake index 8853f5a5b0cb6f..2551f41832a932 100644 --- a/cmake/modules/unittest.cmake +++ b/cmake/modules/unittest.cmake @@ -4,7 +4,7 @@ cmake_minimum_required(VERSION 3.20.0) include(root) include(boards) -include(arch) +include(arch_v1) include(configuration_files) include(west) diff --git a/cmake/modules/zephyr_default.cmake b/cmake/modules/zephyr_default.cmake index 98a580c3a2d5da..7472331255b814 100644 --- a/cmake/modules/zephyr_default.cmake +++ b/cmake/modules/zephyr_default.cmake @@ -96,7 +96,8 @@ list(APPEND zephyr_cmake_modules zephyr_module) list(APPEND zephyr_cmake_modules boards) list(APPEND zephyr_cmake_modules shields) list(APPEND zephyr_cmake_modules snippets) -list(APPEND zephyr_cmake_modules arch) +list(APPEND zephyr_cmake_modules arch_v1) +list(APPEND zephyr_cmake_modules hwm_v2) list(APPEND zephyr_cmake_modules configuration_files) list(APPEND zephyr_cmake_modules generated_file_directories) @@ -108,7 +109,9 @@ list(APPEND zephyr_cmake_modules "\${pre_dt_board}") # kconfig and dts should be available at the same time. list(APPEND zephyr_cmake_modules dts) list(APPEND zephyr_cmake_modules kconfig) -list(APPEND zephyr_cmake_modules soc) +list(APPEND zephyr_cmake_modules arch_v2) +list(APPEND zephyr_cmake_modules soc_v1) +list(APPEND zephyr_cmake_modules soc_v2) foreach(component ${SUB_COMPONENTS}) if(NOT ${component} IN_LIST zephyr_cmake_modules) diff --git a/doc/_extensions/zephyr/kconfig/__init__.py b/doc/_extensions/zephyr/kconfig/__init__.py index c4042e298ad0ac..c268ac474f92d9 100644 --- a/doc/_extensions/zephyr/kconfig/__init__.py +++ b/doc/_extensions/zephyr/kconfig/__init__.py @@ -28,8 +28,10 @@ ${BASE_PATH}/modules/${MODULE_NAME}/Kconfig. """ +import argparse import json import os +import re import sys from itertools import chain from pathlib import Path @@ -61,6 +63,8 @@ sys.path.insert(0, str(KCONFIGLIB)) import kconfiglib +import list_boards +import list_hardware import zephyr_module @@ -83,6 +87,47 @@ def kconfig_load(app: Sphinx) -> Tuple[kconfiglib.Kconfig, Dict[str, str]]: with open(Path(td) / "Kconfig.dts", "w") as f: f.write(kconfig) + (Path(td) / 'soc').mkdir(exist_ok=True) + root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]}) + v2_systems = list_hardware.find_v2_systems(root_args) + + soc_folders = {soc.folder for soc in v2_systems.get_socs()} + with open(Path(td) / "soc" / "Kconfig.defconfig", "w") as f: + f.write('') + + with open(Path(td) / "soc" / "Kconfig.soc", "w") as f: + for folder in soc_folders: + f.write('source "' + os.path.join(folder, 'Kconfig.soc') + '"\n') + + with open(Path(td) / "soc" / "Kconfig", "w") as f: + for folder in soc_folders: + f.write('osource "' + os.path.join(folder, 'Kconfig') + '"\n') + + (Path(td) / 'arch').mkdir(exist_ok=True) + root_args = argparse.Namespace(**{'arch_roots': [Path(ZEPHYR_BASE)], 'arch': None}) + v2_archs = list_hardware.find_v2_archs(root_args) + kconfig = "" + for arch in v2_archs['archs']: + kconfig += 'source "' + str(Path(arch['path']) / 'Kconfig') + '"\n' + with open(Path(td) / "arch" / "Kconfig", "w") as f: + f.write(kconfig) + + (Path(td) / 'boards').mkdir(exist_ok=True) + root_args = argparse.Namespace(**{'board_roots': [Path(ZEPHYR_BASE)], + 'soc_roots': [Path(ZEPHYR_BASE)], 'board': None}) + v2_boards = list_boards.find_v2_boards(root_args) + + with open(Path(td) / "boards" / "Kconfig.boards", "w") as f: + for board in v2_boards: + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", board.name).upper() + f.write('config ' + board_str + '\n') + f.write('\t bool\n') + for identifier in list_boards.board_v2_identifiers(board): + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", identifier).upper() + f.write('config ' + board_str + '\n') + f.write('\t bool\n') + f.write('source "' + os.path.join(board.dir, 'Kconfig.') + board.name + '"\n\n') + # base environment os.environ["ZEPHYR_BASE"] = str(ZEPHYR_BASE) os.environ["srctree"] = str(ZEPHYR_BASE) @@ -91,8 +136,11 @@ def kconfig_load(app: Sphinx) -> Tuple[kconfiglib.Kconfig, Dict[str, str]]: # include all archs and boards os.environ["ARCH_DIR"] = "arch" - os.environ["ARCH"] = "*" - os.environ["BOARD_DIR"] = "boards/*/*" + os.environ["ARCH"] = "[!v][!2]*" + os.environ["HWM_SCHEME"] = "v2" + + os.environ["BOARD"] = "boards" + os.environ["BOARD_DIR"] = str(Path(td) / "boards") # insert external Kconfigs to the environment module_paths = dict() diff --git a/doc/connectivity/bluetooth/autopts/autopts-win10.rst b/doc/connectivity/bluetooth/autopts/autopts-win10.rst index 54b609ef1fd11d..ff308261f4419f 100644 --- a/doc/connectivity/bluetooth/autopts/autopts-win10.rst +++ b/doc/connectivity/bluetooth/autopts/autopts-win10.rst @@ -116,7 +116,7 @@ Build the auto-pts tester app .. code-block:: - west build -p auto -b nrf52840dk_nrf52840 zephyr/tests/bluetooth/tester/ + west build -p auto -b nrf52840dk/nrf52840 zephyr/tests/bluetooth/tester/ You can display flashing options with: diff --git a/doc/develop/beyond-GSG.rst b/doc/develop/beyond-GSG.rst index 8f5361d8512a8a..8c965877a430c4 100644 --- a/doc/develop/beyond-GSG.rst +++ b/doc/develop/beyond-GSG.rst @@ -163,8 +163,8 @@ supported by a CMake file with content like this: # Variable foo_BOARD_ALIAS=bar replaces BOARD=foo with BOARD=bar and # sets BOARD_ALIAS=foo in the CMake cache. - set(pca10028_BOARD_ALIAS nrf51dk_nrf51422) - set(pca10056_BOARD_ALIAS nrf52840dk_nrf52840) + set(pca10028_BOARD_ALIAS nrf51dk/nrf51822) + set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) set(k64f_BOARD_ALIAS frdm_k64f) set(sltb004a_BOARD_ALIAS efr32mg_sltb004a) diff --git a/doc/develop/flash_debug/nordic_segger.rst b/doc/develop/flash_debug/nordic_segger.rst index 918d0051aa2d12..92e2c31d5fc46c 100644 --- a/doc/develop/flash_debug/nordic_segger.rst +++ b/doc/develop/flash_debug/nordic_segger.rst @@ -63,7 +63,7 @@ Where ```` is either 1 for nRF51-based boards or 2 for nRF52-based boards nrfjprog --program outdir//zephyr.hex -f nrf5 -Where: ```` is the board name you used in the BOARD directive when building (for example nrf52dk_nrf52832) +Where: ```` is the board name you used in the BOARD directive when building (for example nrf52dk/nrf52832) and ```` is either 1 for nRF51-based boards or 2 for nRF52-based boards * Reset and start Zephyr: diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst index c2974509ca8cff..39e68ba6a02bad 100644 --- a/doc/develop/getting_started/index.rst +++ b/doc/develop/getting_started/index.rst @@ -560,6 +560,17 @@ users. Users may also use the ``-p auto`` option, which will use heuristics to determine if a pristine build is required, such as when building another sample. +.. note:: + + A board may contain one or multiple SoCs, Also, each SoC may contain one or + more CPU clusters. + When building for such boards it is necessary to specify the SoC or CPU + cluster for which the sample must be built. + For example to build :zephyr:code-sample:`blinky` for the ``cpuapp`` core on + the :ref:`nRF5340DK ` the board must be provided as: + ``nrf5340dk/nrf5340/cpuapp``. Also read :ref:`board_and_identifiers` for more + details. + Flash the Sample **************** diff --git a/doc/develop/sca/sparse.rst b/doc/develop/sca/sparse.rst index 38b720d4448fa8..4af699fc34322b 100644 --- a/doc/develop/sca/sparse.rst +++ b/doc/develop/sca/sparse.rst @@ -23,4 +23,4 @@ called with a ``-DZEPHYR_SCA_VARIANT=sparse`` parameter, e.g. .. code-block:: shell - west build -d hello -b intel_adsp_cavs25 zephyr/samples/hello_world -- -DZEPHYR_SCA_VARIANT=sparse + west build -d hello -b intel_adsp/cavs25 zephyr/samples/hello_world -- -DZEPHYR_SCA_VARIANT=sparse diff --git a/doc/develop/test/coverage.rst b/doc/develop/test/coverage.rst index 60faffa1a90ff6..5c86adda1b3251 100644 --- a/doc/develop/test/coverage.rst +++ b/doc/develop/test/coverage.rst @@ -49,7 +49,7 @@ These steps will produce an HTML coverage report for a single application. 1. Build the code with CONFIG_COVERAGE=y. .. zephyr-app-commands:: - :board: mps2_an385 + :board: mps2/an385 :gen-args: -DCONFIG_COVERAGE=y -DCONFIG_COVERAGE_DUMP=y :goals: build :compact: diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst index faa8c475b2da45..f84fc73b99c6e7 100644 --- a/doc/develop/test/twister.rst +++ b/doc/develop/test/twister.rst @@ -839,7 +839,7 @@ In this case you can run twister with the following options: .. code-block:: bash scripts/twister --device-testing --device-serial-pty "script.py" \ - -p intel_adsp_cavs25 -T tests/kernel + -p intel_adsp/cavs25 -T tests/kernel .. group-tab:: Windows @@ -923,7 +923,7 @@ devices, for example: Any options marked as ``unknown`` need to be changed and set with the correct values, in the above example the platform names, the products and the runners need to be replaced with the correct values corresponding to the connected hardware. -In this example we are using a reel_board and an nrf52840dk_nrf52840: +In this example we are using a reel_board and an nrf52840dk/nrf52840: .. tabs:: @@ -940,7 +940,7 @@ In this example we are using a reel_board and an nrf52840dk_nrf52840: baud: 9600 - connected: true id: 000683759358 - platform: nrf52840dk_nrf52840 + platform: nrf52840dk/nrf52840 product: J-Link runner: nrfjprog serial: /dev/cu.usbmodem0006837593581 @@ -959,7 +959,7 @@ In this example we are using a reel_board and an nrf52840dk_nrf52840: baud: 9600 - connected: true id: 000683759358 - platform: nrf52840dk_nrf52840 + platform: nrf52840dk/nrf52840 product: J-Link runner: nrfjprog serial: COM2 @@ -1008,7 +1008,7 @@ hardware map: - connected: true id: None - platform: intel_adsp_cavs25 + platform: intel_adsp/cavs25 product: None runner: intel_adsp serial_pty: path/to/script.py @@ -1029,7 +1029,7 @@ work. It is equivalent to following west and twister commands. west flash --remote-host remote_host_ip_addr --key /path/to/key.pem - twister -p intel_adsp_cavs25 --device-testing --device-serial-pty script.py + twister -p intel_adsp/cavs25 --device-testing --device-serial-pty script.py --west-flash="--remote-host=remote_host_ip_addr,--key=/path/to/key.pem" .. group-tab:: Windows @@ -1092,12 +1092,12 @@ example: fixtures: - gpio_loopback id: 000683290670 - notes: An nrf5340dk_nrf5340 is detected as an nrf52840dk_nrf52840 with no serial + notes: An nrf5340dk/nrf5340 is detected as an nrf52840dk/nrf52840 with no serial port, and three serial ports with an unknown platform. The board id of the serial ports is not the same as the board id of the development kit. If you regenerate this file you will need to update serial to reference the third port, and platform - to nrf5340dk_nrf5340_cpuapp or another supported board target. - platform: nrf52840dk_nrf52840 + to nrf5340dk/nrf5340/cpuapp or another supported board target. + platform: nrf52840dk/nrf52840 product: J-Link runner: jlink serial: null diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst index 5be561aecb2517..c45b2a7bb5470a 100644 --- a/doc/hardware/porting/board_porting.rst +++ b/doc/hardware/porting/board_porting.rst @@ -8,17 +8,78 @@ directory* with various files in it. Files in the board directory inherit support for at least one SoC and all of its features. Therefore, Zephyr must support your :term:`SoC` as well. +.. _board_and_identifiers: + +Board and board identifiers +*************************** + +A board may be a physical piece of hardware or an emulated board. +Furthermore a board may contain one or multiple SoCs. Also, each SoC may contain +one or multiple CPU clusters. A CPU cluster refers to a group of CPU cores. +Only CPU cores of same architecture can be in the same cluster. In the case +where a physical SoC considers a CPU cluster to contain CPU cores of different +architectures then those must be modelled as multiple clusters, where all CPU +cores within a cluster is having the same architecture. +It is possible to have only a single CPU core within a CPU cluster. + +It's possible to define variants for dedicated use-cases. +Examples of such use-cases are: + +- Variant which enables non-secure builds for SoCs containing a security + processor. +- Variant enabling / changing the type of RAM used in by the build. + +A ``/`` is used as separator between the board name and the following: +SoC, CPU cluster, and variant identifiers. + +If a board contains only a single core SoC, then the SoC can be omitted when +building. + +Let's say there is a board named ``plank`` with a single-core SoC ``soc1``. +The board including the identifier is: ``plank/soc1``. + +As ``plank`` is a single SoC board, then the following is sufficient: ``plank`` +to use as board when building. + +If ``plank`` defines board variants, then those are identified by appending the +``/`` name after the SoC, for example to build for the ``foo`` variant, +use: ``plank/soc1/foo``, and if omitting the SoC use: ``plank//foo``. +Here the double ``//`` indicates to the build system that the SoC has been +omitted. + +So to build hello world for ``plank``, variant ``foo``, you can do: + +.. code-block:: console + + west build -b plank//foo samples/hello_world + +When using multi-core SoCs, the CPU cluster is identified after the SoC +identifier. + +If ``soc1`` above has two cores, ``first`` and ``second``, then those are +identified as: ``plank/soc1/first`` and ``plank/soc1/second``. + +And similar to before, if the board has only a single SoC, the SoC can be +omitted, that is ``plank//first`` and ``plank//second`` is an identical short +form. + +.. _hw_support_hierarchy: + Boards, SoCs, etc. ****************** Zephyr's hardware support hierarchy has these layers, from most to least specific: -- Board: a particular CPU instance and its peripherals in a concrete hardware - specification +- Board: a specific board which usually corresponds to a physical board. + A board may contain multiple SoCs. + A build targets a specific CPU cluster on a board which has multiple + CPUs, be these in different SOCs or in a SOC with multiple AMP CPU + clusters. - SoC: the exact system on a chip the board's CPU is part of - SoC series: a smaller group of tightly related SoCs - SoC family: a wider group of SoCs with similar characteristics +- CPU Cluster: a cluster of one or more CPU cores. - CPU core: a particular CPU in an architecture - Architecture: an instruction set architecture @@ -34,39 +95,26 @@ You can visualize the hierarchy like this: Here are some examples. Notice how the SoC series and family levels are not always used. -.. list-table:: - :header-rows: 1 - - * - Board - - SoC - - SoC series - - SoC family - - CPU core - - Architecture - * - :ref:`nrf52dk_nrf52832 ` - - nRF52832 - - nRF52 - - Nordic nRF5 - - Arm Cortex-M4 - - Arm - * - :ref:`frdm_k64f ` - - MK64F12 - - Kinetis K6x - - NXP Kinetis - - Arm Cortex-M4 - - Arm - * - :ref:`stm32h747i_disco ` - - STM32H747XI - - STM32H7 - - STMicro STM32 - - Arm Cortex-M7 - - Arm - * - :ref:`rv32m1_vega_ri5cy ` - - RV32M1 - - (Not used) - - (Not used) - - RI5CY - - RISC-V +.. table:: + + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | Board | Identifier | SoC | SoC Series | SoC family | CPU core | Architecture | + +============================================+=======================+=============+===============+===============+================+==============+ + | :ref:`nrf52dk ` | /nrf52832 | nRF52832 | nRF52 | Nordic nRF | Arm Cortex-M4 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`frdm_k64f ` | /mk64f12 | MK64F12 | Kinetis K6x | NXP Kinetis | Arm Cortex-M4 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`rv32m1_vega ` | /openisa_rv32m1/ri5cy | RV32M1 | (Not used) | (Not used) | RI5CY | RISC-V | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`nrf5340dk ` | /nrf5340/cpuapp | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | Arm | + | +-----------------------+-------------+---------------+---------------+----------------+--------------+ + | | /nrf5340/cpunet | nRF5340 | nRF53 | Nordic nRF | Arm Cortex-M33 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + | :ref:`mimx8mp_evk ` | /mimx8m/a53 | i.MX8M Plus | i.MXM8M A53 | NXP i.MX | Arm Cortex-A53 | Arm64 | + | +-----------------------+-------------+---------------+---------------+----------------+--------------+ + | | /mimx8m/m7 | i.MX8M Plus | i.MXM8MM M4 | NXP i.MX | Arm Cortex-M7 | Arm | + +--------------------------------------------+-----------------------+-------------+---------------+---------------+----------------+--------------+ + Make sure your SoC is supported ******************************* @@ -78,7 +126,7 @@ Start by making sure your SoC is supported by Zephyr. If it is, it's time to board documentation to find out for sure. - asking your SoC vendor -If you need to add SoC, CPU core, or even architecture support, this is the +If you need to add a SoC, CPU cluster, or even architecture support, this is the wrong page, but here is some general advice. Architecture @@ -107,7 +155,7 @@ Zephyr SoC support files are in architecture-specific subdirectories of When adding a new SoC family or series for a vendor that already has SoC support within Zephyr, please try to extract common functionality into shared files to avoid duplication. If there is no support for your vendor yet, you can -add it in a new directory ``zephyr/soc//``; please use +add it in a new directory ``zephyr/soc//``; please use self-explanatory directory names. .. _create-your-board-directory: @@ -123,52 +171,72 @@ You need to give your board a unique name. Run ``west boards`` for a list of names that are already taken, and pick something new. Let's say your board is called ``plank`` (please don't actually use that name). -Start by creating the board directory ``zephyr/boards//plank``, where -```` is your SoC's architecture subdirectory. (You don't have to put your +Start by creating the board directory ``zephyr/boards//plank``, where +```` is your vendor subdirectory. (You don't have to put your board directory in the zephyr repository, but it's the easiest way to get started. See :ref:`custom_board_definition` for documentation on moving your board directory to a separate repository once it's working.) +.. note:: + A ```` subdirectory is mandatory if contributing your board + to Zephyr, but if your board is placed in a local repo, then any folder + structure under ``/boards`` is permitted. + If the vendor is defined in the list in + :zephyr_file:`dts/bindings/vendor-prefixes.txt` then you must use + that vendor prefix as ````. ``others`` may be used as vendor prefix if + the vendor is not defined. + .. note:: The board directory name does not need to match the name of the board. Multiple boards can even defined be in one directory. - For example, for boards with multi-core SoC, a logical board might be created - for each core following the naming scheme `_`, with definitions - for all of these different boards defined inside the same directory. This and - similar schemes are common for upstream vendor boards. Your board directory should look like this: .. code-block:: none - boards//plank + boards//plank + ├── board.yml ├── board.cmake ├── CMakeLists.txt ├── doc │   ├── plank.png │   └── index.rst - ├── Kconfig.board + ├── Kconfig.plank ├── Kconfig.defconfig ├── plank_defconfig + ├── plank__defconfig ├── plank.dts + ├── plank_.dts └── plank.yaml Replace ``plank`` with your board's name, of course. The mandatory files are: -#. :file:`plank.dts`: a hardware description in :ref:`devicetree - ` format. This declares your SoC, connectors, and any - other hardware components such as LEDs, buttons, sensors, or communication - peripherals (USB, BLE controller, etc). +#. :file:`board.yml`: a YAML file describing the high-level meta data of the + boards such as the boards names, their SoCs, and variants. + CPU clusters for multi-core SoCs are not described in this file as they are + inherited from the SoC's YAML description. + +#. :file:`plank.dts` or :file:`plank_.dts`: a hardware description + in :ref:`devicetree ` format. This declares your SoC, connectors, + and any other hardware components such as LEDs, buttons, sensors, or + communication peripherals (USB, BLE controller, etc). + +#. :file:`Kconfig.plank`: the base software configuration for selecting SoC and + other board and SoC related settings. Kconfig settings outside of the board + and SoC tree must not be selected. To select general Zephyr Kconfig settings + the :file:`Kconfig` file must be used. -#. :file:`Kconfig.board`, :file:`Kconfig.defconfig`, :file:`plank_defconfig`: - software configuration in :ref:`kconfig` formats. This provides default - settings for software features and peripheral drivers. The optional files are: +- :file:`Kconfig`, :file:`Kconfig.defconfig` software configuration in + :ref:`kconfig` formats. This provides default settings for software features + and peripheral drivers. +- :file:`plank_defconfig` and :file:`plank__defconfig`: software + configuration in Kconfig ``.conf`` format. - :file:`board.cmake`: used for :ref:`flash-and-debug-support` - :file:`CMakeLists.txt`: if you need to add additional source files to your build. @@ -178,12 +246,70 @@ The optional files are: - :file:`plank.yaml`: a YAML file with miscellaneous metadata used by the :ref:`twister_script`. +Board identifiers of the form ``//`` are sanitized so +that ``/`` is replaced with ``_`` when used for filenames, for example: +``soc1/foo`` becomes ``soc1_foo`` when used in filenames. + +.. _board_description: + +Write your board YAML +********************* + +The board YAML file describes the board at a high level. +This includes the SoC, board variants, and board revisions. + +Detailed configurations, such as hardware description and configuration are done +in devicetree and Kconfig. + +The skeleton of the board YAML file is: + +.. code-block:: yaml + + board: + name: + vendor: + revision: + format: + default: + exact: + revisions: + - name: + - name: + ... + socs: + - name: + variants: + - name: + - name: + variants: + - name: + ... + - name: + ... + +It is possible to have multiple boards located in the board folder. +If multiple boards are placed in the same board folder, then the file +:file:`board.yml` must describe those in a list as: + +.. code-block:: yaml + + boards: + - name: + vendor: + ... + - name: + vendor: + ... + ... + + .. _default_board_configuration: Write your devicetree ********************* -The devicetree file :file:`boards//plank/plank.dts` describes your board +The devicetree file :file:`boards//plank/plank.dts` or +:file:`boards//plank/plank_.dts` describes your board hardware in the Devicetree Source (DTS) format (as usual, change ``plank`` to your board's name). If you're new to devicetree, see :ref:`devicetree-intro`. @@ -195,48 +321,59 @@ In general, :file:`plank.dts` should look like this: #include / { - model = "A human readable name"; - compatible = "yourcompany,plank"; - - chosen { - zephyr,console = &your_uart_console; - zephyr,sram = &your_memory_node; - /* other chosen settings for your hardware */ - }; - - /* - * Your board-specific hardware: buttons, LEDs, sensors, etc. - */ - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = < /* GPIO your LED is hooked up to */ >; - label = "LED 0"; - }; - /* ... other LEDs ... */ - }; - - buttons { - compatible = "gpio-keys"; - /* ... your button definitions ... */ - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; /* now you support the blinky sample! */ - /* other aliases go here */ - }; + model = "A human readable name"; + compatible = "yourcompany,plank"; + + chosen { + zephyr,console = &your_uart_console; + zephyr,sram = &your_memory_node; + /* other chosen settings for your hardware */ + }; + + /* + * Your board-specific hardware: buttons, LEDs, sensors, etc. + */ + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = < /* GPIO your LED is hooked up to */ >; + label = "LED 0"; + }; + /* ... other LEDs ... */ + }; + + buttons { + compatible = "gpio-keys"; + /* ... your button definitions ... */ + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; /* now you support the blinky sample! */ + /* other aliases go here */ + }; }; &some_peripheral_you_want_to_enable { /* like a GPIO or SPI controller */ - status = "okay"; + status = "okay"; }; &another_peripheral_you_want { - status = "okay"; + status = "okay"; }; +Only one ``.dts`` file will be used, and the most specific file which exists +will be used. + +This means that if both :file:`plank.dts` and :file:`plank_soc1_foo.dts` exist, +then when building for ``plank`` / ``plank/soc1``, then :file:`plank.dts` is +used. When building for ``plank//foo`` / ``plank/soc1/foo`` the +:file:`plank_soc1_foo.dts` is used. + +This allows board maintainers to write a base devicetree file for the board +or write specific devicetree files for a given board's SoC or variant. + If you're in a hurry, simple hardware can usually be supported by copy/paste followed by trial and error. If you want to understand details, you will need to read the rest of the devicetree documentation and the devicetree @@ -273,9 +410,9 @@ follows (with unimportant parts skipped): .. code-block:: devicetree can0: can@40024000 { - ... - status = "disabled"; - ... + ... + status = "disabled"; + ... }; It is up to the board :file:`.dts` or application overlay files to enable these @@ -289,8 +426,8 @@ controller and sets the bus speed: .. code-block:: devicetree &can0 { - status = "okay"; - bus-speed = <125000>; + status = "okay"; + bus-speed = <125000>; }; The ``&can0 { ... };`` syntax adds/overrides properties on the node with label @@ -300,6 +437,8 @@ Other examples of board-specific customization is pointing properties in ``aliases`` and ``chosen`` to the right nodes (see :ref:`dt-alias-chosen`), and making GPIO/pinmux assignments. +.. _board_kconfig_files: + Write Kconfig files ******************* @@ -310,33 +449,61 @@ application for it. Setting Kconfig configuration values is documented in detail in :ref:`setting_configuration_values`. -There are three mandatory Kconfig files in the board directory for a board -named ``plank``: +There is one mandatory Kconfig file in the board directory, and several optional +files for a board named ``plank``: .. code-block:: none - boards//plank - ├── Kconfig.board + boards//plank + ├── Kconfig + ├── Kconfig.plank ├── Kconfig.defconfig - └── plank_defconfig + ├── plank_defconfig + └── plank__defconfig + +:file:`Kconfig.plank` + A shared Kconfig file which can be sourced both in Zephyr Kconfig and sysbuild + Kconfig trees. -:file:`Kconfig.board` - Included by :zephyr_file:`boards/Kconfig` to include your board - in the list of options. + This file selects the SoC in the Kconfig tree and potential other SoC related + Kconfig settings. This file must not select anything outside the re-usable + Kconfig board and SoC trees. - This should at least contain a definition for a ``BOARD_PLANK`` option, - which looks something like this: + A :file:`Kconfig.plank` may look like this: .. code-block:: kconfig config BOARD_PLANK - bool "Plank board" - depends on SOC_SERIES_YOUR_SOC_SERIES_HERE - select SOC_PART_NUMBER_ABCDEFGH + select SOC_SOC1 + + The Kconfig symbols :kconfig:option:`BOARD_` and + :kconfig:option:`BOARD_` are constructed by the build + system, therefore no type shall be defined in above code snippet. + +:file:`Kconfig` + Included by :zephyr_file:`boards/Kconfig`. + + This file can add Kconfig settings which are specific to the current board. + + Not all boards have a :file:`Kconfig` file. + + A board specific setting should be defining a custom setting and usually with + a prompt, like this: + + .. code-block:: kconfig + + config BOARD_FEATURE + bool "Board specific feature" + + If the setting name is identical to an existing Kconfig setting in Zephyr and + only modifies the default value of said setting, then + :file:`Kconfig.defconfig` should be used instead. :file:`Kconfig.defconfig` Board-specific default values for Kconfig options. + Not all boards have a :file:`Kconfig.defconfig` file. + The entire file should be inside an ``if BOARD_PLANK`` / ``endif`` pair of lines, like this: @@ -347,35 +514,42 @@ named ``plank``: # Always set CONFIG_BOARD here. This isn't meant to be customized, # but is set as a "default" due to Kconfig language restrictions. config BOARD - default "plank" + default "plank" # Other options you want enabled by default go next. Examples: config FOO - default y + default y if NETWORKING config SOC_ETHERNET_DRIVER - default y + default y endif # NETWORKING endif # BOARD_PLANK -:file:`plank_defconfig` +:file:`plank_defconfig` / :file:`plank__defconfig` A Kconfig fragment that is merged as-is into the final build directory :file:`.config` whenever an application is compiled for your board. - You should at least select your board's SOC and do any mandatory settings for - your system clock, console, etc. The results are architecture-specific, but - typically look something like this: + If both the common :file:`plank_defconfig` file and one or more board + identifier specific :file:`plank__defconfig` files exist, then + all matching files will be used. + This allows you to place configuration which is common for all board SoCs, + CPU clusters, and board variants in the base :file:`plank_defconfig` and only + place the adjustments specific for a given SoC or board variant in the + :file:`plank__defconfig`. + + The ``_defconfig`` should contain mandatory settings for your system clock, + console, etc. The results are architecture-specific, but typically look + something like this: .. code-block:: cfg - CONFIG_SOC_${VENDOR_XYZ3000}=y # select your SoC CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000 # set up your clock, etc CONFIG_SERIAL=y -:file:`plank_x_y_z.conf` +:file:`plank_x_y_z_defconfig` / :file:`plank__x_y_z_defconfig` A Kconfig fragment that is merged as-is into the final build directory :file:`.config` whenever an application is compiled for your board revision ``x.y.z``. @@ -523,90 +697,37 @@ Multiple board revisions See :ref:`application_board_version` for basics on this feature from the user perspective. -To create a new board revision for the ``plank`` board, create these additional -files in the board folder: - -.. code-block:: none - - boards//plank - ├── plank_.conf # optional - ├── plank_.overlay # optional - └── revision.cmake - -When the user builds for board ``plank@``: +Board revisions are described in the ``revision`` entry of the +:file:`board.yml`. -- The optional Kconfig settings specified in the file - :file:`plank_.conf` will be merged into the board's default Kconfig - configuration. +.. code-block:: yaml -- The optional devicetree overlay :file:`plank_.overlay` will be added - to the common :file:`plank.dts` devicetree file + board: + revision: + format: + default: + exact: + revisions: + - name: + - name: -- The :file:`revision.cmake` file controls how the Zephyr build system matches - the ``@`` string specified by the user when building an - application for the board. +Zephyr natively supports the following revision formats: -Currently, ```` can be either a numeric ``MAJOR.MINOR.PATCH`` style -revision like ``1.5.0``, an integer number like ``1``, or single letter like -``A``, ``B``, etc. Zephyr provides a CMake board extension function, -``board_check_revision()``, to make it easy to match either style from -:file:`revision.cmake`. +- ``major.minor.patch``: match a three digit revision, such as ``1.2.3``. +- ``number``: matches integer revisions +- ``letter``: matches single letter revisions from ``A`` to ``Z`` only -Valid board revisions may be specified as arguments to the -``board_check_revision()`` function, like: - -.. code-block:: cmake - - board_check_revision(FORMAT MAJOR.MINOR.PATCH - VALID_REVISIONS 0.1.0 0.3.0 ... - ) - -.. note:: - ``VALID_REVISIONS`` can be omitted if all valid revisions have specific - Kconfig fragments, such as ``_0_1_0.conf``, ``_0_3_0.conf``. - This allows you to just place Kconfig revision fragments in the board - folder and not have to keep the corresponding ``VALID_REVISIONS`` in sync. - -The following sections describe how to support these styles of revision -numbers. - -MAJOR.MINOR.PATCH revisions -=========================== - -Let's say you want to add support for revisions ``0.5.0``, ``1.0.0``, and -``1.5.0`` of the ``plank`` board with both Kconfig fragments and devicetree -overlays. Create :file:`revision.cmake` with -``board_check_revision(FORMAT MAJOR.MINOR.PATCH)``, and create the following -additional files in the board directory: - -.. code-block:: none - - boards//plank - ├── plank_0_5_0.conf - ├── plank_0_5_0.overlay - ├── plank_1_0_0.conf - ├── plank_1_0_0.overlay - ├── plank_1_5_0.conf - ├── plank_1_5_0.overlay - └── revision.cmake - -Notice how the board files have changed periods (".") in the revision number to -underscores ("_"). +.. _board_fuzzy_revision_matching: Fuzzy revision matching ------------------------ - -To support "fuzzy" ``MAJOR.MINOR.PATCH`` revision matching for the ``plank`` -board, use the following code in :file:`revision.cmake`: - -.. code-block:: cmake +======================= - board_check_revision(FORMAT MAJOR.MINOR.PATCH) +Fuzzy revision matching is enabled per default. If the user selects a revision between those available, the closest revision number that is not larger than the user's choice is used. For example, if the -user builds for ``plank@0.7.0``, the build system will target revision -``0.5.0``. +board ``plank`` defines revisions ``0.5.0``, and ``1.5.0`` and the user builds +for ``plank@0.7.0``, the build system will target revision ``0.5.0``. The build system will print this at CMake configuration time: @@ -617,149 +738,107 @@ The build system will print this at CMake configuration time: This allows you to only create revision configuration files for board revision numbers that introduce incompatible changes. -Any revision less than the minimum defined will be treated as an error. - -You may use ``0.0.0`` as a minimum revision to build for by creating the file -:file:`plank_0_0_0.conf` in the board directory. This will be used for any -revision lower than ``0.5.0``, for example if the user builds for -``plank@0.1.0``. +Similar for ``letter`` where revision ``A``, ``D``, and ``F`` could be defined +and the user builds for ``plank@E``, the build system will target revision ``D`` +. Exact revision matching ------------------------ - -Alternatively, the ``EXACT`` keyword can be given to ``board_check_revision()`` -in :file:`revision.cmake` to allow exact matches only, like this: +======================= -.. code-block:: cmake +Exact revision matching is enabled when ``exact: true`` is specified in the +revision section in :file:`board.yml`. - board_check_revision(FORMAT MAJOR.MINOR.PATCH EXACT) - -With this :file:`revision.cmake`, building for ``plank@0.7.0`` in the above -example will result in the following error message: +When exact is defined then building for ``plank@0.7.0`` in the above example +will result in the following error message: .. code-block:: console Board revision `0.7.0` not found. Please specify a valid board revision. -Letter revision matching -======================== +Board revision configuration adjustment +======================================= -Let's say instead that you need to support revisions ``A``, ``B``, and ``C`` of -the ``plank`` board. Create the following additional files in the board -directory: +When the user builds for board ``plank@`` it is possible to make +adjustments to the board's normal configuration. -.. code-block:: none +As described in the :ref:`default_board_configuration` and +:ref:`board_kconfig_files` sections the board default configuration is created +from the files :file:`.dts` / :file:`_.dts` and +:file:`_defconfig` / :file:`__defconfig`. +When building for a specific board revision, the above files are used as a +starting point and the following board files will be used in addition: - boards//plank - ├── plank_A.conf - ├── plank_A.overlay - ├── plank_B.conf - ├── plank_B.overlay - ├── plank_C.conf - ├── plank_C.overlay - └── revision.cmake +- :file:`___defconfig`: a specific revision + defconfig which is only used for the board and SOC / variants identified by + ``_``. -And add the following to :file:`revision.cmake`: +- :file:`__defconfig`: a specific revision defconfig which is + used for the board regardless of the SOC / variants. -.. code-block:: cmake +- :file:`__.overlay`: a specific revision dts + overlay which is only used for the board and SOC / variants identified by + ``_``. - board_check_revision(FORMAT LETTER) +- :file:`_.overlay`: a specific revision dts overlay which is + used for the board regardless of the SOC / variants. -Number revision matching -======================== +This split allows boards with multiple SoCs, multi-core SoCs, or variants to +place common revision adjustments which apply to all SoCs and variants in a +single file, while still providing the ability to place SoC or variant specific +adjustments in a dedicated revision file. -Let's say instead that you need to support revisions ``1``, ``2``, and ``3`` of -the ``plank`` board. Create the following additional files in the board -directory: +Using the ``plank`` board from previous sections, then we could have the following +revision adjustments: .. code-block:: none - boards//plank - ├── plank_1.conf - ├── plank_1.overlay - ├── plank_2.conf - ├── plank_2.overlay - ├── plank_3.conf - ├── plank_3.overlay - └── revision.cmake + boards/zephyr/plank + ├── plank_0_5_0_defconfig # Kconfig adjustment for all plank board identifiers on revision 0.5.0 + ├── plank_0_5_0.overlay # DTS overlay for all plank board identifiers on revision 0.5.0 + └── plank_soc1_foo_1_5_0_defconfig # Kconfig adjustment for plank board when building for soc1 variant foo on revision 1.5.0 -And add the following to :file:`revision.cmake`: +Custom revision.cmake files +*************************** -.. code-block:: cmake +Some boards may not use board revisions supported natively by Zephyr. +For example string revisions. - board_check_revision(FORMAT NUMBER) +One reason why Zephyr doesn't support string revisions is that strings can take +many forms and it's not always clear if the given strings are just strings, such +as ``blue``, ``green``, ``red``, etc. or if they provide an order which can be +matched against higher or lower revisions, such as ``alpha``, ``beta```, +``gamma``. -board_check_revision() details -============================== +Due to the sheer number of possibilities with strings, including the possibility +of doing regex matches internally, then string revisions must be done using +``custom`` revision type. -.. code-block:: cmake +To indicate to the build system that ``custom`` revisions are used, the format +field in the ``revision`` section of the :file:`board.yml` must be written as: - board_check_revision(FORMAT - [OPTIONAL EXACT] - [DEFAULT_REVISION ] - [HIGHEST_REVISION ] - [VALID_REVISIONS [ ...]] - ) - -This function supports the following arguments: - -* ``FORMAT LETTER``: matches single letter revisions from ``A`` to ``Z`` only -* ``FORMAT NUMBER``: matches integer revisions -* ``FORMAT MAJOR.MINOR.PATCH``: matches exactly three digits. The command line - allows for loose typing, that is ``-DBOARD=@1`` and - ``-DBOARD=@1.0`` will be handled as ``-DBOARD=@1.0.0``. - Kconfig fragment and devicetree overlay files must use full numbering to avoid - ambiguity, so only :file:`_1_0_0.conf` and - :file:`_1_0_0.overlay` are allowed. - -* ``OPTIONAL``: if given, a revision is not required to be specified. - If the revision is not supplied, the base board is used with no overlays. - Can be combined with ``EXACT``, in which case providing the revision is - optional, but if given the ``EXACT`` rules apply. Mutually exclusive with - ``DEFAULT_REVISION``. - -* ``EXACT``: if given, the revision is required to be an exact match. - Otherwise, the closest matching revision not greater than the user's choice - will be selected. - -* ``DEFAULT_REVISION ``: if given, ```` is the default - revision to use when user has not selected a revision number. If not given, - the build system prints an error when the user does not specify a board - revision. - -* ``HIGHEST_REVISION``: if given, specifies the highest valid revision for a - board. This can be used to ensure that a newer board cannot be used with an - older Zephyr. For example, if the current board directory supports revisions - 0.x.0-0.99.99 and 1.0.0-1.99.99, and it is expected that the implementation - will not work with board revision 2.0.0, then giving ``HIGHEST_REVISION - 1.99.99`` causes an error if the user builds using ``@2.0.0``. - -* ``VALID_REVISIONS``: if given, specifies a list of revisions that are valid - for this board. If this argument is not given, then each Kconfig fragment of - the form ``_.conf`` in the board folder will be used as a - valid revision for the board. - -.. _porting_custom_board_revisions: +.. code-block:: yaml -Custom revision.cmake files -*************************** + board: + revision: + format: custom + +When using custom revisions then a :file:`revision.cmake` must be created in the +board directory. -Some boards may not use board revisions supported by -``board_check_revision()``. To support revisions of any type, the file -:file:`revision.cmake` can implement custom revision matching without calling -``board_check_revision()``. +The :file:`revision.cmake` will be included by the build system when building +for the board and it is the responsibility of the file to validate the revision +specified by the user. + +The :makevar:`BOARD_REVISION` variable holds the revision value specified by the +user. To signal to the build system that it should use a different revision than the one specified by the user, :file:`revision.cmake` can set the variable ``ACTIVE_BOARD_REVISION`` to the revision to use instead. The corresponding Kconfig files and devicetree overlays must be named -:file:`_.conf` and +:file:`__defconfig` and :file:`_.overlay`. -For example, if the user builds for ``plank@zero``, :file:`revision.cmake` can -set ``ACTIVE_BOARD_REVISION`` to ``one`` to use the files -:file:`plank_one.conf` and :file:`plank_one.overlay`. - .. _contributing-your-board: Contributing your board diff --git a/doc/releases/migration-guide-3.7.rst b/doc/releases/migration-guide-3.7.rst index f2867bf5a4905e..3fa482458d3464 100644 --- a/doc/releases/migration-guide-3.7.rst +++ b/doc/releases/migration-guide-3.7.rst @@ -18,6 +18,12 @@ the :ref:`release notes`. Build System ************ +* Completely overhauled the way SoCs and boards are defined. This requires all + out-of-tree SoCs and boards to be ported to the new model. See the + :ref:`board_porting_guide` for more detailed information. + * Pull Request: https://github.com/zephyrproject-rtos/zephyr/pull/69607 + * Issue: https://github.com/zephyrproject-rtos/zephyr/issues/51831 + Kernel ****** diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst index d97f69bf628841..6ad59d5988f679 100644 --- a/doc/releases/release-notes-3.7.rst +++ b/doc/releases/release-notes-3.7.rst @@ -9,6 +9,10 @@ We are pleased to announce the release of Zephyr version 3.7.0. Major enhancements with this release include: +* A new, completely overhauled hardware model has been introduced. This changes + the way both SoCs and boards are named, defined and constructed in Zephyr. + Additional information can be found in the :ref:`board_porting_guide`. + An overview of the changes required or recommended when migrating your application from Zephyr v3.6.0 to Zephyr v3.7.0 can be found in the separate :ref:`migration guide`. diff --git a/doc/services/device_mgmt/mcumgr.rst b/doc/services/device_mgmt/mcumgr.rst index 0b21ce0771a323..6d4d575baa1733 100644 --- a/doc/services/device_mgmt/mcumgr.rst +++ b/doc/services/device_mgmt/mcumgr.rst @@ -319,7 +319,7 @@ On boards where a J-Link OB is present which has both CDC and MSC (virtual Mass Storage Device, also known as drag-and-drop) support, the MSD functionality can prevent MCUmgr commands over the CDC UART port from working due to how USB endpoints are configured in the J-Link firmware (for example on the -:ref:`Nordic nrf52840dk_nrf52840 board `) because of +:ref:`Nordic nrf52840dk/nrf52840 board `) because of limiting the maximum packet size (most likely to occur when using image management commands for updating firmware). This issue can be resolved by disabling MSD functionality on the J-Link device, follow the diff --git a/doc/services/tfm/requirements.rst b/doc/services/tfm/requirements.rst index 58f573821e43bb..13795986875bef 100644 --- a/doc/services/tfm/requirements.rst +++ b/doc/services/tfm/requirements.rst @@ -13,19 +13,19 @@ The following are some of the boards that can be used with TF-M: * - :ref:`mps3_an547_board` - ``mps3_an547_ns`` (qemu supported) * - :ref:`bl5340_dvk` - - ``bl5340_dvk_cpuapp_ns`` + - ``bl5340_dvk/nrf5340/cpuapp/ns`` * - :ref:`lpcxpresso55s69` - ``lpcxpresso55s69_ns`` * - :ref:`nrf9160dk_nrf9160` - - ``nrf9160dk_nrf9160_ns`` + - ``nrf9160dk/nrf9160/ns`` * - :ref:`nrf5340dk_nrf5340` - - ``nrf5340dk_nrf5340_cpuapp_ns`` + - ``nrf5340dk/nrf5340/cpuapp/ns`` * - :ref:`b_u585i_iot02a_board` - - ``b_u585i_iot02a_ns`` + - ``b_u585i_iot02a/stm32u585xx/ns`` * - :ref:`nucleo_l552ze_q_board` - - ``nucleo_l552ze_q_ns`` + - ``nucleo_l552ze_q/stm32l552xx/ns`` * - :ref:`stm32l562e_dk_board` - - ``stm32l562e_dk_ns`` + - ``stm32l562e_dk/stm32l562xx/ns`` * - :ref:`v2m_musca_b1_board` - ``v2m_musca_b1_ns`` * - :ref:`v2m_musca_s1_board` diff --git a/drivers/can/Kconfig.mcux b/drivers/can/Kconfig.mcux index 7df67684e8a7c7..e995a19ab6f1a3 100644 --- a/drivers/can/Kconfig.mcux +++ b/drivers/can/Kconfig.mcux @@ -31,9 +31,9 @@ config CAN_MCUX_FLEXCAN_WAIT_TIMEOUT config CAN_MAX_MB int "Maximum number of message buffers for concurrent active instances" default 16 - depends on SOC_SERIES_S32K3XX || SOC_SERIES_S32K1XX - range 1 96 if SOC_SERIES_S32K3XX - range 1 32 if SOC_SERIES_S32K1XX && !SOC_S32K142W && !SOC_S32K144W + depends on SOC_SERIES_S32K3 || SOC_SERIES_S32K1 + range 1 96 if SOC_SERIES_S32K3 + range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W range 1 64 if SOC_S32K142W || SOC_S32K144W help Defines maximum number of message buffers for concurrent active instances. @@ -42,10 +42,10 @@ config CAN_MAX_FILTER int "Maximum number of concurrent active RX filters" default 5 range 1 15 if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_KINETIS_K6X - range 1 13 if SOC_SERIES_IMX_RT && CAN_MCUX_FLEXCAN_FD - range 1 63 if SOC_SERIES_IMX_RT - range 1 96 if SOC_SERIES_S32K3XX - range 1 32 if SOC_SERIES_S32K1XX && !SOC_S32K142W && !SOC_S32K144W + range 1 13 if (SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX) && CAN_MCUX_FLEXCAN_FD + range 1 63 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + range 1 96 if SOC_SERIES_S32K3 + range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W range 1 64 if SOC_S32K142W || SOC_S32K144W help Defines maximum number of concurrent active RX filters diff --git a/drivers/clock_control/Kconfig.rcar b/drivers/clock_control/Kconfig.rcar index 0caa072355456c..2947c3da6f4541 100644 --- a/drivers/clock_control/Kconfig.rcar +++ b/drivers/clock_control/Kconfig.rcar @@ -4,6 +4,6 @@ config CLOCK_CONTROL_RCAR_CPG_MSSR bool "RCar CPG MSSR driver" default y - depends on SOC_FAMILY_RCAR + depends on SOC_FAMILY_RENESAS_RCAR help Enable support for Renesas RCar CPG MSSR driver. diff --git a/drivers/clock_control/Kconfig.smartbond b/drivers/clock_control/Kconfig.smartbond index a8e2d2f86fc79f..d20907c60018cf 100644 --- a/drivers/clock_control/Kconfig.smartbond +++ b/drivers/clock_control/Kconfig.smartbond @@ -5,6 +5,6 @@ config CLOCK_CONTROL_SMARTBOND bool "Smartbond Clock Control" - depends on SOC_FAMILY_SMARTBOND + depends on SOC_FAMILY_RENESAS_SMARTBOND help Enable driver for Clock Control subsystem found in SmartBond diff --git a/drivers/clock_control/clock_control_mchp_xec.c b/drivers/clock_control/clock_control_mchp_xec.c index ae79ae1b416558..11b0b54ac41fc1 100644 --- a/drivers/clock_control/clock_control_mchp_xec.c +++ b/drivers/clock_control/clock_control_mchp_xec.c @@ -122,7 +122,7 @@ struct pcr_hw_regs { #define XEC_CC_PCR_CLK32K_SRC_PIN 2 #define XEC_CC_PCR_CLK32K_SRC_OFF 3 -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX #define XEC_CC_PCR3_CRYPTO_MASK (BIT(26) | BIT(27) | BIT(28)) #else #define XEC_CC_PCR3_CRYPTO_MASK BIT(26) @@ -263,7 +263,7 @@ static int periph_clk_src_using_pin(enum periph_clk32k_src src) } } -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX /* MEC15xx uses the same 32KHz source for both PLL and Peripheral 32K clock domains. * We ignore the peripheral clock source. * If XTAL is selected (parallel) or single-ended the external 32KHz MUST stay on @@ -915,7 +915,7 @@ static inline int xec_clock_control_off(const struct device *dev, */ static uint32_t get_turbo_clock(const struct device *dev) { -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX ARG_UNUSED(dev); return MHZ(48); @@ -1079,7 +1079,7 @@ const struct xec_pcr_config pcr_xec_config = { (uint16_t)DT_INST_PROP_OR(0, pll_lock_timeout_ms, XEC_CC_DFLT_PLL_LOCK_WAIT_MS), .period_min = (uint16_t)DT_INST_PROP_OR(0, clk32kmon_period_min, CNT32K_TMIN), .period_max = (uint16_t)DT_INST_PROP_OR(0, clk32kmon_period_max, CNT32K_TMAX), - .core_clk_div = (uint8_t)DT_INST_PROP_OR(0, core_clk_div, CONFIG_SOC_MEC172X_PROC_CLK_DIV), + .core_clk_div = (uint8_t)DT_INST_PROP_OR(0, core_clk_div, CONFIG_SOC_MEC_PROC_CLK_DIV), .xtal_se = (uint8_t)DT_INST_PROP_OR(0, xtal_single_ended, 0), .max_dc_va = (uint8_t)DT_INST_PROP_OR(0, clk32kmon_duty_cycle_var_max, CNT32K_DUTY_MAX), .min_valid = (uint8_t)DT_INST_PROP_OR(0, clk32kmon_valid_min, CNT32K_VAL_MIN), diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c index 6245788961c86a..14959446d898d1 100644 --- a/drivers/clock_control/clock_control_mcux_ccm.c +++ b/drivers/clock_control/clock_control_mcux_ccm.c @@ -353,7 +353,7 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev, case IMX_CCM_FLEXSPI_CLK: __fallthrough; case IMX_CCM_FLEXSPI2_CLK: -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) /* The SOC is using the FlexSPI for XIP. Therefore, * the FlexSPI itself must be managed within the function, * which is SOC specific. diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c index c99741a78f2f48..a30a3b934914b7 100644 --- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c +++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c @@ -115,7 +115,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, break; #endif -#if defined(CONFIG_SOC_MIMX93_A55) && defined(CONFIG_DAI_NXP_SAI) +#if defined(CONFIG_SOC_MIMX9352_A55) && defined(CONFIG_DAI_NXP_SAI) case IMX_CCM_SAI1_CLK: case IMX_CCM_SAI2_CLK: case IMX_CCM_SAI3_CLK: @@ -144,7 +144,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev, default: return -EINVAL; } -#ifdef CONFIG_SOC_MIMX93_A55 +#ifdef CONFIG_SOC_MIMX9352_A55 *rate = CLOCK_GetIpFreq(clock_root); #else *rate = CLOCK_GetRootClockFreq(clock_root); @@ -173,7 +173,7 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev, case IMX_CCM_FLEXSPI_CLK: __fallthrough; case IMX_CCM_FLEXSPI2_CLK: -#if defined(CONFIG_SOC_SERIES_IMX_RT11XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) +#if defined(CONFIG_SOC_SERIES_IMXRT11XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI) /* The SOC is using the FlexSPI for XIP. Therefore, * the FlexSPI itself must be managed within the function, * which is SOC specific. diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index a0a7db57d2813b..5386b41ed04133 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -27,7 +27,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, if ((uint32_t)sub_system == MCUX_MRT_CLK) { #if defined(CONFIG_SOC_FAMILY_LPC) CLOCK_EnableClock(kCLOCK_Mrt); -#elif defined(CONFIG_SOC_FAMILY_IMX) +#elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT) CLOCK_EnableClock(kCLOCK_Mrt0); #endif } diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c index 9d76004c92fdf4..871b1d50a3acd7 100644 --- a/drivers/clock_control/clock_stm32_ll_h7.c +++ b/drivers/clock_control/clock_stm32_ll_h7.c @@ -90,8 +90,8 @@ /* Datasheet maximum frequency definitions */ #if defined(CONFIG_SOC_STM32H743XX) ||\ - defined(CONFIG_SOC_STM32H745XX) ||\ - defined(CONFIG_SOC_STM32H747XX) ||\ + defined(CONFIG_SOC_STM32H745XX_M7) || defined(CONFIG_SOC_STM32H745XX_M4) ||\ + defined(CONFIG_SOC_STM32H747XX_M7) || defined(CONFIG_SOC_STM32H747XX_M4) ||\ defined(CONFIG_SOC_STM32H750XX) ||\ defined(CONFIG_SOC_STM32H753XX) /* All h7 SoC with maximum 480MHz SYSCLK */ diff --git a/drivers/counter/counter_cmos.c b/drivers/counter/counter_cmos.c index 3edd718b9fecd9..00645bc71b0c63 100644 --- a/drivers/counter/counter_cmos.c +++ b/drivers/counter/counter_cmos.c @@ -11,11 +11,12 @@ * crossing clock domains (no pun intended). Use accordingly. */ -#define DT_DRV_COMPAT motorola_mc146818 - +#include #include #include -#include +#include + +#define DT_DRV_COMPAT motorola_mc146818 /* The "CMOS" device is accessed via an address latch and data port. */ diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c index 3da5fb8c538cf1..f65c554cf989ac 100644 --- a/drivers/dai/intel/dmic/dmic.c +++ b/drivers/dai/intel/dmic/dmic.c @@ -570,7 +570,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic) dai_dmic_start_fifo_packers(dmic, dmic->dai_config_params.dai_index); for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, CIC_CONTROL_SOFT_RESET, 0); @@ -621,7 +621,7 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic) FIELD_PREP(FIR_CONTROL_START, start_fir)); } -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Clear soft reset for all/used PDM controllers. This should * start capture in sync. */ diff --git a/drivers/dai/intel/dmic/dmic_nhlt.c b/drivers/dai/intel/dmic/dmic_nhlt.c index 3d803da33b9cc1..c7fe48e1432da7 100644 --- a/drivers/dai/intel/dmic/dmic_nhlt.c +++ b/drivers/dai/intel/dmic/dmic_nhlt.c @@ -175,7 +175,7 @@ static int dai_nhlt_update_rate(struct dai_intel_dmic *dmic, const int clock_sou return 0; } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE static int dai_ipm_source_to_enable(struct dai_intel_dmic *dmic, int *count, int pdm_count, int stereo, int source_pdm) @@ -426,7 +426,7 @@ static inline int dai_dmic_set_clock(const struct dai_intel_dmic *dmic, const ui static int print_outcontrol(uint32_t val) { int bf1, bf2, bf3, bf4, bf5, bf6, bf7, bf8; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE int bf9, bf10, bf11, bf12, bf13; #endif uint32_t ref; @@ -447,7 +447,7 @@ static int print_outcontrol(uint32_t val) return -EINVAL; } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf9 = FIELD_GET(OUTCONTROL_IPM_SOURCE_1, val); bf10 = FIELD_GET(OUTCONTROL_IPM_SOURCE_2, val); bf11 = FIELD_GET(OUTCONTROL_IPM_SOURCE_3, val); @@ -487,7 +487,7 @@ static void print_cic_control(uint32_t val) bf4 = FIELD_GET(CIC_CONTROL_MIC_B_POLARITY, val); bf5 = FIELD_GET(CIC_CONTROL_MIC_A_POLARITY, val); bf6 = FIELD_GET(CIC_CONTROL_MIC_MUTE, val); -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf7 = FIELD_GET(CIC_CONTROL_STEREO_MODE, val); #else bf7 = -1; @@ -503,7 +503,7 @@ static void print_cic_control(uint32_t val) FIELD_PREP(CIC_CONTROL_MIC_B_POLARITY, bf4) | FIELD_PREP(CIC_CONTROL_MIC_A_POLARITY, bf5) | FIELD_PREP(CIC_CONTROL_MIC_MUTE, bf6) -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE | FIELD_PREP(CIC_CONTROL_STEREO_MODE, bf7) #endif ; @@ -520,7 +520,7 @@ static void print_fir_control(uint32_t val) bf1 = FIELD_GET(FIR_CONTROL_START, val); bf2 = FIELD_GET(FIR_CONTROL_ARRAY_START_EN, val); -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf3 = FIELD_GET(FIR_CONTROL_PERIODIC_START_EN, val); #else bf3 = -1; @@ -534,7 +534,7 @@ static void print_fir_control(uint32_t val) LOG_DBG(" dccomp=%d, mute=%d, stereo=%d", bf4, bf5, bf6); ref = FIELD_PREP(FIR_CONTROL_START, bf1) | FIELD_PREP(FIR_CONTROL_ARRAY_START_EN, bf2) | -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE FIELD_PREP(FIR_CONTROL_PERIODIC_START_EN, bf3) | #endif FIELD_PREP(FIR_CONTROL_DCCOMP, bf4) | @@ -561,7 +561,7 @@ static void print_pdm_ctrl(const struct nhlt_pdm_ctrl_cfg *pdm_cfg) val = pdm_cfg->mic_control; -#ifndef CONFIG_SOC_SERIES_INTEL_ACE +#ifndef CONFIG_SOC_SERIES_INTEL_ADSP_ACE bf1 = FIELD_GET(MIC_CONTROL_PDM_SKEW, val); #else bf1 = -1; @@ -797,7 +797,7 @@ int dai_dmic_set_config_nhlt(struct dai_intel_dmic *dmic, const void *bespoke_cf } } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ret = dai_nhlt_dmic_dai_params_get(dmic, dmic_cfg->clock_source); #else ret = dai_nhlt_dmic_dai_params_get(dmic); diff --git a/drivers/dai/intel/ssp/Kconfig.ssp b/drivers/dai/intel/ssp/Kconfig.ssp index c44d4c4ec23810..adb88e7645bd8f 100644 --- a/drivers/dai/intel/ssp/Kconfig.ssp +++ b/drivers/dai/intel/ssp/Kconfig.ssp @@ -15,7 +15,7 @@ config DAI_INTEL_SSP config DAI_SSP_HAS_POWER_CONTROL bool "DAI ssp pm_runtime en/dis ssp power" - default y if SOC_SERIES_INTEL_ACE + default y if SOC_SERIES_INTEL_ADSP_ACE depends on DAI_INTEL_SSP if DAI_INTEL_SSP diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c index 682077a6d73d72..447a31c235f872 100644 --- a/drivers/dai/intel/ssp/ssp.c +++ b/drivers/dai/intel/ssp/ssp.c @@ -1607,7 +1607,7 @@ static int dai_ssp_check_aux_data(struct ssp_intel_aux_tlv *aux_tlv, int aux_len size = sizeof(struct ssp_intel_ext_ctl); break; case SSP_LINK_CLK_SOURCE: -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE size = sizeof(struct ssp_intel_link_ctl); break; #else @@ -1642,7 +1642,7 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con struct ssp_intel_node_ctl *node; struct ssp_intel_sync_ctl *sync; struct ssp_intel_ext_ctl *ext; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE struct ssp_intel_link_ctl *link; #endif uint8_t *aux_ptr; @@ -1698,7 +1698,7 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con LOG_INF("ext ext_data %u", ext->ext_data); break; case SSP_LINK_CLK_SOURCE: -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE link = (struct ssp_intel_link_ctl *)&aux_tlv->val; #if CONFIG_SOC_INTEL_ACE15_MTPM diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h index 0d53c0c6159825..5a187730dd538b 100644 --- a/drivers/dai/intel/ssp/ssp.h +++ b/drivers/dai/intel/ssp/ssp.h @@ -236,7 +236,7 @@ #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /** \brief Offset of MCLK Divider Control Register. */ #define MN_MDIVCTRL 0x100 diff --git a/drivers/disk/nvme/nvme_controller.c b/drivers/disk/nvme/nvme_controller.c index 699df325add4d8..e58a1baa7346eb 100644 --- a/drivers/disk/nvme/nvme_controller.c +++ b/drivers/disk/nvme/nvme_controller.c @@ -13,7 +13,6 @@ LOG_MODULE_REGISTER(nvme, CONFIG_NVME_LOG_LEVEL); #include -#include #include #include diff --git a/drivers/dma/Kconfig.intel_adsp_gpdma b/drivers/dma/Kconfig.intel_adsp_gpdma index 4e26ca5d93b950..9fa7f3baed5ddc 100644 --- a/drivers/dma/Kconfig.intel_adsp_gpdma +++ b/drivers/dma/Kconfig.intel_adsp_gpdma @@ -21,7 +21,7 @@ config DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP config DMA_INTEL_ADSP_GPDMA_HAS_LLP bool "Intel ADSP GPDMA Linear Link Position Feature" - default y if SOC_SERIES_INTEL_ACE + default y if SOC_SERIES_INTEL_ADSP_ACE help Intel ADSP GPDMA may optionally have a linear link position feature. diff --git a/drivers/dma/Kconfig.mcux_edma b/drivers/dma/Kconfig.mcux_edma index d1e513e3c136fb..6abf1cba489f0f 100644 --- a/drivers/dma/Kconfig.mcux_edma +++ b/drivers/dma/Kconfig.mcux_edma @@ -28,10 +28,10 @@ config DMA_TCD_QUEUE_SIZE config DMA_MCUX_TEST_SLOT_START int "test slot start num" - depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3XX) + depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3) default 58 if SOC_SERIES_KINETIS_K6X default 60 if SOC_SERIES_KINETIS_KE1XF - default 62 if SOC_SERIES_S32K3XX + default 62 if SOC_SERIES_S32K3 help test slot start num diff --git a/drivers/dma/dma_intel_adsp_gpdma.c b/drivers/dma/dma_intel_adsp_gpdma.c index e2927471050198..5e3850244d9b2d 100644 --- a/drivers/dma/dma_intel_adsp_gpdma.c +++ b/drivers/dma/dma_intel_adsp_gpdma.c @@ -162,7 +162,7 @@ static int intel_adsp_gpdma_config(const struct device *dev, uint32_t channel, static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel) { int ret = 0; -#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE +#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE bool first_use = false; enum pm_device_state state; @@ -187,7 +187,7 @@ static int intel_adsp_gpdma_start(const struct device *dev, uint32_t channel) intel_adsp_gpdma_llp_disable(dev, channel); } -#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE +#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Device usage is counted by the calls of dw_dma_start and dw_dma_stop. For the first use, * we need to make sure that the pm_device_runtime_get and pm_device_runtime_put functions * calls are balanced. @@ -246,7 +246,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev) uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val; - if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE)) { + if (IS_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)) { val = sys_read32(reg) | GPDMA_CTL_DCGD; } else { val = GPDMA_CTL_FDCGB; @@ -258,7 +258,7 @@ static void intel_adsp_gpdma_clock_enable(const struct device *dev) #ifdef CONFIG_PM_DEVICE static void intel_adsp_gpdma_clock_disable(const struct device *dev) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val = sys_read32(reg) & ~GPDMA_CTL_DCGD; @@ -271,7 +271,7 @@ static void intel_adsp_gpdma_clock_disable(const struct device *dev) static void intel_adsp_gpdma_claim_ownership(const struct device *dev) { #ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val = sys_read32(reg) | GPDMA_OSEL(0x3); @@ -281,7 +281,7 @@ static void intel_adsp_gpdma_claim_ownership(const struct device *dev) sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(0)); sys_write32(LPGPDMA_CHOSEL_FLAG | LPGPDMA_CTLOSEL_FLAG, DSP_INIT_LPGPDMA(1)); ARG_UNUSED(dev); -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ #endif /* CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP */ } @@ -289,7 +289,7 @@ static void intel_adsp_gpdma_claim_ownership(const struct device *dev) static void intel_adsp_gpdma_release_ownership(const struct device *dev) { #ifdef CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; uint32_t reg = dev_cfg->shim + GPDMA_CTL_OFFSET; uint32_t val = sys_read32(reg) & ~GPDMA_OSEL(0x3); @@ -298,12 +298,12 @@ static void intel_adsp_gpdma_release_ownership(const struct device *dev) /* CHECKME: Do CAVS platforms set ownership over DMA, * if yes, add support for it releasing. */ -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ #endif /* CONFIG_DMA_INTEL_ADSP_GPDMA_NEED_CONTROLLER_OWNERSHIP */ } #endif -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE static int intel_adsp_gpdma_enable(const struct device *dev) { const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; @@ -329,14 +329,14 @@ static int intel_adsp_gpdma_disable(const struct device *dev) return 0; } #endif /* CONFIG_PM_DEVICE */ -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ static int intel_adsp_gpdma_power_on(const struct device *dev) { const struct intel_adsp_gpdma_cfg *const dev_cfg = dev->config; int ret; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Power up */ ret = intel_adsp_gpdma_enable(dev); @@ -377,12 +377,12 @@ static int intel_adsp_gpdma_power_off(const struct device *dev) /* Relesing DMA ownership*/ intel_adsp_gpdma_release_ownership(dev); -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE /* Power down */ return intel_adsp_gpdma_disable(dev); #else return 0; -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ } #endif /* CONFIG_PM_DEVICE */ @@ -423,7 +423,7 @@ int intel_adsp_gpdma_get_attribute(const struct device *dev, uint32_t type, uint return 0; } -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE static inline void ace_gpdma_intc_unmask(void) { ACE_DINT[0].ie[ACE_INTL_GPDMA] = BIT(0); @@ -444,7 +444,7 @@ int intel_adsp_gpdma_init(const struct device *dev) ace_gpdma_intc_unmask(); -#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ACE +#if CONFIG_PM_DEVICE && CONFIG_SOC_SERIES_INTEL_ADSP_ACE if (pm_device_on_power_domain(dev)) { pm_device_init_off(dev); } else { diff --git a/drivers/dma/dma_intel_adsp_hda_host_in.c b/drivers/dma/dma_intel_adsp_hda_host_in.c index a999c7fbba6dd6..a6114b05404267 100644 --- a/drivers/dma/dma_intel_adsp_hda_host_in.c +++ b/drivers/dma/dma_intel_adsp_hda_host_in.c @@ -49,7 +49,8 @@ static const struct dma_driver_api intel_adsp_hda_dma_host_in_api = { DEVICE_DT_INST_GET(inst), \ DT_INST_IRQ(inst, sense)); \ irq_enable(DT_INST_IRQN(inst)); \ - IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE, (ACE_DINT[0].ie[ACE_INTL_HDAHIDMA] = 1;)) \ + IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE, \ + (ACE_DINT[0].ie[ACE_INTL_HDAHIDMA] = 1;)) \ } DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_IN_INIT) diff --git a/drivers/dma/dma_intel_adsp_hda_host_out.c b/drivers/dma/dma_intel_adsp_hda_host_out.c index cb7d9137a1a42d..f06d177ed29632 100644 --- a/drivers/dma/dma_intel_adsp_hda_host_out.c +++ b/drivers/dma/dma_intel_adsp_hda_host_out.c @@ -53,7 +53,8 @@ static const struct dma_driver_api intel_adsp_hda_dma_host_out_api = { DEVICE_DT_INST_GET(inst), \ DT_INST_IRQ(inst, sense)); \ irq_enable(DT_INST_IRQN(inst)); \ - IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ACE, (ACE_DINT[0].ie[ACE_INTL_HDAHODMA] = 1;)) \ + IF_ENABLED(CONFIG_SOC_SERIES_INTEL_ADSP_ACE, \ + (ACE_DINT[0].ie[ACE_INTL_HDAHODMA] = 1;)) \ } DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_HDA_DMA_HOST_OUT_INIT) diff --git a/drivers/espi/Kconfig.xec b/drivers/espi/Kconfig.xec index b110f91cfb0f27..b1752285c59c78 100644 --- a/drivers/espi/Kconfig.xec +++ b/drivers/espi/Kconfig.xec @@ -39,7 +39,7 @@ config ESPI_PERIPHERAL_UART config ESPI_PERIPHERAL_UART_SOC_MAPPING int "SoC port exposed as logical eSPI UART" - default 2 if SOC_SERIES_MEC1501X + default 2 if SOC_SERIES_MEC15XX default 1 if SOC_SERIES_MEC172X depends on ESPI_PERIPHERAL_UART help @@ -66,7 +66,7 @@ config ESPI_FLASH_BUFFER_SIZE config ESPI_SAF_XEC bool "XEC Microchip ESPI SAF driver" default y - depends on SOC_SERIES_MEC1501X + depends on SOC_SERIES_MEC15XX depends on DT_HAS_MICROCHIP_XEC_ESPI_SAF_ENABLED help Enable the Microchip XEC SAF ESPI driver for MEC15xx family. diff --git a/drivers/ethernet/Kconfig.mcux b/drivers/ethernet/Kconfig.mcux index 8996d7239ffbe9..c9b8e4fb6f27ca 100644 --- a/drivers/ethernet/Kconfig.mcux +++ b/drivers/ethernet/Kconfig.mcux @@ -94,8 +94,8 @@ if PTP_CLOCK_MCUX config ETH_MCUX_PTP_CLOCK_SRC_HZ int "Frequency of the clock source for the PTP timer" default 50000000 if SOC_SERIES_KINETIS_K6X - default 50000000 if SOC_SERIES_IMX_RT10XX - default 24000000 if SOC_SERIES_IMX_RT11XX + default 50000000 if SOC_SERIES_IMXRT10XX + default 24000000 if SOC_SERIES_IMXRT11XX help Set the frequency in Hz sourced to the PTP timer. If the value is set properly, the timer will be accurate. diff --git a/drivers/ethernet/eth_mcux.c b/drivers/ethernet/eth_mcux.c index 02f3a83049531a..a00b7ff57cc17c 100644 --- a/drivers/ethernet/eth_mcux.c +++ b/drivers/ethernet/eth_mcux.c @@ -396,7 +396,7 @@ static void eth_mcux_phy_start(struct eth_context *context) k_work_submit(&context->phy_work); break; #endif -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) context->phy_state = eth_mcux_phy_state_initial; #else context->phy_state = eth_mcux_phy_state_reset; @@ -453,7 +453,7 @@ static void eth_mcux_phy_event(struct eth_context *context) uint32_t status; #endif bool link_up; -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) status_t res; uint16_t ctrl2; #endif @@ -466,7 +466,7 @@ static void eth_mcux_phy_event(struct eth_context *context) #endif switch (context->phy_state) { case eth_mcux_phy_state_initial: -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) ENET_DisableInterrupts(context->base, ENET_EIR_MII_MASK); res = PHY_Read(context->phy_handle, PHY_CONTROL2_REG, &ctrl2); ENET_EnableInterrupts(context->base, ENET_EIR_MII_MASK); @@ -481,7 +481,7 @@ static void eth_mcux_phy_event(struct eth_context *context) ctrl2); } context->phy_state = eth_mcux_phy_state_reset; -#endif /* CONFIG_SOC_SERIES_IMX_RT */ +#endif #if defined(CONFIG_ETH_MCUX_NO_PHY_SMI) /* * When the iface is available proceed with the eth link setup, @@ -633,7 +633,7 @@ static void eth_mcux_delayed_phy_work(struct k_work *item) static void eth_mcux_phy_setup(struct eth_context *context) { -#if defined(CONFIG_SOC_SERIES_IMX_RT) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) status_t res; uint16_t oms_override; @@ -1024,14 +1024,14 @@ static void eth_mcux_init(const struct device *dev) context->phy_state = eth_mcux_phy_state_initial; context->phy_handle->ops = &phyksz8081_ops; -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) sys_clock = CLOCK_GetFreq(kCLOCK_IpgClk); #endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) sys_clock = CLOCK_GetFreq(kCLOCK_EnetPll1Clk); #endif -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) sys_clock = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus); #else sys_clock = CLOCK_GetFreq(kCLOCK_CoreSysClk); @@ -1391,9 +1391,9 @@ static void eth_mcux_err_isr(const struct device *dev) } #endif -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) #define ETH_MCUX_UNIQUE_ID (OCOTP->CFG1 ^ OCOTP->CFG2) -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) #define ETH_MCUX_UNIQUE_ID (OCOTP->FUSEN[40].FUSE) #elif defined(CONFIG_SOC_SERIES_KINETIS_K6X) #define ETH_MCUX_UNIQUE_ID (SIM->UIDH ^ SIM->UIDMH ^ SIM->UIDML ^ SIM->UIDL) diff --git a/drivers/ethernet/eth_nxp_enet.c b/drivers/ethernet/eth_nxp_enet.c index 244867dddf6977..864a488f55426a 100644 --- a/drivers/ethernet/eth_nxp_enet.c +++ b/drivers/ethernet/eth_nxp_enet.c @@ -772,9 +772,9 @@ static const struct ethernet_api api_funcs = { #define FREESCALE_OUI_B1 0x04 #define FREESCALE_OUI_B2 0x9f -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) #define ETH_NXP_ENET_UNIQUE_ID (OCOTP->CFG1 ^ OCOTP->CFG2) -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) #define ETH_NXP_ENET_UNIQUE_ID (OCOTP->FUSEN[40].FUSE) #elif defined(CONFIG_SOC_SERIES_KINETIS_K6X) #define ETH_NXP_ENET_UNIQUE_ID (SIM->UIDH ^ SIM->UIDMH ^ SIM->UIDML ^ SIM->UIDL) diff --git a/drivers/ethernet/eth_nxp_s32_gmac.c b/drivers/ethernet/eth_nxp_s32_gmac.c index 67a725d1fc528b..e6efb3f72c7597 100644 --- a/drivers/ethernet/eth_nxp_s32_gmac.c +++ b/drivers/ethernet/eth_nxp_s32_gmac.c @@ -147,7 +147,7 @@ static void phy_link_state_changed(const struct device *pdev, } } -#if defined(CONFIG_SOC_SERIES_S32K3XX) +#if defined(CONFIG_SOC_SERIES_S32K3) static int select_phy_interface(Gmac_Ip_MiiModeType mode) { uint32_t regval; @@ -174,7 +174,7 @@ static int select_phy_interface(Gmac_Ip_MiiModeType mode) } #else #error "SoC not supported" -#endif /* CONFIG_SOC_SERIES_S32K3XX */ +#endif /* CONFIG_SOC_SERIES_S32K3 */ static int eth_nxp_s32_init(const struct device *dev) { diff --git a/drivers/ethernet/eth_sam_gmac.c b/drivers/ethernet/eth_sam_gmac.c index 80d43f3616c169..1b559a9e0dcbe0 100644 --- a/drivers/ethernet/eth_sam_gmac.c +++ b/drivers/ethernet/eth_sam_gmac.c @@ -19,7 +19,7 @@ * - no statistics collection */ -#if defined(CONFIG_SOC_FAMILY_SAM) +#if defined(CONFIG_SOC_FAMILY_ATMEL_SAM) #define DT_DRV_COMPAT atmel_sam_gmac #else #define DT_DRV_COMPAT atmel_sam0_gmac @@ -51,7 +51,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #include "eth.h" -#ifdef CONFIG_SOC_FAMILY_SAM0 +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM0 #include "eth_sam0_gmac.h" #endif @@ -97,9 +97,9 @@ static inline void dcache_clean(uint32_t addr, uint32_t size) #define dcache_clean(addr, size) #endif -#ifdef CONFIG_SOC_FAMILY_SAM0 +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM0 #define MCK_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#elif CONFIG_SOC_FAMILY_SAM +#elif CONFIG_SOC_FAMILY_ATMEL_SAM #define MCK_FREQ_HZ SOC_ATMEL_SAM_MCK_FREQ_HZ #else #error Unsupported SoC family @@ -1796,7 +1796,7 @@ static int eth_initialize(const struct device *dev) cfg->config_func(); -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM /* Enable GMAC module's clock */ (void)clock_control_on(SAM_DT_PMC_CONTROLLER, (clock_control_subsys_t)&cfg->clock_cfg); @@ -2235,7 +2235,7 @@ PINCTRL_DT_INST_DEFINE(0); static const struct eth_sam_dev_cfg eth0_config = { .regs = (Gmac *)DT_INST_REG_ADDR(0), .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0), -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM .clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(0), #endif .config_func = eth0_irq_config, diff --git a/drivers/ethernet/eth_sam_gmac_priv.h b/drivers/ethernet/eth_sam_gmac_priv.h index 21765d5c57f110..8fd5a2b257b57d 100644 --- a/drivers/ethernet/eth_sam_gmac_priv.h +++ b/drivers/ethernet/eth_sam_gmac_priv.h @@ -261,7 +261,7 @@ struct gmac_queue { /* Device constant configuration parameters */ struct eth_sam_dev_cfg { Gmac *regs; -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM const struct atmel_sam_pmc_config clock_cfg; #endif const struct pinctrl_dev_config *pcfg; diff --git a/drivers/flash/Kconfig.it8xxx2 b/drivers/flash/Kconfig.it8xxx2 index 0302e01e61d998..50b881335a4fed 100644 --- a/drivers/flash/Kconfig.it8xxx2 +++ b/drivers/flash/Kconfig.it8xxx2 @@ -8,6 +8,9 @@ config SOC_FLASH_ITE_IT8XXX2 default y depends on DT_HAS_ITE_IT8XXX2_FLASH_CONTROLLER_ENABLED select SOC_IT8XXX2_USE_ILM + select FLASH_HAS_PAGE_LAYOUT + select FLASH_HAS_DRIVER_ENABLED + select HAS_FLASH_LOAD_OFFSET help The flash driver includes support for read, write and erase flash operations. It also supports protection. diff --git a/drivers/flash/Kconfig.mcux b/drivers/flash/Kconfig.mcux index ec7f5be22b2c2c..52e7220595bd25 100644 --- a/drivers/flash/Kconfig.mcux +++ b/drivers/flash/Kconfig.mcux @@ -101,30 +101,4 @@ config FLASH_MCUX_FLEXSPI_HYPERFLASH_WRITE_BUFFER This prevents faults when the data to write would be located on the flash itself. -if FLASH_MCUX_FLEXSPI_XIP - -choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET - prompt "FlexSPI drivers relocation target" - default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM - help - Select the location to run the FlexSPI drivers when using - the flash API. - -config FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM - bool "ITCM" - select CODE_DATA_RELOCATION - -config FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM - bool "RAM" - select CODE_DATA_RELOCATION_SRAM - -endchoice - -config FLASH_MCUX_FLEXSPI_XIP_MEM - string - default "ITCM" if FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM - default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM - -endif # FLASH_MCUX_FLEXSPI_XIP - endif # HAS_MCUX_FLEXSPI diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c index fbb8d85b6fbaab..91ed22b4422b51 100644 --- a/drivers/gpio/gpio_mcux_igpio.c +++ b/drivers/gpio/gpio_mcux_igpio.c @@ -72,7 +72,7 @@ static int mcux_igpio_configure(const struct device *dev, (volatile uint32_t *)config->pin_muxes[cfg_idx].config_register; uint32_t reg = *gpio_cfg_reg; -#ifdef CONFIG_SOC_SERIES_IMX_RT10XX +#ifdef CONFIG_SOC_SERIES_IMXRT10XX if ((flags & GPIO_SINGLE_ENDED) != 0) { /* Set ODE bit */ reg |= IOMUXC_SW_PAD_CTL_PAD_ODE_MASK; @@ -92,7 +92,7 @@ static int mcux_igpio_configure(const struct device *dev, /* Set pin to keeper */ reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUE_MASK; } -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) if (config->pin_muxes[pin].pue_mux) { /* PUE type register layout (GPIO_AD pins) */ if ((flags & GPIO_SINGLE_ENDED) != 0) { @@ -152,7 +152,7 @@ static int mcux_igpio_configure(const struct device *dev, } -#elif defined(CONFIG_SOC_SERIES_IMX8MQ_M4) +#elif defined(CONFIG_SOC_MIMX8MQ6_M4) if ((flags & GPIO_SINGLE_ENDED) != 0) { /* Set ODE bit */ reg |= (0x1 << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT); @@ -184,7 +184,7 @@ static int mcux_igpio_configure(const struct device *dev, /* Set pin to highz */ reg &= ~(0x1 << MCUX_IMX_BIAS_PULL_ENABLE_SHIFT); } -#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX */ memcpy(&pin_cfg.pinmux, &config->pin_muxes[cfg_idx], sizeof(pin_cfg.pinmux)); /* cfg register will be set by pinctrl_configure_pins */ diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig index 84afbefd84feb1..81888bd3a78088 100644 --- a/drivers/hwinfo/Kconfig +++ b/drivers/hwinfo/Kconfig @@ -66,7 +66,7 @@ config HWINFO_STM32 config HWINFO_NRF bool "NRF device ID" default y - depends on SOC_FAMILY_NRF + depends on SOC_FAMILY_NORDIC_NRF depends on NRF_SOC_SECURE_SUPPORTED help Enable Nordic NRF hwinfo driver. @@ -109,7 +109,7 @@ config HWINFO_MCUX_SYSCON config HWINFO_IMXRT bool "NXP i.mx RT device ID" default y - depends on SOC_SERIES_IMX_RT + depends on SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX help Enable NXP i.mx RT hwinfo driver. @@ -124,14 +124,14 @@ config HWINFO_RPI_PICO config HWINFO_SAM_RSTC bool "Atmel SAM reset cause" default y - depends on SOC_FAMILY_SAM && !SOC_SERIES_SAM4L + depends on SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L help Enable Atmel SAM reset cause hwinfo driver. config HWINFO_SAM bool "Atmel SAM device ID" default y - depends on SOC_FAMILY_SAM && !SOC_SERIES_SAM4L + depends on SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L help Enable Atmel SAM device ID hwinfo driver. @@ -145,28 +145,28 @@ config HWINFO_SAM4L config HWINFO_SAM0 bool "Atmel SAM0 device ID" default y - depends on SOC_FAMILY_SAM0 + depends on SOC_FAMILY_ATMEL_SAM0 help Enable Atmel SAM0 hwinfo driver. config HWINFO_SMARTBOND bool "Smartbond device reset cause" default y - depends on SOC_FAMILY_SMARTBOND + depends on SOC_FAMILY_RENESAS_SMARTBOND help Enable Smartbond reset cause hwinfo driver. config HWINFO_ESP32 bool "ESP32 device ID" default y - depends on SOC_FAMILY_ESP32 + depends on SOC_FAMILY_ESPRESSIF_ESP32 help Enable ESP32 hwinfo driver. config HWINFO_LITEX bool "LiteX device ID" default y - depends on SOC_RISCV32_LITEX_VEXRISCV + depends on SOC_LITEX_VEXRISCV help Enable LiteX hwinfo driver @@ -180,7 +180,7 @@ config HWINFO_PSOC6 config HWINFO_GECKO bool "GECKO hwinfo" default y - depends on SOC_FAMILY_EXX32 && !SOC_SERIES_EFR32MG21 && !SOC_SERIES_EFR32BG22 + depends on SOC_VENDOR_SILABS && !SOC_SERIES_EFR32MG21 && !SOC_SERIES_EFR32BG22 select SOC_GECKO_RMU help Enable Silabs GECKO hwinfo driver. diff --git a/drivers/hwinfo/hwinfo_imxrt.c b/drivers/hwinfo/hwinfo_imxrt.c index 79cc613d51f9cc..ea748482f76d72 100644 --- a/drivers/hwinfo/hwinfo_imxrt.c +++ b/drivers/hwinfo/hwinfo_imxrt.c @@ -17,7 +17,7 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length) { struct imxrt_uid dev_id; -#ifdef CONFIG_SOC_SERIES_IMX_RT11XX +#ifdef CONFIG_SOC_SERIES_IMXRT11XX dev_id.id[0] = sys_cpu_to_be32(OCOTP->FUSEN[17].FUSE); dev_id.id[1] = sys_cpu_to_be32(OCOTP->FUSEN[16].FUSE); #else diff --git a/drivers/i2c/Kconfig.nrfx b/drivers/i2c/Kconfig.nrfx index 78967177a3ac2a..6898d6e42a93e9 100644 --- a/drivers/i2c/Kconfig.nrfx +++ b/drivers/i2c/Kconfig.nrfx @@ -6,7 +6,7 @@ menuconfig I2C_NRFX bool "nRF TWI nrfx drivers" default y - depends on SOC_FAMILY_NRF + depends on SOC_FAMILY_NORDIC_NRF depends on MULTITHREADING select PINCTRL help diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c index 08bcdbb6343fe3..1ab1677c46a3ad 100644 --- a/drivers/i2s/i2s_mcux_sai.c +++ b/drivers/i2s/i2s_mcux_sai.c @@ -1148,13 +1148,13 @@ static void audio_clock_settings(const struct device *dev) imxrt_audio_codec_pll_init(clock_name, dev_cfg->clk_src, dev_cfg->clk_pre_div, dev_cfg->clk_src_div); - #ifdef CONFIG_SOC_SERIES_IMX_RT11XX + #ifdef CONFIG_SOC_SERIES_IMXRT11XX audioPllConfig.loopDivider = dev_cfg->pll_lp; audioPllConfig.postDivider = dev_cfg->pll_pd; audioPllConfig.numerator = dev_cfg->pll_num; audioPllConfig.denominator = dev_cfg->pll_den; audioPllConfig.ssEnable = false; - #elif defined CONFIG_SOC_SERIES_IMX_RT10XX + #elif defined CONFIG_SOC_SERIES_IMXRT10XX audioPllConfig.src = dev_cfg->pll_src; audioPllConfig.loopDivider = dev_cfg->pll_lp; audioPllConfig.postDivider = dev_cfg->pll_pd; diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32 index dd8599bfbd22e5..1d88fcb1966059 100644 --- a/drivers/interrupt_controller/Kconfig.esp32 +++ b/drivers/interrupt_controller/Kconfig.esp32 @@ -5,7 +5,7 @@ config INTC_ESP32 bool "Interrupt allocator for Xtensa-based Espressif SoCs" - default y if SOC_FAMILY_ESP32 && !SOC_SERIES_ESP32C3 + default y if SOC_FAMILY_ESPRESSIF_ESP32 && !SOC_SERIES_ESP32C3 help Enable custom interrupt allocator for Espressif SoCs based on Xtensa architecture. diff --git a/drivers/led/led_mchp_xec.c b/drivers/led/led_mchp_xec.c index db8bffb83f7aea..588a8bc2642dad 100644 --- a/drivers/led/led_mchp_xec.c +++ b/drivers/led/led_mchp_xec.c @@ -12,7 +12,7 @@ */ #include -#ifndef CONFIG_SOC_SERIES_MEC1501X +#ifndef CONFIG_SOC_SERIES_MEC15XX #include #include #endif @@ -207,7 +207,7 @@ static int xec_bbled_off(const struct device *dev, uint32_t led) return 0; } -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX static inline void xec_bbled_slp_en_clr(const struct device *dev) { const struct xec_bbled_config * const cfg = dev->config; diff --git a/drivers/mdio/mdio_sam.c b/drivers/mdio/mdio_sam.c index 5665057f7c91e4..216e0dd80f421f 100644 --- a/drivers/mdio/mdio_sam.c +++ b/drivers/mdio/mdio_sam.c @@ -21,7 +21,7 @@ LOG_MODULE_REGISTER(mdio_sam, CONFIG_MDIO_LOG_LEVEL); /* GMAC */ -#ifdef CONFIG_SOC_FAMILY_SAM0 +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM0 #define GMAC_MAN MAN.reg #define GMAC_NSR NSR.reg #define GMAC_NCR NCR.reg @@ -34,7 +34,7 @@ struct mdio_sam_dev_data { struct mdio_sam_dev_config { Gmac * const regs; const struct pinctrl_dev_config *pcfg; -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM const struct atmel_sam_pmc_config clock_cfg; #endif }; @@ -144,7 +144,7 @@ static int mdio_sam_initialize(const struct device *dev) k_sem_init(&data->sem, 1, 1); -#ifdef CONFIG_SOC_FAMILY_SAM +#ifdef CONFIG_SOC_FAMILY_ATMEL_SAM /* Enable GMAC module's clock */ (void) clock_control_on(SAM_DT_PMC_CONTROLLER, (clock_control_subsys_t) &cfg->clock_cfg); #else @@ -168,7 +168,7 @@ static const struct mdio_driver_api mdio_sam_driver_api = { }; #define MDIO_SAM_CLOCK(n) \ - COND_CODE_1(CONFIG_SOC_FAMILY_SAM, \ + COND_CODE_1(CONFIG_SOC_FAMILY_ATMEL_SAM, \ (.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n),), () \ ) diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c index 51d176a5fefa93..b78a247ae0122c 100644 --- a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c +++ b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c @@ -94,7 +94,7 @@ static uint32_t get_hpsram_bank_idx(uintptr_t pa) */ static uint16_t flags_to_tlb_perms(uint32_t flags) { -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) uint16_t perms = 0; if ((flags & SYS_MM_MEM_PERM_RW) == SYS_MM_MEM_PERM_RW) { @@ -111,7 +111,7 @@ static uint16_t flags_to_tlb_perms(uint32_t flags) #endif } -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) /** * Convert TLB entry permission bits to the SYS_MM_MEM_PERM_* flags. * @@ -136,7 +136,7 @@ static uint16_t tlb_perms_to_flags(uint16_t perms) static int sys_mm_drv_hpsram_pwr(uint32_t bank_idx, bool enable, bool non_blocking) { -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) if (bank_idx > ace_hpsram_get_bank_count()) { return -1; } @@ -484,7 +484,7 @@ int sys_mm_drv_page_flag_get(void *virt, uint32_t *flags) ARG_UNUSED(virt); int ret = 0; -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) uint16_t *tlb_entries = UINT_TO_POINTER(TLB_BASE); uint16_t ent; diff --git a/drivers/pinctrl/pinctrl_gecko.c b/drivers/pinctrl/pinctrl_gecko.c index cdb1118768f3b8..0573ef3a40caf2 100644 --- a/drivers/pinctrl/pinctrl_gecko.c +++ b/drivers/pinctrl/pinctrl_gecko.c @@ -12,7 +12,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp { USART_TypeDef *base = (USART_TypeDef *)reg; uint8_t loc; -#ifdef CONFIG_SOC_GECKO_SERIES1 +#ifdef CONFIG_SOC_FAMILY_SILABS_S1 LEUART_TypeDef *lebase = (LEUART_TypeDef *)reg; #else int usart_num = USART_NUM(base); @@ -50,7 +50,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp txpin.out); break; -#ifdef CONFIG_SOC_GECKO_SERIES1 +#ifdef CONFIG_SOC_FAMILY_SILABS_S1 case GECKO_FUN_UART_RTS: pin_config.mode = gpioModePushPull; pin_config.out = 1; @@ -100,7 +100,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp lebase->ROUTELOC0 &= ~_LEUART_ROUTELOC0_TXLOC_MASK; lebase->ROUTELOC0 |= (loc << _LEUART_ROUTELOC0_TXLOC_SHIFT); break; -#else /* CONFIG_SOC_GECKO_SERIES1 */ +#else /* CONFIG_SOC_FAMILY_SILABS_S1 */ case GECKO_FUN_UART_LOC: #ifdef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION /* For SOCs with configurable pin_cfg locations (set in SOC Kconfig) */ @@ -156,11 +156,11 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp } #endif /* UART_GECKO_HW_FLOW_CONTROL */ break; -#endif /* CONFIG_SOC_GECKO_SERIES1 */ +#endif /* CONFIG_SOC_FAMILY_SILABS_S1 */ #endif /* CONFIG_UART_GECKO */ #ifdef CONFIG_SPI_GECKO -#ifdef CONFIG_SOC_GECKO_SERIES1 +#ifdef CONFIG_SOC_FAMILY_SILABS_S1 case GECKO_FUN_SPIM_SCK: pin_config.mode = gpioModePushPull; pin_config.out = 1; @@ -241,7 +241,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_CSLOC_SHIFT); break; -#else /* CONFIG_SOC_GECKO_SERIES1 */ +#else /* CONFIG_SOC_FAMILY_SILABS_S1 */ case GECKO_FUN_SPI_SCK: pin_config.mode = gpioModePushPull; pin_config.out = 1; @@ -274,7 +274,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp GPIO_PinModeSet(pin_config.port, pin_config.pin, pin_config.mode, pin_config.out); break; -#endif /* CONFIG_SOC_GECKO_SERIES1 */ +#endif /* CONFIG_SOC_FAMILY_SILABS_S1 */ #endif /* CONFIG_SPI_GECKO */ default: diff --git a/drivers/pinctrl/pinctrl_imx.c b/drivers/pinctrl/pinctrl_imx.c index 8959ff4cb582d7..2996657914c141 100644 --- a/drivers/pinctrl/pinctrl_imx.c +++ b/drivers/pinctrl/pinctrl_imx.c @@ -19,7 +19,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uint32_t input_daisy = pins[i].pinmux.input_daisy; uint32_t config_register = pins[i].pinmux.config_register; uint32_t pin_ctrl_flags = pins[i].pin_ctrl_flags; -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) || defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) volatile uint32_t *gpr_register = (volatile uint32_t *)((uintptr_t)pins[i].pinmux.gpr_register); if (gpr_register) { @@ -33,7 +33,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, } #endif -#ifdef CONFIG_SOC_MIMX93_A55 +#ifdef CONFIG_SOC_MIMX9352_A55 sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) | IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)), (mem_addr_t)mux_register); @@ -65,17 +65,17 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, static int imx_pinctrl_init(void) { -#ifdef CONFIG_SOC_SERIES_IMX_RT +#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX) CLOCK_EnableClock(kCLOCK_Iomuxc); -#ifdef CONFIG_SOC_SERIES_IMX_RT10XX +#ifdef CONFIG_SOC_SERIES_IMXRT10XX CLOCK_EnableClock(kCLOCK_IomuxcSnvs); CLOCK_EnableClock(kCLOCK_IomuxcGpr); -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) CLOCK_EnableClock(kCLOCK_Iomuxc_Lpsr); -#endif /* CONFIG_SOC_SERIES_IMX_RT10XX */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX */ #elif defined(CONFIG_SOC_MIMX8MQ6) CLOCK_EnableClock(kCLOCK_Iomux); -#endif /* CONFIG_SOC_SERIES_IMX_RT */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */ return 0; } diff --git a/drivers/ps2/Kconfig.xec b/drivers/ps2/Kconfig.xec index 86643b11e841b2..79dd43cfdcc79f 100644 --- a/drivers/ps2/Kconfig.xec +++ b/drivers/ps2/Kconfig.xec @@ -5,7 +5,7 @@ config PS2_XEC bool "XEC Microchip PS2 driver" - depends on SOC_FAMILY_MEC && ESPI_PERIPHERAL_8042_KBC + depends on SOC_FAMILY_MICROCHIP_MEC && ESPI_PERIPHERAL_8042_KBC select PINCTRL help Enable the Microchip XEC PS2 IO driver. The driver also diff --git a/drivers/pwm/Kconfig.rcar b/drivers/pwm/Kconfig.rcar index 39d5eeb1c4f2bf..bf8bd912b6af89 100644 --- a/drivers/pwm/Kconfig.rcar +++ b/drivers/pwm/Kconfig.rcar @@ -6,7 +6,7 @@ config PWM_RCAR bool "Renesas R-Car PWM Driver" default y - depends on SOC_FAMILY_RCAR + depends on SOC_FAMILY_RENESAS_RCAR depends on DT_HAS_RENESAS_PWM_RCAR_ENABLED help Enable Renesas R-Car PWM Driver. diff --git a/drivers/sensor/mchp_tach_xec/Kconfig b/drivers/sensor/mchp_tach_xec/Kconfig index d0ce0827e40675..870f05944b54a4 100644 --- a/drivers/sensor/mchp_tach_xec/Kconfig +++ b/drivers/sensor/mchp_tach_xec/Kconfig @@ -7,7 +7,7 @@ config TACH_XEC bool "XEC Tachometer sensor" default y depends on DT_HAS_MICROCHIP_XEC_TACH_ENABLED - depends on SOC_FAMILY_MEC + depends on SOC_FAMILY_MICROCHIP_MEC select PINCTRL help Enable the Microchip XEC tachometer sensor. diff --git a/drivers/sensor/qdec_sam/Kconfig b/drivers/sensor/qdec_sam/Kconfig index 32f05769537fa2..45daf9e56a5143 100644 --- a/drivers/sensor/qdec_sam/Kconfig +++ b/drivers/sensor/qdec_sam/Kconfig @@ -8,6 +8,6 @@ config QDEC_SAM bool "Atmel SAM QDEC driver" default y depends on DT_HAS_ATMEL_SAM_TC_QDEC_ENABLED - depends on SOC_FAMILY_SAM + depends on SOC_FAMILY_ATMEL_SAM help Atmel SAM MCU family Quadrature Decoder (TC) driver. diff --git a/drivers/serial/Kconfig.gecko b/drivers/serial/Kconfig.gecko index 2330fd401c74e6..8bc311cd5232b1 100644 --- a/drivers/serial/Kconfig.gecko +++ b/drivers/serial/Kconfig.gecko @@ -10,6 +10,6 @@ config UART_GECKO select SERIAL_HAS_DRIVER select SERIAL_SUPPORT_INTERRUPT select SOC_GECKO_USART - select PINCTRL if SOC_GECKO_SERIES1 + select PINCTRL if SOC_FAMILY_SILABS_S1 help Enable the Gecko uart driver. diff --git a/drivers/serial/uart_mcux_flexcomm.c b/drivers/serial/uart_mcux_flexcomm.c index 4332b20cb910ad..a15ba82873a26f 100644 --- a/drivers/serial/uart_mcux_flexcomm.c +++ b/drivers/serial/uart_mcux_flexcomm.c @@ -813,7 +813,7 @@ static void mcux_flexcomm_uart_dma_rx_callback(const struct device *dma_device, data->rx_data.offset = 0; } -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX) +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT6XX) /* * This functions calculates the inputmux connection value * needed by INPUTMUX_EnableSignal to allow the UART's DMA @@ -825,7 +825,7 @@ static uint32_t fc_uart_calc_inmux_connection(uint8_t channel, DMA_Type *base) uint32_t chmux_sel = 0; uint32_t chmux_val = 0; -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) uint32_t chmux_sel_id = 0; if (base == (DMA_Type *)DMA0_BASE) { @@ -902,7 +902,7 @@ static int flexcomm_uart_async_init(const struct device *dev) USART_EnableRxDMA(config->base, false); /* Route DMA requests */ -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || defined(CONFIG_SOC_SERIES_IMX_RT6XX) +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT6XX) /* RT 3 digit uses input mux to route DMA requests from * the UART peripheral to a hardware designated DMA channel */ diff --git a/drivers/spi/Kconfig.nrfx b/drivers/spi/Kconfig.nrfx index 0ee1c03065baf3..4d158b935a7d47 100644 --- a/drivers/spi/Kconfig.nrfx +++ b/drivers/spi/Kconfig.nrfx @@ -4,7 +4,7 @@ menuconfig SPI_NRFX bool "nRF SPI nrfx drivers" default y - depends on SOC_FAMILY_NRF + depends on SOC_FAMILY_NORDIC_NRF depends on MULTITHREADING select PINCTRL help diff --git a/drivers/timer/Kconfig.gecko b/drivers/timer/Kconfig.gecko index 7a14af67e6ad06..cd53f9977b5cc1 100644 --- a/drivers/timer/Kconfig.gecko +++ b/drivers/timer/Kconfig.gecko @@ -3,7 +3,7 @@ config GECKO_BURTC_TIMER bool "SiLabs Gecko BURTC system clock driver" - depends on SOC_GECKO_SERIES2 + depends on SOC_FAMILY_SILABS_S2 depends on DT_HAS_SILABS_GECKO_BURTC_ENABLED select SOC_GECKO_BURTC select TICKLESS_CAPABLE diff --git a/drivers/timer/Kconfig.x86 b/drivers/timer/Kconfig.x86 index aa5f1a9c6d6d97..ea6d4a216b7d45 100644 --- a/drivers/timer/Kconfig.x86 +++ b/drivers/timer/Kconfig.x86 @@ -5,7 +5,7 @@ choice prompt "Default System Timer" - default HPET_TIMER if SOC_FAMILY_INTEL_ISH || SOC_IA32 || SOC_LAKEMONT + default HPET_TIMER if SOC_FAMILY_INTEL_ISH || SOC_ATOM || SOC_LAKEMONT default APIC_TSC_DEADLINE_TIMER depends on X86 help diff --git a/drivers/timer/hpet.c b/drivers/timer/hpet.c index 8a7134a762efa1..de2abf757f8531 100644 --- a/drivers/timer/hpet.c +++ b/drivers/timer/hpet.c @@ -14,8 +14,6 @@ #include -#include - /** * @file * @brief HPET (High Precision Event Timers) driver diff --git a/drivers/timer/intel_adsp_timer.c b/drivers/timer/intel_adsp_timer.c index 116a512f8fe287..330e5bbd425669 100644 --- a/drivers/timer/intel_adsp_timer.c +++ b/drivers/timer/intel_adsp_timer.c @@ -27,7 +27,7 @@ #define COMPARATOR_IDX 0 /* 0 or 1 */ -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE #define TIMER_IRQ ACE_IRQ_TO_ZEPHYR(ACE_INTL_TTS) #else #define TIMER_IRQ DSP_WCT_IRQ(COMPARATOR_IDX) @@ -198,7 +198,7 @@ static void irq_init(void) * (for per-core control) above the interrupt controller. * Drivers need to do that part. */ -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DINT[cpu].ie[ACE_INTL_TTS] |= BIT(COMPARATOR_IDX + 1); sys_write32(sys_read32(DSPWCTCS_ADDR) | ADSP_SHIM_DSPWCTCS_TTIE(COMPARATOR_IDX), DSPWCTCS_ADDR); diff --git a/drivers/timer/mchp_xec_rtos_timer.c b/drivers/timer/mchp_xec_rtos_timer.c index 18be700d5a49df..b57fee45a3991e 100644 --- a/drivers/timer/mchp_xec_rtos_timer.c +++ b/drivers/timer/mchp_xec_rtos_timer.c @@ -420,7 +420,7 @@ static int sys_clock_driver_init(void) | MCHP_BTMR_CTRL_COUNT_UP | (47UL << MCHP_BTMR_CTRL_PRESCALE_POS)); -#if CONFIG_SOC_SERIES_MEC1501X +#if CONFIG_SOC_SERIES_MEC15XX mchp_pcr_periph_slp_ctrl(PCR_B32TMR0, 0); #else PCR_XEC_REGS->SLP_EN[BTMR32_0_PCR_REG_IDX] &= ~BIT(BTMR32_0_PCR_BITPOS); diff --git a/drivers/usb/device/usb_dc_mcux.c b/drivers/usb/device/usb_dc_mcux.c index 0667486b62806a..a4e979d206bbdb 100644 --- a/drivers/usb/device/usb_dc_mcux.c +++ b/drivers/usb/device/usb_dc_mcux.c @@ -76,8 +76,8 @@ static void usb_isr_handler(void); BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported"); /* Controller ID is for HAL usage */ -#if defined(CONFIG_SOC_SERIES_IMX_RT5XX) || \ - defined(CONFIG_SOC_SERIES_IMX_RT6XX) || \ +#if defined(CONFIG_SOC_SERIES_IMXRT5XX) || \ + defined(CONFIG_SOC_SERIES_IMXRT6XX) || \ defined(CONFIG_SOC_LPC55S28) || \ defined(CONFIG_SOC_LPC55S16) #define CONTROLLER_ID kUSB_ControllerLpcIp3511Hs0 @@ -89,7 +89,7 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported"); #elif DT_NODE_HAS_STATUS(DT_NODELABEL(usbfs), okay) #define CONTROLLER_ID kUSB_ControllerLpcIp3511Fs0 #endif /* LPC55s69 */ -#elif defined(CONFIG_SOC_SERIES_IMX_RT) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) #if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) #define CONTROLLER_ID kUSB_ControllerEhci0 #elif DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) diff --git a/dts/arm/intel_socfpga_std/socfpga_cyclone5.dtsi b/dts/arm/intel_socfpga_std/socfpga_cyclonev.dtsi similarity index 100% rename from dts/arm/intel_socfpga_std/socfpga_cyclone5.dtsi rename to dts/arm/intel_socfpga_std/socfpga_cyclonev.dtsi diff --git a/dts/arm/seeed/lora-e5.dtsi b/dts/arm/seeed_studio/lora-e5.dtsi similarity index 100% rename from dts/arm/seeed/lora-e5.dtsi rename to dts/arm/seeed_studio/lora-e5.dtsi diff --git a/dts/arm/st/f0/stm32f071.dtsi b/dts/arm/st/f0/stm32f071.dtsi index b9547808738824..35156176e11fbd 100644 --- a/dts/arm/st/f0/stm32f071.dtsi +++ b/dts/arm/st/f0/stm32f071.dtsi @@ -7,6 +7,15 @@ #include / { + clocks { + clk_hsi48: clk-hsi48 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + status = "disabled"; + }; + }; + soc { compatible = "st,stm32f071", "st,stm32f0", "simple-bus"; @@ -16,15 +25,6 @@ }; }; - clocks { - clk_hsi48: clk-hsi48 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = ; - status = "disabled"; - }; - }; - pinctrl: pin-controller@48000000 { gpioe: gpio@48001000 { compatible = "st,stm32-gpio"; diff --git a/dts/arm/st/f0/stm32f091.dtsi b/dts/arm/st/f0/stm32f091.dtsi index b1ad8f0646ea66..67497b09d8d8e1 100644 --- a/dts/arm/st/f0/stm32f091.dtsi +++ b/dts/arm/st/f0/stm32f091.dtsi @@ -43,9 +43,9 @@ status = "disabled"; }; - usart8: serial@40011C00 { + usart8: serial@40011c00 { compatible = "st,stm32-usart", "st,stm32-uart"; - reg = <0x40011C00 0x400>; + reg = <0x40011c00 0x400>; clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>; resets = <&rctl STM32_RESET(APB2, 7U)>; interrupts = <29 0>; diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt index ce372c6ed7f1a2..1b5ebf3b30a372 100644 --- a/dts/bindings/vendor-prefixes.txt +++ b/dts/bindings/vendor-prefixes.txt @@ -10,6 +10,8 @@ # # +# zephyr-keep-sorted-start +96boards 96Boards aaeon AAEON Technology Inc. abb ABB abilis Abilis Systems @@ -17,9 +19,10 @@ abracon Abracon Corporation abt ShenZhen Asia Better Technology Ltd. acer Acer Inc. acme Acme Systems srl +aconno aconno GmbH +actinius Actinius B.V. actions Actions Semiconductor Co., Ltd. active-semi Active-Semi International Inc -actinius Actinius B.V. ad Avionic Design GmbH adafruit Adafruit Industries, LLC adapteva Adapteva, Inc. @@ -31,6 +34,7 @@ aeroflexgaisler Aeroflex Gaisler AB aesop AESOP Embedded Forum al Annapurna Labs alcatel Alcatel +alientek Alientek allegro Allegro DVT allo Allo.com allwinner Allwinner Technology Co., Ltd. @@ -38,9 +42,9 @@ alphascale AlphaScale Integrated Circuits Systems, Inc. alps Alps Electric Co., Ltd. alt Altus-Escon-Company BV altr Altera Corp. -ambiq Ambiq Micro, Inc. amarula Amarula Solutions amazon Amazon.com, Inc. +ambiq Ambiq Micro, Inc. amcc Applied Micro Circuits Corporation (APM, formally AMCC) amd Advanced Micro Devices (AMD), Inc. amediatech Shenzhen Amediatech Technology Co., Ltd @@ -58,8 +62,8 @@ apm Applied Micro Circuits Corporation (APM) apple Apple Inc. aptina Aptina Imaging arasan Arasan Chip Systems -archermind ArcherMind Technology (Nanjing) Co., Ltd. arc Synopsys, Inc. (formerly ARC International PLC) +archermind ArcherMind Technology (Nanjing) Co., Ltd. arctic Arctic Sand arcx arcx Inc. / Archronix Inc. arduino Arduino @@ -69,11 +73,12 @@ armadeus ARMadeus Systems SARL arrow Arrow Electronics artesyn Artesyn Embedded Technologies Inc. asahi-kasei Asahi Kasei Corp. -asmedia ASMedia Technology Inc. asc All Sensors Corporation +asmedia ASMedia Technology Inc. aspeed ASPEED Technology Inc. asus AsusTek Computer Inc. atlas Atlas Scientific LLC +atmarktechno Atmark Techno, Inc. atmel Atmel Corporation auo AU Optronics Corporation auvidea Auvidea GmbH @@ -88,6 +93,8 @@ azoteq Azoteq (Pty) Ltd azw Shenzhen AZW Technology Co., Ltd. baikal BAIKAL ELECTRONICS, JSC bananapi BIPAI KEJI LIMITED +bbc BBC +bcdevices Blue Clover Devices beacon Compass Electronics Group, LLC beagle BeagleBoard.org Foundation bhf Beckhoff Automation GmbH & Co. KG @@ -97,11 +104,11 @@ blutek BluTek Power boe BOE Technology Group Co., Ltd. bosch Bosch Sensortec GmbH boundary Boundary Devices Inc. -broadmobi Shanghai Broadmobi Communication Technology Co.,Ltd. brcm Broadcom Corporation +broadmobi Shanghai Broadmobi Communication Technology Co.,Ltd. +bticino Bticino International buffalo Buffalo, Inc. bur B&R Industrial Automation GmbH -bticino Bticino International calaosystems CALAO Systems SAS calxeda Calxeda canaan Canaan, Inc. @@ -124,6 +131,7 @@ chrp Common Hardware Reference Platform chunghwa Chunghwa Picture Tubes Ltd. chuwi Chuwi Innovation Ltd. ciaa Computadora Industrial Abierta Argentina +circuitdojo Circuit Dojo cirrus Cirrus Logic, Inc. cisco Cisco Systems, Inc. cloudengines Cloud Engines, Inc. @@ -131,6 +139,7 @@ cnm Chips&Media, Inc. cnxt Conexant Systems, Inc. colorfly Colorful GRP, Shenzhen Xueyushi Technology Ltd. compulab CompuLab Ltd. +contextualelectronics Contextual Electronics coreriver CORERIVER Semiconductor Co.,Ltd. corpro Chengdu Corpro Technology Co., Ltd. cortina Cortina Systems, Inc. @@ -173,12 +182,14 @@ ea Embedded Artists AB ebang Zhejiang Ebang Communication Co., Ltd ebs-systart EBS-SYSTART GmbH ebv EBV Elektronik +ebyte Chengdu Ebyte Electronic Technology eckelmann Eckelmann AG edt Emerging Display Technologies eeti eGalax_eMPIA Technology Inc efinix Efinix Inc einfochips Einfochips elan Elan Microelectronic Corp. +electronut Electronut Labs element14 Element14 (A Premier Farnell Company) elgin Elgin S/A. elida Shenzhen Elida Technology Co., Ltd. @@ -188,6 +199,7 @@ emlid Emlid, Ltd. emmicro EM Microelectronic empire-electronix Empire Electronix emtrion emtrion GmbH +enclustra Enclustra endless Endless Mobile, Inc. ene ENE Technology, Inc. energymicro Silicon Laboratories (formerly Energy Micro AS) @@ -232,7 +244,7 @@ gd GigaDevice Semiconductor ge General Electric Company geekbuying GeekBuying gef GE Fanuc Intelligent Platforms Embedded Systems, Inc. -GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. +gefanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc. gemei Gemei Digital Technology Co., Ltd. geniatech Geniatech, Inc. giantec Giantec Semiconductor, Inc. @@ -252,6 +264,7 @@ hamamatsu Hamamatsu Photonics K.K. hannstar HannStar Display Corporation haoyu Haoyu Microelectronic Co. Ltd. hardkernel Hardkernel Co., Ltd +heltec Chengdu Heltec Automation Technology Co., Ltd. hideep HiDeep Inc. himax Himax Technologies, Inc. hirschmann Hirschmann Automation and Control GmbH @@ -259,13 +272,14 @@ hisilicon Hisilicon Limited. hit Hitachi Ltd. hitex Hitex Development Tools holt Holt Integrated Circuits, Inc. +holtek Holtek Semiconductor, Inc. +holyiot Shenzhen Holyiot Technology Co., Ltd. honestar Honestar Technologies Co., Ltd. honeywell Honeywell hoperf HOPERF Microelectronics Co. Ltd hoperun Jiangsu HopeRun Software Co., Ltd. hp Hewlett Packard hsg HannStar Display Co. -holtek Holtek Semiconductor, Inc. hugsun Shenzhen Hugsun Technology Co. Ltd. hwacom HwaCom Systems Inc. hycon Hycon Technology Corp. @@ -285,15 +299,15 @@ incircuit In-Circuit GmbH inet-tek Shenzhen iNet Mobile Internet Technology Co., Ltd infineon Infineon Technologies inforce Inforce Computing -inventek Inventek Systems -ivo InfoVision Optoelectronics Kunshan Co. Ltd. ingenic Ingenic Semiconductor +innblue innblue UG innolux Innolux Corporation inside-secure INSIDE Secure inspur Inspur Corporation intel Intel Corporation intercontrol Inter Control Group invensense InvenSense Inc. +inventek Inventek Systems inversepath Inverse Path iom Iomega Corporation isee ISEE 2007 S.L. @@ -302,18 +316,20 @@ isil Intersil issi Integrated Silicon Solutions Inc. ite ITE Tech. Inc. itead ITEAD Intelligent Systems Co.Ltd +ivo InfoVision Optoelectronics Kunshan Co. Ltd. iwave iWave Systems Technologies Pvt. Ltd. jdi Japan Display Inc. jedec JEDEC Solid State Technology Association jesurun Shenzhen Jesurun Electronics Business Dept. -jianda Jiandangjing Technology Co., Ltd. jhd Shenzhen Jinghua Displays Electronics Co., Ltd. +jianda Jiandangjing Technology Co., Ltd. kam Kamstrup A/S karo Ka-Ro electronics GmbH keithkoep Keith & Koep GmbH keymile Keymile GmbH khadas Khadas kiebackpeter Kieback & Peter GmbH +kincony KinCony Electronics Co., Ltd. kinetic Kinetic Technologies kingdisplay King & Display Technology Co., Ltd. kingnovel Kingnovel Technology Co., Ltd. @@ -357,10 +373,13 @@ loongson Loongson Technology Corporation Limited lowrisc lowRISC Community Interest Company lsi LSI Corp. (LSI Logic) ltr LiteOn OptoElectronics +luatos LuatOS Team lwn Liebherr-Werk Nenzing GmbH lxa Linux Automation GmbH m5stack M5Stack macnica Macnica Americas +madmachine Shenzhen FeiKaiTe Technology Co., Ltd. +makerdiary Shenzhen Zaowubang Technology Co., Ltd. mantix Mantix Display Technology Co.,Ltd. mapleboard Mapleboard.org marvell Marvell Technology Group Ltd. @@ -409,6 +428,7 @@ mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) multi-inno Multi-Inno Technology Co.,Ltd mundoreader Mundo Reader S.L. murata Murata Manufacturing Co., Ltd. +mxchip Shanghai MXCHIP Information Technology Co., Ltd. mxicy Macronix International Co., Ltd. myir MYIR Tech Limited national National Semiconductor @@ -420,9 +440,9 @@ netron-dy Netron DY netronix Netronix, Inc. netxeon Shenzhen Netxeon Technology CO., LTD neweast Guangdong Neweast Optoelectronics CO., LTD +newhaven Newhaven Display International nexbox Nexbox nextthing Next Thing Co. -newhaven Newhaven Display International ni National Instruments nintendo Nintendo nlt NLT Technologies, Ltd. @@ -430,8 +450,8 @@ nokia Nokia nordic Nordic Semiconductor noritake Noritake Co., Inc. Electronics Division novtech NovTech, Inc. -nutsboard NutsBoard nuclei Nuclei System Technology +nutsboard NutsBoard nuvoton Nuvoton Technology Corporation nvd New Vision Display nvidia NVIDIA @@ -442,7 +462,6 @@ okaya Okaya Electric America, Inc. oki Oki Electric Industry Co., Ltd. olimex OLIMEX Ltd. olpc One Laptop Per Child -ovti OmniVision Technologies Co., Ltd. onion Onion Corporation onnn ON Semiconductor Corp. ontat On Tat Industrial Company @@ -453,19 +472,20 @@ openrisc OpenRISC.io openthread OpenThread.io option Option NV oranth Shenzhen Oranth Technology Co., Ltd. -ORCL Oracle Corporation +orcl Oracle Corporation orisetech Orise Technology ortustech Ortus Technology Co., Ltd. osddisplays OSD Displays ouya Ouya Inc. overkiz Overkiz SAS ovti OmniVision Technologies +ovti OmniVision Technologies Co., Ltd. oxsemi Oxford Semiconductor, Ltd. ozzmaker OzzMaker panasonic Panasonic Corporation parade Parade Technologies Inc. -particle Particle.io parallax Parallax Inc. +particle Particle.io pda Precision Design Associates, Inc. pericom Pericom Technology Inc. pervasive Pervasive Displays, Inc. @@ -476,6 +496,7 @@ pine64 Pine64 pineriver Shenzhen PineRiver Designs Co., Ltd. pixart PixArt Imaging Inc. pixcir PIXCIR MICROELECTRONICS Co., Ltd +pjrc PJRC plantower Plantower Co., Ltd plathome Plat'Home Co., Ltd. plda PLDA @@ -499,38 +520,41 @@ qca Qualcomm Atheros, Inc. qcom Qualcomm Technologies, Inc qemu QEMU, a generic and open source machine emulator and virtualizer qi Qi Hardware -qihua Chengdu Kaixuan Information Technology Co., Ltd. qiaodian QiaoDian XianShi Corporation +qihua Chengdu Kaixuan Information Technology Co., Ltd. qnap QNAP Systems, Inc. qorvo Qorvo, Inc. quectel Quectel Wireless Solutions Co., Ltd. quicklogic QuickLogic Corp. radxa Radxa raidsonic RaidSonic Technology GmbH +rakwireless RAKwireless Technology Limited ralink Mediatek/Ralink Technology Corp. ramtron Ramtron International raspberrypi Raspberry Pi Foundation raydium Raydium Semiconductor Corp. +raytac Raytac Corporation rda Unisoc Communications, Inc. realtek Realtek Semiconductor Corp. remarkable reMarkable AS renesas Renesas Electronics Corporation renode Antmicro's open source simulation and virtual development framework -rex iMX6 Rex Project rervision Shenzhen Rervision Technology Co., Ltd. revotics Revolution Robotics, Inc. (Revotics) +rex iMX6 Rex Project richtek Richtek Technology Corporation ricoh Ricoh Co. Ltd. rikomagic Rikomagic Tech Corp. Ltd -riscv RISC-V Foundation riot Embest RIoT +riscv RISC-V Foundation rockchip Fuzhou Rockchip Electronics Co., Ltd rocktech ROCKTECH DISPLAYS LIMITED rohm ROHM Semiconductor Co., Ltd ronbo Ronbo Electronics +ronoth Ronoth roofull Shenzhen Roofull Technology Co, Ltd -ruuvi Ruuvi Innovations Ltd (Oy) roseapplepi RoseapplePi.org +ruuvi Ruuvi Innovations Ltd (Oy) samsung Samsung Semiconductor samtec Samtec/Softing company sancloud Sancloud Ltd @@ -538,11 +562,12 @@ sandisk Sandisk Corporation satoz Satoz International Co., Ltd sbs Smart Battery System sc Space Cubics, LLC -sciosense Sciosense B.V. schindler Schindler +sciosense Sciosense B.V. seagate Seagate Technology PLC -segger SEGGER Microcontroller GmbH +seco SECO S.p.A. seeed Seeed Technology Co., Ltd +segger SEGGER Microcontroller GmbH seirobotics Shenzhen SEI Robotics Co., Ltd semtech Semtech Corporation sensirion Sensirion AG @@ -556,6 +581,7 @@ shimafuji Shimafuji Electric, Inc. shiratech Shiratech Solutions si-en Si-En Technology Ltd. si-linux Silicon Linux Corporation +siemens Siemens AG sifive SiFive, Inc. sigma Sigma Designs, Inc. sii Seiko Instruments, Inc. @@ -566,7 +592,7 @@ silergy Silergy Corp. silex-insight Silex Insight siliconfile Siliconfile Technologies lnc. siliconmitus Silicon Mitus, Inc. -siemens Siemens AG +silvaco Silvaco, Inc. simcom SIMCom Wireless Solutions Co., LTD simtek Cypress Semiconductor Corporation (Simtek Corporation) sinlinx Sinlinx Electronics Technology Co., LTD @@ -580,12 +606,13 @@ skyworks Skyworks Solutions, Inc. smartlabs SmartLabs LLC smsc Standard Microsystems Corporation snps Synopsys, Inc. -starfive StarFive Technology Co. Ltd. sochip Shenzhen SoChip Technology Co., Ltd. socionext Socionext Inc. +solderparty Solder Party AB solidrun SolidRun solomon Solomon Systech Limited sony Sony Corporation +spacecubics Space Cubics, LLC spansion Spansion Inc. sparkfun SparkFun Electronics sprd Spreadtrum Communications Inc. @@ -593,16 +620,16 @@ sqn Sequans Communications sst Silicon Storage Technology, Inc. sstar Xiamen Xingchen(SigmaStar) Technology Co., Ltd. (formerly part of MStar Semiconductor, Inc.) st STMicroelectronics +st-ericsson ST-Ericsson +starfive StarFive Technology Co. Ltd. starry Starry Electronic Technology (ShenZhen) Co., LTD startek Startek ste ST-Ericsson stericsson ST-Ericsson -st-ericsson ST-Ericsson summit Summit microelectronics sunchip Shenzhen Sunchip Technology Co., Ltd -SUNW Sun Microsystems, Inc +sunw Sun Microsystems, Inc supermicro Super Micro Computer, Inc. -silvaco Silvaco, Inc. swir Sierra Wireless syna Synaptics Inc. synology Synology, Inc. @@ -615,10 +642,10 @@ tdk TDK Corporation. tdo Shangai Top Display Optoelectronics Co., Ltd technexion TechNexion technologic Technologic Systems +techstar Shenzhen Techstar Electronics Co., Ltd. telink Telink Semiconductor telit Telit Cinterion tempo Tempo Semiconductor -techstar Shenzhen Techstar Electronics Co., Ltd. terasic Terasic Inc. tfc Three Five Corp thine THine Electronics, Inc. @@ -641,13 +668,12 @@ tq TQ-Systems GmbH tronfy Tronfy tronsmart Tronsmart truly Truly Semiconductors Limited -visionox Visionox tsd Theobroma Systems Design und Consulting GmbH tyan Tyan Computer Corporation u-blox u-blox u-boot U-Boot bootloader -ucrobotics uCRobotics ubnt Ubiquiti Networks +ucrobotics uCRobotics udoo Udoo ugoos Ugoos Industrial Co., Ltd. ultrachip UltraChip Inc. @@ -660,15 +686,18 @@ v3 V3 Semiconductor vaisala Vaisala vamrs Vamrs Ltd. variscite Variscite Ltd. +vcc-gnd VCC-GND Studio vdl Van der Laan b.v. via VIA Technologies, Inc. videostrong Videostrong Technology Co., Ltd. virtio Virtual I/O Device Specification, developed by the OASIS consortium virtual Used for virtual device without specific vendor. vishay Vishay Intertechnology, Inc +visionox Visionox vitesse Vitesse Semiconductor Corporation vivante Vivante Corporation vnd A stand-in for a real vendor which can be used in examples and tests +vngiotlab VNGIoTLab vocore VoCore Studio voipac Voipac Technologies s.r.o. vot Vision Optical Technology Co., Ltd. @@ -678,6 +707,7 @@ waveshare Waveshare Electronics wd Western Digital Corp. we Würth Elektronik GmbH. weact WeAct Studio +wemos WEMOS Electronics wetek WeTek Electronics, limited. wexler Wexler whwave Shenzhen whwave Electronics, Inc. @@ -693,6 +723,7 @@ wnc Wistron NeWeb Corporation wobo Wobo wolfson Cirrus Logic, Inc. (formerly Wolfson Microelectronics plc) worldsemi Worldsemi Co., Limited +wurth Wurth Elektronik x-powers X-Powers xen Xen Hypervisor xes Extreme Engineering Solutions (X-ES) @@ -714,8 +745,8 @@ yna YSH & ATIL yones-toptech Yones Toptech Co., Ltd. ys Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. ysoft Y Soft Corporation a.s. -zealz Zealz zarlink Zarlink Semiconductor +zealz Zealz zeitec ZEITEC Semiconductor Co., LTD. zephyr Zephyr-specific binding zidoo Shenzhen Zidoo Technology Co., Ltd. @@ -724,3 +755,4 @@ zinitix Zinitix Co., Ltd zkmagic Shenzhen Zkmagic Technology Co., Ltd. zte ZTE Corp. zyxel ZyXEL Communications Corp. +# zephyr-keep-sorted-stop diff --git a/dts/x86/intel/ia32.dtsi b/dts/x86/intel/atom.dtsi similarity index 100% rename from dts/x86/intel/ia32.dtsi rename to dts/x86/intel/atom.dtsi diff --git a/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h b/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h index 2dc7e53b13e0c6..214b08b26f5f95 100644 --- a/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h +++ b/include/zephyr/drivers/pinctrl/pinctrl_soc_sam_common.h @@ -38,14 +38,14 @@ typedef uint32_t pinctrl_soc_pin_t; * @param prop Property name. * @param idx Property entry index. */ -#if defined(CONFIG_SOC_FAMILY_SAM) +#if defined(CONFIG_SOC_FAMILY_ATMEL_SAM) #define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ ((DT_PROP_BY_IDX(node_id, prop, idx) << SAM_PINCTRL_PINMUX_POS) \ | (DT_PROP(node_id, bias_pull_up) << SAM_PINCTRL_PULLUP_POS) \ | (DT_PROP(node_id, bias_pull_down) << SAM_PINCTRL_PULLDOWN_POS) \ | (DT_PROP(node_id, drive_open_drain) << SAM_PINCTRL_OPENDRAIN_POS) \ ), -#else /* CONFIG_SOC_FAMILY_SAM0 */ +#else /* CONFIG_SOC_FAMILY_ATMEL_SAM0 */ #define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ ((DT_PROP_BY_IDX(node_id, prop, idx) << SAM_PINCTRL_PINMUX_POS) \ | (DT_PROP(node_id, bias_pull_up) << SAM_PINCTRL_PULLUP_POS) \ diff --git a/modules/Kconfig.atmel b/modules/Kconfig.atmel index 980762585dd494..a5605146ad9994 100644 --- a/modules/Kconfig.atmel +++ b/modules/Kconfig.atmel @@ -6,7 +6,7 @@ config ASF bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_SAM || SOC_FAMILY_SAM0 + depends on SOC_FAMILY_ATMEL_SAM || SOC_FAMILY_ATMEL_SAM0 config ATMEL_WINC1500 bool diff --git a/modules/Kconfig.esp32 b/modules/Kconfig.esp32 index 4022f7534b0324..eec39d1dbf77bd 100644 --- a/modules/Kconfig.esp32 +++ b/modules/Kconfig.esp32 @@ -3,4 +3,4 @@ config HAS_ESPRESSIF_HAL bool - depends on SOC_FAMILY_ESP32 + depends on SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/modules/Kconfig.imx b/modules/Kconfig.imx index 5b387f1e9a54c3..80e4b3434a54d8 100644 --- a/modules/Kconfig.imx +++ b/modules/Kconfig.imx @@ -6,7 +6,7 @@ config HAS_IMX_HAL bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_IMX + depends on SOC_FAMILY_NXP_IMX if HAS_IMX_HAL diff --git a/modules/Kconfig.infineon b/modules/Kconfig.infineon index 7ca374f4f32a4d..fc39318c8b2002 100644 --- a/modules/Kconfig.infineon +++ b/modules/Kconfig.infineon @@ -6,7 +6,7 @@ config HAS_XMCLIB bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_XMC + depends on SOC_FAMILY_INFINEON_XMC if HAS_XMCLIB diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index fb5b18a63d3f0d..21658c1ebd0759 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -5,11 +5,16 @@ config HAS_MCUX bool - depends on SOC_FAMILY_KINETIS || SOC_FAMILY_IMX || SOC_FAMILY_LPC || \ - SOC_FAMILY_NXP_ADSP || SOC_FAMILY_NXP_S32 - + depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \ + SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT if HAS_MCUX +config MCUX_CORE_SUFFIX + string + help + String describing the core identifer used by MCUX SDK when using + dual core parts + config HAS_MCUX_12B1MSPS_SAR bool help diff --git a/modules/Kconfig.silabs b/modules/Kconfig.silabs index 8abab8b1dd73ce..0078bfc0b98794 100644 --- a/modules/Kconfig.silabs +++ b/modules/Kconfig.silabs @@ -6,4 +6,4 @@ config HAS_SILABS_GECKO bool select HAS_CMSIS_CORE - depends on SOC_FAMILY_EXX32 + depends on SOC_VENDOR_SILABS diff --git a/modules/Kconfig.vega b/modules/Kconfig.vega index 2e4fbf01cad08a..ba16ae5c523382 100644 --- a/modules/Kconfig.vega +++ b/modules/Kconfig.vega @@ -3,7 +3,7 @@ config VEGA_SDK_HAL bool "RV32M1 VEGA SDK support" - depends on SOC_OPENISA_RV32M1_RISCV32 + depends on SOC_OPENISA_RV32M1 config HAS_RV32M1_LPUART bool diff --git a/modules/hal_nxp/CMakeLists.txt b/modules/hal_nxp/CMakeLists.txt index 01e6d58ccae8a2..2f2e53d22ea85c 100644 --- a/modules/hal_nxp/CMakeLists.txt +++ b/modules/hal_nxp/CMakeLists.txt @@ -15,4 +15,12 @@ if(CONFIG_HAS_MCUX OR CONFIG_HAS_IMX_HAL OR CONFIG_HAS_NXP_S32_HAL) zephyr_compile_definitions_ifdef(CONFIG_CAN_MCUX_FLEXCAN FLEXCAN_WAIT_TIMEOUT=${CONFIG_CAN_MCUX_FLEXCAN_WAIT_TIMEOUT}) + + if(CONFIG_CPU_HAS_DCACHE) + zephyr_compile_definitions_ifdef(CONFIG_ENTROPY_MCUX_CAAM CACHE_MODE_WRITE_THROUGH) + endif() + + if(CONFIG_NOCACHE_MEMORY) + zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER DATA_SECTION_IS_CACHEABLE=1) + endif() endif() diff --git a/modules/trusted-firmware-m/CMakeLists.txt b/modules/trusted-firmware-m/CMakeLists.txt index 2ca875c4df2384..146d17512032c1 100644 --- a/modules/trusted-firmware-m/CMakeLists.txt +++ b/modules/trusted-firmware-m/CMakeLists.txt @@ -201,7 +201,7 @@ if (CONFIG_BUILD_WITH_TFM) ${TFM_INTERFACE_SOURCE_DIR}/tfm_ps_api.c ${TFM_INTERFACE_SOURCE_DIR}/tfm_tz_psa_ns_api.c - # Specific to nordic_nrf platform + # Specific to nordic platform ${TFM_INTERFACE_SOURCE_DIR}/tfm_ioctl_core_ns_api.c ) @@ -226,7 +226,7 @@ if (CONFIG_BUILD_WITH_TFM) string(REPLACE "toolchain" "toolchain_ns" TFM_TOOLCHAIN_NS_FILE ${TFM_TOOLCHAIN_FILE}) - if(CONFIG_BOARD_LPCXPRESSO55S69_CPU0) + if(CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0) # Supply path to NXP HAL sources used for TF-M build set(TFM_PLATFORM_NXP_HAL_FILE_PATH ${ZEPHYR_TRUSTED_FIRMWARE_M_MODULE_DIR}/platform/ext/target/nxp/) list(APPEND TFM_CMAKE_ARGS -DTFM_PLATFORM_NXP_HAL_FILE_PATH=${TFM_PLATFORM_NXP_HAL_FILE_PATH}) @@ -358,7 +358,7 @@ if (CONFIG_BUILD_WITH_TFM) zephyr_library_sources(${TFM_INTERFACE_SOURCE_DIR}/tfm_tz_psa_ns_api.c) - if(CONFIG_SOC_FAMILY_NRF) + if(CONFIG_SOC_FAMILY_NORDIC_NRF) zephyr_library_sources_ifdef(CONFIG_TFM_PARTITION_PLATFORM ${TFM_INTERFACE_SOURCE_DIR}/tfm_ioctl_core_ns_api.c) endif() diff --git a/modules/trusted-firmware-m/Kconfig.tfm b/modules/trusted-firmware-m/Kconfig.tfm index 277dd8a8d09cbe..6d3b8a40c04b6c 100644 --- a/modules/trusted-firmware-m/Kconfig.tfm +++ b/modules/trusted-firmware-m/Kconfig.tfm @@ -9,17 +9,17 @@ config ZEPHYR_TRUSTED_FIRMWARE_M_MODULE config TFM_BOARD string - default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_CPU0 + default "nxp/lpcxpresso55s69" if BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 default "arm/mps2/an521" if BOARD_MPS2_AN521_CPU0_NS default "arm/mps3/an547" if BOARD_MPS3_AN547 default "stm/b_u585i_iot02a" if BOARD_B_U585I_IOT02A default "stm/nucleo_l552ze_q" if BOARD_NUCLEO_L552ZE_Q default "stm/stm32l562e_dk" if BOARD_STM32L562E_DK - default "arm/musca_b1" if BOARD_MUSCA_B1 - default "arm/musca_s1" if BOARD_MUSCA_S1 - default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic_nrf/nrf9160" if SOC_NRF9160 - default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic_nrf/nrf9120" if SOC_NRF9120 - default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP + default "arm/musca_b1" if BOARD_V2M_MUSCA_B1 + default "arm/musca_s1" if BOARD_V2M_MUSCA_S1 + default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf9160" if SOC_NRF9160 + default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf9120" if SOC_NRF9120 + default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP help The board name used for building TFM. Building with TFM requires that TFM has been ported to the given board/SoC. @@ -43,7 +43,7 @@ menuconfig BUILD_WITH_TFM them, are generated during the normal Zephyr build process. Notes: - Building with the "_ns" BOARD variant (e.g. "mps2_an521_ns") + Building with the "/ns" BOARD variant (e.g. "mps2/an521/cpu0/ns") ensures that CONFIG_TRUSTED_EXECUTION_NONSECURE is enabled. By default we allow Zephyr preemptible threads be preempted diff --git a/modules/trusted-firmware-m/nordic_nrf/CMakeLists.txt b/modules/trusted-firmware-m/nordic/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/include/RTE_Device.h b/modules/trusted-firmware-m/nordic/include/RTE_Device.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/RTE_Device.h rename to modules/trusted-firmware-m/nordic/include/RTE_Device.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/device_cfg.h b/modules/trusted-firmware-m/nordic/include/device_cfg.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/device_cfg.h rename to modules/trusted-firmware-m/nordic/include/device_cfg.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/tfm_ioctl_api.h b/modules/trusted-firmware-m/nordic/include/tfm_ioctl_api.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/tfm_ioctl_api.h rename to modules/trusted-firmware-m/nordic/include/tfm_ioctl_api.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/tfm_peripherals_config.h b/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/tfm_peripherals_config.h rename to modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/tfm_read_ranges.h b/modules/trusted-firmware-m/nordic/include/tfm_read_ranges.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/tfm_read_ranges.h rename to modules/trusted-firmware-m/nordic/include/tfm_read_ranges.h diff --git a/modules/trusted-firmware-m/nordic_nrf/include/util/array.h b/modules/trusted-firmware-m/nordic/include/util/array.h similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/include/util/array.h rename to modules/trusted-firmware-m/nordic/include/util/array.h diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/config.cmake b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/config.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/config.cmake rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/config.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/cpuarch.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/cpuarch.cmake rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/cpuarch.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf5340_cpuapp/ns/cpuarch_ns.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf5340_cpuapp/ns/cpuarch_ns.cmake rename to modules/trusted-firmware-m/nordic/nrf5340_cpuapp/ns/cpuarch_ns.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf9120/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/nrf9120/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/config.cmake b/modules/trusted-firmware-m/nordic/nrf9120/config.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/config.cmake rename to modules/trusted-firmware-m/nordic/nrf9120/config.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf9120/cpuarch.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/cpuarch.cmake rename to modules/trusted-firmware-m/nordic/nrf9120/cpuarch.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9120/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf9120/ns/cpuarch_ns.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9120/ns/cpuarch_ns.cmake rename to modules/trusted-firmware-m/nordic/nrf9120/ns/cpuarch_ns.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf9160/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/nrf9160/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/config.cmake b/modules/trusted-firmware-m/nordic/nrf9160/config.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/config.cmake rename to modules/trusted-firmware-m/nordic/nrf9160/config.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf9160/cpuarch.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/cpuarch.cmake rename to modules/trusted-firmware-m/nordic/nrf9160/cpuarch.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/nrf9160/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf9160/ns/cpuarch_ns.cmake similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/nrf9160/ns/cpuarch_ns.cmake rename to modules/trusted-firmware-m/nordic/nrf9160/ns/cpuarch_ns.cmake diff --git a/modules/trusted-firmware-m/nordic_nrf/ns/CMakeLists.txt b/modules/trusted-firmware-m/nordic/ns/CMakeLists.txt similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/ns/CMakeLists.txt rename to modules/trusted-firmware-m/nordic/ns/CMakeLists.txt diff --git a/modules/trusted-firmware-m/nordic_nrf/src/tfm_hal_platform.c b/modules/trusted-firmware-m/nordic/src/tfm_hal_platform.c similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/src/tfm_hal_platform.c rename to modules/trusted-firmware-m/nordic/src/tfm_hal_platform.c diff --git a/modules/trusted-firmware-m/nordic_nrf/src/tfm_platform_system.c b/modules/trusted-firmware-m/nordic/src/tfm_platform_system.c similarity index 100% rename from modules/trusted-firmware-m/nordic_nrf/src/tfm_platform_system.c rename to modules/trusted-firmware-m/nordic/src/tfm_platform_system.c diff --git a/samples/application_development/code_relocation_nocopy/README.rst b/samples/application_development/code_relocation_nocopy/README.rst index 8ad98bb8af7a77..f8ac178a7e94df 100644 --- a/samples/application_development/code_relocation_nocopy/README.rst +++ b/samples/application_development/code_relocation_nocopy/README.rst @@ -27,7 +27,7 @@ To build and flash the application (including the external memory part): .. zephyr-app-commands:: :zephyr-app: samples/application_development/code_relocation_nocopy - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build flash :compact: @@ -41,4 +41,4 @@ Execution output: Address of var_ext_sram_data 0x200000a0 (10) Address of function_in_sram 0x20000001 Address of var_sram_data 0x200000a4 (10) - Hello World! nrf5340dk_nrf5340_cpuapp + Hello World! nrf5340dk/nrf5340/cpuapp diff --git a/samples/application_development/code_relocation_nocopy/sample.yaml b/samples/application_development/code_relocation_nocopy/sample.yaml index 2504f0838c94d1..b9415221e24680 100644 --- a/samples/application_development/code_relocation_nocopy/sample.yaml +++ b/samples/application_development/code_relocation_nocopy/sample.yaml @@ -5,7 +5,7 @@ tests: sample.application_development.code_relocation_nocopy: platform_allow: - qemu_cortex_m3 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp integration_platforms: - qemu_cortex_m3 tags: linker diff --git a/samples/application_development/sysbuild/with_mcuboot/README.rst b/samples/application_development/sysbuild/with_mcuboot/README.rst index 293236146bb07a..2f9078cab9c761 100644 --- a/samples/application_development/sysbuild/with_mcuboot/README.rst +++ b/samples/application_development/sysbuild/with_mcuboot/README.rst @@ -45,7 +45,7 @@ Execution output: *** Booting Zephyr OS build v3.2.0-rc3-209-gdcf4201d3573 *** *** Booting Zephyr OS build v3.2.0-rc3-209-gdcf4201d3573 *** Address of sample 0xc000 - Hello sysbuild with mcuboot! nrf52840dk_nrf52840 + Hello sysbuild with mcuboot! nrf52840dk The first ``Booting Zephyr OS build`` is printed by MCUboot itself and the following lines are printed by the ``with_mcuboot`` sample. diff --git a/samples/application_development/sysbuild/with_mcuboot/sample.yaml b/samples/application_development/sysbuild/with_mcuboot/sample.yaml index 90aea4e0541a99..785bc0d24004d0 100644 --- a/samples/application_development/sysbuild/with_mcuboot/sample.yaml +++ b/samples/application_development/sysbuild/with_mcuboot/sample.yaml @@ -8,9 +8,9 @@ tests: # filtering support, see discussion in #49552. platform_allow: - reel_board - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: mcuboot harness: console harness_config: diff --git a/samples/arch/smp/pktqueue/sample.yaml b/samples/arch/smp/pktqueue/sample.yaml index 890d36653d6200..f819e6ce576e8e 100644 --- a/samples/arch/smp/pktqueue/sample.yaml +++ b/samples/arch/smp/pktqueue/sample.yaml @@ -18,13 +18,5 @@ tests: depends_on: - smp filter: (CONFIG_MP_MAX_NUM_CPUS > 1) - platform_exclude: - - esp32_devkitc_wroom - - esp_wrover_kit - - esp32_ethernet_kit - - heltec_wifi_lora32_v2 - - m5stickc_plus - - odroid_go - - olimex_esp32_evb integration_platforms: - qemu_x86_64 diff --git a/samples/basic/blinky_pwm/README.rst b/samples/basic/blinky_pwm/README.rst index f31c65982fbc4c..5999e9063b4805 100644 --- a/samples/basic/blinky_pwm/README.rst +++ b/samples/basic/blinky_pwm/README.rst @@ -67,11 +67,11 @@ To build and flash this sample for the :ref:`nrf52840dk_nrf52840`: .. zephyr-app-commands:: :zephyr-app: samples/basic/blinky_pwm - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: -Change ``nrf52840dk_nrf52840`` appropriately for other supported boards. +Change ``nrf52840dk/nrf52840`` appropriately for other supported boards. After flashing, the sample starts blinking the LED as described above. It also prints information to the board's console. diff --git a/samples/basic/blinky_pwm/boards/mimxrt685_evk_cm33.overlay b/samples/basic/blinky_pwm/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/mimxrt685_evk_cm33.overlay rename to samples/basic/blinky_pwm/boards/mimxrt685_evk.overlay diff --git a/samples/basic/blinky_pwm/boards/rcar_h3ulcb_cr7.overlay b/samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay similarity index 100% rename from samples/basic/blinky_pwm/boards/rcar_h3ulcb_cr7.overlay rename to samples/basic/blinky_pwm/boards/rcar_h3ulcb_r8a77951_r7.overlay diff --git a/samples/basic/blinky_pwm/boards/rpi_pico.overlay b/samples/basic/blinky_pwm/boards/rpi_pico.overlay index c3a3f1ff5d3913..2487fc181f1b84 100644 --- a/samples/basic/blinky_pwm/boards/rpi_pico.overlay +++ b/samples/basic/blinky_pwm/boards/rpi_pico.overlay @@ -1,3 +1,11 @@ +/* The rpi_pico/rp2040/w doesn't have a pwm. */ +/* Use the HAS_DT_PWM defined by the based board to identify when this overlay is valid */ +#if HAS_DT_PWM_LED + +&{/pwm_leds} { + status = "okay"; +}; + &pwm_led0 { status = "okay"; }; @@ -7,3 +15,5 @@ divider-frac-4 = <15>; divider-int-4 = <255>; }; + +#endif diff --git a/samples/basic/button/sample.yaml b/samples/basic/button/sample.yaml index b0c748d6be25bc..b2d76330fcf588 100644 --- a/samples/basic/button/sample.yaml +++ b/samples/basic/button/sample.yaml @@ -7,6 +7,6 @@ tests: - gpio filter: dt_enabled_alias_with_parent_compat("sw0", "gpio-keys") integration_platforms: - - nrf52833dk_nrf52820 + - nrf52833dk/nrf52820 depends_on: gpio harness: button diff --git a/samples/basic/fade_led/README.rst b/samples/basic/fade_led/README.rst index 4e855548704662..2b569f6d5a5ade 100644 --- a/samples/basic/fade_led/README.rst +++ b/samples/basic/fade_led/README.rst @@ -28,11 +28,11 @@ To build and flash this sample for the :ref:`nrf52840dk_nrf52840`: .. zephyr-app-commands:: :zephyr-app: samples/basic/fade_led - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: -Change ``nrf52840dk_nrf52840`` appropriately for other supported boards. +Change ``nrf52840dk/nrf52840`` appropriately for other supported boards. After flashing, the sample starts fading the LED as described above. It also prints information to the board's console. diff --git a/samples/basic/fade_led/sample.yaml b/samples/basic/fade_led/sample.yaml index f141f4abfc35f7..eae1afefe5b483 100644 --- a/samples/basic/fade_led/sample.yaml +++ b/samples/basic/fade_led/sample.yaml @@ -9,4 +9,4 @@ tests: harness: led filter: dt_alias_exists("pwm-led0") and dt_compat_enabled("pwm-leds") integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/samples/basic/hash_map/sample.yaml b/samples/basic/hash_map/sample.yaml index 9e1ee6558cab54..dad9af8a994b9d 100644 --- a/samples/basic/hash_map/sample.yaml +++ b/samples/basic/hash_map/sample.yaml @@ -10,7 +10,7 @@ common: min_ram: 24 integration_platforms: - qemu_x86_64 - - mps2_an385 + - mps2/an385 harness: console harness_config: type: one_line diff --git a/samples/basic/minimal/sample.yaml b/samples/basic/minimal/sample.yaml index ed934859f37a4b..54e0d718bdc461 100644 --- a/samples/basic/minimal/sample.yaml +++ b/samples/basic/minimal/sample.yaml @@ -15,8 +15,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 integration_platforms: @@ -27,8 +27,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.mt-no-preempt-no-timers.arm: @@ -37,8 +37,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.no-mt.arm: @@ -47,8 +47,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.no-mt-no-timers.arm: @@ -57,8 +57,8 @@ tests: platform_allow: - reel_board - frdm_k64f - - mps2_an385 - - nrf51dk_nrf51422 + - mps2/an385 + - nrf51dk/nrf51822 - nucleo_f429zi - disco_l475_iot1 sample.minimal.mt.x86: @@ -88,7 +88,7 @@ tests: tags: - kernel integration_platforms: - - qemu_arc_em + - qemu_arc/qemu_arc_em sample.minimal.riscv.runtime: extra_args: - CONF_FILE='common-runtime.conf;no-timers.conf;no-mt.conf;riscv.conf' diff --git a/samples/basic/rgb_led/README.rst b/samples/basic/rgb_led/README.rst index 11cc5d6e646f79..b3dca648d5704a 100644 --- a/samples/basic/rgb_led/README.rst +++ b/samples/basic/rgb_led/README.rst @@ -39,7 +39,7 @@ an unsupported board: Unsupported board: green-pwm-led devicetree alias is not defined Unsupported board: blue-pwm-led devicetree alias is not defined -See :zephyr_file:`boards/arm/hexiwear_k64/hexiwear_k64.dts` for an example +See :zephyr_file:`boards/nxp/hexiwear/hexiwear_mk64f12.dts` for an example :file:`BOARD.dts` file which supports this sample. Wiring @@ -53,12 +53,12 @@ Otherwise, LEDs should be connected to the appropriate PWM channels. Building and Running ******************** -For example, to build and flash this board for :ref:`hexiwear_k64`: +For example, to build and flash this board for :ref:`hexiwear`: .. zephyr-app-commands:: :zephyr-app: samples/basic/rgb_led - :board: hexiwear_k64 + :board: hexiwear/mk64f12 :goals: build flash :compact: -Change ``hexiwear_k64`` appropriately for other supported boards. +Change ``hexiwear/mk64f12`` appropriately for other supported boards. diff --git a/samples/basic/threads/README.rst b/samples/basic/threads/README.rst index 1ade8e9d360927..f58c886fdd2569 100644 --- a/samples/basic/threads/README.rst +++ b/samples/basic/threads/README.rst @@ -47,8 +47,8 @@ For example, to build this sample for :ref:`96b_carbon_board`: .. zephyr-app-commands:: :zephyr-app: samples/basic/threads - :board: 96b_carbon + :board: 96b_carbon/stm32f401xe :goals: build flash :compact: -Change ``96b_carbon`` appropriately for other supported boards. +Change ``96b_carbon/stm32f401xe`` appropriately for other supported boards. diff --git a/samples/basic/threads/sample.yaml b/samples/basic/threads/sample.yaml index d76669c9263d18..0d3acce55fd2dd 100644 --- a/samples/basic/threads/sample.yaml +++ b/samples/basic/threads/sample.yaml @@ -10,7 +10,7 @@ tests: filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") and dt_enabled_alias_with_parent_compat("led1", "gpio-leds") integration_platforms: - - nrf52833dk_nrf52820 + - nrf52833dk/nrf52820 depends_on: gpio harness: console harness_config: diff --git a/samples/bluetooth/beacon/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/beacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/beacon/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/beacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/beacon/sample.yaml b/samples/bluetooth/beacon/sample.yaml index 062c71f7259273..9073de8c1fc0fb 100644 --- a/samples/bluetooth/beacon/sample.yaml +++ b/samples/bluetooth/beacon/sample.yaml @@ -6,7 +6,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 @@ -14,5 +14,5 @@ tests: sample.bluetooth.beacon-coex: extra_args: CONF_FILE="prj-coex.conf" harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/bluetooth.rst b/samples/bluetooth/bluetooth.rst index 0b59b9626b4ea8..35b49bfd0abfcd 100644 --- a/samples/bluetooth/bluetooth.rst +++ b/samples/bluetooth/bluetooth.rst @@ -17,8 +17,8 @@ documentation and are prefixed with :literal:`hci_` in their folder names. .. note:: If you want to run any bluetooth sample on the nRF5340 device (build using - ``-DBOARD=nrf5340dk_nrf5340_cpuapp`` or - ``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns``) you must also build + ``-DBOARD=nrf5340dk/nrf5340/cpuapp`` or + ``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns``) you must also build and program the corresponding sample for the nRF5340 network core :ref:`bluetooth-hci-ipc-sample` which implements the Bluetooth Low Energy controller. diff --git a/samples/bluetooth/broadcast_audio_assistant/README.rst b/samples/bluetooth/broadcast_audio_assistant/README.rst index faff37a6e2229e..e0a7ec5a0126d9 100644 --- a/samples/bluetooth/broadcast_audio_assistant/README.rst +++ b/samples/bluetooth/broadcast_audio_assistant/README.rst @@ -52,5 +52,5 @@ Building for an nrf52840dk .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_assistant/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build diff --git a/samples/bluetooth/broadcast_audio_assistant/sample.yaml b/samples/bluetooth/broadcast_audio_assistant/sample.yaml index 8481ebeeeb45f9..cc36702ac4d58d 100644 --- a/samples/bluetooth/broadcast_audio_assistant/sample.yaml +++ b/samples/bluetooth/broadcast_audio_assistant/sample.yaml @@ -5,7 +5,7 @@ tests: sample.bluetooth.broadcast_audio_assistant: harness: bluetooth platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild b/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild index f434010f81d27c..d609fd0ec854c7 100644 --- a/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild +++ b/samples/bluetooth/broadcast_audio_sink/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/broadcast_audio_sink/README.rst b/samples/bluetooth/broadcast_audio_sink/README.rst index aca5d18bb94a88..3c2d8d39d17998 100644 --- a/samples/bluetooth/broadcast_audio_sink/README.rst +++ b/samples/bluetooth/broadcast_audio_sink/README.rst @@ -41,7 +41,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -49,7 +49,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/broadcast_audio_sink/sample.yaml b/samples/bluetooth/broadcast_audio_sink/sample.yaml index e81b86de3e0b60..1df6e582baaecc 100644 --- a/samples/bluetooth/broadcast_audio_sink/sample.yaml +++ b/samples/bluetooth/broadcast_audio_sink/sample.yaml @@ -7,21 +7,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.broadcast_audio_sink.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild b/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild index f434010f81d27c..d609fd0ec854c7 100644 --- a/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild +++ b/samples/bluetooth/broadcast_audio_source/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/broadcast_audio_source/README.rst b/samples/bluetooth/broadcast_audio_source/README.rst index 1c36236231b77a..515eb64177ee60 100644 --- a/samples/bluetooth/broadcast_audio_source/README.rst +++ b/samples/bluetooth/broadcast_audio_source/README.rst @@ -40,7 +40,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -48,7 +48,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/broadcast_audio_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/broadcast_audio_source/sample.yaml b/samples/bluetooth/broadcast_audio_source/sample.yaml index 3c55480340933b..4df6ed34f5403b 100644 --- a/samples/bluetooth/broadcast_audio_source/sample.yaml +++ b/samples/bluetooth/broadcast_audio_source/sample.yaml @@ -7,23 +7,23 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.broadcast_audio_source.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 - - nrf52840dongle_nrf52840 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 + - nrf52840dongle/nrf52840 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 - - nrf52840dongle_nrf52840 + - nrf52833dk/nrf52833 + - nrf52840dongle/nrf52840 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/broadcaster/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/broadcaster/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/broadcaster/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/broadcaster/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/broadcaster/sample.yaml b/samples/bluetooth/broadcaster/sample.yaml index d0ee925d9c7970..7556e2aba7f577 100644 --- a/samples/bluetooth/broadcaster/sample.yaml +++ b/samples/bluetooth/broadcaster/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/broadcaster_multiple/sample.yaml b/samples/bluetooth/broadcaster_multiple/sample.yaml index a3b95d629460f8..96e274f5514a48 100644 --- a/samples/bluetooth/broadcaster_multiple/sample.yaml +++ b/samples/bluetooth/broadcaster_multiple/sample.yaml @@ -6,9 +6,9 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/central/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/central/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/central/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/central/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/central_hr/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/central_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/central_hr/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/central_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/central_ht/sample.yaml b/samples/bluetooth/central_ht/sample.yaml index b9838607cad987..f41b2289705765 100644 --- a/samples/bluetooth/central_ht/sample.yaml +++ b/samples/bluetooth/central_ht/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/central_multilink/sample.yaml b/samples/bluetooth/central_multilink/sample.yaml index 112533a784f655..bca1027d37f652 100644 --- a/samples/bluetooth/central_multilink/sample.yaml +++ b/samples/bluetooth/central_multilink/sample.yaml @@ -6,7 +6,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_cortex_m3 tags: bluetooth diff --git a/samples/bluetooth/central_otc/sample.yaml b/samples/bluetooth/central_otc/sample.yaml index ac49056252f6cd..4d7221bd653362 100644 --- a/samples/bluetooth/central_otc/sample.yaml +++ b/samples/bluetooth/central_otc/sample.yaml @@ -4,9 +4,9 @@ tests: sample.bluetooth.central_otc: harness: bluetooth platform_allow: - - nrf21540dk_nrf52840 - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf21540dk/nrf52840 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 tags: bluetooth integration_platforms: - - nrf21540dk_nrf52840 + - nrf21540dk/nrf52840 diff --git a/samples/bluetooth/direction_finding_central/README.rst b/samples/bluetooth/direction_finding_central/README.rst index 07a5d1c52be976..1a6d6519dcf6bd 100644 --- a/samples/bluetooth/direction_finding_central/README.rst +++ b/samples/bluetooth/direction_finding_central/README.rst @@ -26,12 +26,12 @@ Building and Running By default the application supports Angle of Arrival and Angle of Departure mode. To use Angle of Departure mode only, build this application as follows, -changing ``nrf52833dk_nrf52833`` as needed for your board: +changing ``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_central :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aod.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_central/sample.yaml b/samples/bluetooth/direction_finding_central/sample.yaml index e46c5b623a1373..b0c94537b518b2 100644 --- a/samples/bluetooth/direction_finding_central/sample.yaml +++ b/samples/bluetooth/direction_finding_central/sample.yaml @@ -6,23 +6,23 @@ tests: sample.bluetooth.direction_finding.central: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding.central.aod: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aod.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/direction_finding_connectionless_rx/README.rst b/samples/bluetooth/direction_finding_connectionless_rx/README.rst index ad8416dd5376a8..c9380c6e7e6bca 100644 --- a/samples/bluetooth/direction_finding_connectionless_rx/README.rst +++ b/samples/bluetooth/direction_finding_connectionless_rx/README.rst @@ -26,12 +26,12 @@ Building and Running By default the application supports Angle of Arrival and Angle of Departure mode. To use Angle of Departure mode only, build this application as follows, -changing ``nrf52833dk_nrf52833`` as needed for your board: +changing ``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_connectionless_rx :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aod.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml b/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml index 4aa2f2f76eabb9..1c79df412757ab 100644 --- a/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml +++ b/samples/bluetooth/direction_finding_connectionless_rx/sample.yaml @@ -4,22 +4,22 @@ tests: sample.bluetooth.direction_finding_connectionless_rx: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding_connectionless_rx.aod: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aod.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/direction_finding_connectionless_tx/README.rst b/samples/bluetooth/direction_finding_connectionless_tx/README.rst index 6fe3dd68722b50..8ccd97d9251a92 100644 --- a/samples/bluetooth/direction_finding_connectionless_tx/README.rst +++ b/samples/bluetooth/direction_finding_connectionless_tx/README.rst @@ -26,12 +26,12 @@ By default the application supports Angle of Arrival (AoA) and Angle of Departure (AoD) mode. To use Angle of Arrival mode only, build this application as follows, changing -``nrf52833dk_nrf52833`` as needed for your board: +``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_connectionless_tx :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aoa.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml b/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml index 06b29cb3e315e3..1ea189f5088530 100644 --- a/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml +++ b/samples/bluetooth/direction_finding_connectionless_tx/sample.yaml @@ -4,22 +4,22 @@ tests: sample.bluetooth.direction_finding_connectionless: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding_connectionless.aoa: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aoa.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/direction_finding_peripheral/README.rst b/samples/bluetooth/direction_finding_peripheral/README.rst index 75cc5b9a917684..68d709173d9855 100644 --- a/samples/bluetooth/direction_finding_peripheral/README.rst +++ b/samples/bluetooth/direction_finding_peripheral/README.rst @@ -25,12 +25,12 @@ Building and Running By default the application supports Angle of Arrival and Angle of Departure mode. To use Angle of Arrival mode only, build this application as follows, -changing ``nrf52833dk_nrf52833`` as needed for your board: +changing ``nrf52833dk/nrf52833`` as needed for your board: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/direction_finding_peripheral :host-os: unix - :board: nrf52833dk_nrf52833 + :board: nrf52833dk/nrf52833 :gen-args: -DEXTRA_CONF_FILE=overlay-aoa.conf :goals: build flash :compact: diff --git a/samples/bluetooth/direction_finding_peripheral/sample.yaml b/samples/bluetooth/direction_finding_peripheral/sample.yaml index 71e00710ef532f..126355a735f518 100644 --- a/samples/bluetooth/direction_finding_peripheral/sample.yaml +++ b/samples/bluetooth/direction_finding_peripheral/sample.yaml @@ -6,23 +6,23 @@ tests: sample.bluetooth.direction_finding.peripheral: harness: bluetooth platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp sample.bluetooth.direction_finding.peripheral.aod: harness: bluetooth extra_args: OVERLAY_CONFIG="overlay-aoa.conf" platform_allow: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp tags: bluetooth integration_platforms: - - nrf52833dk_nrf52833 - - nrf52833dk_nrf52820 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52833 + - nrf52833dk/nrf52820 + - nrf5340dk/nrf5340/cpuapp diff --git a/samples/bluetooth/eddystone/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/eddystone/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/eddystone/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/eddystone/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/encrypted_advertising/central/sample.yaml b/samples/bluetooth/encrypted_advertising/central/sample.yaml index b26b5f8ac2aef1..d14ef45444ba02 100644 --- a/samples/bluetooth/encrypted_advertising/central/sample.yaml +++ b/samples/bluetooth/encrypted_advertising/central/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.central_ead: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml b/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml index d948e618336748..94ff3ee3a9db20 100644 --- a/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml +++ b/samples/bluetooth/encrypted_advertising/peripheral/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.peripheral_ead: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/extended_adv/advertiser/sample.yaml b/samples/bluetooth/extended_adv/advertiser/sample.yaml index 06b723062ce7c4..b93a44f3180c87 100644 --- a/samples/bluetooth/extended_adv/advertiser/sample.yaml +++ b/samples/bluetooth/extended_adv/advertiser/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.extended_advertising.advertiser: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/extended_adv/scanner/sample.yaml b/samples/bluetooth/extended_adv/scanner/sample.yaml index 7cb06719dffca0..e9f72f20bcdaad 100644 --- a/samples/bluetooth/extended_adv/scanner/sample.yaml +++ b/samples/bluetooth/extended_adv/scanner/sample.yaml @@ -3,5 +3,5 @@ sample: tests: sample.bluetooth.extended_advertising.scanner: harness: bluetooth - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/hci_ipc/sample.yaml b/samples/bluetooth/hci_ipc/sample.yaml index e05a5d384d214d..e0612025e6d784 100644 --- a/samples/bluetooth/hci_ipc/sample.yaml +++ b/samples/bluetooth/hci_ipc/sample.yaml @@ -6,91 +6,91 @@ tests: harness: bluetooth tags: bluetooth platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_broadcast.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_receive.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.bis.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_bis-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_central.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_central-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso_peripheral.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.cis.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_cis-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf5340_audio_dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet + - nrf5340_audio_dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.iso.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_iso-bt_ll_sw_split.conf" platform_allow: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.df.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: - CONF_FILE="nrf5340_cpunet_df-bt_ll_sw_split.conf" - DTC_OVERLAY_FILE="nrf5340_cpunet_df-bt_ll_sw_split.overlay" - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.df.no_phy_coded.bt_ll_sw_split: harness: bluetooth tags: bluetooth @@ -98,13 +98,13 @@ tests: - CONF_FILE="nrf5340_cpunet_df-bt_ll_sw_split.conf" - DTC_OVERLAY_FILE="nrf5340_cpunet_df-bt_ll_sw_split.overlay" - CONFIG_BT_CTLR_PHY_CODED=n - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet sample.bluetooth.hci_ipc.mesh.bt_ll_sw_split: harness: bluetooth tags: bluetooth extra_args: CONF_FILE="nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf" - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet diff --git a/samples/bluetooth/hci_pwr_ctrl/sample.yaml b/samples/bluetooth/hci_pwr_ctrl/sample.yaml index dc68b809a1b9b6..67733b7edd04e3 100644 --- a/samples/bluetooth/hci_pwr_ctrl/sample.yaml +++ b/samples/bluetooth/hci_pwr_ctrl/sample.yaml @@ -5,8 +5,8 @@ tests: harness: bluetooth platform_allow: - bbc_microbit - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 - qemu_cortex_m3 - qemu_x86 tags: bluetooth diff --git a/samples/bluetooth/hci_spi/boards/nrf51dk_nrf51422.overlay b/samples/bluetooth/hci_spi/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/bluetooth/hci_spi/boards/nrf51dk_nrf51422.overlay rename to samples/bluetooth/hci_spi/boards/nrf51dk_nrf51822.overlay diff --git a/samples/bluetooth/hci_spi/sample.yaml b/samples/bluetooth/hci_spi/sample.yaml index 25e86d93001214..37d66fdb80a11f 100644 --- a/samples/bluetooth/hci_spi/sample.yaml +++ b/samples/bluetooth/hci_spi/sample.yaml @@ -5,11 +5,11 @@ tests: sample.bluetooth.hci_spi: harness: bluetooth platform_allow: - - 96b_carbon_nrf51 - - nrf51dk_nrf51422 + - 96b_carbon/nrf51822 + - nrf51dk/nrf51822 integration_platforms: - - 96b_carbon_nrf51 - - nrf51dk_nrf51422 + - 96b_carbon/nrf51822 + - nrf51dk/nrf51822 tags: - bluetooth - spi diff --git a/samples/bluetooth/hci_uart/README.rst b/samples/bluetooth/hci_uart/README.rst index 0beb105035d82a..a7a82fc8d01d0e 100644 --- a/samples/bluetooth/hci_uart/README.rst +++ b/samples/bluetooth/hci_uart/README.rst @@ -50,7 +50,7 @@ For example, to build for the nRF52832 Development Kit: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/hci_uart - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash .. _bluetooth-hci-uart-qemu-posix: @@ -135,12 +135,12 @@ required hardware configuration for the Radio. .. code-block:: console - west build samples/bluetooth/hci_uart -b nrf52833dk_nrf52833@df -- -DCONFIG_BT_CTLR_DF=y + west build samples/bluetooth/hci_uart -b nrf52833dk/nrf52833@df -- -DCONFIG_BT_CTLR_DF=y You can use following targets: -* ``nrf5340dk_nrf5340_cpunet@df`` -* ``nrf52833dk_nrf52833@df`` +* ``nrf5340dk/nrf5340/cpunet@df`` +* ``nrf52833dk/nrf52833@df`` Check the :ref:`bluetooth_direction_finding_connectionless_rx` and the :ref:`bluetooth_direction_finding_connectionless_tx` for more details. diff --git a/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.conf b/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.conf similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.conf rename to samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.conf diff --git a/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.overlay b/samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dk_nrf51422.overlay rename to samples/bluetooth/hci_uart/boards/nrf51dk_nrf51822.overlay diff --git a/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.conf b/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.conf similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.conf rename to samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.conf diff --git a/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.overlay b/samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51422.overlay rename to samples/bluetooth/hci_uart/boards/nrf51dongle_nrf51822.overlay diff --git a/samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.conf b/samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.conf similarity index 100% rename from samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.conf rename to samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.conf diff --git a/samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/hci_uart/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/hci_uart/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/hci_uart/sample.yaml b/samples/bluetooth/hci_uart/sample.yaml index c24ae0f68f5394..033a16c0cb143c 100644 --- a/samples/bluetooth/hci_uart/sample.yaml +++ b/samples/bluetooth/hci_uart/sample.yaml @@ -5,13 +5,13 @@ tests: sample.bluetooth.hci_uart.nrf5: harness: bluetooth platform_allow: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: - uart - bluetooth sample.bluetooth.hci_uart.nrf52833.df: harness: bluetooth - platform_allow: nrf52833dk_nrf52833 + platform_allow: nrf52833dk/nrf52833 extra_args: DTC_OVERLAY_FILE=./boards/nrf52833dk_nrf52833_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -20,7 +20,7 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf5340_netcore.df: harness: bluetooth - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet extra_args: DTC_OVERLAY_FILE=./boards/nrf5340dk_nrf5340_cpunet_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -29,7 +29,7 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf52833.df.iq_report: harness: bluetooth - platform_allow: nrf52833dk_nrf52833 + platform_allow: nrf52833dk/nrf52833 extra_args: DTC_OVERLAY_FILE=./boards/nrf52833dk_nrf52833_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -39,7 +39,7 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf5340_netcore.df.iq_report: harness: bluetooth - platform_allow: nrf5340dk_nrf5340_cpunet + platform_allow: nrf5340dk/nrf5340/cpunet extra_args: DTC_OVERLAY_FILE=./boards/nrf5340dk_nrf5340_cpunet_df.overlay extra_configs: - CONFIG_BT_CTLR_DF=y @@ -49,9 +49,9 @@ tests: - bluetooth sample.bluetooth.hci_uart.nrf52833.all: harness: bluetooth - platform_allow: nrf52833dk_nrf52833 + platform_allow: nrf52833dk/nrf52833 integration_platforms: - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: - OVERLAY_CONFIG=overlay-all-bt_ll_sw_split.conf - DTC_OVERLAY_FILE=./boards/nrf52833dk_nrf52833_df.overlay diff --git a/samples/bluetooth/hci_uart_async/README.rst b/samples/bluetooth/hci_uart_async/README.rst index f5caf0f965d1e5..7dbb4bbbdb63c7 100644 --- a/samples/bluetooth/hci_uart_async/README.rst +++ b/samples/bluetooth/hci_uart_async/README.rst @@ -47,7 +47,7 @@ For example, to build for the nRF52832 Development Kit: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/hci_uart_async - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash .. _bluetooth-hci-uart-async-qemu-posix: diff --git a/samples/bluetooth/hci_uart_async/sample.yaml b/samples/bluetooth/hci_uart_async/sample.yaml index d0db2b90385eca..7faad998c6f434 100644 --- a/samples/bluetooth/hci_uart_async/sample.yaml +++ b/samples/bluetooth/hci_uart_async/sample.yaml @@ -13,7 +13,7 @@ tests: sample.bluetooth.hci_uart_async.nrf5: harness: bluetooth platform_allow: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: - uart - bluetooth diff --git a/samples/bluetooth/hci_usb/sample.yaml b/samples/bluetooth/hci_usb/sample.yaml index 9848aed2430c11..7e34cf68f53313 100644 --- a/samples/bluetooth/hci_usb/sample.yaml +++ b/samples/bluetooth/hci_usb/sample.yaml @@ -20,4 +20,4 @@ tests: - usb - bluetooth extra_args: CONF_FILE="usbd_next_prj.conf" - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 diff --git a/samples/bluetooth/hci_usb_h4/sample.yaml b/samples/bluetooth/hci_usb_h4/sample.yaml index afc6e2429cbc85..b8b9d6d91b6e02 100644 --- a/samples/bluetooth/hci_usb_h4/sample.yaml +++ b/samples/bluetooth/hci_usb_h4/sample.yaml @@ -10,4 +10,4 @@ tests: - usb - bluetooth # FIXME: exclude due to build error - platform_exclude: 96b_carbon stm32l562e_dk + platform_exclude: 96b_carbon/stm32f401xe stm32l562e_dk diff --git a/samples/bluetooth/ibeacon/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/ibeacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/ibeacon/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/ibeacon/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/ipsp/README.rst b/samples/bluetooth/ipsp/README.rst index 36da6dae4d7089..2ec160d2a2229b 100644 --- a/samples/bluetooth/ipsp/README.rst +++ b/samples/bluetooth/ipsp/README.rst @@ -18,7 +18,7 @@ Sample can be built and executed for the nRF52840 DK NRF52840 as follows: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/ipsp - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: @@ -27,7 +27,7 @@ To build a debug version, with logging and shell support, use the config file .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/ipsp - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: prj_dbg.conf :goals: build flash :compact: @@ -43,7 +43,7 @@ Building and Running for Linux kernels released before 4.12 .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/ipsp - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj_zep1656.conf" :goals: build flash :compact: diff --git a/samples/bluetooth/ipsp/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/ipsp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/ipsp/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/ipsp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/iso_broadcast/sample.yaml b/samples/bluetooth/iso_broadcast/sample.yaml index 0961f5621c0970..10fb481688c628 100644 --- a/samples/bluetooth/iso_broadcast/sample.yaml +++ b/samples/bluetooth/iso_broadcast/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - qemu_cortex_m3 tags: bluetooth @@ -17,8 +17,8 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/iso_broadcast_benchmark/sample.yaml b/samples/bluetooth/iso_broadcast_benchmark/sample.yaml index 0c22b5f597ac35..d9804ac7029e23 100644 --- a/samples/bluetooth/iso_broadcast_benchmark/sample.yaml +++ b/samples/bluetooth/iso_broadcast_benchmark/sample.yaml @@ -5,9 +5,9 @@ tests: sample.bluetooth.iso_broadcast_benchmark: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340_audio_dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340_audio_dk/nrf5340/cpuapp integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth diff --git a/samples/bluetooth/iso_connected_benchmark/sample.yaml b/samples/bluetooth/iso_connected_benchmark/sample.yaml index 7c7ca228c99b5a..fd4eb7d9615b4c 100644 --- a/samples/bluetooth/iso_connected_benchmark/sample.yaml +++ b/samples/bluetooth/iso_connected_benchmark/sample.yaml @@ -5,6 +5,6 @@ tests: sample.bluetooth.iso_connected_benchmark: build_only: true platform_allow: - - nrf5340dk_nrf5340_cpuapp - - nrf5340_audio_dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp + - nrf5340_audio_dk/nrf5340/cpuapp tags: bluetooth diff --git a/samples/bluetooth/iso_receive/sample.yaml b/samples/bluetooth/iso_receive/sample.yaml index 7d4fbabf5e9957..2a065b7baa22d5 100644 --- a/samples/bluetooth/iso_receive/sample.yaml +++ b/samples/bluetooth/iso_receive/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - qemu_cortex_m3 tags: bluetooth @@ -17,8 +17,8 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/mesh/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/mesh/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/mesh/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/mesh/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/mesh/sample.yaml b/samples/bluetooth/mesh/sample.yaml index cbb474cd92f24a..7ad548623f78a2 100644 --- a/samples/bluetooth/mesh/sample.yaml +++ b/samples/bluetooth/mesh/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - bbc_microbit - qemu_x86 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp_ns + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp/ns integration_platforms: - qemu_x86 tags: bluetooth diff --git a/samples/bluetooth/mesh_demo/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/mesh_demo/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/mesh_demo/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/mesh_demo/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/mesh_demo/sample.yaml b/samples/bluetooth/mesh_demo/sample.yaml index adcb1af05cb4cb..255793f5657808 100644 --- a/samples/bluetooth/mesh_demo/sample.yaml +++ b/samples/bluetooth/mesh_demo/sample.yaml @@ -6,8 +6,8 @@ tests: platform_allow: - bbc_microbit - qemu_x86 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp_ns + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp/ns integration_platforms: - qemu_x86 - bbc_microbit diff --git a/samples/bluetooth/mesh_provisioner/sample.yaml b/samples/bluetooth/mesh_provisioner/sample.yaml index abaaf79aae31f2..4e122b08a6cad5 100644 --- a/samples/bluetooth/mesh_provisioner/sample.yaml +++ b/samples/bluetooth/mesh_provisioner/sample.yaml @@ -5,8 +5,8 @@ tests: harness: bluetooth platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp_ns + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp/ns integration_platforms: - qemu_x86 tags: bluetooth diff --git a/samples/bluetooth/observer/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/observer/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/observer/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/observer/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/observer/sample.yaml b/samples/bluetooth/observer/sample.yaml index b6ef4d4bb34584..b60ccc9fe8ed38 100644 --- a/samples/bluetooth/observer/sample.yaml +++ b/samples/bluetooth/observer/sample.yaml @@ -6,7 +6,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_cortex_m3 tags: bluetooth @@ -16,7 +16,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/periodic_adv/sample.yaml b/samples/bluetooth/periodic_adv/sample.yaml index b37f7ccd13fda5..f9018ff09ef32e 100644 --- a/samples/bluetooth/periodic_adv/sample.yaml +++ b/samples/bluetooth/periodic_adv/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/periodic_adv_conn/sample.yaml b/samples/bluetooth/periodic_adv_conn/sample.yaml index 985c1665b260ca..cfc9d0522f4925 100644 --- a/samples/bluetooth/periodic_adv_conn/sample.yaml +++ b/samples/bluetooth/periodic_adv_conn/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/periodic_adv_rsp/sample.yaml b/samples/bluetooth/periodic_adv_rsp/sample.yaml index f249ca55257b98..dcb37b9fe4a834 100644 --- a/samples/bluetooth/periodic_adv_rsp/sample.yaml +++ b/samples/bluetooth/periodic_adv_rsp/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/periodic_sync/sample.yaml b/samples/bluetooth/periodic_sync/sample.yaml index 3417c2096f4007..5e54024ff7b68a 100644 --- a/samples/bluetooth/periodic_sync/sample.yaml +++ b/samples/bluetooth/periodic_sync/sample.yaml @@ -7,7 +7,7 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf52_bsim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/periodic_sync_conn/sample.yaml b/samples/bluetooth/periodic_sync_conn/sample.yaml index bb6f83acd59441..e7aca788eea6bc 100644 --- a/samples/bluetooth/periodic_sync_conn/sample.yaml +++ b/samples/bluetooth/periodic_sync_conn/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/periodic_sync_rsp/sample.yaml b/samples/bluetooth/periodic_sync_rsp/sample.yaml index 68c84563ce442b..c0f073b19e01ba 100644 --- a/samples/bluetooth/periodic_sync_rsp/sample.yaml +++ b/samples/bluetooth/periodic_sync_rsp/sample.yaml @@ -6,10 +6,10 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_BT_CTLR=n - CONFIG_BT_NO_DRIVER=y diff --git a/samples/bluetooth/peripheral/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_csc/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_csc/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_csc/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_csc/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_dis/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_dis/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_dis/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_dis/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_esp/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_esp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_esp/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_esp/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_hids/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_hids/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_hids/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_hids/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_hr/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_hr/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_hr/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_hr/sample.yaml b/samples/bluetooth/peripheral_hr/sample.yaml index be557da861182a..71a19327c60aeb 100644 --- a/samples/bluetooth/peripheral_hr/sample.yaml +++ b/samples/bluetooth/peripheral_hr/sample.yaml @@ -10,8 +10,8 @@ tests: integration_platforms: - qemu_cortex_m3 tags: bluetooth - sample.bluetooth.peripheral_hr_rv32m1_vega_ri5cy: - platform_allow: rv32m1_vega_ri5cy + sample.bluetooth.peripheral_hr_rv32m1_vega_openisa_rv32m1_ri5cy: + platform_allow: rv32m1_vega/openisa_rv32m1/ri5cy tags: bluetooth build_only: true sample.bluetooth.peripheral_hr.frdm_kw41z_shield: diff --git a/samples/bluetooth/peripheral_ht/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_ht/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_ht/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_ht/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/peripheral_ht/sample.yaml b/samples/bluetooth/peripheral_ht/sample.yaml index c539113907b9cb..4ff509843e0649 100644 --- a/samples/bluetooth/peripheral_ht/sample.yaml +++ b/samples/bluetooth/peripheral_ht/sample.yaml @@ -7,8 +7,8 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/peripheral_identity/sample.yaml b/samples/bluetooth/peripheral_identity/sample.yaml index 58fbc0e26f0b2f..8bb4b277e6b7e1 100644 --- a/samples/bluetooth/peripheral_identity/sample.yaml +++ b/samples/bluetooth/peripheral_identity/sample.yaml @@ -8,7 +8,7 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth integration_platforms: - qemu_cortex_m3 diff --git a/samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/peripheral_sc_only/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild b/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild index f434010f81d27c..d609fd0ec854c7 100644 --- a/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild +++ b/samples/bluetooth/public_broadcast_sink/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/public_broadcast_sink/README.rst b/samples/bluetooth/public_broadcast_sink/README.rst index 5f47bcd05abafd..2ec0e41e7e599d 100644 --- a/samples/bluetooth/public_broadcast_sink/README.rst +++ b/samples/bluetooth/public_broadcast_sink/README.rst @@ -38,7 +38,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -46,7 +46,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_sink/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/public_broadcast_sink/sample.yaml b/samples/bluetooth/public_broadcast_sink/sample.yaml index 8b81f4cc36456d..3f2302aa4b17c2 100644 --- a/samples/bluetooth/public_broadcast_sink/sample.yaml +++ b/samples/bluetooth/public_broadcast_sink/sample.yaml @@ -7,21 +7,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.public_broadcast_sink.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild b/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild index f434010f81d27c..d609fd0ec854c7 100644 --- a/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild +++ b/samples/bluetooth/public_broadcast_source/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/public_broadcast_source/README.rst b/samples/bluetooth/public_broadcast_source/README.rst index 9111cd3f614c13..d0d1cf44afa5a0 100644 --- a/samples/bluetooth/public_broadcast_source/README.rst +++ b/samples/bluetooth/public_broadcast_source/README.rst @@ -38,7 +38,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -46,7 +46,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/public_broadcast_source/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/public_broadcast_source/sample.yaml b/samples/bluetooth/public_broadcast_source/sample.yaml index eb2bd5dc79b909..f4f1fc435f7aa9 100644 --- a/samples/bluetooth/public_broadcast_source/sample.yaml +++ b/samples/bluetooth/public_broadcast_source/sample.yaml @@ -7,21 +7,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - nrf5340bsim_nrf5340_cpuapp integration_platforms: - qemu_x86 - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: bluetooth sysbuild: true sample.bluetooth.public_broadcast_source.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 integration_platforms: - nrf52_bsim - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/scan_adv/boards/rv32m1_vega_ri5cy.overlay b/samples/bluetooth/scan_adv/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from samples/bluetooth/scan_adv/boards/rv32m1_vega_ri5cy.overlay rename to samples/bluetooth/scan_adv/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild b/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild index f434010f81d27c..d609fd0ec854c7 100644 --- a/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild +++ b/samples/bluetooth/unicast_audio_client/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/unicast_audio_client/README.rst b/samples/bluetooth/unicast_audio_client/README.rst index 3735aff4ebdb29..19e7cdf8679233 100644 --- a/samples/bluetooth/unicast_audio_client/README.rst +++ b/samples/bluetooth/unicast_audio_client/README.rst @@ -32,7 +32,7 @@ Building for an nrf52840dk .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_client/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :gen-args: -DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf @@ -44,7 +44,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_client/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -52,7 +52,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/unicast_audio_client/sample.yaml b/samples/bluetooth/unicast_audio_client/sample.yaml index 76ff71f350bf97..1b488d9eb94777 100644 --- a/samples/bluetooth/unicast_audio_client/sample.yaml +++ b/samples/bluetooth/unicast_audio_client/sample.yaml @@ -8,19 +8,19 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340bsim_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - native_sim tags: bluetooth integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp sysbuild: true sample.bluetooth.audio_unicast_client.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild b/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild index f434010f81d27c..d609fd0ec854c7 100644 --- a/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild +++ b/samples/bluetooth/unicast_audio_server/Kconfig.sysbuild @@ -5,9 +5,9 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "nrf5340_audio_dk_nrf5340_cpunet" if $(BOARD) = "nrf5340_audio_dk_nrf5340_cpuapp" - default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk" + default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk" + default "nrf5340bsim_nrf5340_cpunet" if "$(BOARD)" = "nrf5340bsim_nrf5340_cpuapp" config NET_CORE_IMAGE_HCI_IPC bool "HCI IPC image on network core" diff --git a/samples/bluetooth/unicast_audio_server/README.rst b/samples/bluetooth/unicast_audio_server/README.rst index 79a06244839640..9caeac854a7edc 100644 --- a/samples/bluetooth/unicast_audio_server/README.rst +++ b/samples/bluetooth/unicast_audio_server/README.rst @@ -32,7 +32,7 @@ Building for an nrf52840dk .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :gen-args: -DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf @@ -44,7 +44,7 @@ core with: .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build :west-args: --sysbuild @@ -52,7 +52,7 @@ If you prefer to only build the application core image, you can do so by doing i .. zephyr-app-commands:: :zephyr-app: samples/bluetooth/unicast_audio_server/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build In that case you can pair this application core image with the diff --git a/samples/bluetooth/unicast_audio_server/sample.yaml b/samples/bluetooth/unicast_audio_server/sample.yaml index 0c7496e288b956..0ff20f735d7a7c 100644 --- a/samples/bluetooth/unicast_audio_server/sample.yaml +++ b/samples/bluetooth/unicast_audio_server/sample.yaml @@ -8,19 +8,19 @@ tests: - qemu_cortex_m3 - qemu_x86 - nrf5340bsim_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp - native_sim tags: bluetooth integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp sysbuild: true sample.bluetooth.audio_unicast_server.bt_ll_sw_split: harness: bluetooth platform_allow: - nrf52_bsim - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf tags: bluetooth diff --git a/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig b/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig index 059ce331b600ea..cfa607745c6c40 100644 --- a/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig +++ b/samples/boards/arc_secure_services/em_starterkit_em7d_normal_defconfig @@ -1,7 +1,6 @@ CONFIG_SOC_EMSK=y CONFIG_SOC_EMSK_EM7D=y CONFIG_BOARD_EM_STARTERKIT=y -CONFIG_BOARD_EM_STARTERKIT_R23=y CONFIG_SYS_CLOCK_TICKS_PER_SEC=100 CONFIG_XIP=n CONFIG_BUILD_NO_GAP_FILL=y diff --git a/samples/boards/arc_secure_services/sample.yaml b/samples/boards/arc_secure_services/sample.yaml index 8e99393eb77266..8b6be2343393a8 100644 --- a/samples/boards/arc_secure_services/sample.yaml +++ b/samples/boards/arc_secure_services/sample.yaml @@ -7,10 +7,10 @@ tests: # Requires multiple kernels in an AMP config. See README.rst build_only: true platform_allow: - - nsim_sem - - em_starterkit_em7d + - nsim/nsim_sem + - em_starterkit/emsk_em7d integration_platforms: - - nsim_sem + - nsim/nsim_sem tags: secure harness: console harness_config: diff --git a/samples/boards/esp32/deep_sleep/README.rst b/samples/boards/esp32/deep_sleep/README.rst index a5de4def742326..ac73969915b3c3 100644 --- a/samples/boards/esp32/deep_sleep/README.rst +++ b/samples/boards/esp32/deep_sleep/README.rst @@ -51,7 +51,7 @@ Building, Flashing and Running .. zephyr-app-commands:: :zephyr-app: samples/boards/esp32/deep_sleep - :board: esp32_devkitc_wroom + :board: esp32_devkitc_wroom/esp32/procpu :goals: build flash :compact: diff --git a/samples/boards/esp32/ethernet/sample.yaml b/samples/boards/esp32/ethernet/sample.yaml index 2280fec7c7c498..35f9b4a44afded 100644 --- a/samples/boards/esp32/ethernet/sample.yaml +++ b/samples/boards/esp32/ethernet/sample.yaml @@ -3,5 +3,5 @@ sample: name: ESP32 Ethernet tests: sample.board.esp32.ethernet: - platform_allow: esp32_ethernet_kit + platform_allow: esp32_ethernet_kit/esp32/procpu tags: esp32 diff --git a/samples/boards/esp32/flash_encryption/sample.yaml b/samples/boards/esp32/flash_encryption/sample.yaml index 84749b9910884e..26e7f309f096f0 100644 --- a/samples/boards/esp32/flash_encryption/sample.yaml +++ b/samples/boards/esp32/flash_encryption/sample.yaml @@ -4,7 +4,7 @@ sample: tests: sample.board.esp32: platform_allow: - - esp32_devkitc_wroom - - esp32_devkitc_wrover - - yd_esp32 + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu + - yd_esp32/esp32/procpu tags: esp32 diff --git a/samples/boards/esp32/flash_memory_mapped/sample.yaml b/samples/boards/esp32/flash_memory_mapped/sample.yaml index c8601961d94c33..83ccc9f4101af3 100644 --- a/samples/boards/esp32/flash_memory_mapped/sample.yaml +++ b/samples/boards/esp32/flash_memory_mapped/sample.yaml @@ -4,7 +4,7 @@ sample: tests: sample.board.esp32.flash_memory_mapped: platform_allow: - - esp32_devkitc_wroom + - esp32_devkitc_wroom/esp32/procpu - esp32c3_devkitm - - esp32s3_devkitm + - esp32s3_devkitm/esp32s3/procpu tags: esp32 diff --git a/samples/boards/esp32/light_sleep/README.rst b/samples/boards/esp32/light_sleep/README.rst index 581e9a352b950a..72f58c2b418051 100644 --- a/samples/boards/esp32/light_sleep/README.rst +++ b/samples/boards/esp32/light_sleep/README.rst @@ -31,7 +31,7 @@ Building, Flashing and Running .. zephyr-app-commands:: :zephyr-app: samples/boards/esp32/light_sleep - :board: esp32_devkitc_wroom + :board: esp32_devkitc_wroom/esp32/procpu :goals: build flash :compact: diff --git a/samples/boards/esp32/spiram_test/sample.yaml b/samples/boards/esp32/spiram_test/sample.yaml index d8cbfaa62d7868..20c01a3028ac2b 100644 --- a/samples/boards/esp32/spiram_test/sample.yaml +++ b/samples/boards/esp32/spiram_test/sample.yaml @@ -3,5 +3,5 @@ sample: name: spiram_test tests: sample.board.esp32.spiram: - platform_allow: esp32_devkitc_wrover + platform_allow: esp32_devkitc_wrover/esp32/procpu tags: esp32 diff --git a/samples/boards/intel_adsp/code_relocation/README.rst b/samples/boards/intel_adsp/code_relocation/README.rst index 3ab0025f3c5da5..84797018e7c51e 100644 --- a/samples/boards/intel_adsp/code_relocation/README.rst +++ b/samples/boards/intel_adsp/code_relocation/README.rst @@ -20,7 +20,7 @@ This application can be built and executed as follows: .. zephyr-app-commands:: :zephyr-app: samples/hello_world - :board: intel_adsp_cavs25 + :board: intel_adsp/cavs25 :goals: build :compact: diff --git a/samples/boards/intel_adsp/code_relocation/sample.yaml b/samples/boards/intel_adsp/code_relocation/sample.yaml index 5fab5d98767eaf..6c0dfd6c756935 100644 --- a/samples/boards/intel_adsp/code_relocation/sample.yaml +++ b/samples/boards/intel_adsp/code_relocation/sample.yaml @@ -3,5 +3,5 @@ sample: name: cavs_code_reloc tests: sample.intel_adsp.code_relocation: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 tags: linker diff --git a/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml b/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml index 10e876847f7310..462a1d165e534b 100644 --- a/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml +++ b/samples/boards/mimxrt1170_evk_cm7/magic_addr/sample.yaml @@ -3,10 +3,10 @@ sample: name: magic addr common: integration_platforms: - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 tests: sample.boards.mimxrt1170_evk.magic_addr: platform_allow: - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 diff --git a/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c b/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c index 6856ca8f10f9d9..f44c3f23923ffd 100644 --- a/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c +++ b/samples/boards/mimxrt1170_evk_cm7/magic_addr/src/main.c @@ -27,7 +27,6 @@ void flexram_magic_addr_isr_cb(enum memc_flexram_interrupt_cause cause, } } - int main(void) { memc_flexram_register_callback(flexram_magic_addr_isr_cb, NULL); diff --git a/samples/boards/mimxrt595_evk/system_off/CMakeLists.txt b/samples/boards/mimxrt595_evk/system_off/CMakeLists.txt new file mode 100644 index 00000000000000..97d8abdea0e7a7 --- /dev/null +++ b/samples/boards/mimxrt595_evk/system_off/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright 2022, NXP +# +# SPDX-License-Identifier: Apache-2.0 + +cmake_minimum_required(VERSION 3.20.0) +find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) +project(mimxrt595_evk_system_off) + +target_sources(app PRIVATE src/main.c) diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/Kconfig b/samples/boards/mimxrt595_evk/system_off/Kconfig similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/Kconfig rename to samples/boards/mimxrt595_evk/system_off/Kconfig diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/README.rst b/samples/boards/mimxrt595_evk/system_off/README.rst similarity index 98% rename from samples/boards/mimxrt595_evk_cm33/system_off/README.rst rename to samples/boards/mimxrt595_evk/system_off/README.rst index 00d0aeaf910d55..edec7a0b10470d 100644 --- a/samples/boards/mimxrt595_evk_cm33/system_off/README.rst +++ b/samples/boards/mimxrt595_evk/system_off/README.rst @@ -22,8 +22,8 @@ Building, Flashing and Running ****************************** .. zephyr-app-commands:: - :zephyr-app: samples/boards/mimxrt595_evk_cm33/system_off - :board: mimxrt595_evk_cm33 + :zephyr-app: samples/boards/mimxrt595_evk/system_off + :board: mimxrt595_evk/mimxrt595s/cm33 :goals: build flash :compact: diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/app.overlay b/samples/boards/mimxrt595_evk/system_off/app.overlay similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/app.overlay rename to samples/boards/mimxrt595_evk/system_off/app.overlay diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/prj.conf b/samples/boards/mimxrt595_evk/system_off/prj.conf similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/prj.conf rename to samples/boards/mimxrt595_evk/system_off/prj.conf diff --git a/samples/boards/mimxrt595_evk/system_off/sample.yaml b/samples/boards/mimxrt595_evk/system_off/sample.yaml new file mode 100644 index 00000000000000..5d85a280a3e433 --- /dev/null +++ b/samples/boards/mimxrt595_evk/system_off/sample.yaml @@ -0,0 +1,13 @@ +# +# Copyright 2022, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +sample: + name: Deep Power Down State Sample for mimxrt595_evk +common: + tags: power +tests: + sample.boards.mimxrt595_evk.system_off: + build_only: true + platform_allow: mimxrt595_evk/mimxrt595s/cm33 diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/src/main.c b/samples/boards/mimxrt595_evk/system_off/src/main.c similarity index 100% rename from samples/boards/mimxrt595_evk_cm33/system_off/src/main.c rename to samples/boards/mimxrt595_evk/system_off/src/main.c diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/CMakeLists.txt b/samples/boards/mimxrt595_evk_cm33/system_off/CMakeLists.txt deleted file mode 100644 index 44e9ad4d6cd440..00000000000000 --- a/samples/boards/mimxrt595_evk_cm33/system_off/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 - -cmake_minimum_required(VERSION 3.20.0) -find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -project(mimxrt595_evk_cm33_system_off) - -target_sources(app PRIVATE src/main.c) diff --git a/samples/boards/mimxrt595_evk_cm33/system_off/sample.yaml b/samples/boards/mimxrt595_evk_cm33/system_off/sample.yaml deleted file mode 100644 index 58c906414b30d5..00000000000000 --- a/samples/boards/mimxrt595_evk_cm33/system_off/sample.yaml +++ /dev/null @@ -1,13 +0,0 @@ -# -# Copyright 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -sample: - name: Deep Power Down State Sample for mimxrt595_evk -common: - tags: power -tests: - sample.boards.mimxrt595_evk_cm33.system_off: - build_only: true - platform_allow: mimxrt595_evk_cm33 diff --git a/samples/boards/nrf/battery/README.rst b/samples/boards/nrf/battery/README.rst index 7f73ecabecfa64..323e5609640e07 100644 --- a/samples/boards/nrf/battery/README.rst +++ b/samples/boards/nrf/battery/README.rst @@ -73,7 +73,7 @@ The code can be found in :zephyr_file:`samples/boards/nrf/battery`. .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/battery - :board: thingy52_nrf52832 + :board: thingy52/nrf52832 :goals: build flash :compact: diff --git a/samples/boards/nrf/battery/sample.yaml b/samples/boards/nrf/battery/sample.yaml index e662296b0df7bc..61e696f6c13d11 100644 --- a/samples/boards/nrf/battery/sample.yaml +++ b/samples/boards/nrf/battery/sample.yaml @@ -5,7 +5,7 @@ tests: build_only: true platform_allow: - particle_xenon - - thingy52_nrf52832 + - thingy52/nrf52832 tags: battery integration_platforms: - particle_xenon diff --git a/samples/boards/nrf/clock_skew/README.rst b/samples/boards/nrf/clock_skew/README.rst index 7891ab075b6fce..a6861d47056224 100644 --- a/samples/boards/nrf/clock_skew/README.rst +++ b/samples/boards/nrf/clock_skew/README.rst @@ -28,7 +28,7 @@ Building, Flashing and Running .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/clock_skew - :board: nrf52dk_nrf52840 + :board: nrf52dk/nrf52832 :goals: build flash :compact: diff --git a/samples/boards/nrf/clock_skew/sample.yaml b/samples/boards/nrf/clock_skew/sample.yaml index 2b1eae0a6aa3f8..3da8823ea51509 100644 --- a/samples/boards/nrf/clock_skew/sample.yaml +++ b/samples/boards/nrf/clock_skew/sample.yaml @@ -4,9 +4,9 @@ tests: sample.boards.nrf.clock_skew: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 tags: power integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/boards/nrf/dynamic_pinctrl/README.rst b/samples/boards/nrf/dynamic_pinctrl/README.rst index f44a58c3563c65..b98c4482353688 100644 --- a/samples/boards/nrf/dynamic_pinctrl/README.rst +++ b/samples/boards/nrf/dynamic_pinctrl/README.rst @@ -53,7 +53,7 @@ You can build this application for the nRF52840 DK as follows: .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/dynamic_pinctrl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/boards/nrf/dynamic_pinctrl/sample.yaml b/samples/boards/nrf/dynamic_pinctrl/sample.yaml index b8f38be6ae3c34..03ccf19ec7eb23 100644 --- a/samples/boards/nrf/dynamic_pinctrl/sample.yaml +++ b/samples/boards/nrf/dynamic_pinctrl/sample.yaml @@ -4,6 +4,6 @@ sample: tests: sample.boards.nrf.dynamic_pinctrl: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml b/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml index d99dcceaa32fa0..f1a7fae2a9a7f9 100644 --- a/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml +++ b/samples/boards/nrf/ieee802154/802154_rpmsg/sample.yaml @@ -6,5 +6,5 @@ tests: sample.boards.nrf.802154_rpmsg: build_only: true platform_allow: - - nrf5340dk_nrf5340_cpunet + - nrf5340dk/nrf5340/cpunet - nrf5340bsim_nrf5340_cpunet diff --git a/samples/boards/nrf/mesh/onoff-app/README.rst b/samples/boards/nrf/mesh/onoff-app/README.rst index 35e37d6a599b57..70d3e3bb1eb8e0 100644 --- a/samples/boards/nrf/mesh/onoff-app/README.rst +++ b/samples/boards/nrf/mesh/onoff-app/README.rst @@ -38,7 +38,7 @@ Requirements ************ This sample has been tested on the Nordic nRF52840-PDK board, but would -likely also run on the nrf52dk_nrf52832 board. +likely also run on the nrf52dk/nrf52832 board. Building and Running ******************** @@ -50,7 +50,7 @@ The following commands build the application. .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/mesh/onoff-app - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/boards/nrf/mesh/onoff-app/sample.yaml b/samples/boards/nrf/mesh/onoff-app/sample.yaml index af80fff7fb67b3..bdc6f023a5b986 100644 --- a/samples/boards/nrf/mesh/onoff-app/sample.yaml +++ b/samples/boards/nrf/mesh/onoff-app/sample.yaml @@ -2,6 +2,6 @@ sample: name: Bluetooth Mesh tests: sample.bluetooth.mesh.onoff: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth harness: bluetooth diff --git a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst index f33bf1e7761110..911e4b41430e81 100644 --- a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst +++ b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/README.rst @@ -55,7 +55,7 @@ also publish its relevant status. Requirements ************ This sample has been tested on the Nordic nRF52840-PDK board, but would -likely also run on the nrf52dk_nrf52832 board. +likely also run on the nrf52dk/nrf52832 board. Building and Running ******************** @@ -66,7 +66,7 @@ The following commands build the application. .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/mesh/onoff_level_lighting_vnd_app - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml index ba0c0c0c1d3a28..d10821ca92ee0c 100644 --- a/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml +++ b/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/sample.yaml @@ -2,6 +2,6 @@ sample: name: Bluetooth Mesh tests: sample.bluetooth.mesh.onoff_level_lighting_vnd: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: bluetooth harness: bluetooth diff --git a/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt b/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt index 432f5497009e1e..a09354a9e05c79 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt +++ b/samples/boards/nrf/nrf53_sync_rtc/CMakeLists.txt @@ -7,7 +7,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp")) message(INFO " ${BOARD} used for Application Core") else() diff --git a/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild b/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild index b6dc3d0a6d0d35..e6d2ccd9930040 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild +++ b/samples/boards/nrf/nrf53_sync_rtc/Kconfig.sysbuild @@ -6,5 +6,5 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" diff --git a/samples/boards/nrf/nrf53_sync_rtc/README.rst b/samples/boards/nrf/nrf53_sync_rtc/README.rst index 0b2fd2a22fa506..7d2a2945ffce17 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/README.rst +++ b/samples/boards/nrf/nrf53_sync_rtc/README.rst @@ -22,12 +22,12 @@ interrupt handling. For simplicity and low latency sample is not using more sophisticated IPM protocols. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/nrf53_sync_rtc - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: flash :flash-args: --hex-file build/nrf53_sync_rtc/zephyr/zephyr.hex :west-args: --sysbuild diff --git a/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt b/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt index feced555bc77f1..341d961d8f06f5 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt +++ b/samples/boards/nrf/nrf53_sync_rtc/net/CMakeLists.txt @@ -7,7 +7,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpunet") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpunet")) message(INFO " ${BOARD} used for Network Core") else() diff --git a/samples/boards/nrf/nrf53_sync_rtc/sample.yaml b/samples/boards/nrf/nrf53_sync_rtc/sample.yaml index d1905e0cc47848..95e0471073faee 100644 --- a/samples/boards/nrf/nrf53_sync_rtc/sample.yaml +++ b/samples/boards/nrf/nrf53_sync_rtc/sample.yaml @@ -7,9 +7,9 @@ common: tests: sample.boards.nrf.nrf53_sync_rtc.real_hw: platform_allow: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp harness: remote sample.boards.nrf.nrf53_sync_rtc.simu: platform_allow: diff --git a/samples/boards/nrf/nrfx/README.rst b/samples/boards/nrf/nrfx/README.rst index e993ebe935b383..d03e155e105ed8 100644 --- a/samples/boards/nrf/nrfx/README.rst +++ b/samples/boards/nrf/nrfx/README.rst @@ -29,7 +29,7 @@ Requirements ************ This sample has been tested on the NordicSemiconductor nRF9160 DK -(nrf9160dk_nrf9160) and nRF52840 DK (nrf52840dk_nrf52840) boards. +(nrf9160dk/nrf9160) and nRF52840 DK (nrf52840dk/nrf52840) boards. Building and Running ******************** @@ -40,7 +40,7 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/nrfx - :board: nrf9160dk_nrf9160 + :board: nrf9160dk/nrf9160 :goals: build flash :compact: diff --git a/samples/boards/nrf/nrfx/sample.yaml b/samples/boards/nrf/nrfx/sample.yaml index f20fe8203e1f2c..5483d1d9be0c11 100644 --- a/samples/boards/nrf/nrfx/sample.yaml +++ b/samples/boards/nrf/nrfx/sample.yaml @@ -3,10 +3,10 @@ sample: tests: sample.boards.nrf.nrfx: platform_allow: - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: board harness: console harness_config: diff --git a/samples/boards/nrf/nrfx_prs/README.rst b/samples/boards/nrf/nrfx_prs/README.rst index 0924eecd85f27a..8151a7cf5c5616 100644 --- a/samples/boards/nrf/nrfx_prs/README.rst +++ b/samples/boards/nrf/nrfx_prs/README.rst @@ -38,7 +38,7 @@ Requirements ************ This sample has been tested on the Nordic Semiconductor nRF9160 DK -(nrf9160dk_nrf9160) and nRF5340 DK (nrf5340dk_nrf5340_cpuapp) boards. +(nrf9160dk/nrf9160) and nRF5340 DK (nrf5340dk/nrf5340/cpuapp) boards. Building and Running ******************** @@ -49,7 +49,7 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/boards/nrf/nrfx_prs - :board: nrf9160dk_nrf9160 + :board: nrf9160dk/nrf9160 :goals: build flash :compact: diff --git a/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay b/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay index ee851e77b24542..535d8272d45fbf 100644 --- a/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay +++ b/samples/boards/nrf/nrfx_prs/boards/nrf9160dk_nrf9160.overlay @@ -79,7 +79,7 @@ pinctrl-names = "default"; }; -/* This node also needs to be disabled, as in the default nrf9160dk_nrf9160 +/* This node also needs to be disabled, as in the default nrf9160dk/nrf9160 * board configuration it uses the same pin numbers that are above assigned * to the spi1 node (17, 18, and 19). */ diff --git a/samples/boards/nrf/nrfx_prs/sample.yaml b/samples/boards/nrf/nrfx_prs/sample.yaml index 9a15c276859a6b..149dd1724838e9 100644 --- a/samples/boards/nrf/nrfx_prs/sample.yaml +++ b/samples/boards/nrf/nrfx_prs/sample.yaml @@ -3,11 +3,11 @@ sample: tests: sample.boards.nrf.nrfx_prs: platform_allow: - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 integration_platforms: - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 tags: nrfx harness: console harness_config: diff --git a/samples/boards/nrf/system_off/README.rst b/samples/boards/nrf/system_off/README.rst index 8d5636be0f9089..fa1bacb110fc0a 100644 --- a/samples/boards/nrf/system_off/README.rst +++ b/samples/boards/nrf/system_off/README.rst @@ -33,5 +33,5 @@ nRF52 core output *** Booting Zephyr OS build v2.3.0-rc1-204-g5f2eb85f728d *** - nrf52dk_nrf52832 system off demo + nrf52dk system off demo Entering system off; press sw0 to restart diff --git a/samples/boards/nrf/system_off/sample.yaml b/samples/boards/nrf/system_off/sample.yaml index 84a61f427b7230..0a58d8fc009367 100644 --- a/samples/boards/nrf/system_off/sample.yaml +++ b/samples/boards/nrf/system_off/sample.yaml @@ -3,18 +3,18 @@ sample: common: tags: power integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tests: sample.boards.nrf.system_off: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 sample.boards.nrf.system_off.retained: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 extra_configs: - CONFIG_APP_RETENTION=y diff --git a/samples/boards/nxp_s32/netc/README.rst b/samples/boards/nxp_s32/netc/README.rst index f779dcffed9a33..f8dca18f3be43c 100644 --- a/samples/boards/nxp_s32/netc/README.rst +++ b/samples/boards/nxp_s32/netc/README.rst @@ -36,7 +36,7 @@ To build and run the sample application for use-case 1: .. zephyr-app-commands:: :zephyr-app: samples/boards/nxp_s32/netc - :board: s32z270dc2_rtu0_r52 + :board: s32z2xxdc2/s32z270/rtu0 :goals: build flash Once started, you should see the network interface details, for example: @@ -59,7 +59,7 @@ To build and run the sample application for use-case 2: .. zephyr-app-commands:: :zephyr-app: samples/boards/nxp_s32/netc - :board: s32z270dc2_rtu0_r52 + :board: s32z2xxdc2/s32z270/rtu0 :goals: build flash :gen-args: -DDTC_OVERLAY_FILE="./vsi-and-psi.overlay" diff --git a/samples/boards/nxp_s32/netc/sample.yaml b/samples/boards/nxp_s32/netc/sample.yaml index 8329b04d134dc5..9adf63fd16d833 100644 --- a/samples/boards/nxp_s32/netc/sample.yaml +++ b/samples/boards/nxp_s32/netc/sample.yaml @@ -2,7 +2,9 @@ sample: description: Sample for show-casing the different use-cases of NXP S32 NETC driver name: NXP S32 NETC sample common: - platform_allow: s32z270dc2_rtu0_r52 + platform_allow: + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu0 depends_on: netif tags: net tests: diff --git a/samples/boards/stm32/ccm/README.rst b/samples/boards/stm32/ccm/README.rst index 3b5cc0a961e5b8..76959722d7a742 100644 --- a/samples/boards/stm32/ccm/README.rst +++ b/samples/boards/stm32/ccm/README.rst @@ -36,7 +36,7 @@ board's DTS file ``chosen`` section: For example the olimex STM32 E407 DTS file looks like this: -.. literalinclude:: ../../../../boards/arm/olimex_stm32_e407/olimex_stm32_e407.dts +.. literalinclude:: ../../../../boards/olimex/stm32_e407/olimex_stm32_e407.dts :linenos: Building and Running diff --git a/samples/boards/stm32/h7_dual_core/README.rst b/samples/boards/stm32/h7_dual_core/README.rst index 2fb5aa63f4ffc6..eba0db90dfbe38 100644 --- a/samples/boards/stm32/h7_dual_core/README.rst +++ b/samples/boards/stm32/h7_dual_core/README.rst @@ -10,18 +10,18 @@ Blinky led triggered by mailbox new message. Building and Running ******************** -Build for stm32h747i_disco_m7: +Build for stm32h747i_disco/stm32h747xx/m7: .. zephyr-app-commands:: :zephyr-app: samples/boards/stm32/h7_dual_core - :board: stm32h747i_disco_m7 + :board: stm32h747i_disco/stm32h747xx/m7 :goals: build -Build for stm32h747i_disco_m4: +Build for stm32h747i_disco/stm32h747xx/m4: .. zephyr-app-commands:: :zephyr-app: samples/boards/stm32/h7_dual_core - :board: stm32h747i_disco_m4 + :board: stm32h747i_disco/stm32h747xx/m4 :goals: build Sample Output diff --git a/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m4.overlay b/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m4.overlay similarity index 100% rename from samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m4.overlay rename to samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m4.overlay diff --git a/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m7.overlay b/samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_m7.overlay rename to samples/boards/stm32/h7_dual_core/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/samples/boards/up_squared/gpio_counter/CMakeLists.txt b/samples/boards/up_squared/gpio_counter/CMakeLists.txt index 82a09134bf4d79..be34f4fe1fddb0 100644 --- a/samples/boards/up_squared/gpio_counter/CMakeLists.txt +++ b/samples/boards/up_squared/gpio_counter/CMakeLists.txt @@ -6,4 +6,3 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) project(gpio_counter) target_sources(app PRIVATE src/main.c) -zephyr_include_directories(${ZEPHYR_BASE}/boards/x86/up_squared) diff --git a/samples/compression/lz4/README.rst b/samples/compression/lz4/README.rst index 18045284130f52..0188b52afe9c7e 100644 --- a/samples/compression/lz4/README.rst +++ b/samples/compression/lz4/README.rst @@ -12,12 +12,12 @@ compress & decompress the user data to the console. Building and Running ******************** -The sample can be built and executed on nrf52840dk_nrf52840 as follows: +The sample can be built and executed on nrf52840dk/nrf52840 as follows: .. zephyr-app-commands:: :zephyr-app: samples/compression/lz4 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: -To build for another board, change "nrf52840dk_nrf52840" above to that board's name. +To build for another board, change "nrf52840dk/nrf52840" above to that board's name. diff --git a/samples/compression/lz4/sample.yaml b/samples/compression/lz4/sample.yaml index f9758f26984aff..a5c36ff7a8e28c 100644 --- a/samples/compression/lz4/sample.yaml +++ b/samples/compression/lz4/sample.yaml @@ -17,7 +17,7 @@ common: tests: sample.compression.lz4: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_riscv64 tags: - compression diff --git a/samples/drivers/adc/boards/longan_nano_lite.overlay b/samples/drivers/adc/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from samples/drivers/adc/boards/longan_nano_lite.overlay rename to samples/drivers/adc/boards/longan_nano_gd32vf103_lite.overlay diff --git a/samples/drivers/adc/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/adc/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay new file mode 100644 index 00000000000000..a27042020df4a2 --- /dev/null +++ b/samples/drivers/adc/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay @@ -0,0 +1,34 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright 2021,2023 NXP + */ + +#include + +/ { + zephyr,user { + /* adjust channel number according to pinmux in board.dts */ + io-channels = <&lpadc0 0>; + }; +}; + +&lpadc0 { + #address-cells = <1>; + #size-cells = <0>; + + /* + * To use this sample: + * - Connect LPADC0 CH0 signal to voltage between 0~1.8V (J9 pin 10) + */ + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_EXTERNAL0"; + zephyr,vref-mv = <1800>; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = ; + }; +}; diff --git a/samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/samples/drivers/adc/boards/mimxrt1170_evkb_cm7.overlay b/samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt1170_evkb_cm7.overlay rename to samples/drivers/adc/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/samples/drivers/adc/boards/mimxrt595_evk_cm33.overlay b/samples/drivers/adc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt595_evk_cm33.overlay rename to samples/drivers/adc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay b/samples/drivers/adc/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/drivers/adc/boards/mimxrt685_evk_cm33.overlay rename to samples/drivers/adc/boards/mimxrt685_evk.overlay diff --git a/samples/drivers/adc/boards/nrf51dk_nrf51422.overlay b/samples/drivers/adc/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/adc/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/adc/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/adc/boards/tdk_robokit1.overlay b/samples/drivers/adc/boards/robokit1.overlay similarity index 100% rename from samples/drivers/adc/boards/tdk_robokit1.overlay rename to samples/drivers/adc/boards/robokit1.overlay diff --git a/samples/drivers/adc/boards/sam_e70_xplained.overlay b/samples/drivers/adc/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from samples/drivers/adc/boards/sam_e70_xplained.overlay rename to samples/drivers/adc/boards/sam_e70_xplained_same70q21.overlay diff --git a/samples/drivers/adc/boards/sam_v71_xult.overlay b/samples/drivers/adc/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from samples/drivers/adc/boards/sam_v71_xult.overlay rename to samples/drivers/adc/boards/sam_v71_xult_samv71q21.overlay diff --git a/samples/drivers/adc/boards/atsamc21n_xpro.overlay b/samples/drivers/adc/boards/samc21n_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamc21n_xpro.overlay rename to samples/drivers/adc/boards/samc21n_xpro.overlay diff --git a/samples/drivers/adc/boards/atsamd21_xpro.overlay b/samples/drivers/adc/boards/samd21_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamd21_xpro.overlay rename to samples/drivers/adc/boards/samd21_xpro.overlay diff --git a/samples/drivers/adc/boards/atsame54_xpro.overlay b/samples/drivers/adc/boards/same54_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsame54_xpro.overlay rename to samples/drivers/adc/boards/same54_xpro.overlay diff --git a/samples/drivers/adc/boards/atsaml21_xpro.overlay b/samples/drivers/adc/boards/saml21_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsaml21_xpro.overlay rename to samples/drivers/adc/boards/saml21_xpro.overlay diff --git a/samples/drivers/adc/boards/atsamr21_xpro.overlay b/samples/drivers/adc/boards/samr21_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamr21_xpro.overlay rename to samples/drivers/adc/boards/samr21_xpro.overlay diff --git a/samples/drivers/adc/boards/atsamr34_xpro.overlay b/samples/drivers/adc/boards/samr34_xpro.overlay similarity index 100% rename from samples/drivers/adc/boards/atsamr34_xpro.overlay rename to samples/drivers/adc/boards/samr34_xpro.overlay diff --git a/samples/drivers/adc/sample.yaml b/samples/drivers/adc/sample.yaml index 2ed1681a0e0c00..7b523ea062cc0f 100644 --- a/samples/drivers/adc/sample.yaml +++ b/samples/drivers/adc/sample.yaml @@ -13,25 +13,25 @@ tests: - cy8cproto_063_ble - stm32l496g_disco - stm32h735g_disco - - nrf51dk_nrf51422 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52840dk/nrf52840 - mec172xevb_assy6906 - gd32f350r_eval - gd32f450i_eval - gd32vf103v_eval - gd32f403z_eval - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - esp32c3_devkitm - gd32l233r_eval - lpcxpresso55s36 - mr_canhubk3 - longan_nano - - longan_nano_lite + - longan_nano/gd32vf103/lite integration_platforms: - nucleo_l073rz - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness: console timeout: 10 harness_config: diff --git a/samples/drivers/audio/dmic/README.rst b/samples/drivers/audio/dmic/README.rst index 3e1463795c0fc5..1382ff0a9cea12 100644 --- a/samples/drivers/audio/dmic/README.rst +++ b/samples/drivers/audio/dmic/README.rst @@ -17,8 +17,8 @@ Requirements The device to be used by the sample is specified by defining a devicetree node label named ``dmic_dev``. -The sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk_nrf52840) -and :ref:`nrf5340dk_nrf5340` (nrf5340dk_nrf5340_cpuapp), and provides overlay +The sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk/nrf52840) +and :ref:`nrf5340dk_nrf5340` (nrf5340dk/nrf5340/cpuapp), and provides overlay files for both of these boards. Building and Running @@ -30,6 +30,6 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/drivers/audio/dmic - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/audio/dmic/boards/mimxrt595_evk_cm33.overlay b/samples/drivers/audio/dmic/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from samples/drivers/audio/dmic/boards/mimxrt595_evk_cm33.overlay rename to samples/drivers/audio/dmic/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/samples/drivers/audio/dmic/sample.yaml b/samples/drivers/audio/dmic/sample.yaml index 07a086518ec84e..8cc5464b781678 100644 --- a/samples/drivers/audio/dmic/sample.yaml +++ b/samples/drivers/audio/dmic/sample.yaml @@ -5,8 +5,8 @@ tests: tags: dmic filter: dt_nodelabel_enabled("dmic_dev") integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/drivers/can/counter/README.rst b/samples/drivers/can/counter/README.rst index 6addd47b71444c..3b66661a714e3a 100644 --- a/samples/drivers/can/counter/README.rst +++ b/samples/drivers/can/counter/README.rst @@ -38,12 +38,12 @@ For the NXP TWR-KE18F board: Stand alone CAN controller ========================== -For the nrf52dk_nrf52832 board combined with the DFRobot CAN bus V2.0 shield that +For the nrf52dk/nrf52832 board combined with the DFRobot CAN bus V2.0 shield that provides the MCP2515 CAN controller: .. zephyr-app-commands:: :zephyr-app: samples/drivers/can/counter - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :shield: dfrobot_can_bus_v2_0 :goals: build flash diff --git a/samples/drivers/clock_control_xec/src/main.c b/samples/drivers/clock_control_xec/src/main.c index d4462bb882b7c5..21d598fa5016a5 100644 --- a/samples/drivers/clock_control_xec/src/main.c +++ b/samples/drivers/clock_control_xec/src/main.c @@ -17,7 +17,7 @@ LOG_MODULE_REGISTER(clock32k, CONFIG_CLOCK_CONTROL_LOG_LEVEL); #include -#ifdef CONFIG_SOC_SERIES_MEC1501X +#ifdef CONFIG_SOC_SERIES_MEC15XX static void pcr_clock_regs(void) { struct pcr_regs *pcr = ((struct pcr_regs *)DT_REG_ADDR_BY_IDX(DT_NODELABEL(pcr), 0)); diff --git a/samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.conf b/samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.conf similarity index 100% rename from samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.conf rename to samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.conf diff --git a/samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.overlay b/samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/bl5340_dvk_cpuapp.overlay rename to samples/drivers/counter/alarm/boards/bl5340_dvk_nrf5340_cpuapp.overlay diff --git a/samples/drivers/counter/alarm/boards/nrf51dk_nrf51422.overlay b/samples/drivers/counter/alarm/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/counter/alarm/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/counter/alarm/boards/s32z270dc2_rtu0_r52.overlay b/samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/s32z270dc2_rtu0_r52.overlay rename to samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/samples/drivers/counter/alarm/boards/s32z270dc2_rtu1_r52.overlay b/samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/s32z270dc2_rtu1_r52.overlay rename to samples/drivers/counter/alarm/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_e70_xplained.overlay b/samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_e70_xplained.overlay rename to samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_e70b_xplained.overlay b/samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21b.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_e70b_xplained.overlay rename to samples/drivers/counter/alarm/boards/sam_e70_xplained_same70q21b.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_v71_xult.overlay b/samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_v71_xult.overlay rename to samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21.overlay diff --git a/samples/drivers/counter/alarm/boards/sam_v71b_xult.overlay b/samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21b.overlay similarity index 100% rename from samples/drivers/counter/alarm/boards/sam_v71b_xult.overlay rename to samples/drivers/counter/alarm/boards/sam_v71_xult_samv71q21b.overlay diff --git a/samples/drivers/counter/alarm/boards/stm32l562e_dk_ns.conf b/samples/drivers/counter/alarm/boards/stm32l562e_dk_stm32l562xx_ns.conf similarity index 100% rename from samples/drivers/counter/alarm/boards/stm32l562e_dk_ns.conf rename to samples/drivers/counter/alarm/boards/stm32l562e_dk_stm32l562xx_ns.conf diff --git a/samples/drivers/counter/alarm/sample.yaml b/samples/drivers/counter/alarm/sample.yaml index fe81529a45bcb5..6b93637ccaa9a7 100644 --- a/samples/drivers/counter/alarm/sample.yaml +++ b/samples/drivers/counter/alarm/sample.yaml @@ -8,12 +8,12 @@ tests: harness: console platform_allow: - nucleo_f746zg - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - atsamd20_xpro - - bl5340_dvk_cpuapp + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - samd20_xpro + - bl5340_dvk/nrf5340/cpuapp - gd32e103v_eval - gd32e507z_eval - gd32f403z_eval diff --git a/samples/drivers/counter/alarm/src/main.c b/samples/drivers/counter/alarm/src/main.c index 9eee4d3fba2b12..2b009068ba91ad 100644 --- a/samples/drivers/counter/alarm/src/main.c +++ b/samples/drivers/counter/alarm/src/main.c @@ -15,9 +15,9 @@ struct counter_alarm_cfg alarm_cfg; -#if defined(CONFIG_BOARD_ATSAMD20_XPRO) +#if defined(CONFIG_BOARD_SAMD20_XPRO) #define TIMER DT_NODELABEL(tc4) -#elif defined(CONFIG_SOC_FAMILY_SAM) +#elif defined(CONFIG_SOC_FAMILY_ATMEL_SAM) #define TIMER DT_NODELABEL(tc0) #elif defined(CONFIG_COUNTER_MICROCHIP_MCP7940N) #define TIMER DT_NODELABEL(extrtc0) diff --git a/samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51422.overlay b/samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/counter/maxim_ds3231/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/counter/maxim_ds3231/sample.yaml b/samples/drivers/counter/maxim_ds3231/sample.yaml index 4e9c209047c95b..bf32d825e7a4c1 100644 --- a/samples/drivers/counter/maxim_ds3231/sample.yaml +++ b/samples/drivers/counter/maxim_ds3231/sample.yaml @@ -8,7 +8,7 @@ tests: platform_allow: - efr32mg_sltb004a - frdm_k64f - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - nucleo_l476rg - particle_xenon integration_platforms: diff --git a/samples/drivers/dac/README.rst b/samples/drivers/dac/README.rst index 2803abd8ba7621..a9983494389089 100644 --- a/samples/drivers/dac/README.rst +++ b/samples/drivers/dac/README.rst @@ -171,7 +171,7 @@ built and executed for the :ref:`bl5340_dvk` as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/dac - :board: bl5340_dvk_cpuapp + :board: bl5340_dvk/nrf5340/cpuapp :goals: build flash :compact: @@ -206,7 +206,7 @@ also can run for the .. zephyr-app-commands:: :zephyr-app: samples/drivers/dac - :board: longan_nano_lite + :board: longan_nano/gd32vf103/lite :goals: build flash :compact: diff --git a/samples/drivers/dac/boards/bl5340_dvk_cpuapp.overlay b/samples/drivers/dac/boards/bl5340_dvk_nrf5340_cpuapp.overlay similarity index 100% rename from samples/drivers/dac/boards/bl5340_dvk_cpuapp.overlay rename to samples/drivers/dac/boards/bl5340_dvk_nrf5340_cpuapp.overlay diff --git a/samples/drivers/dac/boards/longan_nano_lite.overlay b/samples/drivers/dac/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from samples/drivers/dac/boards/longan_nano_lite.overlay rename to samples/drivers/dac/boards/longan_nano_gd32vf103_lite.overlay diff --git a/samples/drivers/dac/boards/sam_e70_xplained.overlay b/samples/drivers/dac/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_e70_xplained.overlay rename to samples/drivers/dac/boards/sam_e70_xplained_same70q21.overlay diff --git a/samples/drivers/dac/boards/sam_e70b_xplained.overlay b/samples/drivers/dac/boards/sam_e70_xplained_same70q21b.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_e70b_xplained.overlay rename to samples/drivers/dac/boards/sam_e70_xplained_same70q21b.overlay diff --git a/samples/drivers/dac/boards/sam_v71_xult.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_v71_xult.overlay rename to samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay diff --git a/samples/drivers/dac/boards/sam_v71b_xult.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay similarity index 100% rename from samples/drivers/dac/boards/sam_v71b_xult.overlay rename to samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay diff --git a/samples/drivers/dac/sample.yaml b/samples/drivers/dac/sample.yaml index 8ac2943ecfce62..e83c20d5fc0fff 100644 --- a/samples/drivers/dac/sample.yaml +++ b/samples/drivers/dac/sample.yaml @@ -9,18 +9,18 @@ tests: - bl652_dvk - bl653_dvk - bl654_dvk - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp - disco_l475_iot1 - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - frdm_k22f - frdm_k64f - gd32a503v_eval - gd32e103v_eval - gd32f450i_eval - - longan_nano_lite - longan_nano + - longan_nano/gd32vf103/lite - nucleo_f091rc - nucleo_f207zg - nucleo_f429zi @@ -35,10 +35,10 @@ tests: - nucleo_l552ze_q - nucleo_u575zi_q - nucleo_wl55jc - - sam_e70_xplained - - sam_e70b_xplained - - sam_v71_xult - - sam_v71b_xult + - sam_e70_xplained/same70q21 + - sam_e70_xplained/same70q21b + - sam_v71_xult/samv71q21 + - sam_v71_xult/samv71q21b - stm32f3_disco - stm32l562e_dk - twr_ke18f diff --git a/samples/drivers/display/README.rst b/samples/drivers/display/README.rst index 872a0b5f5d2224..68a25e1b9965b3 100644 --- a/samples/drivers/display/README.rst +++ b/samples/drivers/display/README.rst @@ -25,7 +25,7 @@ Below is an example on how to build for a :ref:`nrf52840dk_nrf52840` board with .. zephyr-app-commands:: :zephyr-app: samples/drivers/display - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :shield: adafruit_2_8_tft_touch_v2 :compact: diff --git a/samples/drivers/display/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/drivers/display/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000000..072545354b964a --- /dev/null +++ b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,7 @@ +# +# Copyright 2023, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_HEAP_MEM_POOL_SIZE=4194304 diff --git a/samples/drivers/display/boards/mimxrt595_evk_cm33.conf b/samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from samples/drivers/display/boards/mimxrt595_evk_cm33.conf rename to samples/drivers/display/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/samples/drivers/display/sample.yaml b/samples/drivers/display/sample.yaml index 579773f3c8c8ed..e1d938eda056b4 100644 --- a/samples/drivers/display/sample.yaml +++ b/samples/drivers/display/sample.yaml @@ -9,8 +9,8 @@ tests: - arduino_spi platform_exclude: - reel_board - - reel_board_v2 - - ubx_evkannab1_nrf52832 + - reel_board@2 + - ubx_evkannab1/nrf52832 - stm32f769i_disco - pan1781_evb - pan1782_evb @@ -23,7 +23,7 @@ tests: harness_config: fixture: fixture_display sample.display.shield.ssd1306_128x32: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=ssd1306_128x32 tags: - display @@ -32,7 +32,7 @@ tests: harness_config: fixture: fixture_display sample.display.shield.ssd1306_128x64: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=ssd1306_128x64 tags: - display @@ -41,19 +41,19 @@ tests: harness_config: fixture: fixture_display sample.display.shield.waveshare_epaper_gdeh0213b1: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=waveshare_epaper_gdeh0213b1 harness: console harness_config: fixture: fixture_display sample.display.shield.waveshare_epaper_gdew042t2: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=waveshare_epaper_gdew042t2 harness: console harness_config: fixture: fixture_display sample.display.st7789v_tl019fqv01: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=st7789v_tl019fqv01 tags: - display @@ -62,7 +62,7 @@ tests: harness_config: fixture: fixture_display sample.display.st7789v_waveshare_240x240: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=st7789v_waveshare_240x240 tags: - display @@ -71,7 +71,7 @@ tests: harness_config: fixture: fixture_display sample.display.ls013b7dh03: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=ls013b7dh03 tags: - display @@ -80,7 +80,7 @@ tests: harness_config: fixture: fixture_display sample.display.st7735r_ada_160x128: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: SHIELD=st7735r_ada_160x128 tags: - display @@ -95,7 +95,7 @@ tests: harness_config: fixture: fixture_display sample.display.mcux_dcnano_lcdif: - platform_allow: mimxrt595_evk_cm33 + platform_allow: mimxrt595_evk/mimxrt595s/cm33 tags: display harness: console extra_args: SHIELD=rk055hdmipi4m @@ -118,7 +118,7 @@ tests: - CONFIG_TEST=y tags: display sample.display.max7219: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=max7219_8x8 tags: - display @@ -127,7 +127,7 @@ tests: harness_config: fixture: fixture_display sample.display.st_b_lcd40_dsi1_mb1166: - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 tags: - display @@ -136,7 +136,7 @@ tests: harness_config: fixture: fixture_display sample.display.g1120b0mipi: - platform_allow: mimxrt595_evk_cm33 + platform_allow: mimxrt595_evk/mimxrt595s/cm33 tags: display harness: console extra_args: SHIELD=g1120b0mipi diff --git a/samples/drivers/eeprom/README.rst b/samples/drivers/eeprom/README.rst index 079a3ebb469b8c..5381444bac5e03 100644 --- a/samples/drivers/eeprom/README.rst +++ b/samples/drivers/eeprom/README.rst @@ -30,7 +30,7 @@ as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/eeprom - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :shield: x_nucleo_eeprma2 :compact: diff --git a/samples/drivers/eeprom/sample.yaml b/samples/drivers/eeprom/sample.yaml index c9dfa7dd071a16..1c592eb87817b1 100644 --- a/samples/drivers/eeprom/sample.yaml +++ b/samples/drivers/eeprom/sample.yaml @@ -26,9 +26,9 @@ tests: - arduino_i2c - arduino_spi platform_exclude: - - ubx_evkannab1_nrf52832 - - sam_v71_xult - - sam_v71b_xult + - ubx_evkannab1/nrf52832 + - sam_v71_xult/samv71q21 + - sam_v71_xult/samv71q21b - pan1781_evb - pan1782_evb - pan1770_evb diff --git a/samples/drivers/flash_shell/sample.yaml b/samples/drivers/flash_shell/sample.yaml index 2734a63c7dec32..cd19cdad656fc7 100644 --- a/samples/drivers/flash_shell/sample.yaml +++ b/samples/drivers/flash_shell/sample.yaml @@ -8,11 +8,11 @@ tests: - shell filter: CONFIG_FLASH_HAS_DRIVER_ENABLED platform_exclude: - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 - gd32f350r_eval - - arduino_portenta_h7_m4 - - arduino_giga_r1_m4 + - arduino_portenta_h7/stm32h747xx/m4 + - arduino_giga_r1/stm32h747xx/m4 harness: keyboard min_ram: 12 integration_platforms: diff --git a/samples/drivers/ht16k33/README.rst b/samples/drivers/ht16k33/README.rst index 06fcc50a69782d..f0bde1a10790c3 100644 --- a/samples/drivers/ht16k33/README.rst +++ b/samples/drivers/ht16k33/README.rst @@ -28,7 +28,7 @@ connect an HT16K33 LED driver at address 0x70 on the I2C-0 bus. .. zephyr-app-commands:: :zephyr-app: samples/drivers/ht16k33 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/drivers/ht16k33/sample.yaml b/samples/drivers/ht16k33/sample.yaml index ed0ed04acd6e4d..3bb0107b60b064 100644 --- a/samples/drivers/ht16k33/sample.yaml +++ b/samples/drivers/ht16k33/sample.yaml @@ -3,6 +3,6 @@ sample: name: HT16K33 sample tests: sample.drivers.ht16k33: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness: TBD tags: LED diff --git a/samples/drivers/i2s/echo/README.rst b/samples/drivers/i2s/echo/README.rst index 8f7838d6298230..6dfb674c1e242b 100644 --- a/samples/drivers/i2s/echo/README.rst +++ b/samples/drivers/i2s/echo/README.rst @@ -22,8 +22,8 @@ a devicetree node label named ``i2s_rxtx`` or separate node labels ``i2s_rx`` and ``i2s_tx`` if separate I2S devices are to be used for the RX and TX streams. -This sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk_nrf52840) -and :ref:`nrf5340dk_nrf5340` (nrf5340dk_nrf5340_cpuapp), using the Audio Codec +This sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk/nrf52840) +and :ref:`nrf5340dk_nrf5340` (nrf5340dk/nrf5340/cpuapp), using the Audio Codec Shield, and provides overlay files for both of these boards. More information about the used shield and the CODEC itself can be found here: @@ -40,7 +40,7 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/drivers/i2s/echo - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/i2s/echo/sample.yaml b/samples/drivers/i2s/echo/sample.yaml index f5ce0e58dd0d2b..ca9c7bc859bb2b 100644 --- a/samples/drivers/i2s/echo/sample.yaml +++ b/samples/drivers/i2s/echo/sample.yaml @@ -6,8 +6,8 @@ tests: filter: dt_nodelabel_enabled("i2s_rxtx") or (dt_nodelabel_enabled("i2s_rx") and dt_nodelabel_enabled("i2s_tx")) integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp platform_exclude: litex_vexriscv harness: console harness_config: diff --git a/samples/drivers/ipm/ipm_esp32/CMakeLists.txt b/samples/drivers/ipm/ipm_esp32/CMakeLists.txt index 8386967632472c..c4399df8a9280d 100644 --- a/samples/drivers/ipm/ipm_esp32/CMakeLists.txt +++ b/samples/drivers/ipm/ipm_esp32/CMakeLists.txt @@ -4,12 +4,12 @@ cmake_minimum_required(VERSION 3.20.0) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/ipm_esp32_appcpu-prefix/src/ipm_esp32_appcpu-build/zephyr) -if("${BOARD}" STREQUAL "esp32_devkitc_wrover") - set(BOARD_REMOTE "esp32_devkitc_wrover_appcpu") -elseif("${BOARD}" STREQUAL "esp32_devkitc_wroom") - set(BOARD_REMOTE "esp32_devkitc_wroom_appcpu") -elseif("${BOARD}" STREQUAL "esp32s3_devkitm") - set(BOARD_REMOTE "esp32s3_devkitm_appcpu") +if("${BOARD}" STREQUAL "esp32_devkitc_wrover/esp32/procpu") + set(BOARD_REMOTE "esp32_devkitc_wrover/esp32/appcpu") +elseif("${BOARD}" STREQUAL "esp32_devkitc_wroom/esp32/procpu") + set(BOARD_REMOTE "esp32_devkitc_wroom/esp32/appcpu") +elseif("${BOARD}" STREQUAL "esp32s3_devkitm/esp32s3/procpu") + set(BOARD_REMOTE "esp32s3_devkitm/esp32s3/appcpu") else() message(FATAL_ERROR "${BOARD} was not supported for this sample") endif() diff --git a/samples/drivers/ipm/ipm_esp32/README.rst b/samples/drivers/ipm/ipm_esp32/README.rst index 3219ee7b307ddf..5deb498b2f9d58 100644 --- a/samples/drivers/ipm/ipm_esp32/README.rst +++ b/samples/drivers/ipm/ipm_esp32/README.rst @@ -26,7 +26,7 @@ Build the ESP32 IPM sample code as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_esp32 - :board: esp32_devkitc_wroom + :board: esp32_devkitc_wroom/esp32/procpu :goals: build :compact: diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.conf b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.conf deleted file mode 100644 index 0bef3d481fdde5..00000000000000 --- a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32_PROCPU=y diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.overlay b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom_esp32_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom.overlay rename to samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wroom_esp32_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.conf b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.conf deleted file mode 100644 index 0bef3d481fdde5..00000000000000 --- a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32_PROCPU=y diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.overlay b/samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover_esp32_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover.overlay rename to samples/drivers/ipm/ipm_esp32/boards/esp32_devkitc_wrover_esp32_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.conf b/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.conf deleted file mode 100644 index a8ee714a955969..00000000000000 --- a/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SOC_ESP32S3_PROCPU=y diff --git a/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.overlay b/samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm_esp32s3_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm.overlay rename to samples/drivers/ipm/ipm_esp32/boards/esp32s3_devkitm_esp32s3_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/boards/yd_esp32.overlay b/samples/drivers/ipm/ipm_esp32/boards/yd_esp32_esp32_procpu.overlay similarity index 100% rename from samples/drivers/ipm/ipm_esp32/boards/yd_esp32.overlay rename to samples/drivers/ipm/ipm_esp32/boards/yd_esp32_esp32_procpu.overlay diff --git a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wroom_appcpu.overlay b/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wroom_appcpu.overlay deleted file mode 100644 index 80f7950333f2b2..00000000000000 --- a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wroom_appcpu.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&ipm0 { - status = "okay"; -}; diff --git a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wrover_appcpu.overlay b/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wrover_appcpu.overlay deleted file mode 100644 index 80f7950333f2b2..00000000000000 --- a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32_devkitc_wrover_appcpu.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&ipm0 { - status = "okay"; -}; diff --git a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32s3_dekvitm_appcpu.overlay b/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32s3_dekvitm_appcpu.overlay deleted file mode 100644 index 80f7950333f2b2..00000000000000 --- a/samples/drivers/ipm/ipm_esp32/ipm_esp_appcpu/boards/esp32s3_dekvitm_appcpu.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&ipm0 { - status = "okay"; -}; diff --git a/samples/drivers/ipm/ipm_esp32/sample.yaml b/samples/drivers/ipm/ipm_esp32/sample.yaml index 0e7384093e5962..68ef394450ceb0 100644 --- a/samples/drivers/ipm/ipm_esp32/sample.yaml +++ b/samples/drivers/ipm/ipm_esp32/sample.yaml @@ -2,7 +2,10 @@ sample: name: ESP32 IPM Sample tests: sample.ipm.ipm_esp32: - platform_allow: esp32_devkitc_wroom esp32_devkitc_wrover + platform_allow: + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu tags: - samples - ipm + skip: true diff --git a/samples/drivers/ipm/ipm_imx/README.rst b/samples/drivers/ipm/ipm_imx/README.rst index 570f711536253d..ecffdbede07b38 100644 --- a/samples/drivers/ipm/ipm_imx/README.rst +++ b/samples/drivers/ipm/ipm_imx/README.rst @@ -35,11 +35,11 @@ It can be built as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_imx - :board: udoo_neo_full_m4 + :board: udoo_neo_full/mcimx6x/m4 :goals: build flash :compact: -Follow the instructions in the :ref:`udoo_neo_full_m4` board documentation +Follow the instructions in the :ref:`udoo_neo_full` board documentation for how to load the Zephyr binary to the desired core and execute it. Building and Running the Linux Code diff --git a/samples/drivers/ipm/ipm_imx/sample.yaml b/samples/drivers/ipm/ipm_imx/sample.yaml index 227faf7a8dc34c..b6adc4db10fcd1 100644 --- a/samples/drivers/ipm/ipm_imx/sample.yaml +++ b/samples/drivers/ipm/ipm_imx/sample.yaml @@ -5,13 +5,13 @@ sample: tests: sample.ipm.ipm_imx: build_only: true - filter: CONFIG_SOC_FAMILY_IMX + filter: CONFIG_SOC_FAMILY_NXP_IMX platform_allow: - - udoo_neo_full_m4 - - colibri_imx7d_m4 - - warp7_m4 + - udoo_neo_full/mcimx6x/m4 + - colibri_imx7d/mcimx7d/m4 + - warp7/mcimx7d/m4 integration_platforms: - - udoo_neo_full_m4 + - udoo_neo_full/mcimx6x/m4 tags: - samples - ipm diff --git a/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild b/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild index 208a052f83d4d4..242d25e0f68fa6 100644 --- a/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild +++ b/samples/drivers/ipm/ipm_mcux/Kconfig.sysbuild @@ -6,5 +6,5 @@ source "share/sysbuild/Kconfig" config IPM_REMOTE_BOARD string - default "lpcxpresso54114_m0" if $(BOARD) = "lpcxpresso54114_m4" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "lpcxpresso54114/lpc54114/m0" if $(BOARD) = "lpcxpresso54114" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/samples/drivers/ipm/ipm_mcux/README.rst b/samples/drivers/ipm/ipm_mcux/README.rst index 1fcd1e9818e6a7..887437403f5a5f 100644 --- a/samples/drivers/ipm/ipm_mcux/README.rst +++ b/samples/drivers/ipm/ipm_mcux/README.rst @@ -21,21 +21,21 @@ Requirements - :ref:`lpcxpresso54114` board - :ref:`lpcxpresso55s69` board -Building the application for lpcxpresso54114_m4 -*********************************************** +Building the application for lpcxpresso54114/lpc54114/m4 +******************************************************** .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mcux - :board: lpcxpresso54114_m4 + :board: lpcxpresso54114/lpc54114/m4 :goals: debug -Building the application for lpcxpresso55s69_cpu0 -************************************************* +Building the application for lpcxpresso55s69/lpc55s69/cpu0 +********************************************************** .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mcux - :board: lpcxpresso55s69_cpu0 + :board: lpcxpresso55s69/lpc55s69/cpu0 :goals: debug Running diff --git a/samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_m4.conf b/samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_lpc54114_m4.conf similarity index 100% rename from samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_m4.conf rename to samples/drivers/ipm/ipm_mcux/boards/lpcxpresso54114_lpc54114_m4.conf diff --git a/samples/drivers/ipm/ipm_mcux/remote/sample.yaml b/samples/drivers/ipm/ipm_mcux/remote/sample.yaml index 2daa712630812d..82d8dc9e3dea4c 100644 --- a/samples/drivers/ipm/ipm_mcux/remote/sample.yaml +++ b/samples/drivers/ipm/ipm_mcux/remote/sample.yaml @@ -5,9 +5,9 @@ sample: tests: sample.ipm.ipm_mcux.remote: platform_allow: - - lpcxpresso54114_m0 - - lpcxpresso55s69_cpu1 + - lpcxpresso54114/lpc54114/m0 + - lpcxpresso55s69/lpc55s69/cpu1 integration_platforms: - - lpcxpresso54114_m0 + - lpcxpresso54114/lpc54114/m0 tags: ipm harness: remote diff --git a/samples/drivers/ipm/ipm_mcux/sample.yaml b/samples/drivers/ipm/ipm_mcux/sample.yaml index 6d46791d7a4c0b..4df4045e45495a 100644 --- a/samples/drivers/ipm/ipm_mcux/sample.yaml +++ b/samples/drivers/ipm/ipm_mcux/sample.yaml @@ -5,10 +5,10 @@ sample: tests: sample.ipm.ipm_mcux: platform_allow: - - lpcxpresso54114_m4 - - lpcxpresso55s69_cpu0 + - lpcxpresso54114/lpc54114/m4 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - lpcxpresso54114_m4 + - lpcxpresso54114/lpc54114/m4 tags: ipm harness: console sysbuild: true diff --git a/samples/drivers/ipm/ipm_mhu_dual_core/README.rst b/samples/drivers/ipm/ipm_mhu_dual_core/README.rst index fc6414d83ffe9c..750b32fd0a02c2 100644 --- a/samples/drivers/ipm/ipm_mhu_dual_core/README.rst +++ b/samples/drivers/ipm/ipm_mhu_dual_core/README.rst @@ -27,7 +27,7 @@ It can be built and executed on Musca B1 CPU 0 as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core - :board: v2m_musca_b1 + :board: v2m_musca_b1/musca_b1 :goals: run :compact: @@ -36,7 +36,7 @@ It can be built and executed on Musca B1 CPU 1 as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/ipm/ipm_mhu_dual_core - :board: v2m_musca_b1_ns + :board: v2m_musca_b1/musca_b1/ns :goals: run :compact: diff --git a/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml b/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml index 935f5ced8d3b75..83473ed088d2fe 100644 --- a/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml +++ b/samples/drivers/ipm/ipm_mhu_dual_core/sample.yaml @@ -5,7 +5,7 @@ tests: sample.ipm.ipm_mhu_dual_core: tags: ipm platform_allow: - - v2m_musca_b1 - - v2m_musca_b1_ns + - v2m_musca_b1/musca_b1 + - v2m_musca_b1/musca_b1/ns integration_platforms: - - v2m_musca_b1 + - v2m_musca_b1/musca_b1 diff --git a/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay b/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay index 68086d46fc70d6..e9bbc3fbf379ac 100644 --- a/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay +++ b/samples/drivers/jesd216/boards/nrf52840dk_nrf52840_spi.overlay @@ -10,7 +10,7 @@ status = "disabled"; }; -/* The mx25, on nrf52840dk_nrf52840, uses pins for spi0, spi1, spi2 and spi3 +/* The mx25, on nrf52840dk/nrf52840, uses pins for spi0, spi1, spi2 and spi3 * to provide quad-spi feature. In individual specifications each of the spi * notes define own clock source (SCK), but spi2 shares the same clock source * as qspi configuration, which is pin (0,19). That is why spi2 is used here diff --git a/samples/drivers/jesd216/sample.yaml b/samples/drivers/jesd216/sample.yaml index c50ce41d0f3183..4ab18259153c73 100644 --- a/samples/drivers/jesd216/sample.yaml +++ b/samples/drivers/jesd216/sample.yaml @@ -17,17 +17,17 @@ tests: - hifive1 - hifive_unleashed - hifive_unmatched - - mimxrt1170_evk_cm7 - - mimxrt1170_evk_cm4 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm4 filter: dt_compat_enabled("jedec,spi-nor") depends_on: spi sample.drivers.jesd216.nrf52840dk_spi: extra_args: - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_spi.overlay - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_spi.conf - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.drivers.stm32.jesd216: filter: dt_compat_enabled("st,stm32-ospi-nor") or dt_compat_enabled("st,stm32-qspi-nor") depends_on: spi diff --git a/samples/drivers/lcd_hd44780/src/main.c b/samples/drivers/lcd_hd44780/src/main.c index 19f873e52d4ae1..3210f9c030534c 100644 --- a/samples/drivers/lcd_hd44780/src/main.c +++ b/samples/drivers/lcd_hd44780/src/main.c @@ -70,14 +70,13 @@ #include #include - -#if defined(CONFIG_SOC_PART_NUMBER_SAM3X8E) +#if defined(CONFIG_SOC_SAM3X8E) #define GPIO_NODE DT_NODELABEL(pioc) #else #error "Unsupported GPIO driver" #endif -#if defined(CONFIG_SOC_PART_NUMBER_SAM3X8E) +#if defined(CONFIG_SOC_SAM3X8E) /* Define GPIO OUT to LCD */ #define GPIO_PIN_PC12_D0 12 /* PC12 - pin 51 */ #define GPIO_PIN_PC13_D1 13 /* PC13 - pin 50 */ diff --git a/samples/drivers/led_lp5562/README.rst b/samples/drivers/led_lp5562/README.rst index 4848455ab329ec..62994f5e7a5b23 100644 --- a/samples/drivers/led_lp5562/README.rst +++ b/samples/drivers/led_lp5562/README.rst @@ -35,7 +35,7 @@ a LP5562 LED driver on the bus I2C0 at the address 0x30. .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_lp5562 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/drivers/led_lp5562/sample.yaml b/samples/drivers/led_lp5562/sample.yaml index 24b46765155ef1..128258cb9beb74 100644 --- a/samples/drivers/led_lp5562/sample.yaml +++ b/samples/drivers/led_lp5562/sample.yaml @@ -3,6 +3,6 @@ sample: name: LP5562 sample tests: sample.drivers.led.lp5562: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: led harness: TBD diff --git a/samples/drivers/led_lp5569/README.rst b/samples/drivers/led_lp5569/README.rst index f9d0f5febd9ff0..456bc2baaad84c 100644 --- a/samples/drivers/led_lp5569/README.rst +++ b/samples/drivers/led_lp5569/README.rst @@ -18,7 +18,7 @@ a LP5569 LED controller on the bus I2C0 at the address 0x32. .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_lp5569 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/drivers/led_lp5569/sample.yaml b/samples/drivers/led_lp5569/sample.yaml index 40d8f24ace1731..25b03a87b318e0 100644 --- a/samples/drivers/led_lp5569/sample.yaml +++ b/samples/drivers/led_lp5569/sample.yaml @@ -3,5 +3,5 @@ sample: name: LP5569 sample tests: sample.drivers.led.lp5569: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: led diff --git a/samples/drivers/led_lpd8806/boards/96b_carbon.conf b/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf similarity index 100% rename from samples/drivers/led_lpd8806/boards/96b_carbon.conf rename to samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.conf diff --git a/samples/drivers/led_lpd8806/boards/96b_carbon.overlay b/samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.overlay similarity index 100% rename from samples/drivers/led_lpd8806/boards/96b_carbon.overlay rename to samples/drivers/led_lpd8806/boards/96b_carbon_stm32f401xe.overlay diff --git a/samples/drivers/led_lpd8806/sample.yaml b/samples/drivers/led_lpd8806/sample.yaml index cca50ea3751ae9..7d0e66d79bae82 100644 --- a/samples/drivers/led_lpd8806/sample.yaml +++ b/samples/drivers/led_lpd8806/sample.yaml @@ -3,5 +3,5 @@ sample: name: LPD880x sample tests: sample.drivers.led.lpd8806: - platform_allow: 96b_carbon + platform_allow: 96b_carbon/stm32f401xe tags: LED diff --git a/samples/drivers/led_sx1509b_intensity/README.rst b/samples/drivers/led_sx1509b_intensity/README.rst index 2fdeee737ac0a6..2ed8eb826ec264 100644 --- a/samples/drivers/led_sx1509b_intensity/README.rst +++ b/samples/drivers/led_sx1509b_intensity/README.rst @@ -15,7 +15,7 @@ Building and Running .. zephyr-app-commands:: :zephyr-app: samples/drivers/led_sx1509b_intensity - :board: thingy52_nrf52832 + :board: thingy52/nrf52832 :goals: build flash :compact: diff --git a/samples/drivers/led_sx1509b_intensity/sample.yaml b/samples/drivers/led_sx1509b_intensity/sample.yaml index 9893d3a0969880..532626276b7384 100644 --- a/samples/drivers/led_sx1509b_intensity/sample.yaml +++ b/samples/drivers/led_sx1509b_intensity/sample.yaml @@ -9,6 +9,6 @@ sample: name: SX1509B intensity sample tests: sample.drivers.led.sx1509b_intensity: - platform_allow: thingy52_nrf52832 + platform_allow: thingy52/nrf52832 tags: LED depends_on: i2c diff --git a/samples/drivers/led_ws2812/README.rst b/samples/drivers/led_ws2812/README.rst index 183875520f2d27..d41bad1e207888 100644 --- a/samples/drivers/led_ws2812/README.rst +++ b/samples/drivers/led_ws2812/README.rst @@ -69,7 +69,7 @@ To make sure the sample is set up properly for building, you must: For example devicetree configurations for each compatible, see :zephyr_file:`samples/drivers/led_ws2812/boards/thingy52_nrf52832.overlay`, :zephyr_file:`samples/drivers/led_ws2812/boards/nrf52dk_nrf52832.overlay` and -:zephyr_file:`samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.overlay`. +:zephyr_file:`samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay`. Some boards are already supported out of the box; see the :file:`boards` directory for this sample for details. @@ -101,15 +101,14 @@ This sample uses different drivers depending on the selected board: I2S driver: -- thingy52_nrf52832 -- nrf5340dk_nrf5340 (3.3V logic level, a logic level shifter may be required) +- thingy52/nrf52832 +- nrf5340dk/nrf5340 (3.3V logic level, a logic level shifter may be required) - should work for other boards featuring an nRF5340 host processor SPI driver: - mimxrt1050_evk -- mimxrt1050_evk_qspi -- nrf52dk_nrf52832 +- nrf52dk/nrf52832 - nucleo_f070rb - nucleo_g071rb - nucleo_h743zi @@ -118,7 +117,7 @@ SPI driver: GPIO driver (cortex-M0 only): - bbc_microbit -- nrf51dk_nrf51422 +- nrf51dk/nrf51822 References ********** diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.conf b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.conf rename to samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.conf diff --git a/samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.overlay b/samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/drivers/led_ws2812/boards/nrf51dk_nrf51422.overlay rename to samples/drivers/led_ws2812/boards/nrf51dk_nrf51822.overlay diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt index ec79db9deed4b6..382aefad0ddc96 100644 --- a/samples/drivers/mbox/CMakeLists.txt +++ b/samples/drivers/mbox/CMakeLists.txt @@ -11,13 +11,13 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp") OR - ("${BOARD}" STREQUAL "adp_xc7k_ae350") OR - ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0")) + ("${BOARD}" STREQUAL "adp_xc7k") OR + ("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild index a17dd56ee558be..53f83ddeb9ee8e 100644 --- a/samples/drivers/mbox/Kconfig.sysbuild +++ b/samples/drivers/mbox/Kconfig.sysbuild @@ -7,10 +7,10 @@ source "share/sysbuild/Kconfig" config REMOTE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" - default "adp_xc7k_ae350" if $(BOARD) = "adp_xc7k_ae350" - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "adp_xc7k/ae350" if $(BOARD) = "adp_xc7k" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/samples/drivers/mbox/README.rst b/samples/drivers/mbox/README.rst index cee903710f7737..e4ab895ade4950 100644 --- a/samples/drivers/mbox/README.rst +++ b/samples/drivers/mbox/README.rst @@ -14,12 +14,12 @@ Building and Running The sample can be built and executed on boards supporting MBOX. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/drivers/mbox/ - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug :west-args: --sysbuild diff --git a/samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.conf b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.conf rename to samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.overlay b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from samples/drivers/mbox/boards/lpcxpresso55s69_cpu0.overlay rename to samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from samples/drivers/mbox/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from samples/drivers/mbox/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from samples/drivers/mbox/boards/mimxrt1170_evkb_cm7.overlay rename to samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000000..0dfb100ed70476 --- /dev/null +++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000000..942f67ba6a9d72 --- /dev/null +++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,29 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c48000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c48000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c48000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt index 2c7c8fff29e781..5fbec71ce413e4 100644 --- a/samples/drivers/mbox/remote/CMakeLists.txt +++ b/samples/drivers/mbox/remote/CMakeLists.txt @@ -9,13 +9,13 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpunet") OR +if(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpunet") OR - ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1") OR - ("${BOARD}" STREQUAL "adp_xc7k_ae350")) + ("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69") OR + ("${BOARD}" STREQUAL "adp_xc7k")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.conf b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.conf rename to samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.overlay b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from samples/drivers/mbox/remote/boards/lpcxpresso55s69_cpu1.overlay rename to samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000000..cc05e9b96c1cbb --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,48 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000000..cc05e9b96c1cbb --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,48 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000000..392141712a9dec --- /dev/null +++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,49 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; + +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml index e38deda55d3135..1e0feb4e3f0acc 100644 --- a/samples/drivers/mbox/sample.yaml +++ b/samples/drivers/mbox/sample.yaml @@ -6,14 +6,14 @@ common: tests: sample.drivers.mbox.real_hw: platform_allow: - - nrf5340dk_nrf5340_cpuapp - - adp_xc7k_ae350 - - mimxrt1170_evkb_cm7 - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - nrf5340dk/nrf5340/cpuapp + - adp_xc7k/ae350 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/drivers/mbox/sysbuild.cmake b/samples/drivers/mbox/sysbuild.cmake index 063f6157ddb220..2e7d69d9da5899 100644 --- a/samples/drivers/mbox/sysbuild.cmake +++ b/samples/drivers/mbox/sysbuild.cmake @@ -23,7 +23,7 @@ native_simulator_set_final_executable(${DEFAULT_IMAGE}) if ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7" OR "${BOARD}" STREQUAL "mimxrt1170_evk_cm7" OR "${BOARD}" STREQUAL "mimxrt1160_evk_cm7" OR - "${BOARD}" STREQUAL "lpcxpresso55s69_cpu0" + "${BOARD}" STREQUAL "lpcxpresso55s69" ) # For these NXP boards the main core application is dependent on # 'zephyr_image_info.h' generated by remote application. diff --git a/samples/drivers/mbox_data/CMakeLists.txt b/samples/drivers/mbox_data/CMakeLists.txt index a410ac3d214940..fa444f592df913 100644 --- a/samples/drivers/mbox_data/CMakeLists.txt +++ b/samples/drivers/mbox_data/CMakeLists.txt @@ -9,10 +9,10 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox_data/Kconfig.sysbuild b/samples/drivers/mbox_data/Kconfig.sysbuild index 2ddab22817754b..66a4e929ae2f95 100644 --- a/samples/drivers/mbox_data/Kconfig.sysbuild +++ b/samples/drivers/mbox_data/Kconfig.sysbuild @@ -6,7 +6,7 @@ source "share/sysbuild/Kconfig" config REMOTE_BOARD string - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.conf b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.conf rename to samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.overlay b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from samples/drivers/mbox_data/boards/lpcxpresso55s69_cpu0.overlay rename to samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.conf b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.conf rename to samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from samples/drivers/mbox_data/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000000..583b495036082b --- /dev/null +++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from samples/drivers/mbox_data/boards/mimxrt1170_evkb_cm7.overlay rename to samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000000..0dfb100ed70476 --- /dev/null +++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_cm7.overlay rename to samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/samples/drivers/mbox_data/remote/CMakeLists.txt b/samples/drivers/mbox_data/remote/CMakeLists.txt index 47e1cae86284fd..234d58a2164369 100644 --- a/samples/drivers/mbox_data/remote/CMakeLists.txt +++ b/samples/drivers/mbox_data/remote/CMakeLists.txt @@ -7,10 +7,10 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf rename to samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay rename to samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000000..3f6115b9c583b7 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000000..3f6115b9c583b7 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000000..e3576826702554 --- /dev/null +++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,55 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; + +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/drivers/mbox_data/sample.yaml b/samples/drivers/mbox_data/sample.yaml index b4a1e23a9bcee8..53390b5b16a249 100644 --- a/samples/drivers/mbox_data/sample.yaml +++ b/samples/drivers/mbox_data/sample.yaml @@ -6,13 +6,13 @@ common: tests: sample.drivers.mbox_data.real_hw: platform_allow: - - mimxrt1170_evkb_cm7 - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 harness: console harness_config: type: multi_line diff --git a/samples/drivers/memc/README.rst b/samples/drivers/memc/README.rst index 814b7e949fc517..fbfcc08c60698c 100644 --- a/samples/drivers/memc/README.rst +++ b/samples/drivers/memc/README.rst @@ -23,11 +23,11 @@ This application can be built and executed on an RT595 EVK as follows: .. zephyr-app-commands:: :zephyr-app: samples/drivers/memc :host-os: unix - :board: mimxrt595_evk_cm33 + :board: mimxrt595_evk/mimxrt595s/cm33 :goals: run :compact: -To build for another board, change "mimxrt595_evk_cm33" above to that +To build for another board, change "mimxrt595_evk/mimxrt595s/cm33" above to that board's name. Sample Output diff --git a/samples/drivers/memc/boards/mimxrt595_evk_cm33.overlay b/samples/drivers/memc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from samples/drivers/memc/boards/mimxrt595_evk_cm33.overlay rename to samples/drivers/memc/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/samples/drivers/memc/sample.yaml b/samples/drivers/memc/sample.yaml index 2ffbc370252a20..d9fa753edf571e 100644 --- a/samples/drivers/memc/sample.yaml +++ b/samples/drivers/memc/sample.yaml @@ -5,7 +5,7 @@ common: tags: memc filter: dt_alias_exists("sram-ext") integration_platforms: - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 harness: console harness_config: type: one_line diff --git a/samples/drivers/misc/ft800/README.rst b/samples/drivers/misc/ft800/README.rst index 5c72c3641e6ae4..64e0742c7593fe 100644 --- a/samples/drivers/misc/ft800/README.rst +++ b/samples/drivers/misc/ft800/README.rst @@ -33,7 +33,7 @@ described below: .. zephyr-app-commands:: :zephyr-app: samples/drivers/misc/ft800 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: flash :compact: @@ -42,7 +42,7 @@ below: .. zephyr-app-commands:: :zephyr-app: samples/drivers/misc/ft800 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: ftdi_vm800c :goals: flash :compact: diff --git a/samples/drivers/misc/ft800/sample.yaml b/samples/drivers/misc/ft800/sample.yaml index e9f89259e271e8..4d475ed87345c9 100644 --- a/samples/drivers/misc/ft800/sample.yaml +++ b/samples/drivers/misc/ft800/sample.yaml @@ -6,7 +6,7 @@ tests: - drivers - display depends_on: spi - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=ftdi_vm800c harness: display harness_config: diff --git a/samples/drivers/soc_flash_nrf/README.rst b/samples/drivers/soc_flash_nrf/README.rst index 2ee87739aad002..2b69d8d6cb6390 100644 --- a/samples/drivers/soc_flash_nrf/README.rst +++ b/samples/drivers/soc_flash_nrf/README.rst @@ -27,7 +27,7 @@ or `slot1_ns_partition`, when the Kconfig option is selected. .. zephyr-app-commands:: :zephyr-app: samples/drivers/soc_flash_nrf - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/soc_flash_nrf/sample.yaml b/samples/drivers/soc_flash_nrf/sample.yaml index d1f635ca93faa7..bdec7c607cc035 100644 --- a/samples/drivers/soc_flash_nrf/sample.yaml +++ b/samples/drivers/soc_flash_nrf/sample.yaml @@ -3,11 +3,11 @@ sample: tests: sample.drivers.flash.soc_flash_nrf: platform_allow: - - nrf52dk_nrf52832 - - nrf9160dk_nrf9160 - - nrf9160dk_nrf9160_ns + - nrf52dk/nrf52832 + - nrf9160dk/nrf9160 + - nrf9160dk/nrf9160/ns integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: - flash - drivers diff --git a/samples/drivers/spi_bitbang/README.rst b/samples/drivers/spi_bitbang/README.rst index a8ff597f0023eb..35a784139ee16f 100644 --- a/samples/drivers/spi_bitbang/README.rst +++ b/samples/drivers/spi_bitbang/README.rst @@ -25,7 +25,7 @@ test for receive data. .. zephyr-app-commands:: :zephyr-app: samples/drivers/spi_bitbang - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/drivers/spi_bitbang/sample.yaml b/samples/drivers/spi_bitbang/sample.yaml index cc0941d3b0219b..57fb178b09304b 100644 --- a/samples/drivers/spi_bitbang/sample.yaml +++ b/samples/drivers/spi_bitbang/sample.yaml @@ -6,7 +6,7 @@ tests: - drivers - spi - gpio - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 depends_on: gpio harness: console harness_config: diff --git a/samples/drivers/spi_flash/README.rst b/samples/drivers/spi_flash/README.rst index 6f2e81959be408..3767444b3a2c8c 100644 --- a/samples/drivers/spi_flash/README.rst +++ b/samples/drivers/spi_flash/README.rst @@ -25,7 +25,7 @@ The application will build only for a target that has a :ref:`devicetree ` section of the native_sim board diff --git a/samples/drivers/w1/scanner/README.rst b/samples/drivers/w1/scanner/README.rst index 325b02f528c4eb..e9f460975ebf20 100644 --- a/samples/drivers/w1/scanner/README.rst +++ b/samples/drivers/w1/scanner/README.rst @@ -19,7 +19,7 @@ enable and configure the drivers. .. zephyr-app-commands:: :zephyr-app: samples/drivers/w1/scanner - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DDTC_OVERLAY_FILE=w1_serial.overlay :goals: build flash :compact: diff --git a/samples/drivers/w1/scanner/sample.yaml b/samples/drivers/w1/scanner/sample.yaml index c05df2c59e27f6..9a610bf63f12d0 100644 --- a/samples/drivers/w1/scanner/sample.yaml +++ b/samples/drivers/w1/scanner/sample.yaml @@ -8,7 +8,7 @@ tests: sample.drivers.w1.scanner.ds2482-800: depends_on: arduino_i2c extra_args: DTC_OVERLAY_FILE=ds2482-800.overlay - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness_config: type: one_line regex: @@ -18,7 +18,7 @@ tests: depends_on: arduino_i2c extra_args: DTC_OVERLAY_FILE=ds2484.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g0b1re harness_config: type: one_line @@ -29,7 +29,7 @@ tests: depends_on: arduino_i2c extra_args: DTC_OVERLAY_FILE=ds2485.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g0b1re harness_config: type: one_line @@ -41,7 +41,7 @@ tests: - arduino_serial extra_args: DTC_OVERLAY_FILE=w1_serial.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g0b1re harness_config: type: one_line diff --git a/samples/drivers/watchdog/sample.yaml b/samples/drivers/watchdog/sample.yaml index f3e11dda9b5c34..4297f28d77af45 100644 --- a/samples/drivers/watchdog/sample.yaml +++ b/samples/drivers/watchdog/sample.yaml @@ -16,12 +16,12 @@ common: depends_on: watchdog tests: sample.drivers.watchdog: - filter: not (CONFIG_SOC_FAMILY_STM32 or CONFIG_SOC_FAMILY_GD32 or SOC_SERIES_GD32VF103) + filter: not (CONFIG_SOC_FAMILY_STM32 or CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103) platform_exclude: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 sample.drivers.watchdog.stm32_wwdg: extra_args: DTC_OVERLAY_FILE=boards/stm32_wwdg.overlay filter: dt_compat_enabled("st,stm32-window-watchdog") @@ -106,7 +106,7 @@ tests: sample.drivers.watchdog.s32z270dc2_r52: build_only: true platform_allow: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 diff --git a/samples/fuel_gauge/max17048/sample.yaml b/samples/fuel_gauge/max17048/sample.yaml index 0ae4d6c7f3d3a7..82d2b537b8199c 100644 --- a/samples/fuel_gauge/max17048/sample.yaml +++ b/samples/fuel_gauge/max17048/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.sensor.max17048: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: fuel_gauge diff --git a/samples/kernel/metairq_dispatch/sample.yaml b/samples/kernel/metairq_dispatch/sample.yaml index 82090751b33fc5..38431c15c57400 100644 --- a/samples/kernel/metairq_dispatch/sample.yaml +++ b/samples/kernel/metairq_dispatch/sample.yaml @@ -6,7 +6,7 @@ common: tags: - kernel integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 harness: console harness_config: diff --git a/samples/modules/canopennode/sample.yaml b/samples/modules/canopennode/sample.yaml index 279fdf46c28045..7cc95c0ed179c3 100644 --- a/samples/modules/canopennode/sample.yaml +++ b/samples/modules/canopennode/sample.yaml @@ -20,7 +20,7 @@ tests: platform_exclude: - nucleo_h723zg - nucleo_h743zi - - nucleo_h745zi_q + - nucleo_h745zi_q/stm32h745xx/m7 - nucleo_h753zi sample.modules.canopennode.program_download: sysbuild: true diff --git a/samples/modules/lvgl/demos/boards/mimxrt1170_evk_cm7.conf b/samples/modules/lvgl/demos/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/modules/lvgl/demos/boards/mimxrt1170_evk_cm7.conf rename to samples/modules/lvgl/demos/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/modules/lvgl/demos/sample.yaml b/samples/modules/lvgl/demos/sample.yaml index bd7461dd46c3e1..4184f7df1af8a7 100644 --- a/samples/modules/lvgl/demos/sample.yaml +++ b/samples/modules/lvgl/demos/sample.yaml @@ -25,7 +25,7 @@ tests: extra_configs: - CONFIG_LV_Z_DEMO_WIDGETS=y sample.modules.lvgl.demos.st_b_lcd40_dsi1_mb1166: - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 harness: console harness_config: diff --git a/samples/modules/tflite-micro/hello_world/README.rst b/samples/modules/tflite-micro/hello_world/README.rst index 9d6fff4db93cb4..6b639da44731b2 100644 --- a/samples/modules/tflite-micro/hello_world/README.rst +++ b/samples/modules/tflite-micro/hello_world/README.rst @@ -58,7 +58,7 @@ the `PATH` variable, then building and testing can be done with following commands. ``` -$ west build -p auto -b mps3_an547 samples/modules/tflite-micro/hello_world/ -T sample.tensorflow.helloworld.cmsis_nn +$ west build -p auto -b mps3/an547 samples/modules/tflite-micro/hello_world/ -T sample.tensorflow.helloworld.cmsis_nn $ FVP_Corstone_SSE-300_Ethos-U55 build/zephyr/zephyr.elf ``` diff --git a/samples/modules/tflite-micro/hello_world/sample.yaml b/samples/modules/tflite-micro/hello_world/sample.yaml index bfd142f6702794..000db6fffe2ebb 100644 --- a/samples/modules/tflite-micro/hello_world/sample.yaml +++ b/samples/modules/tflite-micro/hello_world/sample.yaml @@ -23,6 +23,6 @@ tests: filter: CONFIG_FULL_LIBC_SUPPORTED sample.tensorflow.helloworld.cmsis_nn: tags: tensorflow - platform_allow: mps3_an547 + platform_allow: mps3/an547 extra_configs: - CONFIG_TENSORFLOW_LITE_MICRO_CMSIS_NN_KERNELS=y diff --git a/samples/modules/tflite-micro/tflm_ethosu/README.rst b/samples/modules/tflite-micro/tflm_ethosu/README.rst index 0156ce8636cfb6..3ebefa36095689 100644 --- a/samples/modules/tflite-micro/tflm_ethosu/README.rst +++ b/samples/modules/tflite-micro/tflm_ethosu/README.rst @@ -33,5 +33,5 @@ commands. .. code-block:: bash - $ west build -b mps3_an547 zephyr/samples/modules/tflite-micro/tflm_ethosu + $ west build -b mps3/an547 zephyr/samples/modules/tflite-micro/tflm_ethosu $ FVP_Corstone_SSE-300_Ethos-U55 build/zephyr/zephyr.elf diff --git a/samples/modules/tflite-micro/tflm_ethosu/sample.yaml b/samples/modules/tflite-micro/tflm_ethosu/sample.yaml index e1ff20cbd0fa49..6e0342e6a56567 100644 --- a/samples/modules/tflite-micro/tflm_ethosu/sample.yaml +++ b/samples/modules/tflite-micro/tflm_ethosu/sample.yaml @@ -10,4 +10,4 @@ tests: filter: dt_compat_enabled("arm,ethos-u") build_only: true integration_platforms: - - mps3_an547 + - mps3/an547 diff --git a/samples/modules/thrift/hello/client/sample.yaml b/samples/modules/thrift/hello/client/sample.yaml index 64ba41fe5e133f..6a1ef0caecd762 100644 --- a/samples/modules/thrift/hello/client/sample.yaml +++ b/samples/modules/thrift/hello/client/sample.yaml @@ -10,7 +10,7 @@ common: modules: - thrift platform_allow: - - mps2_an385 + - mps2/an385 - qemu_x86_64 integration_platforms: - qemu_x86_64 diff --git a/samples/modules/thrift/hello/server/sample.yaml b/samples/modules/thrift/hello/server/sample.yaml index 16b70a6b71038a..02bfe323d01eaa 100644 --- a/samples/modules/thrift/hello/server/sample.yaml +++ b/samples/modules/thrift/hello/server/sample.yaml @@ -10,7 +10,7 @@ common: modules: - thrift platform_allow: - - mps2_an385 + - mps2/an385 - qemu_x86_64 integration_platforms: - qemu_x86_64 diff --git a/samples/net/cloud/mqtt_azure/sample.yaml b/samples/net/cloud/mqtt_azure/sample.yaml index ffa3e86689540f..0513b8e0c2a481 100644 --- a/samples/net/cloud/mqtt_azure/sample.yaml +++ b/samples/net/cloud/mqtt_azure/sample.yaml @@ -7,7 +7,7 @@ tests: sample.net.cloud.mqtt_azure: harness: net platform_allow: - - sam_e70_xplained + - sam_e70_xplained/same70q21 - frdm_k64f - qemu_x86 integration_platforms: diff --git a/samples/net/cloud/tagoio_http_post/README.rst b/samples/net/cloud/tagoio_http_post/README.rst index dc0f2b9da6c061..30778353c503ca 100644 --- a/samples/net/cloud/tagoio_http_post/README.rst +++ b/samples/net/cloud/tagoio_http_post/README.rst @@ -51,7 +51,7 @@ tagoio-http-client sample application with minimal configuration: .. zephyr-app-commands:: :zephyr-app: samples/net/cloud/tagoio_http_post - :board: [sam4e_xpro | sam_v71_xult | frdm_k64f | nucleo_f767zi] + :board: [sam4e_xpro | sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi] :goals: build flash :compact: @@ -75,7 +75,7 @@ need fill ``CONFIG_TAGOIO_HTTP_WIFI_SSID`` with your wifi network SSID and .. zephyr-app-commands:: :zephyr-app: samples/net/cloud/tagoio_http_post - :board: [sam_v71_xult | frdm_k64f | nucleo_f767zi] + :board: [sam_v71_xult/samv71q21 | frdm_k64f | nucleo_f767zi] :shield: [esp_8266_arduino | inventek_eswifi_arduino_uart] :gen-args: -DEXTRA_CONF_FILE=overlay-wifi.conf :goals: build flash diff --git a/samples/net/gptp/boards/sam_e70_xplained.conf b/samples/net/gptp/boards/sam_e70_xplained_same70q21.conf similarity index 100% rename from samples/net/gptp/boards/sam_e70_xplained.conf rename to samples/net/gptp/boards/sam_e70_xplained_same70q21.conf diff --git a/samples/net/gptp/sample.yaml b/samples/net/gptp/sample.yaml index e65327ef47a565..02591c22a6b241 100644 --- a/samples/net/gptp/sample.yaml +++ b/samples/net/gptp/sample.yaml @@ -10,14 +10,14 @@ tests: sample.net.gptp: platform_allow: - frdm_k64f - - sam_e70_xplained + - sam_e70_xplained/same70q21 - native_posix - native_posix_64 - native_sim - native_sim_64 - nucleo_f767zi - nucleo_h743zi - - nucleo_h745zi_q_m7 + - nucleo_h745zi_q/stm32h745xx/m7 depends_on: netif integration_platforms: - frdm_k64f diff --git a/samples/net/ipv4_autoconf/boards/sam_e70_xplained.conf b/samples/net/ipv4_autoconf/boards/sam_e70_xplained.conf deleted file mode 100644 index ce81ebf899e41d..00000000000000 --- a/samples/net/ipv4_autoconf/boards/sam_e70_xplained.conf +++ /dev/null @@ -1,6 +0,0 @@ -# sam_e70_xplained board need more buffers, otherwise it fails to build - -CONFIG_NET_PKT_RX_COUNT=20 -CONFIG_NET_PKT_TX_COUNT=20 -CONFIG_NET_BUF_RX_COUNT=30 -CONFIG_NET_BUF_TX_COUNT=30 diff --git a/samples/net/ipv4_autoconf/boards/sam_e70_xplained_same70q21.conf b/samples/net/ipv4_autoconf/boards/sam_e70_xplained_same70q21.conf new file mode 100644 index 00000000000000..e89285e418cd77 --- /dev/null +++ b/samples/net/ipv4_autoconf/boards/sam_e70_xplained_same70q21.conf @@ -0,0 +1,6 @@ +# sam_e70_xplained/same70q21 board need more buffers, otherwise it fails to build + +CONFIG_NET_PKT_RX_COUNT=20 +CONFIG_NET_PKT_TX_COUNT=20 +CONFIG_NET_BUF_RX_COUNT=30 +CONFIG_NET_BUF_TX_COUNT=30 diff --git a/samples/net/lwm2m_client/sample.yaml b/samples/net/lwm2m_client/sample.yaml index 9c0cada2c1fa09..29fccca4416a59 100644 --- a/samples/net/lwm2m_client/sample.yaml +++ b/samples/net/lwm2m_client/sample.yaml @@ -56,7 +56,7 @@ tests: harness: net extra_args: OVERLAY_CONFIG=overlay-bt.conf platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - disco_l475_iot1 tags: - net @@ -80,7 +80,7 @@ tests: extra_args: SHIELD=wnc_m14a2a platform_allow: - frdm_k64f - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - frdm_k64f tags: diff --git a/samples/net/openthread/coprocessor/README.rst b/samples/net/openthread/coprocessor/README.rst index 9ba9fc62f0dd6b..5fbf49c836833f 100644 --- a/samples/net/openthread/coprocessor/README.rst +++ b/samples/net/openthread/coprocessor/README.rst @@ -37,17 +37,17 @@ Build the OpenThread NCP sample application which uses CDC ACM UART device: .. zephyr-app-commands:: :zephyr-app: samples/net/openthread/coprocessor - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :gen-args: -DDTC_OVERLAY_FILE=usb.overlay -DEXTRA_CONF_FILE=overlay-usb-nrf-br.conf :compact: -Example building for the nrf52840dk_nrf52840 for RCP: +Example building for the nrf52840dk/nrf52840 for RCP: .. zephyr-app-commands:: :zephyr-app: samples/net/openthread/coprocessor :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj.conf overlay-rcp.conf" :goals: run :compact: diff --git a/samples/net/openthread/coprocessor/sample.yaml b/samples/net/openthread/coprocessor/sample.yaml index d8159481aac4af..bf2f2a55b32ce2 100644 --- a/samples/net/openthread/coprocessor/sample.yaml +++ b/samples/net/openthread/coprocessor/sample.yaml @@ -12,18 +12,18 @@ tests: sample.net.openthread.coprocessor: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 - tlsr9518adk80d integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.net.openthread.coprocessor.usb: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: ci_build extra_args: - OVERLAY_CONFIG=overlay-usb-nrf-br.conf @@ -31,9 +31,9 @@ tests: sample.openthread.coprocessor.rcp: build_only: true platform_allow: - - nrf52840dk_nrf52840 - - nrf52833dk_nrf52833 + - nrf52840dk/nrf52840 + - nrf52833dk/nrf52833 - tlsr9518adk80d integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG=overlay-rcp.conf diff --git a/samples/net/sockets/dumb_http_server/sample.yaml b/samples/net/sockets/dumb_http_server/sample.yaml index 13fd552b8aa0e6..23eee0b0d48225 100644 --- a/samples/net/sockets/dumb_http_server/sample.yaml +++ b/samples/net/sockets/dumb_http_server/sample.yaml @@ -9,7 +9,7 @@ common: tags: - net - socket - platform_exclude: intel_adsp_cavs25 + platform_exclude: intel_adsp/cavs25 tests: sample.net.sockets.dumb_http_server: extra_configs: diff --git a/samples/net/sockets/echo_client/README.rst b/samples/net/sockets/echo_client/README.rst index ce9ccf2532b1fd..e142cd8b02fae2 100644 --- a/samples/net/sockets/echo_client/README.rst +++ b/samples/net/sockets/echo_client/README.rst @@ -60,12 +60,12 @@ Build echo-client sample application like this: :goals: build :compact: -Example building for the nrf52840dk_nrf52840 with OpenThread support: +Example building for the nrf52840dk/nrf52840 with OpenThread support: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_client :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj.conf overlay-ot.conf" :goals: run :compact: @@ -75,7 +75,7 @@ Example building for the IEEE 802.15.4 RF2XX transceiver: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_client :host-os: unix - :board: [atsamr21_xpro | sam4s_xplained | sam_v71_xult] + :board: [samr21_xpro | sam4s_xplained | sam_v71_xult/samv71q21] :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :goals: build flash :compact: diff --git a/samples/net/sockets/echo_client/boards/atsamr21_xpro.conf b/samples/net/sockets/echo_client/boards/samr21_xpro.conf similarity index 100% rename from samples/net/sockets/echo_client/boards/atsamr21_xpro.conf rename to samples/net/sockets/echo_client/boards/samr21_xpro.conf diff --git a/samples/net/sockets/echo_client/sample.yaml b/samples/net/sockets/echo_client/sample.yaml index 7c37257e420ef9..008920a33bfd5f 100644 --- a/samples/net/sockets/echo_client/sample.yaml +++ b/samples/net/sockets/echo_client/sample.yaml @@ -13,7 +13,7 @@ tests: platform_allow: - qemu_x86 - frdm_k64f - - sam_e70_xplained + - sam_e70_xplained/same70q21 - qemu_cortex_m3 - frdm_kw41z integration_platforms: @@ -23,7 +23,7 @@ tests: platform_allow: qemu_x86 sample.net.sockets.echo_client.802154.rf2xx: extra_args: OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: atsamr21_xpro + platform_allow: samr21_xpro sample.net.sockets.echo_client.802154.rf2xx.xplained: extra_args: - SHIELD=atmel_rf2xx_xplained @@ -35,33 +35,33 @@ tests: - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_client.802154.rf2xx.legacy: extra_args: - SHIELD=atmel_rf2xx_legacy - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_client.802154.rf2xx.arduino: extra_args: - SHIELD=atmel_rf2xx_arduino - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - - sam_v71_xult + - sam_v71_xult/samv71q21 - frdm_k64f - nucleo_f767zi integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_client.802154.rf2xx.mikrobus: extra_args: - SHIELD=atmel_rf2xx_mikrobus - OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: lpcxpresso55s69_ns + platform_allow: lpcxpresso55s69/lpc55s69/cpu0/ns sample.net.sockets.echo_client.bt: extra_args: OVERLAY_CONFIG="overlay-bt.conf" platform_allow: qemu_x86 @@ -73,14 +73,14 @@ tests: platform_allow: frdm_k64f sample.net.sockets.echo_client.nrf_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 sample.net.sockets.echo_client.nrf_openthread: extra_args: OVERLAY_CONFIG="overlay-ot.conf" slow: true tags: - net - openthread - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC sample.net.sockets.echo_client.b91_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" diff --git a/samples/net/sockets/echo_server/README.rst b/samples/net/sockets/echo_server/README.rst index 20ce37e799181f..0d87359e7b1c45 100644 --- a/samples/net/sockets/echo_server/README.rst +++ b/samples/net/sockets/echo_server/README.rst @@ -64,22 +64,22 @@ Build echo-server sample application like this: :goals: build :compact: -Example building for the nrf52840dk_nrf52840 with OpenThread support: +Example building for the nrf52840dk/nrf52840 with OpenThread support: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :conf: "prj.conf overlay-ot.conf" :goals: run :compact: -Example building for the atsamr21_xpro with RF2XX driver support: +Example building for the samr21_xpro with RF2XX driver support: .. zephyr-app-commands:: :zephyr-app: samples/net/sockets/echo_server :host-os: unix - :board: [atsamr21_xpro | sam4e_xpro | sam_v71_xult] + :board: [samr21_xpro | sam4e_xpro | sam_v71_xult/samv71q21] :gen-args: -DEXTRA_CONF_FILE=overlay-802154.conf :goals: build flash :compact: diff --git a/samples/net/sockets/echo_server/boards/atsamr21_xpro.conf b/samples/net/sockets/echo_server/boards/samr21_xpro.conf similarity index 100% rename from samples/net/sockets/echo_server/boards/atsamr21_xpro.conf rename to samples/net/sockets/echo_server/boards/samr21_xpro.conf diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml index 1174797d04a396..a04c96fe4a041c 100644 --- a/samples/net/sockets/echo_server/sample.yaml +++ b/samples/net/sockets/echo_server/sample.yaml @@ -13,7 +13,7 @@ tests: platform_allow: - qemu_x86 - qemu_x86_64 - - sam_e70_xplained + - sam_e70_xplained/same70q21 - frdm_k64f - qemu_cortex_m3 - frdm_kw41z @@ -36,33 +36,33 @@ tests: - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_server.802154.rf2xx.legacy: extra_args: - SHIELD=atmel_rf2xx_legacy - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - sam4e_xpro - - sam_v71_xult + - sam_v71_xult/samv71q21 integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_server.802154.rf2xx.arduino: extra_args: - SHIELD=atmel_rf2xx_arduino - OVERLAY_CONFIG="overlay-802154.conf" platform_allow: - - sam_v71_xult + - sam_v71_xult/samv71q21 - frdm_k64f - nucleo_f767zi integration_platforms: - - sam_v71_xult + - sam_v71_xult/samv71q21 sample.net.sockets.echo_server.802154.rf2xx.mikrobus: extra_args: - SHIELD=atmel_rf2xx_mikrobus - OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: lpcxpresso55s69_ns + platform_allow: lpcxpresso55s69/lpc55s69/cpu0/ns sample.net.sockets.echo_server.bt: extra_args: OVERLAY_CONFIG="overlay-bt.conf" platform_allow: qemu_x86 @@ -74,7 +74,7 @@ tests: platform_allow: frdm_k64f sample.net.sockets.echo_server.nrf_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 sample.net.sockets.echo_server.b91_802154: extra_args: OVERLAY_CONFIG="overlay-802154.conf" platform_allow: tlsr9518adk80d @@ -91,7 +91,7 @@ tests: tags: - net - openthread - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC sample.net.sockets.echo_server.b91_openthread: extra_args: OVERLAY_CONFIG="overlay-ot.conf" @@ -122,7 +122,7 @@ tests: sample.net.sockets.echo_server.smsc911x: extra_args: OVERLAY_CONFIG="overlay-smsc911x.conf" tags: net - platform_allow: mps2_an385 + platform_allow: mps2/an385 sample.net.sockets.echo_server.userspace: extra_args: - CONFIG_USERSPACE=y diff --git a/samples/net/sockets/txtime/README.rst b/samples/net/sockets/txtime/README.rst index 46979ce68bbceb..d0eb9ad0827c11 100644 --- a/samples/net/sockets/txtime/README.rst +++ b/samples/net/sockets/txtime/README.rst @@ -11,7 +11,7 @@ This sample is a simple UDP sender/receiver which will set the SO_TXTIME socket option and expects the Ethernet driver to send the data when the TX time is expected. The application requires that the board has PTP clock support. A simulated PTP clock is -provided for qemu_x86 board. Also frdm_k64f and sam_e70_xplained boards +provided for qemu_x86 board. Also frdm_k64f and sam_e70_xplained/same70q21 boards are supported. Other mcux or gmac Ethernet driver based boards should work too. User can control how long the application should wait between packets sent by diff --git a/samples/net/sockets/websocket_client/sample.yaml b/samples/net/sockets/websocket_client/sample.yaml index 41ea3a113e982b..a0472b856f967f 100644 --- a/samples/net/sockets/websocket_client/sample.yaml +++ b/samples/net/sockets/websocket_client/sample.yaml @@ -12,5 +12,5 @@ sample: name: websocket_client tests: sample.net.sockets.websocket_client: - platform_exclude: intel_adsp_cavs25 + platform_exclude: intel_adsp/cavs25 harness: net diff --git a/samples/net/wifi/sample.yaml b/samples/net/wifi/sample.yaml index a199e23b636290..c3bbdc08416f43 100644 --- a/samples/net/wifi/sample.yaml +++ b/samples/net/wifi/sample.yaml @@ -16,7 +16,7 @@ tests: - cc3220sf_launchxl sample.net.wifi.mikroe_wifi_bt_click: extra_args: SHIELD=mikroe_wifi_bt_click_mikrobus - platform_allow: lpcxpresso55s69_cpu0 + platform_allow: lpcxpresso55s69/lpc55s69/cpu0 sample.net.wifi.esp_8266: extra_args: SHIELD=esp_8266 platform_allow: sam4e_xpro diff --git a/samples/net/wpan_serial/README.rst b/samples/net/wpan_serial/README.rst index 3bcf5dbb4d49f6..7edaf3b2a9708a 100644 --- a/samples/net/wpan_serial/README.rst +++ b/samples/net/wpan_serial/README.rst @@ -51,7 +51,7 @@ Building and Running .. zephyr-app-commands:: :zephyr-app: samples/net/wpan_serial - :board: atsamr21_xpro + :board: samr21_xpro :goals: build flash :compact: diff --git a/samples/net/wpan_serial/sample.yaml b/samples/net/wpan_serial/sample.yaml index c9ff33d9a42d69..ac48bc1278998f 100644 --- a/samples/net/wpan_serial/sample.yaml +++ b/samples/net/wpan_serial/sample.yaml @@ -9,8 +9,8 @@ common: tests: sample.net.wpan.serial: filter: dt_chosen_enabled("zephyr,ieee802154") - platform_exclude: thingy53_nrf5340_cpuapp_ns raytac_mdbt53_db_40_nrf5340_cpuapp_ns - raytac_mdbt53_db_40_nrf5340_cpuapp + platform_exclude: thingy53/nrf5340/cpuapp/ns raytac_mdbt53_db_40/nrf5340/cpuapp/ns + raytac_mdbt53_db_40/nrf5340/cpuapp sample.net.wpan_serial.frdm_cr20a: extra_args: SHIELD=frdm_cr20a platform_allow: frdm_k64f diff --git a/samples/net/wpanusb/README.rst b/samples/net/wpanusb/README.rst index 27c6c2bae721b7..4c594d359eaad0 100644 --- a/samples/net/wpanusb/README.rst +++ b/samples/net/wpanusb/README.rst @@ -17,7 +17,7 @@ Requirements ************ - a Zephyr board with supported 802.15.4 radio and supported USB driver - (such as the :ref:`nrf52840dk_nrf52840` or :ref:`atsamr21_xpro`) + (such as the :ref:`nrf52840dk_nrf52840` or :ref:`samr21_xpro`) connected via USB to a Linux host - wpanusb Linux kernel driver (in the process of being open sourced) - wpan-tools (available for all Linux distributions) @@ -48,7 +48,7 @@ Example building for the Nordic nRF52840 Development Kit: .. zephyr-app-commands:: :zephyr-app: samples/net/wpanusb - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/net/wpanusb/sample.yaml b/samples/net/wpanusb/sample.yaml index bf16524ea7253f..43371d8c44c231 100644 --- a/samples/net/wpanusb/sample.yaml +++ b/samples/net/wpanusb/sample.yaml @@ -9,8 +9,8 @@ common: tests: sample.net.wpanusb: filter: dt_chosen_enabled("zephyr,ieee802154") - platform_exclude: thingy53_nrf5340_cpuapp_ns raytac_mdbt53_db_40_nrf5340_cpuapp_ns - raytac_mdbt53_db_40_nrf5340_cpuapp + platform_exclude: thingy53/nrf5340/cpuapp/ns raytac_mdbt53_db_40/nrf5340/cpuapp/ns + raytac_mdbt53_db_40/nrf5340/cpuapp sample.net.wpanusb_frdm_cr20a: extra_args: SHIELD=frdm_cr20a platform_allow: frdm_k64f diff --git a/samples/net/zperf/boards/mimxrt1170_evk_cm7.conf b/samples/net/zperf/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/net/zperf/boards/mimxrt1170_evk_cm7.conf rename to samples/net/zperf/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/net/zperf/sample.yaml b/samples/net/zperf/sample.yaml index 99b8f50d31acb7..b3aa90f569f37c 100644 --- a/samples/net/zperf/sample.yaml +++ b/samples/net/zperf/sample.yaml @@ -6,7 +6,7 @@ common: platform_exclude: - native_posix - native_posix_64 - - sam_e70_xplained + - sam_e70_xplained/same70q21 min_ram: 64 sample: description: Network performance measurement tool for Zephyr @@ -44,7 +44,7 @@ tests: harness: net extra_args: OVERLAY_CONFIG="overlay-usbd_next_ecm.conf" DTC_OVERLAY_FILE="usbd_next_ecm.overlay" - platform_allow: nrf52840dk_nrf52840 frdm_k64f + platform_allow: nrf52840dk/nrf52840 frdm_k64f tags: usb net zperf depends_on: usb_device sample.net.zperf.netusb_eem: @@ -91,5 +91,5 @@ tests: - mimxrt1064_evk - mimxrt1024_evk - frdm_k64f - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 diff --git a/samples/posix/eventfd/sample.yaml b/samples/posix/eventfd/sample.yaml index 8e1e16b4eb7554..f4db0db5ae849d 100644 --- a/samples/posix/eventfd/sample.yaml +++ b/samples/posix/eventfd/sample.yaml @@ -6,7 +6,7 @@ common: tags: posix platform_exclude: m2gl025_miv integration_platforms: - - mps2_an385 + - mps2/an385 tests: sample.posix.eventfd: min_ram: 32 diff --git a/samples/sensor/accel_polling/sample.yaml b/samples/sensor/accel_polling/sample.yaml index 2b51c2f0e8abd7..3dac2474dcf6fd 100644 --- a/samples/sensor/accel_polling/sample.yaml +++ b/samples/sensor/accel_polling/sample.yaml @@ -12,16 +12,16 @@ tests: \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$" integration_platforms: - cc1352r_sensortag # adxl362 - - blueclover_plt_demo_v2_nrf52832 # bmi270 + - blueclover_plt_demo_v2/nrf52832 # bmi270 - frdm_kl25z # mma8451q - lpcxpresso55s28 # mma8652fc - bbc_microbit # mmc8653fc - frdm_k64f # fxos8700 - - sparkfun_thing_plus_nrf9160 # lis2dh - - thingy52_nrf52832 # lis2dh12 + - sparkfun_thing_plus/nrf9160 # lis2dh + - thingy52/nrf52832 # lis2dh12 - stm32f411e_disco # lsm303agr_accel - stm32f3_disco # lsm303dlhc_accel - - bl5340_dvk_cpuapp # lis3dh + - bl5340_dvk/nrf5340/cpuapp # lis3dh - b_l4s5i_iot01a # lsm6dsl - sensortile_box # lis2dw12, lsm6dso, iisdhhc - - thingy53_nrf5340_cpuapp # adxl362, bmi270 + - thingy53/nrf5340/cpuapp # adxl362, bmi270 diff --git a/samples/sensor/adt7420/README.rst b/samples/sensor/adt7420/README.rst index f1620ef0b131bb..762195bdcef2b1 100644 --- a/samples/sensor/adt7420/README.rst +++ b/samples/sensor/adt7420/README.rst @@ -41,7 +41,7 @@ In this example below the :ref:`nrf52dk_nrf52832` board is used. .. zephyr-app-commands:: :zephyr-app: samples/sensor/adt7420 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/bme680/README.rst b/samples/sensor/bme680/README.rst index c070cf64f4cce8..b02cf4fe4978f4 100644 --- a/samples/sensor/bme680/README.rst +++ b/samples/sensor/bme680/README.rst @@ -35,7 +35,7 @@ In this example below the :ref:`nrf52840dk_nrf52840` board is used. .. zephyr-app-commands:: :zephyr-app: samples/sensor/bme680 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash Sample Output diff --git a/samples/sensor/bme680/sample.yaml b/samples/sensor/bme680/sample.yaml index b862d26d80b38b..4ef00482d721f4 100644 --- a/samples/sensor/bme680/sample.yaml +++ b/samples/sensor/bme680/sample.yaml @@ -7,7 +7,7 @@ tests: - samples - sensor integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 platform_allow: - - nrf52840dk_nrf52840 - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - adafruit_feather/nrf52840 diff --git a/samples/sensor/bmi270/README.rst b/samples/sensor/bmi270/README.rst index 056c306dcda02e..d638549258d2ab 100644 --- a/samples/sensor/bmi270/README.rst +++ b/samples/sensor/bmi270/README.rst @@ -34,7 +34,7 @@ In this example below the :ref:`nrf52840dk_nrf52840` board is used. .. zephyr-app-commands:: :zephyr-app: samples/sensor/bmi270 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash Sample Output diff --git a/samples/sensor/bq274xx/README.rst b/samples/sensor/bq274xx/README.rst index 53e8dc482b76e3..82ee54b01e8bd1 100644 --- a/samples/sensor/bq274xx/README.rst +++ b/samples/sensor/bq274xx/README.rst @@ -25,7 +25,7 @@ from BQ274XX sensor and prints this information to the UART console. Requirements ************ -- nrf9160_innblue22 board with BQ274XX sensor `BQ274XX Sensor`_ +- innblue22/nrf9160 board with BQ274XX sensor `BQ274XX Sensor`_ Building and Running ******************** @@ -34,7 +34,7 @@ Build this sample using the following commands: .. zephyr-app-commands:: :zephyr-app: samples/sensor/bq274xx - :board: nrf9160_innblue22 + :board: innblue22/nrf9160 :goals: build flash References diff --git a/samples/sensor/bq274xx/sample.yaml b/samples/sensor/bq274xx/sample.yaml index 1912a288b1951b..8b3020a25362bf 100644 --- a/samples/sensor/bq274xx/sample.yaml +++ b/samples/sensor/bq274xx/sample.yaml @@ -4,16 +4,16 @@ sample: tests: sample.sensor.bq274xx: harness: sensor - platform_allow: nrf9160_innblue22 + platform_allow: innblue22/nrf9160 integration_platforms: - - nrf9160_innblue22 + - innblue22/nrf9160 tags: sensors depends_on: i2c sample.sensor.bq274xx_without_int_gpios: harness: sensor - platform_allow: nrf9160_innblue22 + platform_allow: innblue22/nrf9160 integration_platforms: - - nrf9160_innblue22 + - innblue22/nrf9160 tags: sensors depends_on: i2c extra_configs: diff --git a/samples/sensor/ccs811/README.rst b/samples/sensor/ccs811/README.rst index 771c50e4eae99a..38258db5c64afa 100644 --- a/samples/sensor/ccs811/README.rst +++ b/samples/sensor/ccs811/README.rst @@ -17,12 +17,12 @@ human presence. Building and Running ******************** -Building and Running on thingy52_nrf52832 +Building and Running on thingy52/nrf52832 ========================================= .. zephyr-app-commands:: :zephyr-app: samples/sensor/ccs811 - :board: thingy52_nrf52832 + :board: thingy52/nrf52832 :goals: build flash :compact: @@ -32,7 +32,7 @@ Sample Output The sample output below is from a `Nordic Thingy:52 `_ -(thingy52_nrf52832) that includes this sensor (and others). +(thingy52/nrf52832) that includes this sensor (and others). After a soft reset, there is a 5-second startup period where readings are unstable, and then we can see steady reported measurements of about 400 ppm eC02 and 0 ppb eTVOC. diff --git a/samples/sensor/ccs811/sample.yaml b/samples/sensor/ccs811/sample.yaml index 44540e5aeb69ff..838eb82b51438a 100644 --- a/samples/sensor/ccs811/sample.yaml +++ b/samples/sensor/ccs811/sample.yaml @@ -12,7 +12,7 @@ tests: harness: sensor tags: sensors platform_allow: - - thingy52_nrf52832 + - thingy52/nrf52832 - efr32mg_sltb004a integration_platforms: - efr32mg_sltb004a diff --git a/samples/sensor/dht/README.rst b/samples/sensor/dht/README.rst index 20fc3276215c82..d99a7278e9ca53 100644 --- a/samples/sensor/dht/README.rst +++ b/samples/sensor/dht/README.rst @@ -24,7 +24,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/dht - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/dht/sample.yaml b/samples/sensor/dht/sample.yaml index ad74cb83d9cc75..bf73aeedd11580 100644 --- a/samples/sensor/dht/sample.yaml +++ b/samples/sensor/dht/sample.yaml @@ -11,7 +11,7 @@ sample: tests: sample.sensor.dht: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: sensors diff --git a/samples/sensor/die_temp_polling/boards/nrf51dk_nrf51422.overlay b/samples/sensor/die_temp_polling/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from samples/sensor/die_temp_polling/boards/nrf51dk_nrf51422.overlay rename to samples/sensor/die_temp_polling/boards/nrf51dk_nrf51822.overlay diff --git a/samples/sensor/dps310/README.rst b/samples/sensor/dps310/README.rst index 57ad36d29820d9..440a43896b6516 100644 --- a/samples/sensor/dps310/README.rst +++ b/samples/sensor/dps310/README.rst @@ -18,12 +18,12 @@ This sample application uses an DPS310 sensor connected to a board via I2C. Connect the sensor pins according to the connection diagram given in the `dps310 datasheet`_ at page 18 figure 7. -Build and flash this sample (for example, for the nrf52840dk_nrf52840 board) +Build and flash this sample (for example, for the nrf52840dk/nrf52840 board) using these commands: .. zephyr-app-commands:: :zephyr-app: samples/sensor/dps310 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: flash :compact: diff --git a/samples/sensor/ds18b20/sample.yaml b/samples/sensor/ds18b20/sample.yaml index fb8001758a1bb5..4969db03164472 100644 --- a/samples/sensor/ds18b20/sample.yaml +++ b/samples/sensor/ds18b20/sample.yaml @@ -7,10 +7,10 @@ tests: sample.sensor.ds18b20.w1_serial: platform_allow: - nucleo_g0b1re - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - nucleo_g0b1re - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness_config: type: one_line regex: diff --git a/samples/sensor/fdc2x1x/README.rst b/samples/sensor/fdc2x1x/README.rst index 5ab5ea6ca1fbcd..626310e6b3f243 100644 --- a/samples/sensor/fdc2x1x/README.rst +++ b/samples/sensor/fdc2x1x/README.rst @@ -50,7 +50,7 @@ you can use as a reference for other platforms. .. zephyr-app-commands:: :zephyr-app: samples/sensor/fdc2x1x - :board: nrf9160dk_nrf9160 + :board: nrf9160dk/nrf9160 :goals: build flash :compact: diff --git a/samples/sensor/fdc2x1x/sample.yaml b/samples/sensor/fdc2x1x/sample.yaml index 1cf1e2d8441fa6..e8e61a66466022 100644 --- a/samples/sensor/fdc2x1x/sample.yaml +++ b/samples/sensor/fdc2x1x/sample.yaml @@ -5,6 +5,6 @@ tests: sample.sensor.fdc2x1x: harness: sensor tags: sensors - platform_allow: nrf9160dk_nrf9160 + platform_allow: nrf9160dk/nrf9160 integration_platforms: - - nrf9160dk_nrf9160 + - nrf9160dk/nrf9160 diff --git a/samples/sensor/fxas21002/README.rst b/samples/sensor/fxas21002/README.rst index 014a27f12f9abd..3281e29b8309a6 100644 --- a/samples/sensor/fxas21002/README.rst +++ b/samples/sensor/fxas21002/README.rst @@ -13,12 +13,12 @@ Building and Running ******************** This project outputs sensor data to the console. It requires an fxas21002 -sensor, which is present on the :ref:`hexiwear_k64` board. It does not work on +sensor, which is present on the :ref:`hexiwear` board. It does not work on QEMU. .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxas21002 - :board: hexiwear_k64 + :board: hexiwear/mk64f12 :goals: build :compact: diff --git a/samples/sensor/fxas21002/sample.yaml b/samples/sensor/fxas21002/sample.yaml index 8f598b8f7bcc09..c43306c3d0be7f 100644 --- a/samples/sensor/fxas21002/sample.yaml +++ b/samples/sensor/fxas21002/sample.yaml @@ -4,6 +4,6 @@ tests: sample.sensor.fxas21002: harness: sensor tags: sensors - platform_allow: hexiwear_k64 + platform_allow: hexiwear/mk64f12 integration_platforms: - - hexiwear_k64 + - hexiwear/mk64f12 diff --git a/samples/sensor/fxos8700/README.rst b/samples/sensor/fxos8700/README.rst index c6aec0921fc84c..0c0fa8af66a1ea 100644 --- a/samples/sensor/fxos8700/README.rst +++ b/samples/sensor/fxos8700/README.rst @@ -15,7 +15,7 @@ Building and Running This project outputs sensor data to the console. FXOS8700 sensor is present on the :ref:`frdm_k64f`, :ref:`frdm_k22f`, -:ref:`frdm_kw41z`, :ref:`hexiwear_k64`, and :ref:`twr_ke18f` boards. +:ref:`frdm_kw41z`, :ref:`hexiwear`, and :ref:`twr_ke18f` boards. Accelerometer only devices are present on the :ref:`frdm_kl25z`, :ref:`bbc_microbit`, and :ref:`reel_board` boards. It does not work on QEMU. @@ -117,7 +117,7 @@ Sample can be built and executed for the MIMXRT685-EVK as follows: .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxos8700 - :board: mimxrt685_evk_cm33 + :board: mimxrt685_evk :goals: build flash :compact: @@ -129,7 +129,7 @@ Sample can be built and executed for the MIMXRT595-EVK as follows: .. zephyr-app-commands:: :zephyr-app: samples/sensor/fxos8700 - :board: mimxrt595_evk_cm33 + :board: mimxrt595_evk/mimxrt595s/cm33 :goals: build flash :compact: diff --git a/samples/sensor/fxos8700/boards/mimxrt1170_evk_cm7.conf b/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm4.conf similarity index 100% rename from samples/sensor/fxos8700/boards/mimxrt1170_evk_cm7.conf rename to samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm4.conf diff --git a/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm7.conf b/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm7.conf new file mode 100644 index 00000000000000..16c619082c684c --- /dev/null +++ b/samples/sensor/fxos8700/boards/mimxrt1160_evk_mimxrt1166_cm7.conf @@ -0,0 +1,2 @@ +CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n +CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000000..16c619082c684c --- /dev/null +++ b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,2 @@ +CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n +CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000000..16c619082c684c --- /dev/null +++ b/samples/sensor/fxos8700/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,2 @@ +CONFIG_FXOS8700_TRIGGER_OWN_THREAD=n +CONFIG_FXOS8700_TRIGGER_NONE=y diff --git a/samples/sensor/fxos8700/sample.yaml b/samples/sensor/fxos8700/sample.yaml index d0e9e27d4dbe7f..29215833f63bfa 100644 --- a/samples/sensor/fxos8700/sample.yaml +++ b/samples/sensor/fxos8700/sample.yaml @@ -10,16 +10,16 @@ tests: sample.sensor.fxos8700.hybrid: platform_allow: - frdm_k64f - - hexiwear_k64 - - warp7_m4 + - hexiwear/mk64f12 + - warp7/mcimx7d/m4 - frdm_kw41z - - rv32m1_vega_ri5cy + - rv32m1_vega/openisa_rv32m1/ri5cy - twr_ke18f - lpcxpresso55s16 - - mimxrt685_evk_cm33 + - mimxrt685_evk - frdm_k22f - mimxrt1024_evk - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 integration_platforms: - frdm_k64f extra_configs: @@ -32,10 +32,10 @@ tests: platform_allow: - frdm_kl25z - bbc_microbit - - lpcxpresso55s69_cpu0 + - lpcxpresso55s69/lpc55s69/cpu0 - reel_board - - mimxrt685_evk_cm33 - - mimxrt595_evk_cm33 + - mimxrt685_evk + - mimxrt595_evk/mimxrt595s/cm33 integration_platforms: - bbc_microbit extra_args: CONF_FILE=prj_accel.conf diff --git a/samples/sensor/grove_light/sample.yaml b/samples/sensor/grove_light/sample.yaml index 3eb1083a883f46..24e020f7fb505a 100644 --- a/samples/sensor/grove_light/sample.yaml +++ b/samples/sensor/grove_light/sample.yaml @@ -9,8 +9,8 @@ tests: - sensor - grove - light - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 harness: grove depends_on: adc diff --git a/samples/sensor/grove_temperature/sample.yaml b/samples/sensor/grove_temperature/sample.yaml index 83035b9b9fb613..4669a8de56b0a2 100644 --- a/samples/sensor/grove_temperature/sample.yaml +++ b/samples/sensor/grove_temperature/sample.yaml @@ -10,8 +10,8 @@ tests: - sensor - grove - temperature - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 harness: grove depends_on: adc diff --git a/samples/sensor/grow_r502a/README.rst b/samples/sensor/grow_r502a/README.rst index 0b71517bc38e43..032be38bfff67e 100644 --- a/samples/sensor/grow_r502a/README.rst +++ b/samples/sensor/grow_r502a/README.rst @@ -42,7 +42,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/grow_r502a - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash Sample Output diff --git a/samples/sensor/icm42605/README.rst b/samples/sensor/icm42605/README.rst index a438f0dfbf544e..6723a15d0a2817 100644 --- a/samples/sensor/icm42605/README.rst +++ b/samples/sensor/icm42605/README.rst @@ -26,7 +26,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/icm42605 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/icm42605/sample.yaml b/samples/sensor/icm42605/sample.yaml index 763a914e6fdcb1..43e49982c4550e 100644 --- a/samples/sensor/icm42605/sample.yaml +++ b/samples/sensor/icm42605/sample.yaml @@ -9,7 +9,7 @@ sample: tests: sample.sensor.icm42605: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 tags: sensors diff --git a/samples/sensor/isl29035/README.rst b/samples/sensor/isl29035/README.rst index 10acaef639653b..675bc1f143ca10 100644 --- a/samples/sensor/isl29035/README.rst +++ b/samples/sensor/isl29035/README.rst @@ -27,7 +27,7 @@ Building and Running .. zephyr-app-commands:: :zephyr-app: samples/sensor/isl29035 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build :compact: diff --git a/samples/sensor/isl29035/sample.yaml b/samples/sensor/isl29035/sample.yaml index 8ef21237dbaa9c..086e4eec8cf302 100644 --- a/samples/sensor/isl29035/sample.yaml +++ b/samples/sensor/isl29035/sample.yaml @@ -4,6 +4,6 @@ tests: sample.sensor.isl29035: tags: sensors depends_on: i2c - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/samples/sensor/lps22hh/README.rst b/samples/sensor/lps22hh/README.rst index ad0e780a076ed5..dc1ca12cd79303 100644 --- a/samples/sensor/lps22hh/README.rst +++ b/samples/sensor/lps22hh/README.rst @@ -27,7 +27,7 @@ sensor, which is present on the X-NUCLEO-IKS01A3 shield. .. zephyr-app-commands:: :zephyr-app: samples/sensor/lps22hh - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :shield: x_nucleo_iks01a3 :goals: build :compact: diff --git a/samples/sensor/lps22hh_i3c/README.rst b/samples/sensor/lps22hh_i3c/README.rst index 1f4ff486241496..5e8b1d4dff573b 100644 --- a/samples/sensor/lps22hh_i3c/README.rst +++ b/samples/sensor/lps22hh_i3c/README.rst @@ -37,20 +37,20 @@ sensor (for example, the one on evaluation board STEVALMKI192-V1). resulting in the sample not being able to communicate with the sensor. -Building on mimxrt685_evk_cm33 board +Building on mimxrt685_evk board ==================================== .. zephyr-app-commands:: :zephyr-app: samples/sensor/lps22hh_i3c :host-os: unix - :board: mimxrt685_evk_cm33 + :board: mimxrt685_evk :goals: build :compact: Board Preparations ================== -mimxrt685_evk_cm33 +mimxrt685_evk ------------------ On the board :ref:`mimxrt685_evk`, the I3C pins are exposed on the J18 diff --git a/samples/sensor/lps22hh_i3c/boards/mimxrt685_evk_cm33.overlay b/samples/sensor/lps22hh_i3c/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/sensor/lps22hh_i3c/boards/mimxrt685_evk_cm33.overlay rename to samples/sensor/lps22hh_i3c/boards/mimxrt685_evk.overlay diff --git a/samples/sensor/lsm6dsl/README.rst b/samples/sensor/lsm6dsl/README.rst index e75cbe773db4c5..0ca5303bd2b42d 100644 --- a/samples/sensor/lsm6dsl/README.rst +++ b/samples/sensor/lsm6dsl/README.rst @@ -48,13 +48,13 @@ Building on disco_l475_iot1 board :goals: build :compact: -Building on nrf52840dk_nrf52840 board with x-nucleo-iks01a2 shield +Building on nrf52840dk/nrf52840 board with x-nucleo-iks01a2 shield ================================================================== .. zephyr-app-commands:: :zephyr-app: samples/sensor/lsm6dsl :host-os: unix - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: x_nucleo_iks01a2 :goals: build :compact: diff --git a/samples/sensor/lsm6dso_i2c_on_i3c/README.rst b/samples/sensor/lsm6dso_i2c_on_i3c/README.rst index a4e42306d581fb..872d244364baf5 100644 --- a/samples/sensor/lsm6dso_i2c_on_i3c/README.rst +++ b/samples/sensor/lsm6dso_i2c_on_i3c/README.rst @@ -28,20 +28,20 @@ Building and Running This project outputs sensor data to the console. It requires an LSM6DSO sensor (for example, the one on evaluation board STEVAL-MKI196V1). -Building on mimxrt685_evk_cm33 board +Building on mimxrt685_evk board ==================================== .. zephyr-app-commands:: :zephyr-app: samples/sensor/lsm6dso_i2c_on_i3c :host-os: unix - :board: mimxrt685_evk_cm33 + :board: mimxrt685_evk :goals: build :compact: Board Preparations ================== -mimxrt685_evk_cm33 +mimxrt685_evk ------------------ On the board :ref:`mimxrt685_evk`, the I3C pins are exposed on the J18 diff --git a/samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk_cm33.overlay b/samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk.overlay similarity index 100% rename from samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk_cm33.overlay rename to samples/sensor/lsm6dso_i2c_on_i3c/boards/mimxrt685_evk.overlay diff --git a/samples/sensor/magn_polling/sample.yaml b/samples/sensor/magn_polling/sample.yaml index 97aa17419f3158..8c44c0c74ddae4 100644 --- a/samples/sensor/magn_polling/sample.yaml +++ b/samples/sensor/magn_polling/sample.yaml @@ -7,7 +7,7 @@ tests: filter: dt_alias_exists("magn0") integration_platforms: - frdm_k64f # fxos8700 - - thingy53_nrf5340_cpuapp # bmm150 + - thingy53/nrf5340/cpuapp # bmm150 - sensortile_box # lis2mdl - stm32f411e_disco # lsm303agr_magn - stm32f3_disco # lsm303dlhc_magn diff --git a/samples/sensor/max17262/README.rst b/samples/sensor/max17262/README.rst index d54039945276cb..b73b411903f91a 100644 --- a/samples/sensor/max17262/README.rst +++ b/samples/sensor/max17262/README.rst @@ -32,7 +32,7 @@ Connect the sensor pins according to the connection diagram given in the .. zephyr-app-commands:: :zephyr-app: samples/sensor/max17262 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/sensor/max17262/sample.yaml b/samples/sensor/max17262/sample.yaml index ac403802235125..d87c4a5a896c2a 100644 --- a/samples/sensor/max17262/sample.yaml +++ b/samples/sensor/max17262/sample.yaml @@ -7,7 +7,7 @@ tests: depends_on: arduino_i2c harness: console tags: sensors - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness_config: type: one_line regex: diff --git a/samples/sensor/max30101/README.rst b/samples/sensor/max30101/README.rst index 446231ef0a3239..3d7aa9e8be5d6f 100644 --- a/samples/sensor/max30101/README.rst +++ b/samples/sensor/max30101/README.rst @@ -12,14 +12,14 @@ rate sensor. Building and Running ******************** -This project configures the max30101 sensor on the :ref:`hexiwear_k64` board to +This project configures the max30101 sensor on the :ref:`hexiwear` board to enable the green LED and measure the reflected light with a photodiode. The raw ADC data prints to the console. Further processing (not included in this sample) is required to extract a heart rate signal from the light measurement. .. zephyr-app-commands:: :zephyr-app: samples/sensor/max30101 - :board: hexiwear_k64 + :board: hexiwear/mk64f12 :goals: build :compact: diff --git a/samples/sensor/max30101/boards/hexiwear_k64.overlay b/samples/sensor/max30101/boards/hexiwear_mk64f12.overlay similarity index 100% rename from samples/sensor/max30101/boards/hexiwear_k64.overlay rename to samples/sensor/max30101/boards/hexiwear_mk64f12.overlay diff --git a/samples/sensor/max30101/sample.yaml b/samples/sensor/max30101/sample.yaml index f1d82339432247..abe92a10d24745 100644 --- a/samples/sensor/max30101/sample.yaml +++ b/samples/sensor/max30101/sample.yaml @@ -5,7 +5,7 @@ tests: sample.sensor.max30101: harness: sensor tags: sensors - platform_allow: hexiwear_k64 + platform_allow: hexiwear/mk64f12 depends_on: i2c integration_platforms: - - hexiwear_k64 + - hexiwear/mk64f12 diff --git a/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_cm7.overlay b/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay similarity index 100% rename from samples/sensor/mcux_acmp/boards/mimxrt1170_evk_cm7.overlay rename to samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay diff --git a/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000000..b7aa1131ec7cd2 --- /dev/null +++ b/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,22 @@ +/* + * Copyright 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + acmp1_default: acmp1_default { + group0 { + pinmux = <&iomuxc_gpio_ad_01_acmp1_in2>; + drive-strength = "high"; + bias-pull-up; + slew-rate = "fast"; + }; + }; +}; + +&acmp1 { + status = "okay"; + pinctrl-0 = <&acmp1_default>; + pinctrl-names = "default"; +}; diff --git a/samples/sensor/mcux_acmp/sample.yaml b/samples/sensor/mcux_acmp/sample.yaml index 3f47cfcd1b51c2..6c4e0bb314f152 100644 --- a/samples/sensor/mcux_acmp/sample.yaml +++ b/samples/sensor/mcux_acmp/sample.yaml @@ -4,8 +4,8 @@ sample: common: platform_allow: - twr_ke18f - - mimxrt1170_evk_cm7 - - mimxrt1170_evk_cm4 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm4 integration_platforms: - twr_ke18f tags: diff --git a/samples/sensor/mcux_acmp/src/main.c b/samples/sensor/mcux_acmp/src/main.c index f6960168b8f4e6..a1475d145c0aa7 100644 --- a/samples/sensor/mcux_acmp/src/main.c +++ b/samples/sensor/mcux_acmp/src/main.c @@ -16,7 +16,7 @@ #define ACMP_POSITIVE 5 #define ACMP_NEGATIVE 5 #define ACMP_DAC_VREF 0 -#elif (defined(CONFIG_BOARD_MIMXRT1170_EVK_CM7) || defined(CONFIG_BOARD_MIMXRT1170_EVK_CM4)) +#elif defined(CONFIG_BOARD_MIMXRT1170_EVK) #define ACMP_NODE DT_NODELABEL(acmp1) #define ACMP_POSITIVE 2 #define ACMP_NEGATIVE 7 diff --git a/samples/sensor/mpu6050/README.rst b/samples/sensor/mpu6050/README.rst index 793323f73a2279..52550218808369 100644 --- a/samples/sensor/mpu6050/README.rst +++ b/samples/sensor/mpu6050/README.rst @@ -28,7 +28,7 @@ build this sample app using: .. zephyr-app-commands:: :zephyr-app: samples/sensor/mpu6050 - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash Sample Output diff --git a/samples/sensor/mpu6050/sample.yaml b/samples/sensor/mpu6050/sample.yaml index 1633dd4b64fca3..5a9ed1e2803529 100644 --- a/samples/sensor/mpu6050/sample.yaml +++ b/samples/sensor/mpu6050/sample.yaml @@ -9,7 +9,7 @@ sample: tests: sample.sensor.mpu6050: build_only: true - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 tags: sensors integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/samples/sensor/ms5837/README.rst b/samples/sensor/ms5837/README.rst index 03bf40dc188b69..dd1b0a99564940 100644 --- a/samples/sensor/ms5837/README.rst +++ b/samples/sensor/ms5837/README.rst @@ -37,7 +37,7 @@ Build this sample using the following commands: .. zephyr-app-commands:: :zephyr-app: samples/sensor/ms5837 - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/sensor/ms5837/sample.yaml b/samples/sensor/ms5837/sample.yaml index 59adc486e64688..2e3b50a9a575e6 100644 --- a/samples/sensor/ms5837/sample.yaml +++ b/samples/sensor/ms5837/sample.yaml @@ -4,7 +4,7 @@ sample: tests: sample.sensor.ms5837: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: sensors diff --git a/samples/sensor/proximity_polling/sample.yaml b/samples/sensor/proximity_polling/sample.yaml index 8a5d8bb9307131..35ef1647b22d2d 100644 --- a/samples/sensor/proximity_polling/sample.yaml +++ b/samples/sensor/proximity_polling/sample.yaml @@ -8,4 +8,4 @@ tests: - proximity filter: dt_alias_exists("prox-sensor0") integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/sensor/qdec/sample.yaml b/samples/sensor/qdec/sample.yaml index 5849f3e00c7985..cbd90ba6f3e2de 100644 --- a/samples/sensor/qdec/sample.yaml +++ b/samples/sensor/qdec/sample.yaml @@ -18,10 +18,10 @@ tests: fixture: fixture_mech_encoder sample.sensor.nrf_qdec_sensor: platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness_config: fixture: gpio_loopback diff --git a/samples/sensor/sensor_shell/boards/tdk_robokit1.conf b/samples/sensor/sensor_shell/boards/robokit1.conf similarity index 100% rename from samples/sensor/sensor_shell/boards/tdk_robokit1.conf rename to samples/sensor/sensor_shell/boards/robokit1.conf diff --git a/samples/sensor/sht3xd/sample.yaml b/samples/sensor/sht3xd/sample.yaml index 5d72975465396b..0319ba3a7e29cb 100644 --- a/samples/sensor/sht3xd/sample.yaml +++ b/samples/sensor/sht3xd/sample.yaml @@ -11,10 +11,10 @@ common: - efr32mg_sltb004a - frdm_k64f - nrf51_ble400 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_l476rg integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: sensors build_only: true tests: diff --git a/samples/sensor/thermometer/README.rst b/samples/sensor/thermometer/README.rst index e37ad7b016b0e5..255425fc22e064 100644 --- a/samples/sensor/thermometer/README.rst +++ b/samples/sensor/thermometer/README.rst @@ -18,17 +18,17 @@ VOUT pin connected to the ADC input pin. .. _`MCP970X Sensor`: http://ww1.microchip.com/downloads/en/devicedoc/20001942g.pdf -An overlay is provided for the nrf52840dk_nrf52840 board with the +An overlay is provided for the nrf52840dk/nrf52840 board with the sensor connected to pin AIN7. Building and Running ******************** -To build for the nrf52840dk_nrf52840 board use: +To build for the nrf52840dk/nrf52840 board use: .. zephyr-app-commands:: :zephyr-app: samples/sensor/thermometer - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: @@ -36,7 +36,7 @@ To build for the nrf52840dk_nrf52840 board use: To build for other boards and ambient temperature sensors, enable the sensor node that supports ``SENSOR_CHAN_AMBIENT_TEMP`` and use an overlay to create an alias named ``ambient-temp0`` to link to the node. See the overlay used for the -``nrf52840dk_nrf52840`` board within this sample: +``nrf52840dk/nrf52840`` board within this sample: ``boards/nrf52840dk_nrf52840.overlay`` diff --git a/samples/sensor/thermometer/sample.yaml b/samples/sensor/thermometer/sample.yaml index 64a4de64380cee..8acb9f72576b13 100644 --- a/samples/sensor/thermometer/sample.yaml +++ b/samples/sensor/thermometer/sample.yaml @@ -5,5 +5,5 @@ tests: tags: sensors harness: sensor integration_platforms: - - nrf52840dk_nrf52840 - platform_allow: nrf52840dk_nrf52840 frdm_k22f + - nrf52840dk/nrf52840 + platform_allow: nrf52840dk/nrf52840 frdm_k22f diff --git a/samples/shields/npm1300_ek/doc/index.rst b/samples/shields/npm1300_ek/doc/index.rst index f32f301104a002..4761ba6f8a270b 100644 --- a/samples/shields/npm1300_ek/doc/index.rst +++ b/samples/shields/npm1300_ek/doc/index.rst @@ -28,7 +28,7 @@ building for the nRF52 DK, the following command can be used: .. zephyr-app-commands:: :zephyr-app: samples/shields/npm1300_ek - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build :compact: diff --git a/samples/shields/npm1300_ek/sample.yaml b/samples/shields/npm1300_ek/sample.yaml index 20e16d50238725..de89e80d79ea44 100644 --- a/samples/shields/npm1300_ek/sample.yaml +++ b/samples/shields/npm1300_ek/sample.yaml @@ -5,7 +5,7 @@ sample: name: nPM1300 EK tests: sample.shields.npm1300_ek: - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 harness: shield tags: shield extra_args: SHIELD=npm1300_ek diff --git a/samples/shields/npm6001_ek/doc/index.rst b/samples/shields/npm6001_ek/doc/index.rst index cb3fab7016df09..13e4f64ce2988e 100644 --- a/samples/shields/npm6001_ek/doc/index.rst +++ b/samples/shields/npm6001_ek/doc/index.rst @@ -34,7 +34,7 @@ building for the nRF52840 DK, the following command can be used: .. zephyr-app-commands:: :zephyr-app: samples/shields/npm6001_ek - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/shields/x_nucleo_iks01a2/standard/README.rst b/samples/shields/x_nucleo_iks01a2/standard/README.rst index ccfedc1cfcb23d..fb0b8af84a841f 100644 --- a/samples/shields/x_nucleo_iks01a2/standard/README.rst +++ b/samples/shields/x_nucleo_iks01a2/standard/README.rst @@ -22,8 +22,8 @@ stacked on a board with an Arduino connector. The board's I2C must be configured for the I2C Arduino connector in the devicetree. See for example the :ref:`nucleo_f401re_board` board source code: -- :zephyr_file:`boards/arm/nucleo_f401re/nucleo_f401re.dts` -- :zephyr_file:`boards/arm/nucleo_f401re/arduino_r3_connector.dtsi` +- :zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re.dts` +- :zephyr_file:`boards/st/nucleo_f401re/arduino_r3_connector.dtsi` Please note that this sample can't be used with boards already supporting one of the sensors available on the shield (such as disco_l475_iot1) as zephyr diff --git a/samples/shields/x_nucleo_iks02a1/microphone/README.rst b/samples/shields/x_nucleo_iks02a1/microphone/README.rst index adc6831c81d772..ee9a222c79f5a0 100644 --- a/samples/shields/x_nucleo_iks02a1/microphone/README.rst +++ b/samples/shields/x_nucleo_iks02a1/microphone/README.rst @@ -52,11 +52,11 @@ To build the sample you can use following command: building the sample is the I2S output clock frequency configuration. For example, for nucleo_f411re board, we have the following file that configures the I2SPLL and have a dependency on HSE/HSI: - :zephyr_file:`boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.defconfig` + :zephyr_file:`boards/shields/x_nucleo_iks02a1/boards/nucleo_f411re.overlay` The user is invited to to verify which osci is configured on the used host board defconfig file and calculate the final I2SClk frequency, e.g. - :zephyr_file:`boards/arm/nucleo_f411re/nucleo_f411re.dts` + :zephyr_file:`boards/st/nucleo_f411re/nucleo_f411re.dts` Sample Output diff --git a/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst b/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst index e8b17efc65c617..699c63e92ebf0c 100644 --- a/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst +++ b/samples/shields/x_nucleo_iks02a1/sensorhub/README.rst @@ -31,8 +31,8 @@ configured for the I2C Arduino connector (both for pin muxing and devicetree). See for example the :ref:`nucleo_f401re_board` board source code: -- :zephyr_file:`boards/arm/nucleo_f401re/nucleo_f401re.dts` -- :zephyr_file:`boards/arm/nucleo_f401re/pinmux.c` +- :zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re.dts` +- :zephyr_file:`boards/st/nucleo_f401re/pinmux.c` Please note that this sample can't be used with boards already supporting one of the sensors available on the shield (such as disco_l475_iot1) diff --git a/samples/subsys/console/echo/sample.yaml b/samples/subsys/console/echo/sample.yaml index 9e94abe66560cd..e1fa3f8ac4676b 100644 --- a/samples/subsys/console/echo/sample.yaml +++ b/samples/subsys/console/echo/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.console.echo: integration_platforms: - - mps2_an385 + - mps2/an385 filter: CONFIG_UART_CONSOLE and CONFIG_SERIAL_SUPPORT_INTERRUPT tags: console harness: keyboard diff --git a/samples/subsys/console/getchar/sample.yaml b/samples/subsys/console/getchar/sample.yaml index d7117eea6ab630..4a4ffcb59787a9 100644 --- a/samples/subsys/console/getchar/sample.yaml +++ b/samples/subsys/console/getchar/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.console.getchar: integration_platforms: - - mps2_an385 + - mps2/an385 filter: CONFIG_UART_CONSOLE and CONFIG_SERIAL_SUPPORT_INTERRUPT tags: console harness: keyboard diff --git a/samples/subsys/console/getline/sample.yaml b/samples/subsys/console/getline/sample.yaml index 820d61900798d9..9d7e6b72325065 100644 --- a/samples/subsys/console/getline/sample.yaml +++ b/samples/subsys/console/getline/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.console.getline: integration_platforms: - - mps2_an385 + - mps2/an385 filter: CONFIG_UART_CONSOLE and CONFIG_SERIAL_SUPPORT_INTERRUPT tags: console harness: keyboard diff --git a/samples/subsys/display/cfb/boards/reel_board_v2.conf b/samples/subsys/display/cfb/boards/reel_board_v2.conf deleted file mode 100644 index 5616bfc48d779a..00000000000000 --- a/samples/subsys/display/cfb/boards/reel_board_v2.conf +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SPI=y diff --git a/samples/subsys/display/lvgl/README.rst b/samples/subsys/display/lvgl/README.rst index be5eecd9db1960..34b58f4c866ea8 100644 --- a/samples/subsys/display/lvgl/README.rst +++ b/samples/subsys/display/lvgl/README.rst @@ -68,7 +68,7 @@ Example building for :ref:`nrf52840dk_nrf52840`: .. zephyr-app-commands:: :zephyr-app: samples/subsys/display/lvgl - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: adafruit_2_8_tft_touch_v2 :goals: build flash diff --git a/samples/subsys/display/lvgl/boards/mimxrt1170_evk_cm7.conf b/samples/subsys/display/lvgl/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from samples/subsys/display/lvgl/boards/mimxrt1170_evk_cm7.conf rename to samples/subsys/display/lvgl/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/samples/subsys/display/lvgl/sample.yaml b/samples/subsys/display/lvgl/sample.yaml index 3c6e56cdfe124b..7d8eb7a3b1bce6 100644 --- a/samples/subsys/display/lvgl/sample.yaml +++ b/samples/subsys/display/lvgl/sample.yaml @@ -36,12 +36,12 @@ tests: - lvgl extra_args: SHIELD="rk055hdmipi4m" platform_allow: - - mimxrt1170_evk_cm7 - - mimxrt595_evk_cm33 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt595_evk/mimxrt595s/cm33 integration_platforms: - - mimxrt1170_evk_cm7 + - mimxrt1170_evk/mimxrt1176/cm7 sample.subsys.display.lvgl.st_b_lcd40_dsi1_mb1166: - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: SHIELD=st_b_lcd40_dsi1_mb1166 harness: console harness_config: diff --git a/samples/subsys/fs/format/README.rst b/samples/subsys/fs/format/README.rst index 1801af343060f1..fdcc575ec00bec 100644 --- a/samples/subsys/fs/format/README.rst +++ b/samples/subsys/fs/format/README.rst @@ -18,7 +18,7 @@ Building and running To run this sample, build it for the desired board and scenario and flash it. -The Flash scenario is supported on the nrf52dk_nrf52832 board. +The Flash scenario is supported on the nrf52dk/nrf52832 board. The RAM disk scenario is supported on the mimxrt1064_evk board. To build the RAM disk sample, the configuration `prj_ram.conf` needs to be used by setting `CONF_FILE=prj_ram.conf`. @@ -26,7 +26,7 @@ The Flash sample for the nrf 52DK board can be build as follow: .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/format - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash :compact: diff --git a/samples/subsys/fs/format/sample.yaml b/samples/subsys/fs/format/sample.yaml index aafe86f7989132..897c95c348eb80 100644 --- a/samples/subsys/fs/format/sample.yaml +++ b/samples/subsys/fs/format/sample.yaml @@ -5,7 +5,7 @@ tests: platform_allow: - native_posix - native_sim - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 build_only: true tags: filesystem sample.filesystem.format.fat_fs: diff --git a/samples/subsys/fs/fs_sample/README.rst b/samples/subsys/fs/fs_sample/README.rst index e53068b92c7f04..f51d1db9c2c518 100644 --- a/samples/subsys/fs/fs_sample/README.rst +++ b/samples/subsys/fs/fs_sample/README.rst @@ -28,20 +28,20 @@ For the FAT FS to work with internal flash, the device needs to support erase pages of size <= 4096 bytes and have at least 64kiB of flash available for FAT FS partition alone. Currently the following boards are supported: -``nrf52840dk_nrf52840`` +``nrf52840dk/nrf52840`` Requirements for setting up FAT FS on external flash **************************************************** This type of configuration requires external flash device to be available on DK board. Currently following boards support the configuration: -``nrf52840dk_nrf52840`` by ``nrf52840dk_nrf52840_qspi`` configuration. +``nrf52840dk/nrf52840`` by ``nrf52840dk_nrf52840_qspi`` configuration. Building and Running FAT samples ******************************** Boards with default configurations, for example ``arduino_mkrzero`` or -``nrf52840dk_nrf52840`` using internal flash can be build using command: +``nrf52840dk/nrf52840`` using internal flash can be build using command: .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/fs_sample @@ -52,12 +52,12 @@ Boards with default configurations, for example ``arduino_mkrzero`` or Where used example board ``nrf52840_blip`` should be replaced with desired board. In case when some more specific configuration is to be used for a given board, -for example ``nrf52840dk_nrf52840`` with MX25 device over QSPI, configuration +for example ``nrf52840dk/nrf52840`` with MX25 device over QSPI, configuration and DTS overlays need to be also selected. The command would look like this: .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/fs_sample - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DEXTRA_CONF_FILE=nrf52840dk_nrf52840_qspi.conf -DDTC_OVERLAY_FILE=nrf52840dk_nrf52840_qspi.overlay :goals: build :compact: @@ -73,7 +73,7 @@ sample lists them out on the debug serial output. Building and Running EXT2 samples ********************************* -Ext2 sample can be build for ``hifive_unmatched`` or ``bl5340_dvk_cpuapp``. Because +Ext2 sample can be build for ``hifive_unmatched`` or ``bl5340_dvk/nrf5340/cpuapp``. Because FAT is default file system for this sample, additional flags must be passed to build the sample. diff --git a/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.conf b/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.conf similarity index 100% rename from samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.conf rename to samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.conf diff --git a/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.overlay b/samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from samples/subsys/fs/fs_sample/boards/stm32h747i_disco_m7.overlay rename to samples/subsys/fs/fs_sample/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/samples/subsys/fs/fs_sample/sample.yaml b/samples/subsys/fs/fs_sample/sample.yaml index 58c0cf623619dd..22d47ca3b261fb 100644 --- a/samples/subsys/fs/fs_sample/sample.yaml +++ b/samples/subsys/fs/fs_sample/sample.yaml @@ -30,10 +30,10 @@ tests: fixture: fixture_shield_adafruit_2_8_tft_touch_v2 sample.filesystem.fat_fs.nrf52840dk_nrf52840: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 sample.filesystem.fat_fs.nrf52840dk_nrf52840.qspi: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_qspi.overlay @@ -46,9 +46,7 @@ tests: simulation_exclude: - renode extra_args: CONF_FILE="prj_ext.conf" - platform_allow: hifive_unmatched bl5340_dvk_cpuapp + platform_allow: hifive_unmatched bl5340_dvk/nrf5340/cpuapp sample.filesystem.fat_fs.stm32h747i_disco_m7_sdmmc: build_only: true - platform_allow: stm32h747i_disco_m7 - extra_args: - - OVERLAY_CONFIG=boards/stm32h747i_disco_m7.conf + platform_allow: stm32h747i_disco/stm32h747xx/m7 diff --git a/samples/subsys/fs/littlefs/README.rst b/samples/subsys/fs/littlefs/README.rst index 40911001ddab37..69be12cfefeca7 100644 --- a/samples/subsys/fs/littlefs/README.rst +++ b/samples/subsys/fs/littlefs/README.rst @@ -112,7 +112,7 @@ On this device the file system will be placed in the SOC flash. .. zephyr-app-commands:: :zephyr-app: samples/subsys/fs/littlefs - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build :compact: diff --git a/samples/subsys/fs/littlefs/boards/lpcxpresso55s69_cpu0.conf b/samples/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/subsys/fs/littlefs/boards/lpcxpresso55s69_cpu0.conf rename to samples/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay b/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay index 3b06e8e97a3677..8cb06841754b25 100644 --- a/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay +++ b/samples/subsys/fs/littlefs/boards/nrf52840dk_nrf52840_spi.overlay @@ -10,7 +10,7 @@ status = "disabled"; }; -/* The mx25, on nrf52840dk_nrf52840, uses pins for spi0, spi1, spi2 and spi3 +/* The mx25, on nrf52840dk/nrf52840, uses pins for spi0, spi1, spi2 and spi3 * to provide quad-spi feature. In individual specifications each of the spi * notes define own clock source (SCK), but spi2 shares the same clock source * as qspi configuration, which is pin (0,19). That is why spi2 is used here diff --git a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.conf b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf similarity index 100% rename from samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.conf rename to samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.conf diff --git a/samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.overlay b/samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from samples/subsys/fs/littlefs/boards/stm32h747i_disco_m7.overlay rename to samples/subsys/fs/littlefs/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/samples/subsys/fs/littlefs/sample.yaml b/samples/subsys/fs/littlefs/sample.yaml index cee428271733cd..6ba8e33e5a775f 100644 --- a/samples/subsys/fs/littlefs/sample.yaml +++ b/samples/subsys/fs/littlefs/sample.yaml @@ -8,35 +8,34 @@ tests: sample.filesystem.littlefs: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - particle_xenon - disco_l475_iot1 - - mimxrt685_evk_cm33 + - mimxrt685_evk - mimxrt1060_evk - mimxrt1064_evk - qemu_x86 - native_posix - native_sim - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.filesystem.littlefs.nrf52840dk_spi: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_spi.overlay sample.filesystem.littlefs.nrf52840dk_qspi: build_only: true - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_nrf52840_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_qspi.overlay sample.filesystem.littlefs.stm32h747i_disco_m7_sdmmc: build_only: true - platform_allow: stm32h747i_disco_m7 + platform_allow: stm32h747i_disco/stm32h747xx/m7 extra_args: - - OVERLAY_CONFIG=boards/stm32h747i_disco_m7.conf - CONF_FILE=prj_blk.conf diff --git a/samples/subsys/input/input_dump/README.rst b/samples/subsys/input/input_dump/README.rst index 0492f02b831b22..e16649382b2d1f 100644 --- a/samples/subsys/input/input_dump/README.rst +++ b/samples/subsys/input/input_dump/README.rst @@ -17,11 +17,11 @@ The samples works on any board with an input driver defined in the board devicet Building and Running ******************** -Build and flash as follows, changing ``nrf52dk_nrf52832`` for your board: +Build and flash as follows, changing ``nrf52dk/nrf52832`` for your board: .. zephyr-app-commands:: :zephyr-app: samples/subsys/input/input_dump - :board: nrf52dk_nrf52832 + :board: nrf52dk/nrf52832 :goals: build flash :compact: diff --git a/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt b/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt index 2d9d62bdf23ac9..215648de38aafa 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt +++ b/samples/subsys/ipc/ipc_service/icmsg/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT ("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp")) +if(NOT ("${BOARD}" STREQUAL "nrf5340dk")) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild index 47884745130c14..d0849e37ddef1f 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild +++ b/samples/subsys/ipc/ipc_service/icmsg/Kconfig.sysbuild @@ -6,4 +6,4 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" diff --git a/samples/subsys/ipc/ipc_service/icmsg/README.rst b/samples/subsys/ipc/ipc_service/icmsg/README.rst index c12c410707592f..897fa2503b0fc8 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/README.rst +++ b/samples/subsys/ipc/ipc_service/icmsg/README.rst @@ -11,12 +11,12 @@ This application demonstrates how to use IPC Service and the icmsg backend with Zephyr. It is designed to demonstrate how to integrate it with Zephyr both from a build perspective and code. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/ipc_service/icmsg - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug :west-args: --sysbuild diff --git a/samples/subsys/ipc/ipc_service/icmsg/sample.yaml b/samples/subsys/ipc/ipc_service/icmsg/sample.yaml index b54fc7f8962037..af1f172d7097ce 100644 --- a/samples/subsys/ipc/ipc_service/icmsg/sample.yaml +++ b/samples/subsys/ipc/ipc_service/icmsg/sample.yaml @@ -2,9 +2,9 @@ sample: name: IPC Service example integration (icmsg backend) tests: sample.ipc.icmsg: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true harness: remote diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt b/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt index b342f55061637f..0b8090dd500b94 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT ("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp")) +if(NOT ("${BOARD}" STREQUAL "nrf5340dk")) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild index 47884745130c14..d0849e37ddef1f 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/Kconfig.sysbuild @@ -6,4 +6,4 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst b/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst index faff69e007fbc5..c3d0c2019fe7ba 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/README.rst @@ -7,12 +7,12 @@ This application demonstrates how to use IPC Service with multiple endpoints. By default, it uses the ``icmsg_me`` backend. You can also configure it to use the ``icbmsg`` backend. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/ipc_service/multi_endpoint - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug Open a serial terminal (for example Minicom or PuTTY) and connect the board with the following settings: @@ -68,6 +68,6 @@ overlay files as follows: .. code-block:: console - west build -b nrf5340dk_nrf5340_cpuapp --sysbuild -- \ + west build -b nrf5340dk/nrf5340/cpuapp --sysbuild -- \ -DDTC_OVERLAY_FILE=boards/nrf5340dk_nrf5340_cpuapp_icbmsg.overlay \ -Dremote_DTC_OVERLAY_FILE=boards/nrf5340dk_nrf5340_cpunet_icbmsg.overlay diff --git a/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml b/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml index fdb3c707d8e5ad..401bbf517357fa 100644 --- a/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml +++ b/samples/subsys/ipc/ipc_service/multi_endpoint/sample.yaml @@ -2,16 +2,16 @@ sample: name: IPC Service example integration (icmsg multi endpoint backend) tests: sample.ipc.multi_endpoint: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true harness: remote sample.ipc.multi_endpoint.icbmsg: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true extra_args: diff --git a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt index 6af69691e1e0c1..eb26f752c96716 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt +++ b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT ("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp")) +if(NOT ("${BOARD}" STREQUAL "nrf5340dk")) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild index 47884745130c14..d0849e37ddef1f 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild +++ b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild @@ -6,4 +6,4 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" diff --git a/samples/subsys/ipc/ipc_service/static_vrings/README.rst b/samples/subsys/ipc/ipc_service/static_vrings/README.rst index 7fbed84cad8ced..97cd8c823b2478 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/README.rst +++ b/samples/subsys/ipc/ipc_service/static_vrings/README.rst @@ -11,12 +11,12 @@ This application demonstrates how to use IPC Service and the static vrings backend with Zephyr. It is designed to demonstrate how to integrate it with Zephyr both from a build perspective and code. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/ipc_service/static_vrings - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug :west-args: --sysbuild diff --git a/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml b/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml index 3e57abf32eb932..f776f90adb9e24 100644 --- a/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml +++ b/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml @@ -2,9 +2,9 @@ sample: name: IPC Service example integration (OpenAMP static_vrings backend) tests: sample.ipc.static_vrings: - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tags: ipc sysbuild: true harness: remote diff --git a/samples/subsys/ipc/openamp/Kconfig.sysbuild b/samples/subsys/ipc/openamp/Kconfig.sysbuild index 7a7963ad16f19d..9063dacafa1d70 100644 --- a/samples/subsys/ipc/openamp/Kconfig.sysbuild +++ b/samples/subsys/ipc/openamp/Kconfig.sysbuild @@ -6,10 +6,10 @@ source "share/sysbuild/Kconfig" config OPENAMP_REMOTE_BOARD string - default "lpcxpresso54114_m0" if $(BOARD) = "lpcxpresso54114_m4" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" - default "mps2_an521_remote" if $(BOARD) = "mps2_an521" - default "v2m_musca_b1_ns" if $(BOARD) = "v2m_musca_b1" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" + default "lpcxpresso54114/lpc54114/m0" if $(BOARD) = "lpcxpresso54114" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" + default "mps2/an521/cpu1" if $(BOARD) = "mps2" + default "v2m_musca_b1/musca_b1/ns" if $(BOARD) = "v2m_musca_b1" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" diff --git a/samples/subsys/ipc/openamp/README.rst b/samples/subsys/ipc/openamp/README.rst index 1ad79dff354264..a75ef69017d5ba 100644 --- a/samples/subsys/ipc/openamp/README.rst +++ b/samples/subsys/ipc/openamp/README.rst @@ -17,34 +17,34 @@ Building the application for lpcxpresso54114_m4 .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: lpcxpresso54114_m4 + :board: lpcxpresso54114/lpc54114/m4 :goals: debug :west-args: --sysbuild -Building the application for lpcxpresso55s69_cpu0 -************************************************* +Building the application for lpcxpresso55s69/lpc55s69/cpu0 +********************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: lpcxpresso55s69_cpu0 + :board: lpcxpresso55s69/lpc55s69/cpu0 :goals: debug :west-args: --sysbuild -Building the application for mps2_an521 -*************************************** +Building the application for mps2/an521/cpu0 +******************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: mps2_an521 + :board: mps2/an521/cpu0 :goals: debug :west-args: --sysbuild -Building the application for v2m_musca_b1 -***************************************** +Building the application for v2m_musca_b1/musca_b1 +************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/openamp - :board: v2m_musca_b1 + :board: v2m_musca_b1/musca_b1 :goals: debug :west-args: --sysbuild diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.conf b/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.conf similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.conf rename to samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.conf diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.overlay b/samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso54114_m4.overlay rename to samples/subsys/ipc/openamp/boards/lpcxpresso54114_lpc54114_m4.overlay diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.conf b/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.conf rename to samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.overlay b/samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/lpcxpresso55s69_cpu0.overlay rename to samples/subsys/ipc/openamp/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.conf b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.conf rename to samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evk_cm7.overlay rename to samples/subsys/ipc/openamp/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000000..630a1933d62bd4 --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,2 @@ +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000000..7facea692cbeac --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2022 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + chosen { + zephyr,ipc_shm = &ocram2_overlay; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set. + */ + ocram2_overlay: memory@202c0000{ + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000000..ae8dba8cc217f1 --- /dev/null +++ b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,7 @@ +# +# Copyright 2023, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evkb_cm7.overlay rename to samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.conf b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.conf similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.conf rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.conf diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.overlay b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_m0.overlay rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso54114_lpc54114_m0.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.conf b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.conf rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.overlay b/samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_cpu1.overlay rename to samples/subsys/ipc/openamp/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000000..4dfc4a60b76ac7 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000000..87159192cf249e --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,51 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + /* Switch to lpuart2, since primary core uses lpuart1 */ + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,ipc_shm = &ocram2_overlay; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set + */ + ocram2_overlay: memory@202c0000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000000..4dfc4a60b76ac7 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000000..87159192cf249e --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,51 @@ +/* + * Copyright 2022-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + /* Switch to lpuart2, since primary core uses lpuart1 */ + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,ipc_shm = &ocram2_overlay; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set + */ + ocram2_overlay: memory@202c0000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000000..7b43b448c72c27 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,8 @@ +# +# Copyright 2023, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000000..72510d261664a0 --- /dev/null +++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,49 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + /* Switch to lpuart2, since primary core uses lpuart1 */ + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + zephyr,ipc_shm = &ocram2_overlay; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + }; + + /* OpenAMP fails with full 512K OCRAM2 memory region as shared memory. + * Define a subset of the OCRAM2 region for demo to use + * Note that shared memory must have specific MPU attributes set + */ + ocram2_overlay: memory@202c0000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x202c0000 DT_SIZE_K(16)>; + zephyr,memory-region="OCRAM2_OVERLAY"; + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/samples/subsys/ipc/openamp/remote/boards/mps2_an521_remote.overlay b/samples/subsys/ipc/openamp/remote/boards/mps2_an521_cpu1.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/mps2_an521_remote.overlay rename to samples/subsys/ipc/openamp/remote/boards/mps2_an521_cpu1.overlay diff --git a/samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_ns.overlay b/samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_musca_b1_ns.overlay similarity index 100% rename from samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_ns.overlay rename to samples/subsys/ipc/openamp/remote/boards/v2m_musca_b1_musca_b1_ns.overlay diff --git a/samples/subsys/ipc/openamp/remote/sample.yaml b/samples/subsys/ipc/openamp/remote/sample.yaml index 60a8d38681da8f..906449cfdc319a 100644 --- a/samples/subsys/ipc/openamp/remote/sample.yaml +++ b/samples/subsys/ipc/openamp/remote/sample.yaml @@ -4,9 +4,9 @@ sample: tests: sample.ipc.openamp.remote: platform_allow: - - lpcxpresso54114_m0 - - lpcxpresso55s69_cpu1 + - lpcxpresso54114/lpc54114/m0 + - lpcxpresso55s69/lpc55s69/cpu1 integration_platforms: - - lpcxpresso54114_m0 + - lpcxpresso54114/lpc54114/m0 tags: ipm harness: remote diff --git a/samples/subsys/ipc/openamp/sample.yaml b/samples/subsys/ipc/openamp/sample.yaml index 7a6635f72b469d..63268230d9b02c 100644 --- a/samples/subsys/ipc/openamp/sample.yaml +++ b/samples/subsys/ipc/openamp/sample.yaml @@ -4,12 +4,12 @@ sample: tests: sample.ipc.openamp: platform_allow: - - lpcxpresso54114_m4 - - lpcxpresso55s69_cpu0 - - mps2_an521 - - v2m_musca_b1 + - lpcxpresso54114/lpc54114/m4 + - lpcxpresso55s69/lpc55s69/cpu0 + - mps2/an521/cpu0 + - v2m_musca_b1/musca_b1 integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 tags: ipm harness: console sysbuild: true diff --git a/samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.conf b/samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.conf similarity index 100% rename from samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.conf rename to samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.conf diff --git a/samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.overlay b/samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.overlay similarity index 100% rename from samples/subsys/ipc/openamp_rsc_table/boards/nxp_adsp_imx8m.overlay rename to samples/subsys/ipc/openamp_rsc_table/boards/imx8mp_evk_mimx8ml8_adsp.overlay diff --git a/samples/subsys/ipc/openamp_rsc_table/sample.yaml b/samples/subsys/ipc/openamp_rsc_table/sample.yaml index 3c9d58d320216a..d1c94c10585d82 100644 --- a/samples/subsys/ipc/openamp_rsc_table/sample.yaml +++ b/samples/subsys/ipc/openamp_rsc_table/sample.yaml @@ -7,8 +7,8 @@ tests: build_only: true platform_allow: - stm32mp157c_dk2 - - nxp_adsp_imx8m + - imx8mp_evk/mimx8ml8/adsp integration_platforms: - stm32mp157c_dk2 - - nxp_adsp_imx8m + - imx8mp_evk/mimx8ml8/adsp tags: ipm diff --git a/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild b/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild index 9dec2087f953b8..9af87af157f121 100644 --- a/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild +++ b/samples/subsys/ipc/rpmsg_service/Kconfig.sysbuild @@ -5,10 +5,10 @@ source "share/sysbuild/Kconfig" config RPMSG_REMOTE_BOARD -string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" - default "bl5340_dvk_cpunet" if $(BOARD) = "bl5340_dvk_cpuapp" - default "lpcxpresso54114_m0" if $(BOARD) = "lpcxpresso54114_m4" + string + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" + default "bl5340_dvk/nrf5340/cpunet" if $(BOARD) = "bl5340_dvk" + default "lpcxpresso54114/lpc54114/m0" if $(BOARD) = "lpcxpresso54114" default "mps2_an521_remote" if $(BOARD) = "mps2_an521" default "v2m_musca_b1_ns" if $(BOARD) = "v2m_musca_b1" default "esp32_devkitc_wroom_appcpu" if $(BOARD) = "esp32_devkitc_wroom" diff --git a/samples/subsys/ipc/rpmsg_service/README.rst b/samples/subsys/ipc/rpmsg_service/README.rst index 0c63b8dc3bb094..6ff5a61be80437 100644 --- a/samples/subsys/ipc/rpmsg_service/README.rst +++ b/samples/subsys/ipc/rpmsg_service/README.rst @@ -15,28 +15,28 @@ perspective and code. Note that the remote and primary image core images can be flashed independently, but sysbuild must be used in order to flash them in one step. -Building the application for nrf5340dk_nrf5340_cpuapp +Building the application for nrf5340dk/nrf5340/cpuapp ***************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: debug -Building the application for mps2_an521 -*************************************** +Building the application for mps2/an521/cpu0 +******************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: mps2_an521 + :board: mps2/an521/cpu0 :goals: debug -Building the application for v2m_musca_b1 -***************************************** +Building the application for v2m_musca_b1/musca_b1 +************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: v2m_musca_b1 + :board: v2m_musca_b1/musca_b1 :goals: debug Open a serial terminal (minicom, putty, etc.) and connect the board with the @@ -77,17 +77,17 @@ serial port, one is master another is remote: Remote core received a message: 98 RPMsg Service demo ended. -Building the application for bl5340_dvk_cpuapp -********************************************** +Building the application for bl5340_dvk/nrf5340/cpuapp +****************************************************** .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: bl5340_dvk_cpuapp + :board: bl5340_dvk/nrf5340/cpuapp :goals: debug .. zephyr-app-commands:: :zephyr-app: samples/subsys/ipc/rpmsg_service - :board: bl5340_dvk_cpunet + :board: bl5340_dvk/nrf5340/cpunet :goals: debug Open a serial terminal (for example Minicom or PuTTY) and connect to the board diff --git a/samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_cpuapp.conf b/samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf similarity index 100% rename from samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_cpuapp.conf rename to samples/subsys/ipc/rpmsg_service/boards/bl5340_dvk_nrf5340_cpuapp.conf diff --git a/samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_remote.overlay b/samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_cpu1.overlay similarity index 100% rename from samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_remote.overlay rename to samples/subsys/ipc/rpmsg_service/remote/boards/mps2_an521_cpu1.overlay diff --git a/samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_ns.overlay b/samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_musca_b1_ns.overlay similarity index 100% rename from samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_ns.overlay rename to samples/subsys/ipc/rpmsg_service/remote/boards/v2m_musca_b1_musca_b1_ns.overlay diff --git a/samples/subsys/llext/shell_loader/README.rst b/samples/subsys/llext/shell_loader/README.rst index 583299028be0e8..5062222ff2b0e5 100644 --- a/samples/subsys/llext/shell_loader/README.rst +++ b/samples/subsys/llext/shell_loader/README.rst @@ -20,7 +20,7 @@ Building .. zephyr-app-commands:: :zephyr-app: samples/subsys/llext/shell_loader - :board: tdk_robokit1 + :board: robokit1 :goals: build :compact: diff --git a/samples/subsys/llext/shell_loader/sample.yaml b/samples/subsys/llext/shell_loader/sample.yaml index 3cf54e450204d6..2af28551af595e 100644 --- a/samples/subsys/llext/shell_loader/sample.yaml +++ b/samples/subsys/llext/shell_loader/sample.yaml @@ -3,9 +3,9 @@ common: arch_allow: - arm - xtensa - filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52 + filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE platform_exclude: - - nuvoton_pfm_m487 # See #63167 + - numaker_pfm_m487 # See #63167 sample: description: Loadable extensions with shell sample name: Extension loader shell diff --git a/samples/subsys/logging/dictionary/sample.yaml b/samples/subsys/logging/dictionary/sample.yaml index a135f70df2f38f..6bbe7622c0e441 100644 --- a/samples/subsys/logging/dictionary/sample.yaml +++ b/samples/subsys/logging/dictionary/sample.yaml @@ -30,9 +30,9 @@ tests: sample.logger.basic.dictionary.uart_async_frontend: build_only: true tags: logging - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_LOG_BACKEND_UART=n - CONFIG_LOG_BACKEND_RTT=n @@ -44,9 +44,9 @@ tests: sample.logger.basic.dictionary.uart_frontend_rt: build_only: true tags: logging - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp extra_configs: - CONFIG_SHELL=y - CONFIG_LOG_RUNTIME_FILTERING=y diff --git a/samples/subsys/logging/logger/sample.yaml b/samples/subsys/logging/logger/sample.yaml index 8ef962daeb95e3..3d82207668543e 100644 --- a/samples/subsys/logging/logger/sample.yaml +++ b/samples/subsys/logging/logger/sample.yaml @@ -31,7 +31,7 @@ tests: sample.logger.usermode: integration_platforms: - - mps2_an385 + - mps2/an385 platform_exclude: - ip_k66f - bl652_dvk diff --git a/samples/subsys/logging/multidomain/CMakeLists.txt b/samples/subsys/logging/multidomain/CMakeLists.txt index a0cc842a6a8b49..d800a86fac2782 100644 --- a/samples/subsys/logging/multidomain/CMakeLists.txt +++ b/samples/subsys/logging/multidomain/CMakeLists.txt @@ -8,7 +8,7 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(NOT(("${BOARD}" STREQUAL "nrf5340dk_nrf5340_cpuapp") +if(NOT(("${BOARD}" STREQUAL "nrf5340dk") OR ("${BOARD}" STREQUAL "nrf5340bsim_nrf5340_cpuapp"))) message(FATAL_ERROR "${BOARD} is not supported for this sample") endif() diff --git a/samples/subsys/logging/multidomain/Kconfig.sysbuild b/samples/subsys/logging/multidomain/Kconfig.sysbuild index b6dc3d0a6d0d35..e6d2ccd9930040 100644 --- a/samples/subsys/logging/multidomain/Kconfig.sysbuild +++ b/samples/subsys/logging/multidomain/Kconfig.sysbuild @@ -6,5 +6,5 @@ source "share/sysbuild/Kconfig" config NET_CORE_BOARD string - default "nrf5340dk_nrf5340_cpunet" if $(BOARD) = "nrf5340dk_nrf5340_cpuapp" + default "nrf5340dk/nrf5340/cpunet" if $(BOARD) = "nrf5340dk" default "nrf5340bsim_nrf5340_cpunet" if $(BOARD) = "nrf5340bsim_nrf5340_cpuapp" diff --git a/samples/subsys/logging/multidomain/sample.yaml b/samples/subsys/logging/multidomain/sample.yaml index 79523c9951a3a0..9d0075017fa05e 100644 --- a/samples/subsys/logging/multidomain/sample.yaml +++ b/samples/subsys/logging/multidomain/sample.yaml @@ -6,9 +6,9 @@ common: tests: sample.logging.multidomain.ipc_static_vrings.hw: platform_allow: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp integration_platforms: - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp build_only: true sample.logging.multidomain.ipc_static_vrings.simu: platform_allow: diff --git a/samples/subsys/logging/syst/sample.yaml b/samples/subsys/logging/syst/sample.yaml index 4501d5740e3bb7..8c4681c4fe8823 100644 --- a/samples/subsys/logging/syst/sample.yaml +++ b/samples/subsys/logging/syst/sample.yaml @@ -15,7 +15,7 @@ tests: sample.logger.syst.deferred: toolchain_exclude: xcc integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_args: OVERLAY_CONFIG=overlay_deferred.conf harness: console @@ -38,7 +38,7 @@ tests: extra_args: OVERLAY_CONFIG=overlay_immediate.conf integration_platforms: - qemu_x86 - - sam_e70_xplained + - sam_e70_xplained/same70q21 harness: console harness_config: type: multi_line @@ -95,7 +95,7 @@ tests: sample.logger.syst.immediate_cpp: toolchain_exclude: xcc integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 harness: console harness_config: diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/README.rst b/samples/subsys/mgmt/mcumgr/smp_svr/README.rst index c24103815aff93..ce5cd64561dbb0 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/README.rst +++ b/samples/subsys/mgmt/mcumgr/smp_svr/README.rst @@ -90,7 +90,7 @@ Zephyr. The ``smp_svr`` sample comes in different flavours. .. code-block:: console west build \ - -b nrf52dk_nrf52832 \ + -b nrf52dk/nrf52832 \ samples/subsys/mgmt/mcumgr/smp_svr \ -- \ -DEXTRA_CONF_FILE=overlay-bt.conf @@ -114,7 +114,7 @@ Zephyr. The ``smp_svr`` sample comes in different flavours. .. code-block:: console west build \ - -b nrf52840dk_nrf52840 \ + -b nrf52840dk/nrf52840 \ samples/subsys/mgmt/mcumgr/smp_svr \ -- \ -DEXTRA_CONF_FILE=overlay-cdc.conf \ diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml index a13270e5845443..007179b2f804a7 100644 --- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml +++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml @@ -8,13 +8,13 @@ tests: sample.mcumgr.smp_svr.bt: extra_args: OVERLAY_CONFIG="overlay-bt.conf" platform_allow: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.udp: extra_args: OVERLAY_CONFIG="overlay-udp.conf" platform_allow: frdm_k64f @@ -25,24 +25,24 @@ tests: - OVERLAY_CONFIG="overlay-cdc.conf" - DTC_OVERLAY_FILE="usb.overlay" platform_allow: - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp - pinnacle_100_dvk integration_platforms: - - nrf52833dk_nrf52820 - - nrf52833dk_nrf52833 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52833dk/nrf52820 + - nrf52833dk/nrf52833 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp sample.mcumgr.smp_svr.serial: extra_args: OVERLAY_CONFIG="overlay-serial.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 # In mcuboot_flags test overlay-serial.conf is used for convenience as it is the simplest # transport. Transport does not affect flags so it does not really matter which is selected, # flags should affect any transport the same way. @@ -51,44 +51,44 @@ tests: extra_configs: - CONFIG_MCUBOOT_BOOTLOADER_MODE_DIRECT_XIP_WITH_REVERT=y platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.serial-console: extra_args: OVERLAY_CONFIG="overlay-serial-console.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.shell: extra_args: OVERLAY_CONFIG="overlay-shell.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mimxrt1060_evk - mimxrt1064_evk - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mimxrt1060_evk - mimxrt1064_evk sample.mcumgr.smp_svr.shell_mgmt: extra_args: OVERLAY_CONFIG="overlay-shell-mgmt.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 sample.mcumgr.smp_svr.fs: extra_args: OVERLAY_CONFIG="overlay-fs.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - pinnacle_100_dvk - mg100 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/samples/subsys/mgmt/osdp/control_panel/sample.yaml b/samples/subsys/mgmt/osdp/control_panel/sample.yaml index 5fecf6ad24a796..d527c7a7d15f26 100644 --- a/samples/subsys/mgmt/osdp/control_panel/sample.yaml +++ b/samples/subsys/mgmt/osdp/control_panel/sample.yaml @@ -8,7 +8,8 @@ common: dt_chosen_enabled("zephyr,osdp-uart") and CONFIG_SERIAL harness: osdp integration_platforms: - - stm32_min_dev_black + - stm32_min_dev@black + - stm32_min_dev@blue tests: sample.mgmt.osdp.control_panel: extra_args: CONF_FILE=prj.conf diff --git a/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml b/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml index 994ea535e3ff79..724f468a2aeb3f 100644 --- a/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml +++ b/samples/subsys/mgmt/osdp/peripheral_device/sample.yaml @@ -8,7 +8,8 @@ common: dt_chosen_enabled("zephyr,osdp-uart") and CONFIG_SERIAL harness: osdp integration_platforms: - - stm32_min_dev_black + - stm32_min_dev@black + - stm32_min_dev@blue tests: sample.mgmt.osdp.peripheral_device: extra_args: CONF_FILE=prj.conf diff --git a/samples/subsys/mgmt/updatehub/README.rst b/samples/subsys/mgmt/updatehub/README.rst index ad29354146e29a..f502e1a1795e32 100644 --- a/samples/subsys/mgmt/updatehub/README.rst +++ b/samples/subsys/mgmt/updatehub/README.rst @@ -188,7 +188,7 @@ for details. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: [ frdm_k64f | nrf52840dk_nrf52840 | nucleo_f767zi ] + :board: [ frdm_k64f | nrf52840dk/nrf52840 | nucleo_f767zi ] :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-wifi.conf;overlay-prj.conf" :shield: esp_8266_arduino @@ -208,7 +208,7 @@ uses PPP over GSM modem, see :zephyr:code-sample:`gsm-modem` sample application. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: [ frdm_k64f | nrf52840dk_nrf52840 | nucleo_f767zi ] + :board: [ frdm_k64f | nrf52840dk/nrf52840 | nucleo_f767zi ] :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-modem.conf;overlay-prj.conf" \ -DDTC_OVERLAY_FILE=arduino.overlay @@ -227,7 +227,7 @@ tested with both native linux driver and ``atusb`` and with ``wpanusb`` sample. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-802154.conf;overlay-prj.conf" :goals: build @@ -255,7 +255,7 @@ tested with native linux driver and an USB dongle. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-ipsp.conf;overlay-prj.conf" :goals: build @@ -273,7 +273,7 @@ gateway was tested using two boards with OpenThread 1.1.1 on NCP mode. .. zephyr-app-commands:: :zephyr-app: zephyr/samples/subsys/mgmt/updatehub - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :build-dir: app :gen-args: -DEXTRA_CONF_FILE="overlay-ot.conf;overlay-prj.conf" :goals: build diff --git a/samples/subsys/modbus/rtu_client/sample.yaml b/samples/subsys/modbus/rtu_client/sample.yaml index 0ff16e34204ac4..006e76f97028cf 100644 --- a/samples/subsys/modbus/rtu_client/sample.yaml +++ b/samples/subsys/modbus/rtu_client/sample.yaml @@ -4,10 +4,10 @@ tests: sample.modbus.rtu_client: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - uart - modbus diff --git a/samples/subsys/modbus/rtu_server/README.rst b/samples/subsys/modbus/rtu_server/README.rst index 289aa73ea7b7a1..aae880b78659f9 100644 --- a/samples/subsys/modbus/rtu_server/README.rst +++ b/samples/subsys/modbus/rtu_server/README.rst @@ -58,7 +58,7 @@ The following commands build and flash RTU server sample. .. zephyr-app-commands:: :zephyr-app: samples/subsys/modbus/rtu_server - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: @@ -66,7 +66,7 @@ The following commands build and flash RTU server sample using CDC ACM UART. .. zephyr-app-commands:: :zephyr-app: samples/subsys/modbus/rtu_server - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :gen-args: -DDTC_OVERLAY_FILE=cdc-acm.overlay -DEXTRA_CONF_FILE=overlay-cdc-acm.conf :compact: diff --git a/samples/subsys/modbus/rtu_server/sample.yaml b/samples/subsys/modbus/rtu_server/sample.yaml index cdc239211b2f51..76f1eba7f44c14 100644 --- a/samples/subsys/modbus/rtu_server/sample.yaml +++ b/samples/subsys/modbus/rtu_server/sample.yaml @@ -4,10 +4,10 @@ tests: sample.modbus.rtu_server: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - uart - modbus @@ -20,10 +20,10 @@ tests: sample.modbus.rtu_server.cdc_acm: build_only: true platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - usb - modbus diff --git a/samples/subsys/nvs/README.rst b/samples/subsys/nvs/README.rst index ac1df6f9cf794a..c9912631614d93 100644 --- a/samples/subsys/nvs/README.rst +++ b/samples/subsys/nvs/README.rst @@ -23,11 +23,11 @@ Building and Running This sample can be found under :zephyr_file:`samples/subsys/nvs` in the Zephyr tree. The sample can be build for several platforms, the following commands build the -application for the nrf51dk_nrf51422 board. +application for the nrf51dk/nrf51822 board. .. zephyr-app-commands:: :zephyr-app: samples/subsys/nvs - :board: nrf51dk_nrf51422 + :board: nrf51dk/nrf51822 :goals: build flash :compact: diff --git a/samples/subsys/nvs/sample.yaml b/samples/subsys/nvs/sample.yaml index e2249e9f3eb03a..051edc635f9d87 100644 --- a/samples/subsys/nvs/sample.yaml +++ b/samples/subsys/nvs/sample.yaml @@ -7,7 +7,7 @@ tests: depends_on: nvs platform_exclude: qemu_x86 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 harness: console harness_config: type: multi_line diff --git a/samples/subsys/pm/device_pm/sample.yaml b/samples/subsys/pm/device_pm/sample.yaml index 13a57cd4b2ae4e..ee91d4678fa1f5 100644 --- a/samples/subsys/pm/device_pm/sample.yaml +++ b/samples/subsys/pm/device_pm/sample.yaml @@ -3,10 +3,10 @@ sample: tests: sample.power.ospm.dev_idle_pm: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - qemu_x86 - - mps2_an385 + - mps2/an385 integration_platforms: - qemu_x86 tags: power diff --git a/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml b/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml index f4a8ad690cf27f..f3ef6778395855 100644 --- a/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml +++ b/samples/subsys/portability/cmsis_rtos_v2/timer_synchronization/sample.yaml @@ -5,7 +5,7 @@ tests: integration_platforms: - native_sim platform_exclude: - - qemu_arc_hs5x # See issue #62405 + - qemu_arc/qemu_arc_hs5x # See issue #62405 tags: cmsis_rtos min_ram: 32 min_flash: 34 diff --git a/samples/subsys/settings/README.rst b/samples/subsys/settings/README.rst index 82f8b797e86de8..c126ca1d0daef4 100644 --- a/samples/subsys/settings/README.rst +++ b/samples/subsys/settings/README.rst @@ -16,7 +16,7 @@ register them. Requirements ************ -* A board with settings support, for instance: nrf52840dk_nrf52840 +* A board with settings support, for instance: nrf52840dk/nrf52840 * Or qemu_x86 target Building and Running diff --git a/samples/subsys/shell/fs/sample.yaml b/samples/subsys/shell/fs/sample.yaml index 2f30aad68bbb5b..e065b4e27eba8f 100644 --- a/samples/subsys/shell/fs/sample.yaml +++ b/samples/subsys/shell/fs/sample.yaml @@ -25,7 +25,7 @@ tests: sample.filesystem.shell.flash_load: tags: - flash_load - platform_allow: nrf52dk_nrf52832 + platform_allow: nrf52dk/nrf52832 extra_args: CONF_FILE=prj_flash_load.conf integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/samples/subsys/shell/shell_module/sample.yaml b/samples/subsys/shell/shell_module/sample.yaml index 95ac36bc6b33e9..ceba72d68422c4 100644 --- a/samples/subsys/shell/shell_module/sample.yaml +++ b/samples/subsys/shell/shell_module/sample.yaml @@ -43,7 +43,7 @@ tests: harness: keyboard extra_args: CONF_FILE="prj_minimal_rtt.conf" integration_platforms: - - nrf52833dk_nrf52833 + - nrf52833dk/nrf52833 sample.shell.shell_module.login: filter: CONFIG_SERIAL and dt_chosen_enabled("zephyr,shell-uart") tags: shell diff --git a/samples/subsys/task_wdt/sample.yaml b/samples/subsys/task_wdt/sample.yaml index 334d6e3a24f7cb..fc4ca93776b497 100644 --- a/samples/subsys/task_wdt/sample.yaml +++ b/samples/subsys/task_wdt/sample.yaml @@ -17,8 +17,10 @@ common: - "Task watchdog sample application." depends_on: watchdog platform_exclude: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 tests: sample.task_wdt: integration_platforms: diff --git a/samples/subsys/tracing/README.rst b/samples/subsys/tracing/README.rst index 299ab0a751d61c..89c3ac1eb5f358 100644 --- a/samples/subsys/tracing/README.rst +++ b/samples/subsys/tracing/README.rst @@ -19,7 +19,7 @@ Build a UART-tracing image with: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: mps2_an521 + :board: mps2/an521 :conf: "prj_uart.conf" :goals: build :compact: @@ -28,7 +28,7 @@ or: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: mps2_an521 + :board: mps2/an521 :conf: "prj_uart_ctf.conf" :goals: build :compact: @@ -44,7 +44,7 @@ Build a USB-tracing image with: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: sam_e70_xplained + :board: sam_e70_xplained/same70q21 :conf: "prj_usb.conf" :goals: build :compact: @@ -53,7 +53,7 @@ or: .. zephyr-app-commands:: :zephyr-app: samples/subsys/tracing - :board: sam_e70_xplained + :board: sam_e70_xplained/same70q21 :conf: "prj_usb_ctf.conf" :goals: build :compact: diff --git a/samples/subsys/tracing/sample.yaml b/samples/subsys/tracing/sample.yaml index 23db8876ceebc5..877ea096b5802a 100644 --- a/samples/subsys/tracing/sample.yaml +++ b/samples/subsys/tracing/sample.yaml @@ -23,11 +23,11 @@ tests: - "sys_trace_.*_user.*" sample.tracing.format.sysview: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mimxrt1050_evk - mimxrt1064_evk integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: CONF_FILE="prj_sysview.conf" sample.tracing.osawareness.openocd: arch_exclude: @@ -45,7 +45,7 @@ tests: extra_args: CONF_FILE="prj_uart.conf" filter: dt_chosen_enabled("zephyr,tracing-uart") sample.tracing.transport.usb: - platform_allow: sam_e70_xplained + platform_allow: sam_e70_xplained/same70q21 depends_on: usb_device extra_args: CONF_FILE="prj_usb.conf" sample.tracing.transport.uart.ctf: @@ -57,7 +57,7 @@ tests: extra_args: CONF_FILE="prj_uart_ctf.conf" filter: dt_chosen_enabled("zephyr,tracing-uart") sample.tracing.transport.usb.ctf: - platform_allow: sam_e70_xplained + platform_allow: sam_e70_xplained/same70q21 depends_on: usb_device extra_args: CONF_FILE="prj_usb_ctf.conf" sample.tracing.transport.native: diff --git a/samples/subsys/usb/audio/headphones_microphone/sample.yaml b/samples/subsys/usb/audio/headphones_microphone/sample.yaml index dde503ee1ea4b3..16420c75f440dc 100644 --- a/samples/subsys/usb/audio/headphones_microphone/sample.yaml +++ b/samples/subsys/usb/audio/headphones_microphone/sample.yaml @@ -6,8 +6,8 @@ tests: tags: usb arch_exclude: posix integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/subsys/usb/audio/headset/sample.yaml b/samples/subsys/usb/audio/headset/sample.yaml index 83a20596db7101..6c61a4ce7ef527 100644 --- a/samples/subsys/usb/audio/headset/sample.yaml +++ b/samples/subsys/usb/audio/headset/sample.yaml @@ -6,8 +6,8 @@ tests: tags: usb arch_exclude: posix integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp harness: console harness_config: type: multi_line diff --git a/samples/subsys/usb/cdc_acm/sample.yaml b/samples/subsys/usb/cdc_acm/sample.yaml index 61b72fa41efdc1..85dc6b7af27641 100644 --- a/samples/subsys/usb/cdc_acm/sample.yaml +++ b/samples/subsys/usb/cdc_acm/sample.yaml @@ -15,9 +15,9 @@ tests: tags: usb extra_args: CONF_FILE="usbd_next_prj.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f - - 96b_carbon + - 96b_carbon/stm32f401xe harness: console harness_config: type: one_line diff --git a/samples/subsys/usb/dfu/README.rst b/samples/subsys/usb/dfu/README.rst index 0ca87d7a8cf322..04e0fbf332d18a 100644 --- a/samples/subsys/usb/dfu/README.rst +++ b/samples/subsys/usb/dfu/README.rst @@ -39,7 +39,7 @@ For example: .. code-block:: console - west build -b nrf52840dk_nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ + west build -b nrf52840dk/nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"bootloader/mcuboot/root-rsa-2048.pem\" Build and flash MCUboot bootloader for Zephyr project as it is described in @@ -53,7 +53,7 @@ in :ref:`mcuboot`). For example: .. code-block:: console - west build -b nrf52840dk_nrf52840 zephyr/samples/hello_world -d build-hello_world -- \ + west build -b nrf52840dk/nrf52840 zephyr/samples/hello_world -d build-hello_world -- \ -DCONFIG_BOOTLOADER_MCUBOOT=y '-DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem"' Testing @@ -88,7 +88,7 @@ showing this output to the console: I: Bootloader chainload address offset: 0xc000 I: Jumping to the first image slot *** Booting Zephyr OS build zephyr-v3.0.0-361-gb987e6daa2f9 *** - Hello World! nrf52840dk_nrf52840 + Hello World! nrf52840dk Reset the SoC again and MCUboot should revert the images and boot @@ -128,7 +128,7 @@ Both symbols can be enabled with the :file:`overlay-permanent-download.conf` ove .. code-block:: console - west build -b nrf52840dk_nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ + west build -b nrf52840dk/nrf52840 zephyr/samples/subsys/usb/dfu -d build-dfu -- \ -DCONFIG_BOOTLOADER_MCUBOOT=y '-DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE="bootloader/mcuboot/root-rsa-2048.pem"' \ -DEXTRA_CONF_FILE=overlay-permanent-download.conf @@ -150,7 +150,7 @@ Note the ``Swap type: perm``. I: Bootloader chainload address offset: 0xc000 I: Jumping to the first image slot *** Booting Zephyr OS build zephyr-v3.0.0-361-gb987e6daa2f9 *** - Hello World! nrf52840dk_nrf52840 + Hello World! nrf52840dk .. _MCUboot GitHub repo: https://github.com/zephyrproject-rtos/mcuboot diff --git a/samples/subsys/usb/dfu/sample.yaml b/samples/subsys/usb/dfu/sample.yaml index f74c6327c86b2b..1700b087473395 100644 --- a/samples/subsys/usb/dfu/sample.yaml +++ b/samples/subsys/usb/dfu/sample.yaml @@ -6,26 +6,26 @@ common: arch_exclude: posix platform_exclude: - mimxrt1010_evk - - mimxrt1050_evk_qspi + - mimxrt1050_evk@qspi - mimxrt1020_evk - mimxrt1015_evk - mimxrt1060_evk - sam4l_ek - mimxrt1050_evk - - mimxrt1060_evk_hyperflash + - mimxrt1060_evk@hyperflash - nucleo_f207zg - teensy40 - teensy41 - b_u585i_iot02a - frdm_kl25z - - lpcxpresso55s69_cpu0 - - stm32l562e_dk_ns + - lpcxpresso55s69/lpc55s69/cpu0 + - stm32l562e_dk/stm32l562xx/ns depends_on: usb_device filter: dt_label_with_parent_compat_enabled("slot0_partition", "fixed-partitions") and dt_label_with_parent_compat_enabled("slot1_partition", "fixed-partitions") and dt_chosen_enabled("zephyr,flash-controller") and CONFIG_FLASH_HAS_DRIVER_ENABLED integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f tests: sample.usb.dfu: diff --git a/samples/subsys/usb/hid-cdc/README.rst b/samples/subsys/usb/hid-cdc/README.rst index 403785ef25e62b..e0678d9d17364a 100644 --- a/samples/subsys/usb/hid-cdc/README.rst +++ b/samples/subsys/usb/hid-cdc/README.rst @@ -42,7 +42,7 @@ for the :ref:`nrf52840dk_nrf52840` board: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/hid-cdc - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :goals: build flash :compact: diff --git a/samples/subsys/usb/hid-cdc/sample.yaml b/samples/subsys/usb/hid-cdc/sample.yaml index 15ee2d5a47dde3..acc25a0ac1a7b0 100644 --- a/samples/subsys/usb/hid-cdc/sample.yaml +++ b/samples/subsys/usb/hid-cdc/sample.yaml @@ -4,9 +4,9 @@ tests: sample.usb.hid-cdc: depends_on: usb_device platform_allow: - - nrf52840dk_nrf52840 - - nrf52840dongle_nrf52840 + - nrf52840dk/nrf52840 + - nrf52840dongle/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness: button tags: usb diff --git a/samples/subsys/usb/mass/README.rst b/samples/subsys/usb/mass/README.rst index 1c2011f363f9d1..64b6293cbdd16f 100644 --- a/samples/subsys/usb/mass/README.rst +++ b/samples/subsys/usb/mass/README.rst @@ -61,7 +61,7 @@ to use the external 16 MiBi QSPI flash chip with a 2 MiBy FAT partition. .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass - :board: adafruit_feather_nrf52840 + :board: adafruit_feather/nrf52840 :gen-args: -DCONFIG_APP_MSC_STORAGE_FLASH_FATFS=y :goals: build :compact: @@ -128,7 +128,7 @@ be connected to SPI using e.g. a shield, example can be built as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: waveshare_epaper_gdeh0154a07 :gen-args: -DCONFIG_APP_MSC_STORAGE_SDCARD=y :goals: build @@ -162,7 +162,7 @@ This board configures to use the external 64 MiBi QSPI flash chip with a .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/mass - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DCONFIG_APP_MSC_STORAGE_FLASH_LITTLEFS=y :goals: build :compact: diff --git a/samples/subsys/usb/mass/boards/stm32l562e_dk_ns.conf b/samples/subsys/usb/mass/boards/stm32l562e_dk_stm32l562xx_ns.conf similarity index 100% rename from samples/subsys/usb/mass/boards/stm32l562e_dk_ns.conf rename to samples/subsys/usb/mass/boards/stm32l562e_dk_stm32l562xx_ns.conf diff --git a/samples/subsys/usb/mass/sample.yaml b/samples/subsys/usb/mass/sample.yaml index 9149012a212aae..d7c2c32bc59334 100644 --- a/samples/subsys/usb/mass/sample.yaml +++ b/samples/subsys/usb/mass/sample.yaml @@ -23,7 +23,7 @@ tests: min_ram: 128 depends_on: usb_device platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f extra_args: - CONF_FILE="usbd_next_prj.conf" @@ -66,11 +66,11 @@ tests: depends_on: usb_device filter: dt_compat_enabled("nordic,qspi-nor") platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - adafruit_feather/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_LOG_DEFAULT_LEVEL=3 - CONFIG_APP_MSC_STORAGE_FLASH_FATFS=y @@ -91,11 +91,11 @@ tests: depends_on: usb_device filter: dt_compat_enabled("nordic,qspi-nor") platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - adafruit_feather/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: CONF_FILE="usbd_next_prj.conf" extra_configs: - CONFIG_LOG_DEFAULT_LEVEL=3 @@ -138,11 +138,11 @@ tests: depends_on: usb_device filter: dt_compat_enabled("nordic,qspi-nor") platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - adafruit_feather_nrf52840 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - adafruit_feather/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_configs: - CONFIG_LOG_DEFAULT_LEVEL=3 - CONFIG_APP_MSC_STORAGE_FLASH_LITTLEFS=y diff --git a/samples/subsys/usb/shell/README.rst b/samples/subsys/usb/shell/README.rst index 0e368187c79e11..9f2ddb8898d6ed 100644 --- a/samples/subsys/usb/shell/README.rst +++ b/samples/subsys/usb/shell/README.rst @@ -28,7 +28,7 @@ currently it is only MAX3421E. The example can be built as follows: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/shell - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :shield: sparkfun_max3421e :gen-args: -DCONFIG_UHC_DRIVER=y -DCONFIG_USB_HOST_STACK=y :goals: flash @@ -40,7 +40,7 @@ the platform has already defined or not `zephyr_uhc0` or `zephyr_udc0` nodelabel .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/shell - :board: nrf52840dk_nrf52840 + :board: nrf52840dk/nrf52840 :gen-args: -DEXTRA_CONF_FILE=virtual.conf -DDTC_OVERLAY_FILE=virtual.overlay :goals: flash :compact: diff --git a/samples/subsys/usb/shell/sample.yaml b/samples/subsys/usb/shell/sample.yaml index fa09a7769d12e2..834044da3df5f3 100644 --- a/samples/subsys/usb/shell/sample.yaml +++ b/samples/subsys/usb/shell/sample.yaml @@ -3,7 +3,7 @@ sample: tests: sample.usbd.shell: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f depends_on: usb_device harness: keyboard @@ -17,7 +17,7 @@ tests: - CONF_FILE="device_and_host_prj.conf" - SHIELD="sparkfun_max3421e" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - frdm_k64f build_only: true sample.usbh.shell.virtual: diff --git a/samples/subsys/usb/uac2_explicit_feedback/README.rst b/samples/subsys/usb/uac2_explicit_feedback/README.rst index 8d9ff40dc7a269..dd6ec13908e788 100644 --- a/samples/subsys/usb/uac2_explicit_feedback/README.rst +++ b/samples/subsys/usb/uac2_explicit_feedback/README.rst @@ -59,6 +59,6 @@ To build and flash the application: .. zephyr-app-commands:: :zephyr-app: samples/subsys/usb/uac2_explicit_feedback - :board: nrf5340dk_nrf5340_cpuapp + :board: nrf5340dk/nrf5340/cpuapp :goals: build flash :compact: diff --git a/samples/subsys/usb/uac2_explicit_feedback/sample.yaml b/samples/subsys/usb/uac2_explicit_feedback/sample.yaml index c1f851c009b7a7..c9d5457470168a 100644 --- a/samples/subsys/usb/uac2_explicit_feedback/sample.yaml +++ b/samples/subsys/usb/uac2_explicit_feedback/sample.yaml @@ -6,5 +6,5 @@ tests: - usb_device - i2s tags: usb i2s - platform_allow: nrf5340dk_nrf5340_cpuapp + platform_allow: nrf5340dk/nrf5340/cpuapp harness: TBD diff --git a/samples/subsys/zbus/benchmark/README.rst b/samples/subsys/zbus/benchmark/README.rst index 52a7d864481839..2db3e7d23ff3ca 100644 --- a/samples/subsys/zbus/benchmark/README.rst +++ b/samples/subsys/zbus/benchmark/README.rst @@ -56,9 +56,9 @@ The complete benchmark command using Robot framework is: .. code-block:: console - robot --variable serial_port:/dev/ttyACM0 --variable board:nrf52dk_nrf52832 -d /tmp/benchmark_out benchmark_256KB.robot + robot --variable serial_port:/dev/ttyACM0 --variable board:nrf52dk/nrf52832 -d /tmp/benchmark_out benchmark_256KB.robot -An example of execution using the ``nrf52dk_nrf52832`` board would generate a file like this: +An example of execution using the ``nrf52dk/nrf52832`` board would generate a file like this: .. code-block:: diff --git a/samples/subsys/zbus/benchmark/benchmark_256KB.robot b/samples/subsys/zbus/benchmark/benchmark_256KB.robot index db2ab59d6a4a54..810438f30983e0 100644 --- a/samples/subsys/zbus/benchmark/benchmark_256KB.robot +++ b/samples/subsys/zbus/benchmark/benchmark_256KB.robot @@ -9,7 +9,7 @@ Suite Teardown Terminate All Processes kill=True *** Variables *** ${csv_file} zbus_dyn_benchmark_256kb.csv -${board} hifive1_revb +${board} hifive1@B ${serial_port} /dev/ttyACM0 diff --git a/samples/subsys/zbus/dyn_channel/sample.yaml b/samples/subsys/zbus/dyn_channel/sample.yaml index 478516474f1856..3a2f9fb0c70b8a 100644 --- a/samples/subsys/zbus/dyn_channel/sample.yaml +++ b/samples/subsys/zbus/dyn_channel/sample.yaml @@ -68,4 +68,4 @@ tests: tags: zbus integration_platforms: - qemu_x86 - - mps2_an521 + - mps2/an521/cpu0 diff --git a/samples/subsys/zbus/remote_mock/boards/hifive1_revb.conf b/samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.conf similarity index 100% rename from samples/subsys/zbus/remote_mock/boards/hifive1_revb.conf rename to samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.conf diff --git a/samples/subsys/zbus/remote_mock/boards/hifive1_revb.overlay b/samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.overlay similarity index 100% rename from samples/subsys/zbus/remote_mock/boards/hifive1_revb.overlay rename to samples/subsys/zbus/remote_mock/boards/hifive1_fe310_B.overlay diff --git a/samples/subsys/zbus/remote_mock/sample.yaml b/samples/subsys/zbus/remote_mock/sample.yaml index 1b632901ed21d5..75898cc1644076 100644 --- a/samples/subsys/zbus/remote_mock/sample.yaml +++ b/samples/subsys/zbus/remote_mock/sample.yaml @@ -7,6 +7,6 @@ tests: platform_allow: - native_posix - native_sim - - hifive1_revb + - hifive1@B integration_platforms: - native_sim diff --git a/samples/subsys/zbus/uart_bridge/boards/hifive1_revb.conf b/samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.conf similarity index 100% rename from samples/subsys/zbus/uart_bridge/boards/hifive1_revb.conf rename to samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.conf diff --git a/samples/subsys/zbus/uart_bridge/boards/hifive1_revb.overlay b/samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.overlay similarity index 100% rename from samples/subsys/zbus/uart_bridge/boards/hifive1_revb.overlay rename to samples/subsys/zbus/uart_bridge/boards/hifive1_fe310_B.overlay diff --git a/samples/tfm_integration/psa_crypto/README.rst b/samples/tfm_integration/psa_crypto/README.rst index baef7287bb0957..2173cc356433ed 100644 --- a/samples/tfm_integration/psa_crypto/README.rst +++ b/samples/tfm_integration/psa_crypto/README.rst @@ -84,14 +84,14 @@ On MPS2+ AN521: =============== 1. Build Zephyr with a non-secure configuration - (``-DBOARD=mps2_an521_ns``). + (``-DBOARD=mps2/an521/cpu0/ns``). Using ``west`` .. code-block:: bash cd - west build -p -b mps2_an521_ns samples/tfm_integration/psa_crypto + west build -p -b mps2/an521/cpu0/ns samples/tfm_integration/psa_crypto Using ``cmake`` and ``ninja`` @@ -100,7 +100,7 @@ On MPS2+ AN521: cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=mps2_an521_ns .. + cmake -GNinja -DBOARD=mps2/an521/cpu0/ns .. ninja Using ``cmake`` and ``make`` @@ -110,7 +110,7 @@ On MPS2+ AN521: cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -DBOARD=mps2_an521_ns .. + cmake -DBOARD=mps2/an521/cpu0/ns .. make 2. Copy application binary files (mcuboot.bin and tfm_sign.bin) to @@ -137,7 +137,7 @@ On MPS2+ AN521: On QEMU: ======== -Build Zephyr with a non-secure configuration (``-DBOARD=mps2_an521_ns``) +Build Zephyr with a non-secure configuration (``-DBOARD=mps2/an521/cpu0/ns``) and run it in qemu via the ``run`` command. Using ``west`` @@ -145,7 +145,7 @@ and run it in qemu via the ``run`` command. .. code-block:: bash cd - west build -p -b mps2_an521_ns samples/tfm_integration/psa_crypto -t run + west build -p -b mps2/an521/cpu0/ns samples/tfm_integration/psa_crypto -t run Using ``cmake`` and ``ninja`` @@ -154,7 +154,7 @@ and run it in qemu via the ``run`` command. cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=mps2_an521_ns .. + cmake -GNinja -DBOARD=mps2/an521/cpu0/ns .. ninja run Using ``cmake`` and ``make`` @@ -164,7 +164,7 @@ and run it in qemu via the ``run`` command. cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -DBOARD=mps2_an521_ns .. + cmake -DBOARD=mps2/an521/cpu0/ns .. make run On LPCxpresso55S69: @@ -198,7 +198,7 @@ On nRF5340 and nRF9160: ======================= Build Zephyr with a non-secure configuration -(``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns`` or ``-DBOARD=nrf9160dk_nrf9160_ns``). +(``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns`` or ``-DBOARD=nrf9160dk/nrf9160/ns``). Example, for nRF9160, using ``cmake`` and ``ninja`` @@ -207,7 +207,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=nrf9160dk_nrf9160_ns .. + cmake -GNinja -DBOARD=nrf9160dk/nrf9160/ns .. If building with BL2 (MCUboot bootloader) enabled, manually flash the MCUboot bootloader image binary (``bl2.hex``). @@ -230,7 +230,7 @@ On BL5340: ========== Build Zephyr with a non-secure configuration -(``-DBOARD=bl5340_dvk_cpuapp_ns``). +(``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``). Example using ``cmake`` and ``ninja`` @@ -239,7 +239,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/psa_crypto/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=bl5340_dvk_cpuapp_ns .. + cmake -GNinja -DBOARD=bl5340_dvk/nrf5340/cpuapp/ns .. Flash the concatenated TF-M + Zephyr binary. diff --git a/samples/tfm_integration/psa_crypto/sample.yaml b/samples/tfm_integration/psa_crypto/sample.yaml index 45c9940b02165b..3f25acf88f33f8 100644 --- a/samples/tfm_integration/psa_crypto/sample.yaml +++ b/samples/tfm_integration/psa_crypto/sample.yaml @@ -11,9 +11,9 @@ tests: - crypto - csr - mcuboot - platform_allow: mps2_an521_ns v2m_musca_s1_ns - nrf5340dk_nrf5340_cpuapp_ns nrf9160dk_nrf9160_ns - stm32l562e_dk_ns bl5340_dvk_cpuapp_ns + platform_allow: mps2/an521/cpu0/ns v2m_musca_s1/musca_s1/ns + nrf5340dk/nrf5340/cpuapp/ns nrf9160dk/nrf9160/ns + stm32l562e_dk/stm32l562xx/ns bl5340_dvk/nrf5340/cpuapp/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/psa_protected_storage/README.rst b/samples/tfm_integration/psa_protected_storage/README.rst index 1600fde5f5382e..67c72440b1b9fa 100644 --- a/samples/tfm_integration/psa_protected_storage/README.rst +++ b/samples/tfm_integration/psa_protected_storage/README.rst @@ -46,7 +46,7 @@ Following is an example based on ``west build`` .. code-block:: bash - $ west build samples/tfm_integration/psa_protected_storage/ -p -b mps2_an521_ns -t run + $ west build samples/tfm_integration/psa_protected_storage/ -p -b mps2/an521/cpu0/ns -t run Sample Output ============= diff --git a/samples/tfm_integration/psa_protected_storage/sample.yaml b/samples/tfm_integration/psa_protected_storage/sample.yaml index 83ddde8675812a..4c3e2b277a918d 100644 --- a/samples/tfm_integration/psa_protected_storage/sample.yaml +++ b/samples/tfm_integration/psa_protected_storage/sample.yaml @@ -4,13 +4,13 @@ sample: common: tags: psa platform_allow: - - mps2_an521_ns - - v2m_musca_s1_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - bl5340_dvk_cpuapp_ns + - mps2/an521/cpu0/ns + - v2m_musca_s1/musca_s1/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - bl5340_dvk/nrf5340/cpuapp/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/tfm_ipc/README.rst b/samples/tfm_integration/tfm_ipc/README.rst index dc5233c7fc5efb..839f5f99523ff7 100644 --- a/samples/tfm_integration/tfm_ipc/README.rst +++ b/samples/tfm_integration/tfm_ipc/README.rst @@ -33,21 +33,21 @@ executed on MPS2+ AN521 and ST Nucleo L552ZE Q. On MPS2+ AN521: =============== -#. Build Zephyr with a non-secure configuration (``-DBOARD=mps2_an521_ns``). +#. Build Zephyr with a non-secure configuration (``-DBOARD=mps2/an521/cpu0/ns``). .. code-block:: bash cd $ZEPHYR_ROOT/samples/tfm_integration/tfm_ipc/ mkdir build cd build - cmake -DBOARD=mps2_an521_ns .. + cmake -DBOARD=mps2/an521/cpu0/ns .. make You can also use west as follows: .. code-block:: bash - $ west build -p -b mps2_an521_ns zephyr/samples/tfm_integration/tfm_ipc + $ west build -p -b mps2/an521/cpu0/ns zephyr/samples/tfm_integration/tfm_ipc #. Copy application binary files (mcuboot.bin and tfm_sign.bin) to ``/SOFTWARE/``. @@ -82,7 +82,7 @@ folder to update the ``-DGNUARM_PATH=/opt/toolchain/arm-none-eabi`` path. On QEMU: ======== -The MPS2+ AN521 target (``mps2_an521_ns``), which is based on a +The MPS2+ AN521 target (``mps2/an521/cpu0/ns``), which is based on a dual core ARM Cortex-M33 setup, also allows you to run TF-M tests using QEMU if you don't have access to a supported ARMv8-M development board. @@ -99,7 +99,7 @@ ninja or make, adding the ``run`` commands: .. code-block:: bash - $ west build -b mps2_an521_ns zephyr/samples/tfm_integration/tfm_ipc -t run + $ west build -b mps2/an521/cpu0/ns zephyr/samples/tfm_integration/tfm_ipc -t run Or, post build: @@ -118,7 +118,7 @@ Build Zephyr with a non-secure configuration: .. code-block:: bash - $ west build -b nucleo_l552ze_q_ns samples/tfm_integration/tfm_ipc/ + $ west build -b nucleo_l552ze_q/stm32l552xx/ns samples/tfm_integration/tfm_ipc/ Example, for building non-secure configuration for STM32L562E-DK Discovery @@ -171,7 +171,7 @@ On nRF5340 and nRF9160: ======================= Build Zephyr with a non-secure configuration -(``-DBOARD=nrf5340dk_nrf5340_cpuapp_ns`` or ``-DBOARD=nrf9160dk_nrf9160_ns``). +(``-DBOARD=nrf5340dk/nrf5340/cpuapp/ns`` or ``-DBOARD=nrf9160dk/nrf9160/ns``). Example, for nRF9160, using ``cmake`` and ``ninja`` @@ -180,7 +180,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/tfm_ipc/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=nrf9160dk_nrf9160_ns .. + cmake -GNinja -DBOARD=nrf9160dk/nrf9160/ns .. If building with BL2 (MCUboot bootloader) enabled, manually flash the MCUboot bootloader image binary (``bl2.hex``). @@ -203,7 +203,7 @@ On BL5340: ========== Build Zephyr with a non-secure configuration -(``-DBOARD=bl5340_dvk_cpuapp_ns``). +(``-DBOARD=bl5340_dvk/nrf5340/cpuapp/ns``). Example using ``cmake`` and ``ninja`` @@ -212,7 +212,7 @@ Build Zephyr with a non-secure configuration cd /samples/tfm_integration/tfm_ipc/ rm -rf build mkdir build && cd build - cmake -GNinja -DBOARD=bl5340_dvk_cpuapp_ns .. + cmake -GNinja -DBOARD=bl5340_dvk/nrf5340/cpuapp/ns .. Flash the concatenated TF-M + Zephyr binary. diff --git a/samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_ns.overlay b/samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_ns.overlay rename to samples/tfm_integration/tfm_ipc/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/samples/tfm_integration/tfm_ipc/sample.yaml b/samples/tfm_integration/tfm_ipc/sample.yaml index 4537b5c48dce29..0d141f4555ce05 100644 --- a/samples/tfm_integration/tfm_ipc/sample.yaml +++ b/samples/tfm_integration/tfm_ipc/sample.yaml @@ -9,16 +9,16 @@ tests: - trusted-firmware-m - mcuboot platform_allow: - - mps2_an521_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - nucleo_l552ze_q_ns - - stm32l562e_dk_ns - - v2m_musca_s1_ns - - bl5340_dvk_cpuapp_ns - - b_u585i_iot02a_ns + - mps2/an521/cpu0/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - nucleo_l552ze_q/stm32l552xx/ns + - stm32l562e_dk/stm32l562xx/ns + - v2m_musca_s1/musca_s1/ns + - bl5340_dvk/nrf5340/cpuapp/ns + - b_u585i_iot02a/stm32u585xx/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line @@ -31,7 +31,7 @@ tests: tags: - introduction - trusted-firmware-m - platform_allow: mps2_an521_ns + platform_allow: mps2/an521/cpu0/ns extra_configs: - CONFIG_TFM_BL2=n harness: console diff --git a/samples/tfm_integration/tfm_psa_test/README.rst b/samples/tfm_integration/tfm_psa_test/README.rst index 1060629baba1cb..73944b6ec656aa 100644 --- a/samples/tfm_integration/tfm_psa_test/README.rst +++ b/samples/tfm_integration/tfm_psa_test/README.rst @@ -32,7 +32,7 @@ You can indicate the desired test suite at build time via a config flag: .. code-block:: bash $ west build samples/tfm_integration/tfm_psa_test/ \ - -p -b mps2_an521_ns -t run -- \ + -p -b mps2/an521/cpu0/ns -t run -- \ -DCONFIG_TFM_PSA_TEST_STORAGE=y Note that not all test suites are valid on all boards. @@ -50,7 +50,7 @@ Following is an example based on ``west build`` .. code-block:: bash - $ west build samples/tfm_integration/tfm_psa_test/ -p -b mps2_an521_ns -t run -- -DCONFIG_TFM_PSA_TEST_STORAGE=y + $ west build samples/tfm_integration/tfm_psa_test/ -p -b mps2/an521/cpu0/ns -t run -- -DCONFIG_TFM_PSA_TEST_STORAGE=y Sample Output ============= diff --git a/samples/tfm_integration/tfm_psa_test/sample.yaml b/samples/tfm_integration/tfm_psa_test/sample.yaml index df8ae92a372f9c..d924e70461862f 100644 --- a/samples/tfm_integration/tfm_psa_test/sample.yaml +++ b/samples/tfm_integration/tfm_psa_test/sample.yaml @@ -3,16 +3,16 @@ common: - trusted-firmware-m - mcuboot platform_allow: - - mps2_an521_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - nrf9161dk_nrf9161_ns - - v2m_musca_s1_ns + - mps2/an521/cpu0/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - nrf9161dk/nrf9161/ns + - v2m_musca_s1/musca_s1/ns modules: - psa-arch-tests - tf-m-tests integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/tfm_regression_test/README.rst b/samples/tfm_integration/tfm_regression_test/README.rst index e5e634bb4bc619..2257414344f02b 100644 --- a/samples/tfm_integration/tfm_regression_test/README.rst +++ b/samples/tfm_integration/tfm_regression_test/README.rst @@ -34,7 +34,7 @@ Following is an example based on ``west build`` .. code-block:: bash - $ west build samples/tfm_integration/tfm_regression_test/ -p -b mps2_an521_ns -t run + $ west build samples/tfm_integration/tfm_regression_test/ -p -b mps2/an521/cpu0/ns -t run Sample Output ============= diff --git a/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_ns.overlay b/samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_ns.overlay rename to samples/tfm_integration/tfm_regression_test/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/samples/tfm_integration/tfm_regression_test/sample.yaml b/samples/tfm_integration/tfm_regression_test/sample.yaml index e5612d909c8e06..61af265e77b105 100644 --- a/samples/tfm_integration/tfm_regression_test/sample.yaml +++ b/samples/tfm_integration/tfm_regression_test/sample.yaml @@ -5,12 +5,12 @@ common: modules: - psa-arch-tests platform_allow: - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns - - nrf9161dk_nrf9161_ns - - v2m_musca_s1_ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns + - nrf9161dk/nrf9161/ns + - v2m_musca_s1/musca_s1/ns integration_platforms: - - nrf5340dk_nrf5340_cpuapp_ns + - nrf5340dk/nrf5340/cpuapp/ns harness: console harness_config: type: multi_line diff --git a/samples/tfm_integration/tfm_secure_partition/sample.yaml b/samples/tfm_integration/tfm_secure_partition/sample.yaml index 06cb3bc2e96057..7cd36b084758d9 100644 --- a/samples/tfm_integration/tfm_secure_partition/sample.yaml +++ b/samples/tfm_integration/tfm_secure_partition/sample.yaml @@ -2,12 +2,12 @@ common: tags: - trusted-firmware-m platform_allow: - - mps2_an521_ns - - v2m_musca_s1_ns - - nrf5340dk_nrf5340_cpuapp_ns - - nrf9160dk_nrf9160_ns + - mps2/an521/cpu0/ns + - v2m_musca_s1/musca_s1/ns + - nrf5340dk/nrf5340/cpuapp/ns + - nrf9160dk/nrf9160/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns harness: console harness_config: type: multi_line diff --git a/samples/userspace/hello_world_user/sample.yaml b/samples/userspace/hello_world_user/sample.yaml index b40042f71f5e6b..297ee8e906259e 100644 --- a/samples/userspace/hello_world_user/sample.yaml +++ b/samples/userspace/hello_world_user/sample.yaml @@ -4,7 +4,7 @@ sample: name: hello world user common: integration_platforms: - - mps2_an385 + - mps2/an385 tags: introduction harness: console harness_config: @@ -17,5 +17,5 @@ tests: arch_exclude: - posix platform_exclude: - - qemu_xtensa_mmu + - qemu_xtensa/dc233c/mmu tags: introduction diff --git a/samples/userspace/prod_consumer/sample.yaml b/samples/userspace/prod_consumer/sample.yaml index 232fdd31f063d6..f316d26ef4990f 100644 --- a/samples/userspace/prod_consumer/sample.yaml +++ b/samples/userspace/prod_consumer/sample.yaml @@ -3,7 +3,7 @@ sample: name: producer-consumer common: integration_platforms: - - mps2_an385 + - mps2/an385 tags: userspace harness: console harness_config: diff --git a/samples/userspace/shared_mem/README.rst b/samples/userspace/shared_mem/README.rst index 7ed6328e66f6df..7c9db36f243f2c 100644 --- a/samples/userspace/shared_mem/README.rst +++ b/samples/userspace/shared_mem/README.rst @@ -17,7 +17,7 @@ Requirements The sample is dependent on the subsystem app_memory, and it will not run on boards that do not support the subsystem. The sample -was tested on the following boards qemu_x86,frdm_k64, an 96b_carbon. +was tested on the following boards qemu_x86,frdm_k64, and ``96b_carbon/stm32f401xe``. Building and Running ******************** diff --git a/samples/userspace/shared_mem/sample.yaml b/samples/userspace/shared_mem/sample.yaml index 5b42ae2b7e3ece..e53d93490fd0f9 100644 --- a/samples/userspace/shared_mem/sample.yaml +++ b/samples/userspace/shared_mem/sample.yaml @@ -4,7 +4,7 @@ sample: name: protected memory common: integration_platforms: - - mps2_an385 + - mps2/an385 tags: userspace harness: console harness_config: diff --git a/samples/userspace/syscall_perf/sample.yaml b/samples/userspace/syscall_perf/sample.yaml index 8f27b925d643e4..69830fd89462e4 100644 --- a/samples/userspace/syscall_perf/sample.yaml +++ b/samples/userspace/syscall_perf/sample.yaml @@ -13,4 +13,4 @@ tests: filter: CONFIG_ARCH_HAS_USERSPACE arch_allow: riscv integration_platforms: - - hifive1_revb + - hifive1@B diff --git a/scripts/ci/Kconfig.board.v2 b/scripts/ci/Kconfig.board.v2 new file mode 100644 index 00000000000000..e1335cafe3938e --- /dev/null +++ b/scripts/ci/Kconfig.board.v2 @@ -0,0 +1,10 @@ +# Kconfig top-level ci for compliance testing Kconfig tree for boards / SoC v2 scheme. +# +# Copyright (c) 2022 Nordic Semiconductor ASA +# +# SPDX-License-Identifier: Apache-2.0 + +mainmenu "Zephyr board / SoC v2 Configuration" + +source "boards/Kconfig.v2" +source "soc/Kconfig.v2" diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py index 6985896d018143..dcad0ca51b93c9 100755 --- a/scripts/ci/check_compliance.py +++ b/scripts/ci/check_compliance.py @@ -29,6 +29,8 @@ sys.path.insert(0, str(Path(__file__).resolve().parents[1])) from get_maintainer import Maintainers, MaintainersError +import list_boards +import list_hardware logger = None @@ -226,6 +228,40 @@ def run(self): self.failure(output) +class BoardYmlCheck(ComplianceTest): + """ + Check the board.yml files + """ + name = "BoardYml" + doc = "Check the board.yml file format" + path_hint = "" + + def check_board_file(self, file, vendor_prefixes): + """Validate a single board file.""" + with open(file) as fp: + for line_num, line in enumerate(fp.readlines(), start=1): + if "vendor:" in line: + _, vnd = line.strip().split(":", 2) + vnd = vnd.strip() + if vnd not in vendor_prefixes: + desc = f"invalid vendor: {vnd}" + self.fmtd_failure("error", "BoardYml", file, line_num, + desc=desc) + + def run(self): + vendor_prefixes = ["others"] + with open(os.path.join(ZEPHYR_BASE, "dts", "bindings", "vendor-prefixes.txt")) as fp: + for line in fp.readlines(): + line = line.strip() + if not line or line.startswith("#"): + continue + vendor, _ = line.split("\t", 2) + vendor_prefixes.append(vendor) + + path = Path(ZEPHYR_BASE) + for file in path.glob("**/board.yml"): + self.check_board_file(file, vendor_prefixes) + class DevicetreeBindingsCheck(ComplianceTest): """ Checks if we are introducing any unwanted properties in Devicetree Bindings. @@ -273,16 +309,17 @@ class KconfigCheck(ComplianceTest): doc = "See https://docs.zephyrproject.org/latest/build/kconfig/tips.html for more details." path_hint = "" - def run(self, full=True, no_modules=False): + def run(self, full=True, no_modules=False, filename="Kconfig", hwm=None): self.no_modules = no_modules - kconf = self.parse_kconfig() + kconf = self.parse_kconfig(filename=filename, hwm=hwm) self.check_top_menu_not_too_long(kconf) self.check_no_pointless_menuconfigs(kconf) self.check_no_undef_within_kconfig(kconf) self.check_no_redefined_in_defconfig(kconf) self.check_no_enable_in_boolean_prompt(kconf) + self.check_soc_name_sync(kconf) if full: self.check_no_undef_outside_kconfig(kconf) @@ -360,8 +397,98 @@ def get_kconfig_dts(self, kconfig_dts_file, settings_file): except subprocess.CalledProcessError as ex: self.error(ex.output.decode("utf-8")) + def get_v1_model_syms(self, kconfig_v1_file, kconfig_v1_syms_file): + """ + Generate a symbol define Kconfig file. + This function creates a file with all Kconfig symbol definitions from + old boards model so that those symbols will not appear as undefined + symbols in hardware model v2. + + This is needed to complete Kconfig compliance tests. + """ + os.environ['HWM_SCHEME'] = 'v1' + # 'kconfiglib' is global + # pylint: disable=undefined-variable + + try: + kconf_v1 = kconfiglib.Kconfig(filename=kconfig_v1_file, warn=False) + except kconfiglib.KconfigError as e: + self.failure(str(e)) + raise EndTest + + with open(kconfig_v1_syms_file, 'w') as fp_kconfig_v1_syms_file: + for s in kconf_v1.defined_syms: + if s.type != kconfiglib.UNKNOWN: + fp_kconfig_v1_syms_file.write('config ' + s.name) + fp_kconfig_v1_syms_file.write('\n\t' + kconfiglib.TYPE_TO_STR[s.type]) + fp_kconfig_v1_syms_file.write('\n\n') + + def get_v2_model(self, kconfig_dir): + """ + Get lists of v2 boards and SoCs and put them in a file that is parsed by + Kconfig - def parse_kconfig(self): + This is needed to complete Kconfig sanity tests. + """ + os.environ['HWM_SCHEME'] = 'v2' + kconfig_file = os.path.join(kconfig_dir, 'boards', 'Kconfig') + kconfig_boards_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.boards') + kconfig_defconfig_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.defconfig') + + root_args = argparse.Namespace(**{'board_roots': [Path(ZEPHYR_BASE)], + 'soc_roots': [Path(ZEPHYR_BASE)], 'board': None}) + v2_boards = list_boards.find_v2_boards(root_args) + + with open(kconfig_defconfig_file, 'w') as fp: + for board in v2_boards: + fp.write('osource "' + os.path.join(board.dir, 'Kconfig.defconfig') + '"\n') + + with open(kconfig_boards_file, 'w') as fp: + for board in v2_boards: + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", board.name).upper() + fp.write('config ' + board_str + '\n') + fp.write('\t bool\n') + for identifier in list_boards.board_v2_identifiers(board): + board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", identifier).upper() + fp.write('config ' + board_str + '\n') + fp.write('\t bool\n') + fp.write('source "' + os.path.join(board.dir, 'Kconfig.') + board.name + '"\n\n') + + with open(kconfig_file, 'w') as fp: + fp.write('osource "' + os.path.join(kconfig_dir, 'boards', 'Kconfig.syms.v1') + '"\n') + for board in v2_boards: + fp.write('osource "' + os.path.join(board.dir, 'Kconfig') + '"\n') + + kconfig_defconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.defconfig') + kconfig_soc_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.soc') + kconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig') + + root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]}) + v2_systems = list_hardware.find_v2_systems(root_args) + + soc_folders = {soc.folder for soc in v2_systems.get_socs()} + with open(kconfig_defconfig_file, 'w') as fp: + for folder in soc_folders: + fp.write('osource "' + os.path.join(folder, 'Kconfig.defconfig') + '"\n') + + with open(kconfig_soc_file, 'w') as fp: + for folder in soc_folders: + fp.write('source "' + os.path.join(folder, 'Kconfig.soc') + '"\n') + + with open(kconfig_file, 'w') as fp: + for folder in soc_folders: + fp.write('source "' + os.path.join(folder, 'Kconfig') + '"\n') + + kconfig_file = os.path.join(kconfig_dir, 'arch', 'Kconfig') + + root_args = argparse.Namespace(**{'arch_roots': [Path(ZEPHYR_BASE)], 'arch': None}) + v2_archs = list_hardware.find_v2_archs(root_args) + + with open(kconfig_file, 'w') as fp: + for arch in v2_archs['archs']: + fp.write('source "' + os.path.join(arch['path'], 'Kconfig') + '"\n') + + def parse_kconfig(self, filename="Kconfig", hwm=None): """ Returns a kconfiglib.Kconfig object for the Kconfig files. We reuse this object for all tests to avoid having to reparse for each test. @@ -386,7 +513,7 @@ def parse_kconfig(self): # Parse the entire Kconfig tree, to make sure we see all symbols os.environ["SOC_DIR"] = "soc/" os.environ["ARCH_DIR"] = "arch/" - os.environ["BOARD_DIR"] = "boards/*/*" + os.environ["BOARD"] = "boards" os.environ["ARCH"] = "*" os.environ["KCONFIG_BINARY_DIR"] = kconfiglib_dir os.environ['DEVICETREE_CONF'] = "dummy" @@ -403,6 +530,15 @@ def parse_kconfig(self): self.get_kconfig_dts(os.path.join(kconfiglib_dir, "Kconfig.dts"), os.path.join(kconfiglib_dir, "settings_file.txt")) + # To make compliance work with old hw model and HWMv2 simultaneously. + kconfiglib_boards_dir = os.path.join(kconfiglib_dir, 'boards') + os.makedirs(kconfiglib_boards_dir, exist_ok=True) + os.makedirs(os.path.join(kconfiglib_dir, 'soc'), exist_ok=True) + os.makedirs(os.path.join(kconfiglib_dir, 'arch'), exist_ok=True) + + os.environ["BOARD_DIR"] = kconfiglib_boards_dir + self.get_v2_model(kconfiglib_dir) + # Tells Kconfiglib to generate warnings for all references to undefined # symbols within Kconfig files os.environ["KCONFIG_WARN_UNDEF"] = "y" @@ -412,7 +548,7 @@ def parse_kconfig(self): # them: so some warnings might get printed # twice. "warn_to_stderr=False" could unfortunately cause # some (other) warnings to never be printed. - return kconfiglib.Kconfig() + return kconfiglib.Kconfig(filename=filename) except kconfiglib.KconfigError as e: self.failure(str(e)) raise EndTest @@ -444,7 +580,6 @@ def get_defined_syms(self, kconf): return set([sym.name for sym in kconf_syms] + re.findall(regex, grep_stdout, re.MULTILINE)) - def check_top_menu_not_too_long(self, kconf): """ Checks that there aren't too many items in the top-level menu (which @@ -545,6 +680,34 @@ def check_no_undef_within_kconfig(self, kconf): if undef_ref_warnings: self.failure(f"Undefined Kconfig symbols:\n\n {undef_ref_warnings}") + def check_soc_name_sync(self, kconf): + root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]}) + v2_systems = list_hardware.find_v2_systems(root_args) + + soc_names = {soc.name for soc in v2_systems.get_socs()} + + soc_kconfig_names = set() + for node in kconf.node_iter(): + # 'kconfiglib' is global + # pylint: disable=undefined-variable + if isinstance(node.item, kconfiglib.Symbol) and node.item.name == "SOC": + n = node.item + for d in n.defaults: + soc_kconfig_names.add(d[0].name) + + soc_name_warnings = [] + for name in soc_names: + if name not in soc_kconfig_names: + soc_name_warnings.append(f"soc name: {name} not found in CONFIG_SOC defaults.") + + if soc_name_warnings: + soc_name_warning_str = '\n'.join(soc_name_warnings) + self.failure(f''' +Missing SoC names or CONFIG_SOC vs soc.yml out of sync: + +{soc_name_warning_str} +''') + def check_no_undef_outside_kconfig(self, kconf): """ Checks that there are no references to undefined Kconfig symbols @@ -639,6 +802,7 @@ def check_no_undef_outside_kconfig(self, kconf): # toolchain Kconfig which is sourced based on # Zephyr toolchain variant and therefore not # visible to compliance. + "BOARD_", # Used as regex in scripts/utils/board_v1_to_v2.py "BOOT_ENCRYPTION_KEY_FILE", # Used in sysbuild "BOOT_ENCRYPT_IMAGE", # Used in sysbuild "BINDESC_", # Used in documentation as a prefix @@ -718,6 +882,7 @@ def check_no_undef_outside_kconfig(self, kconf): "LOG_BACKEND_MOCK_OUTPUT_SYST", #Referenced in testcase.yaml of log_syst test "SEL", "SHIFT", + "SOC_SERIES_", # Used as regex in scripts/utils/board_v1_to_v2.py "SOC_WATCH", # Issue 13749 "SOME_BOOL", "SOME_INT", @@ -773,6 +938,23 @@ def run(self): super().run(full=False, no_modules=True) +class KconfigHWMv2Check(KconfigCheck, ComplianceTest): + """ + This runs the Kconfig test for board and SoC v2 scheme. + This check ensures that all symbols inside the v2 scheme is also defined + within the same tree. + This ensures the board and SoC trees are fully self-contained and reusable. + """ + name = "KconfigHWMv2" + doc = "See https://docs.zephyrproject.org/latest/guides/kconfig/index.html for more details." + + def run(self): + # Use dedicated Kconfig board / soc v2 scheme file. + # This file sources only v2 scheme tree. + kconfig_file = os.path.join(os.path.dirname(__file__), "Kconfig.board.v2") + super().run(full=False, hwm="v2", filename=kconfig_file) + + class Nits(ComplianceTest): """ Checks various nits in added/modified files. Doesn't check stuff that's @@ -1222,6 +1404,8 @@ def check_file(self, file, fp): start_marker = f"{self.MARKER}-start" stop_marker = f"{self.MARKER}-stop" + start_line = None + stop_line = None for line_num, line in enumerate(fp.readlines(), start=1): if start_marker in line: @@ -1231,15 +1415,18 @@ def check_file(self, file, fp): desc=desc) in_block = True block_data = "" + start_line = line_num + 1 elif stop_marker in line: if not in_block: desc = f"{stop_marker} without {start_marker}" self.fmtd_failure("error", "KeepSorted", file, line_num, desc=desc) in_block = False + stop_line = line_num - 1 if not self.block_is_sorted(block_data): - desc = f"sorted block is not sorted" + desc = (f"sorted block is not sorted, sort by running: " + + f"\"ex -s -c '{start_line},{stop_line} sort i|x' {file}\"") self.fmtd_failure("error", "KeepSorted", file, line_num, desc=desc) elif not line.strip() or line.startswith("#"): diff --git a/scripts/ci/test_plan.py b/scripts/ci/test_plan.py index 216cfe5b9bad1e..26787496a7cccc 100755 --- a/scripts/ci/test_plan.py +++ b/scripts/ci/test_plan.py @@ -226,7 +226,8 @@ def find_boards(self): roots.append(repository_path) # Look for boards in monitored repositories - lb_args = argparse.Namespace(**{ 'arch_roots': roots, 'board_roots': roots}) + lb_args = argparse.Namespace(**{'arch_roots': roots, 'board_roots': roots, 'board': None, + 'board_dir': None}) known_boards = list_boards.find_boards(lb_args) for b in boards: name_re = re.compile(b) diff --git a/scripts/footprint/plan.txt b/scripts/footprint/plan.txt index 948a430c62e60a..8e3f5b1b089405 100644 --- a/scripts/footprint/plan.txt +++ b/scripts/footprint/plan.txt @@ -2,8 +2,8 @@ footprints,default,frdm_k64f,tests/benchmarks/footprints, footprints,userspace,frdm_k64f,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf footprints,default,disco_l475_iot1,tests/benchmarks/footprints, footprints,userspace,disco_l475_iot1,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf -footprints,default,nrf5340dk_nrf5340_cpuapp,tests/benchmarks/footprints, -footprints,default,nrf51dk_nrf51422,tests/benchmarks/footprints, +footprints,default,nrf5340dk/nrf5340/cpuapp,tests/benchmarks/footprints, +footprints,default,nrf51dk/nrf51822,tests/benchmarks/footprints, footprints,default,altera_max10,tests/benchmarks/footprints, footprints,default,hifive1_revb,tests/benchmarks/footprints, footprints,default,intel_ehl_crb,tests/benchmarks/footprints, @@ -14,17 +14,17 @@ footprints,power-management,it8xxx2_evb,tests/benchmarks/footprints,-DCONF_FILE= footprints,power-management,iotdk,tests/benchmarks/footprints,-DCONF_FILE=prj_pm.conf echo_client,default,frdm_k64f,samples/net/sockets/echo_client, echo_server,default,frdm_k64f,samples/net/sockets/echo_server, -bt_beacon,default,nrf52840dk_nrf52840,samples/bluetooth/beacon, -bt_peripheral,default,nrf52840dk_nrf52840,samples/bluetooth/peripheral, -bt_central_hr,default,nrf52840dk_nrf52840,samples/bluetooth/central_hr, +bt_beacon,default,nrf52840dk/nrf52840,samples/bluetooth/beacon, +bt_peripheral,default,nrf52840dk/nrf52840,samples/bluetooth/peripheral, +bt_central_hr,default,nrf52840dk/nrf52840,samples/bluetooth/central_hr, bt_mesh_demo,default,bbc_microbit,samples/bluetooth/mesh_demo, -bt_hap_ha,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/hap_ha, -bt_unicast_audio_client,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/unicast_audio_client, -bt_unicast_audio_server,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/unicast_audio_server, -bt_tmap_central,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_central, -bt_tmap_peripheral,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_peripheral, -bt_tmap_bms,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_bms, -bt_tmap_bmr,default,nrf5340dk_nrf5340_cpuapp,samples/bluetooth/tmap_bmr, -bt_hci_ipc,default,nrf5340dk_nrf5340_cpunet,samples/bluetooth/hci_ipc, -bt_hci_ipc,iso-broadcast,nrf5340dk_nrf5340_cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf -bt_hci_ipc,iso-receive,nrf5340dk_nrf5340_cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf +bt_hap_ha,default,nrf5340dk/nrf5340_cpuapp,samples/bluetooth/hap_ha, +bt_unicast_audio_client,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/unicast_audio_client, +bt_unicast_audio_server,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/unicast_audio_server, +bt_tmap_central,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_central, +bt_tmap_peripheral,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_peripheral, +bt_tmap_bms,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_bms, +bt_tmap_bmr,default,nrf5340dk/nrf5340/cpuapp,samples/bluetooth/tmap_bmr, +bt_hci_ipc,default,nrf5340dk/nrf5340/cpunet,samples/bluetooth/hci_ipc, +bt_hci_ipc,iso-broadcast,nrf5340dk/nrf5340/cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf +bt_hci_ipc,iso-receive,nrf5340dk/nrf5340/cpunet,samples/bluetooth/hci_ipc,-DCONF_FILE=nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf diff --git a/scripts/kconfig/kconfigfunctions.py b/scripts/kconfig/kconfigfunctions.py index 71200b7f955acc..bb4b4dd519f179 100644 --- a/scripts/kconfig/kconfigfunctions.py +++ b/scripts/kconfig/kconfigfunctions.py @@ -6,6 +6,7 @@ import inspect import os import pickle +import re import sys from pathlib import Path @@ -840,6 +841,17 @@ def dt_gpio_hogs_enabled(kconf, _): return "n" + +def sanitize_upper(kconf, _, string): + """ + Sanitize the string, so that the string only contains alpha-numeric + characters or underscores. All non-alpha-numeric characters are replaced + with an underscore, '_'. + When string has been sanitized it will be converted into upper case. + """ + return re.sub(r'[^a-zA-Z0-9_]', '_', string).upper() + + def shields_list_contains(kconf, _, shield): """ Return "n" if cmake environment variable 'SHIELD_AS_LIST' doesn't exist. @@ -907,5 +919,6 @@ def shields_list_contains(kconf, _, shield): "dt_gpio_hogs_enabled": (dt_gpio_hogs_enabled, 0, 0), "dt_chosen_partition_addr_int": (dt_chosen_partition_addr, 1, 3), "dt_chosen_partition_addr_hex": (dt_chosen_partition_addr, 1, 3), + "sanitize_upper": (sanitize_upper, 1, 1), "shields_list_contains": (shields_list_contains, 1, 1), } diff --git a/scripts/list_boards.py b/scripts/list_boards.py index 4c7c87cad452e5..55fbe970d745d5 100755 --- a/scripts/list_boards.py +++ b/scripts/list_boards.py @@ -5,9 +5,20 @@ import argparse from collections import defaultdict +from dataclasses import dataclass, field import itertools from pathlib import Path -from typing import NamedTuple +import pykwalify.core +import sys +from typing import List +import yaml +import list_hardware + +BOARD_SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'board-schema.yml') +with open(BOARD_SCHEMA_PATH, 'r') as f: + board_schema = yaml.safe_load(f.read()) + +BOARD_YML = 'board.yml' # # This is shared code between the build system's 'boards' target @@ -18,10 +29,73 @@ # 'ninja boards' in a build directory without west installed.) # -class Board(NamedTuple): +@dataclass +class Revision: + name: str + variants: List[str] = field(default_factory=list) + + @staticmethod + def from_dict(revision): + revisions = [] + for r in revision.get('revisions', []): + revisions.append(Revision.from_dict(r)) + return Revision(revision['name'], revisions) + + + +@dataclass +class Variant: + name: str + variants: List[str] = field(default_factory=list) + + @staticmethod + def from_dict(variant): + variants = [] + for v in variant.get('variants', []): + variants.append(Variant.from_dict(v)) + return Variant(variant['name'], variants) + + +@dataclass +class Cpucluster: + name: str + variants: List[str] = field(default_factory=list) + + +@dataclass +class Soc: + name: str + cpuclusters: List[str] = field(default_factory=list) + variants: List[str] = field(default_factory=list) + + @staticmethod + def from_soc(soc, variants): + if soc is None: + return None + if soc.cpuclusters: + cpus = [] + for c in soc.cpuclusters: + cpus.append(Cpucluster(c, + [Variant.from_dict(v) for v in variants if c == v['cpucluster']] + )) + return Soc(soc.name, cpuclusters=cpus) + return Soc(soc.name, variants=[Variant.from_dict(v) for v in variants]) + + +@dataclass(frozen=True) +class Board: name: str - arch: str dir: Path + hwm: str + arch: str = None + vendor: str = None + revision_format: str = None + revision_default: str = None + revision_exact: bool = False + revisions: List[str] = field(default_factory=list, compare=False) + socs: List[Soc] = field(default_factory=list, compare=False) + variants: List[str] = field(default_factory=list, compare=False) + def board_key(board): return board.name @@ -40,8 +114,11 @@ def find_arch2board_set(args): ret = defaultdict(set) for root in args.board_roots: - for arch, boards in find_arch2board_set_in(root, arches).items(): - ret[arch] |= boards + for arch, boards in find_arch2board_set_in(root, arches, args.board_dir).items(): + if args.board is not None: + ret[arch] |= {b for b in boards if b.name == args.board} + else: + ret[arch] |= boards return ret @@ -68,30 +145,107 @@ def find_arches_in(root): return ret -def find_arch2board_set_in(root, arches): +def find_arch2board_set_in(root, arches, board_dir): ret = defaultdict(set) boards = root / 'boards' for arch in arches: - if not (boards / arch).is_dir(): + if not (boards / "boards_legacy" / arch).is_dir(): continue - for maybe_board in (boards / arch).iterdir(): + for maybe_board in (boards / "boards_legacy" / arch).iterdir(): if not maybe_board.is_dir(): continue + if board_dir is not None and board_dir != maybe_board: + continue for maybe_defconfig in maybe_board.iterdir(): file_name = maybe_defconfig.name if file_name.endswith('_defconfig'): board_name = file_name[:-len('_defconfig')] - ret[arch].add(Board(board_name, arch, maybe_board)) + ret[arch].add(Board(board_name, maybe_board, 'v1', arch=arch)) return ret + +def load_v2_boards(board_name, board_yml, systems): + boards = [] + if board_yml.is_file(): + with board_yml.open('r') as f: + b = yaml.safe_load(f.read()) + + try: + pykwalify.core.Core(source_data=b, schema_data=board_schema).validate() + except pykwalify.errors.SchemaError as e: + sys.exit('ERROR: Malformed "build" section in file: {}\n{}' + .format(board_yml.as_posix(), e)) + + mutual_exclusive = {'board', 'boards'} + if len(mutual_exclusive - b.keys()) < 1: + sys.exit(f'ERROR: Malformed content in file: {board_yml.as_posix()}\n' + f'{mutual_exclusive} are mutual exclusive at this level.') + + board_array = b.get('boards', [ b.get('board', None) ]) + for board in board_array: + if board_name is not None: + if board['name'] != board_name: + # Not the board we're looking for, ignore. + continue + + board_revision = board.get('revision') + if board_revision is not None and board_revision.get('format') != 'custom': + if board_revision.get('default') is None: + sys.exit(f'ERROR: Malformed "board" section in file: {board_yml.as_posix()}\n' + "Cannot find required key 'default'. Path: '/board/revision.'") + if board_revision.get('revisions') is None: + sys.exit(f'ERROR: Malformed "board" section in file: {board_yml.as_posix()}\n' + "Cannot find required key 'revisions'. Path: '/board/revision.'") + + mutual_exclusive = {'socs', 'variants'} + if len(mutual_exclusive - board.keys()) < 1: + sys.exit(f'ERROR: Malformed "board" section in file: {board_yml.as_posix()}\n' + f'{mutual_exclusive} are mutual exclusive at this level.') + socs = [Soc.from_soc(systems.get_soc(s['name']), s.get('variants', [])) + for s in board.get('socs', {})] + + board = Board( + name=board['name'], + dir=board_yml.parent, + vendor=board.get('vendor'), + revision_format=board.get('revision', {}).get('format'), + revision_default=board.get('revision', {}).get('default'), + revision_exact=board.get('revision', {}).get('exact', False), + revisions=[Revision.from_dict(v) for v in + board.get('revision', {}).get('revisions', [])], + socs=socs, + variants=[Variant.from_dict(v) for v in board.get('variants', [])], + hwm='v2', + ) + boards.append(board) + return boards + + +def find_v2_boards(args): + root_args = argparse.Namespace(**{'soc_roots': args.soc_roots}) + systems = list_hardware.find_v2_systems(root_args) + + boards = [] + board_files = [] + for root in args.board_roots: + board_files.extend((root / 'boards').rglob(BOARD_YML)) + + for board_yml in board_files: + b = load_v2_boards(args.board, board_yml, systems) + boards.extend(b) + return boards + + def parse_args(): parser = argparse.ArgumentParser(allow_abbrev=False) add_args(parser) + add_args_formatting(parser) return parser.parse_args() + def add_args(parser): # Remember to update west-completion.bash if you add or remove # flags @@ -101,12 +255,112 @@ def add_args(parser): parser.add_argument("--board-root", dest='board_roots', default=[], type=Path, action='append', help='add a board root, may be given more than once') + parser.add_argument("--soc-root", dest='soc_roots', default=[], + type=Path, action='append', + help='add a soc root, may be given more than once') + parser.add_argument("--board", dest='board', default=None, + help='lookup the specific board, fail if not found') + parser.add_argument("--board-dir", default=None, type=Path, + help='Only look for boards at the specific location') + + +def add_args_formatting(parser): + parser.add_argument("--cmakeformat", default=None, + help='''CMake Format string to use to list each board''') + -def dump_boards(arch2boards): +def variant_v2_identifiers(variant, identifier): + identifiers = [identifier + '/' + variant.name] + for v in variant.variants: + identifiers.extend(variant_v2_identifiers(v, identifier + '/' + variant.name)) + return identifiers + + +def board_v2_identifiers(board): + identifiers = [] + + for s in board.socs: + if s.cpuclusters: + for c in s.cpuclusters: + id_str = board.name + '/' + s.name + '/' + c.name + identifiers.append(id_str) + for v in c.variants: + identifiers.extend(variant_v2_identifiers(v, id_str)) + else: + id_str = board.name + '/' + s.name + identifiers.append(id_str) + for v in s.variants: + identifiers.extend(variant_v2_identifiers(v, id_str)) + + if not board.socs: + identifiers.append(board.name) + + for v in board.variants: + identifiers.extend(variant_v2_identifiers(v, board.name)) + return identifiers + + +def board_v2_identifiers_csv(board): + # Return in csv (comma separated value) format + return ",".join(board_v2_identifiers(board)) + + +def dump_v2_boards(args): + if args.board_dir: + root_args = argparse.Namespace(**{'soc_roots': args.soc_roots}) + systems = list_hardware.find_v2_systems(root_args) + boards = load_v2_boards(args.board, args.board_dir / BOARD_YML, systems) + else: + boards = find_v2_boards(args) + + for b in boards: + identifiers = board_v2_identifiers(b) + if args.cmakeformat is not None: + notfound = lambda x: x or 'NOTFOUND' + info = args.cmakeformat.format( + NAME='NAME;' + b.name, + DIR='DIR;' + str(b.dir.as_posix()), + VENDOR='VENDOR;' + notfound(b.vendor), + HWM='HWM;' + b.hwm, + REVISION_DEFAULT='REVISION_DEFAULT;' + notfound(b.revision_default), + REVISION_FORMAT='REVISION_FORMAT;' + notfound(b.revision_format), + REVISION_EXACT='REVISION_EXACT;' + str(b.revision_exact), + REVISIONS='REVISIONS;' + ';'.join( + [x.name for x in b.revisions]), + SOCS='SOCS;' + ';'.join([s.name for s in b.socs]), + IDENTIFIERS='IDENTIFIERS;' + ';'.join(identifiers) + ) + print(info) + else: + print(f'{b.name}') + + +def dump_boards(args): + arch2boards = find_arch2boards(args) for arch, boards in arch2boards.items(): - print(f'{arch}:') + if args.cmakeformat is None: + print(f'{arch}:') for board in boards: - print(f' {board.name}') + if args.cmakeformat is not None: + info = args.cmakeformat.format( + NAME='NAME;' + board.name, + DIR='DIR;' + str(board.dir.as_posix()), + HWM='HWM;' + board.hwm, + VENDOR='VENDOR;NOTFOUND', + REVISION_DEFAULT='REVISION_DEFAULT;NOTFOUND', + REVISION_FORMAT='REVISION_FORMAT;NOTFOUND', + REVISION_EXACT='REVISION_EXACT;NOTFOUND', + REVISIONS='REVISIONS;NOTFOUND', + VARIANT_DEFAULT='VARIANT_DEFAULT;NOTFOUND', + SOCS='SOCS;', + IDENTIFIERS='IDENTIFIERS;' + ) + print(info) + else: + print(f' {board.name}') + if __name__ == '__main__': - dump_boards(find_arch2boards(parse_args())) + args = parse_args() + dump_boards(args) + dump_v2_boards(args) diff --git a/scripts/list_hardware.py b/scripts/list_hardware.py new file mode 100755 index 00000000000000..d43cfb29c39302 --- /dev/null +++ b/scripts/list_hardware.py @@ -0,0 +1,283 @@ +#!/usr/bin/env python3 + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +import argparse +from dataclasses import dataclass +from pathlib import Path, PurePath +import pykwalify.core +import sys +from typing import List +import yaml + + +SOC_SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'soc-schema.yml') +with open(SOC_SCHEMA_PATH, 'r') as f: + soc_schema = yaml.safe_load(f.read()) + +ARCH_SCHEMA_PATH = str(Path(__file__).parent / 'schemas' / 'arch-schema.yml') +with open(ARCH_SCHEMA_PATH, 'r') as f: + arch_schema = yaml.safe_load(f.read()) + +SOC_YML = 'soc.yml' +ARCHS_YML_PATH = PurePath('arch/archs.yml') + +class Systems: + + def __init__(self, folder='', soc_yaml=None): + self._socs = [] + self._series = [] + self._families = [] + + if soc_yaml is None: + return + + try: + data = yaml.safe_load(soc_yaml) + pykwalify.core.Core(source_data=data, + schema_data=soc_schema).validate() + except (yaml.YAMLError, pykwalify.errors.SchemaError) as e: + sys.exit(f'ERROR: Malformed yaml {soc_yaml.as_posix()}', e) + + for f in data.get('family', []): + family = Family(f['name'], folder, [], []) + for s in f.get('series', []): + series = Series(s['name'], folder, f['name'], []) + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, s['name'], f['name'])) + for soc in s.get('socs', [])] + series.socs.extend(socs) + self._series.append(series) + self._socs.extend(socs) + family.series.append(series) + family.socs.extend(socs) + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, None, f['name'])) + for soc in f.get('socs', [])] + self._socs.extend(socs) + self._families.append(family) + + for s in data.get('series', []): + series = Series(s['name'], folder, '', []) + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, s['name'], '')) + for soc in s.get('socs', [])] + series.socs.extend(socs) + self._series.append(series) + self._socs.extend(socs) + + socs = [(Soc(soc['name'], + [c['name'] for c in soc.get('cpuclusters', [])], + folder, '', '')) + for soc in data.get('socs', [])] + self._socs.extend(socs) + + @staticmethod + def from_file(socs_file): + '''Load SoCs from a soc.yml file. + ''' + try: + with open(socs_file, 'r') as f: + socs_yaml = f.read() + except FileNotFoundError as e: + sys.exit(f'ERROR: socs.yml file not found: {socs_file.as_posix()}', e) + + return Systems(str(socs_file.parent), socs_yaml) + + @staticmethod + def from_yaml(socs_yaml): + '''Load socs from a string with YAML contents. + ''' + return Systems('', socs_yaml) + + def extend(self, systems): + self._families.extend(systems.get_families()) + self._series.extend(systems.get_series()) + self._socs.extend(systems.get_socs()) + + def get_families(self): + return self._families + + def get_series(self): + return self._series + + def get_socs(self): + return self._socs + + def get_soc(self, name): + try: + return next(s for s in self._socs if s.name == name) + except StopIteration: + sys.exit(f"ERROR: SoC '{name}' is not found, please ensure that the SoC exists " + f"and that soc-root containing '{name}' has been correctly defined.") + + +@dataclass +class Soc: + name: str + cpuclusters: List[str] + folder: str + series: str = '' + family: str = '' + + +@dataclass +class Series: + name: str + folder: str + family: str + socs: List[Soc] + + +@dataclass +class Family: + name: str + folder: str + series: List[Series] + socs: List[Soc] + + +def find_v2_archs(args): + ret = {'archs': []} + for root in args.arch_roots: + archs_yml = root / ARCHS_YML_PATH + + if Path(archs_yml).is_file(): + with Path(archs_yml).open('r') as f: + archs = yaml.safe_load(f.read()) + + try: + pykwalify.core.Core(source_data=archs, schema_data=arch_schema).validate() + except pykwalify.errors.SchemaError as e: + sys.exit('ERROR: Malformed "build" section in file: {}\n{}' + .format(archs_yml.as_posix(), e)) + + if args.arch is not None: + archs = {'archs': list(filter( + lambda arch: arch.get('name') == args.arch, archs['archs']))} + for arch in archs['archs']: + arch.update({'path': root / 'arch' / arch['path']}) + arch.update({'hwm': 'v2'}) + arch.update({'type': 'arch'}) + + ret['archs'].extend(archs['archs']) + + return ret + + +def find_v2_systems(args): + yml_files = [] + systems = Systems() + for root in args.soc_roots: + yml_files.extend((root / 'soc').rglob(SOC_YML)) + + for soc_yml in yml_files: + if soc_yml.is_file(): + systems.extend(Systems.from_file(soc_yml)) + + return systems + + +def parse_args(): + parser = argparse.ArgumentParser(allow_abbrev=False) + add_args(parser) + return parser.parse_args() + + +def add_args(parser): + default_fmt = '{name}' + + parser.add_argument("--soc-root", dest='soc_roots', default=[], + type=Path, action='append', + help='add a SoC root, may be given more than once') + parser.add_argument("--soc", default=None, help='lookup the specific soc') + parser.add_argument("--soc-series", default=None, help='lookup the specific soc series') + parser.add_argument("--soc-family", default=None, help='lookup the specific family') + parser.add_argument("--socs", action='store_true', help='lookup all socs') + parser.add_argument("--arch-root", dest='arch_roots', default=[], + type=Path, action='append', + help='add a arch root, may be given more than once') + parser.add_argument("--arch", default=None, help='lookup the specific arch') + parser.add_argument("--archs", action='store_true', help='lookup all archs') + parser.add_argument("--format", default=default_fmt, + help='''Format string to use to list each soc.''') + parser.add_argument("--cmakeformat", default=None, + help='''CMake format string to use to list each arch/soc.''') + + +def dump_v2_archs(args): + archs = find_v2_archs(args) + + for arch in archs['archs']: + if args.cmakeformat is not None: + info = args.cmakeformat.format( + TYPE='TYPE;' + arch['type'], + NAME='NAME;' + arch['name'], + DIR='DIR;' + str(arch['path'].as_posix()), + HWM='HWM;' + arch['hwm'], + # Below is non exising for arch but is defined here to support + # common formatting string. + SERIES='', + FAMILY='', + ARCH='', + VENDOR='' + ) + else: + info = args.format.format( + type=arch.get('type'), + name=arch.get('name'), + dir=arch.get('path'), + hwm=arch.get('hwm'), + # Below is non exising for arch but is defined here to support + # common formatting string. + series='', + family='', + arch='', + vendor='' + ) + + print(info) + + +def dump_v2_system(args, type, system): + if args.cmakeformat is not None: + info = args.cmakeformat.format( + TYPE='TYPE;' + type, + NAME='NAME;' + system.name, + DIR='DIR;' + Path(system.folder).as_posix(), + HWM='HWM;' + 'v2' + ) + else: + info = args.format.format( + type=type, + name=system.name, + dir=system.folder, + hwm='v2' + ) + + print(info) + + +def dump_v2_systems(args): + systems = find_v2_systems(args) + + for f in systems.get_families(): + dump_v2_system(args, 'family', f) + + for s in systems.get_series(): + dump_v2_system(args, 'series', s) + + for s in systems.get_socs(): + dump_v2_system(args, 'soc', s) + + +if __name__ == '__main__': + args = parse_args() + if any([args.socs, args.soc, args.soc_series, args.soc_family]): + dump_v2_systems(args) + if args.archs or args.arch is not None: + dump_v2_archs(args) diff --git a/scripts/pylib/pytest-twister-harness/README.rst b/scripts/pylib/pytest-twister-harness/README.rst index 860b7cd645de02..2c7baf4e89245e 100644 --- a/scripts/pylib/pytest-twister-harness/README.rst +++ b/scripts/pylib/pytest-twister-harness/README.rst @@ -24,7 +24,7 @@ Run exemplary test shell application by Twister: ./scripts/twister -p native_sim -p qemu_x86 -T samples/subsys/testsuite/pytest/shell # hardware - ./scripts/twister -p nrf52840dk_nrf52840 --device-testing --device-serial /dev/ttyACM0 -T samples/subsys/testsuite/pytest/shell + ./scripts/twister -p nrf52840dk/nrf52840 --device-testing --device-serial /dev/ttyACM0 -T samples/subsys/testsuite/pytest/shell or build shell application by west and call pytest directly: @@ -43,5 +43,5 @@ or build shell application by west and call pytest directly: pytest --twister-harness --device-type=qemu --build-dir=build -p twister_harness.plugin # hardware - west build -p -b nrf52840dk_nrf52840 + west build -p -b nrf52840dk/nrf52840 pytest --twister-harness --device-type=hardware --device-serial=/dev/ttyACM0 --build-dir=build -p twister_harness.plugin diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py index dbd3465aba19e9..0c5cf2ab839061 100644 --- a/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py +++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/plugin.py @@ -51,7 +51,7 @@ def pytest_addoption(parser: pytest.Parser): ) twister_harness_group.addoption( '--platform', - help='Name of used platform (qemu_x86, nrf52840dk_nrf52840, etc.).' + help='Name of used platform (qemu_x86, nrf52840dk/nrf52840, etc.).' ) twister_harness_group.addoption( '--device-serial', diff --git a/scripts/pylib/twister/boards/unit/unit_testing/board.yml b/scripts/pylib/twister/boards/unit/unit_testing/board.yml new file mode 100644 index 00000000000000..c3427dc0c65eb8 --- /dev/null +++ b/scripts/pylib/twister/boards/unit/unit_testing/board.yml @@ -0,0 +1,5 @@ +board: + name: unit_testing + vendor: zephyr + socs: + - name: unit_testing diff --git a/scripts/pylib/twister/soc/unit/unit_testing/soc.yml b/scripts/pylib/twister/soc/unit/unit_testing/soc.yml new file mode 100644 index 00000000000000..b965aa6a6f6a89 --- /dev/null +++ b/scripts/pylib/twister/soc/unit/unit_testing/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: unit_testing diff --git a/scripts/pylib/twister/twisterlib/platform.py b/scripts/pylib/twister/twisterlib/platform.py index d6123b2a5bec32..91c1df83428d2f 100644 --- a/scripts/pylib/twister/twisterlib/platform.py +++ b/scripts/pylib/twister/twisterlib/platform.py @@ -52,6 +52,7 @@ def load(self, platform_file): data = scp.data self.name = data['identifier'] + self.normalized_name = self.name.replace("/", "_") self.twister = data.get("twister", True) # if no RAM size is specified by the board, take a default of 128K self.ram = data.get("ram", 128) diff --git a/scripts/pylib/twister/twisterlib/reports.py b/scripts/pylib/twister/twisterlib/reports.py index 3d4b155fa9ddcd..001ee7d5092220 100644 --- a/scripts/pylib/twister/twisterlib/reports.py +++ b/scripts/pylib/twister/twisterlib/reports.py @@ -545,13 +545,13 @@ def save_reports(self, name, suffix, report_dir, no_update, platform_reports): def target_report(self, json_file, outdir, suffix): - platforms = {inst.platform.name for _, inst in self.instances.items()} + platforms = {inst.platform for _, inst in self.instances.items()} for platform in platforms: if suffix: - filename = os.path.join(outdir,"{}_{}.xml".format(platform, suffix)) - json_platform_file = os.path.join(outdir,"{}_{}.json".format(platform, suffix)) + filename = os.path.join(outdir,"{}_{}.xml".format(platform.normalized_name, suffix)) + json_platform_file = os.path.join(outdir,"{}_{}.json".format(platform.normalized_name, suffix)) else: - filename = os.path.join(outdir,"{}.xml".format(platform)) - json_platform_file = os.path.join(outdir,"{}.json".format(platform)) - self.xunit_report(json_file, filename, platform, full_report=True) - self.json_report(json_platform_file, version=self.env.version, platform=platform) + filename = os.path.join(outdir,"{}.xml".format(platform.normalized_name)) + json_platform_file = os.path.join(outdir,"{}.json".format(platform.normalized_name)) + self.xunit_report(json_file, filename, platform.name, full_report=True) + self.json_report(json_platform_file, version=self.env.version, platform=platform.name) diff --git a/scripts/pylib/twister/twisterlib/testinstance.py b/scripts/pylib/twister/twisterlib/testinstance.py index 3b307e41cf2867..e11f8eddfdbceb 100644 --- a/scripts/pylib/twister/twisterlib/testinstance.py +++ b/scripts/pylib/twister/twisterlib/testinstance.py @@ -56,13 +56,13 @@ def __init__(self, testsuite, platform, outdir): self.name = os.path.join(platform.name, testsuite.name) self.dut = None + if testsuite.detailed_test_id: - self.build_dir = os.path.join(outdir, platform.name, testsuite.name) + self.build_dir = os.path.join(outdir, platform.normalized_name, testsuite.name) else: # if suite is not in zephyr, keep only the part after ".." in reconstructed dir structure source_dir_rel = testsuite.source_dir_rel.rsplit(os.pardir+os.path.sep, 1)[-1] - self.build_dir = os.path.join(outdir, platform.name, source_dir_rel, testsuite.name) - + self.build_dir = os.path.join(outdir, platform.normalized_name, source_dir_rel, testsuite.name) self.run_id = self._get_run_id() self.domains = None diff --git a/scripts/pylib/twister/twisterlib/testplan.py b/scripts/pylib/twister/twisterlib/testplan.py index 782ceb0608cc37..5966e223180841 100755 --- a/scripts/pylib/twister/twisterlib/testplan.py +++ b/scripts/pylib/twister/twisterlib/testplan.py @@ -18,6 +18,7 @@ import random import snippets from pathlib import Path +from argparse import Namespace logger = logging.getLogger('twister') logger.setLevel(logging.DEBUG) @@ -34,7 +35,7 @@ from twisterlib.testinstance import TestInstance from twisterlib.quarantine import Quarantine - +import list_boards from zephyr_module import parse_modules ZEPHYR_BASE = os.getenv("ZEPHYR_BASE") @@ -398,13 +399,25 @@ def info(what): def add_configurations(self): - for board_root in self.env.board_roots: - board_root = os.path.abspath(board_root) - logger.debug("Reading platform configuration files under %s..." % - board_root) + board_dirs = set() + # Create a list of board roots as defined by the build system in general + # Note, internally in twister a board root includes the `boards` folder + # but in Zephyr build system, the board root is without the `boards` in folder path. + board_roots = [Path(os.path.dirname(root)) for root in self.env.board_roots] + lb_args = Namespace(arch_roots=[Path(ZEPHYR_BASE)], soc_roots=[Path(ZEPHYR_BASE), + Path(ZEPHYR_BASE) / 'scripts' / 'pylib' / 'twister'], + board_roots=board_roots, board=None, board_dir=None) + v1_boards = list_boards.find_boards(lb_args) + v2_boards = list_boards.find_v2_boards(lb_args) + for b in v1_boards: + board_dirs.add(b.dir) + for b in v2_boards: + board_dirs.add(b.dir) + logger.debug("Reading platform configuration files under %s..." % self.env.board_roots) - platform_config = self.test_config.get('platforms', {}) - for file in glob.glob(os.path.join(board_root, "*", "*", "*.yaml")): + platform_config = self.test_config.get('platforms', {}) + for folder in board_dirs: + for file in glob.glob(os.path.join(folder, "*.yaml")): try: platform = Platform() platform.load(file) @@ -447,6 +460,7 @@ def add_configurations(self): platform_revision = copy.deepcopy(platform) revision = revision.replace("_", ".") platform_revision.name = f"{platform.name}@{revision}" + platform_revision.normalized_name = platform_revision.name.replace("/", "_") platform_revision.default = False self.platforms.append(platform_revision) diff --git a/scripts/schemas/arch-schema.yml b/scripts/schemas/arch-schema.yml new file mode 100644 index 00000000000000..e1228ee1519522 --- /dev/null +++ b/scripts/schemas/arch-schema.yml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +## A pykwalify schema for basic validation of the structure of a +## arch metadata YAML file. +## +# The archs.yml file is a simple list of key value pairs containing architectures +# and their location which is used by the build system. +type: map +mapping: + archs: + required: true + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + desc: Name of the arch + path: + required: true + type: str + desc: Location of the arch implementation relative to the archs.yml file. + comment: + required: false + type: str + desc: Free form comment with extra information regarding the arch. diff --git a/scripts/schemas/board-schema.yml b/scripts/schemas/board-schema.yml new file mode 100644 index 00000000000000..6a9262bf8f5ec0 --- /dev/null +++ b/scripts/schemas/board-schema.yml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +## A pykwalify schema for basic validation of the structure of a +## board metadata YAML file. +## +# The board.yml file is a simple list of key value pairs containing board +# information like: name, vendor, socs, variants. +schema;variant-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + cpucluster: + required: false + type: str + variants: + required: false + include: variant-schema + +schema;board-schema: + type: map + mapping: + name: + required: true + type: str + desc: Name of the board + vendor: + required: false + type: str + desc: SoC family of the SoC on the board. + revision: + required: false + type: map + mapping: + format: + required: true + type: str + enum: + ["major.minor.patch", "letter", "number", "custom"] + default: + required: false # This field is required when 'format' != 'custom' + type: str + exact: + required: false + type: bool + revisions: + required: false # This field is required when 'format' != 'custom' + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + socs: + required: true + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + variants: + include: variant-schema + +type: map +mapping: + board: + include: board-schema + boards: + type: seq + sequence: + - include: board-schema diff --git a/scripts/schemas/soc-schema.yml b/scripts/schemas/soc-schema.yml new file mode 100644 index 00000000000000..dd62ee3c17dcca --- /dev/null +++ b/scripts/schemas/soc-schema.yml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023, Nordic Semiconductor ASA + +## A pykwalify schema for basic validation of the structure of a SoC +## metadata YAML file. +## +# The soc.yml file is a simple list of key value pairs containing SoCs +# located and the current structure level. +schema;cpucluster-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + +schema;soc-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + cpuclusters: + include: cpucluster-schema + +schema;series-schema: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + socs: + required: false + include: soc-schema + +type: map +mapping: + family: + required: false + type: seq + sequence: + - type: map + mapping: + name: + required: true + type: str + series: + include: series-schema + socs: + include: soc-schema + series: + include: series-schema + socs: + include: soc-schema + vendor: + required: false + type: str + desc: SoC series of the SoC. + This field is of informational use and can be used for filtering of SoCs. + comment: + required: false + type: str + desc: Free form comment with extra information regarding the SoC. diff --git a/scripts/snippets.py b/scripts/snippets.py index 78ab896e85bddb..48733ee3b55dde 100644 --- a/scripts/snippets.py +++ b/scripts/snippets.py @@ -159,11 +159,11 @@ def print_appends_for_board(self, board: str, appends: Appends): board_re = board[1:-1] self.print(f'''\ # Appends for board regular expression '{board_re}' -if("${{BOARD}}" MATCHES "^{board_re}$")''') +if("${{BOARD}}${{BOARD_IDENTIFIER}}" MATCHES "^{board_re}$")''') else: self.print(f'''\ # Appends for board '{board}' -if("${{BOARD}}" STREQUAL "{board}")''') +if("${{BOARD}}${{BOARD_IDENTIFIER}}" STREQUAL "{board}")''') self.print_appends(appends, 1) self.print('endif()') diff --git a/scripts/tests/twister_blackbox/test_report.py b/scripts/tests/twister_blackbox/test_report.py index 56d1bc3e098b16..5d120be727e3fb 100644 --- a/scripts/tests/twister_blackbox/test_report.py +++ b/scripts/tests/twister_blackbox/test_report.py @@ -26,9 +26,9 @@ class TestReport: TESTDATA_1 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], [ - 'qemu_x86_64.xml', 'qemu_x86.xml', + 'qemu_x86.xml', 'mps2_an385.xml', 'testplan.json', 'twister.json', 'twister.log', 'twister_report.xml', 'twister_suite_report.xml', 'twister.xml' @@ -38,9 +38,9 @@ class TestReport: TESTDATA_2 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], [ - 'qemu_x86_64_TEST.xml', 'qemu_x86_TEST.xml', + 'mps2_an385_TEST.xml', 'qemu_x86_TEST.xml', 'twister_TEST.json', 'twister_TEST_report.xml', 'twister_TEST_suite_report.xml', 'twister_TEST.xml' ] @@ -49,7 +49,7 @@ class TestReport: TESTDATA_3 = [ ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], ['--report-name', 'abcd'], [ 'abcd.json', 'abcd_report.xml', @@ -58,20 +58,20 @@ class TestReport: ), ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], ['--report-name', '1234', '--platform-reports'], [ - 'qemu_x86_64.xml', 'qemu_x86.xml', + 'mps2_an385.xml', 'qemu_x86.xml', '1234.json', '1234_report.xml', '1234_suite_report.xml', '1234.xml' ] ), ( os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic'), - ['qemu_x86', 'qemu_x86_64'], + ['qemu_x86', 'mps2/an385'], ['--report-name', 'Final', '--platform-reports', '--report-suffix=Test'], [ - 'qemu_x86_64_Test.xml', 'qemu_x86_Test.xml', + 'mps2_an385_Test.xml', 'qemu_x86_Test.xml', 'Final_Test.json', 'Final_Test_report.xml', 'Final_Test_suite_report.xml', 'Final_Test.xml' ] @@ -182,7 +182,7 @@ def test_platform_reports(self, capfd, out_path, test_path, test_platforms, file pytest.fail(f"Unsupported file type: '{path}'") for f_platform in test_platforms: - platform_path = os.path.join(out_path, f_platform) + platform_path = os.path.join(out_path, f_platform.replace("/", "_")) assert os.path.exists(platform_path), f'file not found {f_platform}' assert str(sys_exit.value) == '0' diff --git a/scripts/utils/board_v1_to_v2.py b/scripts/utils/board_v1_to_v2.py new file mode 100644 index 00000000000000..da84efb2ef9955 --- /dev/null +++ b/scripts/utils/board_v1_to_v2.py @@ -0,0 +1,215 @@ +#!/usr/bin/env python +""" +Utility script to assist in the migration of a board from hardware model v1 +(HWMv1) to hardware model v2 (HWMv2). + +.. warning:: + This script is not a complete migration tool. It is meant to assist in the + migration process, but it does not handle all cases. + +This script requires the following arguments: + +- ``-b|--board``: The name of the board to migrate. +- ``-g|--group``: The group the board belongs to. This is used to group a set of + boards in the same folder. In HWMv2, the boards are no longer organized by + architecture. +- ``-v|--vendor``: The vendor name. +- ``-s|--soc``: The SoC name. + +In some cases, the new board name will differ from the old board name. For +example, the old board name may have the SoC name as a suffix, while in HWMv2, +this is no longer needed. In such cases, ``-n|--new-board`` needs to be +provided. + +For boards with variants, ``--variants`` needs to be provided. + +For out-of-tree boards, provide ``--board-root`` pointing to the custom board +root. + +Copyright (c) 2023 Nordic Semiconductor ASA +SPDX-License-Identifier: Apache-2.0 +""" + +import argparse +from pathlib import Path +import re +import sys + +import ruamel.yaml + + +ZEPHYR_BASE = Path(__file__).parents[2] + + +def board_v1_to_v2(board_root, board, new_board, group, vendor, soc, variants): + try: + board_path = next(board_root.glob(f"boards/*/{board}")) + except StopIteration: + sys.exit(f"Board not found: {board}") + + new_board_path = board_root / "boards" / group / new_board + if new_board_path.exists(): + print("New board already exists, updating board with additional SoC") + if not soc: + sys.exit("No SoC provided") + + new_board_path.mkdir(parents=True, exist_ok=True) + + print("Moving files to the new board folder...") + for f in board_path.iterdir(): + f_new = new_board_path / f.name + if f_new.exists(): + print(f"Skipping existing file: {f_new}") + continue + f.rename(f_new) + + print("Creating or updating board.yaml...") + board_settings_file = new_board_path / "board.yml" + if not board_settings_file.exists(): + board_settings = { + "board": { + "name": new_board, + "vendor": vendor, + "socs": [] + } + } + else: + with open(board_settings_file) as f: + yaml = ruamel.yaml.YAML(typ='safe', pure=True) + board_settings = yaml.load(f) # pylint: disable=assignment-from-no-return + + soc = {"name": soc} + if variants: + soc["variants"] = [{"name": variant} for variant in variants] + + board_settings["board"]["socs"].append(soc) + + yaml = ruamel.yaml.YAML() + yaml.indent(sequence=4, offset=2) + with open(board_settings_file, "w") as f: + yaml.dump(board_settings, f) + + print(f"Updating {board}_defconfig...") + board_defconfig_file = new_board_path / f"{board}_defconfig" + with open(board_defconfig_file) as f: + board_soc_settings = [] + board_defconfig = "" + + dropped_line = False + for line in f.readlines(): + m = re.match(r"^CONFIG_BOARD_.*$", line) + if m: + dropped_line = True + continue + + m = re.match(r"^CONFIG_(SOC_[A-Z0-9_]+).*$", line) + if m: + dropped_line = True + if not re.match(r"^CONFIG_SOC_SERIES_.*$", line): + board_soc_settings.append(m.group(1)) + continue + + if dropped_line and re.match(r"^$", line): + continue + + dropped_line = False + board_defconfig += line + + with open(board_defconfig_file, "w") as f: + f.write(board_defconfig) + + print("Updating Kconfig.defconfig...") + board_kconfig_defconfig_file = new_board_path / "Kconfig.defconfig" + with open(board_kconfig_defconfig_file) as f: + board_kconfig_defconfig = "" + has_kconfig_defconfig_entries = False + + in_board = False + for line in f.readlines(): + # drop "config BOARD" entry from Kconfig.defconfig + m = re.match(r"^config BOARD$", line) + if m: + in_board = True + continue + + if in_board and re.match(r"^\s+.*$", line): + continue + + in_board = False + + m = re.match(r"^config .*$", line) + if m: + has_kconfig_defconfig_entries = True + + m = re.match(rf"^(.*)BOARD_{board.upper()}(.*)$", line) + if m: + board_kconfig_defconfig += ( + m.group(1) + "BOARD_" + new_board.upper() + m.group(2) + "\n" + ) + continue + + board_kconfig_defconfig += line + + if has_kconfig_defconfig_entries: + with open(board_kconfig_defconfig_file, "w") as f: + f.write(board_kconfig_defconfig) + else: + print("Removing empty Kconfig.defconfig after update...") + board_kconfig_defconfig_file.unlink() + + print(f"Creating or updating Kconfig.{new_board}...") + board_kconfig_file = new_board_path / "Kconfig.board" + copyright = None + with open(board_kconfig_file) as f: + for line in f.readlines(): + if "Copyright" in line: + copyright = line + new_board_kconfig_file = new_board_path / f"Kconfig.{new_board}" + header = "# SPDX-License-Identifier: Apache-2.0\n" + if copyright is not None: + header = copyright + header + selects = "\n\t" + "\n\t".join(["select " + setting for setting in board_soc_settings]) + "\n" + if not new_board_kconfig_file.exists(): + with open(new_board_kconfig_file, "w") as f: + f.write( + header + + f"\nconfig BOARD_{new_board.upper()}{selects}" + ) + else: + with open(new_board_kconfig_file, "a") as f: + f.write(selects) + + print("Removing old Kconfig.board...") + board_kconfig_file.unlink() + + print("Conversion done!") + + +if __name__ == "__main__": + parser = argparse.ArgumentParser(allow_abbrev=False) + + parser.add_argument( + "--board-root", + type=Path, + default=ZEPHYR_BASE, + help="Board root", + ) + + parser.add_argument("-b", "--board", type=str, required=True, help="Board name") + parser.add_argument("-n", "--new-board", type=str, help="New board name") + parser.add_argument("-g", "--group", type=str, required=True, help="Board group") + parser.add_argument("-v", "--vendor", type=str, required=True, help="Vendor name") + parser.add_argument("-s", "--soc", type=str, required=True, help="Board SoC") + parser.add_argument("--variants", nargs="+", default=[], help="Board variants") + + args = parser.parse_args() + + board_v1_to_v2( + args.board_root, + args.board, + args.new_board or args.board, + args.group, + args.vendor, + args.soc, + args.variants, + ) diff --git a/scripts/west_commands/boards.py b/scripts/west_commands/boards.py index 39238756f61215..d7fc2838bc276f 100644 --- a/scripts/west_commands/boards.py +++ b/scripts/west_commands/boards.py @@ -49,6 +49,7 @@ def do_add_parser(self, parser_adder): The following arguments are available: - name: board name + - identifiers: board identifiers - arch: board architecture - dir: directory that contains the board definition ''')) @@ -72,6 +73,7 @@ def do_run(self, args, _): name_re = None args.arch_roots = [ZEPHYR_BASE] + args.soc_roots = [ZEPHYR_BASE] modules_board_roots = [ZEPHYR_BASE] for module in zephyr_module.parse_modules(ZEPHYR_BASE, self.manifest): @@ -85,4 +87,10 @@ def do_run(self, args, _): if name_re is not None and not name_re.search(board.name): continue log.inf(args.format.format(name=board.name, arch=board.arch, - dir=board.dir)) + dir=board.dir, hwm=board.hwm, identifiers='')) + + for board in list_boards.find_v2_boards(args): + if name_re is not None and not name_re.search(board.name): + continue + log.inf(args.format.format(name=board.name, dir=board.dir, hwm=board.hwm, + identifiers=list_boards.board_v2_identifiers_csv(board))) diff --git a/scripts/west_commands/completion/west-completion.bash b/scripts/west_commands/completion/west-completion.bash index ca3f5669d05bcb..2ccc4446ad3af2 100644 --- a/scripts/west_commands/completion/west-completion.bash +++ b/scripts/west_commands/completion/west-completion.bash @@ -392,7 +392,8 @@ __set_comp_west_projs() __set_comp_west_boards() { - __set_comp "$(__west_x boards --format={name} "$@")" + boards="$(__west_x boards --format={identifiers} "$@")\n$(__west_x boards --format={name} "$@")" + __set_comp ${boards//,/\ } } __comp_west_west() @@ -660,6 +661,7 @@ __comp_west_boards() local dir_opts=" --arch-root --board-root + --soc-root " all_opts="$dir_opts $other_opts" diff --git a/scripts/west_commands/completion/west-completion.fish b/scripts/west_commands/completion/west-completion.fish index 92dbc65c800df7..33c6942dd8e107 100644 --- a/scripts/west_commands/completion/west-completion.fish +++ b/scripts/west_commands/completion/west-completion.fish @@ -196,11 +196,21 @@ function __zephyr_west_complete_help end function __zephyr_west_complete_board + # HWMv1 set -l boards (west 2>/dev/null boards --format="{name} {arch}") for board in $boards set -l b (string split " " $board) printf "%s\n" $b[1]\t"$b[2]" end + + # HWMv2 + set -l boards (west 2>/dev/null boards --format="{identifiers}") + for board in $boards + set -l b (string split "," $board) + for variant in $b + printf "%s\n" $variant[1] + end + end end # disable file completion, if an option need it, it should use '--force-files' @@ -292,6 +302,7 @@ complete -c west -n "__zephyr_west_seen_subcommand_from boards" -o f -l format - complete -c west -n "__zephyr_west_seen_subcommand_from boards" -o n -l name -d "name regex" complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l arch-root -xa "(__zephyr_west_complete_directories)" -d "add an arch root" complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l board-root -xa "(__zephyr_west_complete_directories)" -d "add a board root" +complete -c west -n "__zephyr_west_seen_subcommand_from boards" -l soc-root -xa "(__zephyr_west_complete_directories)" -d "add a soc root" # build complete -c west -n "__zephyr_west_use_subcommand; and __zephyr_west_check_if_in_workspace" -ra build -d "compile a Zephyr application" diff --git a/scripts/west_commands/completion/west-completion.zsh b/scripts/west_commands/completion/west-completion.zsh index b3a881288c0868..000b43a87b3121 100644 --- a/scripts/west_commands/completion/west-completion.zsh +++ b/scripts/west_commands/completion/west-completion.zsh @@ -102,7 +102,11 @@ _get_west_projs() { } _get_west_boards() { - _west_boards=($(__west_x boards --format={name})) + _west_boards="$(__west_x boards --format={identifiers})\n$(__west_x boards --format={name})" + _west_boards=${_west_boards//$'\n'/\ } + _west_boards=${_west_boards//,/\ } + _west_boards=(${(@s/ /)_west_boards}) + _describe 'boards' _west_boards } @@ -214,6 +218,7 @@ _west_boards() { {-n,--name}'[name regex]:regex:' '*--arch-root[Add an arch root]:arch root:_directories' '*--board-root[Add a board root]:board root:_directories' + '*--soc-root[Add a soc root]:soc root:_directories' ) _arguments -S $opts diff --git a/scripts/west_commands/runners/core.py b/scripts/west_commands/runners/core.py index 9b3ca51d90038b..21a60edc1a06fd 100644 --- a/scripts/west_commands/runners/core.py +++ b/scripts/west_commands/runners/core.py @@ -362,7 +362,7 @@ class ZephyrBinaryRunner(abc.ABC): This class provides an API for these commands. Every subclass is called a 'runner' for short. Each runner has a name (like 'pyocd'), and declares commands it can handle (like - 'flash'). Boards (like 'nrf52dk_nrf52832') declare which runner(s) + 'flash'). Boards (like 'nrf52dk/nrf52832') declare which runner(s) are compatible with them to the Zephyr build system, along with information on how to configure the runner to work with the board. diff --git a/scripts/west_commands/runners/intel_adsp.py b/scripts/west_commands/runners/intel_adsp.py index f7587331dc36cd..24552c8f61c3e8 100644 --- a/scripts/west_commands/runners/intel_adsp.py +++ b/scripts/west_commands/runners/intel_adsp.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2022-2024 Intel Corporation # # SPDX-License-Identifier: Apache-2.0 @@ -14,7 +14,7 @@ from runners.core import ZephyrBinaryRunner, RunnerCaps from zephyr_ext_common import ZEPHYR_BASE -DEFAULT_CAVSTOOL='soc/xtensa/intel_adsp/tools/cavstool_client.py' +DEFAULT_CAVSTOOL='soc/intel/intel_adsp/tools/cavstool_client.py' class SignParamError(argparse.Action): 'User-friendly feedback when trying to sign with west flash' @@ -78,7 +78,7 @@ def do_create(cls, cfg, args): def do_run(self, command, **kwargs): self.logger.info('Starting Intel ADSP runner') - if re.search("intel_adsp", self.platform): + if re.search("adsp", self.platform): self.require(self.cavstool) self.flash(**kwargs) else: diff --git a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake index 9de1ea0f47f333..05cde48a0e04c2 100644 --- a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake +++ b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake @@ -146,9 +146,9 @@ function(sysbuild_cache) endif() endforeach() if(DEFINED BOARD_REVISION) - list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}@${BOARD_REVISION}\n") + list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}@${BOARD_REVISION}${BOARD_IDENTIFIER}\n") else() - list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}\n") + list(APPEND sysbuild_cache_strings "BOARD:STRING=${BOARD}${BOARD_IDENTIFIER}\n") endif() list(APPEND sysbuild_cache_strings "SYSBUILD_NAME:STRING=${SB_CACHE_APPLICATION}\n") diff --git a/snippets/nordic-ppr/snippet.yml b/snippets/nordic-ppr/snippet.yml index 9e1f20bb75702f..ce8c3437c4c052 100644 --- a/snippets/nordic-ppr/snippet.yml +++ b/snippets/nordic-ppr/snippet.yml @@ -3,6 +3,6 @@ append: EXTRA_DTC_OVERLAY_FILE: nordic-ppr.overlay boards: - nrf54h20pdk_nrf54h20_cpuapp: + nrf54h20pdk/nrf54h20/cpuapp: append: EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20pdk_nrf54h20_cpuapp.overlay diff --git a/snippets/xen_dom0/boards/rcar_h3ulcb_ca57.overlay b/snippets/xen_dom0/boards/rcar_h3ulcb_r8a77951_a57.overlay similarity index 100% rename from snippets/xen_dom0/boards/rcar_h3ulcb_ca57.overlay rename to snippets/xen_dom0/boards/rcar_h3ulcb_r8a77951_a57.overlay diff --git a/snippets/xen_dom0/boards/rcar_salvator_xs_m3.overlay b/snippets/xen_dom0/boards/rcar_salvator_xs.overlay similarity index 100% rename from snippets/xen_dom0/boards/rcar_salvator_xs_m3.overlay rename to snippets/xen_dom0/boards/rcar_salvator_xs.overlay diff --git a/snippets/xen_dom0/snippet.yml b/snippets/xen_dom0/snippet.yml index cb6fddeaccdc5d..84d13bf77c1add 100644 --- a/snippets/xen_dom0/snippet.yml +++ b/snippets/xen_dom0/snippet.yml @@ -4,12 +4,12 @@ append: EXTRA_CONF_FILE: xen_dom0.conf boards: - qemu_cortex_a53: + qemu_cortex_a53/qemu_cortex_a53: append: EXTRA_DTC_OVERLAY_FILE: boards/qemu_cortex_a53.overlay - rcar_h3ulcb_ca57: + rcar_h3ulcb/r8a77951/a57: append: - EXTRA_DTC_OVERLAY_FILE: boards/rcar_h3ulcb_ca57.overlay - rcar_salvator_xs_m3: + EXTRA_DTC_OVERLAY_FILE: boards/rcar_h3ulcb_r8a77951_a57.overlay + rcar_salvator_xs/r8a77961: append: - EXTRA_DTC_OVERLAY_FILE: boards/rcar_salvator_xs_m3.overlay + EXTRA_DTC_OVERLAY_FILE: boards/rcar_salvator_xs.overlay diff --git a/soc/CMakeLists.txt b/soc/CMakeLists.txt index d55bd63f496d25..f9d754cfbb341c 100644 --- a/soc/CMakeLists.txt +++ b/soc/CMakeLists.txt @@ -11,8 +11,38 @@ unset(_SOC_IS_IN_TREE) add_subdirectory(common) -if(EXISTS ${SOC_DIR}/${ARCH}/CMakeLists.txt) - add_subdirectory(${SOC_DIR}/${ARCH} soc/${ARCH}) -else() - add_subdirectory(${SOC_DIR}/${ARCH}/${SOC_PATH} soc/${ARCH}/${SOC_PATH}) +if(HWMv1) + if(EXISTS ${SOC_DIR}/${ARCH}/CMakeLists.txt) + add_subdirectory(${SOC_DIR}/${ARCH} soc/${ARCH}) + else() + add_subdirectory(${SOC_DIR}/${ARCH}/${SOC_PATH} soc/${ARCH}/${SOC_PATH}) + endif() +elseif(HWMv2) + # Below is inclusion of HWMv2 SoC CMake lists. + string(TOUPPER SOC_FAMILY_${SOC_FAMILY}_DIR family_setting_dir) + string(TOUPPER SOC_SERIES_${SOC_SERIES}_DIR series_setting_dir) + string(TOUPPER SOC_${SOC_NAME}_DIR soc_setting_dir) + + if(DEFINED ${soc_setting_dir}) + add_subdirectory(${${soc_setting_dir}} soc/${SOC_NAME}) + elseif(DEFINED ${series_setting_dir}) + add_subdirectory(${${series_setting_dir}} soc/${SOC_SERIES}) + elseif(DEFINED ${family_setting_dir}) + add_subdirectory(${${family_setting_dir}} soc/${SOC_FAMILY}) + else() + message(FATAL_ERROR "No CMakeLists.txt file found for SoC: ${SOC_NAME}, " + "series: ${SOC_SERIES}, family: ${SOC_FAMILY}") + endif() + + # Include all SoC roots except Zephyr, as we are already in the Zephyr SoC root. + set(local_soc_root ${SOC_ROOT}) + list(REMOVE_ITEM local_soc_root ${ZEPHYR_BASE}) + foreach(root ${local_soc_root}) + cmake_path(GET root FILENAME name) + # A SoC root for HWMv1 may not contain a CMakeLists.txt file on this so + # let's check for existence before including. + if(EXISTS ${root}/soc/CMakeLists.txt) + add_subdirectory(${root}/soc soc/${name}) + endif() + endforeach() endif() diff --git a/soc/Kconfig b/soc/Kconfig index 33c2d0c29a4358..0063021c3e3c80 100644 --- a/soc/Kconfig +++ b/soc/Kconfig @@ -1,21 +1,22 @@ # SPDX-License-Identifier: Apache-2.0 -choice - prompt "SoC/CPU/Configuration Selection" +# Only v1 model has choice for SoC selection, therefore the optional source +# Sourced here and not in Kconfig.v1 to keep current SoC/CPU selection menu +# side-by-side with "Hardware Configuration" in the menu structure. +orsource "Kconfig.$(HWM_SCHEME).choice" -# This loads custom SoC root Kconfig (only available if custom SoC root are defined) -osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc" -# This loads Zephyr base SoC root Kconfig -osource "soc/$(ARCH)/*/Kconfig.soc" +menu "Hardware Configuration" -endchoice +rsource "Kconfig.$(HWM_SCHEME)" -menu "Hardware Configuration" -# This loads custom SoC root Kconfig (only available if custom SoC root are defined) -osource "$(KCONFIG_BINARY_DIR)/Kconfig.soc.arch" -# This loads Zephyr base SoC Kconfigs -osource "soc/$(ARCH)/Kconfig" -osource "soc/$(ARCH)/*/Kconfig" +# This loads Zephyr base SoC Kconfigs for both hw model v1 and v2 +osource "soc/soc_legacy/$(ARCH)/Kconfig" + +# Source Zephyr Kconfig specifics from SoC roots. +osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig" + +# Source common Kconfig file +osource "soc/common/Kconfig" module = SOC module-str = SOC @@ -44,10 +45,6 @@ config SOC_COMPATIBLE_NRF5340_CPUNET config SOC_COMPATIBLE_NRF5340_CPUAPP bool -# -# SOC_*_LD: SoC specific Linker script additions -# - config SOC_DEPRECATED_RELEASE string help diff --git a/soc/Kconfig.v1 b/soc/Kconfig.v1 new file mode 100644 index 00000000000000..f3762b8c6e2433 --- /dev/null +++ b/soc/Kconfig.v1 @@ -0,0 +1,27 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +config SOC + string + help + SoC name. The value of this setting must be defined by the selected + SoC for hw model v2. + +config SOC_SERIES + string + help + SoC series. The value of this setting must be defined by the selected + SoC if the SoC belongs to a common series. + +config SOC_FAMILY + string + help + SoC family. The value of this setting must be defined by the selected + SoC if the SoC belongs to a SoC family. Usually a SoC family also + indicates the vendor of the SoC. + +# This loads custom SoC root Kconfig (only available if custom SoC root are defined) +osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc.arch" +# This loads Zephyr base SoC Kconfigs +osource "soc/soc_legacy/$(ARCH)/*/Kconfig" diff --git a/soc/Kconfig.v1.choice b/soc/Kconfig.v1.choice new file mode 100644 index 00000000000000..f3424f71196e1d --- /dev/null +++ b/soc/Kconfig.v1.choice @@ -0,0 +1,13 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +choice + prompt "SoC/CPU/Configuration Selection" + +# This loads custom SoC root Kconfig (only available if custom SoC root are defined) +osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc.choice" +# This loads Zephyr base SoC scheme v1 root Kconfig +osource "soc/soc_legacy/$(ARCH)/*/Kconfig.soc" + +endchoice diff --git a/soc/Kconfig.v2 b/soc/Kconfig.v2 new file mode 100644 index 00000000000000..40008123a02880 --- /dev/null +++ b/soc/Kconfig.v2 @@ -0,0 +1,39 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +# Load all SoCs. +# SoCs that has transitioned to SoC scheme v2 are promptless, and thus +# unselectable by the user or through configuration files. +# +# SoC that are still using scheme v1 are still having a prompt but is loaded as +# they offer board maintainers the possibility to use board scheme v2. + +config SOC + string + help + SoC name. The value of this setting must be defined by the selected + SoC for hw model v2. + +config SOC_SERIES + string + help + SoC series. The value of this setting must be defined by the selected + SoC if the SoC belongs to a common series. + +config SOC_FAMILY + string + help + SoC family. The value of this setting must be defined by the selected + SoC if the SoC belongs to a SoC family. Usually a SoC family also + indicates the vendor of the SoC. + +config SOC_PART_NUMBER + string + help + This string holds the full part number of the SoC. It is a hidden option + that you should not set directly. The part number selection choice defines + the default value for this string. + +# Source all Kconfig HWMv2 from SoC roots. +source "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc" diff --git a/soc/altr/qemu_nios2/CMakeLists.txt b/soc/altr/qemu_nios2/CMakeLists.txt new file mode 100644 index 00000000000000..8afc2e701961a6 --- /dev/null +++ b/soc/altr/qemu_nios2/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/altr/qemu_nios2/Kconfig b/soc/altr/qemu_nios2/Kconfig new file mode 100644 index 00000000000000..3d64aa15b77954 --- /dev/null +++ b/soc/altr/qemu_nios2/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_NIOS2 + select NIOS2 + select HAS_MUL_INSTRUCTION + select HAS_DIV_INSTRUCTION + select HAS_MULX_INSTRUCTION diff --git a/soc/altr/qemu_nios2/Kconfig.defconfig b/soc/altr/qemu_nios2/Kconfig.defconfig new file mode 100644 index 00000000000000..7584fb7af4bc62 --- /dev/null +++ b/soc/altr/qemu_nios2/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_NIOS2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +endif diff --git a/soc/altr/qemu_nios2/Kconfig.soc b/soc/altr/qemu_nios2/Kconfig.soc new file mode 100644 index 00000000000000..1455b3ae7ac719 --- /dev/null +++ b/soc/altr/qemu_nios2/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_NIOS2 + bool + +config SOC + default "qemu_nios2" if SOC_QEMU_NIOS2 diff --git a/soc/nios2/nios2-qemu/include/layout.h b/soc/altr/qemu_nios2/include/layout.h similarity index 100% rename from soc/nios2/nios2-qemu/include/layout.h rename to soc/altr/qemu_nios2/include/layout.h diff --git a/soc/nios2/nios2-qemu/include/linker.h b/soc/altr/qemu_nios2/include/linker.h similarity index 100% rename from soc/nios2/nios2-qemu/include/linker.h rename to soc/altr/qemu_nios2/include/linker.h diff --git a/soc/nios2/nios2-qemu/include/system.h b/soc/altr/qemu_nios2/include/system.h similarity index 100% rename from soc/nios2/nios2-qemu/include/system.h rename to soc/altr/qemu_nios2/include/system.h diff --git a/soc/nios2/nios2-qemu/linker.ld b/soc/altr/qemu_nios2/linker.ld similarity index 100% rename from soc/nios2/nios2-qemu/linker.ld rename to soc/altr/qemu_nios2/linker.ld diff --git a/soc/nios2/nios2-qemu/soc.h b/soc/altr/qemu_nios2/soc.h similarity index 100% rename from soc/nios2/nios2-qemu/soc.h rename to soc/altr/qemu_nios2/soc.h diff --git a/soc/altr/qemu_nios2/soc.yml b/soc/altr/qemu_nios2/soc.yml new file mode 100644 index 00000000000000..414892bcc3f8fb --- /dev/null +++ b/soc/altr/qemu_nios2/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: qemu_nios2 diff --git a/soc/altr/zephyr_nios2f/CMakeLists.txt b/soc/altr/zephyr_nios2f/CMakeLists.txt new file mode 100644 index 00000000000000..3277239a967040 --- /dev/null +++ b/soc/altr/zephyr_nios2f/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/altr/zephyr_nios2f/Kconfig b/soc/altr/zephyr_nios2f/Kconfig new file mode 100644 index 00000000000000..6aa5654f7b50a7 --- /dev/null +++ b/soc/altr/zephyr_nios2f/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ZEPHYR_NIOS2F + select NIOS2 + select HAS_MUL_INSTRUCTION + select HAS_DIV_INSTRUCTION diff --git a/soc/altr/zephyr_nios2f/Kconfig.defconfig b/soc/altr/zephyr_nios2f/Kconfig.defconfig new file mode 100644 index 00000000000000..5f021107cac9f2 --- /dev/null +++ b/soc/altr/zephyr_nios2f/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ZEPHYR_NIOS2F + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +config ALTERA_AVALON_SYSID + def_bool y + +config ALTERA_AVALON_QSPI + def_bool y + depends on SOC_FLASH_NIOS2_QSPI + +config ALTERA_AVALON_I2C + def_bool y + depends on I2C_NIOS2 + +config ALTERA_AVALON_MSGDMA + def_bool y + depends on DMA_NIOS2_MSGDMA + +endif # SOC_ZEPHYR_NIOS2F diff --git a/soc/altr/zephyr_nios2f/Kconfig.soc b/soc/altr/zephyr_nios2f/Kconfig.soc new file mode 100644 index 00000000000000..b976d0b4795bb8 --- /dev/null +++ b/soc/altr/zephyr_nios2f/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2016 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ZEPHYR_NIOS2F + bool + +config SOC + default "zephyr_nios2f" if SOC_ZEPHYR_NIOS2F diff --git a/soc/nios2/nios2f-zephyr/cpu/README b/soc/altr/zephyr_nios2f/cpu/README similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/README rename to soc/altr/zephyr_nios2f/cpu/README diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qpf b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qpf rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qpf diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsf b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsf rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsf diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsys b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.qsys rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.qsys diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sof rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sof diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da.sopcinfo rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da.sopcinfo diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da_top.v b/soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_10m50da_top.v rename to soc/altr/zephyr_nios2f/cpu/ghrd_10m50da_top.v diff --git a/soc/nios2/nios2f-zephyr/cpu/ghrd_timing.sdc b/soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc similarity index 100% rename from soc/nios2/nios2f-zephyr/cpu/ghrd_timing.sdc rename to soc/altr/zephyr_nios2f/cpu/ghrd_timing.sdc diff --git a/soc/nios2/nios2f-zephyr/include/layout.h b/soc/altr/zephyr_nios2f/include/layout.h similarity index 100% rename from soc/nios2/nios2f-zephyr/include/layout.h rename to soc/altr/zephyr_nios2f/include/layout.h diff --git a/soc/nios2/nios2f-zephyr/include/linker.h b/soc/altr/zephyr_nios2f/include/linker.h similarity index 100% rename from soc/nios2/nios2f-zephyr/include/linker.h rename to soc/altr/zephyr_nios2f/include/linker.h diff --git a/soc/nios2/nios2f-zephyr/include/system.h b/soc/altr/zephyr_nios2f/include/system.h similarity index 100% rename from soc/nios2/nios2f-zephyr/include/system.h rename to soc/altr/zephyr_nios2f/include/system.h diff --git a/soc/nios2/nios2f-zephyr/linker.ld b/soc/altr/zephyr_nios2f/linker.ld similarity index 100% rename from soc/nios2/nios2f-zephyr/linker.ld rename to soc/altr/zephyr_nios2f/linker.ld diff --git a/soc/nios2/nios2f-zephyr/soc.h b/soc/altr/zephyr_nios2f/soc.h similarity index 100% rename from soc/nios2/nios2f-zephyr/soc.h rename to soc/altr/zephyr_nios2f/soc.h diff --git a/soc/altr/zephyr_nios2f/soc.yml b/soc/altr/zephyr_nios2f/soc.yml new file mode 100644 index 00000000000000..156e865a4cb588 --- /dev/null +++ b/soc/altr/zephyr_nios2f/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: zephyr_nios2f diff --git a/soc/arm/ambiq/CMakeLists.txt b/soc/ambiq/CMakeLists.txt similarity index 100% rename from soc/arm/ambiq/CMakeLists.txt rename to soc/ambiq/CMakeLists.txt diff --git a/soc/ambiq/Kconfig b/soc/ambiq/Kconfig new file mode 100644 index 00000000000000..ec2fa6129228ef --- /dev/null +++ b/soc/ambiq/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +if SOC_FAMILY_AMBIQ + +rsource "*/Kconfig" + +endif # SOC_FAMILY_AMBIQ diff --git a/soc/ambiq/Kconfig.defconfig b/soc/ambiq/Kconfig.defconfig new file mode 100644 index 00000000000000..2d0efbe54242ea --- /dev/null +++ b/soc/ambiq/Kconfig.defconfig @@ -0,0 +1,15 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +if SOC_FAMILY_AMBIQ + +rsource "*/Kconfig.defconfig" + +config CORTEX_M_SYSTICK + default n if AMBIQ_STIMER_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if AMBIQ_STIMER_TIMER + +endif # SOC_FAMILY_AMBIQ diff --git a/soc/ambiq/Kconfig.soc b/soc/ambiq/Kconfig.soc new file mode 100644 index 00000000000000..ba6d5302abb7b0 --- /dev/null +++ b/soc/ambiq/Kconfig.soc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +config SOC_FAMILY_AMBIQ + bool + +config SOC_FAMILY + default "ambiq" if SOC_FAMILY_AMBIQ + +rsource "*/Kconfig.soc" diff --git a/soc/ambiq/apollo4x/CMakeLists.txt b/soc/ambiq/apollo4x/CMakeLists.txt new file mode 100644 index 00000000000000..19f7fa032af3af --- /dev/null +++ b/soc/ambiq/apollo4x/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ambiq/apollo4x/Kconfig b/soc/ambiq/apollo4x/Kconfig new file mode 100644 index 00000000000000..a224512cd08dd0 --- /dev/null +++ b/soc/ambiq/apollo4x/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro +# Copyright (c) 2023 Ambiq Micro Inc. + +config SOC_SERIES_APOLLO4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_SWO + select AMBIQ_HAL diff --git a/soc/ambiq/apollo4x/Kconfig.defconfig b/soc/ambiq/apollo4x/Kconfig.defconfig new file mode 100644 index 00000000000000..182adf42cd541e --- /dev/null +++ b/soc/ambiq/apollo4x/Kconfig.defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro + +if SOC_SERIES_APOLLO4X + +rsource "Kconfig.defconfig.apollo4*" + +endif # SOC_SERIES_APOLLO4X diff --git a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p b/soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p similarity index 100% rename from soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p rename to soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p diff --git a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue b/soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue similarity index 100% rename from soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue rename to soc/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue diff --git a/soc/ambiq/apollo4x/Kconfig.soc b/soc/ambiq/apollo4x/Kconfig.soc new file mode 100644 index 00000000000000..fe06f28a7a85a5 --- /dev/null +++ b/soc/ambiq/apollo4x/Kconfig.soc @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2023 Antmicro +# Copyright (c) 2023 Ambiq Micro Inc. + +config SOC_SERIES_APOLLO4X + bool + select SOC_FAMILY_AMBIQ + help + Apollo4 Series MCU + +config SOC_APOLLO4P + bool + select SOC_SERIES_APOLLO4X + help + Apollo4P + +config SOC_APOLLO4P_BLUE + bool + select SOC_SERIES_APOLLO4X + help + Apollo4 Blue Plus + +config SOC_SERIES + default "apollo4x" if SOC_SERIES_APOLLO4X + +config SOC + default "apollo4p" if SOC_APOLLO4P + default "apollo4p_blue" if SOC_APOLLO4P_BLUE diff --git a/soc/arm/ambiq/apollo4x/pinctrl_soc.h b/soc/ambiq/apollo4x/pinctrl_soc.h similarity index 100% rename from soc/arm/ambiq/apollo4x/pinctrl_soc.h rename to soc/ambiq/apollo4x/pinctrl_soc.h diff --git a/soc/arm/ambiq/apollo4x/soc.c b/soc/ambiq/apollo4x/soc.c similarity index 100% rename from soc/arm/ambiq/apollo4x/soc.c rename to soc/ambiq/apollo4x/soc.c diff --git a/soc/arm/ambiq/apollo4x/soc.h b/soc/ambiq/apollo4x/soc.h similarity index 100% rename from soc/arm/ambiq/apollo4x/soc.h rename to soc/ambiq/apollo4x/soc.h diff --git a/soc/ambiq/soc.yml b/soc/ambiq/soc.yml new file mode 100644 index 00000000000000..2fd2f06529fe81 --- /dev/null +++ b/soc/ambiq/soc.yml @@ -0,0 +1,7 @@ +family: +- name: ambiq + series: + - name: apollo4x + socs: + - name: apollo4p + - name: apollo4p_blue diff --git a/soc/riscv/andes_v5/CMakeLists.txt b/soc/andestech/CMakeLists.txt similarity index 100% rename from soc/riscv/andes_v5/CMakeLists.txt rename to soc/andestech/CMakeLists.txt diff --git a/soc/andestech/Kconfig b/soc/andestech/Kconfig new file mode 100644 index 00000000000000..f050c5b55db2d7 --- /dev/null +++ b/soc/andestech/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ANDES_V5 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ANDES_V5 diff --git a/soc/andestech/Kconfig.defconfig b/soc/andestech/Kconfig.defconfig new file mode 100644 index 00000000000000..1560bc1c4fda15 --- /dev/null +++ b/soc/andestech/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ANDES_V5 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ANDES_V5 diff --git a/soc/andestech/Kconfig.soc b/soc/andestech/Kconfig.soc new file mode 100644 index 00000000000000..56bfb37f6338eb --- /dev/null +++ b/soc/andestech/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ANDES_V5 + bool + +config SOC_FAMILY + default "andes_v5" if SOC_FAMILY_ANDES_V5 + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/andes_v5/ae350/CMakeLists.txt b/soc/andestech/ae350/CMakeLists.txt similarity index 100% rename from soc/riscv/andes_v5/ae350/CMakeLists.txt rename to soc/andestech/ae350/CMakeLists.txt diff --git a/soc/andestech/ae350/Kconfig b/soc/andestech/ae350/Kconfig new file mode 100644 index 00000000000000..1a0a2443492b78 --- /dev/null +++ b/soc/andestech/ae350/Kconfig @@ -0,0 +1,122 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ANDES_AE350 + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_ANDES_AE350 + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select RISCV_PMP + +if SOC_SERIES_ANDES_AE350 + +choice +prompt "Base CPU ISA options" +default RV32I_CPU + +config RV32I_CPU + bool "RISCV32 CPU ISA" + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config RV32E_CPU + bool "RISCV32E CPU ISA" + select RISCV_ISA_RV32E + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config RV64I_CPU + bool "RISCV64 CPU ISA" + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select 64BIT + +endchoice + +choice +prompt "FPU options" +default NO_FPU + +config NO_FPU + bool "No FPU" + +config SINGLE_PRECISION_FPU + bool "Single precision FPU" + select CPU_HAS_FPU + +config DOUBLE_PRECISION_FPU + bool "Double precision FPU" + select CPU_HAS_FPU_DOUBLE_PRECISION + +endchoice + +config SOC_ANDES_V5_HWDSP + bool "AndeStar V5 DSP ISA" + select RISCV_SOC_CONTEXT_SAVE + depends on !RISCV_GENERIC_TOOLCHAIN + help + This option enables the AndeStar v5 hardware DSP, in order to + support using the DSP instructions. + +config SOC_ANDES_V5_PFT + bool "Andes V5 PowerBrake extension" + default y + select RISCV_SOC_CONTEXT_SAVE + help + The PowerBrake extension throttles performance by reducing instruction + executing rate. + +config SOC_ANDES_V5_EXECIT + bool "Andes V5 EXEC.IT extension" + depends on RISCV_ISA_EXT_C + depends on !RISCV_GENERIC_TOOLCHAIN + depends on !LINKER_USE_NO_RELAX + help + The EXEC.IT extension (Execution on Instruction Table) generate + a look-up table and replaces suitable 32-bit instructions with + the 16-bit "exec.it ". + +config SOC_ANDES_V5_PMA + bool "Andes V5 Physical Memory Attribute (PMA)" + select ARCH_HAS_NOCACHE_MEMORY_SUPPORT + help + This option enables the Andes V5 PMA, in order to support SW to + configure physical memory attribute by PMA CSRs. The address + matching of Andes V5 PMA is like RISC-V PMP NAPOT mode + (power-of-two alignment). + +config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE + int + depends on SOC_ANDES_V5_PMA + default 4096 + help + Minimum size (and alignment) of an PMA region. Use this symbol + to guarantee minimum size and alignment of PMA regions. + +# Workaround for not being able to have commas in macro arguments +DT_ANDESTECH_L2C := andestech,l2c + +config SOC_ANDES_V5_L2C + bool + default $(dt_compat_enabled,$(DT_ANDESTECH_L2C)) + +config SOC_ANDES_V5_IOCP + bool "Andes V5 I/O Coherence Port (IOCP)" + depends on SOC_ANDES_V5_L2C + depends on DCACHE + help + Support Andes V5 I/O Coherence Port to handle cache coherency + between cache and external non-caching master, such as DMA + controller. + +endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/andestech/ae350/Kconfig.defconfig b/soc/andestech/ae350/Kconfig.defconfig new file mode 100644 index 00000000000000..ba36eddc354675 --- /dev/null +++ b/soc/andestech/ae350/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ANDES_AE350 + +# Kconfig picks the first default with a satisfied condition. +# SoC defaults should be parsed before SoC Series defaults, because SoCs usually +# overrides SoC Series values. +rsource "Kconfig.defconfig.ae*" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 60000000 + +config KERNEL_ENTRY + default "entry" + +config RISCV_GENERIC_TOOLCHAIN + default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" + default n + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae350 b/soc/andestech/ae350/Kconfig.defconfig.ae350 similarity index 93% rename from soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae350 rename to soc/andestech/ae350/Kconfig.defconfig.ae350 index fee73684b7150c..ba661c96e63715 100644 --- a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae350 +++ b/soc/andestech/ae350/Kconfig.defconfig.ae350 @@ -3,9 +3,6 @@ if SOC_ANDES_AE350 -config SOC - default "ae350" - config SYS_CLOCK_TICKS_PER_SEC default 100 if (!ICACHE || XIP) diff --git a/soc/andestech/ae350/Kconfig.soc b/soc/andestech/ae350/Kconfig.soc new file mode 100644 index 00000000000000..be7310adcc233c --- /dev/null +++ b/soc/andestech/ae350/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021 Andes Technology Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ANDES_AE350 + bool + select SOC_FAMILY_ANDES_V5 + help + Andes V5 AE350 SoC Series Implementation" + +config SOC_ANDES_AE350 + bool + select SOC_SERIES_ANDES_AE350 + help + Andes AE350 SoC implementation" + +config SOC_SERIES + default "ae350" if SOC_SERIES_ANDES_AE350 + +config SOC + default "ae350" if SOC_ANDES_AE350 diff --git a/soc/riscv/andes_v5/ae350/common_linker/execit.ld b/soc/andestech/ae350/common_linker/execit.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/common_linker/execit.ld rename to soc/andestech/ae350/common_linker/execit.ld diff --git a/soc/riscv/andes_v5/ae350/common_linker/init.ld b/soc/andestech/ae350/common_linker/init.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/common_linker/init.ld rename to soc/andestech/ae350/common_linker/init.ld diff --git a/soc/riscv/andes_v5/ae350/common_linker/ram_start_nonzero.ld b/soc/andestech/ae350/common_linker/ram_start_nonzero.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/common_linker/ram_start_nonzero.ld rename to soc/andestech/ae350/common_linker/ram_start_nonzero.ld diff --git a/soc/riscv/andes_v5/ae350/l2_cache.c b/soc/andestech/ae350/l2_cache.c similarity index 100% rename from soc/riscv/andes_v5/ae350/l2_cache.c rename to soc/andestech/ae350/l2_cache.c diff --git a/soc/riscv/andes_v5/ae350/linker.ld b/soc/andestech/ae350/linker.ld similarity index 100% rename from soc/riscv/andes_v5/ae350/linker.ld rename to soc/andestech/ae350/linker.ld diff --git a/soc/riscv/andes_v5/ae350/pma.c b/soc/andestech/ae350/pma.c similarity index 100% rename from soc/riscv/andes_v5/ae350/pma.c rename to soc/andestech/ae350/pma.c diff --git a/soc/riscv/andes_v5/ae350/soc_context.h b/soc/andestech/ae350/soc_context.h similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_context.h rename to soc/andestech/ae350/soc_context.h diff --git a/soc/riscv/andes_v5/ae350/soc_irq.S b/soc/andestech/ae350/soc_irq.S similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_irq.S rename to soc/andestech/ae350/soc_irq.S diff --git a/soc/riscv/andes_v5/ae350/soc_offsets.h b/soc/andestech/ae350/soc_offsets.h similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_offsets.h rename to soc/andestech/ae350/soc_offsets.h diff --git a/soc/riscv/andes_v5/ae350/soc_v5.h b/soc/andestech/ae350/soc_v5.h similarity index 100% rename from soc/riscv/andes_v5/ae350/soc_v5.h rename to soc/andestech/ae350/soc_v5.h diff --git a/soc/riscv/andes_v5/ae350/start.S b/soc/andestech/ae350/start.S similarity index 100% rename from soc/riscv/andes_v5/ae350/start.S rename to soc/andestech/ae350/start.S diff --git a/soc/andestech/soc.yml b/soc/andestech/soc.yml new file mode 100644 index 00000000000000..be842155259efe --- /dev/null +++ b/soc/andestech/soc.yml @@ -0,0 +1,6 @@ +family: +- name: andes_v5 + series: + - name: ae350 + socs: + - name: ae350 diff --git a/soc/arc/snps_arc_hsdk/Kconfig.defconfig b/soc/arc/snps_arc_hsdk/Kconfig.defconfig deleted file mode 100644 index 44791dc680a247..00000000000000 --- a/soc/arc/snps_arc_hsdk/Kconfig.defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_HSDK - -config SOC - default "snps_arc_hsdk" - -config CPU_HS3X - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 2 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). - default 2 - -config NUM_IRQS - # must be > the highest interrupt number used - default 88 - -config RGF_NUM_BANKS - default 2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 500000000 - -config ARC_FIRQ - default y - -config CODE_DENSITY - default y - -config ARCV2_TIMER_IRQ_PRIORITY - default 1 - -config ARC_CONNECT - default y - -config MP_MAX_NUM_CPUS - default 4 - -config UART_NS16550_ACCESS_WORD_ONLY - default y - depends on UART_NS16550 - -config ARC_HAS_ACCL_REGS - default y - -endif # ARC_HSDK diff --git a/soc/arc/snps_arc_hsdk/Kconfig.soc b/soc/arc/snps_arc_hsdk/Kconfig.soc deleted file mode 100644 index 93791fdb088a2a..00000000000000 --- a/soc/arc/snps_arc_hsdk/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_HSDK - bool "Synopsys ARC HSDK SoC" - select ARC - select CPU_HAS_FPU diff --git a/soc/arc/snps_arc_hsdk4xd/CMakeLists.txt b/soc/arc/snps_arc_hsdk4xd/CMakeLists.txt deleted file mode 100644 index 0c13259ca2b7f2..00000000000000 --- a/soc/arc/snps_arc_hsdk4xd/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(COMPILER STREQUAL gcc) - # GNU compiler options - zephyr_compile_options(-mno-sdata) - zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all) -else() - # MWDT compiler options - zephyr_compile_options(-arcv2hs -core4 -Xdual_issue -Xcode_density -Hrgf_banked_regs=32 -HL - -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist - -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -Hld_cycles=2) - - zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div) - - zephyr_ld_options(-Hlib=hs48_slc_full) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_arc_hsdk4xd/Kconfig.defconfig b/soc/arc/snps_arc_hsdk4xd/Kconfig.defconfig deleted file mode 100644 index 1b70bce3721de7..00000000000000 --- a/soc/arc/snps_arc_hsdk4xd/Kconfig.defconfig +++ /dev/null @@ -1,56 +0,0 @@ -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_HSDK4XD - -config SOC - default "snps_arc_hsdk4xd" - -config CPU_HS4X - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 2 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). - default 2 - -config NUM_IRQS - # must be > the highest interrupt number used - default 88 - -config RGF_NUM_BANKS - # Actually cpu has 4 banks but zephys currently supports up to 2 - default 2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 500000000 - -config ARC_FIRQ - default y - -config CODE_DENSITY - default y - -config ARCV2_TIMER_IRQ_PRIORITY - default 1 - -config ARC_CONNECT - default y - -config MP_MAX_NUM_CPUS - default 4 - -config UART_NS16550_ACCESS_WORD_ONLY - default y - depends on UART_NS16550 - -config ARC_HAS_ACCL_REGS - default y - -config ARC_EARLY_SOC_INIT - default y - -config ARC_HAS_STACK_CHECKING - default n - -endif # SOC_ARC_HS4XD diff --git a/soc/arc/snps_arc_hsdk4xd/Kconfig.soc b/soc/arc/snps_arc_hsdk4xd/Kconfig.soc deleted file mode 100644 index 6354c659d30bfd..00000000000000 --- a/soc/arc/snps_arc_hsdk4xd/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_HSDK4XD - bool "Synopsys ARC HSDK4XD SoC" - select ARC - select CPU_HAS_FPU - select CPU_HAS_DSP diff --git a/soc/arc/snps_arc_iot/Kconfig.defconfig b/soc/arc/snps_arc_iot/Kconfig.defconfig deleted file mode 100644 index 202697a7cf9e2c..00000000000000 --- a/soc/arc/snps_arc_iot/Kconfig.defconfig +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_IOT - -config SOC - default "snps_arc_iot" - -config CPU_EM4_FPUS - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 4 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). - default 4 - -config ARC_MPU_VER - default 2 - -config NUM_IRQS - # must be > the highest interrupt number used - default 95 - -config RGF_NUM_BANKS - default 2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 144000000 - -config HARVARD - default y - -config ARC_FIRQ - default y - -endif # ARC_IOT diff --git a/soc/arc/snps_arc_iot/Kconfig.soc b/soc/arc/snps_arc_iot/Kconfig.soc deleted file mode 100644 index f9793b27354589..00000000000000 --- a/soc/arc/snps_arc_iot/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_IOT - bool "Synopsys ARC IoT SoC" - select ARC - select CPU_HAS_MPU - select CPU_HAS_FPU diff --git a/soc/arc/snps_emsdp/CMakeLists.txt b/soc/arc/snps_emsdp/CMakeLists.txt deleted file mode 100644 index 04466b802c0292..00000000000000 --- a/soc/arc/snps_emsdp/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata) - -if(CONFIG_SOC_EMSDP_EM4) - zephyr_compile_options(-mmpy-option=3 -mno-div-rem) -elseif(CONFIG_SOC_EMSDP_EM6) - zephyr_compile_options(-mmpy-option=3 -mno-div-rem) -elseif(CONFIG_SOC_EMSDP_EM5D) - zephyr_compile_options(-mmpy-option=6) -elseif(CONFIG_SOC_EMSDP_EM7D) - zephyr_compile_options(-mmpy-option=6) -elseif(CONFIG_SOC_EMSDP_EM7D_ESP) - zephyr_compile_options(-mmpy-option=6) -elseif(CONFIG_SOC_EMSDP_EM9D) - zephyr_compile_options(-mmpy-option=6) - zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) -elseif(CONFIG_SOC_EMSDP_EM11D) - zephyr_compile_options(-mmpy-option=6) - zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_emsdp/Kconfig b/soc/arc/snps_emsdp/Kconfig deleted file mode 100644 index b8f6888433ff5a..00000000000000 --- a/soc/arc/snps_emsdp/Kconfig +++ /dev/null @@ -1,43 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC EM Software Development Platform Core Selection" - default SOC_EMSDP_EM11D - depends on SOC_ARC_EMSDP - -config SOC_EMSDP_EM4 - bool "Synopsys ARC EM4 of EMSDP" - select CPU_HAS_MPU - -config SOC_EMSDP_EM6 - bool "Synopsys ARC EM6 of EMSDP" - select CPU_HAS_MPU - -config SOC_EMSDP_EM5D - bool "Synopsys ARC EM5D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_EMSDP_EM7D - bool "Synopsys ARC EM7D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_EMSDP_EM7D_ESP - bool "Synopsys ARC EM7D+ESP of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - select ARC_HAS_SECURE - -config SOC_EMSDP_EM9D - bool "Synopsys ARC EM9D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_EMSDP_EM11D - bool "Synopsys ARC EM11D of EMSDP" - select CPU_HAS_MPU - select CPU_HAS_FPU - -endchoice diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig b/soc/arc/snps_emsdp/Kconfig.defconfig deleted file mode 100644 index 0e04f92315ac94..00000000000000 --- a/soc/arc/snps_emsdp/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARC_EMSDP - -config SOC - default "snps_emsdp" - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 4 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). - default 4 - -source "soc/arc/snps_emsdp/Kconfig.defconfig.em4" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em5d" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em6" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em7d" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em7d_esp" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em9d" -source "soc/arc/snps_emsdp/Kconfig.defconfig.em11d" - - -endif # SOC_ARC_EMSDP diff --git a/soc/arc/snps_emsdp/Kconfig.soc b/soc/arc/snps_emsdp/Kconfig.soc deleted file mode 100644 index ed0a2f88e20c40..00000000000000 --- a/soc/arc/snps_emsdp/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ARC_EMSDP - bool "Synopsys ARC EM Software Development Platform" - select ARC diff --git a/soc/arc/snps_emsk/CMakeLists.txt b/soc/arc/snps_emsk/CMakeLists.txt deleted file mode 100644 index 8e8ef5865caabb..00000000000000 --- a/soc/arc/snps_emsk/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata -mmpy-option=6) - -if(CONFIG_SOC_EMSK_EM9D) -zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) -elseif(CONFIG_SOC_EMSK_EM11D) -zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) -endif() - -zephyr_sources(soc_config.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_emsk/Kconfig b/soc/arc/snps_emsk/Kconfig deleted file mode 100644 index b1f0f7e54aac90..00000000000000 --- a/soc/arc/snps_emsk/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC EM Starter Kit Core Selection" - default SOC_EMSK_EM7D - depends on SOC_EMSK - -config SOC_EMSK_EM7D - bool "Synopsys ARC EM7D of EMSK" - select CPU_HAS_MPU - -config SOC_EMSK_EM11D - bool "Synopsys ARC EM11D of EMSK" - select CPU_HAS_FPU - -config SOC_EMSK_EM9D - bool "Synopsys ARC EM9D of EMSK" - select CPU_HAS_FPU - -endchoice diff --git a/soc/arc/snps_emsk/Kconfig.defconfig b/soc/arc/snps_emsk/Kconfig.defconfig deleted file mode 100644 index 4d25c7b634be76..00000000000000 --- a/soc/arc/snps_emsk/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EMSK - -config SOC - default "snps_emsk" - -source "soc/arc/snps_emsk/Kconfig.defconfig.em7d" -source "soc/arc/snps_emsk/Kconfig.defconfig.em11d" -source "soc/arc/snps_emsk/Kconfig.defconfig.em9d" - -endif # SOC_EMSK diff --git a/soc/arc/snps_emsk/Kconfig.defconfig.em7d b/soc/arc/snps_emsk/Kconfig.defconfig.em7d deleted file mode 100644 index 24f744b91af1d5..00000000000000 --- a/soc/arc/snps_emsk/Kconfig.defconfig.em7d +++ /dev/null @@ -1,55 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EMSK_EM7D - -config CPU_EM4_DMIPS - default y - -config NUM_IRQ_PRIO_LEVELS - # This processor supports 4 priority levels: - # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). - default 4 - -config NUM_IRQS - # must be > the highest interrupt number used - default 38 if BOARD_EM_STARTERKIT_R23 - default 36 if BOARD_EM_STARTERKIT_R22 - -config ARC_MPU_VER - default 4 if BOARD_EM_STARTERKIT_R23 - default 2 if BOARD_EM_STARTERKIT_R22 - -config RGF_NUM_BANKS - default 1 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 if BOARD_EM_STARTERKIT_R23 - default 30000000 if BOARD_EM_STARTERKIT_R22 - -config HARVARD - default y - -config ARC_FIRQ - default n if BOARD_EM_STARTERKIT_R23 - default y if BOARD_EM_STARTERKIT_R22 - -config CACHE_MANAGEMENT - default y - -if (ARC_MPU_VER = 2) - -config MAIN_STACK_SIZE - default 2048 - -config IDLE_STACK_SIZE - default 2048 - -config ZTEST_STACK_SIZE - default 2048 - depends on ZTEST - -endif # ARC_MPU_VER - -endif # SOC_EMSK_EM7D diff --git a/soc/arc/snps_emsk/Kconfig.soc b/soc/arc/snps_emsk/Kconfig.soc deleted file mode 100644 index d172c4144a7faa..00000000000000 --- a/soc/arc/snps_emsk/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2014 Wind River Systems, Inc. -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EMSK - bool "Synopsys ARC EM Starter Kit SoC" - select ARC diff --git a/soc/arc/snps_nsim/Kconfig b/soc/arc/snps_nsim/Kconfig deleted file mode 100644 index cdf2ec69cae16d..00000000000000 --- a/soc/arc/snps_nsim/Kconfig +++ /dev/null @@ -1,58 +0,0 @@ -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC nSIM SoC Selection" - default SOC_NSIM_EM - depends on SOC_NSIM - -config SOC_NSIM_EM - bool "Synopsys ARC EM in nSIM" - select CPU_HAS_MPU - -config SOC_NSIM_EM7D_V22 - bool "Synopsys ARC EM7D_V22 in nSIM" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_NSIM_EM11D - bool "Synopsys ARC EM11D in nSIM" - select CPU_HAS_MPU - select CPU_HAS_DSP - -config SOC_NSIM_SEM - bool "Synopsys ARC SEM in nSIM" - select CPU_HAS_MPU - select CPU_HAS_FPU - select ARC_HAS_SECURE - -config SOC_NSIM_HS - bool "Synopsys ARC HS in nSIM" - select CPU_HAS_FPU - select CPU_HAS_MPU - -config SOC_NSIM_HS_SMP - bool "Multi-core Synopsys ARC HS in nSIM" - select CPU_HAS_FPU - -config SOC_NSIM_HS_MPUV6 - bool "Synopsys ARC HS with MPU v6 in nSIM" - select CPU_HAS_MPU - select CPU_HAS_FPU - -config SOC_NSIM_VPX5 - bool "Synopsys ARC VPX5 in nSIM" - -config SOC_NSIM_HS6X - bool "Synopsys ARC HS6x in nSIM" - -config SOC_NSIM_HS6X_SMP - bool "Multi-core Synopsys ARC HS6x in nSIM" - -config SOC_NSIM_HS5X - bool "Synopsys ARC HS5x in nSIM" - -config SOC_NSIM_HS5X_SMP - bool "Multi-core Synopsys ARC HS5x in nSIM" - -endchoice diff --git a/soc/arc/snps_nsim/Kconfig.defconfig b/soc/arc/snps_nsim/Kconfig.defconfig deleted file mode 100644 index 69f8d9f440fe11..00000000000000 --- a/soc/arc/snps_nsim/Kconfig.defconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NSIM - -config SOC - default "snps_nsim" - -config XIP - default n - -source "soc/arc/snps_nsim/Kconfig.defconfig.em" -source "soc/arc/snps_nsim/Kconfig.defconfig.em11d" -source "soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22" -source "soc/arc/snps_nsim/Kconfig.defconfig.sem" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs_smp" -source "soc/arc/snps_nsim/Kconfig.defconfig.vpx5" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs5x" -source "soc/arc/snps_nsim/Kconfig.defconfig.hs5x_smp" - -endif # SOC_NSIM diff --git a/soc/arc/snps_nsim/Kconfig.soc b/soc/arc/snps_nsim/Kconfig.soc deleted file mode 100644 index 69e9fdce863c75..00000000000000 --- a/soc/arc/snps_nsim/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2018 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NSIM - bool "Synopsys nSIM simulator for ARC cores" - select ARC diff --git a/soc/arc/snps_qemu/CMakeLists.txt b/soc/arc/snps_qemu/CMakeLists.txt deleted file mode 100644 index a05efdfa22d8ce..00000000000000 --- a/soc/arc/snps_qemu/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(COMPILER STREQUAL gcc) - zephyr_compile_options(-mcpu=${GCC_M_CPU}) - - zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mno-sdata) - -else() - - zephyr_compile_options_ifdef(CONFIG_SOC_QEMU_ARC_HS -arcv2hs -core2 -Xatomic - -Xunaligned -Xcode_density -Xswap -Xbitscan - -Xmpy_option=qmpyh -Xshift_assist -Xbarrel_shifter - -Xtimer0 -Xtimer1) - - zephyr_ld_option_ifdef(CONFIG_SOC_QEMU_ARC_HS -Hlib=hs38_full) - - if(NOT CONFIG_SOC_QEMU_ARC_HS) - message(WARNING "QEMU ARC platforms other than HS are not supported yet with MW toolchain") - endif() - -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arc/snps_qemu/Kconfig b/soc/arc/snps_qemu/Kconfig deleted file mode 100644 index 3146c6c5e9134e..00000000000000 --- a/soc/arc/snps_qemu/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARC QEMU SoC Selection" - default SOC_QEMU_ARC_HS - depends on SOC_QEMU_ARC - -config SOC_QEMU_ARC_EM - bool "Synopsys ARC EM in QEMU" - -config SOC_QEMU_ARC_HS - bool "Synopsys ARC HS in QEMU" - -config SOC_QEMU_ARC_HS6X - bool "Synopsys ARC HS6x in QEMU" - -config SOC_QEMU_ARC_HS5X - bool "Synopsys ARC HS5x in QEMU" - -endchoice diff --git a/soc/arc/snps_qemu/Kconfig.defconfig b/soc/arc/snps_qemu/Kconfig.defconfig deleted file mode 100644 index 25b03b3375fd84..00000000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC - -config SOC - string - default "snps_qemu" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 10000000 - -config RGF_NUM_BANKS - default 1 - -config ARC_FIRQ - default n - -config NUM_IRQ_PRIO_LEVELS - default 15 - -config NUM_IRQS - default 26 - -# Technically ARC HS supports MPUv3, but not v2. But given MPUv3 -# is the same as v2 but with minimal region size of 32 bytes, we -# may assume MPUv3 is just a subset of MPUv2. - -config ARC_MPU_VER - default 2 - -source "soc/arc/snps_qemu/Kconfig.defconfig.em" -source "soc/arc/snps_qemu/Kconfig.defconfig.hs" -source "soc/arc/snps_qemu/Kconfig.defconfig.hs5x" -source "soc/arc/snps_qemu/Kconfig.defconfig.hs6x" - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.em b/soc/arc/snps_qemu/Kconfig.defconfig.em deleted file mode 100644 index 6123c3a9c69a4d..00000000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.em +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_EM - -config CPU_EM4 - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.hs b/soc/arc/snps_qemu/Kconfig.defconfig.hs deleted file mode 100644 index cabb99713e3102..00000000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.hs +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_HS - -config CPU_HS3X - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.hs5x b/soc/arc/snps_qemu/Kconfig.defconfig.hs5x deleted file mode 100644 index 502a78299c3496..00000000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.hs5x +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_HS5X - -config CPU_HS5X - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.defconfig.hs6x b/soc/arc/snps_qemu/Kconfig.defconfig.hs6x deleted file mode 100644 index 1b4d6884ee1f5a..00000000000000 --- a/soc/arc/snps_qemu/Kconfig.defconfig.hs6x +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_ARC_HS6X - -config CPU_HS6X - default y - -endif diff --git a/soc/arc/snps_qemu/Kconfig.soc b/soc/arc/snps_qemu/Kconfig.soc deleted file mode 100644 index 1d3a6c2335c4a4..00000000000000 --- a/soc/arc/snps_qemu/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 Synopsys, Inc. All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_ARC - bool "QEMU emulation of ARC cores" - select ARC - select CPU_HAS_MPU diff --git a/soc/arm/CMakeLists.txt b/soc/arm/CMakeLists.txt index b826da926caf12..e2bba115e17eb2 100644 --- a/soc/arm/CMakeLists.txt +++ b/soc/arm/CMakeLists.txt @@ -1,7 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) +if(DEFINED SOC_SERIES) + add_subdirectory(${SOC_SERIES}) else() add_subdirectory(${SOC_NAME}) endif() diff --git a/soc/arm/Kconfig b/soc/arm/Kconfig index 461f0b41f84c0f..44ffc5d2b39994 100644 --- a/soc/arm/Kconfig +++ b/soc/arm/Kconfig @@ -1,53 +1,8 @@ -# General options signifying CPU capabilities of ARM SoCs - -# Copyright (c) 2018 Nordic Semiconductor ASA. +# Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config CPU_HAS_ARM_MPU - bool - select CPU_HAS_MPU - help - This option is enabled when the CPU has a Memory Protection Unit (MPU) - in ARM flavor. - -config CPU_HAS_NXP_MPU - bool - select CPU_HAS_MPU - help - This option is enabled when the CPU has a Memory Protection Unit (MPU) - in NXP flavor. - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - bool "Custom fixed SoC MPU region definition" - help - If enabled, this option signifies that the SoC will - define and configure its own fixed MPU regions in the - SoC definition. These fixed MPU regions are currently - used to set Flash and SRAM default access policies and - they are programmed at boot time. - -config CPU_HAS_ARM_SAU - bool - select CPU_HAS_TEE - help - MCU implements the ARM Security Attribution Unit (SAU). - -config CPU_HAS_NRF_IDAU - bool - select CPU_HAS_TEE - help - MCU implements the nRF (vendor-specific) Security Attribution Unit. - (IDAU: "Implementation-Defined Attribution Unit", in accordance with - ARM terminology). +if SOC_FAMILY_ARM || SOC_FAMILY_ARM64 -config HAS_SWO - bool - help - When enabled, indicates that SoC has an SWO output +rsource "*/Kconfig" -config SOC_PART_NUMBER - string - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. +endif # SOC_FAMILY_ARM || SOC_FAMILY_ARM64 diff --git a/soc/arm/Kconfig.defconfig b/soc/arm/Kconfig.defconfig new file mode 100644 index 00000000000000..d25284634e3031 --- /dev/null +++ b/soc/arm/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ARM || SOC_FAMILY_ARM64 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ARM || SOC_FAMILY_ARM64 diff --git a/soc/arm/Kconfig.soc b/soc/arm/Kconfig.soc new file mode 100644 index 00000000000000..159cb16c43cac7 --- /dev/null +++ b/soc/arm/Kconfig.soc @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ARM + bool + +config SOC_FAMILY_ARM64 + bool + +config SOC_FAMILY + default "arm" if SOC_FAMILY_ARM + default "arm64" if SOC_FAMILY_ARM64 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/ambiq/Kconfig b/soc/arm/ambiq/Kconfig deleted file mode 100644 index eba0a01db719cf..00000000000000 --- a/soc/arm/ambiq/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -config SOC_FAMILY_AMBIQ - bool - -if SOC_FAMILY_AMBIQ - -config SOC_FAMILY - string - default "ambiq" - -source "soc/arm/ambiq/*/Kconfig.soc" - -endif # SOC_FAMILY_AMBIQ diff --git a/soc/arm/ambiq/Kconfig.defconfig b/soc/arm/ambiq/Kconfig.defconfig deleted file mode 100644 index b3102f50375d2e..00000000000000 --- a/soc/arm/ambiq/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -source "soc/arm/ambiq/*/Kconfig.defconfig.series" - -config CORTEX_M_SYSTICK - default n if AMBIQ_STIMER_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 if AMBIQ_STIMER_TIMER diff --git a/soc/arm/ambiq/Kconfig.soc b/soc/arm/ambiq/Kconfig.soc deleted file mode 100644 index e1e31309730703..00000000000000 --- a/soc/arm/ambiq/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -source "soc/arm/ambiq/*/Kconfig.series" diff --git a/soc/arm/ambiq/apollo4x/CMakeLists.txt b/soc/arm/ambiq/apollo4x/CMakeLists.txt deleted file mode 100644 index a82fe0a51f3960..00000000000000 --- a/soc/arm/ambiq/apollo4x/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Antmicro -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) -zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.series b/soc/arm/ambiq/apollo4x/Kconfig.defconfig.series deleted file mode 100644 index f933eb5d1c400e..00000000000000 --- a/soc/arm/ambiq/apollo4x/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -if SOC_SERIES_APOLLO4X - -source "soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4*" - -config SOC_SERIES - default "apollo4x" - -endif # SOC_SERIES_APOLLO4X diff --git a/soc/arm/ambiq/apollo4x/Kconfig.series b/soc/arm/ambiq/apollo4x/Kconfig.series deleted file mode 100644 index a9e72567206407..00000000000000 --- a/soc/arm/ambiq/apollo4x/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro - -# Ambiq Apollo4 MCU Series - -config SOC_SERIES_APOLLO4X - bool "Apollo4 Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_AMBIQ - select HAS_SWO - select AMBIQ_HAL - help - Enable support for Apollo4 MCU series diff --git a/soc/arm/ambiq/apollo4x/Kconfig.soc b/soc/arm/ambiq/apollo4x/Kconfig.soc deleted file mode 100644 index a9b5cf00824eac..00000000000000 --- a/soc/arm/ambiq/apollo4x/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2023 Antmicro -# Copyright (c) 2023 Ambiq Micro Inc. - -choice - prompt "Ambiq Apollo4X Selection" - depends on SOC_SERIES_APOLLO4X - -config SOC_APOLLO4P - bool "Apollo4P" - -config SOC_APOLLO4P_BLUE - bool "Apollo4 Blue Plus" - -endchoice diff --git a/soc/arm/arm/Kconfig b/soc/arm/arm/Kconfig deleted file mode 100644 index de5b5d581cb16d..00000000000000 --- a/soc/arm/arm/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ARM - bool - -if SOC_FAMILY_ARM -config SOC_FAMILY - string - default "arm" - -source "soc/arm/arm/*/Kconfig.soc" -endif # SOC_FAMILY_ARM diff --git a/soc/arm/arm/Kconfig.defconfig b/soc/arm/arm/Kconfig.defconfig deleted file mode 100644 index 54abe04110df58..00000000000000 --- a/soc/arm/arm/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/arm/*/Kconfig.defconfig.series" diff --git a/soc/arm/arm/Kconfig.soc b/soc/arm/arm/Kconfig.soc deleted file mode 100644 index 60ee85807189ea..00000000000000 --- a/soc/arm/arm/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/arm/*/Kconfig.series" diff --git a/soc/arm/arm/beetle/CMakeLists.txt b/soc/arm/arm/beetle/CMakeLists.txt deleted file mode 100644 index e911f5faab5067..00000000000000 --- a/soc/arm/arm/beetle/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/beetle/Kconfig.defconfig.beetle_r0 b/soc/arm/arm/beetle/Kconfig.defconfig.beetle_r0 deleted file mode 100644 index ae6d93ca0ccdd7..00000000000000 --- a/soc/arm/arm/beetle/Kconfig.defconfig.beetle_r0 +++ /dev/null @@ -1,8 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "beetle_r0" - depends on SOC_BEETLE_R0 diff --git a/soc/arm/arm/beetle/Kconfig.defconfig.series b/soc/arm/arm/beetle/Kconfig.defconfig.series deleted file mode 100644 index 2c2f58634a0430..00000000000000 --- a/soc/arm/arm/beetle/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_BEETLE - -source "soc/arm/arm/beetle/Kconfig.defconfig.beetle*" - -config SOC_SERIES - default "beetle" - -config NUM_IRQS - default 45 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 24000000 - -config CLOCK_CONTROL_INIT_PRIORITY - default 1 - depends on CLOCK_CONTROL - -endif # SOC_SERIES_BEETLE diff --git a/soc/arm/arm/beetle/Kconfig.series b/soc/arm/arm/beetle/Kconfig.series deleted file mode 100644 index 2217f282cf06fe..00000000000000 --- a/soc/arm/arm/beetle/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_BEETLE - bool "Arm Beetle MCU Series" - select ARM - select CPU_CORTEX_M3 - select SOC_FAMILY_ARM - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_DWT - help - Enable support for Beetle MCU Series diff --git a/soc/arm/arm/beetle/Kconfig.soc b/soc/arm/arm/beetle/Kconfig.soc deleted file mode 100644 index e577ee7060e12f..00000000000000 --- a/soc/arm/arm/beetle/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# ARM LTD Beetle SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM Beetle SoC" - depends on SOC_SERIES_BEETLE - -config SOC_BEETLE_R0 - bool "ARM BEETLE R0" - -endchoice diff --git a/soc/arm/arm/designstart/CMakeLists.txt b/soc/arm/arm/designstart/CMakeLists.txt deleted file mode 100644 index 5d2598e239b056..00000000000000 --- a/soc/arm/arm/designstart/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m1 b/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m1 deleted file mode 100644 index 8c6052ffa2dbb8..00000000000000 --- a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m1 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1 - -config SOC - default "designstart_cortex_m1" - -endif # SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1 diff --git a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m3 b/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m3 deleted file mode 100644 index 49275b57afe25b..00000000000000 --- a/soc/arm/arm/designstart/Kconfig.defconfig.cortex_m3 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3 - -config SOC - default "designstart_cortex_m3" - -endif # SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/soc/arm/arm/designstart/Kconfig.defconfig.series b/soc/arm/arm/designstart/Kconfig.defconfig.series deleted file mode 100644 index de0c30c9cf6f79..00000000000000 --- a/soc/arm/arm/designstart/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ARM_DESIGNSTART - -config SOC_SERIES - default "designstart" - -source "soc/arm/arm/designstart/Kconfig.defconfig.cortex*" - -endif # SOC_SERIES_ARM_DESIGNSTART diff --git a/soc/arm/arm/designstart/Kconfig.series b/soc/arm/arm/designstart/Kconfig.series deleted file mode 100644 index 23c49edc8c6ed8..00000000000000 --- a/soc/arm/arm/designstart/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ARM_DESIGNSTART - bool "Arm DesignStart SoC Series" - select ARM - select SOC_FAMILY_ARM - help - Enable support for the ARM DesignStart SoC Series diff --git a/soc/arm/arm/designstart/Kconfig.soc b/soc/arm/arm/designstart/Kconfig.soc deleted file mode 100644 index 00ce3c7a4eb7ad..00000000000000 --- a/soc/arm/arm/designstart/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM DesignStart SoCs" - depends on SOC_SERIES_ARM_DESIGNSTART - -config SOC_ARM_DESIGNSTART_FPGA_CORTEX_M1 - bool "ARM Cortex-M1 DesignStart FPGA" - select CPU_CORTEX_M1 - imply XIP - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -config SOC_ARM_DESIGNSTART_FPGA_CORTEX_M3 - bool "ARM Cortex-M3 DesignStart FPGA" - select CPU_CORTEX_M3 - imply XIP - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -endchoice diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt b/soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt deleted file mode 100644 index d9264843fae857..00000000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c) -zephyr_library_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.defconfig.series b/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.defconfig.series deleted file mode 100644 index d884d3e5494ecd..00000000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.defconfig.series +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_FVP_AEMV8R_AARCH32 - -config SOC_SERIES - default "fvp_aemv8r_aarch32" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 128 - -if SOC_FVP_AEMV8R_AARCH32 - -config SOC - default "fvp_aemv8r_aarch32" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config MAX_DOMAIN_PARTITIONS - default 24 if USERSPACE - -endif # SOC_FVP_AEMV8R_AARCH32 - -endif # SOC_SERIES_FVP_AEMV8R_AARCH32 diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.series b/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.series deleted file mode 100644 index 2479afe413090c..00000000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_FVP_AEMV8R_AARCH32 - bool "ARM FVP AEMv8R AArch32 Series" - select ARM - select SOC_FAMILY_ARM - help - Enable support for ARM FVP AEMv8R AArch32 Series diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc b/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc deleted file mode 100644 index 6993cfe715abae..00000000000000 --- a/soc/arm/arm/fvp_aemv8r_aarch32/Kconfig.soc +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2022 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM FVP AEMv8R AArch32 SoCs" - depends on SOC_SERIES_FVP_AEMV8R_AARCH32 - -config SOC_FVP_AEMV8R_AARCH32 - bool "ARM FVP AEMv8R aarch32 simulation" - select CPU_CORTEX_R52 - select CPU_HAS_ARM_MPU - select CPU_HAS_MPU - select VFP_DP_D32_FP16_FMAC if !USE_SWITCH - select GIC_V3 - select GIC_SINGLE_SECURITY_STATE - select PLATFORM_SPECIFIC_INIT - -endchoice diff --git a/soc/arm/arm/mps2/CMakeLists.txt b/soc/arm/arm/mps2/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9bc8..00000000000000 --- a/soc/arm/arm/mps2/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an385 b/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an385 deleted file mode 100644 index 3f0e09b3b78b99..00000000000000 --- a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an385 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MPS2_AN385 - -config SOC - default "mps2_an385" - -config NUM_IRQS - default 32 - -endif diff --git a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 b/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 deleted file mode 100644 index a4bd9aea47f922..00000000000000 --- a/soc/arm/arm/mps2/Kconfig.defconfig.mps2_an521 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2018-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MPS2_AN521 - -config SOC - default "mps2_an521" - -config NUM_IRQS - default 96 - -endif diff --git a/soc/arm/arm/mps2/Kconfig.defconfig.series b/soc/arm/arm/mps2/Kconfig.defconfig.series deleted file mode 100644 index 62234279c140a6..00000000000000 --- a/soc/arm/arm/mps2/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MPS2 - -config SOC_SERIES - default "mps2" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 - -source "soc/arm/arm/mps2/Kconfig.defconfig.mps2*" - -endif # SOC_SERIES_MPS2 diff --git a/soc/arm/arm/mps2/Kconfig.series b/soc/arm/arm/mps2/Kconfig.series deleted file mode 100644 index c8715c21c83044..00000000000000 --- a/soc/arm/arm/mps2/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2017 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MPS2 - bool "Arm MPS2 MCU Series" - select ARM - select SOC_FAMILY_ARM - select GPIO_MMIO32 if GPIO - help - Enable support for ARM MPS2 MCU Series diff --git a/soc/arm/arm/mps2/Kconfig.soc b/soc/arm/arm/mps2/Kconfig.soc deleted file mode 100644 index 6a01c0d27fa762..00000000000000 --- a/soc/arm/arm/mps2/Kconfig.soc +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2017-2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_MPS2_AN521 - bool - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - -choice - prompt "ARM MPS2 SoCs" - depends on SOC_SERIES_MPS2 - -config SOC_MPS2_AN385 - bool "ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)" - select CPU_CORTEX_M3 - select CPU_HAS_ARM_MPU - -config SOC_MPS2_AN521_CPU0 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0" - select SOC_MPS2_AN521 - select CPU_HAS_ARM_SAU - -config SOC_MPS2_AN521_CPU1 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1" - select SOC_MPS2_AN521 - select CPU_HAS_FPU - select ARMV8_M_DSP - -endchoice diff --git a/soc/arm/arm/mps2/soc.c b/soc/arm/arm/mps2/soc.c deleted file mode 100644 index 76edaa388f5aae..00000000000000 --- a/soc/arm/arm/mps2/soc.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * Initial contents based on soc/arm/ti_lm3s6965/soc.c which is: - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - - -/* Setup GPIO drivers for accessing FPGAIO registers */ -#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio) -#define FPGAIO_INIT(n) \ - GPIO_MMIO32_INIT(FPGAIO_NODE(n), \ - DT_REG_ADDR(FPGAIO_NODE(n)), \ - BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios))) - -/* We expect there to be 3 arm,mps2-fpgaio-gpio devices: - * led0, button, and misc - */ -FPGAIO_INIT(0); -FPGAIO_INIT(1); -FPGAIO_INIT(2); - -/* (Secure System Control) Base Address */ -#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL) -#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114) -#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118) -#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL) - -/* The base address that the application image will start at on the secondary - * (non-TrustZone) Cortex-M33 mcu. - */ -#define CPU1_FLASH_ADDRESS (0x38B000) - -/* The memory map offset for the application image, which is used - * to determine the location of the reset vector at startup. - */ -#define CPU1_FLASH_OFFSET (0x10000000) - -/** - * @brief Wake up CPU 1 from another CPU, this is platform specific. - */ -void wakeup_cpu1(void) -{ - /* Set the Initial Secure Reset Vector Register for CPU 1 */ - *(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) = - (uint32_t)_vector_start + - CPU1_FLASH_ADDRESS - - CPU1_FLASH_OFFSET; - - /* Set the CPU Boot wait control after reset */ - *(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0; -} - -/** - * @brief Get the current CPU ID, this is platform specific. - * - * @return Current CPU ID - */ -uint32_t sse_200_platform_get_cpu_id(void) -{ - volatile uint32_t *p_cpu_id = (volatile uint32_t *)SSE_200_CPU_ID_UNIT_BASE; - - return (uint32_t)*p_cpu_id; -} diff --git a/soc/arm/arm/mps3/CMakeLists.txt b/soc/arm/arm/mps3/CMakeLists.txt deleted file mode 100644 index d82e1bc62c5dcd..00000000000000 --- a/soc/arm/arm/mps3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/mps3/Kconfig.defconfig.series b/soc/arm/arm/mps3/Kconfig.defconfig.series deleted file mode 100644 index 6cd25168380102..00000000000000 --- a/soc/arm/arm/mps3/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MPS3 - -config SOC_SERIES - default "mps3" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 - -source "soc/arm/arm/mps3/Kconfig.defconfig.mps3*" - -endif # SOC_SERIES_MPS3 diff --git a/soc/arm/arm/mps3/Kconfig.series b/soc/arm/arm/mps3/Kconfig.series deleted file mode 100644 index 2b73ade4a69f28..00000000000000 --- a/soc/arm/arm/mps3/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MPS3 - bool "Arm MPS3 MCU Series" - select ARM - select SOC_FAMILY_ARM - select GPIO_MMIO32 if GPIO - help - Enable support for ARM MPS3 MCU Series diff --git a/soc/arm/arm/mps3/Kconfig.soc b/soc/arm/arm/mps3/Kconfig.soc deleted file mode 100644 index ae577fa549b1b7..00000000000000 --- a/soc/arm/arm/mps3/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2017-2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Arm MPS3 SoCs" - depends on SOC_SERIES_MPS3 - -config SOC_MPS3_AN547 - bool "Arm Cortex-M55 SSE-300 on MPS3 (AN547)" - select CPU_CORTEX_M55 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARMV8_1_M_MVEI - select ARMV8_1_M_MVEF - select ARMV8_1_M_PMU - -endchoice - -config ARMV8_1_M_PMU_EVENTCNT - int - default 8 if SOC_MPS3_AN547 diff --git a/soc/arm/arm/musca_b1/CMakeLists.txt b/soc/arm/arm/musca_b1/CMakeLists.txt deleted file mode 100644 index 9c8a3b15eb2355..00000000000000 --- a/soc/arm/arm/musca_b1/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2018 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1 b/soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1 deleted file mode 100644 index 59fac252df4382..00000000000000 --- a/soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_V2M_MUSCA_B1 - -config SOC - default "musca_b1" - -config NUM_IRQS - default 96 - -endif diff --git a/soc/arm/arm/musca_b1/Kconfig.defconfig.series b/soc/arm/arm/musca_b1/Kconfig.defconfig.series deleted file mode 100644 index 356f945dc5620c..00000000000000 --- a/soc/arm/arm/musca_b1/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MUSCA_B1 - -config SOC_SERIES - default "musca_b1" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 40000000 - -source "soc/arm/arm/musca_b1/Kconfig.defconfig.musca_b1" - -endif # SOC_SERIES_MUSCA_B1 diff --git a/soc/arm/arm/musca_b1/Kconfig.series b/soc/arm/arm/musca_b1/Kconfig.series deleted file mode 100644 index 1a74a623f8d427..00000000000000 --- a/soc/arm/arm/musca_b1/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MUSCA_B1 - bool "Arm v2m MUSCA B1 MCU Series" - select ARM - select SOC_FAMILY_ARM - select BUILD_OUTPUT_HEX - help - Enable support for arm V2M Musca B1 MCU Series diff --git a/soc/arm/arm/musca_b1/Kconfig.soc b/soc/arm/arm/musca_b1/Kconfig.soc deleted file mode 100644 index da7ae30698a0a2..00000000000000 --- a/soc/arm/arm/musca_b1/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM Musca B1 SoCs" - depends on SOC_SERIES_MUSCA_B1 - -config SOC_V2M_MUSCA_B1 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_DWT - -endchoice diff --git a/soc/arm/arm/musca_s1/CMakeLists.txt b/soc/arm/arm/musca_s1/CMakeLists.txt deleted file mode 100644 index 51df24c9b73152..00000000000000 --- a/soc/arm/arm/musca_s1/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2018 Linaro Limited -# -# SPDX-License-Identifier: Apache-2.0 -# - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1 b/soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1 deleted file mode 100644 index e0a0336c9edff4..00000000000000 --- a/soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1 +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_V2M_MUSCA_S1 - -config SOC - default "musca_s1" - -config NUM_IRQS - default 96 - -endif diff --git a/soc/arm/arm/musca_s1/Kconfig.defconfig.series b/soc/arm/arm/musca_s1/Kconfig.defconfig.series deleted file mode 100644 index ae4e31a0e72019..00000000000000 --- a/soc/arm/arm/musca_s1/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MUSCA_S1 - -config SOC_SERIES - default "musca_s1" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -source "soc/arm/arm/musca_s1/Kconfig.defconfig.musca_s1" - -endif # SOC_SERIES_MUSCA_S1 diff --git a/soc/arm/arm/musca_s1/Kconfig.series b/soc/arm/arm/musca_s1/Kconfig.series deleted file mode 100644 index 95b054e3d8a5cd..00000000000000 --- a/soc/arm/arm/musca_s1/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MUSCA_S1 - bool "Arm v2m MUSCA-S1 MCU Series" - select ARM - select SOC_FAMILY_ARM - select BUILD_OUTPUT_HEX - help - Enable support for Arm V2M Musca-S1 MCU Series diff --git a/soc/arm/arm/musca_s1/Kconfig.soc b/soc/arm/arm/musca_s1/Kconfig.soc deleted file mode 100644 index 0c0763fae2a0ad..00000000000000 --- a/soc/arm/arm/musca_s1/Kconfig.soc +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2019-2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM Musca-S1 SoCs" - depends on SOC_SERIES_MUSCA_S1 - -config SOC_V2M_MUSCA_S1 - bool "ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-S1" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select ARMV8_M_DSP - -endchoice diff --git a/soc/arm/aspeed/Kconfig b/soc/arm/aspeed/Kconfig deleted file mode 100644 index 78df65d605b70d..00000000000000 --- a/soc/arm/aspeed/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -config SOC_FAMILY_ASPEED - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_ASPEED - -config SOC_FAMILY - string - default "aspeed" - -source "soc/arm/aspeed/*/Kconfig.soc" - -endif # SOC_FAMILY_ASPEED diff --git a/soc/arm/aspeed/Kconfig.defconfig b/soc/arm/aspeed/Kconfig.defconfig deleted file mode 100644 index bbfbf4de751b9e..00000000000000 --- a/soc/arm/aspeed/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -source "soc/arm/aspeed/*/Kconfig.defconfig.series" diff --git a/soc/arm/aspeed/Kconfig.soc b/soc/arm/aspeed/Kconfig.soc deleted file mode 100644 index 3bd886a676aab6..00000000000000 --- a/soc/arm/aspeed/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -source "soc/arm/aspeed/*/Kconfig.series" diff --git a/soc/arm/aspeed/ast10x0/CMakeLists.txt b/soc/arm/aspeed/ast10x0/CMakeLists.txt deleted file mode 100644 index 0d73ca4ba3459c..00000000000000 --- a/soc/arm/aspeed/ast10x0/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021 ASPEED Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) -zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m) -zephyr_linker_sources(ROM_START SORT_KEY 0x1sboot sboot.ld) -zephyr_linker_sources(RAM_SECTIONS nocache.ld) - -set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/${SOC_SERIES}/tools/gen_uart_booting_image.py - ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin - ${PROJECT_BINARY_DIR}/uart_${CONFIG_KERNEL_BIN_NAME}.bin -) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series b/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series deleted file mode 100644 index a6440b71d9df97..00000000000000 --- a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -if SOC_SERIES_AST10X0 - -source "soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast10*0" - -config SOC_SERIES - default "ast10x0" - -config ICACHE_LINE_SIZE - default 32 - -config DCACHE_LINE_SIZE - default 32 - -choice CACHE_TYPE - default EXTERNAL_CACHE -endchoice - -endif # SOC_SERIES_AST10X0 diff --git a/soc/arm/aspeed/ast10x0/Kconfig.series b/soc/arm/aspeed/ast10x0/Kconfig.series deleted file mode 100644 index e4d0fdcd0561e2..00000000000000 --- a/soc/arm/aspeed/ast10x0/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -config SOC_SERIES_AST10X0 - bool "Aspeed AST10X0 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_ASPEED - select SYSCON - select CACHE - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CACHE_MANAGEMENT - select CACHE_ASPEED - help - Enable support for ASPEED AST10X0 series diff --git a/soc/arm/aspeed/ast10x0/Kconfig.soc b/soc/arm/aspeed/ast10x0/Kconfig.soc deleted file mode 100644 index 844362576259d9..00000000000000 --- a/soc/arm/aspeed/ast10x0/Kconfig.soc +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2021 ASPEED Technology Inc. - -choice - prompt "ASPEED AST10X0 Selection" - depends on SOC_SERIES_AST10X0 - -config SOC_AST1030 - bool "AST1030" - -endchoice - -config SRAM_NC_SIZE - int "noncached SRAM Size in kB" - help - The non-cached SRAM size in kB. The default value comes from reg[1] - of /chosen/zephyr,sram in devicetree. The user should generally avoid - changing it via menuconfig or in configuration files. - -config SRAM_NC_BASE_ADDRESS - hex "noncached SRAM Base Address" - help - The non-cached SRAM base address. The default value comes from from - reg[1] of /chosen/zephyr,sram in devicetree. The user should - generally avoid changing it via menuconfig or in configuration files. diff --git a/soc/arm/atmel_sam/CMakeLists.txt b/soc/arm/atmel_sam/CMakeLists.txt deleted file mode 100644 index d02e74e706b4af..00000000000000 --- a/soc/arm/atmel_sam/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Makefile - Atmel SAM MCU family -# -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) -add_subdirectory_ifdef(CONFIG_ASF common) diff --git a/soc/arm/atmel_sam/Kconfig b/soc/arm/atmel_sam/Kconfig deleted file mode 100644 index 963d90a450e4f8..00000000000000 --- a/soc/arm/atmel_sam/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Atmel SAM MCU family configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SAM - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_SAM - -config SOC_FAMILY - string - default "atmel_sam" - -# Select SoC Part No. and configuration options -source "soc/arm/atmel_sam/*/Kconfig.soc" - -endif # SOC_FAMILY_SAM diff --git a/soc/arm/atmel_sam/Kconfig.defconfig b/soc/arm/atmel_sam/Kconfig.defconfig deleted file mode 100644 index f8a0e1ed5769a4..00000000000000 --- a/soc/arm/atmel_sam/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAM MCU family default configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam/*/Kconfig.defconfig.series" - -if SOC_FAMILY_SAM - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config CLOCK_CONTROL - default y - -config PINCTRL - default y - -config WATCHDOG - default y - -endif # SOC_FAMILY_SAM diff --git a/soc/arm/atmel_sam/Kconfig.soc b/soc/arm/atmel_sam/Kconfig.soc deleted file mode 100644 index 688cd650b7f84f..00000000000000 --- a/soc/arm/atmel_sam/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Atmel SAM MCU series selection - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam/*/Kconfig.series" diff --git a/soc/arm/atmel_sam/common/CMakeLists.txt b/soc/arm/atmel_sam/common/CMakeLists.txt deleted file mode 100644 index 3fe8bdd1d6d21b..00000000000000 --- a/soc/arm/atmel_sam/common/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_pmc.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_gpio.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_supc.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_power.c) -zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_poweroff.c) - -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_pm.c) -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_gpio.c) -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_poweroff.c) diff --git a/soc/arm/atmel_sam/sam3x/CMakeLists.txt b/soc/arm/atmel_sam/sam3x/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9bc8..00000000000000 --- a/soc/arm/atmel_sam/sam3x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam3x/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam3x/Kconfig.defconfig.series deleted file mode 100644 index 7873880dc587a5..00000000000000 --- a/soc/arm/atmel_sam/sam3x/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Atmel SAM3X MCU series configuration options - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM3X - -config SOC_SERIES - default "sam3x" - -config SOC_PART_NUMBER - default "sam3x4c" if SOC_PART_NUMBER_SAM3X4C - default "sam3x4e" if SOC_PART_NUMBER_SAM3X4E - default "sam3x8c" if SOC_PART_NUMBER_SAM3X8C - default "sam3x8e" if SOC_PART_NUMBER_SAM3X8E - default "sam3x8h" if SOC_PART_NUMBER_SAM3X8H - -# -# SAM3 family has total 45 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 45 - -endif # SOC_SERIES_SAM3X diff --git a/soc/arm/atmel_sam/sam3x/Kconfig.series b/soc/arm/atmel_sam/sam3x/Kconfig.series deleted file mode 100644 index 08a3781b6d3ea1..00000000000000 --- a/soc/arm/atmel_sam/sam3x/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Atmel SAM3X MCU series - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM3X - bool "Atmel SAM3X MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM3X Cortex-M3 microcontrollers. - Part No.: SAM3X8E diff --git a/soc/arm/atmel_sam/sam3x/Kconfig.soc b/soc/arm/atmel_sam/sam3x/Kconfig.soc deleted file mode 100644 index 1e9a203396a300..00000000000000 --- a/soc/arm/atmel_sam/sam3x/Kconfig.soc +++ /dev/null @@ -1,89 +0,0 @@ -# Atmel SAM3X MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2016 Intel Corporation. -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM3X MCU Selection" - depends on SOC_SERIES_SAM3X - - config SOC_PART_NUMBER_SAM3X4C - bool "SAM3X4C" - config SOC_PART_NUMBER_SAM3X4E - bool "SAM3X4E" - config SOC_PART_NUMBER_SAM3X8C - bool "SAM3X8C" - config SOC_PART_NUMBER_SAM3X8E - bool "SAM3X8E" - config SOC_PART_NUMBER_SAM3X8H - bool "SAM3X8H" -endchoice - -if SOC_SERIES_SAM3X - -config SOC_ATMEL_SAM3X_EXT_SLCK - bool "Atmel SAM3 to use external crystal oscillator for slow clock" - help - Says y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAM3X_EXT_MAINCK - bool "Atmel SAM3 to use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Says y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAM3X_PLLA_MULA - hex - default 0x06 - help - This is the multiplier (MULA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 6, and DIVA == 1, - PLL is running at 7 times of main clock. - -config SOC_ATMEL_SAM3X_PLLA_DIVA - hex - default 0x01 - help - This is the divider (DIVA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 6, and DIVA == 1, - PLL is running at 7 times of main clock. - -config SOC_ATMEL_SAM3X_WAIT_MODE - bool "Atmel SAM3 goes to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAM3X_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -endif # SOC_SERIES_SAM3X diff --git a/soc/arm/atmel_sam/sam3x/soc.c b/soc/arm/atmel_sam/sam3x/soc.c deleted file mode 100644 index 9a20d566375317..00000000000000 --- a/soc/arm/atmel_sam/sam3x/soc.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2023 Gerson Fernando Budke - * Copyright (c) 2023 Basalte bv - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Atmel SAM3X MCU series initialization code - * - * This module provides routines to initialize and support board-level hardware - * for the Atmel SAM3X series processor. - */ - -#include -#include -#include - -/** - * @brief Setup various clocks on SoC at boot time. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC0->EEFC_FMR = EEFC_FMR_FWS(0); - EFC1->EEFC_FMR = EEFC_FMR_FWS(0); - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. - * TODO: set FWS based on the actual MCK frequency and VDDCORE value - * rather than maximum supported 84 MHz at standard VDDCORE=1.8V - */ - EFC0->EEFC_FMR = EEFC_FMR_FWS(4); - EFC1->EEFC_FMR = EEFC_FMR_FWS(4); - - /* - * Setup PLLA - */ - - /* - * PLL clock = Main * (MULA + 1) / DIVA - * - * By default, MULA == 6, DIVA == 1. - * With main crystal running at 12 MHz, - * PLL = 12 * (6 + 1) / 1 = 84 MHz - * - * With Processor Clock prescaler at 1 - * Processor Clock (HCLK) = 84 MHz. - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM3X_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAM3X_PLLA_DIVA); - - /* - * Final setup of the Master Clock - */ - - /* prescaler has to be set before PLL lock */ - soc_pmc_mck_set_prescaler(1); - - /* Select PLL as Master Clock source. */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM3X_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - /* Setup system clocks */ - clock_init(); -} diff --git a/soc/arm/atmel_sam/sam3x/soc.h b/soc/arm/atmel_sam/sam3x/soc.h deleted file mode 100644 index 3fe78a7e6ba7b0..00000000000000 --- a/soc/arm/atmel_sam/sam3x/soc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Register access macros for the Atmel SAM3X MCU. - * - * This file provides register access macros for the Atmel SAM3X MCU, HAL - * drivers for core peripherals as well as symbols specific to Atmel SAM family. - */ - -#ifndef _ATMEL_SAM3X_SOC_H_ -#define _ATMEL_SAM3X_SOC_H_ - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined CONFIG_SOC_PART_NUMBER_SAM3X4C -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X4E -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8C -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8E -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAM3X8H -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -#endif /* _ASMLANGUAGE */ - -#endif /* _ATMEL_SAM3X_SOC_H_ */ diff --git a/soc/arm/atmel_sam/sam4e/CMakeLists.txt b/soc/arm/atmel_sam/sam4e/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9bc8..00000000000000 --- a/soc/arm/atmel_sam/sam4e/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series deleted file mode 100644 index 779c0d5dbed051..00000000000000 --- a/soc/arm/atmel_sam/sam4e/Kconfig.defconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# Atmel SAM4E MCU series configuration options - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM4E - -config SOC_SERIES - default "sam4e" - -config SOC_PART_NUMBER - default "sam4e16e" if SOC_PART_NUMBER_SAM4E16E - default "sam4e16c" if SOC_PART_NUMBER_SAM4E16C - default "sam4e8e" if SOC_PART_NUMBER_SAM4E8E - default "sam4e8c" if SOC_PART_NUMBER_SAM4E8C - -# -# SAM4E family has total 47 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 47 - -if NETWORKING - -config NET_L2_ETHERNET - default y - -endif # NETWORKING - -endif # SOC_SERIES_SAM4E diff --git a/soc/arm/atmel_sam/sam4e/Kconfig.series b/soc/arm/atmel_sam/sam4e/Kconfig.series deleted file mode 100644 index 93cc0e20a48365..00000000000000 --- a/soc/arm/atmel_sam/sam4e/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Atmel SAM4E MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2019-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM4E - bool "Atmel SAM4E MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM4E Cortex-M4 microcontrollers. - Part No.: SAM4E16E, SAM4E16C, SAM4E8E, SAM4E8C diff --git a/soc/arm/atmel_sam/sam4e/Kconfig.soc b/soc/arm/atmel_sam/sam4e/Kconfig.soc deleted file mode 100644 index e48e8de0170871..00000000000000 --- a/soc/arm/atmel_sam/sam4e/Kconfig.soc +++ /dev/null @@ -1,91 +0,0 @@ -# Atmel SAM4E MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2019 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM4E MCU Selection" - depends on SOC_SERIES_SAM4E - - config SOC_PART_NUMBER_SAM4E16E - bool "SAM4E16E" - - config SOC_PART_NUMBER_SAM4E16C - bool "SAM4E16C" - - config SOC_PART_NUMBER_SAM4E8E - bool "SAM4E8E" - - config SOC_PART_NUMBER_SAM4E8C - bool "SAM4E8C" - -endchoice - -if SOC_SERIES_SAM4E - -config SOC_ATMEL_SAM4E_EXT_SLCK - bool "Atmel SAM4E to use external crystal oscillator for slow clock" - help - Says y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAM4E_EXT_MAINCK - bool "Atmel SAM4E to use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Says y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAM4E_PLLA_MULA - hex "PLL MULA" - default 0x09 - help - This is the multiplier (MULA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4E_PLLA_DIVA - hex "PLL DIVA" - default 0x01 - help - This is the divider (DIVA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4E_WAIT_MODE - bool "Atmel SAM4E goes to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAM4E_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -endif # SOC_SERIES_SAM4E diff --git a/soc/arm/atmel_sam/sam4e/soc.c b/soc/arm/atmel_sam/sam4e/soc.c deleted file mode 100644 index b1c8174fddcf61..00000000000000 --- a/soc/arm/atmel_sam/sam4e/soc.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2019-2023 Gerson Fernando Budke - * Copyright (c) 2023 Basalte bv - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Atmel SAM4E MCU series initialization code - * - * This module provides routines to initialize and support board-level hardware - * for the Atmel SAM4E series processor. - */ - -#include -#include -#include - -/** - * @brief Setup various clock on SoC at boot time. - * - * Setup the SoC clocks according to section 28.12 in datasheet. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC->EEFC_FMR = EEFC_FMR_FWS(0); - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet. - * This is set to the highest number of read cycles because it won't - * hurt lower clock frequencies. However, a high frequency with too - * few read cycles could cause flash read problems. FWS 5 (6 cycles) - * is the safe setting for all of this SoCs usable frequencies. - */ - EFC->EEFC_FMR = EEFC_FMR_FWS(5); - - /* - * Setup PLLA - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4E_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAM4E_PLLA_DIVA); - - /* - * Final setup of the Master Clock - */ - - /* prescaler has to be set before PLL lock */ - soc_pmc_mck_set_prescaler(1); - - /* Select PLL as Master Clock source. */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4E_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - /* Setup system clocks. */ - clock_init(); -} diff --git a/soc/arm/atmel_sam/sam4e/soc.h b/soc/arm/atmel_sam/sam4e/soc.h deleted file mode 100644 index 290653e148ab8d..00000000000000 --- a/soc/arm/atmel_sam/sam4e/soc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2019-2020 Gerson Fernando Budke - * Copyright (c) 2018 Vincent van der Locht - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM4E family processors. - */ - -#ifndef _ATMEL_SAM4E_SOC_H_ -#define _ATMEL_SAM4E_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined(CONFIG_SOC_PART_NUMBER_SAM4E16E) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E16C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8E) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4E8C) -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -#endif /* !_ASMLANGUAGE */ - -#endif /* _ATMEL_SAM4E_SOC_H_ */ diff --git a/soc/arm/atmel_sam/sam4l/CMakeLists.txt b/soc/arm/atmel_sam/sam4l/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9bc8..00000000000000 --- a/soc/arm/atmel_sam/sam4l/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam4l/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam4l/Kconfig.defconfig.series deleted file mode 100644 index 71fc855d112932..00000000000000 --- a/soc/arm/atmel_sam/sam4l/Kconfig.defconfig.series +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM4L - -config SOC_SERIES - default "sam4l" - -config SOC_PART_NUMBER - default "sam4ls8c" if SOC_PART_NUMBER_SAM4LS8C - default "sam4ls8b" if SOC_PART_NUMBER_SAM4LS8B - default "sam4ls8a" if SOC_PART_NUMBER_SAM4LS8A - default "sam4ls4c" if SOC_PART_NUMBER_SAM4LS4C - default "sam4ls4b" if SOC_PART_NUMBER_SAM4LS4B - default "sam4ls4a" if SOC_PART_NUMBER_SAM4LS4A - default "sam4ls2c" if SOC_PART_NUMBER_SAM4LS2C - default "sam4ls2b" if SOC_PART_NUMBER_SAM4LS2B - default "sam4ls2a" if SOC_PART_NUMBER_SAM4LS2A - default "sam4lc8c" if SOC_PART_NUMBER_SAM4LC8C - default "sam4lc8b" if SOC_PART_NUMBER_SAM4LC8B - default "sam4lc8a" if SOC_PART_NUMBER_SAM4LC8A - default "sam4lc4c" if SOC_PART_NUMBER_SAM4LC4C - default "sam4lc4b" if SOC_PART_NUMBER_SAM4LC4B - default "sam4lc4a" if SOC_PART_NUMBER_SAM4LC4A - default "sam4lc2c" if SOC_PART_NUMBER_SAM4LC2C - default "sam4lc2b" if SOC_PART_NUMBER_SAM4LC2B - default "sam4lc2a" if SOC_PART_NUMBER_SAM4LC2A - -# -# SAM4L family has total 43 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 80 - -# Configure default device drivers. If a feature is supported by more than one -# device driver the default configuration will be placed in the board defconfig -# file. - -config USART_SAM - default y - depends on SERIAL - -endif # SOC_SERIES_SAM4L diff --git a/soc/arm/atmel_sam/sam4l/Kconfig.series b/soc/arm/atmel_sam/sam4l/Kconfig.series deleted file mode 100644 index 0a8192f5bd9fdd..00000000000000 --- a/soc/arm/atmel_sam/sam4l/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2020-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM4L - bool "Atmel SAM4L MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM4L Cortex-M4 microcontrollers. - Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B, - SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B, - SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B, - SAM4LC2A diff --git a/soc/arm/atmel_sam/sam4l/Kconfig.soc b/soc/arm/atmel_sam/sam4l/Kconfig.soc deleted file mode 100644 index 358cfc76042c1c..00000000000000 --- a/soc/arm/atmel_sam/sam4l/Kconfig.soc +++ /dev/null @@ -1,61 +0,0 @@ -# Copyright (c) 2020 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM4L MCU Selection" - depends on SOC_SERIES_SAM4L - - config SOC_PART_NUMBER_SAM4LS8C - bool "SAM4LS8C" - - config SOC_PART_NUMBER_SAM4LS8B - bool "SAM4LS8B" - - config SOC_PART_NUMBER_SAM4LS8A - bool "SAM4LS8A" - - config SOC_PART_NUMBER_SAM4LS4C - bool "SAM4LS4C" - - config SOC_PART_NUMBER_SAM4LS4B - bool "SAM4LS4B" - - config SOC_PART_NUMBER_SAM4LS4A - bool "SAM4LS4A" - - config SOC_PART_NUMBER_SAM4LS2C - bool "SAM4LS2C" - - config SOC_PART_NUMBER_SAM4LS2B - bool "SAM4LS2B" - - config SOC_PART_NUMBER_SAM4LS2A - bool "SAM4LS2A" - - config SOC_PART_NUMBER_SAM4LC8C - bool "SAM4LC8C" - - config SOC_PART_NUMBER_SAM4LC8B - bool "SAM4LC8B" - - config SOC_PART_NUMBER_SAM4LC8A - bool "SAM4LC8A" - - config SOC_PART_NUMBER_SAM4LC4C - bool "SAM4LC4C" - - config SOC_PART_NUMBER_SAM4LC4B - bool "SAM4LC4B" - - config SOC_PART_NUMBER_SAM4LC4A - bool "SAM4LC4A" - - config SOC_PART_NUMBER_SAM4LC2C - bool "SAM4LC2C" - - config SOC_PART_NUMBER_SAM4LC2B - bool "SAM4LC2B" - - config SOC_PART_NUMBER_SAM4LC2A - bool "SAM4LC2A" -endchoice diff --git a/soc/arm/atmel_sam/sam4l/soc.h b/soc/arm/atmel_sam/sam4l/soc.h deleted file mode 100644 index f044fc8363c81b..00000000000000 --- a/soc/arm/atmel_sam/sam4l/soc.h +++ /dev/null @@ -1,223 +0,0 @@ -/* - * Copyright (c) 2020 Gerson Fernando Budke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM4L family processors. - */ - -#ifndef _ATMEL_SAM4L_SOC_H_ -#define _ATMEL_SAM4L_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined(CONFIG_SOC_PART_NUMBER_SAM4LS8C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS8A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS4A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LS2A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC8A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC4A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4LC2A) -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -/** Oscillator identifiers - * External Oscillator 0 - * External 32 kHz oscillator - * Internal 32 kHz RC oscillator - * Internal 80 MHz RC oscillator - * Internal 4-8-12 MHz RCFAST oscillator - * Internal 1 MHz RC oscillator - * Internal System RC oscillator - */ -#define OSC_ID_OSC0 0 -#define OSC_ID_OSC32 1 -#define OSC_ID_RC32K 2 -#define OSC_ID_RC80M 3 -#define OSC_ID_RCFAST 4 -#define OSC_ID_RC1M 5 -#define OSC_ID_RCSYS 6 - -/** System clock source - * System RC oscillator - * Oscillator 0 - * Phase Locked Loop 0 - * Digital Frequency Locked Loop - * 80 MHz RC oscillator - * 4-8-12 MHz RC oscillator - * 1 MHz RC oscillator - */ -#define OSC_SRC_RCSYS 0 -#define OSC_SRC_OSC0 1 -#define OSC_SRC_PLL0 2 -#define OSC_SRC_DFLL 3 -#define OSC_SRC_RC80M 4 -#define OSC_SRC_RCFAST 5 -#define OSC_SRC_RC1M 6 - -#define PM_CLOCK_MASK(bus, per) ((bus << 5) + per) - -/** Bus index of maskable module clocks. Peripheral ids are defined out of - * order. It start from PBA up to PBD, then move to HSB, and finally CPU. - */ -#define PM_CLK_GRP_CPU 5 -#define PM_CLK_GRP_HSB 4 -#define PM_CLK_GRP_PBA 0 -#define PM_CLK_GRP_PBB 1 -#define PM_CLK_GRP_PBC 2 -#define PM_CLK_GRP_PBD 3 - -/** Clocks derived from the CPU clock - */ -#define SYSCLK_OCD 0 - -/** Clocks derived from the HSB clock - */ -#define SYSCLK_PDCA_HSB 0 -#define SYSCLK_HFLASHC_DATA 1 -#define SYSCLK_HRAMC1_DATA 2 -#define SYSCLK_USBC_DATA 3 -#define SYSCLK_CRCCU_DATA 4 -#define SYSCLK_PBA_BRIDGE 5 -#define SYSCLK_PBB_BRIDGE 6 -#define SYSCLK_PBC_BRIDGE 7 -#define SYSCLK_PBD_BRIDGE 8 -#define SYSCLK_AESA_HSB 9 - -/** Clocks derived from the PBA clock - */ -#define SYSCLK_IISC 0 -#define SYSCLK_SPI 1 -#define SYSCLK_TC0 2 -#define SYSCLK_TC1 3 -#define SYSCLK_TWIM0 4 -#define SYSCLK_TWIS0 5 -#define SYSCLK_TWIM1 6 -#define SYSCLK_TWIS1 7 -#define SYSCLK_USART0 8 -#define SYSCLK_USART1 9 -#define SYSCLK_USART2 10 -#define SYSCLK_USART3 11 -#define SYSCLK_ADCIFE 12 -#define SYSCLK_DACC 13 -#define SYSCLK_ACIFC 14 -#define SYSCLK_GLOC 15 -#define SYSCLK_ABDACB 16 -#define SYSCLK_TRNG 17 -#define SYSCLK_PARC 18 -#define SYSCLK_CATB 19 -#define SYSCLK_TWIM2 21 -#define SYSCLK_TWIM3 22 -#define SYSCLK_LCDCA 23 - -/** Clocks derived from the PBB clock - */ -#define SYSCLK_HFLASHC_REGS 0 -#define SYSCLK_HRAMC1_REGS 1 -#define SYSCLK_HMATRIX 2 -#define SYSCLK_PDCA_PB 3 -#define SYSCLK_CRCCU_REGS 4 -#define SYSCLK_USBC_REGS 5 -#define SYSCLK_PEVC 6 - -/** Clocks derived from the PBC clock - */ -#define SYSCLK_PM 0 -#define SYSCLK_CHIPID 1 -#define SYSCLK_SCIF 2 -#define SYSCLK_FREQM 3 -#define SYSCLK_GPIO 4 - -/** Clocks derived from the PBD clock - */ -#define SYSCLK_BPM 0 -#define SYSCLK_BSCIF 1 -#define SYSCLK_AST 2 -#define SYSCLK_WDT 3 -#define SYSCLK_EIC 4 -#define SYSCLK_PICOUART 5 - -/** Divided clock mask derived from the PBA clock - */ -#define PBA_DIVMASK_TIMER_CLOCK2 (1u << 0) -#define PBA_DIVMASK_TIMER_CLOCK3 (1u << 2) -#define PBA_DIVMASK_CLK_USART (1u << 2) -#define PBA_DIVMASK_TIMER_CLOCK4 (1u << 4) -#define PBA_DIVMASK_TIMER_CLOCK5 (1u << 6) -#define PBA_DIVMASK_Msk (0x7Fu << 0) - -/** Generic Clock Instances - * 0- DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF) - * 1- DFLLIF dithering and SSG reference and GCLK1 pin (CLK_DFLLIF_DITHER) - * 2- AST and GCLK2 pin - * 3- CATB and GCLK3 pin - * 4- AESA - * 5- GLOC, TC0 and RC32KIFB_REF - * 6- ABDACB and IISC - * 7- USBC - * 8- TC1 and PEVC[0] - * 9- PLL0 and PEVC[1] - * 10- ADCIFE - * 11- Master generic clock. Can be used as source for other generic clocks. - */ -#define GEN_CLK_DFLL_REF 0 -#define GEN_CLK_DFLL_DITHER 1 -#define GEN_CLK_AST 2 -#define GEN_CLK_CATB 3 -#define GEN_CLK_AESA 4 -#define GEN_CLK_GLOC 5 -#define GEN_CLK_ABDACB 6 -#define GEN_CLK_USBC 7 -#define GEN_CLK_TC1_PEVC0 8 -#define GEN_CLK_PLL0_PEVC1 9 -#define GEN_CLK_ADCIFE 10 -#define GEN_CLK_MASTER_GEN 11 - -#endif /* !_ASMLANGUAGE */ - -#endif /* _ATMEL_SAM4L_SOC_H_ */ diff --git a/soc/arm/atmel_sam/sam4s/CMakeLists.txt b/soc/arm/atmel_sam/sam4s/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9bc8..00000000000000 --- a/soc/arm/atmel_sam/sam4s/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series b/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series deleted file mode 100644 index 78afd905d6348f..00000000000000 --- a/soc/arm/atmel_sam/sam4s/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Atmel SAM4S MCU series configuration options - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAM4S - -config SOC_SERIES - default "sam4s" - -config SOC_PART_NUMBER - default "sam4s16c" if SOC_PART_NUMBER_SAM4S16C - default "sam4sa16c" if SOC_PART_NUMBER_SAM4SA16C - default "sam4s16b" if SOC_PART_NUMBER_SAM4S16B - default "sam4s8c" if SOC_PART_NUMBER_SAM4S8C - default "sam4s8b" if SOC_PART_NUMBER_SAM4S8B - default "sam4s4c" if SOC_PART_NUMBER_SAM4S4C - default "sam4s4b" if SOC_PART_NUMBER_SAM4S4B - default "sam4s4a" if SOC_PART_NUMBER_SAM4S4A - default "sam4s2c" if SOC_PART_NUMBER_SAM4S2C - default "sam4s2b" if SOC_PART_NUMBER_SAM4S2B - default "sam4s2a" if SOC_PART_NUMBER_SAM4S2A - -# -# SAM4S family has total 35 peripherals capable of -# generating interrupts. -# -config NUM_IRQS - default 35 - -endif # SOC_SERIES_SAM4S diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.series b/soc/arm/atmel_sam/sam4s/Kconfig.series deleted file mode 100644 index f591d96ba88e3a..00000000000000 --- a/soc/arm/atmel_sam/sam4s/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Atmel SAM4S MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# Copyright (c) 2020-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAM4S - bool "Atmel SAM4S MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_POWEROFF - help - Enable support for Atmel SAM4S Cortex-M4 microcontrollers. - Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B, - SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A diff --git a/soc/arm/atmel_sam/sam4s/Kconfig.soc b/soc/arm/atmel_sam/sam4s/Kconfig.soc deleted file mode 100644 index c8c9dd9e21e4a5..00000000000000 --- a/soc/arm/atmel_sam/sam4s/Kconfig.soc +++ /dev/null @@ -1,111 +0,0 @@ -# Atmel SAM4S MCU series - -# Copyright (c) 2017 Justin Watson -# Copyright (c) 2018 Vincent van der Locht -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM4S MCU Selection" - depends on SOC_SERIES_SAM4S - - config SOC_PART_NUMBER_SAM4S16C - bool "SAM4S16C" - - config SOC_PART_NUMBER_SAM4SA16C - bool "SAM4SA16C" - - config SOC_PART_NUMBER_SAM4S16B - bool "SAM4S16B" - - config SOC_PART_NUMBER_SAM4S8C - bool "SAM4S8C" - - config SOC_PART_NUMBER_SAM4S8B - bool "SAM4S8B" - - config SOC_PART_NUMBER_SAM4S4C - bool "SAM4S4C" - - config SOC_PART_NUMBER_SAM4S4B - bool "SAM4S4B" - - config SOC_PART_NUMBER_SAM4S4A - bool "SAM4S4A" - - config SOC_PART_NUMBER_SAM4S2C - bool "SAM4S2C" - - config SOC_PART_NUMBER_SAM4S2B - bool "SAM4S2B" - - config SOC_PART_NUMBER_SAM4S2A - bool "SAM4S2A" - -endchoice - -if SOC_SERIES_SAM4S - -config SOC_ATMEL_SAM4S_EXT_SLCK - bool "Atmel SAM4S to use external crystal oscillator for slow clock" - help - Says y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAM4S_EXT_MAINCK - bool "Atmel SAM4S to use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Says y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAM4S_PLLA_MULA - hex "PLL MULA" - default 0x09 - help - This is the multiplier (MULA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4S_PLLA_DIVA - hex "PLL DIVA" - default 0x01 - help - This is the divider (DIVA) used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - With default of MULA == 9, and DIVA == 1, - PLL is running at 10 times of main clock. - -config SOC_ATMEL_SAM4S_WAIT_MODE - bool "Atmel SAM4S goes to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAM4S_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -endif # SOC_SERIES_SAM4S diff --git a/soc/arm/atmel_sam/sam4s/soc.c b/soc/arm/atmel_sam/sam4s/soc.c deleted file mode 100644 index 5efaa35e894986..00000000000000 --- a/soc/arm/atmel_sam/sam4s/soc.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2023 Gerson Fernando Budke - * Copyright (c) 2023 Basalte bv - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Atmel SAM4S MCU series initialization code - * - * This module provides routines to initialize and support board-level hardware - * for the Atmel SAM4S series processor. - */ - -#include -#include -#include - -/** - * @brief Setup various clock on SoC at boot time. - * - * Setup the SoC clocks according to section 28.12 in datasheet. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC0->EEFC_FMR = EEFC_FMR_FWS(0); -#if defined(ID_EFC1) - EFC1->EEFC_FMR = EEFC_FMR_FWS(0); -#endif - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet. - * This is set to the highest number of read cycles because it won't - * hurt lower clock frequencies. However, a high frequency with too - * few read cycles could cause flash read problems. FWS 5 (6 cycles) - * is the safe setting for all of this SoCs usable frequencies. - */ - EFC0->EEFC_FMR = EEFC_FMR_FWS(5); -#if defined(ID_EFC1) - EFC1->EEFC_FMR = EEFC_FMR_FWS(5); -#endif - - /* - * Setup PLLA - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM4S_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAM4S_PLLA_DIVA); - - /* - * Final setup of the Master Clock - */ - - /* prescaler has to be set before PLL lock */ - soc_pmc_mck_set_prescaler(1); - - /* Select PLL as Master Clock source. */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM4S_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - - /* Setup system clocks. */ - clock_init(); -} diff --git a/soc/arm/atmel_sam/sam4s/soc.h b/soc/arm/atmel_sam/sam4s/soc.h deleted file mode 100644 index ec3ab20471e87b..00000000000000 --- a/soc/arm/atmel_sam/sam4s/soc.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2020 Gerson Fernando Budke - * Copyright (c) 2018 Vincent van der Locht - * Copyright (c) 2017 Justin Watson - * Copyright (c) 2016 Intel Corporation. - * Copyright (c) 2013-2015 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file SoC configuration macros for the Atmel SAM4S family processors. - */ - -#ifndef _ATMEL_SAM4S_SOC_H_ -#define _ATMEL_SAM4S_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined(CONFIG_SOC_PART_NUMBER_SAM4S16C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4SA16C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S8C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S8B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S4A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2C) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAM4S2A) -#include -#else -#error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ - -#endif /* !_ASMLANGUAGE */ - -#endif /* _ATMEL_SAM4S_SOC_H_ */ diff --git a/soc/arm/atmel_sam/same70/CMakeLists.txt b/soc/arm/atmel_sam/same70/CMakeLists.txt deleted file mode 100644 index 8373266d4ec020..00000000000000 --- a/soc/arm/atmel_sam/same70/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - soc_config.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/same70/Kconfig.defconfig.series b/soc/arm/atmel_sam/same70/Kconfig.defconfig.series deleted file mode 100644 index f024e0d0616193..00000000000000 --- a/soc/arm/atmel_sam/same70/Kconfig.defconfig.series +++ /dev/null @@ -1,41 +0,0 @@ -# Atmel SAM E70 MCU series configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME70 - -config SOC_SERIES - default "same70" - -config SOC_PART_NUMBER - default "same70q21" if SOC_PART_NUMBER_SAME70Q21 - default "same70q20" if SOC_PART_NUMBER_SAME70Q20 - default "same70q19" if SOC_PART_NUMBER_SAME70Q19 - default "same70n21" if SOC_PART_NUMBER_SAME70N21 - default "same70n20" if SOC_PART_NUMBER_SAME70N20 - default "same70n19" if SOC_PART_NUMBER_SAME70N19 - default "same70j21" if SOC_PART_NUMBER_SAME70J21 - default "same70j20" if SOC_PART_NUMBER_SAME70J20 - default "same70j19" if SOC_PART_NUMBER_SAME70J19 - default "same70q21b" if SOC_PART_NUMBER_SAME70Q21B - default "same70q20b" if SOC_PART_NUMBER_SAME70Q20B - default "same70q19b" if SOC_PART_NUMBER_SAME70Q19B - default "same70n21b" if SOC_PART_NUMBER_SAME70N21B - default "same70n20b" if SOC_PART_NUMBER_SAME70N20B - default "same70n19b" if SOC_PART_NUMBER_SAME70N19B - default "same70j21b" if SOC_PART_NUMBER_SAME70J21B - default "same70j20b" if SOC_PART_NUMBER_SAME70J20B - default "same70j19b" if SOC_PART_NUMBER_SAME70J19B - -# -# SAM E70 family has in total 71 peripherals capable of generating interrupts -# for the revision A and 74 for the revision B (not all Peripheral Identifiers -# are used). -# -config NUM_IRQS - default 74 if SOC_ATMEL_SAME70_REVB - default 71 - -endif # SOC_SERIES_SAME70 diff --git a/soc/arm/atmel_sam/same70/Kconfig.series b/soc/arm/atmel_sam/same70/Kconfig.series deleted file mode 100644 index 4e7d6aa396e94d..00000000000000 --- a/soc/arm/atmel_sam/same70/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Atmel SAM E70 MCU series - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME70 - bool "Atmel SAME70 MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select SOC_FAMILY_SAM - select INIT_ARCH_HW_AT_BOOT - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_SWO - select XIP - select HAS_POWEROFF - help - Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers. - Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20, - SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B, - SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B, - SAME70Q20B, SAME70Q21B diff --git a/soc/arm/atmel_sam/same70/Kconfig.soc b/soc/arm/atmel_sam/same70/Kconfig.soc deleted file mode 100644 index c396e1e59d7255..00000000000000 --- a/soc/arm/atmel_sam/same70/Kconfig.soc +++ /dev/null @@ -1,167 +0,0 @@ -# Atmel SAM E70 MCU series - -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME70 MCU Selection" - depends on SOC_SERIES_SAME70 - - config SOC_PART_NUMBER_SAME70Q21 - bool "SAME70Q21" - - config SOC_PART_NUMBER_SAME70Q20 - bool "SAME70Q20" - - config SOC_PART_NUMBER_SAME70Q19 - bool "SAME70Q19" - - config SOC_PART_NUMBER_SAME70N21 - bool "SAME70N21" - - config SOC_PART_NUMBER_SAME70N20 - bool "SAME70N20" - - config SOC_PART_NUMBER_SAME70N19 - bool "SAME70N19" - - config SOC_PART_NUMBER_SAME70J21 - bool "SAME70J21" - - config SOC_PART_NUMBER_SAME70J20 - bool "SAME70J20" - - config SOC_PART_NUMBER_SAME70J19 - bool "SAME70J19" - - config SOC_PART_NUMBER_SAME70Q21B - bool "SAME70Q21B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70Q20B - bool "SAME70Q20B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70Q19B - bool "SAME70Q19B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70N21B - bool "SAME70N21B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70N20B - bool "SAME70N20B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70N19B - bool "SAME70N19B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70J21B - bool "SAME70J21B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70J20B - bool "SAME70J20B" - select SOC_ATMEL_SAME70_REVB - - config SOC_PART_NUMBER_SAME70J19B - bool "SAME70J19B" - select SOC_ATMEL_SAME70_REVB -endchoice - -if SOC_SERIES_SAME70 - -config SOC_ATMEL_SAME70_REVB - bool - -config SOC_ATMEL_SAME70_EXT_SLCK - bool "Use external crystal oscillator for slow clock" - help - Say y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAME70_EXT_MAINCK - bool "Use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Say y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAME70_MDIV - int "MDIV" - default 2 - range 1 4 - help - This divisor defines a ratio between processor clock (HCLK) - and master clock (MCK): - MCK = HCLK / MDIV - -config SOC_ATMEL_SAME70_PLLA_MULA - int "PLL MULA" - default 24 - range 1 62 - help - This is the multiplier MULA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting MULA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAME70_PLLA_DIVA - int "PLL DIVA" - default 1 - range 1 255 - help - This is the divider DIVA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting DIVA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAME70_WAIT_MODE - bool "Go to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAME70_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -config SOC_ATMEL_SAME70_DISABLE_ERASE_PIN - bool "Disable ERASE pin" - help - At reset ERASE pin is configured in System IO mode. Asserting the ERASE - pin at '1' will completely erase Flash memory. Setting this option will - switch the pin to general IO mode giving control of the pin to the GPIO - module. - -endif # SOC_SERIES_SAME70 diff --git a/soc/arm/atmel_sam/same70/soc.c b/soc/arm/atmel_sam/same70/soc.c deleted file mode 100644 index 02ebce73c6de90..00000000000000 --- a/soc/arm/atmel_sam/same70/soc.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * Copyright (c) 2023 Gerson Fernando Budke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Atmel SAM E70 MCU initialization code - * - * This file provides routines to initialize and support board-level hardware - * for the Atmel SAM E70 MCU. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL -LOG_MODULE_REGISTER(soc); - -/** - * @brief Setup various clocks on SoC at boot time. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. - * TODO: set FWS based on the actual MCK frequency and VDDIO value - * rather than maximum supported 150 MHz at standard VDDIO=2.7V - */ - EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; - - /* - * Setup PLLA - */ - - /* - * PLL clock = Main * (MULA + 1) / DIVA - * - * By default, MULA == 24, DIVA == 1. - * With main crystal running at 12 MHz, - * PLL = 12 * (24 + 1) / 1 = 300 MHz - * - * With Processor Clock prescaler at 1 - * Processor Clock (HCLK)=300 MHz. - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAME70_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA); - - - soc_pmc_enable_upllck(0x3Fu); - - /* - * Final setup of the Master Clock - */ - - /* Setting PLLA as MCK, first prescaler, then divider and source last */ - soc_pmc_mck_set_prescaler(1); - soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAME70_MDIV); - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAME70_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - - /* - * DTCM is enabled by default at reset, therefore we have to disable - * it first to get the caches into a state where then the - * sys_cache*-functions can enable them, if requested by the - * configuration. - */ - SCB_DisableDCache(); - - /* - * Enable the caches only if configured to do so. - */ - sys_cache_instr_enable(); - sys_cache_data_enable(); - - /* Setup system clocks */ - clock_init(); -} - -/** - * @brief Perform basic hardware initialization at boot. - * - * This needs to be run at the very beginning. - * So the init priority has to be 0 (zero). - * - * @return 0 - */ -static int atmel_same70_init(void) -{ - /* Check that the CHIP CIDR matches the HAL one */ - if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { - LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", - (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); - } - - return 0; -} - -SYS_INIT(atmel_same70_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam/same70/soc.h b/soc/arm/atmel_sam/same70/soc.h deleted file mode 100644 index ad72b4d2ef0b69..00000000000000 --- a/soc/arm/atmel_sam/same70/soc.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Register access macros for the Atmel SAM E70 MCU. - * - * This file provides register access macros for the Atmel SAM E70 MCU, HAL - * drivers for core peripherals as well as symbols specific to Atmel SAM family. - */ - -#ifndef _ATMEL_SAME70_SOC_H_ -#define _ATMEL_SAME70_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined CONFIG_SOC_PART_NUMBER_SAME70J19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21B -#include -#else - #error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ - (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAME70_MDIV) - -/** UTMI PLL clock (UPLLCK) Frequency */ -#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) - -#endif /* _ASMLANGUAGE */ - -#endif /* _ATMEL_SAME70_SOC_H_ */ diff --git a/soc/arm/atmel_sam/same70/soc_config.c b/soc/arm/atmel_sam/same70/soc_config.c deleted file mode 100644 index 27d71da492078b..00000000000000 --- a/soc/arm/atmel_sam/same70/soc_config.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief System module to support early Atmel SAM E70 MCU configuration - */ - -#include -#include -#include -#include - -/** - * @brief Perform SoC configuration at boot. - * - * This should be run early during the boot process but after basic hardware - * initialization is done. - * - * @return 0 - */ -static int atmel_same70_config(void) -{ -#ifdef CONFIG_SOC_ATMEL_SAME70_DISABLE_ERASE_PIN - /* Disable ERASE function on PB12 pin, this is controlled by Bus Matrix */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; -#endif - - /* In Cortex-M based SoCs JTAG interface can be used to perform - * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug - * interface therefore there is no harm done by disabling the JTAG TDI - * pin by default. - */ - /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Disable PCK3 clock used by ETM module */ - PMC->PMC_SCDR = PMC_SCDR_PCK3; - while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { - ; - } - /* Select PLLA clock as PCK3 clock */ - PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; - /* Enable PCK3 clock */ - PMC->PMC_SCER = PMC_SCER_PCK3; - /* Wait for PCK3 setup to complete */ - while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { - ; - } - /* Enable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; -#else - /* Disable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; -#endif - - return 0; -} - -SYS_INIT(atmel_same70_config, PRE_KERNEL_1, 1); diff --git a/soc/arm/atmel_sam/samv71/CMakeLists.txt b/soc/arm/atmel_sam/samv71/CMakeLists.txt deleted file mode 100644 index 8373266d4ec020..00000000000000 --- a/soc/arm/atmel_sam/samv71/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - soc_config.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series deleted file mode 100644 index 5209139f61c765..00000000000000 --- a/soc/arm/atmel_sam/samv71/Kconfig.defconfig.series +++ /dev/null @@ -1,41 +0,0 @@ -# Atmel SAM V71 MCU series configuration options - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2019-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMV71 - -config SOC_SERIES - default "samv71" - -config SOC_PART_NUMBER - default "samv71q21" if SOC_PART_NUMBER_SAMV71Q21 - default "samv71q20" if SOC_PART_NUMBER_SAMV71Q20 - default "samv71q19" if SOC_PART_NUMBER_SAMV71Q19 - default "samv71n21" if SOC_PART_NUMBER_SAMV71N21 - default "samv71n20" if SOC_PART_NUMBER_SAMV71N20 - default "samv71n19" if SOC_PART_NUMBER_SAMV71N19 - default "samv71j21" if SOC_PART_NUMBER_SAMV71J21 - default "samv71j20" if SOC_PART_NUMBER_SAMV71J20 - default "samv71j19" if SOC_PART_NUMBER_SAMV71J19 - default "samv71q21b" if SOC_PART_NUMBER_SAMV71Q21B - default "samv71q20b" if SOC_PART_NUMBER_SAMV71Q20B - default "samv71q19b" if SOC_PART_NUMBER_SAMV71Q19B - default "samv71n21b" if SOC_PART_NUMBER_SAMV71N21B - default "samv71n20b" if SOC_PART_NUMBER_SAMV71N20B - default "samv71n19b" if SOC_PART_NUMBER_SAMV71N19B - default "samv71j21b" if SOC_PART_NUMBER_SAMV71J21B - default "samv71j20b" if SOC_PART_NUMBER_SAMV71J20B - default "samv71j19b" if SOC_PART_NUMBER_SAMV71J19B - -# -# SAM V71 family has in total 71 peripherals capable of generating interrupts -# for the revision A and 74 for the revision B (not all Peripheral Identifiers -# are used). -# -config NUM_IRQS - default 74 if SOC_ATMEL_SAMV71_REVB - default 71 - -endif # SOC_SERIES_SAMV71 diff --git a/soc/arm/atmel_sam/samv71/Kconfig.series b/soc/arm/atmel_sam/samv71/Kconfig.series deleted file mode 100644 index cadee35acb5219..00000000000000 --- a/soc/arm/atmel_sam/samv71/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Atmel SAM V71 MCU series - -# Copyright (c) 2016 Piotr Mienkowski -# Copyright (c) 2019-2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMV71 - bool "Atmel SAMV71 MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select SOC_FAMILY_SAM - select INIT_ARCH_HW_AT_BOOT - select PLATFORM_SPECIFIC_INIT - select ASF - select HAS_SWO - select XIP - select HAS_POWEROFF - help - Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers. - Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20, - SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B, - SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B, - SAMV71Q20B, SAMV71Q21B diff --git a/soc/arm/atmel_sam/samv71/Kconfig.soc b/soc/arm/atmel_sam/samv71/Kconfig.soc deleted file mode 100644 index c8e7d60438c720..00000000000000 --- a/soc/arm/atmel_sam/samv71/Kconfig.soc +++ /dev/null @@ -1,168 +0,0 @@ -# Atmel SAM V71 MCU series - -# Copyright (c) 2019 Gerson Fernando Budke -# Copyright (c) 2016 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMV71 MCU Selection" - depends on SOC_SERIES_SAMV71 - - config SOC_PART_NUMBER_SAMV71Q21 - bool "SAMV71Q21" - - config SOC_PART_NUMBER_SAMV71Q20 - bool "SAMV71Q20" - - config SOC_PART_NUMBER_SAMV71Q19 - bool "SAMV71Q19" - - config SOC_PART_NUMBER_SAMV71N21 - bool "SAMV71N21" - - config SOC_PART_NUMBER_SAMV71N20 - bool "SAMV71N20" - - config SOC_PART_NUMBER_SAMV71N19 - bool "SAMV71N19" - - config SOC_PART_NUMBER_SAMV71J21 - bool "SAMV71J21" - - config SOC_PART_NUMBER_SAMV71J20 - bool "SAMV71J20" - - config SOC_PART_NUMBER_SAMV71J19 - bool "SAMV71J19" - - config SOC_PART_NUMBER_SAMV71Q21B - bool "SAMV71Q21B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71Q20B - bool "SAMV71Q20B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71Q19B - bool "SAMV71Q19B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71N21B - bool "SAMV71N21B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71N20B - bool "SAMV71N20B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71N19B - bool "SAMV71N19B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71J21B - bool "SAMV71J21B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71J20B - bool "SAMV71J20B" - select SOC_ATMEL_SAMV71_REVB - - config SOC_PART_NUMBER_SAMV71J19B - bool "SAMV71J19B" - select SOC_ATMEL_SAMV71_REVB -endchoice - -if SOC_SERIES_SAMV71 - -config SOC_ATMEL_SAMV71_REVB - bool - -config SOC_ATMEL_SAMV71_EXT_SLCK - bool "Use external crystal oscillator for slow clock" - help - Say y if you want to use external 32 kHz crystal - oscillator to drive the slow clock. Note that this - adds a few seconds to boot time, as the crystal - needs to stabilize after power-up. - - Says n if you do not need accurate and precise timers. - The slow clock will be driven by the internal fast - RC oscillator running at 32 kHz. - -config SOC_ATMEL_SAMV71_EXT_MAINCK - bool "Use external crystal oscillator for main clock" - help - The main clock is being used to drive the PLL, and - thus driving the processor clock. - - Say y if you want to use external crystal oscillator - to drive the main clock. Note that this adds about - a second to boot time, as the crystal needs to - stabilize after power-up. - - The crystal used here can be from 3 to 20 MHz. - - Says n here will use the internal fast RC oscillator - running at 12 MHz. - -config SOC_ATMEL_SAMV71_MDIV - int "MDIV" - default 2 - range 1 4 - help - This divisor defines a ratio between processor clock (HCLK) - and master clock (MCK): - MCK = HCLK / MDIV - -config SOC_ATMEL_SAMV71_PLLA_MULA - int "PLL MULA" - default 24 - range 1 62 - help - This is the multiplier MULA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting MULA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAMV71_PLLA_DIVA - int "PLL DIVA" - default 1 - range 1 255 - help - This is the divider DIVA used by the PLL. - The processor clock is (MAINCK * (MULA + 1) / DIVA). - - Board config file can override this settings - for a particular board. - - Setting DIVA=0 would disable PLL at boot, this is currently - not supported. - - With default of MULA == 24, and DIVA == 1, - PLL is running at 25 times the main clock frequency. - -config SOC_ATMEL_SAMV71_WAIT_MODE - bool "Go to Wait mode instead of Sleep mode" - depends on SOC_ATMEL_SAMV71_EXT_MAINCK - default y if DEBUG - help - For JTAG debugging CPU clock (HCLK) should not stop. In order - to achieve this, make CPU go to Wait mode instead of Sleep - mode while using external crystal oscillator for main clock. - -config SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN - bool "Disable ERASE pin" - help - At reset ERASE pin is configured in System IO mode. Asserting the ERASE - pin at '1' will completely erase Flash memory. Setting this option will - switch the pin to general IO mode giving control of the pin to the GPIO - module. - -endif # SOC_SERIES_SAMV71 diff --git a/soc/arm/atmel_sam/samv71/soc.c b/soc/arm/atmel_sam/samv71/soc.c deleted file mode 100644 index 6e82b9fe2f63c6..00000000000000 --- a/soc/arm/atmel_sam/samv71/soc.c +++ /dev/null @@ -1,153 +0,0 @@ -/* - * Copyright (c) 2016 Piotr Mienkowski - * Copyright (c) 2019-2023 Gerson Fernando Budke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Atmel SAM V71 MCU initialization code - * - * This file provides routines to initialize and support board-level hardware - * for the Atmel SAM V71 MCU. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL -LOG_MODULE_REGISTER(soc); - -/** - * @brief Setup various clocks on SoC at boot time. - * - * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. - * It is assumed that the relevant registers are at their reset value. - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Switch the main clock to the internal OSC with 12MHz */ - soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); - - /* Switch MCK (Master Clock) to the main clock */ - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); - - EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; - - soc_pmc_enable_clock_failure_detector(); - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_SLCK)) { - soc_supc_slow_clock_select_crystal_osc(); - } - - - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK)) { - /* - * Setup main external crystal oscillator. - */ - - /* We select maximum setup time. - * While start up time could be shortened - * this optimization is not deemed - * critical now. - */ - soc_pmc_switch_mainck_to_xtal(false, 0xff); - } - - /* - * Set FWS (Flash Wait State) value before increasing Master Clock - * (MCK) frequency. - * TODO: set FWS based on the actual MCK frequency and VDDIO value - * rather than maximum supported 150 MHz at standard VDDIO=2.7V - */ - EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; - - /* - * Setup PLLA - */ - - /* - * PLL clock = Main * (MULA + 1) / DIVA - * - * By default, MULA == 24, DIVA == 1. - * With main crystal running at 12 MHz, - * PLL = 12 * (24 + 1) / 1 = 300 MHz - * - * With Processor Clock prescaler at 1 - * Processor Clock (HCLK)=300 MHz. - */ - soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAMV71_PLLA_MULA, 0x3Fu, - CONFIG_SOC_ATMEL_SAMV71_PLLA_DIVA); - - - soc_pmc_enable_upllck(0x3Fu); - - /* - * Final setup of the Master Clock - */ - - /* Setting PLLA as MCK, first prescaler, then divider and source last */ - soc_pmc_mck_set_prescaler(1); - soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAMV71_MDIV); - soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); - - /* Disable internal fast RC if we have an external crystal oscillator */ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_EXT_MAINCK)) { - soc_pmc_osc_disable_fastrc(); - } -} - -void z_arm_platform_init(void) -{ - if (IS_ENABLED(CONFIG_SOC_ATMEL_SAMV71_WAIT_MODE)) { - /* - * Instruct CPU to enter Wait mode instead of Sleep mode to - * keep Processor Clock (HCLK) and thus be able to debug - * CPU using JTAG. - */ - soc_pmc_enable_waitmode(); - } - - /* - * DTCM is enabled by default at reset, therefore we have to disable - * it first to get the caches into a state where then the - * sys_cache*-functions can enable them, if requested by the - * configuration. - */ - SCB_DisableDCache(); - - /* - * Enable the caches only if configured to do so. - */ - sys_cache_instr_enable(); - sys_cache_data_enable(); - - /* Setup system clocks */ - clock_init(); -} - -/** - * @brief Perform basic hardware initialization at boot. - * - * This needs to be run at the very beginning. - * So the init priority has to be 0 (zero). - * - * @return 0 - */ -static int atmel_samv71_init(void) -{ - /* Check that the CHIP CIDR matches the HAL one */ - if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { - LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", - (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); - } - - return 0; -} - -SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/atmel_sam/samv71/soc.h b/soc/arm/atmel_sam/samv71/soc.h deleted file mode 100644 index 4c85be42136075..00000000000000 --- a/soc/arm/atmel_sam/samv71/soc.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2019 Gerson Fernando Budke - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Register access macros for the Atmel SAM V71 MCU. - * - * This file provides register access macros for the Atmel SAM V71 MCU, HAL - * drivers for core peripherals as well as symbols specific to Atmel SAM family. - */ - -#ifndef _ATMEL_SAMV71_SOC_H_ -#define _ATMEL_SAMV71_SOC_H_ - -#include - -#ifndef _ASMLANGUAGE - - -#define DONT_USE_CMSIS_INIT -#define DONT_USE_PREDEFINED_CORE_HANDLERS -#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS - -#if defined CONFIG_SOC_PART_NUMBER_SAMV71J19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21 -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71J21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71N21B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q19B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q20B -#include -#elif defined CONFIG_SOC_PART_NUMBER_SAMV71Q21B -#include -#else - #error Library does not support the specified device. -#endif - -#include "../common/soc_pmc.h" -#include "../common/soc_gpio.h" -#include "../common/soc_supc.h" -#include "../common/atmel_sam_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ - (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAMV71_MDIV) - -/** UTMI PLL clock (UPLLCK) Frequency */ -#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) - -#endif /* _ASMLANGUAGE */ - -#include "pwm_fixup.h" - -#endif /* _ATMEL_SAMV71_SOC_H_ */ diff --git a/soc/arm/atmel_sam/samv71/soc_config.c b/soc/arm/atmel_sam/samv71/soc_config.c deleted file mode 100644 index 2bcff027539840..00000000000000 --- a/soc/arm/atmel_sam/samv71/soc_config.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (c) 2019 Gerson Fernando Budke - * Copyright (c) 2016 Piotr Mienkowski - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief System module to support early Atmel SAM V71 MCU configuration - */ - -#include -#include -#include -#include - -/** - * @brief Perform SoC configuration at boot. - * - * This should be run early during the boot process but after basic hardware - * initialization is done. - * - * @return 0 - */ -static int atmel_samv71_config(void) -{ -#ifdef CONFIG_SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN - /* Disable ERASE function on PB12 pin, this is controlled by Bus - * Matrix - */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; -#endif - - /* In Cortex-M based SoCs JTAG interface can be used to perform - * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug - * interface therefore there is no harm done by disabling the JTAG TDI - * pin by default. - */ - /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix - */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Disable PCK3 clock used by ETM module */ - PMC->PMC_SCDR = PMC_SCDR_PCK3; - while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { - ; - } - /* Select PLLA clock as PCK3 clock */ - PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; - /* Enable PCK3 clock */ - PMC->PMC_SCER = PMC_SCER_PCK3; - /* Wait for PCK3 setup to complete */ - while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { - ; - } - /* Enable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; -#else - /* Disable TDO/TRACESWO function on PB5 pin */ - MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; -#endif - - return 0; -} - -SYS_INIT(atmel_samv71_config, PRE_KERNEL_1, 1); diff --git a/soc/arm/atmel_sam0/CMakeLists.txt b/soc/arm/atmel_sam0/CMakeLists.txt deleted file mode 100644 index 1af186063c9190..00000000000000 --- a/soc/arm/atmel_sam0/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Makefile - Atmel SAM0 MCU family -# -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -add_subdirectory(common) diff --git a/soc/arm/atmel_sam0/Kconfig b/soc/arm/atmel_sam0/Kconfig deleted file mode 100644 index 47c8d180027805..00000000000000 --- a/soc/arm/atmel_sam0/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Atmel SAM0 MCU family configuration options - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SAM0 - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_SAM0 - -config SOC_FAMILY - string - default "atmel_sam0" - -source "soc/arm/atmel_sam0/common/Kconfig.samc2x" -source "soc/arm/atmel_sam0/common/Kconfig.saml2x" -source "soc/arm/atmel_sam0/common/Kconfig.samd2x" -source "soc/arm/atmel_sam0/common/Kconfig.samd5x" -source "soc/arm/atmel_sam0/*/Kconfig.soc" -source "soc/arm/atmel_sam0/Kconfig.soc.revisions" - -endif diff --git a/soc/arm/atmel_sam0/Kconfig.defconfig b/soc/arm/atmel_sam0/Kconfig.defconfig deleted file mode 100644 index b4f25f92c75269..00000000000000 --- a/soc/arm/atmel_sam0/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Atmel SAM0 MCU family default configuration options - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam0/*/Kconfig.defconfig.series" - -if SOC_FAMILY_SAM0 - -config PINCTRL - default y - -endif # SOC_FAMILY_SAM0 diff --git a/soc/arm/atmel_sam0/Kconfig.soc b/soc/arm/atmel_sam0/Kconfig.soc deleted file mode 100644 index 8e81395f5e3cd8..00000000000000 --- a/soc/arm/atmel_sam0/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Atmel SAM0 MCU series selection - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/atmel_sam0/*/Kconfig.series" diff --git a/soc/arm/atmel_sam0/Kconfig.soc.revisions b/soc/arm/atmel_sam0/Kconfig.soc.revisions deleted file mode 100644 index a152528ac7b79a..00000000000000 --- a/soc/arm/atmel_sam0/Kconfig.soc.revisions +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_REVISION_N - bool - -config SOC_SERIES_REVISION - string - default "n" if SOC_SERIES_REVISION_N - default "" diff --git a/soc/arm/atmel_sam0/common/Kconfig.defconfig.series b/soc/arm/atmel_sam0/common/Kconfig.defconfig.series deleted file mode 100644 index 8d9068424fd314..00000000000000 --- a/soc/arm/atmel_sam0/common/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAM0 MCU family configuration options - -# Copyright (c) 2020 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_SAM0 - -config HWINFO_SAM0 - default HWINFO - -if USB_DEVICE_DRIVER - -config HEAP_MEM_POOL_ADD_SIZE_SOC - def_int 1024 - -endif # USB_DEVICE_DRIVER - -endif # SOC_FAMILY_SAM0 diff --git a/soc/arm/atmel_sam0/common/Kconfig.samc2x b/soc/arm/atmel_sam0/common/Kconfig.samc2x deleted file mode 100644 index 3fca87f23ce1d8..00000000000000 --- a/soc/arm/atmel_sam0/common/Kconfig.samc2x +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMC20 || SOC_SERIES_SAMC21 - -endif diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series deleted file mode 100644 index 05a52d3af2a613..00000000000000 --- a/soc/arm/atmel_sam0/samc20/Kconfig.defconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SAMC MCU series configuration options - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMC20 - -config SOC_SERIES - default "samc20" - -config SOC_PART_NUMBER - default "samc20e15a" if SOC_PART_NUMBER_SAMC20E15A - default "samc20e16a" if SOC_PART_NUMBER_SAMC20E16A - default "samc20e17a" if SOC_PART_NUMBER_SAMC20E17A - default "samc20e18a" if SOC_PART_NUMBER_SAMC20E18A - default "samc20g15a" if SOC_PART_NUMBER_SAMC20G15A - default "samc20g16a" if SOC_PART_NUMBER_SAMC20G16A - default "samc20g17a" if SOC_PART_NUMBER_SAMC20G17A - default "samc20g18a" if SOC_PART_NUMBER_SAMC20G18A - default "samc20j15a" if SOC_PART_NUMBER_SAMC20J15A - default "samc20j16a" if SOC_PART_NUMBER_SAMC20J16A - default "samc20j17a" if SOC_PART_NUMBER_SAMC20J17A - default "samc20j17au" if SOC_PART_NUMBER_SAMC20J17AU - default "samc20j18a" if SOC_PART_NUMBER_SAMC20J18A - default "samc20j18au" if SOC_PART_NUMBER_SAMC20J18AU - default "samc20n17a" if SOC_PART_NUMBER_SAMC20N17A - default "samc20n18a" if SOC_PART_NUMBER_SAMC20N18A - -config NUM_IRQS - default 32 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMC20 diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.series b/soc/arm/atmel_sam0/samc20/Kconfig.series deleted file mode 100644 index 4406e1bead4ba4..00000000000000 --- a/soc/arm/atmel_sam0/samc20/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMC20 MCU series - -# Copyright (c) 2022 Kamil Serwus -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMC20 - bool "Atmel SAMC20 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samc20/Kconfig.soc b/soc/arm/atmel_sam0/samc20/Kconfig.soc deleted file mode 100644 index 9ccd4ca2714870..00000000000000 --- a/soc/arm/atmel_sam0/samc20/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# Atmel SAMC MCU series - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMC20 MCU Selection" - depends on SOC_SERIES_SAMC20 - -config SOC_PART_NUMBER_SAMC20E15A - bool "SAMC20E15A" - -config SOC_PART_NUMBER_SAMC20E16A - bool "SAMC20E16A" - -config SOC_PART_NUMBER_SAMC20E17A - bool "SAMC20E17A" - -config SOC_PART_NUMBER_SAMC20E18A - bool "SAMC20E18A" - -config SOC_PART_NUMBER_SAMC20G15A - bool "SAMC20G15A" - -config SOC_PART_NUMBER_SAMC20G16A - bool "SAMC20G16A" - -config SOC_PART_NUMBER_SAMC20G17A - bool "SAMC20G17A" - -config SOC_PART_NUMBER_SAMC20G18A - bool "SAMC20G18A" - -config SOC_PART_NUMBER_SAMC20J15A - bool "SAMC20J15A" - -config SOC_PART_NUMBER_SAMC20J16A - bool "SAMC20J16A" - -config SOC_PART_NUMBER_SAMC20J17A - bool "SAMC20J17A" - -config SOC_PART_NUMBER_SAMC20J17AU - bool "SAMC20J17AU" - -config SOC_PART_NUMBER_SAMC20J18A - bool "SAMC20J18A" - -config SOC_PART_NUMBER_SAMC20J18AU - bool "SAMC20J18AU" - -config SOC_PART_NUMBER_SAMC20N17A - bool "SAMC20N17A" - select SOC_SERIES_REVISION_N - -config SOC_PART_NUMBER_SAMC20N18A - bool "SAMC20N18A" - select SOC_SERIES_REVISION_N - -endchoice diff --git a/soc/arm/atmel_sam0/samc20/soc.h b/soc/arm/atmel_sam0/samc20/soc.h deleted file mode 100644 index 026479c31a5d59..00000000000000 --- a/soc/arm/atmel_sam0/samc20/soc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2022 Kamil Serwus - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMC_SOC_H_ -#define _ATMEL_SAMC_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAMC20E15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J17AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20J18AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC20N18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series deleted file mode 100644 index bc1c4431737f47..00000000000000 --- a/soc/arm/atmel_sam0/samc21/Kconfig.defconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SAMC MCU series configuration options - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMC21 - -config SOC_SERIES - default "samc21" - -config SOC_PART_NUMBER - default "samc21e15a" if SOC_PART_NUMBER_SAMC21E15A - default "samc21e16a" if SOC_PART_NUMBER_SAMC21E16A - default "samc21e17a" if SOC_PART_NUMBER_SAMC21E17A - default "samc21e18a" if SOC_PART_NUMBER_SAMC21E18A - default "samc21g15a" if SOC_PART_NUMBER_SAMC21G15A - default "samc21g16a" if SOC_PART_NUMBER_SAMC21G16A - default "samc21g17a" if SOC_PART_NUMBER_SAMC21G17A - default "samc21g18a" if SOC_PART_NUMBER_SAMC21G18A - default "samc21j15a" if SOC_PART_NUMBER_SAMC21J15A - default "samc21j16a" if SOC_PART_NUMBER_SAMC21J16A - default "samc21j17a" if SOC_PART_NUMBER_SAMC21J17A - default "samc21j17au" if SOC_PART_NUMBER_SAMC21J17AU - default "samc21j18a" if SOC_PART_NUMBER_SAMC21J18A - default "samc21j18au" if SOC_PART_NUMBER_SAMC21J18AU - default "samc21n17a" if SOC_PART_NUMBER_SAMC21N17A - default "samc21n18a" if SOC_PART_NUMBER_SAMC21N18A - -config NUM_IRQS - default 32 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMC21 diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.series b/soc/arm/atmel_sam0/samc21/Kconfig.series deleted file mode 100644 index acb83679e18ea6..00000000000000 --- a/soc/arm/atmel_sam0/samc21/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAMC21 MCU series - -# Copyright (c) 2022 Kamil Serwus -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMC21 - bool "Atmel SAMC21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samc21/Kconfig.soc b/soc/arm/atmel_sam0/samc21/Kconfig.soc deleted file mode 100644 index f3f324abf6c9ee..00000000000000 --- a/soc/arm/atmel_sam0/samc21/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# Atmel SAMC MCU series - -# Copyright (c) 2022 Kamil Serwus -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMC21 MCU Selection" - depends on SOC_SERIES_SAMC21 - -config SOC_PART_NUMBER_SAMC21E15A - bool "SAMC21E15A" - -config SOC_PART_NUMBER_SAMC21E16A - bool "SAMC21E16A" - -config SOC_PART_NUMBER_SAMC21E17A - bool "SAMC21E17A" - -config SOC_PART_NUMBER_SAMC21E18A - bool "SAMC21E18A" - -config SOC_PART_NUMBER_SAMC21G15A - bool "SAMC21G15A" - -config SOC_PART_NUMBER_SAMC21G16A - bool "SAMC21G16A" - -config SOC_PART_NUMBER_SAMC21G17A - bool "SAMC21G17A" - -config SOC_PART_NUMBER_SAMC21G18A - bool "SAMC21G18A" - -config SOC_PART_NUMBER_SAMC21J15A - bool "SAMC21J15A" - -config SOC_PART_NUMBER_SAMC21J16A - bool "SAMC21J16A" - -config SOC_PART_NUMBER_SAMC21J17A - bool "SAMC21J17A" - -config SOC_PART_NUMBER_SAMC21J17AU - bool "SAMC21J17AU" - -config SOC_PART_NUMBER_SAMC21J18A - bool "SAMC21J18A" - -config SOC_PART_NUMBER_SAMC21J18AU - bool "SAMC21J18AU" - -config SOC_PART_NUMBER_SAMC21N17A - bool "SAMC21N17A" - select SOC_SERIES_REVISION_N - -config SOC_PART_NUMBER_SAMC21N18A - bool "SAMC21N18A" - select SOC_SERIES_REVISION_N - -endchoice diff --git a/soc/arm/atmel_sam0/samc21/soc.h b/soc/arm/atmel_sam0/samc21/soc.h deleted file mode 100644 index 56e33169150ab0..00000000000000 --- a/soc/arm/atmel_sam0/samc21/soc.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2022 Kamil Serwus - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMC_SOC_H_ -#define _ATMEL_SAMC_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAMC21E15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J17AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21J18AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMC21N18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samd20/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samd20/Kconfig.defconfig.series deleted file mode 100644 index f08047ae1ca60a..00000000000000 --- a/soc/arm/atmel_sam0/samd20/Kconfig.defconfig.series +++ /dev/null @@ -1,36 +0,0 @@ -# Atmel SAMD MCU series configuration options - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMD20 - -config SOC_SERIES - default "samd20" - -config SOC_PART_NUMBER - default "samd20e14" if SOC_PART_NUMBER_SAMD20E14 - default "samd20e15" if SOC_PART_NUMBER_SAMD20E15 - default "samd20e16" if SOC_PART_NUMBER_SAMD20E16 - default "samd20e17" if SOC_PART_NUMBER_SAMD20E17 - default "samd20e18" if SOC_PART_NUMBER_SAMD20E18 - default "samd20g14" if SOC_PART_NUMBER_SAMD20G14 - default "samd20g15" if SOC_PART_NUMBER_SAMD20G15 - default "samd20g16" if SOC_PART_NUMBER_SAMD20G16 - default "samd20g17" if SOC_PART_NUMBER_SAMD20G17 - default "samd20g17u" if SOC_PART_NUMBER_SAMD20G17U - default "samd20g18" if SOC_PART_NUMBER_SAMD20G18 - default "samd20g18u" if SOC_PART_NUMBER_SAMD20G18U - default "samd20j14" if SOC_PART_NUMBER_SAMD20J14 - default "samd20j15" if SOC_PART_NUMBER_SAMD20J15 - default "samd20j16" if SOC_PART_NUMBER_SAMD20J16 - default "samd20j17" if SOC_PART_NUMBER_SAMD20J17 - default "samd20j18" if SOC_PART_NUMBER_SAMD20J18 - -config NUM_IRQS - default 25 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -endif # SOC_SERIES_SAMD20 diff --git a/soc/arm/atmel_sam0/samd20/Kconfig.series b/soc/arm/atmel_sam0/samd20/Kconfig.series deleted file mode 100644 index 2ec93b4954c0ff..00000000000000 --- a/soc/arm/atmel_sam0/samd20/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMD20 MCU series - -# Copyright (c) 2018 Sean Nyekjaer -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMD20 - bool "Atmel SAMD20 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samd20/Kconfig.soc b/soc/arm/atmel_sam0/samd20/Kconfig.soc deleted file mode 100644 index 6cfc12f1f02cbd..00000000000000 --- a/soc/arm/atmel_sam0/samd20/Kconfig.soc +++ /dev/null @@ -1,61 +0,0 @@ -# Atmel SAMD MCU series - -# Copyright (c) 2018 Sean Nyekjaer -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMD20 MCU Selection" - depends on SOC_SERIES_SAMD20 - -config SOC_PART_NUMBER_SAMD20E14 - bool "SAMD20E14" - -config SOC_PART_NUMBER_SAMD20E15 - bool "SAMD20E15" - -config SOC_PART_NUMBER_SAMD20E16 - bool "SAMD20E16" - -config SOC_PART_NUMBER_SAMD20E17 - bool "SAMD20E17" - -config SOC_PART_NUMBER_SAMD20E18 - bool "SAMD20E18" - -config SOC_PART_NUMBER_SAMD20G14 - bool "SAMD20G14" - -config SOC_PART_NUMBER_SAMD20G15 - bool "SAMD20G15" - -config SOC_PART_NUMBER_SAMD20G16 - bool "SAMD20G16" - -config SOC_PART_NUMBER_SAMD20G17 - bool "SAMD20G17" - -config SOC_PART_NUMBER_SAMD20G17U - bool "SAMD20G17U" - -config SOC_PART_NUMBER_SAMD20G18 - bool "SAMD20G18" - -config SOC_PART_NUMBER_SAMD20G18U - bool "SAMD20G18U" - -config SOC_PART_NUMBER_SAMD20J14 - bool "SAMD20J14" - -config SOC_PART_NUMBER_SAMD20J15 - bool "SAMD20J15" - -config SOC_PART_NUMBER_SAMD20J16 - bool "SAMD20J16" - -config SOC_PART_NUMBER_SAMD20J17 - bool "SAMD20J17" - -config SOC_PART_NUMBER_SAMD20J18 - bool "SAMD20J18" - -endchoice diff --git a/soc/arm/atmel_sam0/samd20/soc.h b/soc/arm/atmel_sam0/samd20/soc.h deleted file mode 100644 index 7101e4e5315254..00000000000000 --- a/soc/arm/atmel_sam0/samd20/soc.h +++ /dev/null @@ -1,121 +0,0 @@ -/* - * Copyright (c) 2018 Sean Nyekjaer - * Copyright (c) 2023 Ionut Catalin Pavel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMD_SOC_H_ -#define _ATMEL_SAMD_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMD20E14) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E15) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E16) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E17) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20E18) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G14) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G15) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G16) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G17U) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20G18U) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J14) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J15) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J16) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J17) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD20J18) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ - -/** Known values */ -#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 -#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 - -/** GCLK1 source frequency selector */ -#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -/** Dividers and frequency for GCLK0 */ -#define SOC_ATMEL_SAM0_GCLK0_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -/** DFLL48M output frequency */ -#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ - (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) - -/** Dividers and frequency for GCLK1 */ -#define SOC_ATMEL_SAM0_GCLK1_DIV \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) - -/** DFLL48M output multiplier */ -#define SOC_ATMEL_SAM0_DFLL48M_MUL \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) - -/** Frequency for GCLK2 */ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ - -/** Dividers and frequency for GCLK3 */ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samd21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samd21/Kconfig.defconfig.series deleted file mode 100644 index 085a0c5e60d8d5..00000000000000 --- a/soc/arm/atmel_sam0/samd21/Kconfig.defconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# Atmel SAMD MCU series configuration options - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMD21 - -config SOC_SERIES - default "samd21" - -config SOC_PART_NUMBER - default "samd21e15a" if SOC_PART_NUMBER_SAMD21E15A - default "samd21e16a" if SOC_PART_NUMBER_SAMD21E16A - default "samd21e17a" if SOC_PART_NUMBER_SAMD21E17A - default "samd21e18a" if SOC_PART_NUMBER_SAMD21E18A - default "samd21g15a" if SOC_PART_NUMBER_SAMD21G15A - default "samd21g16a" if SOC_PART_NUMBER_SAMD21G16A - default "samd21g17a" if SOC_PART_NUMBER_SAMD21G17A - default "samd21g17au" if SOC_PART_NUMBER_SAMD21G17AU - default "samd21g18a" if SOC_PART_NUMBER_SAMD21G18A - default "samd21g18au" if SOC_PART_NUMBER_SAMD21G18AU - default "samd21j15a" if SOC_PART_NUMBER_SAMD21J15A - default "samd21j16a" if SOC_PART_NUMBER_SAMD21J16A - default "samd21j17a" if SOC_PART_NUMBER_SAMD21J17A - default "samd21j18a" if SOC_PART_NUMBER_SAMD21J18A - -config NUM_IRQS - default 28 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -endif # SOC_SERIES_SAMD21 diff --git a/soc/arm/atmel_sam0/samd21/Kconfig.series b/soc/arm/atmel_sam0/samd21/Kconfig.series deleted file mode 100644 index b947c755a7ad34..00000000000000 --- a/soc/arm/atmel_sam0/samd21/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMD21 MCU series - -# Copyright (c) 2017 Google LLC. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMD21 - bool "Atmel SAMD21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samd21/Kconfig.soc b/soc/arm/atmel_sam0/samd21/Kconfig.soc deleted file mode 100644 index 51ffa5d6322d85..00000000000000 --- a/soc/arm/atmel_sam0/samd21/Kconfig.soc +++ /dev/null @@ -1,52 +0,0 @@ -# Atmel SAMD MCU series - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMD21 MCU Selection" - depends on SOC_SERIES_SAMD21 - -config SOC_PART_NUMBER_SAMD21E15A - bool "SAMD21E15A" - -config SOC_PART_NUMBER_SAMD21E16A - bool "SAMD21E16A" - -config SOC_PART_NUMBER_SAMD21E17A - bool "SAMD21E17A" - -config SOC_PART_NUMBER_SAMD21E18A - bool "SAMD21E18A" - -config SOC_PART_NUMBER_SAMD21G15A - bool "SAMD21G15A" - -config SOC_PART_NUMBER_SAMD21G16A - bool "SAMD21G16A" - -config SOC_PART_NUMBER_SAMD21G17A - bool "SAMD21G17A" - -config SOC_PART_NUMBER_SAMD21G17AU - bool "SAMD21G17AU" - -config SOC_PART_NUMBER_SAMD21G18A - bool "SAMD21G18A" - -config SOC_PART_NUMBER_SAMD21G18AU - bool "SAMD21G18AU" - -config SOC_PART_NUMBER_SAMD21J15A - bool "SAMD21J15A" - -config SOC_PART_NUMBER_SAMD21J16A - bool "SAMD21J16A" - -config SOC_PART_NUMBER_SAMD21J17A - bool "SAMD21J17A" - -config SOC_PART_NUMBER_SAMD21J18A - bool "SAMD21J18A" - -endchoice diff --git a/soc/arm/atmel_sam0/samd21/soc.h b/soc/arm/atmel_sam0/samd21/soc.h deleted file mode 100644 index c4a33a95a54fd0..00000000000000 --- a/soc/arm/atmel_sam0/samd21/soc.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2017 Google LLC. - * Copyright (c) 2023 Ionut Catalin Pavel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMD_SOC_H_ -#define _ATMEL_SAMD_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMD21E15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G17AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21G18AU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J15A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD21J18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ - -/** Known values */ -#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 -#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 - -/** GCLK1 source frequency selector */ -#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -/** Dividers and frequency for GCLK0 */ -#define SOC_ATMEL_SAM0_GCLK0_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -/** DFLL48M output frequency */ -#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ - (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) - -/** Dividers and frequency for GCLK1 */ -#define SOC_ATMEL_SAM0_GCLK1_DIV \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) - -/** DFLL48M output multiplier */ -#define SOC_ATMEL_SAM0_DFLL48M_MUL \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) - -/** Frequency for GCLK2 */ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ - -/** Dividers and frequency for GCLK3 */ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMD_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samd51/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samd51/Kconfig.defconfig.series deleted file mode 100644 index fb90434abd8a2f..00000000000000 --- a/soc/arm/atmel_sam0/samd51/Kconfig.defconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Atmel SAMD51 MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMD51 - -config SOC_SERIES - string - default "samd51" - -config SOC_PART_NUMBER - string - default "samd51g18a" if SOC_PART_NUMBER_SAMD51G18A - default "samd51g19a" if SOC_PART_NUMBER_SAMD51G19A - default "samd51j18a" if SOC_PART_NUMBER_SAMD51J18A - default "samd51j19a" if SOC_PART_NUMBER_SAMD51J19A - default "samd51j20a" if SOC_PART_NUMBER_SAMD51J20A - default "samd51n19a" if SOC_PART_NUMBER_SAMD51N19A - default "samd51n20a" if SOC_PART_NUMBER_SAMD51N20A - default "samd51p19a" if SOC_PART_NUMBER_SAMD51P19A - default "samd51p20a" if SOC_PART_NUMBER_SAMD51P20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAMD51 diff --git a/soc/arm/atmel_sam0/samd51/Kconfig.series b/soc/arm/atmel_sam0/samd51/Kconfig.series deleted file mode 100644 index c85832735d8eb6..00000000000000 --- a/soc/arm/atmel_sam0/samd51/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAMD51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMD51 - bool "Atmel SAMD51 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMD51 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/samd51/Kconfig.soc b/soc/arm/atmel_sam0/samd51/Kconfig.soc deleted file mode 100644 index 043ccdcab1aefd..00000000000000 --- a/soc/arm/atmel_sam0/samd51/Kconfig.soc +++ /dev/null @@ -1,37 +0,0 @@ -# Atmel SAMD51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMD51 MCU Selection" - depends on SOC_SERIES_SAMD51 - -config SOC_PART_NUMBER_SAMD51G18A - bool "SAMD51G18A" - -config SOC_PART_NUMBER_SAMD51G19A - bool "SAMD51G19A" - -config SOC_PART_NUMBER_SAMD51J18A - bool "SAMD51J18A" - -config SOC_PART_NUMBER_SAMD51J19A - bool "SAMD51J19A" - -config SOC_PART_NUMBER_SAMD51J20A - bool "SAMD51J20A" - -config SOC_PART_NUMBER_SAMD51N19A - bool "SAMD51N19A" - -config SOC_PART_NUMBER_SAMD51N20A - bool "SAMD51N20A" - -config SOC_PART_NUMBER_SAMD51P19A - bool "SAMD51P19A" - -config SOC_PART_NUMBER_SAMD51P20A - bool "SAMD51P20A" - -endchoice diff --git a/soc/arm/atmel_sam0/samd51/soc.h b/soc/arm/atmel_sam0/samd51/soc.h deleted file mode 100644 index 48a3b64ef8e9ae..00000000000000 --- a/soc/arm/atmel_sam0/samd51/soc.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMD51_SOC_H_ -#define _ATMEL_SAMD51_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAMD51G18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51G19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51J19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51J20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51N20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51P19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMD51P20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAMD51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/same51/Kconfig.defconfig.series b/soc/arm/atmel_sam0/same51/Kconfig.defconfig.series deleted file mode 100644 index 4b30d635aa2bc5..00000000000000 --- a/soc/arm/atmel_sam0/same51/Kconfig.defconfig.series +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAME51 MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME51 - -config SOC_SERIES - string - default "same51" - -config SOC_PART_NUMBER - string - default "same51j18a" if SOC_PART_NUMBER_SAME51J18A - default "same51j19a" if SOC_PART_NUMBER_SAME51J19A - default "same51j20a" if SOC_PART_NUMBER_SAME51J20A - default "same51n19a" if SOC_PART_NUMBER_SAME51N19A - default "same51n20a" if SOC_PART_NUMBER_SAME51N20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAME51 diff --git a/soc/arm/atmel_sam0/same51/Kconfig.series b/soc/arm/atmel_sam0/same51/Kconfig.series deleted file mode 100644 index ced8b081fbed61..00000000000000 --- a/soc/arm/atmel_sam0/same51/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAME51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME51 - bool "Atmel SAME51 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAME51 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/same51/Kconfig.soc b/soc/arm/atmel_sam0/same51/Kconfig.soc deleted file mode 100644 index 08b3db89456fee..00000000000000 --- a/soc/arm/atmel_sam0/same51/Kconfig.soc +++ /dev/null @@ -1,25 +0,0 @@ -# Atmel SAME51 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME51 MCU Selection" - depends on SOC_SERIES_SAME51 - -config SOC_PART_NUMBER_SAME51J18A - bool "SAME51J18A" - -config SOC_PART_NUMBER_SAME51J19A - bool "SAME51J19A" - -config SOC_PART_NUMBER_SAME51J20A - bool "SAME51J20A" - -config SOC_PART_NUMBER_SAME51N19A - bool "SAME51N19A" - -config SOC_PART_NUMBER_SAME51N20A - bool "SAME51N20A" - -endchoice diff --git a/soc/arm/atmel_sam0/same51/soc.h b/soc/arm/atmel_sam0/same51/soc.h deleted file mode 100644 index 746a001be69ece..00000000000000 --- a/soc/arm/atmel_sam0/same51/soc.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAME51_SOC_H_ -#define _ATMEL_SAME51_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAME51J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51J19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51J20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME51N20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAME51_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/same53/Kconfig.defconfig.series b/soc/arm/atmel_sam0/same53/Kconfig.defconfig.series deleted file mode 100644 index f49d2741b3df9f..00000000000000 --- a/soc/arm/atmel_sam0/same53/Kconfig.defconfig.series +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAME53 MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME53 - -config SOC_SERIES - string - default "same53" - -config SOC_PART_NUMBER - string - default "same53j18a" if SOC_PART_NUMBER_SAME53J18A - default "same53j19a" if SOC_PART_NUMBER_SAME53J19A - default "same53j20a" if SOC_PART_NUMBER_SAME53J20A - default "same53n19a" if SOC_PART_NUMBER_SAME53N19A - default "same53n20a" if SOC_PART_NUMBER_SAME53N20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAME53 diff --git a/soc/arm/atmel_sam0/same53/Kconfig.series b/soc/arm/atmel_sam0/same53/Kconfig.series deleted file mode 100644 index a90a89229cbba6..00000000000000 --- a/soc/arm/atmel_sam0/same53/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAME53 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME53 - bool "Atmel SAME53 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAME53 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/same53/Kconfig.soc b/soc/arm/atmel_sam0/same53/Kconfig.soc deleted file mode 100644 index f59797204fee4a..00000000000000 --- a/soc/arm/atmel_sam0/same53/Kconfig.soc +++ /dev/null @@ -1,25 +0,0 @@ -# Atmel SAME53 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME53 MCU Selection" - depends on SOC_SERIES_SAME53 - -config SOC_PART_NUMBER_SAME53J18A - bool "SAME53J18A" - -config SOC_PART_NUMBER_SAME53J19A - bool "SAME53J19A" - -config SOC_PART_NUMBER_SAME53J20A - bool "SAME53J20A" - -config SOC_PART_NUMBER_SAME53N19A - bool "SAME53N19A" - -config SOC_PART_NUMBER_SAME53N20A - bool "SAME53N20A" - -endchoice diff --git a/soc/arm/atmel_sam0/same53/soc.h b/soc/arm/atmel_sam0/same53/soc.h deleted file mode 100644 index f3b1e460e33238..00000000000000 --- a/soc/arm/atmel_sam0/same53/soc.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAME53_SOC_H_ -#define _ATMEL_SAME53_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAME53J18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53J19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53J20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME53N20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "gmac_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAME53_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/same54/Kconfig.defconfig.series b/soc/arm/atmel_sam0/same54/Kconfig.defconfig.series deleted file mode 100644 index f2b3f9844a7523..00000000000000 --- a/soc/arm/atmel_sam0/same54/Kconfig.defconfig.series +++ /dev/null @@ -1,30 +0,0 @@ -# Atmel SAME MCU series configuration options - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAME54 - -config SOC_SERIES - string - default "same54" - -config SOC_PART_NUMBER - string - default "same54n19a" if SOC_PART_NUMBER_SAME54N19A - default "same54n20a" if SOC_PART_NUMBER_SAME54N20A - default "same54p19a" if SOC_PART_NUMBER_SAME54P19A - default "same54p20a" if SOC_PART_NUMBER_SAME54P20A - -config NUM_IRQS - int - default 137 - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 120000000 - -endif # SOC_SERIES_SAME54 diff --git a/soc/arm/atmel_sam0/same54/Kconfig.series b/soc/arm/atmel_sam0/same54/Kconfig.series deleted file mode 100644 index 5840a5e3515905..00000000000000 --- a/soc/arm/atmel_sam0/same54/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Atmel SAME54 MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAME54 - bool "Atmel SAME54 MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAME54 Cortex-M4F microcontrollers. diff --git a/soc/arm/atmel_sam0/same54/Kconfig.soc b/soc/arm/atmel_sam0/same54/Kconfig.soc deleted file mode 100644 index 35db63eab805a0..00000000000000 --- a/soc/arm/atmel_sam0/same54/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAME MCU series - -# Copyright (c) 2019 ML!PA Consulting GmbH -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAME54 MCU Selection" - depends on SOC_SERIES_SAME54 - -config SOC_PART_NUMBER_SAME54N19A - bool "SAME54N19A" - -config SOC_PART_NUMBER_SAME54N20A - bool "SAME54N20A" - -config SOC_PART_NUMBER_SAME54P19A - bool "SAME54P19A" - -config SOC_PART_NUMBER_SAME54P20A - bool "SAME54P20A" - -endchoice diff --git a/soc/arm/atmel_sam0/same54/soc.h b/soc/arm/atmel_sam0/same54/soc.h deleted file mode 100644 index b62eead707e488..00000000000000 --- a/soc/arm/atmel_sam0/same54/soc.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2019 ML!PA Consulting GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAME54_SOC_H_ -#define _ATMEL_SAME54_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - - -#if defined(CONFIG_SOC_PART_NUMBER_SAME54N19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME54N20A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME54P19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAME54P20A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "sercom_fixup_samd5x.h" -#include "tc_fixup_samd5x.h" -#include "gmac_fixup_samd5x.h" -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 - -#endif /* _ATMEL_SAME54_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series deleted file mode 100644 index 23bfcb70262e74..00000000000000 --- a/soc/arm/atmel_sam0/saml21/Kconfig.defconfig.series +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAML MCU series configuration options - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAML21 - -config SOC_SERIES - default "saml21" - -config SOC_PART_NUMBER - default "saml21e15b" if SOC_PART_NUMBER_SAML21E15B - default "saml21e16b" if SOC_PART_NUMBER_SAML21E16B - default "saml21e17b" if SOC_PART_NUMBER_SAML21E17B - default "saml21e18b" if SOC_PART_NUMBER_SAML21E18B - default "saml21g16b" if SOC_PART_NUMBER_SAML21G16B - default "saml21g17b" if SOC_PART_NUMBER_SAML21G17B - default "saml21g18b" if SOC_PART_NUMBER_SAML21G18B - default "saml21j16b" if SOC_PART_NUMBER_SAML21J16B - default "saml21j17b" if SOC_PART_NUMBER_SAML21J17B - default "saml21j17bu" if SOC_PART_NUMBER_SAML21J17BU - default "saml21j18b" if SOC_PART_NUMBER_SAML21J18B - default "saml21j18bu" if SOC_PART_NUMBER_SAML21J18BU - -config NUM_IRQS - default 29 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAML21 diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.series b/soc/arm/atmel_sam0/saml21/Kconfig.series deleted file mode 100644 index 662120102bb895..00000000000000 --- a/soc/arm/atmel_sam0/saml21/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAML21 MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAML21 - bool "Atmel SAML21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAML21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/saml21/Kconfig.soc b/soc/arm/atmel_sam0/saml21/Kconfig.soc deleted file mode 100644 index f6ab97367a93da..00000000000000 --- a/soc/arm/atmel_sam0/saml21/Kconfig.soc +++ /dev/null @@ -1,46 +0,0 @@ -# Atmel SAML MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAML21 MCU Selection" - depends on SOC_SERIES_SAML21 - -config SOC_PART_NUMBER_SAML21E15B - bool "SAML21E15B" - -config SOC_PART_NUMBER_SAML21E16B - bool "SAML21E16B" - -config SOC_PART_NUMBER_SAML21E17B - bool "SAML21E17B" - -config SOC_PART_NUMBER_SAML21E18B - bool "SAML21E18B" - -config SOC_PART_NUMBER_SAML21G16B - bool "SAML21G16B" - -config SOC_PART_NUMBER_SAML21G17B - bool "SAML21G17B" - -config SOC_PART_NUMBER_SAML21G18B - bool "SAML21G18B" - -config SOC_PART_NUMBER_SAML21J16B - bool "SAML21J16B" - -config SOC_PART_NUMBER_SAML21J17B - bool "SAML21J17B" - -config SOC_PART_NUMBER_SAML21J17BU - bool "SAML21J17BU" - -config SOC_PART_NUMBER_SAML21J18B - bool "SAML21J18B" - -config SOC_PART_NUMBER_SAML21J18BU - bool "SAML21J18BU" - -endchoice diff --git a/soc/arm/atmel_sam0/saml21/soc.h b/soc/arm/atmel_sam0/saml21/soc.h deleted file mode 100644 index de6b80dee61078..00000000000000 --- a/soc/arm/atmel_sam0/saml21/soc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAML_SOC_H_ -#define _ATMEL_SAML_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#if defined(CONFIG_SOC_PART_NUMBER_SAML21E15B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21E18B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21G18B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J17BU) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAML21J18BU) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 - -#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAML_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr21/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr21/Kconfig.defconfig.series deleted file mode 100644 index de04abe775587d..00000000000000 --- a/soc/arm/atmel_sam0/samr21/Kconfig.defconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# Atmel SAMR21 MCU series configuration options - -# Copyright (c) 2019 Benjamin Valentin -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMR21 - -config SOC_SERIES - default "samr21" - -config SOC_PART_NUMBER - default "samr21e16a" if SOC_PART_NUMBER_SAMR21E16A - default "samr21e17a" if SOC_PART_NUMBER_SAMR21E17A - default "samr21e18a" if SOC_PART_NUMBER_SAMR21E18A - default "samr21e19a" if SOC_PART_NUMBER_SAMR21E19A - default "samr21g16a" if SOC_PART_NUMBER_SAMR21G16A - default "samr21g17a" if SOC_PART_NUMBER_SAMR21G17A - default "samr21g18a" if SOC_PART_NUMBER_SAMR21G18A - -config NUM_IRQS - default 28 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 48000000 - -endif # SOC_SERIES_SAMR21 diff --git a/soc/arm/atmel_sam0/samr21/Kconfig.series b/soc/arm/atmel_sam0/samr21/Kconfig.series deleted file mode 100644 index 8dd60e5f65090b..00000000000000 --- a/soc/arm/atmel_sam0/samr21/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMR21 MCU series - -# Copyright (c) 2017 Google LLC. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMR21 - bool "Atmel SAMR21 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr21/Kconfig.soc b/soc/arm/atmel_sam0/samr21/Kconfig.soc deleted file mode 100644 index 98fb2781818ac5..00000000000000 --- a/soc/arm/atmel_sam0/samr21/Kconfig.soc +++ /dev/null @@ -1,31 +0,0 @@ -# Atmel SAMR21 MCU series - -# Copyright (c) 2017 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMR21 MCU Selection" - depends on SOC_SERIES_SAMR21 - -config SOC_PART_NUMBER_SAMR21E16A - bool "SAMR21E16A" - -config SOC_PART_NUMBER_SAMR21E17A - bool "SAMR21E17A" - -config SOC_PART_NUMBER_SAMR21E18A - bool "SAMR21E18A" - -config SOC_PART_NUMBER_SAMR21E19A - bool "SAMR21E19A" - -config SOC_PART_NUMBER_SAMR21G16A - bool "SAMR21G16A" - -config SOC_PART_NUMBER_SAMR21G17A - bool "SAMR21G17A" - -config SOC_PART_NUMBER_SAMR21G18A - bool "SAMR21G18A" - -endchoice diff --git a/soc/arm/atmel_sam0/samr21/soc.h b/soc/arm/atmel_sam0/samr21/soc.h deleted file mode 100644 index 0e19aa9b45dfe8..00000000000000 --- a/soc/arm/atmel_sam0/samr21/soc.h +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Copyright (c) 2017 Google LLC. - * Copyright (c) 2023 Ionut Catalin Pavel - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_ATMEL_SAMR21_SOC_H_ -#define ZEPHYR_ATMEL_SAMR21_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMR21E16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E18A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E19A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G16A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G17A) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G18A) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ - -/** Known values */ -#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 -#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 - -/** GCLK1 source frequency selector */ -#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -/** Dividers and frequency for GCLK0 */ -#define SOC_ATMEL_SAM0_GCLK0_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -/** DFLL48M output frequency */ -#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ - (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) - -/** Dividers and frequency for GCLK1 */ -#define SOC_ATMEL_SAM0_GCLK1_DIV \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ - (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) - -/** DFLL48M output multiplier */ -#define SOC_ATMEL_SAM0_DFLL48M_MUL \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) - -/** Frequency for GCLK2 */ -#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ - -/** Dividers and frequency for GCLK3 */ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_DIV \ - (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* ZEPHYR_ATMEL_SAMR21_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series deleted file mode 100644 index 96ca593b5a9dfd..00000000000000 --- a/soc/arm/atmel_sam0/samr34/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAML MCU series configuration options - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMR34 - -config SOC_SERIES - default "samr34" - -config SOC_PART_NUMBER - default "samr34j16b" if SOC_PART_NUMBER_SAMR34J16B - default "samr34j17b" if SOC_PART_NUMBER_SAMR34J17B - default "samr34j18b" if SOC_PART_NUMBER_SAMR34J18B - -config NUM_IRQS - default 23 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMR34 diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.series b/soc/arm/atmel_sam0/samr34/Kconfig.series deleted file mode 100644 index d3be127ac16406..00000000000000 --- a/soc/arm/atmel_sam0/samr34/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMR34 MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMR34 - bool "Atmel SAMR34 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr34/Kconfig.soc b/soc/arm/atmel_sam0/samr34/Kconfig.soc deleted file mode 100644 index 088d56b710913b..00000000000000 --- a/soc/arm/atmel_sam0/samr34/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Atmel SAMR MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAMR34 MCU Selection" - depends on SOC_SERIES_SAMR34 - -config SOC_PART_NUMBER_SAMR34J16B - bool "SAMR34J16B" - -config SOC_PART_NUMBER_SAMR34J17B - bool "SAMR34J17B" - -config SOC_PART_NUMBER_SAMR34J18B - bool "SAMR34J18B" - -endchoice diff --git a/soc/arm/atmel_sam0/samr34/soc.h b/soc/arm/atmel_sam0/samr34/soc.h deleted file mode 100644 index 2da117cf14e579..00000000000000 --- a/soc/arm/atmel_sam0/samr34/soc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMR_SOC_H_ -#define _ATMEL_SAMR_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMR34J16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR34J18B) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 - -#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMR_SOC_H_ */ diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series b/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series deleted file mode 100644 index edc7636d96d6a0..00000000000000 --- a/soc/arm/atmel_sam0/samr35/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# Atmel SAML MCU series configuration options - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SAMR35 - -config SOC_SERIES - default "samr35" - -config SOC_PART_NUMBER - default "samr35j16b" if SOC_PART_NUMBER_SAMR35J16B - default "samr35j17b" if SOC_PART_NUMBER_SAMR35J17B - default "samr35j18b" if SOC_PART_NUMBER_SAMR35J18B - -config NUM_IRQS - default 23 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -endif # SOC_SERIES_SAMR35 diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.series b/soc/arm/atmel_sam0/samr35/Kconfig.series deleted file mode 100644 index d55718d8524a75..00000000000000 --- a/soc/arm/atmel_sam0/samr35/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Atmel SAMR35 MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# Copyright (c) 2023 Gerson Fernando Budke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SAMR35 - bool "Atmel SAMR35 MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_SAM0 - select PLATFORM_SPECIFIC_INIT - select ASF - help - Enable support for Atmel SAMR35 Cortex-M0+ microcontrollers. diff --git a/soc/arm/atmel_sam0/samr35/Kconfig.soc b/soc/arm/atmel_sam0/samr35/Kconfig.soc deleted file mode 100644 index ceb95243806eec..00000000000000 --- a/soc/arm/atmel_sam0/samr35/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Atmel SAMR MCU series - -# Copyright (c) 2021 Argentum Systems Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Atmel SAM35 MCU Selection" - depends on SOC_SERIES_SAMR35 - -config SOC_PART_NUMBER_SAMR35J16B - bool "SAMR35J16B" - -config SOC_PART_NUMBER_SAMR35J17B - bool "SAMR35J17B" - -config SOC_PART_NUMBER_SAMR35J18B - bool "SAMR35J18B" - -endchoice diff --git a/soc/arm/atmel_sam0/samr35/soc.h b/soc/arm/atmel_sam0/samr35/soc.h deleted file mode 100644 index db3fd85b865b01..00000000000000 --- a/soc/arm/atmel_sam0/samr35/soc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* Copyright (c) 2021 Argentum Systems Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _ATMEL_SAMR_SOC_H_ -#define _ATMEL_SAMR_SOC_H_ - -#ifndef _ASMLANGUAGE - -#define DONT_USE_CMSIS_INIT - -#include - -#if defined(CONFIG_SOC_PART_NUMBER_SAMR35J16B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR35J17B) -#include -#elif defined(CONFIG_SOC_PART_NUMBER_SAMR35J18B) -#include -#else -#error Library does not support the specified device. -#endif - -#endif /* _ASMLANGUAGE */ - -#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED - -#include "adc_fixup_sam0.h" -#include "../common/soc_port.h" -#include "../common/atmel_sam0_dt.h" - -/** Processor Clock (HCLK) Frequency */ -#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ - -/** Master Clock (MCK) Frequency */ -#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ -#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 -#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 -#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 - -#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ -#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) -#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ -#else -#error Unsupported GCLK1 clock source. -#endif - -#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ -#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ - -#endif /* _ATMEL_SAMR_SOC_H_ */ diff --git a/soc/arm/bcm_vk/Kconfig b/soc/arm/bcm_vk/Kconfig deleted file mode 100644 index ae6122bd24737e..00000000000000 --- a/soc/arm/bcm_vk/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config SOC_FAMILY_BCMVK - bool - -if SOC_FAMILY_BCMVK -config SOC_FAMILY - string - default "bcm_vk" - -source "soc/arm/bcm_vk/*/Kconfig.soc" - -endif diff --git a/soc/arm/bcm_vk/Kconfig.defconfig b/soc/arm/bcm_vk/Kconfig.defconfig deleted file mode 100644 index 1258ea005a3888..00000000000000 --- a/soc/arm/bcm_vk/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm/bcm_vk/*/Kconfig.defconfig.series" diff --git a/soc/arm/bcm_vk/Kconfig.soc b/soc/arm/bcm_vk/Kconfig.soc deleted file mode 100644 index ce1114d22276cd..00000000000000 --- a/soc/arm/bcm_vk/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm/bcm_vk/*/Kconfig.series" diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series b/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series deleted file mode 100644 index b3de9e877462ce..00000000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -if SOC_SERIES_VALKYRIE - -config SOC_SERIES - default "valkyrie" - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 500000000 - -source "soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie*" - -endif # SOC_SERIES_VALKYRIE diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie_bcm58400 b/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie_bcm58400 deleted file mode 100644 index 9b5d7a45a2634a..00000000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.defconfig.valkyrie_bcm58400 +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. - -config SOC - default "BCM58400" - depends on SOC_BCM58400 diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.series b/soc/arm/bcm_vk/valkyrie/Kconfig.series deleted file mode 100644 index ca4542b5e89bae..00000000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config SOC_SERIES_VALKYRIE - bool "Broadcom Valkyrie Series" - select ARM - select CPU_CORTEX_M7 - select SOC_FAMILY_BCMVK - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - help - Enable support for Broadcom Valkyrie Series diff --git a/soc/arm/bcm_vk/valkyrie/Kconfig.soc b/soc/arm/bcm_vk/valkyrie/Kconfig.soc deleted file mode 100644 index 76f3ac196eef1d..00000000000000 --- a/soc/arm/bcm_vk/valkyrie/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -choice -prompt "Broadcom Valkyrie SoC" -depends on SOC_SERIES_VALKYRIE - -config SOC_BCM58400 - bool "Broadcom BCM58400" -endchoice diff --git a/soc/arm/bcm_vk/viper/CMakeLists.txt b/soc/arm/bcm_vk/viper/CMakeLists.txt deleted file mode 100644 index b81c75442e1245..00000000000000 --- a/soc/arm/bcm_vk/viper/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources( - soc.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/bcm_vk/viper/Kconfig.defconfig.series b/soc/arm/bcm_vk/viper/Kconfig.defconfig.series deleted file mode 100644 index 98623b5c6a5f00..00000000000000 --- a/soc/arm/bcm_vk/viper/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_VIPER - -config SOC_SERIES - default "viper" - -source "soc/arm/bcm_vk/viper/Kconfig.defconfig.viper*" - -endif # SOC_SERIES_VIPER diff --git a/soc/arm/bcm_vk/viper/Kconfig.series b/soc/arm/bcm_vk/viper/Kconfig.series deleted file mode 100644 index 90a9c162e2f256..00000000000000 --- a/soc/arm/bcm_vk/viper/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_VIPER - bool "Broadcom Viper Series" - select ARM - select SOC_FAMILY_BCMVK - help - Enable support for Broadcom Viper Series. diff --git a/soc/arm/bcm_vk/viper/Kconfig.soc b/soc/arm/bcm_vk/viper/Kconfig.soc deleted file mode 100644 index b72e9dd736a80c..00000000000000 --- a/soc/arm/bcm_vk/viper/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Broadcom Viper SoC" -depends on SOC_SERIES_VIPER - -config SOC_BCM58402_M7 - bool "Broadcom BCM58402 M7" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - -endchoice diff --git a/soc/arm/arm/beetle/CMSDK_BEETLE.h b/soc/arm/beetle/CMSDK_BEETLE.h similarity index 100% rename from soc/arm/arm/beetle/CMSDK_BEETLE.h rename to soc/arm/beetle/CMSDK_BEETLE.h diff --git a/soc/arm/beetle/CMakeLists.txt b/soc/arm/beetle/CMakeLists.txt new file mode 100644 index 00000000000000..7cad91bdc85d22 --- /dev/null +++ b/soc/arm/beetle/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/beetle/Kconfig b/soc/arm/beetle/Kconfig new file mode 100644 index 00000000000000..19de2b1717ca1a --- /dev/null +++ b/soc/arm/beetle/Kconfig @@ -0,0 +1,10 @@ +# ARM LTD Beetle SoC configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_BEETLE + select ARM + select CPU_CORTEX_M3 + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_DWT diff --git a/soc/arm/beetle/Kconfig.defconfig b/soc/arm/beetle/Kconfig.defconfig new file mode 100644 index 00000000000000..4052632978be37 --- /dev/null +++ b/soc/arm/beetle/Kconfig.defconfig @@ -0,0 +1,18 @@ +# ARM LTD Beetle SoC configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_BEETLE + +config NUM_IRQS + default 45 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 24000000 + +config CLOCK_CONTROL_INIT_PRIORITY + default 1 + depends on CLOCK_CONTROL + +endif # SOC_SERIES_BEETLE diff --git a/soc/arm/beetle/Kconfig.soc b/soc/arm/beetle/Kconfig.soc new file mode 100644 index 00000000000000..9b28a76106b89c --- /dev/null +++ b/soc/arm/beetle/Kconfig.soc @@ -0,0 +1,22 @@ +# ARM LTD Beetle SoC configuration options + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_BEETLE + bool + select SOC_FAMILY_ARM + help + Enable support for Beetle MCU Series + +config SOC_BEETLE_R0 + bool + select SOC_SERIES_BEETLE + help + ARM BEETLE R0 + +config SOC_SERIES + default "beetle" if SOC_SERIES_BEETLE + +config SOC + default "beetle_r0" if SOC_BEETLE_R0 diff --git a/soc/arm/arm/beetle/power.c b/soc/arm/beetle/power.c similarity index 100% rename from soc/arm/arm/beetle/power.c rename to soc/arm/beetle/power.c diff --git a/soc/arm/arm/beetle/soc.c b/soc/arm/beetle/soc.c similarity index 100% rename from soc/arm/arm/beetle/soc.c rename to soc/arm/beetle/soc.c diff --git a/soc/arm/arm/beetle/soc.h b/soc/arm/beetle/soc.h similarity index 100% rename from soc/arm/arm/beetle/soc.h rename to soc/arm/beetle/soc.h diff --git a/soc/arm/beetle/soc.yml b/soc/arm/beetle/soc.yml new file mode 100644 index 00000000000000..20bbf8445fde82 --- /dev/null +++ b/soc/arm/beetle/soc.yml @@ -0,0 +1,4 @@ +series: +- name: beetle + socs: + - name: beetle_r0 diff --git a/soc/arm/arm/beetle/soc_irq.h b/soc/arm/beetle/soc_irq.h similarity index 100% rename from soc/arm/arm/beetle/soc_irq.h rename to soc/arm/beetle/soc_irq.h diff --git a/soc/arm/arm/beetle/soc_pins.h b/soc/arm/beetle/soc_pins.h similarity index 100% rename from soc/arm/arm/beetle/soc_pins.h rename to soc/arm/beetle/soc_pins.h diff --git a/soc/arm/arm/beetle/soc_pll.h b/soc/arm/beetle/soc_pll.h similarity index 100% rename from soc/arm/arm/beetle/soc_pll.h rename to soc/arm/beetle/soc_pll.h diff --git a/soc/arm/arm/beetle/soc_power.h b/soc/arm/beetle/soc_power.h similarity index 100% rename from soc/arm/arm/beetle/soc_power.h rename to soc/arm/beetle/soc_power.h diff --git a/soc/arm/arm/beetle/soc_registers.h b/soc/arm/beetle/soc_registers.h similarity index 100% rename from soc/arm/arm/beetle/soc_registers.h rename to soc/arm/beetle/soc_registers.h diff --git a/soc/arm/cypress/CMakeLists.txt b/soc/arm/cypress/CMakeLists.txt deleted file mode 100644 index 95451afda66d85..00000000000000 --- a/soc/arm/cypress/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2021, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) diff --git a/soc/arm/cypress/Kconfig b/soc/arm/cypress/Kconfig deleted file mode 100644 index cb76ccb1090250..00000000000000 --- a/soc/arm/cypress/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Cypress PSoC6 MCU Selection" - depends on SOC_SERIES_PSOC62 || \ - SOC_SERIES_PSOC63 - -config SOC_PSOC6_M0 - bool "SOC_PSOC6_M0" - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - -config SOC_PSOC6_M4 - bool "SOC_PSOC6_M4" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - -endchoice - -config SOC_PSOC6_M0_ENABLES_M4 - bool "Dual-core support [activate Cortex-M4]" - depends on SOC_PSOC6_M0 - help - Cortex-M0 CPU should boot Cortex-M4 - -config SOC_FAMILY_PSOC6 - bool - -if SOC_FAMILY_PSOC6 - -config SOC_FAMILY - string - default "cypress" - -source "soc/arm/cypress/*/Kconfig.soc" - -endif # SOC_FAMILY_PSOC6 diff --git a/soc/arm/cypress/Kconfig.defconfig b/soc/arm/cypress/Kconfig.defconfig deleted file mode 100644 index 74310b9ea01761..00000000000000 --- a/soc/arm/cypress/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/cypress/*/Kconfig.defconfig.series" diff --git a/soc/arm/cypress/Kconfig.soc b/soc/arm/cypress/Kconfig.soc deleted file mode 100644 index 04e3e203b2f6dd..00000000000000 --- a/soc/arm/cypress/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/cypress/*/Kconfig.series" diff --git a/soc/arm/cypress/psoc6/CMakeLists.txt b/soc/arm/cypress/psoc6/CMakeLists.txt deleted file mode 100644 index e2ea2eb6ae1e45..00000000000000 --- a/soc/arm/cypress/psoc6/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_include_directories(.) -zephyr_sources( - soc.c -) - -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 NOINIT noinit.ld) -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 RWDATA rwdata.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0 b/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0 deleted file mode 100644 index 7e97640dc7997c..00000000000000 --- a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m0 +++ /dev/null @@ -1,14 +0,0 @@ -# Cypress PSoC6 CM0 platform configuration options - -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -if SOC_PSOC6_M0 - -config SOC - default "psoc6_m0" - -config NUM_IRQS - default 32 - -endif # SOC_PSOC6_M0 diff --git a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4 b/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4 deleted file mode 100644 index 0b4f3e0a4fed81..00000000000000 --- a/soc/arm/cypress/psoc6/Kconfig.defconfig.psoc6_m4 +++ /dev/null @@ -1,14 +0,0 @@ -# Cypress PSoC6 CM4 platform configuration options - -# Copyright (c) 2018, Cypress -# SPDX-License-Identifier: Apache-2.0 - -if SOC_PSOC6_M4 - -config SOC - default "psoc6_m4" - -config NUM_IRQS - default 147 - -endif # SOC_PSOC6_M4 diff --git a/soc/arm/cypress/psoc6/Kconfig.defconfig.series b/soc/arm/cypress/psoc6/Kconfig.defconfig.series deleted file mode 100644 index 36dfd19d566890..00000000000000 --- a/soc/arm/cypress/psoc6/Kconfig.defconfig.series +++ /dev/null @@ -1,25 +0,0 @@ -# Cypress Semiconductor PSoC6 series configuration options - -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_PSOC62 || \ - SOC_SERIES_PSOC63 - -config SOC_SERIES - default "psoc6" - -config SOC_PART_NUMBER - default "CY8C6247BZI_D54" if SOC_PART_NUMBER_CY8C6247BZI_D54 - -config SOC_PART_NUMBER - default "CY8C6347BZI_BLD53" if SOC_PART_NUMBER_CY8C6347BZI_BLD53 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -source "soc/arm/cypress/psoc6/Kconfig.defconfig.psoc*" - -endif # SOC_SERIES_PSOC62 || \ - # SOC_SERIES_PSOC63 diff --git a/soc/arm/cypress/psoc6/Kconfig.series b/soc/arm/cypress/psoc6/Kconfig.series deleted file mode 100644 index 35eb08685e12d8..00000000000000 --- a/soc/arm/cypress/psoc6/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Cypress PSoC6 MCU line - -# Copyright (c) 2018, Cypress Semiconductor -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_PSOC62 - bool "Cypress PSoC6 series MCU - Standard" - select ARM - select SOC_FAMILY_PSOC6 - select HAS_CYPRESS_DRIVERS - help - Enable support for Cypress PSoC6 MCU series - -config SOC_SERIES_PSOC63 - bool "Cypress PSoC6 series MCU - Bluetooth Low Energy" - select ARM - select SOC_FAMILY_PSOC6 - select HAS_CYPRESS_DRIVERS - help - Enable support for Cypress PSoC6-BLE MCU series diff --git a/soc/arm/cypress/psoc6/Kconfig.soc b/soc/arm/cypress/psoc6/Kconfig.soc deleted file mode 100644 index 49db89979e0178..00000000000000 --- a/soc/arm/cypress/psoc6/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# Cypress PSOC6 MCU line - -# Copyright (c) 2018, Cypress -# Copyright (c) 2020, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Cypress PSoC6 MCU Selection" - depends on SOC_SERIES_PSOC62 || \ - SOC_SERIES_PSOC63 - -config SOC_PART_NUMBER_CY8C6247BZI_D54 - bool "CY8C6247BZI_D54" - depends on SOC_SERIES_PSOC62 - -config SOC_PART_NUMBER_CY8C6347BZI_BLD53 - bool "CY8C6347BZI_BLD53" - depends on SOC_SERIES_PSOC63 - -endchoice diff --git a/soc/arm/bcm_vk/valkyrie/CMakeLists.txt b/soc/arm/designstart/CMakeLists.txt similarity index 100% rename from soc/arm/bcm_vk/valkyrie/CMakeLists.txt rename to soc/arm/designstart/CMakeLists.txt diff --git a/soc/arm/designstart/Kconfig b/soc/arm/designstart/Kconfig new file mode 100644 index 00000000000000..5ccdcaf661cc4e --- /dev/null +++ b/soc/arm/designstart/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DESIGNSTART + select ARM + +config SOC_DESIGNSTART_FPGA_CORTEX_M1 + select CPU_CORTEX_M1 + imply XIP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_DESIGNSTART_FPGA_CORTEX_M3 + select CPU_CORTEX_M3 + imply XIP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE diff --git a/soc/arm/designstart/Kconfig.soc b/soc/arm/designstart/Kconfig.soc new file mode 100644 index 00000000000000..19ceaea64e62f4 --- /dev/null +++ b/soc/arm/designstart/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2020 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DESIGNSTART + bool + select SOC_FAMILY_ARM + help + ARM DesignStart SoC Series + +config SOC_DESIGNSTART_FPGA_CORTEX_M1 + bool + select SOC_SERIES_DESIGNSTART + help + ARM Cortex-M1 DesignStart FPGA + +config SOC_DESIGNSTART_FPGA_CORTEX_M3 + bool + select SOC_SERIES_DESIGNSTART + help + ARM Cortex-M3 DesignStart FPGA + +config SOC_SERIES + default "designstart" if SOC_SERIES_DESIGNSTART + +config SOC + default "designstart_fpga_cortex_m1" if SOC_DESIGNSTART_FPGA_CORTEX_M1 + default "designstart_fpga_cortex_m3" if SOC_DESIGNSTART_FPGA_CORTEX_M3 diff --git a/soc/arm/arm/designstart/soc.h b/soc/arm/designstart/soc.h similarity index 100% rename from soc/arm/arm/designstart/soc.h rename to soc/arm/designstart/soc.h diff --git a/soc/arm/fvp_aemv8a/CMakeLists.txt b/soc/arm/fvp_aemv8a/CMakeLists.txt new file mode 100644 index 00000000000000..35d88056740af3 --- /dev/null +++ b/soc/arm/fvp_aemv8a/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/fvp_aemv8a/Kconfig b/soc/arm/fvp_aemv8a/Kconfig new file mode 100644 index 00000000000000..879ff0030db6ae --- /dev/null +++ b/soc/arm/fvp_aemv8a/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_FVP_AEMV8A + select ARM64 + help + Enable support for ARM FVP AEMv8A AArch64 Series + +config SOC_FVP_BASE_REVC_2XAEMV8A + select CPU_CORTEX_A53 diff --git a/soc/arm/fvp_aemv8a/Kconfig.defconfig b/soc/arm/fvp_aemv8a/Kconfig.defconfig new file mode 100644 index 00000000000000..38c672c7675648 --- /dev/null +++ b/soc/arm/fvp_aemv8a/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_FVP_AEMV8A + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config NUM_IRQS + default 16384 if GIC_V3_ITS + default 128 if !GIC_V3_ITS + +if SOC_FVP_BASE_REVC_2XAEMV8A + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_FVP_BASE_REVC_2XAEMV8A + +endif # SOC_SERIES_FVP_AEMV8A diff --git a/soc/arm/fvp_aemv8a/Kconfig.soc b/soc/arm/fvp_aemv8a/Kconfig.soc new file mode 100644 index 00000000000000..bf7739156749e1 --- /dev/null +++ b/soc/arm/fvp_aemv8a/Kconfig.soc @@ -0,0 +1,15 @@ +# Copyright (c) 2021 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_FVP_AEMV8A + bool + select SOC_FAMILY_ARM64 + +config SOC_FVP_BASE_REVC_2XAEMV8A + bool + +config SOC + default "fvp_base_revc_2xaemv8a" if SOC_FVP_BASE_REVC_2XAEMV8A + +config SOC_SERIES + default "fvp_aemv8a" if SOC_SERIES_FVP_AEMV8A diff --git a/soc/arm64/arm/fvp_aemv8a/mmu_regions.c b/soc/arm/fvp_aemv8a/mmu_regions.c similarity index 100% rename from soc/arm64/arm/fvp_aemv8a/mmu_regions.c rename to soc/arm/fvp_aemv8a/mmu_regions.c diff --git a/soc/arm/fvp_aemv8r/CMakeLists.txt b/soc/arm/fvp_aemv8r/CMakeLists.txt new file mode 100644 index 00000000000000..09a01f47ebd5b9 --- /dev/null +++ b/soc/arm/fvp_aemv8r/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +if(CONFIG_SOC_FVP_AEMV8R_AARCH64) + zephyr_library_sources(aarch64/soc.c) + zephyr_library_sources_ifdef(CONFIG_ARM_MPU aarch64/arm_mpu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_FVP_AEMV8R_AARCH32) + zephyr_library_sources_ifdef(CONFIG_ARM_MPU aarch32/arm_mpu_regions.c) + zephyr_library_sources(aarch32/soc.c) + zephyr_include_directories(aarch32) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/arm/fvp_aemv8r/Kconfig b/soc/arm/fvp_aemv8r/Kconfig new file mode 100644 index 00000000000000..7713ed672bef7f --- /dev/null +++ b/soc/arm/fvp_aemv8r/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FVP_AEMV8R_AARCH64 + select CPU_CORTEX_R82 + select CPU_HAS_MPU + select GIC_SINGLE_SECURITY_STATE + select ARM64 + +config SOC_FVP_AEMV8R_AARCH32 + select CPU_CORTEX_R52 + select CPU_HAS_ARM_MPU + select CPU_HAS_MPU + select VFP_DP_D32_FP16_FMAC if !USE_SWITCH + select GIC_V3 + select GIC_SINGLE_SECURITY_STATE + select PLATFORM_SPECIFIC_INIT + select ARM diff --git a/soc/arm/fvp_aemv8r/Kconfig.defconfig b/soc/arm/fvp_aemv8r/Kconfig.defconfig new file mode 100644 index 00000000000000..8fd46271f2c269 --- /dev/null +++ b/soc/arm/fvp_aemv8r/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_FVP_AEMV8R + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config NUM_IRQS + default 128 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config MAX_DOMAIN_PARTITIONS + default 8 if SOC_FVP_AEMV8R_AARCH64 + default 24 if USERSPACE && SOC_FVP_AEMV8R_AARCH32 + +endif # SOC_SERIES_FVP_AEMV8R diff --git a/soc/arm/fvp_aemv8r/Kconfig.soc b/soc/arm/fvp_aemv8r/Kconfig.soc new file mode 100644 index 00000000000000..296de41643bc1e --- /dev/null +++ b/soc/arm/fvp_aemv8r/Kconfig.soc @@ -0,0 +1,33 @@ +# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_FVP_AEMV8R + bool + help + Enable support for ARM FVP AEMv8R AArch64 Series + +config SOC_FVP_AEMV8R_AARCH64 + bool + select SOC_SERIES_FVP_AEMV8R + select SOC_FAMILY_ARM64 + +config SOC_FVP_AEMV8R_AARCH32 + bool + select SOC_SERIES_FVP_AEMV8R + select SOC_FAMILY_ARM + +config SOC_FVP_AEMV8R_SIMULATE_CPU_PM + bool "Simulate CPU Power Management for FVP_BaseR_AEMv8R" + depends on SOC_FVP_AEMV8R_AARCH64 + help + It simulates the cpu power management function for + FVP_BaseR_AEMv8R. When zephyr kernel try to bring up secondary + core through pm_cpu_on(), it always succeeds because + it indeed bring up secondary core successfully. + +config SOC_SERIES + default "fvp_aemv8r" if SOC_SERIES_FVP_AEMV8R + +config SOC + default "fvp_aemv8r_aarch64" if SOC_FVP_AEMV8R_AARCH64 + default "fvp_aemv8r_aarch32" if SOC_FVP_AEMV8R_AARCH32 diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c b/soc/arm/fvp_aemv8r/aarch32/arm_mpu_regions.c similarity index 100% rename from soc/arm/arm/fvp_aemv8r_aarch32/arm_mpu_regions.c rename to soc/arm/fvp_aemv8r/aarch32/arm_mpu_regions.c diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/soc.c b/soc/arm/fvp_aemv8r/aarch32/soc.c similarity index 100% rename from soc/arm/arm/fvp_aemv8r_aarch32/soc.c rename to soc/arm/fvp_aemv8r/aarch32/soc.c diff --git a/soc/arm/arm/fvp_aemv8r_aarch32/soc.h b/soc/arm/fvp_aemv8r/aarch32/soc.h similarity index 100% rename from soc/arm/arm/fvp_aemv8r_aarch32/soc.h rename to soc/arm/fvp_aemv8r/aarch32/soc.h diff --git a/soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c b/soc/arm/fvp_aemv8r/aarch64/arm_mpu_regions.c similarity index 100% rename from soc/arm64/arm/fvp_aemv8r/arm_mpu_regions.c rename to soc/arm/fvp_aemv8r/aarch64/arm_mpu_regions.c diff --git a/soc/arm64/arm/fvp_aemv8r/soc.c b/soc/arm/fvp_aemv8r/aarch64/soc.c similarity index 100% rename from soc/arm64/arm/fvp_aemv8r/soc.c rename to soc/arm/fvp_aemv8r/aarch64/soc.c diff --git a/soc/arm/gd_gd32/Kconfig b/soc/arm/gd_gd32/Kconfig deleted file mode 100644 index 69f21b210d08a2..00000000000000 --- a/soc/arm/gd_gd32/Kconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_GD32 - bool - select HAS_GD32_HAL - select BUILD_OUTPUT_HEX - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -config SOC_FAMILY - string - default "gd_gd32" - depends on SOC_FAMILY_GD32 - -config SOC_FAMILY_GD32_ARM - bool - select SOC_FAMILY_GD32 - -if SOC_FAMILY_GD32_ARM - -source "soc/arm/gd_gd32/*/Kconfig.soc" - -endif # SOC_FAMILY_GD32_ARM diff --git a/soc/arm/gd_gd32/Kconfig.defconfig b/soc/arm/gd_gd32/Kconfig.defconfig deleted file mode 100644 index b6fae5d43ec6ae..00000000000000 --- a/soc/arm/gd_gd32/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_GD32 - -source "soc/arm/gd_gd32/*/Kconfig.defconfig.series" - -config PINCTRL - default y - -config RESET - default y - -config CLOCK_CONTROL - default y - -endif # SOC_FAMILY_GD32 diff --git a/soc/arm/gd_gd32/Kconfig.soc b/soc/arm/gd_gd32/Kconfig.soc deleted file mode 100644 index 20a2f4c8cb402d..00000000000000 --- a/soc/arm/gd_gd32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/gd_gd32/*/Kconfig.series" diff --git a/soc/arm/gd_gd32/common/pinctrl_soc.h b/soc/arm/gd_gd32/common/pinctrl_soc.h deleted file mode 100644 index 608dd00e95ea06..00000000000000 --- a/soc/arm/gd_gd32/common/pinctrl_soc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2021 Teslabs Engineering S.L. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * Gigadevice SoC specific helpers for pinctrl driver - */ - -#ifndef ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ - -#include - -#endif /* ZEPHYR_SOC_ARM_GIGADEVICE_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.series deleted file mode 100644 index 0b250325c457e2..00000000000000 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32A50X - -source "soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32a50x" - -endif # SOC_SERIES_GD32A50X diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.series b/soc/arm/gd_gd32/gd32a50x/Kconfig.series deleted file mode 100644 index 2488c643727dd9..00000000000000 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32A50X - bool "GigaDevice GD32A50X series Cortex-M33 MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_40K - select PLATFORM_SPECIFIC_INIT - help - Enable support for GigaDevice GD32A50X MCU series diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.soc b/soc/arm/gd_gd32/gd32a50x/Kconfig.soc deleted file mode 100644 index 6601c77c11af7c..00000000000000 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32A50X MCU Selection" - depends on SOC_SERIES_GD32A50X - - config SOC_GD32A503 - bool "gd32a503" - -endchoice diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.series deleted file mode 100644 index f16328e1e70ec6..00000000000000 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32E10X - -source "soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32e10x" - -endif # SOC_SERIES_GD32E10X diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.series b/soc/arm/gd_gd32/gd32e10x/Kconfig.series deleted file mode 100644 index 010e649671ca87..00000000000000 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32E10X - bool "GigaDevice GD32E10X series Cortex-M4F MCU" - select ARM - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32E10X MCU series diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.soc b/soc/arm/gd_gd32/gd32e10x/Kconfig.soc deleted file mode 100644 index 42e6cd14d99085..00000000000000 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 YuLong Yao -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32E103 MCU Selection" - depends on SOC_SERIES_GD32E10X - - config SOC_GD32E103 - bool "gd32e103" -endchoice diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.series deleted file mode 100644 index f771aea44d912c..00000000000000 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32E50X - -source "soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32e50x" - -endif # SOC_SERIES_GD32E50X diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.series b/soc/arm/gd_gd32/gd32e50x/Kconfig.series deleted file mode 100644 index 546ca45679341c..00000000000000 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32E50X - bool "GigaDevice GD32E50X series Cortex-M33 MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_CORTEX_M33 - select ARMV8_M_DSP - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32E50X MCU series diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.soc b/soc/arm/gd_gd32/gd32e50x/Kconfig.soc deleted file mode 100644 index 98494f0dab48cf..00000000000000 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32E50X MCU Selection" - depends on SOC_SERIES_GD32E50X - - config SOC_GD32E507 - bool "gd32e507" - -endchoice diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.series deleted file mode 100644 index 4852255d255df3..00000000000000 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32F3X0 - -source "soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32f3x0" - -endif # SOC_SERIES_GD32F3X0 diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.series b/soc/arm/gd_gd32/gd32f3x0/Kconfig.series deleted file mode 100644 index 123d26a6f7ae65..00000000000000 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32F3X0 - bool "GigaDevice GD32F3X0 series Cortex-M4F MCU" - select ARM - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32F3X0 MCU series diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.soc b/soc/arm/gd_gd32/gd32f3x0/Kconfig.soc deleted file mode 100644 index 1acbaaf4ae0a4b..00000000000000 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32F3X0 MCU Selection" - depends on SOC_SERIES_GD32F3X0 - - config SOC_GD32F350 - bool "gd32f350" -endchoice diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.series deleted file mode 100644 index 8923e1582a32c7..00000000000000 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32F403 - -source "soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403" - -config SOC_SERIES - default "gd32f403" - -endif # SOC_SERIES_GD32F403 diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.series b/soc/arm/gd_gd32/gd32f403/Kconfig.series deleted file mode 100644 index 86c57f224f74a1..00000000000000 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32F403 - bool "GigaDevice GD32F403 series Cortex-M4F MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - help - Enable support for GigaDevice GD32F403 MCU series diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.soc b/soc/arm/gd_gd32/gd32f403/Kconfig.soc deleted file mode 100644 index 17e960ce40ca68..00000000000000 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021, ATL Electronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32F403 MCU Selection" - depends on SOC_SERIES_GD32F403 - - config SOC_GD32F403 - bool "gd32f403" - -endchoice diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.series deleted file mode 100644 index a4ccaed4e802f2..00000000000000 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32F4XX - -source "soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32f4xx" - -endif # SOC_SERIES_GD32F4XX diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.series b/soc/arm/gd_gd32/gd32f4xx/Kconfig.series deleted file mode 100644 index 9b1d74dfa978d9..00000000000000 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32F4XX - bool "GigaDevice GD32F4XX series Cortex-M4F MCU" - select ARM - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_CORTEX_M4 - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_32K - help - Enable support for GigaDevice GD32F4XX MCU series diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.soc b/soc/arm/gd_gd32/gd32f4xx/Kconfig.soc deleted file mode 100644 index d0cfda3817c5fc..00000000000000 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.soc +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021, Teslabs Engineering S.L. -# Copyright (c) 2022, Rtone. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32F4XX MCU Selection" - depends on SOC_SERIES_GD32F4XX - - config SOC_GD32F405 - bool "gd32f405" - - config SOC_GD32F407 - bool "gd32f407" - - config SOC_GD32F450 - bool "gd32f450" - - config SOC_GD32F470 - bool "gd32f470" - -endchoice diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.series b/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.series deleted file mode 100644 index 36a6476dbfbc6a..00000000000000 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32L23X - -source "soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32*" - -config SOC_SERIES - default "gd32l23x" - -endif # SOC_SERIES_GD32L23X diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.series b/soc/arm/gd_gd32/gd32l23x/Kconfig.series deleted file mode 100644 index d6125ca4152fed..00000000000000 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32L23X - bool "GigaDevice GD32L23X series Cortex-M23 MCU" - select ARM - select CPU_CORTEX_M23 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_GD32_ARM - select GD32_HAS_AF_PINMUX - select GD32_HAS_IRC_32K - help - Enable support for GigaDevice GD32L23X MCU series diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.soc b/soc/arm/gd_gd32/gd32l23x/Kconfig.soc deleted file mode 100644 index 927ef4158faeff..00000000000000 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 BrainCo Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32L23X MCU Selection" - depends on SOC_SERIES_GD32L23X - - config SOC_GD32L233 - bool "gd32l233" -endchoice diff --git a/soc/arm/infineon_cat1/CMakeLists.txt b/soc/arm/infineon_cat1/CMakeLists.txt deleted file mode 100644 index 83da7b62c08d1d..00000000000000 --- a/soc/arm/infineon_cat1/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(common/) -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/infineon_cat1/Kconfig b/soc/arm/infineon_cat1/Kconfig deleted file mode 100644 index c0c79bb00f9279..00000000000000 --- a/soc/arm/infineon_cat1/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - - -config SOC_FAMILY_INFINEON_CAT1 - bool - -config SOC_FAMILY_INFINEON_CAT1A - bool - -if SOC_FAMILY_INFINEON_CAT1 -source "soc/arm/infineon_cat1/*/Kconfig.soc" - -config SOC_FAMILY - string - default "infineon_cat1" - -endif # SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/arm/infineon_cat1/Kconfig.defconfig b/soc/arm/infineon_cat1/Kconfig.defconfig deleted file mode 100644 index 28567181600c2e..00000000000000 --- a/soc/arm/infineon_cat1/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/infineon_cat1/*/Kconfig.defconfig" diff --git a/soc/arm/infineon_cat1/Kconfig.soc b/soc/arm/infineon_cat1/Kconfig.soc deleted file mode 100644 index 5d34753aa6ad95..00000000000000 --- a/soc/arm/infineon_cat1/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/infineon_cat1/*/Kconfig.series" diff --git a/soc/arm/infineon_cat1/psoc6/CMakeLists.txt b/soc/arm/infineon_cat1/psoc6/CMakeLists.txt deleted file mode 100644 index 26c9fb8cd9c175..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/CMakeLists.txt +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_include_directories(.) - -# Add sections -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 NOINIT noinit.ld) - -# Add section for cm0p image ROM -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ROM_START SORT_KEY 0x0cm0p rom_cm0image.ld) - -# Add section for cm0p image RAM -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAM_SECTIONS SORT_KEY 0 ram_cm0image.ld) - -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAMFUNC_SECTION SORT_KEY 0 ram_func.ld) - -zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 RODATA SORT_KEY 0 rom.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig deleted file mode 100644 index f7bf4bc80762b1..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_INFINEON_CAT1 -source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*" - -config SOC_SERIES - default "psoc6" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE - hex - default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP - -config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE - hex - default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP - -endif # SOC_FAMILY_INFINEON_CAT1A diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc deleted file mode 100644 index f0aa02e7536a11..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.*" diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01 deleted file mode 100644 index 7452cb797efdd6..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_01 +++ /dev/null @@ -1,77 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_01 based MCU default configuration - -if SOC_DIE_PSOC6_01 - -config NUM_IRQS - default 32 if CPU_CORTEX_M0PLUS - default 147 if CPU_CORTEX_M4 - -config SOC - default "CY8C6036BZI_F04" if SOC_CY8C6036BZI_F04 - default "CY8C6016BZI_F04" if SOC_CY8C6016BZI_F04 - default "CY8C6116BZI_F54" if SOC_CY8C6116BZI_F54 - default "CY8C6136BZI_F14" if SOC_CY8C6136BZI_F14 - default "CY8C6136BZI_F34" if SOC_CY8C6136BZI_F34 - default "CY8C6137BZI_F14" if SOC_CY8C6137BZI_F14 - default "CY8C6137BZI_F34" if SOC_CY8C6137BZI_F34 - default "CY8C6137BZI_F54" if SOC_CY8C6137BZI_F54 - default "CY8C6117BZI_F34" if SOC_CY8C6117BZI_F34 - default "CY8C6246BZI_D04" if SOC_CY8C6246BZI_D04 - default "CY8C6247BZI_D44" if SOC_CY8C6247BZI_D44 - default "CY8C6247BZI_D34" if SOC_CY8C6247BZI_D34 - default "CY8C6247BZI_D54" if SOC_CY8C6247BZI_D54 - default "CY8C6336BZI_BLF03" if SOC_CY8C6336BZI_BLF03 - default "CY8C6316BZI_BLF03" if SOC_CY8C6316BZI_BLF03 - default "CY8C6316BZI_BLF53" if SOC_CY8C6316BZI_BLF53 - default "CY8C6336BZI_BLD13" if SOC_CY8C6336BZI_BLD13 - default "CY8C6347BZI_BLD43" if SOC_CY8C6347BZI_BLD43 - default "CY8C6347BZI_BLD33" if SOC_CY8C6347BZI_BLD33 - default "CY8C6347BZI_BLD53" if SOC_CY8C6347BZI_BLD53 - default "CY8C6347FMI_BLD13" if SOC_CY8C6347FMI_BLD13 - default "CY8C6347FMI_BLD43" if SOC_CY8C6347FMI_BLD43 - default "CY8C6347FMI_BLD33" if SOC_CY8C6347FMI_BLD33 - default "CY8C6347FMI_BLD53" if SOC_CY8C6347FMI_BLD53 - default "CY8C6137FDI_F02" if SOC_CY8C6137FDI_F02 - default "CY8C6117FDI_F02" if SOC_CY8C6117FDI_F02 - default "CY8C6247FDI_D02" if SOC_CY8C6247FDI_D02 - default "CY8C6247FDI_D32" if SOC_CY8C6247FDI_D32 - default "CY8C6336BZI_BUD13" if SOC_CY8C6336BZI_BUD13 - default "CY8C6347BZI_BUD43" if SOC_CY8C6347BZI_BUD43 - default "CY8C6347BZI_BUD33" if SOC_CY8C6347BZI_BUD33 - default "CY8C6347BZI_BUD53" if SOC_CY8C6347BZI_BUD53 - default "CY8C6337BZI_BLF13" if SOC_CY8C6337BZI_BLF13 - default "CY8C6136FDI_F42" if SOC_CY8C6136FDI_F42 - default "CY8C6247FDI_D52" if SOC_CY8C6247FDI_D52 - default "CY8C6136FTI_F42" if SOC_CY8C6136FTI_F42 - default "CY8C6247FTI_D52" if SOC_CY8C6247FTI_D52 - default "CY8C6247BZI_AUD54" if SOC_CY8C6247BZI_AUD54 - default "CY8C6336BZI_BLF04" if SOC_CY8C6336BZI_BLF04 - default "CY8C6316BZI_BLF04" if SOC_CY8C6316BZI_BLF04 - default "CY8C6316BZI_BLF54" if SOC_CY8C6316BZI_BLF54 - default "CY8C6336BZI_BLD14" if SOC_CY8C6336BZI_BLD14 - default "CY8C6347BZI_BLD44" if SOC_CY8C6347BZI_BLD44 - default "CY8C6347BZI_BLD34" if SOC_CY8C6347BZI_BLD34 - default "CY8C6347BZI_BLD54" if SOC_CY8C6347BZI_BLD54 - default "CY8C6247BFI_D54" if SOC_CY8C6247BFI_D54 - default "CYBLE_416045_02_device" if SOC_CYBLE_416045_02 - default "CY8C6347FMI_BUD53" if SOC_CY8C6347FMI_BUD53 - default "CY8C6347FMI_BUD13" if SOC_CY8C6347FMI_BUD13 - default "CY8C6347FMI_BUD43" if SOC_CY8C6347FMI_BUD43 - default "CY8C6347FMI_BUD33" if SOC_CY8C6347FMI_BUD33 - default "CY8C6137WI_F54" if SOC_CY8C6137WI_F54 - default "CY8C6117WI_F34" if SOC_CY8C6117WI_F34 - default "CY8C6247WI_D54" if SOC_CY8C6247WI_D54 - default "CY8C6336LQI_BLF02" if SOC_CY8C6336LQI_BLF02 - default "CY8C6336LQI_BLF42" if SOC_CY8C6336LQI_BLF42 - default "CY8C6347LQI_BLD52" if SOC_CY8C6347LQI_BLD52 - default "CYB06447BZI_BLD54" if SOC_CYB06447BZI_BLD54 - default "CYB06447BZI_BLD53" if SOC_CYB06447BZI_BLD53 - default "CYB06447BZI_D54" if SOC_CYB06447BZI_D54 - -# add additional die specific params - -endif # SOC_DIE_PSOC6_01 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02 deleted file mode 100644 index 087d5e0597823f..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_02 +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_02 based MCU default configuration - -if SOC_DIE_PSOC6_02 - -config NUM_IRQS - default 32 if CPU_CORTEX_M0PLUS - default 168 if CPU_CORTEX_M4 - -config SOC - default "CYB0644ABZI_S2D44" if SOC_CYB0644ABZI_S2D44 - default "CYS0644ABZI_S2D44" if SOC_CYS0644ABZI_S2D44 - default "CY8C624ABZI_S2D44A0" if SOC_CY8C624ABZI_S2D44A0 - default "CY8C624ABZI_S2D44" if SOC_CY8C624ABZI_S2D44 - default "CY8C624AAZI_S2D44" if SOC_CY8C624AAZI_S2D44 - default "CY8C624AFNI_S2D43" if SOC_CY8C624AFNI_S2D43 - default "CY8C624ABZI_S2D04" if SOC_CY8C624ABZI_S2D04 - default "CY8C624ABZI_S2D14" if SOC_CY8C624ABZI_S2D14 - default "CY8C624AAZI_S2D14" if SOC_CY8C624AAZI_S2D14 - default "CY8C6248AZI_S2D14" if SOC_CY8C6248AZI_S2D14 - default "CY8C6248BZI_S2D44" if SOC_CY8C6248BZI_S2D44 - default "CY8C6248AZI_S2D44" if SOC_CY8C6248AZI_S2D44 - default "CY8C6248FNI_S2D43" if SOC_CY8C6248FNI_S2D43 - default "CY8C614ABZI_S2F04" if SOC_CY8C614ABZI_S2F04 - default "CY8C614AAZI_S2F04" if SOC_CY8C614AAZI_S2F04 - default "CY8C614AFNI_S2F03" if SOC_CY8C614AFNI_S2F03 - default "CY8C614AAZI_S2F14" if SOC_CY8C614AAZI_S2F14 - default "CY8C614ABZI_S2F44" if SOC_CY8C614ABZI_S2F44 - default "CY8C614AAZI_S2F44" if SOC_CY8C614AAZI_S2F44 - default "CY8C614AFNI_S2F43" if SOC_CY8C614AFNI_S2F43 - default "CY8C6148BZI_S2F44" if SOC_CY8C6148BZI_S2F44 - default "CY8C6148AZI_S2F44" if SOC_CY8C6148AZI_S2F44 - default "CY8C6148FNI_S2F43" if SOC_CY8C6148FNI_S2F43 - default "CY8C624ABZI_D44" if SOC_CY8C624ABZI_D44 - default "CY8C624ALQI_S2D42" if SOC_CY8C624ALQI_S2D42 - default "CY8C624ALQI_S2D02" if SOC_CY8C624ALQI_S2D02 - default "CY8C6248LQI_S2D42" if SOC_CY8C6248LQI_S2D42 - default "CY8C6248LQI_S2D02" if SOC_CY8C6248LQI_S2D02 - default "CY8C614ALQI_S2F42" if SOC_CY8C614ALQI_S2F42 - default "CY8C614ALQI_S2F02" if SOC_CY8C614ALQI_S2F02 - default "CY8C6148LQI_S2F42" if SOC_CY8C6148LQI_S2F42 - default "CY8C6148LQI_S2F02" if SOC_CY8C6148LQI_S2F02 - -# add additional die specific params - -endif # SOC_DIE_PSOC6_02 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04 b/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04 deleted file mode 100644 index 622a0af848f39e..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.defconfig.soc.psoc6_04 +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# Copyright (c) David Ullmann -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_04 based MCU default configuration - -if SOC_DIE_PSOC6_04 - -config NUM_IRQS - default 16 if CPU_CORTEX_M0PLUS - default 175 if CPU_CORTEX_M4 - -config SOC - default "CY8C6244AZI_S4D92" if SOC_CY8C6244AZI_S4D92 - default "CY8C6244LQI_S4D92" if SOC_CY8C6244LQI_S4D92 - default "CY8C6244AZI_S4D93" if SOC_CY8C6244AZI_S4D93 - default "CY8C6244AZI_S4D82" if SOC_CY8C6244AZI_S4D82 - default "CY8C6244LQI_S4D82" if SOC_CY8C6244LQI_S4D82 - default "CY8C6244AZI_S4D83" if SOC_CY8C6244AZI_S4D83 - default "CY8C6244AZI_S4D62" if SOC_CY8C6244AZI_S4D62 - default "CY8C6244LQI_S4D62" if SOC_CY8C6244LQI_S4D62 - default "CY8C6244AZI_S4D12" if SOC_CY8C6244AZI_S4D12 - default "CY8C6244LQI_S4D12" if SOC_CY8C6244LQI_S4D12 - default "CY8C6144AZI_S4F92" if SOC_CY8C6144AZI_S4F92 - default "CY8C6144LQI_S4F92" if SOC_CY8C6144LQI_S4F92 - default "CY8C6144AZI_S4F93" if SOC_CY8C6144AZI_S4F93 - default "CY8C6144AZI_S4F82" if SOC_CY8C6144AZI_S4F82 - default "CY8C6144LQI_S4F82" if SOC_CY8C6144LQI_S4F82 - default "CY8C6144AZI_S4F83" if SOC_CY8C6144AZI_S4F83 - default "CY8C6144AZI_S4F62" if SOC_CY8C6144AZI_S4F62 - default "CY8C6144LQI_S4F62" if SOC_CY8C6144LQI_S4F62 - default "CY8C6144AZI_S4F12" if SOC_CY8C6144AZI_S4F12 - default "CY8C6144LQI_S4F12" if SOC_CY8C6144LQI_S4F12 - - -endif # SOC_DIE_PSOC6_04 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.series b/soc/arm/infineon_cat1/psoc6/Kconfig.series deleted file mode 100644 index e86402da73bee8..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.series +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Cypress PSoC™ 6 MCU lines -config SOC_SERIES_PSOC_60 - bool "Infineon PSoC™ 60 series MCU(Value Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 60 MCU series - -config SOC_SERIES_PSOC_61 - bool "Infineon PSoC™ 61 series MCU (Programmable Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 61 MCU series - -config SOC_SERIES_PSOC_62 - bool "Infineon PSoC™ 62 series MCU (Performance Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 62 MCU series - -config SOC_SERIES_PSOC_63 - bool "Infineon PSoC™ 63 series MCU (Connectivity Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 63 MCU series - -config SOC_SERIES_PSOC_64 - bool "Infineon PSoC™ 64 series MCU (Security Line)" - select SOC_FAMILY_INFINEON_CAT1 - help - Enable support for Infineon PSoC™ 64 MCU series diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc b/soc/arm/infineon_cat1/psoc6/Kconfig.soc deleted file mode 100644 index d1652cca84070a..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc +++ /dev/null @@ -1,117 +0,0 @@ -# Copyright (c) 2021 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6 die -config SOC_DIE_PSOC6 - bool - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select SOC_FAMILY_INFINEON_CAT1A - select DYNAMIC_INTERRUPTS - select CPU_HAS_FPU - -# Infineon PSoC6_01 die -config SOC_DIE_PSOC6_01 - bool - select SOC_DIE_PSOC6 - -# Infineon PSoC6_02 die -config SOC_DIE_PSOC6_02 - bool - select SOC_DIE_PSOC6 - -# Infineon PSoC6_03 die -config SOC_DIE_PSOC6_03 - bool - select SOC_DIE_PSOC6 - -# Infineon PSoC6_04 die -config SOC_DIE_PSOC6_04 - bool - select SOC_DIE_PSOC6 - -# Infineon soc packages -config SOC_PACKAGE_PSOC6_01_124_BGA - bool - -config SOC_PACKAGE_PSOC6_01_116_BGA_BLE - bool - -config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - bool - -config SOC_PACKAGE_PSOC6_01_80_WLCSP - bool - -config SOC_PACKAGE_PSOC6_01_116_BGA_USB - bool - -config SOC_PACKAGE_PSOC6_01_124_BGA_SIP - bool - -config SOC_PACKAGE_PSOC6_01_43_SMT - bool - -config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - bool - -config SOC_PACKAGE_PSOC6_01_68_QFN_BLE - bool - -config SOC_PACKAGE_PSOC6_02_124_BGA - bool - -config SOC_PACKAGE_PSOC6_02_128_TQFP - bool - -config SOC_PACKAGE_PSOC6_02_100_WLCSP - bool - -config SOC_PACKAGE_PSOC6_02_68_QFN - bool - -config SOC_PACKAGE_PSOC6_03_100_TQFP - bool - -config SOC_PACKAGE_PSOC6_03_68_QFN - bool - -config SOC_PACKAGE_PSOC6_03_49_WLCSP - bool - -config SOC_PACKAGE_PSOC6_04_64_TQFP - bool - -config SOC_PACKAGE_PSOC6_04_68_QFN - bool - -config SOC_PACKAGE_PSOC6_04_80_TQFP - bool - -## Infineon MCUs -choice - prompt "MPN" - osource "soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_*" -endchoice - -if SOC_FAMILY_INFINEON_CAT1A -## PSoC™ 6 Cortex M0+ prebuilt images -choice - prompt "PSoC™ 6 Cortex M0+ prebuilt images" - help - Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6 - dual-core MCU. The image is responsible for booting the Cortex-M4 on the device. - -config SOC_PSOC6_CM0P_IMAGE_SLEEP - bool "DeepSleep" - help - DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE - dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4 - application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4 - linker script. - -endchoice - -endif # SOC_FAMILY_INFINEON_CAT1A diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_01 b/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_01 deleted file mode 100644 index 1ae22e52ef7218..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_01 +++ /dev/null @@ -1,365 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_01 series MCUs - -config SOC_CY8C6036BZI_F04 - bool "CY8C6036BZI_F04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_60 - -config SOC_CY8C6016BZI_F04 - bool "CY8C6016BZI_F04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_60 - -config SOC_CY8C6116BZI_F54 - bool "CY8C6116BZI_F54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6136BZI_F14 - bool "CY8C6136BZI_F14" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6136BZI_F34 - bool "CY8C6136BZI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6137BZI_F14 - bool "CY8C6137BZI_F14" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6137BZI_F34 - bool "CY8C6137BZI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6137BZI_F54 - bool "CY8C6137BZI_F54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6117BZI_F34 - bool "CY8C6117BZI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6246BZI_D04 - bool "CY8C6246BZI_D04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_D44 - bool "CY8C6247BZI_D44" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_D34 - bool "CY8C6247BZI_D34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_D54 - bool "CY8C6247BZI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336BZI_BLF03 - bool "CY8C6336BZI_BLF03" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF03 - bool "CY8C6316BZI_BLF03" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF53 - bool "CY8C6316BZI_BLF53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6336BZI_BLD13 - bool "CY8C6336BZI_BLD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD43 - bool "CY8C6347BZI_BLD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD33 - bool "CY8C6347BZI_BLD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD53 - bool "CY8C6347BZI_BLD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD13 - bool "CY8C6347FMI_BLD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD43 - bool "CY8C6347FMI_BLD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD33 - bool "CY8C6347FMI_BLD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BLD53 - bool "CY8C6347FMI_BLD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6137FDI_F02 - bool "CY8C6137FDI_F02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6117FDI_F02 - bool "CY8C6117FDI_F02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247FDI_D02 - bool "CY8C6247FDI_D02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247FDI_D32 - bool "CY8C6247FDI_D32" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336BZI_BUD13 - bool "CY8C6336BZI_BUD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BUD43 - bool "CY8C6347BZI_BUD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BUD33 - bool "CY8C6347BZI_BUD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BUD53 - bool "CY8C6347BZI_BUD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6337BZI_BLF13 - bool "CY8C6337BZI_BLF13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6136FDI_F42 - bool "CY8C6136FDI_F42" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247FDI_D52 - bool "CY8C6247FDI_D52" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6136FTI_F42 - bool "CY8C6136FTI_F42" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247FTI_D52 - bool "CY8C6247FTI_D52" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_80_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6247BZI_AUD54 - bool "CY8C6247BZI_AUD54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336BZI_BLF04 - bool "CY8C6336BZI_BLF04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF04 - bool "CY8C6316BZI_BLF04" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6316BZI_BLF54 - bool "CY8C6316BZI_BLF54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6336BZI_BLD14 - bool "CY8C6336BZI_BLD14" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD44 - bool "CY8C6347BZI_BLD44" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD34 - bool "CY8C6347BZI_BLD34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347BZI_BLD54 - bool "CY8C6347BZI_BLD54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6247BFI_D54 - bool "CY8C6247BFI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CYBLE_416045_02 - bool "CYBLE_416045_02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD53 - bool "CY8C6347FMI_BUD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD13 - bool "CY8C6347FMI_BUD13" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD43 - bool "CY8C6347FMI_BUD43" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347FMI_BUD33 - bool "CY8C6347FMI_BUD33" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6137WI_F54 - bool "CY8C6137WI_F54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6117WI_F34 - bool "CY8C6117WI_F34" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6247WI_D54 - bool "CY8C6247WI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6336LQI_BLF02 - bool "CY8C6336LQI_BLF02" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_68_QFN_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6336LQI_BLF42 - bool "CY8C6336LQI_BLF42" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_68_QFN_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CY8C6347LQI_BLD52 - bool "CY8C6347LQI_BLD52" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_68_QFN_BLE - depends on SOC_SERIES_PSOC_63 - -config SOC_CYB06447BZI_BLD54 - bool "CYB06447BZI_BLD54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA_SIP - depends on SOC_SERIES_PSOC_64 - -config SOC_CYB06447BZI_BLD53 - bool "CYB06447BZI_BLD53" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_116_BGA_BLE - depends on SOC_SERIES_PSOC_64 - -config SOC_CYB06447BZI_D54 - bool "CYB06447BZI_D54" - select SOC_DIE_PSOC6_01 - select SOC_PACKAGE_PSOC6_01_124_BGA - depends on SOC_SERIES_PSOC_64 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_02 b/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_02 deleted file mode 100644 index c9e9a92ba2d8b8..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_02 +++ /dev/null @@ -1,197 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_02 series MCUs - -config SOC_CYB0644ABZI_S2D44 - bool "CYB0644ABZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_64 - -config SOC_CYS0644ABZI_S2D44 - bool "CYS0644ABZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_64 - -config SOC_CY8C624ABZI_S2D44A0 - bool "CY8C624ABZI_S2D44A0" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ABZI_S2D44 - bool "CY8C624ABZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624AAZI_S2D44 - bool "CY8C624AAZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624AFNI_S2D43 - bool "CY8C624AFNI_S2D43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ABZI_S2D04 - bool "CY8C624ABZI_S2D04" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ABZI_S2D14 - bool "CY8C624ABZI_S2D14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624AAZI_S2D14 - bool "CY8C624AAZI_S2D14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248AZI_S2D14 - bool "CY8C6248AZI_S2D14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248BZI_S2D44 - bool "CY8C6248BZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248AZI_S2D44 - bool "CY8C6248AZI_S2D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248FNI_S2D43 - bool "CY8C6248FNI_S2D43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C614ABZI_S2F04 - bool "CY8C614ABZI_S2F04" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AAZI_S2F04 - bool "CY8C614AAZI_S2F04" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AFNI_S2F03 - bool "CY8C614AFNI_S2F03" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AAZI_S2F14 - bool "CY8C614AAZI_S2F14" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614ABZI_S2F44 - bool "CY8C614ABZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AAZI_S2F44 - bool "CY8C614AAZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614AFNI_S2F43 - bool "CY8C614AFNI_S2F43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148BZI_S2F44 - bool "CY8C6148BZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148AZI_S2F44 - bool "CY8C6148AZI_S2F44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_128_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148FNI_S2F43 - bool "CY8C6148FNI_S2F43" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_100_WLCSP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C624ABZI_D44 - bool "CY8C624ABZI_D44" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_124_BGA - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ALQI_S2D42 - bool "CY8C624ALQI_S2D42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C624ALQI_S2D02 - bool "CY8C624ALQI_S2D02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248LQI_S2D42 - bool "CY8C6248LQI_S2D42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6248LQI_S2D02 - bool "CY8C6248LQI_S2D02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C614ALQI_S2F42 - bool "CY8C614ALQI_S2F42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C614ALQI_S2F02 - bool "CY8C614ALQI_S2F02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148LQI_S2F42 - bool "CY8C6148LQI_S2F42" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6148LQI_S2F02 - bool "CY8C6148LQI_S2F02" - select SOC_DIE_PSOC6_02 - select SOC_PACKAGE_PSOC6_02_68_QFN - depends on SOC_SERIES_PSOC_61 diff --git a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_04 b/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_04 deleted file mode 100644 index b18e8ecaa825e3..00000000000000 --- a/soc/arm/infineon_cat1/psoc6/Kconfig.soc.psoc6_04 +++ /dev/null @@ -1,125 +0,0 @@ -# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or -# an affiliate of Cypress Semiconductor Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Infineon PSoC6_04 series MCUs - -config SOC_CY8C6244AZI_S4D92 - bool "CY8C6244AZI_S4D92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D92 - bool "CY8C6244LQI_S4D92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D93 - bool "CY8C6244AZI_S4D93" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D82 - bool "CY8C6244AZI_S4D82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D82 - bool "CY8C6244LQI_S4D82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D83 - bool "CY8C6244AZI_S4D83" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D62 - bool "CY8C6244AZI_S4D62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D62 - bool "CY8C6244LQI_S4D62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244AZI_S4D12 - bool "CY8C6244AZI_S4D12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6244LQI_S4D12 - bool "CY8C6244LQI_S4D12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_62 - -config SOC_CY8C6144AZI_S4F92 - bool "CY8C6144AZI_S4F92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F92 - bool "CY8C6144LQI_S4F92" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F93 - bool "CY8C6144AZI_S4F93" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F82 - bool "CY8C6144AZI_S4F82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F82 - bool "CY8C6144LQI_S4F82" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F83 - bool "CY8C6144AZI_S4F83" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_80_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F62 - bool "CY8C6144AZI_S4F62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F62 - bool "CY8C6144LQI_S4F62" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144AZI_S4F12 - bool "CY8C6144AZI_S4F12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_64_TQFP - depends on SOC_SERIES_PSOC_61 - -config SOC_CY8C6144LQI_S4F12 - bool "CY8C6144LQI_S4F12" - select SOC_DIE_PSOC6_04 - select SOC_PACKAGE_PSOC6_04_68_QFN - depends on SOC_SERIES_PSOC_61 diff --git a/soc/arm/infineon_xmc/4xxx/CMakeLists.txt b/soc/arm/infineon_xmc/4xxx/CMakeLists.txt deleted file mode 100644 index 8216f9a09ee8be..00000000000000 --- a/soc/arm/infineon_xmc/4xxx/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -zephyr_sources(soc.c) -zephyr_linker_sources(NOINIT noinit.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.series b/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.series deleted file mode 100644 index 2e92bd626bfb0c..00000000000000 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# XMC 4xxx series configuration options -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -if SOC_SERIES_XMC_4XXX - -config SOC_SERIES - default "4xxx" - -config NUM_IRQS - default 112 - -source "soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc*" - -endif # SOC_SERIES_XMC_4XXX diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.series b/soc/arm/infineon_xmc/4xxx/Kconfig.series deleted file mode 100644 index 7c7f9a85496fd3..00000000000000 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# XMC4xxx MCU series -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_XMC_4XXX - bool "XMC 4xxx Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_XMC - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select HAS_XMCLIB_UART - select HAS_XMCLIB_FLASH - select HAS_XMCLIB_ERU - select HAS_XMCLIB_VADC - select HAS_XMCLIB_DMA - select HAS_XMCLIB_SPI - select HAS_XMCLIB_I2C - select HAS_XMCLIB_CCU - select HAS_XMCLIB_WDT - select HAS_XMCLIB_ETH - select HAS_XMCLIB_CAN - help - Enable support for XMC 4xxx MCU series diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.soc b/soc/arm/infineon_xmc/4xxx/Kconfig.soc deleted file mode 100644 index 83fd92a23d3a76..00000000000000 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.soc +++ /dev/null @@ -1,38 +0,0 @@ -# XMC 4xxx MCU line -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "XMC 4xxx MCU Selection" - depends on SOC_SERIES_XMC_4XXX - -config SOC_XMC4500 - bool "SOC_XMC4500" - select HAS_XMCLIB - -config SOC_XMC4700 - bool "SOC_XMC4700" - select HAS_XMCLIB - -endchoice - -if SOC_SERIES_XMC_4XXX - -config SOC_PART_NUMBER_F100X1024 - bool - -config SOC_PART_NUMBER_F144X2048 - bool - -config SOC_PART_NUMBER_XMC_4XXX - string - default "F100x1024" if SOC_PART_NUMBER_F100X1024 - default "F144x2048" if SOC_PART_NUMBER_F144X2048 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_XMC_4XXX diff --git a/soc/arm/infineon_xmc/Kconfig b/soc/arm/infineon_xmc/Kconfig deleted file mode 100644 index 8252399754b959..00000000000000 --- a/soc/arm/infineon_xmc/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -config SOC_FAMILY_XMC - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select PLATFORM_SPECIFIC_INIT - -if SOC_FAMILY_XMC - -config SOC_FAMILY - string - default "infineon_xmc" - -source "soc/arm/infineon_xmc/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_XMC_4XXX if SOC_SERIES_XMC_4XXX - -endif # SOC_FAMILY_XMC diff --git a/soc/arm/infineon_xmc/Kconfig.defconfig b/soc/arm/infineon_xmc/Kconfig.defconfig deleted file mode 100644 index b7cd34f591a963..00000000000000 --- a/soc/arm/infineon_xmc/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -source "soc/arm/infineon_xmc/*/Kconfig.defconfig.series" - -if SOC_FAMILY_XMC - -config PINCTRL - default y - -endif # SOC_FAMILY_XMC diff --git a/soc/arm/infineon_xmc/Kconfig.soc b/soc/arm/infineon_xmc/Kconfig.soc deleted file mode 100644 index 05f2c3841c4ce6..00000000000000 --- a/soc/arm/infineon_xmc/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Parthiban Nallathambi - -source "soc/arm/infineon_xmc/*/Kconfig.series" diff --git a/soc/arm/intel_socfpga_std/CMakeLists.txt b/soc/arm/intel_socfpga_std/CMakeLists.txt deleted file mode 100644 index b2e4b540bf8068..00000000000000 --- a/soc/arm/intel_socfpga_std/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Intel Cyclone V SoC - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/intel_socfpga_std/Kconfig b/soc/arm/intel_socfpga_std/Kconfig deleted file mode 100644 index 22729a46343881..00000000000000 --- a/soc/arm/intel_socfpga_std/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support to Cyclone V SoC FPGA - -config SOC_FAMILY_INTEL_SOCFPGA_STD - bool - -if SOC_FAMILY_INTEL_SOCFPGA_STD -config SOC_FAMILY - string - default "intel_socfpga_std" - -source "soc/arm/intel_socfpga_std/*/Kconfig.soc" -endif diff --git a/soc/arm/intel_socfpga_std/Kconfig.defconfig b/soc/arm/intel_socfpga_std/Kconfig.defconfig deleted file mode 100644 index 1d1155a3c1b0e9..00000000000000 --- a/soc/arm/intel_socfpga_std/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -source "soc/arm/intel_socfpga_std/*/Kconfig.defconfig.series" diff --git a/soc/arm/intel_socfpga_std/Kconfig.soc b/soc/arm/intel_socfpga_std/Kconfig.soc deleted file mode 100644 index 207fa5a5c69278..00000000000000 --- a/soc/arm/intel_socfpga_std/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -source "soc/arm/intel_socfpga_std/*/Kconfig.series" diff --git a/soc/arm/intel_socfpga_std/cyclonev/CMakeLists.txt b/soc/arm/intel_socfpga_std/cyclonev/CMakeLists.txt deleted file mode 100644 index 4b94d9047e4831..00000000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -zephyr_include_directories(.) -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev deleted file mode 100644 index e627daf0f397a1..00000000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -if SOC_CYCLONE5 - -config SOC - default "intel_socfpga_std_cyclonev" - -config NUM_IRQS - int - default 211 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 231250000 - -endif diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.series b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.series deleted file mode 100644 index bdca517d2c3e5b..00000000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support for Cyclone V SoC FPGA - -if SOC_SERIES_CYCLONE5 - -config SOC_SERIES - default "cyclonev" - -source "soc/arm/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev*" - -endif # SOC_SERIES_CYCLONE5 diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.series b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.series deleted file mode 100644 index e9fba7bdba24e8..00000000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description -# Adding configuration options for Cyclone V SoC FPGA - -config SOC_SERIES_CYCLONE5 - bool "Intel SoC FPGA Cyclone5 Series" - select ARM - select CPU_CORTEX_A9 - select SOC_FAMILY_INTEL_SOCFPGA_STD - select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER - select ARCH_HAS_RESERVED_PAGE_FRAMES - help - Support for Intel SoC FPGA Series diff --git a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.soc b/soc/arm/intel_socfpga_std/cyclonev/Kconfig.soc deleted file mode 100644 index 8851d9e17b2252..00000000000000 --- a/soc/arm/intel_socfpga_std/cyclonev/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 -# Description: -# Adding support to Cyclone V SoC FPGA - -choice - prompt "Intel SoC FPGA Cyclone5" - depends on SOC_SERIES_CYCLONE5 - -config SOC_CYCLONE5 - bool "Intel SoC FPGA Cyclone5" -endchoice diff --git a/soc/arm/microchip_mec/Kconfig b/soc/arm/microchip_mec/Kconfig deleted file mode 100644 index 017344ab470d6d..00000000000000 --- a/soc/arm/microchip_mec/Kconfig +++ /dev/null @@ -1,222 +0,0 @@ -# Microchip MEC MCU line - -# Copyright (c) 2018, Intel Corporation -# Copyright (c) 2022, Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_MEC - bool - -if SOC_FAMILY_MEC -config SOC_FAMILY - string - default "microchip_mec" - -menuconfig MCHP_MEC_UNSIGNED_HEADER - bool "Create an unsigned output binary with MCHP MEC binary header" - help - On Microchip MEC series chip, the ROM code loads firmware image from flash - to RAM using a TAG to locate a Header which specifies the location and - size of the firmware image. Enable this to invoke the mec_spi_gen tool - which generates an SPI image with TAG, Header, and firmware binary. This - tool does not produce a signed image which can be authenticated by the - Boot-ROM. Use the full Microchip SPI image generator program for - authentication and all other Boot-ROM loader features. Refer to the MCHP - EVB boards for an example. - -if MCHP_MEC_UNSIGNED_HEADER - -config MCHP_MEC_HEADER_CHIP - string - default "mec152x" if SOC_SERIES_MEC1501X - default "mec172x" if SOC_SERIES_MEC172X - -choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE - prompt "Clock rate to use for SPI flash" - default MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 - help - This selects the SPI clock frequency that will be used for loading - firmware binary from flash to RAM. - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 - bool "SPI flash clock rate of 12 MHz" - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 - bool "SPI flash clock rate of 16 MHz" - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 - bool "SPI flash clock rate of 24 MHz" - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 - bool "SPI flash clock rate of 48 MHz" - -endchoice - -config MCHP_MEC_HEADER_SPI_FREQ_MHZ - int - default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 - default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 - default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 - default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 - -choice MCHP_MEC_HEADER_SPI_READ_MODE_CHOICE - prompt "Reading mode used by the SPI flash" - default MCHP_MEC_HEADER_SPI_READ_MODE_FAST - help - This sets the reading mode that can be used by the SPI flash. - Reading modes supported are normal, fast, dual, and quad. - -config MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL - bool "SPI flash operates full-duplex with frequency (< 25 MHz)" - -config MCHP_MEC_HEADER_SPI_READ_MODE_FAST - bool "SPI flash operates full-duplex with fast reading mode" - -config MCHP_MEC_HEADER_SPI_READ_MODE_DUAL - bool "SPI flash operates with dual data reading mode" - -config MCHP_MEC_HEADER_SPI_READ_MODE_QUAD - bool "SPI flash operates with quad data reading mode" - -endchoice - -config MCHP_MEC_HEADER_SPI_READ_MODE - string - default "slow" if MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL - default "fast" if MCHP_MEC_HEADER_SPI_READ_MODE_FAST - default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL - default "quad" if MCHP_MEC_HEADER_SPI_READ_MODE_QUAD - -choice MCHP_MEC_HEADER_FLASH_SIZE_CHOICE - prompt "Flash size" - default MCHP_MEC_HEADER_FLASH_SIZE_16M - help - This sets the SPI flash size. - -config MCHP_MEC_HEADER_FLASH_SIZE_256K - bool "SPI flash size 256K Bytes" - help - The SPI flash size is 256K Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_512K - bool "SPI flash size 512K Bytes" - help - The SPI flash size is 512K Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_1M - bool "SPI flash size 1M Bytes" - help - The SPI flash size is 1M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_2M - bool "SPI flash size 2M Bytes" - help - The SPI flash size is 2M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_4M - bool "SPI flash size 4M Bytes" - help - The SPI flash size is 4M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_8M - bool "SPI flash size 8M Bytes" - help - The SPI flash size is 8M Bytes. - -config MCHP_MEC_HEADER_FLASH_SIZE_16M - bool "SPI flash size 16M Bytes" - help - The SPI flash size is 16M Bytes. - -endchoice - -config MCHP_MEC_HEADER_FLASH_SIZE - int - default 256 if MCHP_MEC_HEADER_FLASH_SIZE_256K - default 512 if MCHP_MEC_HEADER_FLASH_SIZE_512K - default 1024 if MCHP_MEC_HEADER_FLASH_SIZE_1M - default 2048 if MCHP_MEC_HEADER_FLASH_SIZE_2M - default 4096 if MCHP_MEC_HEADER_FLASH_SIZE_4M - default 8192 if MCHP_MEC_HEADER_FLASH_SIZE_8M - default 16384 if MCHP_MEC_HEADER_FLASH_SIZE_16M - -choice MCHP_MEC_HEADER_SPI_DRVSTR_CHOICE - prompt "Flash drive strength" - default MCHP_MEC_HEADER_SPI_DRVSTR_1X - help - This sets the SPI flash size. - -config MCHP_MEC_HEADER_SPI_DRVSTR_1X - bool "SPI flash drive strength multiplier 1" - help - The SPI flash size is 256K Bytes. - -config MCHP_MEC_HEADER_SPI_DRVSTR_2X - bool "SPI flash drive strength multiplier 2" - help - The SPI flash size is 256K Bytes. - -config MCHP_MEC_HEADER_SPI_DRVSTR_4X - bool "SPI flash drive strength multiplier 4" - help - The SPI flash size is 512K Bytes. - -config MCHP_MEC_HEADER_SPI_DRVSTR_6X - bool "SPI flash drive strength multiplier 6" - help - The SPI flash size is 1M Bytes. - -endchoice - -config MCHP_MEC_HEADER_SPI_DRVSTR - string - default "1x" if MCHP_MEC_HEADER_SPI_DRVSTR_1X - default "2x" if MCHP_MEC_HEADER_SPI_DRVSTR_2X - default "4x" if MCHP_MEC_HEADER_SPI_DRVSTR_4X - default "6x" if MCHP_MEC_HEADER_SPI_DRVSTR_6X - -choice MCHP_MEC_HEADER_SPI_SLEW_RATE_CHOICE - prompt "Slew rate of SPI pins" - default MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW - help - This sets the slew rate of the SPI pins. Default is slow - slew rate which is 1/2 the AHB clock rate. Fast slew is the - AHB clock rate. - -config MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW - bool "SPI pins slew rate is 1/2 AHB frequency" - -config MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST - bool "SPI pins slew rate is 1x AHB frequency" - -endchoice - -config MCHP_MEC_HEADER_SPI_SLEW_RATE - string - default "slow" if MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW - default "fast" if MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST - -config MCHP_MEC_HEADER_FLASH_SPI_MODE - int "Flash SPI Mode" - range 0 7 - default 0 - help - This three bit value corresponds to the QMSPI controllers clock idle and - input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer - to the data sheet. Default value is 0 corresponding to SPI Mode 0 - signalling. - Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0 - Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1 - -config MCHP_HEADER_VERBOSE_OUTPUT - bool "Debug console output" - default n - help - Enable print output from SPI generator script for debug - -endif # MCHP_MEC_UNSIGNED_HEADER - -# Select SoC Part No. and configuration options -source "soc/arm/microchip_mec/*/Kconfig.soc" - -endif # SOC_FAMILY_MEC diff --git a/soc/arm/microchip_mec/Kconfig.defconfig b/soc/arm/microchip_mec/Kconfig.defconfig deleted file mode 100644 index f23bddaa1edaf2..00000000000000 --- a/soc/arm/microchip_mec/Kconfig.defconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/microchip_mec/*/Kconfig.defconfig.series" diff --git a/soc/arm/microchip_mec/Kconfig.soc b/soc/arm/microchip_mec/Kconfig.soc deleted file mode 100644 index 85734699608d1f..00000000000000 --- a/soc/arm/microchip_mec/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Microchip MEC172x, MEC1501 MCU line - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/microchip_mec/*/Kconfig.series" diff --git a/soc/arm/microchip_mec/common/CMakeLists.txt b/soc/arm/microchip_mec/common/CMakeLists.txt deleted file mode 100644 index fe1dc724ec9c0f..00000000000000 --- a/soc/arm/microchip_mec/common/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MEC172X - soc_i2c.c -) - -if (DEFINED CONFIG_MCHP_HEADER_VERBOSE_OUTPUT) - set(MCHP_HEADER_VERBOSE_OPTION "-v") -endif() - -if (DEFINED CONFIG_MCHP_MEC_UNSIGNED_HEADER) - set(MCHP_MEC_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.mchp.bin) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/spigen/mec_spi_gen.py - -i ${KERNEL_BIN_NAME} - -o ${MCHP_MEC_BIN_NAME} - -c ${CONFIG_MCHP_MEC_HEADER_CHIP} - -s ${CONFIG_MCHP_MEC_HEADER_FLASH_SIZE} - -f ${CONFIG_MCHP_MEC_HEADER_SPI_FREQ_MHZ} - -r ${CONFIG_MCHP_MEC_HEADER_SPI_READ_MODE} - -m ${CONFIG_MCHP_MEC_HEADER_FLASH_SPI_MODE} - --drvstr ${CONFIG_MCHP_MEC_HEADER_SPI_DRVSTR} - --slewrate ${CONFIG_MCHP_MEC_HEADER_SPI_SLEW_RATE} - ${MCHP_HEADER_VERBOSE_OPTION} - ) -endif() diff --git a/soc/arm/microchip_mec/mec1501/CMakeLists.txt b/soc/arm/microchip_mec/mec1501/CMakeLists.txt deleted file mode 100644 index e92250a6989158..00000000000000 --- a/soc/arm/microchip_mec/mec1501/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (c) 2019, Microchip Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - device_power.c - power.c - ) - -if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) - if(CONFIG_TIMING_FUNCTIONS) - # Use MEC15xx timing calculations only if DWT is not present - if(NOT CONFIG_CORTEX_M_DWT) - zephyr_library_sources(timing.c) - endif() - endif() -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.series b/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.series deleted file mode 100644 index bb0f205afcae97..00000000000000 --- a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Microchip MEC MCU series configuration options - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MEC1501X - -config SOC_SERIES - default "mec1501" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # All NVIC external sources. - default 174 - -source "soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501*" - -if RTOS_TIMER - -config SOC_HAS_TIMING_FUNCTIONS - default y if !CORTEX_M_DWT - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y - -endif # RTOS_TIMER - -config CORTEX_M_SYSTICK - depends on !RTOS_TIMER - -endif # SOC_SERIES_MEC1501X diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.series b/soc/arm/microchip_mec/mec1501/Kconfig.series deleted file mode 100644 index 92dc6f3f8f9f8f..00000000000000 --- a/soc/arm/microchip_mec/mec1501/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Microchip MEC1501 MCU core series - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MEC1501X - bool "Microchip MEC1501X Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_MEC - select HAS_PM - help - Enable support for Microchip MEC Cortex-M4 MCU series diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.soc b/soc/arm/microchip_mec/mec1501/Kconfig.soc deleted file mode 100644 index 51db7329f98687..00000000000000 --- a/soc/arm/microchip_mec/mec1501/Kconfig.soc +++ /dev/null @@ -1,97 +0,0 @@ -# Microchip MEC1501 MCU core series - -# Copyright (c) 2018 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "MEC1501 Selection" - depends on SOC_SERIES_MEC1501X - -config SOC_MEC1501_HSZ - bool "MEC1501_HSZ" - select HAS_MEC_HAL - -endchoice - -config RTOS_TIMER - bool "MEC1501 RTOS timer" - -config SOC_MEC1501_PROC_CLK_DIV - int "PROC_CLK_DIV" - default 1 - range 1 48 - help - This divisor defines a ratio between processor clock (HCLK) - and master clock (MCK): - HCLK = MCK / PROC_CLK_DIV - Allowed divider values: 1, 3, 4, 16, and 48. - -config SOC_MEC1501_VTR3_1_8V - bool "VTR3 power rail is tied to 1.8V" - help - Set this is if VTR3 power sourcejumper in the board is changed. - -config SOC_MEC1501_VCI_PINS_AS_GPIOS - bool "Use VCI block pins as GPIOS" - default y - help - By default these pins are not GPIOs, but HW controlled. - Set this if VCI pin block HW logic is not required in the board - design. - -choice - prompt "MEC1501 debug interface general configuration" - default SOC_MEC1501_DEBUG_WITHOUT_TRACING - depends on SOC_SERIES_MEC1501X - help - Select Debug SoC interface support for MEC15xx SoC family - - config SOC_MEC1501_DEBUG_DISABLED - bool "Disable debug support" - help - Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# - pin is ignored. All other JTAG pins can be used as GPIOs - or other non-JTAG alternate functions. - - config SOC_MEC1501_DEBUG_WITHOUT_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode. UART2 and ADC00-03 can be used. - - config SOC_MEC1501_DEBUG_AND_TRACING - bool "Debug support via Serial wire debug with tracing enabled" - help - JTAG port is enabled in SWD mode. Refer to tracing options - to see if ADC00-03 can be used or not. - -endchoice - -choice - prompt "MEC1501 debug interface trace configuration" - default SOC_MEC1501_DEBUG_AND_ETM_TRACING - depends on SOC_MEC1501_DEBUG_AND_TRACING - help - Select tracing mode for debug interface - - config SOC_MEC1501_DEBUG_AND_ETM_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode and SWV as tracing method. - UART2 can be used, but ADC00-03 cannot. - - config SOC_MEC1501_DEBUG_AND_SWV_TRACING - bool "debug support via Serial Wire Debug and Viewer" - help - JTAG port in SWD mode and SWV as tracing method. - UART2 cannot be used. ADC00-03 can be used. -endchoice - -# GPIO initialization depends on SOC initialization, which happen at -# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be -# higher than that. -if GPIO - -config GPIO_INIT_PRIORITY - default 41 - -endif # GPIO diff --git a/soc/arm/microchip_mec/mec172x/CMakeLists.txt b/soc/arm/microchip_mec/mec172x/CMakeLists.txt deleted file mode 100644 index 59f3b5e4d2bca7..00000000000000 --- a/soc/arm/microchip_mec/mec172x/CMakeLists.txt +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (c) 2021, Microchip Technology Inc. -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -if(CONFIG_PM) - zephyr_library_sources(power.c device_power.c) -endif() - -if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) - if(CONFIG_TIMING_FUNCTIONS) - # Use MEC172x timing calculations only if DWT is not present - if(NOT CONFIG_CORTEX_M_DWT) - zephyr_library_sources(timing.c) - endif() - endif() -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series b/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series deleted file mode 100644 index d23de11262d152..00000000000000 --- a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.series +++ /dev/null @@ -1,36 +0,0 @@ -# Microchip MEC MCU series configuration options - -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MEC172X - -config SOC_SERIES - default "mec172x" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # All NVIC external sources. - default 181 - -source "soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172x*" - -if RTOS_TIMER - -config SOC_HAS_TIMING_FUNCTIONS - default y if !CORTEX_M_DWT - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y - -endif # RTOS_TIMER - -config CORTEX_M_SYSTICK - depends on !RTOS_TIMER - -config PS2_XEC - default y - depends on PS2 - -endif # SOC_SERIES_MEC172X diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.series b/soc/arm/microchip_mec/mec172x/Kconfig.series deleted file mode 100644 index cb62a2bbfa91fd..00000000000000 --- a/soc/arm/microchip_mec/mec172x/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Microchip MEC172X MCU core series - -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MEC172X - bool "Microchip MEC172X Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_MEC - select HAS_SWO - select HAS_PM - help - Enable support for Microchip MEC Cortex-M4F MCU series diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.soc b/soc/arm/microchip_mec/mec172x/Kconfig.soc deleted file mode 100644 index d5f256605d0f7d..00000000000000 --- a/soc/arm/microchip_mec/mec172x/Kconfig.soc +++ /dev/null @@ -1,84 +0,0 @@ -# Microchip MEC172x MCU core series - -# Copyright (c) 2021 Microchip Technology Inc. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "MEC172x Selection" - depends on SOC_SERIES_MEC172X - -config SOC_MEC172X_NSZ - bool "MEC172X_NSZ" -config SOC_MEC172X_NLJ - bool "MEC172X_NLJ" - -endchoice - -config RTOS_TIMER - bool "MEC172x RTOS Timer(32KHz) as kernel timer" - -config SOC_MEC172X_PROC_CLK_DIV - int "PROC_CLK_DIV" - default 1 - range 1 48 - help - This divisor defines a ratio between processor clock (HCLK) - and main 96 MHz clock (MCK): - HCLK = MCK / PROC_CLK_DIV - Allowed divider values: 1, 3, 4, 16, and 48. - -choice - prompt "MEC172x debug interface general configuration" - default SOC_MEC172X_DEBUG_WITHOUT_TRACING - depends on SOC_SERIES_MEC172X - help - Select Debug SoC interface support for MEC172X SoC family - - config SOC_MEC172X_DEBUG_DISABLED - bool "Disable debug support" - help - Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# - pin is ignored. All other JTAG pins can be used as GPIOs - or other non-JTAG alternate functions. - - config SOC_MEC172X_DEBUG_WITHOUT_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode. I2C09 and ADC00-03 can be used. - - config SOC_MEC172X_DEBUG_AND_TRACING - bool "Debug support via Serial wire debug with tracing enabled" - help - JTAG port is enabled in SWD mode. Refer to tracing options - to see if ADC00-03 can be used or not. -endchoice - -choice - prompt "MEC172X debug interface trace configuration" - default SOC_MEC172X_DEBUG_AND_ETM_TRACING - depends on SOC_MEC172X_DEBUG_AND_TRACING - help - Select tracing mode for debug interface - - config SOC_MEC172X_DEBUG_AND_ETM_TRACING - bool "Debug support via Serial wire debug" - help - JTAG port in SWD mode and ETM as tracing method. - I2C09 can be used, but ADC00-03 cannot. - - config SOC_MEC172X_DEBUG_AND_SWV_TRACING - bool "debug support via Serial Wire Debug and Viewer" - help - JTAG port in SWD mode and SWV as tracing method. - I2C09 cannot be used. ADC00-03 can be used. -endchoice - -# GPIO initialization depends on ECIA initialization, which happen at -# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be -# higher than that. -if GPIO - -config GPIO_INIT_PRIORITY - default 41 - -endif # GPIO diff --git a/soc/arm/mps2/CMakeLists.txt b/soc/arm/mps2/CMakeLists.txt new file mode 100644 index 00000000000000..5beaeea5684b10 --- /dev/null +++ b/soc/arm/mps2/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/mps2/Kconfig b/soc/arm/mps2/Kconfig new file mode 100644 index 00000000000000..248be2250a21c5 --- /dev/null +++ b/soc/arm/mps2/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2017-2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS2 + select ARM + select GPIO_MMIO32 if GPIO + +config SOC_MPS2_AN521 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + +config SOC_MPS2_AN385 + select CPU_CORTEX_M3 + select CPU_HAS_ARM_MPU + +config SOC_MPS2_AN521_CPU0 + select CPU_HAS_ARM_SAU + +config SOC_MPS2_AN521_CPU1 + select CPU_HAS_FPU + select ARMV8_M_DSP diff --git a/soc/arm/mps2/Kconfig.defconfig b/soc/arm/mps2/Kconfig.defconfig new file mode 100644 index 00000000000000..3804dd607091d0 --- /dev/null +++ b/soc/arm/mps2/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MPS2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_MPS2 diff --git a/soc/arm/mps2/Kconfig.defconfig.an385 b/soc/arm/mps2/Kconfig.defconfig.an385 new file mode 100644 index 00000000000000..fbcec3977f1126 --- /dev/null +++ b/soc/arm/mps2/Kconfig.defconfig.an385 @@ -0,0 +1,9 @@ +# Copyright (c) 2017 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MPS2_AN385 + +config NUM_IRQS + default 32 + +endif diff --git a/soc/arm/mps2/Kconfig.defconfig.an521 b/soc/arm/mps2/Kconfig.defconfig.an521 new file mode 100644 index 00000000000000..944bdf4f067b07 --- /dev/null +++ b/soc/arm/mps2/Kconfig.defconfig.an521 @@ -0,0 +1,9 @@ +# Copyright (c) 2018-2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MPS2_AN521 + +config NUM_IRQS + default 96 + +endif diff --git a/soc/arm/mps2/Kconfig.soc b/soc/arm/mps2/Kconfig.soc new file mode 100644 index 00000000000000..bc9fa98fdcc6c8 --- /dev/null +++ b/soc/arm/mps2/Kconfig.soc @@ -0,0 +1,37 @@ +# Copyright (c) 2017-2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS2 + bool + select SOC_FAMILY_ARM + help + Enable support for ARM MPS2 MCU Series + +config SOC_MPS2_AN385 + bool + select SOC_SERIES_MPS2 + help + ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385) + +config SOC_MPS2_AN521 + bool + select SOC_SERIES_MPS2 + +config SOC_MPS2_AN521_CPU0 + bool + select SOC_MPS2_AN521 + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU0 + +config SOC_MPS2_AN521_CPU1 + bool + select SOC_MPS2_AN521 + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MPS2+ (AN521) CPU1 + +config SOC_SERIES + default "mps2" if SOC_SERIES_MPS2 + +config SOC + default "an385" if SOC_MPS2_AN385 + default "an521" if SOC_MPS2_AN521 diff --git a/soc/arm/mps2/soc.c b/soc/arm/mps2/soc.c new file mode 100644 index 00000000000000..343330d4515c80 --- /dev/null +++ b/soc/arm/mps2/soc.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * Initial contents based on soc/soc_legacy/arm/ti_lm3s6965/soc.c which is: + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include + + +/* Setup GPIO drivers for accessing FPGAIO registers */ +#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio) +#define FPGAIO_INIT(n) \ + GPIO_MMIO32_INIT(FPGAIO_NODE(n), \ + DT_REG_ADDR(FPGAIO_NODE(n)), \ + BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios))) + +/* We expect there to be 3 arm,mps2-fpgaio-gpio devices: + * led0, button, and misc + */ +FPGAIO_INIT(0); +FPGAIO_INIT(1); +FPGAIO_INIT(2); + +/* (Secure System Control) Base Address */ +#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL) +#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114) +#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118) +#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL) + +/* The base address that the application image will start at on the secondary + * (non-TrustZone) Cortex-M33 mcu. + */ +#define CPU1_FLASH_ADDRESS (0x38B000) + +/* The memory map offset for the application image, which is used + * to determine the location of the reset vector at startup. + */ +#define CPU1_FLASH_OFFSET (0x10000000) + +/** + * @brief Wake up CPU 1 from another CPU, this is platform specific. + */ +void wakeup_cpu1(void) +{ + /* Set the Initial Secure Reset Vector Register for CPU 1 */ + *(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) = + (uint32_t)_vector_start + + CPU1_FLASH_ADDRESS - + CPU1_FLASH_OFFSET; + + /* Set the CPU Boot wait control after reset */ + *(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0; +} + +/** + * @brief Get the current CPU ID, this is platform specific. + * + * @return Current CPU ID + */ +uint32_t sse_200_platform_get_cpu_id(void) +{ + volatile uint32_t *p_cpu_id = (volatile uint32_t *)SSE_200_CPU_ID_UNIT_BASE; + + return (uint32_t)*p_cpu_id; +} diff --git a/soc/arm/arm/mps2/soc.h b/soc/arm/mps2/soc.h similarity index 100% rename from soc/arm/arm/mps2/soc.h rename to soc/arm/mps2/soc.h diff --git a/soc/arm/arm/mps2/soc_registers.h b/soc/arm/mps2/soc_registers.h similarity index 100% rename from soc/arm/arm/mps2/soc_registers.h rename to soc/arm/mps2/soc_registers.h diff --git a/soc/arm/mps3/CMakeLists.txt b/soc/arm/mps3/CMakeLists.txt new file mode 100644 index 00000000000000..3cf33caa58dbaf --- /dev/null +++ b/soc/arm/mps3/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/mps3/Kconfig b/soc/arm/mps3/Kconfig new file mode 100644 index 00000000000000..06c1af46d5d2b0 --- /dev/null +++ b/soc/arm/mps3/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2017-2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS3 + select ARM + select GPIO_MMIO32 if GPIO + +config SOC_MPS3_AN547 + select CPU_CORTEX_M55 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARMV8_1_M_MVEI + select ARMV8_1_M_MVEF + select ARMV8_1_M_PMU + +config ARMV8_1_M_PMU_EVENTCNT + int + default 8 if SOC_MPS3_AN547 diff --git a/soc/arm/mps3/Kconfig.defconfig b/soc/arm/mps3/Kconfig.defconfig new file mode 100644 index 00000000000000..449b87d33a179c --- /dev/null +++ b/soc/arm/mps3/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MPS3 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 + +rsource "Kconfig.defconfig.mps3*" + +endif # SOC_SERIES_MPS3 diff --git a/soc/arm/arm/mps3/Kconfig.defconfig.mps3_an547 b/soc/arm/mps3/Kconfig.defconfig.mps3_an547 similarity index 79% rename from soc/arm/arm/mps3/Kconfig.defconfig.mps3_an547 rename to soc/arm/mps3/Kconfig.defconfig.mps3_an547 index 870bbb46c0b021..0961808eae213a 100644 --- a/soc/arm/arm/mps3/Kconfig.defconfig.mps3_an547 +++ b/soc/arm/mps3/Kconfig.defconfig.mps3_an547 @@ -3,9 +3,6 @@ if SOC_MPS3_AN547 -config SOC - default "mps3_an547" - config NUM_IRQS default 128 diff --git a/soc/arm/mps3/Kconfig.soc b/soc/arm/mps3/Kconfig.soc new file mode 100644 index 00000000000000..99bb1fb78c496e --- /dev/null +++ b/soc/arm/mps3/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2017-2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MPS3 + bool + select SOC_FAMILY_ARM + help + Enable support for ARM MPS3 MCU Series + +config SOC_SERIES + default "mps3" if SOC_SERIES_MPS3 + +config SOC_MPS3_AN547 + bool + select SOC_SERIES_MPS3 + +config SOC + default "an547" if SOC_MPS3_AN547 diff --git a/soc/arm/arm/mps3/soc.c b/soc/arm/mps3/soc.c similarity index 100% rename from soc/arm/arm/mps3/soc.c rename to soc/arm/mps3/soc.c diff --git a/soc/arm/arm/mps3/soc.h b/soc/arm/mps3/soc.h similarity index 100% rename from soc/arm/arm/mps3/soc.h rename to soc/arm/mps3/soc.h diff --git a/soc/arm/musca/CMakeLists.txt b/soc/arm/musca/CMakeLists.txt new file mode 100644 index 00000000000000..988efa1875817d --- /dev/null +++ b/soc/arm/musca/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2018 Linaro Limited +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_V2M_MUSCA_B1) + zephyr_sources(b1/soc.c) + zephyr_include_directories(b1) +elseif(CONFIG_SOC_V2M_MUSCA_S1) + zephyr_include_directories(s1) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/musca/Kconfig b/soc/arm/musca/Kconfig new file mode 100644 index 00000000000000..83abe182c1e648 --- /dev/null +++ b/soc/arm/musca/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MUSCA + select ARM + select BUILD_OUTPUT_HEX + +config SOC_V2M_MUSCA_B1 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_DWT + +config SOC_V2M_MUSCA_S1 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select ARMV8_M_DSP diff --git a/soc/arm/musca/Kconfig.defconfig b/soc/arm/musca/Kconfig.defconfig new file mode 100644 index 00000000000000..8f457d9d50b2a9 --- /dev/null +++ b/soc/arm/musca/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 40000000 if SOC_V2M_MUSCA_B1 + default 50000000 if SOC_V2M_MUSCA_S1 + +config NUM_IRQS + default 96 if SOC_SERIES_MUSCA diff --git a/soc/arm/musca/Kconfig.soc b/soc/arm/musca/Kconfig.soc new file mode 100644 index 00000000000000..3c81f3d5713e92 --- /dev/null +++ b/soc/arm/musca/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MUSCA + bool + select SOC_FAMILY_ARM + help + ARM v2m MUSCA MCU Series + +config SOC_V2M_MUSCA_B1 + bool + select SOC_SERIES_MUSCA + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-B1 + +config SOC_V2M_MUSCA_S1 + bool + select SOC_SERIES_MUSCA + help + ARM Cortex-M33 SMM-SSE-200 on V2M-MUSCA-S1 + +config SOC_SERIES + default "musca" if SOC_SERIES_MUSCA + +config SOC + default "musca_b1" if SOC_V2M_MUSCA_B1 + default "musca_s1" if SOC_V2M_MUSCA_S1 diff --git a/soc/arm/arm/musca_b1/soc.c b/soc/arm/musca/b1/soc.c similarity index 100% rename from soc/arm/arm/musca_b1/soc.c rename to soc/arm/musca/b1/soc.c diff --git a/soc/arm/arm/musca_b1/soc.h b/soc/arm/musca/b1/soc.h similarity index 100% rename from soc/arm/arm/musca_b1/soc.h rename to soc/arm/musca/b1/soc.h diff --git a/soc/arm/arm/musca_b1/system_cmsdk_musca_b1.h b/soc/arm/musca/b1/system_cmsdk_musca_b1.h similarity index 100% rename from soc/arm/arm/musca_b1/system_cmsdk_musca_b1.h rename to soc/arm/musca/b1/system_cmsdk_musca_b1.h diff --git a/soc/arm/arm/musca_s1/soc.h b/soc/arm/musca/s1/soc.h similarity index 100% rename from soc/arm/arm/musca_s1/soc.h rename to soc/arm/musca/s1/soc.h diff --git a/soc/arm/arm/musca_s1/system_cmsdk_musca_s1.h b/soc/arm/musca/s1/system_cmsdk_musca_s1.h similarity index 100% rename from soc/arm/arm/musca_s1/system_cmsdk_musca_s1.h rename to soc/arm/musca/s1/system_cmsdk_musca_s1.h diff --git a/soc/arm/nordic_nrf/CMakeLists.txt b/soc/arm/nordic_nrf/CMakeLists.txt deleted file mode 100644 index bd7725404b8c7e..00000000000000 --- a/soc/arm/nordic_nrf/CMakeLists.txt +++ /dev/null @@ -1,34 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) - -zephyr_library_sources( - validate_base_addresses.c - validate_enabled_instances.c - ) - -if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) - if(CONFIG_TIMING_FUNCTIONS) - # Use nRF-specific timing calculations only if DWT is not present - if(NOT CONFIG_CORTEX_M_DWT) - zephyr_library_sources(timing.c) - endif() - endif() -endif() - -if(CONFIG_BUILD_WITH_TFM) - set_property(TARGET zephyr_property_target - APPEND PROPERTY TFM_CMAKE_OPTIONS -DHAL_NORDIC_PATH=${ZEPHYR_HAL_NORDIC_MODULE_DIR} - ) - - set_property(TARGET zephyr_property_target - APPEND PROPERTY TFM_CMAKE_OPTIONS -DZEPHYR_BASE=${ZEPHYR_BASE} - ) - - set_property(TARGET zephyr_property_target - APPEND PROPERTY TFM_CMAKE_OPTIONS -DNRF_NS_STORAGE=${CONFIG_TFM_NRF_NS_STORAGE} - ) -endif() diff --git a/soc/arm/nordic_nrf/Kconfig b/soc/arm/nordic_nrf/Kconfig deleted file mode 100644 index b2d164e7c78497..00000000000000 --- a/soc/arm/nordic_nrf/Kconfig +++ /dev/null @@ -1,175 +0,0 @@ -# Nordic Semiconductor nRFx MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NRF - select SOC_COMPATIBLE_NRF - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_NRF -config SOC_FAMILY - string - default "nordic_nrf" - -source "soc/common/nordic_nrf/Kconfig.peripherals" -source "soc/arm/nordic_nrf/*/Kconfig.soc" - -config NRF_SOC_SECURE_SUPPORTED - def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM) - depends on !SOC_SERIES_NRF54HX - help - Hidden function to indicate that that the soc_secure functions are - available. - The functions are always available when not in non-secure. - For non-secure the functions must redirect to secure services exposed - by the secure firmware. - -config BUILD_WITH_TFM - default y if TRUSTED_EXECUTION_NONSECURE - help - By default, if we build for a Non-Secure version of the board, - enable building with TF-M as the Secure Execution Environment. - -if BUILD_WITH_TFM - -config TFM_FLASH_MERGED_BINARY - default y - help - By default, if we build with TF-M, instruct build system to - flash the combined TF-M (Secure) & Zephyr (Non Secure) image - -config TFM_LOG_LEVEL_SILENCE - default y if !$(dt_nodelabel_has_prop,uart1,pinctrl-names) - help - Disable TF-M secure output if the uart1 node has not assigned GPIO - pins using pinctrl. - -config TFM_NRF_NS_STORAGE - bool "TF-M non-secure storage partition" - default y - -endif # BUILD_WITH_TFM - - -config NRF_MPU_FLASH_REGION_SIZE - hex - default 0x1000 - depends on HAS_HW_NRF_MPU - help - FLASH region size for the NRF_MPU peripheral. - -config NRF_BPROT_FLASH_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) - depends on HAS_HW_NRF_BPROT - help - FLASH region size for the NRF_BPROT peripheral (nRF52). - -config NRF_ACL_FLASH_REGION_SIZE - hex - default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) - depends on HAS_HW_NRF_ACL - help - FLASH region size for the NRF_ACL peripheral. - -config NFCT_PINS_AS_GPIOS - bool "[DEPRECATED] NFCT pins as GPIOs" - depends on $(dt_has_compat,$(DT_COMPAT_NORDIC_NRF_NFCT)) - select DEPRECATED - help - Two pins are usually reserved for NFC in SoCs that implement the - NFCT peripheral. This option switches them to normal GPIO mode. - HW enabling happens once in the device lifetime, during the first - system startup. Disabling this option will not switch back these - pins to NFCT mode. Doing this requires UICR erase prior to - flashing device using the image which has this option disabled. - - NFC pins in nRF52 series: P0.09 and P0.10 - NFC pins in nRF5340: P0.02 and P0.03 - - This option is deprecated, please use devicetree to configure NFCT - pins as GPIOS like this: - - &uicr { - nfct-pins-as-gpios; - }; - -choice NRF_APPROTECT_HANDLING - bool "APPROTECT handling" - depends on SOC_SERIES_NRF52X || SOC_NRF5340_CPUNET || \ - (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) || \ - SOC_SERIES_NRF91X - default NRF_APPROTECT_USE_UICR - help - Specifies how the SystemInit() function should handle the APPROTECT - mechanism. - -config NRF_APPROTECT_USE_UICR - bool "Use UICR" - help - When this option is selected, the SystemInit() function loads the - firmware branch state of the APPROTECT mechanism from UICR, so if - UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. - -config NRF_APPROTECT_LOCK - bool "Lock" - help - When this option is selected, the SystemInit() function locks - the firmware branch of the APPROTECT mechanism, preventing it - from being opened. - -config NRF_APPROTECT_USER_HANDLING - bool "Allow user handling" - depends on !SOC_SERIES_NRF52X - help - When this option is selected, the SystemInit() function does not - touch the APPROTECT mechanism, allowing the user code to handle it - at later stages, for example, to implement authenticated debug. - -endchoice - -choice NRF_SECURE_APPROTECT_HANDLING - bool "Secure APPROTECT handling" - depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) - default NRF_SECURE_APPROTECT_USE_UICR - help - Specifies how the SystemInit() function should handle the secure - APPROTECT mechanism. - -config NRF_SECURE_APPROTECT_USE_UICR - bool "Use UICR" - help - When this option is selected, the SystemInit() function loads the - firmware branch state of the secure APPROTECT mechanism from UICR, - so if UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT - will be disabled. - -config NRF_SECURE_APPROTECT_LOCK - bool "Lock" - help - When this option is selected, the SystemInit() function locks the - firmware branch of the secure APPROTECT mechanism, preventing it - from being opened. - -config NRF_SECURE_APPROTECT_USER_HANDLING - bool "Allow user handling" - depends on !SOC_SERIES_NRF52X - help - When this option is selected, the SystemInit() function does not - touch the secure APPROTECT mechanism, allowing the user code to - handle it at later stages, for example, to implement authenticated - debug. - -endchoice - -config NRF_TRACE_PORT - bool "nRF TPIU" - depends on !SOC_SERIES_NRF51X - help - Enable this option to initialize the TPIU (Trace Port Interface - Unit) for tracing using a hardware probe. If disabled, the trace - pins will be used as GPIO. - -endif # SOC_FAMILY_NRF diff --git a/soc/arm/nordic_nrf/Kconfig.defconfig b/soc/arm/nordic_nrf/Kconfig.defconfig deleted file mode 100644 index ad3c97443ffa1c..00000000000000 --- a/soc/arm/nordic_nrf/Kconfig.defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# Nordic Semiconductor nRFx MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_NRF - -source "soc/arm/nordic_nrf/*/Kconfig.defconfig.series" - -# If the kernel has timer support, enable clock control -if SYS_CLOCK_EXISTS - -config CLOCK_CONTROL - default y if !SOC_SERIES_NRF54HX - -endif # SYS_CLOCK_EXISTS - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 if NRF_GRTC_TIMER - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 128 if !TICKLESS_KERNEL - default 10000 if NRF_GRTC_TIMER - default 32768 - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y if !QEMU_TARGET - -config BUILD_OUTPUT_HEX - default y - -if !CORTEX_M_DWT && NRF_RTC_TIMER -config SOC_HAS_TIMING_FUNCTIONS - default y -endif - -config GPIO - default y - depends on SPI - -config UART_USE_RUNTIME_CONFIGURE - default n - -endif # SOC_FAMILY_NRF diff --git a/soc/arm/nordic_nrf/Kconfig.soc b/soc/arm/nordic_nrf/Kconfig.soc deleted file mode 100644 index 1eda7294674df7..00000000000000 --- a/soc/arm/nordic_nrf/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Nordic Semiconductor nRFx MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nordic_nrf/*/Kconfig.series" diff --git a/soc/arm/nordic_nrf/common/CMakeLists.txt b/soc/arm/nordic_nrf/common/CMakeLists.txt deleted file mode 100644 index ea05f3d369e5ab..00000000000000 --- a/soc/arm/nordic_nrf/common/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_NRF soc_nrf_common.S) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -zephyr_include_directories(.) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") - -if (CONFIG_TFM_PARTITION_PLATFORM) - zephyr_library_sources(soc_secure.c) - zephyr_library_include_directories( - $/api_ns/interface/include - ) -endif() diff --git a/soc/arm/nordic_nrf/nrf51/CMakeLists.txt b/soc/arm/nordic_nrf/nrf51/CMakeLists.txt deleted file mode 100644 index 35d47fb252bc8c..00000000000000 --- a/soc/arm/nordic_nrf/nrf51/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAA b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAA deleted file mode 100644 index ada60bd28f450c..00000000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAA +++ /dev/null @@ -1,9 +0,0 @@ -# Nordic Semiconductor nRF51822 MCU - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "nRF51822_QFAA" - depends on SOC_NRF51822_QFAA diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAB b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAB deleted file mode 100644 index a1027b4cfd8e95..00000000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAB +++ /dev/null @@ -1,9 +0,0 @@ -# Nordic Semiconductor nRF51822 MCU - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "nRF51822_QFAB" - depends on SOC_NRF51822_QFAB diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAC b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAC deleted file mode 100644 index 7f92c991dec908..00000000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51822_QFAC +++ /dev/null @@ -1,9 +0,0 @@ -# Nordic Semiconductor nRF51822 MCU - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2016 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "nRF51822_QFAC" - depends on SOC_NRF51822_QFAC diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.series deleted file mode 100644 index a4053bf7fed035..00000000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Nordic Semiconductor nRF51 MCU line - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF51X - -source "soc/arm/nordic_nrf/nrf51/Kconfig.defconfig.nrf51*" - -config SOC_SERIES - default "nrf51" - -config NUM_IRQS - default 26 - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF51X diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.series b/soc/arm/nordic_nrf/nrf51/Kconfig.series deleted file mode 100644 index c484d44fc30fc9..00000000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF51 MCU line - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF51X - bool "Nordic Semiconductor nRF51 series MCU" - select ARM - select CPU_CORTEX_M0 - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_POWEROFF - help - Enable support for NRF51 MCU series diff --git a/soc/arm/nordic_nrf/nrf51/Kconfig.soc b/soc/arm/nordic_nrf/nrf51/Kconfig.soc deleted file mode 100644 index aa42e2a729ad2f..00000000000000 --- a/soc/arm/nordic_nrf/nrf51/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Nordic Semiconductor nRF51 MCU line - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "nRF51x MCU Selection" - depends on SOC_SERIES_NRF51X - -config SOC_NRF51822_QFAA - bool "NRF51822_QFAA" - -config SOC_NRF51822_QFAB - bool "NRF51822_QFAB" - -config SOC_NRF51822_QFAC - bool "NRF51822_QFAC" - -endchoice diff --git a/soc/arm/nordic_nrf/nrf52/CMakeLists.txt b/soc/arm/nordic_nrf/nrf52/CMakeLists.txt deleted file mode 100644 index 1b7d4d5257a1df..00000000000000 --- a/soc/arm/nordic_nrf/nrf52/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) - -if(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 AND CONFIG_SPI_NRFX_SPIM) - message(WARNING "Both SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 and an NRF SPIM driver are enabled, therefore PAN 58 will apply if RXD.MAXCNT == 1 and TXD.MAXCNT <= 1") -endif() - -if(CONFIG_SOC_NRF52832) - if(NOT CONFIG_NRF52_ANOMALY_109_WORKAROUND) - if (CONFIG_NRFX_SPIS OR CONFIG_NRFX_SPIM OR CONFIG_NRFX_TWIM OR CONFIG_NRFX_PWM) - message(WARNING "NRF52_ANOMALY_109_WORKAROUND disabled with SPIS, SPIM, TWIM or PWM enabled. This will occasionally cause the first byte transmitted to be incorrect") - endif() - endif() -endif() diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.series deleted file mode 100644 index 2e89a5130a6810..00000000000000 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF52 MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF52X - -source "soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52*" - -config SOC_SERIES - default "nrf52" - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF52X diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.series b/soc/arm/nordic_nrf/nrf52/Kconfig.series deleted file mode 100644 index d47089cd5953d9..00000000000000 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Nordic Semiconductor nRF52 MCU line - -# Copyright (c) 2016-2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF52X - bool "Nordic Semiconductor nRF52 series MCU" - select ARM - select SOC_COMPATIBLE_NRF52X - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_SWO - select HAS_POWEROFF - help - Enable support for NRF52 MCU series diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.soc b/soc/arm/nordic_nrf/nrf52/Kconfig.soc deleted file mode 100644 index de6a16129d3785..00000000000000 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.soc +++ /dev/null @@ -1,158 +0,0 @@ -# Nordic Semiconductor nRF52 MCU line - -# Copyright (c) 2016-2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF52X - -config SOC_NRF52805 - bool - -config SOC_NRF52810 - bool - -config SOC_NRF52811 - bool - -config SOC_NRF52820 - bool - -config SOC_NRF52832 - bool - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - -config SOC_NRF52833 - bool - select SOC_COMPATIBLE_NRF52833 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - -config SOC_NRF52840 - bool - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - -choice - prompt "nRF52x MCU Selection" - -config SOC_NRF52805_CAAA - bool "NRF52805_CAAA" - select SOC_NRF52805 - -config SOC_NRF52810_QFAA - bool "NRF52810_QFAA" - select SOC_NRF52810 - -config SOC_NRF52811_QFAA - bool "NRF52811_QFAA" - select SOC_NRF52811 - -config SOC_NRF52820_QDAA - bool "NRF52820_QDAA" - select SOC_NRF52820 - -config SOC_NRF52832_CIAA - bool "NRF52832_CIAA" - select SOC_NRF52832 - -config SOC_NRF52832_QFAA - bool "NRF52832_QFAA" - select SOC_NRF52832 - -config SOC_NRF52832_QFAB - bool "NRF52832_QFAB" - select SOC_NRF52832 - -config SOC_NRF52833_QDAA - bool "NRF52833_QDAA" - select SOC_NRF52833 - -config SOC_NRF52833_QIAA - bool "NRF52833_QIAA" - select SOC_NRF52833 - -config SOC_NRF52840_QFAA - bool "NRF52840_QFAA" - select SOC_NRF52840 - -config SOC_NRF52840_QIAA - bool "NRF52840_QIAA" - select SOC_NRF52840 - -endchoice - -config SOC_DCDC_NRF52X - bool - help - Enable nRF52 series System on Chip DC/DC converter. - -config SOC_DCDC_NRF52X_HV - bool - depends on SOC_NRF52840_QIAA - help - Enable nRF52 series System on Chip High Voltage DC/DC converter. - -config GPIO_AS_PINRESET - bool "[DEPRECATED] GPIO as pin reset (reset button)" - select DEPRECATED - help - This option is deprecated, use devicetree instead. Example - configuration: - - &uicr { - gpio-as-nreset; - }; - -config NRF_ENABLE_ICACHE - bool "The instruction cache (I-Cache)" - depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840 - default y - -config NRF52_ANOMALY_132_DELAY_US - int "Anomaly 132 workaround delay (microseconds)" - default 330 - range 0 330 - depends on NRF52_ANOMALY_132_WORKAROUND - help - Due to Anomaly 132 LF RC source may not start if restarted in certain - window after stopping (230 us to 330 us). Software reset also stops the - clock so if clock is initiated in certain window, the clock may also fail - to start at reboot. A delay is added before starting LF clock to ensure - that anomaly conditions are not met. Delay should be long enough to ensure - that clock is started later than 330 us after reset. If crystal oscillator - (XO) is used then low frequency clock initially starts with RC and then - seamlessly switches to XO which has much longer startup time thus, - depending on application, workaround may also need to be applied. - Additional drivers initialization increases initialization time and delay - may be shortened. Workaround is disabled by setting delay to 0. - -config NRF52_ANOMALY_198_WORKAROUND - bool "Anomaly 198 workaround" - default y - depends on SOC_NRF52840 - depends on NRFX_SPIM3 - help - This anomaly applies to IC revisions "Engineering B" up to "3", the most - recent one. - -config NRF52_ANOMALY_109_WORKAROUND - bool "Anomaly 109 workaround" - default y - depends on SOC_NRF52832 - depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM - help - Due to Anomaly 109 the first byte sent out by these peripherals is - sometimes wrong. This occurs when the system enters IDLE and stops the - 64MHz clock at the same time as the peripheral that is using DMA is started. - This anomaly applies to IC revisions up to "3", the most recent one. - -config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE - int "Anomaly 109 workaround EGU instance" - depends on NRF52_ANOMALY_109_WORKAROUND - range 0 5 - default 5 - help - EGU instance used by the nRF52 Anomaly 109 workaround for PWM. - -endif # SOC_SERIES_NRF52X diff --git a/soc/arm/nordic_nrf/nrf53/CMakeLists.txt b/soc/arm/nordic_nrf/nrf53/CMakeLists.txt deleted file mode 100644 index be275df68f5566..00000000000000 --- a/soc/arm/nordic_nrf/nrf53/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) - -zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC sync_rtc.c) - -if (CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED AND - NOT CONFIG_SYS_CLOCK_EXISTS) - message(WARNING " - Your application may be affected by the anomaly 160 that concerns the - nRF5340 SoC. The related workaround cannot be applied, because your - application has the system clock disabled (CONFIG_SYS_CLOCK_EXISTS=n). - Consider enabling the system clock to apply the workaround. - " " - At your own risk, you can suppress this warning by setting - CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED=n.") -endif() diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series deleted file mode 100644 index 7e5660cf514b3c..00000000000000 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF53 MCU line - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF53X - -source "soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf53*" - -config SOC_SERIES - default "nrf53" - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF53X diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.series b/soc/arm/nordic_nrf/nrf53/Kconfig.series deleted file mode 100644 index 28d1c10fc1e2f7..00000000000000 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Nordic Semiconductor nRF53 MCU line - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF53X - bool "Nordic Semiconductor nRF53 series MCU" - select ARM - select SOC_COMPATIBLE_NRF53X - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_SWO - help - Enable support for NRF53 MCU series diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.soc b/soc/arm/nordic_nrf/nrf53/Kconfig.soc deleted file mode 100644 index 3ecf09ecd92ed1..00000000000000 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.soc +++ /dev/null @@ -1,225 +0,0 @@ -# Nordic Semiconductor nRF53 MCU line - -# Copyright (c) 2019 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF53X -config SOC_NRF5340_CPUAPP - bool - select CPU_HAS_NRF_IDAU - select CPU_HAS_FPU - select ARMV8_M_DSP - select HAS_POWEROFF - select SOC_COMPATIBLE_NRF5340_CPUAPP - imply SOC_NRF53_RTC_PRETICK - imply SOC_NRF53_ANOMALY_168_WORKAROUND - -config SOC_NRF5340_CPUNET - bool - select SOC_COMPATIBLE_NRF5340_CPUNET - imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX - imply SOC_NRF53_ANOMALY_168_WORKAROUND - -choice - prompt "nRF53x MCU Selection" - -config SOC_NRF5340_CPUAPP_QKAA - bool "NRF5340_CPUAPP_QKAA" - select SOC_NRF5340_CPUAPP - -config SOC_NRF5340_CPUNET_QKAA - bool "NRF5340_CPUNET_QKAA" - select SOC_NRF5340_CPUNET - -endchoice - -config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - bool "Workaround for nRF5340 anomaly 160" - imply SOC_NRF53_ANOMALY_160_WORKAROUND - help - Indicates that the workaround for the anomaly 160 that affects - the nRF5340 SoC should be applied. - This option is enabled by default for the Application MCU when - DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator - and always for the Network MCU. - If this option is enabled, but the workaround cannot be applied, - because the system clock is disabled, a related cmake warning is - issued. - -config SOC_NRF53_ANOMALY_160_WORKAROUND - bool - depends on SYS_CLOCK_EXISTS - select ARM_ON_ENTER_CPU_IDLE_HOOK - -config SOC_NRF53_RTC_PRETICK - bool "Pre-tick workaround for nRF5340 anomaly 165" - depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP - select NRFX_DPPI - select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET - select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET - help - Indicates that the pre-tick workaround for the anomaly 165 that affects - the nRF5340 SoC should be applied. The workaround applies to wake ups caused - by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are - enabled through INTENSET register. The case when these events are generated - by EVTEN but without interrupts enabled through INTENSET is not handled. - The EVENTS_TICK event is not handled. - -if SOC_NRF53_RTC_PRETICK - -config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET - int "IPC 0 channel for RTC pretick" - range 0 15 - default 10 - -config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET - int "IPC 1 channel for RTC pretick" - range 0 15 - default 11 - -endif - -config SOC_NRF53_ANOMALY_168_WORKAROUND - bool "Workaround for nRF5340 anomaly 168" - select ARM_ON_EXIT_CPU_IDLE - help - Indicates that the workaround for the anomaly 168 that affects - the nRF5340 SoC should be applied. - The workaround involves execution of 8 NOP instructions when the CPU - exist its idle state (when the WFI/WFE instruction returns) and it is - enabled by default for both the application and network core. - -config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM - bool "Extend the workaround to execution at 128 MHz from RAM" - depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP - help - Indicates that the anomaly 168 workaround is to be extended to cover - also a specific case when the WFI/WFE instruction is executed at 128 - MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be - executed after WFI/WFE. This extension is not enabled by default. - -if SOC_NRF5340_CPUAPP - -config SOC_DCDC_NRF53X_APP - bool - imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - help - Enable nRF53 series System on Chip Application MCU DC/DC converter. - -config SOC_DCDC_NRF53X_NET - bool - imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED - help - Enable nRF53 series System on Chip Network MCU DC/DC converter. - -config SOC_DCDC_NRF53X_HV - bool - help - Enable nRF53 series System on Chip High Voltage DC/DC converter. - -config NRF_SPU_FLASH_REGION_SIZE - hex - default 0x4000 - help - FLASH region size for the NRF_SPU peripheral - -config NRF_SPU_RAM_REGION_SIZE - hex - default 0x2000 - help - RAM region size for the NRF_SPU peripheral - -config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 - bool - depends on NRF_SOC_SECURE_SUPPORTED - help - hidden option for including the nRF GPIO pin forwarding - -if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM - -config SOC_ENABLE_LFXO - bool "LFXO" - default y - help - Enable the low-frequency oscillator (LFXO) functionality on XL1 and - XL2 pins. - This option must be enabled if either application or network core is - to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular - GPIOs. - -choice SOC_LFXO_LOAD_CAPACITANCE - prompt "LFXO load capacitance" - depends on SOC_ENABLE_LFXO - default SOC_LFXO_CAP_INT_7PF - -config SOC_LFXO_CAP_EXTERNAL - bool "Use external load capacitors" - -config SOC_LFXO_CAP_INT_6PF - bool "6 pF internal load capacitance" - -config SOC_LFXO_CAP_INT_7PF - bool "7 pF internal load capacitance" - -config SOC_LFXO_CAP_INT_9PF - bool "9 pF internal load capacitance" - -endchoice - -choice SOC_HFXO_LOAD_CAPACITANCE - prompt "HFXO load capacitance" - default SOC_HFXO_CAP_DEFAULT - -config SOC_HFXO_CAP_DEFAULT - bool "SoC default" - help - When this option is used, the SoC initialization routine does not - touch the XOSC32MCAPS register value, so the default setting for - the SoC is in effect. Please note that this may not necessarily be - the reset value (0) for the register, as the register can be set - during the device trimming in the SystemInit() function. - -config SOC_HFXO_CAP_EXTERNAL - bool "Use external load capacitors" - -config SOC_HFXO_CAP_INTERNAL - bool "Use internal load capacitors" - depends on NRF_SOC_SECURE_SUPPORTED - -endchoice - -config SOC_HFXO_CAP_INT_VALUE_X2 - int "Doubled value of HFXO internal load capacitors (in pF)" - depends on SOC_HFXO_CAP_INTERNAL - range 14 40 - help - Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps - can be enabled on pins XC1 and XC2. This option specifies doubled - capacitance value for the two capacitors. Set it to 14 to get 7.0 pF - for each capacitor, 15 to get 7.5 pF, and so on. - -endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM - -endif # SOC_NRF5340_CPUAPP - - -config NRF_ENABLE_CACHE - bool "Cache" - depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \ - || SOC_NRF5340_CPUNET - default y - help - Instruction and Data cache is available on nRF5340 CPUAPP - (Application MCU). It may only be accessed by Secure code. - - Instruction cache only (I-Cache) is available in nRF5340 - CPUNET (Network MCU). - -config BUILD_WITH_TFM - # TF-M nRF53 platform enables the cache unconditionally. - select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP - -rsource "Kconfig.sync_rtc" - -endif # SOC_SERIES_NRF53X diff --git a/soc/arm/nordic_nrf/nrf54h/CMakeLists.txt b/soc/arm/nordic_nrf/nrf54h/CMakeLists.txt deleted file mode 100644 index 8b4df42fa5534b..00000000000000 --- a/soc/arm/nordic_nrf/nrf54h/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) - -# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes -# for the image correctly -zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp deleted file mode 100644 index d90f87c0b896c4..00000000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpuapp +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF54H20 Application MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPUAPP - -config SOC - default "nrf54h20_enga_cpuapp" - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad deleted file mode 100644 index 6aae8c3a1052c6..00000000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_cpurad +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF54H20 Radio MCU - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NRF54H20_ENGA_CPURAD - -config SOC - default "nrf54h20_enga_cpurad" - -config NUM_IRQS - default 471 - -config NRF_REGTOOL_GENERATE_UICR - default y - -endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.series deleted file mode 100644 index ddc902d213eb54..00000000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nordic Semiconductor nRF54H MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54HX - -rsource "Kconfig.defconfig.nrf54h*" - -config SOC_SERIES - default "nrf54h" - -config CACHE_NRF_CACHE - default y if EXTERNAL_CACHE - -endif # SOC_SERIES_NRF54HX diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.series b/soc/arm/nordic_nrf/nrf54h/Kconfig.series deleted file mode 100644 index 0b896f477acca6..00000000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nordic Semiconductor nRF54H MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF54HX - bool "Nordic Semiconductor nRF54H series MCU" - select ARM - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select SOC_FAMILY_NRF - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - help - Enable support for nRF54H MCU series diff --git a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc b/soc/arm/nordic_nrf/nrf54h/Kconfig.soc deleted file mode 100644 index 9c065e79eaf73d..00000000000000 --- a/soc/arm/nordic_nrf/nrf54h/Kconfig.soc +++ /dev/null @@ -1,37 +0,0 @@ -# Nordic Semiconductor nRF54H MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NRF54H20 - bool "nRF54H20" - depends on SOC_SERIES_NRF54HX - -if SOC_NRF54H20 - -choice - prompt "nRF54H20 MCU Selection" - -config SOC_NRF54H20_ENGA_CPUAPP - bool "nRF54H20 ENGA CPUAPP" - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - -config SOC_NRF54H20_ENGA_CPURAD - bool "nRF54H20 ENGA CPURAD" - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_FPU - -endchoice - -config NRF_ENABLE_ICACHE - bool "Instruction cache (I-Cache)" - default y - -endif # SOC_NRF54H20 diff --git a/soc/arm/nordic_nrf/nrf54l/CMakeLists.txt b/soc/arm/nordic_nrf/nrf54l/CMakeLists.txt deleted file mode 100644 index 33036acce8feca..00000000000000 --- a/soc/arm/nordic_nrf/nrf54l/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources( - soc.c - ../validate_rram_partitions.c) - -if (CONFIG_ELV_GRTC_LFXO_ALLOWED) - message(WARNING "WARNING! ELV mode feature is EXPERIMENTAL and may brick your device!") -endif() diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series deleted file mode 100644 index 6c0a5bc606d5cc..00000000000000 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Nordic Semiconductor nRF54L MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54LX - -rsource "Kconfig.defconfig.nrf54l*" - -config SOC_SERIES - default "nrf54l" - -config CORTEX_M_SYSTICK - default !NRF_GRTC_TIMER - -config CACHE_NRF_CACHE - default y if EXTERNAL_CACHE - -endif # SOC_SERIES_NRF54LX diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.series b/soc/arm/nordic_nrf/nrf54l/Kconfig.series deleted file mode 100644 index a9367a0bf363e6..00000000000000 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Nordic Semiconductor nRF54L MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF54LX - bool "Nordic Semiconductor nRF54L series MCU" - select HAS_NRFX - select HAS_NORDIC_DRIVERS - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select SOC_FAMILY_NRF - help - Enable support for nRF54L MCU series diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc b/soc/arm/nordic_nrf/nrf54l/Kconfig.soc deleted file mode 100644 index c42c8cfc9b378e..00000000000000 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.soc +++ /dev/null @@ -1,70 +0,0 @@ -# Nordic Semiconductor nRF54 MCU line - -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54LX - -config SOC_NRF54L15 - bool "NRF54L15" - -config SOC_NRF54L15_ENGA - bool "NRF54L15 ENGA" - select SOC_NRF54L15 - -config SOC_NRF54L15_ENGA_CPUAPP - bool "NRF54L15 ENGA CPUAPP" - select ARM - select ARMV8_M_DSP - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_ARM_SAU - select CPU_HAS_FPU - select HAS_HW_NRF_RADIO_IEEE802154 - select HAS_POWEROFF - select SOC_NRF54L15_ENGA - -config SOC_NRF54LX_SKIP_CLOCK_CONFIG - bool "Skip clock frequency configuration in system initialization" - help - With this option, the CPU clock frequency is not set during system initialization. - The CPU runs with the default, hardware-selected frequency. - -config SOC_NRF_FORCE_CONSTLAT - bool "Force constant-latency mode" - help - In constant latency mode the CPU wakeup latency and the PPI task response - will be constant and kept at a minimum. This is secured by forcing a set - of base resources on while in sleep. The advantage of having a constant - and predictable latency will be at the cost of having increased power consumption. - -config SOC_NRF54L_VREG_MAIN_DCDC - bool "NRF54L DC/DC converter." - help - To enable, an inductor must be connected to the DC/DC converter pin. - -config SOC_NRF54L_NORMAL_VOLTAGE_MODE - bool "NRF54L Normal Voltage Mode." - -config SOC_NRF54L_GLITCHDET_WORKAROUND - bool "Workaround that disables glitch detector" - default y - help - Temporary workaround - disabling glitch detector to limit power consumption. - -if NRF_GRTC_TIMER - -config ELV_GRTC_LFXO_ALLOWED - bool - depends on NRF_GRTC_SLEEP_ALLOWED - select EXPERIMENTAL - help - This feature allows using ELV mode when GRTC operates with the LFXO as - a low-frequency clock source. The LFXO is automatically activated when - preparing to system-off. - WARNING! This feature is EXPERIMENTAL and may brick your device! - -endif # NRF_GRTC_TIMER - -endif # SOC_SERIES_NRF54LX diff --git a/soc/arm/nordic_nrf/nrf91/CMakeLists.txt b/soc/arm/nordic_nrf/nrf91/CMakeLists.txt deleted file mode 100644 index 35d47fb252bc8c..00000000000000 --- a/soc/arm/nordic_nrf/nrf91/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources(soc.c) diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.series b/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.series deleted file mode 100644 index 6d6cccab999964..00000000000000 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nordic Semiconductor nRF91 MCU line - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF91X - -source "soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf91*" - -config SOC_SERIES - default "nrf91" - -# If the kernel has timer support, enable the timer -config NRF_RTC_TIMER - default y if SYS_CLOCK_EXISTS - -endif # SOC_SERIES_NRF91X diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.series b/soc/arm/nordic_nrf/nrf91/Kconfig.series deleted file mode 100644 index 1be69c377e5e0b..00000000000000 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.series +++ /dev/null @@ -1,35 +0,0 @@ -# Nordic Semiconductor nRF91 MCU line - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF91X - bool "Nordic Semiconductor nRF91 series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_NRF_IDAU - select CPU_HAS_FPU - select ARMV8_M_DSP - select SOC_FAMILY_NRF - imply XIP - select HAS_NRFX - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_POWEROFF - help - Enable support for NRF91 MCU series - -if SOC_SERIES_NRF91X -config NRF_SPU_FLASH_REGION_SIZE - hex - default 0x8000 - help - FLASH region size for the NRF_SPU peripheral - -config NRF_SPU_RAM_REGION_SIZE - hex - default 0x2000 - help - RAM region size for the NRF_SPU peripheral -endif diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.soc b/soc/arm/nordic_nrf/nrf91/Kconfig.soc deleted file mode 100644 index 0267ada4850e27..00000000000000 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.soc +++ /dev/null @@ -1,47 +0,0 @@ -# Nordic Semiconductor nRF91 MCU line - -# Copyright (c) 2018 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF91X - -config SOC_NRF9120 - bool - -config SOC_NRF9160 - bool - -choice - prompt "nRF91x MCU Selection" - -config SOC_NRF9160_SICA - bool "NRF9160_SICA" - select SOC_NRF9160 - -# The nRF9161 is technically a SiP (System-in-Package) that consists of -# the nRF9120 SoC and additional components like PMIC, FEM, and XTAL, -# so for nrfx/MDK the nRF9120 SoC is to be indicated as the build target, -# but since the nRF9161 is what a user can actually see on a board, using -# only nRF9120 in the Zephyr build infrastructure might be confusing. -# That's why in the top level of SoC definitions (for user-configurable -# options in Kconfig, for example) the nRF9161 term is used and nRF9120 -# underneath. -config SOC_NRF9161_LACA - bool "NRF9161_LACA" - select SOC_NRF9120 - -config SOC_NRF9131_LACA - bool "NRF9131_LACA" - select SOC_NRF9120 - -config SOC_NRF9151_LACA - bool "NRF9151_LACA" - select SOC_NRF9120 - -endchoice - -config NRF_ENABLE_ICACHE - bool "Instruction cache (I-Cache)" - default y - -endif # SOC_SERIES_NRF91X diff --git a/soc/arm/nuvoton_npcx/Kconfig b/soc/arm/nuvoton_npcx/Kconfig deleted file mode 100644 index 1e27a6c4608d89..00000000000000 --- a/soc/arm/nuvoton_npcx/Kconfig +++ /dev/null @@ -1,195 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NPCX - bool - -if SOC_FAMILY_NPCX -config SOC_FAMILY - string - default "nuvoton_npcx" - -menuconfig NPCX_HEADER - bool "The output binary with NPCX binary header" - help - On NPCX series chip, the NPCX ROM code loads firmware image from flash - to RAM by the firmware binary header setting. Enable this to invoke - the 'ecst' which generates the NPCX firmware header. - -if NPCX_HEADER - -config NPCX_IMAGE_OUTPUT_BIN - bool "Build npcx binary in BIN format" - default y - help - Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory. - The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. - -config NPCX_IMAGE_OUTPUT_HEX - bool "Build npcx binary in HEX format" - depends on NPCX_IMAGE_OUTPUT_BIN - help - Build an HEX binary zephyr/zephyr.npcx.hex in the build directory. - This is generated from the npcx BIN image. - The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. - -config NPCX_HEADER_CHIP - string - default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC - default "npcx7m7" if SOC_NPCX7M7FC - default "npcx9m3" if SOC_NPCX9M3F - default "npcx9m6" if SOC_NPCX9M6F - default "npcx9m7" if SOC_NPCX9M7F - default "npcx9mfp" if SOC_NPCX9MFP - default "npcx4m3" if SOC_NPCX4M3F - default "npcx4m8" if SOC_NPCX4M8F - -choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE - prompt "Clock rate to use for SPI flash" - default NPCX_HEADER_SPI_MAX_CLOCK_20 - help - This selects the max clock rate that will be used for loading firmware - binary from flash to RAM. - -config NPCX_HEADER_SPI_MAX_CLOCK_20 - bool "SPI flash max clock rate of 20 MHz" - -config NPCX_HEADER_SPI_MAX_CLOCK_25 - bool "SPI flash max clock rate of 25 MHz" - -config NPCX_HEADER_SPI_MAX_CLOCK_33 - bool "SPI flash max clock rate of 33 MHz" - depends on !SOC_SERIES_NPCX9 - -config NPCX_HEADER_SPI_MAX_CLOCK_40 - bool "SPI flash max clock rate of 40 MHz" - -config NPCX_HEADER_SPI_MAX_CLOCK_50 - bool "SPI flash max clock rate of 50 MHz" -endchoice - -config NPCX_HEADER_SPI_MAX_CLOCK - int - default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20 - default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25 - default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33 - default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40 - default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50 - -choice NPCX_HEADER_SPI_READ_MODE_CHOICE - prompt "Reading mode used by the SPI flash" - default NPCX_HEADER_SPI_READ_MODE_NORMAL - help - This sets the reading mode that can be used by the SPI flash. - Reading modes supported are normal, fast, dual, and quad. - -config NPCX_HEADER_SPI_READ_MODE_NORMAL - bool "SPI flash operates with normal reading mode" - -config NPCX_HEADER_SPI_READ_MODE_FAST - bool "SPI flash operates with fast reading mode" - -config NPCX_HEADER_SPI_READ_MODE_DUAL - bool "SPI flash operates with dual reading mode" - -config NPCX_HEADER_SPI_READ_MODE_QUAD - bool "SPI flash operates with quad reading mode" -endchoice - -config NPCX_HEADER_SPI_READ_MODE - string - default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL - default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST - default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL - default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD - -choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE - prompt "Core clock to SPI flash clock ratio" - default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 - help - This sets the clock ratio (core clock / SPI clock) - -config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 - bool "NPCX SPI clock ratio 1" - help - The SPI flash clock has the same frequency as the core clock. - -config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 - bool "NPCX SPI clock ratio 2" - help - The core clock frequency is twice the flash clock frequency. -endchoice - -config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO - int - default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 - default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 - -config NPCX_HEADER_ENABLE_HEADER_CRC - bool "Header crc check" - help - When enabled, the header will be verified at boot using a crc - checksum. - -config NPCX_HEADER_ENABLE_FIRMWARE_CRC - bool "Firmware image crc check" - help - When enabled, the firmware image will be verified at boot using a - crc checksum. - -choice NPCX_HEADER_FLASH_SIZE_CHOICE - prompt "Flash size" - default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \ - SOC_SERIES_NPCX9 - default NPCX_HEADER_FLASH_SIZE_16M - help - This sets the SPI flash size. - -config NPCX_HEADER_FLASH_SIZE_0P5M_1M - bool "SPI flash size 0.5M or 1M Bytes" - help - The SPI flash size is 0.5M or 1M Bytes. - -config NPCX_HEADER_FLASH_SIZE_2M - bool "SPI flash size 2M Bytes" - help - The SPI flash size is 2M Bytes. - -config NPCX_HEADER_FLASH_SIZE_4M - bool "SPI flash size 4M Bytes" - help - The SPI flash size is 4M Bytes. - -config NPCX_HEADER_FLASH_SIZE_8M - bool "SPI flash size 8M Bytes" - help - The SPI flash size is 8M Bytes. - -config NPCX_HEADER_FLASH_SIZE_16M - bool "SPI flash size 16M Bytes" - help - The SPI flash size is 16M Bytes. -endchoice - -config NPCX_HEADER_FLASH_SIZE - int - default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M - default 2 if NPCX_HEADER_FLASH_SIZE_2M - default 4 if NPCX_HEADER_FLASH_SIZE_4M - default 8 if NPCX_HEADER_FLASH_SIZE_8M - default 16 if NPCX_HEADER_FLASH_SIZE_16M - -endif # NPCX_HEADER - -# Select SoC Part No. and configuration options -source "soc/arm/nuvoton_npcx/*/Kconfig.soc" - -config NPCX_PM_TRACE - bool "Trace System Power Management in NPCX family" - depends on PM - help - Internal config to enable runtime power management traces. - -endif # SOC_FAMILY_NPCX diff --git a/soc/arm/nuvoton_npcx/Kconfig.defconfig b/soc/arm/nuvoton_npcx/Kconfig.defconfig deleted file mode 100644 index 0dcfc62eb23bd4..00000000000000 --- a/soc/arm/nuvoton_npcx/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_npcx/*/Kconfig.defconfig.series" diff --git a/soc/arm/nuvoton_npcx/Kconfig.soc b/soc/arm/nuvoton_npcx/Kconfig.soc deleted file mode 100644 index 6cf9e5b9828644..00000000000000 --- a/soc/arm/nuvoton_npcx/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_npcx/*/Kconfig.series" diff --git a/soc/arm/nuvoton_npcx/common/CMakeLists.txt b/soc/arm/nuvoton_npcx/common/CMakeLists.txt deleted file mode 100644 index d541efa0e4e1f3..00000000000000 --- a/soc/arm/nuvoton_npcx/common/CMakeLists.txt +++ /dev/null @@ -1,47 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources_ifdef(CONFIG_PM power.c) -zephyr_sources( - scfg.c - registers.c -) - -# Check for disabling header CRC. -if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC) - set(NPCX_HEADER_HCRC "-nohcrc") -endif() - -# Check for disabling firmware CRC. -if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_FIRMWARE_CRC) - set(NPCX_HEADER_FCRC "-nofcrc") -endif() - -if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_BIN) - set(NPCX_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.bin) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${SOC_DIR}/${ARCH}/${SOC_FAMILY}/common/ecst/ecst.py - -i ${KERNEL_BIN_NAME} - -o ${NPCX_BIN_NAME} - ${NPCX_HEADER_HCRC} ${NPCX_HEADER_FCRC} - -chip ${CONFIG_NPCX_HEADER_CHIP} - -flashsize ${CONFIG_NPCX_HEADER_FLASH_SIZE} - -spiclkratio ${CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO} - -spimaxclk ${CONFIG_NPCX_HEADER_SPI_MAX_CLOCK} - -spireadmode ${CONFIG_NPCX_HEADER_SPI_READ_MODE} - ) - if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_HEX) - set(NPCX_HEX_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.hex) - # Property magic which makes west flash choose right file. - set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CONFIG_KERNEL_BIN_NAME}.npcx.hex") - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND $ - $ - $binary - $ihex - $${NPCX_BIN_NAME} - $${NPCX_HEX_NAME} - $ - ) - endif() -endif() diff --git a/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt deleted file mode 100644 index 158ae5cbbc7c99..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx4/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources( - soc.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f deleted file mode 100644 index d56b4fac92564a..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m3f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX4M3F - -config SOC - default "npcx4m3f" - -endif # SOC_NPCX4M3F diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f deleted file mode 100644 index 00ba5b3b62385c..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4m8f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX4M8F - -config SOC - default "npcx4m8f" - -endif # SOC_NPCX4M8F diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series deleted file mode 100644 index 1b692cf76211a4..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NPCX4 - -config SOC_SERIES - default "npcx4" - -config NUM_IRQS - default 128 - -config CORTEX_M_SYSTICK - default !NPCX_ITIM_TIMER - -config ESPI_TAF_NPCX - default y - depends on ESPI_SAF - -source "soc/arm/nuvoton_npcx/npcx4/Kconfig.defconfig.npcx4*" - -endif # SOC_SERIES_NPCX4 diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.series b/soc/arm/nuvoton_npcx/npcx4/Kconfig.series deleted file mode 100644 index 1585ace4e981bc..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller NPCX4 series - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NPCX4 - bool "Nuvoton NPCX4 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NPCX - select HAS_PM - help - Enable support for Nuvoton NPCX4 series diff --git a/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc b/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc deleted file mode 100644 index 3e5f5e1d195748..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx4/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# Nuvoton NPCX4 EC series - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NPCX4 Selection" - depends on SOC_SERIES_NPCX4 - -config SOC_NPCX4M3F - bool "NPCX4M3F" - -config SOC_NPCX4M8F - bool "NPCX4M8F" - -endchoice diff --git a/soc/arm/nuvoton_npcx/npcx7/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx7/CMakeLists.txt deleted file mode 100644 index 01792bf9fce87d..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx7/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources( - soc.c -) - -zephyr_sources_ifdef( - CONFIG_ARM_MPU - mpu_regions.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fb b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fb deleted file mode 100644 index 84f429d2211eea..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fb +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX7M6FB - -config SOC - default "npcx7m6fb" - -endif # SOC_NPCX7M6FB diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fc b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fc deleted file mode 100644 index 54d4fbc9b9d142..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m6fc +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX7M6FC - -config SOC - default "npcx7m6fc" - -endif # SOC_NPCX7M6FC diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m7fc b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m7fc deleted file mode 100644 index a038a5df9bbfaf..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7m7fc +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX7M7FC - -config SOC - default "npcx7m7fc" - -endif # SOC_NPCX7M7FC diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series deleted file mode 100644 index 9b12678dc8e44d..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NPCX7 - -config SOC_SERIES - default "npcx7" - -config NUM_IRQS - default 64 - -config CORTEX_M_SYSTICK - default !NPCX_ITIM_TIMER - -source "soc/arm/nuvoton_npcx/npcx7/Kconfig.defconfig.npcx7*" - -endif # SOC_SERIES_NPCX7 diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.series b/soc/arm/nuvoton_npcx/npcx7/Kconfig.series deleted file mode 100644 index 8f8898388cf210..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller NPCX7 series - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NPCX7 - bool "Nuvoton NPCX7 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NPCX - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select HAS_PM - help - Enable support for Nuvoton NPCX7 series diff --git a/soc/arm/nuvoton_npcx/npcx7/Kconfig.soc b/soc/arm/nuvoton_npcx/npcx7/Kconfig.soc deleted file mode 100644 index efb7c8ff3215e8..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx7/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Nuvoton NPCX7 EC series - -# Copyright (c) 2020 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NPCX7 Selection" - depends on SOC_SERIES_NPCX7 - -config SOC_NPCX7M6FB - bool "NPCX7M6FB" - -config SOC_NPCX7M6FC - bool "NPCX7M6FC" - -config SOC_NPCX7M7FC - bool "NPCX7M7FC" - -endchoice diff --git a/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt b/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt deleted file mode 100644 index 56f793d0580f1e..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m3f b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m3f deleted file mode 100644 index f9696aa2fc9564..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m3f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9M3F - -config SOC - default "npcx9m3f" - -endif # SOC_NPCX9M3F diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m6f b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m6f deleted file mode 100644 index 9bdb30c57ce662..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m6f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9M6F - -config SOC - default "npcx9m6f" - -endif # SOC_NPCX9M6F diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m7f b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m7f deleted file mode 100644 index 391554865c7997..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9m7f +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2022 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9M7F - -config SOC - default "npcx9m7f" - -endif # SOC_NPCX9M7F diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9mfp b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9mfp deleted file mode 100644 index 170c3deceaa0c6..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9mfp +++ /dev/null @@ -1,11 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2023 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NPCX9MFP - -config SOC - default "npcx9mfp" - -endif # SOC_NPCX9MFP diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.series b/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.series deleted file mode 100644 index 6487b70cf59cf6..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NPCX9 - -config SOC_SERIES - default "npcx9" - -config NUM_IRQS - default 64 - -config CORTEX_M_SYSTICK - default !NPCX_ITIM_TIMER - -source "soc/arm/nuvoton_npcx/npcx9/Kconfig.defconfig.npcx9*" - -endif # SOC_SERIES_NPCX9 diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.series b/soc/arm/nuvoton_npcx/npcx9/Kconfig.series deleted file mode 100644 index 82423b37059844..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Nuvoton Cortex-M4 Embedded Controller NPCX9 series - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NPCX9 - bool "Nuvoton NPCX9 Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NPCX - select HAS_PM - help - Enable support for Nuvoton NPCX9 series diff --git a/soc/arm/nuvoton_npcx/npcx9/Kconfig.soc b/soc/arm/nuvoton_npcx/npcx9/Kconfig.soc deleted file mode 100644 index dbebc40d52d696..00000000000000 --- a/soc/arm/nuvoton_npcx/npcx9/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# Nuvoton NPCX9 EC series - -# Copyright (c) 2021 Nuvoton Technology Corporation. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NPCX9 Selection" - depends on SOC_SERIES_NPCX9 - -config SOC_NPCX9M3F - bool "NPCX9M3F" - -config SOC_NPCX9M6F - bool "NPCX9M6F" - -config SOC_NPCX9M7F - bool "NPCX9M7F" - -config SOC_NPCX9MFP - bool "NPCX9MFP" - -endchoice diff --git a/soc/arm/nuvoton_numaker/Kconfig b/soc/arm/nuvoton_numaker/Kconfig deleted file mode 100644 index e9b668ec911872..00000000000000 --- a/soc/arm/nuvoton_numaker/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - - -config SOC_FAMILY_NUMAKER - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_NUMAKER - -config SOC_FAMILY - string - default "nuvoton_numaker" - -source "soc/arm/nuvoton_numaker/*/Kconfig.soc" - -endif # SOC_FAMILY_NUMAKER diff --git a/soc/arm/nuvoton_numaker/Kconfig.defconfig b/soc/arm/nuvoton_numaker/Kconfig.defconfig deleted file mode 100644 index 72d91af7c01efa..00000000000000 --- a/soc/arm/nuvoton_numaker/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_numaker/*/Kconfig.defconfig.series" - -if SOC_FAMILY_NUMAKER - -config RESET - default y - -endif diff --git a/soc/arm/nuvoton_numaker/Kconfig.soc b/soc/arm/nuvoton_numaker/Kconfig.soc deleted file mode 100644 index 8e3ff44930a3b0..00000000000000 --- a/soc/arm/nuvoton_numaker/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nuvoton_numaker/*/Kconfig.series" diff --git a/soc/arm/nuvoton_numaker/m46x/CMakeLists.txt b/soc/arm/nuvoton_numaker/m46x/CMakeLists.txt deleted file mode 100644 index 2fa91b640cfe02..00000000000000 --- a/soc/arm/nuvoton_numaker/m46x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.series b/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.series deleted file mode 100644 index 8bf1440b0ae6cf..00000000000000 --- a/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_M46X - -source "soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.m46*" - -config SOC_SERIES - default "m46x" - -endif # SOC_SERIES_M46X diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.series b/soc/arm/nuvoton_numaker/m46x/Kconfig.series deleted file mode 100644 index 381312bee1ad98..00000000000000 --- a/soc/arm/nuvoton_numaker/m46x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_M46X - bool "Nuvoton M46X Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CORTEX_M_SYSTICK if SYS_CLOCK_EXISTS - select SOC_FAMILY_NUMAKER - help - Enable support for Nuvoton M46X MCU series diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.soc b/soc/arm/nuvoton_numaker/m46x/Kconfig.soc deleted file mode 100644 index 898d23bcecee06..00000000000000 --- a/soc/arm/nuvoton_numaker/m46x/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Nuvoton Technology Corporation. -# -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Nuvoton M46X MCU Selection" - depends on SOC_SERIES_M46X - -config SOC_M467 - bool "M467" - select HAS_NUMAKER_HAL - -endchoice diff --git a/soc/arm/nuvoton_numicro/Kconfig b/soc/arm/nuvoton_numicro/Kconfig deleted file mode 100644 index a45654ac935155..00000000000000 --- a/soc/arm/nuvoton_numicro/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -config SOC_FAMILY_NUMICRO - select PLATFORM_SPECIFIC_INIT - bool - -if SOC_FAMILY_NUMICRO -config SOC_FAMILY - string - default "nuvoton_numicro" - -source "soc/arm/nuvoton_numicro/*/Kconfig.soc" - -endif # SOC_FAMILY_NUMICRO diff --git a/soc/arm/nuvoton_numicro/Kconfig.defconfig b/soc/arm/nuvoton_numicro/Kconfig.defconfig deleted file mode 100644 index 1786f2b0d5fcb7..00000000000000 --- a/soc/arm/nuvoton_numicro/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -source "soc/arm/nuvoton_numicro/*/Kconfig.defconfig.series" diff --git a/soc/arm/nuvoton_numicro/Kconfig.soc b/soc/arm/nuvoton_numicro/Kconfig.soc deleted file mode 100644 index 4345be93264844..00000000000000 --- a/soc/arm/nuvoton_numicro/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -source "soc/arm/nuvoton_numicro/*/Kconfig.series" diff --git a/soc/arm/nuvoton_numicro/m48x/CMakeLists.txt b/soc/arm/nuvoton_numicro/m48x/CMakeLists.txt deleted file mode 100644 index 322465a92cedb2..00000000000000 --- a/soc/arm/nuvoton_numicro/m48x/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.series b/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.series deleted file mode 100644 index ba54547881400e..00000000000000 --- a/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -if SOC_SERIES_M48X - -source "soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.m48*" - -config SOC_SERIES - default "m48x" - -endif # SOC_SERIES_M48X diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.series b/soc/arm/nuvoton_numicro/m48x/Kconfig.series deleted file mode 100644 index 5e79ddfab9a1ca..00000000000000 --- a/soc/arm/nuvoton_numicro/m48x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -config SOC_SERIES_M48X - bool "Nuvoton M48X Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_NUMICRO - help - Enable support for NUVOTON M48X MCU series diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.soc b/soc/arm/nuvoton_numicro/m48x/Kconfig.soc deleted file mode 100644 index cf8ca3d13c517f..00000000000000 --- a/soc/arm/nuvoton_numicro/m48x/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright (c) 2020 Linumiz -# Author: Saravanan Sekar - -choice - prompt "NUVOTON M48X MCU Selection" - depends on SOC_SERIES_M48X - -config SOC_M487 - bool "M487" - select HAS_NUMICRO_HAL - -endchoice diff --git a/soc/arm/nxp_imx/CMakeLists.txt b/soc/arm/nxp_imx/CMakeLists.txt deleted file mode 100644 index 00c429b533cbd1..00000000000000 --- a/soc/arm/nxp_imx/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/nxp_imx/Kconfig b/soc/arm/nxp_imx/Kconfig deleted file mode 100644 index cd77ab5c717e12..00000000000000 --- a/soc/arm/nxp_imx/Kconfig +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright (c) 2017-2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_IMX - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_IMX - -config SOC_FAMILY - string - default "nxp_imx" - - -# Used for default value in FLASH_MCUX_FLEXSPI_XIP -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi -# Macros to shorten Kconfig definitions -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - - -source "soc/arm/nxp_imx/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_IMX_RT5XX if SOC_SERIES_IMX_RT5XX - default SOC_PART_NUMBER_IMX_RT6XX if SOC_SERIES_IMX_RT6XX - default SOC_PART_NUMBER_IMX_RT if SOC_SERIES_IMX_RT - default SOC_PART_NUMBER_IMX_6X_M4 if SOC_SERIES_IMX_6X_M4 - default SOC_PART_NUMBER_IMX7_M4 if SOC_SERIES_IMX7_M4 - default SOC_PART_NUMBER_IMX8MM_M4 if SOC_SERIES_IMX8MM_M4 - default SOC_PART_NUMBER_IMX8ML_M7 if SOC_SERIES_IMX8ML_M7 - default SOC_PART_NUMBER_IMX8MQ_M4 if SOC_SERIES_IMX8MQ_M4 - -config FLASH_MCUX_FLEXSPI_XIP - bool "MCUX FlexSPI flash access with xip" - default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) - depends on (CODE_FLEXSPI || CODE_FLEXSPI2 || SOC_SERIES_IMX_RT6XX || SOC_SERIES_IMX_RT5XX) - select XIP - help - Allows for the soc to safely initialize the clocks for the - FlexSpi when planning to execute code in FlexSpi Memory. - - -endif # SOC_FAMILY_IMX diff --git a/soc/arm/nxp_imx/Kconfig.defconfig b/soc/arm/nxp_imx/Kconfig.defconfig deleted file mode 100644 index 7e27aff32fc34b..00000000000000 --- a/soc/arm/nxp_imx/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL - -source "soc/arm/nxp_imx/*/Kconfig.defconfig.series" diff --git a/soc/arm/nxp_imx/Kconfig.soc b/soc/arm/nxp_imx/Kconfig.soc deleted file mode 100644 index ccc5b2dc9ec96e..00000000000000 --- a/soc/arm/nxp_imx/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_imx/*/Kconfig.series" diff --git a/soc/arm/nxp_imx/mcimx6x_m4/CMakeLists.txt b/soc/arm/nxp_imx/mcimx6x_m4/CMakeLists.txt deleted file mode 100644 index ee28789fe7daae..00000000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2018, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - soc_clk_freq.c -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 deleted file mode 100644 index d8f09a6d8b17db..00000000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4 +++ /dev/null @@ -1,14 +0,0 @@ -# i.MX 6SoloX - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MCIMX6X_M4 - -config SOC - default "mcimx6x" - -config FPU - default y - -endif # SOC_MCIMX6X_M4 diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series deleted file mode 100644 index aa2a90633f866a..00000000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# i.MX 6SoloX M4 core series - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_6X_M4 - -config SOC_SERIES - default "mcimx6x_m4" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 128 - -config PINCTRL_IMX - default y if HAS_IMX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mcimx6x_m4/Kconfig.defconfig.mcimx6x_m4" - -endif # SOC_SERIES_IMX_6X_M4 diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series deleted file mode 100644 index 7279ac8596ec74..00000000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX 6SoloX M4 core series - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_6X_M4 - bool "i.MX 6SoloX M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select HAS_IMX_HAL - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CLOCK_CONTROL - help - Enable support for M4 core of i.MX 6SoloX MCU series diff --git a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc b/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc deleted file mode 100644 index 028d4f09212fbd..00000000000000 --- a/soc/arm/nxp_imx/mcimx6x_m4/Kconfig.soc +++ /dev/null @@ -1,85 +0,0 @@ -# i.MX 6SoloX M4 core series - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX 6SoloX Selection" - depends on SOC_SERIES_IMX_6X_M4 - -config SOC_MCIMX6X_M4 - bool "SOC_MCIMX6X_M4" - select HAS_IMX_HAL - select HAS_IMX_GPIO - select HAS_IMX_EPIT - select HAS_IMX_I2C - select HAS_IMX_IOMUXC - -endchoice - -if SOC_SERIES_IMX_6X_M4 - -config SOC_PART_NUMBER_MCIMX6X1EVK10AB - bool - -config SOC_PART_NUMBER_MCIMX6X1EVK10AC - bool - -config SOC_PART_NUMBER_MCIMX6X3EVK10AB - bool - -config SOC_PART_NUMBER_MCIMX6X3EVK10AC - bool - -config SOC_PART_NUMBER_MCIMX6X1EVO10AB - bool - -config SOC_PART_NUMBER_MCIMX6X1EVO10AC - bool - -config SOC_PART_NUMBER_MCIMX6X3EVO10AB - bool - -config SOC_PART_NUMBER_MCIMX6X3EVO10AC - bool - -config SOC_PART_NUMBER_MCIMX6X2EVN10AB - bool - -config SOC_PART_NUMBER_MCIMX6X2EVN10AC - bool - -config SOC_PART_NUMBER_MCIMX6X3EVN10AB - bool - -config SOC_PART_NUMBER_MCIMX6X3EVN10AC - bool - -config SOC_PART_NUMBER_MCIMX6X4EVM10AB - bool - -config SOC_PART_NUMBER_MCIMX6X4EVM10AC - bool - -config SOC_PART_NUMBER_IMX_6X_M4 - string - default "MCIMX6X1EVK10AB" if SOC_PART_NUMBER_MCIMX6X1EVK10AB - default "MCIMX6X1EVK10AC" if SOC_PART_NUMBER_MCIMX6X1EVK10AC - default "MCIMX6X3EVK10AB" if SOC_PART_NUMBER_MCIMX6X3EVK10AB - default "MCIMX6X3EVK10AC" if SOC_PART_NUMBER_MCIMX6X3EVK10AC - default "MCIMX6X1EVO10AB" if SOC_PART_NUMBER_MCIMX6X1EVO10AB - default "MCIMX6X1EVO10AC" if SOC_PART_NUMBER_MCIMX6X1EVO10AC - default "MCIMX6X3EVO10AB" if SOC_PART_NUMBER_MCIMX6X3EVO10AB - default "MCIMX6X3EVO10AC" if SOC_PART_NUMBER_MCIMX6X3EVO10AC - default "MCIMX6X2EVN10AB" if SOC_PART_NUMBER_MCIMX6X2EVN10AB - default "MCIMX6X2EVN10AC" if SOC_PART_NUMBER_MCIMX6X2EVN10AC - default "MCIMX6X3EVN10AB" if SOC_PART_NUMBER_MCIMX6X3EVN10AB - default "MCIMX6X3EVN10AC" if SOC_PART_NUMBER_MCIMX6X3EVN10AC - default "MCIMX6X4EVM10AB" if SOC_PART_NUMBER_MCIMX6X4EVM10AB - default "MCIMX6X4EVM10AC" if SOC_PART_NUMBER_MCIMX6X4EVM10AC - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX_6X_M4 diff --git a/soc/arm/nxp_imx/mcimx7_m4/CMakeLists.txt b/soc/arm/nxp_imx/mcimx7_m4/CMakeLists.txt deleted file mode 100644 index e5c7ae22fd6a0c..00000000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - soc_clk_freq.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4 b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4 deleted file mode 100644 index 60def652e346a5..00000000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4 +++ /dev/null @@ -1,17 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MCIMX7_M4 - -config SOC - default "mcimx7d" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 200000000 - -config GPIO - default y - -endif # SOC_MCIMX7_M4 diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.series deleted file mode 100644 index 8e53a01f6d407a..00000000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX7_M4 - -config SOC_SERIES - default "mcimx7_m4" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 127 - -config PINCTRL_IMX - default y if HAS_IMX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4" - -endif # SOC_SERIES_IMX7_M4 diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.series b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.series deleted file mode 100644 index e7ae54bcbdadd3..00000000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX7_M4 - bool "i.MX7 M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for i.MX7 M4 MCU series diff --git a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.soc b/soc/arm/nxp_imx/mcimx7_m4/Kconfig.soc deleted file mode 100644 index 38d593fc85e7eb..00000000000000 --- a/soc/arm/nxp_imx/mcimx7_m4/Kconfig.soc +++ /dev/null @@ -1,40 +0,0 @@ -# iMX7 M4 core series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX7 M4 Selection" - depends on SOC_SERIES_IMX7_M4 - -config SOC_MCIMX7_M4 - bool "SOC_MCIMX7_M4" - select HAS_IMX_HAL - select HAS_IMX_GPIO - select HAS_IMX_I2C - select HAS_IMX_IOMUXC - -endchoice - -if SOC_MCIMX7_M4 - -config SOC_PART_NUMBER_MCIMX7D7DVM10SC - bool - -config SOC_PART_NUMBER_MCIMX7D5EVM10SC - bool - -config SOC_PART_NUMBER_MCIMX7S3DVK08SA - bool - -config SOC_PART_NUMBER_IMX7_M4 - string - default "MCIMX7D7DVM10SC" if SOC_PART_NUMBER_MCIMX7D7DVM10SC - default "MCIMX7D5EVM10SC" if SOC_PART_NUMBER_MCIMX7D5EVM10SC - default "MCIMX7S3DVK08SA" if SOC_PART_NUMBER_MCIMX7S3DVK08SA - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX7_M4 diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/CMakeLists.txt b/soc/arm/nxp_imx/mimx8ml8_m7/CMakeLists.txt deleted file mode 100644 index 3dce744104fcbb..00000000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -# -# Copyright (c) 2021, Laird Connectivity -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources( - soc.c - mpu_regions.c -) - -if(CONFIG_OPENAMP_RSC_TABLE) - zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) - zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7 b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7 deleted file mode 100644 index 8b92477601c721..00000000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7 +++ /dev/null @@ -1,43 +0,0 @@ -# MIMX8ML8 SoC defconfig - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8ML8 - -config SOC - string - default "mimx8ml8" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 800000000 - -config GPIO - default y - -config IPM_IMX - default y - depends on IPM - -if CODE_ITCM - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/itcm@0,0,K) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/itcm@0) - -endif # CODE_ITCM - -if CODE_DDR - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/code@80000000,0,K) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/code@80000000) - -endif # CODE_DDR - -endif # SOC_MIMX8ML8 diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series deleted file mode 100644 index 01d49fdf49b2e2..00000000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# i.MX8ML M7 SoC series defconfig - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX8ML_M7 - -config SOC_SERIES - default "mimx8ml8_m7" - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 159 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.defconfig.mimx8ml8_m7" - -endif # SOC_SERIES_IMX8ML_M7 diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series deleted file mode 100644 index f1eb1fd40fdef4..00000000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# i.MX8ML M7 core series - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX8ML_M7 - bool "i.MX8ML M7 Core Series" - select ARM - select CPU_CORTEX_M7 - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select INIT_VIDEO_PLL - help - Enable support for i.MX8ML M7 MCU series diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc b/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc deleted file mode 100644 index 224a112a67f228..00000000000000 --- a/soc/arm/nxp_imx/mimx8ml8_m7/Kconfig.soc +++ /dev/null @@ -1,50 +0,0 @@ -# i.MX8ML M7 SoC series - -# Copyright (c) 2021, Laird Connectivity -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "i.MX8ML M7 Selection" -depends on SOC_SERIES_IMX8ML_M7 - -config SOC_MIMX8ML8 - bool "SOC_MIMX8ML8" - select HAS_MCUX - select HAS_MCUX_CCM - select HAS_MCUX_RDC - select CPU_HAS_ARM_MPU - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select ARM_MPU - select HAS_MCUX_IGPIO - select HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_IMX8ML_M7 - -config SOC_PART_NUMBER_MIMX8ML8DVNLZ - bool - -config SOC_PART_NUMBER_IMX8ML_M7 - string - default "MIMX8ML8DVNLZ" if SOC_PART_NUMBER_MIMX8ML8DVNLZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -choice CODE_LOCATION - prompt "Code location selection" - -config CODE_ITCM - bool "Link code into internal instruction tightly coupled memory (ITCM)" - -config CODE_DDR - bool "Link code into DDR memory" - -endchoice - -config INIT_VIDEO_PLL - bool "Initialize Video PLL" - -endif # SOC_SERIES_IMX8ML_M7 diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/CMakeLists.txt b/soc/arm/nxp_imx/mimx8mm6_m4/CMakeLists.txt deleted file mode 100644 index ef0ba73b1594b4..00000000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2020, Manivannan Sadhasivam -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -if(CONFIG_OPENAMP_RSC_TABLE) - zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) - zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4 b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4 deleted file mode 100644 index 70e75a6bfce481..00000000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4 +++ /dev/null @@ -1,20 +0,0 @@ -# MIMX8MM6 SoC defconfig - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MM6 - -config SOC - string - default "mimx8mm6" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 400000000 - -config IPM_IMX - default y - depends on IPM - -endif # SOC_MIMX8MM6 diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.series deleted file mode 100644 index e9a6760962b201..00000000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# i.MX8MM M4 SoC series defconfig - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX8MM_M4 - -config SOC_SERIES - default "mimx8mm6_m4" - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 127 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -source "soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.defconfig.mimx8mm6_m4" - -endif # SOC_SERIES_IMX8MM_M4 diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series deleted file mode 100644 index f860a7fbd26290..00000000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# i.MX8MM M4 core series - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX8MM_M4 - bool "i.MX8MM M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for i.MX8MM M4 MCU series diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.soc b/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.soc deleted file mode 100644 index 94d41bb544a81c..00000000000000 --- a/soc/arm/nxp_imx/mimx8mm6_m4/Kconfig.soc +++ /dev/null @@ -1,33 +0,0 @@ -# i.MX8MM M4 SoC series - -# Copyright (c) 2020, Manivannan Sadhasivam -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "i.MX8MM M4 Selection" -depends on SOC_SERIES_IMX8MM_M4 - -config SOC_MIMX8MM6 - bool "SOC_MIMX8MM6" - select HAS_MCUX - select HAS_MCUX_CCM - select HAS_MCUX_RDC - select HAS_MCUX_IGPIO - select HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_IMX8MM_M4 - -config SOC_PART_NUMBER_MIMX8MM6DVTLZ - bool - -config SOC_PART_NUMBER_IMX8MM_M4 - string - default "MIMX8MM6DVTLZ" if SOC_PART_NUMBER_MIMX8MM6DVTLZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX8MM_M4 diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt b/soc/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt deleted file mode 100644 index 9555fd57a89a7f..00000000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# -# Copyright (c) 2021, Kwon Tae-young -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 deleted file mode 100644 index be244e4b61ccd3..00000000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4 +++ /dev/null @@ -1,20 +0,0 @@ -# MIMX8MQ6 SoC defconfig - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MQ6 - -config SOC - string - default "mimx8mq6" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 266000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif # SOC_MIMX8MQ6 diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.series b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.series deleted file mode 100644 index e5e8ed6d6de2bd..00000000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# i.MX8MQ M4 SoC series defconfig - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX8MQ_M4 - -config SOC_SERIES - default "mimx8mq6_m4" - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 127 - -source "soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.defconfig.mimx8mq6_m4" - -endif # SOC_SERIES_IMX8MQ_M4 diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series deleted file mode 100644 index 3933037c3a034c..00000000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# i.MX8MQ M4 core series - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX8MQ_M4 - bool "i.MX8MQ M4 Core Series" - select ARM - select CPU_CORTEX_M4 - select SOC_FAMILY_IMX - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for i.MX8MQ M4 MCU series diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc b/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc deleted file mode 100644 index 0165a4d2a19762..00000000000000 --- a/soc/arm/nxp_imx/mimx8mq6_m4/Kconfig.soc +++ /dev/null @@ -1,32 +0,0 @@ -# i.MX8MQ M4 SoC series - -# Copyright (c) 2021, Kwon Tae-young -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "i.MX8MQ M4 Selection" - depends on SOC_SERIES_IMX8MQ_M4 - -config SOC_MIMX8MQ6 - bool "SOC_MIMX8MQ6" - select HAS_MCUX - select HAS_MCUX_CCM - select HAS_MCUX_RDC - select HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_IMX8MQ_M4 - -config SOC_PART_NUMBER_MIMX8MQ6DVAJZ - bool - -config SOC_PART_NUMBER_IMX8MQ_M4 - string - default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_IMX8MQ_M4 diff --git a/soc/arm/nxp_imx/rt/CMakeLists.txt b/soc/arm/nxp_imx/rt/CMakeLists.txt deleted file mode 100644 index a8f1d00765a4d3..00000000000000 --- a/soc/arm/nxp_imx/rt/CMakeLists.txt +++ /dev/null @@ -1,76 +0,0 @@ -# -# Copyright (c) 2017-2021, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX soc_rt11xx.c) -zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT10XX soc_rt10xx.c) - -zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER - ROM_START SORT_KEY 0 boot_header.ld) - -# Add custom mpu regions -zephyr_sources(mpu_regions.c) - -zephyr_linker_section_configure( - SECTION .rom_start - INPUT ".boot_hdr.conf" - OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET} - KEEP - PRIO 10 -) - -if(CONFIG_DEVICE_CONFIGURATION_DATA) - set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data") -endif() - -if(CONFIG_PM) - zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT11XX power_rt11xx.c) -endif() - -if (CONFIG_SOC_SERIES_IMX_RT10XX AND CONFIG_MEMC_MCUX_FLEXSPI) - zephyr_sources(flexspi_rt10xx.c) - if (CONFIG_FLASH_MCUX_FLEXSPI_XIP) - zephyr_code_relocate(FILES flexspi_rt10xx.c LOCATION ITCM_TEXT) - endif() -endif () - - -if (CONFIG_SOC_SERIES_IMX_RT11XX AND CONFIG_MEMC_MCUX_FLEXSPI) - zephyr_sources(flexspi_rt11xx.c) - if (CONFIG_FLASH_MCUX_FLEXSPI_XIP) - zephyr_code_relocate(FILES flexspi_rt11xx.c LOCATION ITCM_TEXT) - endif() -endif () - -if (CONFIG_PM AND CONFIG_SOC_SERIES_IMX_RT10XX) - zephyr_sources(power_rt10xx.c) - zephyr_code_relocate(FILES power_rt10xx.c LOCATION ITCM_TEXT) - if (CONFIG_SOC_MIMXRT1064) - zephyr_sources(lpm_rt1064.c) - zephyr_code_relocate(FILES lpm_rt1064.c LOCATION ITCM_TEXT) - endif() -endif() - -zephyr_compile_definitions( - XIP_EXTERNAL_FLASH -) - -zephyr_compile_definitions_ifdef(CONFIG_ENTROPY_MCUX_CAAM CACHE_MODE_WRITE_THROUGH) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER DATA_SECTION_IS_CACHEABLE=1) - -# flexram header -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc) - -zephyr_linker_section_configure( - SECTION .rom_start - INPUT ".boot_hdr.ivt" - ".boot_hdr.data" - ${boot_hdr_dcd_data_section} - OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET} - KEEP - PRIO 11 -) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010 deleted file mode 100644 index 3ff5ee2ae89b8f..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1010 +++ /dev/null @@ -1,24 +0,0 @@ -# i.MX RT1010 - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1011 - -config SOC - string - default "mimxrt1011" - -config NUM_IRQS - default 80 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -config FLEXSPI_CONFIG_BLOCK_OFFSET - default 0x400 - -endif # SOC_MIMXRT1010 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 deleted file mode 100644 index dac14a43468159..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1015 - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1015 - -config SOC - default "mimxrt1015" - -config NUM_IRQS - default 142 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -endif # SOC_MIMXRT1015 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021 deleted file mode 100644 index b941b4a37a6233..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1021 - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1021 - -config SOC - default "mimxrt1021" - -config NUM_IRQS - default 142 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -endif # SOC_MIMXRT1021 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024 deleted file mode 100644 index aa08f04f2d01f6..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1024 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1024 - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1024 - -config SOC - default "mimxrt1024" - -config NUM_IRQS - default 142 - -config DCDC_VALUE - default 0x12 - -config GPIO - default y - -endif # SOC_MIMXRT1024 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1042 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1042 deleted file mode 100644 index 878e70e27d2ab6..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1042 +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1042 - -config SOC - default "mimxrt1042" - -config NUM_IRQS - default 157 - -config GPIO - default y - -# Set DCDC to 1.275V for 600 MHz AHB operation -config DCDC_VALUE - default 0x13 - -endif # SOC_MIMXRT1042 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052 deleted file mode 100644 index dc4c0189cad71b..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1052 +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT1052 - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1052 - -config SOC - default "mimxrt1052" - -config NUM_IRQS - default 160 - -config GPIO - default y - -endif # SOC_MIMXRT1052 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062 deleted file mode 100644 index 5866a4a7c33767..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1062 +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT1062 - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1062 - -config SOC - default "mimxrt1062" - -config NUM_IRQS - default 160 - -config GPIO - default y - -endif # SOC_MIMXRT1062 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064 deleted file mode 100644 index a31c7dbd39b754..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1064 +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT1064 - -# Copyright (c) 2018, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1064 - -config SOC - default "mimxrt1064" - -config NUM_IRQS - default 160 - -config GPIO - default y - -endif # SOC_MIMXRT1064 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 deleted file mode 100644 index c3043d935231b1..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1160 CM4 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1166_CM4 - -config SOC - default "mimxrt1166_cm4" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 240000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1166_CM4 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 deleted file mode 100644 index e26825f98a8ffc..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1160 CM7 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1166_CM7 - -config SOC - default "mimxrt1166_cm7" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 600000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1166_CM7 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4 deleted file mode 100644 index 9df2704af34d71..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm4 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1170 CM4 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1176_CM4 - -config SOC - default "mimxrt1176_cm4" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 400000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1170_CM4 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7 deleted file mode 100644 index f829da5de87bcf..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1176_cm7 +++ /dev/null @@ -1,20 +0,0 @@ -# i.MX RT1170 CM7 - -# Copyright (c) 2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT1176_CM7 - -config SOC - default "mimxrt1176_cm7" - -config NUM_IRQS - default 218 - -config GPIO - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 996000000 if CORTEX_M_SYSTICK - -endif # SOC_MIMXRT1176_CM7 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt/Kconfig.defconfig.series deleted file mode 100644 index 61f537a402d2ee..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.defconfig.series +++ /dev/null @@ -1,146 +0,0 @@ -# i.MX RT series - -# Copyright (c) 2017-2021, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_RT - -config SOC_SERIES - default "rt" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -config ADC_MCUX_12B1MSPS_SAR - default y if HAS_MCUX_12B1MSPS_SAR - depends on ADC - -config LOG_BACKEND_SWO_FREQ_HZ - default 7500000 - depends on LOG_BACKEND_SWO - -if FLASH_MCUX_FLEXSPI_XIP - -# Avoid RWW hazards by defaulting logging to disabled -choice FLASH_LOG_LEVEL_CHOICE - default FLASH_LOG_LEVEL_OFF -endchoice - -choice MEMC_LOG_LEVEL_CHOICE - default MEMC_LOG_LEVEL_OFF -endchoice - -endif - -# set the tick per sec as a divider of the GPT clock source -config SYS_CLOCK_TICKS_PER_SEC - default 4096 if MCUX_GPT_TIMER - -DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk) - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMX_RT10XX && CORTEX_M_SYSTICK - default 32768 if MCUX_GPT_TIMER - -# Disable systick if using MCUX_GPT_TIMER, as they will conflict -config CORTEX_M_SYSTICK - default n if MCUX_GPT_TIMER - -config PM_MCUX_GPC - default y if HAS_MCUX_GPC - depends on SOC_SERIES_IMX_RT11XX && PM - -# Don't allow SOC to sleep after tests complete when PM is enabled -config ZTEST_NO_YIELD - default y if (ZTEST && PM) - -if SOC_SERIES_IMX_RT10XX && PM - -config CODE_DATA_RELOCATION - default y - -config PM_MCUX_GPC - default y if HAS_MCUX_GPC - -config PM_MCUX_DCDC - default y if HAS_MCUX_DCDC - -config PM_MCUX_PMU - default y if HAS_MCUX_PMU - -endif # SOC_SERIES_IMX_RT10XX && PM - -if ETH_NXP_ENET - -config SYSTEM_WORKQUEUE_STACK_SIZE - default 1560 - -endif # ETH_NXP_ENET - -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi - -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - -DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) -DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ - if $(DT_FLASH_PARENT_IS_FLEXSPI) - -config FLASH_SIZE - default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ - if $(DT_FLASH_HAS_SIZE_PROP) - -config MEMC - default y - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_EHCI -endchoice - -DT_CHOSEN_Z_DTCM := zephyr,dtcm - -choice SEGGER_RTT_SECTION - default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) - depends on USE_SEGGER_RTT -endchoice - -choice SEGGER_SYSVIEW_SECTION - default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) - depends on SEGGER_SYSTEMVIEW -endchoice - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -config MBEDTLS -#config TINYCRYPT - default y if CSPRNG_ENABLED - depends on ENTROPY_GENERATOR - -if MBEDTLS -# -# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than -# what the ztest_thread_stack defaults to. -# -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # MBEDTLS - -# Enable cache management features when using M7 core, since these parts -# have L1 instruction and data caches that should be enabled at boot -config CACHE_MANAGEMENT - default y if CPU_CORTEX_M7 - -source "soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt*" - -endif # SOC_SERIES_IMX_RT diff --git a/soc/arm/nxp_imx/rt/Kconfig.series b/soc/arm/nxp_imx/rt/Kconfig.series deleted file mode 100644 index 65edffe3cd55dd..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# iMX RT series - -# Copyright (c) 2017-2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_RT - bool "i.MX RT Series" - select ARM - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select HAS_PM - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - help - Enable support for i.MX RT MCU series diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc deleted file mode 100644 index cbc00915046a32..00000000000000 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ /dev/null @@ -1,837 +0,0 @@ -# i.MX RT series - -# Copyright 2017-2021,2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX RT Selection" - depends on SOC_SERIES_IMX_RT - -config SOC_MIMXRT1011 - bool "SOC_MIMXRT1011" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_TRNG - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_EDMA - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1015 - bool "SOC_MIMXRT1015" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_TRNG - select CPU_HAS_FPU - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_EDMA - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1021 - bool "SOC_MIMXRT1021" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_PWM - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1024 - bool "SOC_MIMXRT1024" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ENET_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_SRC - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1042 - bool "SOC_MIMXRT1042" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_FLEXSPI - select HAS_MCUX_SEMC - select HAS_MCUX_IGPIO - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select HAS_MCUX_EDMA - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1051 - bool "SOC_MIMXRT1051" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1052 - bool "SOC_MIMXRT1052" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ELCDIF - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_PWM - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_MCUX_SRC - select HAS_SWO - select HAS_MCUX_XBARA - -config SOC_MIMXRT1061 - bool "SOC_MIMXRT1061" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_SEMC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1062 - bool "SOC_MIMXRT1062" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ELCDIF - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_PWM - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_QTMR - select HAS_MCUX_SEMC - select HAS_MCUX_SNVS - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_I2S - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_MCUX_ADC_ETC - select HAS_MCUX_SRC - select HAS_SWO - select HAS_MCUX_XBARA - -config SOC_MIMXRT1064 - bool "SOC_MIMXRT1064" - select SOC_SERIES_IMX_RT10XX - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_12B1MSPS_SAR - select HAS_MCUX_CCM - select HAS_MCUX_ELCDIF - select HAS_MCUX_ENET - select HAS_MCUX_FLEXSPI - select HAS_MCUX_PWM - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select HAS_MCUX_QTMR - select HAS_MCUX_SEMC - select HAS_MCUX_SNVS - select HAS_MCUX_SRC - select HAS_MCUX_TRNG - select CPU_HAS_FPU_DOUBLE_PRECISION - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select HAS_MCUX_USB_EHCI - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_CSI - select HAS_MCUX_EDMA - select HAS_MCUX_FLEXCAN - select HAS_MCUX_GPC - select HAS_MCUX_DCDC - select HAS_MCUX_PMU - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1176_CM7 - bool "SOC_MIMXRT1176_CM7" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPADC - select HAS_MCUX_LPUART - select HAS_MCUX_ELCDIF - select HAS_MCUX_MIPI_DSI - select HAS_MCUX_GPT - select HAS_MCUX_FLEXSPI - select HAS_MCUX_FLEXCAN - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - select BYPASS_LDO_LPSR - select ADJUST_LDO - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_I2S - select HAS_MCUX_USB_EHCI - select HAS_MCUX_ACMP - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_MCUX_XBARA - select HAS_SWO - -config SOC_MIMXRT1176_CM4 - bool "SOC_MIMXRT1176_CM4" - select CPU_CORTEX_M4 - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_FLEXSPI - select HAS_MCUX_LPUART - select HAS_MCUX_GPT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_I2S - select HAS_MCUX_ACMP - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_SWO - -config SOC_MIMXRT1166_CM7 - bool "SOC_MIMXRT1166_CM7" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPADC - select HAS_MCUX_LPUART - select HAS_MCUX_FLEXSPI - select HAS_MCUX_GPT - select HAS_MCUX_FLEXCAN - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select CPU_HAS_FPU_DOUBLE_PRECISION - select BYPASS_LDO_LPSR - select ADJUST_LDO - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_USB_EHCI - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_SWO - - -config SOC_MIMXRT1166_CM4 - bool "SOC_MIMXRT1166_CM4" - select CPU_CORTEX_M4 - select SOC_SERIES_IMX_RT11XX - select HAS_MCUX_CACHE - select HAS_MCUX - select HAS_MCUX_SEMC - select HAS_MCUX_CCM_REV2 - select HAS_MCUX_IGPIO - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_FLEXSPI - select HAS_MCUX_GPT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select INIT_ARM_PLL - select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER - select INIT_VIDEO_PLL - select HAS_MCUX_EDMA - select HAS_MCUX_PWM - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_ENET - select HAS_MCUX_GPC - select HAS_MCUX_SRC_V2 - select HAS_MCUX_IOMUXC - select HAS_SWO - -endchoice - -if SOC_SERIES_IMX_RT - -config SOC_PART_NUMBER_MIMXRT1011CAE4A - bool - -config SOC_PART_NUMBER_MIMXRT1011DAE5A - bool - -config SOC_PART_NUMBER_MIMXRT1015CAF4A - bool - -config SOC_PART_NUMBER_MIMXRT1015DAF5A - bool - -config SOC_PART_NUMBER_MIMXRT1021CAF4A - bool - -config SOC_PART_NUMBER_MIMXRT1021CAG4A - bool - -config SOC_PART_NUMBER_MIMXRT1021DAF5A - bool - -config SOC_PART_NUMBER_MIMXRT1021DAG5A - bool - -config SOC_PART_NUMBER_MIMXRT1024CAG4A - bool - -config SOC_PART_NUMBER_MIMXRT1024DAG5A - bool - -config SOC_PART_NUMBER_MIMXRT1041DFP6B - bool - -config SOC_PART_NUMBER_MIMXRT1041DJM6B - bool - -config SOC_PART_NUMBER_MIMXRT1041XFP5B - bool - -config SOC_PART_NUMBER_MIMXRT1041XJM5B - bool - -config SOC_PART_NUMBER_MIMXRT1042DFP6B - bool - -config SOC_PART_NUMBER_MIMXRT1042DJM6B - bool - -config SOC_PART_NUMBER_MIMXRT1042XFP5B - bool - -config SOC_PART_NUMBER_MIMXRT1042XJM5B - bool - -config SOC_PART_NUMBER_MIMXRT1051CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1051DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1052CVJ5B - bool - -config SOC_PART_NUMBER_MIMXRT1052CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1052CVL5B - bool - -config SOC_PART_NUMBER_MIMXRT1052DVJ6B - bool - -config SOC_PART_NUMBER_MIMXRT1052DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1052DVL6B - bool - -config SOC_PART_NUMBER_MIMXRT1061CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1061DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1062CVJ5A - bool - -config SOC_PART_NUMBER_MIMXRT1062CVJ5B - bool - -config SOC_PART_NUMBER_MIMXRT1062CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1062DVJ6A - bool - -config SOC_PART_NUMBER_MIMXRT1062DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1064CVL5A - bool - -config SOC_PART_NUMBER_MIMXRT1064DVL6A - bool - -config SOC_PART_NUMBER_MIMXRT1166DVM6A - bool - -config SOC_PART_NUMBER_MIMXRT1176AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1176CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1176DVMAA - bool - -config SOC_PART_NUMBER_MIMXRT1175AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1175CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1175DVMAA - bool - -config SOC_PART_NUMBER_MIMXRT1173CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1172AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1172CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1172DVMAA - bool - -config SOC_PART_NUMBER_MIMXRT1171AVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1171CVM8A - bool - -config SOC_PART_NUMBER_MIMXRT1171DVMAA - bool - -config SOC_PART_NUMBER_IMX_RT - string - default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A - default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A - default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A - default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A - default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A - default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A - default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A - default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A - default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A - default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A - default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B - default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B - default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B - default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B - default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B - default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B - default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B - default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B - default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A - default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A - default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B - default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A - default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B - default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B - default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A - default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B - default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A - default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A - default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A - default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B - default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A - default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A - default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A - default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A - default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A - default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A - default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A - default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA - default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A - default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A - default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A - default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA - default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A - default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A - default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A - default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA - default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A - default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A - default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_SERIES_IMX_RT10XX - bool "i.MX RT 10XX Series" - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select PLATFORM_SPECIFIC_INIT - -config SOC_SERIES_IMX_RT11XX - bool "i.MX RT 11XX Series" - select PLATFORM_SPECIFIC_INIT - -config INIT_ARM_PLL - bool "Initialize ARM PLL" - -config INIT_VIDEO_PLL - bool "Initialize Video PLL" - -config INIT_ENET_PLL - bool - help - If y, the Ethernet PLL is initialized. Always enabled on e.g. - MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection - for MIMXRT1021"). - -config DCDC_VALUE - hex "DCDC value for VDD_SOC" - default 0x13 - -config ADJUST_DCDC - bool "Adjust internal DCDC output" - default y if SOC_SERIES_IMX_RT11XX - -config BYPASS_LDO_LPSR - bool "Bypass LDO lpsr" - -config ADJUST_LDO - bool "Adjust LDO setting" - -config PM_MCUX_GPC - bool "MCUX general power controller driver" - -config PM_MCUX_DCDC - bool "MCUX dcdc converter module driver" - -config PM_MCUX_PMU - bool "MCUX power management unit driver" - -menuconfig NXP_IMX_RT_BOOT_HEADER - bool "Boot header" - depends on (!BOOTLOADER_MCUBOOT) && CPU_CORTEX_M7 - help - Enable data structures required by the boot ROM to boot the - application from an external flash device. - -if NXP_IMX_RT_BOOT_HEADER - -choice BOOT_DEVICE - prompt "Boot device selection" - default BOOT_FLEXSPI_NOR - -config BOOT_FLEXSPI_NOR - bool "FlexSPI serial NOR" - -config BOOT_FLEXSPI_NAND - bool "FlexSPI serial NAND" - -config BOOT_SEMC_NOR - bool "SEMC parallel NOR" - -config BOOT_SEMC_NAND - bool "SEMC parallel NAND" - -endchoice - -config FLEXSPI_CONFIG_BLOCK_OFFSET - hex "FlexSPI config block offset" - default 0x0 if BOOT_FLEXSPI_NOR - help - FlexSPI configuration block consists of parameters regarding specific - flash devices including read command sequence, quad mode enablement - sequence (optional), etc. The boot ROM expects FlexSPI configuration - parameter to be presented in serial nor flash. - -config IMAGE_VECTOR_TABLE_OFFSET - hex "Image vector table offset" - default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR - default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND - help - The Image Vector Table (IVT) provides the boot ROM with pointers to - the application entry point and device configuration data. The boot - ROM requires a fixed IVT offset for each type of boot device. - -config DEVICE_CONFIGURATION_DATA - bool "Device configuration data" - help - Device configuration data (DCD) provides a sequence of commands to - the boot ROM to initialize components such as an SDRAM. This is - useful if your application expects components like SDRAM to be - initialized at boot time. - -endif # NXP_IMX_RT_BOOT_HEADER - -choice CODE_LOCATION - prompt "Code location selection" - default CODE_ITCM - -config CODE_SEMC - bool "Link code into external SEMC-controlled memory" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_ITCM - bool "Link code into internal instruction tightly coupled memory (ITCM)" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_FLEXSPI - bool "Link code into external FlexSPI-controlled memory" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_FLEXSPI2 - bool "Link code into internal FlexSPI-controlled memory" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_SRAM0 - bool "Link code into RAM_L memory (RAM_L)" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -config CODE_OCRAM - bool "Link code into OCRAM memory (OCRAM-M4)" - imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT - -endchoice - -config NXP_IMX_EXTERNAL_SDRAM - bool "Allow access to external SDRAM region" - help - Enable access to external SDRAM region managed by the SEMC. This - setting should be enabled when the application uses SDRAM, or - an MPU region will be defined to disable cached access to the - SDRAM memory space. - -config NXP_IMX_RT_ROM_RAMLOADER - depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMX_RT_BOOT_HEADER - # Required so that debugger will load image to correct offset - select BUILD_OUTPUT_HEX - bool "Create output image that IMX RT ROM can load from FlexSPI to ram" - help - Builds an output image that the IMX RT BootROM can load from the - FlexSPI boot device into RAM region. The image will be loaded - from FLEXSPI into the region specified by `zephyr,flash` node. - -# Setup LMA adjustment if using the RAMLOADER feature of ROM -FLASH_CHOSEN := zephyr,flash -FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) -FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) -config BUILD_OUTPUT_ADJUST_LMA - default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER - -config SECOND_CORE_MCUX - bool "Dual core operation on the RT11xx series" - depends on SOC_SERIES_IMX_RT11XX - help - Indicates the second core will be enabled, and the part will run - in dual core mode. Enables dual core operation on the RT11xx series, - by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. - The M4 image will be loaded from flash into RAM based off a - generated header specifying the VMA and LMA of each memory section - to load - -endif # SOC_SERIES_IMX_RT diff --git a/soc/arm/nxp_imx/rt/boot_header.ld b/soc/arm/nxp_imx/rt/boot_header.ld deleted file mode 100644 index 501fde9fd4a4fc..00000000000000 --- a/soc/arm/nxp_imx/rt/boot_header.ld +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2019 NXP - * Copyright (c) 2019 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: Apache-2.0 - */ - -. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; -KEEP(*(.boot_hdr.conf)) -. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; -KEEP(*(.boot_hdr.ivt)) -KEEP(*(.boot_hdr.data)) -#ifdef CONFIG_DEVICE_CONFIGURATION_DATA - KEEP(*(.boot_hdr.dcd_data)) -#endif diff --git a/soc/arm/nxp_imx/rt/linker.ld b/soc/arm/nxp_imx/rt/linker.ld deleted file mode 100644 index e4d5ad56db00c4..00000000000000 --- a/soc/arm/nxp_imx/rt/linker.ld +++ /dev/null @@ -1,18 +0,0 @@ -/* - * Copyright (c) 2014 Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - - #include - -#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) - -MEMORY - { -#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) - SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) -#endif - } - -#include diff --git a/soc/arm/nxp_imx/rt/pinctrl_soc.h b/soc/arm/nxp_imx/rt/pinctrl_soc.h deleted file mode 100644 index 81ea64f385f38e..00000000000000 --- a/soc/arm/nxp_imx/rt/pinctrl_soc.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2022, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ -#if defined(CONFIG_SOC_SERIES_IMX_RT10XX) -#include "pinctrl_rt10xx.h" -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) -#include "pinctrl_rt11xx.h" -#endif - -#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT_PINCTRL_SOC_H_ */ diff --git a/soc/arm/nxp_imx/rt/power_rt10xx.c b/soc/arm/nxp_imx/rt/power_rt10xx.c deleted file mode 100644 index dea16d99570deb..00000000000000 --- a/soc/arm/nxp_imx/rt/power_rt10xx.c +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2021 NXP - * - * SPDX-License-Identifier: Apache-2.0 - * - * Note: this file is linked to RAM. Any functions called while preparing for - * sleep mode must be defined within this file, or linked to RAM. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "power_rt10xx.h" - -LOG_MODULE_REGISTER(soc_power, CONFIG_SOC_LOG_LEVEL); - - -static struct clock_callbacks lpm_clock_hooks; - -/* - * Boards with RT10XX SOCs can register callbacks to set their clocks into - * normal/full speed mode, low speed mode, and low power mode. - * If callbacks are present, the low power subsystem will disable - * PLLs for power savings when entering low power states. - */ -void imxrt_clock_pm_callbacks_register(struct clock_callbacks *callbacks) -{ - /* If run callback is set, low power must be as well. */ - __ASSERT_NO_MSG(callbacks && callbacks->clock_set_run && callbacks->clock_set_low_power); - lpm_clock_hooks.clock_set_run = callbacks->clock_set_run; - lpm_clock_hooks.clock_set_low_power = callbacks->clock_set_low_power; - if (callbacks->clock_lpm_init) { - lpm_clock_hooks.clock_lpm_init = callbacks->clock_lpm_init; - } -} - -static void lpm_set_sleep_mode_config(clock_mode_t mode) -{ - uint32_t clpcr; - - /* Set GPC wakeup config to GPT timer interrupt */ - GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); - /* - * ERR050143: CCM: When improper low-power sequence is used, - * the SoC enters low power mode before the ARM core executes WFI. - * - * Software workaround: - * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending - * by setting IOMUXC_GPR_GPR1_GINT. - * 2) Software should then unmask IRQ #41 in GPC before setting CCM - * Low-Power mode. - * 3) Software should mask IRQ #41 right after CCM Low-Power mode - * is set (set bits 0-1 of CCM_CLPCR). - */ - GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); - clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); - /* Note: if CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK is set, - * debugger will not connect in sleep mode - */ - /* Set clock control module to transfer system to idle mode */ - clpcr |= CCM_CLPCR_LPM(mode) | CCM_CLPCR_MASK_SCU_IDLE_MASK | - CCM_CLPCR_MASK_L2CC_IDLE_MASK | - CCM_CLPCR_STBY_COUNT_MASK | - CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK; -#ifndef CONFIG_SOC_MIMXRT1011 - /* RT1011 does not include handshake bits */ - clpcr |= CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK; -#endif - CCM->CLPCR = clpcr; - GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); -} - -static void lpm_enter_soft_off_mode(void) -{ - /* Enable the SNVS RTC as a wakeup source from soft-off mode, in case an RTC alarm - * was set. - */ - GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_imx_snvs_rtc))); - SNVS->LPCR |= SNVS_LPCR_TOP_MASK; -} - -static void lpm_enter_sleep_mode(clock_mode_t mode) -{ - /* FIXME: When this function is entered the Kernel has disabled - * interrupts using BASEPRI register. This is incorrect as it prevents - * waking up from any interrupt which priority is not 0. Work around the - * issue and disable interrupts using PRIMASK register as recommended - * by ARM. - */ - - /* Set PRIMASK */ - __disable_irq(); - /* Set BASEPRI to 0 */ - irq_unlock(0); - barrier_dsync_fence_full(); - barrier_isync_fence_full(); - - if (mode == kCLOCK_ModeWait) { - /* Clear the SLEEPDEEP bit to go into sleep mode (WAIT) */ - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; - } else { - /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - } - /* WFI instruction will start entry into WAIT/STOP mode */ - __WFI(); - -} - -static void lpm_set_run_mode_config(void) -{ - /* Clear GPC wakeup source */ - GPC_DisableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); - CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); -} - -/* Toggle the analog bandgap reference circuitry on and off */ -static void bandgap_set(bool on) -{ - if (on) { - /* Enable bandgap in PMU */ - PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK; - /* Wait for it to stabilize */ - while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0) { - - } - /* Disable low power bandgap */ - XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; - } else { - /* Disable bandgap in PMU and switch to low power one */ - XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; - PMU->MISC0_SET = PMU_MISC0_REFTOP_PWD_MASK; - } -} - -/* Should only be used if core clocks have been reduced- drops SOC voltage */ -static void lpm_drop_voltage(void) -{ - /* Move to the internal RC oscillator, since we are using low power clocks */ - CLOCK_InitRcOsc24M(); - /* Switch to internal RC oscillator */ - CLOCK_SwitchOsc(kCLOCK_RcOsc); - CLOCK_DeinitExternalClk(); - /* - * Change to 1.075V SOC voltage. If you are experiencing issues with - * low power mode stability, try raising this voltage value. - */ - DCDC_AdjustRunTargetVoltage(DCDC, 0xB); - /* Enable 2.5 and 1.1V weak regulators */ - PMU_2P5EnableWeakRegulator(PMU, true); - PMU_1P1EnableWeakRegulator(PMU, true); - /* Disable normal regulators */ - PMU_2P5EnableOutput(PMU, false); - PMU_1P1EnableOutput(PMU, false); - /* Disable analog bandgap */ - bandgap_set(false); -} - -/* Undo the changes made by lpm_drop_voltage so clocks can be raised */ -static void lpm_raise_voltage(void) -{ - /* Enable analog bandgap */ - bandgap_set(true); - /* Enable regulator LDOs */ - PMU_2P5EnableOutput(PMU, true); - PMU_1P1EnableOutput(PMU, true); - /* Disable weak LDOs */ - PMU_2P5EnableWeakRegulator(PMU, false); - PMU_1P1EnableWeakRegulator(PMU, false); - /* Change to 1.275V SOC voltage */ - DCDC_AdjustRunTargetVoltage(DCDC, 0x13); - /* Move to the external RC oscillator */ - CLOCK_InitExternalClk(0); - /* Switch clock source to external OSC. */ - CLOCK_SwitchOsc(kCLOCK_XtalOsc); -} - - -/* Sets device into low power mode */ -void pm_state_set(enum pm_state state, uint8_t substate_id) -{ - ARG_UNUSED(substate_id); - - switch (state) { - case PM_STATE_RUNTIME_IDLE: - LOG_DBG("entering PM state runtime idle"); - lpm_set_sleep_mode_config(kCLOCK_ModeWait); - lpm_enter_sleep_mode(kCLOCK_ModeWait); - break; - case PM_STATE_SUSPEND_TO_IDLE: - LOG_DBG("entering PM state suspend to idle"); - if (lpm_clock_hooks.clock_set_low_power) { - /* Drop the SOC clocks to low power mode, and decrease core voltage */ - lpm_clock_hooks.clock_set_low_power(); - lpm_drop_voltage(); - } - lpm_set_sleep_mode_config(kCLOCK_ModeWait); - lpm_enter_sleep_mode(kCLOCK_ModeWait); - break; - case PM_STATE_SOFT_OFF: - LOG_DBG("Entering PM state soft off"); - lpm_enter_soft_off_mode(); - break; - default: - return; - } -} - -/* Handle SOC specific activity after Low Power Mode Exit */ -void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) -{ - ARG_UNUSED(substate_id); - - /* Set run mode config after wakeup */ - switch (state) { - case PM_STATE_RUNTIME_IDLE: - lpm_set_run_mode_config(); - LOG_DBG("exited PM state runtime idle"); - break; - case PM_STATE_SUSPEND_TO_IDLE: - lpm_set_run_mode_config(); - if (lpm_clock_hooks.clock_set_run) { - /* Raise core voltage and restore SOC clocks */ - lpm_raise_voltage(); - lpm_clock_hooks.clock_set_run(); - } - LOG_DBG("exited PM state suspend to idle"); - break; - default: - break; - } - /* Clear PRIMASK after wakeup */ - __enable_irq(); -} - -/* Initialize power system */ -static int rt10xx_power_init(void) -{ - dcdc_internal_regulator_config_t reg_config; - - - /* Ensure clocks to ARM core memory will not be gated in low power mode - * if interrupt is pending - */ - CCM->CGPR |= CCM_CGPR_INT_MEM_CLK_LPM_MASK; - - if (lpm_clock_hooks.clock_lpm_init) { - lpm_clock_hooks.clock_lpm_init(); - } - - /* Errata ERR050143 */ - IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK; - - /* Configure DCDC */ - DCDC_BootIntoDCM(DCDC); - /* Set target voltage for low power mode to 0.925V*/ - DCDC_AdjustLowPowerTargetVoltage(DCDC, 0x1); - /* Reconfigure DCDC to disable internal load resistor */ - reg_config.enableLoadResistor = false; - reg_config.feedbackPoint = 0x1; /* 1.0V with 1.3V reference voltage */ - DCDC_SetInternalRegulatorConfig(DCDC, ®_config); - - /* Enable high gate drive on power FETs to reduce leakage current */ - PMU_CoreEnableIncreaseGateDrive(PMU, true); - - - return 0; -} - -SYS_INIT(rt10xx_power_init, PRE_KERNEL_2, 0); diff --git a/soc/arm/nxp_imx/rt/soc.h b/soc/arm/nxp_imx/rt/soc.h deleted file mode 100644 index e5129c947d0308..00000000000000 --- a/soc/arm/nxp_imx/rt/soc.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2017, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _SOC__H_ -#define _SOC__H_ - -#include - -#ifndef _ASMLANGUAGE - -#include - -/* Add include for DTS generated information */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if CONFIG_I2S_MCUX_SAI -void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, - uint32_t clk_pre_div, uint32_t clk_src_div); - -#endif - -#if CONFIG_MIPI_DSI -void imxrt_pre_init_display_interface(void); - -void imxrt_post_init_display_interface(void); -#endif - -#ifdef CONFIG_MEMC -uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* !_ASMLANGUAGE */ - -#endif /* _SOC__H_ */ diff --git a/soc/arm/nxp_imx/rt/soc_rt10xx.c b/soc/arm/nxp_imx/rt/soc_rt10xx.c deleted file mode 100644 index dd6e534be232cd..00000000000000 --- a/soc/arm/nxp_imx/rt/soc_rt10xx.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * Copyright 2017-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#include -#endif -#include -#include -#if CONFIG_USB_DC_NXP_EHCI -#include "usb_phy.h" -#include "usb.h" -#endif - -#include "memc_nxp_flexram.h" - -#include - -#define CCM_NODE DT_INST(0, nxp_imx_ccm) - -#define BUILD_ASSERT_PODF_IN_RANGE(podf, a, b) \ - BUILD_ASSERT(DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) >= (a) && \ - DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \ - #podf " is out of supported range (" #a ", " #b ")") - -#ifdef CONFIG_INIT_ARM_PLL -/* ARM PLL configuration for RUN mode */ -const clock_arm_pll_config_t armPllConfig = { - .loopDivider = 100U -}; -#endif - -#if CONFIG_USB_DC_NXP_EHCI -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -#ifdef CONFIG_INIT_ENET_PLL -/* ENET PLL configuration for RUN mode */ -const clock_enet_pll_config_t ethPllConfig = { -#if defined(CONFIG_SOC_MIMXRT1011) || \ - defined(CONFIG_SOC_MIMXRT1015) || \ - defined(CONFIG_SOC_MIMXRT1021) || \ - defined(CONFIG_SOC_MIMXRT1024) - .enableClkOutput500M = true, -#endif -#if defined(CONFIG_ETH_NXP_ENET) || defined(CONFIG_ETH_MCUX) -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) - .enableClkOutput = true, -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) - .enableClkOutput1 = true, -#endif -#endif -#if defined(CONFIG_PTP_CLOCK_MCUX) - .enableClkOutput25M = true, -#else - .enableClkOutput25M = false, -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) - .loopDivider = 1, -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) - .loopDivider1 = 1, -#endif -}; -#endif - -#if CONFIG_USB_DC_NXP_EHCI - usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, - }; -#endif - -#ifdef CONFIG_INIT_VIDEO_PLL -const clock_video_pll_config_t videoPllConfig = { - .loopDivider = 31, - .postDivider = 8, - .numerator = 0, - .denominator = 0, -}; -#endif - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -const __imx_boot_data_section BOOT_DATA_T boot_data = { -#ifdef CONFIG_XIP - .start = CONFIG_FLASH_BASE_ADDRESS, - .size = (uint32_t)&_flash_used, -#else - .start = CONFIG_SRAM_BASE_ADDRESS, - .size = (uint32_t)&_image_ram_size, -#endif - .plugin = PLUGIN_FLAG, - .placeholder = 0xFFFFFFFF, -}; - -const __imx_boot_ivt_section ivt image_vector_table = { - .hdr = IVT_HEADER, - .entry = (uint32_t) _vector_start, - .reserved1 = IVT_RSVD, -#ifdef CONFIG_DEVICE_CONFIGURATION_DATA - .dcd = (uint32_t) dcd_data, -#else - .dcd = (uint32_t) NULL, -#endif - .boot_data = (uint32_t) &boot_data, - .self = (uint32_t) &image_vector_table, - .csf = (uint32_t)CSF_ADDRESS, - .reserved2 = IVT_RSVD, -}; -#endif - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ - /* Boot ROM did initialize the XTAL, here we only sets external XTAL - * OSC freq - */ - CLOCK_SetXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, xtal), - clock_frequency)); - CLOCK_SetRtcXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, rtc_xtal), - clock_frequency)); - - /* Set PERIPH_CLK2 MUX to OSC */ - CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); - - /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); - - /* Setting the VDD_SOC value. - */ - DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); - /* Waiting for DCDC_STS_DC_OK bit is asserted */ - while (DCDC_REG0_STS_DC_OK_MASK != - (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { - ; - } - -#ifdef CONFIG_INIT_ARM_PLL - CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ -#endif -#ifdef CONFIG_INIT_ENET_PLL - CLOCK_InitEnetPll(ðPllConfig); -#endif -#ifdef CONFIG_INIT_VIDEO_PLL - CLOCK_InitVideoPll(&videoPllConfig); -#endif - -#if DT_NODE_EXISTS(DT_CHILD(CCM_NODE, arm_podf)) - /* Set ARM PODF */ - BUILD_ASSERT_PODF_IN_RANGE(arm_podf, 1, 8); - CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); -#endif - /* Set AHB PODF */ - BUILD_ASSERT_PODF_IN_RANGE(ahb_podf, 1, 8); - CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1); - /* Set IPG PODF */ - BUILD_ASSERT_PODF_IN_RANGE(ipg_podf, 1, 4); - CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1); - - /* Set PRE_PERIPH_CLK to PLL1, 1200M */ - CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); - - /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ - CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); - -#ifdef CONFIG_UART_MCUX_LPUART - /* Configure UART divider to default */ - CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ - CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ -#endif - -#ifdef CONFIG_I2C_MCUX_LPI2C - CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */ - CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set I2C divider to 6 */ -#endif - -#ifdef CONFIG_SPI_MCUX_LPSPI - CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */ - CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */ -#endif - -#ifdef CONFIG_DISPLAY_MCUX_ELCDIF - /* MUX selects video PLL, which is initialized to 93MHz */ - CLOCK_SetMux(kCLOCK_LcdifPreMux, 2); - /* Divide output by 2 */ - CLOCK_SetDiv(kCLOCK_LcdifDiv, 1); - /* Set final div based on LCDIF clock-frequency */ - CLOCK_SetDiv(kCLOCK_LcdifPreDiv, - ((CLOCK_GetPllFreq(kCLOCK_PllVideo) / 2) / - DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), - clock_frequency)) - 1); -#endif - - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET -#if CONFIG_ETH_MCUX_RMII_EXT_CLK - /* Enable clock input for ENET1 */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false); -#else - /* Enable clock output for ENET1 */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); -#endif -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) && CONFIG_NET_L2_ETHERNET - /* Set ENET2 ref clock to be generated by External OSC,*/ - /* direction as output and frequency to 50MHz */ - IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir | - kIOMUXC_GPR_ENET2RefClkMode, true); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC - /* Configure USDHC clock source and divider */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); - CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); - CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); - CLOCK_EnableClock(kCLOCK_Usdhc1); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC - /* Configure USDHC clock source and divider */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); - CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1U); - CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U); - CLOCK_EnableClock(kCLOCK_Usdhc2); -#endif - -#ifdef CONFIG_VIDEO_MCUX_CSI - CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */ - CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */ - CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Set CSI source to OSC 24M */ -#endif -#ifdef CONFIG_CAN_MCUX_FLEXCAN - CLOCK_SetDiv(kCLOCK_CanDiv, 1); /* Set CAN_CLK_PODF. */ - CLOCK_SetMux(kCLOCK_CanMux, 2); /* Set Can clock source. */ -#endif - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Enable ARM trace clock to enable SWO output */ - CLOCK_EnableClock(kCLOCK_Trace); - /* Divide root clock output by 3 */ - CLOCK_SetDiv(kCLOCK_TraceDiv, 3); - /* Source clock from 528MHz system PLL */ - CLOCK_SetMux(kCLOCK_TraceMux, 0); -#endif - - /* Keep the system clock running so SYSTICK can wake up the system from - * wfi. - */ - CLOCK_SetMode(kCLOCK_ModeRun); - -} - -#if CONFIG_I2S_MCUX_SAI -void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, - uint32_t clk_pre_div, uint32_t clk_src_div) -{ - switch (clock_name) { - case IMX_CCM_SAI1_CLK: - CLOCK_SetMux(kCLOCK_Sai1Mux, clk_src); - CLOCK_SetDiv(kCLOCK_Sai1PreDiv, clk_pre_div); - CLOCK_SetDiv(kCLOCK_Sai1Div, clk_src_div); - break; - case IMX_CCM_SAI2_CLK: - CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); - CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); - break; - case IMX_CCM_SAI3_CLK: - CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); - CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); - CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); - break; - default: - return; - } -} -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ - -static int imxrt_init(void) -{ - sys_cache_instr_enable(); - sys_cache_data_enable(); - - /* Initialize system clock */ - clock_init(); - - return 0; -} - -#ifdef CONFIG_PLATFORM_SPECIFIC_INIT -void z_arm_platform_init(void) -{ - /* Call CMSIS SystemInit */ - SystemInit(); - -#if defined(FLEXRAM_RUNTIME_BANKS_USED) - /* Configure flexram if not running from RAM */ - memc_flexram_dt_partition(); -#endif -} -#endif - -SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt/soc_rt11xx.c b/soc/arm/nxp_imx/rt/soc_rt11xx.c deleted file mode 100644 index 3adedde8d38c51..00000000000000 --- a/soc/arm/nxp_imx/rt/soc_rt11xx.c +++ /dev/null @@ -1,728 +0,0 @@ -/* - * Copyright 2021-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -#include -#endif -#include -#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) -#include -/* Memcpy macro to copy segments from secondary core image stored in flash - * to RAM section that secondary core boots from. - * n is the segment number, as defined in zephyr_image_info.h - */ -#define MEMCPY_SEGMENT(n, _) \ - memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \ - (uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n), \ - (SEGMENT_SIZE_ ## n)) -#endif -#if CONFIG_USB_DC_NXP_EHCI -#include "usb_phy.h" -#include "usb.h" -#endif -#include "memc_nxp_flexram.h" - -#include - -#define DUAL_CORE_MU_ENABLED \ - (CONFIG_SECOND_CORE_MCUX && CONFIG_IPM && CONFIG_IPM_IMX) - -#if DUAL_CORE_MU_ENABLED -/* Dual core mode is enabled, and messaging unit is present */ -#include -#define BOOT_FLAG 0x1U -#define MU_BASE (MU_Type *)DT_REG_ADDR(DT_INST(0, nxp_imx_mu)) -#endif - -#if CONFIG_USB_DC_NXP_EHCI /* USB PHY configuration */ -#define BOARD_USB_PHY_D_CAL (0x07U) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -#ifdef CONFIG_INIT_ARM_PLL -static const clock_arm_pll_config_t armPllConfig = { -#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) - /* resulting frequency: 24 * (166/(2* 2)) = 984MHz */ - /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ - .postDivider = kCLOCK_PllPostDiv2, - /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ - .loopDivider = 166, -#elif defined(CONFIG_SOC_MIMXRT1166_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM7) - /* resulting frequency: 24 * (200/(2 * 4)) = 600MHz */ - /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ - .postDivider = kCLOCK_PllPostDiv4, - /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ - .loopDivider = 200, -#else - #error "Unknown SOC, no pll configuration defined" -#endif -}; -#endif - -static const clock_sys_pll2_config_t sysPll2Config = { - /* Denominator of spread spectrum */ - .mfd = 268435455, - /* Spread spectrum parameter */ - .ss = NULL, - /* Enable spread spectrum or not */ - .ssEnable = false, -}; - -#ifdef CONFIG_INIT_ENET_PLL -static const clock_sys_pll1_config_t sysPll1Config = { - .pllDiv2En = true, -}; -#endif - -#ifdef CONFIG_INIT_VIDEO_PLL -static const clock_video_pll_config_t videoPllConfig = { - /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ - .loopDivider = 41, - /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ - .postDivider = 0, - /* - * 30 bit numerator of fractional loop divider, - * Fout = Fin * ( loopDivider + numerator / denominator ) - */ - .numerator = 1, - /* - * 30 bit denominator of fractional loop divider, - * Fout = Fin * ( loopDivider + numerator / denominator ) - */ - .denominator = 960000, - /* Spread spectrum parameter */ - .ss = NULL, - /* Enable spread spectrum or not */ - .ssEnable = false, -}; -#endif - -#if CONFIG_USB_DC_NXP_EHCI - usb_phy_config_struct_t usbPhyConfig = { - BOARD_USB_PHY_D_CAL, - BOARD_USB_PHY_TXCAL45DP, - BOARD_USB_PHY_TXCAL45DM, - }; -#endif - -#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER -const __imx_boot_data_section BOOT_DATA_T boot_data = { -#ifdef CONFIG_XIP - .start = CONFIG_FLASH_BASE_ADDRESS, - .size = (uint32_t)&_flash_used, -#else - .start = CONFIG_SRAM_BASE_ADDRESS, - .size = (uint32_t)&_image_ram_size, -#endif - .plugin = PLUGIN_FLAG, - .placeholder = 0xFFFFFFFF, -}; - -extern char __start[]; -const __imx_boot_ivt_section ivt image_vector_table = { - .hdr = IVT_HEADER, - .entry = (uint32_t) __start, - .reserved1 = IVT_RSVD, -#ifdef CONFIG_DEVICE_CONFIGURATION_DATA - .dcd = (uint32_t) dcd_data, -#else - .dcd = (uint32_t) NULL, -#endif - .boot_data = (uint32_t) &boot_data, - .self = (uint32_t) &image_vector_table, - .csf = (uint32_t)CSF_ADDRESS, - .reserved2 = IVT_RSVD, -}; -#endif - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ - clock_root_config_t rootCfg = {0}; - -#if CONFIG_ADJUST_DCDC - DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); -#endif - -/* RT1160 does not have Forward Body Biasing on the CM7 core */ -#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) - /* Check if FBB need to be enabled in OverDrive(OD) mode */ - if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { - PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); - } else { - PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); - } -#endif - -#if CONFIG_BYPASS_LDO_LPSR - PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); - PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); -#endif - -#if CONFIG_ADJUST_LDO - pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; - pmu_static_lpsr_dig_config_t lpsrDigConfig; - - if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) { - PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); - PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); - } - - if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & - ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) { - PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); - lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; - PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); - } -#endif - - /* PLL LDO shall be enabled first before enable PLLs */ - - /* Config CLK_1M */ - CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); - - /* Init OSC RC 16M */ - ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; - - /* Init OSC RC 400M */ - CLOCK_OSC_EnableOscRc400M(); - CLOCK_OSC_GateOscRc400M(true); - - /* Init OSC RC 48M */ - CLOCK_OSC_EnableOsc48M(true); - CLOCK_OSC_EnableOsc48MDiv2(true); - - /* Config OSC 24M */ - ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | - ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | - ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | - ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | - ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); - - /* Wait for 24M OSC to be stable. */ - while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != - (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { - } - - rootCfg.div = 1; - -#ifdef CONFIG_CPU_CORTEX_M7 - /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ - rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); - - rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); -#endif - -#if CONFIG_CPU_CORTEX_M4 - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); - - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); -#endif - - /* - * If DCD is used, please make sure the clock source of SEMC is not - * changed in the following PLL/PFD configuration code. - */ - -#ifdef CONFIG_INIT_ARM_PLL - /* Init Arm Pll. */ - CLOCK_InitArmPll(&armPllConfig); -#endif - -#ifdef CONFIG_INIT_ENET_PLL - CLOCK_InitSysPll1(&sysPll1Config); -#else - /* Bypass Sys Pll1. */ - CLOCK_SetPllBypass(kCLOCK_PllSys1, true); - - /* DeInit Sys Pll1. */ - CLOCK_DeinitSysPll1(); -#endif - - /* Init Sys Pll2. */ - CLOCK_InitSysPll2(&sysPll2Config); - - /* Init System Pll2 pfd0. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); - - /* Init System Pll2 pfd1. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); - - /* Init System Pll2 pfd2. */ - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); - - /* Init System Pll2 pfd3. */ -#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24); -#else - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); -#endif - - /* Init Sys Pll3. */ - CLOCK_InitSysPll3(); - - /* Init System Pll3 pfd0. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); - - /* Init System Pll3 pfd1. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); - - /* Init System Pll3 pfd2. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); - - /* Init System Pll3 pfd3. */ - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); - -#ifdef CONFIG_INIT_VIDEO_PLL - /* Init Video Pll. */ - CLOCK_InitVideoPll(&videoPllConfig); -#endif - - /* Module clock root configurations. */ - /* Configure M7 using ARM_PLL_CLK */ -#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); -#endif - -#if defined(CONFIG_SOC_MIMXRT1166_CM4) - /* Configure M4 using SYS_PLL3_CLK */ - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); -#elif defined(CONFIG_SOC_MIMXRT1176_CM4) - /* Configure M4 using SYS_PLL3_CLK_PFD3_CLK */ - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); -#endif - - /* Configure BUS using SYS_PLL3_CLK */ -#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET - /* Configure root bus clock at 198M */ - rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); -#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - /* Keep root bus clock at default 240M */ - rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); -#endif - - /* Configure BUS_LPSR using SYS_PLL3_CLK */ -#if defined(CONFIG_SOC_MIMXRT1176_CM4) - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; - rootCfg.div = 3; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); -#elif defined(CONFIG_SOC_MIMXRT1166_CM4) - rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; - rootCfg.div = 4; - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); -#endif - - /* Configure CSSYS using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); - - /* Configure CSTRACE using SYS_PLL2_CLK */ - rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out; - rootCfg.div = 4; - CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); - - /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ -#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4) - rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); -#endif - - /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ -#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 240; - CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); -#endif - -#ifdef CONFIG_UART_MCUX_LPUART - /* Configure Lpuart1 using SysPll2*/ - rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); - - /* Configure Lpuart2 using SysPll2*/ - rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); -#endif - -#ifdef CONFIG_I2C_MCUX_LPI2C - /* Configure Lpi2c1 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); - - /* Configure Lpi2c5 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); -#endif - - -#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) - /* 50 MHz ENET clock */ - rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; - rootCfg.div = 10; - CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); -#if CONFIG_ETH_MCUX_RMII_EXT_CLK - /* Set ENET_REF_CLK as an input driven by PHY */ - IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U); - IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U); -#else - /* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */ - IOMUXC_GPR->GPR4 |= (IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) | - IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U)); -#endif -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay) - /* - * 50 MHz clock for 10/100Mbit RMII PHY - - * operate ENET1G just like ENET peripheral - */ - rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2; - rootCfg.div = 10; - CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); -#if CONFIG_ETH_MCUX_RMII_EXT_CLK - /* Set ENET1G_REF_CLK as an input driven by PHY */ - IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U); - IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U); -#else - /* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */ - IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) | - IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U)); -#endif -#endif -#endif - -#ifdef CONFIG_PTP_CLOCK_MCUX - /* 24MHz PTP clock */ - rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); -#endif - -#ifdef CONFIG_SPI_MCUX_LPSPI - /* Configure lpspi using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); -#endif - -#ifdef CONFIG_CAN_MCUX_FLEXCAN -#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay) - /* Configure CAN1 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); -#endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay) - /* Configure CAN1 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); -#endif -#endif - -#ifdef CONFIG_MCUX_ACMP -#if DT_NODE_HAS_STATUS(DT_NODELABEL(acmp1), okay) - /* Configure ACMP1 using Osc48MDiv2*/ - rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); -#endif -#endif - -#ifdef CONFIG_DISPLAY_MCUX_ELCDIF - rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out; - /* - * PLL2 is fixed at 528MHz. Use desired panel clock clock to - * calculate LCDIF clock. - */ - rootCfg.div = ((SYS_PLL2_FREQ / - DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), - clock_frequency)) + 1); - CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); -#endif - -#ifdef CONFIG_COUNTER_MCUX_GPT - rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI - CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, - DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); - USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); -#endif - -#if CONFIG_IMX_USDHC -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) - /* Configure USDHC1 using SysPll2Pfd2*/ - rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); - CLOCK_EnableClock(kCLOCK_Usdhc1); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) - /* Configure USDHC2 using SysPll2Pfd2*/ - rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); - CLOCK_EnableClock(kCLOCK_Usdhc2); -#endif -#endif - -#if !(defined(CONFIG_CODE_FLEXSPI) || defined(CONFIG_CODE_FLEXSPI2)) && \ - defined(CONFIG_MEMC_MCUX_FLEXSPI) && \ - DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) - /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ - rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); -#endif - - /* Keep core clock ungated during WFI */ - CCM->GPR_PRIVATE1_SET = 0x1; - /* Keep the system clock running so SYSTICK can wake up the system from - * wfi. - */ - GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_0, kGPC_RunMode); - GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_1, kGPC_RunMode); - GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_0, false); - GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_1, false); - -#if !defined(CONFIG_PM) - /* Enable the AHB clock while the CM7 is sleeping to allow debug access - * to TCM - */ - IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK; -#endif -} - -#if CONFIG_I2S_MCUX_SAI -void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, - uint32_t clk_pre_div, uint32_t clk_src_div) -{ - ARG_UNUSED(clk_pre_div); - - switch (clock_name) { - case IMX_CCM_SAI1_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai1, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai1, clk_src_div); - break; - case IMX_CCM_SAI2_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai2, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai2, clk_src_div); - break; - case IMX_CCM_SAI3_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai3, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai3, clk_src_div); - break; - case IMX_CCM_SAI4_CLK: - CLOCK_SetRootClockMux(kCLOCK_Root_Sai4, clk_src); - CLOCK_SetRootClockDiv(kCLOCK_Root_Sai4, clk_src_div); - break; - default: - return; - } -} -#endif - -#if CONFIG_MIPI_DSI -void imxrt_pre_init_display_interface(void) -{ - /* elcdif output to MIPI DSI */ - CLOCK_EnableClock(kCLOCK_Video_Mux); - VIDEO_MUX->VID_MUX_CTRL.CLR = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK; - - /* Power on and isolation off. */ - PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK | - PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK); - - /* Assert MIPI reset. */ - IOMUXC_GPR->GPR62 &= ~(IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); - - /* setup clock */ - const clock_root_config_t mipiEscClockConfig = { - .clockOff = false, - .mux = 4, - .div = 11, - }; - - CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &mipiEscClockConfig); - - /* TX esc clock */ - const clock_group_config_t mipiEscClockGroupConfig = { - .clockOff = false, - .resetDiv = 2, - .div0 = 2, - }; - - CLOCK_SetGroupConfig(kCLOCK_Group_MipiDsi, &mipiEscClockGroupConfig); - - const clock_root_config_t mipiDphyRefClockConfig = { - .clockOff = false, - .mux = 1, - .div = 1, - }; - - CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &mipiDphyRefClockConfig); - - /* Deassert PCLK and ESC reset. */ - IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK); -} - -void imxrt_post_init_display_interface(void) -{ - /* deassert BYTE and DBI reset */ - IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | - IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); -} - -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * If dual core operation is enabled, the second core image will be loaded to RAM - * - * @return 0 - */ - -static int imxrt_init(void) -{ -#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) - /** - * Copy CM4 core from flash to memory. Note that depending on where the - * user decided to store CM4 code, this is likely going to read from the - * flexspi while using XIP. Provided we DO NOT WRITE TO THE FLEXSPI, - * this operation is safe. - * - * Note that this copy MUST occur before enabling the M7 caching to - * ensure the data is written directly to RAM (since the M4 core will use it) - */ - LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;)); - /* Set the boot address for the second core */ - uint32_t boot_address = (uint32_t)(DT_REG_ADDR(DT_CHOSEN(zephyr_cpu1_region))); - /* Set VTOR for the CM4 core */ - IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(boot_address >> 3u); - IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(boot_address >> 16u); -#endif - -#if DUAL_CORE_MU_ENABLED && CONFIG_CPU_CORTEX_M4 - /* Set boot flag in messaging unit to indicate boot to primary core */ - MU_SetFlags(MU_BASE, BOOT_FLAG); -#endif - - -#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) - sys_cache_instr_enable(); - sys_cache_data_enable(); -#endif - - /* Initialize system clock */ - clock_init(); - - return 0; -} - -#ifdef CONFIG_PLATFORM_SPECIFIC_INIT -void z_arm_platform_init(void) -{ - SystemInit(); - -#if defined(FLEXRAM_RUNTIME_BANKS_USED) - /* Configure flexram if not running from RAM */ - memc_flexram_dt_partition(); -#endif -} -#endif - -SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); - -#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) -/** - * @brief Kickoff secondary core. - * - * Kick the secondary core out of reset and wait for it to indicate boot. The - * core image was already copied to RAM (and the boot address was set) in - * imxrt_init() - * - * @return 0 - */ -static int second_core_boot(void) -{ - /* Kick CM4 core out of reset */ - SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK; - SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK; -#if DUAL_CORE_MU_ENABLED - /* Wait for the secondary core to start up and set boot flag in - * imxrt_init - */ - while (MU_GetFlags(MU_BASE) != BOOT_FLAG) { - /* Wait for secondary core to set flag */ - } -#endif - return 0; -} - -SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); -#endif diff --git a/soc/arm/nxp_imx/rt5xx/CMakeLists.txt b/soc/arm/nxp_imx/rt5xx/CMakeLists.txt deleted file mode 100644 index e12f2e9ae18090..00000000000000 --- a/soc/arm/nxp_imx/rt5xx/CMakeLists.txt +++ /dev/null @@ -1,33 +0,0 @@ -# -# Copyright (c) 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) - -zephyr_sources( - soc.c - flash_clock_setup.c - ) - -zephyr_sources_ifdef(CONFIG_PM power.c) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - -zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT5XX_BOOT_HEADER - ROM_START SORT_KEY 0 boot_header.ld) - -zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER - SECTIONS usb.ld) - -zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 b/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 deleted file mode 100644 index f8419fc3b1a534..00000000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt595_cm33 +++ /dev/null @@ -1,40 +0,0 @@ -# NXP MIMXRT5XX platform configuration options - -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT595S_CM33 - -config SOC - default "mimxrt595s_cm33" - -if MCUX_OS_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif # MCUX_OS_TIMER - -if CORTEX_M_SYSTICK - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 250105263 - -endif # CORTEX_M_SYSTICK - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -# Enable the MEMC FlexSPI driver when using device power -# management so we can reconfigure the FlexSPI pins to -# save power. The MEMC FlexSPI driver is enabled when we -# enable the Flash subsystem, however we would like to -# reconfigure the FlexSPI pins even when the Flash driver -# is disabled, hence MEMC is selected when PM_DEVICE -# is turned on. -config MEMC - default y if PM_DEVICE - select MEMC_MCUX_FLEXSPI - -endif # SOC_MIMXRT685S_CM33 diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series deleted file mode 100644 index b277f621d0a2c4..00000000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.series +++ /dev/null @@ -1,82 +0,0 @@ -# i.MX RT5XX series configuration options - -# Copyright (c) 2022-2024, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_RT5XX - -config SOC_SERIES - default "rt5xx" - -config ROM_START_OFFSET - default 0x1200 if NXP_IMX_RT5XX_BOOT_HEADER - -# The PVT Sensor uses IRQ #75. For more details, see -# https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/application-software-pack-dynamic-voltage-scaling-using-pvt-sensor:APP-SW-PACK-DVS-PVT-SENSOR -config NUM_IRQS - default 76 - -config ZTEST_NO_YIELD - default y if (PM && ZTEST) - -# The base address is determined from the zephyr,flash node with the following -# precedence: -# FlexSPI base address (if flash node is on a FlexSPI bus) -# node reg property (used for memory regions such as SRAM) - -# Workaround for not being able to have commas in macro arguments - -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi - -# Macros to shorten Kconfig definitions -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ - if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -# The RT5xx has no internal flash. If the flash node has a size property, -# use that over the reg property. This is used for the external flash -# present on the board. Otherwise, fallback to the reg property -config FLASH_SIZE - default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ - if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -if FLASH_MCUX_FLEXSPI_XIP - -# Avoid RWW hazards by defaulting logging to disabled -choice FLASH_LOG_LEVEL_CHOICE - default FLASH_LOG_LEVEL_OFF -endchoice - -choice MEMC_LOG_LEVEL_CHOICE - default MEMC_LOG_LEVEL_OFF -endchoice - -endif - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -config MBEDTLS -#config TINYCRYPT - default y if CSPRNG_ENABLED - depends on ENTROPY_GENERATOR - -if MBEDTLS -# -# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than -# what the ztest_thread_stack defaults to. -# -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # MBEDTLS - -source "soc/arm/nxp_imx/rt5xx/Kconfig.defconfig.mimxrt5*" - -endif # SOC_SERIES_MIMXRT5XX diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.series b/soc/arm/nxp_imx/rt5xx/Kconfig.series deleted file mode 100644 index 9656803165193b..00000000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# i.MX RT5XX Series - -# Copyright (c) 2022, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_RT5XX - bool "i.MX RT5XX Series Family MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select HAS_PM - select HAS_POWEROFF - help - Enable support for i.MX RT5XX Series MCU series diff --git a/soc/arm/nxp_imx/rt5xx/Kconfig.soc b/soc/arm/nxp_imx/rt5xx/Kconfig.soc deleted file mode 100644 index 35b86c2e90358e..00000000000000 --- a/soc/arm/nxp_imx/rt5xx/Kconfig.soc +++ /dev/null @@ -1,156 +0,0 @@ -# i.MX RT5XX Series - -# Copyright 2022-2023, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX RT5XX Series MCU Selection" - depends on SOC_SERIES_IMX_RT5XX - -config SOC_MIMXRT595S_CM33 - bool "SOC_MIMXRT595S M33" - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select PLATFORM_SPECIFIC_INIT - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_MCUX - select HAS_MCUX_SYSCON - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_CACHE - select HAS_MCUX_LPC_DMA - select HAS_MCUX_LPADC - select HAS_MCUX_OS_TIMER - select HAS_MCUX_LPC_RTC - select HAS_MCUX_TRNG - select HAS_MCUX_SCTIMER - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select HAS_MCUX_USB_LPCIP3511 - select HAS_MCUX_CTIMER -endchoice - -if SOC_SERIES_IMX_RT5XX - -config SOC_PART_NUMBER_MIMXRT533SFFOC - bool - -config SOC_PART_NUMBER_MIMXRT555SFFOC - bool - -config SOC_PART_NUMBER_MIMXRT595SFFOC - bool - -config SOC_PART_NUMBER_MIMXRT533SFAWC - bool - -config SOC_PART_NUMBER_MIMXRT555SFAWC - bool - -config SOC_PART_NUMBER_MIMXRT595SFAWC - bool - -config SOC_PART_NUMBER_IMX_RT5XX - string - default "MIMXRT533SFAWC" if SOC_PART_NUMBER_MIMXRT533SFAWC - default "MIMXRT555SFAWC" if SOC_PART_NUMBER_MIMXRT555SFAWC - default "MIMXRT595SFAWC" if SOC_PART_NUMBER_MIMXRT595SFAWC - default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC - default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC - default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -menuconfig NXP_IMX_RT5XX_BOOT_HEADER - bool "The boot header" - depends on !BOOTLOADER_MCUBOOT - help - Enable data structures required by the boot ROM to boot the - application from an external flash device. - -if NXP_IMX_RT5XX_BOOT_HEADER - -choice BOOT_DEVICE - prompt "Boot device selection" - default BOOT_FLEXSPI_NOR - -config BOOT_FLEXSPI_NOR - bool "FlexSPI serial NOR" - -endchoice - -config FLASH_CONFIG_OFFSET - hex "Flash config data offset" - default 0x400 - help - The flash config offset provides the boot ROM with the on-board - flash type and parameters. The boot ROM requires a fixed flash config - offset for FlexSPI device. - -config IMAGE_VECTOR_TABLE_OFFSET - hex "Image vector table offset" - default 0x1000 - help - The Image Vector Table (IVT) provides the boot ROM with pointers to - the application entry point and device configuration data. The boot - ROM requires a fixed IVT offset for each type of boot device. - -config NXP_IMX_RT_ROM_RAMLOADER - depends on !FLASH_MCUX_FLEXSPI_XIP - # Required so that debugger will load image to correct offset - select BUILD_OUTPUT_HEX - bool "Create output image that IMX RT ROM can load from FlexSPI to ram" - help - Builds an output image that the IMX RT BootROM can load from the - FlexSPI boot device into RAM region. The image will be loaded - from FLEXSPI0 into the region specified by `zephyr,flash` node. - -# Setup LMA adjustment if using the RAMLOADER feature of ROM -FLASH_CHOSEN := zephyr,flash -FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) -FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) -config BUILD_OUTPUT_ADJUST_LMA - default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER - -endif # NXP_IMX_RT5XX_BOOT_HEADER - - - -config IMXRT5XX_CODE_CACHE - bool "Code cache" - default y - help - Enable code cache for FlexSPI region at boot. If this Kconfig is - cleared, the CACHE64 controller will be disabled during SOC init - -choice FLEXCOMM0_CLK_SRC - prompt "Clock source for Flexcomm0" - default FLEXCOMM0_CLK_SRC_FRG - -config FLEXCOMM0_CLK_SRC_FRG - bool "FRG is source of Flexcomm0 clock" - -config FLEXCOMM0_CLK_SRC_FRO - bool "FRO_DIV4 is source of Flexcomm0 clock" - -endchoice - -choice MIPI_DPHY_CLK_SRC - prompt "Clock source for MIPI DPHY" - default MIPI_DPHY_CLK_SRC_AUX1_PLL - -config MIPI_DPHY_CLK_SRC_AUX1_PLL - bool "AUX1_PLL is source of MIPI_DPHY clock" - -config MIPI_DPHY_CLK_SRC_FRO - bool "FRO 192/96M is source of MIPI_DPHY clock" - -endchoice - -endif # SOC_SERIES_IMX_RT5XX diff --git a/soc/arm/nxp_imx/rt5xx/boot_header.ld b/soc/arm/nxp_imx/rt5xx/boot_header.ld deleted file mode 100644 index 43683f6c7be87e..00000000000000 --- a/soc/arm/nxp_imx/rt5xx/boot_header.ld +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2022 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -. = CONFIG_FLASH_CONFIG_OFFSET; -KEEP(*(.flash_conf)) -. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; -KEEP(*(.boot_hdr.ivt)) diff --git a/soc/arm/nxp_imx/rt5xx/soc.c b/soc/arm/nxp_imx/rt5xx/soc.c deleted file mode 100644 index ca2a89cd553247..00000000000000 --- a/soc/arm/nxp_imx/rt5xx/soc.c +++ /dev/null @@ -1,544 +0,0 @@ -/* - * Copyright 2022-2023, NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for NXP RT5XX platform - * - * This module provides routines to initialize and support board-level - * hardware for the RT5XX platforms. - */ - -#include -#include -#include -#include -#include "fsl_power.h" -#include "fsl_clock.h" -#include - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP -#include "flash_clock_setup.h" -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 -#include "usb_phy.h" -#include "usb.h" -#endif - -/* Board System oscillator settling time in us */ -#define BOARD_SYSOSC_SETTLING_US 100U -/* Board xtal frequency in Hz */ -#define BOARD_XTAL_SYS_CLK_HZ 24000000U -/* Core clock frequency: 198000000Hz */ -#define CLOCK_INIT_CORE_CLOCK 198000000U - -#define CTIMER_CLOCK_SOURCE(node_id) \ - TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) -#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) -#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) -#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); - -const clock_sys_pll_config_t g_sysPllConfig_clock_init = { - /* OSC clock */ - .sys_pll_src = kCLOCK_SysPllXtalIn, - /* Numerator of the SYSPLL0 fractional loop divider is 0 */ - .numerator = 0, - /* Denominator of the SYSPLL0 fractional loop divider is 1 */ - .denominator = 1, - /* Divide by 22 */ - .sys_pll_mult = kCLOCK_SysPllMult22 -}; - -const clock_audio_pll_config_t g_audioPllConfig_clock_init = { - /* OSC clock */ - .audio_pll_src = kCLOCK_AudioPllXtalIn, - /* Numerator of the Audio PLL fractional loop divider is 0 */ - .numerator = 5040, - /* Denominator of the Audio PLL fractional loop divider is 1 */ - .denominator = 27000, - /* Divide by 22 */ - .audio_pll_mult = kCLOCK_AudioPllMult22 -}; - -const clock_frg_clk_config_t g_frg0Config_clock_init = { - .num = 0, - .sfg_clock_src = kCLOCK_FrgPllDiv, - .divider = 255U, - .mult = 0 -}; - -const clock_frg_clk_config_t g_frg12Config_clock_init = { - .num = 12, - .sfg_clock_src = kCLOCK_FrgMainClk, - .divider = 255U, - .mult = 167 -}; - -#if CONFIG_USB_DC_NXP_LPCIP3511 -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -/* System clock frequency. */ -extern uint32_t SystemCoreClock; -/* Main stack pointer */ -extern char z_main_stack[]; - -#ifdef CONFIG_NXP_IMX_RT5XX_BOOT_HEADER -extern char _flash_used[]; - -extern void z_arm_reset(void); -extern void z_arm_nmi(void); -extern void z_arm_hard_fault(void); -extern void z_arm_mpu_fault(void); -extern void z_arm_bus_fault(void); -extern void z_arm_usage_fault(void); -extern void z_arm_secure_fault(void); -extern void z_arm_svc(void); -extern void z_arm_debug_monitor(void); -extern void z_arm_pendsv(void); -extern void sys_clock_isr(void); -extern void z_arm_exc_spurious(void); - -__imx_boot_ivt_section void (* const image_vector_table[])(void) = { - (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ - z_arm_reset, /* 0x04 */ - z_arm_nmi, /* 0x08 */ - z_arm_hard_fault, /* 0x0C */ - z_arm_mpu_fault, /* 0x10 */ - z_arm_bus_fault, /* 0x14 */ - z_arm_usage_fault, /* 0x18 */ -#if defined(CONFIG_ARM_SECURE_FIRMWARE) - z_arm_secure_fault, /* 0x1C */ -#else - z_arm_exc_spurious, -#endif /* CONFIG_ARM_SECURE_FIRMWARE */ - (void (*)())_flash_used, /* 0x20, imageLength. */ - 0, /* 0x24, imageType (Plain Image) */ - 0, /* 0x28, authBlockOffset/crcChecksum */ - z_arm_svc, /* 0x2C */ - z_arm_debug_monitor, /* 0x30 */ - (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ - z_arm_pendsv, /* 0x38 */ -#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ - defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) - sys_clock_isr, /* 0x3C */ -#else - z_arm_exc_spurious, -#endif -}; -#endif /* CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */ - -#if CONFIG_USB_DC_NXP_LPCIP3511 - -static void usb_device_clock_init(void) -{ - uint8_t usbClockDiv = 1; - uint32_t usbClockFreq; - usb_phy_config_struct_t phyConfig = { - BOARD_USB_PHY_D_CAL, - BOARD_USB_PHY_TXCAL45DP, - BOARD_USB_PHY_TXCAL45DM, - }; - - /* Make sure USBHS ram buffer and usb1 phy has power up */ - POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); - POWER_ApplyPD(); - - RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); - - /* enable usb ip clock */ - CLOCK_EnableUsbHs0DeviceClock(kOSC_CLK_to_USB_CLK, usbClockDiv); - /* save usb ip clock freq*/ - usbClockFreq = g_xtalFreq / usbClockDiv; - CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4); - /* enable usb ram clock */ - CLOCK_EnableClock(kCLOCK_UsbhsSram); - /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ - CLOCK_EnableUsbHs0PhyPllClock(kOSC_CLK_to_USB_CLK, usbClockFreq); - - /* USB PHY initialization */ - USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL_SYS_CLK_HZ, &phyConfig); - -#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) - for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { - ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; - } -#endif - - /* The following code should run after phy initialization and should wait - * some microseconds to make sure utmi clock valid - */ - /* enable usb1 host clock */ - CLOCK_EnableClock(kCLOCK_UsbhsHost); - /* Wait until host_needclk de-asserts */ - while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { - __ASM("nop"); - } - /* According to reference mannual, device mode setting has to be set by access - * usb host register - */ - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - /* disable usb1 host clock */ - CLOCK_DisableClock(kCLOCK_UsbhsHost); -} - -#endif - -void z_arm_platform_init(void) -{ -#ifndef CONFIG_NXP_IMX_RT5XX_BOOT_HEADER - /* - * If boot did not proceed using a boot header, we should not assume - * the core is in reset state. Disable the MPU and correctly - * set the stack pointer, since we are about to push to - * the stack when we call SystemInit - */ - /* Clear stack limit registers */ - __set_MSPLIM(0); - __set_PSPLIM(0); - /* Disable MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - /* Set stack pointer */ - __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); -#endif /* !CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */ - /* This is provided by the SDK */ - SystemInit(); -} - -/* Weak so that board can override with their own clock init routine. */ -void __weak rt5xx_clock_init(void) -{ - /* Configure LPOSC 1M */ - /* Power on LPOSC (1MHz) */ - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - /* Wait until LPOSC stable */ - CLOCK_EnableLpOscClk(); - - /* Configure FRO clock source */ - /* Power on FRO (192MHz or 96MHz) */ - POWER_DisablePD(kPDRUNCFG_PD_FFRO); - /* FRO_DIV1 is always enabled and used as Main clock during PLL update. */ - /* Enable all FRO outputs */ - CLOCK_EnableFroClk(kCLOCK_FroAllOutEn); - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable - * clock source to avoid instruction/data fetch issue when updating PLL and Main - * clock if XIP(execute code on FLEXSPI memory). - */ - flexspi_clock_safe_config(); -#endif - - /* Let CPU run on FRO with divider 2 for safe switching. */ - CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2); - CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK); - - /* Configure SYSOSC clock source. */ - /* Power on SYSXTAL */ - POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); - /* Updated XTAL oscillator settling time */ - POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); - /* Enable system OSC */ - CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); - /* Sets external XTAL OSC freq */ - CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); - - /* Configure SysPLL0 clock source. */ - CLOCK_InitSysPll(&g_sysPllConfig_clock_init); - /* Enable MAIN PLL clock */ - CLOCK_InitSysPfd(kCLOCK_Pfd0, 24); - /* Enable AUX0 PLL clock */ - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); - - /* Configure Audio PLL clock source. */ - CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); - /* Enable Audio PLL clock */ - CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); - - /* Set SYSCPUAHBCLKDIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); - - /* Setup FRG0 clock */ - CLOCK_SetFRGClock(&g_frg0Config_clock_init); - /* Setup FRG12 clock */ - CLOCK_SetFRGClock(&g_frg12Config_clock_init); - - /* Set up clock selectors - Attach clocks to the peripheries. */ - /* Switch MAIN_CLK to MAIN_PLL */ - CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); - /* Switch SYSTICK_CLK to MAIN_CLK_DIV */ - CLOCK_AttachClk(kMAIN_CLK_DIV_to_SYSTICK_CLK); -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) - #ifdef CONFIG_FLEXCOMM0_CLK_SRC_FRG - /* Switch FLEXCOMM0 to FRG */ - CLOCK_AttachClk(kFRG_to_FLEXCOMM0); - #elif defined(CONFIG_FLEXCOMM0_CLK_SRC_FRO) - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM0); - #endif -#endif -#if CONFIG_USB_DC_NXP_LPCIP3511 - usb_device_clock_init(); -#endif - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay) && CONFIG_I2S) - /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); -#endif -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay) && CONFIG_I2S) - /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay) - /* Switch FLEXCOMM4 to FRO_DIV4 */ - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM4); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay) - /* Attach main clock to I3C, divider will be set in i3c_mcux.c */ - CLOCK_AttachClk(kMAIN_CLK_to_I3C_CLK); - CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(hs_spi1), nxp_lpc_spi, okay) - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM16); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm12), nxp_lpc_usart, okay) - /* Switch FLEXCOMM12 to FRG */ - CLOCK_AttachClk(kFRG_to_FLEXCOMM12); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) - CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM15); -#endif -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_dcnano_lcdif, okay) && CONFIG_DISPLAY - POWER_DisablePD(kPDRUNCFG_APD_DCNANO_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_DCNANO_SRAM); - POWER_ApplyPD(); - - CLOCK_AttachClk(kAUX0_PLL_to_DCPIXEL_CLK); - /* Note- pixel clock follows formula - * (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate. - * this means the clock divider will vary depending on - * the attached display. - * - * The root clock used here is the AUX0 PLL (PLL0 PFD2). - */ - CLOCK_SetClkDiv(kCLOCK_DivDcPixelClk, - ((CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / - DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), - clock_frequency)) + 1)); - - CLOCK_EnableClock(kCLOCK_DisplayCtrl); - RESET_ClearPeripheralReset(kDISP_CTRL_RST_SHIFT_RSTn); - - CLOCK_EnableClock(kCLOCK_AxiSwitch); - RESET_ClearPeripheralReset(kAXI_SWITCH_RST_SHIFT_RSTn); -#if defined(CONFIG_MEMC) && DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), \ - nxp_imx_flexspi, okay) - /* Enable write-through for FlexSPI1 space */ - CACHE64_POLSEL0->REG1_TOP = 0x27FFFC00U; - CACHE64_POLSEL0->POLSEL = 0x11U; -#endif -#endif - - /* Switch CLKOUT to FRO_DIV2 */ - CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT); - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC - /* Make sure USDHC ram buffer has been power up*/ - POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - POWER_ApplyPD(); - - /* usdhc depend on 32K clock also */ - CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); - CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); - CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); - CLOCK_EnableClock(kCLOCK_Sdio0); - RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(smartdma), okay) && CONFIG_DMA_MCUX_SMARTDMA - /* Power up SMARTDMA ram */ - POWER_DisablePD(kPDRUNCFG_APD_SMARTDMA_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_SMARTDMA_SRAM); - POWER_ApplyPD(); - - RESET_ClearPeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); - CLOCK_EnableClock(kCLOCK_Smartdma); -#endif - - DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) - - /* Set up dividers. */ - /* Set AUDIOPLLCLKDIV divider to value 15 */ - CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); - /* Set FRGPLLCLKDIV divider to value 11 */ - CLOCK_SetClkDiv(kCLOCK_DivPLLFRGClk, 11U); - /* Set SYSTICKFCLKDIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 2U); - /* Set PFC0DIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); - /* Set PFC1DIV divider to value 4 */ - CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4U); - /* Set CLKOUTFCLKDIV divider to value 100 */ - CLOCK_SetClkDiv(kCLOCK_DivClockOut, 100U); - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_setup_clock() to set user configured clock source/divider - * for FlexSPI. - */ - flexspi_setup_clock(FLEXSPI0, 0U, 2U); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), nxp_imx_flexspi, okay) - /* Power up FlexSPI1 SRAM */ - POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI1_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI1_SRAM); - POWER_ApplyPD(); - /* Setup clock frequency for FlexSPI1 */ - CLOCK_AttachClk(kMAIN_CLK_to_FLEXSPI1_CLK); - CLOCK_SetClkDiv(kCLOCK_DivFlexspi1Clk, 1); - /* Reset peripheral module */ - RESET_PeripheralReset(kFLEXSPI1_RST_SHIFT_RSTn); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; - RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); - CLOCK_AttachClk(kFRO_DIV4_to_ADC_CLK); - CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1); -#endif - -#if CONFIG_COUNTER_NXP_MRT - RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) - /* Using the Audio PLL as input clock leads to better clock dividers - * for typical PCM sample rates ({8,16,24,32,48,96} kHz. - */ - /* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ - * Select Audio PLL as clock source. This should produce a bit clock - * of 3.072MHZ - */ - CLOCK_AttachClk(kAUDIO_PLL_to_DMIC); - CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8); - -#endif - - /* Set SystemCoreClock variable. */ - SystemCoreClock = CLOCK_INIT_CORE_CLOCK; - - /* Set main clock to FRO as deep sleep clock by default. */ - POWER_SetDeepSleepClock(kDeepSleepClk_Fro); -} - -#if CONFIG_MIPI_DSI -/* Weak so board can override this function */ -void __weak imxrt_pre_init_display_interface(void) -{ - /* Assert MIPI DPHY reset. */ - RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); - POWER_DisablePD(kPDRUNCFG_APD_MIPIDSI_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_MIPIDSI_SRAM); - POWER_DisablePD(kPDRUNCFG_PD_MIPIDSI); - POWER_ApplyPD(); - - /* RxClkEsc max 60MHz, TxClkEsc 12 to 20MHz. */ - CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHYESC_CLK); - /* RxClkEsc = 192MHz / 4 = 48MHz. */ - CLOCK_SetClkDiv(kCLOCK_DivDphyEscRxClk, 4); - /* TxClkEsc = 192MHz / 4 / 3 = 16MHz. */ - CLOCK_SetClkDiv(kCLOCK_DivDphyEscTxClk, 3); - - /* - * The DPHY bit clock must be fast enough to send out the pixels, - * it should be larger than: - * - * (Pixel clock * bit per output pixel) / number of MIPI data lane - * - * DPHY supports up to 895.1MHz bit clock. - * We set the divider of the PFD3 output of the SYSPLL, which has a - * fixed multiplied of 18, and use this output frequency for the DPHY. - */ - -#ifdef CONFIG_MIPI_DPHY_CLK_SRC_AUX1_PLL - /* Note: AUX1 PLL clock is system pll clock * 18 / pfd. - * system pll clock is configured at 528MHz by default. - */ - CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK); - CLOCK_InitSysPfd(kCLOCK_Pfd3, - ((CLOCK_GetSysPllFreq() * 18ull) / - ((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))))); - CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1); -#elif defined(CONFIG_MIPI_DPHY_CLK_SRC_FRO) - CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHY_CLK); - CLOCK_SetClkDiv(kCLOCK_DivDphyClk, - (CLK_FRO_CLK / DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))); -#endif - /* Clear DSI control reset (Note that DPHY reset is cleared later)*/ - RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); -} - -void __weak imxrt_post_init_display_interface(void) -{ - /* Deassert MIPI DPHY reset. */ - RESET_ClearPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); -} - -void __weak imxrt_deinit_display_interface(void) -{ - /* Assert MIPI DPHY and DSI reset */ - RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); - RESET_SetPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); - /* Remove clock from DPHY */ - CLOCK_AttachClk(kNONE_to_MIPI_DPHY_CLK); -} - - -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ -static int nxp_rt500_init(void) -{ - /* Initialize clocks with tool generated code */ - rt5xx_clock_init(); - -#ifndef CONFIG_IMXRT5XX_CODE_CACHE - CACHE64_DisableCache(CACHE64_CTRL0); -#endif - - /* Some ROM versions may have errata leaving these pins in a non-reset state, - * which can often cause power leakage on most expected board designs, - * restore the reset state here and leave the pin configuration up to board/user DT - */ - IOPCTL->PIO[1][15] = 0; - IOPCTL->PIO[3][28] = 0; - IOPCTL->PIO[3][29] = 0; - - return 0; -} - -SYS_INIT(nxp_rt500_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt6xx/CMakeLists.txt b/soc/arm/nxp_imx/rt6xx/CMakeLists.txt deleted file mode 100644 index 57d5cb3fd04671..00000000000000 --- a/soc/arm/nxp_imx/rt6xx/CMakeLists.txt +++ /dev/null @@ -1,36 +0,0 @@ -# -# Copyright (c) 2020, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP - flash_clock_setup.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) - -zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT6XX_BOOT_HEADER - ROM_START SORT_KEY 0 boot_header.ld) - -zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER - SECTIONS usb.ld) - -if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) - zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33 b/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33 deleted file mode 100644 index 47670d0b6aea87..00000000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt685_cm33 +++ /dev/null @@ -1,32 +0,0 @@ -# NXP MIMXRT6XX platform configuration options - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMXRT685S_CM33 - -config SOC - default "mimxrt685s_cm33" - -config I2S_MCUX_FLEXCOMM - select INIT_AUDIO_PLL - -if MCUX_OS_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -endif # MCUX_OS_TIMER - -if CORTEX_M_SYSTICK - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 250105263 - -endif # CORTEX_M_SYSTICK - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -endif # SOC_MIMXRT685S_CM33 diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series b/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series deleted file mode 100644 index 7bcbc4e8e801ba..00000000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.series +++ /dev/null @@ -1,81 +0,0 @@ -# i.MX RT6XX series configuration options - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_IMX_RT6XX - -config SOC_SERIES - default "rt6xx" - -config ROM_START_OFFSET - default 0x1200 if NXP_IMX_RT6XX_BOOT_HEADER - -config NUM_IRQS - default 60 - -config ZTEST_NO_YIELD - default y if (ZTEST && PM) - - -# The base address is determined from the zephyr,flash node with the following -# precedence: -# FlexSPI base address (if flash node is on a FlexSPI bus) -# node reg property (used for memory regions such as SRAM) - -# Workaround for not being able to have commas in macro arguments - -DT_CHOSEN_Z_FLASH := zephyr,flash -DT_COMPAT_FLEXSPI := nxp,imx-flexspi - -# Macros to shorten Kconfig definitions -DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) -DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ - if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -# The RT6xx has no internal flash. If the flash node has a size property, -# use that over the reg property. This is used for the external flash -# present on the board. Otherwise, fallback to the reg property -config FLASH_SIZE - default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ - if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -if FLASH_MCUX_FLEXSPI_XIP - -# Avoid RWW hazards by defaulting logging to disabled -choice FLASH_LOG_LEVEL_CHOICE - default FLASH_LOG_LEVEL_OFF -endchoice - -choice MEMC_LOG_LEVEL_CHOICE - default MEMC_LOG_LEVEL_OFF -endchoice - -endif - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -config MBEDTLS -#config TINYCRYPT - default y if CSPRNG_ENABLED - depends on ENTROPY_GENERATOR - -if MBEDTLS -# -# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than -# what the ztest_thread_stack defaults to. -# -config TEST_EXTRA_STACK_SIZE - int - default 1024 -endif # MBEDTLS - -source "soc/arm/nxp_imx/rt6xx/Kconfig.defconfig.mimxrt6*" - -endif # SOC_SERIES_MIMXRT6XX diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.series b/soc/arm/nxp_imx/rt6xx/Kconfig.series deleted file mode 100644 index bcbf86ff6bfbb6..00000000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# i.MX RT6XX Series - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_IMX_RT6XX - bool "i.MX RT6XX Series Family MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_IMX - select CLOCK_CONTROL - select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP - select PLATFORM_SPECIFIC_INIT - select HAS_PM - help - Enable support for i.MX RT6XX Series MCU series diff --git a/soc/arm/nxp_imx/rt6xx/Kconfig.soc b/soc/arm/nxp_imx/rt6xx/Kconfig.soc deleted file mode 100644 index e2222ab3214b17..00000000000000 --- a/soc/arm/nxp_imx/rt6xx/Kconfig.soc +++ /dev/null @@ -1,136 +0,0 @@ -# i.MX RT6XX Series - -# Copyright (c) 2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "i.MX RT6XX Series MCU Selection" - depends on SOC_SERIES_IMX_RT6XX - -config SOC_MIMXRT685S_CM33 - bool "SOC_MIMXRT685S M33" - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_MCUX - select HAS_MCUX_SYSCON - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_FLEXSPI - select HAS_MCUX_CACHE - select HAS_MCUX_LPC_DMA - select HAS_MCUX_LPADC - select HAS_MCUX_OS_TIMER - select HAS_MCUX_LPC_RTC - select HAS_MCUX_TRNG - select HAS_MCUX_SCTIMER - select HAS_MCUX_USDHC1 - select HAS_MCUX_USDHC2 - select INIT_SYS_PLL - select HAS_MCUX_USB_LPCIP3511 - select HAS_MCUX_CTIMER -endchoice - -if SOC_SERIES_IMX_RT6XX - -config SOC_PART_NUMBER_MIMXRT685SFVKB - bool - -config SOC_PART_NUMBER_MIMXRT685SFFOB - bool - -config SOC_PART_NUMBER_MIMXRT685SFAWBR - bool - -config SOC_PART_NUMBER_IMX_RT6XX - string - default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB - default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB - default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -config INIT_SYS_PLL - bool "Initialize SYS PLL" - -config INIT_AUDIO_PLL - bool "Initialize Audio PLL" - -config XTAL_SYS_CLK_HZ - int "External oscillator frequency" - help - Set the external oscillator frequency in Hz. This should be set by the - board's defconfig. - -config SYSOSC_SETTLING_US - int "System oscillator settling time" - help - Set the board system oscillator settling time in us. This should be set by the - board's defconfig. - -menuconfig NXP_IMX_RT6XX_BOOT_HEADER - bool "Boot header" - depends on !BOOTLOADER_MCUBOOT - help - Enable data structures required by the boot ROM to boot the - application from an external flash device. - -if NXP_IMX_RT6XX_BOOT_HEADER - -choice BOOT_DEVICE - prompt "Boot device selection" - default BOOT_FLEXSPI_NOR - -config BOOT_FLEXSPI_NOR - bool "FlexSPI serial NOR" - -endchoice - -config FLASH_CONFIG_OFFSET - hex "Flash config data offset" - default 0x400 - help - The flash config offset provides the boot ROM with the on-board - flash type and parameters. The boot ROM requires a fixed flash config - offset for FlexSPI device. - -config IMAGE_VECTOR_TABLE_OFFSET - hex "Image vector table offset" - default 0x1000 - help - The Image Vector Table (IVT) provides the boot ROM with pointers to - the application entry point and device configuration data. The boot - ROM requires a fixed IVT offset for each type of boot device. - -config NXP_IMX_RT_ROM_RAMLOADER - depends on !FLASH_MCUX_FLEXSPI_XIP - # Required so that debugger will load image to correct offset - select BUILD_OUTPUT_HEX - bool "Create output image that IMX RT ROM can load from FlexSPI to ram" - help - Builds an output image that the IMX RT BootROM can load from the - FlexSPI boot device into RAM region. The image will be loaded - from FLEXSPI into the region specified by `zephyr,flash` node. - -# Setup LMA adjustment if using the RAMLOADER feature of ROM -FLASH_CHOSEN := zephyr,flash -FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) -FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) -config BUILD_OUTPUT_ADJUST_LMA - default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER - -endif # NXP_IMX_RT6XX_BOOT_HEADER - -config IMXRT6XX_CODE_CACHE - bool "Code cache" - default y - help - Enable code cache for FlexSPI region at boot. If this Kconfig is - cleared, the CACHE64 controller will be disabled during SOC init - -endif # SOC_SERIES_IMX_RT6XX diff --git a/soc/arm/nxp_imx/rt6xx/boot_header.ld b/soc/arm/nxp_imx/rt6xx/boot_header.ld deleted file mode 100644 index b2b0eda70e39eb..00000000000000 --- a/soc/arm/nxp_imx/rt6xx/boot_header.ld +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2020 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -. = CONFIG_FLASH_CONFIG_OFFSET; -KEEP(*(.flash_conf)) -. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; -KEEP(*(.boot_hdr.ivt)) diff --git a/soc/arm/nxp_imx/rt6xx/soc.c b/soc/arm/nxp_imx/rt6xx/soc.c deleted file mode 100644 index 165cf92e234b1c..00000000000000 --- a/soc/arm/nxp_imx/rt6xx/soc.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * Copyright 2020-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for nxp_lpc55s69 platform - * - * This module provides routines to initialize and support board-level - * hardware for the nxp_lpc55s69 platform. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP -#include "flash_clock_setup.h" -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 -#include "usb_phy.h" -#include "usb.h" -#endif - -/* Core clock frequency: 250105263Hz */ -#define CLOCK_INIT_CORE_CLOCK 250105263U - -#define SYSTEM_IS_XIP_FLEXSPI() \ - ((((uint32_t)nxp_rt600_init >= 0x08000000U) && \ - ((uint32_t)nxp_rt600_init < 0x10000000U)) || \ - (((uint32_t)nxp_rt600_init >= 0x18000000U) && \ - ((uint32_t)nxp_rt600_init < 0x20000000U))) - -#define CTIMER_CLOCK_SOURCE(node_id) \ - TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) -#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) -#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) -#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); - -#ifdef CONFIG_INIT_SYS_PLL -const clock_sys_pll_config_t g_sysPllConfig = { - .sys_pll_src = kCLOCK_SysPllXtalIn, - .numerator = 0, - .denominator = 1, - .sys_pll_mult = kCLOCK_SysPllMult22 -}; -#endif - -#ifdef CONFIG_INIT_AUDIO_PLL -const clock_audio_pll_config_t g_audioPllConfig = { - .audio_pll_src = kCLOCK_AudioPllXtalIn, - .numerator = 5040, - .denominator = 27000, - .audio_pll_mult = kCLOCK_AudioPllMult22 -}; -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 -/* USB PHY condfiguration */ -#define BOARD_USB_PHY_D_CAL (0x0CU) -#define BOARD_USB_PHY_TXCAL45DP (0x06U) -#define BOARD_USB_PHY_TXCAL45DM (0x06U) -#endif - -/* System clock frequency. */ -extern uint32_t SystemCoreClock; -/* Main stack pointer */ -extern char z_main_stack[]; - -#ifdef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER -extern char _flash_used[]; -extern void z_arm_reset(void); -extern void z_arm_nmi(void); -extern void z_arm_hard_fault(void); -extern void z_arm_mpu_fault(void); -extern void z_arm_bus_fault(void); -extern void z_arm_usage_fault(void); -extern void z_arm_secure_fault(void); -extern void z_arm_svc(void); -extern void z_arm_debug_monitor(void); -extern void z_arm_pendsv(void); -extern void sys_clock_isr(void); -extern void z_arm_exc_spurious(void); - -__imx_boot_ivt_section void (* const image_vector_table[])(void) = { - (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ - z_arm_reset, /* 0x04 */ - z_arm_nmi, /* 0x08 */ - z_arm_hard_fault, /* 0x0C */ - z_arm_mpu_fault, /* 0x10 */ - z_arm_bus_fault, /* 0x14 */ - z_arm_usage_fault, /* 0x18 */ -#if defined(CONFIG_ARM_SECURE_FIRMWARE) - z_arm_secure_fault, /* 0x1C */ -#else - z_arm_exc_spurious, -#endif /* CONFIG_ARM_SECURE_FIRMWARE */ - (void (*)())_flash_used, /* 0x20, imageLength. */ - 0, /* 0x24, imageType (Plain Image) */ - 0, /* 0x28, authBlockOffset/crcChecksum */ - z_arm_svc, /* 0x2C */ - z_arm_debug_monitor, /* 0x30 */ - (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ - z_arm_pendsv, /* 0x38 */ -#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ - defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) - sys_clock_isr, /* 0x3C */ -#else - z_arm_exc_spurious, -#endif -}; -#endif /* CONFIG_NXP_IMX_RT6XX_BOOT_HEADER */ - -#if CONFIG_USB_DC_NXP_LPCIP3511 - -static void usb_device_clock_init(void) -{ - uint8_t usbClockDiv = 1; - uint32_t usbClockFreq; - usb_phy_config_struct_t phyConfig = { - BOARD_USB_PHY_D_CAL, - BOARD_USB_PHY_TXCAL45DP, - BOARD_USB_PHY_TXCAL45DM, - }; - - /* enable USB IP clock */ - CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 5); - CLOCK_AttachClk(kXTALIN_CLK_to_USB_CLK); - CLOCK_SetClkDiv(kCLOCK_DivUsbHsFclk, usbClockDiv); - CLOCK_EnableUsbhsDeviceClock(); - RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); - RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); - /*Make sure USBHS ram buffer has power up*/ - POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); - POWER_ApplyPD(); - - /* save usb ip clock freq*/ - usbClockFreq = g_xtalFreq / usbClockDiv; - /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ - CLOCK_EnableUsbHs0PhyPllClock(kXTALIN_CLK_to_USB_CLK, usbClockFreq); - -#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) - for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { - ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; - } -#endif - USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_XTAL_OSC_CLK, &phyConfig); - - /* the following code should run after phy initialization and - * should wait some microseconds to make sure utmi clock valid - */ - /* enable usb1 host clock */ - CLOCK_EnableClock(kCLOCK_UsbhsHost); - /* Wait until host_needclk de-asserts */ - while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) { - __ASM("nop"); - } - /* According to reference mannual, device mode setting has to be set by - * access usb host register - */ - USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; - /* disable usb1 host clock */ - CLOCK_DisableClock(kCLOCK_UsbhsHost); -} - -#endif - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ -#ifdef CONFIG_SOC_MIMXRT685S_CM33 - /* Configure LPOSC clock*/ - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - /* Configure FFRO clock */ - POWER_DisablePD(kPDRUNCFG_PD_FFRO); - CLOCK_EnableFfroClk(kCLOCK_Ffro48M); - /* Configure SFRO clock */ - POWER_DisablePD(kPDRUNCFG_PD_SFRO); - CLOCK_EnableSfroClk(); - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable - * clock source to avoid instruction/data fetch issue when updating PLL and Main - * clock if XIP(execute code on FLEXSPI memory). - */ - flexspi_clock_safe_config(); -#endif - - /* Let CPU run on FFRO for safe switching. */ - CLOCK_AttachClk(kFFRO_to_MAIN_CLK); - - /* Configure SYSOSC clock source */ - POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); - POWER_UpdateOscSettlingTime(CONFIG_SYSOSC_SETTLING_US); - CLOCK_EnableSysOscClk(true, true, CONFIG_SYSOSC_SETTLING_US); - CLOCK_SetXtalFreq(CONFIG_XTAL_SYS_CLK_HZ); - -#ifdef CONFIG_INIT_SYS_PLL - /* Configure SysPLL0 clock source */ - CLOCK_InitSysPll(&g_sysPllConfig); - CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); - CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); -#endif - -#ifdef CONFIG_INIT_AUDIO_PLL - /* Configure Audio PLL clock source */ - CLOCK_InitAudioPll(&g_audioPllConfig); - CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); - CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); -#endif - - /* Set SYSCPUAHBCLKDIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); - - /* Set up clock selectors - Attach clocks to the peripheries */ - CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); - - /* Set up dividers */ - /* Set PFC0DIV divider to value 2 */ - CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); - /* Set FRGPLLCLKDIV divider to value 12 */ - CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) - CLOCK_AttachClk(kSFRO_to_FLEXCOMM0); -#endif - -#if CONFIG_USB_DC_NXP_LPCIP3511 - usb_device_clock_init(); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay) - CLOCK_AttachClk(kSFRO_to_FLEXCOMM2); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) - CLOCK_AttachClk(kFFRO_to_FLEXCOMM15); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_usart, okay) - CLOCK_AttachClk(kSFRO_to_FLEXCOMM4); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay) - CLOCK_AttachClk(kFFRO_to_FLEXCOMM5); -#endif - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) - /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); -#endif -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) - /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ - CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); -#endif - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)) - CLOCK_AttachClk(kLPOSC_to_WDT0_CLK); -#else - /* Allowed to select none if not being used for watchdog to - * reduce power - */ - CLOCK_AttachClk(kNONE_to_WDT0_CLK); -#endif - -#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC - /* Make sure USDHC ram buffer has been power up*/ - POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); - POWER_DisablePD(kPDRUNCFG_PD_LPOSC); - POWER_ApplyPD(); - - /* usdhc depend on 32K clock also */ - CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); - CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); - CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); - CLOCK_EnableClock(kCLOCK_Sdio0); - RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); -#endif - - DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) - DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP) - -#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay)) - CLOCK_AttachClk(kFFRO_to_I3C_CLK); - CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); -#endif - -#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; - SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; - RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); - CLOCK_AttachClk(kSFRO_to_ADC_CLK); - CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider)); -#endif - -#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP - /* - * Call function flexspi_setup_clock() to set user configured clock source/divider - * for FlexSPI. - */ - flexspi_setup_clock(FLEXSPI, 1U, 9U); -#endif - -#if CONFIG_COUNTER_NXP_MRT - RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); -#endif - - /* Set SystemCoreClock variable. */ - SystemCoreClock = CLOCK_INIT_CORE_CLOCK; - -#endif /* CONFIG_SOC_MIMXRT685S_CM33 */ -} - -#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC) - -void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init, - uint32_t speed, uint32_t strength) -{ - -} - -void imxrt_usdhc_dat3_pull(bool pullup) -{ - -} -#endif - -/** - * - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ - -static int nxp_rt600_init(void) -{ - /* Initialize clock */ - clock_init(); - -#ifndef CONFIG_IMXRT6XX_CODE_CACHE - CACHE64_DisableCache(CACHE64); -#endif - - return 0; -} - -#ifdef CONFIG_PLATFORM_SPECIFIC_INIT - -void z_arm_platform_init(void) -{ -#ifndef CONFIG_NXP_IMX_RT6XX_BOOT_HEADER - /* - * If boot did not proceed using a boot header, we should not assume - * the core is in reset state. Disable the MPU and correctly - * set the stack pointer, since we are about to push to - * the stack when we call SystemInit - */ - /* Clear stack limit registers */ - __set_MSPLIM(0); - __set_PSPLIM(0); - /* Disable MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - /* Set stack pointer */ - __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); -#endif /* !CONFIG_NXP_IMX_RT5XX_BOOT_HEADER */ - /* This is provided by the SDK */ - SystemInit(); -} - -#endif - -SYS_INIT(nxp_rt600_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_kinetis/Kconfig b/soc/arm/nxp_kinetis/Kconfig deleted file mode 100644 index 251bc13ef914f0..00000000000000 --- a/soc/arm/nxp_kinetis/Kconfig +++ /dev/null @@ -1,168 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# Copyright (c) 2016, Freescale Semiconductor, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_KINETIS - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_KINETIS - -config SOC_FAMILY - string - default "nxp_kinetis" - -source "soc/arm/nxp_kinetis/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_KINETIS_K2X if SOC_SERIES_KINETIS_K2X - default SOC_PART_NUMBER_KINETIS_K6X if SOC_SERIES_KINETIS_K6X - default SOC_PART_NUMBER_KINETIS_K8X if SOC_SERIES_KINETIS_K8X - default SOC_PART_NUMBER_KINETIS_KWX if SOC_SERIES_KINETIS_KWX - default SOC_PART_NUMBER_KINETIS_KL2X if SOC_SERIES_KINETIS_KL2X - default SOC_PART_NUMBER_KINETIS_KE1XF if SOC_SERIES_KINETIS_KE1XF - default SOC_PART_NUMBER_KINETIS_KV5X if SOC_SERIES_KINETIS_KV5X - -config HAS_OSC - bool - help - Set if the oscillator (OSC) module is present in the SoC. - -config HAS_MCG - bool - help - Set if the multipurpose clock generator (MCG) module is present in the SoC. - -if HAS_OSC - -choice - prompt "Oscillator Mode Selection" - default OSC_EXTERNAL - -config OSC_EXTERNAL - bool "External reference clock" - help - Set this option to use the oscillator in external reference clock mode. - -config OSC_LOW_POWER - bool "Low power oscillator" - help - Set this option to use the oscillator in low-power mode. - -config OSC_HIGH_GAIN - bool "High gain oscillator" - help - Set this option to use the oscillator in high-gain mode. - -endchoice - -config OSC_XTAL0_FREQ - int "External oscillator frequency" - help - Set the external oscillator frequency in Hz. This should be set by the - board's defconfig. - -endif # HAS_OSC - -if HAS_MCG - -config MCG_PRDIV0 - hex "PLL external reference divider" - range 0 0x18 - default 0 - help - Selects the amount to divide down the external reference clock for the PLL. - The resulting frequency must be in the range of 2 MHz to 4 MHz. - -config MCG_VDIV0 - hex "VCO 0 divider" - range 0 0x1F - default 0 - help - Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits - establish the multiplication factor (M) applied to the reference clock - frequency. - -config MCG_FCRDIV - int "Fast internal reference clock divider" - range 0 7 - default 1 - help - Selects the amount to divide down the fast internal reference clock. The - resulting frequency must be in the range 31.25 kHz to 4 MHz. - -config MCG_FRDIV - int "FLL external reference divider" - range 0 7 - default 0 - help - Selects the amount to divide down the external reference clock for the - FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 - kHz. - -endif # HAS_MCG - -config KINETIS_FLASH_CONFIG - bool "Kinetis flash configuration field" - default y if XIP && !BOOTLOADER_MCUBOOT - help - Include the 16-byte flash configuration field that stores default - protection settings (loaded on reset) and security information that - allows the MCU to restrict access to the FTFx module. - -if KINETIS_FLASH_CONFIG - -config KINETIS_FLASH_CONFIG_OFFSET - hex "Kinetis flash configuration field offset" - default 0x400 - -config KINETIS_FLASH_CONFIG_FSEC - hex "Flash security byte (FSEC)" - range 0 0xff - default 0xfe - help - Configures the reset value of the FSEC register, which includes - backdoor key access, mass erase, factory access, and flash security - options. - -config KINETIS_FLASH_CONFIG_FOPT - hex "Flash nonvolatile option byte (FOPT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FOPT register, which includes boot, - NMI, and EzPort options. - -config KINETIS_FLASH_CONFIG_FEPROT - hex "EEPROM protection byte (FEPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FEPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -config KINETIS_FLASH_CONFIG_FDPROT - hex "Data flash protection byte (FDPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FDPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -endif # KINETIS_FLASH_CONFIG - -config WDOG_ENABLE_AT_BOOT - bool "Keep watchdog timer enabled at boot" - help - Leave SOC watchdog timer enabled at boot. The specific timeout - and clock configuration of the watchdog at boot is SOC dependent. - Note: if the watchdog timer is enabled at boot, the user will - need to configure the watchdog using z_arm_watchdog_init, as - the SOC requires watchdog configuration before initial expiration - -# Enable watchdog configuration function if watchdog is left enabled at boot -config WDOG_INIT - bool - default WDOG_ENABLE_AT_BOOT - -endif # SOC_FAMILY_KINETIS diff --git a/soc/arm/nxp_kinetis/Kconfig.defconfig b/soc/arm/nxp_kinetis/Kconfig.defconfig deleted file mode 100644 index 1a117657c0543d..00000000000000 --- a/soc/arm/nxp_kinetis/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL - -config ADC_INIT_PRIORITY - default 80 if ADC_MCUX_ADC16_ENABLE_EDMA - depends on ADC - -source "soc/arm/nxp_kinetis/*/Kconfig.defconfig.series" diff --git a/soc/arm/nxp_kinetis/Kconfig.soc b/soc/arm/nxp_kinetis/Kconfig.soc deleted file mode 100644 index 0a207260af311e..00000000000000 --- a/soc/arm/nxp_kinetis/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2016 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_kinetis/*/Kconfig.series" diff --git a/soc/arm/nxp_kinetis/k2x/CMakeLists.txt b/soc/arm/nxp_kinetis/k2x/CMakeLists.txt deleted file mode 100644 index 8ff38d089cea99..00000000000000 --- a/soc/arm/nxp_kinetis/k2x/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2018 Prevas A/S - -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - soc.c - ) - -if(DEFINED CONFIG_ARM_MPU AND DEFINED CONFIG_CPU_HAS_NXP_MPU) - # MK22F12 series MCUs have NXP MPU - zephyr_sources(nxp_mpu_regions.c) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22f12 b/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22f12 deleted file mode 100644 index 01f0ec78f2ffec..00000000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22f12 +++ /dev/null @@ -1,17 +0,0 @@ -# FSL FRDM K22F platform configuration options - -# Copyright (c) 2018 Prevas A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MK22F51212 - -config SOC - default "mk22f51212" - -config GPIO - default y - -config NUM_IRQS - default 74 - -endif # SOC_MK22F12 diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12 b/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12 deleted file mode 100644 index 963fdf87162ad5..00000000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk22fx12 +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2023 Daniel DeGrasse -# SPDX-License-Identifier: Apache-2.0 - -# Kinetis MK22FX12 configuration options - -if SOC_MK22F12 - -config SOC - default "mk22f12" - -config NUM_IRQS - default 81 - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -endif # SOC_MK22F12 diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.series deleted file mode 100644 index 254fd251014933..00000000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Kinetis K2x series configuration options - -# Copyright (c) 2018 Prevas A/S -# Copyright (c) 2019 Thomas Burdick - -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_KINETIS_K2X - -config SOC_SERIES - default "k2x" - -source "soc/arm/nxp_kinetis/k2x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_K2X diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.series b/soc/arm/nxp_kinetis/k2x/Kconfig.series deleted file mode 100644 index be22027b46a37c..00000000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Kinetis K2X MCU line - -# Copyright (c) 2018 Prevas A/S -# Copyright (c) 2019 Thomas Burdick - -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_KINETIS_K2X - bool "Kinetis K2x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis K2x MCU series diff --git a/soc/arm/nxp_kinetis/k2x/Kconfig.soc b/soc/arm/nxp_kinetis/k2x/Kconfig.soc deleted file mode 100644 index 0535ac2e684123..00000000000000 --- a/soc/arm/nxp_kinetis/k2x/Kconfig.soc +++ /dev/null @@ -1,69 +0,0 @@ -# Kinetis K2X MCU line - -# Copyright (c) 2018 Prevas A/S -# Copyright (c) 2019 Thomas Burdick - -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice - prompt "Kinetis K2x MCU Selection" - depends on SOC_SERIES_KINETIS_K2X - -config SOC_MK22F51212 - bool "SOC_MK22F51212" - select HAS_MCUX - select HAS_MCUX_SMC - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_DAC - select HAS_MCUX_RCM - -# Note- the MK22F12 SKU is a legacy SOC, no longer officially supported by -# NXP's MCUX SDK, and not recommended for new designs. -config SOC_MK22F12 - bool "SOC_MK22F12" - select HAS_MCUX - select HAS_MCUX_SMC - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_DAC - select HAS_MCUX_RCM - select CPU_HAS_NXP_MPU - -endchoice - -if SOC_SERIES_KINETIS_K2X - -config SOC_PART_NUMBER_MK22FN512VLH12 - bool - -config SOC_PART_NUMBER_MK22FX512AVLK12 - bool - -config SOC_PART_NUMBER_MK22FX512VLQ12 - bool - -config SOC_PART_NUMBER_KINETIS_K2X - string - default "MK22FN512VLH12" if SOC_PART_NUMBER_MK22FN512VLH12 - default "MK22FX512VLQ12" if SOC_PART_NUMBER_MK22FX512VLQ12 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_KINETIS_K2X diff --git a/soc/arm/nxp_kinetis/k6x/CMakeLists.txt b/soc/arm/nxp_kinetis/k6x/CMakeLists.txt deleted file mode 100644 index 8cf7a11f62e15a..00000000000000 --- a/soc/arm/nxp_kinetis/k6x/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - nxp_mpu_regions.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12 b/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12 deleted file mode 100644 index f8c2c7db12e69f..00000000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk64f12 +++ /dev/null @@ -1,21 +0,0 @@ -# FSL FRDM K64F platform configuration options - -# Copyright (c) 2014-2016 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MK64F12 - -config SOC - default "mk64f12" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 86 - -config GPIO - default y - -config SPI - default n - -endif # SOC_MK64F12 diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk66f18 b/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk66f18 deleted file mode 100644 index 3aa887880097be..00000000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk66f18 +++ /dev/null @@ -1,18 +0,0 @@ -# FSL SEGGER K66F platform configuration options - -# Copyright (c) 2020 DENX Software Engineering GmbH, 2021 Electromaticus LLC, 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MK66F18 - -config SOC - default "mk66f18" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 100 - -config GPIO - default y - -endif # SOC_MK66F18 diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.series deleted file mode 100644 index 4593295961c4fc..00000000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Kinetis K6x series configuration options - -# Copyright (c) 2014-2016 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_K6X - -config SOC_SERIES - default "k6x" - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -source "soc/arm/nxp_kinetis/k6x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_K6X diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.series b/soc/arm/nxp_kinetis/k6x/Kconfig.series deleted file mode 100644 index df24b5d600ede6..00000000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Kinetis K6X MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_K6X - bool "Kinetis K6x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_NXP_MPU - select HAS_MCUX_PIT - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis K6x MCU series diff --git a/soc/arm/nxp_kinetis/k6x/Kconfig.soc b/soc/arm/nxp_kinetis/k6x/Kconfig.soc deleted file mode 100644 index 42a0cb6891b666..00000000000000 --- a/soc/arm/nxp_kinetis/k6x/Kconfig.soc +++ /dev/null @@ -1,110 +0,0 @@ -# Kinetis K6X MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis K6x MCU Selection" - depends on SOC_SERIES_KINETIS_K6X - -config SOC_MK64F12 - bool "SOC_MK64F12" - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_ENET - select HAS_MCUX_FLEXCAN - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_RTC - select HAS_MCUX_DAC - select HAS_MCUX_EDMA - select HAS_MCUX_RCM - -config SOC_MK66F18 - bool "SOC_MK66F18" - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_ENET - select HAS_MCUX_FLEXCAN - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select CPU_HAS_FPU - select HAS_MCUX_RTC - select HAS_MCUX_DAC - select HAS_MCUX_EDMA - select HAS_MCUX_RCM - select HAS_MCUX_LPUART - -endchoice - -if SOC_SERIES_KINETIS_K6X - -config SOC_PART_NUMBER_MK64FN1M0CAJ12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VDC12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VLL12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VLQ12 - bool - -config SOC_PART_NUMBER_MK64FN1M0VMD12 - bool - -config SOC_PART_NUMBER_MK64FX512VDC12 - bool - -config SOC_PART_NUMBER_MK64FX512VLL12 - bool - -config SOC_PART_NUMBER_MK64FX512VLQ12 - bool - -config SOC_PART_NUMBER_MK64FX512VMD12 - bool - -config SOC_PART_NUMBER_MK66FN2M0VMD18 - bool - -config SOC_PART_NUMBER_MK66FN2M0VLQ18 - bool - -config SOC_PART_NUMBER_KINETIS_K6X - string - default "MK64FN1M0CAJ12" if SOC_PART_NUMBER_MK64FN1M0CAJ12 - default "MK64FN1M0VDC12" if SOC_PART_NUMBER_MK64FN1M0VDC12 - default "MK64FN1M0VLL12" if SOC_PART_NUMBER_MK64FN1M0VLL12 - default "MK64FN1M0VLQ12" if SOC_PART_NUMBER_MK64FN1M0VLQ12 - default "MK64FN1M0VMD12" if SOC_PART_NUMBER_MK64FN1M0VMD12 - default "MK64FX512VDC12" if SOC_PART_NUMBER_MK64FX512VDC12 - default "MK64FX512VLL12" if SOC_PART_NUMBER_MK64FX512VLL12 - default "MK64FX512VLQ12" if SOC_PART_NUMBER_MK64FX512VLQ12 - default "MK64FX512VMD12" if SOC_PART_NUMBER_MK64FX512VMD12 - default "MK66FN2M0VMD18" if SOC_PART_NUMBER_MK66FN2M0VMD18 - default "MK66FN2M0VLQ18" if SOC_PART_NUMBER_MK66FN2M0VLQ18 - - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config K6X_HSRUN - bool "High Speed RUN mode" - depends on SOC_MK66F18 - default y - help - This options enables support for High Speed RUN mode on K66F SoC. - -endif # SOC_SERIES_KINETIS_K6X diff --git a/soc/arm/nxp_kinetis/k8x/CMakeLists.txt b/soc/arm/nxp_kinetis/k8x/CMakeLists.txt deleted file mode 100644 index 8cf7a11f62e15a..00000000000000 --- a/soc/arm/nxp_kinetis/k8x/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - nxp_mpu_regions.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk80f25615 b/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk80f25615 deleted file mode 100644 index 4dfa011ce26916..00000000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk80f25615 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis K80F25615 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mk80f25615" - depends on SOC_MK80F25615 diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk82f25615 b/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk82f25615 deleted file mode 100644 index 4a7a81d73cb3ff..00000000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk82f25615 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis K82F25615 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mk82f25615" - depends on SOC_MK82F25615 diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.series deleted file mode 100644 index 3f300ac61dcda1..00000000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Kinetis K8x series configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_K8X - -config SOC_SERIES - default "k8x" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 106 - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -config KINETIS_FLASH_CONFIG_FOPT - default 0x3f - depends on KINETIS_FLASH_CONFIG - -config GPIO - default y - -source "soc/arm/nxp_kinetis/k8x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.series b/soc/arm/nxp_kinetis/k8x/Kconfig.series deleted file mode 100644 index 537a65bf1177be..00000000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Kinetis K8x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_K8X - bool "Kinetis K8x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_NXP_MPU - select CPU_HAS_FPU - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_LPUART - select HAS_MCUX_PIT - select HAS_MCUX_RTC - select HAS_MCUX_SIM - select HAS_MCUX_TRNG - select HAS_OSC - select HAS_MCG - select HAS_MCUX_EDMA - select HAS_MCUX_PIT - select HAS_MCUX_RCM - select HAS_MCUX_CACHE - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis K8x MCU series diff --git a/soc/arm/nxp_kinetis/k8x/Kconfig.soc b/soc/arm/nxp_kinetis/k8x/Kconfig.soc deleted file mode 100644 index b7127ad1bd4a60..00000000000000 --- a/soc/arm/nxp_kinetis/k8x/Kconfig.soc +++ /dev/null @@ -1,72 +0,0 @@ -# Kinetis K8x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis K8x MCU Selection" - depends on SOC_SERIES_KINETIS_K8X - -config SOC_MK80F25615 - bool "MK80F25615" - -config SOC_MK82F25615 - bool "MK82F25615" - -endchoice - -if SOC_SERIES_KINETIS_K8X - -config SOC_PART_NUMBER_MK80FN256VDC15 - bool - -config SOC_PART_NUMBER_MK80FN256VLL15 - bool - -config SOC_PART_NUMBER_MK82FN256VDC15 - bool - -config SOC_PART_NUMBER_MK82FN256VLL15 - bool - -config SOC_PART_NUMBER_KINETIS_K8X - string - default "MK80FN256VDC15" if SOC_PART_NUMBER_MK80FN256VDC15 - default "MK80FN256VLL15" if SOC_PART_NUMBER_MK80FN256VLL15 - default "MK82FN256VDC15" if SOC_PART_NUMBER_MK82FN256VDC15 - default "MK82FN256VLL15" if SOC_PART_NUMBER_MK82FN256VLL15 - help - This string holds the full part number of the SoC. It is a - hidden option that you should not set directly. The part - number selection choice defines the default value for this - string. - -config K8X_CORE_CLOCK_DIVIDER - int "Freescale K8x core clock divider" - default 1 - help - This option specifies the divide value for the K8x processor core clock - from the system clock. - -config K8X_BUS_CLOCK_DIVIDER - int "Freescale K8x bus clock divider" - default 2 - help - This option specifies the divide value for the K8x bus clock from the - system clock. - -config K8X_FLEXBUS_CLOCK_DIVIDER - int "Freescale K8x FlexBus clock divider" - default 2 - help - This option specifies the divide value for the K8x FlexBus clock from the - system clock. - -config K8X_FLASH_CLOCK_DIVIDER - int "Freescale K8x flash clock divider" - default 5 - help - This option specifies the divide value for the K8x flash clock from the - system clock. - -endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/arm/nxp_kinetis/ke1xf/CMakeLists.txt b/soc/arm/nxp_kinetis/ke1xf/CMakeLists.txt deleted file mode 100644 index ccbf2208d5a0fa..00000000000000 --- a/soc/arm/nxp_kinetis/ke1xf/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - nxp_mpu_regions.c - ) -zephyr_sources_ifdef( - CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke14f16 b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke14f16 deleted file mode 100644 index 801bfbf158a0c7..00000000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke14f16 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis KE14F16 configuration options - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mke14f16" - depends on SOC_MKE14F16 diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke16f16 b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke16f16 deleted file mode 100644 index 9c53760952b6a3..00000000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke16f16 +++ /dev/null @@ -1,11 +0,0 @@ -# Kinetis KE16F16 configuration options - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKE16F16 - -config SOC - default "mke16f16" - -endif # SOC_MKE16F16 diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke18f16 b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke18f16 deleted file mode 100644 index 555839e3586347..00000000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke18f16 +++ /dev/null @@ -1,11 +0,0 @@ -# Kinetis KE18F16 configuration options - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKE18F16 - -config SOC - default "mke18f16" - -endif # SOC_MKE18F16 diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.series deleted file mode 100644 index 28fb7e44b6841d..00000000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.series +++ /dev/null @@ -1,41 +0,0 @@ -# Kinetis KE1xF series configuration options - -# Copyright (c) 2019-2021 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KE1XF - -config SOC_SERIES - default "ke1xf" - -config MCUX_LPTMR_TIMER - default y if PM - -config CORTEX_M_SYSTICK - default n if MCUX_LPTMR_TIMER - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK - default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER - -config NUM_IRQS - # must be >= the highest interrupt number used - default 91 - -config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - default y - -config KINETIS_FLASH_CONFIG_FOPT - default 0x7d - depends on KINETIS_FLASH_CONFIG - -config PWM_MCUX_PWT - default y - depends on PWM_CAPTURE - -config GPIO - default y - -source "soc/arm/nxp_kinetis/ke1xf/Kconfig.defconfig.mke*" - -endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.series b/soc/arm/nxp_kinetis/ke1xf/Kconfig.series deleted file mode 100644 index 640bc4ec8fdf8b..00000000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.series +++ /dev/null @@ -1,37 +0,0 @@ -# Kinetis KE1xF series MCU - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KE1XF - bool "Kinetis KE1xF Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_NXP_MPU - select CPU_HAS_FPU - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_CACHE - select HAS_MCUX_FTFX - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_LPUART - select HAS_MCUX_PCC - select HAS_MCUX_RTC - select HAS_MCUX_SIM - select HAS_MCUX_ADC12 - select HAS_MCUX_SCG - select HAS_MCUX_WDOG32 - select HAS_MCUX_FTM - select HAS_MCUX_LPTMR - select HAS_MCUX_DAC32 - select HAS_MCUX_EDMA - select HAS_MCUX_ACMP - select HAS_MCUX_PWT - select HAS_MCUX_RCM - select PLATFORM_SPECIFIC_INIT - select HAS_PM - help - Enable support for Kinetis KE1xF MCU series diff --git a/soc/arm/nxp_kinetis/ke1xf/Kconfig.soc b/soc/arm/nxp_kinetis/ke1xf/Kconfig.soc deleted file mode 100644 index dec70f364f06af..00000000000000 --- a/soc/arm/nxp_kinetis/ke1xf/Kconfig.soc +++ /dev/null @@ -1,103 +0,0 @@ -# Kinetis KE1xF MCU line - -# Copyright (c) 2019 Vestas Wind Systems A/S -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KE1xF MCU Selection" - depends on SOC_SERIES_KINETIS_KE1XF - -config SOC_MKE14F16 - bool "MKE14F16" - -config SOC_MKE16F16 - bool "MKE16F16" - select HAS_MCUX_FLEXCAN - -config SOC_MKE18F16 - bool "MKE18F16" - select HAS_MCUX_FLEXCAN - -endchoice - -if SOC_SERIES_KINETIS_KE1XF - -config SOC_PART_NUMBER_MKE14F256VLH16 - bool - -config SOC_PART_NUMBER_MKE14F256VLL16 - bool - -config SOC_PART_NUMBER_MKE14F512VLH16 - bool - -config SOC_PART_NUMBER_MKE14F512VLL16 - bool - -config SOC_PART_NUMBER_MKE16F256VLH16 - bool - -config SOC_PART_NUMBER_MKE16F256VLL16 - bool - -config SOC_PART_NUMBER_MKE16F512VLH16 - bool - -config SOC_PART_NUMBER_MKE16F512VLL16 - bool - -config SOC_PART_NUMBER_MKE18F256VLH16 - bool - -config SOC_PART_NUMBER_MKE18F256VLL16 - bool - -config SOC_PART_NUMBER_MKE18F512VLH16 - bool - -config SOC_PART_NUMBER_MKE18F512VLL16 - bool - -config SOC_PART_NUMBER_KINETIS_KE1XF - string - default "MKE14F256VLH16" if SOC_PART_NUMBER_MKE14F256VLH16 - default "MKE14F256VLL16" if SOC_PART_NUMBER_MKE14F256VLL16 - default "MKE14F512VLH16" if SOC_PART_NUMBER_MKE14F512VLH16 - default "MKE14F512VLL16" if SOC_PART_NUMBER_MKE14F512VLL16 - default "MKE16F256VLH16" if SOC_PART_NUMBER_MKE16F256VLH16 - default "MKE16F256VLL16" if SOC_PART_NUMBER_MKE16F256VLL16 - default "MKE16F512VLH16" if SOC_PART_NUMBER_MKE16F512VLH16 - default "MKE16F512VLL16" if SOC_PART_NUMBER_MKE16F512VLL16 - default "MKE18F256VLH16" if SOC_PART_NUMBER_MKE18F256VLH16 - default "MKE18F256VLL16" if SOC_PART_NUMBER_MKE18F256VLL16 - default "MKE18F512VLH16" if SOC_PART_NUMBER_MKE18F512VLH16 - default "MKE18F512VLL16" if SOC_PART_NUMBER_MKE18F512VLL16 - help - This string holds the full part number of the SoC. It is a - hidden option that you should not set directly. The part - number selection choice defines the default value for this - string. - -config WDOG_ENABLE_AT_BOOT - bool "Keep watchdog timer enabled at boot" - help - Keep the watchdog timer enabled at boot with the internal - 128kHz LPO clock (and a prescaler of 256) as clock - source. The application can take over control of the - watchdog timer after boot and install a different timeout, - if needed. - -config WDOG_INITIAL_TIMEOUT - int "Initial timeout for the watchdog timer in milliseconds" - depends on WDOG_ENABLE_AT_BOOT && WDOG_INIT - range 2 131070 - default 2048 - help - Initial timeout value for the watchdog timer in - milliseconds. - -config KINETIS_KE1XF_ENABLE_CODE_CACHE - bool "Code cache" - default y - -endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/arm/nxp_kinetis/kl2x/CMakeLists.txt b/soc/arm/nxp_kinetis/kl2x/CMakeLists.txt deleted file mode 100644 index 268f065fb12d7f..00000000000000 --- a/soc/arm/nxp_kinetis/kl2x/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 b/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 deleted file mode 100644 index 25fb897a470cd2..00000000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mkl25z4 +++ /dev/null @@ -1,14 +0,0 @@ -# Kinetis KL2x SoC configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKL25Z4 - -config SOC - default "mkl25z4" - -config NUM_IRQS - default 32 - -endif # SOC_MKL25Z diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.series deleted file mode 100644 index d117f4bfb7ec79..00000000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Kinetis KL2x series configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KL2X - -config SOC_SERIES - default "kl2x" - -source "soc/arm/nxp_kinetis/kl2x/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_KL2X diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.series b/soc/arm/nxp_kinetis/kl2x/Kconfig.series deleted file mode 100644 index 3c606c7db272de..00000000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Kinetis KL2x MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KL2X - bool "Kinetis KL2x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select SOC_FAMILY_KINETIS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis KL2x MCU series diff --git a/soc/arm/nxp_kinetis/kl2x/Kconfig.soc b/soc/arm/nxp_kinetis/kl2x/Kconfig.soc deleted file mode 100644 index 66d6bce9c8f82e..00000000000000 --- a/soc/arm/nxp_kinetis/kl2x/Kconfig.soc +++ /dev/null @@ -1,81 +0,0 @@ -# Kinetis KL2x MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KL2x MCU Selection" - depends on SOC_SERIES_KINETIS_KL2X - -config SOC_MKL25Z4 - bool "SOC_MKL25Z4" - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_LPSCI - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -endchoice - -if SOC_SERIES_KINETIS_KL2X - -config SOC_PART_NUMBER_MKL25Z32VFM4 - bool - -config SOC_PART_NUMBER_MKL25Z64VFM4 - bool - -config SOC_PART_NUMBER_MKL25Z128VFM4 - bool - -config SOC_PART_NUMBER_MKL25Z32VFT4 - bool - -config SOC_PART_NUMBER_MKL25Z64VFT4 - bool - -config SOC_PART_NUMBER_MKL25Z128VFT4 - bool - -config SOC_PART_NUMBER_MKL25Z32VLH4 - bool - -config SOC_PART_NUMBER_MKL25Z64VLH4 - bool - -config SOC_PART_NUMBER_MKL25Z128VLH4 - bool - -config SOC_PART_NUMBER_MKL25Z32VLK4 - bool - -config SOC_PART_NUMBER_MKL25Z64VLK4 - bool - -config SOC_PART_NUMBER_MKL25Z128VLK4 - bool - -config SOC_PART_NUMBER_KINETIS_KL2X - string - default "MKL25Z32VFM4" if SOC_PART_NUMBER_MKL25Z32VFM4 - default "MKL25Z64VFM4" if SOC_PART_NUMBER_MKL25Z64VFM4 - default "MKL25Z128VFM4" if SOC_PART_NUMBER_MKL25Z128VFM4 - default "MKL25Z32VFT4" if SOC_PART_NUMBER_MKL25Z32VFT4 - default "MKL25Z64VFT4" if SOC_PART_NUMBER_MKL25Z64VFT4 - default "MKL25Z128VFT4" if SOC_PART_NUMBER_MKL25Z128VFT4 - default "MKL25Z32VLH4" if SOC_PART_NUMBER_MKL25Z32VLH4 - default "MKL25Z64VLH4" if SOC_PART_NUMBER_MKL25Z64VLH4 - default "MKL25Z128VLH4" if SOC_PART_NUMBER_MKL25Z128VLH4 - default "MKL25Z32VLK4" if SOC_PART_NUMBER_MKL25Z32VLK4 - default "MKL25Z64VLK4" if SOC_PART_NUMBER_MKL25Z64VLK4 - default "MKL25Z128VLK4" if SOC_PART_NUMBER_MKL25Z128VLK4 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_KINETIS_KL2X diff --git a/soc/arm/nxp_kinetis/kv5x/CMakeLists.txt b/soc/arm/nxp_kinetis/kv5x/CMakeLists.txt deleted file mode 100644 index 7424bb9f7b9bc8..00000000000000 --- a/soc/arm/nxp_kinetis/kv5x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24 b/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24 deleted file mode 100644 index 88ac4d75c588cd..00000000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv56f24 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis KV56F24 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mkv56f24" - depends on SOC_MKV56F24 diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24 b/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24 deleted file mode 100644 index 5f186f3cdef46b..00000000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv58f24 +++ /dev/null @@ -1,8 +0,0 @@ -# Kinetis KV58F24 configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "mkv58f24" - depends on SOC_MKV58F24 diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series deleted file mode 100644 index 4e9ba8ce5a308f..00000000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Kinetis KV5x series configuration options - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KV5X - -config SOC_SERIES - default "kv5x" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 121 - -config GPIO - default y - -source "soc/arm/nxp_kinetis/kv5x/Kconfig.defconfig.mkv*" - -endif # SOC_SERIES_KINETIS_KV5X diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.series b/soc/arm/nxp_kinetis/kv5x/Kconfig.series deleted file mode 100644 index 0df355a58236c8..00000000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Kinetis KV5x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KV5X - bool "Kinetis KV5x Series MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_KINETIS - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis KV5x MCU series diff --git a/soc/arm/nxp_kinetis/kv5x/Kconfig.soc b/soc/arm/nxp_kinetis/kv5x/Kconfig.soc deleted file mode 100644 index dd69ca523b0b41..00000000000000 --- a/soc/arm/nxp_kinetis/kv5x/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# Kinetis KV5x series MCU - -# Copyright (c) 2019 SEAL AG -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KV5x MCU Selection" - depends on SOC_SERIES_KINETIS_KV5X - -config SOC_MKV56F24 - bool "MKV56F24" - -config SOC_MKV58F24 - bool "MKV58F24" - -endchoice - -if SOC_SERIES_KINETIS_KV5X - -config SOC_PART_NUMBER_MKV56F512VLL24 - bool - -config SOC_PART_NUMBER_MKV56F512VLQ24 - bool - -config SOC_PART_NUMBER_MKV56F1M0VLL24 - bool - -config SOC_PART_NUMBER_MKV56F1M0VLQ24 - bool - -config SOC_PART_NUMBER_MKV58F512VLL24 - bool - -config SOC_PART_NUMBER_MKV58F512VLQ24 - bool - -config SOC_PART_NUMBER_MKV58F1M0VLL24 - bool - -config SOC_PART_NUMBER_MKV58F1M0VLQ24 - bool - -config SOC_PART_NUMBER_KINETIS_KV5X - string - default "MKV56F512VLL24" if SOC_PART_NUMBER_MKV56F512VLL24 - default "MKV56F512VLQ24" if SOC_PART_NUMBER_MKV56F512VLQ24 - default "MKV56F1M0VLL24" if SOC_PART_NUMBER_MKV56F1M0VLL24 - default "MKV56F1M0VLQ24" if SOC_PART_NUMBER_MKV56F1M0VLQ24 - default "MKV58F512VLL24" if SOC_PART_NUMBER_MKV58F512VLL24 - default "MKV58F512VLQ24" if SOC_PART_NUMBER_MKV58F512VLQ24 - default "MKV58F1M0VLL24" if SOC_PART_NUMBER_MKV58F1M0VLL24 - default "MKV58F1M0VLQ24" if SOC_PART_NUMBER_MKV58F1M0VLQ24 - help - This string holds the full part number of the SoC. It is a - hidden option that you should not set directly. The part - number selection choice defines the default value for this - string. - -endif # SOC_SERIES_KINETIS_KV5X diff --git a/soc/arm/nxp_kinetis/kwx/CMakeLists.txt b/soc/arm/nxp_kinetis/kwx/CMakeLists.txt deleted file mode 100644 index d414d72a63a4f5..00000000000000 --- a/soc/arm/nxp_kinetis/kwx/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_SOC_MKW24D5 soc_kw2xd.c) -zephyr_sources_ifdef(CONFIG_SOC_MKW22D5 soc_kw2xd.c) -zephyr_sources_ifdef(CONFIG_SOC_MKW41Z4 soc_kw4xz.c) -zephyr_sources_ifdef(CONFIG_SOC_MKW40Z4 soc_kw4xz.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw2xd512 b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw2xd512 deleted file mode 100644 index b497baf92915bb..00000000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw2xd512 +++ /dev/null @@ -1,22 +0,0 @@ -# Kinetis KW2xD SoC configuration options - -# Copyright (c) 2017, Phytec Messtechnik GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKW22D5 || SOC_MKW24D5 - -config SOC - default "mkw22d5" - depends on SOC_MKW22D5 - -config SOC - default "mkw24d5" - depends on SOC_MKW24D5 - -config NUM_IRQS - default 65 - -config SPI - default y - -endif # SOC_MKW2xD512 diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 deleted file mode 100644 index d865c6def0480b..00000000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw40z4 +++ /dev/null @@ -1,24 +0,0 @@ -# Kinetis KWx SoC configuration options - -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKW40Z4 - -config SOC - default "mkw40z4" - -config NUM_IRQS - default 32 - -choice CSPRNG_GENERATOR_CHOICE - default CTR_DRBG_CSPRNG_GENERATOR -endchoice - -choice RNG_GENERATOR_CHOICE - default XOSHIRO_RANDOM_GENERATOR -endchoice - -config TINYCRYPT - default y - -endif # SOC_MKW40Z4 diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 deleted file mode 100644 index c87b1a5b5b0f13..00000000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mkw41z4 +++ /dev/null @@ -1,42 +0,0 @@ -# Kinetis KWx SoC configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MKW41Z4 - -config SOC - default "mkw41z4" - -config NUM_IRQS - default 32 - -if NETWORKING - -config NET_L2_IEEE802154 - default y - depends on !NET_L2_OPENTHREAD - -endif # NETWORKING - -choice CSPRNG_GENERATOR_CHOICE - default CTR_DRBG_CSPRNG_GENERATOR -endchoice - -# -# MBEDTLS is larger but much faster than TinyCrypt so choose wisely -# -#config MBEDTLS -config TINYCRYPT - default y - depends on ENTROPY_GENERATOR - -# -# KW41Z TRNG entropy source cannot be used as a Hardware RNG source so -# use XOSHIRO for PRNG -# -choice RNG_GENERATOR_CHOICE - default XOSHIRO_RANDOM_GENERATOR -endchoice - -endif # SOC_MKW41Z4 diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.series b/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.series deleted file mode 100644 index e653088f70dfe4..00000000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Kinetis KWx series configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_KINETIS_KWX - -config SOC_SERIES - default "kwx" - -source "soc/arm/nxp_kinetis/kwx/Kconfig.defconfig.mk*" - -endif # SOC_SERIES_KINETIS_KWX diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.series b/soc/arm/nxp_kinetis/kwx/Kconfig.series deleted file mode 100644 index 36ba7b54c2199a..00000000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Kinetis KWx MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_KINETIS_KWX - bool "Kinetis KWx Series MCU" - select ARM - select SOC_FAMILY_KINETIS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CLOCK_CONTROL - select PLATFORM_SPECIFIC_INIT - help - Enable support for Kinetis KWx MCU series diff --git a/soc/arm/nxp_kinetis/kwx/Kconfig.soc b/soc/arm/nxp_kinetis/kwx/Kconfig.soc deleted file mode 100644 index 525637d7f1ed4d..00000000000000 --- a/soc/arm/nxp_kinetis/kwx/Kconfig.soc +++ /dev/null @@ -1,96 +0,0 @@ -# Kinetis KWx MCU series - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Kinetis KWx MCU Selection" - depends on SOC_SERIES_KINETIS_KWX - -config SOC_MKW22D5 - bool "SOC_MKW22D5" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -config SOC_MKW24D5 - bool "SOC_MKW24D5" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_FTM - select HAS_MCUX_RNGA - select HAS_MCUX_SIM - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -config SOC_MKW40Z4 - bool "SOC_MKW40Z4" - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_LPUART - select HAS_MCUX_SIM - select HAS_MCUX_TRNG - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -config SOC_MKW41Z4 - bool "SOC_MKW41Z4" - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_ADC16 - select HAS_MCUX_FTFX - select HAS_MCUX_LPUART - select HAS_MCUX_RTC - select HAS_MCUX_SIM - select HAS_MCUX_TPM - select HAS_MCUX_TRNG - select HAS_OSC - select HAS_MCG - select HAS_MCUX_RCM - -endchoice - -if SOC_SERIES_KINETIS_KWX - -config SOC_PART_NUMBER_MKW22D512VHA5 - bool - -config SOC_PART_NUMBER_MKW24D512VHA5 - bool - -config SOC_PART_NUMBER_MKW40Z160VHT4 - bool - -config SOC_PART_NUMBER_MKW41Z256VHT4 - bool - -config SOC_PART_NUMBER_MKW41Z512VHT4 - bool - -config SOC_PART_NUMBER_KINETIS_KWX - string - default "MKW22D512VHA5" if SOC_PART_NUMBER_MKW22D512VHA5 - default "MKW24D512VHA5" if SOC_PART_NUMBER_MKW24D512VHA5 - default "MKW40Z160VHT4" if SOC_PART_NUMBER_MKW40Z160VHT4 - default "MKW41Z256VHT4" if SOC_PART_NUMBER_MKW41Z256VHT4 - default "MKW41Z512VHT4" if SOC_PART_NUMBER_MKW41Z512VHT4 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_SERIES_KINETIS_KWX diff --git a/soc/arm/nxp_lpc/Kconfig b/soc/arm/nxp_lpc/Kconfig deleted file mode 100644 index 45d31a8c6c0daf..00000000000000 --- a/soc/arm/nxp_lpc/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_LPC - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_LPC - -config SOC_FAMILY - string - default "nxp_lpc" - -source "soc/arm/nxp_lpc/*/Kconfig.soc" - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_LPC54XXX if SOC_SERIES_LPC54XXX - default SOC_PART_NUMBER_LPC55XXX if SOC_SERIES_LPC55XXX - default SOC_PART_NUMBER_LPC11U6X if SOC_SERIES_LPC11U6X - default SOC_PART_NUMBER_LPC51U68 if SOC_SERIES_LPC51U68 - -endif # SOC_FAMILY_LPC diff --git a/soc/arm/nxp_lpc/Kconfig.defconfig b/soc/arm/nxp_lpc/Kconfig.defconfig deleted file mode 100644 index cf1250bfa84e89..00000000000000 --- a/soc/arm/nxp_lpc/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_lpc/*/Kconfig.defconfig.series" - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL diff --git a/soc/arm/nxp_lpc/Kconfig.soc b/soc/arm/nxp_lpc/Kconfig.soc deleted file mode 100644 index 5538bbfd297af7..00000000000000 --- a/soc/arm/nxp_lpc/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_lpc/*/Kconfig.series" diff --git a/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt b/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt deleted file mode 100644 index e9a04818a9376a..00000000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u66 b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u66 deleted file mode 100644 index 92f023fffb23ca..00000000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u66 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC11U66 platform configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC11U66 - -config SOC - default "lpc11u66" - -endif # SOC_LPC11U66 diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u67 b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u67 deleted file mode 100644 index 08f6c9438f8407..00000000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u67 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC11U67 platform configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC11U67 - -config SOC - default "lpc11u67" - -endif # SOC_LPC11U67 diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u68 b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u68 deleted file mode 100644 index 010402e73a3874..00000000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lpc11u68 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC11U68 platform configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC11U68 - -config SOC - default "lpc11u68" - -endif # SOC_LPC11U68 diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.series deleted file mode 100644 index 0845fedf612027..00000000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# LPC11U6X series configuration options - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC11U6X - -source "soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.lp*" - -config SOC_SERIES - default "lpc11u6x" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 40 - -endif # SOC_SERIES_LPC11U6X diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.series b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.series deleted file mode 100644 index 5eb64a392ec32a..00000000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# LPC LPC11U6X MCU line - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC11U6X - bool "LPC LPC11U6X Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select SOC_FAMILY_LPC - select PINCTRL - select CLOCK_CONTROL - help - Enable support for LPC LPC11U6X MCU series diff --git a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.soc b/soc/arm/nxp_lpc/lpc11u6x/Kconfig.soc deleted file mode 100644 index 9dd0ad19c1fd25..00000000000000 --- a/soc/arm/nxp_lpc/lpc11u6x/Kconfig.soc +++ /dev/null @@ -1,52 +0,0 @@ -# LPC LPC11U6x MCU line - -# Copyright (c) 2020, Seagate -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "LPC LPC11U6X MCU Selection" - depends on SOC_SERIES_LPC11U6X - -config SOC_LPC11U68 - bool "SOC_LPC11U68" - -config SOC_LPC11U67 - bool "SOC_LPC11U67" - -config SOC_LPC11U66 - bool "SOC_LPC11U66" - -endchoice - -if SOC_SERIES_LPC11U6X - -config SOC_PART_NUMBER_LPC11U66JBD48 - bool -config SOC_PART_NUMBER_LPC11U67JBD48 - bool -config SOC_PART_NUMBER_LPC11U67JBD64 - bool -config SOC_PART_NUMBER_LPC11U67JBD100 - bool -config SOC_PART_NUMBER_LPC11U68JBD48 - bool -config SOC_PART_NUMBER_LPC11U68JBD64 - bool -config SOC_PART_NUMBER_LPC11U68JBD100 - bool - -config SOC_PART_NUMBER_LPC11U6X - string - default "LPC11U66JBD48" if SOC_PART_NUMBER_LPC11U66JBD48 - default "LPC11U67JBD48" if SOC_PART_NUMBER_LPC11U67JBD48 - default "LPC11U67JBD64" if SOC_PART_NUMBER_LPC11U67JBD64 - default "LPC11U67JBD100" if SOC_PART_NUMBER_LPC11U67JBD100 - default "LPC11U68JBD48" if SOC_PART_NUMBER_LPC11U68JBD48 - default "LPC11U68JBD64" if SOC_PART_NUMBER_LPC11U68JBD64 - default "LPC11U68JBD100" if SOC_PART_NUMBER_LPC11U68JBD100 - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. -endif # SOC_SERIES_LPC11U6X diff --git a/soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt b/soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt deleted file mode 100644 index a0b6a030303270..00000000000000 --- a/soc/arm/nxp_lpc/lpc51u68/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# -# Copyright (c) 2021 metraTec GmbH -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_library() - -zephyr_library_sources(soc.c) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc51u68/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc51u68/Kconfig.defconfig.series deleted file mode 100644 index fb2e30d3a6ed63..00000000000000 --- a/soc/arm/nxp_lpc/lpc51u68/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# LPC51U68 series configuration options - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC51U68 - -config SOC_SERIES - default "lpc51u68" - -config NUM_IRQS - # must be >= the highest interrupt number used. - default 32 - -config SOC - default "lpc51u68" - -config SOC_FLASH_LPC - default y - depends on FLASH - -endif diff --git a/soc/arm/nxp_lpc/lpc51u68/Kconfig.series b/soc/arm/nxp_lpc/lpc51u68/Kconfig.series deleted file mode 100644 index 8b1a9dd18b1863..00000000000000 --- a/soc/arm/nxp_lpc/lpc51u68/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# LPC LPC51U68 Series - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC51U68 - bool "LPC LPC51U68 Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select HAS_MCUX - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_SYSCON - select HAS_MCUX_SCTIMER - select SOC_FAMILY_LPC - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select PLATFORM_SPECIFIC_INIT - help - Enable support for LPC LPC51U68 MCU Series diff --git a/soc/arm/nxp_lpc/lpc51u68/Kconfig.soc b/soc/arm/nxp_lpc/lpc51u68/Kconfig.soc deleted file mode 100644 index e6290615c2c00d..00000000000000 --- a/soc/arm/nxp_lpc/lpc51u68/Kconfig.soc +++ /dev/null @@ -1,27 +0,0 @@ -# LPC LPC51U68 MCU line - -# Copyright (c) 2021 metraTec GmbH -# SPDX-License Identifier: Apache-2.0 - -config SOC_LPC51U68 - bool "SOC_LPC51U68" - depends on SOC_SERIES_LPC51U68 - select CLOCK_CONTROL - -if SOC_SERIES_LPC51U68 - -config SOC_PART_NUMBER_LPC51U68JBD48 - bool -config SOC_PART_NUMBER_LPC51U68JBD64 - bool - -config SOC_PART_NUMBER_LPC51U68 - string - default "LPC51U68JBD48" if SOC_PART_NUMBER_LPC51U68JBD48 - default "LPC51U68JBD64" if SOC_PART_NUMBER_LPC51U68JBD64 - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -endif # SOC_SERIES_LPC51U68 diff --git a/soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt b/soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt deleted file mode 100644 index fda5d9532e8fc5..00000000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -# -# Copyright (c) 2017, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_library() - -zephyr_library_sources(soc.c) -zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT gcc/startup_LPC54114_cm4.S) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) - - -# CMSIS SystemInit allows us to skip enabling clock to SRAM2 bank via -# this compiler definition -if(NOT DEFINED CONFIG_LPC54XXX_SRAM2_CLOCK) -zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0 b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0 deleted file mode 100644 index fc46266c3a8c86..00000000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m0 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP LPC54114 M0 platform configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC54114_M0 - -config SOC - default "lpc54114_m0" - -config GPIO - default n - -endif # SOC_LPC54114_M0 diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m4 b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m4 deleted file mode 100644 index 703ed8a6cf0155..00000000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lpc54114_m4 +++ /dev/null @@ -1,11 +0,0 @@ -# NXP LPC54114 platform configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC54114_M4 - -config SOC - default "lpc54114" - -endif # SOC_LPC54114_M4 diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.series deleted file mode 100644 index f719b183f7620d..00000000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# LPC54XXX series configuration options - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC54XXX - -config SOC_SERIES - default "lpc54xxx" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 40 - -source "soc/arm/nxp_lpc/lpc54xxx/Kconfig.defconfig.lp*" - -endif # SOC_SERIES_LPC54XXX diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.series b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.series deleted file mode 100644 index eece2a1293f99a..00000000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# LPC LPC54XXX MCU line - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC54XXX - bool "LPC LPC54xxx Series MCU" - select ARM - select HAS_MCUX - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_SYSCON - select SOC_FAMILY_LPC - select CPU_CORTEX_M_HAS_SYSTICK - select PLATFORM_SPECIFIC_INIT - help - Enable support for LPC LPC54XXX MCU series diff --git a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc b/soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc deleted file mode 100644 index e71bc8f451e46e..00000000000000 --- a/soc/arm/nxp_lpc/lpc54xxx/Kconfig.soc +++ /dev/null @@ -1,78 +0,0 @@ -# LPC LPC54XXX MCU line - -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "LPC LPC54XXX MCU Selection" - depends on SOC_SERIES_LPC54XXX - -config SOC_LPC54114_M4 - bool "SOC_LPC54114_M4" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select PLATFORM_SPECIFIC_INIT - select CLOCK_CONTROL - select HAS_MCUX_IAP_LEGACY - -config SOC_LPC54114_M0 - bool "SOC_LPC54114_M0" - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select CLOCK_CONTROL - -endchoice - -if SOC_SERIES_LPC54XXX - -config SOC_PART_NUMBER_LPC54114J256BD64 - bool - -config SOC_PART_NUMBER_LPC54XXX - string - default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64 - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -config SECOND_CORE_MCUX - bool "LPC54114 Cortex-M0 second core" - depends on HAS_MCUX - help - Driver for second core startup - -config SECOND_CORE_BOOT_ADDRESS_MCUX - depends on SECOND_CORE_MCUX - hex "Address the second core will boot at" - default 0x20010000 - help - This is the address the second core will boot from. Additionally this - address is where we will copy the SECOND_IMAGE to. We default this to - the base of SRAM1. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition - -# Move the LMA address of second core into flash -config BUILD_OUTPUT_ADJUST_LMA - depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 - default "-0x20010000+\ - $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))" - -config BUILD_OUTPUT_INFO_HEADER - default y - depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 - -config LPC54XXX_SRAM2_CLOCK - bool "Clock LPC54XXX SRAM2" - default y - help - SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit - will enable the clock to this RAM bank. Disable this Kconfig to leave - this ram bank untouched out of reset. - -endif # SOC_SERIES_LPC54XXX diff --git a/soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt b/soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt deleted file mode 100644 index fb58ca649f232a..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (c) 2019, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# -zephyr_library() - -zephyr_library_sources(soc.c) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/${ARCH}/include - ) -if(DEFINED CONFIG_LPC55XXX_USB_RAM) -zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER - SECTIONS usb.ld) - -zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) -endif() - -# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via -# this compiler definition -if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS) -zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S06 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S06 deleted file mode 100644 index 94f479b9b9fabe..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S06 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP LPC55S06 platform configuration options - -# Copyright (c) 2022 metraTec -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S06 - -config SOC - default "lpc55S06" - -config LPC55XXX_USB_RAM - default n - -endif # SOC_LPC55S06 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 deleted file mode 100644 index 4f93fffb5864d0..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S16 +++ /dev/null @@ -1,19 +0,0 @@ -# NXP LPC55S16 platform configuration options - -# Copyright (c) 2020 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S16 - -config SOC - default "lpc55S16" - -config CAN_MCUX_MCAN - default y - depends on CAN - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -endif # SOC_LPC55S16 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S28 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S28 deleted file mode 100644 index 4dd2f605dd609e..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S28 +++ /dev/null @@ -1,15 +0,0 @@ -# NXP LPC55S28 platform configuration options - -# Copyright (c) 2020 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S28 - -config SOC - default "lpc55S28" - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -endif # SOC_LPC55S28 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S36 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S36 deleted file mode 100644 index a83bdf55313279..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S36 +++ /dev/null @@ -1,18 +0,0 @@ -# NXP LPC55S36 platform configuration options - -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S36 - -config SOC - default "lpc55S36" - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -config LPC55XXX_USB_RAM - default n - -endif # SOC_LPC55S36 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0 deleted file mode 100644 index 4963ad86a75f96..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu0 +++ /dev/null @@ -1,23 +0,0 @@ -# NXP LPC55XXX CPU0 platform configuration options - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S69_CPU0 - -config SOC - default "lpc55S69_cpu0" - -config SOC_FLASH_MCUX - default y - depends on FLASH - depends on !TRUSTED_EXECUTION_NONSECURE - -choice USB_MCUX_CONTROLLER_TYPE - default USB_DC_NXP_LPCIP3511 -endchoice - -config I2S_MCUX_FLEXCOMM - select INIT_PLL0 - -endif # SOC_LPC55S69_CPU0 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1 b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1 deleted file mode 100644 index c061c7b83d838f..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lpc55S69_cpu1 +++ /dev/null @@ -1,17 +0,0 @@ -# NXP LPC55S69 CPU1 platform configuration options - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LPC55S69_CPU1 - -config SOC - default "lpc55S69_cpu1" - -config GPIO - default y - -config SERIAL - default n - -endif # SOC_LPC55S69_CPU1 diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series deleted file mode 100644 index 05a0f086b95a52..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# LPC55XXX series configuration options - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_LPC55XXX - -config SOC_SERIES - default "lpc55xxx" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 60 - -source "soc/arm/nxp_lpc/lpc55xxx/Kconfig.defconfig.lp*" - -endif # SOC_SERIES_LPC55XXX diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.series b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.series deleted file mode 100644 index 733bf9ecc34bf5..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# LPC LPC55XXX Series - -# Copyright (c) 2019, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_LPC55XXX - bool "LPC5500 Series Family MCU" - select ARM - select HAS_MCUX - select HAS_MCUX_FLEXCOMM - select HAS_MCUX_SYSCON - select HAS_MCUX_WWDT - select SOC_FAMILY_LPC - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_DWT - select PLATFORM_SPECIFIC_INIT - help - Enable support for LPC5500 Series MCU series diff --git a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc b/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc deleted file mode 100644 index c8c3cae3c49628..00000000000000 --- a/soc/arm/nxp_lpc/lpc55xxx/Kconfig.soc +++ /dev/null @@ -1,177 +0,0 @@ -# LPC LPC55XXX Series - -# Copyright 2019, 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "LPC5500 Series MCU Selection" - depends on SOC_SERIES_LPC55XXX - -config SOC_LPC55S06 - bool "SOC_LPC55S06 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE - select HAS_MCUX_RNG - -config SOC_LPC55S16 - bool "SOC_LPC55S16 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE - select HAS_MCUX_MCAN - select HAS_MCUX_RNG - -config SOC_LPC55S28 - bool "SOC_LPC55S28 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CLOCK_CONTROL - select HAS_MCUX_IAP - select HAS_MCUX_LPADC - select HAS_MCUX_LPC_DMA - select HAS_MCUX_RNG - -config SOC_LPC55S36 - bool "SOC_LPC55S36 M33" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_MCAN - select HAS_MCUX_PWM - -config SOC_LPC55S69_CPU0 - bool "SOC_LPC55S69 M33 [CPU 0]" - select CPU_CORTEX_M33 - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CLOCK_CONTROL - select HAS_MCUX_IAP - select HAS_MCUX_LPADC - select HAS_MCUX_LPC_DMA - select HAS_MCUX_USB_LPCIP3511 - select HAS_MCUX_CTIMER - select HAS_MCUX_SCTIMER - select HAS_MCUX_RNG - -config SOC_LPC55S69_CPU1 - bool "SOC_LPC55S69 M33 [CPU 1]" - select CPU_CORTEX_M33 - -endchoice - -if SOC_SERIES_LPC55XXX - -config SOC_PART_NUMBER_LPC55S06JBD64 - bool - -config SOC_PART_NUMBER_LPC55S16JBD64 - bool - -config SOC_PART_NUMBER_LPC55S16JBD100 - bool - -config SOC_PART_NUMBER_LPC55S28JBD100 - bool - -config SOC_PART_NUMBER_LPC55S36JBD100 - bool - -config SOC_PART_NUMBER_LPC55S69JBD100 - bool - -config SOC_PART_NUMBER_LPC55S69JET98 - bool - -config SOC_PART_NUMBER_LPC55XXX - string - default "LPC55S06JBD64" if SOC_PART_NUMBER_LPC55S06JBD64 - default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64 - default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100 - default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100 - default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100 - default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100 - default "LPC55S69JET98" if SOC_PART_NUMBER_LPC55S69JET98 - - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -config INIT_PLL0 - bool "Initialize PLL0" - -config INIT_PLL1 - bool "Initialize PLL1" - default "y" - depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM) - help - In the LPC55XXX Family, this is currently being used to set the - core clock value at it's highest frequency which clocks at 150MHz. - Note that flash programming operations are limited to 100MHz, and - this PLL should not be used as the core clock in those cases. - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 144000000 if INIT_PLL1 - default 96000000 - -config SECOND_CORE_MCUX - bool "LPC55xxx's second core" - depends on HAS_MCUX - help - Indicates the second core will be enabled, and the part will run - in dual core mode. - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition - -config SECOND_CORE_BOOT_ADDRESS_MCUX - depends on SECOND_CORE_MCUX - hex "Address the second core will boot at" - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION)) - help - This is the address the second core will boot from. - -# Move the LMA for the second core image to be in the flash region of primary -# core, so that JLink flash will load it correctly. -config BUILD_OUTPUT_ADJUST_LMA - depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1 - default "0x10000000" - -config LPC55XXX_SRAM_CLOCKS - bool "CLock LPC SRAM banks" - default y - help - SRAM controllers 1,2,3, and 4 are disabled at reset. - By default, CMSIS SystemInit will enable the clock to these RAM banks. - Disable this Kconfig to leave the ram banks untouched out of reset. - -config LPC55XXX_USB_RAM - bool - default y - help - Some SoC's in the LPC5500 Series do have a dedicated USB RAM. - By default, USB RAM is assumed to be present. - Disable this Kconfig in case there is no dedicated USB RAM. - -endif # SOC_SERIES_LPC55XXX diff --git a/soc/arm/nxp_s32/Kconfig b/soc/arm/nxp_s32/Kconfig deleted file mode 100644 index d014315e4d70b1..00000000000000 --- a/soc/arm/nxp_s32/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NXP_S32 - bool - -if SOC_FAMILY_NXP_S32 - -config SOC_FAMILY - string - default "nxp_s32" - -config NXP_S32_FUNC_RESET_THRESHOLD - int "Functional Reset Escalation threshold" - default 15 - range 0 15 - help - If the value of this option is 0, the Functional reset escalation - function is disabled. Any other value is the number of Functional - resets that causes a Destructive reset, if the FRET register isn't - written to beforehand. - Default to maximum threshold (hardware reset value). - -config NXP_S32_DEST_RESET_THRESHOLD - int "Destructive Reset Escalation threshold" - default 0 - range 0 15 - help - If the value of this field is 0, the Destructive reset escalation - function is disabled. Any other value is the number of Destructive - resets which keeps the chip in the reset state until the next power-on - reset triggers a new reset sequence, if the DRET register isn't - written to beforehand. - Default to disabled (hardware reset value). - -source "soc/arm/nxp_s32/*/Kconfig.soc" - -endif # SOC_FAMILY_NXP_S32 diff --git a/soc/arm/nxp_s32/Kconfig.defconfig b/soc/arm/nxp_s32/Kconfig.defconfig deleted file mode 100644 index 49c9a142934a67..00000000000000 --- a/soc/arm/nxp_s32/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_s32/*/Kconfig.defconfig.series" diff --git a/soc/arm/nxp_s32/Kconfig.soc b/soc/arm/nxp_s32/Kconfig.soc deleted file mode 100644 index 85c8414b5ee037..00000000000000 --- a/soc/arm/nxp_s32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/nxp_s32/*/Kconfig.series" diff --git a/soc/arm/nxp_s32/common/CMakeLists.txt b/soc/arm/nxp_s32/common/CMakeLists.txt deleted file mode 100644 index 6142be7ab642d9..00000000000000 --- a/soc/arm/nxp_s32/common/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources(osif.c) -zephyr_sources_ifdef(CONFIG_SOC_SERIES_S32K3XX power_soc.c) diff --git a/soc/arm/nxp_s32/s32k1/CMakeLists.txt b/soc/arm/nxp_s32/s32k1/CMakeLists.txt deleted file mode 100644 index ff8085fc5c1cc8..00000000000000 --- a/soc/arm/nxp_s32/s32k1/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") - -zephyr_sources(soc.c) -zephyr_sources_ifdef(CONFIG_ARM_MPU nxp_mpu_regions.c) - -zephyr_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG flash_configuration.c) -zephyr_linker_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG ROM_START SORT_KEY 0x1 flash_config.ld) diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k146 b/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k146 deleted file mode 100644 index 522710112dcac0..00000000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k146 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP S32K146 - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_S32K146 - -config SOC - default "s32k146" - -config FPU - default y - -endif # SOC_S32K146 diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.series deleted file mode 100644 index 49dfd9f31cf04a..00000000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# NXP S32K1XX MCU series - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_S32K1XX - -config SOC_SERIES - default "s32k1" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 80000000 - -config NUM_IRQS - default 239 if CPU_CORTEX_M4 - default 47 if CPU_CORTEX_M0PLUS - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -# The S32K1xx have 8 MPU regions, which is not enough for both HW stack protection -# and userspace. Only enable HW stack protection if userspace is not enabled. -config HW_STACK_PROTECTION - default y if !USERSPACE - -source "soc/arm/nxp_s32/s32k1/Kconfig.defconfig.s32k1*" - -endif # SOC_SERIES_S32K1XX diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.series b/soc/arm/nxp_s32/s32k1/Kconfig.series deleted file mode 100644 index 31102f347fdf1e..00000000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# NXP S32K1XX MCU series - -# Copyright 2023-2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_S32K1XX - bool "NXP S32K1XX MCU series" - select ARM - select SOC_FAMILY_NXP_S32 - select HAS_NXP_S32_HAL - select HAS_MCUX - select CPU_HAS_NXP_MPU - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select MPU_ALLOW_FLASH_WRITE if !XIP - select CLOCK_CONTROL - select HAS_MCUX_LPUART - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_FTM - select HAS_MCUX_FLEXCAN - select HAS_MCUX_WDOG32 - select HAS_MCUX_RTC - help - Enable support for NXP S32K1XX MCU series. diff --git a/soc/arm/nxp_s32/s32k1/Kconfig.soc b/soc/arm/nxp_s32/s32k1/Kconfig.soc deleted file mode 100644 index 78caf49f677fb9..00000000000000 --- a/soc/arm/nxp_s32/s32k1/Kconfig.soc +++ /dev/null @@ -1,445 +0,0 @@ -# NXP S32K1XX MCUs line - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP S32K1XX MCU selection" - depends on SOC_SERIES_S32K1XX - -config SOC_S32K116 - bool "S32K116" - select CPU_CORTEX_M0PLUS - -config SOC_S32K118 - bool "S32K118" - select CPU_CORTEX_M0PLUS - -config SOC_S32K142 - bool "S32K142" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K142W - bool "S32K142W" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K144 - bool "S32K144" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K144W - bool "S32K144W" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K146 - bool "S32K146" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -config SOC_S32K148 - bool "S32K148" - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select HAS_MCUX_CACHE - -endchoice - -if SOC_SERIES_S32K1XX - -config SOC_PART_NUMBER_FS32K116LAT0MFMT - bool - -config SOC_PART_NUMBER_FS32K116LAT0MLFR - bool - -config SOC_PART_NUMBER_FS32K116LAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K116LIT0VFMT - bool - -config SOC_PART_NUMBER_FS32K116LIT0VLFT - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLFR - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLHR - bool - -config SOC_PART_NUMBER_FS32K118LAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K118LIT0VLFT - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K142HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K142HVT0VLHT - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLFT - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLHR - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLHT - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLLR - bool - -config SOC_PART_NUMBER_FS32K142UAT0VLLT - bool - -config SOC_PART_NUMBER_FS32K142UIT0VLHT - bool - -config SOC_PART_NUMBER_FS32K142WAT0WLFT - bool - -config SOC_PART_NUMBER_FS32K142WAT0WLHT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLFT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLHR - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K144HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K144HAT0MMHR - bool - -config SOC_PART_NUMBER_FS32K144HAT0MMHT - bool - -config SOC_PART_NUMBER_FS32K144HVT0VLHR - bool - -config SOC_PART_NUMBER_FS32K144HVT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144HXT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144HXT0VLLT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLFT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLHR - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VLLT - bool - -config SOC_PART_NUMBER_FS32K144UAT0VMHR - bool - -config SOC_PART_NUMBER_FS32K144UAT0VMHT - bool - -config SOC_PART_NUMBER_FS32K144UIT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144ULT0VLHT - bool - -config SOC_PART_NUMBER_FS32K144ULT0VLLR - bool - -config SOC_PART_NUMBER_FS32K144ULT0VLLT - bool - -config SOC_PART_NUMBER_FS32K144WAT0WLFT - bool - -config SOC_PART_NUMBER_FS32K144WAT0WLHT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLHR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLHT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLQR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MLQT - bool - -config SOC_PART_NUMBER_FS32K146HAT0MMHR - bool - -config SOC_PART_NUMBER_FS32K146HAT0MMHT - bool - -config SOC_PART_NUMBER_FS32K146HVT0VLHT - bool - -config SOC_PART_NUMBER_FS32K146HXT0VLLT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLHR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLHT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLLR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLLT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLQR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VLQT - bool - -config SOC_PART_NUMBER_FS32K146UAT0VMHR - bool - -config SOC_PART_NUMBER_FS32K146UAT0VMHT - bool - -config SOC_PART_NUMBER_FS32K146UIT0VLLT - bool - -config SOC_PART_NUMBER_FS32K146ULT0VLLT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLLR - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLLT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLQR - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLQT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MLUT - bool - -config SOC_PART_NUMBER_FS32K148HAT0MMHT - bool - -config SOC_PART_NUMBER_FS32K148UGT0VLQT - bool - -config SOC_PART_NUMBER_FS32K148UIT0VLQT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VLLT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VLQT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VLUT - bool - -config SOC_PART_NUMBER_FS32K148UJT0VMHR - bool - -config SOC_PART_NUMBER_FS32K148UJT0VMHT - bool - -config SOC_PART_NUMBER_S32K1XX - string - default "FS32K116LAT0MFMT" if SOC_PART_NUMBER_FS32K116LAT0MFMT - default "FS32K116LAT0MLFR" if SOC_PART_NUMBER_FS32K116LAT0MLFR - default "FS32K116LAT0MLFT" if SOC_PART_NUMBER_FS32K116LAT0MLFT - default "FS32K116LIT0VFMT" if SOC_PART_NUMBER_FS32K116LIT0VFMT - default "FS32K116LIT0VLFT" if SOC_PART_NUMBER_FS32K116LIT0VLFT - default "FS32K118LAT0MLFR" if SOC_PART_NUMBER_FS32K118LAT0MLFR - default "FS32K118LAT0MLFT" if SOC_PART_NUMBER_FS32K118LAT0MLFT - default "FS32K118LAT0MLHR" if SOC_PART_NUMBER_FS32K118LAT0MLHR - default "FS32K118LAT0MLHT" if SOC_PART_NUMBER_FS32K118LAT0MLHT - default "FS32K118LIT0VLFT" if SOC_PART_NUMBER_FS32K118LIT0VLFT - default "FS32K142HAT0MLFT" if SOC_PART_NUMBER_FS32K142HAT0MLFT - default "FS32K142HAT0MLHT" if SOC_PART_NUMBER_FS32K142HAT0MLHT - default "FS32K142HAT0MLLR" if SOC_PART_NUMBER_FS32K142HAT0MLLR - default "FS32K142HAT0MLLT" if SOC_PART_NUMBER_FS32K142HAT0MLLT - default "FS32K142HVT0VLHT" if SOC_PART_NUMBER_FS32K142HVT0VLHT - default "FS32K142UAT0VLFT" if SOC_PART_NUMBER_FS32K142UAT0VLFT - default "FS32K142UAT0VLHR" if SOC_PART_NUMBER_FS32K142UAT0VLHR - default "FS32K142UAT0VLHT" if SOC_PART_NUMBER_FS32K142UAT0VLHT - default "FS32K142UAT0VLLR" if SOC_PART_NUMBER_FS32K142UAT0VLLR - default "FS32K142UAT0VLLT" if SOC_PART_NUMBER_FS32K142UAT0VLLT - default "FS32K142UIT0VLHT" if SOC_PART_NUMBER_FS32K142UIT0VLHT - default "FS32K142WAT0WLFT" if SOC_PART_NUMBER_FS32K142WAT0WLFT - default "FS32K142WAT0WLHT" if SOC_PART_NUMBER_FS32K142WAT0WLHT - default "FS32K144HAT0MLFT" if SOC_PART_NUMBER_FS32K144HAT0MLFT - default "FS32K144HAT0MLHR" if SOC_PART_NUMBER_FS32K144HAT0MLHR - default "FS32K144HAT0MLHT" if SOC_PART_NUMBER_FS32K144HAT0MLHT - default "FS32K144HAT0MLLR" if SOC_PART_NUMBER_FS32K144HAT0MLLR - default "FS32K144HAT0MLLT" if SOC_PART_NUMBER_FS32K144HAT0MLLT - default "FS32K144HAT0MMHR" if SOC_PART_NUMBER_FS32K144HAT0MMHR - default "FS32K144HAT0MMHT" if SOC_PART_NUMBER_FS32K144HAT0MMHT - default "FS32K144HVT0VLHR" if SOC_PART_NUMBER_FS32K144HVT0VLHR - default "FS32K144HVT0VLHT" if SOC_PART_NUMBER_FS32K144HVT0VLHT - default "FS32K144HXT0VLHT" if SOC_PART_NUMBER_FS32K144HXT0VLHT - default "FS32K144HXT0VLLT" if SOC_PART_NUMBER_FS32K144HXT0VLLT - default "FS32K144UAT0VLFT" if SOC_PART_NUMBER_FS32K144UAT0VLFT - default "FS32K144UAT0VLHR" if SOC_PART_NUMBER_FS32K144UAT0VLHR - default "FS32K144UAT0VLHT" if SOC_PART_NUMBER_FS32K144UAT0VLHT - default "FS32K144UAT0VLLT" if SOC_PART_NUMBER_FS32K144UAT0VLLT - default "FS32K144UAT0VMHR" if SOC_PART_NUMBER_FS32K144UAT0VMHR - default "FS32K144UAT0VMHT" if SOC_PART_NUMBER_FS32K144UAT0VMHT - default "FS32K144UIT0VLHT" if SOC_PART_NUMBER_FS32K144UIT0VLHT - default "FS32K144ULT0VLHT" if SOC_PART_NUMBER_FS32K144ULT0VLHT - default "FS32K144ULT0VLLR" if SOC_PART_NUMBER_FS32K144ULT0VLLR - default "FS32K144ULT0VLLT" if SOC_PART_NUMBER_FS32K144ULT0VLLT - default "FS32K144WAT0WLFT" if SOC_PART_NUMBER_FS32K144WAT0WLFT - default "FS32K144WAT0WLHT" if SOC_PART_NUMBER_FS32K144WAT0WLHT - default "FS32K146HAT0MLHR" if SOC_PART_NUMBER_FS32K146HAT0MLHR - default "FS32K146HAT0MLHT" if SOC_PART_NUMBER_FS32K146HAT0MLHT - default "FS32K146HAT0MLLR" if SOC_PART_NUMBER_FS32K146HAT0MLLR - default "FS32K146HAT0MLLT" if SOC_PART_NUMBER_FS32K146HAT0MLLT - default "FS32K146HAT0MLQR" if SOC_PART_NUMBER_FS32K146HAT0MLQR - default "FS32K146HAT0MLQT" if SOC_PART_NUMBER_FS32K146HAT0MLQT - default "FS32K146HAT0MMHR" if SOC_PART_NUMBER_FS32K146HAT0MMHR - default "FS32K146HAT0MMHT" if SOC_PART_NUMBER_FS32K146HAT0MMHT - default "FS32K146HVT0VLHT" if SOC_PART_NUMBER_FS32K146HVT0VLHT - default "FS32K146HXT0VLLT" if SOC_PART_NUMBER_FS32K146HXT0VLLT - default "FS32K146UAT0VLHR" if SOC_PART_NUMBER_FS32K146UAT0VLHR - default "FS32K146UAT0VLHT" if SOC_PART_NUMBER_FS32K146UAT0VLHT - default "FS32K146UAT0VLLR" if SOC_PART_NUMBER_FS32K146UAT0VLLR - default "FS32K146UAT0VLLT" if SOC_PART_NUMBER_FS32K146UAT0VLLT - default "FS32K146UAT0VLQR" if SOC_PART_NUMBER_FS32K146UAT0VLQR - default "FS32K146UAT0VLQT" if SOC_PART_NUMBER_FS32K146UAT0VLQT - default "FS32K146UAT0VMHR" if SOC_PART_NUMBER_FS32K146UAT0VMHR - default "FS32K146UAT0VMHT" if SOC_PART_NUMBER_FS32K146UAT0VMHT - default "FS32K146UIT0VLLT" if SOC_PART_NUMBER_FS32K146UIT0VLLT - default "FS32K146ULT0VLLT" if SOC_PART_NUMBER_FS32K146ULT0VLLT - default "FS32K148HAT0MLLR" if SOC_PART_NUMBER_FS32K148HAT0MLLR - default "FS32K148HAT0MLLT" if SOC_PART_NUMBER_FS32K148HAT0MLLT - default "FS32K148HAT0MLQR" if SOC_PART_NUMBER_FS32K148HAT0MLQR - default "FS32K148HAT0MLQT" if SOC_PART_NUMBER_FS32K148HAT0MLQT - default "FS32K148HAT0MLUT" if SOC_PART_NUMBER_FS32K148HAT0MLUT - default "FS32K148HAT0MMHT" if SOC_PART_NUMBER_FS32K148HAT0MMHT - default "FS32K148UGT0VLQT" if SOC_PART_NUMBER_FS32K148UGT0VLQT - default "FS32K148UIT0VLQT" if SOC_PART_NUMBER_FS32K148UIT0VLQT - default "FS32K148UJT0VLLT" if SOC_PART_NUMBER_FS32K148UJT0VLLT - default "FS32K148UJT0VLQT" if SOC_PART_NUMBER_FS32K148UJT0VLQT - default "FS32K148UJT0VLUT" if SOC_PART_NUMBER_FS32K148UJT0VLUT - default "FS32K148UJT0VMHR" if SOC_PART_NUMBER_FS32K148UJT0VMHR - default "FS32K148UJT0VMHT" if SOC_PART_NUMBER_FS32K148UJT0VMHT - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config WDOG_INIT - bool - default y - -config NXP_S32_FLASH_CONFIG - bool "NXP S32 flash configuration field" - default y if XIP && !BOOTLOADER_MCUBOOT - help - Include the 16-byte flash configuration field that stores default - protection settings (loaded on reset) and security information that - allows the MCU to restrict access to the FTFx module. - -if NXP_S32_FLASH_CONFIG - -config NXP_S32_FLASH_CONFIG_OFFSET - hex "NXP S32 flash configuration field offset" - default 0x400 - -config NXP_S32_FLASH_CONFIG_FSEC - hex "Flash security byte (FSEC)" - range 0 0xff - default 0xfe - help - Configures the reset value of the FSEC register, which includes - backdoor key access, mass erase, factory access, and flash security - options. - -config NXP_S32_FLASH_CONFIG_FOPT - hex "Flash nonvolatile option byte (FOPT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FOPT register, which includes boot, - NMI, and EzPort options. - -config NXP_S32_FLASH_CONFIG_FEPROT - hex "EEPROM protection byte (FEPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FEPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -config NXP_S32_FLASH_CONFIG_FDPROT - hex "Data flash protection byte (FDPROT)" - range 0 0xff - default 0xff - help - Configures the reset value of the FDPROT register for FlexNVM - devices. For program flash only devices, this byte is reserved. - -endif # NXP_S32_FLASH_CONFIG - -config NXP_S32_ENABLE_CODE_CACHE - bool "Code cache" - default y - depends on HAS_MCUX_CACHE - -endif # SOC_SERIES_S32K1XX diff --git a/soc/arm/nxp_s32/s32k1/soc.c b/soc/arm/nxp_s32/s32k1/soc.c deleted file mode 100644 index bed85dbc91ddae..00000000000000 --- a/soc/arm/nxp_s32/s32k1/soc.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright 2023 NXP - * - * Based on zephyr/soc/arm/nxp_kinetis/ke1xf/soc.c, which is: - * Copyright (c) 2019-2021 Vestas Wind Systems A/S - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include - -#include -#include - -#if defined(CONFIG_HAS_MCUX_CACHE) -#include -#endif - -#if defined(CONFIG_WDOG_INIT) -void z_arm_watchdog_init(void) -{ - /* - * NOTE: DO NOT SINGLE STEP THROUGH THIS SECTION!!! Watchdog - * reconfiguration must take place within 128 bus clocks from - * unlocking. Single stepping through the code will cause the - * watchdog to close the unlock window again. - */ - if ((IP_WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) { - IP_WDOG->CNT = WDOG_UPDATE_KEY; - } else { - IP_WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU; - IP_WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU; - } - while (!(IP_WDOG->CS & WDOG_CS_ULK_MASK)) { - ; - } - - IP_WDOG->TOVAL = 0xFFFFU; - IP_WDOG->CS = (uint32_t) ((IP_WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; - - /* Wait for new configuration to take effect */ - while (!(IP_WDOG->CS & WDOG_CS_RCS_MASK)) { - ; - } -} -#endif /* CONFIG_WDOG_INIT */ - -static int soc_init(void) -{ -#if !defined(CONFIG_ARM_MPU) - uint32_t tmp; - - /* - * Disable memory protection and clear slave port errors. - * Note that the S32K1xx does not implement the optional Arm MPU but - * instead the Soc includes its own NXP MPU module. - */ - tmp = IP_MPU->CESR; - tmp &= ~MPU_CESR_VLD_MASK; - tmp |= MPU_CESR_SPERR0_MASK | MPU_CESR_SPERR1_MASK - | MPU_CESR_SPERR2_MASK | MPU_CESR_SPERR3_MASK; - IP_MPU->CESR = tmp; -#endif /* !CONFIG_ARM_MPU */ - -#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE) - L1CACHE_EnableCodeCache(); - barrier_isync_fence_full(); -#endif - - OsIf_Init(NULL); - - return 0; -} - -SYS_INIT(soc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_s32/s32k3/CMakeLists.txt b/soc/arm/nxp_s32/s32k3/CMakeLists.txt deleted file mode 100644 index d65a1a2e73b66b..00000000000000 --- a/soc/arm/nxp_s32/s32k3/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources(soc.c) -zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c) -zephyr_linker_sources(SECTIONS sections.ld) -zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT s32k3xx_startup.S) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k344 b/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k344 deleted file mode 100644 index b1b534f6102dad..00000000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k344 +++ /dev/null @@ -1,14 +0,0 @@ -# NXP S32K344 - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_S32K344 - -config SOC - default "s32k344" - -config FPU - default y - -endif # SOC_S32K344 diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.series deleted file mode 100644 index 2307571611aba0..00000000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.defconfig.series +++ /dev/null @@ -1,40 +0,0 @@ -# NXP S32K3XX MCU series - -# Copyright 2023-2024 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_S32K3XX - -config SOC_SERIES - default "s32k3" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 2000000 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 239 - -if !XIP -config FLASH_SIZE - default 0 -config FLASH_BASE_ADDRESS - default 0 -endif - -if NET_L2_ETHERNET - -config NET_TCP_CHECKSUM - default n - -config NET_UDP_CHECKSUM - default n - -endif # NET_L2_ETHERNET - -config CACHE_MANAGEMENT - default y - -source "soc/arm/nxp_s32/s32k3/Kconfig.defconfig.s32k*" - -endif # SOC_SERIES_S32K3XX diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.series b/soc/arm/nxp_s32/s32k3/Kconfig.series deleted file mode 100644 index ac90439b6446a3..00000000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# NXP S32K3XX MCU series - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_S32K3XX - bool "NXP S32K3XX MCU series" - select ARM - select CPU_CORTEX_M7 - select SOC_FAMILY_NXP_S32 - select HAS_NXP_S32_HAL - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - select PLATFORM_SPECIFIC_INIT if XIP - select USE_DT_CODE_PARTITION if XIP - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_LPUART - select HAS_MCUX_FLEXCAN - select HAS_MCUX_LPI2C - select HAS_MCUX_LPSPI - select HAS_MCUX_CACHE - help - Enable support for NXP S32K3XX MCU series. diff --git a/soc/arm/nxp_s32/s32k3/Kconfig.soc b/soc/arm/nxp_s32/s32k3/Kconfig.soc deleted file mode 100644 index 6b8f4e3a883970..00000000000000 --- a/soc/arm/nxp_s32/s32k3/Kconfig.soc +++ /dev/null @@ -1,61 +0,0 @@ -# NXP S32K3XX MCU series - -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP S32K3XX MCU selection" - depends on SOC_SERIES_S32K3XX - -config SOC_S32K344 - bool "s32k344" - -endchoice - -if SOC_SERIES_S32K3XX - -config SOC_PART_NUMBER_PS32K344EHVPBS - bool - -config SOC_PART_NUMBER - string - default "PS32K344EHVPBS" if SOC_PART_NUMBER_PS32K344EHVPBS - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config IVT_HEADER_OFFSET - hex - depends on XIP - default $(dt_node_reg_addr_hex,$(dt_nodelabel_path,ivt_header)) - help - The offset address from flash base address for ivt header - -config IVT_HEADER_SIZE - hex - depends on XIP - default $(dt_node_reg_size_hex,$(dt_nodelabel_path,ivt_header)) - help - Size of ivt header region - -config NXP_S32_PMC_LMEN - bool "Last Mile regulator" - default y if CLOCK_CONTROL - help - Enables the Last Mile regulator, which regulates an external 1.5V - voltage on V15 down to the core and logic supply (V11 power domain), - which is typically 1.1V. - When enabling PLL as system clock, the PMC last mile regulator should - be enabled. - -config NXP_S32_PMC_LMBCTLEN - bool "External BCTL regulator for V15" - depends on NXP_S32_PMC_LMEN - help - This option must be selected if an external BJT between VDD_HV_A and - V15 is used on the PCB. The base of this BJT must be connected to the - VRC_CTRL pin and is controlled by the PMC to regulate a voltage of - 1.5V on V15 pin. - -endif diff --git a/soc/arm/nxp_s32/s32ze/CMakeLists.txt b/soc/arm/nxp_s32/s32ze/CMakeLists.txt deleted file mode 100644 index d0eb4cf78b1e1a..00000000000000 --- a/soc/arm/nxp_s32/s32ze/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources( - soc.c -) - -zephyr_library_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 deleted file mode 100644 index 2a88861fc98c6d..00000000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32z27 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_S32Z27_R52 - -config SOC - default "s32z27" - -endif # SOC_S32Z27_R52 diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series b/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series deleted file mode 100644 index a418c054792374..00000000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.defconfig.series +++ /dev/null @@ -1,45 +0,0 @@ -# NXP S32Z/E MCUs family default configuration - -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_S32ZE_R52 - -config SOC_SERIES - default "s32ze" - -config NUM_IRQS - # must be >= the highest interrupt number used - default 991 - -config FPU - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 2000000 - -config MAIN_STACK_SIZE - default 1024 - -if !XIP -config FLASH_SIZE - default 0 - -config FLASH_BASE_ADDRESS - default 0 -endif # !XIP - -if NET_L2_ETHERNET - -# NETC drops TCP/UDP packets with invalid checksum -config NET_TCP_CHECKSUM - default n - -config NET_UDP_CHECKSUM - default n - -endif # NET_L2_ETHERNET - -source "soc/arm/nxp_s32/s32ze/Kconfig.defconfig.s32*" - -endif # SOC_SERIES_S32ZE_R52 diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.series b/soc/arm/nxp_s32/s32ze/Kconfig.series deleted file mode 100644 index c1f2d3606ec3dc..00000000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# NXP S32Z/E MCUs family - -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_S32ZE_R52 - bool "NXP S32Z/E series" - select ARM - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select CPU_CORTEX_R52 - select CPU_HAS_DCLS - select CPU_HAS_ARM_MPU - select GIC_SINGLE_SECURITY_STATE - select VFP_DP_D16 - select PLATFORM_SPECIFIC_INIT - select SOC_FAMILY_NXP_S32 - select CLOCK_CONTROL - select HAS_MCUX - select HAS_MCUX_PIT - help - Enable support for NXP S32Z/E MCUs family on Cortex-R52 cores. diff --git a/soc/arm/nxp_s32/s32ze/Kconfig.soc b/soc/arm/nxp_s32/s32ze/Kconfig.soc deleted file mode 100644 index 790751362d3e63..00000000000000 --- a/soc/arm/nxp_s32/s32ze/Kconfig.soc +++ /dev/null @@ -1,35 +0,0 @@ -# NXP S32Z/E MCUs family - -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP S32Z/E MCUs family SoC selection" - depends on SOC_SERIES_S32ZE_R52 - -config SOC_S32Z27_R52 - bool "SOC_S32Z27_R52" - select HAS_NXP_S32_HAL - -endchoice - -if SOC_SERIES_S32ZE_R52 - -config SOC_PART_NUMBER_S32Z27 - bool - -config SOC_PART_NUMBER - string - default "S32Z27" if SOC_PART_NUMBER_S32Z27 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config NXP_S32_RTU_INDEX - int - range 0 1 - help - This option indicates the index of the target RTU (Real-Time Unit) subsystem. - -endif # SOC_SERIES_S32ZE_R52 diff --git a/soc/arm/nxp_s32/s32ze/soc.h b/soc/arm/nxp_s32/s32ze/soc.h deleted file mode 100644 index e042ebe8af9075..00000000000000 --- a/soc/arm/nxp_s32/s32ze/soc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2022-2023 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef _NXP_S32_S32ZE_SOC_H_ -#define _NXP_S32_S32ZE_SOC_H_ - -/* Do not let CMSIS to handle GIC */ -#define __GIC_PRESENT 0 - -#if defined(CONFIG_SOC_S32Z27_R52) -#include -#else -#error "SoC not supported" -#endif - -#if defined(CONFIG_CMSIS_RTOS_V2) -#include -#endif - -/* Aliases for peripheral base addresses */ - -/* SIUL2 */ -#define IP_SIUL2_2_BASE 0U /* instance does not exist on this SoC */ - -/* LINFlexD*/ -#define IP_LINFLEX_12_BASE IP_MSC_0_LIN_BASE - -/* SWT */ -#define IP_SWT_0_BASE IP_CE_SWT_0_BASE -#define IP_SWT_1_BASE IP_CE_SWT_1_BASE -#define IP_SWT_2_BASE IP_RTU0__SWT_0_BASE -#define IP_SWT_3_BASE IP_RTU0__SWT_1_BASE -#define IP_SWT_4_BASE IP_RTU0__SWT_2_BASE -#define IP_SWT_5_BASE IP_RTU0__SWT_3_BASE -#define IP_SWT_6_BASE IP_RTU0__SWT_4_BASE -#define IP_SWT_7_BASE IP_RTU1__SWT_0_BASE -#define IP_SWT_8_BASE IP_RTU1__SWT_1_BASE -#define IP_SWT_9_BASE IP_RTU1__SWT_2_BASE -#define IP_SWT_10_BASE IP_RTU1__SWT_3_BASE -#define IP_SWT_11_BASE IP_RTU1__SWT_4_BASE -#define IP_SWT_12_BASE IP_SMU__SWT_BASE - -/* STM */ -#define IP_STM_0_BASE IP_CE_STM_0_BASE -#define IP_STM_1_BASE IP_CE_STM_1_BASE -#define IP_STM_2_BASE IP_CE_STM_2_BASE -#define IP_STM_3_BASE IP_RTU0__STM_0_BASE -#define IP_STM_4_BASE IP_RTU0__STM_1_BASE -#define IP_STM_5_BASE IP_RTU0__STM_2_BASE -#define IP_STM_6_BASE IP_RTU0__STM_3_BASE -#define IP_STM_7_BASE IP_RTU1__STM_0_BASE -#define IP_STM_8_BASE IP_RTU1__STM_1_BASE -#define IP_STM_9_BASE IP_RTU1__STM_2_BASE -#define IP_STM_10_BASE IP_RTU1__STM_3_BASE -#define IP_STM_11_BASE IP_SMU__STM_0_BASE -#define IP_STM_12_BASE IP_SMU__STM_2_BASE - -/* NETC */ -#define IP_NETC_EMDIO_0_BASE IP_NETC__EMDIO_BASE_BASE - -/* MRU */ -#define IP_MRU_0_BASE IP_RTU0__MRU_0_BASE -#define IP_MRU_1_BASE IP_RTU0__MRU_1_BASE -#define IP_MRU_2_BASE IP_RTU0__MRU_2_BASE -#define IP_MRU_3_BASE IP_RTU0__MRU_3_BASE -#define IP_MRU_4_BASE IP_RTU1__MRU_0_BASE -#define IP_MRU_5_BASE IP_RTU1__MRU_1_BASE -#define IP_MRU_6_BASE IP_RTU1__MRU_2_BASE -#define IP_MRU_7_BASE IP_RTU1__MRU_3_BASE - -#endif /* _NXP_S32_S32ZE_SOC_H_ */ diff --git a/soc/arm/qemu_cortex_a53/CMakeLists.txt b/soc/arm/qemu_cortex_a53/CMakeLists.txt new file mode 100644 index 00000000000000..35d88056740af3 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/qemu_cortex_a53/Kconfig b/soc/arm/qemu_cortex_a53/Kconfig new file mode 100644 index 00000000000000..2520e012af7138 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_CORTEX_A53 + select ARM64 + select CPU_CORTEX_A53 + select QEMU_TARGET diff --git a/soc/arm/qemu_cortex_a53/Kconfig.defconfig b/soc/arm/qemu_cortex_a53/Kconfig.defconfig new file mode 100644 index 00000000000000..9d628ef3b59a80 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_CORTEX_A53 + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # - LPIs (starting at 8192) if GIC_V3_ITS is used + default 16384 if GIC_V3_ITS + default 220 if !GIC_V3_ITS + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 62500000 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_QEMU_CORTEX_A53 diff --git a/soc/arm/qemu_cortex_a53/Kconfig.soc b/soc/arm/qemu_cortex_a53/Kconfig.soc new file mode 100644 index 00000000000000..e9d9c6640b6145 --- /dev/null +++ b/soc/arm/qemu_cortex_a53/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Carlo Caione +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_CORTEX_A53 + bool + select SOC_FAMILY_ARM64 + +config SOC + default "qemu_cortex_a53" if SOC_QEMU_CORTEX_A53 diff --git a/soc/arm64/qemu_cortex_a53/mmu_regions.c b/soc/arm/qemu_cortex_a53/mmu_regions.c similarity index 100% rename from soc/arm64/qemu_cortex_a53/mmu_regions.c rename to soc/arm/qemu_cortex_a53/mmu_regions.c diff --git a/soc/arm64/qemu_virt_arm64/CMakeLists.txt b/soc/arm/qemu_virt_arm64/CMakeLists.txt similarity index 100% rename from soc/arm64/qemu_virt_arm64/CMakeLists.txt rename to soc/arm/qemu_virt_arm64/CMakeLists.txt diff --git a/soc/arm/qemu_virt_arm64/Kconfig b/soc/arm/qemu_virt_arm64/Kconfig new file mode 100644 index 00000000000000..7c5f7aee6f937b --- /dev/null +++ b/soc/arm/qemu_virt_arm64/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Huawei France Technologies SAS +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_ARM64 + select ARM64 + select CPU_CORTEX_A + select ARMV8_A diff --git a/soc/arm/qemu_virt_arm64/Kconfig.defconfig b/soc/arm/qemu_virt_arm64/Kconfig.defconfig new file mode 100644 index 00000000000000..e1a386130406b9 --- /dev/null +++ b/soc/arm/qemu_virt_arm64/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2022 Huawei France Technologies SAS +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_VIRT_ARM64 + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # - LPIs (starting at 8192) if GIC_V3_ITS is used + default 16384 if GIC_V3_ITS + default 220 if !GIC_V3_ITS + +# Dummy value, read at runtime +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_QEMU_VIRT_ARM64 diff --git a/soc/arm/qemu_virt_arm64/Kconfig.soc b/soc/arm/qemu_virt_arm64/Kconfig.soc new file mode 100644 index 00000000000000..e539b4a40cdec8 --- /dev/null +++ b/soc/arm/qemu_virt_arm64/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2022 Huawei France Technologies SAS +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_ARM64 + bool + select SOC_FAMILY_ARM64 + +config SOC + default "qemu_virt_arm64" if SOC_QEMU_VIRT_ARM64 diff --git a/soc/arm64/qemu_virt_arm64/mmu_regions.c b/soc/arm/qemu_virt_arm64/mmu_regions.c similarity index 100% rename from soc/arm64/qemu_virt_arm64/mmu_regions.c rename to soc/arm/qemu_virt_arm64/mmu_regions.c diff --git a/soc/arm/quicklogic_eos_s3/CMakeLists.txt b/soc/arm/quicklogic_eos_s3/CMakeLists.txt deleted file mode 100644 index 224b298c409638..00000000000000 --- a/soc/arm/quicklogic_eos_s3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/quicklogic_eos_s3/Kconfig b/soc/arm/quicklogic_eos_s3/Kconfig deleted file mode 100644 index d2f7c006428960..00000000000000 --- a/soc/arm/quicklogic_eos_s3/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EOS_S3 - bool diff --git a/soc/arm/quicklogic_eos_s3/Kconfig.defconfig b/soc/arm/quicklogic_eos_s3/Kconfig.defconfig deleted file mode 100644 index d09a30ca53e862..00000000000000 --- a/soc/arm/quicklogic_eos_s3/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EOS_S3 - -config SOC - default "quicklogic_eos_s3" - -config NUM_IRQS - default 52 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 61440000 - -if SERIAL - -config UART_INTERRUPT_DRIVEN - default y - -endif # SERIAL - -endif # SOC_EOS_S3 diff --git a/soc/arm/quicklogic_eos_s3/Kconfig.soc b/soc/arm/quicklogic_eos_s3/Kconfig.soc deleted file mode 100644 index e555933430bbdb..00000000000000 --- a/soc/arm/quicklogic_eos_s3/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2020 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EOS_S3 - bool "QuickLogic EOS S3 SoC" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select EOS_S3_HAL diff --git a/soc/arm/renesas_ra/Kconfig b/soc/arm/renesas_ra/Kconfig deleted file mode 100644 index 628b75a93deeee..00000000000000 --- a/soc/arm/renesas_ra/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RA - bool - -if SOC_FAMILY_RA - -config SOC_FAMILY - string - default "renesas_ra" - -config SERIES_SPECIFIC_SOC_INIT - bool "Use series specific initialize" - -source "soc/arm/renesas_ra/*/Kconfig.soc" - -endif # SOC_FAMILY_RA diff --git a/soc/arm/renesas_ra/Kconfig.defconfig b/soc/arm/renesas_ra/Kconfig.defconfig deleted file mode 100644 index e5e211a94b3da8..00000000000000 --- a/soc/arm/renesas_ra/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_ra/*/Kconfig.defconfig.series" diff --git a/soc/arm/renesas_ra/Kconfig.soc b/soc/arm/renesas_ra/Kconfig.soc deleted file mode 100644 index 2652ee94d2ee23..00000000000000 --- a/soc/arm/renesas_ra/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_ra/*/Kconfig.series" diff --git a/soc/arm/renesas_ra/ra4m1/CMakeLists.txt b/soc/arm/renesas_ra/ra4m1/CMakeLists.txt deleted file mode 100644 index 4debbfdbf8a8e9..00000000000000 --- a/soc/arm/renesas_ra/ra4m1/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.r7fa4m1xxxxxx b/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.r7fa4m1xxxxxx deleted file mode 100644 index c138e20d85cc7d..00000000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.r7fa4m1xxxxxx +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if SOC_R7FA4M1AB3CFM - -config SOC - default "r7fa4m1ab3cfm" - -endif # SOC_R7FA4M1AB3CFM diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.series b/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.series deleted file mode 100644 index 99e8e3f639d26e..00000000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RA4M1 - -rsource "Kconfig.defconfig.r7fa4*" - -config SOC_SERIES - default "ra4m1" - -config NUM_IRQS - default 32 - -endif # SOC_SERIES_RA4M1 diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.series b/soc/arm/renesas_ra/ra4m1/Kconfig.series deleted file mode 100644 index 7307a2d26c0c1f..00000000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RA4M1 - bool "Renesas RA4M1" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_SYSTICK - select DYNAMIC_INTERRUPTS - select SOC_FAMILY_RA - select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME - select XIP diff --git a/soc/arm/renesas_ra/ra4m1/Kconfig.soc b/soc/arm/renesas_ra/ra4m1/Kconfig.soc deleted file mode 100644 index a7b402fd291073..00000000000000 --- a/soc/arm/renesas_ra/ra4m1/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 TOKITA Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RA4M1 SoC Selection" - depends on SOC_SERIES_RA4M1 - -config SOC_R7FA4M1AB3CFM - bool "R7FA4M1AB3CFM" - -endchoice diff --git a/soc/arm/renesas_ra/ra4m1/linker.ld b/soc/arm/renesas_ra/ra4m1/linker.ld deleted file mode 100644 index 44d5ee518896ee..00000000000000 --- a/soc/arm/renesas_ra/ra4m1/linker.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2023 TOKITA Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include diff --git a/soc/arm/renesas_rcar/Kconfig b/soc/arm/renesas_rcar/Kconfig deleted file mode 100644 index d97ae6b987ea55..00000000000000 --- a/soc/arm/renesas_rcar/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RCAR - bool - -if SOC_FAMILY_RCAR - -config SOC_FAMILY - string - default "renesas_rcar" - -source "soc/arm/renesas_rcar/*/Kconfig.soc" - -endif # SOC_FAMILY_RCAR diff --git a/soc/arm/renesas_rcar/Kconfig.defconfig b/soc/arm/renesas_rcar/Kconfig.defconfig deleted file mode 100644 index 604ac57ba70d52..00000000000000 --- a/soc/arm/renesas_rcar/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_rcar/*/Kconfig.defconfig.series" diff --git a/soc/arm/renesas_rcar/Kconfig.soc b/soc/arm/renesas_rcar/Kconfig.soc deleted file mode 100644 index 930e18649e17de..00000000000000 --- a/soc/arm/renesas_rcar/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - - -source "soc/arm/renesas_rcar/*/Kconfig.series" diff --git a/soc/arm/renesas_rcar/gen3/CMakeLists.txt b/soc/arm/renesas_rcar/gen3/CMakeLists.txt deleted file mode 100644 index 4356fe77d51250..00000000000000 --- a/soc/arm/renesas_rcar/gen3/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c -) -zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951 pfc_r8a77951.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 b/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 deleted file mode 100644 index ba218a4caa68c9..00000000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_R8A77951 - -config SOC - default "r8a77951" - -endif # SOC_R8A77951 diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.series b/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.series deleted file mode 100644 index 6bb84ee421b62c..00000000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Renesas R-Car Gen3 SoC line - -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RCAR_GEN3 - -config SOC_SERIES - default "gen3" - -config NUM_IRQS - default 512 - -config PINCTRL - default y - -endif # SOC_SERIES_RCAR_GEN3 diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.series b/soc/arm/renesas_rcar/gen3/Kconfig.series deleted file mode 100644 index 717f9881bf9291..00000000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RCAR_GEN3 - bool "Renesas RCAR Gen3 Cortex R7" - select ARM - select CPU_CORTEX_R7 - select PLATFORM_SPECIFIC_INIT - select CPU_HAS_DCLS - select SOC_FAMILY_RCAR - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL - help - Enable support for Renesas RCar Gen3 SoC series diff --git a/soc/arm/renesas_rcar/gen3/Kconfig.soc b/soc/arm/renesas_rcar/gen3/Kconfig.soc deleted file mode 100644 index c859648634367a..00000000000000 --- a/soc/arm/renesas_rcar/gen3/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RCar SoC Selection" - depends on SOC_SERIES_RCAR_GEN3 - -config SOC_R8A77951 - bool "R8A77951" - -endchoice diff --git a/soc/arm/renesas_rcar/gen4/CMakeLists.txt b/soc/arm/renesas_rcar/gen4/CMakeLists.txt deleted file mode 100644 index 906bfdecfba748..00000000000000 --- a/soc/arm/renesas_rcar/gen4/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series b/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series deleted file mode 100644 index 36218fe504fa3a..00000000000000 --- a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Renesas R-Car Gen4 SoC line - -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RCAR_GEN4 - -source "soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779*" - -config SOC_SERIES - default "gen4" - -endif # SOC_SERIES_RCAR_GEN4 diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.series b/soc/arm/renesas_rcar/gen4/Kconfig.series deleted file mode 100644 index 606b2c50e43a9e..00000000000000 --- a/soc/arm/renesas_rcar/gen4/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RCAR_GEN4 - bool "Renesas R-Car Gen4 Cortex R52" - select ARM - select CPU_CORTEX_R52 - select GIC_SINGLE_SECURITY_STATE - select SOC_FAMILY_RCAR - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL - select ARM_ARCH_TIMER - help - Enable support for Renesas R-Car Gen4 SoC series diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.soc b/soc/arm/renesas_rcar/gen4/Kconfig.soc deleted file mode 100644 index 5c443d6101e73e..00000000000000 --- a/soc/arm/renesas_rcar/gen4/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 IoT.bzh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RCar SoC Selection" - depends on SOC_SERIES_RCAR_GEN4 - -config SOC_R8A779F0 - bool "r8a779f0" - -endchoice diff --git a/soc/arm/renesas_rcar/gen4/linker.ld b/soc/arm/renesas_rcar/gen4/linker.ld deleted file mode 100644 index a51ff84991f899..00000000000000 --- a/soc/arm/renesas_rcar/gen4/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright (c) 2023 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/arm/renesas_rzt2m/CMakeLists.txt b/soc/arm/renesas_rzt2m/CMakeLists.txt deleted file mode 100644 index 05fd66ec83cd40..00000000000000 --- a/soc/arm/renesas_rzt2m/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - ) diff --git a/soc/arm/renesas_rzt2m/Kconfig b/soc/arm/renesas_rzt2m/Kconfig deleted file mode 100644 index fc2f6e81c4eca4..00000000000000 --- a/soc/arm/renesas_rzt2m/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RENESAS_RZT2M - bool - -if SOC_RENESAS_RZT2M - -config SOC_PART_NUMBER_R9A07G075 - bool - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_R9A07G075 - -endif # SOC_RENESAS_RZT2M diff --git a/soc/arm/renesas_rzt2m/Kconfig.defconfig b/soc/arm/renesas_rzt2m/Kconfig.defconfig deleted file mode 100644 index 72f828d4351179..00000000000000 --- a/soc/arm/renesas_rzt2m/Kconfig.defconfig +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RENESAS_RZT2M - -config SOC - default "renesas_rzt2m" - -config NUM_IRQS - default 994 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 20000000 - -config FPU - default y - -config FLASH_SIZE - default 0 - -config FLASH_BASE_ADDRESS - default 0 - -endif # SOC_RENESAS_RZT2M diff --git a/soc/arm/renesas_rzt2m/Kconfig.soc b/soc/arm/renesas_rzt2m/Kconfig.soc deleted file mode 100644 index 0275833b7925ec..00000000000000 --- a/soc/arm/renesas_rzt2m/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RENESAS_RZT2M - bool "Renesas RZ/T2M MCU" - select ARM - select CPU_CORTEX_R52 - select CPU_HAS_ARM_MPU - select GIC_V3 - select GIC_SINGLE_SECURITY_STATE - select ARM_ARCH_TIMER - select SYSCON diff --git a/soc/arm/renesas_smartbond/Kconfig b/soc/arm/renesas_smartbond/Kconfig deleted file mode 100644 index 1fd4e25a6a1793..00000000000000 --- a/soc/arm/renesas_smartbond/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SMARTBOND - bool - select ARM - select CPU_CORTEX_M33 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_SMARTBOND -config SOC_FAMILY - string - default "renesas_smartbond" - -source "soc/arm/renesas_smartbond/*/Kconfig.soc" - -endif # SOC_FAMILY_SMARTBOND diff --git a/soc/arm/renesas_smartbond/Kconfig.defconfig b/soc/arm/renesas_smartbond/Kconfig.defconfig deleted file mode 100644 index 54728dd50383a8..00000000000000 --- a/soc/arm/renesas_smartbond/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_SMARTBOND - -source "soc/arm/renesas_smartbond/*/Kconfig.defconfig.series" - -config PINCTRL - default y - -endif # SOC_FAMILY_SMARTBOND diff --git a/soc/arm/renesas_smartbond/Kconfig.soc b/soc/arm/renesas_smartbond/Kconfig.soc deleted file mode 100644 index 6d91625f8158e3..00000000000000 --- a/soc/arm/renesas_smartbond/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/renesas_smartbond/*/Kconfig.series" diff --git a/soc/arm/renesas_smartbond/da1469x/CMakeLists.txt b/soc/arm/renesas_smartbond/da1469x/CMakeLists.txt deleted file mode 100644 index 115f3a3402875f..00000000000000 --- a/soc/arm/renesas_smartbond/da1469x/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_linker_sources( - RAM_SECTIONS - SORT_KEY 0 - intvect_reserved.ld -) -zephyr_library() -zephyr_library_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14695 b/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14695 deleted file mode 100644 index 101e275b79f69d..00000000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14695 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -if SOC_DA14695 - -config SOC - default "da14695" - -endif # SOC_DA14695 diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14699 b/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14699 deleted file mode 100644 index f723336d864308..00000000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da14699 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_DA14699 - -config SOC - default "da14699" - -endif # SOC_DA14699 diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.series b/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.series deleted file mode 100644 index 801ae9ac9e4766..00000000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_DA1469X - -source "soc/arm/renesas_smartbond/da1469x/Kconfig.defconfig.da1469*" - -config SOC_SERIES - default "da1469x" - -config NUM_IRQS - default 40 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config SRAM_VECTOR_TABLE - default y - -config USE_DT_CODE_PARTITION - default y if MCUBOOT - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config FLASH_LOAD_OFFSET - default 0x2400 if !USE_DT_CODE_PARTITION - -config PLATFORM_SPECIFIC_INIT - default y - -endif # SOC_SERIES_DA1469X diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.series b/soc/arm/renesas_smartbond/da1469x/Kconfig.series deleted file mode 100644 index c3672a9ecaf753..00000000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2022 Renesas Electronics Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_DA1469X - bool "Renesas SmartBond(tm) DA1469x series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_CORTEX_M_HAS_SYSTICK - select ARMV8_M_DSP - select SOC_FAMILY_SMARTBOND - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select CLOCK_CONTROL - select CLOCK_CONTROL_SMARTBOND - help - Enable support for Renesas SmartBond(tm) DA1469x MCU series diff --git a/soc/arm/renesas_smartbond/da1469x/Kconfig.soc b/soc/arm/renesas_smartbond/da1469x/Kconfig.soc deleted file mode 100644 index b1e7eddb850033..00000000000000 --- a/soc/arm/renesas_smartbond/da1469x/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022-2023 Renesas Electronics Corporation and/or its affiliates -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas SmartBond(tm) DA1469x MCU selection" - depends on SOC_SERIES_DA1469X - -config SOC_DA14699 - bool "DA14699" - -config SOC_DA14695 - bool "DA14695" - -endchoice diff --git a/soc/arm/rpi_pico/CMakeLists.txt b/soc/arm/rpi_pico/CMakeLists.txt deleted file mode 100644 index 226f3bd626f611..00000000000000 --- a/soc/arm/rpi_pico/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/rpi_pico/Kconfig b/soc/arm/rpi_pico/Kconfig deleted file mode 100644 index 7d0f4215aad3ff..00000000000000 --- a/soc/arm/rpi_pico/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Raspberry Pi (RP) MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RPI_PICO - bool - -if SOC_FAMILY_RPI_PICO - -config SOC_FAMILY - string - default "rpi_pico" - -source "soc/arm/rpi_pico/*/Kconfig.soc" - -endif # SOC_FAMILY_RPI_PICO diff --git a/soc/arm/rpi_pico/Kconfig.defconfig b/soc/arm/rpi_pico/Kconfig.defconfig deleted file mode 100644 index 468d4545c5b23c..00000000000000 --- a/soc/arm/rpi_pico/Kconfig.defconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Raspberry Pi (RP) MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_RPI_PICO - -source "soc/arm/rpi_pico/*/Kconfig.defconfig.series" - -config PINCTRL - default y - -endif # SOC_FAMILY_RPI_PICO diff --git a/soc/arm/rpi_pico/Kconfig.soc b/soc/arm/rpi_pico/Kconfig.soc deleted file mode 100644 index d53c18307e0d35..00000000000000 --- a/soc/arm/rpi_pico/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Raspberry Pi (RP) MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/rpi_pico/*/Kconfig.series" diff --git a/soc/arm/rpi_pico/rp2/CMakeLists.txt b/soc/arm/rpi_pico/rp2/CMakeLists.txt deleted file mode 100644 index 119517e5e1c7dd..00000000000000 --- a/soc/arm/rpi_pico/rp2/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.series b/soc/arm/rpi_pico/rp2/Kconfig.defconfig.series deleted file mode 100644 index 7df057ae441b1d..00000000000000 --- a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# Raspberry Pi RP2XXX MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RP2XXX - -source "soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2*" - -config SOC_SERIES - default "rp2" - -config NUM_IRQS - default 26 - -endif # SOC_SERIES_RP2XXX diff --git a/soc/arm/rpi_pico/rp2/Kconfig.series b/soc/arm/rpi_pico/rp2/Kconfig.series deleted file mode 100644 index 35795a8d89324c..00000000000000 --- a/soc/arm/rpi_pico/rp2/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Raspberry Pi RP2XXX MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RP2XXX - bool "Raspberry Pi RP2 series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_RPI_PICO - select HAS_RPI_PICO - select XIP - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - help - Enable support for Raspberry Pi RP2 MCU series diff --git a/soc/arm/rpi_pico/rp2/Kconfig.soc b/soc/arm/rpi_pico/rp2/Kconfig.soc deleted file mode 100644 index 601182672db46d..00000000000000 --- a/soc/arm/rpi_pico/rp2/Kconfig.soc +++ /dev/null @@ -1,50 +0,0 @@ -# Raspberry Pi RP2XXX MCU line - -# Copyright (c) 2021 Nordic Semiconductor ASA -# Copyright (c) 2021 Yonatan Schachter -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "RP2xxx MCU Selection" - depends on SOC_SERIES_RP2XXX - -config SOC_RP2040 - bool "Raspberry Pi RP2040" - -endchoice - -config RP2_REQUIRES_SECOND_STAGE_BOOT - bool - default y if FLASH_LOAD_OFFSET = 0x100 - -# Flash type used by the SoC. The board should select the one used. - -config RP2_FLASH_W25Q080 - bool - help - Configure RP2 to use a W25Q080 flash chip, or similar. Should be selected - by the board definition, not the user. - -config RP2_FLASH_GENERIC_03H - bool - help - Configure RP2 to use a flash chip supporting the standard 03h command. - Should be selected by the board definition, not the user. - -config RP2_FLASH_IS25LP080 - bool - help - Configure RP2 to use a IS25LP080 flash chip, or similar. Should be selected - by the board definition, not the user. - -config RP2_FLASH_W25X10CL - bool - help - Configure RP2 to use a W25X10CL flash chip, or similar. Should be selected - by the board definition, not the user. - -config RP2_FLASH_AT25SF128A - bool - help - Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected - by the board definition, not the user. diff --git a/soc/arm/silabs_exx32/CMakeLists.txt b/soc/arm/silabs_exx32/CMakeLists.txt deleted file mode 100644 index 1a7c03d378e7fd..00000000000000 --- a/soc/arm/silabs_exx32/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) diff --git a/soc/arm/silabs_exx32/Kconfig b/soc/arm/silabs_exx32/Kconfig deleted file mode 100644 index 60bda813903d46..00000000000000 --- a/soc/arm/silabs_exx32/Kconfig +++ /dev/null @@ -1,352 +0,0 @@ -# Copyright (c) 2017 Christian Taedcke -# Copyright (c) 2018 Gil Benkoe -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_EXX32 - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select BUILD_OUTPUT_HEX - -if SOC_FAMILY_EXX32 - -config SOC_FAMILY - string - default "silabs_exx32" - -source "soc/arm/silabs_exx32/*/Kconfig.soc" - -config SOC_PART_NUMBER - string - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_GECKO_SERIES0 - bool - help - Set if we're building for Gecko Series 0 SoC. - This is equivalent of _SILICON_LABS_32B_SERIES_0 definition in HAL - code. - -config SOC_GECKO_SERIES1 - bool - help - Set if we're building for Gecko Series 1 SoC. - This is equivalent of _SILICON_LABS_32B_SERIES_1 definition in HAL - code. - -config SOC_GECKO_SERIES2 - bool - help - Set if we're building for Gecko Series 2 SoC. - This is equivalent of _SILICON_LABS_32B_SERIES_2 definition in HAL - code. - -config SOC_GECKO_BURTC - bool - help - Set if the Back-Up Real Time Counter (BURTC) HAL module is used. - -config SOC_GECKO_CORE - bool - default y - help - Set if the Core interrupt handling (CORE) HAL module is used. - -config SOC_GECKO_ADC - bool - help - Set if the Analog to Digital Converter (ADC) HAL module is used. - -config SOC_GECKO_IADC - bool - help - Set if the Incremental Analog to Digital Converter (IADC) HAL module is used. - -config SOC_GECKO_CRYOTIMER - bool - help - Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used. - -config SOC_GECKO_EMU - bool - help - Set if the Energy Management Unit (EMU) HAL module is used. - -config SOC_GECKO_GPIO - bool - help - Set if the General Purpose Input/Output (GPIO) HAL module is used. - -config SOC_GECKO_I2C - bool - help - Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used. - -config SOC_GECKO_LETIMER - bool - help - Set if the Low Energy Timer (LETIMER) HAL module is used. - -config SOC_GECKO_LEUART - bool - help - Set if the Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) - HAL module is used. - -config SOC_GECKO_MSC - bool - help - Set if the Memory System Controller (MSC) HAL module is used. - -config SOC_GECKO_PRS - bool - help - Set if the Peripheral Reflex System (PRS) HAL module is used. - -config SOC_GECKO_RMU - bool - help - Set if the Reset Management Unit (RMU) HAL module is used. - -config SOC_GECKO_RTC - bool - help - Set if the Real Time Counter (RTC) HAL module is used. - -config SOC_GECKO_RTCC - bool - help - Set if the Real Time Counter and Calendar (RTCC) HAL module is used. - -config SOC_GECKO_SE - bool - help - Set if the Secure Element (SE) HAL module is used. - -config SOC_GECKO_TIMER - bool - help - Set if the Timer/Counter (TIMER) HAL module is used. - -config SOC_GECKO_USART - bool - help - Set if the Universal Synchronous Asynchronous Receiver/Transmitter (USART) - HAL module is used. - -config SOC_GECKO_WDOG - bool - help - Set if the Watchdog Timer (WDOG) HAL module is used. - -config SOC_GECKO_TRNG - bool - help - Set if the SoC has a True Random Number Generator (TRNG) module. - -if PM - -config SOC_GECKO_PM_BACKEND_PMGR - bool - depends on SOC_GECKO_DEV_INIT - default y if SOC_GECKO_SERIES2 - help - Implement PM using sl_power_manager service from Gecko SDK - -config SOC_GECKO_PM_BACKEND_EMU - bool - default y if !SOC_GECKO_PM_BACKEND_PMGR - help - Implement PM using direct calls to EMU driver in emlib - -endif - -config SOC_GECKO_EMU_DCDC - bool "SoC DC/DC regulator" - select SOC_GECKO_EMU - help - Enable the on chip DC/DC regulator - -choice SOC_GECKO_EMU_DCDC_MODE - prompt "DC/DC mode" - depends on SOC_GECKO_EMU_DCDC - help - Select power configuration mode of the on chip DC/DC converter. - - config SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED - bool "Initial / Unconfigured" - - config SOC_GECKO_EMU_DCDC_MODE_ON - bool "DC/DC On" - - config SOC_GECKO_EMU_DCDC_MODE_OFF - bool "DC/DC Off" - - config SOC_GECKO_EMU_DCDC_MODE_BYPASS - bool "Bypass" -endchoice - -config CRYPTO_ACC_GECKO_TRNG - bool - help - Enable Entropy driver based on the CRYPTO_ACC module for Silicon Labs - Gecko chips. - -config SOC_GECKO_DEV_INIT - bool - help - Use the device initialization routines from the device_init service - in Silicon Labs HAL. These routines initialize and tune HFXOs, - configures DPLLs and manages the Energy Management Unit. - - Disabling these services may negatively impact counter and timer - routines in EXX32 series SoCs. - -config COUNTER_GECKO_STIMER - bool - help - Enable counter driver based on the Sleep Timer driver for Silicon Labs - Gecko chips. - -config SOC_GECKO_CMU - bool - help - Set if the clock management unit (CMU) is present in the SoC. - -if SOC_GECKO_CMU - -config CMU_NEED_LFXO - bool - help - Set if LFXO oscillator should be configured and enabled, potentially - in on-demand mode, after SoC is initialized. - -choice - prompt "High Frequency Clock Selection" - default CMU_HFCLK_HFXO - -config CMU_HFCLK_HFXO - bool "External high frequency crystal oscillator" - help - Set this option to use the external high frequency crystal oscillator - as high frequency clock. - -config CMU_HFCLK_LFXO - bool "External low frequency crystal oscillator" - select CMU_NEED_LFXO - help - Set this option to use the external low frequency crystal oscillator - as high frequency clock. - -config CMU_HFCLK_HFRCO - bool "Internal high frequency RC oscillator" - help - Set this option to use the internal high frequency RC oscillator as high frequency clock. - -endchoice - - -choice - prompt "BURTC Clock Selection" - depends on SOC_GECKO_BURTC - default CMU_BURTCCLK_LFRCO - -config CMU_BURTCCLK_LFXO - bool "LFXO - external low frequency crystal oscillator" - select CMU_NEED_LFXO - help - Set this option to use LFXO - the external low freqency crystal oscillator - as BURTC clock. - Frequency is set by external crystal, typically 32.768 kHz. - -config CMU_BURTCCLK_LFRCO - bool "LFRCO - internal low frequency RC oscillator" - help - Set this option to use LFRCO - the internal low freqency RC oscillator - as BURTC clock. - Frequency is approximately 32.768 kHz. - -config CMU_BURTCCLK_ULFRCO - bool "ULFRCO - internal ultra low frequency RC oscillator" - help - Set this option to use ULFRCO - the external low freqency crystal oscillator - as BURTC clock. - Frequency is approximately 1 kHz. - -endchoice - - -config CMU_HFXO_FREQ - int "External high frequency oscillator frequency" - help - Set the external high frequency oscillator frequency in Hz. This should be set by the - board's defconfig. - -config CMU_LFXO_FREQ - int "External low frequency oscillator frequency" - help - Set the external low frequency oscillator frequency in Hz. This should be set by the - board's defconfig. - -config CMU_HFRCO_FREQ - int "Internal high frequency RC oscillator frequency" - default 0 - depends on SOC_GECKO_HAS_HFRCO_FREQRANGE - help - Set the internal high frequency RC oscillator frequency in Hz. This should be set by the - board's defconfig. Only supported values may be used here. Setting this to 0, skips the - configuration of the high frequency RC oscillator completely. This may be desired, if - the bootloader already configured it properly or the device's default clock source should - be used with it's default configuration. - -endif # SOC_GECKO_CMU - -config SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - bool - help - If enabled, indicates that SoC allows to configure individual pin - locations. This is supported by e.g. efr32fg1p, efr32mg12p series. - If disabled, indicates that pin locations are configured in groups. - This is supported by e.g. efm32hg, efm32wg series. - -config SOC_GECKO_HAS_ERRATA_RTCC_E201 - bool - help - Set if the SoC is affected by errata RTCC_E201: - "When the RTCC is configured with a prescaler, the CCV1 top value enable - feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter - when RTCC_CNT is equal to RTCC_CC1_CCV, as intended." - -config SOC_GECKO_HAS_HFRCO_FREQRANGE - bool - help - If enabled, indicates that configuration of HFRCO frequency for this SOC is supported - via FREQRANGE field. This is supported for e.g. efr32fg1p, efr32mg12p series. - If disabled, indicates that configuration of HFRCO frequency for corresponding SOC - is not supported via this field. This is the case for e.g. efm32hg, efm32wg series. - -config SOC_GECKO_HAS_RADIO - bool - help - If enabled, indicates that the SoC has a Radio PHY. - -config SOC_GECKO_USE_RAIL - bool "Use RAIL (Radio Abstraction Interface Layer)" - depends on SOC_GECKO_HAS_RADIO - help - RAIL (Radio Abstraction Interface Layer) is a library needed to use the EFR radio - hardware. This option enable the proper set of features to allow to properly compile - with the RAIL blob. - -config SOC_GECKO_CUSTOM_RADIO_PHY - bool "Use RAIL for custom radio phy packet sending and receiving" - depends on SOC_GECKO_HAS_RADIO - select SOC_GECKO_USE_RAIL - help - If enabled, RAIL can be used for user generated custom radio phy - management, sending and receiving packets on radio phy. User has - to provide the radio_config.c and radio_config.h files for the phy. - -endif # SOC_FAMILY_EXX32 diff --git a/soc/arm/silabs_exx32/Kconfig.defconfig b/soc/arm/silabs_exx32/Kconfig.defconfig deleted file mode 100644 index 8f582653b3c8fa..00000000000000 --- a/soc/arm/silabs_exx32/Kconfig.defconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_EXX32 - -source "soc/arm/silabs_exx32/*/Kconfig.defconfig.series" - -config SOC_GECKO_EMU - default y - select SOC_GECKO_CORE - depends on PM - -config CORTEX_M_SYSTICK - default n if GECKO_BURTC_TIMER - -# With sl_power_manager, pm_state_set()'s stack footrpting is noticeably -# large, especially with logs enabled. Since it is called from IDLE task, -# its stack size has to be increased -config IDLE_STACK_SIZE - default 512 if SOC_GECKO_PM_BACKEND_PMGR - -endif diff --git a/soc/arm/silabs_exx32/Kconfig.soc b/soc/arm/silabs_exx32/Kconfig.soc deleted file mode 100644 index c5e43b652efc49..00000000000000 --- a/soc/arm/silabs_exx32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/silabs_exx32/*/Kconfig.series" diff --git a/soc/arm/silabs_exx32/common/pinctrl_soc.h b/soc/arm/silabs_exx32/common/pinctrl_soc.h deleted file mode 100644 index 8cfad9d4688391..00000000000000 --- a/soc/arm/silabs_exx32/common/pinctrl_soc.h +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Copyright (c) 2022 Silicon Labs - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * Silabs SoC specific helpers for pinctrl driver - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ - -#include - -#include -#if CONFIG_SOC_GECKO_SERIES1 -#include -#else -#include -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** @cond INTERNAL_HIDDEN */ - -/** Type for gecko pin. */ -typedef uint32_t pinctrl_soc_pin_t; - -/** - * @brief Utility macro to initialize each pin. - * - * @param node_id Node identifier. - * @param prop Property name. - * @param idx Property entry index. - */ -#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) (DT_PROP_BY_IDX(node_id, prop, idx)), - -/** - * @brief Utility macro to initialize state pins contained in a given property. - * - * @param node_id Node identifier. - * @param prop Property name describing state pins. - */ -#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ - { \ - DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \ - Z_PINCTRL_STATE_PIN_INIT) \ - } - -/** - * @brief Utility macro to obtain pin function. - * - * @param pincfg Pin configuration bit field. - */ -#define GECKO_GET_FUN(pincfg) (((pincfg) >> GECKO_FUN_POS) & GECKO_FUN_MSK) - -/** - * @brief Utility macro to obtain port configuration. - * - * @param pincfg port configuration bit field. - */ -#define GECKO_GET_PORT(pincfg) (((pincfg) >> GECKO_PORT_POS) & GECKO_PORT_MSK) - -/** - * @brief Utility macro to obtain pin configuration. - * - * @param pincfg pin configuration bit field. - */ -#define GECKO_GET_PIN(pincfg) (((pincfg) >> GECKO_PIN_POS) & GECKO_PIN_MSK) - -/** - * @brief Utility macro to obtain location configuration. - * - * @param pincfg Loc configuration bit field. - */ -#define GECKO_GET_LOC(pincfg) (((pincfg) >> GECKO_LOC_POS) & GECKO_LOC_MSK) - -/** - * @brief Utility macro to obtain speed configuration. - * - * @param pincfg speed configuration bit field. - */ -#define GECKO_GET_SPEED(pincfg) (((pincfg) >> GECKO_SPEED_POS) & GECKO_SPEED_MSK) - -/** @endcond */ - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/arm/silabs_exx32/common/soc.c b/soc/arm/silabs_exx32/common/soc.c deleted file mode 100644 index 0aab80ea06b4d3..00000000000000 --- a/soc/arm/silabs_exx32/common/soc.c +++ /dev/null @@ -1,247 +0,0 @@ -/* - * Copyright (c) 2018, Christian Taedcke - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Common SoC initialization for the EXX32 - */ - -#include -#include -#include - -#include -#include -#include -#include -#include - -#ifdef CONFIG_SOC_GECKO_DEV_INIT -#include -#include -#include -#include -#include - -#ifdef CONFIG_PM -#include -#include -#endif - -#endif - -LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); - -#ifdef CONFIG_CMU_HFCLK_HFXO -/** - * @brief Initialization parameters for the external high frequency oscillator - */ -static CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; -#endif - -#ifdef CONFIG_CMU_NEED_LFXO -/** - * @brief Initialization parameters for the external low frequency oscillator - */ -static CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; - -static void init_lfxo(void) -{ - /* - * Configuring LFXO disables it, so we can do that only if it's not - * used as a SYSCLK/HFCLK source. - */ -#if defined(_SILICON_LABS_32B_SERIES_2) - if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_LFXO) { - /* - * Check if device has LFXO configuration info in DEVINFO - * See AN0016.2 - */ - if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_LFXOCALVAL) == - DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { - lfxoInit.capTune = - (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) >> - _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT; - } - CMU_LFXOInit(&lfxoInit); - } -#else - if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO) { - CMU_LFXOInit(&lfxoInit); - CMU_OscillatorEnable(cmuOsc_LFXO, true, true); - } -#endif /* _SILICON_LABS_32B_SERIES_2 */ - SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ); -} - -#endif /* CONFIG_CMU_NEED_LFXO */ - -/** - * @brief Initialize the system clock - */ -static ALWAYS_INLINE void clock_init(void) -{ -#ifdef CONFIG_CMU_HFCLK_HFXO -#if defined(_SILICON_LABS_32B_SERIES_2) - if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_HFXO) { - /* - * Check if device has HFXO configuration info in DEVINFO - * See AN0016.2 - */ - if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_HFXOCALVAL) == - DEVINFO_MODULEINFO_HFXOCALVAL_VALID) { - hfxoInit.ctuneXoAna = - (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK) >> - _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT; - hfxoInit.ctuneXiAna = - (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) >> - _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT; - } - - CMU_HFXOInit(&hfxoInit); - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFXO); - } - - SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); -#else - if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) { - CMU_HFXOInit(&hfxoInit); - CMU_OscillatorEnable(cmuOsc_HFXO, true, true); - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); - } - SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); - CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); -#endif /* _SILICON_LABS_32B_SERIES_2 */ -#elif (defined CONFIG_CMU_HFCLK_LFXO) - /* LFXO should've been already brought up by init_lfxo() */ -#if defined(_SILICON_LABS_32B_SERIES_2) - CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_LFXO); -#else - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_LFXO); - CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); -#endif /* _SILICON_LABS_32B_SERIES_2 */ -#elif (defined CONFIG_CMU_HFCLK_HFRCO) - /* - * This is the default clock, the controller starts with - */ - -#ifdef CONFIG_SOC_GECKO_HAS_HFRCO_FREQRANGE - if (CONFIG_CMU_HFRCO_FREQ) { - /* Setting system HFRCO frequency */ - CMU_HFRCOBandSet(CONFIG_CMU_HFRCO_FREQ); - - /* Using HFRCO as high frequency clock, HFCLK */ - CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); - } -#endif -#else -#error "Unsupported clock source for HFCLK selected" -#endif - -#if defined(_SILICON_LABS_32B_SERIES_2) - /* Enable the High Frequency Peripheral Clock */ - CMU_ClockEnable(cmuClock_PCLK, true); -#else - /* Enable the High Frequency Peripheral Clock */ - CMU_ClockEnable(cmuClock_HFPER, true); -#endif /* _SILICON_LABS_32B_SERIES_2 */ - -#if defined(CONFIG_GPIO_GECKO) || defined(CONFIG_LOG_BACKEND_SWO) - CMU_ClockEnable(cmuClock_GPIO, true); -#endif -} - -#ifdef CONFIG_SOC_GECKO_EMU_DCDC -static ALWAYS_INLINE void dcdc_init(void) -{ -#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED) - /* Nothing to do, leave DC/DC converter in unconfigured, safe state. */ -#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON) || defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) - EMU_DCDCInit_TypeDef init_cfg = EMU_DCDCINIT_DEFAULT; -#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) - init_cfg.dcdcMode = emuDcdcMode_Bypass; -#endif - EMU_DCDCInit(&init_cfg); -#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_OFF) - EMU_DCDCPowerOff(); -#else -#error "Unsupported power configuration mode of the on chip DC/DC converter." -#endif -} -#endif - -#ifdef CONFIG_LOG_BACKEND_SWO -static void swo_init(void) -{ - struct soc_gpio_pin pin_swo = PIN_SWO; - -#if defined(_SILICON_LABS_32B_SERIES_2) - GPIO->TRACEROUTEPEN = GPIO_TRACEROUTEPEN_SWVPEN; -#else - /* Select HFCLK as the debug trace clock */ - CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; - -#if defined(_GPIO_ROUTEPEN_MASK) - /* Enable Serial wire output pin */ - GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN; - /* Set SWO location */ - GPIO->ROUTELOC0 = SWO_LOCATION << _GPIO_ROUTELOC0_SWVLOC_SHIFT; -#else - GPIO->ROUTE = GPIO_ROUTE_SWOPEN | (SWO_LOCATION << 8); -#endif -#endif /* _SILICON_LABS_32B_SERIES_2 */ - - GPIO_PinModeSet(pin_swo.port, pin_swo.pin, pin_swo.mode, pin_swo.out); -} -#endif /* CONFIG_LOG_BACKEND_SWO */ - -/** - * @brief Perform basic hardware initialization - * - * Initialize the interrupt controller device drivers. - * Also initialize the timer device driver, if required. - * - * @return 0 - */ -static int silabs_exx32_init(void) -{ - /* handle chip errata */ - CHIP_Init(); - -#ifdef CONFIG_CMU_NEED_LFXO - init_lfxo(); -#endif - -#ifdef CONFIG_SOC_GECKO_DEV_INIT - sl_device_init_dcdc(); - sl_device_init_hfxo(); - sl_device_init_dpll(); - sl_device_init_emu(); - -#ifdef CONFIG_PM - sl_power_manager_init(); - sl_hfxo_manager_init(); -#endif - -#else /* !CONFIG_SOC_GECKO_DEV_INIT */ - -#ifdef CONFIG_SOC_GECKO_EMU_DCDC - dcdc_init(); -#endif - - /* Initialize system clock according to CONFIG_CMU settings */ - clock_init(); - -#ifdef CONFIG_LOG_BACKEND_SWO - /* Configure SWO debug output */ - swo_init(); -#endif -#endif /* !CONFIG_SOC_GECKO_DEV_INIT */ - - return 0; -} - -SYS_INIT(silabs_exx32_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/silabs_exx32/common/soc_gpio.h b/soc/arm/silabs_exx32/common/soc_gpio.h deleted file mode 100644 index e030c3bc32eb74..00000000000000 --- a/soc/arm/silabs_exx32/common/soc_gpio.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (c) 2017 Christian Taedcke - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Silabs EXX32 MCU family General Purpose Input Output (GPIO) - * module HAL driver. - */ - -#ifndef _SILABS_EXX32_SOC_GPIO_H_ -#define _SILABS_EXX32_SOC_GPIO_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct soc_gpio_pin { - GPIO_Port_TypeDef port; /** GPIO port */ - unsigned int pin; /** GPIO pin on the port */ - GPIO_Mode_TypeDef mode; /** mode of the pin, e.g. gpioModeInput */ - unsigned int out; /** out register value */ -}; - -#ifdef __cplusplus -} -#endif - -#endif /* _SILABS_EXX32_SOC_GPIO_H_ */ diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b deleted file mode 100644 index da0d6b66b910db..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFM32GG-STK3701A platform configuration options -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y - depends on GPIO || LOG_BACKEND_SWO diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.series deleted file mode 100644 index 951969f99fbb98..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# EFM32GG11B series configuration options -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32GG11B - -config SOC_SERIES - default "efm32gg11b" - -config SOC_PART_NUMBER - default "EFM32GG11B820F2048GL192" if SOC_PART_NUMBER_EFM32GG11B820F2048GL192 - default "EFM32GG11B820F2048GM64" if SOC_PART_NUMBER_EFM32GG11B820F2048GM64 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 68 - -source "soc/arm/silabs_exx32/efm32gg11b/Kconfig.defconfig.efm32gg11b" - -endif # SOC_SERIES_EFM32GG11B diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.series b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.series deleted file mode 100644 index 34fa472c23d77d..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# EFM32GG11B MCU line -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32GG11B - bool "EFM32GG11B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select SOC_GECKO_SERIES1 - help - Enable support for EFM32 GiantGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.soc b/soc/arm/silabs_exx32/efm32gg11b/Kconfig.soc deleted file mode 100644 index 573989bd8773d8..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg11b/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# EFM32GG11B (Giant Gecko) MCU line -# Copyright (c) 2019 Interay Solutions B.V. -# Copyright (c) 2019 Oane Kingma -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32GG11B820F2048GL192 - bool - depends on SOC_SERIES_EFM32GG11B - -config SOC_PART_NUMBER_EFM32GG11B820F2048GM64 - bool - depends on SOC_SERIES_EFM32GG11B diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b deleted file mode 100644 index ce234528a584cb..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b +++ /dev/null @@ -1,7 +0,0 @@ -# Silicon Labs EFM32GG12B (Giant Gecko) platform configuration options -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y - depends on GPIO || LOG_BACKEND_SWO diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series deleted file mode 100644 index 469b30573109d0..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# EFM32GG12B series configuration options -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32GG12B - -config SOC_SERIES - default "efm32gg12b" - -config SOC_PART_NUMBER - default "EFM32GG12B810F1024GM64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 68 - -source "soc/arm/silabs_exx32/efm32gg12b/Kconfig.defconfig.efm32gg12b" - -endif # SOC_SERIES_EFM32GG12B diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.series b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.series deleted file mode 100644 index e8dcf52cf17a03..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# EFM32GG12B (Giant Gecko) MCU line -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32GG12B - bool "EFM32GG12B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select SOC_GECKO_SERIES1 - help - Enable support for EFM32 GiantGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc b/soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc deleted file mode 100644 index 72cdf1bf226a23..00000000000000 --- a/soc/arm/silabs_exx32/efm32gg12b/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# EFM32GG12B (Giant Gecko) MCU line -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32GG12B810F1024GM64 - bool - depends on SOC_SERIES_EFM32GG12B diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series deleted file mode 100644 index f854f0d99aec91..00000000000000 --- a/soc/arm/silabs_exx32/efm32hg/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# EFM32HG series configuration options - -# Copyright (c) 2018 Christian Taedcke -# Copyright (c) 2018 Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32HG - -config SOC_SERIES - default "efm32hg" - -config SOC_PART_NUMBER - default "EFM32HG322F64" if SOC_PART_NUMBER_EFM32HG322F64 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 20 - -endif # SOC_SERIES_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.series b/soc/arm/silabs_exx32/efm32hg/Kconfig.series deleted file mode 100644 index d17c24fbcdb286..00000000000000 --- a/soc/arm/silabs_exx32/efm32hg/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# EFM32HG MCU line - -# Copyright (c) 2018 Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32HG - bool "EFM32HG Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select SOC_FAMILY_EXX32 - select CPU_CORTEX_M_HAS_SYSTICK - select CPU_CORTEX_M_HAS_VTOR - select HAS_SILABS_GECKO - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES0 - help - Enable support for EFM32 Happy Gecko MCU series diff --git a/soc/arm/silabs_exx32/efm32hg/Kconfig.soc b/soc/arm/silabs_exx32/efm32hg/Kconfig.soc deleted file mode 100644 index 3c040b5bff15e2..00000000000000 --- a/soc/arm/silabs_exx32/efm32hg/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32HG (Happy Gecko) MCU line - -# Copyright (c) 2018 Marcio Montenegro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32HG322F64 - bool - depends on SOC_SERIES_EFM32HG diff --git a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32jg12b/Kconfig.defconfig.series deleted file mode 100644 index fd7d88352a155d..00000000000000 --- a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32JG12B series configuration options - -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32JG12B - -config SOC_SERIES - default "efm32jg12b" - -config SOC_PART_NUMBER - default "EFM32JG12B500F1024GL125" if SOC_PART_NUMBER_EFM32JG12B500F1024GL125 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 50 - -endif # SOC_SERIES_EFM32JG12B diff --git a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.series b/soc/arm/silabs_exx32/efm32jg12b/Kconfig.series deleted file mode 100644 index c82872f4eec06b..00000000000000 --- a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# EFM32JG12B MCU line - -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32JG12B - bool "EFM32JG12B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M3 - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_SERIES1 - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select HAS_PM - help - Enable support for EFM32 JadeGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.soc b/soc/arm/silabs_exx32/efm32jg12b/Kconfig.soc deleted file mode 100644 index d7644df075d4a2..00000000000000 --- a/soc/arm/silabs_exx32/efm32jg12b/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32JG12B (Jade Gecko) MCU line - -# Copyright (c) 2019 Lemonbeat GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32JG12B500F1024GL125 - bool - depends on SOC_SERIES_EFM32JG12B diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series deleted file mode 100644 index 33fe5a913abd49..00000000000000 --- a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32PG12B series configuration options - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32PG12B - -config SOC_SERIES - default "efm32pg12b" - -config SOC_PART_NUMBER - default "EFM32PG12B500F1024GL125" if SOC_PART_NUMBER_EFM32PG12B500F1024GL125 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 50 - -endif # SOC_SERIES_EFM32PG12B diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series deleted file mode 100644 index 0ab448b6fb7287..00000000000000 --- a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# EFM32PG12B MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32PG12B - bool "EFM32PG12B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_SERIES1 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select SOC_GECKO_ADC - select HAS_PM - help - Enable support for EFM32 PearlGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc b/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc deleted file mode 100644 index 94e499cd4d0d3e..00000000000000 --- a/soc/arm/silabs_exx32/efm32pg12b/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32PG12B (Pearl Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32PG12B500F1024GL125 - bool - depends on SOC_SERIES_EFM32PG12B diff --git a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.series deleted file mode 100644 index c65044482b3d60..00000000000000 --- a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32PG1B series configuration options - -# Copyright (c) 2020 Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32PG1B - -config SOC_SERIES - default "efm32pg1b" - -config SOC_PART_NUMBER - default "EFM32PG1B200F256GM48" if SOC_PART_NUMBER_EFM32PG1B200F256GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 34 - -endif # SOC_SERIES_EFM32PG1B diff --git a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.series b/soc/arm/silabs_exx32/efm32pg1b/Kconfig.series deleted file mode 100644 index 5a22fa2990844d..00000000000000 --- a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# EFM32PG1B MCU line - -# Copyright (c) 2020 Rafael Dias Menezes -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32PG1B - bool "EFM32PG1B Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFM32 PearlGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc b/soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc deleted file mode 100644 index b303eb9dc8e2d2..00000000000000 --- a/soc/arm/silabs_exx32/efm32pg1b/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32PG1B (Pearl Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32PG1B200F256GM48 - bool - depends on SOC_SERIES_EFM32PG1B diff --git a/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.series deleted file mode 100644 index 1d9bd93db5e283..00000000000000 --- a/soc/arm/silabs_exx32/efm32wg/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFM32WG series configuration options - -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFM32WG - -config SOC_SERIES - default "efm32wg" - -config SOC_PART_NUMBER - default "EFM32WG990F256" if SOC_PART_NUMBER_EFM32WG990F256 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 39 - -endif # SOC_SERIES_EFM32WG diff --git a/soc/arm/silabs_exx32/efm32wg/Kconfig.series b/soc/arm/silabs_exx32/efm32wg/Kconfig.series deleted file mode 100644 index 99dfba375d1e79..00000000000000 --- a/soc/arm/silabs_exx32/efm32wg/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# EFM32WG MCU line - -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFM32WG - bool "EFM32WG Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select HAS_SILABS_GECKO - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES0 - help - Enable support for EFM32 WonderGecko MCU series diff --git a/soc/arm/silabs_exx32/efm32wg/Kconfig.soc b/soc/arm/silabs_exx32/efm32wg/Kconfig.soc deleted file mode 100644 index 0c579f591c7cbb..00000000000000 --- a/soc/arm/silabs_exx32/efm32wg/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFM32WG (Wonder Gecko) MCU line - -# Copyright (c) 2017 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFM32WG990F256 - bool - depends on SOC_SERIES_EFM32WG diff --git a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series deleted file mode 100644 index 3d3ecc5a5b7900..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG13P - -config SOC_SERIES - default "efr32bg13p" - -config SOC_PART_NUMBER - default "EFR32BG13P632F512GM48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 47 - -endif # SOC_SERIES_EFR32BG13P diff --git a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.series b/soc/arm/silabs_exx32/efr32bg13p/Kconfig.series deleted file mode 100644 index f48d53d861e0a6..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# Silicon Labs EFR32BG13P (Blue Gecko) MCU - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32BG13P - bool "EFR32BG13P Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32BG13P Blue Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc b/soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc deleted file mode 100644 index e6ceb2f47c3d59..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg13p/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Silicon Labs EFR32BG13P (Blue Gecko) MCU series - -# Copyright (c) 2020 Piotr Mienkowski -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG13P - -config SOC_PART_NUMBER_EFR32BG13P632F512GM48 - bool - -endif # SOC_SERIES_EFR32BG13P diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22 b/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22 deleted file mode 100644 index 7600ace022b8ee..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22 +++ /dev/null @@ -1,7 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU configuration options - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.series deleted file mode 100644 index 377366c65f3c14..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.series +++ /dev/null @@ -1,24 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU configuration options - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG22 - -config SOC_SERIES - default "efr32bg22" - -config SOC_PART_NUMBER - default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 60 - -config PM - select COUNTER - select UART_INTERRUPT_DRIVEN - -source "soc/arm/silabs_exx32/efr32bg22/Kconfig.defconfig.efr32bg22" - -endif # SOC_SERIES_EFR32BG22 diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.series b/soc/arm/silabs_exx32/efr32bg22/Kconfig.series deleted file mode 100644 index 278f702ebac1f1..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32BG22 - bool "EFR32BG22P Series MCU" - select ARM - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_FPU - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select SOC_GECKO_GPIO - select SOC_GECKO_CMU - select SOC_GECKO_CORE - select SOC_GECKO_DEV_INIT - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32BG22 Blue Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32bg22/Kconfig.soc b/soc/arm/silabs_exx32/efr32bg22/Kconfig.soc deleted file mode 100644 index 51c8f0b7092938..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg22/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32BG22 (Blue Gecko) MCU series - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32BG22C224F512IM40 - bool - depends on SOC_SERIES_EFR32BG22 diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27 b/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27 deleted file mode 100644 index 6b33d3ea25e02a..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27 +++ /dev/null @@ -1,7 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.series deleted file mode 100644 index 9d010dba8242a5..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32BG27 - -config SOC_SERIES - default "efr32bg27" - -config SOC_PART_NUMBER - default "EFR32BG27C140F768IM40" if SOC_PART_NUMBER_EFR32BG27C140F768IM40 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 66 - -config PM - select COUNTER - -source "soc/arm/silabs_exx32/efr32bg27/Kconfig.defconfig.efr32bg27" - -endif # SOC_SERIES_EFR32BG27 diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.series b/soc/arm/silabs_exx32/efr32bg27/Kconfig.series deleted file mode 100644 index d826c4d121c370..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU - -# Copyright (c) Antmicro 2023 -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32BG27 - bool "EFR32BG27 Series MCU" - select ARM - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select CPU_CORTEX_M33 - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_HAS_FPU - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select SOC_GECKO_CMU - select SOC_GECKO_CORE - select SOC_GECKO_DEV_INIT - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32BG27 Blue Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32bg27/Kconfig.soc b/soc/arm/silabs_exx32/efr32bg27/Kconfig.soc deleted file mode 100644 index f2b9fe5b34270e..00000000000000 --- a/soc/arm/silabs_exx32/efr32bg27/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32BG27 (Blue Gecko) MCU series - -# Copyright (c) 2023 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32BG27C140F768IM40 - bool - depends on SOC_SERIES_EFR32BG27 diff --git a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32fg13p/Kconfig.defconfig.series deleted file mode 100644 index 2010356d363320..00000000000000 --- a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFR32FG13P series configuration options - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32FG13P - -config SOC_SERIES - default "efr32fg13p" - -config SOC_PART_NUMBER - default "EFR32FG13P233F512GM48" if SOC_PART_NUMBER_EFR32FG13P233F512GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 45 - -endif # SOC_SERIES_EFR32FG13P diff --git a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.series b/soc/arm/silabs_exx32/efr32fg13p/Kconfig.series deleted file mode 100644 index 11074d6f586fe8..00000000000000 --- a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.series +++ /dev/null @@ -1,25 +0,0 @@ -# EFR32FG13P MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32FG13P - bool "EFR32FG13P Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select SOC_GECKO_HAS_ERRATA_RTCC_E201 - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32 FlexGecko MCU series diff --git a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.soc b/soc/arm/silabs_exx32/efr32fg13p/Kconfig.soc deleted file mode 100644 index e79517fb536752..00000000000000 --- a/soc/arm/silabs_exx32/efr32fg13p/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFR32FG13P (Flex Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32FG13P233F512GM48 - bool - depends on SOC_SERIES_EFR32FG13P diff --git a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.series deleted file mode 100644 index cb47bf677b2b80..00000000000000 --- a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# EFR32FG1P series configuration options - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32FG1P - -config SOC_SERIES - default "efr32fg1p" - -config SOC_PART_NUMBER - default "EFR32FG1P133F256GM48" if SOC_PART_NUMBER_EFR32FG1P133F256GM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 33 - -endif # SOC_SERIES_EFR32FG1P diff --git a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.series b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.series deleted file mode 100644 index 8d453472de4bca..00000000000000 --- a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.series +++ /dev/null @@ -1,25 +0,0 @@ -# EFR32FG1P MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32FG1P - bool "EFR32FG1P Series MCU" - select ARM - select HAS_SILABS_GECKO - select HAS_SWO - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_GPIO - select SOC_GECKO_HAS_ERRATA_RTCC_E201 - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32 FlexGecko MCU series diff --git a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.soc b/soc/arm/silabs_exx32/efr32fg1p/Kconfig.soc deleted file mode 100644 index 212db5e6117509..00000000000000 --- a/soc/arm/silabs_exx32/efr32fg1p/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# EFR32FG1P (Flex Gecko) MCU line - -# Copyright (c) 2018 Christian Taedcke -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32FG1P133F256GM48 - bool - depends on SOC_SERIES_EFR32FG1P diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series deleted file mode 100644 index 6f20bfbe57e454..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# EFM32WG series configuration options - -# Copyright (c) 2018 Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32MG12P - -config SOC_SERIES - default "efr32mg12p" - -config SOC_PART_NUMBER - default "EFR32MG12P332F1024GL125" if SOC_PART_NUMBER_EFR32MG12P332F1024GL125 - default "EFR32MG12P432F1024GL125" if SOC_PART_NUMBER_EFR32MG12P432F1024GL125 - default "EFR32MG12P433F1024GM68" if SOC_PART_NUMBER_EFR32MG12P433F1024GM68 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 49 - -endif # SOC_SERIES_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series deleted file mode 100644 index 23426e8ce202e3..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# EFR32MG12P MCU line - -# Copyright (c) 2018 Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32MG12P - bool "EFR32MG12P Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION - select SOC_GECKO_HAS_HFRCO_FREQRANGE - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_TRNG - select HAS_PM - select SOC_GECKO_SERIES1 - help - Enable support for EFR32 Mighty Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc b/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc deleted file mode 100644 index b171553e638842..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg12p/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# EFR32MG12P (Mighty Gecko) MCU line - -# Copyright (c) 2018 Diego Sueiro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32MG12P332F1024GL125 - bool - depends on SOC_SERIES_EFR32MG12P - -config SOC_PART_NUMBER_EFR32MG12P433F1024GM68 - bool - depends on SOC_SERIES_EFR32MG12P - -config SOC_PART_NUMBER_EFR32MG12P432F1024GL125 - bool - depends on SOC_SERIES_EFR32MG12P diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21 b/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21 deleted file mode 100644 index 1844935f0155d7..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21 +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32MG21 (Mighty Gecko) MCU configuration options - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config GPIO_GECKO - default y - depends on GPIO || LOG_BACKEND_SWO diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.series deleted file mode 100644 index 61933d374f26a3..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Silicon Labs EFR32MG21 (Might Gecko) series configuration options - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32MG21 - -config SOC_SERIES - default "efr32mg21" - -config SOC_PART_NUMBER - default "EFR32MG21A020F1024IM32" if SOC_PART_NUMBER_EFR32MG21A020F1024IM32 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 61 - -source "soc/arm/silabs_exx32/efr32mg21/Kconfig.defconfig.efr32mg21" - -endif # SOC_SERIES_EFR32MG21 diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.series b/soc/arm/silabs_exx32/efr32mg21/Kconfig.series deleted file mode 100644 index 731658d29e348b..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.series +++ /dev/null @@ -1,26 +0,0 @@ -# Silicon Labs EFR32MG21 (Mighty Gecko) MCU - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32MG21 - bool "EFR32MG21 Series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_CORTEX_M_HAS_DWT - select ARMV8_M_DSP - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32MG21 Mighty Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32mg21/Kconfig.soc b/soc/arm/silabs_exx32/efr32mg21/Kconfig.soc deleted file mode 100644 index eb216bc355f93c..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg21/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Silicon Labs EFR32MG21 (Mighty Gecko) MCU line - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32MG21A020F1024IM32 - bool - depends on SOC_SERIES_EFR32MG21 diff --git a/soc/arm/silabs_exx32/efr32mg21/soc.h b/soc/arm/silabs_exx32/efr32mg21/soc.h deleted file mode 100644 index 16117e9e62eb49..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg21/soc.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the EFR32MG21 SoC - * - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H - -#include - -#ifndef _ASMLANGUAGE - -#include - -#include "soc_pinmap.h" -#include "../common/soc_gpio.h" - - -#endif /* !_ASMLANGUAGE */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_H */ diff --git a/soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h b/soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h deleted file mode 100644 index 3ebef365a3248d..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg21/soc_pinmap.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Silabs EFR32MG21 MCU pin definitions. - * - * This file contains pin configuration data required by different MCU - * modules to correctly configure GPIO controller. - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_ -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_ - -#include - -#ifdef CONFIG_LOG_BACKEND_SWO -#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } -#endif /* CONFIG_LOG_BACKEND_SWO */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG21_SOC_PINMAP_H_ */ diff --git a/soc/arm/silabs_exx32/efr32mg24/Kconfig.defconfig.series b/soc/arm/silabs_exx32/efr32mg24/Kconfig.defconfig.series deleted file mode 100644 index ec3e460c3556b3..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg24/Kconfig.defconfig.series +++ /dev/null @@ -1,29 +0,0 @@ -# Silicon Labs EFR32MG24 (Mighty Gecko) MCU configuration options - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_EFR32MG24 - -config SOC_SERIES - default "efr32mg24" - -config SOC_PART_NUMBER - default "EFR32MG24B220F1536IM48" if SOC_PART_NUMBER_EFR32MG24B220F1536IM48 - default "EFR32MG24B310F1536IM48" if SOC_PART_NUMBER_EFR32MG24B310F1536IM48 - -config NUM_IRQS - # must be >= the highest interrupt number used - default 75 - -config PM - default n - select COUNTER - select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT - -choice PM_POLICY - default PM_POLICY_DEFAULT - depends on PM -endchoice - -endif # SOC_SERIES_EFR32MG24 diff --git a/soc/arm/silabs_exx32/efr32mg24/Kconfig.series b/soc/arm/silabs_exx32/efr32mg24/Kconfig.series deleted file mode 100644 index a57d2237b3d03f..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg24/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Silicon Labs EFR32MG24 (Mighty Gecko) MCU - -# Copyright (c) 2021 Sateesh Kotapati -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_EFR32MG24 - bool "EFR32MG24 Series MCU" - select ARM - select CPU_CORTEX_M33 - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - select CPU_HAS_ARM_SAU - select CPU_CORTEX_M_HAS_DWT - select ARMV8_M_DSP - select ARM_TRUSTZONE_M - select SOC_FAMILY_EXX32 - select SOC_GECKO_HAS_RADIO - select SOC_GECKO_SERIES2 - select HAS_SILABS_GECKO - select HAS_SWO - select SOC_GECKO_CMU - select SOC_GECKO_EMU - select SOC_GECKO_GPIO - select SOC_GECKO_DEV_INIT - select SOC_GECKO_SE - select HAS_PM - help - Enable support for EFR32MG24 Mighty Gecko MCU series diff --git a/soc/arm/silabs_exx32/efr32mg24/Kconfig.soc b/soc/arm/silabs_exx32/efr32mg24/Kconfig.soc deleted file mode 100644 index 14d5c18d498d01..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg24/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Silicon Labs EFR32MG24 (Mighty Gecko) MCU line - -# Copyright (c) 2020 TriaGnoSys GmbH -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER_EFR32MG24B220F1536IM48 - bool - depends on SOC_SERIES_EFR32MG24 - -config SOC_PART_NUMBER_EFR32MG24B310F1536IM48 - bool - depends on SOC_SERIES_EFR32MG24 diff --git a/soc/arm/silabs_exx32/efr32mg24/soc.h b/soc/arm/silabs_exx32/efr32mg24/soc.h deleted file mode 100644 index a2fd5478c274a0..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg24/soc.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the EFR32MG24 SoC - * - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H - -#include - -#ifndef _ASMLANGUAGE - -#include - -#include "soc_pinmap.h" -#include "../common/soc_gpio.h" - -/* Add include for DTS generated information */ -#include - -#endif /* !_ASMLANGUAGE */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_H */ diff --git a/soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h b/soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h deleted file mode 100644 index 6961aeba60da5f..00000000000000 --- a/soc/arm/silabs_exx32/efr32mg24/soc_pinmap.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2020 TriaGnoSys GmbH - * SPDX-License-Identifier: Apache-2.0 - */ - -/** @file - * @brief Silabs EFR32MG24 MCU pin definitions. - * - * This file contains pin configuration data required by different MCU - * modules to correctly configure GPIO controller. - */ - -#ifndef ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_ -#define ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_ - -#include - -#ifdef CONFIG_LOG_BACKEND_SWO -#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } -#endif /* CONFIG_LOG_BACKEND_SWO */ - -#endif /* ZEPHYR_SOC_ARM_SILABS_EXX32_EFR32MG24_SOC_PINMAP_H_ */ diff --git a/soc/arm/soc.yml b/soc/arm/soc.yml new file mode 100644 index 00000000000000..c0b2456501e0cd --- /dev/null +++ b/soc/arm/soc.yml @@ -0,0 +1,33 @@ +family: +- name: arm + series: + - name: mps2 + socs: + - name: an385 + - name: an521 + cpuclusters: + - name: cpu0 + - name: cpu1 + - name: mps3 + socs: + - name: an547 + - name: musca + socs: + - name: musca_b1 + - name: musca_s1 + - name: designstart + socs: + - name: designstart_fpga_cortex_m1 + - name: designstart_fpga_cortex_m3 +- name: arm64 + series: + - name: fvp_aemv8a + socs: + - name: fvp_base_revc_2xaemv8a + - name: fvp_aemv8r + socs: + - name: fvp_aemv8r_aarch64 + - name: fvp_aemv8r_aarch32 + socs: + - name: qemu_cortex_a53 + - name: qemu_virt_arm64 diff --git a/soc/arm/st_stm32/CMakeLists.txt b/soc/arm/st_stm32/CMakeLists.txt deleted file mode 100644 index 639eff51a002f1..00000000000000 --- a/soc/arm/st_stm32/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) - -zephyr_include_directories(common) diff --git a/soc/arm/st_stm32/Kconfig b/soc/arm/st_stm32/Kconfig deleted file mode 100644 index dcdb22ca26b6d0..00000000000000 --- a/soc/arm/st_stm32/Kconfig +++ /dev/null @@ -1,29 +0,0 @@ -# ST Microelectronics STM32 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_STM32 - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select STM32_ENABLE_DEBUG_SLEEP_STOP if DEBUG || ZTEST - select BUILD_OUTPUT_HEX - -if SOC_FAMILY_STM32 - -config SOC_FAMILY - string - default "st_stm32" - -config STM32_ENABLE_DEBUG_SLEEP_STOP - bool "Allow debugger attach in stop/sleep Mode" - help - Some STM32 parts disable the DBGMCU in sleep/stop modes because - of power consumption. As a side-effects this prevents - debuggers from attaching w/o resetting the target. This - effectivly destroys the use-case of `west attach`. Also - SEGGER RTT and similar technologies need this. - -source "soc/arm/st_stm32/*/Kconfig.soc" - -endif # SOC_FAMILY_STM32 diff --git a/soc/arm/st_stm32/Kconfig.defconfig b/soc/arm/st_stm32/Kconfig.defconfig deleted file mode 100644 index b5232ae4579b6e..00000000000000 --- a/soc/arm/st_stm32/Kconfig.defconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/st_stm32/*/Kconfig.defconfig.series" diff --git a/soc/arm/st_stm32/Kconfig.soc b/soc/arm/st_stm32/Kconfig.soc deleted file mode 100644 index b9ea04e5b1c824..00000000000000 --- a/soc/arm/st_stm32/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# ST Microelectronics STM32 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/st_stm32/*/Kconfig.series" diff --git a/soc/arm/st_stm32/common/CMakeLists.txt b/soc/arm/st_stm32/common/CMakeLists.txt deleted file mode 100644 index af898951cc5f37..00000000000000 --- a/soc/arm/st_stm32/common/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(stm32cube_hal.c) - -zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld) - -zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c) -zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld) - -zephyr_sources(soc_config.c) - -if (NOT CONFIG_DEBUG AND CONFIG_PM) - zephyr_sources_ifdef(CONFIG_DT_HAS_SWJ_CONNECTOR_ENABLED pm_debug_swj.c) -endif() diff --git a/soc/arm/st_stm32/common/Kconfig.defconfig.series b/soc/arm/st_stm32/common/Kconfig.defconfig.series deleted file mode 100644 index 5b586516d83887..00000000000000 --- a/soc/arm/st_stm32/common/Kconfig.defconfig.series +++ /dev/null @@ -1,65 +0,0 @@ -# ST Microelectronics STM32 all MCU lines - -# Copyright (c) 2017, I-SENSE group of ICCS -# SPDX-License-Identifier: Apache-2.0 - -# Here are set all the Kconfig symbols common to the whole STM32 family - -if SOC_FAMILY_STM32 - -config CORTEX_M_SYSTICK - default n if STM32_LPTIM_TIMER - -DT_STM32_RCC_PATH := $(dt_nodelabel_path,rcc) -DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-frequency) - -DT_ST_PRESCALER := st,prescaler -DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source) - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" - -if LOG_BACKEND_SWO - -config LOG_BACKEND_SWO_REF_FREQ_HZ - default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" - -endif # LOG_BACKEND_SWO - -# set the tick per sec as a divider of the LPTIM clock source -# with a minimum value of 4096 for SYS_CLOCK_TICKS_PER_SEC to keep -# SYS_CLOCK_TICKS_PER_SEC not too high compared to the LPTIM counter clock -config SYS_CLOCK_TICKS_PER_SEC - default 4096 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 - default 2048 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 - default 1024 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 - default 512 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 - default 256 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 - depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSE - -config SYS_CLOCK_TICKS_PER_SEC - default 4000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 - default 2000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 - default 1000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 - default 500 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 - default 250 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 - depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSI - -choice STM32_LPTIM_CLOCK - default STM32_LPTIM_CLOCK_LSE if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 2 - default STM32_LPTIM_CLOCK_LSI if "$(dt_node_ph_array_prop_int,$(DT_STM32_LPTIM_PATH),clocks,1,bus)" = 3 -endchoice - -config CLOCK_CONTROL_STM32_CUBE - default y - depends on CLOCK_CONTROL - -config CLOCK_CONTROL_INIT_PRIORITY - default 1 - depends on CLOCK_CONTROL - -config MEMC_STM32 - default y - depends on MEMC - -endif # SOC_FAMILY_STM32 diff --git a/soc/arm/st_stm32/common/Kconfig.soc b/soc/arm/st_stm32/common/Kconfig.soc deleted file mode 100644 index 2fd9084cc55ab7..00000000000000 --- a/soc/arm/st_stm32/common/Kconfig.soc +++ /dev/null @@ -1,72 +0,0 @@ -# ST Microelectronics Common Kconfig - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_CCM := zephyr,ccm - -config STM32_CCM - def_bool $(dt_chosen_enabled,$(DT_CHOSEN_Z_CCM)) - -config STM32_BACKUP_SRAM - bool "STM32 Backup SRAM" - depends on DT_HAS_ST_STM32_BACKUP_SRAM_ENABLED - help - Enable support for STM32 backup SRAM. - -config USE_STM32_ASSERT - depends on ASSERT - bool "STM32Cube HAL and LL drivers asserts" - help - Enable asserts in STM32Cube HAL and LL drivers. - -config SWJ_ANALOG_PRIORITY - int "SWJ DP port to analog routine initialization priority" - default 49 - help - Initialization priority of the routine within the PRE_KERNEL1 level. - This priority must be greater than GPIO_INIT_PRIORITY and lower than - UART_INIT_PRIORITY. - -choice POWER_SUPPLY_CHOICE - prompt "STM32 power supply configuration" - default POWER_SUPPLY_LDO - depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32U5X || \ - SOC_STM32WBA55XX - -config POWER_SUPPLY_LDO - bool "LDO supply" - -config POWER_SUPPLY_DIRECT_SMPS - bool "Direct SMPS supply" - -config POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO - bool "SMPS 1.8V supplies LDO (no external supply)" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO - bool "SMPS 2.5V supplies LDO (no external supply)" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO - bool "External SMPS 1.8V supply, supplies LDO" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO - bool "External SMPS 2.5V supply, supplies LDO" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT - bool "External SMPS 1.8V supply and bypass" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT - bool "External SMPS 2.5V supply and bypass" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -config POWER_SUPPLY_EXTERNAL_SOURCE - bool "Bypass" - depends on !SOC_SERIES_STM32U5X && !SOC_SERIES_STM32WBAX - -endchoice diff --git a/soc/arm/st_stm32/common/pm_debug_swj.c b/soc/arm/st_stm32/common/pm_debug_swj.c deleted file mode 100644 index 5897670e5f6ec4..00000000000000 --- a/soc/arm/st_stm32/common/pm_debug_swj.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2023 STMicroelectronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include - -#define SWJ_NODE DT_NODELABEL(swj_port) - -PINCTRL_DT_DEFINE(SWJ_NODE); - -const struct pinctrl_dev_config *swj_pcfg = PINCTRL_DT_DEV_CONFIG_GET(SWJ_NODE); - -/* - * Serial Wire / JTAG port pins are enabled as part of SoC default configuration. - * When debug access is not needed and in case power consumption performance is - * expected, configure matching pins to analog in order to save power. - */ - -static int swj_to_analog(void) -{ - int err; - - /* Set Serial Wire / JTAG port pins to analog mode */ - err = pinctrl_apply_state(swj_pcfg, PINCTRL_STATE_SLEEP); - if (err < 0) { - __ASSERT(0, "SWJ pinctrl setup failed"); - return err; - } - - return 0; -} - -/* Run this routine as the earliest pin configuration in the target, - * to avoid potential conflicts with devices accessing SWJ-DG pins for - * their own needs. - */ -SYS_INIT(swj_to_analog, PRE_KERNEL_1, CONFIG_SWJ_ANALOG_PRIORITY); diff --git a/soc/arm/st_stm32/stm32c0/CMakeLists.txt b/soc/arm/st_stm32/stm32c0/CMakeLists.txt deleted file mode 100644 index e02052e3946532..00000000000000 --- a/soc/arm/st_stm32/stm32c0/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.series deleted file mode 100644 index d4ee373c0914d5..00000000000000 --- a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# STMicroelectronics STM32C0 MCU line - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32C0X - -source "soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c0*" - -config SOC_SERIES - default "stm32c0" - -endif # SOC_SERIES_STM32C0X diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.series b/soc/arm/st_stm32/stm32c0/Kconfig.series deleted file mode 100644 index cc69099a6c6ec4..00000000000000 --- a/soc/arm/st_stm32/stm32c0/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# STMicroelectronics STM32C0 MCU series - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32C0X - bool "STM32C0x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_CORTEX_M_HAS_SYSTICK - help - Enable support for STM32C0 MCU series diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.soc b/soc/arm/st_stm32/stm32c0/Kconfig.soc deleted file mode 100644 index e54678aefffd2a..00000000000000 --- a/soc/arm/st_stm32/stm32c0/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# STMicroelectronics STM32C0 MCU line - -# Copyright (c) 2023 Benjamin Björnsson -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32C0x MCU Selection" - depends on SOC_SERIES_STM32C0X - -config SOC_STM32C031XX - bool "STM32C031XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f0/CMakeLists.txt b/soc/arm/st_stm32/stm32f0/CMakeLists.txt deleted file mode 100644 index 914e395d27a392..00000000000000 --- a/soc/arm/st_stm32/stm32f0/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -# The vector table must be placed at the start of SRAM -zephyr_linker_sources_ifdef(CONFIG_SRAM_VECTOR_TABLE - RAM_SECTIONS - SORT_KEY 0 - sram_vector_table.ld -) -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.series deleted file mode 100644 index c69b3116767ba2..00000000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.series +++ /dev/null @@ -1,23 +0,0 @@ -# ST Microelectronics STM32F0 MCU line - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F0 series - -if SOC_SERIES_STM32F0X - -source "soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f0*" - -config SOC_SERIES - default "stm32f0" - -config SRAM_VECTOR_TABLE - default y - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 100 - -endif # SOC_SERIES_STM32F0X diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x4 b/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x4 deleted file mode 100644 index 28616f29a2c747..00000000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x4 +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2019 Antony Pavlov -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F030X4 - -# STM32F0 Cube package advises to use 'stm32f030x6' code -# for both STM32F030x4 and STM32F030x6 SoC variants. -config SOC - default "stm32f030x6" - -config NUM_IRQS - default 28 - -endif # SOC_STM32F030X4 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.series b/soc/arm/st_stm32/stm32f0/Kconfig.series deleted file mode 100644 index ac4e6ced15facf..00000000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F0 MCU series - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F0X - bool "STM32F0x Series MCU" - select ARM - select CPU_CORTEX_M0 - select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP - select SOC_FAMILY_STM32 - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_STM32CUBE - help - Enable support for STM32F0 MCU series diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.soc b/soc/arm/st_stm32/stm32f0/Kconfig.soc deleted file mode 100644 index eb82615bb09664..00000000000000 --- a/soc/arm/st_stm32/stm32f0/Kconfig.soc +++ /dev/null @@ -1,46 +0,0 @@ -# ST Microelectronics STM32F0 MCU line - -# Copyright (c) 2017 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F0x MCU Selection" - depends on SOC_SERIES_STM32F0X - -config SOC_STM32F030X4 - bool "STM32F030X4" - -config SOC_STM32F030X6 - bool "STM32F030X6" - -config SOC_STM32F030X8 - bool "STM32F030X8" - -config SOC_STM32F030XC - bool "STM32F030XC" - -config SOC_STM32F031X6 - bool "STM32F031X6" - -config SOC_STM32F042X6 - bool "STM32F042X6" - -config SOC_STM32F051X8 - bool "STM32F051X8" - -config SOC_STM32F070XB - bool "STM32F070XB" - -config SOC_STM32F072X8 - bool "STM32F072X8" - -config SOC_STM32F072XB - bool "STM32F072XB" - -config SOC_STM32F091XC - bool "STM32F091XC" - -config SOC_STM32F098XX - bool "STM32F098XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f1/CMakeLists.txt b/soc/arm/st_stm32/stm32f1/CMakeLists.txt deleted file mode 100644 index e02052e3946532..00000000000000 --- a/soc/arm/st_stm32/stm32f1/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.series deleted file mode 100644 index 5a56f271009c7c..00000000000000 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32F1 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F1 series - -if SOC_SERIES_STM32F1X - -source "soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f1*" - -config SOC_SERIES - default "stm32f1" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -endif # SOC_SERIES_STM32F1X diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.series b/soc/arm/st_stm32/stm32f1/Kconfig.series deleted file mode 100644 index 7e9428cd9cae67..00000000000000 --- a/soc/arm/st_stm32/stm32f1/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F1 MCU series - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F1X - bool "STM32F1x Series MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select HAS_SWO - help - Enable support for STM32F1 MCU series diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.soc b/soc/arm/st_stm32/stm32f1/Kconfig.soc deleted file mode 100644 index 82f9b5100e51b1..00000000000000 --- a/soc/arm/st_stm32/stm32f1/Kconfig.soc +++ /dev/null @@ -1,59 +0,0 @@ -# ST Microelectronics STM32F1 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F1x MCU Selection" - depends on SOC_SERIES_STM32F1X - -config SOC_STM32F100XB - bool "STM32F100XB" - -config SOC_STM32F100XE - bool "STM32F100XE" - -config SOC_STM32F103XE - bool "STM32F103XE" - select SOC_STM32F10X_DENSITY_DEVICE - -config SOC_STM32F103XB - bool "STM32F103XB" - select SOC_STM32F10X_DENSITY_DEVICE - -config SOC_STM32F103X8 - bool "STM32F103X8" - select SOC_STM32F10X_DENSITY_DEVICE - -config SOC_STM32F105XB - bool "STM32F105XB" - select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - -config SOC_STM32F105XC - bool "STM32F105XC" - select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - -config SOC_STM32F107XC - bool "STM32F107XC" - select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - -endchoice - -config SOC_STM32F10X_DENSITY_DEVICE - bool - help - STM32F101xx, STM32F102xx, STM32F103xx: - * Low density Value line devices - * Medium density Value line devices - * High density Value line devices - * XL-density devices Value line devices - -config SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE - bool - help - Connectivity line devices are STM32F105xx and STM32F107xx - microcontrollers. They are intended for applications where - connectivity and real-time performances are required such as - industrial control, control panels for security applications, UPS or - home audio. For STM32F107xx also the Ethernet MAC is available. diff --git a/soc/arm/st_stm32/stm32f2/CMakeLists.txt b/soc/arm/st_stm32/stm32f2/CMakeLists.txt deleted file mode 100644 index e02052e3946532..00000000000000 --- a/soc/arm/st_stm32/stm32f2/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.series deleted file mode 100644 index 580d4d60084ac6..00000000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F2 MCU line - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F2 series - -if SOC_SERIES_STM32F2X - -source "soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f2*" - -config SOC_SERIES - default "stm32f2" - -endif # SOC_SERIES_STM32F2X diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f205xx b/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f205xx deleted file mode 100644 index 46b8acb5286197..00000000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.defconfig.stm32f205xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics stm32f205 MCU - -# Copyright (c) 2021 Manuel Forcen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F207XX - -config SOC - default "STM32F207xx" - -config NUM_IRQS - default 81 - -endif diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.series b/soc/arm/st_stm32/stm32f2/Kconfig.series deleted file mode 100644 index 8d2abe1bdfc0fd..00000000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32F2X MCU series - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F2X - bool "STM32F2x Series MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select HAS_SWO - select CPU_HAS_ARM_MPU - help - Enable support for stm32f2 MCU series diff --git a/soc/arm/st_stm32/stm32f2/Kconfig.soc b/soc/arm/st_stm32/stm32f2/Kconfig.soc deleted file mode 100644 index 5c6bd45373111a..00000000000000 --- a/soc/arm/st_stm32/stm32f2/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics stm32f2 MCU line - -# Copyright (c) 2018 qianfan Zhao -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F2X MCU Selection" - depends on SOC_SERIES_STM32F2X - -config SOC_STM32F207XX - bool "STM32F207XX" - -config SOC_STM32F205XX - bool "STM32F205XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f3/CMakeLists.txt b/soc/arm/st_stm32/stm32f3/CMakeLists.txt deleted file mode 100644 index e02052e3946532..00000000000000 --- a/soc/arm/st_stm32/stm32f3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.series deleted file mode 100644 index 3ed5fd99d14047..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F3 MCU line - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F3 series - -if SOC_SERIES_STM32F3X - -source "soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f3*" - -config SOC_SERIES - default "stm32f3" - -endif # SOC_SERIES_STM32F3X diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302x8 b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302x8 deleted file mode 100644 index 8de2724b831d26..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302x8 +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F302X8 MCU - -# Copyright (c) 2018 Seitz & Associates -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F302X8 - -config SOC - default "stm32f302x8" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F302X8 diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc deleted file mode 100644 index 5cf16dec891b67..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f302xc +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F302XC MCU - -# Copyright (c) 2022, SECO Spa -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F302XC - -config SOC - default "stm32f302xc" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F302XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303xe b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303xe deleted file mode 100644 index 93d98a16cae405..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303xe +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F303XC MCU - -# Copyright (c) 2020 Paul M. Bendixen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F303XE - -config SOC - default "stm32f303xe" - -config NUM_IRQS - default 85 - -endif # SOC_STM32F303XE diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f334x8 b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f334x8 deleted file mode 100644 index dfa82aafe94edc..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f334x8 +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F334X8 MCU - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F334X8 - -config SOC - default "stm32f334x8" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F334X8 diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f373xc b/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f373xc deleted file mode 100644 index 713506da309c7f..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f373xc +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32F373XC MCU - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F373XC - -config SOC - default "stm32f373xc" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F373XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.series b/soc/arm/st_stm32/stm32f3/Kconfig.series deleted file mode 100644 index aab81eb94a9e85..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32F3 MCU series - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F3X - bool "STM32F3x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select CPU_HAS_FPU - select HAS_STM32CUBE - select HAS_SWO - help - Enable support for STM32F3 MCU series diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.soc b/soc/arm/st_stm32/stm32f3/Kconfig.soc deleted file mode 100644 index 20af2538ba5272..00000000000000 --- a/soc/arm/st_stm32/stm32f3/Kconfig.soc +++ /dev/null @@ -1,39 +0,0 @@ -# ST Microelectronics STM32F3 MCU line - -# Copyright (c) 2016 RnDity Sp. z o.o. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F3x MCU Selection" - depends on SOC_SERIES_STM32F3X - -config SOC_STM32F302X8 - bool "STM32F302X8" - -config SOC_STM32F302XC - bool "STM32F302XC" - select CPU_HAS_ARM_MPU - -config SOC_STM32F303X8 - bool "STM32F303X8" - -config SOC_STM32F303XB - bool "STM32F303XB" - select CPU_HAS_ARM_MPU - -config SOC_STM32F303XC - bool "STM32F303XC" - select CPU_HAS_ARM_MPU - -config SOC_STM32F303XE - bool "STM32F303XE" - select CPU_HAS_ARM_MPU - -config SOC_STM32F334X8 - bool "STM32F334X8" - -config SOC_STM32F373XC - bool "STM32F373XC" - select CPU_HAS_ARM_MPU - -endchoice diff --git a/soc/arm/st_stm32/stm32f4/CMakeLists.txt b/soc/arm/st_stm32/stm32f4/CMakeLists.txt deleted file mode 100644 index 021708b9d02db1..00000000000000 --- a/soc/arm/st_stm32/stm32f4/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.series deleted file mode 100644 index 63725609480192..00000000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# ST Microelectronics STM32F4 MCU line - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F4 series - -if SOC_SERIES_STM32F4X - -source "soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f4*" - -config SOC_SERIES - default "stm32f4" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -if PM - -config COUNTER - default y - -config COUNTER_RTC_STM32_SUBSECONDS - default y if DT_HAS_ST_STM32_RTC_ENABLED - -config IDLE_STACK_SIZE - default 512 - -endif # PM - -endif # SOC_SERIES_STM32F4X diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f405xx b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f405xx deleted file mode 100644 index 2d516b61bc1ec4..00000000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f405xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST STM32F405XX MCU configuration options - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F405XG - -config SOC - default "stm32f405xx" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F405XG diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx deleted file mode 100644 index c63a7c0c6ab7bc..00000000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f407xx +++ /dev/null @@ -1,24 +0,0 @@ -# ST STM32F407XX MCU configuration options - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F407XE - -config SOC - default "stm32f407xx" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F407XE - -if SOC_STM32F407XG - -config SOC - default "stm32f407xx" - -config NUM_IRQS - default 82 - -endif # SOC_STM32F407XG diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412xx b/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412xx deleted file mode 100644 index f66b53c2296b9c..00000000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412xx +++ /dev/null @@ -1,34 +0,0 @@ -# ST STM32F412XX MCU configuration options - -# Copyright (c) 2021 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32F412CX - -config SOC - default "stm32f412cx" - -config NUM_IRQS - default 97 - -endif # SOC_STM32F412CX - -if SOC_STM32F412VX - -config SOC - default "stm32f412vx" - -config NUM_IRQS - default 97 - -endif # SOC_STM32F412VX - -if SOC_STM32F412ZX - -config SOC - default "stm32f412zx" - -config NUM_IRQS - default 97 - -endif # SOC_STM32F412ZX diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.series b/soc/arm/st_stm32/stm32f4/Kconfig.series deleted file mode 100644 index a4e65c97784e5a..00000000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# ST Microelectronics STM32F4 MCU series - -# Copyright (c) 2016 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F4X - bool "STM32F4x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select HAS_PM - help - Enable support for STM32F4 MCU series diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.soc b/soc/arm/st_stm32/stm32f4/Kconfig.soc deleted file mode 100644 index ff7dea082efc37..00000000000000 --- a/soc/arm/st_stm32/stm32f4/Kconfig.soc +++ /dev/null @@ -1,70 +0,0 @@ -# ST Microelectronics STM32F4 MCU line - -# Copyright (c) 2016 Linaro Limited. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F4x MCU Selection" - depends on SOC_SERIES_STM32F4X - -config SOC_STM32F401XC - bool "STM32F401XC" - -config SOC_STM32F401XE - bool "STM32F401XE" - -config SOC_STM32F405XG - bool "STM32F405XG" - -config SOC_STM32F407XE - bool "STM32F407XE" - -config SOC_STM32F407XG - bool "STM32F407XG" - -config SOC_STM32F410RX - bool "STM32F410RX" - -config SOC_STM32F411XE - bool "STM32F411XE" - -config SOC_STM32F412CX - bool "STM32F412CX" - -config SOC_STM32F412RX - bool "STM32F412RX" - -config SOC_STM32F412VX - bool "STM32F412VX" - -config SOC_STM32F412ZX - bool "STM32F412ZX" - -config SOC_STM32F413XX - bool "STM32F413XX" - -config SOC_STM32F415XX - bool "STM32F415XX" - -config SOC_STM32F417XX - bool "STM32F417XX" - -config SOC_STM32F423XX - bool "STM32F423XX" - -config SOC_STM32F427XX - bool "STM32F427XI" - -config SOC_STM32F429XX - bool "STM32F429XI" - -config SOC_STM32F437XX - bool "STM32F437XX" - -config SOC_STM32F446XX - bool "STM32F446XX" - -config SOC_STM32F469XX - bool "STM32F469XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32f7/CMakeLists.txt b/soc/arm/st_stm32/stm32f7/CMakeLists.txt deleted file mode 100644 index e02052e3946532..00000000000000 --- a/soc/arm/st_stm32/stm32f7/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.series deleted file mode 100644 index 55af12c6678822..00000000000000 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32F7 MCU line - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32F7 series - -if SOC_SERIES_STM32F7X - -source "soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f7*" - -config SOC_SERIES - default "stm32f7" - -endif # SOC_SERIES_STM32F7X diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.series b/soc/arm/st_stm32/stm32f7/Kconfig.series deleted file mode 100644 index a298fa2b579d94..00000000000000 --- a/soc/arm/st_stm32/stm32f7/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# ST Microelectronics STM32F7 MCU series - -# Copyright (c) 2018 Yurii Hamann -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32F7X - bool "STM32F7x Series MCU" - select ARM - select CPU_CORTEX_M7 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - help - Enable support for STM32F7 MCU series diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.soc b/soc/arm/st_stm32/stm32f7/Kconfig.soc deleted file mode 100644 index c83a9962a604cc..00000000000000 --- a/soc/arm/st_stm32/stm32f7/Kconfig.soc +++ /dev/null @@ -1,43 +0,0 @@ -# ST Microelectronics STM32F7 MCU line - -# Copyright (c) 2018 Yurii Hamann -# Copyright (c) 2022, Rtone. -# Copyright (c) 2023, Rahul Arasikere. -# Copyright (c) 2023 Evan Perry Grove -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32F7x MCU Selection" - depends on SOC_SERIES_STM32F7X - -config SOC_STM32F722XX - bool "STM32F722XX" - -config SOC_STM32F723XX - bool "STM32F723XX" - -config SOC_STM32F745XX - bool "STM32F745XX" - -config SOC_STM32F746XX - bool "STM32F746XX" - -config SOC_STM32F756XX - bool "STM32F756XX" - -config SOC_STM32F750XX - bool "STM32F750XX" - -config SOC_STM32F765XX - bool "STM32F765XX" - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32F767XX - bool "STM32F767XX" - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32F769XX - bool "STM32F769XX" - select CPU_HAS_FPU_DOUBLE_PRECISION - -endchoice diff --git a/soc/arm/st_stm32/stm32g0/CMakeLists.txt b/soc/arm/st_stm32/stm32g0/CMakeLists.txt deleted file mode 100644 index 85869a31ddfc6b..00000000000000 --- a/soc/arm/st_stm32/stm32g0/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 G-Technologies Sdn. Bhd. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series deleted file mode 100644 index 1fc5e19565a504..00000000000000 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# STMicroelectronics STM32G0 MCU line - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# Copyright (c) 2021 G-Technologies Sdn. Bhd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32G0X - -source "soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0*" - -config SOC_SERIES - default "stm32g0" - -endif # SOC_SERIES_STM32G0X diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.series b/soc/arm/st_stm32/stm32g0/Kconfig.series deleted file mode 100644 index acdb926ef61df1..00000000000000 --- a/soc/arm/st_stm32/stm32g0/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# STMicroelectronics STM32G0 MCU series - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32G0X - bool "STM32G0x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select CPU_HAS_ARM_MPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_PM - help - Enable support for STM32G0 MCU series diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.soc b/soc/arm/st_stm32/stm32g0/Kconfig.soc deleted file mode 100644 index 592290e2fb9aa9..00000000000000 --- a/soc/arm/st_stm32/stm32g0/Kconfig.soc +++ /dev/null @@ -1,48 +0,0 @@ -# STMicroelectronics STM32G0 MCU line - -# Copyright (c) 2019 Philippe Retornaz -# Copyright (c) 2019 STMicroelectronics -# Copyright (c) 2020 Thomas Stranger -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32G0x MCU Selection" - depends on SOC_SERIES_STM32G0X - -config SOC_STM32G030XX - bool "STM32G030XX" - -config SOC_STM32G031XX - bool "STM32G031XX" - -config SOC_STM32G041XX - bool "STM32G041XX" - -config SOC_STM32G050XX - bool "STM32G050XX" - -config SOC_STM32G051XX - bool "STM32G051XX" - -config SOC_STM32G061XX - bool "STM32G061XX" - -config SOC_STM32G070XX - bool "STM32G070XX" - -config SOC_STM32G071XX - bool "STM32G071XX" - -config SOC_STM32G081XX - bool "STM32G081XX" - -config SOC_STM32G0B0XX - bool "STM32G0B0XX" - -config SOC_STM32G0B1XX - bool "STM32G0B1XX" - -config SOC_STM32G0C1XX - bool "STM32G0C1XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32g4/CMakeLists.txt b/soc/arm/st_stm32/stm32g4/CMakeLists.txt deleted file mode 100644 index 04911a6a2e47bd..00000000000000 --- a/soc/arm/st_stm32/stm32g4/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series deleted file mode 100644 index 14ca585fc11f88..00000000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# STMicroelectronics STM32G4 MCU line - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32G4X - -source "soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4*" - -config SOC_SERIES - default "stm32g4" - -if PM -config PM_DEVICE - default y - -config STM32_LPTIM_TIMER - default y -endif # PM - -endif # SOC_SERIES_STM32G4X diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb deleted file mode 100644 index 90a68ce0b6d1ab..00000000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g431rb +++ /dev/null @@ -1,14 +0,0 @@ -# STMicroelectronics STM32G431RB MCU - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32G431XX - -config SOC - default "stm32g431xx" - -config NUM_IRQS - default 102 - -endif # SOC_STM32G431XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g474re b/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g474re deleted file mode 100644 index 78bca517cc13eb..00000000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g474re +++ /dev/null @@ -1,14 +0,0 @@ -# STMicroelectronics STM32G474RE MCU - -# Copyright (c) 2019 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32G474XX - -config SOC - default "stm32g474xx" - -config NUM_IRQS - default 102 - -endif # SOC_STM32G474XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.series b/soc/arm/st_stm32/stm32g4/Kconfig.series deleted file mode 100644 index f04432c3ee301b..00000000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# STMicroelectronics STM32G4 MCU series - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32G4X - bool "STM32G4x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL - select HAS_PM - select HAS_SWO - help - Enable support for STM32G4 MCU series diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.soc b/soc/arm/st_stm32/stm32g4/Kconfig.soc deleted file mode 100644 index 9868522fc31131..00000000000000 --- a/soc/arm/st_stm32/stm32g4/Kconfig.soc +++ /dev/null @@ -1,34 +0,0 @@ -# STMicroelectronics STM32G4 MCU line - -# Copyright (c) 2019 Richard Osterloh -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32G4x MCU Selection" - depends on SOC_SERIES_STM32G4X - -config SOC_STM32G4A1XX - bool "STM32G4A1XX" - -config SOC_STM32G431XX - bool "STM32G431XX" - -config SOC_STM32G441XX - bool "STM32G441XX" - -config SOC_STM32G473XX - bool "STM32G473XX" - -config SOC_STM32G474XX - bool "STM32G474XX" - -config SOC_STM32G483XX - bool "STM32G483XX" - -config SOC_STM32G484XX - bool "STM32G484XX" - -config SOC_STM32G491XX - bool "STM32G491XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32g4/soc.c b/soc/arm/st_stm32/stm32g4/soc.c deleted file mode 100644 index 94600c48327dd5..00000000000000 --- a/soc/arm/st_stm32/stm32g4/soc.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2019 Richard Osterloh - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief System/hardware module for STM32G4 processor - */ - -#include -#include -#include - -#include -#if defined(PWR_CR3_UCPD_DBDIS) -#include -#include -#endif /* PWR_CR3_UCPD_DBDIS */ - -/** - * @brief Perform basic hardware initialization at boot. - * - * This needs to be run from the very beginning. - * So the init priority has to be 0 (zero). - * - * @return 0 - */ -static int stm32g4_init(void) -{ - /* Update CMSIS SystemCoreClock variable (HCLK) */ - /* At reset, system core clock is set to 16 MHz from HSI */ - SystemCoreClock = 16000000; - - /* allow reflashing board */ - LL_DBGMCU_EnableDBGSleepMode(); - -#if defined(PWR_CR3_UCPD_DBDIS) - /* Disable USB Type-C dead battery pull-down behavior */ - LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); - LL_PWR_DisableUCPDDeadBattery(); -#endif /* PWR_CR3_UCPD_DBDIS */ - return 0; -} - -SYS_INIT(stm32g4_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32h5/CMakeLists.txt b/soc/arm/st_stm32/stm32h5/CMakeLists.txt deleted file mode 100644 index e02052e3946532..00000000000000 --- a/soc/arm/st_stm32/stm32h5/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series deleted file mode 100644 index 201694ed708a12..00000000000000 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32H5 MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32H5X - -source "soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h5*" - -config SOC_SERIES - default "stm32h5" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -endif # SOC_SERIES_STM32H5X diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.series b/soc/arm/st_stm32/stm32h5/Kconfig.series deleted file mode 100644 index cb84b08b250539..00000000000000 --- a/soc/arm/st_stm32/stm32h5/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32H5 MCU series - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32H5X - bool "STM32H5x Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M if !SOC_STM32H503XX - select CPU_HAS_ARM_SAU if !SOC_STM32H503XX - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select HAS_SWO - help - Enable support for STM32H5 MCU series diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.soc b/soc/arm/st_stm32/stm32h5/Kconfig.soc deleted file mode 100644 index 3bf6a3605c0ea6..00000000000000 --- a/soc/arm/st_stm32/stm32h5/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# ST Microelectronics STM32H5 MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32H5x MCU Selection" -depends on SOC_SERIES_STM32H5X - -config SOC_STM32H503XX - bool "STM32H503XX" - -config SOC_STM32H562XX - bool "STM32H562XX" - -config SOC_STM32H563XX - bool "STM32H563XX" - -config SOC_STM32H573XX - bool "STM32H573XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32h7/CMakeLists.txt b/soc/arm/st_stm32/stm32h7/CMakeLists.txt deleted file mode 100644 index d1ae6c3325da1e..00000000000000 --- a/soc/arm/st_stm32/stm32h7/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c) -zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c) - -zephyr_sources(mpu_regions.c) -zephyr_linker_sources(SECTIONS sections.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series deleted file mode 100644 index 14e35234ea1887..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32H7 MCU line - -# Copyright (c) 2019 Linaro Limited -# Copyright (c) 2022 SILA Embedded Solutions GmbH -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32H7 series - -if SOC_SERIES_STM32H7X - -source "soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7*" - -config SOC_SERIES - default "stm32h7" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - default 0x0 if !BOOTLOADER_MCUBOOT - -endif # SOC_SERIES_STM32H7X diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h745xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h745xx deleted file mode 100644 index c6279b99028ff3..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h745xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST STM32H745X MCU configuration options - -# Copyright (c) 2020 Alexander Kozhinov -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H745XX - -config SOC - default "stm32h745xx" - -config NUM_IRQS - default 150 - -endif # SOC_STM32H745XX diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx deleted file mode 100644 index 73b7c9ea7cec25..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h747xx +++ /dev/null @@ -1,14 +0,0 @@ -# ST STM32H747X MCU configuration options - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H747XX - -config SOC - default "stm32h747xx" - -config NUM_IRQS - default 150 - -endif # SOC_STM32H747XX diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7a3xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7a3xx deleted file mode 100644 index e82faa90bda0c2..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7a3xx +++ /dev/null @@ -1,15 +0,0 @@ -# ST STM32H7A3X MCU configuration options - -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H7A3XX || SOC_STM32H7A3XXQ - -config SOC - default "stm32h7a3xxQ" if SOC_STM32H7A3XXQ - default "stm32h7a3xx" if SOC_STM32H7A3XX - -config NUM_IRQS - default 155 - -endif # SOC_STM32H7A3XX || SOC_STM32H7A3XXQ diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx deleted file mode 100644 index 105021350149c8..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b0xx +++ /dev/null @@ -1,15 +0,0 @@ -# ST STM32H7B0XX MCU configuration options - -# Copyright (c) 2023 Charles Dias -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H7B0XX || SOC_STM32H7B0XXQ - -config SOC - default "stm32h7b0xxQ" if SOC_STM32H7B0XXQ - default "stm32h7b0xx" if SOC_STM32H7B0XX - -config NUM_IRQS - default 155 - -endif # SOC_STM32H7B0XX || SOC_STM32H7B0XXQ diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b3xx b/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b3xx deleted file mode 100644 index 941c6ad5e50233..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h7b3xx +++ /dev/null @@ -1,15 +0,0 @@ -# ST STM32H7B3X MCU configuration options - -# Copyright (c) 2022 Byte-Lab d.o.o -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32H7B3XX || SOC_STM32H7B3XXQ - -config SOC - default "stm32h7b3xxQ" if SOC_STM32H7B3XXQ - default "stm32h7b3xx" if SOC_STM32H7B3XX - -config NUM_IRQS - default 155 - -endif # SOC_STM32H7B3XX || SOC_STM32H7B3XXQ diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.series b/soc/arm/st_stm32/stm32h7/Kconfig.series deleted file mode 100644 index 061a23856c2bad..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# ST Microelectronics STM32H7 MCU series - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32H7X - bool "STM32H7x Series MCU" - select ARM - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select USE_STM32_HAL_CORTEX - select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS - help - Enable support for STM32H7 MCU series diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.soc b/soc/arm/st_stm32/stm32h7/Kconfig.soc deleted file mode 100644 index 4f7441a6fdcf56..00000000000000 --- a/soc/arm/st_stm32/stm32h7/Kconfig.soc +++ /dev/null @@ -1,132 +0,0 @@ -# ST Microelectronics STM32H7 MCU line - -# Copyright (c) 2019 Linaro Limited -# Copyright (c) 2020 Teslabs Engineering S.L. -# Copyright (c) 2021 Electrolance Solutions -# SPDX-License-Identifier: Apache-2.0 - -config STM32H7_DUAL_CORE - bool "Dual Core" - depends on SOC_SERIES_STM32H7X - -choice - prompt "STM32H7x MCU Selection" - depends on SOC_SERIES_STM32H7X - -config SOC_STM32H723XX - bool "STM32H723XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H725XX - bool "STM32H725XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H730XX - bool "STM32H730XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H730XXQ - bool "STM32H730XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H735XX - bool "STM32H735XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H743XX - bool "STM32H743XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H745XX - bool "STM32H745XX" - select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 - select CPU_HAS_ICACHE if CPU_CORTEX_M7 - select CPU_HAS_DCACHE if CPU_CORTEX_M7 - select STM32H7_DUAL_CORE - -config SOC_STM32H747XX - bool "STM32H747XX" - select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 - select CPU_HAS_ICACHE if CPU_CORTEX_M7 - select CPU_HAS_DCACHE if CPU_CORTEX_M7 - select STM32H7_DUAL_CORE - -config SOC_STM32H750XX - bool "STM32H750XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H753XX - bool "STM32H753XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7A3XX - bool "STM32H7A3XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7A3XXQ - bool "STM32H7A3XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B0XX - bool "STM32H7B0XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B0XXQ - bool "STM32H7B0XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B3XX - bool "STM32H7B3XX" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -config SOC_STM32H7B3XXQ - bool "STM32H7B3XXQ" - select CPU_CORTEX_M7 - select CPU_HAS_ICACHE - select CPU_HAS_DCACHE - select CPU_HAS_FPU_DOUBLE_PRECISION - -endchoice - -config STM32H7_BOOT_M4_AT_INIT - bool "Boot M4 core during M7 init independent of option byte BCM4." - default y diff --git a/soc/arm/st_stm32/stm32l0/CMakeLists.txt b/soc/arm/st_stm32/stm32l0/CMakeLists.txt deleted file mode 100644 index 0fd5073770d301..00000000000000 --- a/soc/arm/st_stm32/stm32l0/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.series deleted file mode 100644 index 1f9dbd9333870d..00000000000000 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32L0 MCU line - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32L0 series - -if SOC_SERIES_STM32L0X - -source "soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l0*" - -config SOC_SERIES - default "stm32l0" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -endif # SOC_SERIES_STM32L0X diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.series b/soc/arm/st_stm32/stm32l0/Kconfig.series deleted file mode 100644 index 950c72d4aa7883..00000000000000 --- a/soc/arm/st_stm32/stm32l0/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L0 MCU series - -# Copyright (c) 2018 Endre Karlson -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L0X - bool "STM32L0x Series MCU" - select ARM - select CPU_CORTEX_M0PLUS - select CPU_CORTEX_M_HAS_VTOR - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_CORTEX_M_HAS_SYSTICK - select HAS_PM - help - Enable support for STM32L0 MCU series diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.soc b/soc/arm/st_stm32/stm32l0/Kconfig.soc deleted file mode 100644 index 0baab0cf2b981f..00000000000000 --- a/soc/arm/st_stm32/stm32l0/Kconfig.soc +++ /dev/null @@ -1,55 +0,0 @@ -# ST Microelectronics STM32L0 MCU line - -# Copyright (c) 2018 Endre Karlson -# Copyright (c) 2021 Nomono AS -# Copyright (c) 2023 OS Systems -# -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32L0x MCU Selection" - depends on SOC_SERIES_STM32L0X - -config SOC_STM32L010X4 - bool "STM32L010X4" - -config SOC_STM32L010X6 - bool "STM32L010X6" - -config SOC_STM32L010X8 - bool "STM32L010X8" - -config SOC_STM32L010XB - bool "STM32L010XB" - -config SOC_STM32L011XX - bool "STM32L011XX" - -config SOC_STM32L031XX - bool "STM32L031XX" - -config SOC_STM32L051XX - bool "STM32L051XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L053XX - bool "STM32L053XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L071XX - bool "STM32L071XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L072XX - bool "STM32L072XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L073XX - bool "STM32L073XX" - select CPU_HAS_ARM_MPU - -config SOC_STM32L081XX - bool "STM32L081XX" - select CPU_HAS_ARM_MPU - -endchoice diff --git a/soc/arm/st_stm32/stm32l1/CMakeLists.txt b/soc/arm/st_stm32/stm32l1/CMakeLists.txt deleted file mode 100644 index 68bf00e81c1eb3..00000000000000 --- a/soc/arm/st_stm32/stm32l1/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series deleted file mode 100644 index 873acabf34c66b..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# ST Microelectronics STM32L1 MCU line - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32L1X - -source "soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l1*" - -config SOC_SERIES - default "stm32l1" - -# adjust the fallback because of the LSI oscaillator characteristics -config TASK_WDT_HW_FALLBACK_DELAY - depends on TASK_WDT_HW_FALLBACK - default 200 - -endif # SOC_SERIES_STM32L1X diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151x8a b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151x8a deleted file mode 100644 index cebe7f6b32c101..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151x8a +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32L151X8-A MCU - -# Copyright (c) 2019 eTactica ehf -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151X8A - -config SOC - default "stm32l151x8a" - -config NUM_IRQS - default 45 - -endif # SOC_STM32L151X8A diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb deleted file mode 100644 index f86cb99e14b0c6..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xb +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32L151XB MCU - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151XB - -config SOC - default "stm32l151xb" - -config NUM_IRQS - default 45 - -endif # SOC_STM32L151XB diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xba b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xba deleted file mode 100644 index b93b1e9dd28e13..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xba +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32L151XB-A MCU - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151XBA - -config SOC - default "stm32l151xba" - -config NUM_IRQS - default 45 - -endif # SOC_STM32L151XBA diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xc b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xc deleted file mode 100644 index af0ce69ba01d23..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l151xc +++ /dev/null @@ -1,15 +0,0 @@ -# ST Microelectronics STM32L151XC MCU - -# Copyright (c) 2020 Abel Sensors -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L151XC - -config SOC - default "stm32l151xc" - -# Based on stm32cube number of interrupts+1, not datasheet -config NUM_IRQS - default 57 - -endif # SOC_STM32L151XC diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xc b/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xc deleted file mode 100644 index c0f87fe11ffe7c..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L152XC MCU - -# Copyright (c) 2020 Abel Sensors -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32L152XC - -config SOC - string - default "stm32l152xc" - -config NUM_IRQS - int - default 57 - -endif # SOC_STM32L152XC diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.series b/soc/arm/st_stm32/stm32l1/Kconfig.series deleted file mode 100644 index d21881d6128e86..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L1 MCU series - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L1X - bool "STM32L1x Series MCU" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select HAS_SWO - select CPU_HAS_ARM_MPU - help - Enable support for STM32L1 MCU series diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.soc b/soc/arm/st_stm32/stm32l1/Kconfig.soc deleted file mode 100644 index 07cffb5b3b05c6..00000000000000 --- a/soc/arm/st_stm32/stm32l1/Kconfig.soc +++ /dev/null @@ -1,28 +0,0 @@ -# ST Microelectronics STM32L1 MCU line - -# Copyright (c) 2019 Linaro Ltd. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32L1x MCU Selection" - depends on SOC_SERIES_STM32L1X - -config SOC_STM32L151X8A - bool "STM32L151X8A" - -config SOC_STM32L151XB - bool "STM32L151XB" - -config SOC_STM32L151XBA - bool "STM32L151XBA" - -config SOC_STM32L151XC - bool "STM32L151XC" - -config SOC_STM32L152XC - bool "STM32L152XC" - -config SOC_STM32L152XE - bool "STM32L152XE" - -endchoice diff --git a/soc/arm/st_stm32/stm32l4/CMakeLists.txt b/soc/arm/st_stm32/stm32l4/CMakeLists.txt deleted file mode 100644 index 94edc2622740f6..00000000000000 --- a/soc/arm/st_stm32/stm32l4/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.series deleted file mode 100644 index 481726f0b727de..00000000000000 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L4 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -# Kconfig symbols common to STM32L4 series - -if SOC_SERIES_STM32L4X - -source "soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4*" - -config SOC_SERIES - default "stm32l4" - -endif # SOC_SERIES_STM32L4X diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.series b/soc/arm/st_stm32/stm32l4/Kconfig.series deleted file mode 100644 index 6ac4f1e704ca7f..00000000000000 --- a/soc/arm/st_stm32/stm32l4/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32L4 MCU series - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L4X - bool "STM32L4x Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32L4 MCU series diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.soc b/soc/arm/st_stm32/stm32l4/Kconfig.soc deleted file mode 100644 index 9719ff4b73d9a2..00000000000000 --- a/soc/arm/st_stm32/stm32l4/Kconfig.soc +++ /dev/null @@ -1,70 +0,0 @@ -# ST Microelectronics STM32L4 MCU line - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 BayLibre, SAS -# Copyright (c) 2019 Centaur Analytics, Inc -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32L4x MCU Selection" - depends on SOC_SERIES_STM32L4X - -config SOC_STM32L476XX - bool "STM32L476XX" - -config SOC_STM32L486XX - bool "STM32L486XX" - -config SOC_STM32L496XX - bool "STM32L496XX" - -config SOC_STM32L4A6XX - bool "STM32L4A6XX" - -config SOC_STM32L412XX - bool "STM32L412XX" - -config SOC_STM32L422XX - bool "STM32L422XX" - -config SOC_STM32L431XX - bool "STM32L431XX" - -config SOC_STM32L432XX - bool "STM32L432XX" - -config SOC_STM32L433XX - bool "STM32L433XX" - -config SOC_STM32L451XX - bool "STM32L451XX" - -config SOC_STM32L452XX - bool "STM32L452XX" - -config SOC_STM32L462XX - bool "STM32L462XX" - -config SOC_STM32L475XX - bool "STM32L475XX" - -config SOC_STM32L4P5XX - bool "STM32L4P5XX" - -config SOC_STM32L4Q5XX - bool "STM32L4Q5XX" - -config SOC_STM32L4S5XX - bool "STM32L4S5XX" - -config SOC_STM32L4R5XX - bool "STM32L4R5XX" - -config SOC_STM32L4R9XX - bool "STM32L4R9XX" - -config SOC_STM32L471XX - bool "STM32L471XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32l5/CMakeLists.txt b/soc/arm/st_stm32/stm32l5/CMakeLists.txt deleted file mode 100644 index 0fd5073770d301..00000000000000 --- a/soc/arm/st_stm32/stm32l5/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.series deleted file mode 100644 index 0b92f5dda29b3e..00000000000000 --- a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32L5 MCU line - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32L5X - -source "soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l5*" - -config SOC_SERIES - default "stm32l5" - -endif # SOC_SERIES_STM32L5X diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.series b/soc/arm/st_stm32/stm32l5/Kconfig.series deleted file mode 100644 index ffee96473c3227..00000000000000 --- a/soc/arm/st_stm32/stm32l5/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# ST Microelectronics STM32L5 MCU series - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32L5X - bool "STM32L5x Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select HAS_PM - help - Enable support for STM32L5 MCU series diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.soc b/soc/arm/st_stm32/stm32l5/Kconfig.soc deleted file mode 100644 index c93746ca48873e..00000000000000 --- a/soc/arm/st_stm32/stm32l5/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32L5 MCU line - -# Copyright (c) 2020 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32L5x MCU Selection" -depends on SOC_SERIES_STM32L5X - -config SOC_STM32L552XX - bool "STM32L552XX" - -config SOC_STM32L562XX - bool "STM32L562XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32mp1/CMakeLists.txt b/soc/arm/st_stm32/stm32mp1/CMakeLists.txt deleted file mode 100644 index 7805c0ffbf24f6..00000000000000 --- a/soc/arm/st_stm32/stm32mp1/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2019 STMicroelectronics -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series deleted file mode 100644 index 72c6b452c5d04d..00000000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32MP1 MCU/MPU line - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32MP1X - -source "soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4" - -config SOC_SERIES - default "stm32mp1" - -endif # SOC_SERIES_STM32MP1X diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4 b/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4 deleted file mode 100644 index 20dd43378f7f3b..00000000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.defconfig.stm32mp15_m4 +++ /dev/null @@ -1,14 +0,0 @@ -# ST Microelectronics STM32MP157C_M4 MCU - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_STM32MP15_M4 - -config SOC - default "stm32mp157cxx" - -config NUM_IRQS - default 150 - -endif # SOC_STM32MP15_M4 diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.series b/soc/arm/st_stm32/stm32mp1/Kconfig.series deleted file mode 100644 index c1576a7ee178b7..00000000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# ST Microelectronics STM32MP1 MPU series - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32MP1X - bool "STM32MP15 Series MPU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select OPENAMP_RSC_TABLE if RAM_CONSOLE - help - Enable support for STM32MP1 MPU series diff --git a/soc/arm/st_stm32/stm32mp1/Kconfig.soc b/soc/arm/st_stm32/stm32mp1/Kconfig.soc deleted file mode 100644 index 18e4202ae5f4ff..00000000000000 --- a/soc/arm/st_stm32/stm32mp1/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32MP1 MPU line - -# Copyright (c) 2019 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32MP1 MPU Selection" - depends on SOC_SERIES_STM32MP1X - -config SOC_STM32MP15_M4 - bool "STM32MP15_M4" - -endchoice diff --git a/soc/arm/st_stm32/stm32u5/CMakeLists.txt b/soc/arm/st_stm32/stm32u5/CMakeLists.txt deleted file mode 100644 index 94edc2622740f6..00000000000000 --- a/soc/arm/st_stm32/stm32u5/CMakeLists.txt +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series deleted file mode 100644 index e867bd5f4c9c38..00000000000000 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32U5 MCU line - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32U5X - -source "soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5*" - -config SOC_SERIES - default "stm32u5" - -config ROM_START_OFFSET - default 0x400 if BOOTLOADER_MCUBOOT - -endif # SOC_SERIES_STM32U5X diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.series b/soc/arm/st_stm32/stm32u5/Kconfig.series deleted file mode 100644 index 81094811b389fe..00000000000000 --- a/soc/arm/st_stm32/stm32u5/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# ST Microelectronics STM32U5 MCU series - -# Copyright (c) 2021 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32U5X - bool "STM32U5x Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32U5 MCU series diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.soc b/soc/arm/st_stm32/stm32u5/Kconfig.soc deleted file mode 100644 index ec8c964ad3ee80..00000000000000 --- a/soc/arm/st_stm32/stm32u5/Kconfig.soc +++ /dev/null @@ -1,30 +0,0 @@ -# ST Microelectronics STM32U5 MCU line - -# Copyright (c) 2021 Linaro Limited -# Copyright (c) 2023 PSICONTROL nv -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32U5x MCU Selection" -depends on SOC_SERIES_STM32U5X - -config SOC_STM32U575XX - bool "STM32U575XX" - -config SOC_STM32U585XX - bool "STM32U585XX" - -config SOC_STM32U595XX - bool "STM32U595XX" - -config SOC_STM32U599XX - bool "STM32U599XX" - -config SOC_STM32U5A5XX - bool "STM32U5A5XX" - -config SOC_STM32U5A9XX - bool "STM32U5A9XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32wb/CMakeLists.txt b/soc/arm/st_stm32/stm32wb/CMakeLists.txt deleted file mode 100644 index 32ce62ee53071d..00000000000000 --- a/soc/arm/st_stm32/stm32wb/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_linker_sources_ifdef(CONFIG_BT_STM32_IPM - SECTIONS - ipm.ld - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series deleted file mode 100644 index 748d91394e59f7..00000000000000 --- a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32WB MCU line - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32WBX - -source "soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb*" - -config SOC_SERIES - default "stm32wb" - -config BT_USER_PHY_UPDATE - default y if BT - -endif # SOC_SERIES_STM32WBX diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.series b/soc/arm/st_stm32/stm32wb/Kconfig.series deleted file mode 100644 index a0192ae4e6c94e..00000000000000 --- a/soc/arm/st_stm32/stm32wb/Kconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# ST Microelectronics STM32WB MCU series - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32WBX - bool "STM32WBx Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select HAS_SWO - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32WB MCU series diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.soc b/soc/arm/st_stm32/stm32wb/Kconfig.soc deleted file mode 100644 index df65225d311ec3..00000000000000 --- a/soc/arm/st_stm32/stm32wb/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# ST Microelectronics STM32WB MCU line - -# Copyright (c) 2019 Linaro Limited -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32WBx MCU Selection" - depends on SOC_SERIES_STM32WBX - -config SOC_STM32WB55XX - bool "STM32WB55XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32wba/CMakeLists.txt b/soc/arm/st_stm32/stm32wba/CMakeLists.txt deleted file mode 100644 index d26c143f8f6e8b..00000000000000 --- a/soc/arm/st_stm32/stm32wba/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources( - soc.c - ) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -if(CONFIG_BT_STM32WBA) - zephyr_include_directories(hci_if) - - zephyr_sources(hci_if/linklayer_plat.c) - zephyr_sources(hci_if/bleplat.c) - zephyr_sources(hci_if/host_stack_if.c) - zephyr_sources(hci_if/ll_sys_if.c) - zephyr_sources(hci_if/stm32_timer.c) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.series deleted file mode 100644 index 340b62049e85d9..00000000000000 --- a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.series +++ /dev/null @@ -1,64 +0,0 @@ -# ST Microelectronics STM32WBA MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32WBAX - -source "soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba*" - -config SOC_SERIES - default "stm32wba" - -config STM32_LPTIM_TIMER - default y if PM - -choice BT_HCI_BUS_TYPE - default BT_STM32WBA - depends on BT -endchoice - -config BT_STM32WBA - select DYNAMIC_INTERRUPTS - select DYNAMIC_DIRECT_INTERRUPTS - select ENTROPY_GENERATOR - select USE_STM32_HAL_RAMCFG - -if BT_STM32WBA - -choice LIBC_IMPLEMENTATION - default NEWLIB_LIBC -endchoice - -choice LINKER_ORPHAN_CONFIGURATION - default LINKER_ORPHAN_SECTION_PLACE -endchoice - -config ENTROPY_STM32_CLK_CHECK - default n - -endif - -if PM_S2RAM - -config COUNTER - default y - -config COUNTER_RTC_STM32_SUBSECONDS - default y - -config STM32_LPTIM_STDBY_TIMER - default y - -config TICKLESS_KERNEL - default y - -config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS - default y - -config IDLE_STACK_SIZE - default 512 - -endif - -endif # SOC_SERIES_STM32WBAX diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.series b/soc/arm/st_stm32/stm32wba/Kconfig.series deleted file mode 100644 index 5cdaaa7e6724aa..00000000000000 --- a/soc/arm/st_stm32/stm32wba/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# ST Microelectronics STM32WBA MCU series - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32WBAX - bool "STM32WBAx Series MCU" - select ARM - select CPU_CORTEX_M33 - select SOC_FAMILY_STM32 - select ARM_TRUSTZONE_M - select CPU_HAS_ARM_SAU - select CPU_HAS_ARM_MPU - select CPU_HAS_FPU - select ARMV8_M_DSP - select CPU_CORTEX_M_HAS_DWT - select HAS_STM32CUBE - select USE_STM32_HAL_PWR_EX - select HAS_PM - help - Enable support for STM32WBA MCU series diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.soc b/soc/arm/st_stm32/stm32wba/Kconfig.soc deleted file mode 100644 index 75f48454b1cc2b..00000000000000 --- a/soc/arm/st_stm32/stm32wba/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# ST Microelectronics STM32WBA MCU line - -# Copyright (c) 2023 STMicroelectronics -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "STM32WBAx MCU Selection" -depends on SOC_SERIES_STM32WBAX - -config SOC_STM32WBA52XX - bool "STM32WBA52XX" - -config SOC_STM32WBA55XX - bool "STM32WBA55XX" - -endchoice diff --git a/soc/arm/st_stm32/stm32wl/CMakeLists.txt b/soc/arm/st_stm32/stm32wl/CMakeLists.txt deleted file mode 100644 index af44cc273e1f7c..00000000000000 --- a/soc/arm/st_stm32/stm32wl/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(${ZEPHYR_BASE}/drivers) -zephyr_sources(soc.c) - -zephyr_sources_ifdef(CONFIG_PM - power.c - ) - -zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.series b/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.series deleted file mode 100644 index be9e5eb2ca6a0d..00000000000000 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# STMicroelectronics STM32WL MCU line - -# Copyright (c) 2020 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STM32WLX - -source "soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl*" - -config SOC_SERIES - default "stm32wl" - -endif # SOC_SERIES_STM32WLX diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.series b/soc/arm/st_stm32/stm32wl/Kconfig.series deleted file mode 100644 index 066deab4e920b9..00000000000000 --- a/soc/arm/st_stm32/stm32wl/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# STMicroelectronics STM32WL MCU series - -# Copyright (c) 2020 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STM32WLX - bool "STM32WLx Series MCU" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select SOC_FAMILY_STM32 - select HAS_STM32CUBE - select CPU_HAS_ARM_MPU - select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL - select HAS_PM - select HAS_POWEROFF - help - Enable support for STM32WL MCU series diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.soc b/soc/arm/st_stm32/stm32wl/Kconfig.soc deleted file mode 100644 index 1664c36cb429c8..00000000000000 --- a/soc/arm/st_stm32/stm32wl/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# STMicroelectronics STM32WL MCU line - -# Copyright (c) 2020 STMicroelectronics. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "STM32WLx MCU Selection" - depends on SOC_SERIES_STM32WLX - -config SOC_STM32WLE4XX - bool "STM32WLE4XX" - -config SOC_STM32WLE5XX - bool "STM32WLE5XX" - -config SOC_STM32WL54XX - bool "STM32WL54XX" - -config SOC_STM32WL55XX - bool "STM32WL55XX" - -endchoice diff --git a/soc/arm/ti_k3/CMakeLists.txt b/soc/arm/ti_k3/CMakeLists.txt deleted file mode 100644 index 4f789e9b56ef3f..00000000000000 --- a/soc/arm/ti_k3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/ti_k3/Kconfig b/soc/arm/ti_k3/Kconfig deleted file mode 100644 index 89a5b8813a56b5..00000000000000 --- a/soc/arm/ti_k3/Kconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TI_K3 - bool - -if SOC_FAMILY_TI_K3 - -config SOC_FAMILY - string - default "ti_k3" - -source "soc/arm/ti_k3/*/Kconfig.soc" - -endif # SOC_FAMILY_TI_K3 diff --git a/soc/arm/ti_k3/Kconfig.defconfig b/soc/arm/ti_k3/Kconfig.defconfig deleted file mode 100644 index 0b983592ad4185..00000000000000 --- a/soc/arm/ti_k3/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_k3/*/Kconfig.defconfig.series" diff --git a/soc/arm/ti_k3/Kconfig.soc b/soc/arm/ti_k3/Kconfig.soc deleted file mode 100644 index 8937942882730d..00000000000000 --- a/soc/arm/ti_k3/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_k3/*/Kconfig.series" diff --git a/soc/arm/ti_k3/am62x_m4/CMakeLists.txt b/soc/arm/ti_k3/am62x_m4/CMakeLists.txt deleted file mode 100644 index bc9b13ea188041..00000000000000 --- a/soc/arm/ti_k3/am62x_m4/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -if(CONFIG_OPENAMP_RSC_TABLE) - zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) - zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") -endif() - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4 b/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4 deleted file mode 100644 index 688efcd841fbda..00000000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4 +++ /dev/null @@ -1,13 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_AM62x_M4 - -config SOC - default "am62x_m4" - -endif diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.series b/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.series deleted file mode 100644 index d85c54d9c00774..00000000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.series +++ /dev/null @@ -1,52 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AM62X_M4 - -source "soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62xm4*" - -config SOC_SERIES - default "am62x_m4" - -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - default 64 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 400000000 - -config PINCTRL - default y - -if SERIAL - -config UART_NS16550 - default y - -config UART_NS16550_TI_K3 - default y - -choice UART_NS16550_VARIANT - default UART_NS16550_VARIANT_NS16750 -endchoice - -endif # SERIAL - -config BUILD_OUTPUT_BIN - default n - -source "soc/arm/ti_k3/am62x_m4/Kconfig.defconfig.am62*" - -endif # SOC_SERIES_AM62X_M4 diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.series b/soc/arm/ti_k3/am62x_m4/Kconfig.series deleted file mode 100644 index 0e67595006788e..00000000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.series +++ /dev/null @@ -1,22 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 EVM -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AM62X_M4 - bool "TI AM62X M4 Core Series" - select SOC_FAMILY_TI_K3 - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_SYSTICK - select DYNAMIC_INTERRUPTS - select CPU_CORTEX_M_HAS_DWT - select OPENAMP_RSC_TABLE - select UART_NS16550_ACCESS_WORD_ONLY - select EXTERNAL_ADDRESS_TRANSLATION - select MM_DRV - select MM_TI_RAT - help - Enable support for AM62X M4 Series. diff --git a/soc/arm/ti_k3/am62x_m4/Kconfig.soc b/soc/arm/ti_k3/am62x_m4/Kconfig.soc deleted file mode 100644 index b0eec320f175d0..00000000000000 --- a/soc/arm/ti_k3/am62x_m4/Kconfig.soc +++ /dev/null @@ -1,28 +0,0 @@ -# Texas Instruments Sitara AM62x-SK-M4 -# -# Copyright (c) 2023 Texas Instruments Incorporated -# Copyright (c) 2023 L Lakshmanan -# -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "TI AM62X M4 Selection" -depends on SOC_SERIES_AM62X_M4 - -config SOC_AM62x_M4 - bool "TI AM62x M4" - select SOC_PART_NUMBER_AM62x - -endchoice - -config SOC_PART_NUMBER_AM62x - bool - -config SOC_PART_NUMBER_AM62X_M4 - string - default "AM62x" if SOC_PART_NUMBER_AM62x - help - Full part number of the SoC. Do not select directly. - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_AM62X_M4 if SOC_SERIES_AM62X_M4 diff --git a/soc/arm/ti_k3/pinctrl_soc.h b/soc/arm/ti_k3/pinctrl_soc.h deleted file mode 100644 index d85797bc2b2546..00000000000000 --- a/soc/arm/ti_k3/pinctrl_soc.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2023 Texas Instruments Incorporated - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_SOC_ARM_TI_K3_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_ARM_TI_K3_PINCTRL_SOC_H_ - -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -struct pinctrl_soc_pin { - uint32_t offset; - uint32_t value; -}; - -typedef struct pinctrl_soc_pin pinctrl_soc_pin_t; - -#define TI_K3_DT_PIN(node_id) \ - { \ - .offset = DT_PROP_BY_IDX(node_id, pinmux, 0), \ - .value = DT_PROP_BY_IDX(node_id, pinmux, 1) \ - }, - -#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \ - TI_K3_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)) - -#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ - { DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) } - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_SOC_ARM_TI_K3_PINCTRL_SOC_H_ */ diff --git a/soc/arm/ti_lm3s6965/CMakeLists.txt b/soc/arm/ti_lm3s6965/CMakeLists.txt deleted file mode 100644 index c76906ff5c347e..00000000000000 --- a/soc/arm/ti_lm3s6965/CMakeLists.txt +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_sources( - soc_config.c - reboot.S - sys_arch_reboot.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/arm/include - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_lm3s6965/Kconfig b/soc/arm/ti_lm3s6965/Kconfig deleted file mode 100644 index dd181a943cb0f7..00000000000000 --- a/soc/arm/ti_lm3s6965/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# TI LM3S6965 platform configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_TI_LM3S6965_QEMU - def_bool y - depends on SOC_TI_LM3S6965 - # Platform has only been tested on QEMU, not on real hardware, so always - # assume it is used for a QEMU target. diff --git a/soc/arm/ti_lm3s6965/Kconfig.defconfig b/soc/arm/ti_lm3s6965/Kconfig.defconfig deleted file mode 100644 index 6c8a17a15f4836..00000000000000 --- a/soc/arm/ti_lm3s6965/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# TI LM3S6965 platform configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_TI_LM3S6965 - -config SOC - default "ti_lm3s6965" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts and ethernet interrupts - default 43 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 12000000 - -if UART_STELLARIS - -config UART_STELLARIS_PORT_0 - default y - -config UART_STELLARIS_PORT_1 - default y - -config UART_STELLARIS_PORT_2 - default y - -endif # UART_STELLARIS - -endif diff --git a/soc/arm/ti_lm3s6965/Kconfig.soc b/soc/arm/ti_lm3s6965/Kconfig.soc deleted file mode 100644 index e37f9868dac451..00000000000000 --- a/soc/arm/ti_lm3s6965/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_TI_LM3S6965 - bool "TI LM3S6965" - select ARM - select CPU_CORTEX_M3 - select CPU_CORTEX_M_HAS_DWT diff --git a/soc/arm/ti_simplelink/CMakeLists.txt b/soc/arm/ti_simplelink/CMakeLists.txt deleted file mode 100644 index 226f3bd626f611..00000000000000 --- a/soc/arm/ti_simplelink/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm/ti_simplelink/Kconfig b/soc/arm/ti_simplelink/Kconfig deleted file mode 100644 index e35796ee12117b..00000000000000 --- a/soc/arm/ti_simplelink/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Texas Instruments SimpleLink Family - -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TISIMPLELINK - bool - -if SOC_FAMILY_TISIMPLELINK - -config SOC_FAMILY - string - default "ti_simplelink" - -source "soc/arm/ti_simplelink/*/Kconfig.soc" - -config HAS_TI_CCFG - bool - help - Selected when CCFG (Customer Configuration) registers - appear at the end of flash - -endif # SOC_FAMILY_TISIMPLELINK diff --git a/soc/arm/ti_simplelink/Kconfig.defconfig b/soc/arm/ti_simplelink/Kconfig.defconfig deleted file mode 100644 index 6e5e652b5a8dc4..00000000000000 --- a/soc/arm/ti_simplelink/Kconfig.defconfig +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_simplelink/*/Kconfig.defconfig.series" diff --git a/soc/arm/ti_simplelink/Kconfig.soc b/soc/arm/ti_simplelink/Kconfig.soc deleted file mode 100644 index 780aad1009e830..00000000000000 --- a/soc/arm/ti_simplelink/Kconfig.soc +++ /dev/null @@ -1,5 +0,0 @@ -# Texas Instruments SimpleLink Family - -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm/ti_simplelink/*/Kconfig.series" diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/CMakeLists.txt b/soc/arm/ti_simplelink/cc13x2_cc26x2/CMakeLists.txt deleted file mode 100644 index bf52a055e3b34b..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Brett Witherspoon -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_sources(ccfg.c) - -if(CONFIG_PM OR CONFIG_PM_DEVICE OR CONFIG_POWEROFF) - zephyr_library_sources(power.c) -endif() -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc1352r b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc1352r deleted file mode 100644 index 10ab6b10f75d6c..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc1352r +++ /dev/null @@ -1,9 +0,0 @@ -# Texas Instruments SimpleLink CC1352R -# -# Copyright (c) 2019 Brett Witherspoon -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc1352r" - depends on SOC_CC1352R diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc2652r b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc2652r deleted file mode 100644 index 9d7eff99698a33..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc2652r +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments SimpleLink CC2652R - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc2652r" - depends on SOC_CC2652R diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series deleted file mode 100644 index 9fc6aeafc9b032..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.series +++ /dev/null @@ -1,47 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_CC13X2_CC26X2 - -source "soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.defconfig.cc*" - -config SOC_SERIES - default "cc13x2_cc26x2" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -# Note that when using the RTC as system clock, this needs to be 32768 -# to reduce truncation errors from accumulating due to conversion to/from -# time, ticks, and HW cycles -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -config NUM_IRQS - default 38 - -if IEEE802154 - -config IEEE802154_CC13XX_CC26XX - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -config IEEE802154_CC13XX_CC26XX_SUB_GHZ - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -endif # IEEE802154 - -if BT - -config BLE_CC13XX_CC26XX - bool - default y - -endif # BT - -endif # SOC_SERIES_CC13X2_CC26X2 diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.series b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.series deleted file mode 100644 index b7d26a70539fc1..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_CC13X2_CC26X2 - bool "TI SimpleLink Family CC13x2 / CC26x2" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select DYNAMIC_INTERRUPTS - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_TISIMPLELINK - select HAS_CC13X2_CC26X2_SDK - select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_PM - select HAS_POWEROFF - help - Enable support for TI SimpleLink CC13x2 / CC26x2 SoCs diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.soc b/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.soc deleted file mode 100644 index 920fb7e5e9056d..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2_cc26x2/Kconfig.soc +++ /dev/null @@ -1,68 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2019 Brett Witherspoon -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_CC13X2_CC26X2 - -config SOC_CC2652R - bool "CC2652R" - -config SOC_CC2652P - bool "CC2652P" - -config SOC_CC1352R - bool "CC1352R" - -config SOC_CC1352P - bool "CC1352P" - -endchoice - -menu "Customer Configuration (CCFG)" -depends on SOC_SERIES_CC13X2_CC26X2 - -config CC13X2_CC26X2_BOOST_MODE - bool "Radio boost mode (VDDR_HH)" - help - Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). - -config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS - bool "Board defines custom RFCC26XX hwAttrs structure" - help - The board defines its own RFCC26XX_hwAttrs structure (e.g., for - custom antenna switching callback). - -config CC13X2_CC26X2_BOOTLOADER_ENABLE - bool "ROM bootloader" - help - Enable the serial bootloader which resides in ROM on CC13xx / CC26xx - devices. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - bool "ROM bootloader backdoor" - depends on CC13X2_CC26X2_BOOTLOADER_ENABLE - help - Enable the ROM bootloader backdoor which starts the bootloader if the - associated pin is at the correct logic level on reset. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN - int "ROM bootloader backdoor pin" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 255 - default 255 - help - Set the pin that is level checked if the bootloader backdoor is - enabled. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL - int "ROM bootloader backdoor level" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 1 - default 0 - help - Set the active level of the pin selected for the bootloader backdoor. - -endmenu diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt deleted file mode 100644 index 4194f4262219a6..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2022 Vaishnav Achath -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_sources(ccfg.c) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_PM_DEVICE power.c) - -zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 deleted file mode 100644 index fabdeedf2d60b2..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc1352r7 +++ /dev/null @@ -1,9 +0,0 @@ -# Texas Instruments SimpleLink CC1352R -# -# Copyright (c) 2022 Vaishnav Achath -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc1352r7" - depends on SOC_CC1352R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 deleted file mode 100644 index 2ba4afb8767422..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc2652r7 +++ /dev/null @@ -1,8 +0,0 @@ -# Texas Instruments SimpleLink CC2652R - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "cc2652r7" - depends on SOC_CC2652R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series deleted file mode 100644 index ede32e92701066..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.series +++ /dev/null @@ -1,47 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_CC13X2X7_CC26X2X7 - -source "soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig.cc*" - -config SOC_SERIES - default "cc13x2x7_cc26x2x7" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -# Note that when using the RTC as system clock, this needs to be 32768 -# to reduce truncation errors from accumulating due to conversion to/from -# time, ticks, and HW cycles -config SYS_CLOCK_TICKS_PER_SEC - default 32768 - -config NUM_IRQS - default 38 - -if IEEE802154 - -config IEEE802154_CC13XX_CC26XX - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -config IEEE802154_CC13XX_CC26XX_SUB_GHZ - # required for linking with PowerCC26X2_config in - # soc/arm/ti_simplelink/cc13x2_cc26x2/power.c - select PM - -endif # IEEE802154 - -if BT - -config BLE_CC13XX_CC26XX - bool - default y - -endif # BT - -endif # SOC_SERIES_CC13X2X7_CC26X2X7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series deleted file mode 100644 index 773b3b85253bca..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_CC13X2X7_CC26X2X7 - bool "TI SimpleLink Family CC13x2x7/ CC26x2x7" - select ARM - select CPU_CORTEX_M4 - select CPU_HAS_ARM_MPU - select DYNAMIC_INTERRUPTS - select CPU_CORTEX_M_HAS_DWT - select CPU_HAS_FPU - select SOC_FAMILY_TISIMPLELINK - select HAS_CC13X2X7_CC26X2X7_SDK - select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - select HAS_PM - help - Enable support for TI SimpleLink CC13x2x7 / CC26x2x7 SoCs diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc b/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc deleted file mode 100644 index 96bd6cfce94188..00000000000000 --- a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/Kconfig.soc +++ /dev/null @@ -1,75 +0,0 @@ -# Texas Instruments SimpleLink CC13x2 / CC26x2 - -# Copyright (c) 2022 Vaishnav Achath -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_CC13X2X7_CC26X2X7 - -config SOC_CC2652R7 - bool "CC2652R7" - -config SOC_CC1352R7 - bool "CC1352R7" - -config SOC_CC2652P7 - bool "CC2652P7" - -config SOC_CC1352P7 - bool "CC1352P7" - -endchoice - -menu "Customer Configuration (CCFG)" -depends on SOC_SERIES_CC13X2X7_CC26X2X7 - -config CC13X2_CC26X2_BOOST_MODE - bool "Radio boost mode (VDDR_HH)" - help - Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). - -config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS - bool "Board defines custom RFCC26XX hwAttrs structure" - help - The board defines its own RFCC26XX_hwAttrs structure (e.g., for - custom antenna switching callback). - -config CC13X2_CC26X2_BOOTLOADER_ENABLE - bool "ROM bootloader" - help - Enable the serial bootloader which resides in ROM on CC13xx / CC26xx - devices. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - bool "ROM bootloader backdoor" - depends on CC13X2_CC26X2_BOOTLOADER_ENABLE - help - Enable the ROM bootloader backdoor which starts the bootloader if the - associated pin is at the correct logic level on reset. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN - int "ROM bootloader backdoor pin" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 255 - default 255 - help - Set the pin that is level checked if the bootloader backdoor is - enabled. - -config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL - int "ROM bootloader backdoor level" - depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE - range 0 1 - default 0 - help - Set the active level of the pin selected for the bootloader backdoor. - -config CC13X2_CC26X2_XOSC_CAPARRAY_DELTA - hex "Cap array tuning delta" - range 0 0xFF - default 0xD5 - help - Enable a specific cap array tunning delta. - -endmenu diff --git a/soc/arm/ti_simplelink/cc32xx/CMakeLists.txt b/soc/arm/ti_simplelink/cc32xx/CMakeLists.txt deleted file mode 100644 index 9d704214718a11..00000000000000 --- a/soc/arm/ti_simplelink/cc32xx/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) -zephyr_include_directories(.) - -if (DEFINED CONFIG_CC3220SF_DEBUG OR DEFINED CONFIG_CC3235SF_DEBUG) - zephyr_linker_sources(ROM_START SORT_KEY 0 cc32xx_debug.ld) -endif() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.series b/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.series deleted file mode 100644 index cd586e9fb4c2f2..00000000000000 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# TI SimpleLink Family - -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_CC32XX - -source "soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc32*" - -config SOC_SERIES - default "cc32xx" - -endif # SOC_SERIES_CC32XX diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.series b/soc/arm/ti_simplelink/cc32xx/Kconfig.series deleted file mode 100644 index 5c7344d26e4524..00000000000000 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# TI SimpleLink CC32xx - -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_CC32XX - bool "TI SimpleLink Family" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select DYNAMIC_INTERRUPTS - select SOC_FAMILY_TISIMPLELINK - help - Enable support for TI SimpleLink CC32xx diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.soc b/soc/arm/ti_simplelink/cc32xx/Kconfig.soc deleted file mode 100644 index 5746cb835b97d8..00000000000000 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.soc +++ /dev/null @@ -1,27 +0,0 @@ -# Texas Instruments CC32XX - -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_CC32XX - -config SOC_CC3220SF - bool "CC3220SF" - select HAS_CC3220SDK - -config SOC_CC3235SF - bool "CC3235SF" - select HAS_CC3220SDK - -endchoice - -config CC3220SF_DEBUG - bool "Prepend debug header, disabling flash verification" if XIP - default XIP - depends on SOC_CC3220SF - -config CC3235SF_DEBUG - bool "Prepend debug header, disabling flash verification" if XIP - default XIP - depends on SOC_CC3235SF diff --git a/soc/arm/ti_simplelink/msp432p4xx/CMakeLists.txt b/soc/arm/ti_simplelink/msp432p4xx/CMakeLists.txt deleted file mode 100644 index d93f837e79ec9d..00000000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_compile_definitions(-D__MSP432P401R__) -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.series b/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.series deleted file mode 100644 index 55bf2827f12290..00000000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# TI SimpleLink MSP432P4XX - -# Copyright (c) 2017, Linaro Ltd -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MSP432P4XX - -source "soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p4*" - -config SOC_SERIES - default "msp432p4xx" - -endif # SOC_SERIES_MSP432P4XX diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.series b/soc/arm/ti_simplelink/msp432p4xx/Kconfig.series deleted file mode 100644 index 8af48672ed23be..00000000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# TI SimpleLink MSP432P4XX - -# Copyright (c) 2017, Linaro Ltd -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MSP432P4XX - bool "TI SimpleLink Family MSP432P4XX" - select ARM - select CPU_CORTEX_M4 - select CPU_CORTEX_M_HAS_DWT - select DYNAMIC_INTERRUPTS - select SOC_FAMILY_TISIMPLELINK - select CPU_HAS_FPU - select CPU_HAS_ARM_MPU - help - Enable support for TI SimpleLink MSP432P4XX. diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.soc b/soc/arm/ti_simplelink/msp432p4xx/Kconfig.soc deleted file mode 100644 index 4b3aa5c20868ff..00000000000000 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Texas Instruments MSP432P401R - -# Copyright (c) 2017, Linaro Ltd -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "TI SimpleLink MCU Selection" - depends on SOC_SERIES_MSP432P4XX - -config SOC_MSP432P401R - bool "MSP432P401R" - select HAS_MSP432P4XXSDK -endchoice diff --git a/soc/arm/xilinx_zynq7000/Kconfig b/soc/arm/xilinx_zynq7000/Kconfig deleted file mode 100644 index f9cfab4b58d124..00000000000000 --- a/soc/arm/xilinx_zynq7000/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FAMILY_XILINX_ZYNQ7000 - bool - -if SOC_FAMILY_XILINX_ZYNQ7000 - -config SOC_FAMILY - string - default "xilinx_zynq7000" - -source "soc/arm/xilinx_zynq7000/*/Kconfig.soc" - -endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/arm/xilinx_zynq7000/Kconfig.defconfig b/soc/arm/xilinx_zynq7000/Kconfig.defconfig deleted file mode 100644 index 6370018edf26ba..00000000000000 --- a/soc/arm/xilinx_zynq7000/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm/xilinx_zynq7000/*/Kconfig.defconfig.series" - -if SOC_FAMILY_XILINX_ZYNQ7000 - -config NUM_IRQS - int - # must be >= the highest interrupt number used - default 96 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config PLATFORM_SPECIFIC_INIT - default y - -endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/arm/xilinx_zynq7000/Kconfig.soc b/soc/arm/xilinx_zynq7000/Kconfig.soc deleted file mode 100644 index 94bee4dc052683..00000000000000 --- a/soc/arm/xilinx_zynq7000/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm/xilinx_zynq7000/*/Kconfig.series" diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/CMakeLists.txt b/soc/arm/xilinx_zynq7000/xc7zxxx/CMakeLists.txt deleted file mode 100644 index d47bcfb128fe16..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.series deleted file mode 100644 index 2df9c08aef7c3f..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.series +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_XILINX_XC7ZXXX - -rsource "Kconfig.defconfig.xc7z*" - -config SOC_SERIES - default "xc7zxxx" - -# Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core -config MP_MAX_NUM_CPUS - default 1 - -endif # SOC_SERIES_XILINX_XC7ZXXX diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z010 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z010 deleted file mode 100644 index 22c46c7c026421..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z010 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z010" - depends on SOC_XILINX_XC7Z010 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z015 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z015 deleted file mode 100644 index 357330de387f58..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z015 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z015" - depends on SOC_XILINX_XC7Z015 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z020 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z020 deleted file mode 100644 index a0d9cf9d1aae3b..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z020 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z020" - depends on SOC_XILINX_XC7Z020 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z030 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z030 deleted file mode 100644 index 41be9856cea34a..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z030 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z030" - depends on SOC_XILINX_XC7Z030 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z035 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z035 deleted file mode 100644 index 078721b96fd954..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z035 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z035" - depends on SOC_XILINX_XC7Z035 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z045 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z045 deleted file mode 100644 index 26fb3ed5b5b8d0..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z045 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z045" - depends on SOC_XILINX_XC7Z045 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z100 b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z100 deleted file mode 100644 index ef8d719424278d..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.defconfig.xc7z100 +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z100" - depends on SOC_XILINX_XC7Z100 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.series deleted file mode 100644 index 5a2f0966aadcb7..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_XILINX_XC7ZXXX - bool "Xilinx Zynq-7000 (XC7Zxxx) SoC series" - select SOC_FAMILY_XILINX_ZYNQ7000 - select ARM - select CPU_CORTEX_A9 - select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER - help - Enable support for the Xilinx Zynq-7000 (XC7Zxxx) - SoC series (dual core ARM Cortex-A9). diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.soc b/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.soc deleted file mode 100644 index 3bb2523fbf6e89..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxx/Kconfig.soc +++ /dev/null @@ -1,60 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# -# Device data: comp. -# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable -# - -choice - prompt "XC7Zxxx SoC Selection" - depends on SOC_SERIES_XILINX_XC7ZXXX - -config SOC_XILINX_XC7Z010 - bool "XC7Z010" - help - 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, - 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins. - -config SOC_XILINX_XC7Z015 - bool "XC7Z015" - help - 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, - 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins, - up to 4 transceivers. - -config SOC_XILINX_XC7Z020 - bool "XC7Z020" - help - 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, - 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins. - -config SOC_XILINX_XC7Z030 - bool "XC7Z030" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins, - up to 4 transceivers. - -config SOC_XILINX_XC7Z035 - bool "XC7Z035" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins, - up to 16 transceivers. - -config SOC_XILINX_XC7Z045 - bool "XC7Z045" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins, - up to 16 transceivers. - -config SOC_XILINX_XC7Z100 - bool "XC7Z100" - help - 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, - 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins, - up to 16 transceivers. - -endchoice diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/CMakeLists.txt b/soc/arm/xilinx_zynq7000/xc7zxxxs/CMakeLists.txt deleted file mode 100644 index d47bcfb128fe16..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.series deleted file mode 100644 index f59211e7a3470f..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_XILINX_XC7ZXXXS - -rsource "Kconfig.defconfig.xc7z*" - -config SOC_SERIES - default "xc7zxxxs" - -config MP_MAX_NUM_CPUS - default 1 - -endif # SOC_SERIES_XILINX_XC7ZXXXS diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z007s b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z007s deleted file mode 100644 index aec3ecdca63f53..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z007s +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z007S" - depends on SOC_XILINX_XC7Z007S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z012s b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z012s deleted file mode 100644 index 597fd1aacd8949..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z012s +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z012S" - depends on SOC_XILINX_XC7Z012S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z014s b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z014s deleted file mode 100644 index f01ddc5b782894..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.defconfig.xc7z014s +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC - default "XC7Z014S" - depends on SOC_XILINX_XC7Z014S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.series b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.series deleted file mode 100644 index 3045a8560162fe..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_XILINX_XC7ZXXXS - bool "Xilinx Zynq-7000S (XC7ZxxxS) SoC series" - select SOC_FAMILY_XILINX_ZYNQ7000 - select ARM - select CPU_CORTEX_A9 - select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER - help - Enable support for the Xilinx Zynq-7000S (XC7ZxxxS) - SoC series (single core ARM Cortex-A9). diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.soc b/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.soc deleted file mode 100644 index d69f790f7ddb63..00000000000000 --- a/soc/arm/xilinx_zynq7000/xc7zxxxs/Kconfig.soc +++ /dev/null @@ -1,32 +0,0 @@ -# -# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG -# SPDX-License-Identifier: Apache-2.0 -# -# Device data: comp. -# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable -# - -choice - prompt "XC7ZxxxS SoC Selection" - depends on SOC_SERIES_XILINX_XC7ZXXXS - -config SOC_XILINX_XC7Z007S - bool "XC7Z007S" - help - 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, - 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins. - -config SOC_XILINX_XC7Z012S - bool "XC7Z012S" - help - 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, - 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins, - up to 4 transceivers. - -config SOC_XILINX_XC7Z014S - bool "XC7Z014S" - help - 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, - 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins. - -endchoice diff --git a/soc/arm/xilinx_zynqmp/CMakeLists.txt b/soc/arm/xilinx_zynqmp/CMakeLists.txt deleted file mode 100644 index 65bf778779bc2a..00000000000000 --- a/soc/arm/xilinx_zynqmp/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c -) -zephyr_sources_ifdef( - CONFIG_ARM_MPU - arm_mpu_regions.c -) - -if(CONFIG_SOC_XILINX_ZYNQMP_RPU) - set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") -endif() diff --git a/soc/arm/xilinx_zynqmp/Kconfig b/soc/arm/xilinx_zynqmp/Kconfig deleted file mode 100644 index 7c72b2d50465ac..00000000000000 --- a/soc/arm/xilinx_zynqmp/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2019 Stephanos Ioannidis -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XILINX_ZYNQMP - bool diff --git a/soc/arm/xilinx_zynqmp/Kconfig.defconfig b/soc/arm/xilinx_zynqmp/Kconfig.defconfig deleted file mode 100644 index ad294bbeda78c3..00000000000000 --- a/soc/arm/xilinx_zynqmp/Kconfig.defconfig +++ /dev/null @@ -1,31 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# Copyright (c) 2019 Stephanos Ioannidis -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XILINX_ZYNQMP - -config SOC - default "xilinx_zynqmp" - -if SOC_XILINX_ZYNQMP_RPU - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - default 220 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 5000000 - -endif # SOC_XILINX_ZYNQMP_RPU - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_XILINX_ZYNQMP diff --git a/soc/arm/xilinx_zynqmp/Kconfig.soc b/soc/arm/xilinx_zynqmp/Kconfig.soc deleted file mode 100644 index 6d80f61c68eaa6..00000000000000 --- a/soc/arm/xilinx_zynqmp/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019 Lexmark International, Inc. -# Copyright (c) 2019 Stephanos Ioannidis -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XILINX_ZYNQMP_RPU - bool "Xilinx ZynqMP RPU" - select ARM - select CPU_CORTEX_R5 - select SOC_XILINX_ZYNQMP - select PLATFORM_SPECIFIC_INIT - select CPU_HAS_ARM_MPU - select VFP_DP_D16 diff --git a/soc/arm64/CMakeLists.txt b/soc/arm64/CMakeLists.txt deleted file mode 100644 index b826da926caf12..00000000000000 --- a/soc/arm64/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/arm64/Kconfig b/soc/arm64/Kconfig deleted file mode 100644 index a24f8b3503417e..00000000000000 --- a/soc/arm64/Kconfig +++ /dev/null @@ -1,11 +0,0 @@ -# General options signifying CPU capabilities of ARM64 SoCs - -# Copyright (c) 2018 Nordic Semiconductor ASA. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_PART_NUMBER - string - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. diff --git a/soc/arm64/arm/CMakeLists.txt b/soc/arm64/arm/CMakeLists.txt deleted file mode 100644 index 23fca810f55442..00000000000000 --- a/soc/arm64/arm/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/arm/Kconfig b/soc/arm64/arm/Kconfig deleted file mode 100644 index cbdb14c1ae2ba4..00000000000000 --- a/soc/arm64/arm/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ARM64 - bool - -if SOC_FAMILY_ARM64 -config SOC_FAMILY - string - default "arm" - -source "soc/arm64/arm/*/Kconfig.soc" -endif # SOC_FAMILY_ARM diff --git a/soc/arm64/arm/Kconfig.defconfig b/soc/arm64/arm/Kconfig.defconfig deleted file mode 100644 index f68deebf103653..00000000000000 --- a/soc/arm64/arm/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/arm/*/Kconfig.defconfig.series" diff --git a/soc/arm64/arm/Kconfig.soc b/soc/arm64/arm/Kconfig.soc deleted file mode 100644 index 24e67555b41546..00000000000000 --- a/soc/arm64/arm/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# ARM LTD SoC configuration options - -# Copyright (c) 2016 Linaro Limited -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/arm/*/Kconfig.series" diff --git a/soc/arm64/arm/fvp_aemv8a/CMakeLists.txt b/soc/arm64/arm/fvp_aemv8a/CMakeLists.txt deleted file mode 100644 index b28d8b24523e3d..00000000000000 --- a/soc/arm64/arm/fvp_aemv8a/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/arm/fvp_aemv8a/Kconfig.defconfig.series b/soc/arm64/arm/fvp_aemv8a/Kconfig.defconfig.series deleted file mode 100644 index 00eb592da2ac74..00000000000000 --- a/soc/arm64/arm/fvp_aemv8a/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_FVP_AEMV8A - -config SOC_SERIES - default "fvp_aemv8a" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 16384 if GIC_V3_ITS - default 128 if !GIC_V3_ITS - -if SOC_FVP_BASE_REVC_2XAEMV8A - -config SOC - default "fvp_base_revc_2xaemv8a" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_FVP_BASE_REVC_2XAEMV8A - -endif # SOC_SERIES_FVP_AEMV8A diff --git a/soc/arm64/arm/fvp_aemv8a/Kconfig.series b/soc/arm64/arm/fvp_aemv8a/Kconfig.series deleted file mode 100644 index 27517028bbeb8c..00000000000000 --- a/soc/arm64/arm/fvp_aemv8a/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_FVP_AEMV8A - bool "ARM FVP AEMv8A AArch64 Series" - select ARM64 - select SOC_FAMILY_ARM64 - help - Enable support for ARM FVP AEMv8A AArch64 Series diff --git a/soc/arm64/arm/fvp_aemv8a/Kconfig.soc b/soc/arm64/arm/fvp_aemv8a/Kconfig.soc deleted file mode 100644 index 9dec51555816fe..00000000000000 --- a/soc/arm64/arm/fvp_aemv8a/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2021 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM FVP AEMv8A AArch64 SoCs" - depends on SOC_SERIES_FVP_AEMV8A - -config SOC_FVP_BASE_REVC_2XAEMV8A - bool "ARM FVP Base RevC 2xAEMv8A AArch64 simulation" - select CPU_CORTEX_A53 - -endchoice diff --git a/soc/arm64/arm/fvp_aemv8r/CMakeLists.txt b/soc/arm64/arm/fvp_aemv8r/CMakeLists.txt deleted file mode 100644 index ce116cb936eb41..00000000000000 --- a/soc/arm64/arm/fvp_aemv8r/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 -zephyr_library_sources( - soc.c -) - -zephyr_library_sources_ifdef(CONFIG_ARM_MPU arm_mpu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/arm/fvp_aemv8r/Kconfig.defconfig.series b/soc/arm64/arm/fvp_aemv8r/Kconfig.defconfig.series deleted file mode 100644 index ecc3aef5fdd3cf..00000000000000 --- a/soc/arm64/arm/fvp_aemv8r/Kconfig.defconfig.series +++ /dev/null @@ -1,34 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_FVP_AEMV8R - -config SOC_SERIES - default "fvp_aemv8r" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 128 - -if SOC_FVP_AEMV8R_AARCH64 - -config SOC - default "fvp_aemv8r_aarch64" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config MAX_DOMAIN_PARTITIONS - default 8 - -endif # SOC_FVP_AEMV8R_AARCH64 - -endif # SOC_SERIES_FVP_AEMV8R diff --git a/soc/arm64/arm/fvp_aemv8r/Kconfig.series b/soc/arm64/arm/fvp_aemv8r/Kconfig.series deleted file mode 100644 index cf2f75a18b2e51..00000000000000 --- a/soc/arm64/arm/fvp_aemv8r/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_FVP_AEMV8R - bool "ARM FVP AEMv8R AArch64 Series" - select ARM64 - select SOC_FAMILY_ARM64 - help - Enable support for ARM FVP AEMv8R AArch64 Series diff --git a/soc/arm64/arm/fvp_aemv8r/Kconfig.soc b/soc/arm64/arm/fvp_aemv8r/Kconfig.soc deleted file mode 100644 index 724c37b1182007..00000000000000 --- a/soc/arm64/arm/fvp_aemv8r/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "ARM FVP AEMv8R AArch64 SoCs" - depends on SOC_SERIES_FVP_AEMV8R - -config SOC_FVP_AEMV8R_AARCH64 - bool "ARM FVP AEMv8R aarch64 simulation" - select CPU_CORTEX_R82 - select CPU_HAS_MPU - select GIC_SINGLE_SECURITY_STATE - -endchoice - -config SOC_FVP_AEMV8R_SIMULATE_CPU_PM - bool "Simulate CPU Power Management for FVP_BaseR_AEMv8R" - default n - help - It simulates the cpu power management function for - FVP_BaseR_AEMv8R. When zephyr kernel try to bring up secondary - core through pm_cpu_on(), it always succeeds because - it indeed bring up secondary core successfully. diff --git a/soc/arm64/bcm2711/Kconfig.defconfig b/soc/arm64/bcm2711/Kconfig.defconfig deleted file mode 100644 index 0016ca57d03ce5..00000000000000 --- a/soc/arm64/bcm2711/Kconfig.defconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -if SOC_BCM2711 - -config SOC - default "bcm2711" - -config NUM_IRQS - int - default 260 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 54000000 - -endif diff --git a/soc/arm64/bcm2711/Kconfig.soc b/soc/arm64/bcm2711/Kconfig.soc deleted file mode 100644 index 4e1b69462ea730..00000000000000 --- a/soc/arm64/bcm2711/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2023 honglin leng -# SPDX-License-Identifier: Apache-2.0 - -config SOC_BCM2711 - bool "bcm2711" - select ARM64 - select CPU_CORTEX_A72 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/arm64/bcm_vk/CMakeLists.txt b/soc/arm64/bcm_vk/CMakeLists.txt deleted file mode 100644 index 226f3bd626f611..00000000000000 --- a/soc/arm64/bcm_vk/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/bcm_vk/Kconfig b/soc/arm64/bcm_vk/Kconfig deleted file mode 100644 index 04312d5b77d8f1..00000000000000 --- a/soc/arm64/bcm_vk/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -config SOC_FAMILY_BCMVK - bool - -if SOC_FAMILY_BCMVK -config SOC_FAMILY - string - default "bcm_vk" - -source "soc/arm64/bcm_vk/*/Kconfig.soc" - -endif diff --git a/soc/arm64/bcm_vk/Kconfig.defconfig b/soc/arm64/bcm_vk/Kconfig.defconfig deleted file mode 100644 index b498c95832bbbe..00000000000000 --- a/soc/arm64/bcm_vk/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm64/bcm_vk/*/Kconfig.defconfig.series" diff --git a/soc/arm64/bcm_vk/Kconfig.soc b/soc/arm64/bcm_vk/Kconfig.soc deleted file mode 100644 index 38103238ca743d..00000000000000 --- a/soc/arm64/bcm_vk/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 -# -# Copyright 2020 Broadcom. -# - -source "soc/arm64/bcm_vk/*/Kconfig.series" diff --git a/soc/arm64/bcm_vk/viper/CMakeLists.txt b/soc/arm64/bcm_vk/viper/CMakeLists.txt deleted file mode 100644 index 93f8b45bc82dce..00000000000000 --- a/soc/arm64/bcm_vk/viper/CMakeLists.txt +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) -zephyr_sources( - soc.c -) -zephyr_sources_ifdef(CONFIG_SOC_BCM58402_A72 plat_core.c) - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.series b/soc/arm64/bcm_vk/viper/Kconfig.defconfig.series deleted file mode 100644 index 831c516416e588..00000000000000 --- a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_VIPER - -config SOC_SERIES - default "viper" - -source "soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper*" - -endif # SOC_SERIES_VIPER diff --git a/soc/arm64/bcm_vk/viper/Kconfig.series b/soc/arm64/bcm_vk/viper/Kconfig.series deleted file mode 100644 index a972a7e0d2bc3a..00000000000000 --- a/soc/arm64/bcm_vk/viper/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_VIPER - bool "Broadcom Viper Series" - select ARM64 - select SOC_FAMILY_BCMVK - help - Enable support for Broadcom Viper Series. diff --git a/soc/arm64/bcm_vk/viper/Kconfig.soc b/soc/arm64/bcm_vk/viper/Kconfig.soc deleted file mode 100644 index 96a9f6cf26a6ff..00000000000000 --- a/soc/arm64/bcm_vk/viper/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright 2020 Broadcom -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Broadcom Viper SoC" -depends on SOC_SERIES_VIPER - -config SOC_BCM58402_A72 - bool "Broadcom BCM58402 A72" - select ARM64 - select CPU_CORTEX_A72 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - -endchoice diff --git a/soc/arm64/intel_socfpga/Kconfig b/soc/arm64/intel_socfpga/Kconfig deleted file mode 100644 index 289c186cba302c..00000000000000 --- a/soc/arm64/intel_socfpga/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_SOCFPGA - bool - -if SOC_FAMILY_INTEL_SOCFPGA -config SOC_FAMILY - string - default "intel_socfpga" - -source "soc/arm64/intel_socfpga/*/Kconfig.soc" -endif diff --git a/soc/arm64/intel_socfpga/Kconfig.defconfig b/soc/arm64/intel_socfpga/Kconfig.defconfig deleted file mode 100644 index 58652897d9336b..00000000000000 --- a/soc/arm64/intel_socfpga/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/intel_socfpga/*/Kconfig.defconfig.series" diff --git a/soc/arm64/intel_socfpga/Kconfig.soc b/soc/arm64/intel_socfpga/Kconfig.soc deleted file mode 100644 index 20fdd2fd43807d..00000000000000 --- a/soc/arm64/intel_socfpga/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/intel_socfpga/*/Kconfig.series" diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.series b/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.series deleted file mode 100644 index 6a457bb2255118..00000000000000 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AGILEX - -config SOC_SERIES - default "agilex" - -source "soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex*" - -endif # SOC_SERIES_AGILEX diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.series b/soc/arm64/intel_socfpga/agilex/Kconfig.series deleted file mode 100644 index f1266db5baeff6..00000000000000 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AGILEX - bool "Intel SoC FPGA Agilex Series" - select ARM64 - select CPU_CORTEX_A53 - select SOC_FAMILY_INTEL_SOCFPGA - help - Enable support for Intel SoC FPGA Series diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.soc b/soc/arm64/intel_socfpga/agilex/Kconfig.soc deleted file mode 100644 index e87636f1af36f7..00000000000000 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Intel SoC FPGA Agilex" -depends on SOC_SERIES_AGILEX - -config SOC_AGILEX - bool "Intel SoC FPGA Agilex" -endchoice diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series b/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series deleted file mode 100644 index 6a511cdfd6e62f..00000000000000 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AGILEX5 - -config SOC_SERIES - default "agilex5" - -source "soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5*" - -endif # SOC_SERIES_AGILEX5 diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.series b/soc/arm64/intel_socfpga/agilex5/Kconfig.series deleted file mode 100644 index c64c38dc5577bb..00000000000000 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AGILEX5 - bool "Intel SoC FPGA Agilex5 Series" - select ARM64 - select CPU_CORTEX_A76_A55 - select SOC_FAMILY_INTEL_SOCFPGA - help - Enable support for Intel SoC FPGA Series diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.soc b/soc/arm64/intel_socfpga/agilex5/Kconfig.soc deleted file mode 100644 index bb75833db9e866..00000000000000 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Intel SoC FPGA Agilex5" -depends on SOC_SERIES_AGILEX5 - -config SOC_AGILEX5 - bool "Intel SoC FPGA Agilex5" -endchoice diff --git a/soc/arm64/nxp_imx/CMakeLists.txt b/soc/arm64/nxp_imx/CMakeLists.txt deleted file mode 100644 index fed279096ccbcd..00000000000000 --- a/soc/arm64/nxp_imx/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright (c) 2022, NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/nxp_imx/Kconfig b/soc/arm64/nxp_imx/Kconfig deleted file mode 100644 index c1fbf2dfc1e518..00000000000000 --- a/soc/arm64/nxp_imx/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2017-2020, NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_IMX - bool - select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE - -if SOC_FAMILY_IMX - -config SOC_FAMILY - string - default "nxp_imx" - -source "soc/arm64/nxp_imx/*/Kconfig.soc" - -endif # SOC_FAMILY_IMX diff --git a/soc/arm64/nxp_imx/Kconfig.defconfig b/soc/arm64/nxp_imx/Kconfig.defconfig deleted file mode 100644 index e4ec0b9e0fed81..00000000000000 --- a/soc/arm64/nxp_imx/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/nxp_imx/*/Kconfig.defconfig.series" diff --git a/soc/arm64/nxp_imx/Kconfig.soc b/soc/arm64/nxp_imx/Kconfig.soc deleted file mode 100644 index bd111bf4c9deb3..00000000000000 --- a/soc/arm64/nxp_imx/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2017, NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/nxp_imx/*/Kconfig.series" diff --git a/soc/arm64/nxp_imx/mimx8m/CMakeLists.txt b/soc/arm64/nxp_imx/mimx8m/CMakeLists.txt deleted file mode 100644 index 032c4a8642d4d0..00000000000000 --- a/soc/arm64/nxp_imx/mimx8m/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mm b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mm deleted file mode 100644 index a77d9f837dff8f..00000000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mm +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2020-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MM_A53 - -config SOC - default "mimx8mm6_ca53" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn deleted file mode 100644 index c6c2837d74de18..00000000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mn +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MN_A53 - -config SOC - default "mimx8mn6_ca53" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mp b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mp deleted file mode 100644 index ebdfa764a69917..00000000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8mp +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2021-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8MP_A53 - -config SOC - default "mimx8ml8_ca53" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.series b/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.series deleted file mode 100644 index 51aed03b198ffb..00000000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MIMX8M_A53 - -config SOC_SERIES - default "mimx8m" - -source "soc/arm64/nxp_imx/mimx8m/Kconfig.defconfig.mimx8m*" - -endif # SOC_SERIES_MIMX8M_A53 diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.series b/soc/arm64/nxp_imx/mimx8m/Kconfig.series deleted file mode 100644 index cbb0cb99f529e4..00000000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MIMX8M_A53 - bool "NXP i.MX8M A53 Core Series" - select ARM64 - select SOC_FAMILY_IMX - help - Enable support for i.MX8M A53 Series. diff --git a/soc/arm64/nxp_imx/mimx8m/Kconfig.soc b/soc/arm64/nxp_imx/mimx8m/Kconfig.soc deleted file mode 100644 index 8c29bb50c96c8a..00000000000000 --- a/soc/arm64/nxp_imx/mimx8m/Kconfig.soc +++ /dev/null @@ -1,93 +0,0 @@ -# Copyright 2020-2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "NXP i.MX8M A53 Selection" -depends on SOC_SERIES_MIMX8M_A53 - -config SOC_MIMX8MM_A53 - bool "NXP i.MX8MM A53" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -config SOC_MIMX8MP_A53 - bool "NXP i.MX8MP A53" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -config SOC_MIMX8MN_A53 - bool "NXP i.MX8MN A53" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -endchoice - -config SOC_PART_NUMBER_MIMX8ML8DVNLZ - bool - -config SOC_PART_NUMBER_MIMX8MP_A53 - string - default "MIMX8ML8DVNLZ_ca53" if SOC_PART_NUMBER_MIMX8ML8DVNLZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER_MIMX8MM6DVTLZ - bool - -config SOC_PART_NUMBER_MIMX8MM6CVTKZ - bool - -config SOC_PART_NUMBER_MIMX8MM_A53 - string - default "MIMX8MM6DVTLZ_ca53" if SOC_PART_NUMBER_MIMX8MM6DVTLZ - default "MIMX8MM6CVTKZ_ca53" if SOC_PART_NUMBER_MIMX8MM6CVTKZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -if SOC_MIMX8MN_A53 - -config SOC_PART_NUMBER_MIMX8MN6DVTJZ - bool - -config SOC_PART_NUMBER_MIMX8MN6DUCJZ - bool - -config SOC_PART_NUMBER_MIMX8MN6CVTIZ - bool - -config SOC_PART_NUMBER_MIMX8MN6CUCIZ - bool - -config SOC_PART_NUMBER_MIMX8MN_A53 - string - default "MIMX8MN6DVTJZ_ca53" if SOC_PART_NUMBER_MIMX8MN6DVTJZ - default "MIMX8MN6DUCJZ_ca53" if SOC_PART_NUMBER_MIMX8MN6DUCJZ - default "MIMX8MN6CVTIZ_ca53" if SOC_PART_NUMBER_MIMX8MN6CVTIZ - default "MIMX8MN6CUCIZ_ca53" if SOC_PART_NUMBER_MIMX8MN6CUCIZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -endif # SOC_MIMX8MN_A53 - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_MIMX8MP_A53 if SOC_MIMX8MP_A53 - default SOC_PART_NUMBER_MIMX8MM_A53 if SOC_MIMX8MM_A53 - default SOC_PART_NUMBER_MIMX8MN_A53 if SOC_MIMX8MN_A53 diff --git a/soc/arm64/nxp_imx/mimx9/CMakeLists.txt b/soc/arm64/nxp_imx/mimx9/CMakeLists.txt deleted file mode 100644 index 77a9500f5b7cf4..00000000000000 --- a/soc/arm64/nxp_imx/mimx9/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx93 b/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx93 deleted file mode 100644 index 45e67de35eda52..00000000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx93 +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright 2022-2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX93_A55 - -config SOC - default "mimx9352_ca55" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 240 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 24000000 - -config PINCTRL_IMX - default y if HAS_MCUX_IOMUXC - depends on PINCTRL - -endif diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.series b/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.series deleted file mode 100644 index 83a587bddc8fe2..00000000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MIMX9_A55 - -config SOC_SERIES - default "mimx9" - -source "soc/arm64/nxp_imx/mimx9/Kconfig.defconfig.mimx9*" - -endif # SOC_SERIES_MIMX9_A55 diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.series b/soc/arm64/nxp_imx/mimx9/Kconfig.series deleted file mode 100644 index 2998e0161c3f64..00000000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.series +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MIMX9_A55 - bool "NXP i.MX9 A55 Core Series" - select ARM64 - select SOC_FAMILY_IMX - help - Enable support for i.MX9 A55 Series. diff --git a/soc/arm64/nxp_imx/mimx9/Kconfig.soc b/soc/arm64/nxp_imx/mimx9/Kconfig.soc deleted file mode 100644 index 3f38d40131fd15..00000000000000 --- a/soc/arm64/nxp_imx/mimx9/Kconfig.soc +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright 2022 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "NXP i.MX9 A55 Selection" -depends on SOC_SERIES_MIMX9_A55 - -config SOC_MIMX93_A55 - bool "NXP i.MX93 A55" - select ARM64 - select CPU_CORTEX_A55 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - -endchoice - -config SOC_PART_NUMBER_MIMX9352CVUXK - bool - -config SOC_PART_NUMBER_MIMX9352DVUXM - bool - -config SOC_PART_NUMBER_MIMX93_A55 - string - default "MIMX9352CVUXK_ca55" if SOC_PART_NUMBER_MIMX9352CVUXK - default "MIMX9352DVUXM_ca55" if SOC_PART_NUMBER_MIMX9352DVUXM - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_MIMX93_A55 if SOC_MIMX93_A55 diff --git a/soc/arm64/nxp_layerscape/Kconfig b/soc/arm64/nxp_layerscape/Kconfig deleted file mode 100644 index ac299386195823..00000000000000 --- a/soc/arm64/nxp_layerscape/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FAMILY_LS - bool - -if SOC_FAMILY_LS - -config SOC_FAMILY - string - default "nxp_layerscape" - -source "soc/arm64/nxp_layerscape/*/Kconfig.soc" - -config SOC_PART_NUMBER - default "LS1046A" if SOC_SERIES_LS1046A - -endif # SOC_FAMILY_LS diff --git a/soc/arm64/nxp_layerscape/Kconfig.defconfig b/soc/arm64/nxp_layerscape/Kconfig.defconfig deleted file mode 100644 index 15f1964dd9936f..00000000000000 --- a/soc/arm64/nxp_layerscape/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/nxp_layerscape/*/Kconfig.defconfig.series" diff --git a/soc/arm64/nxp_layerscape/Kconfig.soc b/soc/arm64/nxp_layerscape/Kconfig.soc deleted file mode 100644 index e2ab956ce7ff39..00000000000000 --- a/soc/arm64/nxp_layerscape/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/nxp_layerscape/*/Kconfig.series" diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a deleted file mode 100644 index 86e02eb67d5a24..00000000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_LS1046A - -config SOC - default "ls1046a" - -config NUM_IRQS - int - default 240 - -config FLASH_SIZE - default 0 - -config FLASH_BASE_ADDRESS - default 0 - -endif diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.series b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.series deleted file mode 100644 index 727b4287eeabf3..00000000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_LS1046A - -config SOC_SERIES - default "ls1046a" - -source "soc/arm64/nxp_layerscape/ls1046a/Kconfig.defconfig.ls1046a" - -endif # SOC_SERIES_LS1046A diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.series b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.series deleted file mode 100644 index 259a51f51dd2d5..00000000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_LS1046A - bool "NXP LS1046A Series" - select ARM64 - select SOC_FAMILY_LS - help - Enable support for NXP ls1046a Series. diff --git a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc b/soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc deleted file mode 100644 index be9ea607c82123..00000000000000 --- a/soc/arm64/nxp_layerscape/ls1046a/Kconfig.soc +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2021 NXP -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice -prompt "NXP Layerscpae LS1046A SoC" -depends on SOC_SERIES_LS1046A - -config SOC_LS1046A - bool "NXP ls1046a" - select ARM64 - select CPU_CORTEX_A72 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - -endchoice diff --git a/soc/arm64/qemu_cortex_a53/CMakeLists.txt b/soc/arm64/qemu_cortex_a53/CMakeLists.txt deleted file mode 100644 index b28d8b24523e3d..00000000000000 --- a/soc/arm64/qemu_cortex_a53/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/qemu_cortex_a53/Kconfig.defconfig b/soc/arm64/qemu_cortex_a53/Kconfig.defconfig deleted file mode 100644 index dca1544f7c5f21..00000000000000 --- a/soc/arm64/qemu_cortex_a53/Kconfig.defconfig +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_CORTEX_A53 - -config SOC - default "qemu_cortex_a53" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # - LPIs (starting at 8192) if GIC_V3_ITS is used - default 16384 if GIC_V3_ITS - default 220 if !GIC_V3_ITS - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 62500000 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_QEMU_CORTEX_A53 diff --git a/soc/arm64/qemu_cortex_a53/Kconfig.soc b/soc/arm64/qemu_cortex_a53/Kconfig.soc deleted file mode 100644 index 4aac3e811b5f20..00000000000000 --- a/soc/arm64/qemu_cortex_a53/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019 Carlo Caione -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_CORTEX_A53 - bool "QEMU virt platform (cortex-a53)" - select ARM64 - select CPU_CORTEX_A53 diff --git a/soc/arm64/qemu_virt_arm64/Kconfig.defconfig b/soc/arm64/qemu_virt_arm64/Kconfig.defconfig deleted file mode 100644 index 14c6c3334502f8..00000000000000 --- a/soc/arm64/qemu_virt_arm64/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SAS -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_VIRT_ARM64 - -config SOC - default "qemu_virt_arm64" - -config NUM_IRQS - # must be >= the highest interrupt number used - # - include the UART interrupts - # - LPIs (starting at 8192) if GIC_V3_ITS is used - default 16384 if GIC_V3_ITS - default 220 if !GIC_V3_ITS - -# Dummy value, read at runtime -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1 - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -endif # SOC_QEMU_VIRT_ARM64 diff --git a/soc/arm64/qemu_virt_arm64/Kconfig.soc b/soc/arm64/qemu_virt_arm64/Kconfig.soc deleted file mode 100644 index 109e8e3270a3c1..00000000000000 --- a/soc/arm64/qemu_virt_arm64/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2022 Huawei France Technologies SAS -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_VIRT_ARM64 - bool "QEMU virt platform (AArch64 for KVM)" - select ARM64 - select CPU_CORTEX_A - select ARMV8_A diff --git a/soc/arm64/renesas_rcar/CMakeLists.txt b/soc/arm64/renesas_rcar/CMakeLists.txt deleted file mode 100644 index ce47b609a9aa3c..00000000000000 --- a/soc/arm64/renesas_rcar/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/renesas_rcar/Kconfig b/soc/arm64/renesas_rcar/Kconfig deleted file mode 100644 index 413523e23a75d2..00000000000000 --- a/soc/arm64/renesas_rcar/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_RCAR - bool - -if SOC_FAMILY_RCAR - -config SOC_FAMILY - string - default "renesas_rcar" - -source "soc/arm64/renesas_rcar/*/Kconfig.soc" - -endif # SOC_FAMILY_RCAR diff --git a/soc/arm64/renesas_rcar/Kconfig.defconfig b/soc/arm64/renesas_rcar/Kconfig.defconfig deleted file mode 100644 index fa39233d8dcee1..00000000000000 --- a/soc/arm64/renesas_rcar/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/renesas_rcar/*/Kconfig.defconfig.series" diff --git a/soc/arm64/renesas_rcar/Kconfig.soc b/soc/arm64/renesas_rcar/Kconfig.soc deleted file mode 100644 index 3e191b56f35673..00000000000000 --- a/soc/arm64/renesas_rcar/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Renesas R-Car SoC line - -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/renesas_rcar/*/Kconfig.series" diff --git a/soc/arm64/renesas_rcar/gen3/CMakeLists.txt b/soc/arm64/renesas_rcar/gen3/CMakeLists.txt deleted file mode 100644 index 16dcc07b754a49..00000000000000 --- a/soc/arm64/renesas_rcar/gen3/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library_sources_ifdef(CONFIG_SOC_ARM64_R8A77951 pfc_r8a77951.c) -zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c) -zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 b/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 deleted file mode 100644 index 3df374f28937e4..00000000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77951 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ARM64_R8A77951 - -config SOC - default "r8a77951" - -endif # SOC_ARM64_R8A77951 diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77961 b/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77961 deleted file mode 100644 index 573e7b102fbc77..00000000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.r8a77961 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_R8A77961 - -config SOC - default "r8a77961" - -endif # SOC_R8A77961 diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.series b/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.series deleted file mode 100644 index 369d1beedb8d80..00000000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.defconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Renesas R-Car Gen3 SoC line - -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RCAR_GEN3 - -config SOC_SERIES - default "gen3" - -config NUM_IRQS - int - default 240 - -config PINCTRL - default y - -endif # SOC_SERIES_RCAR_GEN3 diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.series b/soc/arm64/renesas_rcar/gen3/Kconfig.series deleted file mode 100644 index a5c33c2a23c42a..00000000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RCAR_GEN3 - bool "Renesas RCAR Gen3 Cortex A" - select ARM64 - select CPU_CORTEX_A57 - select SOC_FAMILY_RCAR - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL - help - Enable support for Renesas RCar Gen3 SoC series diff --git a/soc/arm64/renesas_rcar/gen3/Kconfig.soc b/soc/arm64/renesas_rcar/gen3/Kconfig.soc deleted file mode 100644 index 4be06397bd1b14..00000000000000 --- a/soc/arm64/renesas_rcar/gen3/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2023 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Renesas RCar SoC Selection" - depends on SOC_SERIES_RCAR_GEN3 - -config SOC_ARM64_R8A77951 - bool "R8A77951" - -config SOC_R8A77961 - bool "R8A77961" - -endchoice diff --git a/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c b/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c deleted file mode 100644 index 2d5c02316efced..00000000000000 --- a/soc/arm64/renesas_rcar/gen3/pfc_r8a77951.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (c) 2021 IoT.bzh - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include "pinctrl_soc.h" -#include - -const struct pfc_drive_reg pfc_drive_regs[] = { - /* DRVCTRL0 */ - { 0x0300, { - { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */ - { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */ - { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */ - { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */ - { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */ - { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */ - { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */ - { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */ - } }, - /* DRVCTRL1 */ - { 0x0304, { - { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */ - { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */ - { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */ - { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */ - { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */ - { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */ - { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */ - { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */ - } }, - /* DRVCTRL2 */ - { 0x0308, { - { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */ - { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */ - { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */ - { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */ - { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */ - { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */ - { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */ - { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */ - } }, - /* DRVCTRL3 */ - { 0x030c, { - { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */ - { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */ - { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */ - { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */ - { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */ - { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */ - { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */ - { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */ - } }, - /* DRVCTRL4 */ - { 0x0310, { - { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */ - { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */ - { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */ - { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */ - { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */ - { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */ - { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */ - { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */ - } }, - /* DRVCTRL5 */ - { 0x0314, { - { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */ - { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */ - { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */ - { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */ - { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */ - { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */ - { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */ - { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */ - } }, - /* DRVCTRL6 */ - { 0x0318, { - { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */ - { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */ - { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */ - { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */ - { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */ - { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */ - { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */ - { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */ - } }, - /* DRVCTRL7 */ - { 0x031c, { - { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */ - { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */ - { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */ - { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */ - { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */ - { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */ - { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */ - { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */ - } }, - /* DRVCTRL8 */ - { 0x0320, { - { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */ - { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */ - { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */ - { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */ - { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */ - { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */ - { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */ - { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */ - } }, - /* DRVCTRL9 */ - { 0x0324, { - { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */ - { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */ - { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */ - { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */ - { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */ - { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */ - { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */ - { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */ - } }, - /* DRVCTRL10 */ - { 0x0328, { - { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */ - { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */ - { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */ - { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */ - { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */ - { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */ - { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */ - { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */ - } }, - /* DRVCTRL11 */ - { 0x032c, { - { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */ - { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */ - { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */ - { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */ - { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */ - { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */ - { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */ - { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */ - } }, - /* DRVCTRL12 */ - { 0x0330, { - { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */ - { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */ - { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */ - { PIN_TMS, 4, 2 }, /* TMS */ - } }, - /* DRVCTRL13 */ - { 0x0334, { - { PIN_TDO, 28, 2 }, /* TDO */ - { PIN_ASEBRK, 24, 2 }, /* ASEBRK */ - { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */ - { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */ - { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */ - { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */ - { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */ - { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */ - } }, - /* DRVCTRL14 */ - { 0x0338, { - { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */ - { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */ - { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */ - { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */ - { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */ - { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */ - { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */ - { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */ - } }, - /* DRVCTRL15 */ - { 0x033c, { - { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */ - { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */ - { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */ - { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */ - { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */ - { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */ - { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */ - { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */ - } }, - /* DRVCTRL16 */ - { 0x0340, { - { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */ - { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */ - { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */ - { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */ - { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */ - { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */ - { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */ - { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */ - } }, - /* DRVCTRL17 */ - { 0x0344, { - { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */ - { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */ - { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */ - { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */ - { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */ - { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */ - { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */ - { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */ - } }, - /* DRVCTRL18 */ - { 0x0348, { - { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */ - { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */ - { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */ - { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */ - { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */ - { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */ - { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */ - { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */ - } }, - /* DRVCTRL19 */ - { 0x034c, { - { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */ - { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */ - { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */ - { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */ - { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */ - { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */ - { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */ - { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */ - } }, - /* DRVCTRL20 */ - { 0x0350, { - { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */ - { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */ - { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */ - { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */ - { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */ - { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */ - { PIN_MLB_REF, 4, 3 }, /* MLB_REF */ - { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */ - } }, - /* DRVCTRL21 */ - { 0x0354, { - { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */ - { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */ - { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */ - { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */ - { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */ - { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */ - { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */ - { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */ - } }, - /* DRVCTRL22 */ - { 0x0358, { - { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */ - { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */ - { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */ - { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */ - { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */ - { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */ - { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */ - { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */ - } }, - /* DRVCTRL23 */ - { 0x035c, { - { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */ - { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */ - { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */ - { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */ - { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */ - { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */ - { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */ - { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */ - } }, - /* DRVCTRL24 */ - { 0x0360, { - { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */ - { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */ - { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */ - { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */ - { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */ - { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */ - { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */ - } }, - { }, -}; - -#define PFC_BIAS_REG(r1, r2) \ - .puen = r1, \ - .pud = r2, \ - .pins = - -const struct pfc_bias_reg pfc_bias_regs[] = { - { PFC_BIAS_REG(0x0400, 0x0440) { /* PUEN0, PUD0 */ - [0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */ - [1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */ - [2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */ - [3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */ - [4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */ - [5] = PIN_QSPI0_SSL, /* QSPI0_SSL */ - [6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */ - [7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */ - [8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */ - [9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */ - [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */ - [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */ - [12] = PIN_RPC_INT_N, /* RPC_INT# */ - [13] = PIN_RPC_WP_N, /* RPC_WP# */ - [14] = PIN_RPC_RESET_N, /* RPC_RESET# */ - [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */ - [16] = PIN_AVB_RXC, /* AVB_RXC */ - [17] = PIN_AVB_RD0, /* AVB_RD0 */ - [18] = PIN_AVB_RD1, /* AVB_RD1 */ - [19] = PIN_AVB_RD2, /* AVB_RD2 */ - [20] = PIN_AVB_RD3, /* AVB_RD3 */ - [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */ - [22] = PIN_AVB_TXC, /* AVB_TXC */ - [23] = PIN_AVB_TD0, /* AVB_TD0 */ - [24] = PIN_AVB_TD1, /* AVB_TD1 */ - [25] = PIN_AVB_TD2, /* AVB_TD2 */ - [26] = PIN_AVB_TD3, /* AVB_TD3 */ - [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */ - [28] = PIN_AVB_MDIO, /* AVB_MDIO */ - [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */ - [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */ - [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */ - } }, - { PFC_BIAS_REG(0x0404, 0x0444) { /* PUEN1, PUD1 */ - [0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */ - [1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */ - [2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */ - [3] = RCAR_GP_PIN(2, 0), /* IRQ0 */ - [4] = RCAR_GP_PIN(2, 1), /* IRQ1 */ - [5] = RCAR_GP_PIN(2, 2), /* IRQ2 */ - [6] = RCAR_GP_PIN(2, 3), /* IRQ3 */ - [7] = RCAR_GP_PIN(2, 4), /* IRQ4 */ - [8] = RCAR_GP_PIN(2, 5), /* IRQ5 */ - [9] = RCAR_GP_PIN(2, 6), /* PWM0 */ - [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */ - [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */ - [12] = RCAR_GP_PIN(1, 0), /* A0 */ - [13] = RCAR_GP_PIN(1, 1), /* A1 */ - [14] = RCAR_GP_PIN(1, 2), /* A2 */ - [15] = RCAR_GP_PIN(1, 3), /* A3 */ - [16] = RCAR_GP_PIN(1, 4), /* A4 */ - [17] = RCAR_GP_PIN(1, 5), /* A5 */ - [18] = RCAR_GP_PIN(1, 6), /* A6 */ - [19] = RCAR_GP_PIN(1, 7), /* A7 */ - [20] = RCAR_GP_PIN(1, 8), /* A8 */ - [21] = RCAR_GP_PIN(1, 9), /* A9 */ - [22] = RCAR_GP_PIN(1, 10), /* A10 */ - [23] = RCAR_GP_PIN(1, 11), /* A11 */ - [24] = RCAR_GP_PIN(1, 12), /* A12 */ - [25] = RCAR_GP_PIN(1, 13), /* A13 */ - [26] = RCAR_GP_PIN(1, 14), /* A14 */ - [27] = RCAR_GP_PIN(1, 15), /* A15 */ - [28] = RCAR_GP_PIN(1, 16), /* A16 */ - [29] = RCAR_GP_PIN(1, 17), /* A17 */ - [30] = RCAR_GP_PIN(1, 18), /* A18 */ - [31] = RCAR_GP_PIN(1, 19), /* A19 */ - } }, - { PFC_BIAS_REG(0x0408, 0x0448) { /* PUEN2, PUD2 */ - [0] = RCAR_GP_PIN(1, 28), /* CLKOUT */ - [1] = RCAR_GP_PIN(1, 20), /* CS0_N */ - [2] = RCAR_GP_PIN(1, 21), /* CS1_N */ - [3] = RCAR_GP_PIN(1, 22), /* BS_N */ - [4] = RCAR_GP_PIN(1, 23), /* RD_N */ - [5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */ - [6] = RCAR_GP_PIN(1, 25), /* WE0_N */ - [7] = RCAR_GP_PIN(1, 26), /* WE1_N */ - [8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */ - [9] = PIN_PRESETOUT_N, /* PRESETOUT# */ - [10] = RCAR_GP_PIN(0, 0), /* D0 */ - [11] = RCAR_GP_PIN(0, 1), /* D1 */ - [12] = RCAR_GP_PIN(0, 2), /* D2 */ - [13] = RCAR_GP_PIN(0, 3), /* D3 */ - [14] = RCAR_GP_PIN(0, 4), /* D4 */ - [15] = RCAR_GP_PIN(0, 5), /* D5 */ - [16] = RCAR_GP_PIN(0, 6), /* D6 */ - [17] = RCAR_GP_PIN(0, 7), /* D7 */ - [18] = RCAR_GP_PIN(0, 8), /* D8 */ - [19] = RCAR_GP_PIN(0, 9), /* D9 */ - [20] = RCAR_GP_PIN(0, 10), /* D10 */ - [21] = RCAR_GP_PIN(0, 11), /* D11 */ - [22] = RCAR_GP_PIN(0, 12), /* D12 */ - [23] = RCAR_GP_PIN(0, 13), /* D13 */ - [24] = RCAR_GP_PIN(0, 14), /* D14 */ - [25] = RCAR_GP_PIN(0, 15), /* D15 */ - [26] = RCAR_GP_PIN(7, 0), /* AVS1 */ - [27] = RCAR_GP_PIN(7, 1), /* AVS2 */ - [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */ - [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */ - [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ - [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */ - } }, - { PFC_BIAS_REG(0x040c, 0x044c) { /* PUEN3, PUD3 */ - [0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */ - [1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */ - [2] = PIN_FSCLKST_N, /* FSCLKST# */ - [3] = PIN_EXTALR, /* EXTALR*/ - [4] = PIN_TRST_N, /* TRST# */ - [5] = PIN_TCK, /* TCK */ - [6] = PIN_TMS, /* TMS */ - [7] = PIN_TDI, /* TDI */ - [8] = PIN_NONE, - [9] = PIN_ASEBRK, /* ASEBRK */ - [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */ - [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */ - [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */ - [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */ - [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */ - [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */ - [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */ - [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */ - [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */ - [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */ - [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */ - [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */ - [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */ - [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */ - [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */ - [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */ - [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */ - [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */ - [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */ - [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */ - [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */ - [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */ - } }, - { PFC_BIAS_REG(0x0410, 0x0450) { /* PUEN4, PUD4 */ - [0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */ - [1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */ - [2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */ - [3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */ - [4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */ - [5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */ - [6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */ - [7] = RCAR_GP_PIN(4, 17), /* SD3_DS */ - [8] = RCAR_GP_PIN(3, 12), /* SD0_CD */ - [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */ - [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */ - [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */ - [12] = RCAR_GP_PIN(5, 0), /* SCK0 */ - [13] = RCAR_GP_PIN(5, 1), /* RX0 */ - [14] = RCAR_GP_PIN(5, 2), /* TX0 */ - [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */ - [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */ - [17] = RCAR_GP_PIN(5, 5), /* RX1_A */ - [18] = RCAR_GP_PIN(5, 6), /* TX1_A */ - [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */ - [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */ - [21] = RCAR_GP_PIN(5, 9), /* SCK2 */ - [22] = RCAR_GP_PIN(5, 10), /* TX2_A */ - [23] = RCAR_GP_PIN(5, 11), /* RX2_A */ - [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */ - [25] = RCAR_GP_PIN(5, 13), /* HRX0 */ - [26] = RCAR_GP_PIN(5, 14), /* HTX0 */ - [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */ - [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */ - [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */ - [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */ - [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */ - } }, - { PFC_BIAS_REG(0x0414, 0x0454) { /* PUEN5, PUD5 */ - [0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */ - [1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */ - [2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */ - [3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */ - [4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */ - [5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */ - [6] = PIN_MLB_REF, /* MLB_REF */ - [7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */ - [8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */ - [9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */ - [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */ - [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */ - [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */ - [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */ - [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */ - [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */ - [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */ - [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */ - [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */ - [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */ - [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */ - [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */ - [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */ - [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */ - [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */ - [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */ - [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */ - [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */ - [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */ - [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */ - [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */ - [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */ - } }, - { PFC_BIAS_REG(0x0418, 0x0458) { /* PUEN6, PUD6 */ - [0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */ - [1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */ - [2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */ - [3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */ - [4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */ - [5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */ - [6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */ - [7] = PIN_NONE, - [8] = PIN_NONE, - [9] = PIN_NONE, - [10] = PIN_NONE, - [11] = PIN_NONE, - [12] = PIN_NONE, - [13] = PIN_NONE, - [14] = PIN_NONE, - [15] = PIN_NONE, - [16] = PIN_NONE, - [17] = PIN_NONE, - [18] = PIN_NONE, - [19] = PIN_NONE, - [20] = PIN_NONE, - [21] = PIN_NONE, - [22] = PIN_NONE, - [23] = PIN_NONE, - [24] = PIN_NONE, - [25] = PIN_NONE, - [26] = PIN_NONE, - [27] = PIN_NONE, - [28] = PIN_NONE, - [29] = PIN_NONE, - [30] = PIN_NONE, - [31] = PIN_NONE, - } }, - { /* sentinel */ }, -}; -const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void) -{ - return pfc_bias_regs; -} -const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void) -{ - return pfc_drive_regs; -} - -int pfc_rcar_get_reg_index(uint8_t pin, uint8_t *reg_index) -{ - /* There is only one register on Gen 3 */ - *reg_index = 0; - return 0; -} diff --git a/soc/arm64/rockchip/CMakeLists.txt b/soc/arm64/rockchip/CMakeLists.txt deleted file mode 100644 index a002d302cf61e4..00000000000000 --- a/soc/arm64/rockchip/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/rockchip/Kconfig b/soc/arm64/rockchip/Kconfig deleted file mode 100644 index e0b4b937c79a81..00000000000000 --- a/soc/arm64/rockchip/Kconfig +++ /dev/null @@ -1,22 +0,0 @@ -# -# Copyright 2021 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_FAMILY_ROCKCHIP - bool - -if SOC_FAMILY_ROCKCHIP - -config SOC_FAMILY - string - default "rockchip" - -source "soc/arm64/rockchip/*/Kconfig.soc" - -config SOC_PART_NUMBER - default "RK3399" if SOC_SERIES_RK3399 - default "RK3568" if SOC_SERIES_RK3568 - -endif # SOC_FAMILY_ROCKCHIP diff --git a/soc/arm64/rockchip/Kconfig.defconfig b/soc/arm64/rockchip/Kconfig.defconfig deleted file mode 100644 index 64ee55264d7cda..00000000000000 --- a/soc/arm64/rockchip/Kconfig.defconfig +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2021 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/rockchip/*/Kconfig.defconfig.series" diff --git a/soc/arm64/rockchip/Kconfig.soc b/soc/arm64/rockchip/Kconfig.soc deleted file mode 100644 index 19bbc3f798fbf3..00000000000000 --- a/soc/arm64/rockchip/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -source "soc/arm64/rockchip/*/Kconfig.series" diff --git a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.series b/soc/arm64/rockchip/rk3399/Kconfig.defconfig.series deleted file mode 100644 index 0bedfa01d8d5a0..00000000000000 --- a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.series +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_RK3399 - -config SOC_SERIES - default "rk3399" - -source "soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399" - -endif # SOC_SERIES_RK3399 diff --git a/soc/arm64/rockchip/rk3399/Kconfig.series b/soc/arm64/rockchip/rk3399/Kconfig.series deleted file mode 100644 index 71b2e5e4851760..00000000000000 --- a/soc/arm64/rockchip/rk3399/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_RK3399 - bool "Rockchip RK3399 Series" - select ARM64 - select SOC_FAMILY_ROCKCHIP - help - Enable support for Rockchip RK3399 Series. diff --git a/soc/arm64/rockchip/rk3399/Kconfig.soc b/soc/arm64/rockchip/rk3399/Kconfig.soc deleted file mode 100644 index 74fb8b6d7d8d55..00000000000000 --- a/soc/arm64/rockchip/rk3399/Kconfig.soc +++ /dev/null @@ -1,17 +0,0 @@ -# -# Copyright 2022 Huawei France Technologies SASU -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice -prompt "Rockchip RK3399 SoC" -depends on SOC_SERIES_RK3399 - -config SOC_RK3399 - bool "Rockchip RK3399" - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - -endchoice diff --git a/soc/arm64/rockchip/rk3568/CMakeLists.txt b/soc/arm64/rockchip/rk3568/CMakeLists.txt deleted file mode 100644 index 2cf9a407f84e01..00000000000000 --- a/soc/arm64/rockchip/rk3568/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) diff --git a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series b/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series deleted file mode 100644 index 96279038e4a197..00000000000000 --- a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_RK3568 - -config SOC_SERIES - default "rk3568" - -source "soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568" - -endif # SOC_SERIES_RK3568 diff --git a/soc/arm64/rockchip/rk3568/Kconfig.series b/soc/arm64/rockchip/rk3568/Kconfig.series deleted file mode 100644 index 15909e5bff0189..00000000000000 --- a/soc/arm64/rockchip/rk3568/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyrs -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_RK3568 - bool "Rockchip RK3568 Series" - select ARM64 - select SOC_FAMILY_ROCKCHIP - help - Enable support for RK3568 Series. diff --git a/soc/arm64/rockchip/rk3568/Kconfig.soc b/soc/arm64/rockchip/rk3568/Kconfig.soc deleted file mode 100644 index 7bb2be41909c99..00000000000000 --- a/soc/arm64/rockchip/rk3568/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright 2022 HNU-ESNL -# Copyright 2022 openEuler SIG-Zephyr -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Rockchip RK3568 SoC" -depends on SOC_SERIES_RK3568 - -config SOC_RK3568 - bool "Rockchip rk3568" - select ARM64 - select CPU_CORTEX_A55 - select ARM_ARCH_TIMER - select GIC_V3 - -endchoice diff --git a/soc/arm64/rockchip/rk3568/linker.ld b/soc/arm64/rockchip/rk3568/linker.ld deleted file mode 100644 index f1b07809e1f7d8..00000000000000 --- a/soc/arm64/rockchip/rk3568/linker.ld +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Copyright 2020 NXP - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include diff --git a/soc/arm64/ti_k3/CMakeLists.txt b/soc/arm64/ti_k3/CMakeLists.txt deleted file mode 100644 index f16a8498786f9f..00000000000000 --- a/soc/arm64/ti_k3/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/arm64/ti_k3/Kconfig b/soc/arm64/ti_k3/Kconfig deleted file mode 100644 index 081632c0b880f6..00000000000000 --- a/soc/arm64/ti_k3/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TI_K3 - bool - -if SOC_FAMILY_TI_K3 - -config SOC_FAMILY - string - default "ti_k3" - -source "soc/arm64/ti_k3/*/Kconfig.soc" - -endif # SOC_FAMILY_TI_K3 diff --git a/soc/arm64/ti_k3/Kconfig.defconfig b/soc/arm64/ti_k3/Kconfig.defconfig deleted file mode 100644 index 18eeadee4e09fd..00000000000000 --- a/soc/arm64/ti_k3/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/ti_k3/*/Kconfig.defconfig.series" diff --git a/soc/arm64/ti_k3/Kconfig.soc b/soc/arm64/ti_k3/Kconfig.soc deleted file mode 100644 index 7d48f5cee1dbfa..00000000000000 --- a/soc/arm64/ti_k3/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Texas Instruments Keystone 3 (K3) Family -# -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -source "soc/arm64/ti_k3/*/Kconfig.series" diff --git a/soc/arm64/ti_k3/am6x/CMakeLists.txt b/soc/arm64/ti_k3/am6x/CMakeLists.txt deleted file mode 100644 index 491cafbec22ff2..00000000000000 --- a/soc/arm64/ti_k3/am6x/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.am6234 b/soc/arm64/ti_k3/am6x/Kconfig.defconfig.am6234 deleted file mode 100644 index a22567299c56c2..00000000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.am6234 +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -if SOC_AM6234_A53 - -config SOC - default "am6234" - -endif # SOC_AM6234_A53 diff --git a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.series b/soc/arm64/ti_k3/am6x/Kconfig.defconfig.series deleted file mode 100644 index 066acc7d66851e..00000000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.defconfig.series +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_AM6X_A53 - -config SOC_SERIES - default "am6x" - -# Workaround for not being able to have commas in macro arguments -DT_CHOSEN_Z_FLASH := zephyr,flash - -config FLASH_SIZE - default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) - -config FLASH_BASE_ADDRESS - default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) - -config NUM_IRQS - int - default 280 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 200000000 - -config PINCTRL - default y - -if SERIAL - -config UART_NS16550 - default y - -choice UART_NS16550_VARIANT - default UART_NS16550_VARIANT_NS16750 -endchoice - -endif # SERIAL - -source "soc/arm64/ti_k3/am6x/Kconfig.defconfig.am62*" - -endif # SOC_SERIES_AM6X_A53 diff --git a/soc/arm64/ti_k3/am6x/Kconfig.series b/soc/arm64/ti_k3/am6x/Kconfig.series deleted file mode 100644 index 1de6052d9eda6c..00000000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_AM6X_A53 - bool "TI AM6X A53 Core Series" - select SOC_FAMILY_TI_K3 - select ARM64 - select CPU_CORTEX_A53 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - help - Enable support for AM6X A53 Series. diff --git a/soc/arm64/ti_k3/am6x/Kconfig.soc b/soc/arm64/ti_k3/am6x/Kconfig.soc deleted file mode 100644 index 74dbb7fedae7ed..00000000000000 --- a/soc/arm64/ti_k3/am6x/Kconfig.soc +++ /dev/null @@ -1,26 +0,0 @@ -# Copyright (c) 2023 Enphase Energy -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "TI AM6X A53 Selection" -depends on SOC_SERIES_AM6X_A53 - -config SOC_AM6234_A53 - bool "TI AM6234 A53" - select SOC_PART_NUMBER_AM6234 - -endchoice - -config SOC_PART_NUMBER_AM6234 - bool - -config SOC_PART_NUMBER_AM6X_A53 - string - default "AM6234" if SOC_PART_NUMBER_AM6234 - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER - default SOC_PART_NUMBER_AM6X_A53 if SOC_SERIES_AM6X_A53 diff --git a/soc/arm64/xenvm/Kconfig.defconfig b/soc/arm64/xenvm/Kconfig.defconfig deleted file mode 100644 index 4a88b6bed9345d..00000000000000 --- a/soc/arm64/xenvm/Kconfig.defconfig +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XENVM - -config SOC - default "xenvm" - -config NUM_IRQS - int - default 500 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 8320000 - -# We need at least 16M of virtual address space to map memory of Xen node -# 32M should be enough for basic use-cases -config KERNEL_VM_SIZE - default 0x2000000 - -endif diff --git a/soc/arm64/xenvm/Kconfig.soc b/soc/arm64/xenvm/Kconfig.soc deleted file mode 100644 index 00f1bf0ca31981..00000000000000 --- a/soc/arm64/xenvm/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright 2020 EPAM Systems -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XENVM - bool "Xen virtual machine on aarch64" - select ARM64 - select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS - select CPU_CORTEX_A72 diff --git a/soc/arm/aspeed/CMakeLists.txt b/soc/aspeed/CMakeLists.txt similarity index 100% rename from soc/arm/aspeed/CMakeLists.txt rename to soc/aspeed/CMakeLists.txt diff --git a/soc/aspeed/Kconfig b/soc/aspeed/Kconfig new file mode 100644 index 00000000000000..5d28220c246083 --- /dev/null +++ b/soc/aspeed/Kconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_FAMILY_ASPEED + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_ASPEED + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ASPEED diff --git a/soc/aspeed/Kconfig.defconfig b/soc/aspeed/Kconfig.defconfig new file mode 100644 index 00000000000000..c0d309927f1930 --- /dev/null +++ b/soc/aspeed/Kconfig.defconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +if SOC_FAMILY_ASPEED + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ASPEED diff --git a/soc/aspeed/Kconfig.soc b/soc/aspeed/Kconfig.soc new file mode 100644 index 00000000000000..546bd4db95b20b --- /dev/null +++ b/soc/aspeed/Kconfig.soc @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_FAMILY_ASPEED + bool + +config SOC_FAMILY + default "aspeed" if SOC_FAMILY_ASPEED + +rsource "*/Kconfig.soc" diff --git a/soc/arm/aspeed/aspeed_util.h b/soc/aspeed/aspeed_util.h similarity index 100% rename from soc/arm/aspeed/aspeed_util.h rename to soc/aspeed/aspeed_util.h diff --git a/soc/aspeed/ast10x0/CMakeLists.txt b/soc/aspeed/ast10x0/CMakeLists.txt new file mode 100644 index 00000000000000..c7de81fc8f1110 --- /dev/null +++ b/soc/aspeed/ast10x0/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) 2021 ASPEED Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_include_directories(.) +zephyr_linker_sources(ROM_START SORT_KEY 0x1sboot sboot.ld) +zephyr_linker_sources(RAM_SECTIONS nocache.ld) + +string(TOUPPER "${SOC_NAME}" soc_name_upper) +set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${SOC_${soc_name_upper}_DIR}/${SOC_SERIES}/tools/gen_uart_booting_image.py + ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin + ${PROJECT_BINARY_DIR}/uart_${CONFIG_KERNEL_BIN_NAME}.bin +) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/aspeed/ast10x0/Kconfig b/soc/aspeed/ast10x0/Kconfig new file mode 100644 index 00000000000000..847980d6b27722 --- /dev/null +++ b/soc/aspeed/ast10x0/Kconfig @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_SERIES_AST10X0 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SYSCON + select CACHE + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CACHE_MANAGEMENT + select CACHE_ASPEED + +if SOC_SERIES_AST10X0 + +config SRAM_NC_SIZE + int "noncached SRAM Size in kB" + help + The non-cached SRAM size in kB. The default value comes from reg[1] + of /chosen/zephyr,sram in devicetree. The user should generally avoid + changing it via menuconfig or in configuration files. + +config SRAM_NC_BASE_ADDRESS + hex "noncached SRAM Base Address" + help + The non-cached SRAM base address. The default value comes from from + reg[1] of /chosen/zephyr,sram in devicetree. The user should + generally avoid changing it via menuconfig or in configuration files. + +endif # SOC_SERIES_AST10X0 diff --git a/soc/aspeed/ast10x0/Kconfig.defconfig b/soc/aspeed/ast10x0/Kconfig.defconfig new file mode 100644 index 00000000000000..6b8b4a07558fbc --- /dev/null +++ b/soc/aspeed/ast10x0/Kconfig.defconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +if SOC_SERIES_AST10X0 + +rsource "Kconfig.defconfig.ast10*0" + +config ICACHE_LINE_SIZE + default 32 + +config DCACHE_LINE_SIZE + default 32 + +choice CACHE_TYPE + default EXTERNAL_CACHE +endchoice + +endif # SOC_SERIES_AST10X0 diff --git a/soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast1030 b/soc/aspeed/ast10x0/Kconfig.defconfig.ast1030 similarity index 100% rename from soc/arm/aspeed/ast10x0/Kconfig.defconfig.ast1030 rename to soc/aspeed/ast10x0/Kconfig.defconfig.ast1030 diff --git a/soc/aspeed/ast10x0/Kconfig.soc b/soc/aspeed/ast10x0/Kconfig.soc new file mode 100644 index 00000000000000..5bc45abc901998 --- /dev/null +++ b/soc/aspeed/ast10x0/Kconfig.soc @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2021 ASPEED Technology Inc. + +config SOC_SERIES_AST10X0 + bool + select SOC_FAMILY_ASPEED + help + Enable support for ASPEED AST10X0 series + +config SOC_AST1030 + bool + select SOC_SERIES_AST10X0 + help + AST1030 + +config SOC_SERIES + default "ast10x0" if SOC_SERIES_AST10X0 + +config SOC + default "ast1030" if SOC_AST1030 diff --git a/soc/arm/aspeed/ast10x0/linker.ld b/soc/aspeed/ast10x0/linker.ld similarity index 100% rename from soc/arm/aspeed/ast10x0/linker.ld rename to soc/aspeed/ast10x0/linker.ld diff --git a/soc/arm/aspeed/ast10x0/nocache.ld b/soc/aspeed/ast10x0/nocache.ld similarity index 100% rename from soc/arm/aspeed/ast10x0/nocache.ld rename to soc/aspeed/ast10x0/nocache.ld diff --git a/soc/arm/aspeed/ast10x0/sboot.ld b/soc/aspeed/ast10x0/sboot.ld similarity index 100% rename from soc/arm/aspeed/ast10x0/sboot.ld rename to soc/aspeed/ast10x0/sboot.ld diff --git a/soc/arm/aspeed/ast10x0/soc.c b/soc/aspeed/ast10x0/soc.c similarity index 100% rename from soc/arm/aspeed/ast10x0/soc.c rename to soc/aspeed/ast10x0/soc.c diff --git a/soc/arm/aspeed/ast10x0/soc.h b/soc/aspeed/ast10x0/soc.h similarity index 100% rename from soc/arm/aspeed/ast10x0/soc.h rename to soc/aspeed/ast10x0/soc.h diff --git a/soc/arm/aspeed/ast10x0/tools/gen_uart_booting_image.py b/soc/aspeed/ast10x0/tools/gen_uart_booting_image.py similarity index 100% rename from soc/arm/aspeed/ast10x0/tools/gen_uart_booting_image.py rename to soc/aspeed/ast10x0/tools/gen_uart_booting_image.py diff --git a/soc/aspeed/soc.yml b/soc/aspeed/soc.yml new file mode 100644 index 00000000000000..48e8d78efd3472 --- /dev/null +++ b/soc/aspeed/soc.yml @@ -0,0 +1,6 @@ +family: + - name: aspeed + series: + - name: ast10x0 + socs: + - name: ast1030 diff --git a/soc/atmel/sam/CMakeLists.txt b/soc/atmel/sam/CMakeLists.txt new file mode 100644 index 00000000000000..b379b725d92b0c --- /dev/null +++ b/soc/atmel/sam/CMakeLists.txt @@ -0,0 +1,9 @@ +# Makefile - Atmel SAM MCU family +# +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/atmel/sam/Kconfig b/soc/atmel/sam/Kconfig new file mode 100644 index 00000000000000..68228c4d3e718c --- /dev/null +++ b/soc/atmel/sam/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM + select ASF + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_ATMEL_SAM + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ATMEL_SAM diff --git a/soc/atmel/sam/Kconfig.defconfig b/soc/atmel/sam/Kconfig.defconfig new file mode 100644 index 00000000000000..49ad6145223763 --- /dev/null +++ b/soc/atmel/sam/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Atmel SAM MCU family default configuration options + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ATMEL_SAM + +rsource "*/Kconfig.defconfig" + +config CLOCK_CONTROL + default y + +config GPIO + default y + +config PINCTRL + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config WATCHDOG + default y + +endif # SOC_FAMILY_ATMEL_SAM diff --git a/soc/atmel/sam/Kconfig.soc b/soc/atmel/sam/Kconfig.soc new file mode 100644 index 00000000000000..5f65786c86b15a --- /dev/null +++ b/soc/atmel/sam/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM + bool + +config SOC_FAMILY + default "atmel_sam" if SOC_FAMILY_ATMEL_SAM + +rsource "*/Kconfig.soc" diff --git a/soc/atmel/sam/common/CMakeLists.txt b/soc/atmel/sam/common/CMakeLists.txt new file mode 100644 index 00000000000000..8f53f047230063 --- /dev/null +++ b/soc/atmel/sam/common/CMakeLists.txt @@ -0,0 +1,14 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_pmc.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_gpio.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_supc.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_power.c) +zephyr_library_sources_ifndef(CONFIG_SOC_SERIES_SAM4L soc_poweroff.c) + +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_pm.c) +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_gpio.c) +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_SAM4L soc_sam4l_poweroff.c) diff --git a/soc/atmel/sam/common/Kconfig b/soc/atmel/sam/common/Kconfig new file mode 100644 index 00000000000000..2642a40eda737c --- /dev/null +++ b/soc/atmel/sam/common/Kconfig @@ -0,0 +1,96 @@ +# Atmel SAM MCU series general configuration options + +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L + +menu "Clocks" + +config SOC_ATMEL_SAM_EXT_SLCK + bool "Use external crystal oscillator for slow clock" + help + Says y if you want to use external 32 kHz crystal oscillator to drive + the slow clock. Note that this adds a few seconds to boot time, as the + crystal needs to stabilize after power-up. + + Says n if you do not need accurate and precise timers. The slow clock + will be driven by the internal fast RC oscillator running at 32 kHz. + +config SOC_ATMEL_SAM_EXT_MAINCK + bool "Use external crystal oscillator for main clock" + default y + help + The main clock is being used to drive the PLL, and thus driving the + processor clock. + + Says y if you want to use external crystal oscillator to drive the + main clock. Note that this adds about a second to boot time, as the + crystal needs to stabilize after power-up. + + The crystal used here can be from 3 to 20 MHz. + + Says n here will use the internal fast RC oscillator running at 12 MHz. + +menu "PLL A" + +config SOC_ATMEL_SAM_PLLA_MULA + int "PLL MULA" + default 6 if SOC_SERIES_SAM3X + default 9 if SOC_SERIES_SAM4S || SOC_SERIES_SAM4E + default 24 if SOC_SERIES_SAME70 || SOC_SERIES_SAMV71 + range 1 62 + help + This is the multiplier (MULA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings for a particular board. + + With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times + the main clock frequency. + +config SOC_ATMEL_SAM_PLLA_DIVA + int "PLL DIVA" + default 1 + range 1 255 + help + This is the divider (DIVA) used by the PLL. + The processor clock is (MAINCK * (MULA + 1) / DIVA). + + Board config file can override this settings + for a particular board. + + With default of MULA == N, and DIVA == 1 the PLL will run at N+1 times + the main clock frequency. + +config SOC_ATMEL_SAM_MDIV + int "MDIV" + depends on SOC_SERIES_SAME70 || SOC_SERIES_SAMV71 + default 2 + range 1 4 + help + This divisor defines a ratio between processor clock (HCLK) + and master clock (MCK) where the maximum value is 150MHz: + MCK = HCLK / MDIV + +endmenu # PLL A +endmenu # clocks + +config SOC_ATMEL_SAM_WAIT_MODE + bool "CPU goes to Wait mode instead of Sleep mode" + depends on SOC_ATMEL_SAM_EXT_MAINCK + default y if DEBUG + help + For JTAG debugging CPU clock (HCLK) should not stop. In order to + achieve this, make CPU go to Wait mode instead of Sleep mode while + using external crystal oscillator for main clock. + +config SOC_ATMEL_SAM_DISABLE_ERASE_PIN + bool "Disable ERASE pin" + help + At reset ERASE pin is configured in System IO mode. Asserting the + ERASE pin at '1' will completely erase Flash memory. Setting this + option will switch the pin to general IO mode giving control of the + pin to the GPIO module. + +endif # SOC_FAMILY_ATMEL_SAM && !SOC_SERIES_SAM4L diff --git a/soc/arm/atmel_sam/common/atmel_sam_dt.h b/soc/atmel/sam/common/atmel_sam_dt.h similarity index 100% rename from soc/arm/atmel_sam/common/atmel_sam_dt.h rename to soc/atmel/sam/common/atmel_sam_dt.h diff --git a/soc/arm/atmel_sam/common/pinctrl_soc.h b/soc/atmel/sam/common/pinctrl_soc.h similarity index 100% rename from soc/arm/atmel_sam/common/pinctrl_soc.h rename to soc/atmel/sam/common/pinctrl_soc.h diff --git a/soc/arm/atmel_sam/common/pwm_fixup.h b/soc/atmel/sam/common/pwm_fixup.h similarity index 100% rename from soc/arm/atmel_sam/common/pwm_fixup.h rename to soc/atmel/sam/common/pwm_fixup.h diff --git a/soc/arm/atmel_sam/common/soc_gpio.c b/soc/atmel/sam/common/soc_gpio.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_gpio.c rename to soc/atmel/sam/common/soc_gpio.c diff --git a/soc/arm/atmel_sam/common/soc_gpio.h b/soc/atmel/sam/common/soc_gpio.h similarity index 100% rename from soc/arm/atmel_sam/common/soc_gpio.h rename to soc/atmel/sam/common/soc_gpio.h diff --git a/soc/arm/atmel_sam/common/soc_pmc.c b/soc/atmel/sam/common/soc_pmc.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_pmc.c rename to soc/atmel/sam/common/soc_pmc.c diff --git a/soc/arm/atmel_sam/common/soc_pmc.h b/soc/atmel/sam/common/soc_pmc.h similarity index 100% rename from soc/arm/atmel_sam/common/soc_pmc.h rename to soc/atmel/sam/common/soc_pmc.h diff --git a/soc/arm/atmel_sam/common/soc_power.c b/soc/atmel/sam/common/soc_power.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_power.c rename to soc/atmel/sam/common/soc_power.c diff --git a/soc/arm/atmel_sam/common/soc_poweroff.c b/soc/atmel/sam/common/soc_poweroff.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_poweroff.c rename to soc/atmel/sam/common/soc_poweroff.c diff --git a/soc/arm/atmel_sam/common/soc_sam4l_gpio.c b/soc/atmel/sam/common/soc_sam4l_gpio.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_sam4l_gpio.c rename to soc/atmel/sam/common/soc_sam4l_gpio.c diff --git a/soc/arm/atmel_sam/common/soc_sam4l_pm.c b/soc/atmel/sam/common/soc_sam4l_pm.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_sam4l_pm.c rename to soc/atmel/sam/common/soc_sam4l_pm.c diff --git a/soc/arm/atmel_sam/common/soc_sam4l_poweroff.c b/soc/atmel/sam/common/soc_sam4l_poweroff.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_sam4l_poweroff.c rename to soc/atmel/sam/common/soc_sam4l_poweroff.c diff --git a/soc/arm/atmel_sam/common/soc_supc.c b/soc/atmel/sam/common/soc_supc.c similarity index 100% rename from soc/arm/atmel_sam/common/soc_supc.c rename to soc/atmel/sam/common/soc_supc.c diff --git a/soc/arm/atmel_sam/common/soc_supc.h b/soc/atmel/sam/common/soc_supc.h similarity index 100% rename from soc/arm/atmel_sam/common/soc_supc.h rename to soc/atmel/sam/common/soc_supc.h diff --git a/soc/atmel/sam/sam3x/CMakeLists.txt b/soc/atmel/sam/sam3x/CMakeLists.txt new file mode 100644 index 00000000000000..6a01266941a27f --- /dev/null +++ b/soc/atmel/sam/sam3x/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam3x/Kconfig b/soc/atmel/sam/sam3x/Kconfig new file mode 100644 index 00000000000000..1f66f4ef398178 --- /dev/null +++ b/soc/atmel/sam/sam3x/Kconfig @@ -0,0 +1,15 @@ +# Atmel SAM3X MCU series + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM3X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam3x/Kconfig.defconfig b/soc/atmel/sam/sam3x/Kconfig.defconfig new file mode 100644 index 00000000000000..7a41eb6fad74cd --- /dev/null +++ b/soc/atmel/sam/sam3x/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Atmel SAM3X MCU series configuration options + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM3X + +config NUM_IRQS + default 45 + +endif # SOC_SERIES_SAM3X diff --git a/soc/atmel/sam/sam3x/Kconfig.soc b/soc/atmel/sam/sam3x/Kconfig.soc new file mode 100644 index 00000000000000..7ab817c8891a3c --- /dev/null +++ b/soc/atmel/sam/sam3x/Kconfig.soc @@ -0,0 +1,43 @@ +# Atmel SAM3X MCU series + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# Copyright (c) 2016 Intel Corporation. +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM3X + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM3X MCU Series + +config SOC_SERIES + default "sam3x" if SOC_SERIES_SAM3X + +config SOC_SAM3X4C + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X4E + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X8C + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X8E + bool + select SOC_SERIES_SAM3X + +config SOC_SAM3X8H + bool + select SOC_SERIES_SAM3X + +config SOC + default "sam3x4c" if SOC_SAM3X4C + default "sam3x4e" if SOC_SAM3X4E + default "sam3x8c" if SOC_SAM3X8C + default "sam3x8e" if SOC_SAM3X8E + default "sam3x8h" if SOC_SAM3X8H diff --git a/soc/atmel/sam/sam3x/soc.c b/soc/atmel/sam/sam3x/soc.c new file mode 100644 index 00000000000000..08e803c4f1dae6 --- /dev/null +++ b/soc/atmel/sam/sam3x/soc.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2023 Basalte bv + * Copyright (c) 2023-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAM3X MCU series initialization code + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM3X series processor. + */ + +#include +#include +#include + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDCORE value + * rather than maximum supported 84 MHz at standard VDDCORE=1.8V + */ + EFC0->EEFC_FMR = EEFC_FMR_FWS(4); + EFC1->EEFC_FMR = EEFC_FMR_FWS(4); + + /* + * Setup PLLA + */ + + /* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 6, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (6 + 1) / 1 = 84 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK) = 84 MHz. + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + /* + * Final setup of the Master Clock + */ + + /* prescaler has to be set before PLL lock */ + soc_pmc_mck_set_prescaler(1); + + /* Select PLL as Master Clock source. */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + /* Setup system clocks */ + clock_init(); +} diff --git a/soc/atmel/sam/sam3x/soc.h b/soc/atmel/sam/sam3x/soc.h new file mode 100644 index 00000000000000..b47450ac052aea --- /dev/null +++ b/soc/atmel/sam/sam3x/soc.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM3X MCU. + * + * This file provides register access macros for the Atmel SAM3X MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _SOC_ATMEL_SAM_SAM3X_SOC_H_ +#define _SOC_ATMEL_SAM_SAM3X_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM3X4C) +#include +#elif defined(CONFIG_SOC_SAM3X4E) +#include +#elif defined(CONFIG_SOC_SAM3X8C) +#include +#elif defined(CONFIG_SOC_SAM3X8E) +#include +#elif defined(CONFIG_SOC_SAM3X8H) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +#endif /* _ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM3X_SOC_H_ */ diff --git a/soc/atmel/sam/sam4e/CMakeLists.txt b/soc/atmel/sam/sam4e/CMakeLists.txt new file mode 100644 index 00000000000000..6a01266941a27f --- /dev/null +++ b/soc/atmel/sam/sam4e/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam4e/Kconfig b/soc/atmel/sam/sam4e/Kconfig new file mode 100644 index 00000000000000..57441f1eaef13b --- /dev/null +++ b/soc/atmel/sam/sam4e/Kconfig @@ -0,0 +1,15 @@ +# Atmel SAM4E MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4E + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam4e/Kconfig.defconfig b/soc/atmel/sam/sam4e/Kconfig.defconfig new file mode 100644 index 00000000000000..bb3d457731def6 --- /dev/null +++ b/soc/atmel/sam/sam4e/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM4E MCU series configuration options + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM4E + +config NUM_IRQS + default 47 + +endif # SOC_SERIES_SAM4E diff --git a/soc/atmel/sam/sam4e/Kconfig.soc b/soc/atmel/sam/sam4e/Kconfig.soc new file mode 100644 index 00000000000000..5cbc0c8781c208 --- /dev/null +++ b/soc/atmel/sam/sam4e/Kconfig.soc @@ -0,0 +1,37 @@ +# Atmel SAM4E MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4E + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM4E MCU series + +config SOC_SERIES + default "sam4e" if SOC_SERIES_SAM4E + +config SOC_SAM4E16E + bool + select SOC_SERIES_SAM4E + +config SOC_SAM4E16C + bool + select SOC_SERIES_SAM4E + +config SOC_SAM4E8E + bool + select SOC_SERIES_SAM4E + +config SOC_SAM4E8C + bool + select SOC_SERIES_SAM4E + +config SOC + default "sam4e16e" if SOC_SAM4E16E + default "sam4e16c" if SOC_SAM4E16C + default "sam4e8e" if SOC_SAM4E8E + default "sam4e8c" if SOC_SAM4E8C diff --git a/soc/atmel/sam/sam4e/soc.c b/soc/atmel/sam/sam4e/soc.c new file mode 100644 index 00000000000000..82468f48738408 --- /dev/null +++ b/soc/atmel/sam/sam4e/soc.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2019-2024 Gerson Fernando Budke + * Copyright (c) 2023 Basalte bv + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAM4E MCU series initialization code + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM4E series processor. + */ + +#include +#include +#include + +/** + * @brief Setup various clock on SoC at boot time. + * + * Setup the SoC clocks according to section 28.12 in datasheet. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC->EEFC_FMR = EEFC_FMR_FWS(0); + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. Look at table 44.73 in the SAM4E datasheet. + * This is set to the highest number of read cycles because it won't + * hurt lower clock frequencies. However, a high frequency with too + * few read cycles could cause flash read problems. FWS 5 (6 cycles) + * is the safe setting for all of this SoCs usable frequencies. + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5); + + /* + * Setup PLLA + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + /* + * Final setup of the Master Clock + */ + + /* prescaler has to be set before PLL lock */ + soc_pmc_mck_set_prescaler(1); + + /* Select PLL as Master Clock source. */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + /* Setup system clocks. */ + clock_init(); +} diff --git a/soc/atmel/sam/sam4e/soc.h b/soc/atmel/sam/sam4e/soc.h new file mode 100644 index 00000000000000..78b42a231c0143 --- /dev/null +++ b/soc/atmel/sam/sam4e/soc.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2018 Vincent van der Locht + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2019-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM4E family processors. + */ + +#ifndef _SOC_ATMEL_SAM_SAM4E_SOC_H_ +#define _SOC_ATMEL_SAM_SAM4E_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM4E16E) +#include +#elif defined(CONFIG_SOC_SAM4E16C) +#include +#elif defined(CONFIG_SOC_SAM4E8E) +#include +#elif defined(CONFIG_SOC_SAM4E8C) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM4E_SOC_H_ */ diff --git a/soc/atmel/sam/sam4l/CMakeLists.txt b/soc/atmel/sam/sam4l/CMakeLists.txt new file mode 100644 index 00000000000000..6a01266941a27f --- /dev/null +++ b/soc/atmel/sam/sam4l/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam4l/Kconfig b/soc/atmel/sam/sam4l/Kconfig new file mode 100644 index 00000000000000..15ad8ba2583413 --- /dev/null +++ b/soc/atmel/sam/sam4l/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4L + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam4l/Kconfig.defconfig b/soc/atmel/sam/sam4l/Kconfig.defconfig new file mode 100644 index 00000000000000..72116af1342c22 --- /dev/null +++ b/soc/atmel/sam/sam4l/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM4L + +config NUM_IRQS + default 80 + +endif # SOC_SERIES_SAM4L diff --git a/soc/atmel/sam/sam4l/Kconfig.soc b/soc/atmel/sam/sam4l/Kconfig.soc new file mode 100644 index 00000000000000..e622f8a70d12ba --- /dev/null +++ b/soc/atmel/sam/sam4l/Kconfig.soc @@ -0,0 +1,107 @@ +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4L + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM4L Cortex-M4 microcontrollers. + Part No.: SAM4LS8C, SAM4LS8B, SAM4LS8A, SAM4LS4C, SAM4LS4B, + SAM4LS4A, SAM4LS2C, SAM4LS2B, SAM4LS2A, SAM4LC8C, SAM4LC8B, + SAM4LC8A, SAM4LC4C, SAM4LC4B, SAM4LC4A SAM4LC2C, SAM4LC2B, + SAM4LC2A + +config SOC_SERIES + default "sam4l" if SOC_SERIES_SAM4L + +config SOC_SAM4LS2A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS2B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS2C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS4A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS4B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS4C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS8A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS8B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LS8C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC2A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC2B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC2C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC4A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC4B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC4C + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC8A + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC8B + bool + select SOC_SERIES_SAM4L + +config SOC_SAM4LC8C + bool + select SOC_SERIES_SAM4L + +config SOC + default "sam4ls2a" if SOC_SAM4LS2A + default "sam4ls2b" if SOC_SAM4LS2B + default "sam4ls2c" if SOC_SAM4LS2C + default "sam4ls4a" if SOC_SAM4LS4A + default "sam4ls4b" if SOC_SAM4LS4B + default "sam4ls4c" if SOC_SAM4LS4C + default "sam4ls8a" if SOC_SAM4LS8A + default "sam4ls8b" if SOC_SAM4LS8B + default "sam4ls8c" if SOC_SAM4LS8C + default "sam4lc2a" if SOC_SAM4LC2A + default "sam4lc2b" if SOC_SAM4LC2B + default "sam4lc2c" if SOC_SAM4LC2C + default "sam4lc4a" if SOC_SAM4LC4A + default "sam4lc4b" if SOC_SAM4LC4B + default "sam4lc4c" if SOC_SAM4LC4C + default "sam4lc8a" if SOC_SAM4LC8A + default "sam4lc8b" if SOC_SAM4LC8B + default "sam4lc8c" if SOC_SAM4LC8C diff --git a/soc/arm/atmel_sam/sam4l/soc.c b/soc/atmel/sam/sam4l/soc.c similarity index 100% rename from soc/arm/atmel_sam/sam4l/soc.c rename to soc/atmel/sam/sam4l/soc.c diff --git a/soc/atmel/sam/sam4l/soc.h b/soc/atmel/sam/sam4l/soc.h new file mode 100644 index 00000000000000..329178aa2884d1 --- /dev/null +++ b/soc/atmel/sam/sam4l/soc.h @@ -0,0 +1,223 @@ +/* + * Copyright (c) 2020-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM4L family processors. + */ + +#ifndef _SOC_ATMEL_SAM_SAM4L_SOC_H_ +#define _SOC_ATMEL_SAM_SAM4L_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM4LS8C) +#include +#elif defined(CONFIG_SOC_SAM4LS8B) +#include +#elif defined(CONFIG_SOC_SAM4LS8A) +#include +#elif defined(CONFIG_SOC_SAM4LS4C) +#include +#elif defined(CONFIG_SOC_SAM4LS4B) +#include +#elif defined(CONFIG_SOC_SAM4LS4A) +#include +#elif defined(CONFIG_SOC_SAM4LS2C) +#include +#elif defined(CONFIG_SOC_SAM4LS2B) +#include +#elif defined(CONFIG_SOC_SAM4LS2A) +#include +#elif defined(CONFIG_SOC_SAM4LC8C) +#include +#elif defined(CONFIG_SOC_SAM4LC8B) +#include +#elif defined(CONFIG_SOC_SAM4LC8A) +#include +#elif defined(CONFIG_SOC_SAM4LC4C) +#include +#elif defined(CONFIG_SOC_SAM4LC4B) +#include +#elif defined(CONFIG_SOC_SAM4LC4A) +#include +#elif defined(CONFIG_SOC_SAM4LC2C) +#include +#elif defined(CONFIG_SOC_SAM4LC2B) +#include +#elif defined(CONFIG_SOC_SAM4LC2A) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +/** Oscillator identifiers + * External Oscillator 0 + * External 32 kHz oscillator + * Internal 32 kHz RC oscillator + * Internal 80 MHz RC oscillator + * Internal 4-8-12 MHz RCFAST oscillator + * Internal 1 MHz RC oscillator + * Internal System RC oscillator + */ +#define OSC_ID_OSC0 0 +#define OSC_ID_OSC32 1 +#define OSC_ID_RC32K 2 +#define OSC_ID_RC80M 3 +#define OSC_ID_RCFAST 4 +#define OSC_ID_RC1M 5 +#define OSC_ID_RCSYS 6 + +/** System clock source + * System RC oscillator + * Oscillator 0 + * Phase Locked Loop 0 + * Digital Frequency Locked Loop + * 80 MHz RC oscillator + * 4-8-12 MHz RC oscillator + * 1 MHz RC oscillator + */ +#define OSC_SRC_RCSYS 0 +#define OSC_SRC_OSC0 1 +#define OSC_SRC_PLL0 2 +#define OSC_SRC_DFLL 3 +#define OSC_SRC_RC80M 4 +#define OSC_SRC_RCFAST 5 +#define OSC_SRC_RC1M 6 + +#define PM_CLOCK_MASK(bus, per) ((bus << 5) + per) + +/** Bus index of maskable module clocks. Peripheral ids are defined out of + * order. It start from PBA up to PBD, then move to HSB, and finally CPU. + */ +#define PM_CLK_GRP_CPU 5 +#define PM_CLK_GRP_HSB 4 +#define PM_CLK_GRP_PBA 0 +#define PM_CLK_GRP_PBB 1 +#define PM_CLK_GRP_PBC 2 +#define PM_CLK_GRP_PBD 3 + +/** Clocks derived from the CPU clock + */ +#define SYSCLK_OCD 0 + +/** Clocks derived from the HSB clock + */ +#define SYSCLK_PDCA_HSB 0 +#define SYSCLK_HFLASHC_DATA 1 +#define SYSCLK_HRAMC1_DATA 2 +#define SYSCLK_USBC_DATA 3 +#define SYSCLK_CRCCU_DATA 4 +#define SYSCLK_PBA_BRIDGE 5 +#define SYSCLK_PBB_BRIDGE 6 +#define SYSCLK_PBC_BRIDGE 7 +#define SYSCLK_PBD_BRIDGE 8 +#define SYSCLK_AESA_HSB 9 + +/** Clocks derived from the PBA clock + */ +#define SYSCLK_IISC 0 +#define SYSCLK_SPI 1 +#define SYSCLK_TC0 2 +#define SYSCLK_TC1 3 +#define SYSCLK_TWIM0 4 +#define SYSCLK_TWIS0 5 +#define SYSCLK_TWIM1 6 +#define SYSCLK_TWIS1 7 +#define SYSCLK_USART0 8 +#define SYSCLK_USART1 9 +#define SYSCLK_USART2 10 +#define SYSCLK_USART3 11 +#define SYSCLK_ADCIFE 12 +#define SYSCLK_DACC 13 +#define SYSCLK_ACIFC 14 +#define SYSCLK_GLOC 15 +#define SYSCLK_ABDACB 16 +#define SYSCLK_TRNG 17 +#define SYSCLK_PARC 18 +#define SYSCLK_CATB 19 +#define SYSCLK_TWIM2 21 +#define SYSCLK_TWIM3 22 +#define SYSCLK_LCDCA 23 + +/** Clocks derived from the PBB clock + */ +#define SYSCLK_HFLASHC_REGS 0 +#define SYSCLK_HRAMC1_REGS 1 +#define SYSCLK_HMATRIX 2 +#define SYSCLK_PDCA_PB 3 +#define SYSCLK_CRCCU_REGS 4 +#define SYSCLK_USBC_REGS 5 +#define SYSCLK_PEVC 6 + +/** Clocks derived from the PBC clock + */ +#define SYSCLK_PM 0 +#define SYSCLK_CHIPID 1 +#define SYSCLK_SCIF 2 +#define SYSCLK_FREQM 3 +#define SYSCLK_GPIO 4 + +/** Clocks derived from the PBD clock + */ +#define SYSCLK_BPM 0 +#define SYSCLK_BSCIF 1 +#define SYSCLK_AST 2 +#define SYSCLK_WDT 3 +#define SYSCLK_EIC 4 +#define SYSCLK_PICOUART 5 + +/** Divided clock mask derived from the PBA clock + */ +#define PBA_DIVMASK_TIMER_CLOCK2 (1u << 0) +#define PBA_DIVMASK_TIMER_CLOCK3 (1u << 2) +#define PBA_DIVMASK_CLK_USART (1u << 2) +#define PBA_DIVMASK_TIMER_CLOCK4 (1u << 4) +#define PBA_DIVMASK_TIMER_CLOCK5 (1u << 6) +#define PBA_DIVMASK_Msk (0x7Fu << 0) + +/** Generic Clock Instances + * 0- DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF) + * 1- DFLLIF dithering and SSG reference and GCLK1 pin (CLK_DFLLIF_DITHER) + * 2- AST and GCLK2 pin + * 3- CATB and GCLK3 pin + * 4- AESA + * 5- GLOC, TC0 and RC32KIFB_REF + * 6- ABDACB and IISC + * 7- USBC + * 8- TC1 and PEVC[0] + * 9- PLL0 and PEVC[1] + * 10- ADCIFE + * 11- Master generic clock. Can be used as source for other generic clocks. + */ +#define GEN_CLK_DFLL_REF 0 +#define GEN_CLK_DFLL_DITHER 1 +#define GEN_CLK_AST 2 +#define GEN_CLK_CATB 3 +#define GEN_CLK_AESA 4 +#define GEN_CLK_GLOC 5 +#define GEN_CLK_ABDACB 6 +#define GEN_CLK_USBC 7 +#define GEN_CLK_TC1_PEVC0 8 +#define GEN_CLK_PLL0_PEVC1 9 +#define GEN_CLK_ADCIFE 10 +#define GEN_CLK_MASTER_GEN 11 + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM4L_SOC_H_ */ diff --git a/soc/atmel/sam/sam4s/CMakeLists.txt b/soc/atmel/sam/sam4s/CMakeLists.txt new file mode 100644 index 00000000000000..6a01266941a27f --- /dev/null +++ b/soc/atmel/sam/sam4s/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/sam4s/Kconfig b/soc/atmel/sam/sam4s/Kconfig new file mode 100644 index 00000000000000..26836bc509b61d --- /dev/null +++ b/soc/atmel/sam/sam4s/Kconfig @@ -0,0 +1,14 @@ +# Atmel SAM4S MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2020-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4S + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT + select HAS_POWEROFF diff --git a/soc/atmel/sam/sam4s/Kconfig.defconfig b/soc/atmel/sam/sam4s/Kconfig.defconfig new file mode 100644 index 00000000000000..bc78f97f404822 --- /dev/null +++ b/soc/atmel/sam/sam4s/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM4S MCU series configuration options + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAM4S + +config NUM_IRQS + default 35 + +endif # SOC_SERIES_SAM4S diff --git a/soc/atmel/sam/sam4s/Kconfig.soc b/soc/atmel/sam/sam4s/Kconfig.soc new file mode 100644 index 00000000000000..3e3cf5bb3b70e1 --- /dev/null +++ b/soc/atmel/sam/sam4s/Kconfig.soc @@ -0,0 +1,74 @@ +# Atmel SAM4S MCU series + +# Copyright (c) 2017 Justin Watson +# Copyright (c) 2018 Vincent van der Locht +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAM4S + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM4S Cortex-M4 microcontrollers. + Part No.: SAM4S16C, SAM4S16B, SAM4S8C, SAM4S8B, + SAM4S4C, SAM4S4B, SAM4S4A, SAM4S2C, SAM4S2B, SAM4S2A + +config SOC_SERIES + default "sam4s" if SOC_SERIES_SAM4S + +config SOC_SAM4S2A + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S2B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S2C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S4A + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S4B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S4C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S8B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S8C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S16B + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4S16C + bool + select SOC_SERIES_SAM4S + +config SOC_SAM4SA16C + bool + select SOC_SERIES_SAM4S + +config SOC + default "sam4s2a" if SOC_SAM4S2A + default "sam4s2b" if SOC_SAM4S2B + default "sam4s2c" if SOC_SAM4S2C + default "sam4s4a" if SOC_SAM4S4A + default "sam4s4b" if SOC_SAM4S4B + default "sam4s4c" if SOC_SAM4S4C + default "sam4s8b" if SOC_SAM4S8B + default "sam4s8c" if SOC_SAM4S8C + default "sam4s16b" if SOC_SAM4S16B + default "sam4s16c" if SOC_SAM4S16C + default "sam4sa16c" if SOC_SAM4SA16C diff --git a/soc/atmel/sam/sam4s/soc.c b/soc/atmel/sam/sam4s/soc.c new file mode 100644 index 00000000000000..09c42eae391208 --- /dev/null +++ b/soc/atmel/sam/sam4s/soc.c @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2023 Basalte bv + * Copyright (c) 2023-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Atmel SAM4S MCU series initialization code + * + * This module provides routines to initialize and support board-level hardware + * for the Atmel SAM4S series processor. + */ + +#include +#include +#include + +/** + * @brief Setup various clock on SoC at boot time. + * + * Setup the SoC clocks according to section 28.12 in datasheet. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC0->EEFC_FMR = EEFC_FMR_FWS(0); +#if defined(ID_EFC1) + EFC1->EEFC_FMR = EEFC_FMR_FWS(0); +#endif + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. Look at table 44.73 in the SAM4S datasheet. + * This is set to the highest number of read cycles because it won't + * hurt lower clock frequencies. However, a high frequency with too + * few read cycles could cause flash read problems. FWS 5 (6 cycles) + * is the safe setting for all of this SoCs usable frequencies. + */ + EFC0->EEFC_FMR = EEFC_FMR_FWS(5); +#if defined(ID_EFC1) + EFC1->EEFC_FMR = EEFC_FMR_FWS(5); +#endif + + /* + * Setup PLLA + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + /* + * Final setup of the Master Clock + */ + + /* prescaler has to be set before PLL lock */ + soc_pmc_mck_set_prescaler(1); + + /* Select PLL as Master Clock source. */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + + /* Setup system clocks. */ + clock_init(); +} diff --git a/soc/atmel/sam/sam4s/soc.h b/soc/atmel/sam/sam4s/soc.h new file mode 100644 index 00000000000000..f74692d6ba8925 --- /dev/null +++ b/soc/atmel/sam/sam4s/soc.h @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2013-2015 Wind River Systems, Inc. + * Copyright (c) 2016 Intel Corporation. + * Copyright (c) 2017 Justin Watson + * Copyright (c) 2018 Vincent van der Locht + * Copyright (c) 2020-2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file SoC configuration macros for the Atmel SAM4S family processors. + */ + +#ifndef _SOC_ATMEL_SAM_SAM4S_SOC_H_ +#define _SOC_ATMEL_SAM_SAM4S_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAM4S16C) +#include +#elif defined(CONFIG_SOC_SAM4SA16C) +#include +#elif defined(CONFIG_SOC_SAM4S16B) +#include +#elif defined(CONFIG_SOC_SAM4S8C) +#include +#elif defined(CONFIG_SOC_SAM4S8B) +#include +#elif defined(CONFIG_SOC_SAM4S4C) +#include +#elif defined(CONFIG_SOC_SAM4S4B) +#include +#elif defined(CONFIG_SOC_SAM4S4A) +#include +#elif defined(CONFIG_SOC_SAM4S2C) +#include +#elif defined(CONFIG_SOC_SAM4S2B) +#include +#elif defined(CONFIG_SOC_SAM4S2A) +#include +#else +#error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAM4S_SOC_H_ */ diff --git a/soc/atmel/sam/same70/CMakeLists.txt b/soc/atmel/sam/same70/CMakeLists.txt new file mode 100644 index 00000000000000..2ed685c2f6f4f1 --- /dev/null +++ b/soc/atmel/sam/same70/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + soc_config.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/same70/Kconfig b/soc/atmel/sam/same70/Kconfig new file mode 100644 index 00000000000000..f799cd43c6911b --- /dev/null +++ b/soc/atmel/sam/same70/Kconfig @@ -0,0 +1,19 @@ +# Atmel SAM E70 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME70 + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_ARCH_HW_AT_BOOT + select PLATFORM_SPECIFIC_INIT + select HAS_SWO + select XIP + select HAS_POWEROFF diff --git a/soc/atmel/sam/same70/Kconfig.defconfig b/soc/atmel/sam/same70/Kconfig.defconfig new file mode 100644 index 00000000000000..6d2a78218c2f6b --- /dev/null +++ b/soc/atmel/sam/same70/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM E70 MCU series configuration options + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME70 + +config NUM_IRQS + default 74 if SOC_ATMEL_SAME70_REVB + default 71 + +endif # SOC_SERIES_SAME70 diff --git a/soc/atmel/sam/same70/Kconfig.soc b/soc/atmel/sam/same70/Kconfig.soc new file mode 100644 index 00000000000000..1cef18f21f1ca2 --- /dev/null +++ b/soc/atmel/sam/same70/Kconfig.soc @@ -0,0 +1,122 @@ +# Atmel SAM E70 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME70 + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers. + Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20, + SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B, + SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B, + SAME70Q20B, SAME70Q21B + +config SOC_ATMEL_SAME70_REVB + bool + +config SOC_SERIES + default "same70" if SOC_SERIES_SAME70 + +config SOC_SAME70J19 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70J20 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70J21 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70N19 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70N20 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70N21 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70Q19 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70Q20 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70Q21 + bool + select SOC_SERIES_SAME70 + +config SOC_SAME70J19B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70J20B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70J21B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70N19B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70N20B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70N21B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70Q19B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70Q20B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC_SAME70Q21B + bool + select SOC_SERIES_SAME70 + select SOC_ATMEL_SAME70_REVB + +config SOC + default "same70j19" if SOC_SAME70J19 + default "same70j20" if SOC_SAME70J20 + default "same70j21" if SOC_SAME70J21 + default "same70n19" if SOC_SAME70N19 + default "same70n20" if SOC_SAME70N20 + default "same70n21" if SOC_SAME70N21 + default "same70q19" if SOC_SAME70Q19 + default "same70q20" if SOC_SAME70Q20 + default "same70q21" if SOC_SAME70Q21 + default "same70j19b" if SOC_SAME70J19B + default "same70j20b" if SOC_SAME70J20B + default "same70j21b" if SOC_SAME70J21B + default "same70n19b" if SOC_SAME70N19B + default "same70n20b" if SOC_SAME70N20B + default "same70n21b" if SOC_SAME70N21B + default "same70q19b" if SOC_SAME70Q19B + default "same70q20b" if SOC_SAME70Q20B + default "same70q21b" if SOC_SAME70Q21B diff --git a/soc/atmel/sam/same70/soc.c b/soc/atmel/sam/same70/soc.c new file mode 100644 index 00000000000000..ba3a44e875af85 --- /dev/null +++ b/soc/atmel/sam/same70/soc.c @@ -0,0 +1,156 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2023-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Atmel SAM E70 MCU initialization code + * + * This file provides routines to initialize and support board-level hardware + * for the Atmel SAM E70 MCU. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDIO value + * rather than maximum supported 150 MHz at standard VDDIO=2.7V + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; + + /* + * Setup PLLA + */ + + /* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 24, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (24 + 1) / 1 = 300 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK)=300 MHz. + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + + soc_pmc_enable_upllck(0x3Fu); + + /* + * Final setup of the Master Clock + */ + + /* Setting PLLA as MCK, first prescaler, then divider and source last */ + soc_pmc_mck_set_prescaler(1); + soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV); + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + + /* + * DTCM is enabled by default at reset, therefore we have to disable + * it first to get the caches into a state where then the + * sys_cache*-functions can enable them, if requested by the + * configuration. + */ + SCB_DisableDCache(); + + /* + * Enable the caches only if configured to do so. + */ + sys_cache_instr_enable(); + sys_cache_data_enable(); + + /* Setup system clocks */ + clock_init(); +} + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run at the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int atmel_same70_init(void) +{ + /* Check that the CHIP CIDR matches the HAL one */ + if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { + LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", + (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); + } + + return 0; +} + +SYS_INIT(atmel_same70_init, PRE_KERNEL_1, 0); diff --git a/soc/atmel/sam/same70/soc.h b/soc/atmel/sam/same70/soc.h new file mode 100644 index 00000000000000..92cec70d926af0 --- /dev/null +++ b/soc/atmel/sam/same70/soc.h @@ -0,0 +1,82 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM E70 MCU. + * + * This file provides register access macros for the Atmel SAM E70 MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _SOC_ATMEL_SAM_SAME70_SOC_H_ +#define _SOC_ATMEL_SAM_SAME70_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAME70J19) +#include +#elif defined(CONFIG_SOC_SAME70J20) +#include +#elif defined(CONFIG_SOC_SAME70J21) +#include +#elif defined(CONFIG_SOC_SAME70N19) +#include +#elif defined(CONFIG_SOC_SAME70N20) +#include +#elif defined(CONFIG_SOC_SAME70N21) +#include +#elif defined(CONFIG_SOC_SAME70Q19) +#include +#elif defined(CONFIG_SOC_SAME70Q20) +#include +#elif defined(CONFIG_SOC_SAME70Q21) +#include +#elif defined(CONFIG_SOC_SAME70J19B) +#include +#elif defined(CONFIG_SOC_SAME70J20B) +#include +#elif defined(CONFIG_SOC_SAME70J21B) +#include +#elif defined(CONFIG_SOC_SAME70N19B) +#include +#elif defined(CONFIG_SOC_SAME70N20B) +#include +#elif defined(CONFIG_SOC_SAME70N21B) +#include +#elif defined(CONFIG_SOC_SAME70Q19B) +#include +#elif defined(CONFIG_SOC_SAME70Q20B) +#include +#elif defined(CONFIG_SOC_SAME70Q21B) +#include +#else + #error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ + (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV) + +/** UTMI PLL clock (UPLLCK) Frequency */ +#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) + +#endif /* _ASMLANGUAGE */ + +#endif /* _SOC_ATMEL_SAM_SAME70_SOC_H_ */ diff --git a/soc/atmel/sam/same70/soc_config.c b/soc/atmel/sam/same70/soc_config.c new file mode 100644 index 00000000000000..cd1f8b80d76dbe --- /dev/null +++ b/soc/atmel/sam/same70/soc_config.c @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief System module to support early Atmel SAM E70 MCU configuration + */ + +#include +#include +#include +#include + +/** + * @brief Perform SoC configuration at boot. + * + * This should be run early during the boot process but after basic hardware + * initialization is done. + * + * @return 0 + */ +static int atmel_same70_config(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) { + /* Disable ERASE function on PB12 pin, this is controlled + * by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; + } + + /* In Cortex-M based SoCs JTAG interface can be used to perform + * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug + * interface therefore there is no harm done by disabling the JTAG TDI + * pin by default. + */ + /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + + if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) { + /* Disable PCK3 clock used by ETM module */ + PMC->PMC_SCDR = PMC_SCDR_PCK3; + while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { + ; + } + /* Select PLLA clock as PCK3 clock */ + PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; + /* Enable PCK3 clock */ + PMC->PMC_SCER = PMC_SCER_PCK3; + /* Wait for PCK3 setup to complete */ + while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { + ; + } + /* Enable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; + } else { + /* Disable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; + } + + return 0; +} + +SYS_INIT(atmel_same70_config, PRE_KERNEL_1, 1); diff --git a/soc/atmel/sam/samv71/CMakeLists.txt b/soc/atmel/sam/samv71/CMakeLists.txt new file mode 100644 index 00000000000000..2ed685c2f6f4f1 --- /dev/null +++ b/soc/atmel/sam/samv71/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + soc_config.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/atmel/sam/samv71/Kconfig b/soc/atmel/sam/samv71/Kconfig new file mode 100644 index 00000000000000..682adb4a7155c0 --- /dev/null +++ b/soc/atmel/sam/samv71/Kconfig @@ -0,0 +1,19 @@ +# Atmel SAM V71 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMV71 + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_ARCH_HW_AT_BOOT + select PLATFORM_SPECIFIC_INIT + select HAS_SWO + select XIP + select HAS_POWEROFF diff --git a/soc/atmel/sam/samv71/Kconfig.defconfig b/soc/atmel/sam/samv71/Kconfig.defconfig new file mode 100644 index 00000000000000..2eefe71ec55a33 --- /dev/null +++ b/soc/atmel/sam/samv71/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Atmel SAM V71 MCU series configuration options + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMV71 + +config NUM_IRQS + default 74 if SOC_ATMEL_SAMV71_REVB + default 71 + +endif # SOC_SERIES_SAMV71 diff --git a/soc/atmel/sam/samv71/Kconfig.soc b/soc/atmel/sam/samv71/Kconfig.soc new file mode 100644 index 00000000000000..180ed60c49dfeb --- /dev/null +++ b/soc/atmel/sam/samv71/Kconfig.soc @@ -0,0 +1,122 @@ +# Atmel SAM V71 MCU series + +# Copyright (c) 2016 Piotr Mienkowski +# Copyright (c) 2019-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMV71 + bool + select SOC_FAMILY_ATMEL_SAM + help + Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers. + Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20, + SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B, + SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B, + SAMV71Q20B, SAMV71Q21B + +config SOC_ATMEL_SAMV71_REVB + bool + +config SOC_SERIES + default "samv71" if SOC_SERIES_SAMV71 + +config SOC_SAMV71J19 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71J20 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71J21 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71N19 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71N20 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71N21 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71Q19 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71Q20 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71Q21 + bool + select SOC_SERIES_SAMV71 + +config SOC_SAMV71J19B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71J20B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71J21B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71N19B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71N20B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71N21B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71Q19B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71Q20B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC_SAMV71Q21B + bool + select SOC_SERIES_SAMV71 + select SOC_ATMEL_SAMV71_REVB + +config SOC + default "samv71j19" if SOC_SAMV71J19 + default "samv71j20" if SOC_SAMV71J20 + default "samv71j21" if SOC_SAMV71J21 + default "samv71n19" if SOC_SAMV71N19 + default "samv71n20" if SOC_SAMV71N20 + default "samv71n21" if SOC_SAMV71N21 + default "samv71q19" if SOC_SAMV71Q19 + default "samv71q20" if SOC_SAMV71Q20 + default "samv71q21" if SOC_SAMV71Q21 + default "samv71j19b" if SOC_SAMV71J19B + default "samv71j20b" if SOC_SAMV71J20B + default "samv71j21b" if SOC_SAMV71J21B + default "samv71n19b" if SOC_SAMV71N19B + default "samv71n20b" if SOC_SAMV71N20B + default "samv71n21b" if SOC_SAMV71N21B + default "samv71q19b" if SOC_SAMV71Q19B + default "samv71q20b" if SOC_SAMV71Q20B + default "samv71q21b" if SOC_SAMV71Q21B diff --git a/soc/atmel/sam/samv71/soc.c b/soc/atmel/sam/samv71/soc.c new file mode 100644 index 00000000000000..c1b58bc126e81e --- /dev/null +++ b/soc/atmel/sam/samv71/soc.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2019-2023 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Atmel SAM V71 MCU initialization code + * + * This file provides routines to initialize and support board-level hardware + * for the Atmel SAM V71 MCU. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL +LOG_MODULE_REGISTER(soc); + +/** + * @brief Setup various clocks on SoC at boot time. + * + * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot. + * It is assumed that the relevant registers are at their reset value. + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Switch the main clock to the internal OSC with 12MHz */ + soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ); + + /* Switch MCK (Master Clock) to the main clock */ + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK); + + EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE; + + soc_pmc_enable_clock_failure_detector(); + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) { + soc_supc_slow_clock_select_crystal_osc(); + } + + + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + /* + * Setup main external crystal oscillator. + */ + + /* We select maximum setup time. + * While start up time could be shortened + * this optimization is not deemed + * critical now. + */ + soc_pmc_switch_mainck_to_xtal(false, 0xff); + } + + /* + * Set FWS (Flash Wait State) value before increasing Master Clock + * (MCK) frequency. + * TODO: set FWS based on the actual MCK frequency and VDDIO value + * rather than maximum supported 150 MHz at standard VDDIO=2.7V + */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE; + + /* + * Setup PLLA + */ + + /* + * PLL clock = Main * (MULA + 1) / DIVA + * + * By default, MULA == 24, DIVA == 1. + * With main crystal running at 12 MHz, + * PLL = 12 * (24 + 1) / 1 = 300 MHz + * + * With Processor Clock prescaler at 1 + * Processor Clock (HCLK)=300 MHz. + */ + soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu, + CONFIG_SOC_ATMEL_SAM_PLLA_DIVA); + + + soc_pmc_enable_upllck(0x3Fu); + + /* + * Final setup of the Master Clock + */ + + /* Setting PLLA as MCK, first prescaler, then divider and source last */ + soc_pmc_mck_set_prescaler(1); + soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV); + soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK); + + /* Disable internal fast RC if we have an external crystal oscillator */ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) { + soc_pmc_osc_disable_fastrc(); + } +} + +void z_arm_platform_init(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) { + /* + * Instruct CPU to enter Wait mode instead of Sleep mode to + * keep Processor Clock (HCLK) and thus be able to debug + * CPU using JTAG. + */ + soc_pmc_enable_waitmode(); + } + + /* + * DTCM is enabled by default at reset, therefore we have to disable + * it first to get the caches into a state where then the + * sys_cache*-functions can enable them, if requested by the + * configuration. + */ + SCB_DisableDCache(); + + /* + * Enable the caches only if configured to do so. + */ + sys_cache_instr_enable(); + sys_cache_data_enable(); + + /* Setup system clocks */ + clock_init(); +} + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run at the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int atmel_samv71_init(void) +{ + /* Check that the CHIP CIDR matches the HAL one */ + if (CHIPID->CHIPID_CIDR != CHIP_CIDR) { + LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x", + (uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR); + } + + return 0; +} + +SYS_INIT(atmel_samv71_init, PRE_KERNEL_1, 0); diff --git a/soc/atmel/sam/samv71/soc.h b/soc/atmel/sam/samv71/soc.h new file mode 100644 index 00000000000000..8b54125bce52ee --- /dev/null +++ b/soc/atmel/sam/samv71/soc.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2019-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Register access macros for the Atmel SAM V71 MCU. + * + * This file provides register access macros for the Atmel SAM V71 MCU, HAL + * drivers for core peripherals as well as symbols specific to Atmel SAM family. + */ + +#ifndef _SOC_ATMEL_SAM_SAMV71_SOC_H_ +#define _SOC_ATMEL_SAM_SAMV71_SOC_H_ + +#include + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT +#define DONT_USE_PREDEFINED_CORE_HANDLERS +#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS + +#if defined(CONFIG_SOC_SAMV71J19) +#include +#elif defined(CONFIG_SOC_SAMV71J20) +#include +#elif defined(CONFIG_SOC_SAMV71J21) +#include +#elif defined(CONFIG_SOC_SAMV71N19) +#include +#elif defined(CONFIG_SOC_SAMV71N20) +#include +#elif defined(CONFIG_SOC_SAMV71N21) +#include +#elif defined(CONFIG_SOC_SAMV71Q19) +#include +#elif defined(CONFIG_SOC_SAMV71Q20) +#include +#elif defined(CONFIG_SOC_SAMV71Q21) +#include +#elif defined(CONFIG_SOC_SAMV71J19B) +#include +#elif defined(CONFIG_SOC_SAMV71J20B) +#include +#elif defined(CONFIG_SOC_SAMV71J21B) +#include +#elif defined(CONFIG_SOC_SAMV71N19B) +#include +#elif defined(CONFIG_SOC_SAMV71N20B) +#include +#elif defined(CONFIG_SOC_SAMV71N21B) +#include +#elif defined(CONFIG_SOC_SAMV71Q19B) +#include +#elif defined(CONFIG_SOC_SAMV71Q20B) +#include +#elif defined(CONFIG_SOC_SAMV71Q21B) +#include +#else + #error Library does not support the specified device. +#endif + +#include "../common/soc_pmc.h" +#include "../common/soc_gpio.h" +#include "../common/soc_supc.h" +#include "../common/atmel_sam_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM_MCK_FREQ_HZ \ + (SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV) + +/** UTMI PLL clock (UPLLCK) Frequency */ +#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480) + +#endif /* _ASMLANGUAGE */ + +#include "pwm_fixup.h" + +#endif /* _SOC_ATMEL_SAM_SAMV71_SOC_H_ */ diff --git a/soc/atmel/sam/samv71/soc_config.c b/soc/atmel/sam/samv71/soc_config.c new file mode 100644 index 00000000000000..51638a997b3752 --- /dev/null +++ b/soc/atmel/sam/samv71/soc_config.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016 Piotr Mienkowski + * Copyright (c) 2019-2024 Gerson Fernando Budke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief System module to support early Atmel SAM V71 MCU configuration + */ + +#include +#include +#include +#include + +/** + * @brief Perform SoC configuration at boot. + * + * This should be run early during the boot process but after basic hardware + * initialization is done. + * + * @return 0 + */ +static int atmel_samv71_config(void) +{ + if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) { + /* Disable ERASE function on PB12 pin, this is controlled + * by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12; + } + + /* In Cortex-M based SoCs JTAG interface can be used to perform + * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug + * interface therefore there is no harm done by disabling the JTAG TDI + * pin by default. + */ + /* Disable TDI function on PB4 pin, this is controlled by Bus Matrix + */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + + if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) { + /* Disable PCK3 clock used by ETM module */ + PMC->PMC_SCDR = PMC_SCDR_PCK3; + while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) { + ; + } + /* Select PLLA clock as PCK3 clock */ + PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK; + /* Enable PCK3 clock */ + PMC->PMC_SCER = PMC_SCER_PCK3; + /* Wait for PCK3 setup to complete */ + while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) { + ; + } + /* Enable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5; + } else { + /* Disable TDO/TRACESWO function on PB5 pin */ + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5; + } + + return 0; +} + +SYS_INIT(atmel_samv71_config, PRE_KERNEL_1, 1); diff --git a/soc/atmel/sam/soc.yml b/soc/atmel/sam/soc.yml new file mode 100644 index 00000000000000..9d95bcdf147f4a --- /dev/null +++ b/soc/atmel/sam/soc.yml @@ -0,0 +1,89 @@ +family: +- name: atmel_sam + series: + - name: sam3x + socs: + - name: sam3x4c + - name: sam3x4e + - name: sam3x8c + - name: sam3x8e + - name: sam3x8h + - name: sam4e + socs: + - name: sam4e8c + - name: sam4e8e + - name: sam4e16c + - name: sam4e16e + - name: sam4l + socs: + - name: sam4ls2a + - name: sam4ls2b + - name: sam4ls2c + - name: sam4ls4a + - name: sam4ls4b + - name: sam4ls4c + - name: sam4ls8a + - name: sam4ls8b + - name: sam4ls8c + - name: sam4lc2a + - name: sam4lc2b + - name: sam4lc2c + - name: sam4lc4a + - name: sam4lc4b + - name: sam4lc4c + - name: sam4lc8a + - name: sam4lc8b + - name: sam4lc8c + - name: sam4s + socs: + - name: sam4s2a + - name: sam4s2b + - name: sam4s2c + - name: sam4s4a + - name: sam4s4b + - name: sam4s4c + - name: sam4s8b + - name: sam4s8c + - name: sam4s16b + - name: sam4s16c + - name: sam4sa16c + - name: same70 + socs: + - name: same70j19 + - name: same70j20 + - name: same70j21 + - name: same70n19 + - name: same70n20 + - name: same70n21 + - name: same70q19 + - name: same70q20 + - name: same70q21 + - name: same70j19b + - name: same70j20b + - name: same70j21b + - name: same70n19b + - name: same70n20b + - name: same70n21b + - name: same70q19b + - name: same70q20b + - name: same70q21b + - name: samv71 + socs: + - name: samv71j19 + - name: samv71j20 + - name: samv71j21 + - name: samv71n19 + - name: samv71n20 + - name: samv71n21 + - name: samv71q19 + - name: samv71q20 + - name: samv71q21 + - name: samv71j19b + - name: samv71j20b + - name: samv71j21b + - name: samv71n19b + - name: samv71n20b + - name: samv71n21b + - name: samv71q19b + - name: samv71q20b + - name: samv71q21b diff --git a/soc/atmel/sam0/CMakeLists.txt b/soc/atmel/sam0/CMakeLists.txt new file mode 100644 index 00000000000000..377651e4f4de56 --- /dev/null +++ b/soc/atmel/sam0/CMakeLists.txt @@ -0,0 +1,10 @@ +# Makefile - Atmel SAM0 MCU family +# +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/atmel/sam0/Kconfig b/soc/atmel/sam0/Kconfig new file mode 100644 index 00000000000000..f5d2f29b879d77 --- /dev/null +++ b/soc/atmel/sam0/Kconfig @@ -0,0 +1,16 @@ +# Atmel SAM0 MCU family configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM0 + select ASF + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_ATMEL_SAM0 + +rsource "common/Kconfig.sam*" +rsource "*/Kconfig" + +endif # SOC_FAMILY_ATMEL_SAM0 diff --git a/soc/atmel/sam0/Kconfig.defconfig b/soc/atmel/sam0/Kconfig.defconfig new file mode 100644 index 00000000000000..2980bbe87c49ce --- /dev/null +++ b/soc/atmel/sam0/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Atmel SAM0 MCU family default configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ATMEL_SAM0 + +rsource "*/Kconfig.defconfig" + +config GPIO + default y + +config HWINFO_SAM0 + default HWINFO + +config PINCTRL + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +if USB_DEVICE_DRIVER + +config HEAP_MEM_POOL_ADD_SIZE_SOC + def_int 1024 + +endif # USB_DEVICE_DRIVER + +endif # SOC_FAMILY_ATMEL_SAM0 diff --git a/soc/atmel/sam0/Kconfig.soc b/soc/atmel/sam0/Kconfig.soc new file mode 100644 index 00000000000000..96697d51625363 --- /dev/null +++ b/soc/atmel/sam0/Kconfig.soc @@ -0,0 +1,21 @@ +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2022-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ATMEL_SAM0 + bool + +config SOC_FAMILY + default "atmel_sam0" if SOC_FAMILY_ATMEL_SAM0 + +config SOC_SERIES_REVISION_N + bool + depends on SOC_FAMILY_ATMEL_SAM0 + +config SOC_SERIES_REVISION + string + default "n" if SOC_SERIES_REVISION_N + default "" + depends on SOC_FAMILY_ATMEL_SAM0 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/atmel_sam0/common/CMakeLists.txt b/soc/atmel/sam0/common/CMakeLists.txt similarity index 100% rename from soc/arm/atmel_sam0/common/CMakeLists.txt rename to soc/atmel/sam0/common/CMakeLists.txt diff --git a/soc/arm/atmel_sam0/common/Kconfig.samd2x b/soc/atmel/sam0/common/Kconfig.samd2x similarity index 100% rename from soc/arm/atmel_sam0/common/Kconfig.samd2x rename to soc/atmel/sam0/common/Kconfig.samd2x diff --git a/soc/arm/atmel_sam0/common/Kconfig.samd5x b/soc/atmel/sam0/common/Kconfig.samd5x similarity index 75% rename from soc/arm/atmel_sam0/common/Kconfig.samd5x rename to soc/atmel/sam0/common/Kconfig.samd5x index fabb588379c391..dd05fe605d1e47 100644 --- a/soc/arm/atmel_sam0/common/Kconfig.samd5x +++ b/soc/atmel/sam0/common/Kconfig.samd5x @@ -12,10 +12,17 @@ config SOC_ATMEL_SAMD5X_XOSC32K choice prompt "Main clock source" + default SOC_ATMEL_SAMD5X_DEFAULT_AS_MAIN help Selects the clock that the main clocks, such as the CPU clock and AHB clock, will be derived from. +config SOC_ATMEL_SAMD5X_DEFAULT_AS_MAIN + bool "DEFAULT" + help + This choice will leave all clocks to their current state. + This can be the default reset state or a state set by a bootloader. + config SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN depends on SOC_ATMEL_SAMD5X_XOSC32K bool "XOSC32K" diff --git a/soc/arm/atmel_sam0/common/Kconfig.saml2x b/soc/atmel/sam0/common/Kconfig.saml2x similarity index 100% rename from soc/arm/atmel_sam0/common/Kconfig.saml2x rename to soc/atmel/sam0/common/Kconfig.saml2x index 7dfa137678a5e4..d250f1adaf0833 100644 --- a/soc/arm/atmel_sam0/common/Kconfig.saml2x +++ b/soc/atmel/sam0/common/Kconfig.saml2x @@ -71,8 +71,6 @@ config SOC_ATMEL_SAML_OSC16M_AS_MAIN endchoice -endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35 - config SOC_ATMEL_SAMR3X_RADIO_OFF_SETUP bool "Configure LoRa radio pins if not in use" default y if !LORA @@ -84,3 +82,5 @@ config SOC_ATMEL_SAMR3X_RADIO_OFF_SETUP further reduce power consumption, radio can be kept in reset state by keeping nRST pin low. When enabling this option, both CS and nRST will be configured high and low, respectively. + +endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35 diff --git a/soc/arm/atmel_sam0/common/adc_fixup_sam0.h b/soc/atmel/sam0/common/adc_fixup_sam0.h similarity index 100% rename from soc/arm/atmel_sam0/common/adc_fixup_sam0.h rename to soc/atmel/sam0/common/adc_fixup_sam0.h diff --git a/soc/arm/atmel_sam0/common/atmel_sam0_dt.h b/soc/atmel/sam0/common/atmel_sam0_dt.h similarity index 100% rename from soc/arm/atmel_sam0/common/atmel_sam0_dt.h rename to soc/atmel/sam0/common/atmel_sam0_dt.h diff --git a/soc/arm/atmel_sam0/common/bossa.c b/soc/atmel/sam0/common/bossa.c similarity index 100% rename from soc/arm/atmel_sam0/common/bossa.c rename to soc/atmel/sam0/common/bossa.c diff --git a/soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h b/soc/atmel/sam0/common/gmac_fixup_samd5x.h similarity index 100% rename from soc/arm/atmel_sam0/common/gmac_fixup_samd5x.h rename to soc/atmel/sam0/common/gmac_fixup_samd5x.h diff --git a/soc/arm/atmel_sam0/common/pinctrl_soc.h b/soc/atmel/sam0/common/pinctrl_soc.h similarity index 100% rename from soc/arm/atmel_sam0/common/pinctrl_soc.h rename to soc/atmel/sam0/common/pinctrl_soc.h diff --git a/soc/arm/atmel_sam0/common/sercom_fixup_samd5x.h b/soc/atmel/sam0/common/sercom_fixup_samd5x.h similarity index 100% rename from soc/arm/atmel_sam0/common/sercom_fixup_samd5x.h rename to soc/atmel/sam0/common/sercom_fixup_samd5x.h diff --git a/soc/arm/atmel_sam0/common/soc_port.c b/soc/atmel/sam0/common/soc_port.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_port.c rename to soc/atmel/sam0/common/soc_port.c diff --git a/soc/arm/atmel_sam0/common/soc_port.h b/soc/atmel/sam0/common/soc_port.h similarity index 100% rename from soc/arm/atmel_sam0/common/soc_port.h rename to soc/atmel/sam0/common/soc_port.h diff --git a/soc/arm/atmel_sam0/common/soc_samc2x.c b/soc/atmel/sam0/common/soc_samc2x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samc2x.c rename to soc/atmel/sam0/common/soc_samc2x.c diff --git a/soc/arm/atmel_sam0/common/soc_samd2x.c b/soc/atmel/sam0/common/soc_samd2x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samd2x.c rename to soc/atmel/sam0/common/soc_samd2x.c diff --git a/soc/arm/atmel_sam0/common/soc_samd5x.c b/soc/atmel/sam0/common/soc_samd5x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samd5x.c rename to soc/atmel/sam0/common/soc_samd5x.c diff --git a/soc/arm/atmel_sam0/common/soc_saml2x.c b/soc/atmel/sam0/common/soc_saml2x.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_saml2x.c rename to soc/atmel/sam0/common/soc_saml2x.c diff --git a/soc/arm/atmel_sam0/common/soc_samr3x_radio_off.c b/soc/atmel/sam0/common/soc_samr3x_radio_off.c similarity index 100% rename from soc/arm/atmel_sam0/common/soc_samr3x_radio_off.c rename to soc/atmel/sam0/common/soc_samr3x_radio_off.c diff --git a/soc/arm/atmel_sam0/common/tc_fixup_samd5x.h b/soc/atmel/sam0/common/tc_fixup_samd5x.h similarity index 100% rename from soc/arm/atmel_sam0/common/tc_fixup_samd5x.h rename to soc/atmel/sam0/common/tc_fixup_samd5x.h diff --git a/soc/atmel/sam0/samc20/CMakeLists.txt b/soc/atmel/sam0/samc20/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samc20/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samc20/Kconfig b/soc/atmel/sam0/samc20/Kconfig new file mode 100644 index 00000000000000..8c9345e000ff2d --- /dev/null +++ b/soc/atmel/sam0/samc20/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMC20 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC20 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samc20/Kconfig.defconfig b/soc/atmel/sam0/samc20/Kconfig.defconfig new file mode 100644 index 00000000000000..ed71a4412be52c --- /dev/null +++ b/soc/atmel/sam0/samc20/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMC20 MCU series configuration options + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMC20 + +config NUM_IRQS + default 32 + +endif # SOC_SERIES_SAMC20 diff --git a/soc/atmel/sam0/samc20/Kconfig.soc b/soc/atmel/sam0/samc20/Kconfig.soc new file mode 100644 index 00000000000000..b64c915745d8a5 --- /dev/null +++ b/soc/atmel/sam0/samc20/Kconfig.soc @@ -0,0 +1,98 @@ +# Atmel SAMC20 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC20 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMC20 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samc20" if SOC_SERIES_SAMC20 + +config SOC_SAMC20E15A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20E16A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20E17A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20E18A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G15A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G16A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G17A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20G18A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J15A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J16A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J17A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J18A + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J17AU + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20J18AU + bool + select SOC_SERIES_SAMC20 + +config SOC_SAMC20N17A + bool + select SOC_SERIES_SAMC20 + select SOC_SERIES_REVISION_N + +config SOC_SAMC20N18A + bool + select SOC_SERIES_SAMC20 + select SOC_SERIES_REVISION_N + +config SOC + default "samc20e15a" if SOC_SAMC20E15A + default "samc20e16a" if SOC_SAMC20E16A + default "samc20e17a" if SOC_SAMC20E17A + default "samc20e18a" if SOC_SAMC20E18A + default "samc20g15a" if SOC_SAMC20G15A + default "samc20g16a" if SOC_SAMC20G16A + default "samc20g17a" if SOC_SAMC20G17A + default "samc20g18a" if SOC_SAMC20G18A + default "samc20j15a" if SOC_SAMC20J15A + default "samc20j16a" if SOC_SAMC20J16A + default "samc20j17a" if SOC_SAMC20J17A + default "samc20j18a" if SOC_SAMC20J18A + default "samc20j17au" if SOC_SAMC20J17AU + default "samc20j18au" if SOC_SAMC20J18AU + default "samc20n17a" if SOC_SAMC20N17A + default "samc20n18a" if SOC_SAMC20N18A diff --git a/soc/atmel/sam0/samc20/soc.h b/soc/atmel/sam0/samc20/soc.h new file mode 100644 index 00000000000000..fbf967444f9dcb --- /dev/null +++ b/soc/atmel/sam0/samc20/soc.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMC20_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMC20_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMC20E15A) +#include +#elif defined(CONFIG_SOC_SAMC20E16A) +#include +#elif defined(CONFIG_SOC_SAMC20E17A) +#include +#elif defined(CONFIG_SOC_SAMC20E18A) +#include +#elif defined(CONFIG_SOC_SAMC20G15A) +#include +#elif defined(CONFIG_SOC_SAMC20G16A) +#include +#elif defined(CONFIG_SOC_SAMC20G17A) +#include +#elif defined(CONFIG_SOC_SAMC20G18A) +#include +#elif defined(CONFIG_SOC_SAMC20J15A) +#include +#elif defined(CONFIG_SOC_SAMC20J16A) +#include +#elif defined(CONFIG_SOC_SAMC20J17A) +#include +#elif defined(CONFIG_SOC_SAMC20J18A) +#include +#elif defined(CONFIG_SOC_SAMC20J17AU) +#include +#elif defined(CONFIG_SOC_SAMC20J18AU) +#include +#elif defined(CONFIG_SOC_SAMC20N17A) +#include +#elif defined(CONFIG_SOC_SAMC20N18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMC20_SOC_H_ */ diff --git a/soc/atmel/sam0/samc21/CMakeLists.txt b/soc/atmel/sam0/samc21/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samc21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samc21/Kconfig b/soc/atmel/sam0/samc21/Kconfig new file mode 100644 index 00000000000000..51637a0b4ba2cd --- /dev/null +++ b/soc/atmel/sam0/samc21/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAMC21 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samc21/Kconfig.defconfig b/soc/atmel/sam0/samc21/Kconfig.defconfig new file mode 100644 index 00000000000000..cafc565f48eb0e --- /dev/null +++ b/soc/atmel/sam0/samc21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMC21 MCU series configuration options + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMC21 + +config NUM_IRQS + default 32 + +endif # SOC_SERIES_SAMC21 diff --git a/soc/atmel/sam0/samc21/Kconfig.soc b/soc/atmel/sam0/samc21/Kconfig.soc new file mode 100644 index 00000000000000..4ccf0e6bdde446 --- /dev/null +++ b/soc/atmel/sam0/samc21/Kconfig.soc @@ -0,0 +1,98 @@ +# Atmel SAMC21 MCU series + +# Copyright (c) 2022 Kamil Serwus +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMC21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMC21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samc21" if SOC_SERIES_SAMC21 + +config SOC_SAMC21E15A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21E16A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21E17A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21E18A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G15A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G16A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G17A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21G18A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J15A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J16A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J17A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J18A + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J17AU + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21J18AU + bool + select SOC_SERIES_SAMC21 + +config SOC_SAMC21N17A + bool + select SOC_SERIES_SAMC21 + select SOC_SERIES_REVISION_N + +config SOC_SAMC21N18A + bool + select SOC_SERIES_SAMC21 + select SOC_SERIES_REVISION_N + +config SOC + default "samc21e15a" if SOC_SAMC21E15A + default "samc21e16a" if SOC_SAMC21E16A + default "samc21e17a" if SOC_SAMC21E17A + default "samc21e18a" if SOC_SAMC21E18A + default "samc21g15a" if SOC_SAMC21G15A + default "samc21g16a" if SOC_SAMC21G16A + default "samc21g17a" if SOC_SAMC21G17A + default "samc21g18a" if SOC_SAMC21G18A + default "samc21j15a" if SOC_SAMC21J15A + default "samc21j16a" if SOC_SAMC21J16A + default "samc21j17a" if SOC_SAMC21J17A + default "samc21j18a" if SOC_SAMC21J18A + default "samc21j17au" if SOC_SAMC21J17AU + default "samc21j18au" if SOC_SAMC21J18AU + default "samc21n17a" if SOC_SAMC21N17A + default "samc21n18a" if SOC_SAMC21N18A diff --git a/soc/atmel/sam0/samc21/soc.h b/soc/atmel/sam0/samc21/soc.h new file mode 100644 index 00000000000000..ad29ad71383567 --- /dev/null +++ b/soc/atmel/sam0/samc21/soc.h @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2022 Kamil Serwus + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMC21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMC21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMC21E15A) +#include +#elif defined(CONFIG_SOC_SAMC21E16A) +#include +#elif defined(CONFIG_SOC_SAMC21E17A) +#include +#elif defined(CONFIG_SOC_SAMC21E18A) +#include +#elif defined(CONFIG_SOC_SAMC21G15A) +#include +#elif defined(CONFIG_SOC_SAMC21G16A) +#include +#elif defined(CONFIG_SOC_SAMC21G17A) +#include +#elif defined(CONFIG_SOC_SAMC21G18A) +#include +#elif defined(CONFIG_SOC_SAMC21J15A) +#include +#elif defined(CONFIG_SOC_SAMC21J16A) +#include +#elif defined(CONFIG_SOC_SAMC21J17A) +#include +#elif defined(CONFIG_SOC_SAMC21J18A) +#include +#elif defined(CONFIG_SOC_SAMC21J17AU) +#include +#elif defined(CONFIG_SOC_SAMC21J18AU) +#include +#elif defined(CONFIG_SOC_SAMC21N17A) +#include +#elif defined(CONFIG_SOC_SAMC21N18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC48M_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMC21_SOC_H_ */ diff --git a/soc/atmel/sam0/samd20/CMakeLists.txt b/soc/atmel/sam0/samd20/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samd20/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samd20/Kconfig b/soc/atmel/sam0/samd20/Kconfig new file mode 100644 index 00000000000000..1fea4396b5f497 --- /dev/null +++ b/soc/atmel/sam0/samd20/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMD20 MCU series + +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD20 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samd20/Kconfig.defconfig b/soc/atmel/sam0/samd20/Kconfig.defconfig new file mode 100644 index 00000000000000..26e007d98b9a7a --- /dev/null +++ b/soc/atmel/sam0/samd20/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMD20 MCU series configuration options + +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMD20 + +config NUM_IRQS + default 25 + +endif # SOC_SERIES_SAMD20 diff --git a/soc/atmel/sam0/samd20/Kconfig.soc b/soc/atmel/sam0/samd20/Kconfig.soc new file mode 100644 index 00000000000000..0c629653f0bc8e --- /dev/null +++ b/soc/atmel/sam0/samd20/Kconfig.soc @@ -0,0 +1,100 @@ +# Atmel SAMD20 MCU series + +# Copyright (c) 2018 Sean Nyekjaer +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD20 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMD20 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samd20" if SOC_SERIES_SAMD20 + +config SOC_SAMD20E14 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E15 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E16 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E17 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20E18 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G14 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G15 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G16 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G17 + bool + +config SOC_SAMD20G18 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G17U + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20G18U + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J14 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J15 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J16 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J17 + bool + select SOC_SERIES_SAMD20 + +config SOC_SAMD20J18 + bool + select SOC_SERIES_SAMD20 + +config SOC + default "samd20e14" if SOC_SAMD20E14 + default "samd20e15" if SOC_SAMD20E15 + default "samd20e16" if SOC_SAMD20E16 + default "samd20e17" if SOC_SAMD20E17 + default "samd20e18" if SOC_SAMD20E18 + default "samd20g14" if SOC_SAMD20G14 + default "samd20g15" if SOC_SAMD20G15 + default "samd20g16" if SOC_SAMD20G16 + default "samd20g17" if SOC_SAMD20G17 + default "samd20g18" if SOC_SAMD20G18 + default "samd20g17u" if SOC_SAMD20G17U + default "samd20g18u" if SOC_SAMD20G18U + default "samd20j14" if SOC_SAMD20J14 + default "samd20j15" if SOC_SAMD20J15 + default "samd20j16" if SOC_SAMD20J16 + default "samd20j17" if SOC_SAMD20J17 + default "samd20j18" if SOC_SAMD20J18 diff --git a/soc/atmel/sam0/samd20/soc.h b/soc/atmel/sam0/samd20/soc.h new file mode 100644 index 00000000000000..9fed14706f8558 --- /dev/null +++ b/soc/atmel/sam0/samd20/soc.h @@ -0,0 +1,122 @@ +/* + * Copyright (c) 2018 Sean Nyekjaer + * Copyright (c) 2023 Ionut Catalin Pavel + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMD20_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMD20_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMD20E14) +#include +#elif defined(CONFIG_SOC_SAMD20E15) +#include +#elif defined(CONFIG_SOC_SAMD20E16) +#include +#elif defined(CONFIG_SOC_SAMD20E17) +#include +#elif defined(CONFIG_SOC_SAMD20E18) +#include +#elif defined(CONFIG_SOC_SAMD20G14) +#include +#elif defined(CONFIG_SOC_SAMD20G15) +#include +#elif defined(CONFIG_SOC_SAMD20G16) +#include +#elif defined(CONFIG_SOC_SAMD20G17) +#include +#elif defined(CONFIG_SOC_SAMD20G18) +#include +#elif defined(CONFIG_SOC_SAMD20G17U) +#include +#elif defined(CONFIG_SOC_SAMD20G18U) +#include +#elif defined(CONFIG_SOC_SAMD20J14) +#include +#elif defined(CONFIG_SOC_SAMD20J15) +#include +#elif defined(CONFIG_SOC_SAMD20J16) +#include +#elif defined(CONFIG_SOC_SAMD20J17) +#include +#elif defined(CONFIG_SOC_SAMD20J18) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ + +/** Known values */ +#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 +#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 + +/** GCLK1 source frequency selector */ +#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +/** Dividers and frequency for GCLK0 */ +#define SOC_ATMEL_SAM0_GCLK0_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +/** DFLL48M output frequency */ +#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ + (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) + +/** Dividers and frequency for GCLK1 */ +#define SOC_ATMEL_SAM0_GCLK1_DIV \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) + +/** DFLL48M output multiplier */ +#define SOC_ATMEL_SAM0_DFLL48M_MUL \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) + +/** Frequency for GCLK2 */ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ + +/** Dividers and frequency for GCLK3 */ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMD20_SOC_H_ */ diff --git a/soc/atmel/sam0/samd21/CMakeLists.txt b/soc/atmel/sam0/samd21/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samd21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samd21/Kconfig b/soc/atmel/sam0/samd21/Kconfig new file mode 100644 index 00000000000000..f968f52246a195 --- /dev/null +++ b/soc/atmel/sam0/samd21/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMD21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samd21/Kconfig.defconfig b/soc/atmel/sam0/samd21/Kconfig.defconfig new file mode 100644 index 00000000000000..f077951fdcb6e8 --- /dev/null +++ b/soc/atmel/sam0/samd21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMD21 MCU series configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMD21 + +config NUM_IRQS + default 28 + +endif # SOC_SERIES_SAMD21 diff --git a/soc/atmel/sam0/samd21/Kconfig.soc b/soc/atmel/sam0/samd21/Kconfig.soc new file mode 100644 index 00000000000000..70d3df11ad3264 --- /dev/null +++ b/soc/atmel/sam0/samd21/Kconfig.soc @@ -0,0 +1,90 @@ +# Atmel SAMD21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMD21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samd21" if SOC_SERIES_SAMD21 + +config SOC_SAMD21E15A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E16A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E17A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E18A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21E19A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G15A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G16A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G17A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G18A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G17AU + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21G18AU + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J15A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J16A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J17A + bool + select SOC_SERIES_SAMD21 + +config SOC_SAMD21J18A + bool + select SOC_SERIES_SAMD21 + +config SOC + default "samd21e15a" if SOC_SAMD21E15A + default "samd21e16a" if SOC_SAMD21E16A + default "samd21e17a" if SOC_SAMD21E17A + default "samd21e18a" if SOC_SAMD21E18A + default "samd21g15a" if SOC_SAMD21G15A + default "samd21g16a" if SOC_SAMD21G16A + default "samd21g17a" if SOC_SAMD21G17A + default "samd21g18a" if SOC_SAMD21G18A + default "samd21g17au" if SOC_SAMD21G17AU + default "samd21g18au" if SOC_SAMD21G18AU + default "samd21j15a" if SOC_SAMD21J15A + default "samd21j16a" if SOC_SAMD21J16A + default "samd21j17a" if SOC_SAMD21J17A + default "samd21j18a" if SOC_SAMD21J18A diff --git a/soc/atmel/sam0/samd21/soc.h b/soc/atmel/sam0/samd21/soc.h new file mode 100644 index 00000000000000..db93c5a954da40 --- /dev/null +++ b/soc/atmel/sam0/samd21/soc.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2017 Google LLC. + * Copyright (c) 2023 Ionut Catalin Pavel + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMD21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMD21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMD21E15A) +#include +#elif defined(CONFIG_SOC_SAMD21E16A) +#include +#elif defined(CONFIG_SOC_SAMD21E17A) +#include +#elif defined(CONFIG_SOC_SAMD21E18A) +#include +#elif defined(CONFIG_SOC_SAMD21G15A) +#include +#elif defined(CONFIG_SOC_SAMD21G16A) +#include +#elif defined(CONFIG_SOC_SAMD21G17A) +#include +#elif defined(CONFIG_SOC_SAMD21G18A) +#include +#elif defined(CONFIG_SOC_SAMD21G17AU) +#include +#elif defined(CONFIG_SOC_SAMD21G18AU) +#include +#elif defined(CONFIG_SOC_SAMD21J15A) +#include +#elif defined(CONFIG_SOC_SAMD21J16A) +#include +#elif defined(CONFIG_SOC_SAMD21J17A) +#include +#elif defined(CONFIG_SOC_SAMD21J18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ + +/** Known values */ +#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 +#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 + +/** GCLK1 source frequency selector */ +#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +/** Dividers and frequency for GCLK0 */ +#define SOC_ATMEL_SAM0_GCLK0_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +/** DFLL48M output frequency */ +#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ + (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) + +/** Dividers and frequency for GCLK1 */ +#define SOC_ATMEL_SAM0_GCLK1_DIV \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) + +/** DFLL48M output multiplier */ +#define SOC_ATMEL_SAM0_DFLL48M_MUL \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) + +/** Frequency for GCLK2 */ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ + +/** Dividers and frequency for GCLK3 */ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMD21_SOC_H_ */ diff --git a/soc/atmel/sam0/samd51/CMakeLists.txt b/soc/atmel/sam0/samd51/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samd51/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samd51/Kconfig b/soc/atmel/sam0/samd51/Kconfig new file mode 100644 index 00000000000000..fb846ef9c64c9c --- /dev/null +++ b/soc/atmel/sam0/samd51/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAMD51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD51 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samd51/Kconfig.defconfig b/soc/atmel/sam0/samd51/Kconfig.defconfig new file mode 100644 index 00000000000000..c37eb407f4d832 --- /dev/null +++ b/soc/atmel/sam0/samd51/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Atmel SAMD51 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMD51 + +config NUM_IRQS + int + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAMD51 diff --git a/soc/atmel/sam0/samd51/Kconfig.soc b/soc/atmel/sam0/samd51/Kconfig.soc new file mode 100644 index 00000000000000..efb67a92851941 --- /dev/null +++ b/soc/atmel/sam0/samd51/Kconfig.soc @@ -0,0 +1,62 @@ +# Atmel SAMD51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMD51 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMD51 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "samd51" if SOC_SERIES_SAMD51 + +config SOC_SAMD51G18A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51G19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51J18A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51J19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51J20A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51N19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51N20A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51P19A + bool + select SOC_SERIES_SAMD51 + +config SOC_SAMD51P20A + bool + select SOC_SERIES_SAMD51 + +config SOC + string + default "samd51g18a" if SOC_SAMD51G18A + default "samd51g19a" if SOC_SAMD51G19A + default "samd51j18a" if SOC_SAMD51J18A + default "samd51j19a" if SOC_SAMD51J19A + default "samd51j20a" if SOC_SAMD51J20A + default "samd51n19a" if SOC_SAMD51N19A + default "samd51n20a" if SOC_SAMD51N20A + default "samd51p19a" if SOC_SAMD51P19A + default "samd51p20a" if SOC_SAMD51P20A diff --git a/soc/atmel/sam0/samd51/soc.h b/soc/atmel/sam0/samd51/soc.h new file mode 100644 index 00000000000000..1ca64486f44933 --- /dev/null +++ b/soc/atmel/sam0/samd51/soc.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMD51_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMD51_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMD51G18A) +#include +#elif defined(CONFIG_SOC_SAMD51G19A) +#include +#elif defined(CONFIG_SOC_SAMD51J18A) +#include +#elif defined(CONFIG_SOC_SAMD51J19A) +#include +#elif defined(CONFIG_SOC_SAMD51J20A) +#include +#elif defined(CONFIG_SOC_SAMD51N19A) +#include +#elif defined(CONFIG_SOC_SAMD51N20A) +#include +#elif defined(CONFIG_SOC_SAMD51P19A) +#include +#elif defined(CONFIG_SOC_SAMD51P20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAMD51_SOC_H_ */ diff --git a/soc/atmel/sam0/same51/CMakeLists.txt b/soc/atmel/sam0/same51/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/same51/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/same51/Kconfig b/soc/atmel/sam0/same51/Kconfig new file mode 100644 index 00000000000000..35aa9996a7b275 --- /dev/null +++ b/soc/atmel/sam0/same51/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAME51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME51 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/same51/Kconfig.defconfig b/soc/atmel/sam0/same51/Kconfig.defconfig new file mode 100644 index 00000000000000..302b528ab4fb5a --- /dev/null +++ b/soc/atmel/sam0/same51/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Atmel SAME51 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME51 + +config NUM_IRQS + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAME51 diff --git a/soc/atmel/sam0/same51/Kconfig.soc b/soc/atmel/sam0/same51/Kconfig.soc new file mode 100644 index 00000000000000..4d858515f3646b --- /dev/null +++ b/soc/atmel/sam0/same51/Kconfig.soc @@ -0,0 +1,41 @@ +# Atmel SAME51 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME51 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAME51 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "same51" if SOC_SERIES_SAME51 + +config SOC_SAME51J18A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51J19A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51J20A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51N19A + bool + select SOC_SERIES_SAME51 + +config SOC_SAME51N20A + bool + select SOC_SERIES_SAME51 + +config SOC + default "same51j18a" if SOC_SAME51J18A + default "same51j19a" if SOC_SAME51J19A + default "same51j20a" if SOC_SAME51J20A + default "same51n19a" if SOC_SAME51N19A + default "same51n20a" if SOC_SAME51N20A diff --git a/soc/atmel/sam0/same51/soc.h b/soc/atmel/sam0/same51/soc.h new file mode 100644 index 00000000000000..8c55ceda812188 --- /dev/null +++ b/soc/atmel/sam0/same51/soc.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAME51_SOC_H_ +#define _SOC_ATMEL_SAM0_SAME51_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + + +#if defined(CONFIG_SOC_SAME51J18A) +#include +#elif defined(CONFIG_SOC_SAME51J19A) +#include +#elif defined(CONFIG_SOC_SAME51J20A) +#include +#elif defined(CONFIG_SOC_SAME51N19A) +#include +#elif defined(CONFIG_SOC_SAME51N20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAME51_SOC_H_ */ diff --git a/soc/atmel/sam0/same53/CMakeLists.txt b/soc/atmel/sam0/same53/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/same53/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/same53/Kconfig b/soc/atmel/sam0/same53/Kconfig new file mode 100644 index 00000000000000..670f155e926936 --- /dev/null +++ b/soc/atmel/sam0/same53/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAME53 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME53 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/same53/Kconfig.defconfig b/soc/atmel/sam0/same53/Kconfig.defconfig new file mode 100644 index 00000000000000..80f00943b5b008 --- /dev/null +++ b/soc/atmel/sam0/same53/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Atmel SAME53 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME53 + +config NUM_IRQS + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAME53 diff --git a/soc/atmel/sam0/same53/Kconfig.soc b/soc/atmel/sam0/same53/Kconfig.soc new file mode 100644 index 00000000000000..f52e7ced3aeb57 --- /dev/null +++ b/soc/atmel/sam0/same53/Kconfig.soc @@ -0,0 +1,41 @@ +# Atmel SAME53 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME53 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAME53 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "same53" if SOC_SERIES_SAME53 + +config SOC_SAME53J18A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53J19A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53J20A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53N19A + bool + select SOC_SERIES_SAME53 + +config SOC_SAME53N20A + bool + select SOC_SERIES_SAME53 + +config SOC + default "same53j18a" if SOC_SAME53J18A + default "same53j19a" if SOC_SAME53J19A + default "same53j20a" if SOC_SAME53J20A + default "same53n19a" if SOC_SAME53N19A + default "same53n20a" if SOC_SAME53N20A diff --git a/soc/atmel/sam0/same53/soc.h b/soc/atmel/sam0/same53/soc.h new file mode 100644 index 00000000000000..de08740a9a0ade --- /dev/null +++ b/soc/atmel/sam0/same53/soc.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAME53_SOC_H_ +#define _SOC_ATMEL_SAM0_SAME53_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAME53J18A) +#include +#elif defined(CONFIG_SOC_SAME53J19A) +#include +#elif defined(CONFIG_SOC_SAME53J20A) +#include +#elif defined(CONFIG_SOC_SAME53N19A) +#include +#elif defined(CONFIG_SOC_SAME53N20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "gmac_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAME53_SOC_H_ */ diff --git a/soc/atmel/sam0/same54/CMakeLists.txt b/soc/atmel/sam0/same54/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/same54/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/same54/Kconfig b/soc/atmel/sam0/same54/Kconfig new file mode 100644 index 00000000000000..2bd2359eb2e0fa --- /dev/null +++ b/soc/atmel/sam0/same54/Kconfig @@ -0,0 +1,13 @@ +# Atmel SAME54 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME54 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/same54/Kconfig.defconfig b/soc/atmel/sam0/same54/Kconfig.defconfig new file mode 100644 index 00000000000000..53555ebce1d959 --- /dev/null +++ b/soc/atmel/sam0/same54/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Atmel SAME54 MCU series configuration options + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAME54 + +config NUM_IRQS + default 137 + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_SAME54 diff --git a/soc/atmel/sam0/same54/Kconfig.soc b/soc/atmel/sam0/same54/Kconfig.soc new file mode 100644 index 00000000000000..1c7621764fa13e --- /dev/null +++ b/soc/atmel/sam0/same54/Kconfig.soc @@ -0,0 +1,36 @@ +# Atmel SAME54 MCU series + +# Copyright (c) 2019 ML!PA Consulting GmbH +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAME54 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAME54 Cortex-M4F microcontrollers. + +config SOC_SERIES + default "same54" if SOC_SERIES_SAME54 + +config SOC_SAME54N19A + bool + select SOC_SERIES_SAME54 + +config SOC_SAME54N20A + bool + select SOC_SERIES_SAME54 + +config SOC_SAME54P19A + bool + select SOC_SERIES_SAME54 + +config SOC_SAME54P20A + bool + select SOC_SERIES_SAME54 + +config SOC + default "same54n19a" if SOC_SAME54N19A + default "same54n20a" if SOC_SAME54N20A + default "same54p19a" if SOC_SAME54P19A + default "same54p20a" if SOC_SAME54P20A diff --git a/soc/atmel/sam0/same54/soc.h b/soc/atmel/sam0/same54/soc.h new file mode 100644 index 00000000000000..b47f5278c099bd --- /dev/null +++ b/soc/atmel/sam0/same54/soc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2019 ML!PA Consulting GmbH + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAME54_SOC_H_ +#define _SOC_ATMEL_SAM0_SAME54_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAME54N19A) +#include +#elif defined(CONFIG_SOC_SAME54N20A) +#include +#elif defined(CONFIG_SOC_SAME54P19A) +#include +#elif defined(CONFIG_SOC_SAME54P20A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "sercom_fixup_samd5x.h" +#include "tc_fixup_samd5x.h" +#include "gmac_fixup_samd5x.h" +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_DFLL48_FREQ_HZ 48000000 + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ 48000000 + +#endif /* _SOC_ATMEL_SAM0_SAME54_SOC_H_ */ diff --git a/soc/atmel/sam0/saml21/CMakeLists.txt b/soc/atmel/sam0/saml21/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/saml21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/saml21/Kconfig b/soc/atmel/sam0/saml21/Kconfig new file mode 100644 index 00000000000000..1fbc5336a570dd --- /dev/null +++ b/soc/atmel/sam0/saml21/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAML21 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAML21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/saml21/Kconfig.defconfig b/soc/atmel/sam0/saml21/Kconfig.defconfig new file mode 100644 index 00000000000000..19ecbdf5cad7cf --- /dev/null +++ b/soc/atmel/sam0/saml21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAML21 MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAML21 + +config NUM_IRQS + default 29 + +endif # SOC_SERIES_SAML21 diff --git a/soc/atmel/sam0/saml21/Kconfig.soc b/soc/atmel/sam0/saml21/Kconfig.soc new file mode 100644 index 00000000000000..c833a172766300 --- /dev/null +++ b/soc/atmel/sam0/saml21/Kconfig.soc @@ -0,0 +1,76 @@ +# Atmel SAML21 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAML21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAML21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "saml21" if SOC_SERIES_SAML21 + +config SOC_SAML21E15B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21E16B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21E17B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21E18B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21G16B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21G17B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21G18B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J16B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J17B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J18B + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J17BU + bool + select SOC_SERIES_SAML21 + +config SOC_SAML21J18BU + bool + select SOC_SERIES_SAML21 + +config SOC + default "saml21e15b" if SOC_SAML21E15B + default "saml21e16b" if SOC_SAML21E16B + default "saml21e17b" if SOC_SAML21E17B + default "saml21e18b" if SOC_SAML21E18B + default "saml21g16b" if SOC_SAML21G16B + default "saml21g17b" if SOC_SAML21G17B + default "saml21g18b" if SOC_SAML21G18B + default "saml21j16b" if SOC_SAML21J16B + default "saml21j17b" if SOC_SAML21J17B + default "saml21j18b" if SOC_SAML21J18B + default "saml21j17bu" if SOC_SAML21J17BU + default "saml21j18bu" if SOC_SAML21J18BU diff --git a/soc/atmel/sam0/saml21/soc.h b/soc/atmel/sam0/saml21/soc.h new file mode 100644 index 00000000000000..40c9444d96cd99 --- /dev/null +++ b/soc/atmel/sam0/saml21/soc.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAML21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAML21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#if defined(CONFIG_SOC_SAML21E15B) +#include +#elif defined(CONFIG_SOC_SAML21E16B) +#include +#elif defined(CONFIG_SOC_SAML21E17B) +#include +#elif defined(CONFIG_SOC_SAML21E18B) +#include +#elif defined(CONFIG_SOC_SAML21G16B) +#include +#elif defined(CONFIG_SOC_SAML21G17B) +#include +#elif defined(CONFIG_SOC_SAML21G18B) +#include +#elif defined(CONFIG_SOC_SAML21J16B) +#include +#elif defined(CONFIG_SOC_SAML21J17B) +#include +#elif defined(CONFIG_SOC_SAML21J18B) +#include +#elif defined(CONFIG_SOC_SAML21J17BU) +#include +#elif defined(CONFIG_SOC_SAML21J18BU) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAML21_SOC_H_ */ diff --git a/soc/atmel/sam0/samr21/CMakeLists.txt b/soc/atmel/sam0/samr21/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samr21/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samr21/Kconfig b/soc/atmel/sam0/samr21/Kconfig new file mode 100644 index 00000000000000..823be5d13ea46b --- /dev/null +++ b/soc/atmel/sam0/samr21/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMR21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR21 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samr21/Kconfig.defconfig b/soc/atmel/sam0/samr21/Kconfig.defconfig new file mode 100644 index 00000000000000..cc93f0a38185c9 --- /dev/null +++ b/soc/atmel/sam0/samr21/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMR21 MCU series configuration options + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR21 + +config NUM_IRQS + default 28 + +endif # SOC_SERIES_SAMR21 diff --git a/soc/atmel/sam0/samr21/Kconfig.soc b/soc/atmel/sam0/samr21/Kconfig.soc new file mode 100644 index 00000000000000..e0e08cb05a0602 --- /dev/null +++ b/soc/atmel/sam0/samr21/Kconfig.soc @@ -0,0 +1,51 @@ +# Atmel SAMR21 MCU series + +# Copyright (c) 2017 Google LLC. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR21 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samr21" if SOC_SERIES_SAMR21 + +config SOC_SAMR21E16A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21E17A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21E18A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21E19A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21G16A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21G17A + bool + select SOC_SERIES_SAMR21 + +config SOC_SAMR21G18A + bool + select SOC_SERIES_SAMR21 + +config SOC + default "samr21e16a" if SOC_SAMR21E16A + default "samr21e17a" if SOC_SAMR21E17A + default "samr21e18a" if SOC_SAMR21E18A + default "samr21e19a" if SOC_SAMR21E19A + default "samr21g16a" if SOC_SAMR21G16A + default "samr21g17a" if SOC_SAMR21G17A + default "samr21g18a" if SOC_SAMR21G18A diff --git a/soc/atmel/sam0/samr21/soc.h b/soc/atmel/sam0/samr21/soc.h new file mode 100644 index 00000000000000..c3dad347372b49 --- /dev/null +++ b/soc/atmel/sam0/samr21/soc.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2017 Google LLC. + * Copyright (c) 2023 Ionut Catalin Pavel + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMR21_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMR21_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMR21E16A) +#include +#elif defined(CONFIG_SOC_SAMR21E17A) +#include +#elif defined(CONFIG_SOC_SAMR21E18A) +#include +#elif defined(CONFIG_SOC_SAMR21E19A) +#include +#elif defined(CONFIG_SOC_SAMR21G16A) +#include +#elif defined(CONFIG_SOC_SAMR21G17A) +#include +#elif defined(CONFIG_SOC_SAMR21G18A) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ + +/** Known values */ +#define SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ 48000000 +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000 +#define SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ 31250 + +/** GCLK1 source frequency selector */ +#if defined(CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ CONFIG_SOC_ATMEL_SAMD_XOSC_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +/** Dividers and frequency for GCLK0 */ +#define SOC_ATMEL_SAM0_GCLK0_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_MAX_FREQ_HZ / SOC_ATMEL_SAM0_MCK_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +/** DFLL48M output frequency */ +#define SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ \ + (SOC_ATMEL_SAM0_MCK_FREQ_HZ * SOC_ATMEL_SAM0_GCLK0_DIV) + +/** Dividers and frequency for GCLK1 */ +#define SOC_ATMEL_SAM0_GCLK1_DIV \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_TARGET_FREQ_HZ) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ \ + (SOC_ATMEL_SAM0_GCLK1_SRC_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_DIV) + +/** DFLL48M output multiplier */ +#define SOC_ATMEL_SAM0_DFLL48M_MUL \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK1_FREQ_HZ) + +/** Frequency for GCLK2 */ +#define SOC_ATMEL_SAM0_GCLK2_FREQ_HZ SOC_ATMEL_SAM0_OSCULP32K_FREQ_HZ + +/** Dividers and frequency for GCLK3 */ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_DIV \ + (SOC_ATMEL_SAM0_DFLL48M_FREQ_HZ / SOC_ATMEL_SAM0_GCLK3_FREQ_HZ) + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMR21_SOC_H_ */ diff --git a/soc/atmel/sam0/samr34/CMakeLists.txt b/soc/atmel/sam0/samr34/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samr34/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samr34/Kconfig b/soc/atmel/sam0/samr34/Kconfig new file mode 100644 index 00000000000000..05675901e4f65f --- /dev/null +++ b/soc/atmel/sam0/samr34/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMR34 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR34 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samr34/Kconfig.defconfig b/soc/atmel/sam0/samr34/Kconfig.defconfig new file mode 100644 index 00000000000000..b7ea78a2c2e709 --- /dev/null +++ b/soc/atmel/sam0/samr34/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAML MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR34 + +config NUM_IRQS + default 23 + +endif # SOC_SERIES_SAMR34 diff --git a/soc/atmel/sam0/samr34/Kconfig.soc b/soc/atmel/sam0/samr34/Kconfig.soc new file mode 100644 index 00000000000000..23ddaa16b67cab --- /dev/null +++ b/soc/atmel/sam0/samr34/Kconfig.soc @@ -0,0 +1,31 @@ +# Atmel SAMR34 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR34 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samr34" if SOC_SERIES_SAMR34 + +config SOC_SAMR34J16B + bool + select SOC_SERIES_SAMR34 + +config SOC_SAMR34J17B + bool + select SOC_SERIES_SAMR34 + +config SOC_SAMR34J18B + bool + select SOC_SERIES_SAMR34 + +config SOC + default "samr34j16b" if SOC_SAMR34J16B + default "samr34j17b" if SOC_SAMR34J17B + default "samr34j18b" if SOC_SAMR34J18B diff --git a/soc/atmel/sam0/samr34/soc.h b/soc/atmel/sam0/samr34/soc.h new file mode 100644 index 00000000000000..06699440d74b9c --- /dev/null +++ b/soc/atmel/sam0/samr34/soc.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMR34_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMR34_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMR34J16B) +#include +#elif defined(CONFIG_SOC_SAMR34J17B) +#include +#elif defined(CONFIG_SOC_SAMR34J18B) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMR34_SOC_H_ */ diff --git a/soc/atmel/sam0/samr35/CMakeLists.txt b/soc/atmel/sam0/samr35/CMakeLists.txt new file mode 100644 index 00000000000000..c7c4bb53ac1464 --- /dev/null +++ b/soc/atmel/sam0/samr35/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) diff --git a/soc/atmel/sam0/samr35/Kconfig b/soc/atmel/sam0/samr35/Kconfig new file mode 100644 index 00000000000000..c5fa8e5d0481cd --- /dev/null +++ b/soc/atmel/sam0/samr35/Kconfig @@ -0,0 +1,12 @@ +# Atmel SAMR35 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2023-2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR35 + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT diff --git a/soc/atmel/sam0/samr35/Kconfig.defconfig b/soc/atmel/sam0/samr35/Kconfig.defconfig new file mode 100644 index 00000000000000..26ac6d74ff4df4 --- /dev/null +++ b/soc/atmel/sam0/samr35/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Atmel SAMR35 MCU series configuration options + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SAMR35 + +config NUM_IRQS + default 23 + +endif # SOC_SERIES_SAMR35 diff --git a/soc/atmel/sam0/samr35/Kconfig.soc b/soc/atmel/sam0/samr35/Kconfig.soc new file mode 100644 index 00000000000000..13042dfeda6530 --- /dev/null +++ b/soc/atmel/sam0/samr35/Kconfig.soc @@ -0,0 +1,31 @@ +# Atmel SAMR35 MCU series + +# Copyright (c) 2021 Argentum Systems Ltd. +# Copyright (c) 2024 Gerson Fernando Budke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SAMR35 + bool + select SOC_FAMILY_ATMEL_SAM0 + help + Enable support for Atmel SAMR35 Cortex-M0+ microcontrollers. + +config SOC_SERIES + default "samr35" if SOC_SERIES_SAMR35 + +config SOC_SAMR35J16B + bool + select SOC_SERIES_SAMR35 + +config SOC_SAMR35J17B + bool + select SOC_SERIES_SAMR35 + +config SOC_SAMR35J18B + bool + select SOC_SERIES_SAMR35 + +config SOC + default "samr35j16b" if SOC_SAMR35J16B + default "samr35j17b" if SOC_SAMR35J17B + default "samr35j18b" if SOC_SAMR35J18B diff --git a/soc/atmel/sam0/samr35/soc.h b/soc/atmel/sam0/samr35/soc.h new file mode 100644 index 00000000000000..24d2a4d1591ef8 --- /dev/null +++ b/soc/atmel/sam0/samr35/soc.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2021 Argentum Systems Ltd. + * Copyright (c) 2024 Gerson Fernando Budke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC_ATMEL_SAM0_SAMR35_SOC_H_ +#define _SOC_ATMEL_SAM0_SAMR35_SOC_H_ + +#ifndef _ASMLANGUAGE + +#define DONT_USE_CMSIS_INIT + +#include + +#if defined(CONFIG_SOC_SAMR35J16B) +#include +#elif defined(CONFIG_SOC_SAMR35J17B) +#include +#elif defined(CONFIG_SOC_SAMR35J18B) +#include +#else +#error Library does not support the specified device. +#endif + +#endif /* _ASMLANGUAGE */ + +#define ADC_SAM0_REFERENCE_ENABLE_PROTECTED + +#include "adc_fixup_sam0.h" +#include "../common/soc_port.h" +#include "../common/atmel_sam0_dt.h" + +/** Processor Clock (HCLK) Frequency */ +#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ + +/** Master Clock (MCK) Frequency */ +#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ +#define SOC_ATMEL_SAM0_OSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768 +#define SOC_ATMEL_SAM0_OSC16M_FREQ_HZ 16000000 +#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ 24000000 + +#if defined(CONFIG_SOC_ATMEL_SAML_OPENLOOP_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ 0 +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_XOSC32K_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ +#elif defined(CONFIG_SOC_ATMEL_SAML_OSC16M_AS_MAIN) +#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC16M_FREQ_HZ +#else +#error Unsupported GCLK1 clock source. +#endif + +#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ +#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ + +#endif /* _SOC_ATMEL_SAM0_SAMR35_SOC_H_ */ diff --git a/soc/atmel/sam0/soc.yml b/soc/atmel/sam0/soc.yml new file mode 100644 index 00000000000000..d0cfa94f7ca1ea --- /dev/null +++ b/soc/atmel/sam0/soc.yml @@ -0,0 +1,138 @@ +family: +- name: atmel_sam0 + series: + - name: samc20 + socs: + - name: samc20e15a + - name: samc20e16a + - name: samc20e17a + - name: samc20e18a + - name: samc20g15a + - name: samc20g16a + - name: samc20g17a + - name: samc20g18a + - name: samc20j15a + - name: samc20j16a + - name: samc20j17a + - name: samc20j18a + - name: samc20j17au + - name: samc20j18au + - name: samc20n17a + - name: samc20n18a + - name: samc21 + socs: + - name: samc21e15a + - name: samc21e16a + - name: samc21e17a + - name: samc21e18a + - name: samc21g15a + - name: samc21g16a + - name: samc21g17a + - name: samc21g18a + - name: samc21j15a + - name: samc21j16a + - name: samc21j17a + - name: samc21j18a + - name: samc21j17au + - name: samc21j18au + - name: samc21n17a + - name: samc21n18a + - name: samd20 + socs: + - name: samd20e14 + - name: samd20e15 + - name: samd20e16 + - name: samd20e17 + - name: samd20e18 + - name: samd20g14 + - name: samd20g15 + - name: samd20g16 + - name: samd20g17 + - name: samd20g18 + - name: samd20g17u + - name: samd20g18u + - name: samd20j14 + - name: samd20j15 + - name: samd20j16 + - name: samd20j17 + - name: samd20j18 + - name: samd21 + socs: + - name: samd21e15a + - name: samd21e16a + - name: samd21e17a + - name: samd21e18a + - name: samd21g15a + - name: samd21g16a + - name: samd21g17a + - name: samd21g18a + - name: samd21g17au + - name: samd21g18au + - name: samd21j15a + - name: samd21j16a + - name: samd21j17a + - name: samd21j18a + - name: samd51 + socs: + - name: samd51g18a + - name: samd51g19a + - name: samd51j18a + - name: samd51j19a + - name: samd51j20a + - name: samd51n19a + - name: samd51n20a + - name: samd51p19a + - name: samd51p20a + - name: same51 + socs: + - name: same51j18a + - name: same51j19a + - name: same51j20a + - name: same51n19a + - name: same51n20a + - name: same53 + socs: + - name: same53j18a + - name: same53j19a + - name: same53j20a + - name: same53n19a + - name: same53n20a + - name: same54 + socs: + - name: same54n19a + - name: same54n20a + - name: same54p19a + - name: same54p20a + - name: saml21 + socs: + - name: saml21e15b + - name: saml21e16b + - name: saml21e17b + - name: saml21e18b + - name: saml21g16b + - name: saml21g17b + - name: saml21g18b + - name: saml21j16b + - name: saml21j17b + - name: saml21j18b + - name: saml21j17bu + - name: saml21j18bu + - name: samr21 + socs: + - name: samr21e16a + - name: samr21e17a + - name: samr21e18a + - name: samr21e19a + - name: samr21g16a + - name: samr21g17a + - name: samr21g18a + - name: samr34 + socs: + - name: samr34j16b + - name: samr34j17b + - name: samr34j18b + - name: samr35 + socs: + - name: samr35j16b + - name: samr35j17b + - name: samr35j18b diff --git a/soc/arm64/bcm2711/CMakeLists.txt b/soc/brcm/bcm2711/CMakeLists.txt similarity index 100% rename from soc/arm64/bcm2711/CMakeLists.txt rename to soc/brcm/bcm2711/CMakeLists.txt diff --git a/soc/brcm/bcm2711/Kconfig b/soc/brcm/bcm2711/Kconfig new file mode 100644 index 00000000000000..2cfb4b2e4e41d9 --- /dev/null +++ b/soc/brcm/bcm2711/Kconfig @@ -0,0 +1,7 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM2711 + select ARM64 + select CPU_CORTEX_A72 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/brcm/bcm2711/Kconfig.defconfig b/soc/brcm/bcm2711/Kconfig.defconfig new file mode 100644 index 00000000000000..21776e5ef160d5 --- /dev/null +++ b/soc/brcm/bcm2711/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +if SOC_BCM2711 + +config NUM_IRQS + int + default 260 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 54000000 + +endif diff --git a/soc/brcm/bcm2711/Kconfig.soc b/soc/brcm/bcm2711/Kconfig.soc new file mode 100644 index 00000000000000..d3c79214257e9b --- /dev/null +++ b/soc/brcm/bcm2711/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright 2023 honglin leng +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM2711 + bool + +config SOC + default "bcm2711" if SOC_BCM2711 diff --git a/soc/arm64/bcm2711/mmu_regions.c b/soc/brcm/bcm2711/mmu_regions.c similarity index 100% rename from soc/arm64/bcm2711/mmu_regions.c rename to soc/brcm/bcm2711/mmu_regions.c diff --git a/soc/brcm/bcm2711/soc.yml b/soc/brcm/bcm2711/soc.yml new file mode 100644 index 00000000000000..ebe1b40e7a0057 --- /dev/null +++ b/soc/brcm/bcm2711/soc.yml @@ -0,0 +1,4 @@ +series: +- name: bcm2711 + socs: + - name: bcm2711 diff --git a/soc/arm/arm/CMakeLists.txt b/soc/brcm/bcmvk/CMakeLists.txt similarity index 100% rename from soc/arm/arm/CMakeLists.txt rename to soc/brcm/bcmvk/CMakeLists.txt diff --git a/soc/brcm/bcmvk/Kconfig b/soc/brcm/bcmvk/Kconfig new file mode 100644 index 00000000000000..c51095bb23f5ed --- /dev/null +++ b/soc/brcm/bcmvk/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +if SOC_FAMILY_BCMVK + +rsource "*/Kconfig" + +endif diff --git a/soc/brcm/bcmvk/Kconfig.defconfig b/soc/brcm/bcmvk/Kconfig.defconfig new file mode 100644 index 00000000000000..ddbe24a6428659 --- /dev/null +++ b/soc/brcm/bcmvk/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +if SOC_FAMILY_BCMVK + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_BCMVK diff --git a/soc/brcm/bcmvk/Kconfig.soc b/soc/brcm/bcmvk/Kconfig.soc new file mode 100644 index 00000000000000..28e14f0e13d77f --- /dev/null +++ b/soc/brcm/bcmvk/Kconfig.soc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config SOC_FAMILY_BCMVK + bool + +config SOC_FAMILY + default "bcmvk" if SOC_FAMILY_BCMVK + +rsource "*/Kconfig.soc" diff --git a/soc/brcm/bcmvk/soc.yml b/soc/brcm/bcmvk/soc.yml new file mode 100644 index 00000000000000..2b0b7d27a37809 --- /dev/null +++ b/soc/brcm/bcmvk/soc.yml @@ -0,0 +1,12 @@ +family: + - name: bcmvk + series: + - name: valkyrie + socs: + - name: bcm58400 + - name: viper + socs: + - name: bcm58402 + cpuclusters: + - name: m7 + - name: a72 diff --git a/soc/brcm/bcmvk/valkyrie/CMakeLists.txt b/soc/brcm/bcmvk/valkyrie/CMakeLists.txt new file mode 100644 index 00000000000000..f5ca7d6435ecf2 --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/brcm/bcmvk/valkyrie/Kconfig b/soc/brcm/bcmvk/valkyrie/Kconfig new file mode 100644 index 00000000000000..9ce1feb9faa7dc --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/Kconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config SOC_SERIES_VALKYRIE + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_HAS_ARM_MPU diff --git a/soc/brcm/bcmvk/valkyrie/Kconfig.defconfig b/soc/brcm/bcmvk/valkyrie/Kconfig.defconfig new file mode 100644 index 00000000000000..5312999e21431b --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/Kconfig.defconfig @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +if SOC_SERIES_VALKYRIE + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 500000000 + +endif # SOC_SERIES_VALKYRIE diff --git a/soc/brcm/bcmvk/valkyrie/Kconfig.soc b/soc/brcm/bcmvk/valkyrie/Kconfig.soc new file mode 100644 index 00000000000000..79bcd0e755cc7b --- /dev/null +++ b/soc/brcm/bcmvk/valkyrie/Kconfig.soc @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright 2020 Broadcom. +# + +config SOC_SERIES_VALKYRIE + bool + select SOC_FAMILY_BCMVK + help + Enable support for Broadcom Valkyrie Series + +config SOC_BCM58400 + bool + select SOC_SERIES_VALKYRIE + help + Broadcom BCM58400 + +config SOC_SERIES + default "valkyrie" if SOC_SERIES_VALKYRIE + +config SOC + default "bcm58400" if SOC_BCM58400 diff --git a/soc/arm/bcm_vk/valkyrie/soc.h b/soc/brcm/bcmvk/valkyrie/soc.h similarity index 100% rename from soc/arm/bcm_vk/valkyrie/soc.h rename to soc/brcm/bcmvk/valkyrie/soc.h diff --git a/soc/brcm/bcmvk/viper/CMakeLists.txt b/soc/brcm/bcmvk/viper/CMakeLists.txt new file mode 100644 index 00000000000000..1a24bb86500ed7 --- /dev/null +++ b/soc/brcm/bcmvk/viper/CMakeLists.txt @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_BCM58402_A72) + zephyr_include_directories(a72) + + zephyr_sources( + a72/soc.c + a72/plat_core.c + ) + + zephyr_sources_ifdef(CONFIG_ARM_MMU a72/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_BCM58402_M7) + zephyr_include_directories(m7) + zephyr_sources(m7/soc.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/brcm/bcmvk/viper/Kconfig b/soc/brcm/bcmvk/viper/Kconfig new file mode 100644 index 00000000000000..e6266d10456485 --- /dev/null +++ b/soc/brcm/bcmvk/viper/Kconfig @@ -0,0 +1,13 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +config SOC_BCM58402_M7 + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_HAS_ARM_MPU + +config SOC_BCM58402_A72 + select ARM64 + select CPU_CORTEX_A72 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/brcm/bcmvk/viper/Kconfig.defconfig b/soc/brcm/bcmvk/viper/Kconfig.defconfig new file mode 100644 index 00000000000000..a0354a2c5913fc --- /dev/null +++ b/soc/brcm/bcmvk/viper/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_VIPER + +rsource "Kconfig.defconfig.viper*" + +endif # SOC_SERIES_VIPER diff --git a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_a72 b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_a72 similarity index 83% rename from soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_a72 rename to soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_a72 index 495490a996b5a7..dba58d12f853b6 100644 --- a/soc/arm64/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_a72 +++ b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_a72 @@ -3,9 +3,6 @@ if SOC_BCM58402_A72 -config SOC - default "bcm58402_a72" - config NUM_IRQS int default 260 diff --git a/soc/arm/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_m7 b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_m7 similarity index 84% rename from soc/arm/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_m7 rename to soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_m7 index 15345da6150aa6..16acf0d29b78d7 100644 --- a/soc/arm/bcm_vk/viper/Kconfig.defconfig.viper_bcm58402_m7 +++ b/soc/brcm/bcmvk/viper/Kconfig.defconfig.viper_bcm58402_m7 @@ -3,9 +3,6 @@ if SOC_BCM58402_M7 -config SOC - default "bcm58402_m7" - config NUM_IRQS int default 240 diff --git a/soc/brcm/bcmvk/viper/Kconfig.soc b/soc/brcm/bcmvk/viper/Kconfig.soc new file mode 100644 index 00000000000000..18af37004606f3 --- /dev/null +++ b/soc/brcm/bcmvk/viper/Kconfig.soc @@ -0,0 +1,26 @@ +# Copyright 2020 Broadcom +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_VIPER + bool + select SOC_FAMILY_BCMVK + help + Enable support for Broadcom Viper Series. + +config SOC_BCM58402_M7 + bool + select SOC_SERIES_VIPER + help + Broadcom BCM58402 M7 + +config SOC_BCM58402_A72 + bool + select SOC_SERIES_VIPER + help + Broadcom BCM58402 A72 + +config SOC_SERIES + default "viper" if SOC_SERIES_VIPER + +config SOC + default "bcm58402" if SOC_BCM58402_M7 || SOC_BCM58402_A72 diff --git a/soc/arm64/bcm_vk/viper/mmu_regions.c b/soc/brcm/bcmvk/viper/a72/mmu_regions.c similarity index 100% rename from soc/arm64/bcm_vk/viper/mmu_regions.c rename to soc/brcm/bcmvk/viper/a72/mmu_regions.c diff --git a/soc/arm64/bcm_vk/viper/plat_core.c b/soc/brcm/bcmvk/viper/a72/plat_core.c similarity index 100% rename from soc/arm64/bcm_vk/viper/plat_core.c rename to soc/brcm/bcmvk/viper/a72/plat_core.c diff --git a/soc/arm64/bcm_vk/viper/soc.c b/soc/brcm/bcmvk/viper/a72/soc.c similarity index 100% rename from soc/arm64/bcm_vk/viper/soc.c rename to soc/brcm/bcmvk/viper/a72/soc.c diff --git a/soc/arm64/bcm_vk/viper/soc.h b/soc/brcm/bcmvk/viper/a72/soc.h similarity index 100% rename from soc/arm64/bcm_vk/viper/soc.h rename to soc/brcm/bcmvk/viper/a72/soc.h diff --git a/soc/arm/bcm_vk/viper/soc.c b/soc/brcm/bcmvk/viper/m7/soc.c similarity index 100% rename from soc/arm/bcm_vk/viper/soc.c rename to soc/brcm/bcmvk/viper/m7/soc.c diff --git a/soc/arm/bcm_vk/viper/soc.h b/soc/brcm/bcmvk/viper/m7/soc.h similarity index 100% rename from soc/arm/bcm_vk/viper/soc.h rename to soc/brcm/bcmvk/viper/m7/soc.h diff --git a/soc/xtensa/dc233c/CMakeLists.txt b/soc/cdns/dc233c/CMakeLists.txt similarity index 100% rename from soc/xtensa/dc233c/CMakeLists.txt rename to soc/cdns/dc233c/CMakeLists.txt diff --git a/soc/cdns/dc233c/Kconfig b/soc/cdns/dc233c/Kconfig new file mode 100644 index 00000000000000..01ffa1c92cabbe --- /dev/null +++ b/soc/cdns/dc233c/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2017, 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_DC233C + select XTENSA + select XTENSA_HAL + select ARCH_HAS_THREAD_LOCAL_STORAGE + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_MMU + select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU + select ARCH_HAS_USERSPACE if XTENSA_MMU + select XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP if XTENSA_MMU diff --git a/soc/cdns/dc233c/Kconfig.defconfig b/soc/cdns/dc233c/Kconfig.defconfig new file mode 100644 index 00000000000000..c872936a0448ab --- /dev/null +++ b/soc/cdns/dc233c/Kconfig.defconfig @@ -0,0 +1,25 @@ +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 Cadence Design Systems, Inc. +# Copyright (c) 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_XTENSA_DC233C + +config XTENSA_MMU_NUM_L2_TABLES + int + default 48 if XTENSA_MMU + +# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB. +# This is to allow VECBASE to be mapped permanently +# via TLB way 4 (which covers 1MB). +config SRAM_OFFSET + hex + default 0x100000 if XTENSA_MMU + default 0x2400 + +config KERNEL_VM_OFFSET + hex + default 0x100000 + +endif diff --git a/soc/cdns/dc233c/Kconfig.soc b/soc/cdns/dc233c/Kconfig.soc new file mode 100644 index 00000000000000..b39e7537b72c00 --- /dev/null +++ b/soc/cdns/dc233c/Kconfig.soc @@ -0,0 +1,13 @@ +# Copyright (c) 2017, 2023 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_DC233C + bool + +config SOC + default "dc233c" if SOC_XTENSA_DC233C + +config SOC_TOOLCHAIN_NAME + string + default "dc233c" if SOC_XTENSA_DC233C diff --git a/soc/xtensa/dc233c/include/_soc_inthandlers.h b/soc/cdns/dc233c/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/dc233c/include/_soc_inthandlers.h rename to soc/cdns/dc233c/include/_soc_inthandlers.h diff --git a/soc/xtensa/dc233c/include/backtrace_helpers.h b/soc/cdns/dc233c/include/backtrace_helpers.h similarity index 100% rename from soc/xtensa/dc233c/include/backtrace_helpers.h rename to soc/cdns/dc233c/include/backtrace_helpers.h diff --git a/soc/xtensa/dc233c/include/xtensa-dc233c.ld b/soc/cdns/dc233c/include/xtensa-dc233c.ld similarity index 100% rename from soc/xtensa/dc233c/include/xtensa-dc233c.ld rename to soc/cdns/dc233c/include/xtensa-dc233c.ld diff --git a/soc/xtensa/dc233c/mmu.c b/soc/cdns/dc233c/mmu.c similarity index 100% rename from soc/xtensa/dc233c/mmu.c rename to soc/cdns/dc233c/mmu.c diff --git a/soc/cdns/dc233c/soc.yml b/soc/cdns/dc233c/soc.yml new file mode 100644 index 00000000000000..ee6c461bc5e1c4 --- /dev/null +++ b/soc/cdns/dc233c/soc.yml @@ -0,0 +1,4 @@ +series: +- name: dc233c + socs: + - name: dc233c diff --git a/soc/xtensa/sample_controller/CMakeLists.txt b/soc/cdns/xtensa_sample_controller/CMakeLists.txt similarity index 100% rename from soc/xtensa/sample_controller/CMakeLists.txt rename to soc/cdns/xtensa_sample_controller/CMakeLists.txt diff --git a/soc/cdns/xtensa_sample_controller/Kconfig b/soc/cdns/xtensa_sample_controller/Kconfig new file mode 100644 index 00000000000000..2e14ded4bc0cf4 --- /dev/null +++ b/soc/cdns/xtensa_sample_controller/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2017 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_SAMPLE_CONTROLLER + select XTENSA + select XTENSA_HAL + select ARCH_SUPPORTS_COREDUMP diff --git a/soc/cdns/xtensa_sample_controller/Kconfig.soc b/soc/cdns/xtensa_sample_controller/Kconfig.soc new file mode 100644 index 00000000000000..e8231c183e8e10 --- /dev/null +++ b/soc/cdns/xtensa_sample_controller/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2017 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XTENSA_SAMPLE_CONTROLLER + bool + +config SOC + default "xtensa_sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER + +config SOC_TOOLCHAIN_NAME + string + default "sample_controller" if SOC_XTENSA_SAMPLE_CONTROLLER diff --git a/soc/xtensa/sample_controller/include/_soc_inthandlers.h b/soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/sample_controller/include/_soc_inthandlers.h rename to soc/cdns/xtensa_sample_controller/include/_soc_inthandlers.h diff --git a/soc/xtensa/sample_controller/include/xtensa-sample-controller.ld b/soc/cdns/xtensa_sample_controller/include/xtensa-sample-controller.ld similarity index 100% rename from soc/xtensa/sample_controller/include/xtensa-sample-controller.ld rename to soc/cdns/xtensa_sample_controller/include/xtensa-sample-controller.ld diff --git a/soc/cdns/xtensa_sample_controller/soc.yml b/soc/cdns/xtensa_sample_controller/soc.yml new file mode 100644 index 00000000000000..52062a2ecfc90e --- /dev/null +++ b/soc/cdns/xtensa_sample_controller/soc.yml @@ -0,0 +1,4 @@ +series: +- name: xtensa_sample_controller + socs: + - name: xtensa_sample_controller diff --git a/soc/common/CMakeLists.txt b/soc/common/CMakeLists.txt index d9abad218cd4f1..8deca3ca0e0862 100644 --- a/soc/common/CMakeLists.txt +++ b/soc/common/CMakeLists.txt @@ -1,4 +1,4 @@ # Copyright (c) 2024 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -add_subdirectory_ifdef(CONFIG_SOC_FAMILY_NRF nordic_nrf) +add_subdirectory_ifdef(CONFIG_RISCV_PRIVILEGED riscv-privileged) diff --git a/soc/common/Kconfig b/soc/common/Kconfig new file mode 100644 index 00000000000000..3f8105b3689906 --- /dev/null +++ b/soc/common/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if RISCV_PRIVILEGED + +rsource "riscv-privileged/Kconfig" + +endif # RISCV_PRIVILEGED diff --git a/soc/common/nordic_nrf/CMakeLists.txt b/soc/common/nordic_nrf/CMakeLists.txt deleted file mode 100644 index 6f397a07fab1b5..00000000000000 --- a/soc/common/nordic_nrf/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) diff --git a/soc/riscv/common/riscv-privileged/CMakeLists.txt b/soc/common/riscv-privileged/CMakeLists.txt similarity index 100% rename from soc/riscv/common/riscv-privileged/CMakeLists.txt rename to soc/common/riscv-privileged/CMakeLists.txt diff --git a/soc/riscv/common/riscv-privileged/Kconfig b/soc/common/riscv-privileged/Kconfig similarity index 100% rename from soc/riscv/common/riscv-privileged/Kconfig rename to soc/common/riscv-privileged/Kconfig diff --git a/soc/riscv/common/riscv-privileged/soc_common_irq.c b/soc/common/riscv-privileged/soc_common_irq.c similarity index 100% rename from soc/riscv/common/riscv-privileged/soc_common_irq.c rename to soc/common/riscv-privileged/soc_common_irq.c diff --git a/soc/riscv/common/riscv-privileged/soc_irq.S b/soc/common/riscv-privileged/soc_irq.S similarity index 100% rename from soc/riscv/common/riscv-privileged/soc_irq.S rename to soc/common/riscv-privileged/soc_irq.S diff --git a/soc/riscv/common/riscv-privileged/vector.S b/soc/common/riscv-privileged/vector.S similarity index 100% rename from soc/riscv/common/riscv-privileged/vector.S rename to soc/common/riscv-privileged/vector.S diff --git a/soc/cypress/CMakeLists.txt b/soc/cypress/CMakeLists.txt new file mode 100644 index 00000000000000..e55e313974031e --- /dev/null +++ b/soc/cypress/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2021, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(psoc6) diff --git a/soc/cypress/Kconfig b/soc/cypress/Kconfig new file mode 100644 index 00000000000000..8c645cb1d7bb67 --- /dev/null +++ b/soc/cypress/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/cypress/Kconfig.defconfig b/soc/cypress/Kconfig.defconfig new file mode 100644 index 00000000000000..1e382579c5f5fc --- /dev/null +++ b/soc/cypress/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_PSOC6 || SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/cypress/Kconfig.soc b/soc/cypress/Kconfig.soc new file mode 100644 index 00000000000000..140274c4e26094 --- /dev/null +++ b/soc/cypress/Kconfig.soc @@ -0,0 +1,17 @@ +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_PSOC6 + bool + +config SOC_FAMILY_INFINEON_CAT1 + bool + +config SOC_FAMILY_INFINEON_CAT1A + bool + +config SOC_FAMILY + default "psoc6" if SOC_FAMILY_PSOC6 + default "infineon_cat1" if SOC_FAMILY_INFINEON_CAT1 + +rsource "*/Kconfig.soc" diff --git a/soc/cypress/psoc6/CMakeLists.txt b/soc/cypress/psoc6/CMakeLists.txt new file mode 100644 index 00000000000000..f7a4bd016ad9b4 --- /dev/null +++ b/soc/cypress/psoc6/CMakeLists.txt @@ -0,0 +1,32 @@ +# +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_SERIES_PSOC62 OR CONFIG_SOC_SERIES_PSOC63) + add_subdirectory(old/common) + zephyr_include_directories(old) + zephyr_sources(old/soc.c) + + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 NOINIT old/noinit.ld) + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6 RWDATA old/rwdata.ld) +else() + zephyr_include_directories(new) + zephyr_include_directories(new/common) + zephyr_sources(new/soc.c) + + # Add sections + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 NOINIT new/noinit.ld) + + # Add section for cm0p image ROM + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A ROM_START SORT_KEY 0x0cm0p new/rom_cm0image.ld) + + # Add section for cm0p image RAM + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAM_SECTIONS SORT_KEY 0 new/ram_cm0image.ld) + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1A RAMFUNC_SECTION SORT_KEY 0 new/ram_func.ld) + zephyr_linker_sources_ifdef(CONFIG_SOC_FAMILY_INFINEON_CAT1 RODATA SORT_KEY 0 new/rom.ld) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/cypress/psoc6/Kconfig b/soc/cypress/psoc6/Kconfig new file mode 100644 index 00000000000000..78c412cc3ef755 --- /dev/null +++ b/soc/cypress/psoc6/Kconfig @@ -0,0 +1,58 @@ +# Cypress Semiconductor PSoC6 series configuration options +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PSOC62_PSOC63 + bool + select ARM + select HAS_CYPRESS_DRIVERS + select CPU_CORTEX_M0PLUS if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_CORTEX_M_HAS_SYSTICK if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_CORTEX_M_HAS_VTOR if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_HAS_ARM_MPU if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + select CPU_CORTEX_M4 if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_CORTEX_M_HAS_DWT if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_CORTEX_M_HAS_SYSTICK if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_HAS_ARM_MPU if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + select CPU_HAS_FPU if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + +config SOC_SERIES_PSOC62 + select SOC_SERIES_PSOC62_PSOC63 + +config SOC_SERIES_PSOC63 + select SOC_SERIES_PSOC62_PSOC63 + +config SOC_PSOC6_M0_ENABLES_M4 + bool "Dual-core support [activate Cortex-M4]" + depends on SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + help + Cortex-M0 CPU should boot Cortex-M4 + +config SOC_DIE_PSOC6 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select DYNAMIC_INTERRUPTS + select CPU_HAS_FPU + +if SOC_FAMILY_INFINEON_CAT1A + +## PSoC™ 6 Cortex M0+ prebuilt images +choice + prompt "PSoC™ 6 Cortex M0+ prebuilt images" + help + Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSoC™ 6 + dual-core MCU. The image is responsible for booting the Cortex-M4 on the device. + +config SOC_PSOC6_CM0P_IMAGE_SLEEP + bool "DeepSleep" + help + DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSoC™ 6 BLE + dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4 + application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4 + linker script. + +endchoice + +endif # SOC_FAMILY_INFINEON_CAT1A diff --git a/soc/cypress/psoc6/Kconfig.defconfig b/soc/cypress/psoc6/Kconfig.defconfig new file mode 100644 index 00000000000000..a5995c61a0c44f --- /dev/null +++ b/soc/cypress/psoc6/Kconfig.defconfig @@ -0,0 +1,30 @@ +# Cypress Semiconductor PSoC6 series configuration options +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_PSOC62 || SOC_SERIES_PSOC63 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 50000000 + +rsource "old/Kconfig.defconfig.psoc*" + +endif # SOC_SERIES_PSOC62 || SOC_SERIES_PSOC63 + +if SOC_FAMILY_INFINEON_CAT1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config SOC_PSOC6_CM0P_IMAGE_ROM_SIZE + hex + default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP + +config SOC_PSOC6_CM0P_IMAGE_RAM_SIZE + hex + default 0x2000 if SOC_PSOC6_CM0P_IMAGE_SLEEP + +rsource "new/Kconfig.defconfig.psoc6*" + +endif # SOC_FAMILY_INFINEON_CAT1 diff --git a/soc/cypress/psoc6/Kconfig.soc b/soc/cypress/psoc6/Kconfig.soc new file mode 100644 index 00000000000000..b644b123a073d4 --- /dev/null +++ b/soc/cypress/psoc6/Kconfig.soc @@ -0,0 +1,1074 @@ +# Cypress Semiconductor PSoC6 series configuration options +# Copyright (c) 2018, Cypress +# Copyright (c) 2020, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_PSOC6 + bool + select SOC_FAMILY_INFINEON_CAT1 + +config SOC_SERIES_PSOC62 + bool + select SOC_FAMILY_PSOC6 + help + Enable support for Cypress PSoC6 MCU series + +config SOC_SERIES_PSOC63 + bool + select SOC_FAMILY_PSOC6 + help + Enable support for Cypress PSoC6-BLE MCU series + +# Cypress PSoC™ 6 MCU lines +config SOC_SERIES_PSOC_60 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 60 MCU series + +config SOC_SERIES_PSOC_61 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 61 MCU series + +config SOC_SERIES_PSOC_62 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 62 MCU series + +config SOC_SERIES_PSOC_63 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 63 MCU series + +config SOC_SERIES_PSOC_64 + bool + select SOC_SERIES_PSOC6 + help + Enable support for Infineon PSoC™ 64 MCU series + +config SOC_CY8C6247_M0 + bool + select SOC_SERIES_PSOC62 + +config SOC_CY8C6247_M4 + bool + select SOC_SERIES_PSOC62 + +config SOC_CY8C6347_M0 + bool + select SOC_SERIES_PSOC63 + +config SOC_CY8C6347_M4 + bool + select SOC_SERIES_PSOC63 + +config SOC_PART_NUMBER_CY8C6247BZI_D54 + bool + depends on SOC_SERIES_PSOC62 + help + CY8C6247BZI_D54 + +config SOC_PART_NUMBER_CY8C6347BZI_BLD53 + bool + depends on SOC_SERIES_PSOC63 + help + CY8C6347BZI_BLD53 + +# Infineon PSoC6 die +config SOC_DIE_PSOC6 + bool + select SOC_FAMILY_INFINEON_CAT1A + +# Infineon PSoC6_01 die +config SOC_DIE_PSOC6_01 + bool + select SOC_DIE_PSOC6 + +# Infineon PSoC6_02 die +config SOC_DIE_PSOC6_02 + bool + select SOC_DIE_PSOC6 + +# Infineon PSoC6_03 die +config SOC_DIE_PSOC6_03 + bool + select SOC_DIE_PSOC6 + +# Infineon PSoC6_04 die +config SOC_DIE_PSOC6_04 + bool + select SOC_DIE_PSOC6 + +# Infineon soc packages +config SOC_PACKAGE_PSOC6_01_124_BGA + bool + +config SOC_PACKAGE_PSOC6_01_116_BGA_BLE + bool + +config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + bool + +config SOC_PACKAGE_PSOC6_01_80_WLCSP + bool + +config SOC_PACKAGE_PSOC6_01_116_BGA_USB + bool + +config SOC_PACKAGE_PSOC6_01_124_BGA_SIP + bool + +config SOC_PACKAGE_PSOC6_01_43_SMT + bool + +config SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + bool + +config SOC_PACKAGE_PSOC6_01_68_QFN_BLE + bool + +config SOC_PACKAGE_PSOC6_02_124_BGA + bool + +config SOC_PACKAGE_PSOC6_02_128_TQFP + bool + +config SOC_PACKAGE_PSOC6_02_100_WLCSP + bool + +config SOC_PACKAGE_PSOC6_02_68_QFN + bool + +config SOC_PACKAGE_PSOC6_03_100_TQFP + bool + +config SOC_PACKAGE_PSOC6_03_68_QFN + bool + +config SOC_PACKAGE_PSOC6_03_49_WLCSP + bool + +config SOC_PACKAGE_PSOC6_04_64_TQFP + bool + +config SOC_PACKAGE_PSOC6_04_68_QFN + bool + +config SOC_PACKAGE_PSOC6_04_80_TQFP + bool + +# Infineon PSoC6_01 series MCUs +config SOC_CY8C6036BZI_F04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_60 + +config SOC_CY8C6016BZI_F04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_60 + +config SOC_CY8C6116BZI_F54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6136BZI_F14 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6136BZI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6137BZI_F14 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6137BZI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6137BZI_F54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6117BZI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6246BZI_D04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_D44 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_D34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336BZI_BLF03 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF03 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6336BZI_BLD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BLD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6137FDI_F02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6117FDI_F02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247FDI_D02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247FDI_D32 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336BZI_BUD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BUD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BUD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BUD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6337BZI_BLF13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6136FDI_F42 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247FDI_D52 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6136FTI_F42 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247FTI_D52 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_80_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6247BZI_AUD54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336BZI_BLF04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF04 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6316BZI_BLF54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6336BZI_BLD14 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD44 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347BZI_BLD54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6247BFI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CYBLE_416045_02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD13 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD43 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347FMI_BUD33 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_104_M_CSP_BLE_USB + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6137WI_F54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6117WI_F34 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6247WI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6336LQI_BLF02 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_68_QFN_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6336LQI_BLF42 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_68_QFN_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CY8C6347LQI_BLD52 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_68_QFN_BLE + select SOC_SERIES_PSOC_63 + +config SOC_CYB06447BZI_BLD54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA_SIP + select SOC_SERIES_PSOC_64 + +config SOC_CYB06447BZI_BLD53 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_116_BGA_BLE + select SOC_SERIES_PSOC_64 + +config SOC_CYB06447BZI_D54 + bool + select SOC_DIE_PSOC6_01 + select SOC_PACKAGE_PSOC6_01_124_BGA + select SOC_SERIES_PSOC_64 + +# Infineon PSoC6_02 series MCUs +config SOC_CYB0644ABZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_64 + +config SOC_CYS0644ABZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_64 + +config SOC_CY8C624ABZI_S2D44A0 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ABZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624AAZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624AFNI_S2D43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ABZI_S2D04 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ABZI_S2D14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624AAZI_S2D14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248AZI_S2D14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248BZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248AZI_S2D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248FNI_S2D43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C614ABZI_S2F04 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AAZI_S2F04 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AFNI_S2F03 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AAZI_S2F14 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614ABZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AAZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614AFNI_S2F43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148BZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148AZI_S2F44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_128_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148FNI_S2F43 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_100_WLCSP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C624ABZI_D44 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_124_BGA + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ALQI_S2D42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C624ALQI_S2D02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248LQI_S2D42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6248LQI_S2D02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C614ALQI_S2F42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C614ALQI_S2F02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148LQI_S2F42 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6148LQI_S2F02 + bool + select SOC_DIE_PSOC6_02 + select SOC_PACKAGE_PSOC6_02_68_QFN + select SOC_SERIES_PSOC_61 + +# Infineon PSoC6_04 series MCUs +config SOC_CY8C6244AZI_S4D92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D93 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D83 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244AZI_S4D12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6244LQI_S4D12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_62 + +config SOC_CY8C6144AZI_S4F92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F92 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F93 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F82 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F83 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_80_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F62 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144AZI_S4F12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_64_TQFP + select SOC_SERIES_PSOC_61 + +config SOC_CY8C6144LQI_S4F12 + bool + select SOC_DIE_PSOC6_04 + select SOC_PACKAGE_PSOC6_04_68_QFN + select SOC_SERIES_PSOC_61 + +config SOC_SERIES + default "psoc62" if SOC_SERIES_PSOC62 + default "psoc63" if SOC_SERIES_PSOC63 + default "psoc6" if SOC_SERIES_PSOC6 + +config SOC + default "cy8c6247" if SOC_CY8C6247_M0 || SOC_CY8C6247_M4 + default "cy8c6347" if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + default "cy8c6036bzi_f04" if SOC_CY8C6036BZI_F04 + default "cy8c6016bzi_f04" if SOC_CY8C6016BZI_F04 + default "cy8c6116bzi_f54" if SOC_CY8C6116BZI_F54 + default "cy8c6136bzi_f14" if SOC_CY8C6136BZI_F14 + default "cy8c6136bzi_f34" if SOC_CY8C6136BZI_F34 + default "cy8c6137bzi_f14" if SOC_CY8C6137BZI_F14 + default "cy8c6137bzi_f34" if SOC_CY8C6137BZI_F34 + default "cy8c6137bzi_f54" if SOC_CY8C6137BZI_F54 + default "cy8c6117bzi_f34" if SOC_CY8C6117BZI_F34 + default "cy8c6246bzi_d04" if SOC_CY8C6246BZI_D04 + default "cy8c6247bzi_d44" if SOC_CY8C6247BZI_D44 + default "cy8c6247bzi_d34" if SOC_CY8C6247BZI_D34 + default "cy8c6247bzi_d54" if SOC_CY8C6247BZI_D54 + default "cy8c6336bzi_blf03" if SOC_CY8C6336BZI_BLF03 + default "cy8c6316bzi_blf03" if SOC_CY8C6316BZI_BLF03 + default "cy8c6316bzi_blf53" if SOC_CY8C6316BZI_BLF53 + default "cy8c6336bzi_bld13" if SOC_CY8C6336BZI_BLD13 + default "cy8c6347bzi_bld43" if SOC_CY8C6347BZI_BLD43 + default "cy8c6347bzi_bld33" if SOC_CY8C6347BZI_BLD33 + default "cy8c6347bzi_bld53" if SOC_CY8C6347BZI_BLD53 + default "cy8c6347fmi_bld13" if SOC_CY8C6347FMI_BLD13 + default "cy8c6347fmi_bld43" if SOC_CY8C6347FMI_BLD43 + default "cy8c6347fmi_bld33" if SOC_CY8C6347FMI_BLD33 + default "cy8c6347fmi_bld53" if SOC_CY8C6347FMI_BLD53 + default "cy8c6137fdi_f02" if SOC_CY8C6137FDI_F02 + default "cy8c6117fdi_f02" if SOC_CY8C6117FDI_F02 + default "cy8c6247fdi_d02" if SOC_CY8C6247FDI_D02 + default "cy8c6247fdi_d32" if SOC_CY8C6247FDI_D32 + default "cy8c6336bzi_bud13" if SOC_CY8C6336BZI_BUD13 + default "cy8c6347bzi_bud43" if SOC_CY8C6347BZI_BUD43 + default "cy8c6347bzi_bud33" if SOC_CY8C6347BZI_BUD33 + default "cy8c6347bzi_bud53" if SOC_CY8C6347BZI_BUD53 + default "cy8c6337bzi_blf13" if SOC_CY8C6337BZI_BLF13 + default "cy8c6136fdi_f42" if SOC_CY8C6136FDI_F42 + default "cy8c6247fdi_d52" if SOC_CY8C6247FDI_D52 + default "cy8c6136fti_f42" if SOC_CY8C6136FTI_F42 + default "cy8c6247fti_d52" if SOC_CY8C6247FTI_D52 + default "cy8c6247bzi_aud54" if SOC_CY8C6247BZI_AUD54 + default "cy8c6336bzi_blf04" if SOC_CY8C6336BZI_BLF04 + default "cy8c6316bzi_blf04" if SOC_CY8C6316BZI_BLF04 + default "cy8c6316bzi_blf54" if SOC_CY8C6316BZI_BLF54 + default "cy8c6336bzi_bld14" if SOC_CY8C6336BZI_BLD14 + default "cy8c6347bzi_bld44" if SOC_CY8C6347BZI_BLD44 + default "cy8c6347bzi_bld34" if SOC_CY8C6347BZI_BLD34 + default "cy8c6347bzi_bld54" if SOC_CY8C6347BZI_BLD54 + default "cy8c6247bfi_d54" if SOC_CY8C6247BFI_D54 + default "cyble_416045_02" if SOC_CYBLE_416045_02 + default "cy8c6347fmi_bud53" if SOC_CY8C6347FMI_BUD53 + default "cy8c6347fmi_bud13" if SOC_CY8C6347FMI_BUD13 + default "cy8c6347fmi_bud43" if SOC_CY8C6347FMI_BUD43 + default "cy8c6347fmi_bud33" if SOC_CY8C6347FMI_BUD33 + default "cy8c6137wi_f54" if SOC_CY8C6137WI_F54 + default "cy8c6117wi_f34" if SOC_CY8C6117WI_F34 + default "cy8c6247wi_d54" if SOC_CY8C6247WI_D54 + default "cy8c6336lqi_blf02" if SOC_CY8C6336LQI_BLF02 + default "cy8c6336lqi_blf42" if SOC_CY8C6336LQI_BLF42 + default "cy8c6347lqi_bld52" if SOC_CY8C6347LQI_BLD52 + default "cyb06447bzi_bld54" if SOC_CYB06447BZI_BLD54 + default "cyb06447bzi_bld53" if SOC_CYB06447BZI_BLD53 + default "cyb06447bzi_d54" if SOC_CYB06447BZI_D54 + default "cyb0644abzi_s2d44" if SOC_CYB0644ABZI_S2D44 + default "cys0644abzi_s2d44" if SOC_CYS0644ABZI_S2D44 + default "cy8c624abzi_s2d44a0" if SOC_CY8C624ABZI_S2D44A0 + default "cy8c624abzi_s2d44" if SOC_CY8C624ABZI_S2D44 + default "cy8c624aazi_s2d44" if SOC_CY8C624AAZI_S2D44 + default "cy8c624afni_s2d43" if SOC_CY8C624AFNI_S2D43 + default "cy8c624abzi_s2d04" if SOC_CY8C624ABZI_S2D04 + default "cy8c624abzi_s2d14" if SOC_CY8C624ABZI_S2D14 + default "cy8c624aazi_s2d14" if SOC_CY8C624AAZI_S2D14 + default "cy8c6248azi_s2d14" if SOC_CY8C6248AZI_S2D14 + default "cy8c6248bzi_s2d44" if SOC_CY8C6248BZI_S2D44 + default "cy8c6248azi_s2d44" if SOC_CY8C6248AZI_S2D44 + default "cy8c6248fni_s2d43" if SOC_CY8C6248FNI_S2D43 + default "cy8c614abzi_s2f04" if SOC_CY8C614ABZI_S2F04 + default "cy8c614aazi_s2f04" if SOC_CY8C614AAZI_S2F04 + default "cy8c614afni_s2f03" if SOC_CY8C614AFNI_S2F03 + default "cy8c614aazi_s2f14" if SOC_CY8C614AAZI_S2F14 + default "cy8c614abzi_s2f44" if SOC_CY8C614ABZI_S2F44 + default "cy8c614aazi_s2f44" if SOC_CY8C614AAZI_S2F44 + default "cy8c614afni_s2f43" if SOC_CY8C614AFNI_S2F43 + default "cy8c6148bzi_s2f44" if SOC_CY8C6148BZI_S2F44 + default "cy8c6148azi_s2f44" if SOC_CY8C6148AZI_S2F44 + default "cy8c6148fni_s2f43" if SOC_CY8C6148FNI_S2F43 + default "cy8c624abzi_d44" if SOC_CY8C624ABZI_D44 + default "cy8c624alqi_s2d42" if SOC_CY8C624ALQI_S2D42 + default "cy8c624alqi_s2d02" if SOC_CY8C624ALQI_S2D02 + default "cy8c6248lqi_s2d42" if SOC_CY8C6248LQI_S2D42 + default "cy8c6248lqi_s2d02" if SOC_CY8C6248LQI_S2D02 + default "cy8c614alqi_s2f42" if SOC_CY8C614ALQI_S2F42 + default "cy8c614alqi_s2f02" if SOC_CY8C614ALQI_S2F02 + default "cy8c6148lqi_s2f42" if SOC_CY8C6148LQI_S2F42 + default "cy8c6148lqi_s2f02" if SOC_CY8C6148LQI_S2F02 + default "cy8c6244azi_s4d92" if SOC_CY8C6244AZI_S4D92 + default "cy8c6244lqi_s4d92" if SOC_CY8C6244LQI_S4D92 + default "cy8c6244azi_s4d93" if SOC_CY8C6244AZI_S4D93 + default "cy8c6244azi_s4d82" if SOC_CY8C6244AZI_S4D82 + default "cy8c6244lqi_s4d82" if SOC_CY8C6244LQI_S4D82 + default "cy8c6244azi_s4d83" if SOC_CY8C6244AZI_S4D83 + default "cy8c6244azi_s4d62" if SOC_CY8C6244AZI_S4D62 + default "cy8c6244lqi_s4d62" if SOC_CY8C6244LQI_S4D62 + default "cy8c6244azi_s4d12" if SOC_CY8C6244AZI_S4D12 + default "cy8c6244lqi_s4d12" if SOC_CY8C6244LQI_S4D12 + default "cy8c6144azi_s4f92" if SOC_CY8C6144AZI_S4F92 + default "cy8c6144lqi_s4f92" if SOC_CY8C6144LQI_S4F92 + default "cy8c6144azi_s4f93" if SOC_CY8C6144AZI_S4F93 + default "cy8c6144azi_s4f82" if SOC_CY8C6144AZI_S4F82 + default "cy8c6144lqi_s4f82" if SOC_CY8C6144LQI_S4F82 + default "cy8c6144azi_s4f83" if SOC_CY8C6144AZI_S4F83 + default "cy8c6144azi_s4f62" if SOC_CY8C6144AZI_S4F62 + default "cy8c6144lqi_s4f62" if SOC_CY8C6144LQI_S4F62 + default "cy8c6144azi_s4f12" if SOC_CY8C6144AZI_S4F12 + default "cy8c6144lqi_s4f12" if SOC_CY8C6144LQI_S4F12 + +config SOC_PART_NUMBER + default "CY8C6247BZI_D54" if SOC_PART_NUMBER_CY8C6247BZI_D54 + default "CY8C6347BZI_BLD53" if SOC_PART_NUMBER_CY8C6347BZI_BLD53 + default "CY8C6036BZI_F04" if SOC_CY8C6036BZI_F04 + default "CY8C6016BZI_F04" if SOC_CY8C6016BZI_F04 + default "CY8C6116BZI_F54" if SOC_CY8C6116BZI_F54 + default "CY8C6136BZI_F14" if SOC_CY8C6136BZI_F14 + default "CY8C6136BZI_F34" if SOC_CY8C6136BZI_F34 + default "CY8C6137BZI_F14" if SOC_CY8C6137BZI_F14 + default "CY8C6137BZI_F34" if SOC_CY8C6137BZI_F34 + default "CY8C6137BZI_F54" if SOC_CY8C6137BZI_F54 + default "CY8C6117BZI_F34" if SOC_CY8C6117BZI_F34 + default "CY8C6246BZI_D04" if SOC_CY8C6246BZI_D04 + default "CY8C6247BZI_D44" if SOC_CY8C6247BZI_D44 + default "CY8C6247BZI_D34" if SOC_CY8C6247BZI_D34 + default "CY8C6247BZI_D54" if SOC_CY8C6247BZI_D54 + default "CY8C6336BZI_BLF03" if SOC_CY8C6336BZI_BLF03 + default "CY8C6316BZI_BLF03" if SOC_CY8C6316BZI_BLF03 + default "CY8C6316BZI_BLF53" if SOC_CY8C6316BZI_BLF53 + default "CY8C6336BZI_BLD13" if SOC_CY8C6336BZI_BLD13 + default "CY8C6347BZI_BLD43" if SOC_CY8C6347BZI_BLD43 + default "CY8C6347BZI_BLD33" if SOC_CY8C6347BZI_BLD33 + default "CY8C6347BZI_BLD53" if SOC_CY8C6347BZI_BLD53 + default "CY8C6347FMI_BLD13" if SOC_CY8C6347FMI_BLD13 + default "CY8C6347FMI_BLD43" if SOC_CY8C6347FMI_BLD43 + default "CY8C6347FMI_BLD33" if SOC_CY8C6347FMI_BLD33 + default "CY8C6347FMI_BLD53" if SOC_CY8C6347FMI_BLD53 + default "CY8C6137FDI_F02" if SOC_CY8C6137FDI_F02 + default "CY8C6117FDI_F02" if SOC_CY8C6117FDI_F02 + default "CY8C6247FDI_D02" if SOC_CY8C6247FDI_D02 + default "CY8C6247FDI_D32" if SOC_CY8C6247FDI_D32 + default "CY8C6336BZI_BUD13" if SOC_CY8C6336BZI_BUD13 + default "CY8C6347BZI_BUD43" if SOC_CY8C6347BZI_BUD43 + default "CY8C6347BZI_BUD33" if SOC_CY8C6347BZI_BUD33 + default "CY8C6347BZI_BUD53" if SOC_CY8C6347BZI_BUD53 + default "CY8C6337BZI_BLF13" if SOC_CY8C6337BZI_BLF13 + default "CY8C6136FDI_F42" if SOC_CY8C6136FDI_F42 + default "CY8C6247FDI_D52" if SOC_CY8C6247FDI_D52 + default "CY8C6136FTI_F42" if SOC_CY8C6136FTI_F42 + default "CY8C6247FTI_D52" if SOC_CY8C6247FTI_D52 + default "CY8C6247BZI_AUD54" if SOC_CY8C6247BZI_AUD54 + default "CY8C6336BZI_BLF04" if SOC_CY8C6336BZI_BLF04 + default "CY8C6316BZI_BLF04" if SOC_CY8C6316BZI_BLF04 + default "CY8C6316BZI_BLF54" if SOC_CY8C6316BZI_BLF54 + default "CY8C6336BZI_BLD14" if SOC_CY8C6336BZI_BLD14 + default "CY8C6347BZI_BLD44" if SOC_CY8C6347BZI_BLD44 + default "CY8C6347BZI_BLD34" if SOC_CY8C6347BZI_BLD34 + default "CY8C6347BZI_BLD54" if SOC_CY8C6347BZI_BLD54 + default "CY8C6247BFI_D54" if SOC_CY8C6247BFI_D54 + default "CYBLE_416045_02_device" if SOC_CYBLE_416045_02 + default "CY8C6347FMI_BUD53" if SOC_CY8C6347FMI_BUD53 + default "CY8C6347FMI_BUD13" if SOC_CY8C6347FMI_BUD13 + default "CY8C6347FMI_BUD43" if SOC_CY8C6347FMI_BUD43 + default "CY8C6347FMI_BUD33" if SOC_CY8C6347FMI_BUD33 + default "CY8C6137WI_F54" if SOC_CY8C6137WI_F54 + default "CY8C6117WI_F34" if SOC_CY8C6117WI_F34 + default "CY8C6247WI_D54" if SOC_CY8C6247WI_D54 + default "CY8C6336LQI_BLF02" if SOC_CY8C6336LQI_BLF02 + default "CY8C6336LQI_BLF42" if SOC_CY8C6336LQI_BLF42 + default "CY8C6347LQI_BLD52" if SOC_CY8C6347LQI_BLD52 + default "CYB06447BZI_BLD54" if SOC_CYB06447BZI_BLD54 + default "CYB06447BZI_BLD53" if SOC_CYB06447BZI_BLD53 + default "CYB06447BZI_D54" if SOC_CYB06447BZI_D54 + default "CYB0644ABZI_S2D44" if SOC_CYB0644ABZI_S2D44 + default "CYS0644ABZI_S2D44" if SOC_CYS0644ABZI_S2D44 + default "CY8C624ABZI_S2D44A0" if SOC_CY8C624ABZI_S2D44A0 + default "CY8C624ABZI_S2D44" if SOC_CY8C624ABZI_S2D44 + default "CY8C624AAZI_S2D44" if SOC_CY8C624AAZI_S2D44 + default "CY8C624AFNI_S2D43" if SOC_CY8C624AFNI_S2D43 + default "CY8C624ABZI_S2D04" if SOC_CY8C624ABZI_S2D04 + default "CY8C624ABZI_S2D14" if SOC_CY8C624ABZI_S2D14 + default "CY8C624AAZI_S2D14" if SOC_CY8C624AAZI_S2D14 + default "CY8C6248AZI_S2D14" if SOC_CY8C6248AZI_S2D14 + default "CY8C6248BZI_S2D44" if SOC_CY8C6248BZI_S2D44 + default "CY8C6248AZI_S2D44" if SOC_CY8C6248AZI_S2D44 + default "CY8C6248FNI_S2D43" if SOC_CY8C6248FNI_S2D43 + default "CY8C614ABZI_S2F04" if SOC_CY8C614ABZI_S2F04 + default "CY8C614AAZI_S2F04" if SOC_CY8C614AAZI_S2F04 + default "CY8C614AFNI_S2F03" if SOC_CY8C614AFNI_S2F03 + default "CY8C614AAZI_S2F14" if SOC_CY8C614AAZI_S2F14 + default "CY8C614ABZI_S2F44" if SOC_CY8C614ABZI_S2F44 + default "CY8C614AAZI_S2F44" if SOC_CY8C614AAZI_S2F44 + default "CY8C614AFNI_S2F43" if SOC_CY8C614AFNI_S2F43 + default "CY8C6148BZI_S2F44" if SOC_CY8C6148BZI_S2F44 + default "CY8C6148AZI_S2F44" if SOC_CY8C6148AZI_S2F44 + default "CY8C6148FNI_S2F43" if SOC_CY8C6148FNI_S2F43 + default "CY8C624ABZI_D44" if SOC_CY8C624ABZI_D44 + default "CY8C624ALQI_S2D42" if SOC_CY8C624ALQI_S2D42 + default "CY8C624ALQI_S2D02" if SOC_CY8C624ALQI_S2D02 + default "CY8C6248LQI_S2D42" if SOC_CY8C6248LQI_S2D42 + default "CY8C6248LQI_S2D02" if SOC_CY8C6248LQI_S2D02 + default "CY8C614ALQI_S2F42" if SOC_CY8C614ALQI_S2F42 + default "CY8C614ALQI_S2F02" if SOC_CY8C614ALQI_S2F02 + default "CY8C6148LQI_S2F42" if SOC_CY8C6148LQI_S2F42 + default "CY8C6148LQI_S2F02" if SOC_CY8C6148LQI_S2F02 + default "CY8C6244AZI_S4D92" if SOC_CY8C6244AZI_S4D92 + default "CY8C6244LQI_S4D92" if SOC_CY8C6244LQI_S4D92 + default "CY8C6244AZI_S4D93" if SOC_CY8C6244AZI_S4D93 + default "CY8C6244AZI_S4D82" if SOC_CY8C6244AZI_S4D82 + default "CY8C6244LQI_S4D82" if SOC_CY8C6244LQI_S4D82 + default "CY8C6244AZI_S4D83" if SOC_CY8C6244AZI_S4D83 + default "CY8C6244AZI_S4D62" if SOC_CY8C6244AZI_S4D62 + default "CY8C6244LQI_S4D62" if SOC_CY8C6244LQI_S4D62 + default "CY8C6244AZI_S4D12" if SOC_CY8C6244AZI_S4D12 + default "CY8C6244LQI_S4D12" if SOC_CY8C6244LQI_S4D12 + default "CY8C6144AZI_S4F92" if SOC_CY8C6144AZI_S4F92 + default "CY8C6144LQI_S4F92" if SOC_CY8C6144LQI_S4F92 + default "CY8C6144AZI_S4F93" if SOC_CY8C6144AZI_S4F93 + default "CY8C6144AZI_S4F82" if SOC_CY8C6144AZI_S4F82 + default "CY8C6144LQI_S4F82" if SOC_CY8C6144LQI_S4F82 + default "CY8C6144AZI_S4F83" if SOC_CY8C6144AZI_S4F83 + default "CY8C6144AZI_S4F62" if SOC_CY8C6144AZI_S4F62 + default "CY8C6144LQI_S4F62" if SOC_CY8C6144LQI_S4F62 + default "CY8C6144AZI_S4F12" if SOC_CY8C6144AZI_S4F12 + default "CY8C6144LQI_S4F12" if SOC_CY8C6144LQI_S4F12 diff --git a/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_01 b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_01 new file mode 100644 index 00000000000000..3120bfdded237d --- /dev/null +++ b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_01 @@ -0,0 +1,15 @@ +# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSoC6_01 based MCU default configuration + +if SOC_DIE_PSOC6_01 + +config NUM_IRQS + default 32 if CPU_CORTEX_M0PLUS + default 147 if CPU_CORTEX_M4 + +# add additional die specific params + +endif # SOC_DIE_PSOC6_01 diff --git a/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_02 b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_02 new file mode 100644 index 00000000000000..b50a91cff1efeb --- /dev/null +++ b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_02 @@ -0,0 +1,15 @@ +# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSoC6_02 based MCU default configuration + +if SOC_DIE_PSOC6_02 + +config NUM_IRQS + default 32 if CPU_CORTEX_M0PLUS + default 168 if CPU_CORTEX_M4 + +# add additional die specific params + +endif # SOC_DIE_PSOC6_02 diff --git a/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_04 b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_04 new file mode 100644 index 00000000000000..30908b188a729d --- /dev/null +++ b/soc/cypress/psoc6/new/Kconfig.defconfig.psoc6_04 @@ -0,0 +1,14 @@ +# Copyright (c) 2022 Cypress Semiconductor Corporation (an Infineon company) or +# an affiliate of Cypress Semiconductor Corporation +# Copyright (c) David Ullmann +# SPDX-License-Identifier: Apache-2.0 + +# Infineon PSoC6_04 based MCU default configuration + +if SOC_DIE_PSOC6_04 + +config NUM_IRQS + default 16 if CPU_CORTEX_M0PLUS + default 175 if CPU_CORTEX_M4 + +endif # SOC_DIE_PSOC6_04 diff --git a/soc/arm/infineon_cat1/common/pinctrl_soc.h b/soc/cypress/psoc6/new/common/pinctrl_soc.h similarity index 100% rename from soc/arm/infineon_cat1/common/pinctrl_soc.h rename to soc/cypress/psoc6/new/common/pinctrl_soc.h diff --git a/soc/arm/infineon_cat1/psoc6/noinit.ld b/soc/cypress/psoc6/new/noinit.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/noinit.ld rename to soc/cypress/psoc6/new/noinit.ld diff --git a/soc/arm/infineon_cat1/psoc6/ram_cm0image.ld b/soc/cypress/psoc6/new/ram_cm0image.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/ram_cm0image.ld rename to soc/cypress/psoc6/new/ram_cm0image.ld diff --git a/soc/arm/infineon_cat1/psoc6/ram_func.ld b/soc/cypress/psoc6/new/ram_func.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/ram_func.ld rename to soc/cypress/psoc6/new/ram_func.ld diff --git a/soc/arm/infineon_cat1/psoc6/rom.ld b/soc/cypress/psoc6/new/rom.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/rom.ld rename to soc/cypress/psoc6/new/rom.ld diff --git a/soc/arm/infineon_cat1/psoc6/rom_cm0image.ld b/soc/cypress/psoc6/new/rom_cm0image.ld similarity index 100% rename from soc/arm/infineon_cat1/psoc6/rom_cm0image.ld rename to soc/cypress/psoc6/new/rom_cm0image.ld diff --git a/soc/arm/infineon_cat1/psoc6/soc.c b/soc/cypress/psoc6/new/soc.c similarity index 100% rename from soc/arm/infineon_cat1/psoc6/soc.c rename to soc/cypress/psoc6/new/soc.c diff --git a/soc/arm/infineon_cat1/psoc6/soc.h b/soc/cypress/psoc6/new/soc.h similarity index 100% rename from soc/arm/infineon_cat1/psoc6/soc.h rename to soc/cypress/psoc6/new/soc.h diff --git a/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0 b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0 new file mode 100644 index 00000000000000..df5e232dc0f0f3 --- /dev/null +++ b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m0 @@ -0,0 +1,10 @@ +# Cypress PSoC6 CM0 platform configuration options +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CY8C6247_M0 || SOC_CY8C6347_M0 + +config NUM_IRQS + default 32 + +endif # SOC_CY8C6247_M0 || SOC_CY8C6347_M0 diff --git a/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4 b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4 new file mode 100644 index 00000000000000..975ea4fa7fb617 --- /dev/null +++ b/soc/cypress/psoc6/old/Kconfig.defconfig.psoc6_m4 @@ -0,0 +1,10 @@ +# Cypress PSoC6 CM4 platform configuration options +# Copyright (c) 2018, Cypress +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CY8C6247_M4 || SOC_CY8C6347_M4 + +config NUM_IRQS + default 147 + +endif # SOC_CY8C6247_M4 || SOC_CY8C6347_M4 diff --git a/soc/arm/cypress/common/CMakeLists.txt b/soc/cypress/psoc6/old/common/CMakeLists.txt similarity index 100% rename from soc/arm/cypress/common/CMakeLists.txt rename to soc/cypress/psoc6/old/common/CMakeLists.txt diff --git a/soc/arm/cypress/common/cypress_psoc6_dt.h b/soc/cypress/psoc6/old/common/cypress_psoc6_dt.h similarity index 100% rename from soc/arm/cypress/common/cypress_psoc6_dt.h rename to soc/cypress/psoc6/old/common/cypress_psoc6_dt.h diff --git a/soc/arm/cypress/common/soc_gpio.c b/soc/cypress/psoc6/old/common/soc_gpio.c similarity index 100% rename from soc/arm/cypress/common/soc_gpio.c rename to soc/cypress/psoc6/old/common/soc_gpio.c diff --git a/soc/arm/cypress/common/soc_gpio.h b/soc/cypress/psoc6/old/common/soc_gpio.h similarity index 100% rename from soc/arm/cypress/common/soc_gpio.h rename to soc/cypress/psoc6/old/common/soc_gpio.h diff --git a/soc/arm/cypress/psoc6/noinit.ld b/soc/cypress/psoc6/old/noinit.ld similarity index 100% rename from soc/arm/cypress/psoc6/noinit.ld rename to soc/cypress/psoc6/old/noinit.ld diff --git a/soc/arm/cypress/psoc6/rwdata.ld b/soc/cypress/psoc6/old/rwdata.ld similarity index 100% rename from soc/arm/cypress/psoc6/rwdata.ld rename to soc/cypress/psoc6/old/rwdata.ld diff --git a/soc/arm/cypress/psoc6/soc.c b/soc/cypress/psoc6/old/soc.c similarity index 100% rename from soc/arm/cypress/psoc6/soc.c rename to soc/cypress/psoc6/old/soc.c diff --git a/soc/arm/cypress/psoc6/soc.h b/soc/cypress/psoc6/old/soc.h similarity index 100% rename from soc/arm/cypress/psoc6/soc.h rename to soc/cypress/psoc6/old/soc.h diff --git a/soc/cypress/soc.yml b/soc/cypress/soc.yml new file mode 100644 index 00000000000000..c973ed24b94123 --- /dev/null +++ b/soc/cypress/soc.yml @@ -0,0 +1,131 @@ +family: +- name: psoc6 + series: + - name: psoc62 + socs: + - name: cy8c6247 + cpuclusters: + - name: m0 + - name: m4 + - name: psoc63 + socs: + - name: cy8c6347 + cpuclusters: + - name: m0 + - name: m4 +- name: infineon_cat1 + series: + - name: psoc6 + socs: + - name: cy8c6036bzi_f04 + - name: cy8c6016bzi_f04 + - name: cy8c6116bzi_f54 + - name: cy8c6136bzi_f14 + - name: cy8c6136bzi_f34 + - name: cy8c6137bzi_f14 + - name: cy8c6137bzi_f34 + - name: cy8c6137bzi_f54 + - name: cy8c6117bzi_f34 + - name: cy8c6246bzi_d04 + - name: cy8c6247bzi_d44 + - name: cy8c6247bzi_d34 + - name: cy8c6247bzi_d54 + - name: cy8c6336bzi_blf03 + - name: cy8c6316bzi_blf03 + - name: cy8c6316bzi_blf53 + - name: cy8c6336bzi_bld13 + - name: cy8c6347bzi_bld43 + - name: cy8c6347bzi_bld33 + - name: cy8c6347bzi_bld53 + - name: cy8c6347fmi_bld13 + - name: cy8c6347fmi_bld43 + - name: cy8c6347fmi_bld33 + - name: cy8c6347fmi_bld53 + - name: cy8c6137fdi_f02 + - name: cy8c6117fdi_f02 + - name: cy8c6247fdi_d02 + - name: cy8c6247fdi_d32 + - name: cy8c6336bzi_bud13 + - name: cy8c6347bzi_bud43 + - name: cy8c6347bzi_bud33 + - name: cy8c6347bzi_bud53 + - name: cy8c6337bzi_blf13 + - name: cy8c6136fdi_f42 + - name: cy8c6247fdi_d52 + - name: cy8c6136fti_f42 + - name: cy8c6247fti_d52 + - name: cy8c6247bzi_aud54 + - name: cy8c6336bzi_blf04 + - name: cy8c6316bzi_blf04 + - name: cy8c6316bzi_blf54 + - name: cy8c6336bzi_bld14 + - name: cy8c6347bzi_bld44 + - name: cy8c6347bzi_bld34 + - name: cy8c6347bzi_bld54 + - name: cy8c6247bfi_d54 + - name: cyble_416045_02 + - name: cy8c6347fmi_bud53 + - name: cy8c6347fmi_bud13 + - name: cy8c6347fmi_bud43 + - name: cy8c6347fmi_bud33 + - name: cy8c6137wi_f54 + - name: cy8c6117wi_f34 + - name: cy8c6247wi_d54 + - name: cy8c6336lqi_blf02 + - name: cy8c6336lqi_blf42 + - name: cy8c6347lqi_bld52 + - name: cyb06447bzi_bld54 + - name: cyb06447bzi_bld53 + - name: cyb06447bzi_d54 + - name: cyb0644abzi_s2d44 + - name: cys0644abzi_s2d44 + - name: cy8c624abzi_s2d44a0 + - name: cy8c624abzi_s2d44 + - name: cy8c624aazi_s2d44 + - name: cy8c624afni_s2d43 + - name: cy8c624abzi_s2d04 + - name: cy8c624abzi_s2d14 + - name: cy8c624aazi_s2d14 + - name: cy8c6248azi_s2d14 + - name: cy8c6248bzi_s2d44 + - name: cy8c6248azi_s2d44 + - name: cy8c6248fni_s2d43 + - name: cy8c614abzi_s2f04 + - name: cy8c614aazi_s2f04 + - name: cy8c614afni_s2f03 + - name: cy8c614aazi_s2f14 + - name: cy8c614abzi_s2f44 + - name: cy8c614aazi_s2f44 + - name: cy8c614afni_s2f43 + - name: cy8c6148bzi_s2f44 + - name: cy8c6148azi_s2f44 + - name: cy8c6148fni_s2f43 + - name: cy8c624abzi_d44 + - name: cy8c624alqi_s2d42 + - name: cy8c624alqi_s2d02 + - name: cy8c6248lqi_s2d42 + - name: cy8c6248lqi_s2d02 + - name: cy8c614alqi_s2f42 + - name: cy8c614alqi_s2f02 + - name: cy8c6148lqi_s2f42 + - name: cy8c6148lqi_s2f02 + - name: cy8c6244azi_s4d92 + - name: cy8c6244lqi_s4d92 + - name: cy8c6244azi_s4d93 + - name: cy8c6244azi_s4d82 + - name: cy8c6244lqi_s4d82 + - name: cy8c6244azi_s4d83 + - name: cy8c6244azi_s4d62 + - name: cy8c6244lqi_s4d62 + - name: cy8c6244azi_s4d12 + - name: cy8c6244lqi_s4d12 + - name: cy8c6144azi_s4f92 + - name: cy8c6144lqi_s4f92 + - name: cy8c6144azi_s4f93 + - name: cy8c6144azi_s4f82 + - name: cy8c6144lqi_s4f82 + - name: cy8c6144azi_s4f83 + - name: cy8c6144azi_s4f62 + - name: cy8c6144lqi_s4f62 + - name: cy8c6144azi_s4f12 + - name: cy8c6144lqi_s4f12 diff --git a/soc/riscv/efinix_sapphire/CMakeLists.txt b/soc/efinix/sapphire/CMakeLists.txt similarity index 100% rename from soc/riscv/efinix_sapphire/CMakeLists.txt rename to soc/efinix/sapphire/CMakeLists.txt diff --git a/soc/efinix/sapphire/Kconfig b/soc/efinix/sapphire/Kconfig new file mode 100644 index 00000000000000..4617e7383c5a1b --- /dev/null +++ b/soc/efinix/sapphire/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EFINIX_SAPPHIRE + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC diff --git a/soc/efinix/sapphire/Kconfig.defconfig b/soc/efinix/sapphire/Kconfig.defconfig new file mode 100644 index 00000000000000..75325b2fa55b46 --- /dev/null +++ b/soc/efinix/sapphire/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EFINIX_SAPPHIRE + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config RISCV_SOC_INTERRUPT_INIT + bool + default y + +config NUM_IRQS + int + default 36 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +endif # SOC_EFINIX_SAPPHIRE diff --git a/soc/efinix/sapphire/Kconfig.soc b/soc/efinix/sapphire/Kconfig.soc new file mode 100644 index 00000000000000..5ab00455e4af10 --- /dev/null +++ b/soc/efinix/sapphire/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Efinix Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EFINIX_SAPPHIRE + bool + help + Efinix Sapphire VexRiscv system implementation + +config SOC + default "efinix_sapphire" if SOC_EFINIX_SAPPHIRE diff --git a/soc/efinix/sapphire/soc.yml b/soc/efinix/sapphire/soc.yml new file mode 100644 index 00000000000000..d976114557a85b --- /dev/null +++ b/soc/efinix/sapphire/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: efinix_sapphire diff --git a/soc/espressif/CMakeLists.txt b/soc/espressif/CMakeLists.txt new file mode 100644 index 00000000000000..5f7b7d6579fe1d --- /dev/null +++ b/soc/espressif/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/espressif/Kconfig b/soc/espressif/Kconfig new file mode 100644 index 00000000000000..3c96a64bff601d --- /dev/null +++ b/soc/espressif/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/Kconfig.defconfig b/soc/espressif/Kconfig.defconfig new file mode 100644 index 00000000000000..86ab7f1bd642f5 --- /dev/null +++ b/soc/espressif/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ESPRESSIF_ESP32 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_ESPRESSIF_ESP32 diff --git a/soc/espressif/Kconfig.soc b/soc/espressif/Kconfig.soc new file mode 100644 index 00000000000000..4ad01dec79d06f --- /dev/null +++ b/soc/espressif/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ESPRESSIF_ESP32 + bool + +config SOC_FAMILY + default "espressif_esp32" if SOC_FAMILY_ESPRESSIF_ESP32 + +rsource "*/Kconfig.soc" diff --git a/soc/espressif/common/CMakeLists.txt b/soc/espressif/common/CMakeLists.txt new file mode 100644 index 00000000000000..9cd2b6747acce6 --- /dev/null +++ b/soc/espressif/common/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_SERIES_ESP32 OR CONFIG_SOC_SERIES_ESP32S2 OR CONFIG_SOC_SERIES_ESP32S3) + zephyr_include_directories(include) +endif() diff --git a/soc/espressif/common/Kconfig b/soc/espressif/common/Kconfig new file mode 100644 index 00000000000000..34d3c153c06d12 --- /dev/null +++ b/soc/espressif/common/Kconfig @@ -0,0 +1,215 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config ESPTOOLPY_FLASHFREQ_80M + bool + +config FLASH_SIZE + int + +config FLASH_BASE_ADDRESS + hex + +if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + +config ESP_SPIRAM + bool "Support for external, SPI-connected RAM" + help + This enables support for an external SPI RAM chip, connected in + parallel with the main SPI flash chip. + +config ESP_HEAP_MIN_EXTRAM_THRESHOLD + int "Minimum threshold for external RAM allocation" + default 8192 + range 1024 131072 + depends on ESP_SPIRAM + help + Threshold to decide if memory will be allocated from DRAM + or SPIRAM. If value of allocation size is less than this value, + memory will be allocated from internal RAM. + +config ESP_HEAP_SEARCH_ALL_REGIONS + bool "Search for all available heap regions" + depends on ESP_SPIRAM + default y + help + This configuration enables searching all available heap + regions. If the region of desired capability is exhausted, + memory will be allocated from other available region. + +config ESP_SPIRAM_HEAP_SIZE + int "Size of SPIRAM heap" + default 262134 if SYS_HEAP_SMALL_ONLY + default 1048576 if !SYS_HEAP_SMALL_ONLY + depends on ESP_SPIRAM + help + Specify size of SPIRAM heap. + +menu "SPI RAM config" + depends on ESP_SPIRAM + +choice SPIRAM_MODE + prompt "Mode (QUAD/OCT) of SPI RAM chip in use" + default SPIRAM_MODE_QUAD + +config SPIRAM_MODE_QUAD + bool "Quad Mode PSRAM" + +endchoice # SPIRAM_MODE + +choice SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + depends on ESP_SPIRAM + default SPIRAM_TYPE_ESPPSRAM16 + +config SPIRAM_TYPE_ESPPSRAM16 + bool "ESP-PSRAM16 or APS1604" + +config SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64 or LY68L6400" + +endchoice # SPIRAM_TYPE + +config ESP_SPIRAM_SIZE + int "Size of SPIRAM part" + default 2097152 if SPIRAM_TYPE_ESPPSRAM16 + default 4194304 if SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if SPIRAM_TYPE_ESPPSRAM64 + help + Specify size of SPIRAM part. + NOTE: If SPIRAM size is greater than 4MB, only + lower 4MB can be allocated using k_malloc(). + +choice SPIRAM_SPEED + prompt "Set RAM clock speed" + default SPIRAM_SPEED_40M + help + Select the speed for the SPI RAM chip. + If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: + + 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz + 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz + 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz + + Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host + will be occupied by the system. Which SPI host to use can be selected by the config item + SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The + option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. + (ESPTOOLPY_FLASHFREQ_79M is true) + +config SPIRAM_SPEED_26M + bool "26MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_20M + bool "20MHz clock speed" + depends on SOC_SERIES_ESP32S2 + +config SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config SPIRAM_SPEED_80M + depends on ESPTOOLPY_FLASHFREQ_80M + bool "80MHz clock speed" + +config SPIRAM_SPEED_120M + depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 + bool "120MHz clock speed" + +endchoice # SPIRAM_SPEED + +menu "PSRAM clock and cs IO for ESP32-DOWD" + +config D0WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 17 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D0WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 16 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use + 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-DOWD + +menu "PSRAM clock and cs IO for ESP32-D2WD" + +config D2WD_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 9 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +config D2WD_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, + so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. + +endmenu # PSRAM clock and cs IO for ESP32-D2WD + +menu "PSRAM clock and cs IO for ESP32-PICO" + +config PICO_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 10 + help + The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. + + For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock + IO. + For the reference hardware design, please refer to + https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf + +endmenu # PSRAM clock and cs IO for ESP32-PICO + +config SPIRAM_CUSTOM_SPIWP_SD3_PIN + bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" + default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 + default n + help + This setting is only used if the SPI flash pins have been overridden by setting the eFuses + SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. + + When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka + ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI + mode, so a WP pin setting is necessary. + + If this config item is set to N (default), the correct WP pin will be automatically used for any + Espressif chip or module with integrated flash. If a custom setting is needed, set this config item + to Y and specify the GPIO number connected to the WP pin. + + When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin + configured in the bootloader. + +config SPIRAM_SPIWP_SD3_PIN + int "Custom SPI PSRAM WP(SD3) Pin" + range 0 33 + default 7 + help + The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored + + If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this + value to the GPIO number of the SPIRAM WP pin. + +config SPIRAM + bool + default y + +endmenu # SPI RAM config + +endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 diff --git a/soc/espressif/common/Kconfig.defconfig b/soc/espressif/common/Kconfig.defconfig new file mode 100644 index 00000000000000..62f930b0283a77 --- /dev/null +++ b/soc/espressif/common/Kconfig.defconfig @@ -0,0 +1,103 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32C3 + +config GEN_ISR_TABLES + default y + +config GEN_SW_ISR_TABLE + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config DYNAMIC_INTERRUPTS + default y + +config ISR_STACK_SIZE + default 2048 + +config ATOMIC_OPERATIONS_C + default y + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 16000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config CLOCK_CONTROL + default y + +if BOOTLOADER_MCUBOOT + +config HAS_FLASH_LOAD_OFFSET + default y + +config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + +config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + +config ROM_START_OFFSET + default 0x20 + +endif # BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_ESP32C3 + +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 + +# Xtensa default options for ESP32 family +config XTENSA_RESET_VECTOR + default n + +config XTENSA_USE_CORE_CRT1 + default n + +config GEN_ISR_TABLES + default y + +config GEN_IRQ_VECTOR_TABLE + default n + +config CLOCK_CONTROL + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +if BOOTLOADER_MCUBOOT + +config HAS_FLASH_LOAD_OFFSET + default y + +config MCUBOOT_GENERATE_UNSIGNED_IMAGE + default y + +config MCUBOOT_GENERATE_CONFIRMED_IMAGE + default y + +config ROM_START_OFFSET + default 0x20 + +endif # BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h b/soc/espressif/common/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/espressif_esp32/common/include/_soc_inthandlers.h rename to soc/espressif/common/include/_soc_inthandlers.h diff --git a/soc/xtensa/espressif_esp32/common/include/gdbstub/soc.h b/soc/espressif/common/include/gdbstub/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/common/include/gdbstub/soc.h rename to soc/espressif/common/include/gdbstub/soc.h diff --git a/soc/espressif/esp32/CMakeLists.txt b/soc/espressif/esp32/CMakeLists.txt new file mode 100644 index 00000000000000..537c7c76accccd --- /dev/null +++ b/soc/espressif/esp32/CMakeLists.txt @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_ESP32_APPCPU) + zephyr_sources(soc_appcpu.c) +else() + zephyr_sources( + soc.c + loader.c + esp32-mp.c + ) +endif() + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) + +zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() +endif() + +## When building for APPCPU +if(CONFIG_SOC_ESP32_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py + ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c + -a "esp32_appcpu_fw_array") + endif() +else() + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + # get code-partition slot0 address + dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") + dt_reg_addr(img_0_off PATH ${dts_partition_path}) + + # get code-partition boot address + dt_nodelabel(dts_partition_path NODELABEL "boot_partition") + dt_reg_addr(boot_off PATH ${dts_partition_path}) + + board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +endif() + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_ESP32_APPCPU) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32/Kconfig b/soc/espressif/esp32/Kconfig new file mode 100644 index 00000000000000..bbcd17d1fb0997 --- /dev/null +++ b/soc/espressif/esp32/Kconfig @@ -0,0 +1,263 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32 + select XTENSA + select CLOCK_CONTROL + select DYNAMIC_INTERRUPTS + select ARCH_HAS_GDBSTUB + select ARCH_SUPPORTS_COREDUMP + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select CPU_HAS_FPU + select HAS_PM + select HAS_POWEROFF + +if SOC_SERIES_ESP32 + +config IDF_TARGET_ESP32 + bool "ESP32 as target board" + default y + +config ESP32_APPCPU_IRAM + hex "ESP32 APPCPU IRAM size" + depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU + default 0x20000 + help + Defines APPCPU IRAM area in bytes. + +config ESP32_APPCPU_DRAM + hex "ESP32 APPCPU DRAM size" + depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU + default 0x10000 + help + Defines APPCPU DRAM area in bytes. + +config SOC_ESP32_PROCPU + bool + help + This hidden configuration defines that build is targeted for PROCPU (core 0). + +config SOC_ESP32_APPCPU + bool + help + This hidden configuration defines that build is targeted for APPCPU (core 1). + +config SOC_ENABLE_APPCPU + bool + default y + depends on IPM && SOC_ESP32_PROCPU + help + This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +config ESP32_BT_RESERVE_DRAM + hex "Bluetooth controller reserved RAM region" + default 0xdb5c if BT + default 0 + +config ESP_HEAP_MEM_POOL_REGION_1_SIZE + int "Internal DRAM region 1 mempool size" + default 0 if MCUBOOT + default 1024 if SOC_ESP32_PROCPU + default 49152 + help + ESP32 has two banks of size 192K and 128K which can be used + as DRAM, system heap allocates area from region 0. + This configuration can be used to add memory from region 1 + to heap and can be allocated using k_malloc. + +choice ESP32_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 150kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8.5MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 150kHz oscillator. It does not require external components. + +config ESP32_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + +config ESP32_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config ESP32_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" + +endchoice # ESP32_RTC_CLK_SRC + +config ESP32_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config ESP32_RTC_XTAL_CAL_RETRY + int "Number of attempts to repeat 32k XTAL calibration" + default 1 + depends on ESP32_RTC_CLK_SRC_EXT_CRYS + help + Number of attempts to repeat 32k XTAL calibration + before giving up and switching to the internal RC. + Increase this option if the 32k crystal oscillator + does not start and switches to internal RC. + +config ESP32_DEEP_SLEEP_WAKEUP_DELAY + int "Extra delay in deep sleep wake stub (in us)" + default 2000 + range 0 5000 + help + When ESP32 exits deep sleep, the CPU and the flash chip are powered on + at the same time. CPU will run deep sleep stub first, and then + proceed to load code from flash. Some flash chips need sufficient + time to pass between power on and first read operation. By default, + without any extra delay, this time is approximately 900us, although + some flash chip types need more than that. + + By default extra delay is set to 2000us. When optimizing startup time + for applications which require it, this value may be reduced. + + If you are seeing "flash read err, 1000" message printed to the + console after deep sleep reset, try increasing this value. + +choice ESP32_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is four, + all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally + administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) + to the final octet of the base MAC address. If the number of universal MAC addresses is two, + only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. + These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. + The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. + These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 2 or 4 per device.) + +config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP_MAC_ADDR_UNIVERSE_BT + bool + +config ESP_MAC_ADDR_UNIVERSE_ETH + bool + +config ESP32_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi/BLE TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +config ESP32_EMAC + bool + default y if ETH_ESP32 + default y if MDIO_ESP32 + default n + help + Hidden option to enable the ESP32 Ethernet MAC driver. + Both Ethernet and MDIO depend on this driver. + This option allows enabling MDIO independently of Ethernet. + +if ESP32_EMAC + +config ETH_DMA_BUFFER_SIZE + int "Ethernet DMA buffer size (Byte)" + range 256 1600 + default 512 + help + Set the size of each buffer used by Ethernet MAC DMA. + +config ETH_DMA_RX_BUFFER_NUM + int "Amount of Ethernet DMA Rx buffers" + range 3 30 + default 10 + help + Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. + Larger number of buffers could increase throughput somehow. + +config ETH_DMA_TX_BUFFER_NUM + int "Amount of Ethernet DMA Tx buffers" + range 3 30 + default 10 + help + Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. + Larger number of buffers could increase throughput somehow. + +endif # ESP32_EMAC config + +endif # SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/Kconfig.defconfig b/soc/espressif/esp32/Kconfig.defconfig new file mode 100644 index 00000000000000..7d793d2ecaa66f --- /dev/null +++ b/soc/espressif/esp32/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0) + +if SMP + +config SCHED_IPI_SUPPORTED + default y + +config SCHED_CPU_MASK + default y + +config MP_MAX_NUM_CPUS + default 2 + +endif # SMP config + +if GDBSTUB + +# ESP32 GDB expects 420 bytes G-packet. +# So double for hexadecimal digits. +config GDBSTUB_BUF_SZ + default 840 if GDBSTUB + +endif # GDBSTUB config + +endif # SOC_SERIES_ESP32 config diff --git a/soc/espressif/esp32/Kconfig.soc b/soc/espressif/esp32/Kconfig.soc new file mode 100644 index 00000000000000..08aa0c413b45cd --- /dev/null +++ b/soc/espressif/esp32/Kconfig.soc @@ -0,0 +1,153 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32 Series + +config SOC_ESP32_D0WD_V3 + bool + select SOC_ESP32 + help + ESP32_D0WD_V3 + +config SOC_ESP32_D0WDR2_V3 + bool + select SOC_ESP32 + help + ESP32_D0WDR2_V3 + +config SOC_ESP32_U4WDH + bool + select SOC_ESP32 + help + ESP32_U4WDH + +config SOC_ESP32_PICO_V3 + bool + select SOC_ESP32 + help + ESP32_PICO_V3 + +config SOC_ESP32_PICO_V3_02 + bool + select SOC_ESP32 + help + ESP32_PICO_V3_02 + +config SOC_ESP32_PICO_D4 + bool + select SOC_ESP32 + help + ESP32_PICO_D4 + +# SiP with external flash / psram +config SOC_ESP32_WROOM_DA_N4 + bool + select SOC_ESP32 + help + ESP32_WROOM_DA_N4 + +config SOC_ESP32_WROOM_DA_N8 + bool + select SOC_ESP32 + help + ESP32_WROOM_DA_N8 + +config SOC_ESP32_WROOM_DA_N16 + bool + select SOC_ESP32 + help + ESP32_WROOM_DA_N16 + +config SOC_ESP32_WROOM_32UE_N4 + bool + select SOC_ESP32 + help + ESP32_WROOM_32UE_N4 + +config SOC_ESP32_WROOM_32UE_N8 + bool + select SOC_ESP32 + help + ESP32_WROOM_32UE_N8 + +config SOC_ESP32_WROOM_32UE_N16 + bool + select SOC_ESP32 + help + ESP32_WROOM_32UE_N16 + +config SOC_ESP32_WROVER_E_N4R2 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N4R2 + +config SOC_ESP32_WROVER_E_N8R2 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N8R2 + +config SOC_ESP32_WROVER_E_N16R2 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N16R2 + +config SOC_ESP32_WROVER_E_N4R8 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N4R8 + +config SOC_ESP32_WROVER_E_N8R8 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N8R8 + +config SOC_ESP32_WROVER_E_N16R8 + bool + select SOC_ESP32 + help + ESP32_WROVER_E_N16R8 + +config SOC_ESP32 + bool + select SOC_SERIES_ESP32 + help + ESP32 + +config SOC_SERIES + default "esp32" if SOC_SERIES_ESP32 + +config SOC + default "esp32" if SOC_SERIES_ESP32 + +config SOC_PART_NUMBER + default "ESP32_D0WD_V3" if SOC_ESP32_D0WD_V3 + default "ESP32_D0WDR2_V3" if SOC_ESP32_D0WDR2_V3 + default "ESP32_U4WDH" if SOC_ESP32_U4WDH + default "ESP32_PICO_V3" if SOC_ESP32_PICO_V3 + default "ESP32_PICO_V3_02" if SOC_ESP32_PICO_V3_02 + default "ESP32_PICO_D4" if SOC_ESP32_PICO_D4 + default "ESP32_WROOM_DA_N4" if SOC_ESP32_WROOM_DA_N4 + default "ESP32_WROOM_DA_N8" if SOC_ESP32_WROOM_DA_N8 + default "ESP32_WROOM_DA_N16" if SOC_ESP32_WROOM_DA_N16 + default "ESP32_WROOM_32UE_N4" if SOC_ESP32_WROOM_32UE_N4 + default "ESP32_WROOM_32UE_N8" if SOC_ESP32_WROOM_32UE_N8 + default "ESP32_WROOM_32UE_N16" if SOC_ESP32_WROOM_32UE_N16 + default "ESP32_WROVER_E_N4R2" if SOC_ESP32_WROVER_E_N4R2 + default "ESP32_WROVER_E_N8R2" if SOC_ESP32_WROVER_E_N8R2 + default "ESP32_WROVER_E_N16R2" if SOC_ESP32_WROVER_E_N16R2 + default "ESP32_WROVER_E_N4R8" if SOC_ESP32_WROVER_E_N4R8 + default "ESP32_WROVER_E_N8R8" if SOC_ESP32_WROVER_E_N8R8 + default "ESP32_WROVER_E_N16R8" if SOC_ESP32_WROVER_E_N16R8 + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32" if SOC_SERIES_ESP32 diff --git a/soc/espressif/esp32/default.ld b/soc/espressif/esp32/default.ld new file mode 100644 index 00000000000000..a3577757dcdac6 --- /dev/null +++ b/soc/espressif/esp32/default.ld @@ -0,0 +1,583 @@ +/* + * Copyright (c) 2016 Cadence Design Systems, Inc. + * Copyright (c) 2017 Intel Corporation + * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the Xtensa platform. + */ + +#include +#include +#include +#include + +#define RAMABLE_REGION dram0_0_seg +#ifndef CONFIG_SOC_ENABLE_APPCPU +#define RAMABLE_REGION_1 dram0_1_seg +#else +#define RAMABLE_REGION_1 dram0_0_seg +#endif +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define FLASH_CODE_REGION irom0_0_seg + +#define ROMABLE_REGION ROM + +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x400000 +#endif + +#ifdef CONFIG_BOOTLOADER_ESP_IDF +#define IROM_SEG_ORG 0x400D0020 +#define IROM_SEG_LEN FLASH_SIZE-0x20 +#define IROM_SEG_ALIGN 0x4 +#else +#define IROM_SEG_ORG 0x400D0000 +#define IROM_SEG_LEN FLASH_SIZE +#define IROM_SEG_ALIGN 0x10000 +#endif +#define IRAM_SEG_LEN 0x20000 + +/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. + * Executing directly from LMA is not possible. */ +#undef GROUP_ROM_LINK_IN +#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion + +MEMORY +{ + mcuboot_hdr (RX): org = 0x0, len = 0x20 + metadata (RX): org = 0x20, len = 0x20 + ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 + + #ifdef CONFIG_SOC_ENABLE_APPCPU + iram0_0_seg(RX): org = 0x40080000, len = 0x08000 + #else + iram0_0_seg(RX): org = 0x40080000, len = IRAM_SEG_LEN + #endif + + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + /* + * Following is DRAM memory split with reserved address ranges in ESP32: + * + * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions) + * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage) + * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU) + * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU) + * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage) + * + * FIXME: + * - Utilize available memory regions to full capacity + */ + dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM + + #ifdef CONFIG_SOC_ENABLE_APPCPU + dram0_shm0_seg(RW): org = 0x3FFE5230, len = 2K /* shared RAM reserved for IPM */ + dram0_sem0_seg(RW): org = 0x3FFE5A30, len = 8 /* shared data reserved for IPM data header */ + dram0_1_seg(RW): org = 0x3FFE5A38, len = 0K /* for AMP builds dram0_1 is reserved for network core */ + #else + dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 /* skip data for APP CPU initialization usage */ + #endif + + /* DROM is the first segment placed in generated binary. + * MCUboot binary for ESP32 has image header of 0x20 bytes. + * Additional load header of 0x20 bytes are appended to the image. + * Hence, an offset of 0x40 is added to DROM segment origin. + */ + drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40 + rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000 + rtc_slow_seg(RW): org = 0x50000000, len = 0x1000 +#if defined(CONFIG_ESP_SPIRAM) + ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE +#endif +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +PROVIDE ( _ResetVector = 0x40000400 ); +ENTRY(CONFIG_KERNEL_ENTRY) + +_rom_store_table = 0; + +PROVIDE(_memmap_vecbase_reset = 0x40000450); +PROVIDE(_memmap_reset_vector = 0x40000400); + +SECTIONS +{ + /* Reserve space for MCUboot header in the binary */ + .mcuboot_header : + { + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + } > mcuboot_hdr + .metadata : + { + /* Magic byte for load header */ + LONG(0xace637d3) + + /* Application entry point address */ + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + + LONG(ADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.vectors)) + LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(.iram0.vectors)) + + /* DRAM metadata: + * - Destination address (VMA) for DRAM region + * - Flash offset (LMA) for start of DRAM region + * - Size of DRAM region + */ + + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) + } > metadata + +#include + + _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); + _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; + _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + + /* NOTE: .rodata section should be the first section in the linker script and no + * other section should appear before .rodata section. This is the requirement + * to align ROM section to 64K page offset. + * Adding .rodata as first section helps to reduce size of generated binary by + * few kBs. + */ + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) + { + __rodata_region_start = ABSOLUTE(.); + + . = ALIGN(4); + #include + + . = ALIGN(4); + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + SECTION_PROLOGUE(_RODATA_SECTION_END,,) + { + . = ALIGN(4); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + _image_dram_start = LOADADDR(.dram0.data); + _image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start; + _image_dram_vaddr = ADDR(.dram0.data); + + .dram0.data : + { + __data_start = ABSOLUTE(.); + + _btdm_data_start = ABSOLUTE(.); + *libbtdm_app.a:(.data .data.*) + . = ALIGN (4); + _btdm_data_end = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + #include + . = ALIGN(4); + _end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + _image_iram_start = LOADADDR(.iram0.vectors); + _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start; + _image_iram_vaddr = ADDR(.iram0.vectors); + + /* Send .iram0 code to iram */ + .iram0.vectors : ALIGN(4) + { + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + + /* This goes here, not at top of linker script, so addr2line finds it last, + and uses it in preference to the first symbol in IRAM */ + _iram_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libesp32.a:panic.*(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) + *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) + *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *libc.a:*(.literal .text .literal.* .text.*) + *libphy.a:( .phyiram .phyiram.*) + *libgcov.a:(.literal .text .literal.* .text.*) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + _iram_text_end = ABSOLUTE(.); + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + /* RTC fast memory holds RTC wake stub code, + including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + *rtc_wake_stub*.o(.literal .text .literal.* .text.*) + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /* RTC slow memory holds RTC wake stub + data/rodata, including from any source file + named rtc_wake_stub*.c + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.o(.bss .bss.*) + *rtc_wake_stub*.o(COMMON) + _rtc_bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(rtc_slow_seg) + + /* This section located in RTC SLOW Memory area. + It holds data marked with RTC_SLOW_ATTR attribute. + See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } > rtc_slow_seg + + /* Get size of rtc slow data */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + +#if defined(CONFIG_ESP_SPIRAM) + .ext_ram.bss (NOLOAD): + { + _ext_ram_data_start = ABSOLUTE(.); + +#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) + *libdrivers__wifi.a:(.noinit .noinit.*) + *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) + *libsubsys__net__lib__config.a:(.noinit .noinit.*) + *libsubsys__net__ip.a:(.noinit .noinit.*) + *libsubsys__net.a:(.noinit .noinit.*) +#endif + _spiram_heap_start = ABSOLUTE(.); + . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + + *(.ext_ram.bss*) + + _ext_ram_data_end = ABSOLUTE(.); + } GROUP_LINK_IN(ext_ram_seg) +#endif + + /* Shared RAM */ + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + _btdm_bss_start = ABSOLUTE(.); + *libbtdm_app.a:(.bss .bss.* COMMON) + . = ALIGN (4); + _btdm_bss_end = ABSOLUTE(.); + + /* Buffer for system heap should be placed in dram0_0_seg */ + *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + _end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), + "DRAM segment data does not fit.") + + SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + { + . = ALIGN (8); + *(.noinit) + *(.noinit.*) + . = ALIGN (8); + } GROUP_LINK_IN(RAMABLE_REGION_1) + + _image_irom_start = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; + _image_irom_vaddr = ADDR(.flash.text); + + .flash.text : ALIGN(IROM_SEG_ALIGN) + { + _stext = .; + _text_start = ABSOLUTE(.); + +#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + *(.literal .text .literal.* .text.*) + . = ALIGN(4); + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + resolved by addr2line in preference to the first symbol in + the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + +_heap_sentry = 0x3ffe3f20; + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + +#if defined(CONFIG_ESP_SPIRAM) +ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), + "External SPIRAM overflowed.") +#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32/default_appcpu.ld b/soc/espressif/esp32/default_appcpu.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/default_appcpu.ld rename to soc/espressif/esp32/default_appcpu.ld diff --git a/soc/xtensa/espressif_esp32/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/esp32-mp.c rename to soc/espressif/esp32/esp32-mp.c diff --git a/soc/xtensa/espressif_esp32/esp32/gdbstub.c b/soc/espressif/esp32/gdbstub.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/gdbstub.c rename to soc/espressif/esp32/gdbstub.c diff --git a/soc/xtensa/espressif_esp32/esp32/loader.c b/soc/espressif/esp32/loader.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/loader.c rename to soc/espressif/esp32/loader.c diff --git a/soc/xtensa/espressif_esp32/esp32/mcuboot.ld b/soc/espressif/esp32/mcuboot.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/mcuboot.ld rename to soc/espressif/esp32/mcuboot.ld diff --git a/soc/xtensa/espressif_esp32/esp32/newlib_fix.c b/soc/espressif/esp32/newlib_fix.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/newlib_fix.c rename to soc/espressif/esp32/newlib_fix.c diff --git a/soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h b/soc/espressif/esp32/pinctrl_soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/pinctrl_soc.h rename to soc/espressif/esp32/pinctrl_soc.h diff --git a/soc/xtensa/espressif_esp32/esp32/power.c b/soc/espressif/esp32/power.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/power.c rename to soc/espressif/esp32/power.c diff --git a/soc/xtensa/espressif_esp32/esp32/poweroff.c b/soc/espressif/esp32/poweroff.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/poweroff.c rename to soc/espressif/esp32/poweroff.c diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c new file mode 100644 index 00000000000000..8e1a8ff737ab57 --- /dev/null +++ b/soc/espressif/esp32/soc.c @@ -0,0 +1,266 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Include esp-idf headers first to avoid redefining BIT() macro */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "esp_private/system_internal.h" +#include "esp32/rom/cache.h" +#include "hal/soc_ll.h" +#include "soc/cpu.h" +#include "soc/gpio_periph.h" +#include "esp_spi_flash.h" +#include "esp_err.h" +#include "esp_timer.h" +#include "esp32/spiram.h" +#include "esp_app_format.h" +#include "hal/wdt_hal.h" + +#ifndef CONFIG_SOC_ENABLE_APPCPU +#include "esp_clk_internal.h" +#endif /* CONFIG_SOC_ENABLE_APPCPU */ + +#ifdef CONFIG_MCUBOOT +#include "bootloader_init.h" +#endif /* CONFIG_MCUBOOT */ +#include + +extern void z_cstart(void); +extern void esp_reset_reason_init(void); + +#ifdef CONFIG_SOC_ENABLE_APPCPU +extern const unsigned char esp32_appcpu_fw_array[]; + +void IRAM_ATTR esp_start_appcpu(void) +{ + esp_image_header_t *header = (esp_image_header_t *)&esp32_appcpu_fw_array[0]; + esp_image_segment_header_t *segment = + (esp_image_segment_header_t *)&esp32_appcpu_fw_array[sizeof(esp_image_header_t)]; + uint8_t *segment_payload; + uint32_t entry_addr = header->entry_addr; + uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); + + for (int i = 0; i < header->segment_count; i++) { + segment_payload = (uint8_t *)&esp32_appcpu_fw_array[idx]; + + if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { + /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ + volatile uint32_t *src = (volatile uint32_t *)segment_payload; + volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; + + for (int j = 0; j < segment->data_len / 4; j++) { + dst[j] = src[j]; + } + } else if (segment->load_addr >= SOC_DRAM_LOW && + segment->load_addr < SOC_DRAM_HIGH) { + + memcpy((void *)segment->load_addr, (const void *)segment_payload, + segment->data_len); + } + + idx += segment->data_len; + segment = (esp_image_segment_header_t *)&esp32_appcpu_fw_array[idx]; + idx += sizeof(esp_image_segment_header_t); + } + + esp_appcpu_start((void *)entry_addr); +} +#endif /* CONFIG_SOC_ENABLE_APPCPU */ + +/* + * This is written in C rather than assembly since, during the port bring up, + * Zephyr is being booted by the Espressif bootloader. With it, the C stack + * is already set up. + */ +void __attribute__((section(".iram1"))) __esp_platform_start(void) +{ + extern uint32_t _init_start; + + /* Move the exception vector table to IRAM. */ + __asm__ __volatile__ ( + "wsr %0, vecbase" + : + : "r"(&_init_start)); + + z_bss_zero(); + + __asm__ __volatile__ ( + "" + : + : "g"(&__bss_start) + : "memory"); + + /* Disable normal interrupts. */ + __asm__ __volatile__ ( + "wsr %0, PS" + : + : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); + + /* Initialize the architecture CPU pointer. Some of the + * initialization code wants a valid _current before + * arch_kernel_init() is invoked. + */ + __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + + esp_reset_reason_init(); + +#ifdef CONFIG_MCUBOOT + /* MCUboot early initialisation. */ + if (bootloader_init()) { + abort(); + } +#else + /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check + * on startup sequence related issues in application. Hence disable that + * as we are about to start Zephyr environment. + */ + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; + + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_disable(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + +#ifdef CONFIG_SOC_ESP32_APPCPU + /* Configures the CPU clock, RTC slow and fast clocks, and performs + * RTC slow clock calibration. + */ + esp_clk_init(); +#endif + + esp_timer_early_init(); + +#if CONFIG_SOC_ENABLE_APPCPU + /* start the ESP32 APP CPU */ + esp_start_appcpu(); +#endif + +#if CONFIG_ESP_SPIRAM + esp_err_t err = esp_spiram_init(); + + if (err != ESP_OK) { + printk("Failed to Initialize SPIRAM, aborting.\n"); + abort(); + } + esp_spiram_init_cache(); + if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + printk("SPIRAM size is less than configured size, aborting.\n"); + abort(); + } +#endif + +/* Scheduler is not started at this point. Hence, guard functions + * must be initialized after esp_spiram_init_cache which internally + * uses guard functions. Setting guard functions before SPIRAM + * cache initialization will result in a crash. + */ +#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM + spi_flash_guard_set(&g_flash_guard_default_ops); +#endif + +#endif /* CONFIG_MCUBOOT */ + + esp_intr_initialize(); + + /* Start Zephyr */ + z_cstart(); + + CODE_UNREACHABLE; +} + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int IRAM_ATTR arch_printk_char_out(int c) +{ + if (c == '\n') { + esp_rom_uart_tx_one_char('\r'); + } + esp_rom_uart_tx_one_char(c); + return 0; +} + +void sys_arch_reboot(int type) +{ + esp_restart_noos(); +} + +void IRAM_ATTR esp_restart_noos(void) +{ + /* Disable interrupts */ + z_xt_ints_off(0xFFFFFFFF); + + const uint32_t core_id = cpu_hal_get_core_id(); + const uint32_t other_core_id = (core_id == 0) ? 1 : 0; + + soc_ll_reset_core(other_core_id); + soc_ll_stall_core(other_core_id); + + /* Flush any data left in UART FIFOs */ + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + esp_rom_uart_tx_wait_idle(2); + + /* Disable cache */ + Cache_Read_Disable(0); + Cache_Read_Disable(1); + + /* 2nd stage bootloader reconfigures SPI flash signals. */ + /* Reset them to the defaults expected by ROM */ + WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); + + /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ + DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, + DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | + DPORT_BT_RST | DPORT_BTMAC_RST | + DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | + DPORT_EMAC_RST | DPORT_MACPWR_RST | + DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); + DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); + + /* Reset timer/spi/uart */ + DPORT_SET_PERI_REG_MASK( + DPORT_PERIP_RST_EN_REG, + /* UART TX FIFO cannot be reset correctly on ESP32, */ + /* so reset the UART memory by DPORT here. */ + DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | + DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); + DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); + + /* Clear entry point for APP CPU */ + DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); + + /* Reset CPUs */ + if (core_id == 0) { + /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ + soc_ll_reset_core(1); + soc_ll_reset_core(0); + } else { + /* Running on APP CPU: need to reset PRO CPU and unstall it, */ + /* then reset APP CPU */ + soc_ll_reset_core(0); + soc_ll_stall_core(0); + soc_ll_reset_core(1); + } + + while (true) { + ; + } +} diff --git a/soc/xtensa/espressif_esp32/esp32/soc.h b/soc/espressif/esp32/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/soc.h rename to soc/espressif/esp32/soc.h diff --git a/soc/xtensa/espressif_esp32/esp32/soc_appcpu.c b/soc/espressif/esp32/soc_appcpu.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32/soc_appcpu.c rename to soc/espressif/esp32/soc_appcpu.c diff --git a/soc/espressif/esp32c3/CMakeLists.txt b/soc/espressif/esp32c3/CMakeLists.txt new file mode 100644 index 00000000000000..3ea38bd5287159 --- /dev/null +++ b/soc/espressif/esp32c3/CMakeLists.txt @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + vectors.S + soc_irq.S + soc_irq.c + soc.c + loader.c + ) + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +# get code-partition slot0 address +dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") +dt_reg_addr(img_0_off PATH ${dts_partition_path}) + +# get code-partition boot address +dt_nodelabel(dts_partition_path NODELABEL "boot_partition") +dt_reg_addr(boot_off PATH ${dts_partition_path}) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() + +endif() + +board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + +board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32c3/Kconfig b/soc/espressif/esp32c3/Kconfig new file mode 100644 index 00000000000000..6533ba0b5d606e --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig @@ -0,0 +1,97 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32C3 + select RISCV + select RISCV_GP + select DYNAMIC_INTERRUPTS + select CLOCK_CONTROL + select PINCTRL + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select HAS_ESPRESSIF_HAL + select XIP if !MCUBOOT + select HAS_PM + select HAS_POWEROFF + +if SOC_SERIES_ESP32C3 + +config IDF_TARGET_ESP32C3 + bool "ESP32C3 as target board" + default y + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +choice ESP32C3_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32C3_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + +config ESP32C3_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + +config ESP32C3_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32C3_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config ESP32C3_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + +endchoice # ESP32C3_RTC_CLK_SRC + +config ESP32C3_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +config MAC_BB_PD + bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" + depends on SOC_SERIES_ESP32C3 && TICKLESS_KERNEL + default n + help + If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered + down when PHY is disabled. Enabling this setting reduces power consumption + by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only), + 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth). + +endif # SOC_SERIES_ESP32C3 diff --git a/soc/espressif/esp32c3/Kconfig.defconfig b/soc/espressif/esp32c3/Kconfig.defconfig new file mode 100644 index 00000000000000..ce148c66d4827e --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32C3 + +config NUM_IRQS + default 62 + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +endif # SOC_SERIES_ESP32C3 diff --git a/soc/espressif/esp32c3/Kconfig.soc b/soc/espressif/esp32c3/Kconfig.soc new file mode 100644 index 00000000000000..ec98aaa3d96eef --- /dev/null +++ b/soc/espressif/esp32c3/Kconfig.soc @@ -0,0 +1,51 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32C3 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32C3 + +config SOC_ESP32C3_FX4 + bool + select SOC_ESP32C3 + help + ESP32C3_FX4 + +config SOC_ESP32C3_MINI_N4 + bool + select SOC_ESP32C3 + help + ESP32C3_MINI_N4 + +config SOC_ESP32C3_WROOM_02_N4 + bool + select SOC_ESP32C3 + help + ESP32C3_WROOM_02_N4 + +config SOC_ESP32C3_WROOM_02_N8 + bool + select SOC_ESP32C3 + help + ESP32C3_WROOM_02_N8 + +config SOC_ESP32C3 + bool + select SOC_SERIES_ESP32C3 + help + ESP32C3 + +config SOC_SERIES + default "esp32c3" if SOC_SERIES_ESP32C3 + +config SOC + default "esp32c3" if SOC_SERIES_ESP32C3 + +config SOC_PART_NUMBER + default "ESP32C3_FX4" if SOC_ESP32C3_FX4 + default "ESP32C3_MINI_N4" if SOC_ESP32C3_MINI_N4 + default "ESP32C3_WROOM_02_N4" if SOC_ESP32C3_WROOM_02_N4 + default "ESP32C3_WROOM_02_N8" if SOC_ESP32C3_WROOM_02_N8 + default "ESP32C3" if SOC_ESP32C3 diff --git a/soc/riscv/espressif_esp32/esp32c3/default.ld b/soc/espressif/esp32c3/default.ld similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/default.ld rename to soc/espressif/esp32c3/default.ld diff --git a/soc/riscv/espressif_esp32/esp32c3/loader.c b/soc/espressif/esp32c3/loader.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/loader.c rename to soc/espressif/esp32c3/loader.c diff --git a/soc/riscv/espressif_esp32/esp32c3/mcuboot.ld b/soc/espressif/esp32c3/mcuboot.ld similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/mcuboot.ld rename to soc/espressif/esp32c3/mcuboot.ld diff --git a/soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h b/soc/espressif/esp32c3/pinctrl_soc.h similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/pinctrl_soc.h rename to soc/espressif/esp32c3/pinctrl_soc.h diff --git a/soc/riscv/espressif_esp32/esp32c3/power.c b/soc/espressif/esp32c3/power.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/power.c rename to soc/espressif/esp32c3/power.c diff --git a/soc/riscv/espressif_esp32/esp32c3/poweroff.c b/soc/espressif/esp32c3/poweroff.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/poweroff.c rename to soc/espressif/esp32c3/poweroff.c diff --git a/soc/riscv/espressif_esp32/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc.c rename to soc/espressif/esp32c3/soc.c diff --git a/soc/riscv/espressif_esp32/esp32c3/soc.h b/soc/espressif/esp32c3/soc.h similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc.h rename to soc/espressif/esp32c3/soc.h diff --git a/soc/riscv/espressif_esp32/esp32c3/soc_irq.S b/soc/espressif/esp32c3/soc_irq.S similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc_irq.S rename to soc/espressif/esp32c3/soc_irq.S diff --git a/soc/riscv/espressif_esp32/esp32c3/soc_irq.c b/soc/espressif/esp32c3/soc_irq.c similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/soc_irq.c rename to soc/espressif/esp32c3/soc_irq.c diff --git a/soc/riscv/espressif_esp32/esp32c3/vectors.S b/soc/espressif/esp32c3/vectors.S similarity index 100% rename from soc/riscv/espressif_esp32/esp32c3/vectors.S rename to soc/espressif/esp32c3/vectors.S diff --git a/soc/espressif/esp32s2/CMakeLists.txt b/soc/espressif/esp32s2/CMakeLists.txt new file mode 100644 index 00000000000000..1c840ce22896c5 --- /dev/null +++ b/soc/espressif/esp32s2/CMakeLists.txt @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + soc_cache.c + loader.c + ) + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +# get code-partition slot0 address +dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") +dt_reg_addr(img_0_off PATH ${dts_partition_path}) + +# get code-partition boot address +dt_nodelabel(dts_partition_path NODELABEL "boot_partition") +dt_reg_addr(boot_off PATH ${dts_partition_path}) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() + +endif() + +board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + +board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32s2/Kconfig b/soc/espressif/esp32s2/Kconfig new file mode 100644 index 00000000000000..1c657c4e1b54a9 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig @@ -0,0 +1,228 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S2 + select XTENSA + select ATOMIC_OPERATIONS_C + select DYNAMIC_INTERRUPTS + select CLOCK_CONTROL + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select ARCH_SUPPORTS_COREDUMP + select HAS_PM + select HAS_POWEROFF + +if SOC_SERIES_ESP32S2 + +config IDF_TARGET_ESP32S2 + bool "ESP32S2 as target SOC" + default y + +config ESP_SYSTEM_RTC_EXT_XTAL + bool + +config ESP_SYSTEM_RTC_EXT_OSC + bool + +choice ESP32S2_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32S2_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 90kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 90kHz oscillator. It does not require external components. + +config ESP32S2_RTC_CLK_SRC_INT_RC + bool "Internal 90kHz RC oscillator" + +config ESP32S2_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32S2_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config ESP32S2_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + +endchoice + +config ESP32S2_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 + default 576 if ESP32S2_RTC_CLK_SRC_INT_RC + range 0 125000 + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +menu "Cache config" + +choice + prompt "Instruction cache line size" + default ESP32S2_INSTRUCTION_CACHE_LINE_32B + + config ESP32S2_INSTRUCTION_CACHE_LINE_16B + bool "16 Bytes" + + config ESP32S2_INSTRUCTION_CACHE_LINE_32B + bool "32 Bytes" + +endchoice + +choice + prompt "Instruction cache size" + default ESP32S2_INSTRUCTION_CACHE_8KB + + config ESP32S2_INSTRUCTION_CACHE_8KB + bool "8KB instruction cache size" + + config ESP32S2_INSTRUCTION_CACHE_16KB + bool "16KB instruction cache size" + +endchoice + +choice + prompt "Data cache size" + default ESP32S2_DATA_CACHE_0KB if !ESP_SPIRAM + default ESP32S2_DATA_CACHE_8KB if ESP_SPIRAM + + config ESP32S2_DATA_CACHE_0KB + bool "0KB data cache size" + + config ESP32S2_DATA_CACHE_8KB + bool "8KB data cache size" + + config ESP32S2_DATA_CACHE_16KB + bool "16KB data cache size" + +endchoice + +choice + prompt "Data cache line size" + default ESP32S2_DATA_CACHE_LINE_32B + + config ESP32S2_DATA_CACHE_LINE_16B + bool "16 Bytes" + + config ESP32S2_DATA_CACHE_LINE_32B + bool "32 Bytes" + +endchoice + +config ESP32S2_INSTRUCTION_CACHE_SIZE + hex + default 0x4000 if ESP32S2_INSTRUCTION_CACHE_16KB + default 0x2000 + +config ESP32S2_DATA_CACHE_SIZE + hex + default 0x2000 if ESP32S2_DATA_CACHE_8KB + default 0x4000 if ESP32S2_DATA_CACHE_16KB + default 0x0000 + +endmenu # Cache config + +menu "PSRAM clock and cs IO for ESP32-S2" + depends on ESP_SPIRAM + +config DEFAULT_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 30 + help + The PSRAM CLOCK IO can be any unused GPIO, user can config + it based on hardware design. + +config DEFAULT_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 26 + help + The PSRAM CS IO can be any unused GPIO, user can config it + based on hardware design. + +endmenu # PSRAM clock and cs IO for ESP32S2 + +choice ESP32S2_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is two, + all interfaces (WiFi station, WiFi softap) receive a universally administered MAC + address. + They are generated sequentially by adding 0, and 1 (respectively) to the final octet of + the base MAC address. If the number of universal MAC addresses is one, only WiFi station + receives a universally administered MAC address. + The WiFi softap receives local MAC addresses. It's derived from the universal WiFi + station MAC addresses. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 1 or 2 per device). + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + bool "One" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + +endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES + int + default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig b/soc/espressif/esp32s2/Kconfig.defconfig new file mode 100644 index 00000000000000..6daf53e76dfe44 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig.series b/soc/espressif/esp32s2/Kconfig.defconfig.series new file mode 100644 index 00000000000000..50ddbd72704e49 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.defconfig.series @@ -0,0 +1,27 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config MP_MAX_NUM_CPUS + default 1 + +config ISR_STACK_SIZE + default 2048 + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.soc b/soc/espressif/esp32s2/Kconfig.soc new file mode 100644 index 00000000000000..17b801087f94b5 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.soc @@ -0,0 +1,126 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S2 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32-S2 Series + +config SOC_ESP32S2_R2 + bool + select SOC_ESP32S2 + help + ESP32S2_R2 + +config SOC_ESP32S2_FH2 + bool + select SOC_ESP32S2 + help + ESP32S2_FH2 + +config SOC_ESP32S2_FH4 + bool + select SOC_ESP32S2 + help + ESP32S2_FH4 + +config SOC_ESP32S2_FN4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_FN4R2 + +# SiP with external flash / psram +config SOC_ESP32S2_SOLO_N4 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N4 + +config SOC_ESP32S2_SOLO_N8 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N8 + +config SOC_ESP32S2_SOLO_N16 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N16 + +config SOC_ESP32S2_SOLO_N4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_SOLO_N4R2 + +config SOC_ESP32S2_MINI_N4 + bool + select SOC_ESP32S2 + help + ESP32S2_MINI_N4 + +config SOC_ESP32S2_MINI_N4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_MINI_N4R2 + +config SOC_ESP32S2_WROOM + bool + select SOC_ESP32S2 + help + ESP32S2_WROOM + +config SOC_ESP32S2_WROVER_N4R2 + bool + select SOC_ESP32S2 + help + ESP32S2_WROVER_N4R2 + +config SOC_ESP32S2_WROVER_N8R2 + bool + select SOC_ESP32S2 + help + ESP32S2_WROVER_N8R2 + +config SOC_ESP32S2_WROVER_N16R2 + bool + select SOC_ESP32S2 + help + ESP32S2_WROVER_N16R2 + +config SOC_ESP32S2 + bool + select SOC_SERIES_ESP32S2 + help + ESP32S2 + +config SOC_SERIES + default "esp32s2" if SOC_SERIES_ESP32S2 + +config SOC + default "esp32s2" if SOC_SERIES_ESP32S2 + +config SOC_PART_NUMBER + default "ESP32S2" if SOC_ESP32S2 + default "ESP32S2_R2" if SOC_ESP32S2_R2 + default "ESP32S2_FH2" if SOC_ESP32S2_FH2 + default "ESP32S2_FH4" if SOC_ESP32S2_FH4 + default "ESP32S2_FN4R2" if SOC_ESP32S2_FN4R2 + default "ESP32S2_SOLO_N4" if SOC_ESP32S2_SOLO_N4 + default "ESP32S2_SOLO_N8" if SOC_ESP32S2_SOLO_N8 + default "ESP32S2_SOLO_N16" if SOC_ESP32S2_SOLO_N16 + default "ESP32S2_SOLO_N4R2" if SOC_ESP32S2_SOLO_N4R2 + default "ESP32S2_MINI_N4" if SOC_ESP32S2_MINI_N4 + default "ESP32S2_MINI_N4R2" if SOC_ESP32S2_MINI_N4R2 + default "ESP32S2_WROOM" if SOC_ESP32S2_WROOM + default "ESP32S2_WROVER_N4R2" if SOC_ESP32S2_WROVER_N4R2 + default "ESP32S2_WROVER_N8R2" if SOC_ESP32S2_WROVER_N8R2 + default "ESP32S2_WROVER_N16R2" if SOC_ESP32S2_WROVER_N16R2 + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32s2" if SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/espressif_esp32/esp32s2/default.ld b/soc/espressif/esp32s2/default.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/default.ld rename to soc/espressif/esp32s2/default.ld diff --git a/soc/xtensa/espressif_esp32/esp32s2/loader.c b/soc/espressif/esp32s2/loader.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/loader.c rename to soc/espressif/esp32s2/loader.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld b/soc/espressif/esp32s2/mcuboot.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/mcuboot.ld rename to soc/espressif/esp32s2/mcuboot.ld diff --git a/soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c b/soc/espressif/esp32s2/newlib_fix.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/newlib_fix.c rename to soc/espressif/esp32s2/newlib_fix.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h b/soc/espressif/esp32s2/pinctrl_soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/pinctrl_soc.h rename to soc/espressif/esp32s2/pinctrl_soc.h diff --git a/soc/xtensa/espressif_esp32/esp32s2/power.c b/soc/espressif/esp32s2/power.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/power.c rename to soc/espressif/esp32s2/power.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/poweroff.c b/soc/espressif/esp32s2/poweroff.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/poweroff.c rename to soc/espressif/esp32s2/poweroff.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/soc.c rename to soc/espressif/esp32s2/soc.c diff --git a/soc/xtensa/espressif_esp32/esp32s2/soc.h b/soc/espressif/esp32s2/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/soc.h rename to soc/espressif/esp32s2/soc.h diff --git a/soc/xtensa/espressif_esp32/esp32s2/soc_cache.c b/soc/espressif/esp32s2/soc_cache.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s2/soc_cache.c rename to soc/espressif/esp32s2/soc_cache.c diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt new file mode 100644 index 00000000000000..75b9f0a3d7e41a --- /dev/null +++ b/soc/espressif/esp32s3/CMakeLists.txt @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_ESP32S3_APPCPU) + zephyr_sources(soc_appcpu.c) +else() + zephyr_sources( + soc.c + soc_cache.c + loader.c + esp32s3-mp.c + ) +endif() + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) + +# get flash size to use in esptool as string +math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") + +if(CONFIG_BOOTLOADER_ESP_IDF) + include(ExternalProject) + + ## we use hello-world project, but I think any can be used. + set(espidf_components_dir ${ESP_IDF_PATH}/components) + set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) + set(espidf_build_dir ${espidf_prefix}/build) + + ExternalProject_Add( + EspIdfBootloader + PREFIX ${espidf_prefix} + SOURCE_DIR ${espidf_components_dir}/bootloader/subproject + BINARY_DIR ${espidf_build_dir}/bootloader + CONFIGURE_COMMAND + ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} + -S ${espidf_components_dir}/bootloader/subproject + -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig + -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} + -DPYTHON_DEPS_CHECKED=1 + -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} + -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} + -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} + -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} + -DPYTHON=${PYTHON_EXECUTABLE} + BUILD_COMMAND + ${CMAKE_COMMAND} --build . + INSTALL_COMMAND "" # This particular build system has no install command + ) + + ExternalProject_Add( + EspPartitionTable + SOURCE_DIR ${espidf_components_dir}/partition_table + BINARY_DIR ${espidf_build_dir} + CONFIGURE_COMMAND "" + BUILD_COMMAND + ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q + --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin + INSTALL_COMMAND "" + ) + + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + add_dependencies(app EspIdfBootloader EspPartitionTable) + + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") + + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + + board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") + +endif() + +if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) + endif() + + if(CONFIG_MCUBOOT) + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") + endif() +endif() + +## When building for APPCPU +if(CONFIG_SOC_ESP32S3_APPCPU) + if(CONFIG_BUILD_OUTPUT_BIN) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py + ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin + -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c + -a "esp32s3_appcpu_fw_array") + endif() +else() + set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) + + # get code-partition slot0 address + dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") + dt_reg_addr(img_0_off PATH ${dts_partition_path}) + + # get code-partition boot address + dt_nodelabel(dts_partition_path NODELABEL "boot_partition") + dt_reg_addr(boot_off PATH ${dts_partition_path}) + + board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") + + board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") +endif() + +if(CONFIG_MCUBOOT) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_ESP32S3_APPCPU) + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") +else() + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") +endif() diff --git a/soc/espressif/esp32s3/Kconfig b/soc/espressif/esp32s3/Kconfig new file mode 100644 index 00000000000000..70fcfbb914458a --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig @@ -0,0 +1,313 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S3 + select XTENSA + select DYNAMIC_INTERRUPTS + select ARCH_SUPPORTS_COREDUMP + select CLOCK_CONTROL + select PINCTRL + select XIP if !MCUBOOT + select HAS_ESPRESSIF_HAL + select CPU_HAS_FPU + +if SOC_SERIES_ESP32S3 + +config IDF_TARGET_ESP32S3 + bool "ESP32S3 as target SOC" + default y + +config ESP32S3_APPCPU_IRAM + hex "ESP32S3 APPCPU IRAM size" + depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU + default 0x20000 + help + Defines APPCPU IRAM area in bytes. + +config ESP32S3_APPCPU_DRAM + hex "ESP32S3 APPCPU DRAM size" + depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU + default 0x10000 + help + Defines APPCPU DRAM area in bytes. + +config SOC_ESP32S3_PROCPU + bool + help + This hidden configuration defines that build is targeted for PROCPU (core 0). + +config SOC_ESP32S3_APPCPU + bool + help + This hidden configuration defines that build is targeted for APPCPU (core 1). + +config SOC_ENABLE_APPCPU + bool + default y + depends on IPM && SOC_ESP32S3_PROCPU + help + This hidden configuration lets PROCPU core to map and start APPCPU whenever IPM is enabled. + +choice ESP32S3_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32S3_RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + config ESP32S3_RTC_CLK_SRC_INT_RC + bool "Internal 150kHz RC oscillator" + config ESP32S3_RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + config ESP32S3_RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XP pin" + select ESP_SYSTEM_RTC_EXT_OSC + config ESP32S3_RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" +endchoice + +config ESP32S3_RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 + default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC + range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 + range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +choice ESP32_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is four, + all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally + administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) + to the final octet of the base MAC address. If the number of universal MAC addresses is two, + only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. + These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. + The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. + These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 2 or 4 per device.) + +config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_BT + +config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + bool "Four" + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + select ESP_MAC_ADDR_UNIVERSE_BT + select ESP_MAC_ADDR_UNIVERSE_ETH + +endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES + +config ESP_MAC_ADDR_UNIVERSE_WIFI_AP + bool + +config ESP_MAC_ADDR_UNIVERSE_WIFI_STA + bool + +config ESP_MAC_ADDR_UNIVERSE_BT + bool + +config ESP_MAC_ADDR_UNIVERSE_ETH + bool + +config ESP32_UNIVERSAL_MAC_ADDRESSES + int + default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO + default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR + +config ESP32_PHY_MAX_WIFI_TX_POWER + int "Max WiFi/BLE TX power (dBm)" + range 10 20 + default 20 + help + Set maximum transmit power for WiFi radio. Actual transmit power for high + data rates may be lower than this setting. + +config ESP32_PHY_MAX_TX_POWER + int + default ESP32_PHY_MAX_WIFI_TX_POWER + +menu "Cache config" + +choice ESP32S3_INSTRUCTION_CACHE_SIZE + prompt "Instruction cache size" + default ESP32S3_INSTRUCTION_CACHE_16KB + help + Instruction cache size to be set on application startup. + If you use 16KB instruction cache rather than 32KB instruction cache, + then the other 16KB will be managed by heap allocator. + + config ESP32S3_INSTRUCTION_CACHE_16KB + bool "16KB" + config ESP32S3_INSTRUCTION_CACHE_32KB + bool "32KB" +endchoice + +config ESP32S3_INSTRUCTION_CACHE_SIZE + hex + default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB + default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB + +choice ESP32S3_ICACHE_ASSOCIATED_WAYS + prompt "Instruction cache associated ways" + default ESP32S3_INSTRUCTION_CACHE_8WAYS + help + Instruction cache associated ways to be set on application startup. + + config ESP32S3_INSTRUCTION_CACHE_4WAYS + bool "4 ways" + config ESP32S3_INSTRUCTION_CACHE_8WAYS + bool "8 ways" +endchoice + +config ESP32S3_ICACHE_ASSOCIATED_WAYS + int + default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS + default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS + +choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE + prompt "Instruction cache line size" + default ESP32S3_INSTRUCTION_CACHE_LINE_32B + help + Instruction cache line size to be set on application startup. + + config ESP32S3_INSTRUCTION_CACHE_LINE_16B + bool "16 Bytes" + depends on ESP32S3_INSTRUCTION_CACHE_16KB + config ESP32S3_INSTRUCTION_CACHE_LINE_32B + bool "32 Bytes" +endchoice + +config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE + int + default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B + default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B + +config ESP32S3_INSTRUCTION_CACHE_WRAP + bool "Define instruction cache wrap mode" + help + If enabled, instruction cache will use wrap mode to read spi flash or spi ram. + The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE. + However, it depends on complex conditions. + +choice ESP32S3_DATA_CACHE_SIZE + prompt "Data cache size" + default ESP32S3_DATA_CACHE_32KB + help + Data cache size to be set on application startup. + If you use 32KB data cache rather than 64KB data cache, + the other 32KB will be added to the heap. + + config ESP32S3_DATA_CACHE_16KB + bool "16KB" + config ESP32S3_DATA_CACHE_32KB + bool "32KB" + config ESP32S3_DATA_CACHE_64KB + bool "64KB" +endchoice + +config ESP32S3_DATA_CACHE_SIZE + hex + # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup + default 0x8000 if ESP32S3_DATA_CACHE_16KB + default 0x8000 if ESP32S3_DATA_CACHE_32KB + default 0x10000 if ESP32S3_DATA_CACHE_64KB + +choice ESP32S3_DCACHE_ASSOCIATED_WAYS + prompt "Data cache associated ways" + default ESP32S3_DATA_CACHE_8WAYS + help + Data cache associated ways to be set on application startup. + + config ESP32S3_DATA_CACHE_4WAYS + bool "4 ways" + config ESP32S3_DATA_CACHE_8WAYS + bool "8 ways" +endchoice + +config ESP32S3_DCACHE_ASSOCIATED_WAYS + int + default 4 if ESP32S3_DATA_CACHE_4WAYS + default 8 if ESP32S3_DATA_CACHE_8WAYS + +choice ESP32S3_DATA_CACHE_LINE_SIZE + prompt "Data cache line size" + default ESP32S3_DATA_CACHE_LINE_32B + help + Data cache line size to be set on application startup. + + config ESP32S3_DATA_CACHE_LINE_16B + bool "16 Bytes" + depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB + config ESP32S3_DATA_CACHE_LINE_32B + bool "32 Bytes" + config ESP32S3_DATA_CACHE_LINE_64B + bool "64 Bytes" +endchoice + +config ESP32S3_DATA_CACHE_LINE_SIZE + int + default 16 if ESP32S3_DATA_CACHE_LINE_16B + default 32 if ESP32S3_DATA_CACHE_LINE_32B + default 64 if ESP32S3_DATA_CACHE_LINE_64B + +config ESP32S3_DATA_CACHE_WRAP + bool "Define data cache wrap mode" + help + If enabled, data cache will use wrap mode to read spi flash or spi ram. + The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE. + However, it depends on complex conditions. + +config MAC_BB_PD + bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" + depends on SOC_SERIES_ESP32S3 && TICKLESS_KERNEL + default n + help + If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered + down when PHY is disabled. Enabling this setting reduces power consumption + by a small amount but increases RAM use by approximat + +endmenu # Cache config + +menu "PSRAM Clock and CS IO for ESP32S3" + depends on ESP_SPIRAM + +config DEFAULT_PSRAM_CLK_IO + int "PSRAM CLK IO number" + range 0 33 + default 30 + help + The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. + +config DEFAULT_PSRAM_CS_IO + int "PSRAM CS IO number" + range 0 33 + default 26 + help + The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. + +endmenu # PSRAM clock and cs IO for ESP32S3 + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.defconfig b/soc/espressif/esp32s3/Kconfig.defconfig new file mode 100644 index 00000000000000..07f719a0bccd29 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S3 + +config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE + default n + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config ESPTOOLPY_FLASHFREQ_80M + default y + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) + +endif # SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/Kconfig.soc b/soc/espressif/esp32s3/Kconfig.soc new file mode 100644 index 00000000000000..6c0c1896c370e3 --- /dev/null +++ b/soc/espressif/esp32s3/Kconfig.soc @@ -0,0 +1,146 @@ +# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ESP32S3 + bool + select SOC_FAMILY_ESPRESSIF_ESP32 + help + ESP32-S3 Series + +config SOC_ESP32S3_R2 + bool + select SOC_ESP32S3 + help + ESP32S3_R2 + +config SOC_ESP32S3_R8 + bool + select SOC_ESP32S3 + help + ESP32S3_R8 + +config SOC_ESP32S3_R8V + bool + select SOC_ESP32S3 + help + ESP32S3_R8V + +config SOC_ESP32S3_FN8 + bool + select SOC_ESP32S3 + help + ESP32S3_FN8 + +config SOC_ESP32S3_PICO_N8R2 + bool + select SOC_ESP32S3 + help + ESP32S3_PICO_N8R2 + +config SOC_ESP32S3_PICO_N8R8 + bool + select SOC_ESP32S3 + help + ESP32S3_PICO_N8R8 + +# SiP with flash and/or psram +config SOC_ESP32S3_MINI_N8 + bool + select SOC_ESP32S3 + help + ESP32S3_MINI_N8 + +config SOC_ESP32S3_MINI_N4R2 + bool + select SOC_ESP32S3 + help + ESP32S3_MINI_N4R2 + +config SOC_ESP32S3_WROOM_N4 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N4 + +config SOC_ESP32S3_WROOM_N8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N8 + +config SOC_ESP32S3_WROOM_N16 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N16 + +config SOC_ESP32S3_WROOM_N4R8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N4R8 + +config SOC_ESP32S3_WROOM_N8R8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N8R8 + +config SOC_ESP32S3_WROOM_N16R8 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N16R8 + +config SOC_ESP32S3_WROOM_N4R2 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N4R2 + +config SOC_ESP32S3_WROOM_N8R2 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N8R2 + +config SOC_ESP32S3_WROOM_N16R2 + bool + select SOC_ESP32S3 + help + ESP32S3_WROOM_N16R2 + +config SOC_ESP32S3 + bool + select SOC_SERIES_ESP32S3 + help + ESP32S3 + +config SOC_SERIES + default "esp32s3" if SOC_SERIES_ESP32S3 + +config SOC + default "esp32s3" if SOC_SERIES_ESP32S3 + +config SOC_PART_NUMBER + default "ESP32S3_R2" if SOC_ESP32S3_R2 + default "ESP32S3_R8" if SOC_ESP32S3_R8 + default "ESP32S3_R8V" if SOC_ESP32S3_R8V + default "ESP32S3_FN8" if SOC_ESP32S3_FN8 + default "ESP32S3_PICO_N8R2" if SOC_ESP32S3_PICO_N8R2 + default "ESP32S3_PICO_N8R8" if SOC_ESP32S3_PICO_N8R8 + default "ESP32S3_MINI_N8" if SOC_ESP32S3_MINI_N8 + default "ESP32S3_MINI_N4R2" if SOC_ESP32S3_MINI_N4R2 + default "ESP32S3_WROOM_N4" if SOC_ESP32S3_WROOM_N4 + default "ESP32S3_WROOM_N8" if SOC_ESP32S3_WROOM_N8 + default "ESP32S3_WROOM_N16" if SOC_ESP32S3_WROOM_N16 + default "ESP32S3_WROOM_N4R8" if SOC_ESP32S3_WROOM_N4R8 + default "ESP32S3_WROOM_N8R8" if SOC_ESP32S3_WROOM_N8R8 + default "ESP32S3_WROOM_N16R8" if SOC_ESP32S3_WROOM_N16R8 + default "ESP32S3_WROOM_N4R2" if SOC_ESP32S3_WROOM_N4R2 + default "ESP32S3_WROOM_N8R2" if SOC_ESP32S3_WROOM_N8R2 + default "ESP32S3_WROOM_N16R2" if SOC_ESP32S3_WROOM_N16R2 + +config SOC_TOOLCHAIN_NAME + string + default "espressif_esp32s3" if SOC_SERIES_ESP32S3 diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld new file mode 100644 index 00000000000000..7c8aff31767f62 --- /dev/null +++ b/soc/espressif/esp32s3/default.ld @@ -0,0 +1,693 @@ +/* + * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the ESP32S3 platform. + */ + +#include +#include +#include +#include + +#define SRAM_IRAM_START 0x40370000 +#define SRAM_DIRAM_I_START 0x40378000 +/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg + start address (that should not be overlapped) */ +#define SRAM_IRAM_END 0x403BA000 +#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) + +#define SRAM_DRAM_START 0x3FC88000 +#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) +#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START) + +#define ICACHE_SIZE 0x8000 +#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) +#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) + +#define DCACHE_SIZE 0x10000 +#define SRAM_DRAM_ORG (SRAM_DRAM_START) + +#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE + +#define FLASH_CODE_REGION irom0_0_seg +#define RODATA_REGION drom0_0_seg +#define IRAM_REGION iram0_0_seg +#define RAMABLE_REGION dram0_0_seg +#define ROMABLE_REGION ROM + +#define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE) + +#ifdef CONFIG_FLASH_SIZE +#define FLASH_SIZE CONFIG_FLASH_SIZE +#else +#define FLASH_SIZE 0x800000 +#endif + +#ifdef CONFIG_BOOTLOADER_ESP_IDF +#define IROM_SEG_ORG 0x42000020 +#define IROM_SEG_LEN FLASH_SIZE-0x20 +#else +#define IROM_SEG_ORG 0x42000000 +#define IROM_SEG_LEN FLASH_SIZE +#endif + +#ifdef CONFIG_SOC_ENABLE_APPCPU +#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM +#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM +#else +#define APPCPU_IRAM_SIZE 0x0 +#define APPCPU_DRAM_SIZE 0x0 +#endif + +#define IROM_SEG_ALIGN 0x10000 + +/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. + * Executing directly from LMA is not possible. */ +#undef GROUP_ROM_LINK_IN +#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion + +MEMORY +{ + mcuboot_hdr (RX): org = 0x0, len = 0x20 + metadata (RX): org = 0x20, len = 0x20 + ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 + iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE + dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE + + irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN + + /* DROM is the first segment placed in generated binary. + * MCUboot binary for ESP32 has image header of 0x20 bytes. + * Additional load header of 0x20 bytes are appended to the image. + * Hence, an offset of 0x40 is added to DROM segment origin. + */ + drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 + /** + * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region. + * so we allocate `extern_ram_seg` at the end of the address region. + */ +#if defined(CONFIG_ESP_SPIRAM) + ext_ram_seg(RWX): org = EXT_RAM_ORG, len = CONFIG_ESP_SPIRAM_SIZE +#endif + + /* RTC fast memory (executable). Persists over deep sleep. + */ + rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 + + /* RTC fast memory (same block as above), viewed from data bus + */ + rtc_data_seg(RW): org = 0x600fe000, len = 0x2000 + + /* RTC slow memory (data accessible). Persists over deep sleep. + */ + rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 + +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 +#endif +} + +/* Default entry point: */ +ENTRY(CONFIG_KERNEL_ENTRY) + +SECTIONS +{ + /* Reserve space for MCUboot header in the binary */ + .mcuboot_header : + { + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + QUAD(0x0) + } > mcuboot_hdr + .metadata : + { + /* Magic byte for load header */ + LONG(0xace637d3) + + /* Application entry point address */ + KEEP(*(.entry_addr)) + + /* IRAM metadata: + * - Destination address (VMA) for IRAM region + * - Flash offset (LMA) for start of IRAM region + * - Size of IRAM region + */ + LONG(ADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.vectors)) + LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) + + /* DRAM metadata: + * - Destination address (VMA) for DRAM region + * - Flash offset (LMA) for start of DRAM region + * - Size of DRAM region + */ + LONG(ADDR(.dram0.data)) + LONG(LOADADDR(.dram0.data)) + LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) + } > metadata + + #include + + _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); + _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; + _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); + + /* NOTE: .rodata section should be the first section in the linker script and no + * other section should appear before .rodata section. This is the requirement + * to align ROM section to 64K page offset. + * Adding .rodata as first section helps to reduce size of generated binary by + * few kBs. + */ + SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) + { + _rodata_reserved_start = ABSOLUTE(.); + _rodata_start = ABSOLUTE(.); + + *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ + *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ + + __rodata_region_start = ABSOLUTE(.); + . = ALIGN(4); + #include + + . = ALIGN(4); + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata) + *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ exception handlers table: */ + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + __rodata_region_end = ABSOLUTE(.); + /* Literals are also RO data. */ + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + *(.rodata_wlog) + *(.rodata_wlog*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + #include + #include + #include + #include + + /* Create an explicit section at the end of all the data that shall be mapped into drom. + * This is used to calculate the size of the _image_drom_size variable */ + SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) + { + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN(16); + _image_rodata_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + +#if defined(CONFIG_ESP_SPIRAM) + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : + { + _ext_ram_data_start = ABSOLUTE(.); + _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + . = ALIGN(4); + _ext_ram_bss_end = ABSOLUTE(.); + } > ext_ram_seg + + .ext_ram_noinit (NOLOAD) : + { +#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) + *libdrivers__wifi.a:(.noinit .noinit.*) + *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) + *libsubsys__net__lib__config.a:(.noinit .noinit.*) + *libsubsys__net__ip.a:(.noinit .noinit.*) + *libsubsys__net.a:(.noinit .noinit.*) +#endif + _spiram_heap_start = ABSOLUTE(.); + . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; + + _ext_ram_data_end = ABSOLUTE(.); + } > ext_ram_seg +#endif + + /* Send .iram0 code to iram */ + .iram0.vectors : ALIGN(4) + { + _iram_start = ABSOLUTE(.); + /* Vectors go to IRAM */ + _init_start = ABSOLUTE(.); + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + . = 0x0; + KEEP(*(.WindowVectors.text)); + . = 0x180; + KEEP(*(.Level2InterruptVector.text)); + . = 0x1c0; + KEEP(*(.Level3InterruptVector.text)); + . = 0x200; + KEEP(*(.Level4InterruptVector.text)); + . = 0x240; + KEEP(*(.Level5InterruptVector.text)); + . = 0x280; + KEEP(*(.DebugExceptionVector.text)); + . = 0x2c0; + KEEP(*(.NMIExceptionVector.text)); + . = 0x300; + KEEP(*(.KernelExceptionVector.text)); + . = 0x340; + KEEP(*(.UserExceptionVector.text)); + . = 0x3C0; + KEEP(*(.DoubleExceptionVector.text)); + . = 0x400; + _invalid_pc_placeholder = ABSOLUTE(.); + *(.*Vector.literal) + + *(.UserEnter.literal); + *(.UserEnter.text); + . = ALIGN (16); + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.text : ALIGN(4) + { + /* Code marked as running out of IRAM */ + _iram_text_start = ABSOLUTE(.); + *(.iram1 .iram1.*) + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + *libesp32.a:panic.*(.literal .text .literal.* .text.*) + *librtc.a:(.literal .text .literal.* .text.*) + *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) + *libkernel.a:(.literal .text .literal.* .text.*) + *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) + *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) + *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) + *libzephyr.a:spiram*.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_timing*.*(.literal .text .literal.* .text.*) + *libzephyr.a:spi_flash*.*(.literal .text .literal.* .text.*) + *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) + *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) + *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) + *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) + *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) + *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) + *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) + *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) + *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) + *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:loader.*(.literal .text .literal.* .text.*) + *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) + *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) + *libc.a:*(.literal .text .literal.* .text.*) + *libphy.a:(.phyiram .phyiram.*) + *libgcov.a:(.literal .text .literal.* .text.*) + +#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + . = ALIGN(4) + 16; + + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + /* Marks the end of IRAM code segment */ + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU + * prefetch and 256B alignment for PMS split lines */ + . = ALIGN(16); + _iram_text_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } GROUP_LINK_IN(IRAM_REGION) + + + /* This section is required to skip .iram0.text area because iram0_0_seg and + * dram0_0_seg reflect the same address space on different buses. + */ + .dram0.dummy (NOLOAD): + { + . = ALIGN (8); + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; + } GROUP_LINK_IN(RAMABLE_REGION) + + /* Shared RAM */ + SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); /* required by bluetooth library */ + __bss_start = ABSOLUTE(.); + + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + __bss_end = ABSOLUTE(.); + } GROUP_LINK_IN(RAMABLE_REGION) + + ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") + + SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) + { + . = ALIGN(8); + *(.noinit) + *(.noinit.*) + . = ALIGN(8) ; + } GROUP_LINK_IN(RAMABLE_REGION) + + .dram0.data : + { + . = ALIGN (8); + __data_start = ABSOLUTE(.); + + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + /* rodata for panic handler(libarch__xtensa__core.a) and all + * dependent functions should be placed in DRAM to avoid issue + * when flash cache is disabled */ + *libarch__xtensa__core.a:(.rodata .rodata.*) + *libkernel.a:fatal.*(.rodata .rodata.*) + *libkernel.a:init.*(.rodata .rodata.*) + *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.*) + *libzephyr.a:log_core.*(.rodata .rodata.*) + *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) + *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:loader.*(.rodata .rodata.*) + *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + + KEEP(*(.jcr)) + *(.dram1 .dram1.*) + . = ALIGN(4); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + #include + #include + #include + #include + #include + + /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ + #pragma push_macro("GROUP_ROM_LINK_IN") + #undef GROUP_ROM_LINK_IN + #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN + #include + #pragma pop_macro("GROUP_ROM_LINK_IN") + + .dram0.end : + { + . = ALIGN(4); + + #include + + . = ALIGN(4); + _end = ABSOLUTE(.); + __data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) + + _image_irom_start = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; + _image_irom_vaddr = ADDR(.flash.text); + + .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) + { + . = SIZEOF(_RODATA_SECTION_NAME); + . = ALIGN(IROM_SEG_ALIGN) + 0x20; + } GROUP_LINK_IN(FLASH_CODE_REGION) + + .flash.text : ALIGN(IROM_SEG_ALIGN) + { + _stext = .; + _text_start = ABSOLUTE(.); + +#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) + *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) + *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) +#endif + +#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) + *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) + *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) +#endif + + *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + *(.literal .text .literal.* .text.*) + + /* CPU will try to prefetch up to 16 bytes of + * of instructions. This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + . += 16; + + _text_end = ABSOLUTE(.); + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + _flash_cache_start = ABSOLUTE(0); + } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) + + /* RTC fast memory holds RTC wake stub code, + * including from any source file named rtc_wake_stub*.c + */ + .rtc.text : + { + . = ALIGN(4); + _rtc_text_start = ABSOLUTE(.); + *(.rtc.literal .rtc.text) + *(.rtc.entry.text) + *rtc_wake_stub*.*(.literal .text .literal.* .text.*) + _rtc_text_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) + + /* This section is required to skip rtc.text area because rtc_iram_seg and + * rtc_data_seg are reflect the same address space on different buses. + */ + .rtc.dummy : + { + _rtc_dummy_start = ABSOLUTE(.); + _rtc_fast_start = ABSOLUTE(.); + . = SIZEOF(.rtc.text); + _rtc_dummy_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + + /* This section located in RTC FAST Memory area. + * It holds data marked with RTC_FAST_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_fast : + { + . = ALIGN(4); + _rtc_force_fast_start = ABSOLUTE(.); + + *(.rtc.force_fast .rtc.force_fast.*) + . = ALIGN(4) ; + _rtc_force_fast_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) + + /* RTC data section holds RTC wake stub + * data/rodata, including from any source file + * named rtc_wake_stub*.c and the data marked with + * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. + */ + .rtc.data : + { + _rtc_data_start = ABSOLUTE(.); + *(.rtc.data) + *(.rtc.rodata) + *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) + _rtc_data_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + *(.rtc.data) + *(.rtc.rodata) + + _rtc_bss_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* RTC bss, from any source file named rtc_wake_stub*.c */ + .rtc.bss (NOLOAD) : + { + _rtc_bss_start = ABSOLUTE(.); + *rtc_wake_stub*.*(.bss .bss.*) + *rtc_wake_stub*.*(COMMON) + + _rtc_bss_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* This section holds data that should not be initialized at power up + * and will be retained during deep sleep. + * User data marked with RTC_NOINIT_ATTR will be placed + * into this section. See the file "esp_attr.h" for more information. + */ + .rtc_noinit (NOLOAD): + { + . = ALIGN(4); + _rtc_noinit_start = ABSOLUTE(.); + *(.rtc_noinit .rtc_noinit.*) + . = ALIGN(4) ; + _rtc_noinit_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* This section located in RTC SLOW Memory area. + * It holds data marked with RTC_SLOW_ATTR attribute. + * See the file "esp_attr.h" for more information. + */ + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4) ; + _rtc_force_slow_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) + + /* Get size of rtc slow data based on rtc_data_location alias */ + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); + _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); + + ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") + ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") + +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + +_heap_sentry = 0x3fceb910; + +#include + + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } + +} + +ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), + "IRAM0 segment data does not fit.") + +#if defined(CONFIG_ESP_SPIRAM) +ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), + "External SPIRAM overflowed.") +#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32s3/default_appcpu.ld b/soc/espressif/esp32s3/default_appcpu.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/default_appcpu.ld rename to soc/espressif/esp32s3/default_appcpu.ld diff --git a/soc/xtensa/espressif_esp32/esp32s3/esp32s3-mp.c b/soc/espressif/esp32s3/esp32s3-mp.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/esp32s3-mp.c rename to soc/espressif/esp32s3/esp32s3-mp.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/loader.c b/soc/espressif/esp32s3/loader.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/loader.c rename to soc/espressif/esp32s3/loader.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld b/soc/espressif/esp32s3/mcuboot.ld similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/mcuboot.ld rename to soc/espressif/esp32s3/mcuboot.ld diff --git a/soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c b/soc/espressif/esp32s3/newlib_fix.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/newlib_fix.c rename to soc/espressif/esp32s3/newlib_fix.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h b/soc/espressif/esp32s3/pinctrl_soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/pinctrl_soc.h rename to soc/espressif/esp32s3/pinctrl_soc.h diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c new file mode 100644 index 00000000000000..d41732db14e1d6 --- /dev/null +++ b/soc/espressif/esp32s3/soc.c @@ -0,0 +1,322 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* Include esp-idf headers first to avoid redefining BIT() macro */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "esp_private/system_internal.h" +#include "esp32s3/rom/cache.h" +#include "esp32s3/rom/rtc.h" +#include "soc/syscon_reg.h" +#include "hal/soc_ll.h" +#include "hal/wdt_hal.h" +#include "soc/cpu.h" +#include "soc/gpio_periph.h" +#include "esp_spi_flash.h" +#include "esp_err.h" +#include "esp_timer.h" +#include "esp_app_format.h" +#include "esp_clk_internal.h" + +#include "esp32s3/spiram.h" + +#ifdef CONFIG_MCUBOOT +#include "bootloader_init.h" +#endif /* CONFIG_MCUBOOT */ +#include + +#if CONFIG_ESP_SPIRAM +extern int _ext_ram_bss_start; +extern int _ext_ram_bss_end; +#endif + +extern void z_cstart(void); +extern void esp_reset_reason_init(void); + +#if CONFIG_SOC_ENABLE_APPCPU +extern const unsigned char esp32s3_appcpu_fw_array[]; + +void IRAM_ATTR esp_start_appcpu(void) +{ + esp_image_header_t *header = (esp_image_header_t *)&esp32s3_appcpu_fw_array[0]; + esp_image_segment_header_t *segment = + (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[sizeof(esp_image_header_t)]; + uint8_t *segment_payload; + uint32_t entry_addr = header->entry_addr; + uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); + + for (int i = 0; i < header->segment_count; i++) { + segment_payload = (uint8_t *)&esp32s3_appcpu_fw_array[idx]; + + if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { + /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ + volatile uint32_t *src = (volatile uint32_t *)segment_payload; + volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; + + for (int i = 0; i < segment->data_len / 4; i++) { + dst[i] = src[i]; + } + + } else if (segment->load_addr >= SOC_DRAM_LOW && + segment->load_addr < SOC_DRAM_HIGH) { + memcpy((void *)segment->load_addr, (const void *)segment_payload, + segment->data_len); + } + + idx += segment->data_len; + segment = (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[idx]; + idx += sizeof(esp_image_segment_header_t); + } + + esp_appcpu_start((void *)entry_addr); +} +#endif /* CONFIG_SOC_ENABLE_APPCPU */ + +#ifndef CONFIG_MCUBOOT +/* + * This function is a container for SoC patches + * that needs to be applied during the startup. + */ +static void IRAM_ATTR esp_errata(void) +{ + /* Handle the clock gating fix */ + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); + /* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING + * signals to ensure that the App core stops running in single-core mode. + */ + REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); + REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); + + /* Handle the Dcache case following the IDF startup code */ +#if CONFIG_ESP32S3_DATA_CACHE_16KB + Cache_Invalidate_DCache_All(); + Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000); +#endif +} +#endif /* CONFIG_MCUBOOT */ + +/* + * This is written in C rather than assembly since, during the port bring up, + * Zephyr is being booted by the Espressif bootloader. With it, the C stack + * is already set up. + */ +void IRAM_ATTR __esp_platform_start(void) +{ + extern uint32_t _init_start; + + /* Move the exception vector table to IRAM. */ + __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); + + z_bss_zero(); + + /* Disable normal interrupts. */ + __asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); + + /* Initialize the architecture CPU pointer. Some of the + * initialization code wants a valid _current before + * arch_kernel_init() is invoked. + */ + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + +#ifdef CONFIG_MCUBOOT + /* MCUboot early initialisation. */ + if (bootloader_init()) { + abort(); + } +#else + /* Configure the mode of instruction cache : cache size, cache line size. */ + esp_config_instruction_cache_mode(); + + /* If we need use SPIRAM, we should use data cache. + * Configure the mode of data : cache size, cache line size. + */ + esp_config_data_cache_mode(); + + /* Apply SoC patches */ + esp_errata(); + +#if CONFIG_ESP_SPIRAM + esp_err_t err = esp_spiram_init(); + + if (err != ESP_OK) { + printk("Failed to Initialize external RAM, aborting.\n"); + abort(); + } + + esp_spiram_init_cache(); + if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + printk("External RAM size is less than configured, aborting.\n"); + abort(); + } + + if (!esp_spiram_test()) { + printk("External RAM failed memory test!\n"); + abort(); + } + + memset(&_ext_ram_bss_start, 0, + (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); + +#endif /* CONFIG_ESP_SPIRAM */ + + /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence + * related issues in application. Hence disable that as we are about to start + * Zephyr environment. + */ + wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; + + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_disable(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + + esp_reset_reason_init(); + + esp_clk_init(); + + esp_timer_early_init(); + +#if CONFIG_SOC_ENABLE_APPCPU + /* start the ESP32S3 APP CPU */ + esp_start_appcpu(); +#endif + +#if CONFIG_SOC_FLASH_ESP32 + spi_flash_guard_set(&g_flash_guard_default_ops); +#endif +#endif /* CONFIG_MCUBOOT */ + + esp_intr_initialize(); + + /* Start Zephyr */ + z_cstart(); + + CODE_UNREACHABLE; +} + +/* Boot-time static default printk handler, possibly to be overridden later. */ +int IRAM_ATTR arch_printk_char_out(int c) +{ + if (c == '\n') { + esp_rom_uart_tx_one_char('\r'); + } + esp_rom_uart_tx_one_char(c); + return 0; +} + +void sys_arch_reboot(int type) +{ + esp_restart_noos(); +} + +void IRAM_ATTR esp_restart_noos(void) +{ + /* disable interrupts */ + z_xt_ints_off(0xFFFFFFFF); + + /* enable RTC watchdog for 1 second */ + wdt_hal_context_t wdt_ctx; + uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); + + wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); + wdt_hal_write_protect_disable(&wdt_ctx); + wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); + wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); + + /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ + wdt_hal_set_flashboot_en(&wdt_ctx, true); + wdt_hal_write_protect_enable(&wdt_ctx); + + /* disable TG0/TG1 watchdogs */ + wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; + + wdt_hal_write_protect_disable(&wdt0_context); + wdt_hal_disable(&wdt0_context); + wdt_hal_write_protect_enable(&wdt0_context); + + wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; + + wdt_hal_write_protect_disable(&wdt1_context); + wdt_hal_disable(&wdt1_context); + wdt_hal_write_protect_enable(&wdt1_context); + + /* Flush any data left in UART FIFOs */ + esp_rom_uart_tx_wait_idle(0); + esp_rom_uart_tx_wait_idle(1); + esp_rom_uart_tx_wait_idle(2); + + /* Disable cache */ + Cache_Disable_ICache(); + Cache_Disable_DCache(); + + const uint32_t core_id = cpu_hal_get_core_id(); +#if CONFIG_SMP + const uint32_t other_core_id = (core_id == 0) ? 1 : 0; + + soc_ll_reset_core(other_core_id); + soc_ll_stall_core(other_core_id); +#endif + + /* 2nd stage bootloader reconfigures SPI flash signals. */ + /* Reset them to the defaults expected by ROM */ + WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); + WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); + + /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ + SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, + SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | + SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | + SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | + SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); + REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); + + /* Reset timer/spi/uart */ + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | + SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); + + /* Reset DMA */ + SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); + REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); + + SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); + + rtc_clk_cpu_freq_set_xtal(); + + /* Reset CPUs */ + if (core_id == 0) { + /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ + soc_ll_reset_core(1); + soc_ll_reset_core(0); + } else { + /* Running on APP CPU: need to reset PRO CPU and unstall it, */ + /* then reset APP CPU */ + soc_ll_reset_core(0); + soc_ll_stall_core(0); + soc_ll_reset_core(1); + } + + while (true) { + ; + } +} diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc.h b/soc/espressif/esp32s3/soc.h similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/soc.h rename to soc/espressif/esp32s3/soc.h diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc_appcpu.c b/soc/espressif/esp32s3/soc_appcpu.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/soc_appcpu.c rename to soc/espressif/esp32s3/soc_appcpu.c diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc_cache.c b/soc/espressif/esp32s3/soc_cache.c similarity index 100% rename from soc/xtensa/espressif_esp32/esp32s3/soc_cache.c rename to soc/espressif/esp32s3/soc_cache.c diff --git a/soc/espressif/soc.yml b/soc/espressif/soc.yml new file mode 100644 index 00000000000000..13f6092e311a85 --- /dev/null +++ b/soc/espressif/soc.yml @@ -0,0 +1,21 @@ +family: +- name: espressif_esp32 + series: + - name: esp32 + socs: + - name: esp32 + cpuclusters: + - name: procpu + - name: appcpu + - name: esp32s2 + socs: + - name: esp32s2 + - name: esp32s3 + socs: + - name: esp32s3 + cpuclusters: + - name: procpu + - name: appcpu + - name: esp32c3 + socs: + - name: esp32c3 diff --git a/soc/gaisler/Kconfig b/soc/gaisler/Kconfig new file mode 100644 index 00000000000000..2a8eb9b88e07ea --- /dev/null +++ b/soc/gaisler/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SPARC_CASA + bool + default y if SPARC diff --git a/soc/gaisler/Kconfig.soc b/soc/gaisler/Kconfig.soc new file mode 100644 index 00000000000000..000f2a774afea0 --- /dev/null +++ b/soc/gaisler/Kconfig.soc @@ -0,0 +1,5 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SPARC_LEON + bool diff --git a/soc/gaisler/gr716a/CMakeLists.txt b/soc/gaisler/gr716a/CMakeLists.txt new file mode 100644 index 00000000000000..f33677ad301f4c --- /dev/null +++ b/soc/gaisler/gr716a/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(../leon3/idle.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/gaisler/gr716a/Kconfig b/soc/gaisler/gr716a/Kconfig new file mode 100644 index 00000000000000..6613952b104efa --- /dev/null +++ b/soc/gaisler/gr716a/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_GR716A + select SPARC + select SOC_SPARC_LEON + select CPU_HAS_FPU + +rsource "../Kconfig" diff --git a/soc/gaisler/gr716a/Kconfig.defconfig b/soc/gaisler/gr716a/Kconfig.defconfig new file mode 100644 index 00000000000000..c6913964fd8062 --- /dev/null +++ b/soc/gaisler/gr716a/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +if SOC_GR716A + +config SPARC_NWIN + default 31 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 50000000 + +if FLASH + +config SPI + default y + +config SPI_NOR + default y + +config SPI_GRLIB_SPIMCTRL + default y + +endif + +endif diff --git a/soc/gaisler/gr716a/Kconfig.soc b/soc/gaisler/gr716a/Kconfig.soc new file mode 100644 index 00000000000000..0eded2f841911a --- /dev/null +++ b/soc/gaisler/gr716a/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_GR716A + bool + +config SOC + default "gr716a" if SOC_GR716A + +rsource "../Kconfig.soc" diff --git a/soc/sparc/gr716a/linker.ld b/soc/gaisler/gr716a/linker.ld similarity index 100% rename from soc/sparc/gr716a/linker.ld rename to soc/gaisler/gr716a/linker.ld diff --git a/soc/sparc/gr716a/soc.h b/soc/gaisler/gr716a/soc.h similarity index 100% rename from soc/sparc/gr716a/soc.h rename to soc/gaisler/gr716a/soc.h diff --git a/soc/gaisler/gr716a/soc.yml b/soc/gaisler/gr716a/soc.yml new file mode 100644 index 00000000000000..e61d3a2a1889bc --- /dev/null +++ b/soc/gaisler/gr716a/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: gr716a diff --git a/soc/gaisler/leon3/CMakeLists.txt b/soc/gaisler/leon3/CMakeLists.txt new file mode 100644 index 00000000000000..7b5ea47c82dfc0 --- /dev/null +++ b/soc/gaisler/leon3/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(idle.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/gaisler/leon3/Kconfig b/soc/gaisler/leon3/Kconfig new file mode 100644 index 00000000000000..106bf077569ce0 --- /dev/null +++ b/soc/gaisler/leon3/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LEON3 + select SPARC + select SOC_SPARC_LEON + +rsource "../Kconfig" diff --git a/soc/gaisler/leon3/Kconfig.defconfig b/soc/gaisler/leon3/Kconfig.defconfig new file mode 100644 index 00000000000000..d93676360d1b20 --- /dev/null +++ b/soc/gaisler/leon3/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +if SOC_LEON3 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 40000000 + +endif diff --git a/soc/gaisler/leon3/Kconfig.soc b/soc/gaisler/leon3/Kconfig.soc new file mode 100644 index 00000000000000..e0e9222c456ff4 --- /dev/null +++ b/soc/gaisler/leon3/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2019-2020 Cobham Gaisler AB +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LEON3 + bool + +config SOC + default "leon3" if SOC_LEON3 + +rsource "../Kconfig.soc" diff --git a/soc/sparc/leon3/idle.c b/soc/gaisler/leon3/idle.c similarity index 100% rename from soc/sparc/leon3/idle.c rename to soc/gaisler/leon3/idle.c diff --git a/soc/sparc/leon3/linker.ld b/soc/gaisler/leon3/linker.ld similarity index 100% rename from soc/sparc/leon3/linker.ld rename to soc/gaisler/leon3/linker.ld diff --git a/soc/sparc/leon3/soc.h b/soc/gaisler/leon3/soc.h similarity index 100% rename from soc/sparc/leon3/soc.h rename to soc/gaisler/leon3/soc.h diff --git a/soc/gaisler/leon3/soc.yml b/soc/gaisler/leon3/soc.yml new file mode 100644 index 00000000000000..f780ea08f81e60 --- /dev/null +++ b/soc/gaisler/leon3/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: leon3 diff --git a/soc/arm/gd_gd32/CMakeLists.txt b/soc/gd/gd32/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/CMakeLists.txt rename to soc/gd/gd32/CMakeLists.txt diff --git a/soc/gd/gd32/Kconfig b/soc/gd/gd32/Kconfig new file mode 100644 index 00000000000000..a94d20b3b1a0c4 --- /dev/null +++ b/soc/gd/gd32/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_GD_GD32 + select HAS_GD32_HAL + select BUILD_OUTPUT_HEX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_GD_GD32 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_GD_GD32 diff --git a/soc/gd/gd32/Kconfig.defconfig b/soc/gd/gd32/Kconfig.defconfig new file mode 100644 index 00000000000000..345f14c0629798 --- /dev/null +++ b/soc/gd/gd32/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_GD_GD32 + +rsource "*/Kconfig.defconfig.series" + +config PINCTRL + default y + +config RESET + default y + +config CLOCK_CONTROL + default y + +endif # SOC_FAMILY_GD_GD32 diff --git a/soc/gd/gd32/Kconfig.soc b/soc/gd/gd32/Kconfig.soc new file mode 100644 index 00000000000000..3b4f6c616b6583 --- /dev/null +++ b/soc/gd/gd32/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_GD_GD32 + bool + +config SOC_FAMILY + default "gd_gd32" if SOC_FAMILY_GD_GD32 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/gd_gd32/common/CMakeLists.txt b/soc/gd/gd32/common/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/common/CMakeLists.txt rename to soc/gd/gd32/common/CMakeLists.txt diff --git a/include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h b/soc/gd/gd32/common/pinctrl_soc.h similarity index 100% rename from include/zephyr/drivers/pinctrl/pinctrl_soc_gd32_common.h rename to soc/gd/gd32/common/pinctrl_soc.h diff --git a/soc/arm/gd_gd32/gd32a50x/CMakeLists.txt b/soc/gd/gd32/gd32a50x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/CMakeLists.txt rename to soc/gd/gd32/gd32a50x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32a50x/Kconfig b/soc/gd/gd32/gd32a50x/Kconfig new file mode 100644 index 00000000000000..8cd903e86ad6a1 --- /dev/null +++ b/soc/gd/gd32/gd32a50x/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32A50X + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_40K + select PLATFORM_SPECIFIC_INIT diff --git a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32a503 b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.gd32a503 similarity index 85% rename from soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32a503 rename to soc/gd/gd32/gd32a50x/Kconfig.defconfig.gd32a503 index a714d56cb61fd7..6b54ab05e61f1e 100644 --- a/soc/arm/gd_gd32/gd32a50x/Kconfig.defconfig.gd32a503 +++ b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.gd32a503 @@ -1,11 +1,12 @@ # Copyright (c) 2022 YuLong Yao # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32a503" +if SOC_GD32A503 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 82 + +endif # SOC_GD32A503 diff --git a/soc/gd/gd32/gd32a50x/Kconfig.defconfig.series b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.series new file mode 100644 index 00000000000000..f54d52b13c9cd2 --- /dev/null +++ b/soc/gd/gd32/gd32a50x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32A50X + +config SOC_SERIES + default "gd32a50x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32A50X diff --git a/soc/gd/gd32/gd32a50x/Kconfig.soc b/soc/gd/gd32/gd32a50x/Kconfig.soc new file mode 100644 index 00000000000000..26345d8cbf0f70 --- /dev/null +++ b/soc/gd/gd32/gd32a50x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2022 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32A50X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32A50X MCU series + +config SOC_SERIES + default "gd32a50x" if SOC_SERIES_GD32A50X + +config SOC_GD32A503 + bool + select SOC_SERIES_GD32A50X + +config SOC + default "gd32a503" if SOC_GD32A503 diff --git a/soc/arm/gd_gd32/gd32a50x/gd32_regs.h b/soc/gd/gd32/gd32a50x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/gd32_regs.h rename to soc/gd/gd32/gd32a50x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32a50x/soc.c b/soc/gd/gd32/gd32a50x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/soc.c rename to soc/gd/gd32/gd32a50x/soc.c diff --git a/soc/arm/gd_gd32/gd32a50x/soc.h b/soc/gd/gd32/gd32a50x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32a50x/soc.h rename to soc/gd/gd32/gd32a50x/soc.h diff --git a/soc/arm/gd_gd32/gd32e10x/CMakeLists.txt b/soc/gd/gd32/gd32e10x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/CMakeLists.txt rename to soc/gd/gd32/gd32e10x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32e10x/Kconfig b/soc/gd/gd32/gd32e10x/Kconfig new file mode 100644 index 00000000000000..6b83464fd719b1 --- /dev/null +++ b/soc/gd/gd32/gd32e10x/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E10X + select ARM + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32e103 b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.gd32e103 similarity index 85% rename from soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32e103 rename to soc/gd/gd32/gd32e10x/Kconfig.defconfig.gd32e103 index 38dfedb9cd05c3..d1b9801bb9a582 100644 --- a/soc/arm/gd_gd32/gd32e10x/Kconfig.defconfig.gd32e103 +++ b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.gd32e103 @@ -1,11 +1,12 @@ # Copyright (c) 2021 YuLong Yao # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32e103" +if SOC_GD32E103 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 83 + +endif # SOC_GD32E103 diff --git a/soc/gd/gd32/gd32e10x/Kconfig.defconfig.series b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.series new file mode 100644 index 00000000000000..2aec533c23ccd2 --- /dev/null +++ b/soc/gd/gd32/gd32e10x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32E10X + +config SOC_SERIES + default "gd32e10x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32E10X diff --git a/soc/gd/gd32/gd32e10x/Kconfig.soc b/soc/gd/gd32/gd32e10x/Kconfig.soc new file mode 100644 index 00000000000000..8108580bba6e71 --- /dev/null +++ b/soc/gd/gd32/gd32e10x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2021 YuLong Yao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E10X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32E10X MCU series + +config SOC_SERIES + default "gd32e10x" if SOC_SERIES_GD32E10X + +config SOC_GD32E103 + bool + select SOC_SERIES_GD32E10X + +config SOC + default "gd32e103" if SOC_GD32E103 diff --git a/soc/arm/gd_gd32/gd32e10x/gd32_regs.h b/soc/gd/gd32/gd32e10x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/gd32_regs.h rename to soc/gd/gd32/gd32e10x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32e10x/soc.c b/soc/gd/gd32/gd32e10x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/soc.c rename to soc/gd/gd32/gd32e10x/soc.c diff --git a/soc/arm/gd_gd32/gd32e10x/soc.h b/soc/gd/gd32/gd32e10x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32e10x/soc.h rename to soc/gd/gd32/gd32e10x/soc.h diff --git a/soc/arm/gd_gd32/gd32e50x/CMakeLists.txt b/soc/gd/gd32/gd32e50x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/CMakeLists.txt rename to soc/gd/gd32/gd32e50x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32e50x/Kconfig b/soc/gd/gd32/gd32e50x/Kconfig new file mode 100644 index 00000000000000..d0672660e85851 --- /dev/null +++ b/soc/gd/gd32/gd32e50x/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E50X + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M33 + select ARMV8_M_DSP + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32e507 b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.gd32e507 similarity index 88% rename from soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32e507 rename to soc/gd/gd32/gd32e50x/Kconfig.defconfig.gd32e507 index b9d9bbb56976a4..b2b15f6ce00e1c 100644 --- a/soc/arm/gd_gd32/gd32e50x/Kconfig.defconfig.gd32e507 +++ b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.gd32e507 @@ -3,9 +3,6 @@ if SOC_GD32E507 -config SOC - default "gd32e507" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/gd/gd32/gd32e50x/Kconfig.defconfig.series b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.series new file mode 100644 index 00000000000000..1b9f8b981502bd --- /dev/null +++ b/soc/gd/gd32/gd32e50x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32E50X + +config SOC_SERIES + default "gd32e50x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32E50X diff --git a/soc/gd/gd32/gd32e50x/Kconfig.soc b/soc/gd/gd32/gd32e50x/Kconfig.soc new file mode 100644 index 00000000000000..4523d95e5c21da --- /dev/null +++ b/soc/gd/gd32/gd32e50x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2022, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32E50X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32E50X MCU series + +config SOC_SERIES + default "gd32e50x" if SOC_SERIES_GD32E50X + +config SOC_GD32E507 + bool + select SOC_SERIES_GD32E50X + +config SOC + default "gd32e507" if SOC_GD32E507 diff --git a/soc/arm/gd_gd32/gd32e50x/gd32_regs.h b/soc/gd/gd32/gd32e50x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/gd32_regs.h rename to soc/gd/gd32/gd32e50x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32e50x/soc.c b/soc/gd/gd32/gd32e50x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/soc.c rename to soc/gd/gd32/gd32e50x/soc.c diff --git a/soc/arm/gd_gd32/gd32e50x/soc.h b/soc/gd/gd32/gd32e50x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32e50x/soc.h rename to soc/gd/gd32/gd32e50x/soc.h diff --git a/soc/arm/gd_gd32/gd32f3x0/CMakeLists.txt b/soc/gd/gd32/gd32f3x0/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/CMakeLists.txt rename to soc/gd/gd32/gd32f3x0/CMakeLists.txt diff --git a/soc/gd/gd32/gd32f3x0/Kconfig b/soc/gd/gd32/gd32f3x0/Kconfig new file mode 100644 index 00000000000000..e2e9bff6ba1f6d --- /dev/null +++ b/soc/gd/gd32/gd32f3x0/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F3X0 + select ARM + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32f350 b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.gd32f350 similarity index 83% rename from soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32f350 rename to soc/gd/gd32/gd32f3x0/Kconfig.defconfig.gd32f350 index 6cd1ca9ec8bed4..ced9dc7095dd60 100644 --- a/soc/arm/gd_gd32/gd32f3x0/Kconfig.defconfig.gd32f350 +++ b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.gd32f350 @@ -1,11 +1,12 @@ # Copyright (c) 2021 BrainCo Inc. # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32f350" +if SOC_GD32F350 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 68 + +endif # SOC_GD32F350 diff --git a/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series new file mode 100644 index 00000000000000..0bb139d227fe8c --- /dev/null +++ b/soc/gd/gd32/gd32f3x0/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F3X0 + +config SOC_SERIES + default "gd32f3x0" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32F3X0 diff --git a/soc/gd/gd32/gd32f3x0/Kconfig.soc b/soc/gd/gd32/gd32f3x0/Kconfig.soc new file mode 100644 index 00000000000000..5f3f00dd638d04 --- /dev/null +++ b/soc/gd/gd32/gd32f3x0/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2021 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F3X0 + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32F3X0 MCU series + +config SOC_SERIES + default "gd32f3x0" if SOC_SERIES_GD32F3X0 + +config SOC_GD32F350 + bool + select SOC_SERIES_GD32F3X0 + +config SOC + default "gd32f350" if SOC_GD32F350 diff --git a/soc/arm/gd_gd32/gd32f3x0/gd32_regs.h b/soc/gd/gd32/gd32f3x0/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/gd32_regs.h rename to soc/gd/gd32/gd32f3x0/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32f3x0/soc.c b/soc/gd/gd32/gd32f3x0/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/soc.c rename to soc/gd/gd32/gd32f3x0/soc.c diff --git a/soc/arm/gd_gd32/gd32f3x0/soc.h b/soc/gd/gd32/gd32f3x0/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32f3x0/soc.h rename to soc/gd/gd32/gd32f3x0/soc.h diff --git a/soc/arm/gd_gd32/gd32f403/CMakeLists.txt b/soc/gd/gd32/gd32f403/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32f403/CMakeLists.txt rename to soc/gd/gd32/gd32f403/CMakeLists.txt diff --git a/soc/gd/gd32/gd32f403/Kconfig b/soc/gd/gd32/gd32f403/Kconfig new file mode 100644 index 00000000000000..c4b31a0e41d0cf --- /dev/null +++ b/soc/gd/gd32/gd32f403/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F403 + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K diff --git a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403 b/soc/gd/gd32/gd32f403/Kconfig.defconfig.gd32f403 similarity index 84% rename from soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403 rename to soc/gd/gd32/gd32f403/Kconfig.defconfig.gd32f403 index f3bc4ac2209235..2a08dbfb61c18d 100644 --- a/soc/arm/gd_gd32/gd32f403/Kconfig.defconfig.gd32f403 +++ b/soc/gd/gd32/gd32f403/Kconfig.defconfig.gd32f403 @@ -1,11 +1,12 @@ # Copyright (c) 2021, ATL Electronics # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32f403" +if SOC_GD32F403 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 68 + +endif # SOC_GD32F403 diff --git a/soc/gd/gd32/gd32f403/Kconfig.defconfig.series b/soc/gd/gd32/gd32f403/Kconfig.defconfig.series new file mode 100644 index 00000000000000..6a316658f9f8d8 --- /dev/null +++ b/soc/gd/gd32/gd32f403/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F403 + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32F403 diff --git a/soc/gd/gd32/gd32f403/Kconfig.soc b/soc/gd/gd32/gd32f403/Kconfig.soc new file mode 100644 index 00000000000000..b377b95c086685 --- /dev/null +++ b/soc/gd/gd32/gd32f403/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2021, ATL Electronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F403 + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32F403 MCU series + +config SOC_SERIES + default "gd32f403" if SOC_SERIES_GD32F403 + +config SOC_GD32F403 + bool + select SOC_SERIES_GD32F403 + +config SOC + default "gd32f403" if SOC_GD32F403 diff --git a/soc/arm/gd_gd32/gd32f403/gd32_regs.h b/soc/gd/gd32/gd32f403/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32f403/gd32_regs.h rename to soc/gd/gd32/gd32f403/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32f403/soc.c b/soc/gd/gd32/gd32f403/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32f403/soc.c rename to soc/gd/gd32/gd32f403/soc.c diff --git a/soc/arm/gd_gd32/gd32f403/soc.h b/soc/gd/gd32/gd32f403/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32f403/soc.h rename to soc/gd/gd32/gd32f403/soc.h diff --git a/soc/arm/gd_gd32/gd32f4xx/CMakeLists.txt b/soc/gd/gd32/gd32f4xx/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/CMakeLists.txt rename to soc/gd/gd32/gd32f4xx/CMakeLists.txt diff --git a/soc/gd/gd32/gd32f4xx/Kconfig b/soc/gd/gd32/gd32f4xx/Kconfig new file mode 100644 index 00000000000000..efc8455e116732 --- /dev/null +++ b/soc/gd/gd32/gd32f4xx/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F4XX + select ARM + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_CORTEX_M4 + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_32K diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f405 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405 similarity index 88% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f405 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405 index 966bf8e80ac15c..cb70828b02274a 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f405 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405 @@ -3,9 +3,6 @@ if SOC_GD32F405 -config SOC - default "gd32f405" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f407 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f407 similarity index 89% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f407 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f407 index 202bb0f5b2e94e..2fc1491a5db4c5 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f407 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f407 @@ -3,9 +3,6 @@ if SOC_GD32F407 -config SOC - default "gd32f407" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f450 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f450 similarity index 88% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f450 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f450 index a4fd9ff66afd14..22d593989a2874 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f450 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f450 @@ -3,9 +3,6 @@ if SOC_GD32F450 -config SOC - default "gd32f450" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f470 b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f470 similarity index 87% rename from soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f470 rename to soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f470 index 3ddc0122dc0d00..3656a3acc0bd94 100644 --- a/soc/arm/gd_gd32/gd32f4xx/Kconfig.defconfig.gd32f470 +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f470 @@ -3,9 +3,6 @@ if SOC_GD32F470 -config SOC - default "gd32f470" - config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) diff --git a/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series new file mode 100644 index 00000000000000..aa626c9523f9b6 --- /dev/null +++ b/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32F4XX + +config SOC_SERIES + default "gd32f4xx" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32F4XX diff --git a/soc/gd/gd32/gd32f4xx/Kconfig.soc b/soc/gd/gd32/gd32f4xx/Kconfig.soc new file mode 100644 index 00000000000000..fde68179bc984b --- /dev/null +++ b/soc/gd/gd32/gd32f4xx/Kconfig.soc @@ -0,0 +1,34 @@ +# Copyright (c) 2021, Teslabs Engineering S.L. +# Copyright (c) 2022, Rtone. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32F4XX + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32F4XX MCU series + +config SOC_SERIES + default "gd32f4xx" if SOC_SERIES_GD32F4XX + +config SOC_GD32F405 + bool + select SOC_SERIES_GD32F4XX + +config SOC_GD32F407 + bool + select SOC_SERIES_GD32F4XX + +config SOC_GD32F450 + bool + select SOC_SERIES_GD32F4XX + +config SOC_GD32F470 + bool + select SOC_SERIES_GD32F4XX + +config SOC + default "gd32f405" if SOC_GD32F405 + default "gd32f407" if SOC_GD32F407 + default "gd32f450" if SOC_GD32F450 + default "gd32f470" if SOC_GD32F470 diff --git a/soc/arm/gd_gd32/gd32f4xx/gd32_regs.h b/soc/gd/gd32/gd32f4xx/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/gd32_regs.h rename to soc/gd/gd32/gd32f4xx/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32f4xx/soc.c b/soc/gd/gd32/gd32f4xx/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/soc.c rename to soc/gd/gd32/gd32f4xx/soc.c diff --git a/soc/arm/gd_gd32/gd32f4xx/soc.h b/soc/gd/gd32/gd32f4xx/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32f4xx/soc.h rename to soc/gd/gd32/gd32f4xx/soc.h diff --git a/soc/arm/gd_gd32/gd32l23x/CMakeLists.txt b/soc/gd/gd32/gd32l23x/CMakeLists.txt similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/CMakeLists.txt rename to soc/gd/gd32/gd32l23x/CMakeLists.txt diff --git a/soc/gd/gd32/gd32l23x/Kconfig b/soc/gd/gd32/gd32l23x/Kconfig new file mode 100644 index 00000000000000..5155d89ea152f9 --- /dev/null +++ b/soc/gd/gd32/gd32l23x/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32L23X + select ARM + select CPU_CORTEX_M23 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select GD32_HAS_AF_PINMUX + select GD32_HAS_IRC_32K diff --git a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32l233 b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.gd32l233 similarity index 83% rename from soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32l233 rename to soc/gd/gd32/gd32l23x/Kconfig.defconfig.gd32l233 index 31ad6d9034eead..bec843575d7082 100644 --- a/soc/arm/gd_gd32/gd32l23x/Kconfig.defconfig.gd32l233 +++ b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.gd32l233 @@ -1,11 +1,12 @@ # Copyright (c) 2022 BrainCo Inc. # SPDX-License-Identifier: Apache-2.0 -config SOC - default "gd32l233" +if SOC_GD32L233 config SYS_CLOCK_HW_CYCLES_PER_SEC default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) config NUM_IRQS default 69 + +endif # SOC_GD32L233 diff --git a/soc/gd/gd32/gd32l23x/Kconfig.defconfig.series b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.series new file mode 100644 index 00000000000000..bc8b2aa4cde864 --- /dev/null +++ b/soc/gd/gd32/gd32l23x/Kconfig.defconfig.series @@ -0,0 +1,11 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32L23X + +config SOC_SERIES + default "gd32l23x" + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32L23X diff --git a/soc/gd/gd32/gd32l23x/Kconfig.soc b/soc/gd/gd32/gd32l23x/Kconfig.soc new file mode 100644 index 00000000000000..da3a950aa256f8 --- /dev/null +++ b/soc/gd/gd32/gd32l23x/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2022 BrainCo Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32L23X + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32L23X MCU series + +config SOC_SERIES + default "gd32l23x" if SOC_SERIES_GD32L23X + +config SOC_GD32L233 + bool + select SOC_SERIES_GD32L23X + +config SOC + default "gd32l233" if SOC_GD32L233 diff --git a/soc/arm/gd_gd32/gd32l23x/gd32_regs.h b/soc/gd/gd32/gd32l23x/gd32_regs.h similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/gd32_regs.h rename to soc/gd/gd32/gd32l23x/gd32_regs.h diff --git a/soc/arm/gd_gd32/gd32l23x/soc.c b/soc/gd/gd32/gd32l23x/soc.c similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/soc.c rename to soc/gd/gd32/gd32l23x/soc.c diff --git a/soc/arm/gd_gd32/gd32l23x/soc.h b/soc/gd/gd32/gd32l23x/soc.h similarity index 100% rename from soc/arm/gd_gd32/gd32l23x/soc.h rename to soc/gd/gd32/gd32l23x/soc.h diff --git a/soc/gd/gd32/gd32vf103/CMakeLists.txt b/soc/gd/gd32/gd32vf103/CMakeLists.txt new file mode 100644 index 00000000000000..6778c0a4f1b3ab --- /dev/null +++ b/soc/gd/gd32/gd32vf103/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(entry.S) +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/gd/gd32/gd32vf103/Kconfig b/soc/gd/gd32/gd32vf103/Kconfig new file mode 100644 index 00000000000000..d206100c53eb97 --- /dev/null +++ b/soc/gd/gd32/gd32vf103/Kconfig @@ -0,0 +1,20 @@ +# GD32VF103 SOC implementation + +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32VF103 + select RISCV + select RISCV_PRIVILEGED + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_HAS_CLIC + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR + select GD32_HAS_AFIO_PINMUX + select GD32_HAS_IRC_40K + select XIP diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 similarity index 86% rename from soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 rename to soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 index d37b27ffbf02ae..714741364bb534 100644 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103 +++ b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103 @@ -3,9 +3,6 @@ if SOC_GD32VF103 -config SOC - default "gd32vf103" - config KERNEL_ENTRY default "__nuclei_start" @@ -30,15 +27,6 @@ config NUM_IRQS config 2ND_LEVEL_INTERRUPTS default y -config PINCTRL - default y - -config RESET - default y - -config CLOCK_CONTROL - default y - config ARCH_IRQ_VECTOR_TABLE_ALIGN default 512 if NUCLEI_ECLIC diff --git a/soc/gd/gd32/gd32vf103/Kconfig.defconfig.series b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.series new file mode 100644 index 00000000000000..78a912701d9926 --- /dev/null +++ b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_GD32VF103 + +rsource "Kconfig.defconfig.gd32*" + +endif # SOC_SERIES_GD32VF103 diff --git a/soc/gd/gd32/gd32vf103/Kconfig.soc b/soc/gd/gd32/gd32vf103/Kconfig.soc new file mode 100644 index 00000000000000..c692e914ad11bb --- /dev/null +++ b/soc/gd/gd32/gd32vf103/Kconfig.soc @@ -0,0 +1,20 @@ +# GD32VF103 SOC configuration options + +# Copyright (c) 2021 Tokita, Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_GD32VF103 + bool + select SOC_FAMILY_GD_GD32 + help + Enable support for GigaDevice GD32VF103 MCU series + +config SOC_SERIES + default "gd32vf103" if SOC_SERIES_GD32VF103 + +config SOC_GD32VF103 + bool + select SOC_SERIES_GD32VF103 + +config SOC + default "gd32vf103" if SOC_GD32VF103 diff --git a/soc/riscv/gd_gd32/gd32vf103/entry.S b/soc/gd/gd32/gd32vf103/entry.S similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/entry.S rename to soc/gd/gd32/gd32vf103/entry.S diff --git a/soc/riscv/gd_gd32/gd32vf103/gd32_regs.h b/soc/gd/gd32/gd32vf103/gd32_regs.h similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/gd32_regs.h rename to soc/gd/gd32/gd32vf103/gd32_regs.h diff --git a/soc/riscv/gd_gd32/gd32vf103/init.ld b/soc/gd/gd32/gd32vf103/init.ld similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/init.ld rename to soc/gd/gd32/gd32vf103/init.ld diff --git a/soc/riscv/gd_gd32/gd32vf103/nuclei_csr.h b/soc/gd/gd32/gd32vf103/nuclei_csr.h similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/nuclei_csr.h rename to soc/gd/gd32/gd32vf103/nuclei_csr.h diff --git a/soc/riscv/gd_gd32/gd32vf103/soc.c b/soc/gd/gd32/gd32vf103/soc.c similarity index 100% rename from soc/riscv/gd_gd32/gd32vf103/soc.c rename to soc/gd/gd32/gd32vf103/soc.c diff --git a/soc/gd/gd32/soc.yml b/soc/gd/gd32/soc.yml new file mode 100644 index 00000000000000..22339687e19cb3 --- /dev/null +++ b/soc/gd/gd32/soc.yml @@ -0,0 +1,30 @@ +family: +- name: gd_gd32 + series: + - name: gd32a50x + socs: + - name: gd32a503 + - name: gd32e10x + socs: + - name: gd32e103 + - name: gd32e50x + socs: + - name: gd32e507 + - name: gd32f3x0 + socs: + - name: gd32f350 + - name: gd32f4xx + socs: + - name: gd32f405 + - name: gd32f407 + - name: gd32f450 + - name: gd32f470 + - name: gd32f403 + socs: + - name: gd32f403 + - name: gd32l23x + socs: + - name: gd32l233 + - name: gd32vf103 + socs: + - name: gd32vf103 diff --git a/soc/arm/infineon_xmc/CMakeLists.txt b/soc/infineon/xmc/CMakeLists.txt similarity index 100% rename from soc/arm/infineon_xmc/CMakeLists.txt rename to soc/infineon/xmc/CMakeLists.txt diff --git a/soc/infineon/xmc/Kconfig b/soc/infineon/xmc/Kconfig new file mode 100644 index 00000000000000..8720e3a27b21c3 --- /dev/null +++ b/soc/infineon/xmc/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +config SOC_FAMILY_INFINEON_XMC + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_INFINEON_XMC + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INFINEON_XMC diff --git a/soc/infineon/xmc/Kconfig.defconfig b/soc/infineon/xmc/Kconfig.defconfig new file mode 100644 index 00000000000000..10a5e55986ab95 --- /dev/null +++ b/soc/infineon/xmc/Kconfig.defconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +if SOC_FAMILY_INFINEON_XMC + +rsource "*/Kconfig.defconfig" + +config PINCTRL + default y + +endif # SOC_FAMILY_INFINEON_XMC diff --git a/soc/infineon/xmc/Kconfig.soc b/soc/infineon/xmc/Kconfig.soc new file mode 100644 index 00000000000000..f0abf738dcab82 --- /dev/null +++ b/soc/infineon/xmc/Kconfig.soc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +config SOC_FAMILY_INFINEON_XMC + bool + +config SOC_FAMILY + default "infineon_xmc" if SOC_FAMILY_INFINEON_XMC + +rsource "*/Kconfig.soc" diff --git a/soc/infineon/xmc/soc.yml b/soc/infineon/xmc/soc.yml new file mode 100644 index 00000000000000..758e3c730d2974 --- /dev/null +++ b/soc/infineon/xmc/soc.yml @@ -0,0 +1,7 @@ +family: +- name: infineon_xmc + series: + - name: xmc4xxx + socs: + - name: xmc4500 + - name: xmc4700 diff --git a/soc/infineon/xmc/xmc4xxx/CMakeLists.txt b/soc/infineon/xmc/xmc4xxx/CMakeLists.txt new file mode 100644 index 00000000000000..811731b51bcf8e --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +zephyr_sources(soc.c) +zephyr_include_directories(.) +zephyr_linker_sources(NOINIT noinit.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/infineon/xmc/xmc4xxx/Kconfig b/soc/infineon/xmc/xmc4xxx/Kconfig new file mode 100644 index 00000000000000..21f4c7b5cb3c5d --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/Kconfig @@ -0,0 +1,24 @@ +# XMC 4xxx MCU line +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_XMC4XXX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select HAS_XMCLIB + select HAS_XMCLIB_UART + select HAS_XMCLIB_FLASH + select HAS_XMCLIB_ERU + select HAS_XMCLIB_VADC + select HAS_XMCLIB_DMA + select HAS_XMCLIB_SPI + select HAS_XMCLIB_I2C + select HAS_XMCLIB_CCU + select HAS_XMCLIB_WDT + select HAS_XMCLIB_ETH + select HAS_XMCLIB_CAN diff --git a/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig new file mode 100644 index 00000000000000..eec3dc0daf8324 --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# XMC 4xxx series configuration options +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi + +if SOC_SERIES_XMC4XXX + +config NUM_IRQS + default 112 + +rsource "Kconfig.defconfig.xmc*" + +endif # SOC_SERIES_XMC4XXX diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4500 b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4500 similarity index 90% rename from soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4500 rename to soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4500 index 7bb9ffc2b1f022..17e2caf1dbb9ec 100644 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4500 +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4500 @@ -6,9 +6,6 @@ if SOC_XMC4500 -config SOC - default "XMC4500" - config SYS_CLOCK_HW_CYCLES_PER_SEC default 120000000 diff --git a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4700 b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4700 similarity index 89% rename from soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4700 rename to soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4700 index febf1b38ab103b..a17429330a1681 100644 --- a/soc/arm/infineon_xmc/4xxx/Kconfig.defconfig.xmc4700 +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.defconfig.xmc4700 @@ -5,9 +5,6 @@ if SOC_XMC4700 -config SOC - default "XMC4700" - config SYS_CLOCK_HW_CYCLES_PER_SEC default 144000000 diff --git a/soc/infineon/xmc/xmc4xxx/Kconfig.soc b/soc/infineon/xmc/xmc4xxx/Kconfig.soc new file mode 100644 index 00000000000000..726e433b10b674 --- /dev/null +++ b/soc/infineon/xmc/xmc4xxx/Kconfig.soc @@ -0,0 +1,40 @@ +# XMC 4xxx MCU line +# +# Copyright (c) 2020 Linumiz +# Author: Parthiban Nallathambi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_XMC4XXX + bool + select SOC_FAMILY_INFINEON_XMC + help + XMC 4xxx Series MCU + +config SOC_XMC4500 + bool + select SOC_SERIES_XMC4XXX + help + SOC_XMC4500 + +config SOC_XMC4700 + bool + select SOC_SERIES_XMC4XXX + help + SOC_XMC4700 + +config SOC_PART_NUMBER_F100X1024 + bool + +config SOC_PART_NUMBER_F144X2048 + bool + +config SOC_SERIES + default "xmc4xxx" if SOC_SERIES_XMC4XXX + +config SOC + default "xmc4500" if SOC_XMC4500 + default "xmc4700" if SOC_XMC4700 + +config SOC_PART_NUMBER + default "F100x1024" if SOC_PART_NUMBER_F100X1024 + default "F144x2048" if SOC_PART_NUMBER_F144X2048 diff --git a/soc/arm/infineon_xmc/4xxx/noinit.ld b/soc/infineon/xmc/xmc4xxx/noinit.ld similarity index 100% rename from soc/arm/infineon_xmc/4xxx/noinit.ld rename to soc/infineon/xmc/xmc4xxx/noinit.ld diff --git a/soc/arm/infineon_xmc/4xxx/pinctrl_soc.h b/soc/infineon/xmc/xmc4xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/infineon_xmc/4xxx/pinctrl_soc.h rename to soc/infineon/xmc/xmc4xxx/pinctrl_soc.h diff --git a/soc/arm/infineon_xmc/4xxx/soc.c b/soc/infineon/xmc/xmc4xxx/soc.c similarity index 100% rename from soc/arm/infineon_xmc/4xxx/soc.c rename to soc/infineon/xmc/xmc4xxx/soc.c diff --git a/soc/arm/infineon_xmc/4xxx/soc.h b/soc/infineon/xmc/xmc4xxx/soc.h similarity index 100% rename from soc/arm/infineon_xmc/4xxx/soc.h rename to soc/infineon/xmc/xmc4xxx/soc.h diff --git a/soc/intel/alder_lake/CMakeLists.txt b/soc/intel/alder_lake/CMakeLists.txt new file mode 100644 index 00000000000000..7db5fbabfc0efc --- /dev/null +++ b/soc/intel/alder_lake/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library() +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_cc_option(-march=goldmont) + +zephyr_library_sources(cpu.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/alder_lake/Kconfig b/soc/intel/alder_lake/Kconfig new file mode 100644 index 00000000000000..1e8808cae13eb7 --- /dev/null +++ b/soc/intel/alder_lake/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ALDER_LAKE + select X86 + select X86_64 + select CPU_ATOM + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU diff --git a/soc/intel/alder_lake/Kconfig.defconfig b/soc/intel/alder_lake/Kconfig.defconfig new file mode 100644 index 00000000000000..ea70a8d5405f88 --- /dev/null +++ b/soc/intel/alder_lake/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Alder Lake SoC configuration options + +# Copyright (c) 2018-2024 Intel Corporation +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ALDER_LAKE + +config PCIE_MMIO_CFG + default y + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_ALDER_LAKE diff --git a/soc/intel/alder_lake/Kconfig.soc b/soc/intel/alder_lake/Kconfig.soc new file mode 100644 index 00000000000000..b808d0d74bb285 --- /dev/null +++ b/soc/intel/alder_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ALDER_LAKE + bool + +config SOC + default "alder_lake" if SOC_ALDER_LAKE diff --git a/soc/x86/alder_lake/cpu.c b/soc/intel/alder_lake/cpu.c similarity index 100% rename from soc/x86/alder_lake/cpu.c rename to soc/intel/alder_lake/cpu.c diff --git a/soc/x86/alder_lake/doc/supported_features.txt b/soc/intel/alder_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/alder_lake/doc/supported_features.txt rename to soc/intel/alder_lake/doc/supported_features.txt diff --git a/soc/x86/alder_lake/linker.ld b/soc/intel/alder_lake/linker.ld similarity index 100% rename from soc/x86/alder_lake/linker.ld rename to soc/intel/alder_lake/linker.ld diff --git a/soc/x86/alder_lake/soc.h b/soc/intel/alder_lake/soc.h similarity index 100% rename from soc/x86/alder_lake/soc.h rename to soc/intel/alder_lake/soc.h diff --git a/soc/intel/alder_lake/soc.yml b/soc/intel/alder_lake/soc.yml new file mode 100644 index 00000000000000..04c9d8b5eb96e3 --- /dev/null +++ b/soc/intel/alder_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Alder Lake SoC" +socs: +- name: alder_lake diff --git a/soc/x86/alder_lake/soc_gpio.h b/soc/intel/alder_lake/soc_gpio.h similarity index 100% rename from soc/x86/alder_lake/soc_gpio.h rename to soc/intel/alder_lake/soc_gpio.h diff --git a/soc/intel/apollo_lake/CMakeLists.txt b/soc/intel/apollo_lake/CMakeLists.txt new file mode 100644 index 00000000000000..7db5fbabfc0efc --- /dev/null +++ b/soc/intel/apollo_lake/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library() +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_cc_option(-march=goldmont) + +zephyr_library_sources(cpu.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/apollo_lake/Kconfig b/soc/intel/apollo_lake/Kconfig new file mode 100644 index 00000000000000..51a410b7fc74f5 --- /dev/null +++ b/soc/intel/apollo_lake/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_APOLLO_LAKE + select X86 + select X86_64 + select CPU_APOLLO_LAKE + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU + select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/intel/apollo_lake/Kconfig.defconfig b/soc/intel/apollo_lake/Kconfig.defconfig new file mode 100644 index 00000000000000..7ea881ce59eb12 --- /dev/null +++ b/soc/intel/apollo_lake/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Apollo Lake SoC configuration options + +# Copyright (c) 2018-2019 Intel Corporation +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_APOLLO_LAKE + +config PCIE_MMIO_CFG + default y + +if APIC_TIMER + +config APIC_TIMER_IRQ + default 24 + +config APIC_TIMER_TSC + default y + +endif # APIC_TIMER + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_APOLLO_LAKE diff --git a/soc/intel/apollo_lake/Kconfig.soc b/soc/intel/apollo_lake/Kconfig.soc new file mode 100644 index 00000000000000..0d45667d46f0fe --- /dev/null +++ b/soc/intel/apollo_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_APOLLO_LAKE + bool + +config SOC + default "apollo_lake" if SOC_APOLLO_LAKE diff --git a/soc/x86/apollo_lake/cpu.c b/soc/intel/apollo_lake/cpu.c similarity index 100% rename from soc/x86/apollo_lake/cpu.c rename to soc/intel/apollo_lake/cpu.c diff --git a/soc/x86/apollo_lake/doc/supported_features.txt b/soc/intel/apollo_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/apollo_lake/doc/supported_features.txt rename to soc/intel/apollo_lake/doc/supported_features.txt diff --git a/soc/x86/apollo_lake/linker.ld b/soc/intel/apollo_lake/linker.ld similarity index 100% rename from soc/x86/apollo_lake/linker.ld rename to soc/intel/apollo_lake/linker.ld diff --git a/soc/x86/apollo_lake/soc.h b/soc/intel/apollo_lake/soc.h similarity index 100% rename from soc/x86/apollo_lake/soc.h rename to soc/intel/apollo_lake/soc.h diff --git a/soc/intel/apollo_lake/soc.yml b/soc/intel/apollo_lake/soc.yml new file mode 100644 index 00000000000000..0e1d16f9746410 --- /dev/null +++ b/soc/intel/apollo_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Apollo Lake SoC" +socs: +- name: apollo_lake diff --git a/soc/x86/apollo_lake/soc_gpio.h b/soc/intel/apollo_lake/soc_gpio.h similarity index 100% rename from soc/x86/apollo_lake/soc_gpio.h rename to soc/intel/apollo_lake/soc_gpio.h diff --git a/soc/intel/atom/CMakeLists.txt b/soc/intel/atom/CMakeLists.txt new file mode 100644 index 00000000000000..9bb60341f1bf99 --- /dev/null +++ b/soc/intel/atom/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2011-2014, Wind River Systems, Inc. + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/atom/Kconfig b/soc/intel/atom/Kconfig new file mode 100644 index 00000000000000..bc0d509eb709d0 --- /dev/null +++ b/soc/intel/atom/Kconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2011-2014, Wind River Systems, Inc. + +config SOC_ATOM + select X86 + select CPU_ATOM + imply X86_MMU + select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/intel/atom/Kconfig.defconfig b/soc/intel/atom/Kconfig.defconfig new file mode 100644 index 00000000000000..35b7deb8e0757c --- /dev/null +++ b/soc/intel/atom/Kconfig.defconfig @@ -0,0 +1,11 @@ +# ATOM SoC configuration options + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ATOM + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 if HPET_TIMER + +endif diff --git a/soc/intel/atom/Kconfig.soc b/soc/intel/atom/Kconfig.soc new file mode 100644 index 00000000000000..63c130640ebae8 --- /dev/null +++ b/soc/intel/atom/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Intel Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ATOM + bool + +config SOC + default "atom" if SOC_ATOM diff --git a/soc/x86/ia32/linker.ld b/soc/intel/atom/linker.ld similarity index 100% rename from soc/x86/ia32/linker.ld rename to soc/intel/atom/linker.ld diff --git a/soc/intel/atom/soc.yml b/soc/intel/atom/soc.yml new file mode 100644 index 00000000000000..456cfe068d71b6 --- /dev/null +++ b/soc/intel/atom/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Atom SoC" +socs: +- name: atom diff --git a/soc/intel/elkhart_lake/CMakeLists.txt b/soc/intel/elkhart_lake/CMakeLists.txt new file mode 100644 index 00000000000000..7db5fbabfc0efc --- /dev/null +++ b/soc/intel/elkhart_lake/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library() +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_cc_option(-march=goldmont) + +zephyr_library_sources(cpu.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/elkhart_lake/Kconfig b/soc/intel/elkhart_lake/Kconfig new file mode 100644 index 00000000000000..6678f3c56e98ea --- /dev/null +++ b/soc/intel/elkhart_lake/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ELKHART_LAKE + select X86 + select X86_64 + select CPU_ATOM + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU diff --git a/soc/intel/elkhart_lake/Kconfig.defconfig b/soc/intel/elkhart_lake/Kconfig.defconfig new file mode 100644 index 00000000000000..c48e6f9d1d8626 --- /dev/null +++ b/soc/intel/elkhart_lake/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Elkhart Lake SoC configuration options + +# Copyright (c) 2018-2020 Intel Corporation +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ELKHART_LAKE + +config PCIE_MMIO_CFG + default y + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_ELKHART_LAKE diff --git a/soc/intel/elkhart_lake/Kconfig.soc b/soc/intel/elkhart_lake/Kconfig.soc new file mode 100644 index 00000000000000..ff1b82106b6a88 --- /dev/null +++ b/soc/intel/elkhart_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2018-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ELKHART_LAKE + bool + +config SOC + default "elkhart_lake" if SOC_ELKHART_LAKE diff --git a/soc/x86/elkhart_lake/cpu.c b/soc/intel/elkhart_lake/cpu.c similarity index 100% rename from soc/x86/elkhart_lake/cpu.c rename to soc/intel/elkhart_lake/cpu.c diff --git a/soc/x86/elkhart_lake/doc/supported_features.txt b/soc/intel/elkhart_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/elkhart_lake/doc/supported_features.txt rename to soc/intel/elkhart_lake/doc/supported_features.txt diff --git a/soc/x86/elkhart_lake/linker.ld b/soc/intel/elkhart_lake/linker.ld similarity index 100% rename from soc/x86/elkhart_lake/linker.ld rename to soc/intel/elkhart_lake/linker.ld diff --git a/soc/x86/elkhart_lake/soc.h b/soc/intel/elkhart_lake/soc.h similarity index 100% rename from soc/x86/elkhart_lake/soc.h rename to soc/intel/elkhart_lake/soc.h diff --git a/soc/intel/elkhart_lake/soc.yml b/soc/intel/elkhart_lake/soc.yml new file mode 100644 index 00000000000000..08a7dbb3854aca --- /dev/null +++ b/soc/intel/elkhart_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Elkhart Lake SoC" +socs: +- name: elkhart_lake diff --git a/soc/x86/elkhart_lake/soc_gpio.h b/soc/intel/elkhart_lake/soc_gpio.h similarity index 100% rename from soc/x86/elkhart_lake/soc_gpio.h rename to soc/intel/elkhart_lake/soc_gpio.h diff --git a/soc/intel/intel_adsp/CMakeLists.txt b/soc/intel/intel_adsp/CMakeLists.txt new file mode 100644 index 00000000000000..45c97d34cfaf88 --- /dev/null +++ b/soc/intel/intel_adsp/CMakeLists.txt @@ -0,0 +1,17 @@ +# Intel ADSP SoCs family CMake file +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(common) + +add_subdirectory(common) +if(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) + zephyr_include_directories(ace) + add_subdirectory(ace) +endif() +if(CONFIG_INTEL_ADSP_CAVS) + zephyr_include_directories(cavs) + add_subdirectory(cavs) +endif() +zephyr_include_directories(common/include) diff --git a/soc/intel/intel_adsp/Kconfig b/soc/intel/intel_adsp/Kconfig new file mode 100644 index 00000000000000..135fecb575aa3e --- /dev/null +++ b/soc/intel/intel_adsp/Kconfig @@ -0,0 +1,132 @@ +# Intel CAVS SoC family configuration options +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ADSP + select WINSTREAM + select ARCH_SUPPORTS_COREDUMP + select CPU_HAS_DCACHE + select ARCH_HAS_USERSPACE if XTENSA_MMU + select CPU_CACHE_INCOHERENT + +if SOC_FAMILY_INTEL_ADSP + +rsource "*/Kconfig" + +DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc +DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc + +config INTEL_ADSP_IPC + bool "Driver for the host IPC interrupt delivery" + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF + default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF + help + Driver for the host IPC interrupt delivery mechanism. + Currently SOF has its own driver for this hardware. + +config MEMORY_WIN_0_SIZE + int "Size of memory window 0" + default 8192 + help + Size of memory window 0. + + This window is used for firmware status & outbox/uplink mbox. + +config MEMORY_WIN_1_SIZE + int "Size of memory window 1" + default 8192 + help + Size of memory window 1. + + This window is used for inbox/downlink mbox. + +config MEMORY_WIN_2_SIZE + int "Size of memory window 2" + default 8192 + help + Size of memory window 2. + + This window is used for debug. + +config MEMORY_WIN_3_SIZE + int "Size of memory window 3" + default 8192 + help + Size of memory window 3. + + This window is used for trace. + +config ADSP_CLOCK + bool + help + Driver for the CAVS clocks. Allow type of clock (and + thus frequency) to be chosen. + +config HP_SRAM_RESERVE + int "Bytes to reserve at start of HP-SRAM" + default 65536 + help + Bytes to reserve at the start of HP-SRAM. Zephyr will not + place any symbols here, though the host windows have + addresses here. The SOF application also makes direct use + of this region, so be very careful changing this value. + +config ADSP_TRACE_SIMCALL + bool "Emit SIMCALL output in addition to window tracing" + help + When true, the trace_out layer will also use a SIMCALL + instruction to emit the passed data to the standard output + of an enclosing simulator process. All window contents will + remain identical. + +config ADSP_NEED_POWER_ON_CACHE + bool + help + Need to power cache SRAM banks on. + +config ADSP_INIT_HPSRAM + bool + default y + help + Need to init HP SRAM. + +config ADSP_POWER_DOWN_HPSRAM + bool + default n if ZTEST + default y + help + Switch off HP SRAM during power down. + +config ADSP_DISABLE_L2CACHE_AT_BOOT + bool + +config ADSP_IMR_CONTEXT_SAVE + bool "Saves FW context into IMR before core is shut down" + default n + help + When true, FW will store its entire context into IMR before + entering D3 state. Later this context can be used to FW restore + when Host power up DSP again. + +config XTENSA_CPU_IDLE_SPIN + bool "Use busy loop for k_cpu_idle" + help + Use a spin loop instead of WAITI for the CPU idle state. + +config XTENSA_WAITI_BUG + bool "Workaround sequence for WAITI bug on LX6" + help + SOF traditionally contains this workaround on its ADSP + platforms which prefixes a WAITI entry with 128 NOP + instructions followed by an ISYNC and EXTW. + +config ADSP_IDLE_CLOCK_GATING + bool "DSP clock gating in Idle" + help + When true, FW will run with enabled clock gating. This options change + HW configuration of a DSP. Evry time core goes to the WAITI state + (wait for interrupt) during idle, the clock can be gated (however, this + does not mean that this will happen). + +endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/intel/intel_adsp/Kconfig.defconfig b/soc/intel/intel_adsp/Kconfig.defconfig new file mode 100644 index 00000000000000..d76faf02defd2e --- /dev/null +++ b/soc/intel/intel_adsp/Kconfig.defconfig @@ -0,0 +1,51 @@ +# Intel CAVS SoC family default configuration options +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_ADSP + +rsource "*/Kconfig.defconfig.series" + +# A workaround for HWMv2 to recover SOF arch/xtensa defaults overridden by arch/host. +if SOF +config CORE_COUNT + int + default MP_MAX_NUM_CPUS +endif + +config XTENSA_RPO_CACHE + def_bool y + +# console can't handle the amount of data coming from many tests, so introduce +# a delay beween testcases. +if ZTEST +config ZTEST_TEST_DELAY_MS + default 100 +endif + +if XTENSA_RPO_CACHE +config XTENSA_CACHED_REGION + default 5 + +config XTENSA_UNCACHED_REGION + default 4 + +endif # XTENSA_RPO_CACHE + +config CONSOLE + def_bool y + +if CONSOLE +config WINSTREAM_CONSOLE + def_bool y +endif + +config CACHE_MANAGEMENT + def_bool y + +choice CACHE_TYPE + default ARCH_CACHE +endchoice + +endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/intel/intel_adsp/Kconfig.soc b/soc/intel/intel_adsp/Kconfig.soc new file mode 100644 index 00000000000000..9df1c63e1a9bab --- /dev/null +++ b/soc/intel/intel_adsp/Kconfig.soc @@ -0,0 +1,12 @@ +# Intel CAVS SoC series selection +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ADSP + bool + +config SOC_FAMILY + default "intel_adsp" if SOC_FAMILY_INTEL_ADSP + +rsource "*/Kconfig.soc" diff --git a/soc/intel/intel_adsp/ace/CMakeLists.txt b/soc/intel/intel_adsp/ace/CMakeLists.txt new file mode 100644 index 00000000000000..78d3d5b9d1e96c --- /dev/null +++ b/soc/intel/intel_adsp/ace/CMakeLists.txt @@ -0,0 +1,22 @@ +# Intel ACE SoC family CMake file +# +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + + +zephyr_library_sources( + sram.c + multiprocessing.c + irq.c + power_down.S + power.c + boot.c + timestamp.c + ) + +zephyr_include_directories(include) +zephyr_include_directories(include/${SOC_TOOLCHAIN_NAME}) +zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c) +zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_adsp/ace/Kconfig b/soc/intel/intel_adsp/ace/Kconfig new file mode 100644 index 00000000000000..162d34daa34698 --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_ACE + select XTENSA + select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) + select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" + select ARCH_HAS_COHERENCE + select SCHED_IPI_SUPPORTED + select DW_ICTL_ACE + select SOC_HAS_RUNTIME_NUM_CPUS + select HAS_PM + +config SOC_INTEL_COMM_WIDGET + bool "Intel Communication Widget driver" + default y + depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED + help + Select this to enable Intel Communication Widget driver. + DSP Communication Widget is a device for generic sideband message transmit/receive. diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm new file mode 100644 index 00000000000000..c9c536f56dd566 --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm @@ -0,0 +1,9 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_INTEL_ACE15_MTPM + +config MP_MAX_NUM_CPUS + default 3 + +endif diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl new file mode 100644 index 00000000000000..2a70da4ac5e422 --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.ace20_lnl @@ -0,0 +1,9 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_INTEL_ACE20_LNL + +config MP_MAX_NUM_CPUS + default 5 + +endif diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series new file mode 100644 index 00000000000000..85d64c3bd0cbfe --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series @@ -0,0 +1,65 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_INTEL_ADSP_ACE + +config SMP + default y + +config POWER_DOMAIN + default y + +# MTL leaves the upper mapping in the same spot as cAVS, but moves the +# lower one inexplicably. +config XTENSA_UNCACHED_REGION + default 2 + +# Parameters for gen_isr_tables.py: + +config 2ND_LVL_INTR_00_OFFSET + default 4 + +config MULTI_LEVEL_INTERRUPTS + default y + +config MAX_IRQ_PER_AGGREGATOR + default 29 + +config NUM_2ND_LEVEL_AGGREGATORS + default 1 + +config 2ND_LVL_ISR_TBL_OFFSET + default 9 + +config 2ND_LEVEL_INTERRUPTS + default y + +config XTENSA_TIMER + default n + +config XTENSA_TIMER_ID + default 0 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 393216000 if XTENSA_TIMER + default 38400000 if INTEL_ADSP_TIMER + +config SYS_CLOCK_TICKS_PER_SEC + default 12000 + +config XTENSA_CCOUNT_HZ + default 393216000 + +config DYNAMIC_INTERRUPTS + default y + +if LOG + +config LOG_BACKEND_ADSP + default y + +endif # LOG + +rsource "Kconfig.defconfig.ace*" + +endif # SOC_SERIES_INTEL_ADSP_ACE diff --git a/soc/intel/intel_adsp/ace/Kconfig.soc b/soc/intel/intel_adsp/ace/Kconfig.soc new file mode 100644 index 00000000000000..3cab72f8f51d8b --- /dev/null +++ b/soc/intel/intel_adsp/ace/Kconfig.soc @@ -0,0 +1,31 @@ +# Copyright (c) 2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_ACE + bool + select SOC_FAMILY_INTEL_ADSP + help + Intel ADSP ACE + +config SOC_INTEL_ACE15_MTPM + bool + select SOC_SERIES_INTEL_ADSP_ACE + help + ACE 1.5 Meteor Lake PCH M + +config SOC_INTEL_ACE20_LNL + bool + select SOC_SERIES_INTEL_ADSP_ACE + help + ACE 2.0 Lunar Lake PCH + +config SOC_SERIES + default "intel_adsp_ace" if SOC_SERIES_INTEL_ADSP_ACE + +config SOC_TOOLCHAIN_NAME + default "intel_ace15_mtpm" if SOC_SERIES_INTEL_ADSP_ACE + +config SOC + default "ace15_mtpm" if SOC_INTEL_ACE15_MTPM + default "ace20_lnl" if SOC_INTEL_ACE20_LNL diff --git a/soc/xtensa/intel_adsp/ace/_soc_inthandlers.h b/soc/intel/intel_adsp/ace/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/_soc_inthandlers.h rename to soc/intel/intel_adsp/ace/_soc_inthandlers.h diff --git a/soc/xtensa/intel_adsp/ace/ace-link.ld b/soc/intel/intel_adsp/ace/ace-link.ld similarity index 100% rename from soc/xtensa/intel_adsp/ace/ace-link.ld rename to soc/intel/intel_adsp/ace/ace-link.ld diff --git a/soc/xtensa/intel_adsp/ace/asm_memory_management.h b/soc/intel/intel_adsp/ace/asm_memory_management.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/asm_memory_management.h rename to soc/intel/intel_adsp/ace/asm_memory_management.h diff --git a/soc/xtensa/intel_adsp/ace/boot.c b/soc/intel/intel_adsp/ace/boot.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/boot.c rename to soc/intel/intel_adsp/ace/boot.c diff --git a/soc/xtensa/intel_adsp/ace/comm_widget.c b/soc/intel/intel_adsp/ace/comm_widget.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/comm_widget.c rename to soc/intel/intel_adsp/ace/comm_widget.c diff --git a/soc/xtensa/intel_adsp/ace/comm_widget.h b/soc/intel/intel_adsp/ace/comm_widget.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/comm_widget.h rename to soc/intel/intel_adsp/ace/comm_widget.h diff --git a/soc/xtensa/intel_adsp/ace/comm_widget_messages.c b/soc/intel/intel_adsp/ace/comm_widget_messages.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/comm_widget_messages.c rename to soc/intel/intel_adsp/ace/comm_widget_messages.c diff --git a/soc/xtensa/intel_adsp/ace/include/adsp_imr_layout.h b/soc/intel/intel_adsp/ace/include/adsp_imr_layout.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/adsp_imr_layout.h rename to soc/intel/intel_adsp/ace/include/adsp_imr_layout.h diff --git a/soc/xtensa/intel_adsp/ace/include/adsp_timestamp.h b/soc/intel/intel_adsp/ace/include/adsp_timestamp.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/adsp_timestamp.h rename to soc/intel/intel_adsp/ace/include/adsp_timestamp.h diff --git a/soc/xtensa/intel_adsp/ace/include/dmic_regs.h b/soc/intel/intel_adsp/ace/include/dmic_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/dmic_regs.h rename to soc/intel/intel_adsp/ace/include/dmic_regs.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_comm_widget.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_interrupt.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_ipc_regs.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_memory_regions.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_power.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/adsp_watchdog.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h b/soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h rename to soc/intel/intel_adsp/ace/include/intel_ace15_mtpm/dmic_regs_ace1x.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_boot.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_interrupt.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_ipc_regs.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_memory_regions.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_power.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h b/soc/intel/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h rename to soc/intel/intel_adsp/ace/include/intel_ace20_lnl/dmic_regs_ace2x.h diff --git a/soc/xtensa/intel_adsp/ace/irq.c b/soc/intel/intel_adsp/ace/irq.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/irq.c rename to soc/intel/intel_adsp/ace/irq.c diff --git a/soc/xtensa/intel_adsp/ace/linker.ld b/soc/intel/intel_adsp/ace/linker.ld similarity index 100% rename from soc/xtensa/intel_adsp/ace/linker.ld rename to soc/intel/intel_adsp/ace/linker.ld diff --git a/soc/xtensa/intel_adsp/ace/multiprocessing.c b/soc/intel/intel_adsp/ace/multiprocessing.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/multiprocessing.c rename to soc/intel/intel_adsp/ace/multiprocessing.c diff --git a/soc/xtensa/intel_adsp/ace/pmc_interface.h b/soc/intel/intel_adsp/ace/pmc_interface.h similarity index 100% rename from soc/xtensa/intel_adsp/ace/pmc_interface.h rename to soc/intel/intel_adsp/ace/pmc_interface.h diff --git a/soc/xtensa/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/power.c rename to soc/intel/intel_adsp/ace/power.c diff --git a/soc/xtensa/intel_adsp/ace/power_down.S b/soc/intel/intel_adsp/ace/power_down.S similarity index 100% rename from soc/xtensa/intel_adsp/ace/power_down.S rename to soc/intel/intel_adsp/ace/power_down.S diff --git a/soc/xtensa/intel_adsp/ace/sram.c b/soc/intel/intel_adsp/ace/sram.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/sram.c rename to soc/intel/intel_adsp/ace/sram.c diff --git a/soc/xtensa/intel_adsp/ace/timestamp.c b/soc/intel/intel_adsp/ace/timestamp.c similarity index 100% rename from soc/xtensa/intel_adsp/ace/timestamp.c rename to soc/intel/intel_adsp/ace/timestamp.c diff --git a/soc/intel/intel_adsp/cavs/CMakeLists.txt b/soc/intel/intel_adsp/cavs/CMakeLists.txt new file mode 100644 index 00000000000000..5c253147aeeeda --- /dev/null +++ b/soc/intel/intel_adsp/cavs/CMakeLists.txt @@ -0,0 +1,22 @@ +# Intel ADSP SoCs family CMake file +# +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) +zephyr_include_directories(include/${SOC_TOOLCHAIN_NAME}) +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_library_sources( + sram.c + power.c + power_down_cavs.S + ) + +if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) + zephyr_library_sources(multiprocessing.c) +endif() + +zephyr_library_sources_ifdef(CONFIG_CAVS_ICTL irq.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-cavs-linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_adsp/cavs/Kconfig b/soc/intel/intel_adsp/cavs/Kconfig new file mode 100644 index 00000000000000..01d325cc325468 --- /dev/null +++ b/soc/intel/intel_adsp/cavs/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2017,2022-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_CAVS + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" + select ATOMIC_OPERATIONS_ARCH if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc" + select ARCH_HAS_COHERENCE + select HAS_PM + +config SOC_INTEL_CAVS_V25 + select XTENSA_WAITI_BUG + select SCHED_IPI_SUPPORTED diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 similarity index 88% rename from soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 rename to soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 index f983aa27bb7094..ad6fa8baac6893 100644 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 +++ b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.cavs_v25 @@ -1,15 +1,8 @@ -# Copyright (c) 2020,2022 Intel Corporation +# Copyright (c) 2020,2022-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 if SOC_INTEL_CAVS_V25 -config SOC_TOOLCHAIN_NAME - string - default "intel_tgl_adsp" - -config SOC - default "intel_tgl_adsp" - # For backward compatibility, to be removed config SOC_SERIES_INTEL_CAVS_V25 def_bool y diff --git a/soc/intel/intel_adsp/cavs/Kconfig.defconfig.series b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.series new file mode 100644 index 00000000000000..6b39e8bc930ae3 --- /dev/null +++ b/soc/intel/intel_adsp/cavs/Kconfig.defconfig.series @@ -0,0 +1,47 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_INTEL_ADSP_CAVS + +config INTEL_ADSP_CAVS + def_bool y + +rsource "Kconfig.defconfig.cavs*" + +config DMA_INTEL_ADSP_GPDMA + default y + depends on DMA + +config XTENSA_CCOUNT_HZ + default 400000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config SMP + default y + +config XTENSA_TIMER + default n + +config KERNEL_ENTRY + default "_MainEntry" + +config MULTI_LEVEL_INTERRUPTS + default y + +config 2ND_LEVEL_INTERRUPTS + default y + +config DYNAMIC_INTERRUPTS + default y + +if LOG + +config LOG_BACKEND_ADSP + default y + +endif # LOG + +endif # SOC_SERIES_INTEL_ADSP_CAVS diff --git a/soc/intel/intel_adsp/cavs/Kconfig.soc b/soc/intel/intel_adsp/cavs/Kconfig.soc new file mode 100644 index 00000000000000..40bac2f99ccbc3 --- /dev/null +++ b/soc/intel/intel_adsp/cavs/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2020-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ADSP_CAVS + bool + select SOC_FAMILY_INTEL_ADSP + help + Intel ADSP CAVS + +config SOC_SERIES + default "intel_adsp_cavs" if SOC_SERIES_INTEL_ADSP_CAVS + +config SOC_INTEL_CAVS_V25 + bool + select SOC_SERIES_INTEL_ADSP_CAVS + help + Intel Tiger Lake + +config SOC + default "cavs25" if SOC_INTEL_CAVS_V25 + +config SOC_TOOLCHAIN_NAME + default "intel_tgl_adsp" if SOC_INTEL_CAVS_V25 diff --git a/soc/xtensa/intel_adsp/common/include/_soc_inthandlers.h b/soc/intel/intel_adsp/cavs/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/_soc_inthandlers.h rename to soc/intel/intel_adsp/cavs/_soc_inthandlers.h diff --git a/soc/xtensa/intel_adsp/cavs/asm_ldo_management.h b/soc/intel/intel_adsp/cavs/asm_ldo_management.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/asm_ldo_management.h rename to soc/intel/intel_adsp/cavs/asm_ldo_management.h diff --git a/soc/xtensa/intel_adsp/cavs/asm_memory_management.h b/soc/intel/intel_adsp/cavs/asm_memory_management.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/asm_memory_management.h rename to soc/intel/intel_adsp/cavs/asm_memory_management.h diff --git a/soc/xtensa/intel_adsp/cavs/include/adsp_interrupt.h b/soc/intel/intel_adsp/cavs/include/adsp_interrupt.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/adsp_interrupt.h rename to soc/intel/intel_adsp/cavs/include/adsp_interrupt.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_imr_layout.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_ipc_regs.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_memory.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/adsp_shim.h diff --git a/soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h b/soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h rename to soc/intel/intel_adsp/cavs/include/intel_tgl_adsp/dmic_regs.h diff --git a/soc/xtensa/intel_adsp/cavs/include/xtensa-cavs-linker.ld b/soc/intel/intel_adsp/cavs/include/xtensa-cavs-linker.ld similarity index 100% rename from soc/xtensa/intel_adsp/cavs/include/xtensa-cavs-linker.ld rename to soc/intel/intel_adsp/cavs/include/xtensa-cavs-linker.ld diff --git a/soc/xtensa/intel_adsp/cavs/irq.c b/soc/intel/intel_adsp/cavs/irq.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/irq.c rename to soc/intel/intel_adsp/cavs/irq.c diff --git a/soc/xtensa/intel_adsp/cavs/multiprocessing.c b/soc/intel/intel_adsp/cavs/multiprocessing.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/multiprocessing.c rename to soc/intel/intel_adsp/cavs/multiprocessing.c diff --git a/soc/xtensa/intel_adsp/cavs/power.c b/soc/intel/intel_adsp/cavs/power.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/power.c rename to soc/intel/intel_adsp/cavs/power.c diff --git a/soc/xtensa/intel_adsp/cavs/power_down_cavs.S b/soc/intel/intel_adsp/cavs/power_down_cavs.S similarity index 100% rename from soc/xtensa/intel_adsp/cavs/power_down_cavs.S rename to soc/intel/intel_adsp/cavs/power_down_cavs.S diff --git a/soc/xtensa/intel_adsp/cavs/sram.c b/soc/intel/intel_adsp/cavs/sram.c similarity index 100% rename from soc/xtensa/intel_adsp/cavs/sram.c rename to soc/intel/intel_adsp/cavs/sram.c diff --git a/soc/intel/intel_adsp/common/CMakeLists.txt b/soc/intel/intel_adsp/common/CMakeLists.txt new file mode 100644 index 00000000000000..11d8ca67c8b197 --- /dev/null +++ b/soc/intel/intel_adsp/common/CMakeLists.txt @@ -0,0 +1,149 @@ +# Intel CAVS SoC family CMake file +# +# Copyright (c) 2020-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_interface_library_named(INTEL_ADSP_COMMON) + +zephyr_library_named(intel_adsp_common) +zephyr_include_directories(include) +zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_IPC ipc.c) + +zephyr_library_sources( + rimage_modules.c + boot.c + soc.c + mem_window.c + boot_complete.c + ) + +zephyr_library_sources_ifdef(CONFIG_ADSP_CLOCK clk.c) + +if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) + zephyr_library_sources(multiprocessing.c) +endif() + +zephyr_library_link_libraries(INTEL_ADSP_COMMON) + +target_include_directories(INTEL_ADSP_COMMON INTERFACE include) +target_link_libraries(INTEL_ADSP_COMMON INTERFACE intel_adsp_common) + +set(KERNEL_REMAPPED ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}-remapped.elf) +set(EXTMAN ${CMAKE_BINARY_DIR}/zephyr/extman.bin) + +if(${CMAKE_HOST_WIN32}) + set(NULL_FILE nul) +elseif(${CMAKE_HOST_UNIX}) + set(NULL_FILE /dev/null) +endif() + +# Generate rimage modules from the base kernel ELF file. Note the +# warning squashing on the objcopy steps. Binutils has a misfeature +# where if the copy removes all the sections from an input ELF program +# header (our link generates lots of phdrs because of the disjoint +# cacheability addresses), it will warn about an "empty" segment even +# though it was TOLD to drop the contents! +# +# Also note that rimage is picky with section flags: it will try to +# include a section in the output data (even its own metadata in +# .module!) if it has any of ALLOC, WRITABLE or EXEC flags in the ELF +# file. The GNU linker will set these automatically based on the +# flags of the sections coming out of C code, so this is fragile and +# breaks easily. Set noload flags explicitly here. +add_custom_target( + gen_modules ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod +) + +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod + COMMENT "Extracting .mod(ule) files for rimage" + DEPENDS ${ZEPHYR_FINAL_EXECUTABLE} ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} + + # The .fw_metadata section may not be present (xcc's older linker + # will remove it if empty). Extract it here (which will create an + # empty file if not present) and add it back when we generate the + # main.mod file below. + COMMAND ${CMAKE_OBJCOPY} -O binary --only-section=.fw_metadata + ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${EXTMAN} + + # Remap uncached section addresses so they appear contiguous + COMMAND ${CMAKE_COMMAND} -E + copy ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${KERNEL_REMAPPED} + + # Extract modules for rimage + COMMAND ${CMAKE_OBJCOPY} + --only-section .imr + --only-section .imrdata + --only-section .module.boot + --set-section-flags .module.boot=noload,readonly + --rename-section .module.boot=.module + ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/boot.mod 2>${NULL_FILE} + + # Remove .fw_metadata here... + COMMAND ${CMAKE_OBJCOPY} + --remove-section .imr + --remove-section .imrdata + --remove-section .module.boot + --remove-section .fw_metadata + --set-section-flags .module.main=noload,readonly + --set-section-flags .static_uuid_entries=noload,readonly + --set-section-flags .static_log_entries=noload,readonly + --rename-section .module.main=.module + ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} + + # ...and copy it back in + COMMAND ${CMAKE_OBJCOPY} + --add-section .fw_metadata=${EXTMAN} + --set-section-flags .fw_metadata=noload,readonly + ${CMAKE_BINARY_DIR}/zephyr/main.mod + ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} +) + +if(CONFIG_BUILD_OUTPUT_STRIPPED) +add_custom_command( + COMMENT "strip main.mod" + APPEND OUTPUT ${CMAKE_BINARY_DIR}/zephyr/main.mod + COMMAND $ + $ + $ + $${CMAKE_BINARY_DIR}/zephyr/main.mod + $${CMAKE_BINARY_DIR}/zephyr/main-stripped.mod + $ +) +endif() + + +# west sign +add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri +) + +# If some of your board(s) need to override default rimage parameters +# then you can define WEST_SIGN_OPTS in boards/my/board/board.cmake. +# Example: +# +# set(WEST_SIGN_OPTS -- -c "/home/sweet home/rimage/config/abc.toml" -i 4) + +# Parameters after the double dash -- are passed through to rimage. For +# other ways to override default rimage parameters check +# boards/intel/adsp/doc/intel_adsp_generic.rst + +# Warning: because `west sign` can also be used interactively, using +# ${WEST_SIGN_OPTS} like this has _higher_ precedence than `west config +# rimage.extra-args`! Avoid overriding default rimage parameters in +# multiple places to avoid unexpected precedence rules. +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + # Use --if-tool-available so we don't force every CI to install + # rimage. We don't want to break build-only and other tests that don't + # require signing. When rimage is missing, `west flash` fails with a + # clear "zephyr.ri missing" error with an "rimage not found" warning + # from west sign immediately before it. + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS gen_modules + ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod +) diff --git a/soc/xtensa/intel_adsp/common/boot.c b/soc/intel/intel_adsp/common/boot.c similarity index 98% rename from soc/xtensa/intel_adsp/common/boot.c rename to soc/intel/intel_adsp/common/boot.c index 75eed9d63b00a9..ad7f91eec7d7a9 100644 --- a/soc/xtensa/intel_adsp/common/boot.c +++ b/soc/intel/intel_adsp/common/boot.c @@ -44,7 +44,7 @@ #define MANIFEST_SEGMENT_COUNT 3 /* FIXME: Use Kconfig or some other means */ -#if !defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if !defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) #define RESET_MEMORY_HOLE #endif diff --git a/soc/xtensa/intel_adsp/common/boot_complete.c b/soc/intel/intel_adsp/common/boot_complete.c similarity index 100% rename from soc/xtensa/intel_adsp/common/boot_complete.c rename to soc/intel/intel_adsp/common/boot_complete.c diff --git a/soc/xtensa/intel_adsp/common/clk.c b/soc/intel/intel_adsp/common/clk.c similarity index 96% rename from soc/xtensa/intel_adsp/common/clk.c rename to soc/intel/intel_adsp/common/clk.c index 0f3f3d32b80ed5..f9a35a3c0184e6 100644 --- a/soc/xtensa/intel_adsp/common/clk.c +++ b/soc/intel/intel_adsp/common/clk.c @@ -26,7 +26,7 @@ static void select_cpu_clock_hw(uint32_t freq_idx) { uint32_t enc = adsp_clock_freq_enc[freq_idx]; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE uint32_t clk_ctl = ADSP_CLKCTL; clk_ctl &= ~ADSP_CLKCTL_OSC_SOURCE_MASK; @@ -89,7 +89,7 @@ void adsp_clock_init(void) int i; #ifdef ADSP_CLOCK_HAS_WOVCRO -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DfPMCCU.dfclkctl |= ACE_CLKCTL_WOVCRO; if (ACE_DfPMCCU.dfclkctl & ACE_CLKCTL_WOVCRO) { ACE_DfPMCCU.dfclkctl = ACE_DfPMCCU.dfclkctl & ~ACE_CLKCTL_WOVCRO; @@ -103,7 +103,7 @@ void adsp_clock_init(void) } else { platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_LPRO; } -#endif /* CONFIG_SOC_SERIES_INTEL_ACE */ +#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE */ #endif /* ADSP_CLOCK_HAS_WOVCRO */ unsigned int num_cpus = arch_num_cpus(); diff --git a/soc/xtensa/intel_adsp/common/include/adsp-vectors.h b/soc/intel/intel_adsp/common/include/adsp-vectors.h similarity index 95% rename from soc/xtensa/intel_adsp/common/include/adsp-vectors.h rename to soc/intel/intel_adsp/common/include/adsp-vectors.h index 383dce93aa3ebf..01e660e43ea657 100644 --- a/soc/xtensa/intel_adsp/common/include/adsp-vectors.h +++ b/soc/intel/intel_adsp/common/include/adsp-vectors.h @@ -24,13 +24,13 @@ #define INTLEVEL4_VECTOR_PADDR_SRAM \ (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL4_VECOFS) -#ifndef SOC_SERIES_INTEL_ACE +#ifndef SOC_SERIES_INTEL_ADSP_ACE #define INTLEVEL5_VECTOR_PADDR_SRAM \ (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL5_VECOFS) #define INTLEVEL6_VECTOR_PADDR_SRAM \ (VECBASE_RESET_PADDR_SRAM + XCHAL_INTLEVEL6_VECOFS) -#endif /* SOC_SERIES_INTEL_ACE */ +#endif /* SOC_SERIES_INTEL_ADSP_ACE */ #define INTLEVEL7_VECTOR_PADDR_SRAM \ diff --git a/soc/xtensa/intel_adsp/common/include/adsp_clk.h b/soc/intel/intel_adsp/common/include/adsp_clk.h similarity index 98% rename from soc/xtensa/intel_adsp/common/include/adsp_clk.h rename to soc/intel/intel_adsp/common/include/adsp_clk.h index 34d7c21822dda1..ccfb5cdc7e7ad6 100644 --- a/soc/xtensa/intel_adsp/common/include/adsp_clk.h +++ b/soc/intel/intel_adsp/common/include/adsp_clk.h @@ -36,7 +36,7 @@ int adsp_clock_set_cpu_freq(uint32_t freq_idx); struct adsp_cpu_clock_info *adsp_cpu_clocks_get(void); /* Device tree defined constants */ -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE #define ADSP_CLKCTL ACE_DfPMCCU.dfclkctl #else #define ADSP_CLKCTL CAVS_SHIM.clkctl diff --git a/soc/xtensa/intel_adsp/common/include/adsp_debug_window.h b/soc/intel/intel_adsp/common/include/adsp_debug_window.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/adsp_debug_window.h rename to soc/intel/intel_adsp/common/include/adsp_debug_window.h diff --git a/soc/xtensa/intel_adsp/common/include/cavs-idc.h b/soc/intel/intel_adsp/common/include/cavs-idc.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/cavs-idc.h rename to soc/intel/intel_adsp/common/include/cavs-idc.h diff --git a/soc/xtensa/intel_adsp/common/include/cavstool.h b/soc/intel/intel_adsp/common/include/cavstool.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/cavstool.h rename to soc/intel/intel_adsp/common/include/cavstool.h diff --git a/soc/xtensa/intel_adsp/common/include/cpu_init.h b/soc/intel/intel_adsp/common/include/cpu_init.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/cpu_init.h rename to soc/intel/intel_adsp/common/include/cpu_init.h diff --git a/soc/xtensa/intel_adsp/common/include/debug_helpers.h b/soc/intel/intel_adsp/common/include/debug_helpers.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/debug_helpers.h rename to soc/intel/intel_adsp/common/include/debug_helpers.h diff --git a/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h b/soc/intel/intel_adsp/common/include/intel_adsp_hda.h similarity index 99% rename from soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h rename to soc/intel/intel_adsp/common/include/intel_adsp_hda.h index f56c77e2523086..628a84cd1a01df 100644 --- a/soc/xtensa/intel_adsp/common/include/intel_adsp_hda.h +++ b/soc/intel/intel_adsp/common/include/intel_adsp_hda.h @@ -446,14 +446,14 @@ static inline void intel_adsp_hda_disable_buffer_interrupt(uint32_t base, uint32 static inline void intel_adsp_force_dmi_l0_state(void) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DfPMCCH.svcfg |= ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT; #endif } static inline void intel_adsp_allow_dmi_l1_state(void) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE ACE_DfPMCCH.svcfg &= ~(ADSP_FORCE_DECOUPLED_HDMA_L1_EXIT_BIT); #endif } diff --git a/soc/xtensa/intel_adsp/common/include/intel_adsp_ipc.h b/soc/intel/intel_adsp/common/include/intel_adsp_ipc.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/intel_adsp_ipc.h rename to soc/intel/intel_adsp/common/include/intel_adsp_ipc.h diff --git a/soc/xtensa/intel_adsp/common/include/intel_adsp_ipc_devtree.h b/soc/intel/intel_adsp/common/include/intel_adsp_ipc_devtree.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/intel_adsp_ipc_devtree.h rename to soc/intel/intel_adsp/common/include/intel_adsp_ipc_devtree.h diff --git a/soc/xtensa/intel_adsp/common/include/manifest.h b/soc/intel/intel_adsp/common/include/manifest.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/manifest.h rename to soc/intel/intel_adsp/common/include/manifest.h diff --git a/soc/xtensa/intel_adsp/common/include/mem_window.h b/soc/intel/intel_adsp/common/include/mem_window.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/mem_window.h rename to soc/intel/intel_adsp/common/include/mem_window.h diff --git a/soc/xtensa/intel_adsp/common/include/soc.h b/soc/intel/intel_adsp/common/include/soc.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/soc.h rename to soc/intel/intel_adsp/common/include/soc.h diff --git a/soc/xtensa/intel_adsp/common/include/soc_util.h b/soc/intel/intel_adsp/common/include/soc_util.h similarity index 100% rename from soc/xtensa/intel_adsp/common/include/soc_util.h rename to soc/intel/intel_adsp/common/include/soc_util.h diff --git a/soc/xtensa/intel_adsp/common/ipc.c b/soc/intel/intel_adsp/common/ipc.c similarity index 98% rename from soc/xtensa/intel_adsp/common/ipc.c rename to soc/intel/intel_adsp/common/ipc.c index 6ae1956ffac389..a73d696a68a49e 100644 --- a/soc/xtensa/intel_adsp/common/ipc.c +++ b/soc/intel/intel_adsp/common/ipc.c @@ -55,7 +55,7 @@ void z_intel_adsp_ipc_isr(const void *devarg) regs->tdr = INTEL_ADSP_IPC_BUSY; if (done) { -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; #else regs->tda = INTEL_ADSP_IPC_DONE; @@ -100,7 +100,7 @@ int intel_adsp_ipc_init(const struct device *dev) */ config->regs->tdr = INTEL_ADSP_IPC_BUSY; config->regs->ida = INTEL_ADSP_IPC_DONE; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; #else config->regs->tda = INTEL_ADSP_IPC_DONE; @@ -115,7 +115,7 @@ void intel_adsp_ipc_complete(const struct device *dev) { const struct intel_adsp_ipc_config *config = dev->config; -#ifdef CONFIG_SOC_SERIES_INTEL_ACE +#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE config->regs->tda = INTEL_ADSP_IPC_ACE1X_TDA_DONE; #else config->regs->tda = INTEL_ADSP_IPC_DONE; @@ -208,7 +208,7 @@ void intel_adsp_ipc_send_message_emergency(const struct device *dev, uint32_t da #if DT_NODE_EXISTS(INTEL_ADSP_IPC_HOST_DTNODE) -#if defined(CONFIG_SOC_SERIES_INTEL_ACE) +#if defined(CONFIG_SOC_SERIES_INTEL_ADSP_ACE) static inline void ace_ipc_intc_unmask(void) { ACE_DINT[0].ie[ACE_INTL_HIPC] = BIT(0); diff --git a/soc/xtensa/intel_adsp/common/mem_window.c b/soc/intel/intel_adsp/common/mem_window.c similarity index 100% rename from soc/xtensa/intel_adsp/common/mem_window.c rename to soc/intel/intel_adsp/common/mem_window.c diff --git a/soc/xtensa/intel_adsp/common/multiprocessing.c b/soc/intel/intel_adsp/common/multiprocessing.c similarity index 100% rename from soc/xtensa/intel_adsp/common/multiprocessing.c rename to soc/intel/intel_adsp/common/multiprocessing.c diff --git a/soc/xtensa/intel_adsp/common/rimage_modules.c b/soc/intel/intel_adsp/common/rimage_modules.c similarity index 100% rename from soc/xtensa/intel_adsp/common/rimage_modules.c rename to soc/intel/intel_adsp/common/rimage_modules.c diff --git a/soc/xtensa/intel_adsp/common/soc.c b/soc/intel/intel_adsp/common/soc.c similarity index 100% rename from soc/xtensa/intel_adsp/common/soc.c rename to soc/intel/intel_adsp/common/soc.c diff --git a/soc/intel/intel_adsp/soc.yml b/soc/intel/intel_adsp/soc.yml new file mode 100644 index 00000000000000..757750eeb379d8 --- /dev/null +++ b/soc/intel/intel_adsp/soc.yml @@ -0,0 +1,10 @@ +family: + - name: intel_adsp + series: + - name: intel_adsp_ace + socs: + - name: ace15_mtpm + - name: ace20_lnl + - name: intel_adsp_cavs + socs: + - name: cavs25 diff --git a/soc/xtensa/intel_adsp/tools/acetool.py b/soc/intel/intel_adsp/tools/acetool.py similarity index 99% rename from soc/xtensa/intel_adsp/tools/acetool.py rename to soc/intel/intel_adsp/tools/acetool.py index 0d0897c0234258..9dd184b9685fdb 100755 --- a/soc/xtensa/intel_adsp/tools/acetool.py +++ b/soc/intel/intel_adsp/tools/acetool.py @@ -35,6 +35,8 @@ INBOX_OFFSET = (512 + (1 * 128)) * 1024 WINSTREAM_OFFSET = WINDOW_BASE + WINDOW_STRIDE*3 +# pylint: disable=duplicate-code + # ADSPCS bits CRST = 0 CSTALL = 8 diff --git a/soc/xtensa/intel_adsp/tools/cavstool.py b/soc/intel/intel_adsp/tools/cavstool.py similarity index 99% rename from soc/xtensa/intel_adsp/tools/cavstool.py rename to soc/intel/intel_adsp/tools/cavstool.py index a28d3c203210ab..97ce9134379105 100755 --- a/soc/xtensa/intel_adsp/tools/cavstool.py +++ b/soc/intel/intel_adsp/tools/cavstool.py @@ -31,6 +31,8 @@ INBOX_OFFSET = (512 + (1 * 128)) * 1024 WINSTREAM_OFFSET = (512 + (3 * 128)) * 1024 +# pylint: disable=duplicate-code + # ADSPCS bits CRST = 0 CSTALL = 8 diff --git a/soc/xtensa/intel_adsp/tools/cavstool_client.py b/soc/intel/intel_adsp/tools/cavstool_client.py similarity index 100% rename from soc/xtensa/intel_adsp/tools/cavstool_client.py rename to soc/intel/intel_adsp/tools/cavstool_client.py diff --git a/soc/xtensa/intel_adsp/tools/cavstwist.sh b/soc/intel/intel_adsp/tools/cavstwist.sh similarity index 94% rename from soc/xtensa/intel_adsp/tools/cavstwist.sh rename to soc/intel/intel_adsp/tools/cavstwist.sh index d965ff26ca3392..89af3434317e77 100755 --- a/soc/xtensa/intel_adsp/tools/cavstwist.sh +++ b/soc/intel/intel_adsp/tools/cavstwist.sh @@ -1,5 +1,5 @@ #!/bin/sh -# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2022-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 set -e @@ -12,9 +12,9 @@ set -e # export CAVS_KEY=$HOME/otc_private_key_3k.pem # export CAVS_RIMAGE=$HOME/rimage # -# twister -p intel_adsp_cavs25 --device-testing \ -# --device-serial-pty=$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstwist.sh \ -# --west-flash=$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstwist.sh +# twister -p intel_adsp/cavs25 --device-testing \ +# --device-serial-pty=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstwist.sh \ +# --west-flash=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstwist.sh # # The CAVS_OLD_FLASHER is necessary because now the client-server-based # cavstool works by default. This is to tell the build system to use @@ -80,7 +80,7 @@ fi ######################################################################## -CAVSTOOL=$ZEPHYR_BASE/soc/xtensa/intel_adsp/tools/cavstool.py +CAVSTOOL=$ZEPHYR_BASE/soc/intel/intel_adsp/tools/cavstool.py IMAGE=$ZEPHYR_BASE/_cavstmp.ri IMAGE2=$ZEPHYR_BASE/_cavstmp2.ri diff --git a/soc/xtensa/intel_adsp/tools/remote-fw-service.py b/soc/intel/intel_adsp/tools/remote-fw-service.py similarity index 99% rename from soc/xtensa/intel_adsp/tools/remote-fw-service.py rename to soc/intel/intel_adsp/tools/remote-fw-service.py index 21e3569721caf2..1d68a7db2a1d8f 100755 --- a/soc/xtensa/intel_adsp/tools/remote-fw-service.py +++ b/soc/intel/intel_adsp/tools/remote-fw-service.py @@ -17,6 +17,8 @@ # Global variable use to sync between log and request services. runner = None +# pylint: disable=duplicate-code + # INADDR_ANY as default HOST = '' PORT_LOG = 9999 diff --git a/soc/x86/intel_ish/CMakeLists.txt b/soc/intel/intel_ish/CMakeLists.txt similarity index 100% rename from soc/x86/intel_ish/CMakeLists.txt rename to soc/intel/intel_ish/CMakeLists.txt diff --git a/soc/intel/intel_ish/Kconfig b/soc/intel/intel_ish/Kconfig new file mode 100644 index 00000000000000..31568e85d65d61 --- /dev/null +++ b/soc/intel/intel_ish/Kconfig @@ -0,0 +1,15 @@ +# Intel ISH family configuration options +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ISH + select X86 + select X86_NO_SPECULATIVE_VULNERABILITIES + select IOAPIC + select LOAPIC + select CPU_HAS_FPU + select INTEL_HAL + select HAS_PM + select HAS_COVERAGE_SUPPORT diff --git a/soc/intel/intel_ish/Kconfig.defconfig b/soc/intel/intel_ish/Kconfig.defconfig new file mode 100644 index 00000000000000..e944782809e842 --- /dev/null +++ b/soc/intel/intel_ish/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Intel ISH family default configuration options +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_ISH + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 if HPET_TIMER + +config X86_VERY_EARLY_CONSOLE + default n + +config SRAM_OFFSET + hex + default 0x0 + +# Target platforms are not PC-compatible +# (e.g. without BIOS, ACPI, CMOS, etc.). +config X86_PC_COMPATIBLE + default n + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_INTEL_ISH diff --git a/soc/intel/intel_ish/Kconfig.soc b/soc/intel/intel_ish/Kconfig.soc new file mode 100644 index 00000000000000..c08d5f15f4ae8f --- /dev/null +++ b/soc/intel/intel_ish/Kconfig.soc @@ -0,0 +1,13 @@ +# Intel ISH family selection +# +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_ISH + bool + +config SOC_FAMILY + default "intel_ish" if SOC_FAMILY_INTEL_ISH + +rsource "*/Kconfig.soc" diff --git a/soc/x86/intel_ish/doc/supported_features.txt b/soc/intel/intel_ish/doc/supported_features.txt similarity index 100% rename from soc/x86/intel_ish/doc/supported_features.txt rename to soc/intel/intel_ish/doc/supported_features.txt diff --git a/soc/intel/intel_ish/intel_ish5/CMakeLists.txt b/soc/intel/intel_ish/intel_ish5/CMakeLists.txt new file mode 100644 index 00000000000000..dce4b9cc906236 --- /dev/null +++ b/soc/intel/intel_ish/intel_ish5/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) + +zephyr_cc_option(-march=pentium -mtune=i486) + +zephyr_sources(soc.c) +add_subdirectory_ifdef(CONFIG_PM pm) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") + +include(../utils/build_ish_firmware.cmake) diff --git a/soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series b/soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series new file mode 100644 index 00000000000000..8b8fea9f29ac0c --- /dev/null +++ b/soc/intel/intel_ish/intel_ish5/Kconfig.defconfig.series @@ -0,0 +1,10 @@ +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_INTEL_ISH5 + +rsource "pm/Kconfig.pm" + +endif # SOC_SERIES_INTEL_ISH5 diff --git a/soc/intel/intel_ish/intel_ish5/Kconfig.soc b/soc/intel/intel_ish/intel_ish5/Kconfig.soc new file mode 100644 index 00000000000000..37c1990ca3f382 --- /dev/null +++ b/soc/intel/intel_ish/intel_ish5/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_INTEL_ISH5 + bool + select SOC_FAMILY_INTEL_ISH + +config SOC_SERIES + default "intel_ish5" if SOC_SERIES_INTEL_ISH5 + +config SOC_INTEL_ISH_5_4_1 + bool + select SOC_SERIES_INTEL_ISH5 + +config SOC_INTEL_ISH_5_6_0 + bool + select SOC_SERIES_INTEL_ISH5 + +config SOC_INTEL_ISH_5_8_0 + bool + select SOC_SERIES_INTEL_ISH5 + +config SOC + default "intel_ish_5_4_1" if SOC_INTEL_ISH_5_4_1 + default "intel_ish_5_6_0" if SOC_INTEL_ISH_5_6_0 + default "intel_ish_5_8_0" if SOC_INTEL_ISH_5_8_0 diff --git a/soc/x86/intel_ish/intel_ish5/linker.ld b/soc/intel/intel_ish/intel_ish5/linker.ld similarity index 100% rename from soc/x86/intel_ish/intel_ish5/linker.ld rename to soc/intel/intel_ish/intel_ish5/linker.ld diff --git a/soc/x86/intel_ish/intel_ish5/pm/CMakeLists.txt b/soc/intel/intel_ish/intel_ish5/pm/CMakeLists.txt similarity index 100% rename from soc/x86/intel_ish/intel_ish5/pm/CMakeLists.txt rename to soc/intel/intel_ish/intel_ish5/pm/CMakeLists.txt diff --git a/soc/x86/intel_ish/intel_ish5/pm/Kconfig.pm b/soc/intel/intel_ish/intel_ish5/pm/Kconfig.pm similarity index 100% rename from soc/x86/intel_ish/intel_ish5/pm/Kconfig.pm rename to soc/intel/intel_ish/intel_ish5/pm/Kconfig.pm diff --git a/soc/x86/intel_ish/intel_ish5/pm/power.c b/soc/intel/intel_ish/intel_ish5/pm/power.c similarity index 100% rename from soc/x86/intel_ish/intel_ish5/pm/power.c rename to soc/intel/intel_ish/intel_ish5/pm/power.c diff --git a/soc/x86/intel_ish/intel_ish5/soc.c b/soc/intel/intel_ish/intel_ish5/soc.c similarity index 100% rename from soc/x86/intel_ish/intel_ish5/soc.c rename to soc/intel/intel_ish/intel_ish5/soc.c diff --git a/soc/x86/intel_ish/intel_ish5/soc.h b/soc/intel/intel_ish/intel_ish5/soc.h similarity index 100% rename from soc/x86/intel_ish/intel_ish5/soc.h rename to soc/intel/intel_ish/intel_ish5/soc.h diff --git a/soc/intel/intel_ish/soc.yml b/soc/intel/intel_ish/soc.yml new file mode 100644 index 00000000000000..ff1330c85f5477 --- /dev/null +++ b/soc/intel/intel_ish/soc.yml @@ -0,0 +1,8 @@ +family: + - name: intel_ish + series: + - name: intel_ish5 + socs: + - name: intel_ish_5_4_1 + - name: intel_ish_5_6_0 + - name: intel_ish_5_8_0 diff --git a/soc/x86/intel_ish/utils/build_ish_firmware.cmake b/soc/intel/intel_ish/utils/build_ish_firmware.cmake similarity index 100% rename from soc/x86/intel_ish/utils/build_ish_firmware.cmake rename to soc/intel/intel_ish/utils/build_ish_firmware.cmake diff --git a/soc/x86/intel_ish/utils/build_ish_firmware.py b/soc/intel/intel_ish/utils/build_ish_firmware.py similarity index 100% rename from soc/x86/intel_ish/utils/build_ish_firmware.py rename to soc/intel/intel_ish/utils/build_ish_firmware.py diff --git a/soc/intel/intel_niosv/CMakeLists.txt b/soc/intel/intel_niosv/CMakeLists.txt new file mode 100644 index 00000000000000..c75ca7f4eb3f49 --- /dev/null +++ b/soc/intel/intel_niosv/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2024 Nordic Semiconductor +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/intel/intel_niosv/Kconfig b/soc/intel/intel_niosv/Kconfig new file mode 100644 index 00000000000000..a3221149249f31 --- /dev/null +++ b/soc/intel/intel_niosv/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_NIOSV + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INTEL_NIOSV diff --git a/soc/intel/intel_niosv/Kconfig.defconfig b/soc/intel/intel_niosv/Kconfig.defconfig new file mode 100644 index 00000000000000..b9ae19a1244954 --- /dev/null +++ b/soc/intel/intel_niosv/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_NIOSV + +rsource "*/Kconfig.defconfig.series" + +endif diff --git a/soc/intel/intel_niosv/Kconfig.soc b/soc/intel/intel_niosv/Kconfig.soc new file mode 100644 index 00000000000000..1d1d2ebe65824a --- /dev/null +++ b/soc/intel/intel_niosv/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2023-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_NIOSV + bool + +config SOC_FAMILY + default "intel_niosv" if SOC_FAMILY_INTEL_NIOSV + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/intel_niosv/niosv/CMakeLists.txt b/soc/intel/intel_niosv/niosv/CMakeLists.txt similarity index 100% rename from soc/riscv/intel_niosv/niosv/CMakeLists.txt rename to soc/intel/intel_niosv/niosv/CMakeLists.txt diff --git a/soc/intel/intel_niosv/niosv/Kconfig b/soc/intel/intel_niosv/niosv/Kconfig new file mode 100644 index 00000000000000..6d479238501081 --- /dev/null +++ b/soc/intel/intel_niosv/niosv/Kconfig @@ -0,0 +1,22 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NIOSV + select RISCV + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config SOC_NIOSV_M + help + Intel FPGA NIOSV Microcontroller Core Processor + +config SOC_NIOSV_G + select RISCV_ISA_EXT_M + help + Intel FPGA NIOSV General Purpose Processor diff --git a/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series b/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series new file mode 100644 index 00000000000000..4d859d24e4edcc --- /dev/null +++ b/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series @@ -0,0 +1,19 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NIOSV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config NUM_IRQS # Platform interrupts IRQs index start from index 16 + default 32 + +config RISCV_GP + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +endif # SOC_SERIES_NIOSV diff --git a/soc/intel/intel_niosv/niosv/Kconfig.soc b/soc/intel/intel_niosv/niosv/Kconfig.soc new file mode 100644 index 00000000000000..89574f455fa72b --- /dev/null +++ b/soc/intel/intel_niosv/niosv/Kconfig.soc @@ -0,0 +1,28 @@ +# Copyright (C) 2023-2024, Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NIOSV + bool + select SOC_FAMILY_INTEL_NIOSV + help + Intel FPGA NIOSV + +config SOC_SERIES + default "niosv" if SOC_SERIES_NIOSV + +config SOC_NIOSV_M + bool + select SOC_SERIES_NIOSV + help + Intel FPGA NIOSV Microcontroller Core Processor + +config SOC_NIOSV_G + bool + select SOC_SERIES_NIOSV + help + Intel FPGA NIOSV General Purpose Processor + +config SOC + default "niosv_m" if SOC_NIOSV_M + default "niosv_g" if SOC_NIOSV_G diff --git a/soc/riscv/intel_niosv/niosv/linker.ld b/soc/intel/intel_niosv/niosv/linker.ld similarity index 100% rename from soc/riscv/intel_niosv/niosv/linker.ld rename to soc/intel/intel_niosv/niosv/linker.ld diff --git a/soc/intel/intel_niosv/soc.yml b/soc/intel/intel_niosv/soc.yml new file mode 100644 index 00000000000000..8dd3982293694c --- /dev/null +++ b/soc/intel/intel_niosv/soc.yml @@ -0,0 +1,7 @@ +family: + - name: intel_niosv + series: + - name: niosv + socs: + - name: niosv_g + - name: niosv_m diff --git a/soc/arm64/intel_socfpga/CMakeLists.txt b/soc/intel/intel_socfpga/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/CMakeLists.txt rename to soc/intel/intel_socfpga/CMakeLists.txt diff --git a/soc/intel/intel_socfpga/Kconfig b/soc/intel/intel_socfpga/Kconfig new file mode 100644 index 00000000000000..c2ea071141424f --- /dev/null +++ b/soc/intel/intel_socfpga/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INTEL_SOCFPGA diff --git a/soc/intel/intel_socfpga/Kconfig.defconfig b/soc/intel/intel_socfpga/Kconfig.defconfig new file mode 100644 index 00000000000000..2b8ba3d8830884 --- /dev/null +++ b/soc/intel/intel_socfpga/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_INTEL_SOCFPGA diff --git a/soc/intel/intel_socfpga/Kconfig.soc b/soc/intel/intel_socfpga/Kconfig.soc new file mode 100644 index 00000000000000..2fbdd5797fee3c --- /dev/null +++ b/soc/intel/intel_socfpga/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_SOCFPGA + bool + +config SOC_FAMILY + default "intel_socfpga" if SOC_FAMILY_INTEL_SOCFPGA + +rsource "*/Kconfig.soc" diff --git a/soc/arm64/intel_socfpga/agilex/CMakeLists.txt b/soc/intel/intel_socfpga/agilex/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/agilex/CMakeLists.txt rename to soc/intel/intel_socfpga/agilex/CMakeLists.txt diff --git a/soc/intel/intel_socfpga/agilex/Kconfig b/soc/intel/intel_socfpga/agilex/Kconfig new file mode 100644 index 00000000000000..ee59d3528f0700 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX + select ARM64 + select CPU_CORTEX_A53 diff --git a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex similarity index 77% rename from soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex rename to soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex index 302b0d779a1f13..4b147ff0df3d49 100644 --- a/soc/arm64/intel_socfpga/agilex/Kconfig.defconfig.agilex +++ b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.agilex @@ -1,11 +1,8 @@ -# Copyright (c) 2021 Intel Corporation +# Copyright (c) 2021-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 if SOC_AGILEX -config SOC - default "intel_socfpga_agilex" - # must be >= the highest interrupt number used # - include the UART interrupts 173 or 204 config NUM_IRQS diff --git a/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series new file mode 100644 index 00000000000000..c99f6232858493 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_AGILEX + +rsource "Kconfig.defconfig.agilex*" + +endif # SOC_SERIES_AGILEX diff --git a/soc/intel/intel_socfpga/agilex/Kconfig.soc b/soc/intel/intel_socfpga/agilex/Kconfig.soc new file mode 100644 index 00000000000000..c83b1b452f4142 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX + bool + select SOC_FAMILY_INTEL_SOCFPGA + help + Intel SoC FPGA Agilex Series + +config SOC_SERIES + default "agilex" if SOC_SERIES_AGILEX + +config SOC_AGILEX + bool + select SOC_SERIES_AGILEX + help + Intel SoC FPGA Agilex + +config SOC + default "agilex" if SOC_AGILEX diff --git a/soc/arm64/intel_socfpga/agilex/mmu_regions.c b/soc/intel/intel_socfpga/agilex/mmu_regions.c similarity index 100% rename from soc/arm64/intel_socfpga/agilex/mmu_regions.c rename to soc/intel/intel_socfpga/agilex/mmu_regions.c diff --git a/soc/arm64/intel_socfpga/agilex5/CMakeLists.txt b/soc/intel/intel_socfpga/agilex5/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/agilex5/CMakeLists.txt rename to soc/intel/intel_socfpga/agilex5/CMakeLists.txt diff --git a/soc/intel/intel_socfpga/agilex5/Kconfig b/soc/intel/intel_socfpga/agilex5/Kconfig new file mode 100644 index 00000000000000..5b8b4716ff98ef --- /dev/null +++ b/soc/intel/intel_socfpga/agilex5/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX5 + select ARM64 + select CPU_CORTEX_A76_A55 diff --git a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 similarity index 77% rename from soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 rename to soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 index d34c7880cd45e4..c072f0c84d7d88 100644 --- a/soc/arm64/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 +++ b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.agilex5 @@ -1,11 +1,8 @@ -# Copyright (c) 2022 Intel Corporation +# Copyright (c) 2022-2024 Intel Corporation # SPDX-License-Identifier: Apache-2.0 if SOC_AGILEX5 -config SOC - default "intel_socfpga_agilex5" - # must be >= the highest interrupt number used # - include the UART interrupts 173 or 204 config NUM_IRQS diff --git a/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series new file mode 100644 index 00000000000000..4f2167d432069f --- /dev/null +++ b/soc/intel/intel_socfpga/agilex5/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_AGILEX5 + +rsource "Kconfig.defconfig.agilex5*" + +endif # SOC_SERIES_AGILEX5 diff --git a/soc/intel/intel_socfpga/agilex5/Kconfig.soc b/soc/intel/intel_socfpga/agilex5/Kconfig.soc new file mode 100644 index 00000000000000..4ca2d603326381 --- /dev/null +++ b/soc/intel/intel_socfpga/agilex5/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AGILEX5 + bool + select SOC_FAMILY_INTEL_SOCFPGA + help + Intel SoC FPGA Agilex5 Series + +config SOC_SERIES + default "agilex5" if SOC_SERIES_AGILEX5 + +config SOC_AGILEX5 + bool + select SOC_SERIES_AGILEX5 + help + Intel SoC FPGA Agilex5 + +config SOC + default "agilex5" if SOC_AGILEX5 diff --git a/soc/arm64/intel_socfpga/agilex5/mmu_regions.c b/soc/intel/intel_socfpga/agilex5/mmu_regions.c similarity index 100% rename from soc/arm64/intel_socfpga/agilex5/mmu_regions.c rename to soc/intel/intel_socfpga/agilex5/mmu_regions.c diff --git a/soc/arm64/intel_socfpga/common/CMakeLists.txt b/soc/intel/intel_socfpga/common/CMakeLists.txt similarity index 100% rename from soc/arm64/intel_socfpga/common/CMakeLists.txt rename to soc/intel/intel_socfpga/common/CMakeLists.txt diff --git a/soc/arm64/intel_socfpga/common/socfpga_handoff.h b/soc/intel/intel_socfpga/common/socfpga_handoff.h similarity index 100% rename from soc/arm64/intel_socfpga/common/socfpga_handoff.h rename to soc/intel/intel_socfpga/common/socfpga_handoff.h diff --git a/soc/arm64/intel_socfpga/common/socfpga_system_manager.h b/soc/intel/intel_socfpga/common/socfpga_system_manager.h similarity index 100% rename from soc/arm64/intel_socfpga/common/socfpga_system_manager.h rename to soc/intel/intel_socfpga/common/socfpga_system_manager.h diff --git a/soc/intel/intel_socfpga/soc.yml b/soc/intel/intel_socfpga/soc.yml new file mode 100644 index 00000000000000..2d3afd3f35e180 --- /dev/null +++ b/soc/intel/intel_socfpga/soc.yml @@ -0,0 +1,9 @@ +family: + - name: intel_socfpga + series: + - name: agilex + socs: + - name: agilex + - name: agilex5 + socs: + - name: agilex5 diff --git a/soc/intel/intel_socfpga_std/CMakeLists.txt b/soc/intel/intel_socfpga_std/CMakeLists.txt new file mode 100644 index 00000000000000..9d71fff8650a07 --- /dev/null +++ b/soc/intel/intel_socfpga_std/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/intel/intel_socfpga_std/Kconfig b/soc/intel/intel_socfpga_std/Kconfig new file mode 100644 index 00000000000000..7d788402691f69 --- /dev/null +++ b/soc/intel/intel_socfpga_std/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA_STD + +rsource "*/Kconfig" + +endif # SOC_FAMILY_INTEL_SOCFPGA_STD diff --git a/soc/intel/intel_socfpga_std/Kconfig.defconfig b/soc/intel/intel_socfpga_std/Kconfig.defconfig new file mode 100644 index 00000000000000..7fa7a378185524 --- /dev/null +++ b/soc/intel/intel_socfpga_std/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_INTEL_SOCFPGA_STD + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_INTEL_SOCFPGA_STD diff --git a/soc/intel/intel_socfpga_std/Kconfig.soc b/soc/intel/intel_socfpga_std/Kconfig.soc new file mode 100644 index 00000000000000..48ed74e216ed63 --- /dev/null +++ b/soc/intel/intel_socfpga_std/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_INTEL_SOCFPGA_STD + bool + +config SOC_FAMILY + default "intel_socfpga_std" if SOC_FAMILY_INTEL_SOCFPGA_STD + +rsource "*/Kconfig.soc" diff --git a/soc/intel/intel_socfpga_std/cyclonev/CMakeLists.txt b/soc/intel/intel_socfpga_std/cyclonev/CMakeLists.txt new file mode 100644 index 00000000000000..698b0ad13b8f9c --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/CMakeLists.txt @@ -0,0 +1,7 @@ +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig b/soc/intel/intel_socfpga_std/cyclonev/Kconfig new file mode 100644 index 00000000000000..81c51390586551 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CYCLONEV + select ARM + select CPU_CORTEX_A9 + select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER + select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev new file mode 100644 index 00000000000000..c127406f62836c --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.cyclonev @@ -0,0 +1,14 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_CYCLONEV + +config NUM_IRQS + int + default 211 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 231250000 + +endif diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series new file mode 100644 index 00000000000000..39865caf5939c8 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.defconfig.series @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CYCLONEV + +rsource "Kconfig.defconfig.cyclonev*" + +endif # SOC_SERIES_CYCLONEV diff --git a/soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc new file mode 100644 index 00000000000000..16811037566838 --- /dev/null +++ b/soc/intel/intel_socfpga_std/cyclonev/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021-2024 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CYCLONEV + bool + select SOC_FAMILY_INTEL_SOCFPGA_STD + help + Intel SoC FPGA Cyclone V Series + +config SOC_SERIES + default "cyclonev" if SOC_SERIES_CYCLONEV + +config SOC_CYCLONEV + bool + select SOC_SERIES_CYCLONEV + help + Intel SoC FPGA Cyclone V + +config SOC + default "cyclonev" if SOC_CYCLONEV diff --git a/soc/arm/intel_socfpga_std/cyclonev/soc.c b/soc/intel/intel_socfpga_std/cyclonev/soc.c similarity index 100% rename from soc/arm/intel_socfpga_std/cyclonev/soc.c rename to soc/intel/intel_socfpga_std/cyclonev/soc.c diff --git a/soc/arm/intel_socfpga_std/cyclonev/soc.h b/soc/intel/intel_socfpga_std/cyclonev/soc.h similarity index 100% rename from soc/arm/intel_socfpga_std/cyclonev/soc.h rename to soc/intel/intel_socfpga_std/cyclonev/soc.h diff --git a/soc/intel/intel_socfpga_std/soc.yml b/soc/intel/intel_socfpga_std/soc.yml new file mode 100644 index 00000000000000..dde15921931aaf --- /dev/null +++ b/soc/intel/intel_socfpga_std/soc.yml @@ -0,0 +1,6 @@ +family: + - name: intel_socfpga_std + series: + - name: cyclonev + socs: + - name: cyclonev diff --git a/soc/intel/lakemont/CMakeLists.txt b/soc/intel/lakemont/CMakeLists.txt new file mode 100644 index 00000000000000..b9f29fef9cac7e --- /dev/null +++ b/soc/intel/lakemont/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_cc_option(-march=pentium) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/lakemont/Kconfig b/soc/intel/lakemont/Kconfig new file mode 100644 index 00000000000000..42727fddd5acb8 --- /dev/null +++ b/soc/intel/lakemont/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LAKEMONT + select X86 + select CPU_LAKEMONT + select X86_MMU if FPU + select X86_SSE if FPU + select X86_SSE2 if FPU + select X86_SSE3 if FPU + select X86_SSSE3 if FPU + select ARCH_HAS_USERSPACE diff --git a/soc/intel/lakemont/Kconfig.defconfig b/soc/intel/lakemont/Kconfig.defconfig new file mode 100644 index 00000000000000..4f5f85f6b3c8e4 --- /dev/null +++ b/soc/intel/lakemont/Kconfig.defconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2021-2024 Intel Corporation +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_LAKEMONT + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Can be enabled once UART is defined in board +# configuration. +config X86_VERY_EARLY_CONSOLE + default n + +# Target platforms are usually not PC-compatible +# (e.g. without BIOS, ACPI, etc.). +config X86_PC_COMPATIBLE + default n + +endif diff --git a/soc/intel/lakemont/Kconfig.soc b/soc/intel/lakemont/Kconfig.soc new file mode 100644 index 00000000000000..da45232a653e31 --- /dev/null +++ b/soc/intel/lakemont/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2021-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LAKEMONT + bool + +config SOC + default "lakemont" if SOC_LAKEMONT diff --git a/soc/x86/atom/linker.ld b/soc/intel/lakemont/linker.ld similarity index 100% rename from soc/x86/atom/linker.ld rename to soc/intel/lakemont/linker.ld diff --git a/soc/x86/lakemont/soc.h b/soc/intel/lakemont/soc.h similarity index 100% rename from soc/x86/lakemont/soc.h rename to soc/intel/lakemont/soc.h diff --git a/soc/intel/lakemont/soc.yml b/soc/intel/lakemont/soc.yml new file mode 100644 index 00000000000000..f6a59074592b85 --- /dev/null +++ b/soc/intel/lakemont/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Lakemont SoC" +socs: +- name: lakemont diff --git a/soc/intel/raptor_lake/CMakeLists.txt b/soc/intel/raptor_lake/CMakeLists.txt new file mode 100644 index 00000000000000..b3d7da79222b98 --- /dev/null +++ b/soc/intel/raptor_lake/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_cc_option(-march=goldmont) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/raptor_lake/Kconfig b/soc/intel/raptor_lake/Kconfig new file mode 100644 index 00000000000000..96ead4ae0348dd --- /dev/null +++ b/soc/intel/raptor_lake/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RAPTOR_LAKE + select X86 + select X86_64 + select CPU_ATOM + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU diff --git a/soc/intel/raptor_lake/Kconfig.defconfig b/soc/intel/raptor_lake/Kconfig.defconfig new file mode 100644 index 00000000000000..35761581eecadf --- /dev/null +++ b/soc/intel/raptor_lake/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Raptor Lake SoC configuration options + +# Copyright (c) 2022 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RAPTOR_LAKE + +config PCIE_MMIO_CFG + default y + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_RAPTOR_LAKE diff --git a/soc/intel/raptor_lake/Kconfig.soc b/soc/intel/raptor_lake/Kconfig.soc new file mode 100644 index 00000000000000..9aa2d7ee5e203a --- /dev/null +++ b/soc/intel/raptor_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2022-2024 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RAPTOR_LAKE + bool + +config SOC + default "raptor_lake" if SOC_RAPTOR_LAKE diff --git a/soc/x86/raptor_lake/doc/supported_features.txt b/soc/intel/raptor_lake/doc/supported_features.txt similarity index 100% rename from soc/x86/raptor_lake/doc/supported_features.txt rename to soc/intel/raptor_lake/doc/supported_features.txt diff --git a/soc/x86/raptor_lake/linker.ld b/soc/intel/raptor_lake/linker.ld similarity index 100% rename from soc/x86/raptor_lake/linker.ld rename to soc/intel/raptor_lake/linker.ld diff --git a/soc/x86/raptor_lake/soc.h b/soc/intel/raptor_lake/soc.h similarity index 100% rename from soc/x86/raptor_lake/soc.h rename to soc/intel/raptor_lake/soc.h diff --git a/soc/intel/raptor_lake/soc.yml b/soc/intel/raptor_lake/soc.yml new file mode 100644 index 00000000000000..66e1e391143a43 --- /dev/null +++ b/soc/intel/raptor_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Raptor Lake SoC" +socs: +- name: raptor_lake diff --git a/soc/x86/raptor_lake/soc_gpio.h b/soc/intel/raptor_lake/soc_gpio.h similarity index 100% rename from soc/x86/raptor_lake/soc_gpio.h rename to soc/intel/raptor_lake/soc_gpio.h diff --git a/soc/riscv/ite_ec/CMakeLists.txt b/soc/ite/ec/CMakeLists.txt similarity index 100% rename from soc/riscv/ite_ec/CMakeLists.txt rename to soc/ite/ec/CMakeLists.txt diff --git a/soc/ite/ec/Kconfig b/soc/ite/ec/Kconfig new file mode 100644 index 00000000000000..a496a62d69f5e4 --- /dev/null +++ b/soc/ite/ec/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ITE_EC + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ITE_EC diff --git a/soc/ite/ec/Kconfig.defconfig b/soc/ite/ec/Kconfig.defconfig new file mode 100644 index 00000000000000..646437f9c53850 --- /dev/null +++ b/soc/ite/ec/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_ITE_EC + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_ITE_EC diff --git a/soc/ite/ec/Kconfig.soc b/soc/ite/ec/Kconfig.soc new file mode 100644 index 00000000000000..f75e4de0039ee5 --- /dev/null +++ b/soc/ite/ec/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_ITE_EC + bool + +config SOC_FAMILY + default "ite_ec" if SOC_FAMILY_ITE_EC + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/ite_ec/common/CMakeLists.txt b/soc/ite/ec/common/CMakeLists.txt similarity index 100% rename from soc/riscv/ite_ec/common/CMakeLists.txt rename to soc/ite/ec/common/CMakeLists.txt diff --git a/soc/riscv/ite_ec/common/check_regs.c b/soc/ite/ec/common/check_regs.c similarity index 100% rename from soc/riscv/ite_ec/common/check_regs.c rename to soc/ite/ec/common/check_regs.c diff --git a/soc/riscv/ite_ec/common/chip_chipregs.h b/soc/ite/ec/common/chip_chipregs.h similarity index 100% rename from soc/riscv/ite_ec/common/chip_chipregs.h rename to soc/ite/ec/common/chip_chipregs.h diff --git a/soc/riscv/ite_ec/common/pinctrl_soc.h b/soc/ite/ec/common/pinctrl_soc.h similarity index 100% rename from soc/riscv/ite_ec/common/pinctrl_soc.h rename to soc/ite/ec/common/pinctrl_soc.h diff --git a/soc/riscv/ite_ec/common/policy.c b/soc/ite/ec/common/policy.c similarity index 100% rename from soc/riscv/ite_ec/common/policy.c rename to soc/ite/ec/common/policy.c diff --git a/soc/riscv/ite_ec/common/power.c b/soc/ite/ec/common/power.c similarity index 100% rename from soc/riscv/ite_ec/common/power.c rename to soc/ite/ec/common/power.c diff --git a/soc/riscv/ite_ec/common/soc_common.h b/soc/ite/ec/common/soc_common.h similarity index 100% rename from soc/riscv/ite_ec/common/soc_common.h rename to soc/ite/ec/common/soc_common.h diff --git a/soc/riscv/ite_ec/common/soc_common_irq.c b/soc/ite/ec/common/soc_common_irq.c similarity index 100% rename from soc/riscv/ite_ec/common/soc_common_irq.c rename to soc/ite/ec/common/soc_common_irq.c diff --git a/soc/riscv/ite_ec/common/soc_dt.h b/soc/ite/ec/common/soc_dt.h similarity index 100% rename from soc/riscv/ite_ec/common/soc_dt.h rename to soc/ite/ec/common/soc_dt.h diff --git a/soc/riscv/ite_ec/common/soc_espi.h b/soc/ite/ec/common/soc_espi.h similarity index 100% rename from soc/riscv/ite_ec/common/soc_espi.h rename to soc/ite/ec/common/soc_espi.h diff --git a/soc/riscv/ite_ec/common/soc_irq.S b/soc/ite/ec/common/soc_irq.S similarity index 100% rename from soc/riscv/ite_ec/common/soc_irq.S rename to soc/ite/ec/common/soc_irq.S diff --git a/soc/riscv/ite_ec/common/vector.S b/soc/ite/ec/common/vector.S similarity index 100% rename from soc/riscv/ite_ec/common/vector.S rename to soc/ite/ec/common/vector.S diff --git a/soc/ite/ec/it8xxx2/CMakeLists.txt b/soc/ite/ec/it8xxx2/CMakeLists.txt new file mode 100644 index 00000000000000..425642c1727d23 --- /dev/null +++ b/soc/ite/ec/it8xxx2/CMakeLists.txt @@ -0,0 +1,9 @@ +zephyr_sources(soc.c) +zephyr_include_directories(.) + +zephyr_library_sources_ifndef(CONFIG_RISCV_ISA_EXT_M __arithmetic.S) +zephyr_sources_ifdef(CONFIG_SOC_IT8XXX2_USE_ILM ilm.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld + CACHE INTERNAL "SoC Linker script ${SOC_NAME}" +) diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig new file mode 100644 index 00000000000000..0c65a11c27ad02 --- /dev/null +++ b/soc/ite/ec/it8xxx2/Kconfig @@ -0,0 +1,154 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ITE_IT8XXX2 + select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M + select HAS_PM + +if SOC_SERIES_ITE_IT8XXX2 + +config SOC_IT8XXX2 + select RISCV + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + # Workaround mul instruction bug, see: + # https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf + select RISCV_ISA_EXT_M if !(SOC_IT81302_BX || SOC_IT81202_BX) + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + +config SOC_IT8XXX2_REG_SET_V1 + bool + help + This option is selected by a variable of which soc, and will + determine the register for the IT81xx2 specification. + +config SOC_IT8XXX2_REG_SET_V2 + bool + help + This option is selected by a variable of which soc, and will + determine the register for the IT82xx2 specification. + +config SOC_IT81302_BX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT81202_BX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT81302_CX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT81202_CX + select SOC_IT8XXX2_REG_SET_V1 + +config SOC_IT82202_AX + select SOC_IT8XXX2_REG_SET_V2 + select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED + +config SOC_IT82302_AX + select SOC_IT8XXX2_REG_SET_V2 + select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED + +config SOC_IT82002_AW + select SOC_IT8XXX2_REG_SET_V2 + select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED + +config SOC_IT8XXX2_PLL_FLASH_48M + bool "Flash frequency is 48MHz" + default y + select FLASH + help + Change frequency of PLL, CPU, and flash to 48MHz during initialization. + + Set n to use the default settings. + (PLL and CPU run at 48MHz, flash frequency is 16MHz) + +config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN + bool "The pins of GPIO group K and L aren't bonding with pad" + default y + help + On IT81202 (128-pins package), the pins of GPIO group K and L aren't + bonding with pad. So we configure these pins as internal pull-down + at default to prevent leakage current due to floating. + +config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW + bool "The GPIOH7 isn't bonding with pad and is left floating internally" + default y + help + On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left + floating internally. We need to enable internal pull-down for the pin + to prevent leakage current, but IT81202/IT81302 doesn't have the + capability to pull it down. We can only set it as output low, + so we enable output low for it at initialization to prevent leakage. + +config SOC_IT8XXX2_CPU_IDLE_GATING + bool + help + This option determines whether the entering CPU idle mode can be + gated by individual drivers. When this option is disabled, CPU idle + mode is always permitted. + +config SOC_IT8XXX2_EC_BUS_24MHZ + bool "EC bus is 24MHz" + help + Raise EC bus to 24MHz (default is 8MHz). + This reduces read/write EC registers latency by 50%. + NOTE: There is limitation to enabling this config on it81xx2 series. + The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will + be fixed at 400KHz. + +choice + prompt "Clock source for PLL reference clock" + +config SOC_IT8XXX2_INT_32K + bool "Use the +/-2.3% internal clock generator" + +config SOC_IT8XXX2_EXT_32K + bool "Use external 32.768 kHz clock source" + +endchoice + +config SOC_IT8XXX2_USE_ILM + bool + default y + help + If enabled, Instruction Local Memory (ILM) will be configured to execute + code placed in the .__ram_code section out of RAM. This consumes RAM in + blocks of 4 kilobytes, but performance of code in ILM is much more + predictable than executing from Flash directly, and some code (such as code + that writes to the internal Flash) must execute out of RAM. + +config SOC_IT8XXX2_EXCEPTIONS_IN_RAM + bool "Place exception handling code in RAM" + default y + select SOC_IT8XXX2_USE_ILM + help + Place exception handling (ISR entry/exit and related) code in ILM, which + has more reliable performance characteristics than executing directly from + Flash. This can significantly improve performance when under I-cache + pressure. + +config SOC_IT8XXX2_SHA256_HW_ACCELERATE + bool "HW SHA256 calculation" + help + IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW. + We place SHA256 message, hash and key data (total 512bytes) in RAM. + If we enable this config, because HW limits, the sha256 data must place in + first 4KB of RAM. + +DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash + +config SOC_IT8XXX2_FLASH_SIZE_BYTES + hex + default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH)) + help + Total size of writable flash. + +config ILM_MAX_SIZE + int "ILM Size in kB" + default 60 if SOC_IT81202_CX || SOC_IT81302_CX + default SRAM_SIZE + +endif # SOC_SERIES_ITE_IT8XXX2 diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202bx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202bx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202bx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202bx index 78a33afc9d53a8..a643011e6b4384 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202bx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202bx @@ -3,9 +3,6 @@ if SOC_IT81202_BX -config SOC - default "it81202bx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202cx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202cx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202cx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202cx index c7d8d5906539c1..e9b5d1d5eb67c7 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81202cx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81202cx @@ -3,9 +3,6 @@ if SOC_IT81202_CX -config SOC - default "it81202cx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302bx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302bx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302bx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302bx index 00429d7f1245d4..051d40f1e4bbeb 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302bx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302bx @@ -3,9 +3,6 @@ if SOC_IT81302_BX -config SOC - default "it81302bx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default n diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302cx b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302cx similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302cx rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302cx index 0adc5809b72d06..06fb93d78df326 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it81302cx +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it81302cx @@ -3,9 +3,6 @@ if SOC_IT81302_CX -config SOC - default "it81302cx" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default n diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82002aw b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002aw similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82002aw rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002aw index 1edba5f674eafe..30e2db747b3f2a 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82002aw +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82002aw @@ -3,9 +3,6 @@ if SOC_IT82002_AW -config SOC - default "it82002aw" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82202ax b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202ax similarity index 83% rename from soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82202ax rename to soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202ax index 8195c2b57fb418..99343db0b37107 100644 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82202ax +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.it82202ax @@ -3,9 +3,6 @@ if SOC_IT82202_AX -config SOC - default "it82202ax" - config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN default y diff --git a/soc/ite/ec/it8xxx2/Kconfig.defconfig.series b/soc/ite/ec/it8xxx2/Kconfig.defconfig.series new file mode 100644 index 00000000000000..98fbee6c0c197a --- /dev/null +++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.series @@ -0,0 +1,56 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ITE_IT8XXX2 + +config RISCV_GP + default y + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 4096 + +config UART_NS16550_WA_ISR_REENABLE_INTERRUPT + default y + depends on UART_NS16550 + +config FLASH_INIT_PRIORITY + default 0 + +config IT8XXX2_PLL_SEQUENCE_PRIORITY + int + default 1 + depends on SOC_IT8XXX2_PLL_FLASH_48M + +config VCMP_IT8XXX2_INIT_PRIORITY + default 91 if VCMP_IT8XXX2_WORKQUEUE + +config PINCTRL + default y + +config NUM_IRQS + default 185 + +config DYNAMIC_INTERRUPTS + default y + +config GEN_ISR_TABLES + default y + +config GEN_IRQ_START_VECTOR + default 0 + +config GEN_SW_ISR_TABLE + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +rsource "Kconfig.defconfig.it8*" + +endif # SOC_SERIES_ITE_IT8XXX2 diff --git a/soc/ite/ec/it8xxx2/Kconfig.soc b/soc/ite/ec/it8xxx2/Kconfig.soc new file mode 100644 index 00000000000000..aba69c553464c4 --- /dev/null +++ b/soc/ite/ec/it8xxx2/Kconfig.soc @@ -0,0 +1,52 @@ +# Copyright (c) 2020 ITE Corporation. All Rights Reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_ITE_IT8XXX2 + bool + select SOC_FAMILY_ITE_EC + help + Enable support for ITE IT8XXX2 + +config SOC_IT8XXX2 + bool + select SOC_SERIES_ITE_IT8XXX2 + +config SOC_IT81302_BX + bool + select SOC_IT8XXX2 + +config SOC_IT81202_BX + bool + select SOC_IT8XXX2 + +config SOC_IT81302_CX + bool + select SOC_IT8XXX2 + +config SOC_IT81202_CX + bool + select SOC_IT8XXX2 + +config SOC_IT82202_AX + bool + select SOC_IT8XXX2 + +config SOC_IT82302_AX + bool + select SOC_IT8XXX2 + +config SOC_IT82002_AW + bool + select SOC_IT8XXX2 + +config SOC_SERIES + default "it8xxx2" if SOC_SERIES_ITE_IT8XXX2 + +config SOC + default "it81202bx" if SOC_IT81202_BX + default "it81202cx" if SOC_IT81202_CX + default "it81302bx" if SOC_IT81302_BX + default "it81302cx" if SOC_IT81302_CX + default "it82002aw" if SOC_IT82002_AW + default "it82202ax" if SOC_IT82202_AX + default "it82302ax" if SOC_IT82302_AX diff --git a/soc/riscv/ite_ec/it8xxx2/__arithmetic.S b/soc/ite/ec/it8xxx2/__arithmetic.S similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/__arithmetic.S rename to soc/ite/ec/it8xxx2/__arithmetic.S diff --git a/soc/riscv/ite_ec/it8xxx2/ilm.c b/soc/ite/ec/it8xxx2/ilm.c similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/ilm.c rename to soc/ite/ec/it8xxx2/ilm.c diff --git a/soc/riscv/ite_ec/it8xxx2/ilm.h b/soc/ite/ec/it8xxx2/ilm.h similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/ilm.h rename to soc/ite/ec/it8xxx2/ilm.h diff --git a/soc/riscv/ite_ec/it8xxx2/linker.ld b/soc/ite/ec/it8xxx2/linker.ld similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/linker.ld rename to soc/ite/ec/it8xxx2/linker.ld diff --git a/soc/riscv/ite_ec/it8xxx2/soc.c b/soc/ite/ec/it8xxx2/soc.c similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/soc.c rename to soc/ite/ec/it8xxx2/soc.c diff --git a/soc/riscv/ite_ec/it8xxx2/soc.h b/soc/ite/ec/it8xxx2/soc.h similarity index 100% rename from soc/riscv/ite_ec/it8xxx2/soc.h rename to soc/ite/ec/it8xxx2/soc.h diff --git a/soc/ite/ec/soc.yml b/soc/ite/ec/soc.yml new file mode 100644 index 00000000000000..c2ffdd222db77c --- /dev/null +++ b/soc/ite/ec/soc.yml @@ -0,0 +1,12 @@ +family: + - name: ite_ec + series: + - name: it8xxxx + socs: + - name: it81202bx + - name: it81202cx + - name: it81302bx + - name: it81302cx + - name: it82002aw + - name: it82202ax + - name: it82302ax diff --git a/soc/litex/litex_vexriscv/CMakeLists.txt b/soc/litex/litex_vexriscv/CMakeLists.txt new file mode 100644 index 00000000000000..3272d0359a12cf --- /dev/null +++ b/soc/litex/litex_vexriscv/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright (c) 2018 - 2019 Antmicro +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + ${ZEPHYR_BASE}/soc/common/riscv-privileged/soc_irq.S + ${ZEPHYR_BASE}/soc/common/riscv-privileged/vector.S +) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/litex/litex_vexriscv/Kconfig b/soc/litex/litex_vexriscv/Kconfig new file mode 100644 index 00000000000000..b13181f017741f --- /dev/null +++ b/soc/litex/litex_vexriscv/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LITEX_VEXRISCV + select RISCV + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +if SOC_LITEX_VEXRISCV + +config LITEX_CSR_DATA_WIDTH + int "Select Control/Status register width" + default 32 + +endif # SOC_LITEX_VEXRISCV diff --git a/soc/litex/litex_vexriscv/Kconfig.defconfig b/soc/litex/litex_vexriscv/Kconfig.defconfig new file mode 100644 index 00000000000000..d2bb5c9ae73e3b --- /dev/null +++ b/soc/litex/litex_vexriscv/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_LITEX_VEXRISCV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 + +config NUM_IRQS + default 12 + +endif # SOC_LITEX_VEXRISCV diff --git a/soc/litex/litex_vexriscv/Kconfig.soc b/soc/litex/litex_vexriscv/Kconfig.soc new file mode 100644 index 00000000000000..4c0c80717b404d --- /dev/null +++ b/soc/litex/litex_vexriscv/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2018 - 2019 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_LITEX_VEXRISCV + bool + help + LiteX VexRiscv system implementation + +config SOC + default "litex_vexriscv" if SOC_LITEX_VEXRISCV diff --git a/soc/riscv/litex_vexriscv/soc.h b/soc/litex/litex_vexriscv/soc.h similarity index 100% rename from soc/riscv/litex_vexriscv/soc.h rename to soc/litex/litex_vexriscv/soc.h diff --git a/soc/litex/litex_vexriscv/soc.yml b/soc/litex/litex_vexriscv/soc.yml new file mode 100644 index 00000000000000..322f95a9e8d3ed --- /dev/null +++ b/soc/litex/litex_vexriscv/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: litex_vexriscv diff --git a/soc/riscv/opentitan/CMakeLists.txt b/soc/lowrisc/opentitan/CMakeLists.txt similarity index 100% rename from soc/riscv/opentitan/CMakeLists.txt rename to soc/lowrisc/opentitan/CMakeLists.txt diff --git a/soc/lowrisc/opentitan/Kconfig b/soc/lowrisc/opentitan/Kconfig new file mode 100644 index 00000000000000..25670a967c6b28 --- /dev/null +++ b/soc/lowrisc/opentitan/Kconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENTITAN + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_ISA_EXT_ZBA + select RISCV_ISA_EXT_ZBB + select RISCV_ISA_EXT_ZBC + select RISCV_ISA_EXT_ZBS + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + # OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode. + select RISCV_VECTORED_MODE + select GEN_IRQ_VECTOR_TABLE diff --git a/soc/lowrisc/opentitan/Kconfig.defconfig b/soc/lowrisc/opentitan/Kconfig.defconfig new file mode 100644 index 00000000000000..b77a9405fbe9d8 --- /dev/null +++ b/soc/lowrisc/opentitan/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2023 Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_OPENTITAN + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 32 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config NUM_IRQS + default 256 + +endif # SOC_OPENTITAN diff --git a/soc/lowrisc/opentitan/Kconfig.soc b/soc/lowrisc/opentitan/Kconfig.soc new file mode 100644 index 00000000000000..bf5ff0780e9d5b --- /dev/null +++ b/soc/lowrisc/opentitan/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Rivos Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENTITAN + bool + +config SOC + default "opentitan" if SOC_OPENTITAN diff --git a/soc/riscv/opentitan/rom_header.S b/soc/lowrisc/opentitan/rom_header.S similarity index 100% rename from soc/riscv/opentitan/rom_header.S rename to soc/lowrisc/opentitan/rom_header.S diff --git a/soc/riscv/opentitan/rom_header.ld b/soc/lowrisc/opentitan/rom_header.ld similarity index 100% rename from soc/riscv/opentitan/rom_header.ld rename to soc/lowrisc/opentitan/rom_header.ld diff --git a/soc/riscv/opentitan/soc.c b/soc/lowrisc/opentitan/soc.c similarity index 100% rename from soc/riscv/opentitan/soc.c rename to soc/lowrisc/opentitan/soc.c diff --git a/soc/lowrisc/opentitan/soc.yml b/soc/lowrisc/opentitan/soc.yml new file mode 100644 index 00000000000000..51ebb26a55c2d4 --- /dev/null +++ b/soc/lowrisc/opentitan/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: opentitan diff --git a/soc/arm/microchip_mec/CMakeLists.txt b/soc/microchip/mec/CMakeLists.txt similarity index 100% rename from soc/arm/microchip_mec/CMakeLists.txt rename to soc/microchip/mec/CMakeLists.txt diff --git a/soc/microchip/mec/Kconfig b/soc/microchip/mec/Kconfig new file mode 100644 index 00000000000000..1b5ccda45e05c2 --- /dev/null +++ b/soc/microchip/mec/Kconfig @@ -0,0 +1,226 @@ +# Microchip MEC MCU line + +# Copyright (c) 2018, Intel Corporation +# Copyright (c) 2022, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MEC + +menuconfig MCHP_MEC_UNSIGNED_HEADER + bool "Create an unsigned output binary with MCHP MEC binary header" + help + On Microchip MEC series chip, the ROM code loads firmware image from flash + to RAM using a TAG to locate a Header which specifies the location and + size of the firmware image. Enable this to invoke the mec_spi_gen tool + which generates an SPI image with TAG, Header, and firmware binary. This + tool does not produce a signed image which can be authenticated by the + Boot-ROM. Use the full Microchip SPI image generator program for + authentication and all other Boot-ROM loader features. Refer to the MCHP + EVB boards for an example. + +if MCHP_MEC_UNSIGNED_HEADER + +config MCHP_MEC_HEADER_CHIP + string + default "mec15xx" if SOC_SERIES_MEC15XX + default "mec172x" if SOC_SERIES_MEC172X + +choice MCHP_MEC_HEADER_SPI_FREQ_MHZ_CHOICE + prompt "Clock rate to use for SPI flash" + default MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 + help + This selects the SPI clock frequency that will be used for loading + firmware binary from flash to RAM. + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 + bool "SPI flash clock rate of 12 MHz" + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 + bool "SPI flash clock rate of 16 MHz" + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 + bool "SPI flash clock rate of 24 MHz" + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 + bool "SPI flash clock rate of 48 MHz" + +endchoice + +config MCHP_MEC_HEADER_SPI_FREQ_MHZ + int + default 12 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_12 + default 25 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_16 + default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24 + default 48 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_48 + +choice MCHP_MEC_HEADER_SPI_READ_MODE_CHOICE + prompt "Reading mode used by the SPI flash" + default MCHP_MEC_HEADER_SPI_READ_MODE_FAST + help + This sets the reading mode that can be used by the SPI flash. + Reading modes supported are normal, fast, dual, and quad. + +config MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL + bool "SPI flash operates full-duplex with frequency (< 25 MHz)" + +config MCHP_MEC_HEADER_SPI_READ_MODE_FAST + bool "SPI flash operates full-duplex with fast reading mode" + +config MCHP_MEC_HEADER_SPI_READ_MODE_DUAL + bool "SPI flash operates with dual data reading mode" + +config MCHP_MEC_HEADER_SPI_READ_MODE_QUAD + bool "SPI flash operates with quad data reading mode" + +endchoice + +config MCHP_MEC_HEADER_SPI_READ_MODE + string + default "slow" if MCHP_MEC_HEADER_SPI_READ_MODE_NORMAL + default "fast" if MCHP_MEC_HEADER_SPI_READ_MODE_FAST + default "dual" if MCHP_MEC_HEADER_SPI_READ_MODE_DUAL + default "quad" if MCHP_MEC_HEADER_SPI_READ_MODE_QUAD + +choice MCHP_MEC_HEADER_FLASH_SIZE_CHOICE + prompt "Flash size" + default MCHP_MEC_HEADER_FLASH_SIZE_16M + help + This sets the SPI flash size. + +config MCHP_MEC_HEADER_FLASH_SIZE_256K + bool "SPI flash size 256K Bytes" + help + The SPI flash size is 256K Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_512K + bool "SPI flash size 512K Bytes" + help + The SPI flash size is 512K Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_1M + bool "SPI flash size 1M Bytes" + help + The SPI flash size is 1M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_2M + bool "SPI flash size 2M Bytes" + help + The SPI flash size is 2M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_4M + bool "SPI flash size 4M Bytes" + help + The SPI flash size is 4M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_8M + bool "SPI flash size 8M Bytes" + help + The SPI flash size is 8M Bytes. + +config MCHP_MEC_HEADER_FLASH_SIZE_16M + bool "SPI flash size 16M Bytes" + help + The SPI flash size is 16M Bytes. + +endchoice + +config MCHP_MEC_HEADER_FLASH_SIZE + int + default 256 if MCHP_MEC_HEADER_FLASH_SIZE_256K + default 512 if MCHP_MEC_HEADER_FLASH_SIZE_512K + default 1024 if MCHP_MEC_HEADER_FLASH_SIZE_1M + default 2048 if MCHP_MEC_HEADER_FLASH_SIZE_2M + default 4096 if MCHP_MEC_HEADER_FLASH_SIZE_4M + default 8192 if MCHP_MEC_HEADER_FLASH_SIZE_8M + default 16384 if MCHP_MEC_HEADER_FLASH_SIZE_16M + +choice MCHP_MEC_HEADER_SPI_DRVSTR_CHOICE + prompt "Flash drive strength" + default MCHP_MEC_HEADER_SPI_DRVSTR_1X + help + This sets the SPI flash size. + +config MCHP_MEC_HEADER_SPI_DRVSTR_1X + bool "SPI flash drive strength multiplier 1" + help + The SPI flash size is 256K Bytes. + +config MCHP_MEC_HEADER_SPI_DRVSTR_2X + bool "SPI flash drive strength multiplier 2" + help + The SPI flash size is 256K Bytes. + +config MCHP_MEC_HEADER_SPI_DRVSTR_4X + bool "SPI flash drive strength multiplier 4" + help + The SPI flash size is 512K Bytes. + +config MCHP_MEC_HEADER_SPI_DRVSTR_6X + bool "SPI flash drive strength multiplier 6" + help + The SPI flash size is 1M Bytes. + +endchoice + +config MCHP_MEC_HEADER_SPI_DRVSTR + string + default "1x" if MCHP_MEC_HEADER_SPI_DRVSTR_1X + default "2x" if MCHP_MEC_HEADER_SPI_DRVSTR_2X + default "4x" if MCHP_MEC_HEADER_SPI_DRVSTR_4X + default "6x" if MCHP_MEC_HEADER_SPI_DRVSTR_6X + +choice MCHP_MEC_HEADER_SPI_SLEW_RATE_CHOICE + prompt "Slew rate of SPI pins" + default MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW + help + This sets the slew rate of the SPI pins. Default is slow + slew rate which is 1/2 the AHB clock rate. Fast slew is the + AHB clock rate. + +config MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW + bool "SPI pins slew rate is 1/2 AHB frequency" + +config MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST + bool "SPI pins slew rate is 1x AHB frequency" + +endchoice + +config MCHP_MEC_HEADER_SPI_SLEW_RATE + string + default "slow" if MCHP_MEC_HEADER_SPI_SLEW_RATE_SLOW + default "fast" if MCHP_MEC_HEADER_SPI_SLEW_RATE_FAST + +config MCHP_MEC_HEADER_FLASH_SPI_MODE + int "Flash SPI Mode" + range 0 7 + default 0 + help + This three bit value corresponds to the QMSPI controllers clock idle and + input/output data phases. Bits[0:2] are CPOL:CPHA_MOSI:CPHA_MISO. Refer + to the data sheet. Default value is 0 corresponding to SPI Mode 0 + signalling. + Setting this field to 0 selects mode 0, CPOL=0, CPHA_MOSI=0, CPHA_MISO=0 + Setting this filed to 7 selects mode 3, CPOL=1, CPHA_MOSI=1, CPHA_MISO=1 + +config MCHP_HEADER_VERBOSE_OUTPUT + bool "Debug console output" + default n + help + Enable print output from SPI generator script for debug + +endif # MCHP_MEC_UNSIGNED_HEADER + +config SOC_MEC_PROC_CLK_DIV + int "PROC_CLK_DIV" + default 1 + range 1 48 + help + This divisor defines a ratio between processor clock (HCLK) + and main 96 MHz clock (MCK): + HCLK = MCK / PROC_CLK_DIV + Allowed divider values: 1, 3, 4, 16, and 48. + +# Select SoC Part No. and configuration options +rsource "*/Kconfig" + +endif # SOC_FAMILY_MICROCHIP_MEC diff --git a/soc/microchip/mec/Kconfig.defconfig b/soc/microchip/mec/Kconfig.defconfig new file mode 100644 index 00000000000000..26163d390c9f21 --- /dev/null +++ b/soc/microchip/mec/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024, Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MEC + +rsource "*/Kconfig.defconfig.series" + +endif # SOC_FAMILY_MICROCHIP_MEC diff --git a/soc/microchip/mec/Kconfig.soc b/soc/microchip/mec/Kconfig.soc new file mode 100644 index 00000000000000..5d1cb955c521a2 --- /dev/null +++ b/soc/microchip/mec/Kconfig.soc @@ -0,0 +1,12 @@ +# Microchip MEC172x, MEC1501 MCU line + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_MEC + bool + +config SOC_FAMILY + default "microchip_mec" if SOC_FAMILY_MICROCHIP_MEC + +rsource "*/Kconfig.soc" diff --git a/soc/microchip/mec/common/CMakeLists.txt b/soc/microchip/mec/common/CMakeLists.txt new file mode 100644 index 00000000000000..0fe0c9f3d8ba5b --- /dev/null +++ b/soc/microchip/mec/common/CMakeLists.txt @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_library_sources_ifdef(CONFIG_SOC_SERIES_MEC172X + soc_i2c.c +) + +if (DEFINED CONFIG_MCHP_HEADER_VERBOSE_OUTPUT) + set(MCHP_HEADER_VERBOSE_OPTION "-v") +endif() + +if (DEFINED CONFIG_MCHP_MEC_UNSIGNED_HEADER) + set(MCHP_MEC_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.mchp.bin) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/soc/microchip/mec/common/spigen/mec_spi_gen.py + -i ${KERNEL_BIN_NAME} + -o ${MCHP_MEC_BIN_NAME} + -c ${CONFIG_MCHP_MEC_HEADER_CHIP} + -s ${CONFIG_MCHP_MEC_HEADER_FLASH_SIZE} + -f ${CONFIG_MCHP_MEC_HEADER_SPI_FREQ_MHZ} + -r ${CONFIG_MCHP_MEC_HEADER_SPI_READ_MODE} + -m ${CONFIG_MCHP_MEC_HEADER_FLASH_SPI_MODE} + --drvstr ${CONFIG_MCHP_MEC_HEADER_SPI_DRVSTR} + --slewrate ${CONFIG_MCHP_MEC_HEADER_SPI_SLEW_RATE} + ${MCHP_HEADER_VERBOSE_OPTION} + ) +endif() diff --git a/soc/arm/microchip_mec/common/pinctrl_soc.h b/soc/microchip/mec/common/pinctrl_soc.h similarity index 100% rename from soc/arm/microchip_mec/common/pinctrl_soc.h rename to soc/microchip/mec/common/pinctrl_soc.h diff --git a/soc/arm/microchip_mec/common/reg/mec_acpi_ec.h b/soc/microchip/mec/common/reg/mec_acpi_ec.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_acpi_ec.h rename to soc/microchip/mec/common/reg/mec_acpi_ec.h diff --git a/soc/arm/microchip_mec/common/reg/mec_adc.h b/soc/microchip/mec/common/reg/mec_adc.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_adc.h rename to soc/microchip/mec/common/reg/mec_adc.h diff --git a/soc/arm/microchip_mec/common/reg/mec_global_cfg.h b/soc/microchip/mec/common/reg/mec_global_cfg.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_global_cfg.h rename to soc/microchip/mec/common/reg/mec_global_cfg.h diff --git a/soc/arm/microchip_mec/common/reg/mec_gpio.h b/soc/microchip/mec/common/reg/mec_gpio.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_gpio.h rename to soc/microchip/mec/common/reg/mec_gpio.h diff --git a/soc/arm/microchip_mec/common/reg/mec_kbc.h b/soc/microchip/mec/common/reg/mec_kbc.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_kbc.h rename to soc/microchip/mec/common/reg/mec_kbc.h diff --git a/soc/arm/microchip_mec/common/reg/mec_keyscan.h b/soc/microchip/mec/common/reg/mec_keyscan.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_keyscan.h rename to soc/microchip/mec/common/reg/mec_keyscan.h diff --git a/soc/arm/microchip_mec/common/reg/mec_peci.h b/soc/microchip/mec/common/reg/mec_peci.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_peci.h rename to soc/microchip/mec/common/reg/mec_peci.h diff --git a/soc/arm/microchip_mec/common/reg/mec_ps2.h b/soc/microchip/mec/common/reg/mec_ps2.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_ps2.h rename to soc/microchip/mec/common/reg/mec_ps2.h diff --git a/soc/arm/microchip_mec/common/reg/mec_pwm.h b/soc/microchip/mec/common/reg/mec_pwm.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_pwm.h rename to soc/microchip/mec/common/reg/mec_pwm.h diff --git a/soc/arm/microchip_mec/common/reg/mec_tach.h b/soc/microchip/mec/common/reg/mec_tach.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_tach.h rename to soc/microchip/mec/common/reg/mec_tach.h diff --git a/soc/arm/microchip_mec/common/reg/mec_tfdp.h b/soc/microchip/mec/common/reg/mec_tfdp.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_tfdp.h rename to soc/microchip/mec/common/reg/mec_tfdp.h diff --git a/soc/arm/microchip_mec/common/reg/mec_timers.h b/soc/microchip/mec/common/reg/mec_timers.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_timers.h rename to soc/microchip/mec/common/reg/mec_timers.h diff --git a/soc/arm/microchip_mec/common/reg/mec_uart.h b/soc/microchip/mec/common/reg/mec_uart.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_uart.h rename to soc/microchip/mec/common/reg/mec_uart.h diff --git a/soc/arm/microchip_mec/common/reg/mec_vci.h b/soc/microchip/mec/common/reg/mec_vci.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_vci.h rename to soc/microchip/mec/common/reg/mec_vci.h diff --git a/soc/arm/microchip_mec/common/reg/mec_wdt.h b/soc/microchip/mec/common/reg/mec_wdt.h similarity index 100% rename from soc/arm/microchip_mec/common/reg/mec_wdt.h rename to soc/microchip/mec/common/reg/mec_wdt.h diff --git a/soc/arm/microchip_mec/common/soc_dt.h b/soc/microchip/mec/common/soc_dt.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_dt.h rename to soc/microchip/mec/common/soc_dt.h diff --git a/soc/arm/microchip_mec/common/soc_espi_channels.h b/soc/microchip/mec/common/soc_espi_channels.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_espi_channels.h rename to soc/microchip/mec/common/soc_espi_channels.h diff --git a/soc/arm/microchip_mec/common/soc_gpio.h b/soc/microchip/mec/common/soc_gpio.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_gpio.h rename to soc/microchip/mec/common/soc_gpio.h diff --git a/soc/arm/microchip_mec/common/soc_i2c.c b/soc/microchip/mec/common/soc_i2c.c similarity index 99% rename from soc/arm/microchip_mec/common/soc_i2c.c rename to soc/microchip/mec/common/soc_i2c.c index 0e33437af98531..162a06695b4d89 100644 --- a/soc/arm/microchip_mec/common/soc_i2c.c +++ b/soc/microchip/mec/common/soc_i2c.c @@ -32,7 +32,7 @@ struct mec_i2c_port { * TODO: MEC15xx and MEC172x handle ports with alternate pins. */ static const struct mec_i2c_port mec_i2c_ports[] = { -#if defined(CONFIG_SOC_SERIES_MEC172X) || defined(CONFIG_SOC_SERIES_MEC1501X) +#if defined(CONFIG_SOC_SERIES_MEC172X) || defined(CONFIG_SOC_SERIES_MEC15XX) { 0004, 1, 0003, 1 }, { 0131, 1, 0130, 1 }, /* VTR2. ALT on eSPI VTR3 {0073, 2, 0072, 2} */ { 0155, 1, 0154, 1 }, diff --git a/soc/arm/microchip_mec/common/soc_i2c.h b/soc/microchip/mec/common/soc_i2c.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_i2c.h rename to soc/microchip/mec/common/soc_i2c.h diff --git a/soc/arm/microchip_mec/common/soc_pcr.h b/soc/microchip/mec/common/soc_pcr.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_pcr.h rename to soc/microchip/mec/common/soc_pcr.h diff --git a/soc/arm/microchip_mec/common/soc_pins.h b/soc/microchip/mec/common/soc_pins.h similarity index 100% rename from soc/arm/microchip_mec/common/soc_pins.h rename to soc/microchip/mec/common/soc_pins.h diff --git a/soc/arm/microchip_mec/common/spigen/mec_spi_gen.py b/soc/microchip/mec/common/spigen/mec_spi_gen.py similarity index 99% rename from soc/arm/microchip_mec/common/spigen/mec_spi_gen.py rename to soc/microchip/mec/common/spigen/mec_spi_gen.py index 41721d4bf3110c..b45a51cf55b33b 100755 --- a/soc/arm/microchip_mec/common/spigen/mec_spi_gen.py +++ b/soc/microchip/mec/common/spigen/mec_spi_gen.py @@ -68,7 +68,7 @@ 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] CHIP_DICT = { - 'mec152x': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 }, + 'mec15xx': { 'sram_base': 0xe0000, 'sram_size': 0x40000, 'header_ver': 2 }, 'mec172x': { 'sram_base': 0xc0000, 'sram_size': 0x68000, 'header_ver': 3 }, } @@ -123,7 +123,7 @@ def build_header(chip, spi_config, hdr_spi_loc, pld_spi_loc, pld_entry_addr, pld """Build MEC152x/MEC172x Boot-ROM SPI image header Args: - chip: mec152x or mec172x + chip: mec15xx or mec172x spi_config: spi configuration hdr_spi_loc: Header location in SPI Image pld_spi_loc: Payload(FW binary) location in SPI Image @@ -242,9 +242,9 @@ def parse_args(): parser.add_argument("-c", type=str, dest="chip", - choices = ["mec152x", "mec172x"], + choices = ["mec15xx", "mec172x"], default="mec172x", - help="Chip name: mec172x(default) or mec152x") + help="Chip name: mec172x(default) or mec15xx") parser.add_argument("-i", type=str, dest="infilename", diff --git a/soc/microchip/mec/mec15xx/CMakeLists.txt b/soc/microchip/mec/mec15xx/CMakeLists.txt new file mode 100644 index 00000000000000..8649cbb15fb431 --- /dev/null +++ b/soc/microchip/mec/mec15xx/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2019, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_include_directories(.) + +zephyr_sources_ifdef(CONFIG_PM + device_power.c + power.c + ) + +if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) + if(CONFIG_TIMING_FUNCTIONS) + # Use MEC15xx timing calculations only if DWT is not present + if(NOT CONFIG_CORTEX_M_DWT) + zephyr_library_sources(timing.c) + endif() + endif() +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/mec/mec15xx/Kconfig b/soc/microchip/mec/mec15xx/Kconfig new file mode 100644 index 00000000000000..d00e938a6d141a --- /dev/null +++ b/soc/microchip/mec/mec15xx/Kconfig @@ -0,0 +1,101 @@ +# Microchip MEC1501 MCU core series + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC15XX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select HAS_PM + +config SOC_MEC1501_HSZ + select HAS_MEC_HAL + +if SOC_SERIES_MEC15XX + +config RTOS_TIMER + bool "MEC1501 RTOS timer" + +config SOC_MEC1501_PROC_CLK_DIV + int "PROC_CLK_DIV" + default 1 + range 1 48 + help + This divisor defines a ratio between processor clock (HCLK) + and master clock (MCK): + HCLK = MCK / PROC_CLK_DIV + Allowed divider values: 1, 3, 4, 16, and 48. + +config SOC_MEC1501_VTR3_1_8V + bool "VTR3 power rail is tied to 1.8V" + help + Set this is if VTR3 power sourcejumper in the board is changed. + +config SOC_MEC1501_VCI_PINS_AS_GPIOS + bool "Use VCI block pins as GPIOS" + default y + help + By default these pins are not GPIOs, but HW controlled. + Set this if VCI pin block HW logic is not required in the board + design. + +choice + prompt "MEC1501 debug interface general configuration" + default SOC_MEC1501_DEBUG_WITHOUT_TRACING + depends on SOC_SERIES_MEC15XX + help + Select Debug SoC interface support for MEC15xx SoC family + + config SOC_MEC1501_DEBUG_DISABLED + bool "Disable debug support" + help + Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# + pin is ignored. All other JTAG pins can be used as GPIOs + or other non-JTAG alternate functions. + + config SOC_MEC1501_DEBUG_WITHOUT_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode. UART2 and ADC00-03 can be used. + + config SOC_MEC1501_DEBUG_AND_TRACING + bool "Debug support via Serial wire debug with tracing enabled" + help + JTAG port is enabled in SWD mode. Refer to tracing options + to see if ADC00-03 can be used or not. + +endchoice + +choice + prompt "MEC1501 debug interface trace configuration" + default SOC_MEC1501_DEBUG_AND_ETM_TRACING + depends on SOC_MEC1501_DEBUG_AND_TRACING + help + Select tracing mode for debug interface + + config SOC_MEC1501_DEBUG_AND_ETM_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode and SWV as tracing method. + UART2 can be used, but ADC00-03 cannot. + + config SOC_MEC1501_DEBUG_AND_SWV_TRACING + bool "debug support via Serial Wire Debug and Viewer" + help + JTAG port in SWD mode and SWV as tracing method. + UART2 cannot be used. ADC00-03 can be used. +endchoice + +# GPIO initialization depends on SOC initialization, which happen at +# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be +# higher than that. +if GPIO + +config GPIO_INIT_PRIORITY + default 41 + +endif # GPIO + +endif # SOC_SERIES_MEC15XX diff --git a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501hsz b/soc/microchip/mec/mec15xx/Kconfig.defconfig.mec1501hsz similarity index 88% rename from soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501hsz rename to soc/microchip/mec/mec15xx/Kconfig.defconfig.mec1501hsz index 052a198be505eb..d14e63d5e1f5e5 100644 --- a/soc/arm/microchip_mec/mec1501/Kconfig.defconfig.mec1501hsz +++ b/soc/microchip/mec/mec15xx/Kconfig.defconfig.mec1501hsz @@ -5,9 +5,6 @@ if SOC_MEC1501_HSZ -config SOC - default "mec1501hsz" - config GPIO default y diff --git a/soc/microchip/mec/mec15xx/Kconfig.defconfig.series b/soc/microchip/mec/mec15xx/Kconfig.defconfig.series new file mode 100644 index 00000000000000..d12e7023128930 --- /dev/null +++ b/soc/microchip/mec/mec15xx/Kconfig.defconfig.series @@ -0,0 +1,29 @@ +# Microchip MEC MCU series configuration options + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MEC15XX + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # All NVIC external sources. + default 174 + +rsource "Kconfig.defconfig.mec1501*" + +if RTOS_TIMER + +config SOC_HAS_TIMING_FUNCTIONS + default y if !CORTEX_M_DWT + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +endif # RTOS_TIMER + +config CORTEX_M_SYSTICK + depends on !RTOS_TIMER + +endif # SOC_SERIES_MEC15XX diff --git a/soc/microchip/mec/mec15xx/Kconfig.soc b/soc/microchip/mec/mec15xx/Kconfig.soc new file mode 100644 index 00000000000000..7d081a0b24a364 --- /dev/null +++ b/soc/microchip/mec/mec15xx/Kconfig.soc @@ -0,0 +1,20 @@ +# Microchip MEC1501 MCU core series + +# Copyright (c) 2018 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC15XX + bool + select SOC_FAMILY_MICROCHIP_MEC + help + Enable support for Microchip MEC Cortex-M4 MCU series + +config SOC_SERIES + default "mec15xx" if SOC_SERIES_MEC15XX + +config SOC_MEC1501_HSZ + bool + select SOC_SERIES_MEC15XX + +config SOC + default "mec1501_hsz" if SOC_MEC1501_HSZ diff --git a/soc/arm/microchip_mec/mec1501/device_power.c b/soc/microchip/mec/mec15xx/device_power.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/device_power.c rename to soc/microchip/mec/mec15xx/device_power.c diff --git a/soc/arm/microchip_mec/mec1501/device_power.h b/soc/microchip/mec/mec15xx/device_power.h similarity index 100% rename from soc/arm/microchip_mec/mec1501/device_power.h rename to soc/microchip/mec/mec15xx/device_power.h diff --git a/soc/arm/microchip_mec/mec1501/power.c b/soc/microchip/mec/mec15xx/power.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/power.c rename to soc/microchip/mec/mec15xx/power.c diff --git a/soc/arm/microchip_mec/mec1501/soc.c b/soc/microchip/mec/mec15xx/soc.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/soc.c rename to soc/microchip/mec/mec15xx/soc.c diff --git a/soc/arm/microchip_mec/mec1501/soc.h b/soc/microchip/mec/mec15xx/soc.h similarity index 100% rename from soc/arm/microchip_mec/mec1501/soc.h rename to soc/microchip/mec/mec15xx/soc.h diff --git a/soc/arm/microchip_mec/mec1501/soc_espi_saf_v1.h b/soc/microchip/mec/mec15xx/soc_espi_saf_v1.h similarity index 100% rename from soc/arm/microchip_mec/mec1501/soc_espi_saf_v1.h rename to soc/microchip/mec/mec15xx/soc_espi_saf_v1.h diff --git a/soc/arm/microchip_mec/mec1501/timing.c b/soc/microchip/mec/mec15xx/timing.c similarity index 100% rename from soc/arm/microchip_mec/mec1501/timing.c rename to soc/microchip/mec/mec15xx/timing.c diff --git a/soc/microchip/mec/mec172x/CMakeLists.txt b/soc/microchip/mec/mec172x/CMakeLists.txt new file mode 100644 index 00000000000000..b776b78c41d414 --- /dev/null +++ b/soc/microchip/mec/mec172x/CMakeLists.txt @@ -0,0 +1,24 @@ +# +# Copyright (c) 2021, Microchip Technology Inc. +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) +zephyr_include_directories(.) + +if(CONFIG_PM) + zephyr_library_sources(power.c device_power.c) +endif() + +if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) + if(CONFIG_TIMING_FUNCTIONS) + # Use MEC172x timing calculations only if DWT is not present + if(NOT CONFIG_CORTEX_M_DWT) + zephyr_library_sources(timing.c) + endif() + endif() +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/mec/mec172x/Kconfig b/soc/microchip/mec/mec172x/Kconfig new file mode 100644 index 00000000000000..c529d83fc3140e --- /dev/null +++ b/soc/microchip/mec/mec172x/Kconfig @@ -0,0 +1,76 @@ +# Microchip MEC172X MCU core series + +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC172X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM + +if SOC_SERIES_MEC172X + +config RTOS_TIMER + bool "MEC172x RTOS Timer(32KHz) as kernel timer" + +choice + prompt "MEC172x debug interface general configuration" + default SOC_MEC172X_DEBUG_WITHOUT_TRACING + depends on SOC_SERIES_MEC172X + help + Select Debug SoC interface support for MEC172X SoC family + + config SOC_MEC172X_DEBUG_DISABLED + bool "Disable debug support" + help + Debug port is disabled, JTAG/SWD cannot be enabled. JTAG_RST# + pin is ignored. All other JTAG pins can be used as GPIOs + or other non-JTAG alternate functions. + + config SOC_MEC172X_DEBUG_WITHOUT_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode. I2C09 and ADC00-03 can be used. + + config SOC_MEC172X_DEBUG_AND_TRACING + bool "Debug support via Serial wire debug with tracing enabled" + help + JTAG port is enabled in SWD mode. Refer to tracing options + to see if ADC00-03 can be used or not. +endchoice + +choice + prompt "MEC172X debug interface trace configuration" + default SOC_MEC172X_DEBUG_AND_ETM_TRACING + depends on SOC_MEC172X_DEBUG_AND_TRACING + help + Select tracing mode for debug interface + + config SOC_MEC172X_DEBUG_AND_ETM_TRACING + bool "Debug support via Serial wire debug" + help + JTAG port in SWD mode and ETM as tracing method. + I2C09 can be used, but ADC00-03 cannot. + + config SOC_MEC172X_DEBUG_AND_SWV_TRACING + bool "debug support via Serial Wire Debug and Viewer" + help + JTAG port in SWD mode and SWV as tracing method. + I2C09 cannot be used. ADC00-03 can be used. +endchoice + +# GPIO initialization depends on ECIA initialization, which happen at +# CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, so GPIO_INIT_PRIORITY needs to be +# higher than that. +if GPIO + +config GPIO_INIT_PRIORITY + default 41 + +endif # GPIO + +endif # SOC_SERIES_MEC172X diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnlj b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj similarity index 89% rename from soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnlj rename to soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj index ad97e3bc5ef196..daa19b0883c030 100644 --- a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnlj +++ b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnlj @@ -5,9 +5,6 @@ if SOC_MEC172X_NLJ -config SOC - default "mec172xnlj" - config GPIO default y diff --git a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz similarity index 84% rename from soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz rename to soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz index b218798465d363..1f1c19e5624e28 100644 --- a/soc/arm/microchip_mec/mec172x/Kconfig.defconfig.mec172xnsz +++ b/soc/microchip/mec/mec172x/Kconfig.defconfig.mec172xnsz @@ -5,9 +5,6 @@ if SOC_MEC172X_NSZ -config SOC - default "mec172xnsz" - config GPIO default y diff --git a/soc/microchip/mec/mec172x/Kconfig.defconfig.series b/soc/microchip/mec/mec172x/Kconfig.defconfig.series new file mode 100644 index 00000000000000..016d13b6818ea1 --- /dev/null +++ b/soc/microchip/mec/mec172x/Kconfig.defconfig.series @@ -0,0 +1,33 @@ +# Microchip MEC MCU series configuration options + +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MEC172X + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + # All NVIC external sources. + default 181 + +rsource "Kconfig.defconfig.mec172x*" + +if RTOS_TIMER + +config SOC_HAS_TIMING_FUNCTIONS + default y if !CORTEX_M_DWT + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y + +endif # RTOS_TIMER + +config CORTEX_M_SYSTICK + depends on !RTOS_TIMER + +config PS2_XEC + default y + depends on PS2 + +endif # SOC_SERIES_MEC172X diff --git a/soc/microchip/mec/mec172x/Kconfig.soc b/soc/microchip/mec/mec172x/Kconfig.soc new file mode 100644 index 00000000000000..ac91b5177e3bf6 --- /dev/null +++ b/soc/microchip/mec/mec172x/Kconfig.soc @@ -0,0 +1,25 @@ +# Microchip MEC172x MCU core series + +# Copyright (c) 2021 Microchip Technology Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MEC172X + bool + select SOC_FAMILY_MICROCHIP_MEC + help + Enable support for Microchip MEC Cortex-M4F MCU series + +config SOC_SERIES + default "mec172x" if SOC_SERIES_MEC172X + +config SOC_MEC172X_NSZ + bool + select SOC_SERIES_MEC172X + +config SOC_MEC172X_NLJ + bool + select SOC_SERIES_MEC172X + +config SOC + default "mec172x_nsz" if SOC_MEC172X_NSZ + default "mec172x_nlj" if SOC_MEC172X_NLJ diff --git a/soc/arm/microchip_mec/mec172x/device_power.c b/soc/microchip/mec/mec172x/device_power.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/device_power.c rename to soc/microchip/mec/mec172x/device_power.c diff --git a/soc/arm/microchip_mec/mec172x/device_power.h b/soc/microchip/mec/mec172x/device_power.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/device_power.h rename to soc/microchip/mec/mec172x/device_power.h diff --git a/soc/arm/microchip_mec/mec172x/power.c b/soc/microchip/mec/mec172x/power.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/power.c rename to soc/microchip/mec/mec172x/power.c diff --git a/soc/arm/microchip_mec/mec172x/reg/gpio_pkg_lj.h b/soc/microchip/mec/mec172x/reg/gpio_pkg_lj.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/gpio_pkg_lj.h rename to soc/microchip/mec/mec172x/reg/gpio_pkg_lj.h diff --git a/soc/arm/microchip_mec/mec172x/reg/gpio_pkg_sz.h b/soc/microchip/mec/mec172x/reg/gpio_pkg_sz.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/gpio_pkg_sz.h rename to soc/microchip/mec/mec172x/reg/gpio_pkg_sz.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_defs.h b/soc/microchip/mec/mec172x/reg/mec172x_defs.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_defs.h rename to soc/microchip/mec/mec172x/reg/mec172x_defs.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_ecia.h b/soc/microchip/mec/mec172x/reg/mec172x_ecia.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_ecia.h rename to soc/microchip/mec/mec172x/reg/mec172x_ecia.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_ecs.h b/soc/microchip/mec/mec172x/reg/mec172x_ecs.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_ecs.h rename to soc/microchip/mec/mec172x/reg/mec172x_ecs.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_emi.h b/soc/microchip/mec/mec172x/reg/mec172x_emi.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_emi.h rename to soc/microchip/mec/mec172x/reg/mec172x_emi.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h b/soc/microchip/mec/mec172x/reg/mec172x_espi_iom.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_espi_iom.h rename to soc/microchip/mec/mec172x/reg/mec172x_espi_iom.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_saf.h b/soc/microchip/mec/mec172x/reg/mec172x_espi_saf.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_espi_saf.h rename to soc/microchip/mec/mec172x/reg/mec172x_espi_saf.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_espi_vw.h b/soc/microchip/mec/mec172x/reg/mec172x_espi_vw.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_espi_vw.h rename to soc/microchip/mec/mec172x/reg/mec172x_espi_vw.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_gpio.h b/soc/microchip/mec/mec172x/reg/mec172x_gpio.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_gpio.h rename to soc/microchip/mec/mec172x/reg/mec172x_gpio.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_i2c_smb.h b/soc/microchip/mec/mec172x/reg/mec172x_i2c_smb.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_i2c_smb.h rename to soc/microchip/mec/mec172x/reg/mec172x_i2c_smb.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_p80bd.h b/soc/microchip/mec/mec172x/reg/mec172x_p80bd.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_p80bd.h rename to soc/microchip/mec/mec172x/reg/mec172x_p80bd.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_pcr.h b/soc/microchip/mec/mec172x/reg/mec172x_pcr.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_pcr.h rename to soc/microchip/mec/mec172x/reg/mec172x_pcr.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_qspi.h b/soc/microchip/mec/mec172x/reg/mec172x_qspi.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_qspi.h rename to soc/microchip/mec/mec172x/reg/mec172x_qspi.h diff --git a/soc/arm/microchip_mec/mec172x/reg/mec172x_vbat.h b/soc/microchip/mec/mec172x/reg/mec172x_vbat.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/reg/mec172x_vbat.h rename to soc/microchip/mec/mec172x/reg/mec172x_vbat.h diff --git a/soc/arm/microchip_mec/mec172x/soc.c b/soc/microchip/mec/mec172x/soc.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc.c rename to soc/microchip/mec/mec172x/soc.c diff --git a/soc/arm/microchip_mec/mec172x/soc.h b/soc/microchip/mec/mec172x/soc.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc.h rename to soc/microchip/mec/mec172x/soc.h diff --git a/soc/arm/microchip_mec/mec172x/soc_espi_saf_v2.h b/soc/microchip/mec/mec172x/soc_espi_saf_v2.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc_espi_saf_v2.h rename to soc/microchip/mec/mec172x/soc_espi_saf_v2.h diff --git a/soc/arm/microchip_mec/mec172x/soc_power_debug.h b/soc/microchip/mec/mec172x/soc_power_debug.h similarity index 100% rename from soc/arm/microchip_mec/mec172x/soc_power_debug.h rename to soc/microchip/mec/mec172x/soc_power_debug.h diff --git a/soc/arm/microchip_mec/mec172x/timing.c b/soc/microchip/mec/mec172x/timing.c similarity index 100% rename from soc/arm/microchip_mec/mec172x/timing.c rename to soc/microchip/mec/mec172x/timing.c diff --git a/soc/microchip/mec/soc.yml b/soc/microchip/mec/soc.yml new file mode 100644 index 00000000000000..6c20b24ff9ffbb --- /dev/null +++ b/soc/microchip/mec/soc.yml @@ -0,0 +1,10 @@ +family: +- name: microchip_mec + series: + - name: mec15xx + socs: + - name: mec1501_hsz + - name: mec172x + socs: + - name: mec172x_nsz + - name: mec172x_nlj diff --git a/soc/riscv/gd_gd32/CMakeLists.txt b/soc/microchip/miv/CMakeLists.txt similarity index 100% rename from soc/riscv/gd_gd32/CMakeLists.txt rename to soc/microchip/miv/CMakeLists.txt diff --git a/soc/microchip/miv/Kconfig b/soc/microchip/miv/Kconfig new file mode 100644 index 00000000000000..d509a53892723e --- /dev/null +++ b/soc/microchip/miv/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig" + +endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/microchip/miv/Kconfig.defconfig b/soc/microchip/miv/Kconfig.defconfig new file mode 100644 index 00000000000000..b63f842dd575dd --- /dev/null +++ b/soc/microchip/miv/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/microchip/miv/Kconfig.soc b/soc/microchip/miv/Kconfig.soc new file mode 100644 index 00000000000000..5725ff29b19a04 --- /dev/null +++ b/soc/microchip/miv/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_MICROCHIP_MIV + bool + +config SOC_FAMILY + default "microchip_miv" if SOC_FAMILY_MICROCHIP_MIV + +rsource "*/Kconfig.soc" diff --git a/soc/microchip/miv/miv/CMakeLists.txt b/soc/microchip/miv/miv/CMakeLists.txt new file mode 100644 index 00000000000000..ee3378886b8deb --- /dev/null +++ b/soc/microchip/miv/miv/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Antmicro + +zephyr_sources() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/microchip/miv/miv/Kconfig b/soc/microchip/miv/miv/Kconfig new file mode 100644 index 00000000000000..132818de4e775a --- /dev/null +++ b/soc/microchip/miv/miv/Kconfig @@ -0,0 +1,18 @@ +# RISCV32_MIV configuration options + +# Copyright (c) 2018 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MIV + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_MIV + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/microchip/miv/miv/Kconfig.defconfig b/soc/microchip/miv/miv/Kconfig.defconfig new file mode 100644 index 00000000000000..4e2653f5cd0d2b --- /dev/null +++ b/soc/microchip/miv/miv/Kconfig.defconfig @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2018 Antmicro + +if SOC_SERIES_MIV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 4000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 30 + +config NUM_IRQS + default 42 + +endif # SOC_SERIES_MIV diff --git a/soc/microchip/miv/miv/Kconfig.soc b/soc/microchip/miv/miv/Kconfig.soc new file mode 100644 index 00000000000000..7e2eafe118eb04 --- /dev/null +++ b/soc/microchip/miv/miv/Kconfig.soc @@ -0,0 +1,22 @@ +# RISCV32_MIV configuration options + +# Copyright (c) 2018 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MIV + bool + select SOC_FAMILY_MICROCHIP_MIV + help + Microchip Mi-V implementation# + +config SOC_MIV + bool + select SOC_SERIES_MIV + help + Microchip Mi-V system implementation + +config SOC_SERIES + default "miv" if SOC_SERIES_MIV + +config SOC + default "miv" if SOC_MIV diff --git a/soc/riscv/microchip_miv/miv/CMakeLists.txt b/soc/microchip/miv/polarfire/CMakeLists.txt similarity index 100% rename from soc/riscv/microchip_miv/miv/CMakeLists.txt rename to soc/microchip/miv/polarfire/CMakeLists.txt diff --git a/soc/microchip/miv/polarfire/Kconfig b/soc/microchip/miv/polarfire/Kconfig new file mode 100644 index 00000000000000..b57d0ee92fbfc0 --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig @@ -0,0 +1,28 @@ +# RISCV64_MIV Microchip Polarfire SOC configuration options + +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_POLARFIRE + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_POLARFIRE + select ATOMIC_OPERATIONS_BUILTIN + select RISCV_GP + select USE_SWITCH_SUPPORTED + select USE_SWITCH + select CPU_HAS_FPU + select SCHED_IPI_SUPPORTED + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + +config MPFS_HAL + depends on SOC_POLARFIRE + bool "Microchip Polarfire SOC hardware abstracton layer" + select HAS_MPFS_HAL diff --git a/soc/microchip/miv/polarfire/Kconfig.defconfig b/soc/microchip/miv/polarfire/Kconfig.defconfig new file mode 100644 index 00000000000000..113a3bd6acb768 --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_POLARFIRE + +# MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock... + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 13 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 186 + +config NUM_IRQS + default 186 + +endif # SOC_SERIES_POLARFIRE diff --git a/soc/microchip/miv/polarfire/Kconfig.soc b/soc/microchip/miv/polarfire/Kconfig.soc new file mode 100644 index 00000000000000..ce44e8b8ada155 --- /dev/null +++ b/soc/microchip/miv/polarfire/Kconfig.soc @@ -0,0 +1,22 @@ +# RISCV64_MIV Microchip Polarfire SOC configuration options + +# Copyright (c) 2020-2021 Microchip Technology Inc +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_POLARFIRE + bool + select SOC_FAMILY_MICROCHIP_MIV + help + Microchip RV64 implementation + +config SOC_POLARFIRE + bool + select SOC_SERIES_POLARFIRE + help + Microchip MPFS system implementation + +config SOC_SERIES + default "polarfire" if SOC_SERIES_POLARFIRE + +config SOC + default "polarfire" if SOC_POLARFIRE diff --git a/soc/microchip/miv/soc.yml b/soc/microchip/miv/soc.yml new file mode 100644 index 00000000000000..11f30cffc32523 --- /dev/null +++ b/soc/microchip/miv/soc.yml @@ -0,0 +1,9 @@ +family: +- name: microchip_miv + series: + - name: miv + socs: + - name: miv + - name: polarfire + socs: + - name: polarfire diff --git a/soc/mips/CMakeLists.txt b/soc/mips/CMakeLists.txt deleted file mode 100644 index f4733688cca662..00000000000000 --- a/soc/mips/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/mips/qemu_malta/CMakeLists.txt b/soc/mips/qemu_malta/CMakeLists.txt deleted file mode 100644 index 351ffebf5b5123..00000000000000 --- a/soc/mips/qemu_malta/CMakeLists.txt +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2020, 2021 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_compile_options( - -mips32 - ${TOOLCHAIN_C_FLAGS} -) - -zephyr_sources( - vector.S -) - -zephyr_ld_options( - -mips32 - ${TOOLCHAIN_LD_FLAGS} -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/mips/linker.ld CACHE INTERNAL "") diff --git a/soc/mips/qemu_malta/Kconfig.defconfig b/soc/mips/qemu_malta/Kconfig.defconfig deleted file mode 100644 index c2811c31ac68bd..00000000000000 --- a/soc/mips/qemu_malta/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_QEMU_MALTA - -config SOC - default "qemu_malta" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 200000000 - -config NUM_IRQS - default 8 - -endif # SOC_QEMU_MALTA diff --git a/soc/mips/qemu_malta/Kconfig.soc b/soc/mips/qemu_malta/Kconfig.soc deleted file mode 100644 index d18a881bd0a8cd..00000000000000 --- a/soc/mips/qemu_malta/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2020 Antony Pavlov -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_QEMU_MALTA - bool "MIPS Qemu Malta implementation" - select MIPS diff --git a/soc/native/inf_clock/CMakeLists.txt b/soc/native/inf_clock/CMakeLists.txt new file mode 100644 index 00000000000000..7f9d09b2c34ffa --- /dev/null +++ b/soc/native/inf_clock/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +zephyr_library() + +zephyr_library_compile_definitions(NO_POSIX_CHEATS) + +zephyr_library_sources( + soc.c + native_tasks.c + ) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/posix/include + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/posix/linker.ld CACHE INTERNAL "") diff --git a/soc/native/inf_clock/Kconfig b/soc/native/inf_clock/Kconfig new file mode 100644 index 00000000000000..4453d3dbccc837 --- /dev/null +++ b/soc/native/inf_clock/Kconfig @@ -0,0 +1,57 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_POSIX + select ARCH_POSIX + select CPU_HAS_FPU + +if SOC_POSIX + +config NATIVE_SIMULATOR_MCU_N + int "CPU Number this image targets" + range 0 15 + default 0 + depends on NATIVE_LIBRARY + help + Which native simulator microcontroller/CPU number is this image targeting. + This option is only applicable for targets which use the + native simulator as their runner. + +config NATIVE_SIMULATOR_NUMBER_MCUS + int "Total number of MCUs this target has" + range 1 16 + default 1 + depends on NATIVE_LIBRARY + help + How many AMP MCUs does this target have in total. + +config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX + int "Which CPU is the primary/preferred" + default 0 + depends on NATIVE_LIBRARY + help + On a multi MCU device, which MCU is the preferred one. + This MCU will for example have its tests command line parameters presented + without any prefix. Note that an MCU being primary does not imply it will be + the first one to boot, or even that it will boot automatically. + +config NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS + string "Other cores images to include" + depends on NATIVE_LIBRARY + help + This option can be used to provide the native simulator with other MCUs/Cores images which have + been produced by either other Zephyr builds or different OS builds. + So you can, for ex., use this application build to produce one core image, and at the same time + have it produce the final link with the native simulator runner and the other MCU images. + +config NATIVE_SIMULATOR_AUTOSTART_MCU + bool "Auto-start this MCU" + depends on NATIVE_LIBRARY + help + Automatically start the MCU this Zephyr image is built for during HW boot, + even if in other circumstances this MCU would not start automatically (for ex. because + another core is meant to release its reset). + If that MCU was, by HW design, going to start at HW boot anyhow, this option does nothing. + This option is meant to facilitate development. + +endif # SOC_POSIX diff --git a/soc/native/inf_clock/Kconfig.soc b/soc/native/inf_clock/Kconfig.soc new file mode 100644 index 00000000000000..62667c55a9760f --- /dev/null +++ b/soc/native/inf_clock/Kconfig.soc @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2023 Nordic Semiconductor ASA + +config SOC_POSIX + bool + help + SOC for to the POSIX arch. It emulates a CPU running at an infinitely fast + clock. That means the CPU will always run in zero time until completion after + each wake reason (e.g. interrupts), before going back to idle. Note that an + infinite loop in the code which does not sleep the CPU will cause the process + to appear "hung", as simulated time does not advance while the CPU does not + sleep. Therefore do not use busy waits while waiting for something to happen + (if needed use k_busy_wait()). + Note that the interrupt handling is provided by the board. + +config SOC + default "native" if SOC_POSIX diff --git a/soc/posix/inf_clock/native_tasks.c b/soc/native/inf_clock/native_tasks.c similarity index 100% rename from soc/posix/inf_clock/native_tasks.c rename to soc/native/inf_clock/native_tasks.c diff --git a/soc/posix/inf_clock/posix_board_if.h b/soc/native/inf_clock/posix_board_if.h similarity index 100% rename from soc/posix/inf_clock/posix_board_if.h rename to soc/native/inf_clock/posix_board_if.h diff --git a/soc/posix/inf_clock/posix_native_task.h b/soc/native/inf_clock/posix_native_task.h similarity index 100% rename from soc/posix/inf_clock/posix_native_task.h rename to soc/native/inf_clock/posix_native_task.h diff --git a/soc/posix/inf_clock/posix_soc.h b/soc/native/inf_clock/posix_soc.h similarity index 100% rename from soc/posix/inf_clock/posix_soc.h rename to soc/native/inf_clock/posix_soc.h diff --git a/soc/posix/inf_clock/soc.c b/soc/native/inf_clock/soc.c similarity index 100% rename from soc/posix/inf_clock/soc.c rename to soc/native/inf_clock/soc.c diff --git a/soc/posix/inf_clock/soc.h b/soc/native/inf_clock/soc.h similarity index 100% rename from soc/posix/inf_clock/soc.h rename to soc/native/inf_clock/soc.h diff --git a/soc/native/inf_clock/soc.yml b/soc/native/inf_clock/soc.yml new file mode 100644 index 00000000000000..67eb6b9f61bd9c --- /dev/null +++ b/soc/native/inf_clock/soc.yml @@ -0,0 +1,4 @@ +family: +- name: native + socs: + - name: native diff --git a/soc/posix/inf_clock/soc_irq.h b/soc/native/inf_clock/soc_irq.h similarity index 100% rename from soc/posix/inf_clock/soc_irq.h rename to soc/native/inf_clock/soc_irq.h diff --git a/soc/riscv/neorv32/CMakeLists.txt b/soc/neorv32/CMakeLists.txt similarity index 100% rename from soc/riscv/neorv32/CMakeLists.txt rename to soc/neorv32/CMakeLists.txt diff --git a/soc/neorv32/Kconfig b/soc/neorv32/Kconfig new file mode 100644 index 00000000000000..6df6c6d2b7c782 --- /dev/null +++ b/soc/neorv32/Kconfig @@ -0,0 +1,35 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NEORV32 + select RISCV + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_PRIVILEGED + +if SOC_NEORV32 + +config SOC_NEORV32_V1_8_6 + bool "v1.8.6" + # NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO + select ATOMIC_OPERATIONS_C + +config SOC_NEORV32_VERSION + hex + default 0x01080600 if SOC_NEORV32_V1_8_6 + help + The targeted NEORV32 version as BCD-coded number. The format is + identical to that of the NEORV32 Machine implementation ID (mimpid) + register. + +config SOC_NEORV32_ISA_C + bool "RISC-V ISA Extension \"C\"" + select RISCV_ISA_EXT_C + help + Enable this if the NEORV32 CPU implementation supports the RISC-V ISA + "C" extension (Compressed Instructions). + +endif # SOC_NEORV32 diff --git a/soc/neorv32/Kconfig.defconfig b/soc/neorv32/Kconfig.defconfig new file mode 100644 index 00000000000000..67d458f7398fc7 --- /dev/null +++ b/soc/neorv32/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NEORV32 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER + +config NUM_IRQS + default 32 + +config RISCV_GP + default y + +config SYSCON + default y + +config SERIAL_INIT_PRIORITY + default 55 + depends on SERIAL + +config ENTROPY_INIT_PRIORITY + default 55 + depends on ENTROPY_GENERATOR + +endif # SOC_NEORV32 diff --git a/soc/neorv32/Kconfig.soc b/soc/neorv32/Kconfig.soc new file mode 100644 index 00000000000000..37a28ec7b446a7 --- /dev/null +++ b/soc/neorv32/Kconfig.soc @@ -0,0 +1,22 @@ +# Copyright (c) 2021 Henrik Brix Andersen +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NEORV32 + bool + help + NEORV32 Processor (SoC). + + The NEORV32 CPU implementation must have the following RISC-V ISA + extensions enabled in order to support Zephyr: + - M (Integer Multiplication and Division) + - Zicsr (Control and Status Register (CSR) Instructions) + + The following NEORV32 CPU ISA extensions are not currently supported + by Zephyr and can safely be disabled: + - A (Atomic Instructions) + - E (Embedded, only 16 integer registers) + - Zbb (Basic Bit Manipulation) + - Zfinx (Floating Point in Integer Registers) + +config SOC + default "neorv32" if SOC_NEORV32 diff --git a/soc/riscv/neorv32/linker.ld b/soc/neorv32/linker.ld similarity index 100% rename from soc/riscv/neorv32/linker.ld rename to soc/neorv32/linker.ld diff --git a/soc/riscv/neorv32/reset.S b/soc/neorv32/reset.S similarity index 100% rename from soc/riscv/neorv32/reset.S rename to soc/neorv32/reset.S diff --git a/soc/riscv/neorv32/soc.c b/soc/neorv32/soc.c similarity index 100% rename from soc/riscv/neorv32/soc.c rename to soc/neorv32/soc.c diff --git a/soc/riscv/neorv32/soc.h b/soc/neorv32/soc.h similarity index 100% rename from soc/riscv/neorv32/soc.h rename to soc/neorv32/soc.h diff --git a/soc/neorv32/soc.yml b/soc/neorv32/soc.yml new file mode 100644 index 00000000000000..c2e51c227779db --- /dev/null +++ b/soc/neorv32/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: neorv32 diff --git a/soc/riscv/neorv32/soc_irq.S b/soc/neorv32/soc_irq.S similarity index 100% rename from soc/riscv/neorv32/soc_irq.S rename to soc/neorv32/soc_irq.S diff --git a/soc/nios2/nios2-qemu/CMakeLists.txt b/soc/nios2/nios2-qemu/CMakeLists.txt deleted file mode 100644 index b6dd454d035ebf..00000000000000 --- a/soc/nios2/nios2-qemu/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nios2/nios2-qemu/Kconfig.defconfig b/soc/nios2/nios2-qemu/Kconfig.defconfig deleted file mode 100644 index 453af05cd8c778..00000000000000 --- a/soc/nios2/nios2-qemu/Kconfig.defconfig +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NIOS2_QEMU - -config SOC - default "nios2-qemu" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -endif diff --git a/soc/nios2/nios2-qemu/Kconfig.soc b/soc/nios2/nios2-qemu/Kconfig.soc deleted file mode 100644 index 0f670e4e4c6c9a..00000000000000 --- a/soc/nios2/nios2-qemu/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NIOS2_QEMU - bool "Nios II - Experimental QEMU emulation" - select NIOS2 - select HAS_MUL_INSTRUCTION - select HAS_DIV_INSTRUCTION - select HAS_MULX_INSTRUCTION diff --git a/soc/nios2/nios2f-zephyr/CMakeLists.txt b/soc/nios2/nios2f-zephyr/CMakeLists.txt deleted file mode 100644 index 789c4c81fc98ec..00000000000000 --- a/soc/nios2/nios2f-zephyr/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nios2/nios2f-zephyr/Kconfig.defconfig b/soc/nios2/nios2f-zephyr/Kconfig.defconfig deleted file mode 100644 index 3ffa3f9e14bb15..00000000000000 --- a/soc/nios2/nios2f-zephyr/Kconfig.defconfig +++ /dev/null @@ -1,26 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NIOS2F_ZEPHYR - -config SOC - default "nios2f-zephyr" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 50000000 - -config ALTERA_AVALON_SYSID - def_bool y - -config ALTERA_AVALON_QSPI - def_bool y - depends on SOC_FLASH_NIOS2_QSPI - -config ALTERA_AVALON_I2C - def_bool y - depends on I2C_NIOS2 - -config ALTERA_AVALON_MSGDMA - def_bool y - depends on DMA_NIOS2_MSGDMA - -endif # SOC_NIOS2F_ZEPHYR diff --git a/soc/nios2/nios2f-zephyr/Kconfig.soc b/soc/nios2/nios2f-zephyr/Kconfig.soc deleted file mode 100644 index 15e123826311be..00000000000000 --- a/soc/nios2/nios2f-zephyr/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NIOS2F_ZEPHYR - bool "Nios IIf - Zephyr Golden Configuration" - select NIOS2 - select HAS_MUL_INSTRUCTION - select HAS_DIV_INSTRUCTION diff --git a/soc/nordic/CMakeLists.txt b/soc/nordic/CMakeLists.txt new file mode 100644 index 00000000000000..9e0619772e2e4f --- /dev/null +++ b/soc/nordic/CMakeLists.txt @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +if(CONFIG_ARM) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "SoC Linker script") + + zephyr_library_sources( + validate_base_addresses.c + validate_enabled_instances.c + ) +endif() + +if(CONFIG_SOC_HAS_TIMING_FUNCTIONS AND NOT CONFIG_BOARD_HAS_TIMING_FUNCTIONS) + if(CONFIG_TIMING_FUNCTIONS) + # Use nRF-specific timing calculations only if DWT is not present + if(NOT CONFIG_CORTEX_M_DWT) + zephyr_library_sources(timing.c) + endif() + endif() +endif() + +if(CONFIG_BUILD_WITH_TFM) + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DHAL_NORDIC_PATH=${ZEPHYR_HAL_NORDIC_MODULE_DIR} + ) + + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DZEPHYR_BASE=${ZEPHYR_BASE} + ) + + set_property(TARGET zephyr_property_target + APPEND PROPERTY TFM_CMAKE_OPTIONS -DNRF_NS_STORAGE=${CONFIG_TFM_NRF_NS_STORAGE} + ) +endif() + +add_subdirectory(${SOC_SERIES}) +add_subdirectory(common) diff --git a/soc/nordic/Kconfig b/soc/nordic/Kconfig new file mode 100644 index 00000000000000..ca0a152272e10e --- /dev/null +++ b/soc/nordic/Kconfig @@ -0,0 +1,174 @@ +# Nordic Semiconductor nRFx MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +# This file is contains Zephyr build system Kconfig references and is not +# re-usable outside the Zephyr tree. + +config SOC_FAMILY_NORDIC_NRF + select SOC_COMPATIBLE_NRF + select PLATFORM_SPECIFIC_INIT if ARM + +if SOC_FAMILY_NORDIC_NRF + +rsource "common/Kconfig.peripherals" +rsource "*/Kconfig" + +config NRF_SOC_SECURE_SUPPORTED + def_bool !TRUSTED_EXECUTION_NONSECURE || (BUILD_WITH_TFM && TFM_PARTITION_PLATFORM) + depends on !SOC_SERIES_NRF54HX + help + Hidden function to indicate that that the soc_secure functions are + available. + The functions are always available when not in non-secure. + For non-secure the functions must redirect to secure services exposed + by the secure firmware. + +config BUILD_WITH_TFM + default y if TRUSTED_EXECUTION_NONSECURE + help + By default, if we build for a Non-Secure version of the board, + enable building with TF-M as the Secure Execution Environment. + +if BUILD_WITH_TFM + +config TFM_FLASH_MERGED_BINARY + default y + help + By default, if we build with TF-M, instruct build system to + flash the combined TF-M (Secure) & Zephyr (Non Secure) image + +config TFM_LOG_LEVEL_SILENCE + default y if !$(dt_nodelabel_has_prop,uart1,pinctrl-names) + help + Disable TF-M secure output if the uart1 node has not assigned GPIO + pins using pinctrl. + +config TFM_NRF_NS_STORAGE + bool "TF-M non-secure storage partition" + default y + +endif # BUILD_WITH_TFM + + +config NRF_MPU_FLASH_REGION_SIZE + hex + default 0x1000 + depends on HAS_HW_NRF_MPU + help + FLASH region size for the NRF_MPU peripheral. + +config NRF_BPROT_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) + depends on HAS_HW_NRF_BPROT + help + FLASH region size for the NRF_BPROT peripheral (nRF52). + +config NRF_ACL_FLASH_REGION_SIZE + hex + default $(dt_node_int_prop_hex,$(DT_CHOSEN_ZEPHYR_FLASH),erase-block-size) + depends on HAS_HW_NRF_ACL + help + FLASH region size for the NRF_ACL peripheral. + +config NFCT_PINS_AS_GPIOS + bool "[DEPRECATED] NFCT pins as GPIOs" + depends on $(dt_has_compat,$(DT_COMPAT_NORDIC_NRF_NFCT)) + select DEPRECATED + help + Two pins are usually reserved for NFC in SoCs that implement the + NFCT peripheral. This option switches them to normal GPIO mode. + HW enabling happens once in the device lifetime, during the first + system startup. Disabling this option will not switch back these + pins to NFCT mode. Doing this requires UICR erase prior to + flashing device using the image which has this option disabled. + + NFC pins in nRF52 series: P0.09 and P0.10 + NFC pins in nRF5340: P0.02 and P0.03 + + This option is deprecated, please use devicetree to configure NFCT + pins as GPIOS like this: + + &uicr { + nfct-pins-as-gpios; + }; + +choice NRF_APPROTECT_HANDLING + bool "APPROTECT handling" + depends on SOC_SERIES_NRF52X || SOC_NRF5340_CPUNET || \ + (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) || \ + SOC_SERIES_NRF91X + default NRF_APPROTECT_USE_UICR + help + Specifies how the SystemInit() function should handle the APPROTECT + mechanism. + +config NRF_APPROTECT_USE_UICR + bool "Use UICR" + help + When this option is selected, the SystemInit() function loads the + firmware branch state of the APPROTECT mechanism from UICR, so if + UICR->APPROTECT is disabled, CTRLAP->APPROTECT will be disabled. + +config NRF_APPROTECT_LOCK + bool "Lock" + help + When this option is selected, the SystemInit() function locks + the firmware branch of the APPROTECT mechanism, preventing it + from being opened. + +config NRF_APPROTECT_USER_HANDLING + bool "Allow user handling" + depends on !SOC_SERIES_NRF52X + help + When this option is selected, the SystemInit() function does not + touch the APPROTECT mechanism, allowing the user code to handle it + at later stages, for example, to implement authenticated debug. + +endchoice + +choice NRF_SECURE_APPROTECT_HANDLING + bool "Secure APPROTECT handling" + depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) + default NRF_SECURE_APPROTECT_USE_UICR + help + Specifies how the SystemInit() function should handle the secure + APPROTECT mechanism. + +config NRF_SECURE_APPROTECT_USE_UICR + bool "Use UICR" + help + When this option is selected, the SystemInit() function loads the + firmware branch state of the secure APPROTECT mechanism from UICR, + so if UICR->SECUREAPPROTECT is disabled, CTRLAP->SECUREAPPROTECT + will be disabled. + +config NRF_SECURE_APPROTECT_LOCK + bool "Lock" + help + When this option is selected, the SystemInit() function locks the + firmware branch of the secure APPROTECT mechanism, preventing it + from being opened. + +config NRF_SECURE_APPROTECT_USER_HANDLING + bool "Allow user handling" + depends on !SOC_SERIES_NRF52X + help + When this option is selected, the SystemInit() function does not + touch the secure APPROTECT mechanism, allowing the user code to + handle it at later stages, for example, to implement authenticated + debug. + +endchoice + +config NRF_TRACE_PORT + bool "nRF TPIU" + depends on !SOC_SERIES_NRF51X + help + Enable this option to initialize the TPIU (Trace Port Interface + Unit) for tracing using a hardware probe. If disabled, the trace + pins will be used as GPIO. + +endif # SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/Kconfig.defconfig b/soc/nordic/Kconfig.defconfig new file mode 100644 index 00000000000000..5e7e9c5a09dc7d --- /dev/null +++ b/soc/nordic/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Nordic Semiconductor nRFx MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NORDIC_NRF + +rsource "*/Kconfig.defconfig" + +# If the kernel has timer support, enable clock control +if SYS_CLOCK_EXISTS + +config CLOCK_CONTROL + default y if !SOC_SERIES_NRF54HX + +endif # SYS_CLOCK_EXISTS + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 if NRF_GRTC_TIMER + default 32768 + +config SYS_CLOCK_TICKS_PER_SEC + default 128 if !TICKLESS_KERNEL + default 10000 if NRF_GRTC_TIMER + default 32768 + +config ARCH_HAS_CUSTOM_BUSY_WAIT + default y if ARM && !QEMU_TARGET + +config BUILD_OUTPUT_HEX + default y + +if !CORTEX_M_DWT && NRF_RTC_TIMER +config SOC_HAS_TIMING_FUNCTIONS + default y +endif + +config GPIO + default y + depends on SPI + +config UART_USE_RUNTIME_CONFIGURE + default n + +endif # SOC_FAMILY_NORDIC_NRF diff --git a/soc/nordic/Kconfig.soc b/soc/nordic/Kconfig.soc new file mode 100644 index 00000000000000..2e47fcb4736116 --- /dev/null +++ b/soc/nordic/Kconfig.soc @@ -0,0 +1,59 @@ +# Copyright (c) 2022 Nordic Semiconductor ASA + +# SPDX-License-Identifier: Apache-2.0 + +# This file contains Zephyr hw module v2 Kconfig description for +# Nordic Semiconductor SoCs. +# The hw model v2 is generic and contains no Kconfig references outside its own +# tree structure and is therefore reusable in Kconfig trees outside a Zephyr build. + +config SOC_SERIES + default "nrf51" if SOC_SERIES_NRF51X + default "nrf52" if SOC_SERIES_NRF52X + default "nrf53" if SOC_SERIES_NRF53X + default "nrf54h" if SOC_SERIES_NRF54HX + default "nrf54l" if SOC_SERIES_NRF54LX + default "nrf91" if SOC_SERIES_NRF91X + +config SOC_FAMILY_NORDIC_NRF + bool + +config SOC_FAMILY + default "nordic_nrf" if SOC_FAMILY_NORDIC_NRF + +config SOC_SERIES_NRF51X + bool + help + Enable support for NRF51 MCU series + +config SOC_SERIES_NRF52X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF52 MCU series + +config SOC_SERIES_NRF53X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF53 MCU series + +config SOC_SERIES_NRF54HX + bool + select SOC_FAMILY_NORDIC_NRF + help + Nordic Semiconductor nRF54H series MCU + +config SOC_SERIES_NRF54LX + bool + select SOC_FAMILY_NORDIC_NRF + help + Nordic Semiconductor nRF54L series MCU + +config SOC_SERIES_NRF91X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF91 MCU series + +rsource "*/Kconfig.soc" diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt new file mode 100644 index 00000000000000..d3cb84fd451eaf --- /dev/null +++ b/soc/nordic/common/CMakeLists.txt @@ -0,0 +1,19 @@ +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) + +if(CONFIG_ARM AND CONFIG_SOC_FAMILY_NORDIC_NRF) + zephyr_library_sources(soc_nrf_common.S) +endif() + +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +if(CONFIG_TFM_PARTITION_PLATFORM) + zephyr_library_sources(soc_secure.c) + zephyr_library_include_directories( + $/api_ns/interface/include + ) +endif() diff --git a/soc/nordic/common/Kconfig b/soc/nordic/common/Kconfig new file mode 100644 index 00000000000000..54e2356c6af938 --- /dev/null +++ b/soc/nordic/common/Kconfig @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +rsource "vpr/Kconfig" diff --git a/soc/nordic/common/Kconfig.defconfig b/soc/nordic/common/Kconfig.defconfig new file mode 100644 index 00000000000000..077a73ad24d999 --- /dev/null +++ b/soc/nordic/common/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if RISCV_CORE_NORDIC_VPR + +rsource "vpr/Kconfig.defconfig" + +endif # RISCV_CORE_NORDIC_VPR diff --git a/soc/common/nordic_nrf/Kconfig.peripherals b/soc/nordic/common/Kconfig.peripherals similarity index 100% rename from soc/common/nordic_nrf/Kconfig.peripherals rename to soc/nordic/common/Kconfig.peripherals diff --git a/soc/common/nordic_nrf/pinctrl_soc.h b/soc/nordic/common/pinctrl_soc.h similarity index 100% rename from soc/common/nordic_nrf/pinctrl_soc.h rename to soc/nordic/common/pinctrl_soc.h diff --git a/soc/arm/nordic_nrf/common/poweroff.c b/soc/nordic/common/poweroff.c similarity index 100% rename from soc/arm/nordic_nrf/common/poweroff.c rename to soc/nordic/common/poweroff.c diff --git a/soc/arm/nordic_nrf/common/soc_nrf_common.S b/soc/nordic/common/soc_nrf_common.S similarity index 100% rename from soc/arm/nordic_nrf/common/soc_nrf_common.S rename to soc/nordic/common/soc_nrf_common.S diff --git a/soc/arm/nordic_nrf/common/soc_nrf_common.h b/soc/nordic/common/soc_nrf_common.h similarity index 100% rename from soc/arm/nordic_nrf/common/soc_nrf_common.h rename to soc/nordic/common/soc_nrf_common.h diff --git a/soc/arm/nordic_nrf/common/soc_secure.c b/soc/nordic/common/soc_secure.c similarity index 100% rename from soc/arm/nordic_nrf/common/soc_secure.c rename to soc/nordic/common/soc_secure.c diff --git a/soc/arm/nordic_nrf/common/soc_secure.h b/soc/nordic/common/soc_secure.h similarity index 100% rename from soc/arm/nordic_nrf/common/soc_secure.h rename to soc/nordic/common/soc_secure.h diff --git a/soc/nordic/common/vpr/CMakeLists.txt b/soc/nordic/common/vpr/CMakeLists.txt new file mode 100644 index 00000000000000..f69b830b465f61 --- /dev/null +++ b/soc/nordic/common/vpr/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library_sources(soc_irq.S soc_irq.c vector.S) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/nordic_nrf/common/vpr/Kconfig b/soc/nordic/common/vpr/Kconfig similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/Kconfig rename to soc/nordic/common/vpr/Kconfig diff --git a/soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig b/soc/nordic/common/vpr/Kconfig.defconfig similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig rename to soc/nordic/common/vpr/Kconfig.defconfig diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_context.h b/soc/nordic/common/vpr/soc_context.h similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_context.h rename to soc/nordic/common/vpr/soc_context.h diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_irq.S b/soc/nordic/common/vpr/soc_irq.S similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_irq.S rename to soc/nordic/common/vpr/soc_irq.S diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_irq.c b/soc/nordic/common/vpr/soc_irq.c similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_irq.c rename to soc/nordic/common/vpr/soc_irq.c diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_isr_stacking.h b/soc/nordic/common/vpr/soc_isr_stacking.h similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_isr_stacking.h rename to soc/nordic/common/vpr/soc_isr_stacking.h diff --git a/soc/riscv/nordic_nrf/common/vpr/soc_offsets.h b/soc/nordic/common/vpr/soc_offsets.h similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/soc_offsets.h rename to soc/nordic/common/vpr/soc_offsets.h diff --git a/soc/riscv/nordic_nrf/common/vpr/vector.S b/soc/nordic/common/vpr/vector.S similarity index 100% rename from soc/riscv/nordic_nrf/common/vpr/vector.S rename to soc/nordic/common/vpr/vector.S diff --git a/soc/nordic/nrf51/CMakeLists.txt b/soc/nordic/nrf51/CMakeLists.txt new file mode 100644 index 00000000000000..533987519826e9 --- /dev/null +++ b/soc/nordic/nrf51/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) diff --git a/soc/nordic/nrf51/Kconfig b/soc/nordic/nrf51/Kconfig new file mode 100644 index 00000000000000..e212c7ecd660fc --- /dev/null +++ b/soc/nordic/nrf51/Kconfig @@ -0,0 +1,13 @@ +# Nordic Semiconductor nRF51 MCU line + +# Copyright (c) 2016 Linaro Limited +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF51X + select ARM + select CPU_CORTEX_M0 + imply XIP + select HAS_NRFX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_POWEROFF diff --git a/soc/nordic/nrf51/Kconfig.defconfig b/soc/nordic/nrf51/Kconfig.defconfig new file mode 100644 index 00000000000000..0168531e1d5d9b --- /dev/null +++ b/soc/nordic/nrf51/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Nordic Semiconductor nRF51 MCU line + +# Copyright (c) 2016 Linaro Limited +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF51X + +config NUM_IRQS + default 26 + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF51X diff --git a/soc/nordic/nrf51/Kconfig.soc b/soc/nordic/nrf51/Kconfig.soc new file mode 100644 index 00000000000000..c19da7a18a14d5 --- /dev/null +++ b/soc/nordic/nrf51/Kconfig.soc @@ -0,0 +1,24 @@ +# Nordic Semiconductor nRF51 MCU line + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF51X + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF51 MCU series + +config SOC_NRF51822_QFAA + bool + select SOC_SERIES_NRF51X + +config SOC_NRF51822_QFAB + bool + select SOC_SERIES_NRF51X + +config SOC_NRF51822_QFAC + bool + select SOC_SERIES_NRF51X + +config SOC + default "nrf51822" if SOC_NRF51822_QFAA || SOC_NRF51822_QFAB || SOC_NRF51822_QFAC diff --git a/soc/arm/nordic_nrf/nrf51/soc.c b/soc/nordic/nrf51/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf51/soc.c rename to soc/nordic/nrf51/soc.c diff --git a/soc/arm/nordic_nrf/nrf51/soc.h b/soc/nordic/nrf51/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf51/soc.h rename to soc/nordic/nrf51/soc.h diff --git a/soc/nordic/nrf52/CMakeLists.txt b/soc/nordic/nrf52/CMakeLists.txt new file mode 100644 index 00000000000000..6b01a1ffc778aa --- /dev/null +++ b/soc/nordic/nrf52/CMakeLists.txt @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) + +if(CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 AND CONFIG_SPI_NRFX_SPIM) + message(WARNING "Both SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58 and an NRF SPIM driver are enabled, therefore PAN 58 will apply if RXD.MAXCNT == 1 and TXD.MAXCNT <= 1") +endif() + +if(CONFIG_SOC_NRF52832) + if(NOT CONFIG_NRF52_ANOMALY_109_WORKAROUND) + if (CONFIG_NRFX_SPIS OR CONFIG_NRFX_SPIM OR CONFIG_NRFX_TWIM OR CONFIG_NRFX_PWM) + message(WARNING "NRF52_ANOMALY_109_WORKAROUND disabled with SPIS, SPIM, TWIM or PWM enabled. This will occasionally cause the first byte transmitted to be incorrect") + endif() + endif() +endif() diff --git a/soc/nordic/nrf52/Kconfig b/soc/nordic/nrf52/Kconfig new file mode 100644 index 00000000000000..b248b972f94d8a --- /dev/null +++ b/soc/nordic/nrf52/Kconfig @@ -0,0 +1,106 @@ +# Nordic Semiconductor nRF52 MCU line + +# Copyright (c) 2016-2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF52X + select ARM + select SOC_COMPATIBLE_NRF52X + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + imply XIP + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_SWO + select HAS_POWEROFF + +config SOC_NRF52832 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + +config SOC_NRF52833 + select SOC_COMPATIBLE_NRF52833 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + +config SOC_NRF52840 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + +if SOC_SERIES_NRF52X + +config SOC_DCDC_NRF52X + bool + help + Enable nRF52 series System on Chip DC/DC converter. + +config SOC_DCDC_NRF52X_HV + bool + depends on SOC_NRF52840_QIAA + help + Enable nRF52 series System on Chip High Voltage DC/DC converter. + +config GPIO_AS_PINRESET + bool "[DEPRECATED] GPIO as pin reset (reset button)" + select DEPRECATED + help + This option is deprecated, use devicetree instead. Example + configuration: + + &uicr { + gpio-as-nreset; + }; + +config NRF_ENABLE_ICACHE + bool "The instruction cache (I-Cache)" + depends on SOC_NRF52832 || SOC_NRF52833 || SOC_NRF52840 + default y + +config NRF52_ANOMALY_132_DELAY_US + int "Anomaly 132 workaround delay (microseconds)" + default 330 + range 0 330 + depends on NRF52_ANOMALY_132_WORKAROUND + help + Due to Anomaly 132 LF RC source may not start if restarted in certain + window after stopping (230 us to 330 us). Software reset also stops the + clock so if clock is initiated in certain window, the clock may also fail + to start at reboot. A delay is added before starting LF clock to ensure + that anomaly conditions are not met. Delay should be long enough to ensure + that clock is started later than 330 us after reset. If crystal oscillator + (XO) is used then low frequency clock initially starts with RC and then + seamlessly switches to XO which has much longer startup time thus, + depending on application, workaround may also need to be applied. + Additional drivers initialization increases initialization time and delay + may be shortened. Workaround is disabled by setting delay to 0. + +config NRF52_ANOMALY_198_WORKAROUND + bool "Anomaly 198 workaround" + default y + depends on SOC_NRF52840 + depends on NRFX_SPIM3 + help + This anomaly applies to IC revisions "Engineering B" up to "3", the most + recent one. + +config NRF52_ANOMALY_109_WORKAROUND + bool "Anomaly 109 workaround" + default y + depends on SOC_NRF52832 + depends on NRFX_SPIS || NRFX_SPIM || NRFX_TWIM || NRFX_PWM + help + Due to Anomaly 109 the first byte sent out by these peripherals is + sometimes wrong. This occurs when the system enters IDLE and stops the + 64MHz clock at the same time as the peripheral that is using DMA is started. + This anomaly applies to IC revisions up to "3", the most recent one. + +config NRF52_ANOMALY_109_WORKAROUND_EGU_INSTANCE + int "Anomaly 109 workaround EGU instance" + depends on NRF52_ANOMALY_109_WORKAROUND + range 0 5 + default 5 + help + EGU instance used by the nRF52 Anomaly 109 workaround for PWM. + +endif # SOC_SERIES_NRF52X diff --git a/soc/nordic/nrf52/Kconfig.defconfig b/soc/nordic/nrf52/Kconfig.defconfig new file mode 100644 index 00000000000000..eed012878e25bd --- /dev/null +++ b/soc/nordic/nrf52/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF52 MCU line + +# Copyright (c) 2016-2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF52X + +rsource "Kconfig.defconfig.nrf52*" + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF52X diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52805_CAAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52805_CAAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA index 25bf9b4e68f56b..684276ebb5416e 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52805_CAAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52805_CAAA @@ -5,9 +5,6 @@ if SOC_NRF52805_CAAA -config SOC - default "nRF52805_CAAA" - config NUM_IRQS default 26 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52810_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52810_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA index 1b5a7b5c314070..7f87637b92f928 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52810_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52810_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52810_QFAA -config SOC - default "nRF52810_QFAA" - config NUM_IRQS default 30 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52811_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52811_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA index 7b291305208dbc..bc4c757e6f8594 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52811_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52811_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52811_QFAA -config SOC - default "nRF52811_QFAA" - config NUM_IRQS default 30 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52820_QDAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA similarity index 81% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52820_QDAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA index 4aa761b93be8cd..2db0291afad8de 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52820_QDAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52820_QDAA @@ -5,10 +5,6 @@ if SOC_NRF52820_QDAA -config SOC - string - default "nRF52820_QDAA" - config NUM_IRQS int default 40 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_CIAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA similarity index 87% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_CIAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA index 4060453badcf48..4f9101f4c61433 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_CIAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_CIAA @@ -5,9 +5,6 @@ if SOC_NRF52832_CIAA -config SOC - default "nRF52832_CIAA" - config NUM_IRQS default 39 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA similarity index 87% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA index cc48aaeaccbfa5..b579b1e3ed080c 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52832_QFAA -config SOC - default "nRF52832_QFAA" - config NUM_IRQS default 39 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAB b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB similarity index 87% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAB rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB index 2b9491cae3babe..1c494d222c96c9 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52832_QFAB +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52832_QFAB @@ -5,9 +5,6 @@ if SOC_NRF52832_QFAB -config SOC - default "nRF52832_QFAB" - config NUM_IRQS default 39 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QDAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA similarity index 81% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QDAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA index 237bee5813a291..055544288e4f28 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QDAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QDAA @@ -5,10 +5,6 @@ if SOC_NRF52833_QDAA -config SOC - string - default "nRF52833_QDAA" - config NUM_IRQS int default 48 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA similarity index 81% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA index 6256b30e741de7..add0c89503b4f7 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52833_QIAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52833_QIAA @@ -5,10 +5,6 @@ if SOC_NRF52833_QIAA -config SOC - string - default "nRF52833_QIAA" - config NUM_IRQS int default 48 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QFAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QFAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA index 451fea911b45a6..877e553cd23b7d 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QFAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QFAA @@ -5,9 +5,6 @@ if SOC_NRF52840_QFAA -config SOC - default "nRF52840_QFAA" - config NUM_IRQS default 48 diff --git a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QIAA b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA similarity index 84% rename from soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QIAA rename to soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA index 62ca5e76cbd664..a2ac50ca5dd6ee 100644 --- a/soc/arm/nordic_nrf/nrf52/Kconfig.defconfig.nrf52840_QIAA +++ b/soc/nordic/nrf52/Kconfig.defconfig.nrf52840_QIAA @@ -5,9 +5,6 @@ if SOC_NRF52840_QIAA -config SOC - default "nRF52840_QIAA" - config NUM_IRQS default 48 diff --git a/soc/nordic/nrf52/Kconfig.soc b/soc/nordic/nrf52/Kconfig.soc new file mode 100644 index 00000000000000..24a5249205da96 --- /dev/null +++ b/soc/nordic/nrf52/Kconfig.soc @@ -0,0 +1,90 @@ +# Nordic Semiconductor nRF52 MCU line, Zephyr hw model v2 compliant + +# Copyright (c) 2022-2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF52X + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF52 MCU series + +config SOC_NRF52805 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52810 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52811 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52820 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52832 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52833 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52840 + bool + select SOC_SERIES_NRF52X + +config SOC_NRF52805_CAAA + bool + select SOC_NRF52805 + +config SOC_NRF52810_QFAA + bool + select SOC_NRF52810 + +config SOC_NRF52811_QFAA + bool + select SOC_NRF52811 + +config SOC_NRF52820_QDAA + bool + select SOC_NRF52820 + +config SOC_NRF52832_CIAA + bool + select SOC_NRF52832 + +config SOC_NRF52832_QFAA + bool + select SOC_NRF52832 + +config SOC_NRF52832_QFAB + bool + select SOC_NRF52832 + +config SOC_NRF52833_QDAA + bool + select SOC_NRF52833 + +config SOC_NRF52833_QIAA + bool + select SOC_NRF52833 + +config SOC_NRF52840_QFAA + bool + select SOC_NRF52840 + +config SOC_NRF52840_QIAA + bool + select SOC_NRF52840 + +config SOC + default "nrf52805" if SOC_NRF52805_CAAA + default "nrf52810" if SOC_NRF52810_QFAA + default "nrf52811" if SOC_NRF52811_QFAA + default "nrf52820" if SOC_NRF52820_QDAA + default "nrf52832" if SOC_NRF52832_CIAA || SOC_NRF52832_QFAA || SOC_NRF52832_QFAB + default "nrf52833" if SOC_NRF52833_QDAA || SOC_NRF52833_QIAA + default "nrf52840" if SOC_NRF52840_QFAA || SOC_NRF52840_QIAA diff --git a/soc/arm/nordic_nrf/nrf52/soc.c b/soc/nordic/nrf52/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf52/soc.c rename to soc/nordic/nrf52/soc.c diff --git a/soc/arm/nordic_nrf/nrf52/soc.h b/soc/nordic/nrf52/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf52/soc.h rename to soc/nordic/nrf52/soc.h diff --git a/soc/nordic/nrf53/CMakeLists.txt b/soc/nordic/nrf53/CMakeLists.txt new file mode 100644 index 00000000000000..0e8b1e69a29dfe --- /dev/null +++ b/soc/nordic/nrf53/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_NRF53_SYNC_RTC sync_rtc.c) + +if (CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED AND + NOT CONFIG_SYS_CLOCK_EXISTS) + message(WARNING " + Your application may be affected by the anomaly 160 that concerns the + nRF5340 SoC. The related workaround cannot be applied, because your + application has the system clock disabled (CONFIG_SYS_CLOCK_EXISTS=n). + Consider enabling the system clock to apply the workaround. + " " + At your own risk, you can suppress this warning by setting + CONFIG_SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED=n.") +endif() diff --git a/soc/nordic/nrf53/Kconfig b/soc/nordic/nrf53/Kconfig new file mode 100644 index 00000000000000..7ef9546058d975 --- /dev/null +++ b/soc/nordic/nrf53/Kconfig @@ -0,0 +1,227 @@ +# Nordic Semiconductor nRF53 MCU line + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF53X + bool + select ARM + select SOC_COMPATIBLE_NRF53X + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + imply XIP + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_SWO + help + Enable support for NRF53 MCU series + +config SOC_NRF5340_CPUAPP + select CPU_HAS_NRF_IDAU + select CPU_HAS_FPU + select ARMV8_M_DSP + select HAS_POWEROFF + select SOC_COMPATIBLE_NRF5340_CPUAPP + imply SOC_NRF53_RTC_PRETICK + imply SOC_NRF53_ANOMALY_168_WORKAROUND + +config SOC_NRF5340_CPUNET + select ARM_ON_EXIT_CPU_IDLE + select SOC_COMPATIBLE_NRF5340_CPUNET + imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX + imply SOC_NRF53_ANOMALY_168_WORKAROUND + +if SOC_SERIES_NRF53X + +config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + bool "Workaround for nRF5340 anomaly 160" + imply SOC_NRF53_ANOMALY_160_WORKAROUND + help + Indicates that the workaround for the anomaly 160 that affects + the nRF5340 SoC should be applied. + This option is enabled by default for the Application MCU when + DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator + and always for the Network MCU. + If this option is enabled, but the workaround cannot be applied, + because the system clock is disabled, a related cmake warning is + issued. + +config SOC_NRF53_ANOMALY_160_WORKAROUND + bool + depends on SYS_CLOCK_EXISTS + select ARM_ON_ENTER_CPU_IDLE_HOOK + +config SOC_NRF53_ANOMALY_168_WORKAROUND + bool "Workaround for nRF5340 anomaly 168" + select ARM_ON_EXIT_CPU_IDLE + help + Indicates that the workaround for the anomaly 168 that affects + the nRF5340 SoC should be applied. + The workaround involves execution of 8 NOP instructions when the CPU + exist its idle state (when the WFI/WFE instruction returns) and it is + enabled by default for both the application and network core. + +config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM + bool "Extend the workaround to execution at 128 MHz from RAM" + depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP + help + Indicates that the anomaly 168 workaround is to be extended to cover + also a specific case when the WFI/WFE instruction is executed at 128 + MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be + executed after WFI/WFE. This extension is not enabled by default. + +config SOC_NRF53_RTC_PRETICK + bool "Pre-tick workaround for nRF5340 anomaly 165" + depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP + select NRFX_DPPI + select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET + select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET + help + Indicates that the pre-tick workaround for the anomaly 165 that affects + the nRF5340 SoC should be applied. The workaround applies to wake ups caused + by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are + enabled through INTENSET register. The case when these events are generated + by EVTEN but without interrupts enabled through INTENSET is not handled. + The EVENTS_TICK event is not handled. + +if SOC_NRF53_RTC_PRETICK + +config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET + int "IPC 0 channel for RTC pretick" + range 0 15 + default 10 + +config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET + int "IPC 1 channel for RTC pretick" + range 0 15 + default 11 + +endif + +if SOC_NRF5340_CPUAPP + +config SOC_DCDC_NRF53X_APP + bool + imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + help + Enable nRF53 series System on Chip Application MCU DC/DC converter. + +config SOC_DCDC_NRF53X_NET + bool + imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED + help + Enable nRF53 series System on Chip Network MCU DC/DC converter. + +config SOC_DCDC_NRF53X_HV + bool + help + Enable nRF53 series System on Chip High Voltage DC/DC converter. + +config NRF_SPU_FLASH_REGION_SIZE + hex + default 0x4000 + help + FLASH region size for the NRF_SPU peripheral + +config NRF_SPU_RAM_REGION_SIZE + hex + default 0x2000 + help + RAM region size for the NRF_SPU peripheral + +config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 + bool + depends on NRF_SOC_SECURE_SUPPORTED + help + hidden option for including the nRF GPIO pin forwarding + +if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM + +config SOC_ENABLE_LFXO + bool "LFXO" + default y + help + Enable the low-frequency oscillator (LFXO) functionality on XL1 and + XL2 pins. + This option must be enabled if either application or network core is + to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular + GPIOs. + +choice SOC_LFXO_LOAD_CAPACITANCE + prompt "LFXO load capacitance" + depends on SOC_ENABLE_LFXO + default SOC_LFXO_CAP_INT_7PF + +config SOC_LFXO_CAP_EXTERNAL + bool "Use external load capacitors" + +config SOC_LFXO_CAP_INT_6PF + bool "6 pF internal load capacitance" + +config SOC_LFXO_CAP_INT_7PF + bool "7 pF internal load capacitance" + +config SOC_LFXO_CAP_INT_9PF + bool "9 pF internal load capacitance" + +endchoice + +choice SOC_HFXO_LOAD_CAPACITANCE + prompt "HFXO load capacitance" + default SOC_HFXO_CAP_DEFAULT + +config SOC_HFXO_CAP_DEFAULT + bool "SoC default" + help + When this option is used, the SoC initialization routine does not + touch the XOSC32MCAPS register value, so the default setting for + the SoC is in effect. Please note that this may not necessarily be + the reset value (0) for the register, as the register can be set + during the device trimming in the SystemInit() function. + +config SOC_HFXO_CAP_EXTERNAL + bool "Use external load capacitors" + +config SOC_HFXO_CAP_INTERNAL + bool "Use internal load capacitors" + depends on NRF_SOC_SECURE_SUPPORTED + +endchoice + +config SOC_HFXO_CAP_INT_VALUE_X2 + int "Doubled value of HFXO internal load capacitors (in pF)" + depends on SOC_HFXO_CAP_INTERNAL + range 14 40 + help + Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps + can be enabled on pins XC1 and XC2. This option specifies doubled + capacitance value for the two capacitors. Set it to 14 to get 7.0 pF + for each capacitor, 15 to get 7.5 pF, and so on. + +endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM + +endif # SOC_NRF5340_CPUAPP + + +config NRF_ENABLE_CACHE + bool "Cache" + depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \ + || SOC_NRF5340_CPUNET + default y + help + Instruction and Data cache is available on nRF5340 CPUAPP + (Application MCU). It may only be accessed by Secure code. + + Instruction cache only (I-Cache) is available in nRF5340 + CPUNET (Network MCU). + +config BUILD_WITH_TFM + # TF-M nRF53 platform enables the cache unconditionally. + select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP + +rsource "Kconfig.sync_rtc" + +endif # SOC_SERIES_NRF53X diff --git a/soc/nordic/nrf53/Kconfig.defconfig b/soc/nordic/nrf53/Kconfig.defconfig new file mode 100644 index 00000000000000..d41e2e57f58e11 --- /dev/null +++ b/soc/nordic/nrf53/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF53 MCU line + +# Copyright (c) 2019 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF53X + +rsource "Kconfig.defconfig.nrf53*" + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF53X diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA similarity index 91% rename from soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA rename to soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA index f0f7f5a7d84180..ab74bd6a9fbfb2 100644 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA +++ b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA @@ -5,9 +5,6 @@ if SOC_NRF5340_CPUAPP_QKAA -config SOC - default "nRF5340_CPUAPP_QKAA" - config NUM_IRQS default 69 diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA similarity index 90% rename from soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA rename to soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA index 0c60adc04f3b4b..41961784daf38d 100644 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA +++ b/soc/nordic/nrf53/Kconfig.defconfig.nrf5340_CPUNET_QKAA @@ -5,9 +5,6 @@ if SOC_NRF5340_CPUNET_QKAA -config SOC - default "nRF5340_CPUNET_QKAA" - config NUM_IRQS default 30 diff --git a/soc/nordic/nrf53/Kconfig.soc b/soc/nordic/nrf53/Kconfig.soc new file mode 100644 index 00000000000000..ff32aabf7fe2da --- /dev/null +++ b/soc/nordic/nrf53/Kconfig.soc @@ -0,0 +1,29 @@ +# Nordic Semiconductor nRF52 MCU line, Zephyr hw model v2 compliant + +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF53X + bool + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF53 MCU series + +config SOC_NRF5340_CPUAPP + bool + select SOC_SERIES_NRF53X + +config SOC_NRF5340_CPUNET + bool + select SOC_SERIES_NRF53X + +config SOC_NRF5340_CPUAPP_QKAA + bool + select SOC_NRF5340_CPUAPP + +config SOC_NRF5340_CPUNET_QKAA + bool + select SOC_NRF5340_CPUNET + +config SOC + default "nrf5340" if SOC_NRF5340_CPUAPP_QKAA || SOC_NRF5340_CPUNET_QKAA diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc b/soc/nordic/nrf53/Kconfig.sync_rtc similarity index 100% rename from soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc rename to soc/nordic/nrf53/Kconfig.sync_rtc diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc_ipm b/soc/nordic/nrf53/Kconfig.sync_rtc_ipm similarity index 100% rename from soc/arm/nordic_nrf/nrf53/Kconfig.sync_rtc_ipm rename to soc/nordic/nrf53/Kconfig.sync_rtc_ipm diff --git a/soc/arm/nordic_nrf/nrf53/soc.c b/soc/nordic/nrf53/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf53/soc.c rename to soc/nordic/nrf53/soc.c diff --git a/soc/arm/nordic_nrf/nrf53/soc.h b/soc/nordic/nrf53/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf53/soc.h rename to soc/nordic/nrf53/soc.h diff --git a/soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h b/soc/nordic/nrf53/soc_cpu_idle.h similarity index 100% rename from soc/arm/nordic_nrf/nrf53/soc_cpu_idle.h rename to soc/nordic/nrf53/soc_cpu_idle.h diff --git a/soc/arm/nordic_nrf/nrf53/sync_rtc.c b/soc/nordic/nrf53/sync_rtc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf53/sync_rtc.c rename to soc/nordic/nrf53/sync_rtc.c diff --git a/soc/nordic/nrf54h/CMakeLists.txt b/soc/nordic/nrf54h/CMakeLists.txt new file mode 100644 index 00000000000000..67a6dab6f8a703 --- /dev/null +++ b/soc/nordic/nrf54h/CMakeLists.txt @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_NRF54H20_ENGA_CPUAPP OR CONFIG_SOC_NRF54H20_ENGA_CPURAD) + zephyr_include_directories(.) + zephyr_library_sources(soc.c) +endif() + +# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes +# for the image correctly +zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig new file mode 100644 index 00000000000000..d9d5b0789f9da5 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig @@ -0,0 +1,41 @@ +# Nordic Semiconductor nRF54H MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF54HX + select HAS_NRFX + select HAS_NORDIC_DRIVERS + +config SOC_NRF54H20_ENGA_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54H20_ENGA_CPURAD + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_DCACHE + select CPU_HAS_ICACHE + select CPU_HAS_FPU + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54H20_ENGA_CPUPPR + depends on RISCV_CORE_NORDIC_VPR + +if SOC_NRF54H20 + +config NRF_ENABLE_ICACHE + bool "Instruction cache (I-Cache)" + default y + +endif # SOC_NRF54H20 diff --git a/soc/nordic/nrf54h/Kconfig.defconfig b/soc/nordic/nrf54h/Kconfig.defconfig new file mode 100644 index 00000000000000..72ba234e883b4f --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig @@ -0,0 +1,36 @@ +# Nordic Semiconductor nRF54H MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF54HX + +rsource "Kconfig.defconfig.nrf54h*" + +if ARM + +config CACHE_NRF_CACHE + default y if EXTERNAL_CACHE + +endif # ARM + +if RISCV + +DT_CHOSEN_Z_SRAM = zephyr,sram +DT_CHOSEN_Z_CODE = zephyr,code-partition + +config BUILD_OUTPUT_ADJUST_LMA + depends on !XIP + default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))" + +config BUILD_OUTPUT_HEX + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 if NRF_GRTC_TIMER + default 32768 if NRF_RTC_TIMER + +endif # RISCV + +endif # SOC_SERIES_NRF54HX diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp new file mode 100644 index 00000000000000..af261c3e0a31fa --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuapp @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF54H20 Application MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_ENGA_CPUAPP + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_ENGA_CPUAPP diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr similarity index 83% rename from soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr rename to soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr index a36d24c72ae204..3d48375b97d37b 100644 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpuppr @@ -3,9 +3,6 @@ if SOC_NRF54H20_ENGA_CPUPPR -config SOC - default "nrf54h20_enga_cpuppr" - config NUM_IRQS default 496 diff --git a/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad new file mode 100644 index 00000000000000..e83eea71b48bf7 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.defconfig.nrf54h20_enga_cpurad @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF54H20 Radio MCU + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NRF54H20_ENGA_CPURAD + +config NUM_IRQS + default 471 + +config NRF_REGTOOL_GENERATE_UICR + default y + +endif # SOC_NRF54H20_ENGA_CPURAD diff --git a/soc/nordic/nrf54h/Kconfig.soc b/soc/nordic/nrf54h/Kconfig.soc new file mode 100644 index 00000000000000..7ea87db22a4330 --- /dev/null +++ b/soc/nordic/nrf54h/Kconfig.soc @@ -0,0 +1,31 @@ +# Nordic Semiconductor nRF54H MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NRF54H20 + bool + select SOC_SERIES_NRF54HX + help + nRF54H20 + +config SOC_NRF54H20_ENGA_CPUAPP + bool + select SOC_NRF54H20 + help + nRF54H20 ENGA CPUAPP + +config SOC_NRF54H20_ENGA_CPURAD + bool + select SOC_NRF54H20 + help + nRF54H20 ENGA CPURAD + +config SOC_NRF54H20_ENGA_CPUPPR + bool + select SOC_NRF54H20 + help + nRF54H20 ENGA CPUPPR + +config SOC + default "nrf54h20" if SOC_NRF54H20 diff --git a/soc/arm/nordic_nrf/nrf54h/align.ld b/soc/nordic/nrf54h/align.ld similarity index 100% rename from soc/arm/nordic_nrf/nrf54h/align.ld rename to soc/nordic/nrf54h/align.ld diff --git a/soc/arm/nordic_nrf/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf54h/soc.c rename to soc/nordic/nrf54h/soc.c diff --git a/soc/arm/nordic_nrf/nrf54h/soc.h b/soc/nordic/nrf54h/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf54h/soc.h rename to soc/nordic/nrf54h/soc.h diff --git a/soc/nordic/nrf54l/CMakeLists.txt b/soc/nordic/nrf54l/CMakeLists.txt new file mode 100644 index 00000000000000..f1c18291fc6bf8 --- /dev/null +++ b/soc/nordic/nrf54l/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources( + soc.c + ../validate_rram_partitions.c + ) +zephyr_include_directories(.) + +if(CONFIG_ELV_GRTC_LFXO_ALLOWED) + message(WARNING "WARNING! ELV mode feature is EXPERIMENTAL and may brick your device!") +endif() diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig new file mode 100644 index 00000000000000..6841e1478f7cf8 --- /dev/null +++ b/soc/nordic/nrf54l/Kconfig @@ -0,0 +1,66 @@ +# Nordic Semiconductor nRF54 MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF54LX + select HAS_NRFX + select HAS_NORDIC_DRIVERS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +config SOC_NRF54L15_ENGA_CPUAPP + select ARM + select ARMV8_M_DSP + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_HW_NRF_RADIO_IEEE802154 + select HAS_POWEROFF + +if SOC_SERIES_NRF54LX + +config SOC_NRF54LX_SKIP_CLOCK_CONFIG + bool "Skip clock frequency configuration in system initialization" + help + With this option, the CPU clock frequency is not set during system initialization. + The CPU runs with the default, hardware-selected frequency. + +config SOC_NRF_FORCE_CONSTLAT + bool "Force constant-latency mode" + help + In constant latency mode the CPU wakeup latency and the PPI task response + will be constant and kept at a minimum. This is secured by forcing a set + of base resources on while in sleep. The advantage of having a constant + and predictable latency will be at the cost of having increased power consumption. + +config SOC_NRF54L_VREG_MAIN_DCDC + bool "NRF54L DC/DC converter." + help + To enable, an inductor must be connected to the DC/DC converter pin. + +config SOC_NRF54L_NORMAL_VOLTAGE_MODE + bool "NRF54L Normal Voltage Mode." + +config SOC_NRF54L_GLITCHDET_WORKAROUND + bool "Workaround that disables glitch detector" + default y + help + Temporary workaround - disabling glitch detector to limit power consumption. + +if NRF_GRTC_TIMER + +config ELV_GRTC_LFXO_ALLOWED + bool + depends on NRF_GRTC_SLEEP_ALLOWED + select EXPERIMENTAL + help + This feature allows using ELV mode when GRTC operates with the LFXO as + a low-frequency clock source. The LFXO is automatically activated when + preparing to system-off. + WARNING! This feature is EXPERIMENTAL and may brick your device! + +endif # NRF_GRTC_TIMER + +endif # SOC_SERIES_NRF54LX diff --git a/soc/nordic/nrf54l/Kconfig.defconfig b/soc/nordic/nrf54l/Kconfig.defconfig new file mode 100644 index 00000000000000..39ed9025ea045e --- /dev/null +++ b/soc/nordic/nrf54l/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Nordic Semiconductor nRF54L MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF54LX + +rsource "Kconfig.defconfig.nrf54l*" + +config CORTEX_M_SYSTICK + default !NRF_GRTC_TIMER + +config CACHE_NRF_CACHE + default y if EXTERNAL_CACHE + +endif # SOC_SERIES_NRF54LX diff --git a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp similarity index 84% rename from soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp rename to soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp index d19df604c02762..80957abfdd7d6d 100644 --- a/soc/arm/nordic_nrf/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp +++ b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l15_enga_cpuapp @@ -5,10 +5,6 @@ if SOC_NRF54L15_ENGA_CPUAPP -config SOC - string - default "nrf54l15_cpuapp" - config NUM_IRQS default 271 diff --git a/soc/nordic/nrf54l/Kconfig.soc b/soc/nordic/nrf54l/Kconfig.soc new file mode 100644 index 00000000000000..05ce9db0a3e127 --- /dev/null +++ b/soc/nordic/nrf54l/Kconfig.soc @@ -0,0 +1,25 @@ +# Nordic Semiconductor nRF54L MCU line + +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NRF54L15 + bool + select SOC_SERIES_NRF54LX + help + NRF54L15 + +config SOC_NRF54L15_ENGA + bool + select SOC_NRF54L15 + help + NRF54L15 ENGA + +config SOC_NRF54L15_ENGA_CPUAPP + bool + select SOC_NRF54L15_ENGA + help + NRF54L15 ENGA CPUAPP + +config SOC + default "nrf54l15" if SOC_NRF54L15 diff --git a/soc/arm/nordic_nrf/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf54l/soc.c rename to soc/nordic/nrf54l/soc.c diff --git a/soc/arm/nordic_nrf/nrf54l/soc.h b/soc/nordic/nrf54l/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf54l/soc.h rename to soc/nordic/nrf54l/soc.h diff --git a/soc/nordic/nrf91/CMakeLists.txt b/soc/nordic/nrf91/CMakeLists.txt new file mode 100644 index 00000000000000..533987519826e9 --- /dev/null +++ b/soc/nordic/nrf91/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library_sources(soc.c) +zephyr_include_directories(.) diff --git a/soc/nordic/nrf91/Kconfig b/soc/nordic/nrf91/Kconfig new file mode 100644 index 00000000000000..ed38eff73a2d3a --- /dev/null +++ b/soc/nordic/nrf91/Kconfig @@ -0,0 +1,37 @@ +# Nordic Semiconductor nRF91 MCU line + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF91X + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_NRF_IDAU + select CPU_HAS_FPU + select ARMV8_M_DSP + imply XIP + select HAS_NRFX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_POWEROFF + +if SOC_SERIES_NRF91X + +config NRF_SPU_FLASH_REGION_SIZE + hex + default 0x8000 + help + FLASH region size for the NRF_SPU peripheral + +config NRF_SPU_RAM_REGION_SIZE + hex + default 0x2000 + help + RAM region size for the NRF_SPU peripheral + +config NRF_ENABLE_ICACHE + bool "Instruction cache (I-Cache)" + default y + +endif # SOC_SERIES_NRF91X diff --git a/soc/nordic/nrf91/Kconfig.defconfig b/soc/nordic/nrf91/Kconfig.defconfig new file mode 100644 index 00000000000000..e28213fc87336f --- /dev/null +++ b/soc/nordic/nrf91/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nordic Semiconductor nRF91 MCU line + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NRF91X + +rsource "Kconfig.defconfig.nrf91*" + +# If the kernel has timer support, enable the timer +config NRF_RTC_TIMER + default y if SYS_CLOCK_EXISTS + +endif # SOC_SERIES_NRF91X diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9131_LACA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9131_LACA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA index c5004045935d87..b34a8d2384b6b1 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9131_LACA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9131_LACA @@ -5,9 +5,6 @@ if SOC_NRF9131_LACA -config SOC - default "nRF9131_LACA" - config NUM_IRQS default 65 diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9151_LACA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9151_LACA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA index 1b3ea88e359bac..f505e4154bfcb5 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9151_LACA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9151_LACA @@ -5,9 +5,6 @@ if SOC_NRF9151_LACA -config SOC - default "nRF9151_LACA" - config NUM_IRQS default 65 diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9160_SICA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9160_SICA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA index e8440846d2eb9f..5970464a6bd60b 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9160_SICA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9160_SICA @@ -5,9 +5,6 @@ if SOC_NRF9160_SICA -config SOC - default "nRF9160_SICA" - config NUM_IRQS default 65 diff --git a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9161_LACA b/soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA similarity index 84% rename from soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9161_LACA rename to soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA index 3358e961203206..1a4d4b863b2eb3 100644 --- a/soc/arm/nordic_nrf/nrf91/Kconfig.defconfig.nrf9161_LACA +++ b/soc/nordic/nrf91/Kconfig.defconfig.nrf9161_LACA @@ -5,9 +5,6 @@ if SOC_NRF9161_LACA -config SOC - default "nRF9161_LACA" - config NUM_IRQS default 65 diff --git a/soc/nordic/nrf91/Kconfig.soc b/soc/nordic/nrf91/Kconfig.soc new file mode 100644 index 00000000000000..452c353a109ee3 --- /dev/null +++ b/soc/nordic/nrf91/Kconfig.soc @@ -0,0 +1,47 @@ +# Nordic Semiconductor nRF91 MCU line + +# Copyright (c) 2018 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NRF91X + select SOC_FAMILY_NORDIC_NRF + help + Enable support for NRF91 MCU series + +config SOC_NRF9120 + bool + select SOC_SERIES_NRF91X + +config SOC_NRF9131_LACA + bool + select SOC_NRF9120 + +config SOC_NRF9151_LACA + bool + select SOC_NRF9120 + +config SOC_NRF9160 + bool + select SOC_SERIES_NRF91X + +config SOC_NRF9160_SICA + bool + select SOC_NRF9160 + +# The nRF9161 is technically a SiP (System-in-Package) that consists of +# the nRF9120 SoC and additional components like PMIC, FEM, and XTAL, +# so for nrfx/MDK the nRF9120 SoC is to be indicated as the build target, +# but since the nRF9161 is what a user can actually see on a board, using +# only nRF9120 in the Zephyr build infrastructure might be confusing. +# That's why in the top level of SoC definitions (for user-configurable +# options in Kconfig, for example) the nRF9161 term is used and nRF9120 +# underneath. +config SOC_NRF9161_LACA + bool + select SOC_NRF9120 + +config SOC + default "nrf9131" if SOC_NRF9131_LACA + default "nrf9151" if SOC_NRF9151_LACA + default "nrf9160" if SOC_NRF9160_SICA + default "nrf9161" if SOC_NRF9161_LACA diff --git a/soc/arm/nordic_nrf/nrf91/soc.c b/soc/nordic/nrf91/soc.c similarity index 100% rename from soc/arm/nordic_nrf/nrf91/soc.c rename to soc/nordic/nrf91/soc.c diff --git a/soc/arm/nordic_nrf/nrf91/soc.h b/soc/nordic/nrf91/soc.h similarity index 100% rename from soc/arm/nordic_nrf/nrf91/soc.h rename to soc/nordic/nrf91/soc.h diff --git a/soc/nordic/soc.yml b/soc/nordic/soc.yml new file mode 100644 index 00000000000000..87f35a46558426 --- /dev/null +++ b/soc/nordic/soc.yml @@ -0,0 +1,39 @@ +family: +- name: nordic_nrf + series: + - name: nrf51 + socs: + - name: nrf51822 + - name: nrf52 + socs: + - name: nrf52805 + - name: nrf52810 + - name: nrf52811 + - name: nrf52820 + - name: nrf52832 + - name: nrf52833 + - name: nrf52840 + - name: nrf53 + socs: + - name: nrf5340 + cpuclusters: + - name: cpuapp + - name: cpunet + - name: nrf54l + socs: + - name: nrf54l15 + cpuclusters: + - name: cpuapp + - name: nrf54h + socs: + - name: nrf54h20 + cpuclusters: + - name: cpuapp + - name: cpurad + - name: cpuppr + - name: nrf91 + socs: + - name: nrf9131 + - name: nrf9151 + - name: nrf9160 + - name: nrf9161 diff --git a/soc/arm/nordic_nrf/timing.c b/soc/nordic/timing.c similarity index 100% rename from soc/arm/nordic_nrf/timing.c rename to soc/nordic/timing.c diff --git a/soc/arm/nordic_nrf/validate_base_addresses.c b/soc/nordic/validate_base_addresses.c similarity index 99% rename from soc/arm/nordic_nrf/validate_base_addresses.c rename to soc/nordic/validate_base_addresses.c index 28ec231b132b9b..79083d630dd91e 100644 --- a/soc/arm/nordic_nrf/validate_base_addresses.c +++ b/soc/nordic/validate_base_addresses.c @@ -5,9 +5,10 @@ */ #include -#include #include +#include + /* * Account for MDK inconsistencies */ diff --git a/soc/arm/nordic_nrf/validate_enabled_instances.c b/soc/nordic/validate_enabled_instances.c similarity index 100% rename from soc/arm/nordic_nrf/validate_enabled_instances.c rename to soc/nordic/validate_enabled_instances.c diff --git a/soc/arm/nordic_nrf/validate_rram_partitions.c b/soc/nordic/validate_rram_partitions.c similarity index 100% rename from soc/arm/nordic_nrf/validate_rram_partitions.c rename to soc/nordic/validate_rram_partitions.c diff --git a/soc/arm/nuvoton_npcx/CMakeLists.txt b/soc/nuvoton/npcx/CMakeLists.txt similarity index 100% rename from soc/arm/nuvoton_npcx/CMakeLists.txt rename to soc/nuvoton/npcx/CMakeLists.txt diff --git a/soc/nuvoton/npcx/Kconfig b/soc/nuvoton/npcx/Kconfig new file mode 100644 index 00000000000000..bb3e92738bcafe --- /dev/null +++ b/soc/nuvoton/npcx/Kconfig @@ -0,0 +1,189 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NPCX + +menuconfig NPCX_HEADER + bool "The output binary with NPCX binary header" + help + On NPCX series chip, the NPCX ROM code loads firmware image from flash + to RAM by the firmware binary header setting. Enable this to invoke + the 'ecst' which generates the NPCX firmware header. + +if NPCX_HEADER + +config NPCX_IMAGE_OUTPUT_BIN + bool "Build npcx binary in BIN format" + default y + help + Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory. + The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. + +config NPCX_IMAGE_OUTPUT_HEX + bool "Build npcx binary in HEX format" + depends on NPCX_IMAGE_OUTPUT_BIN + help + Build an HEX binary zephyr/zephyr.npcx.hex in the build directory. + This is generated from the npcx BIN image. + The name of this file can be customized with CONFIG_KERNEL_BIN_NAME. + +config NPCX_HEADER_CHIP + string + default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC + default "npcx7m7" if SOC_NPCX7M7FC + default "npcx9m3" if SOC_NPCX9M3F + default "npcx9m6" if SOC_NPCX9M6F + default "npcx9m7" if SOC_NPCX9M7F + default "npcx9mfp" if SOC_NPCX9MFP + default "npcx4m3" if SOC_NPCX4M3F + default "npcx4m8" if SOC_NPCX4M8F + +choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE + prompt "Clock rate to use for SPI flash" + default NPCX_HEADER_SPI_MAX_CLOCK_20 + help + This selects the max clock rate that will be used for loading firmware + binary from flash to RAM. + +config NPCX_HEADER_SPI_MAX_CLOCK_20 + bool "SPI flash max clock rate of 20 MHz" + +config NPCX_HEADER_SPI_MAX_CLOCK_25 + bool "SPI flash max clock rate of 25 MHz" + +config NPCX_HEADER_SPI_MAX_CLOCK_33 + bool "SPI flash max clock rate of 33 MHz" + depends on !SOC_SERIES_NPCX9 + +config NPCX_HEADER_SPI_MAX_CLOCK_40 + bool "SPI flash max clock rate of 40 MHz" + +config NPCX_HEADER_SPI_MAX_CLOCK_50 + bool "SPI flash max clock rate of 50 MHz" +endchoice + +config NPCX_HEADER_SPI_MAX_CLOCK + int + default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20 + default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25 + default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33 + default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40 + default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50 + +choice NPCX_HEADER_SPI_READ_MODE_CHOICE + prompt "Reading mode used by the SPI flash" + default NPCX_HEADER_SPI_READ_MODE_NORMAL + help + This sets the reading mode that can be used by the SPI flash. + Reading modes supported are normal, fast, dual, and quad. + +config NPCX_HEADER_SPI_READ_MODE_NORMAL + bool "SPI flash operates with normal reading mode" + +config NPCX_HEADER_SPI_READ_MODE_FAST + bool "SPI flash operates with fast reading mode" + +config NPCX_HEADER_SPI_READ_MODE_DUAL + bool "SPI flash operates with dual reading mode" + +config NPCX_HEADER_SPI_READ_MODE_QUAD + bool "SPI flash operates with quad reading mode" +endchoice + +config NPCX_HEADER_SPI_READ_MODE + string + default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL + default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST + default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL + default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD + +choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE + prompt "Core clock to SPI flash clock ratio" + default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 + help + This sets the clock ratio (core clock / SPI clock) + +config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 + bool "NPCX SPI clock ratio 1" + help + The SPI flash clock has the same frequency as the core clock. + +config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 + bool "NPCX SPI clock ratio 2" + help + The core clock frequency is twice the flash clock frequency. +endchoice + +config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO + int + default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1 + default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2 + +config NPCX_HEADER_ENABLE_HEADER_CRC + bool "Header crc check" + help + When enabled, the header will be verified at boot using a crc + checksum. + +config NPCX_HEADER_ENABLE_FIRMWARE_CRC + bool "Firmware image crc check" + help + When enabled, the firmware image will be verified at boot using a + crc checksum. + +choice NPCX_HEADER_FLASH_SIZE_CHOICE + prompt "Flash size" + default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \ + SOC_SERIES_NPCX9 + default NPCX_HEADER_FLASH_SIZE_16M + help + This sets the SPI flash size. + +config NPCX_HEADER_FLASH_SIZE_0P5M_1M + bool "SPI flash size 0.5M or 1M Bytes" + help + The SPI flash size is 0.5M or 1M Bytes. + +config NPCX_HEADER_FLASH_SIZE_2M + bool "SPI flash size 2M Bytes" + help + The SPI flash size is 2M Bytes. + +config NPCX_HEADER_FLASH_SIZE_4M + bool "SPI flash size 4M Bytes" + help + The SPI flash size is 4M Bytes. + +config NPCX_HEADER_FLASH_SIZE_8M + bool "SPI flash size 8M Bytes" + help + The SPI flash size is 8M Bytes. + +config NPCX_HEADER_FLASH_SIZE_16M + bool "SPI flash size 16M Bytes" + help + The SPI flash size is 16M Bytes. +endchoice + +config NPCX_HEADER_FLASH_SIZE + int + default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M + default 2 if NPCX_HEADER_FLASH_SIZE_2M + default 4 if NPCX_HEADER_FLASH_SIZE_4M + default 8 if NPCX_HEADER_FLASH_SIZE_8M + default 16 if NPCX_HEADER_FLASH_SIZE_16M + +endif # NPCX_HEADER + +config NPCX_PM_TRACE + bool "Trace System Power Management in NPCX family" + depends on PM + help + Internal config to enable runtime power management traces. + +endif # SOC_FAMILY_NPCX + +# Select SoC Part No. and configuration options +rsource "*/Kconfig" diff --git a/soc/nuvoton/npcx/Kconfig.defconfig b/soc/nuvoton/npcx/Kconfig.defconfig new file mode 100644 index 00000000000000..0c47d7083139fc --- /dev/null +++ b/soc/nuvoton/npcx/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NPCX + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NPCX diff --git a/soc/nuvoton/npcx/Kconfig.soc b/soc/nuvoton/npcx/Kconfig.soc new file mode 100644 index 00000000000000..1c8002f8553203 --- /dev/null +++ b/soc/nuvoton/npcx/Kconfig.soc @@ -0,0 +1,12 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NPCX + bool + +config SOC_FAMILY + default "nuvoton_npcx" if SOC_FAMILY_NPCX + +rsource "*/Kconfig.soc" diff --git a/soc/nuvoton/npcx/common/CMakeLists.txt b/soc/nuvoton/npcx/common/CMakeLists.txt new file mode 100644 index 00000000000000..86780d1ad68bc9 --- /dev/null +++ b/soc/nuvoton/npcx/common/CMakeLists.txt @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources_ifdef(CONFIG_PM power.c) +zephyr_sources( + scfg.c + registers.c +) + +# Check for disabling header CRC. +if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC) + set(NPCX_HEADER_HCRC "-nohcrc") +endif() + +# Check for disabling firmware CRC. +if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_FIRMWARE_CRC) + set(NPCX_HEADER_FCRC "-nofcrc") +endif() + +if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_BIN) + set(NPCX_BIN_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.bin) + string(TOUPPER "${SOC_NAME}" soc_name_upper) + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND ${PYTHON_EXECUTABLE} ${SOC_${soc_name_upper}_DIR}/common/ecst/ecst.py + -i ${KERNEL_BIN_NAME} + -o ${NPCX_BIN_NAME} + ${NPCX_HEADER_HCRC} ${NPCX_HEADER_FCRC} + -chip ${CONFIG_NPCX_HEADER_CHIP} + -flashsize ${CONFIG_NPCX_HEADER_FLASH_SIZE} + -spiclkratio ${CONFIG_NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO} + -spimaxclk ${CONFIG_NPCX_HEADER_SPI_MAX_CLOCK} + -spireadmode ${CONFIG_NPCX_HEADER_SPI_READ_MODE} + ) + if (DEFINED CONFIG_NPCX_IMAGE_OUTPUT_HEX) + set(NPCX_HEX_NAME ${CONFIG_KERNEL_BIN_NAME}.npcx.hex) + # Property magic which makes west flash choose right file. + set_property(TARGET runners_yaml_props_target PROPERTY hex_file "${CONFIG_KERNEL_BIN_NAME}.npcx.hex") + set_property(GLOBAL APPEND PROPERTY extra_post_build_commands + COMMAND $ + $ + $binary + $ihex + $${NPCX_BIN_NAME} + $${NPCX_HEX_NAME} + $ + ) + endif() +endif() diff --git a/soc/arm/nuvoton_npcx/common/ecst/ecst.py b/soc/nuvoton/npcx/common/ecst/ecst.py similarity index 100% rename from soc/arm/nuvoton_npcx/common/ecst/ecst.py rename to soc/nuvoton/npcx/common/ecst/ecst.py diff --git a/soc/arm/nuvoton_npcx/common/ecst/ecst_args.py b/soc/nuvoton/npcx/common/ecst/ecst_args.py similarity index 100% rename from soc/arm/nuvoton_npcx/common/ecst/ecst_args.py rename to soc/nuvoton/npcx/common/ecst/ecst_args.py diff --git a/soc/arm/nuvoton_npcx/common/pinctrl_soc.h b/soc/nuvoton/npcx/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/pinctrl_soc.h rename to soc/nuvoton/npcx/common/pinctrl_soc.h diff --git a/soc/arm/nuvoton_npcx/common/power.c b/soc/nuvoton/npcx/common/power.c similarity index 100% rename from soc/arm/nuvoton_npcx/common/power.c rename to soc/nuvoton/npcx/common/power.c diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_access.h b/soc/nuvoton/npcx/common/reg/reg_access.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/reg/reg_access.h rename to soc/nuvoton/npcx/common/reg/reg_access.h diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_def.h b/soc/nuvoton/npcx/common/reg/reg_def.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/reg/reg_def.h rename to soc/nuvoton/npcx/common/reg/reg_def.h diff --git a/soc/arm/nuvoton_npcx/common/registers.c b/soc/nuvoton/npcx/common/registers.c similarity index 100% rename from soc/arm/nuvoton_npcx/common/registers.c rename to soc/nuvoton/npcx/common/registers.c diff --git a/soc/arm/nuvoton_npcx/common/scfg.c b/soc/nuvoton/npcx/common/scfg.c similarity index 100% rename from soc/arm/nuvoton_npcx/common/scfg.c rename to soc/nuvoton/npcx/common/scfg.c diff --git a/soc/arm/nuvoton_npcx/common/soc_clock.h b/soc/nuvoton/npcx/common/soc_clock.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_clock.h rename to soc/nuvoton/npcx/common/soc_clock.h diff --git a/soc/arm/nuvoton_npcx/common/soc_dbg.h b/soc/nuvoton/npcx/common/soc_dbg.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_dbg.h rename to soc/nuvoton/npcx/common/soc_dbg.h diff --git a/soc/arm/nuvoton_npcx/common/soc_dt.h b/soc/nuvoton/npcx/common/soc_dt.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_dt.h rename to soc/nuvoton/npcx/common/soc_dt.h diff --git a/soc/arm/nuvoton_npcx/common/soc_espi.h b/soc/nuvoton/npcx/common/soc_espi.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_espi.h rename to soc/nuvoton/npcx/common/soc_espi.h diff --git a/soc/arm/nuvoton_npcx/common/soc_espi_taf.h b/soc/nuvoton/npcx/common/soc_espi_taf.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_espi_taf.h rename to soc/nuvoton/npcx/common/soc_espi_taf.h diff --git a/soc/arm/nuvoton_npcx/common/soc_gpio.h b/soc/nuvoton/npcx/common/soc_gpio.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_gpio.h rename to soc/nuvoton/npcx/common/soc_gpio.h diff --git a/soc/arm/nuvoton_npcx/common/soc_host.h b/soc/nuvoton/npcx/common/soc_host.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_host.h rename to soc/nuvoton/npcx/common/soc_host.h diff --git a/soc/arm/nuvoton_npcx/common/soc_miwu.h b/soc/nuvoton/npcx/common/soc_miwu.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_miwu.h rename to soc/nuvoton/npcx/common/soc_miwu.h diff --git a/soc/arm/nuvoton_npcx/common/soc_pins.h b/soc/nuvoton/npcx/common/soc_pins.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_pins.h rename to soc/nuvoton/npcx/common/soc_pins.h diff --git a/soc/arm/nuvoton_npcx/common/soc_power.h b/soc/nuvoton/npcx/common/soc_power.h similarity index 100% rename from soc/arm/nuvoton_npcx/common/soc_power.h rename to soc/nuvoton/npcx/common/soc_power.h diff --git a/soc/nuvoton/npcx/npcx4/CMakeLists.txt b/soc/nuvoton/npcx/npcx4/CMakeLists.txt new file mode 100644 index 00000000000000..ea6ef98230ae46 --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . + ${ZEPHYR_BASE}/drivers +) + +zephyr_sources( + soc.c +) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/npcx/npcx4/Kconfig b/soc/nuvoton/npcx/npcx4/Kconfig new file mode 100644 index 00000000000000..0983b7c7eff0d3 --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/Kconfig @@ -0,0 +1,12 @@ +# Nuvoton NPCX4 EC series + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX4 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_PM diff --git a/soc/nuvoton/npcx/npcx4/Kconfig.defconfig b/soc/nuvoton/npcx/npcx4/Kconfig.defconfig new file mode 100644 index 00000000000000..1c4be7c3a579e7 --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NPCX4 + +config NUM_IRQS + default 128 + +config CORTEX_M_SYSTICK + default !NPCX_ITIM_TIMER + +config ESPI_TAF_NPCX + default y + depends on ESPI_SAF + +endif # SOC_SERIES_NPCX4 diff --git a/soc/nuvoton/npcx/npcx4/Kconfig.soc b/soc/nuvoton/npcx/npcx4/Kconfig.soc new file mode 100644 index 00000000000000..e825bc7fc6ff34 --- /dev/null +++ b/soc/nuvoton/npcx/npcx4/Kconfig.soc @@ -0,0 +1,29 @@ +# Nuvoton NPCX4 EC series + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX4 + bool + select SOC_FAMILY_NPCX + help + Enable support for Nuvoton NPCX4 series + +config SOC_NPCX4M3F + bool + select SOC_SERIES_NPCX4 + help + NPCX4M3F + +config SOC_NPCX4M8F + bool + select SOC_SERIES_NPCX4 + help + NPCX4M8F + +config SOC_SERIES + default "npcx4" if SOC_SERIES_NPCX4 + +config SOC + default "npcx4m3f" if SOC_NPCX4M3F + default "npcx4m8f" if SOC_NPCX4M8F diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.c b/soc/nuvoton/npcx/npcx4/soc.c similarity index 100% rename from soc/arm/nuvoton_npcx/npcx4/soc.c rename to soc/nuvoton/npcx/npcx4/soc.c diff --git a/soc/arm/nuvoton_npcx/npcx4/soc.h b/soc/nuvoton/npcx/npcx4/soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/npcx4/soc.h rename to soc/nuvoton/npcx/npcx4/soc.h diff --git a/soc/nuvoton/npcx/npcx7/CMakeLists.txt b/soc/nuvoton/npcx/npcx7/CMakeLists.txt new file mode 100644 index 00000000000000..7b96d5d55075a4 --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/CMakeLists.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . + ${ZEPHYR_BASE}/drivers +) + +zephyr_sources( + soc.c +) + +zephyr_sources_ifdef( + CONFIG_ARM_MPU + mpu_regions.c +) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/npcx/npcx7/Kconfig b/soc/nuvoton/npcx/npcx7/Kconfig new file mode 100644 index 00000000000000..55e5a1c50c0b21 --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/Kconfig @@ -0,0 +1,13 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX7 series + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX7 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select HAS_PM diff --git a/soc/nuvoton/npcx/npcx7/Kconfig.defconfig b/soc/nuvoton/npcx/npcx7/Kconfig.defconfig new file mode 100644 index 00000000000000..76682e0a48ac39 --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NPCX7 + +config NUM_IRQS + default 64 + +config CORTEX_M_SYSTICK + default !NPCX_ITIM_TIMER + +endif # SOC_SERIES_NPCX7 diff --git a/soc/nuvoton/npcx/npcx7/Kconfig.soc b/soc/nuvoton/npcx/npcx7/Kconfig.soc new file mode 100644 index 00000000000000..ca2bb268d239ef --- /dev/null +++ b/soc/nuvoton/npcx/npcx7/Kconfig.soc @@ -0,0 +1,36 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX7 series + +# Copyright (c) 2020 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX7 + bool + select SOC_FAMILY_NPCX + help + Enable support for Nuvoton NPCX7 series + +config SOC_NPCX7M6FB + bool + select SOC_SERIES_NPCX7 + help + NPCX7M6FB + +config SOC_NPCX7M6FC + bool + select SOC_SERIES_NPCX7 + help + NPCX7M6FC + +config SOC_NPCX7M7FC + bool + select SOC_SERIES_NPCX7 + help + NPCX7M7FC + +config SOC_SERIES + default "npcx7" if SOC_SERIES_NPCX7 + +config SOC + default "npcx7m6fb" if SOC_NPCX7M6FB + default "npcx7m6fc" if SOC_NPCX7M6FC + default "npcx7m7fc" if SOC_NPCX7M7FC diff --git a/soc/arm/nuvoton_npcx/npcx7/mpu_regions.c b/soc/nuvoton/npcx/npcx7/mpu_regions.c similarity index 100% rename from soc/arm/nuvoton_npcx/npcx7/mpu_regions.c rename to soc/nuvoton/npcx/npcx7/mpu_regions.c diff --git a/soc/arm/nuvoton_npcx/npcx7/soc.c b/soc/nuvoton/npcx/npcx7/soc.c similarity index 100% rename from soc/arm/nuvoton_npcx/npcx7/soc.c rename to soc/nuvoton/npcx/npcx7/soc.c diff --git a/soc/arm/nuvoton_npcx/npcx7/soc.h b/soc/nuvoton/npcx/npcx7/soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/npcx7/soc.h rename to soc/nuvoton/npcx/npcx7/soc.h diff --git a/soc/nuvoton/npcx/npcx9/CMakeLists.txt b/soc/nuvoton/npcx/npcx9/CMakeLists.txt new file mode 100644 index 00000000000000..7137403126df88 --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories( + . + ${ZEPHYR_BASE}/drivers +) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/npcx/npcx9/Kconfig b/soc/nuvoton/npcx/npcx9/Kconfig new file mode 100644 index 00000000000000..25cee4381b72f4 --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/Kconfig @@ -0,0 +1,13 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX9 series + +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX9 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_FAMILY_NPCX + select HAS_PM diff --git a/soc/nuvoton/npcx/npcx9/Kconfig.defconfig b/soc/nuvoton/npcx/npcx9/Kconfig.defconfig new file mode 100644 index 00000000000000..1f7da8453cbf1d --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Nuvoton Cortex-M4 Embedded Controller + +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_NPCX9 + +config NUM_IRQS + default 64 + +config CORTEX_M_SYSTICK + default !NPCX_ITIM_TIMER + +endif # SOC_SERIES_NPCX9 diff --git a/soc/nuvoton/npcx/npcx9/Kconfig.soc b/soc/nuvoton/npcx/npcx9/Kconfig.soc new file mode 100644 index 00000000000000..30f045eb0bfffc --- /dev/null +++ b/soc/nuvoton/npcx/npcx9/Kconfig.soc @@ -0,0 +1,43 @@ +# Nuvoton Cortex-M4 Embedded Controller NPCX9 series + +# Copyright (c) 2021 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_NPCX9 + bool + select SOC_FAMILY_NPCX + help + Enable support for Nuvoton NPCX9 series + +config SOC_NPCX9M3F + bool + select SOC_SERIES_NPCX9 + help + NPCX9M3F + +config SOC_NPCX9M6F + bool + select SOC_SERIES_NPCX9 + help + NPCX9M6F + +config SOC_NPCX9M7F + bool + select SOC_SERIES_NPCX9 + help + NPCX9M7F + +config SOC_NPCX9MFP + bool + select SOC_SERIES_NPCX9 + help + NPCX9MFP + +config SOC_SERIES + default "npcx9" if SOC_SERIES_NPCX9 + +config SOC + default "npcx9m3f" if SOC_NPCX9M3F + default "npcx9m6f" if SOC_NPCX9M6F + default "npcx9m7f" if SOC_NPCX9M7F + default "npcx9mfp" if SOC_NPCX9MFP diff --git a/soc/arm/nuvoton_npcx/npcx9/soc.h b/soc/nuvoton/npcx/npcx9/soc.h similarity index 100% rename from soc/arm/nuvoton_npcx/npcx9/soc.h rename to soc/nuvoton/npcx/npcx9/soc.h diff --git a/soc/nuvoton/npcx/soc.yml b/soc/nuvoton/npcx/soc.yml new file mode 100644 index 00000000000000..2aab050969ccfc --- /dev/null +++ b/soc/nuvoton/npcx/soc.yml @@ -0,0 +1,18 @@ +family: +- name: npcx + series: + - name: npcx4 + socs: + - name: npcx4m3f + - name: npcx4m8f + - name: npcx7 + socs: + - name: npcx7m6fb + - name: npcx7m6fc + - name: npcx7m7fc + - name: npcx9 + socs: + - name: npcx9m3f + - name: npcx9m6f + - name: npcx9m7f + - name: npcx9mfp diff --git a/soc/arm/nuvoton_numaker/CMakeLists.txt b/soc/nuvoton/numaker/CMakeLists.txt similarity index 100% rename from soc/arm/nuvoton_numaker/CMakeLists.txt rename to soc/nuvoton/numaker/CMakeLists.txt diff --git a/soc/nuvoton/numaker/Kconfig b/soc/nuvoton/numaker/Kconfig new file mode 100644 index 00000000000000..d2a03b31a4d66e --- /dev/null +++ b/soc/nuvoton/numaker/Kconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NUMAKER + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_NUMAKER + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NUMAKER diff --git a/soc/nuvoton/numaker/Kconfig.defconfig b/soc/nuvoton/numaker/Kconfig.defconfig new file mode 100644 index 00000000000000..43cb3e9c43b4d1 --- /dev/null +++ b/soc/nuvoton/numaker/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NUMAKER + +rsource "*/Kconfig.defconfig" + +config RESET + default y + +endif diff --git a/soc/nuvoton/numaker/Kconfig.soc b/soc/nuvoton/numaker/Kconfig.soc new file mode 100644 index 00000000000000..8b09b99bd58311 --- /dev/null +++ b/soc/nuvoton/numaker/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NUMAKER + bool + +config SOC_FAMILY + default "numaker" if SOC_FAMILY_NUMAKER + +rsource "*/Kconfig.soc" diff --git a/soc/arm/nuvoton_numaker/common/pinctrl_soc.h b/soc/nuvoton/numaker/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nuvoton_numaker/common/pinctrl_soc.h rename to soc/nuvoton/numaker/common/pinctrl_soc.h diff --git a/soc/nuvoton/numaker/m46x/CMakeLists.txt b/soc/nuvoton/numaker/m46x/CMakeLists.txt new file mode 100644 index 00000000000000..58be053241b0e6 --- /dev/null +++ b/soc/nuvoton/numaker/m46x/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/numaker/m46x/Kconfig b/soc/nuvoton/numaker/m46x/Kconfig new file mode 100644 index 00000000000000..408b3067bd80aa --- /dev/null +++ b/soc/nuvoton/numaker/m46x/Kconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M46X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CORTEX_M_SYSTICK if SYS_CLOCK_EXISTS + +config SOC_M467 + select HAS_NUMAKER_HAL diff --git a/soc/nuvoton/numaker/m46x/Kconfig.defconfig b/soc/nuvoton/numaker/m46x/Kconfig.defconfig new file mode 100644 index 00000000000000..71e6c62340bddb --- /dev/null +++ b/soc/nuvoton/numaker/m46x/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_M46X + +rsource "Kconfig.defconfig.m46*" + +endif # SOC_SERIES_M46X diff --git a/soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.m467 b/soc/nuvoton/numaker/m46x/Kconfig.defconfig.m467 similarity index 100% rename from soc/arm/nuvoton_numaker/m46x/Kconfig.defconfig.m467 rename to soc/nuvoton/numaker/m46x/Kconfig.defconfig.m467 diff --git a/soc/nuvoton/numaker/m46x/Kconfig.soc b/soc/nuvoton/numaker/m46x/Kconfig.soc new file mode 100644 index 00000000000000..c1207a117a25a3 --- /dev/null +++ b/soc/nuvoton/numaker/m46x/Kconfig.soc @@ -0,0 +1,19 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_M46X + bool + select SOC_FAMILY_NUMAKER + help + Enable support for Nuvoton M46X MCU series + +config SOC_M467 + bool + select SOC_SERIES_M46X + +config SOC_SERIES + default "m46x" if SOC_SERIES_M46X + +config SOC + default "m467" if SOC_M467 diff --git a/soc/arm/nuvoton_numaker/m46x/soc.c b/soc/nuvoton/numaker/m46x/soc.c similarity index 100% rename from soc/arm/nuvoton_numaker/m46x/soc.c rename to soc/nuvoton/numaker/m46x/soc.c diff --git a/soc/arm/nuvoton_numaker/m46x/soc.h b/soc/nuvoton/numaker/m46x/soc.h similarity index 100% rename from soc/arm/nuvoton_numaker/m46x/soc.h rename to soc/nuvoton/numaker/m46x/soc.h diff --git a/soc/nuvoton/numaker/soc.yml b/soc/nuvoton/numaker/soc.yml new file mode 100644 index 00000000000000..cad8f6d1fc48e0 --- /dev/null +++ b/soc/nuvoton/numaker/soc.yml @@ -0,0 +1,6 @@ +family: +- name: numaker + series: + - name: m46x + socs: + - name: m467 diff --git a/soc/arm/nuvoton_numicro/CMakeLists.txt b/soc/nuvoton/numicro/CMakeLists.txt similarity index 100% rename from soc/arm/nuvoton_numicro/CMakeLists.txt rename to soc/nuvoton/numicro/CMakeLists.txt diff --git a/soc/nuvoton/numicro/Kconfig b/soc/nuvoton/numicro/Kconfig new file mode 100644 index 00000000000000..6f80bd23cf7ec4 --- /dev/null +++ b/soc/nuvoton/numicro/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_FAMILY_NUMICRO + select PLATFORM_SPECIFIC_INIT + +if SOC_FAMILY_NUMICRO + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NUMICRO diff --git a/soc/nuvoton/numicro/Kconfig.defconfig b/soc/nuvoton/numicro/Kconfig.defconfig new file mode 100644 index 00000000000000..b5973c5c00a6f9 --- /dev/null +++ b/soc/nuvoton/numicro/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +if SOC_FAMILY_NUMICRO + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NUMICRO diff --git a/soc/nuvoton/numicro/Kconfig.soc b/soc/nuvoton/numicro/Kconfig.soc new file mode 100644 index 00000000000000..157191afeb95c5 --- /dev/null +++ b/soc/nuvoton/numicro/Kconfig.soc @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_FAMILY_NUMICRO + bool + +config SOC_FAMILY + default "numicro" if SOC_FAMILY_NUMICRO + +rsource "*/Kconfig.soc" diff --git a/soc/arm/nuvoton_numicro/common/pinctrl_soc.h b/soc/nuvoton/numicro/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nuvoton_numicro/common/pinctrl_soc.h rename to soc/nuvoton/numicro/common/pinctrl_soc.h diff --git a/soc/nuvoton/numicro/m48x/CMakeLists.txt b/soc/nuvoton/numicro/m48x/CMakeLists.txt new file mode 100644 index 00000000000000..71fa70ed04baa0 --- /dev/null +++ b/soc/nuvoton/numicro/m48x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nuvoton/numicro/m48x/Kconfig b/soc/nuvoton/numicro/m48x/Kconfig new file mode 100644 index 00000000000000..6a14e945244e65 --- /dev/null +++ b/soc/nuvoton/numicro/m48x/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_SERIES_M48X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + +config SOC_M487 + select HAS_NUMICRO_HAL diff --git a/soc/nuvoton/numicro/m48x/Kconfig.defconfig b/soc/nuvoton/numicro/m48x/Kconfig.defconfig new file mode 100644 index 00000000000000..9833529015eaea --- /dev/null +++ b/soc/nuvoton/numicro/m48x/Kconfig.defconfig @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +if SOC_SERIES_M48X + +rsource "Kconfig.defconfig.m48*" + +endif # SOC_SERIES_M48X diff --git a/soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.m487 b/soc/nuvoton/numicro/m48x/Kconfig.defconfig.m487 similarity index 100% rename from soc/arm/nuvoton_numicro/m48x/Kconfig.defconfig.m487 rename to soc/nuvoton/numicro/m48x/Kconfig.defconfig.m487 diff --git a/soc/nuvoton/numicro/m48x/Kconfig.soc b/soc/nuvoton/numicro/m48x/Kconfig.soc new file mode 100644 index 00000000000000..8d0efbe0237078 --- /dev/null +++ b/soc/nuvoton/numicro/m48x/Kconfig.soc @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 +# +# Copyright (c) 2020 Linumiz +# Author: Saravanan Sekar + +config SOC_SERIES_M48X + bool + select SOC_FAMILY_NUMICRO + help + Enable support for NUVOTON M48X MCU series + +config SOC_M487 + bool + select SOC_SERIES_M48X + +config SOC_SERIES + default "m48x" if SOC_SERIES_M48X + +config SOC + default "m487" if SOC_M487 diff --git a/soc/arm/nuvoton_numicro/m48x/soc.c b/soc/nuvoton/numicro/m48x/soc.c similarity index 100% rename from soc/arm/nuvoton_numicro/m48x/soc.c rename to soc/nuvoton/numicro/m48x/soc.c diff --git a/soc/arm/nuvoton_numicro/m48x/soc.h b/soc/nuvoton/numicro/m48x/soc.h similarity index 100% rename from soc/arm/nuvoton_numicro/m48x/soc.h rename to soc/nuvoton/numicro/m48x/soc.h diff --git a/soc/nuvoton/numicro/soc.yml b/soc/nuvoton/numicro/soc.yml new file mode 100644 index 00000000000000..9812e29e4b07e8 --- /dev/null +++ b/soc/nuvoton/numicro/soc.yml @@ -0,0 +1,6 @@ +family: +- name: numicro + series: + - name: m48x + socs: + - name: m487 diff --git a/soc/nxp/imx/CMakeLists.txt b/soc/nxp/imx/CMakeLists.txt new file mode 100644 index 00000000000000..f14f2e1e116add --- /dev/null +++ b/soc/nxp/imx/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) + +zephyr_include_directories(.) +zephyr_include_directories(${SOC_SERIES}) + +zephyr_include_directories(${SOC_SERIES}/include) diff --git a/soc/nxp/imx/Kconfig b/soc/nxp/imx/Kconfig new file mode 100644 index 00000000000000..9fba09a031ea05 --- /dev/null +++ b/soc/nxp/imx/Kconfig @@ -0,0 +1,13 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMX + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_NXP_IMX + +# Source series Kconfig files first, so SOCs +# can override the defaults given here +rsource "*/Kconfig" + +endif # SOC_FAMILY_NXP_IMX diff --git a/soc/nxp/imx/Kconfig.defconfig b/soc/nxp/imx/Kconfig.defconfig new file mode 100644 index 00000000000000..a606387831706e --- /dev/null +++ b/soc/nxp/imx/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_IMX + +# Source series Kconfig files first, so SoCs +# can override the defaults given here +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NXP_IMX diff --git a/soc/nxp/imx/Kconfig.soc b/soc/nxp/imx/Kconfig.soc new file mode 100644 index 00000000000000..d0418fce746bea --- /dev/null +++ b/soc/nxp/imx/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMX + bool + +config SOC_FAMILY + default "nxp_imx" if SOC_FAMILY_NXP_IMX + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/imx/imx6sx/CMakeLists.txt b/soc/nxp/imx/imx6sx/CMakeLists.txt new file mode 100644 index 00000000000000..8bebaa89bee7c0 --- /dev/null +++ b/soc/nxp/imx/imx6sx/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright 2018,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + soc_clk_freq.c +) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imx/imx6sx/Kconfig b/soc/nxp/imx/imx6sx/Kconfig new file mode 100644 index 00000000000000..901b2c90a64967 --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig @@ -0,0 +1,18 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX6SX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_IMX_HAL + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CLOCK_CONTROL + +config SOC_MCIMX6X_M4 + select HAS_IMX_HAL + select HAS_IMX_GPIO + select HAS_IMX_EPIT + select HAS_IMX_I2C + select HAS_IMX_IOMUXC diff --git a/soc/nxp/imx/imx6sx/Kconfig.defconfig b/soc/nxp/imx/imx6sx/Kconfig.defconfig new file mode 100644 index 00000000000000..e2683c90fa1d14 --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig.defconfig @@ -0,0 +1,18 @@ +# i.MX 6SoloX core series + +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX6SX + +config NUM_IRQS + # must be >= the highest interrupt number used + default 128 + +config PINCTRL_IMX + default y if HAS_IMX_IOMUXC + depends on PINCTRL + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX6SX diff --git a/soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 b/soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 new file mode 100644 index 00000000000000..9a925ade2f6a62 --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig.defconfig.mcimx6x_m4 @@ -0,0 +1,11 @@ +# i.MX 6SoloX + +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MCIMX6X_M4 + +config FPU + default y + +endif # SOC_MCIMX6X_M4 diff --git a/soc/nxp/imx/imx6sx/Kconfig.soc b/soc/nxp/imx/imx6sx/Kconfig.soc new file mode 100644 index 00000000000000..e6f968bb9e3f3d --- /dev/null +++ b/soc/nxp/imx/imx6sx/Kconfig.soc @@ -0,0 +1,83 @@ +# i.MX 6SoloX core series + +# Copyright 2018,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + + +config SOC_SERIES_IMX6SX + bool + select SOC_FAMILY_NXP_IMX + +config SOC_MCIMX6X + bool + select SOC_SERIES_IMX6SX + +config SOC_MCIMX6X_M4 + select SOC_MCIMX6X + bool + help + NXP iMX6 SoloX M4 core + +config SOC_SERIES + default "imx6sx" if SOC_SERIES_IMX6SX + +config SOC + default "mcimx6x" if SOC_MCIMX6X + +config SOC_PART_NUMBER_MCIMX6X1EVK10AB + bool + +config SOC_PART_NUMBER_MCIMX6X1EVK10AC + bool + +config SOC_PART_NUMBER_MCIMX6X3EVK10AB + bool + +config SOC_PART_NUMBER_MCIMX6X3EVK10AC + bool + +config SOC_PART_NUMBER_MCIMX6X1EVO10AB + bool + +config SOC_PART_NUMBER_MCIMX6X1EVO10AC + bool + +config SOC_PART_NUMBER_MCIMX6X3EVO10AB + bool + +config SOC_PART_NUMBER_MCIMX6X3EVO10AC + bool + +config SOC_PART_NUMBER_MCIMX6X2EVN10AB + bool + +config SOC_PART_NUMBER_MCIMX6X2EVN10AC + bool + +config SOC_PART_NUMBER_MCIMX6X3EVN10AB + bool + +config SOC_PART_NUMBER_MCIMX6X3EVN10AC + bool + +config SOC_PART_NUMBER_MCIMX6X4EVM10AB + bool + +config SOC_PART_NUMBER_MCIMX6X4EVM10AC + bool + +config SOC_PART_NUMBER + default "MCIMX6X1EVK10AB" if SOC_PART_NUMBER_MCIMX6X1EVK10AB + default "MCIMX6X1EVK10AC" if SOC_PART_NUMBER_MCIMX6X1EVK10AC + default "MCIMX6X3EVK10AB" if SOC_PART_NUMBER_MCIMX6X3EVK10AB + default "MCIMX6X3EVK10AC" if SOC_PART_NUMBER_MCIMX6X3EVK10AC + default "MCIMX6X1EVO10AB" if SOC_PART_NUMBER_MCIMX6X1EVO10AB + default "MCIMX6X1EVO10AC" if SOC_PART_NUMBER_MCIMX6X1EVO10AC + default "MCIMX6X3EVO10AB" if SOC_PART_NUMBER_MCIMX6X3EVO10AB + default "MCIMX6X3EVO10AC" if SOC_PART_NUMBER_MCIMX6X3EVO10AC + default "MCIMX6X2EVN10AB" if SOC_PART_NUMBER_MCIMX6X2EVN10AB + default "MCIMX6X2EVN10AC" if SOC_PART_NUMBER_MCIMX6X2EVN10AC + default "MCIMX6X3EVN10AB" if SOC_PART_NUMBER_MCIMX6X3EVN10AB + default "MCIMX6X3EVN10AC" if SOC_PART_NUMBER_MCIMX6X3EVN10AC + default "MCIMX6X4EVM10AB" if SOC_PART_NUMBER_MCIMX6X4EVM10AB + default "MCIMX6X4EVM10AC" if SOC_PART_NUMBER_MCIMX6X4EVM10AC diff --git a/soc/arm/nxp_imx/mcimx6x_m4/pinctrl_soc.h b/soc/nxp/imx/imx6sx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/pinctrl_soc.h rename to soc/nxp/imx/imx6sx/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.c b/soc/nxp/imx/imx6sx/soc.c similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc.c rename to soc/nxp/imx/imx6sx/soc.c diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc.h b/soc/nxp/imx/imx6sx/soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc.h rename to soc/nxp/imx/imx6sx/soc.h diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.c b/soc/nxp/imx/imx6sx/soc_clk_freq.c similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.c rename to soc/nxp/imx/imx6sx/soc_clk_freq.c diff --git a/soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.h b/soc/nxp/imx/imx6sx/soc_clk_freq.h similarity index 100% rename from soc/arm/nxp_imx/mcimx6x_m4/soc_clk_freq.h rename to soc/nxp/imx/imx6sx/soc_clk_freq.h diff --git a/soc/nxp/imx/imx7d/CMakeLists.txt b/soc/nxp/imx/imx7d/CMakeLists.txt new file mode 100644 index 00000000000000..1c34ea54c88e37 --- /dev/null +++ b/soc/nxp/imx/imx7d/CMakeLists.txt @@ -0,0 +1,14 @@ +# +# Copyright 2017,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + soc_clk_freq.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imx/imx7d/Kconfig b/soc/nxp/imx/imx7d/Kconfig new file mode 100644 index 00000000000000..fbebe524242d84 --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX7D + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + +config SOC_MCIMX7D_M4 + select HAS_IMX_HAL + select HAS_IMX_GPIO + select HAS_IMX_I2C + select HAS_IMX_IOMUXC diff --git a/soc/nxp/imx/imx7d/Kconfig.defconfig b/soc/nxp/imx/imx7d/Kconfig.defconfig new file mode 100644 index 00000000000000..2fa2f371ab0469 --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig.defconfig @@ -0,0 +1,18 @@ +# iMX7 core series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX7D + +config NUM_IRQS + # must be >= the highest interrupt number used + default 127 + +config PINCTRL_IMX + default y if HAS_IMX_IOMUXC + depends on PINCTRL + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX7D diff --git a/soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4 b/soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4 new file mode 100644 index 00000000000000..2e9d5e71d9d9be --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig.defconfig.mcimx7d_m4 @@ -0,0 +1,14 @@ +# iMX7 M4 core series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MCIMX7D_M4 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 200000000 + +config GPIO + default y + +endif # SOC_MCIMX7D_M4 diff --git a/soc/nxp/imx/imx7d/Kconfig.soc b/soc/nxp/imx/imx7d/Kconfig.soc new file mode 100644 index 00000000000000..d7040cdaedb394 --- /dev/null +++ b/soc/nxp/imx/imx7d/Kconfig.soc @@ -0,0 +1,40 @@ +# iMX7D core series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX7D + bool + select SOC_FAMILY_NXP_IMX + help + Enable support for iMX7D MCU series + +config SOC_MCIMX7D + bool + select SOC_SERIES_IMX7D + +config SOC_MCIMX7D_M4 + bool + select SOC_MCIMX7D + help + NXP iMX7 Dual M4 Core + +config SOC_SERIES + default "imx7d" if SOC_SERIES_IMX7D + +config SOC + default "mcimx7d" if SOC_MCIMX7D + +config SOC_PART_NUMBER_MCIMX7D7DVM10SC + bool + +config SOC_PART_NUMBER_MCIMX7D5EVM10SC + bool + +config SOC_PART_NUMBER_MCIMX7S3DVK08SA + bool + +config SOC_PART_NUMBER + default "MCIMX7D7DVM10SC" if SOC_PART_NUMBER_MCIMX7D7DVM10SC + default "MCIMX7D5EVM10SC" if SOC_PART_NUMBER_MCIMX7D5EVM10SC + default "MCIMX7S3DVK08SA" if SOC_PART_NUMBER_MCIMX7S3DVK08SA diff --git a/soc/arm/nxp_imx/mcimx7_m4/pinctrl_soc.h b/soc/nxp/imx/imx7d/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/pinctrl_soc.h rename to soc/nxp/imx/imx7d/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc.c b/soc/nxp/imx/imx7d/soc.c similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc.c rename to soc/nxp/imx/imx7d/soc.c diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc.h b/soc/nxp/imx/imx7d/soc.h similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc.h rename to soc/nxp/imx/imx7d/soc.h diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.c b/soc/nxp/imx/imx7d/soc_clk_freq.c similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.c rename to soc/nxp/imx/imx7d/soc_clk_freq.c diff --git a/soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.h b/soc/nxp/imx/imx7d/soc_clk_freq.h similarity index 100% rename from soc/arm/nxp_imx/mcimx7_m4/soc_clk_freq.h rename to soc/nxp/imx/imx7d/soc_clk_freq.h diff --git a/soc/nxp/imx/imx8/CMakeLists.txt b/soc/nxp/imx/imx8/CMakeLists.txt new file mode 100644 index 00000000000000..209de9c95ad13c --- /dev/null +++ b/soc/nxp/imx/imx8/CMakeLists.txt @@ -0,0 +1,27 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8QM_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + zephyr_sources( + adsp/pinctrl_soc.h + ) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx8/Kconfig b/soc/nxp/imx/imx8/Kconfig new file mode 100644 index 00000000000000..e7993616bbd510 --- /dev/null +++ b/soc/nxp/imx/imx8/Kconfig @@ -0,0 +1,15 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8QM_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select HAS_MCUX + +config MCUX_CORE_SUFFIX + default "_dsp" if SOC_MIMX8QM_ADSP diff --git a/soc/nxp/imx/imx8/Kconfig.defconfig b/soc/nxp/imx/imx8/Kconfig.defconfig new file mode 100644 index 00000000000000..203c43b1214873 --- /dev/null +++ b/soc/nxp/imx/imx8/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8 + +if SOC_MIMX8QM_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 666000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8QM_ADSP + +endif # SOC_SERIES_IMX8 diff --git a/soc/nxp/imx/imx8/Kconfig.soc b/soc/nxp/imx/imx8/Kconfig.soc new file mode 100644 index 00000000000000..46903a8437d313 --- /dev/null +++ b/soc/nxp/imx/imx8/Kconfig.soc @@ -0,0 +1,32 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8 + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8" if SOC_SERIES_IMX8 + +config SOC_MIMX8QM + bool + select SOC_SERIES_IMX8 + +config SOC + default "mimx8qm6" if SOC_MIMX8QM + +config SOC_MIMX8QM_ADSP + bool + select SOC_MIMX8QM + help + Enable support for NXP i.MX 8QM Audio DSP + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx_adsp" if SOC_MIMX8QM_ADSP + +config SOC_PART_NUMBER_MIMX8QM6AVUFF + bool + +config SOC_PART_NUMBER + default "MIMX8QM6AVUFF" if SOC_PART_NUMBER_MIMX8QM6AVUFF diff --git a/soc/nxp/imx/imx8/adsp/CMakeLists.txt b/soc/nxp/imx/imx8/adsp/CMakeLists.txt new file mode 100644 index 00000000000000..a91c59914123ab --- /dev/null +++ b/soc/nxp/imx/imx8/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8/include/_soc_inthandlers.h b/soc/nxp/imx/imx8/adsp/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/include/_soc_inthandlers.h rename to soc/nxp/imx/imx8/adsp/_soc_inthandlers.h diff --git a/soc/xtensa/nxp_adsp/common/include/adsp/cache.h b/soc/nxp/imx/imx8/adsp/include/adsp/cache.h similarity index 100% rename from soc/xtensa/nxp_adsp/common/include/adsp/cache.h rename to soc/nxp/imx/imx8/adsp/include/adsp/cache.h diff --git a/soc/xtensa/nxp_adsp/common/include/adsp/io.h b/soc/nxp/imx/imx8/adsp/include/adsp/io.h similarity index 100% rename from soc/xtensa/nxp_adsp/common/include/adsp/io.h rename to soc/nxp/imx/imx8/adsp/include/adsp/io.h diff --git a/soc/xtensa/nxp_adsp/common/include/soc.h b/soc/nxp/imx/imx8/adsp/include/soc.h similarity index 100% rename from soc/xtensa/nxp_adsp/common/include/soc.h rename to soc/nxp/imx/imx8/adsp/include/soc.h diff --git a/soc/xtensa/nxp_adsp/imx8/linker.ld b/soc/nxp/imx/imx8/adsp/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/linker.ld rename to soc/nxp/imx/imx8/adsp/linker.ld diff --git a/soc/xtensa/nxp_adsp/imx8/include/memory.h b/soc/nxp/imx/imx8/adsp/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/include/memory.h rename to soc/nxp/imx/imx8/adsp/memory.h diff --git a/soc/xtensa/nxp_adsp/imx8/pinctrl_soc.h b/soc/nxp/imx/imx8/adsp/pinctrl_soc.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8/pinctrl_soc.h rename to soc/nxp/imx/imx8/adsp/pinctrl_soc.h diff --git a/soc/nxp/imx/imx8m/CMakeLists.txt b/soc/nxp/imx/imx8m/CMakeLists.txt new file mode 100644 index 00000000000000..8f319c6827ad5f --- /dev/null +++ b/soc/nxp/imx/imx8m/CMakeLists.txt @@ -0,0 +1,52 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8MP_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + zephyr_sources( + adsp/pinctrl_soc.h + ) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() + +if(CONFIG_SOC_MIMX8ML8_A53 OR CONFIG_SOC_MIMX8MM6_A53 OR CONFIG_SOC_MIMX8MN6_A53) + zephyr_include_directories(.) + zephyr_include_directories(a53) + + zephyr_sources( + a53/pinctrl_soc.h + ) + + zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +endif() + +if(CONFIG_SOC_MIMX8MM6_M4) + add_subdirectory(m4_mini) +endif() + +if(CONFIG_SOC_MIMX8MQ6_M4) + add_subdirectory(m4_quad) +endif() + +if(CONFIG_SOC_MIMX8MP_M7) + add_subdirectory(m7) +endif() diff --git a/soc/nxp/imx/imx8m/Kconfig b/soc/nxp/imx/imx8m/Kconfig new file mode 100644 index 00000000000000..ed796a8c2da00a --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig @@ -0,0 +1,98 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8MM6_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config SOC_MIMX8MM6_M4 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_MCUX + select HAS_MCUX_CCM + select HAS_MCUX_RDC + select HAS_MCUX_IGPIO + select HAS_MCUX_IOMUXC + +config SOC_MIMX8ML8_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config SOC_MIMX8MN6_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config SOC_MIMX8MP_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + select PINCTRL_IMX if HAS_MCUX_IOMUXC + +config SOC_MIMX8MP_M7 + select ARM + select CPU_CORTEX_M7 + select CPU_HAS_FPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_VIDEO_PLL + select HAS_MCUX + select HAS_MCUX_CCM + select HAS_MCUX_RDC + select CPU_HAS_ARM_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select ARM_MPU + select HAS_MCUX_IGPIO + select HAS_MCUX_IOMUXC + +config SOC_MIMX8MQ6_M4 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_MCUX + select HAS_MCUX_CCM + select HAS_MCUX_RDC + select HAS_MCUX_IOMUXC + +config MCUX_CORE_SUFFIX + default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53 + default "_dsp" if SOC_MIMX8MP_ADSP + +if SOC_MIMX8MP_M7 + +choice CODE_LOCATION + prompt "Code location selection" + +config CODE_ITCM + bool "Link code into internal instruction tightly coupled memory (ITCM)" + +config CODE_DDR + bool "Link code into DDR memory" + +endchoice + +config INIT_VIDEO_PLL + bool "Initialize Video PLL" + +endif # SOC_MIMX8MP_M7 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig b/soc/nxp/imx/imx8m/Kconfig.defconfig new file mode 100644 index 00000000000000..d2e4264634398b --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8M + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX8M diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 new file mode 100644 index 00000000000000..acd7d02761d881 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8.m7 @@ -0,0 +1,53 @@ +# MIMX8ML8 SoC defconfig + +# Copyright (c) 2021, Laird Connectivity +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MP_M7 + +config SOC + string + default "mimx8ml8" + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 800000000 + +config GPIO + default y + +config IPM_IMX + default y + depends on IPM + +if CODE_ITCM + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/itcm@0,0,K) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/itcm@0) + +endif # CODE_ITCM + +if CODE_DDR + +config FLASH_SIZE + default $(dt_node_reg_size_int,/soc/code@80000000,0,K) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,/soc/code@80000000) + +endif # CODE_DDR + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 159 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif # SOC_MIMX8MP_M7 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp new file mode 100644 index 00000000000000..6c29a2975f7f78 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8ml8_adsp @@ -0,0 +1,48 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8M + +if SOC_MIMX8MP_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 800000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +config DYNAMIC_INTERRUPTS + default y + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8MP_ADSP + +endif # SOC_SERIES_IMX8M diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 new file mode 100644 index 00000000000000..39ce520f5ab6c5 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.a53 @@ -0,0 +1,27 @@ +# Copyright 2020-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MM6_A53 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 new file mode 100644 index 00000000000000..02f068af04f167 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mm.m4 @@ -0,0 +1,26 @@ +# MIMX8MM6 M4 SoC defconfig + +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MM6_M4 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 400000000 + +config IPM_IMX + default y + depends on IPM + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 127 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif # SOC_MIMX8MM6_M4 diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 new file mode 100644 index 00000000000000..f48c3187b1951a --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mn.a53 @@ -0,0 +1,27 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MN6_A53 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 new file mode 100644 index 00000000000000..23edb44e9dd39b --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mp.a53 @@ -0,0 +1,27 @@ +# Copyright 2021-2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8ML8_A53 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 new file mode 100644 index 00000000000000..0f9e144bfdedf7 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.defconfig.mimx8mq.m4 @@ -0,0 +1,22 @@ +# MIMX8MQ6 M4 SoC defconfig + +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX8MQ6_M4 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 266000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 127 + +endif # SOC_MIMX8MQ6_M4 diff --git a/soc/nxp/imx/imx8m/Kconfig.soc b/soc/nxp/imx/imx8m/Kconfig.soc new file mode 100644 index 00000000000000..79471279a75991 --- /dev/null +++ b/soc/nxp/imx/imx8m/Kconfig.soc @@ -0,0 +1,115 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8M + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8m" if SOC_SERIES_IMX8M + +config SOC_MIMX8MP + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MM6 + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MM6_A53 + bool + select SOC_MIMX8MM6 + help + NXP i.MX8MM A53 + +config SOC_MIMX8MM6_M4 + bool + select SOC_MIMX8MM6 + help + NXP i.MX8MM M4 + +config SOC_MIMX8MP + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8ML8_A53 + bool + select SOC_MIMX8MP + help + NXP i.MX8MP A53 + +config SOC_MIMX8MP_ADSP + bool + select SOC_MIMX8MP + help + Enable support for NXP i.MX 8MPLUS Audio DSP + +config SOC_MIMX8MP_M7 + bool + select SOC_MIMX8MP + help + Enable support for NXP i.MX 8MPLUS M7 MCU + +config SOC_MIMX8MQ6 + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MQ6_M4 + bool + select SOC_MIMX8MQ6 + help + Enable support for NXP i.MX 8M Quad M4 MCU + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx8m_adsp" if SOC_MIMX8MP_ADSP + +config SOC_MIMX8MN6 + bool + select SOC_SERIES_IMX8M + +config SOC_MIMX8MN6_A53 + bool + select SOC_MIMX8MN6 + help + NXP i.MX8MN A53 + +config SOC + default "mimx8mm6" if SOC_MIMX8MM6 + default "mimx8mn6" if SOC_MIMX8MN6 + default "mimx8ml8" if SOC_MIMX8MP + default "mimx8mq6" if SOC_MIMX8MQ6 + +config SOC_PART_NUMBER_MIMX8ML8DVNLZ + bool + +config SOC_PART_NUMBER_MIMX8MM6DVTLZ + bool + +config SOC_PART_NUMBER_MIMX8MM6CVTKZ + bool + +config SOC_PART_NUMBER_MIMX8MN6DVTJZ + bool + +config SOC_PART_NUMBER_MIMX8MN6DUCJZ + bool + +config SOC_PART_NUMBER_MIMX8MN6CVTIZ + bool + +config SOC_PART_NUMBER_MIMX8MN6CUCIZ + bool + +config SOC_PART_NUMBER_MIMX8MQ6DVAJZ + bool + +config SOC_PART_NUMBER + default "MIMX8ML8DVNLZ" if SOC_PART_NUMBER_MIMX8ML8DVNLZ + default "MIMX8MM6DVTLZ" if SOC_PART_NUMBER_MIMX8MM6DVTLZ + default "MIMX8MM6CVTKZ" if SOC_PART_NUMBER_MIMX8MM6CVTKZ + default "MIMX8MN6DVTJZ" if SOC_PART_NUMBER_MIMX8MN6DVTJZ + default "MIMX8MN6DUCJZ" if SOC_PART_NUMBER_MIMX8MN6DUCJZ + default "MIMX8MN6CVTIZ" if SOC_PART_NUMBER_MIMX8MN6CVTIZ + default "MIMX8MN6CUCIZ" if SOC_PART_NUMBER_MIMX8MN6CUCIZ + default "MIMX8MQ6DVAJZ" if SOC_PART_NUMBER_MIMX8MQ6DVAJZ diff --git a/soc/arm64/nxp_imx/mimx8m/mmu_regions.c b/soc/nxp/imx/imx8m/a53/mmu_regions.c similarity index 100% rename from soc/arm64/nxp_imx/mimx8m/mmu_regions.c rename to soc/nxp/imx/imx8m/a53/mmu_regions.c diff --git a/soc/arm64/nxp_imx/mimx8m/pinctrl_soc.h b/soc/nxp/imx/imx8m/a53/pinctrl_soc.h similarity index 100% rename from soc/arm64/nxp_imx/mimx8m/pinctrl_soc.h rename to soc/nxp/imx/imx8m/a53/pinctrl_soc.h diff --git a/soc/nxp/imx/imx8m/adsp/CMakeLists.txt b/soc/nxp/imx/imx8m/adsp/CMakeLists.txt new file mode 100644 index 00000000000000..a91c59914123ab --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8m/include/_soc_inthandlers.h b/soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/include/_soc_inthandlers.h rename to soc/nxp/imx/imx8m/adsp/_soc_inthandlers.h diff --git a/soc/nxp/imx/imx8m/adsp/include/adsp/cache.h b/soc/nxp/imx/imx8m/adsp/include/adsp/cache.h new file mode 100644 index 00000000000000..067c08901403cf --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imx/imx8m/adsp/include/adsp/io.h b/soc/nxp/imx/imx8m/adsp/include/adsp/io.h new file mode 100644 index 00000000000000..3d1f0ed98d5a74 --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imx/imx8m/adsp/include/soc.h b/soc/nxp/imx/imx8m/adsp/include/soc.h new file mode 100644 index 00000000000000..89ee9d96a5207b --- /dev/null +++ b/soc/nxp/imx/imx8m/adsp/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/xtensa/nxp_adsp/imx8m/linker.ld b/soc/nxp/imx/imx8m/adsp/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/linker.ld rename to soc/nxp/imx/imx8m/adsp/linker.ld diff --git a/soc/xtensa/nxp_adsp/imx8m/include/memory.h b/soc/nxp/imx/imx8m/adsp/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/include/memory.h rename to soc/nxp/imx/imx8m/adsp/memory.h diff --git a/soc/xtensa/nxp_adsp/imx8m/include/pinctrl_soc.h b/soc/nxp/imx/imx8m/adsp/pinctrl_soc.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8m/include/pinctrl_soc.h rename to soc/nxp/imx/imx8m/adsp/pinctrl_soc.h diff --git a/soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt b/soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt new file mode 100644 index 00000000000000..44a0caa5c78041 --- /dev/null +++ b/soc/nxp/imx/imx8m/m4_mini/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright (c) 2020, Manivannan Sadhasivam +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +if(CONFIG_OPENAMP_RSC_TABLE) + zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) + zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/linker.ld b/soc/nxp/imx/imx8m/m4_mini/linker.ld similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/linker.ld rename to soc/nxp/imx/imx8m/m4_mini/linker.ld diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/pinctrl_soc.h b/soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/pinctrl_soc.h rename to soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/soc.c b/soc/nxp/imx/imx8m/m4_mini/soc.c similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/soc.c rename to soc/nxp/imx/imx8m/m4_mini/soc.c diff --git a/soc/arm/nxp_imx/mimx8mm6_m4/soc.h b/soc/nxp/imx/imx8m/m4_mini/soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mm6_m4/soc.h rename to soc/nxp/imx/imx8m/m4_mini/soc.h diff --git a/soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt b/soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt new file mode 100644 index 00000000000000..2d5bd4a9f30b5f --- /dev/null +++ b/soc/nxp/imx/imx8m/m4_quad/CMakeLists.txt @@ -0,0 +1,13 @@ +# +# Copyright (c) 2021, Kwon Tae-young +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + ) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/pinctrl_soc.h b/soc/nxp/imx/imx8m/m4_quad/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mq6_m4/pinctrl_soc.h rename to soc/nxp/imx/imx8m/m4_quad/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/soc.c b/soc/nxp/imx/imx8m/m4_quad/soc.c similarity index 100% rename from soc/arm/nxp_imx/mimx8mq6_m4/soc.c rename to soc/nxp/imx/imx8m/m4_quad/soc.c diff --git a/soc/arm/nxp_imx/mimx8mq6_m4/soc.h b/soc/nxp/imx/imx8m/m4_quad/soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8mq6_m4/soc.h rename to soc/nxp/imx/imx8m/m4_quad/soc.h diff --git a/soc/nxp/imx/imx8m/m7/CMakeLists.txt b/soc/nxp/imx/imx8m/m7/CMakeLists.txt new file mode 100644 index 00000000000000..8b2c33a6294ca4 --- /dev/null +++ b/soc/nxp/imx/imx8m/m7/CMakeLists.txt @@ -0,0 +1,21 @@ +# +# Copyright (c) 2021, Laird Connectivity +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_include_directories(.) + +zephyr_sources( + soc.c + mpu_regions.c +) + +if(CONFIG_OPENAMP_RSC_TABLE) + zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) + zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/linker.ld b/soc/nxp/imx/imx8m/m7/linker.ld similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/linker.ld rename to soc/nxp/imx/imx8m/m7/linker.ld diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c b/soc/nxp/imx/imx8m/m7/mpu_regions.c similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/mpu_regions.c rename to soc/nxp/imx/imx8m/m7/mpu_regions.c diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h b/soc/nxp/imx/imx8m/m7/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/pinctrl_soc.h rename to soc/nxp/imx/imx8m/m7/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/soc.c b/soc/nxp/imx/imx8m/m7/soc.c similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/soc.c rename to soc/nxp/imx/imx8m/m7/soc.c diff --git a/soc/arm/nxp_imx/mimx8ml8_m7/soc.h b/soc/nxp/imx/imx8m/m7/soc.h similarity index 100% rename from soc/arm/nxp_imx/mimx8ml8_m7/soc.h rename to soc/nxp/imx/imx8m/m7/soc.h diff --git a/soc/nxp/imx/imx8ulp/CMakeLists.txt b/soc/nxp/imx/imx8ulp/CMakeLists.txt new file mode 100644 index 00000000000000..55a7321827309b --- /dev/null +++ b/soc/nxp/imx/imx8ulp/CMakeLists.txt @@ -0,0 +1,23 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8ULP_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx8ulp/Kconfig b/soc/nxp/imx/imx8ulp/Kconfig new file mode 100644 index 00000000000000..5bee7c22107486 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/Kconfig @@ -0,0 +1,11 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8ULP_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY diff --git a/soc/nxp/imx/imx8ulp/Kconfig.defconfig b/soc/nxp/imx/imx8ulp/Kconfig.defconfig new file mode 100644 index 00000000000000..424892563afff1 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8ULP + +if SOC_MIMX8ULP_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 528000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8ULP_ADSP + +endif # SOC_SERIES_IMX8ULP diff --git a/soc/nxp/imx/imx8ulp/Kconfig.soc b/soc/nxp/imx/imx8ulp/Kconfig.soc new file mode 100644 index 00000000000000..b7d4cadef7c6ff --- /dev/null +++ b/soc/nxp/imx/imx8ulp/Kconfig.soc @@ -0,0 +1,26 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8ULP + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8ulp" if SOC_SERIES_IMX8ULP + +config SOC_MIMX8ULP + bool + select SOC_SERIES_IMX8ULP + +config SOC + default "imx8ulp" if SOC_MIMX8ULP + +config SOC_MIMX8ULP_ADSP + bool + select SOC_MIMX8ULP + help + Enable support for NXP i.MX 8ULP Audio DSP + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx8ulp_adsp" if SOC_MIMX8ULP_ADSP diff --git a/soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt b/soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt new file mode 100644 index 00000000000000..a91c59914123ab --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8ulp/include/_soc_inthandlers.h b/soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8ulp/include/_soc_inthandlers.h rename to soc/nxp/imx/imx8ulp/adsp/_soc_inthandlers.h diff --git a/soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h b/soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h new file mode 100644 index 00000000000000..067c08901403cf --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h b/soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h new file mode 100644 index 00000000000000..3d1f0ed98d5a74 --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imx/imx8ulp/adsp/include/soc.h b/soc/nxp/imx/imx8ulp/adsp/include/soc.h new file mode 100644 index 00000000000000..89ee9d96a5207b --- /dev/null +++ b/soc/nxp/imx/imx8ulp/adsp/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/xtensa/nxp_adsp/imx8ulp/linker.ld b/soc/nxp/imx/imx8ulp/adsp/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/imx8ulp/linker.ld rename to soc/nxp/imx/imx8ulp/adsp/linker.ld diff --git a/soc/xtensa/nxp_adsp/imx8ulp/include/memory.h b/soc/nxp/imx/imx8ulp/adsp/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/imx8ulp/include/memory.h rename to soc/nxp/imx/imx8ulp/adsp/memory.h diff --git a/soc/nxp/imx/imx8x/CMakeLists.txt b/soc/nxp/imx/imx8x/CMakeLists.txt new file mode 100644 index 00000000000000..af445cb9e57ca6 --- /dev/null +++ b/soc/nxp/imx/imx8x/CMakeLists.txt @@ -0,0 +1,27 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX8QXP_ADSP) + zephyr_include_directories(adsp) + add_subdirectory(adsp) + + zephyr_sources( + adsp/pinctrl_soc.h + ) + + # west sign + + # See detailed comments in soc/intel/intel_adsp/common/CMakeLists.txt + add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + ) + + add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} + ) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx8x/Kconfig b/soc/nxp/imx/imx8x/Kconfig new file mode 100644 index 00000000000000..b5c9a4e446efd1 --- /dev/null +++ b/soc/nxp/imx/imx8x/Kconfig @@ -0,0 +1,15 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX8QXP_ADSP + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + select ATOMIC_OPERATIONS_BUILTIN + select GEN_ISR_TABLES + select XTENSA_SMALL_VECTOR_TABLE_ENTRY + select HAS_MCUX + +config MCUX_CORE_SUFFIX + default "_dsp" if SOC_MIMX8QXP_ADSP diff --git a/soc/nxp/imx/imx8x/Kconfig.defconfig b/soc/nxp/imx/imx8x/Kconfig.defconfig new file mode 100644 index 00000000000000..2e3699d95321a9 --- /dev/null +++ b/soc/nxp/imx/imx8x/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX8X + +if SOC_MIMX8QXP_ADSP + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 640000000 + +config SYS_CLOCK_TICKS_PER_SEC + default 50000 + +config DCACHE_LINE_SIZE + default 128 + +config GEN_IRQ_VECTOR_TABLE + default n + +config CACHE_MANAGEMENT + default y + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +endif # SOC_MIMX8QXP_ADSP + +endif # SOC_SERIES_IMX8X diff --git a/soc/nxp/imx/imx8x/Kconfig.soc b/soc/nxp/imx/imx8x/Kconfig.soc new file mode 100644 index 00000000000000..dc3c3de187fb52 --- /dev/null +++ b/soc/nxp/imx/imx8x/Kconfig.soc @@ -0,0 +1,36 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX8X + bool + select SOC_FAMILY_NXP_IMX + +config SOC_SERIES + default "imx8x" if SOC_SERIES_IMX8X + +config SOC_MIMX8QXP + bool + select SOC_SERIES_IMX8X + +config SOC + default "mimx8qx6" if SOC_MIMX8QXP + +config SOC_MIMX8QXP_ADSP + bool + select SOC_MIMX8QXP + help + Enable support for NXP i.MX 8QXP Audio DSP + +config SOC_TOOLCHAIN_NAME + string + default "nxp_imx_adsp" if SOC_MIMX8QXP_ADSP + +config SOC_PART_NUMBER_MIMX8QX6AVLFZ + bool + +config SOC_PART_NUMBER_MIMX8QX6CVLDZ + bool + +config SOC_PART_NUMBER + default "MIMX8QX6AVLFZ" if SOC_PART_NUMBER_MIMX8QX6AVLFZ + default "MIMX8QX6CVLDZ" if SOC_PART_NUMBER_MIMX8QX6CVLDZ diff --git a/soc/nxp/imx/imx8x/adsp/CMakeLists.txt b/soc/nxp/imx/imx8x/adsp/CMakeLists.txt new file mode 100644 index 00000000000000..a91c59914123ab --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/CMakeLists.txt @@ -0,0 +1,6 @@ +# NXP SoC family CMake file +# +# Copyright (c) 2021, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(include) diff --git a/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h b/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h new file mode 100644 index 00000000000000..daa9cfe668b416 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/_soc_inthandlers.h @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + * + * Functions here are designed to produce efficient code to + * search an Xtensa bitmask of interrupts, inspecting only those bits + * declared to be associated with a given interrupt level. Each + * dispatcher will handle exactly one flagged interrupt, in numerical + * order (low bits first) and will return a mask of that bit that can + * then be cleared by the calling code. Unrecognized bits for the + * level will invoke an error handler. + */ + +#include +#include +#include + +#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif + +static inline int _xtensa_handle_one_int1(unsigned int mask) +{ + int irq; + + if (mask & BIT(8)) { + mask = BIT(8); + irq = 8; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int2(unsigned int mask) +{ + int irq; + int i = 0; + + mask &= XCHAL_INTLEVEL2_MASK; + for (i = 0; i <= 31; i++) + if (mask & BIT(i)) { + mask = BIT(i); + irq = i; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int3(unsigned int mask) +{ + int irq; + + if (mask & BIT(1)) { + mask = BIT(1); + irq = 1; + goto handle_irq; + } + if (mask & BIT(3)) { + mask = BIT(3); + irq = 3; + goto handle_irq; + } + if (mask & BIT(31)) { + mask = BIT(31); + irq = 31; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int5(unsigned int mask) +{ + int irq; + + if (mask & BIT(0)) { + mask = BIT(0); + irq = 0; + goto handle_irq; + } + return 0; +handle_irq: + _sw_isr_table[irq].isr(_sw_isr_table[irq].arg); + return mask; +} + +static inline int _xtensa_handle_one_int0(unsigned int mask) +{ + return 0; +} + +static inline int _xtensa_handle_one_int4(unsigned int mask) +{ + return 0; +} + +static inline int _xtensa_handle_one_int6(unsigned int mask) +{ + return 0; +} + +static inline int _xtensa_handle_one_int7(unsigned int mask) +{ + return 0; +} diff --git a/soc/nxp/imx/imx8x/adsp/include/adsp/cache.h b/soc/nxp/imx/imx8x/adsp/include/adsp/cache.h new file mode 100644 index 00000000000000..067c08901403cf --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imx/imx8x/adsp/include/adsp/io.h b/soc/nxp/imx/imx8x/adsp/include/adsp/io.h new file mode 100644 index 00000000000000..3d1f0ed98d5a74 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imx/imx8x/adsp/include/soc.h b/soc/nxp/imx/imx8x/adsp/include/soc.h new file mode 100644 index 00000000000000..89ee9d96a5207b --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/nxp/imx/imx8x/adsp/linker.ld b/soc/nxp/imx/imx8x/adsp/linker.ld new file mode 100644 index 00000000000000..52d3a46b2381a9 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/linker.ld @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Linker command/script file + * + * Linker script for the NXP i.MX8 platform + */ + +OUTPUT_ARCH(xtensa) + +#include +#include +#include +#include + +#include +#include + +PROVIDE(__memctl_default = 0x00000000); +PROVIDE(_MemErrorHandler = 0x00000000); + +#define RAMABLE_REGION sdram0 :sdram0_phdr +#define ROMABLE_REGION sdram0 :sdram0_phdr + +MEMORY +{ + vector_reset_text : + org = XCHAL_RESET_VECTOR0_PADDR_IRAM, + len = MEM_RESET_TEXT_SIZE + vector_reset_lit : + org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE, + len = MEM_RESET_LIT_SIZE + vector_base_text : + org = XCHAL_VECBASE_RESET_PADDR_IRAM, + len = MEM_VECBASE_LIT_SIZE + vector_int2_lit : + org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int2_text : + org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_int3_lit : + org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int3_text : + org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_int4_lit : + org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int4_text : + org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_int5_lit : + org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_int5_text : + org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_kernel_lit : + org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_kernel_text : + org = XCHAL_KERNEL_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_user_lit : + org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_user_text : + org = XCHAL_USER_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + vector_double_lit : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE, + len = MEM_VECT_LIT_SIZE + vector_double_text : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM, + len = MEM_VECT_TEXT_SIZE + iram_text_start : + org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE, + len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE) + sdram0 : + org = SDRAM0_BASE, + len = SDRAM0_SIZE + sdram1 : + org = SDRAM1_BASE + SOF_MAILBOX_SIZE, + len = SDRAM1_SIZE - SOF_MAILBOX_SIZE +#ifdef CONFIG_GEN_ISR_TABLES + IDT_LIST : + org = IDT_BASE, + len = IDT_SIZE +#endif + + static_uuid_entries_seg (!ari) : + org = UUID_ENTRY_ELF_BASE, + len = UUID_ENTRY_ELF_SIZE + static_log_entries_seg (!ari) : + org = LOG_ENTRY_ELF_BASE, + len = LOG_ENTRY_ELF_SIZE + fw_metadata_seg (!ari) : + org = EXT_MANIFEST_ELF_BASE, + len = EXT_MANIFEST_ELF_SIZE +} + +PHDRS +{ + vector_reset_text_phdr PT_LOAD; + vector_reset_lit_phdr PT_LOAD; + vector_base_text_phdr PT_LOAD; + vector_base_lit_phdr PT_LOAD; + vector_int2_text_phdr PT_LOAD; + vector_int2_lit_phdr PT_LOAD; + vector_int3_text_phdr PT_LOAD; + vector_int3_lit_phdr PT_LOAD; + vector_int4_text_phdr PT_LOAD; + vector_int4_lit_phdr PT_LOAD; + vector_int5_text_phdr PT_LOAD; + vector_int5_lit_phdr PT_LOAD; + vector_kernel_text_phdr PT_LOAD; + vector_kernel_lit_phdr PT_LOAD; + vector_user_text_phdr PT_LOAD; + vector_user_lit_phdr PT_LOAD; + vector_double_text_phdr PT_LOAD; + vector_double_lit_phdr PT_LOAD; + iram_text_start_phdr PT_LOAD; + sdram0_phdr PT_LOAD; + sdram1_phdr PT_LOAD; + static_uuid_entries_phdr PT_NOTE; + static_log_entries_phdr PT_NOTE; + metadata_entries_phdr PT_NOTE; +} + +_rom_store_table = 0; + +PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR); + +ENTRY(CONFIG_KERNEL_ENTRY) + +/* Various memory-map dependent cache attribute settings: */ +_memmap_cacheattr_wb_base = 0x44024000; +_memmap_cacheattr_wt_base = 0x11021000; +_memmap_cacheattr_bp_base = 0x22022000; +_memmap_cacheattr_unused_mask = 0x00F00FFF; +_memmap_cacheattr_wb_trapnull = 0x4422422F; +_memmap_cacheattr_wba_trapnull = 0x4422422F; +_memmap_cacheattr_wbna_trapnull = 0x25222222; +_memmap_cacheattr_wt_trapnull = 0x1122122F; +_memmap_cacheattr_bp_trapnull = 0x2222222F; +_memmap_cacheattr_wb_strict = 0x44F24FFF; +_memmap_cacheattr_wt_strict = 0x11F21FFF; +_memmap_cacheattr_bp_strict = 0x22F22FFF; +_memmap_cacheattr_wb_allvalid = 0x44224222; +_memmap_cacheattr_wt_allvalid = 0x11221222; +_memmap_cacheattr_bp_allvalid = 0x22222222; +/* + * Every 512M in 4GB space has dedicate cache attribute. + * 1: write through + * 2: cache bypass + * 4: write back + * F: invalid access + */ +_memmap_cacheattr_imx8_wt_allvalid = 0x22212222; +PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_imx8_wt_allvalid); + +_EXT_MAN_ALIGN_ = 16; +EXTERN(ext_man_fw_ver) + +SECTIONS +{ + +#include + .ResetVector.text : ALIGN(4) + { + _ResetVector_text_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + _ResetVector_text_end = ABSOLUTE(.); + } >vector_reset_text :vector_reset_text_phdr + + .ResetVector.literal : ALIGN(4) + { + _ResetVector_literal_start = ABSOLUTE(.); + *(.ResetVector.literal) + _ResetVector_literal_end = ABSOLUTE(.); + } >vector_reset_lit :vector_reset_lit_phdr + + .WindowVectors.text : ALIGN(4) + { + _WindowVectors_text_start = ABSOLUTE(.); + KEEP (*(.WindowVectors.text)) + _WindowVectors_text_end = ABSOLUTE(.); + } >vector_base_text :vector_base_text_phdr + + .Level2InterruptVector.literal : ALIGN(4) + { + _Level2InterruptVector_literal_start = ABSOLUTE(.); + *(.Level2InterruptVector.literal) + _Level2InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int2_lit :vector_int2_lit_phdr + + .Level2InterruptVector.text : ALIGN(4) + { + _Level2InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level2InterruptVector.text)) + _Level2InterruptVector_text_end = ABSOLUTE(.); + } >vector_int2_text :vector_int2_text_phdr + + .Level3InterruptVector.literal : ALIGN(4) + { + _Level3InterruptVector_literal_start = ABSOLUTE(.); + *(.Level3InterruptVector.literal) + _Level3InterruptVector_literal_end = ABSOLUTE(.); + } >vector_int3_lit :vector_int3_lit_phdr + + .Level3InterruptVector.text : ALIGN(4) + { + _Level3InterruptVector_text_start = ABSOLUTE(.); + KEEP (*(.Level3InterruptVector.text)) + _Level3InterruptVector_text_end = ABSOLUTE(.); + } >vector_int3_text :vector_int3_text_phdr + + .DebugExceptionVector.literal : ALIGN(4) + { + _DebugExceptionVector_literal_start = ABSOLUTE(.); + *(.DebugExceptionVector.literal) + _DebugExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int4_lit :vector_int4_lit_phdr + + .DebugExceptionVector.text : ALIGN(4) + { + _DebugExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DebugExceptionVector.text)) + _DebugExceptionVector_text_end = ABSOLUTE(.); + } >vector_int4_text :vector_int4_text_phdr + + .NMIExceptionVector.literal : ALIGN(4) + { + _NMIExceptionVector_literal_start = ABSOLUTE(.); + *(.NMIExceptionVector.literal) + _NMIExceptionVector_literal_end = ABSOLUTE(.); + } >vector_int5_lit :vector_int5_lit_phdr + + .NMIExceptionVector.text : ALIGN(4) + { + _NMIExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.NMIExceptionVector.text)) + _NMIExceptionVector_text_end = ABSOLUTE(.); + } >vector_int5_text :vector_int5_text_phdr + + .KernelExceptionVector.literal : ALIGN(4) + { + _KernelExceptionVector_literal_start = ABSOLUTE(.); + *(.KernelExceptionVector.literal) + _KernelExceptionVector_literal_end = ABSOLUTE(.); + } >vector_kernel_lit :vector_kernel_lit_phdr + + .KernelExceptionVector.text : ALIGN(4) + { + _KernelExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.KernelExceptionVector.text)) + _KernelExceptionVector_text_end = ABSOLUTE(.); + } >vector_kernel_text :vector_kernel_text_phdr + + .UserExceptionVector.literal : ALIGN(4) + { + _UserExceptionVector_literal_start = ABSOLUTE(.); + *(.UserExceptionVector.literal) + _UserExceptionVector_literal_end = ABSOLUTE(.); + } >vector_user_lit :vector_user_lit_phdr + + .UserExceptionVector.text : ALIGN(4) + { + _UserExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.UserExceptionVector.text)) + _UserExceptionVector_text_end = ABSOLUTE(.); + } >vector_user_text :vector_user_text_phdr + + .DoubleExceptionVector.literal : ALIGN(4) + { + _DoubleExceptionVector_literal_start = ABSOLUTE(.); + *(.DoubleExceptionVector.literal) + _DoubleExceptionVector_literal_end = ABSOLUTE(.); + } >vector_double_lit :vector_double_lit_phdr + + .DoubleExceptionVector.text : ALIGN(4) + { + _DoubleExceptionVector_text_start = ABSOLUTE(.); + KEEP (*(.DoubleExceptionVector.text)) + _DoubleExceptionVector_text_end = ABSOLUTE(.); + } >vector_double_text :vector_double_text_phdr + + .iram.text : ALIGN(4) + { + _stext = .; + _iram_text_start = ABSOLUTE(.); + *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) + _iram_text_end = ABSOLUTE(.); + } >iram_text_start :iram_text_start_phdr + + .rodata : ALIGN(4) + { + __rodata_region_start = ABSOLUTE(.); + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); + KEEP (*(.xt_except_table)) + KEEP (*(.gcc_except_table .gcc_except_table.*)) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + KEEP (*(.eh_frame)) + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + . = ALIGN(4); + _bss_table_start = ABSOLUTE(.); + LONG(_bss_start) + LONG(_bss_end) + _bss_table_end = ABSOLUTE(.); + __rodata_region_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + + .module_init : ALIGN(4) + { + _module_init_start = ABSOLUTE(.); + *(*.initcall) + _module_init_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + + .text : ALIGN(4) + { + _stext = .; + __text_region_start = ABSOLUTE(.); + KEEP (*(.ResetVector.text)) + *(.ResetVector.literal) + *(.entry.text) + *(.init.literal) + KEEP(*(.init)) + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.fini.literal) + KEEP(*(.fini)) + *(.gnu.version) + __text_region_end = ABSOLUTE(.); + _etext = .; + } >sdram0 :sdram0_phdr + +#include + + .fw_ready : ALIGN(4) + { + KEEP(*(".fw_ready")); + KEEP (*(.fw_ready_metadata)) + } >sdram0 :sdram0_phdr + + .noinit : ALIGN(4) + { + *(.noinit) + *(.noinit.*) + } >sdram0 :sdram0_phdr + + .data : ALIGN(4) + { + __data_start = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + KEEP(*(.gnu.linkonce.d.*personality*)) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + KEEP(*(.jcr)) + _trace_ctx_start = ABSOLUTE(.); + *(.trace_ctx) + _trace_ctx_end = ABSOLUTE(.); + . = ALIGN(4); + *(.gna_model) + __data_end = ABSOLUTE(.); + . = ALIGN(4096); + } >sdram0 :sdram0_phdr + + .lit4 : ALIGN(4) + { + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + +#include + + .bss (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + _bss_end = ABSOLUTE(.); + } >sdram0 :sdram0_phdr + + .heap_mem (NOLOAD) : ALIGN(8) + { + . = ALIGN (8); + _heap_mem_start = ABSOLUTE(.); + *(*.heap_mem) + _heap_mem_end = ABSOLUTE(.); + } >sdram1 :sdram1_phdr + + /* stack */ + _end = ALIGN (8); + PROVIDE(end = ALIGN (8)); + + __stack = SDRAM1_BASE + SDRAM1_SIZE; + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + .debug_ranges 0 : { *(.debug_ranges) } + .xtensa.info 0 : { *(.xtensa.info) } + .xt.insn 0 : + { + KEEP (*(.xt.insn)) + KEEP (*(.gnu.linkonce.x.*)) + } + .xt.prop 0 : + { + KEEP (*(.xt.prop)) + KEEP (*(.xt.prop.*)) + KEEP (*(.gnu.linkonce.prop.*)) + } + .xt.lit 0 : + { + KEEP (*(.xt.lit)) + KEEP (*(.xt.lit.*)) + KEEP (*(.gnu.linkonce.p.*)) + } + .xt.profile_range 0 : + { + KEEP (*(.xt.profile_range)) + KEEP (*(.gnu.linkonce.profile_range.*)) + } + .xt.profile_ranges 0 : + { + KEEP (*(.xt.profile_ranges)) + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) + } + .xt.profile_files 0 : + { + KEEP (*(.xt.profile_files)) + KEEP (*(.gnu.linkonce.xt.profile_files.*)) + } +#ifdef CONFIG_GEN_ISR_TABLES +#include +#endif + + .static_uuid_entries (COPY) : ALIGN(1024) + { + *(*.static_uuids) + } > static_uuid_entries_seg :static_uuid_entries_phdr + + .static_log_entries (COPY) : ALIGN(1024) + { + *(*.static_log*) + } > static_log_entries_seg :static_log_entries_phdr + + .fw_metadata (COPY) : ALIGN(1024) + { + KEEP (*(.fw_metadata)) + . = ALIGN(_EXT_MAN_ALIGN_); + } >fw_metadata_seg :metadata_entries_phdr +} diff --git a/soc/nxp/imx/imx8x/adsp/memory.h b/soc/nxp/imx/imx8x/adsp/memory.h new file mode 100644 index 00000000000000..56bac21c780b14 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/memory.h @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ +#define ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ + +#define IRAM_RESERVE_HEADER_SPACE 0x400 + +#define IRAM_BASE 0x596f8000 +#define IRAM_SIZE 0x800 + +#define SDRAM0_BASE 0x92400000 +#define SDRAM0_SIZE 0x800000 + +#define SDRAM1_BASE 0x92C00000 +#define SDRAM1_SIZE 0x800000 + +/* The reset vector address in SRAM and its size */ +#define MEM_RESET_TEXT_SIZE 0x2e0 +#define MEM_RESET_LIT_SIZE 0x120 + +/* This is the base address of all the vectors defined in IRAM */ +#define XCHAL_VECBASE_RESET_PADDR_IRAM \ + (IRAM_BASE + IRAM_RESERVE_HEADER_SPACE) + +#define MEM_VECBASE_LIT_SIZE 0x178 + +/* + * EXCEPTIONS and VECTORS + */ +#define XCHAL_RESET_VECTOR0_PADDR_IRAM 0x596F8000 + +/* Vector and literal sizes */ +#define MEM_VECT_LIT_SIZE 0x4 +#define MEM_VECT_TEXT_SIZE 0x1C +#define MEM_VECT_SIZE (MEM_VECT_TEXT_SIZE +\ + MEM_VECT_LIT_SIZE) + +/* The addresses of the vectors. + * Only the mem_error vector continues to point to its ROM address. + */ +#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x17C) + +#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x19C) + +#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1BC) + +#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1DC) + +#define XCHAL_KERNEL_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x1FC) + +#define XCHAL_USER_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x21C) + +#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM \ + (XCHAL_VECBASE_RESET_PADDR_IRAM + 0x23C) + +/* Location for the intList section which is later used to construct the + * Interrupt Descriptor Table (IDT). This is a bogus address as this + * section will be stripped off in the final image. + */ +#define IDT_BASE (IRAM_BASE + IRAM_SIZE) + +/* size of the Interrupt Descriptor Table (IDT) */ +#define IDT_SIZE 0x2000 + +/* physical DSP addresses */ +#define IRAM_BASE 0x596f8000 +#define IRAM_SIZE 0x800 + +#define DRAM0_BASE 0x596e8000 +#define DRAM0_SIZE 0x8000 + +#define DRAM1_BASE 0x596f0000 +#define DRAM1_SIZE 0x8000 + +#define SDRAM0_BASE 0x92400000 +#define SDRAM0_SIZE 0x800000 + +#define SDRAM1_BASE 0x92C00000 +#define SDRAM1_SIZE 0x800000 + +#define XSHAL_MU13_SIDEB_BYPASS_PADDR 0x5D310000 +#define MU_BASE XSHAL_MU13_SIDEB_BYPASS_PADDR + +#define EDMA0_BASE 0x59200000 +#define EDMA0_SIZE 0x10000 + +#define ESAI_BASE 0x59010000 +#define ESAI_SIZE 0x00010000 + +#define SAI_1_BASE 0x59050000 +#define SAI_1_SIZE 0x00010000 + +#define UUID_ENTRY_ELF_BASE 0x1FFFA000 +#define UUID_ENTRY_ELF_SIZE 0x6000 + +#define LOG_ENTRY_ELF_BASE 0x20000000 +#define LOG_ENTRY_ELF_SIZE 0x2000000 + +#define EXT_MANIFEST_ELF_BASE (LOG_ENTRY_ELF_BASE + LOG_ENTRY_ELF_SIZE) +#define EXT_MANIFEST_ELF_SIZE 0x2000000 + +/* + * The Heap and Stack on i.MX8 are organized like this :- + * + * +--------------------------------------------------------------------------+ + * | Offset | Region | Size | + * +---------------------+----------------+-----------------------------------+ + * | SDRAM_BASE | RO Data | SOF_DATA_SIZE | + * | | Data | | + * | | BSS | | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_SYSTEM_BASE | System Heap | HEAP_SYSTEM_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_RUNTIME_BASE | Runtime Heap | HEAP_RUNTIME_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | HEAP_BUFFER_BASE | Module Buffers | HEAP_BUFFER_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_END | Stack | SOF_STACK_SIZE | + * +---------------------+----------------+-----------------------------------+ + * | SOF_STACK_BASE | | | + * +---------------------+----------------+-----------------------------------+ + */ + +#define SRAM_OUTBOX_BASE SDRAM1_BASE +#define SRAM_OUTBOX_SIZE 0x1000 +#define SRAM_OUTBOX_OFFSET 0 + +#define SRAM_INBOX_BASE (SRAM_OUTBOX_BASE + SRAM_OUTBOX_SIZE) +#define SRAM_INBOX_SIZE 0x1000 +#define SRAM_INBOX_OFFSET SRAM_OUTBOX_SIZE + +#define SRAM_DEBUG_BASE (SRAM_INBOX_BASE + SRAM_INBOX_SIZE) +#define SRAM_DEBUG_SIZE 0x800 +#define SRAM_DEBUG_OFFSET (SRAM_INBOX_OFFSET + SRAM_INBOX_SIZE) + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 +#define SRAM_EXCEPT_OFFSET (SRAM_DEBUG_OFFSET + SRAM_DEBUG_SIZE) + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 +#define SRAM_STREAM_OFFSET (SRAM_EXCEPT_OFFSET + SRAM_EXCEPT_SIZE) + +#define SRAM_TRACE_BASE (SRAM_STREAM_BASE + SRAM_STREAM_SIZE) +#define SRAM_TRACE_SIZE 0x1000 +#define SRAM_TRACE_OFFSET (SRAM_STREAM_OFFSET + SRAM_STREAM_SIZE) + +#define SOF_MAILBOX_SIZE (SRAM_INBOX_SIZE + SRAM_OUTBOX_SIZE \ + + SRAM_DEBUG_SIZE + SRAM_EXCEPT_SIZE \ + + SRAM_STREAM_SIZE + SRAM_TRACE_SIZE) + +#endif /* ZEPHYR_SOC_NXP_ADSP_MEMORY_H_ */ diff --git a/soc/nxp/imx/imx8x/adsp/pinctrl_soc.h b/soc/nxp/imx/imx8x/adsp/pinctrl_soc.h new file mode 100644 index 00000000000000..ac748220b56055 --- /dev/null +++ b/soc/nxp/imx/imx8x/adsp/pinctrl_soc.h @@ -0,0 +1,41 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct pinctrl_soc_pinmux { + uint32_t pad; + uint32_t mux; +}; + +typedef struct pinctrl_soc_pinmux pinctrl_soc_pin_t; + +#define IMX8_PINMUX(n) \ +{ \ + .pad = DT_PROP_BY_IDX(n, pinmux, 0), \ + .mux = DT_PROP_BY_IDX(n, pinmux, 1), \ +}, + +#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)\ + IMX8_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx)) + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \ + DT_FOREACH_PROP_ELEM, pinmux, Z_PINCTRL_PINMUX) }; + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_XTENSA_NXP_ADSP_IMX8_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/imx/imx9/CMakeLists.txt b/soc/nxp/imx/imx9/CMakeLists.txt new file mode 100644 index 00000000000000..dc7d1917a16b16 --- /dev/null +++ b/soc/nxp/imx/imx9/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_MIMX9352_A55) + zephyr_include_directories(.) + zephyr_include_directories(a55) + + zephyr_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/a55/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/nxp/imx/imx9/Kconfig b/soc/nxp/imx/imx9/Kconfig new file mode 100644 index 00000000000000..5ea7bed765329e --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig @@ -0,0 +1,13 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMX9352_A55 + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select HAS_MCUX if CLOCK_CONTROL + select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL + select HAS_MCUX_IOMUXC if PINCTRL + +config MCUX_CORE_SUFFIX + default "_ca55" if SOC_MIMX9352_A55 diff --git a/soc/nxp/imx/imx9/Kconfig.defconfig b/soc/nxp/imx/imx9/Kconfig.defconfig new file mode 100644 index 00000000000000..0556f9e915f680 --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMX9 + +rsource "Kconfig.defconfig.*" + +endif # SOC_SERIES_IMX9 diff --git a/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 b/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 new file mode 100644 index 00000000000000..f53cc12c0f0996 --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig.defconfig.mimx93.a55 @@ -0,0 +1,27 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMX9352_A55 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 240 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 24000000 + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +endif diff --git a/soc/nxp/imx/imx9/Kconfig.soc b/soc/nxp/imx/imx9/Kconfig.soc new file mode 100644 index 00000000000000..667e3fc1f0b237 --- /dev/null +++ b/soc/nxp/imx/imx9/Kconfig.soc @@ -0,0 +1,32 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMX9 + bool + select SOC_FAMILY_NXP_IMX + +config SOC_MIMX9352 + bool + select SOC_SERIES_IMX9 + +config SOC_MIMX9352_A55 + bool + select SOC_MIMX9352 + help + NXP i.MX93 A55 + +config SOC_PART_NUMBER_MIMX9352CVUXK + bool + +config SOC_PART_NUMBER_MIMX9352DVUXM + bool + +config SOC_PART_NUMBER + default "MIMX9352CVUXK" if SOC_PART_NUMBER_MIMX9352CVUXK + default "MIMX9352DVUXM" if SOC_PART_NUMBER_MIMX9352DVUXM + +config SOC + default "mimx9352" if SOC_MIMX9352 + +config SOC_SERIES + default "imx9" if SOC_SERIES_IMX9 diff --git a/soc/arm64/nxp_imx/mimx9/linker.ld b/soc/nxp/imx/imx9/a55/linker.ld similarity index 100% rename from soc/arm64/nxp_imx/mimx9/linker.ld rename to soc/nxp/imx/imx9/a55/linker.ld diff --git a/soc/arm64/nxp_imx/mimx9/mmu_regions.c b/soc/nxp/imx/imx9/a55/mmu_regions.c similarity index 100% rename from soc/arm64/nxp_imx/mimx9/mmu_regions.c rename to soc/nxp/imx/imx9/a55/mmu_regions.c diff --git a/soc/arm64/nxp_imx/mimx9/pinctrl_soc.h b/soc/nxp/imx/imx9/pinctrl_soc.h similarity index 100% rename from soc/arm64/nxp_imx/mimx9/pinctrl_soc.h rename to soc/nxp/imx/imx9/pinctrl_soc.h diff --git a/soc/nxp/imx/soc.yml b/soc/nxp/imx/soc.yml new file mode 100644 index 00000000000000..c1a4c16b37b2a9 --- /dev/null +++ b/soc/nxp/imx/soc.yml @@ -0,0 +1,62 @@ +family: +- name: nxp_imx + series: + - name: imx8 + socs: + - name: mimx8qm6 + cpuclusters: + - name: adsp + - name: a72 + - name: a53 + - name: m4 + - name: imx8x + socs: + - name: mimx8qx6 + cpuclusters: + - name: adsp + - name: a35 + - name: m4 + - name: imx8ulp + socs: + - name: imx8ulp + cpuclusters: + - name: adsp + - name: f1_dsp + - name: a35 + - name: imx8m + socs: + - name: mimx8ml8 + cpuclusters: + - name: adsp + - name: a53 + - name: m7 + - name: mimx8mm6 + cpuclusters: + - name: a53 + - name: m4 + - name: mimx8mn6 + cpuclusters: + - name: a53 + - name: m7 + - name: mimx8mq6 + cpuclusters: + - name: a53 + - name: m4 + - name: imx9 + socs: + - name: mimx9352 + cpuclusters: + - name: a55 + - name: m33 + - name: imx6sx + socs: + - name: mcimx6x + cpuclusters: + - name: a9 + - name: m4 + - name: imx7d + socs: + - name: mcimx7d + cpuclusters: + - name: a7 + - name: m4 diff --git a/soc/nxp/imxrt/CMakeLists.txt b/soc/nxp/imxrt/CMakeLists.txt new file mode 100644 index 00000000000000..25cd1b81554513 --- /dev/null +++ b/soc/nxp/imxrt/CMakeLists.txt @@ -0,0 +1,42 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) + +zephyr_include_directories(.) +zephyr_include_directories(${SOC_SERIES}) + +zephyr_linker_sources_ifdef(CONFIG_NXP_IMXRT_BOOT_HEADER + ROM_START SORT_KEY 0 boot_header.ld) + +if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX) + if(CONFIG_DEVICE_CONFIGURATION_DATA) + set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data") + endif() + zephyr_sources(mpu_regions.c) + zephyr_linker_section_configure( + SECTION .rom_start + INPUT ".boot_hdr.conf" + OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET} + KEEP + PRIO 10 + ) + zephyr_linker_section_configure( + SECTION .rom_start + INPUT ".boot_hdr.ivt" + ".boot_hdr.data" + ${boot_hdr_dcd_data_section} + OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET} + KEEP + PRIO 11 + ) + zephyr_compile_definitions(XIP_EXTERNAL_FLASH) +endif() + +if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX) + zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld) +endif() + +if(CONFIG_MEMC) + zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc) +endif() diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig new file mode 100644 index 00000000000000..6306520fd38c1b --- /dev/null +++ b/soc/nxp/imxrt/Kconfig @@ -0,0 +1,190 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMXRT + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_PM + +if SOC_FAMILY_NXP_IMXRT + +# Source series Kconfig files first, so SOCs +# can override the defaults given here +rsource "*/Kconfig" + +# Used for default value in FLASH_MCUX_FLEXSPI_XIP +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_MCUX_FLEXSPI_XIP + bool "MCUX FlexSPI flash access with xip" + default $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + select XIP + help + Allows for the soc to safely initialize the clocks for the + FlexSpi when planning to execute code in FlexSpi Memory. + +if FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET + prompt "FlexSPI drivers relocation target" + default FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM + help + Select the location to run the FlexSPI drivers when using + the flash API. + +config FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM + bool "ITCM" + select CODE_DATA_RELOCATION + +config FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM + bool "RAM" + select CODE_DATA_RELOCATION_SRAM + +endchoice + +config FLASH_MCUX_FLEXSPI_XIP_MEM + string + default "ITCM" if FLASH_MCUX_FLEXSPI_XIP_MEM_ITCM + default "RAM" if FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM + +endif # FLASH_MCUX_FLEXSPI_XIP && MEMC_MCUX_FLEXSPI + +# Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig +# should be set elsewhere, since the determination of which SOC core +# requires the boot header is SOC specific. +config NXP_IMXRT_BOOT_HEADER + bool "Boot header" + default y + depends on !(BOOTLOADER_MCUBOOT || SECOND_CORE_MCUX) + help + Enable data structures required by the boot ROM to boot the + application from an external flash device. + +if NXP_IMXRT_BOOT_HEADER + +choice BOOT_DEVICE + prompt "Boot device" + default BOOT_FLEXSPI_NOR + +config BOOT_FLEXSPI_NOR + bool "FlexSPI serial NOR" + depends on HAS_MCUX_FLEXSPI + +config BOOT_FLEXSPI_NAND + bool "FlexSPI serial NAND" + depends on HAS_MCUX_FLEXSPI + +config BOOT_SEMC_NOR + bool "SEMC parallel NOR" + depends on HAS_MCUX_SEMC + +config BOOT_SEMC_NAND + bool "SEMC parallel NAND" + depends on HAS_MCUX_SEMC + +endchoice # BOOT_DEVICE + +config FLEXSPI_CONFIG_BLOCK_OFFSET + hex "FlexSPI config block offset" + default 0x400 if SOC_SERIES_IMXRT5XX || SOC_SERIES_IMXRT6XX + default 0x0 if BOOT_FLEXSPI_NOR + help + FlexSPI configuration block consists of parameters regarding specific + flash devices including read command sequence, quad mode enablement + sequence (optional), etc. The boot ROM expects FlexSPI configuration + parameter to be presented in serial nor flash. + +config IMAGE_VECTOR_TABLE_OFFSET + hex "Image vector table offset" + default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR + default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND + help + The Image Vector Table (IVT) provides the boot ROM with pointers to + the application entry point and device configuration data. The boot + ROM requires a fixed IVT offset for each type of boot device. + +config DEVICE_CONFIGURATION_DATA + bool "Device configuration data" + help + Device configuration data (DCD) provides a sequence of commands to + the boot ROM to initialize components such as an SDRAM. This is + useful if your application expects components like SDRAM to be + initialized at boot time. + + +endif # NXP_IMXRT_BOOT_HEADER + +config NXP_IMX_EXTERNAL_SDRAM + bool "Allow access to external SDRAM region" + help + Enable access to external SDRAM region managed by the SEMC. This + setting should be enabled when the application uses SDRAM, or + an MPU region will be defined to disable cached access to the + SDRAM memory space. + +config NXP_IMX_RT_ROM_RAMLOADER + depends on !FLASH_MCUX_FLEXSPI_XIP && NXP_IMXRT_BOOT_HEADER + # Required so that debugger will load image to correct offset + select BUILD_OUTPUT_HEX + bool "Create output image that IMX RT ROM can load from FlexSPI to ram" + help + Builds an output image that the IMX RT BootROM can load from the + FlexSPI boot device into RAM region. The image will be loaded + from FLEXSPI into the region specified by `zephyr,flash` node. + +# Setup LMA adjustment if using the RAMLOADER feature of ROM +FLASH_CHOSEN := zephyr,flash +FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) +FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@402a8000,1) +config BUILD_OUTPUT_ADJUST_LMA + default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER + +config SECOND_CORE_MCUX + bool "Dual core operation on the RT11xx series" + depends on SOC_SERIES_IMXRT11XX + help + Indicates the second core will be enabled, and the part will run + in dual core mode. Enables dual core operation on the RT11xx series, + by booting an image targeting the Cortex-M4 from the Cortex-M7 CPU. + The M4 image will be loaded from flash into RAM based off a + generated header specifying the VMA and LMA of each memory section + to load + + +config FLEXSPI_CONFIG_BLOCK_OFFSET + hex + default 0x400 if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +config PM_MCUX_GPC + bool "MCUX general power controller driver" + +config PM_MCUX_DCDC + bool "MCUX dcdc converter module driver" + +config PM_MCUX_PMU + bool "MCUX power management unit driver" + +config DCDC_VALUE + hex "DCDC value for VDD_SOC" + +config INIT_ARM_PLL + bool "Initialize ARM PLL" + +config INIT_VIDEO_PLL + bool "Initialize Video PLL" + +config INIT_ENET_PLL + bool + help + If y, the Ethernet PLL is initialized. Always enabled on e.g. + MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection + for MIMXRT1021"). + +endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +endif # SOC_FAMILY_NXP_IMXRT diff --git a/soc/nxp/imxrt/Kconfig.defconfig b/soc/nxp/imxrt/Kconfig.defconfig new file mode 100644 index 00000000000000..36f048c7f3cefb --- /dev/null +++ b/soc/nxp/imxrt/Kconfig.defconfig @@ -0,0 +1,152 @@ +# Copyright 2017-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_IMXRT + +# Source series Kconfig files first, so SOCs +# can override the defaults given here +rsource "*/Kconfig.defconfig" + +if SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +config SERIAL_INIT_PRIORITY + default 55 if SERIAL + depends on SERIAL + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR + +config PINCTRL_IMX + default y if HAS_MCUX_IOMUXC + depends on PINCTRL + +config ADC_MCUX_12B1MSPS_SAR + default y if HAS_MCUX_12B1MSPS_SAR + depends on ADC + +config LOG_BACKEND_SWO_FREQ_HZ + default 7500000 + depends on LOG_BACKEND_SWO + +# set the tick per sec as a divider of the GPT clock source +config SYS_CLOCK_TICKS_PER_SEC + default 4096 if MCUX_GPT_TIMER + +DT_SYSCLK_PATH := $(dt_nodelabel_path,sysclk) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,$(DT_SYSCLK_PATH),clock-frequency) if SOC_SERIES_IMXRT10XX && CORTEX_M_SYSTICK + default 32768 if MCUX_GPT_TIMER + +# Disable systick if using MCUX_GPT_TIMER, as they will conflict +config CORTEX_M_SYSTICK + default n if MCUX_GPT_TIMER + +config PM_MCUX_GPC + default y if HAS_MCUX_GPC + depends on SOC_SERIES_IMXRT11XX && PM + +# Don't allow SOC to sleep after tests complete when PM is enabled +config ZTEST_NO_YIELD + default y if (ZTEST && PM) + +if SOC_SERIES_IMXRT10XX && PM + +config CODE_DATA_RELOCATION + default y + +config PM_MCUX_GPC + default y if HAS_MCUX_GPC + +config PM_MCUX_DCDC + default y if HAS_MCUX_DCDC + +config PM_MCUX_PMU + default y if HAS_MCUX_PMU + +endif # SOC_SERIES_IMXRT10XX && PM + +if ETH_NXP_ENET + +config SYSTEM_WORKQUEUE_STACK_SIZE + default 1560 + +endif # ETH_NXP_ENET + +config MEMC + default y + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_EHCI +endchoice + +DT_CHOSEN_Z_DTCM := zephyr,dtcm + +choice SEGGER_RTT_SECTION + default SEGGER_RTT_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) + depends on USE_SEGGER_RTT +endchoice + +choice SEGGER_SYSVIEW_SECTION + default SEGGER_SYSVIEW_SECTION_DTCM if $(dt_chosen_enabled,$(DT_CHOSEN_Z_DTCM)) + depends on SEGGER_SYSTEMVIEW +endchoice + +# +# MBEDTLS is larger but much faster than TinyCrypt so choose wisely +# +config MBEDTLS +#config TINYCRYPT + default y if CSPRNG_ENABLED + depends on ENTROPY_GENERATOR + +if MBEDTLS +# +# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than +# what the ztest_thread_stack defaults to. +# +config TEST_EXTRA_STACK_SIZE + int + default 1024 +endif # MBEDTLS + +# Enable cache management features when using M7 core, since these parts +# have L1 instruction and data caches that should be enabled at boot +config CACHE_MANAGEMENT + default y if CPU_CORTEX_M7 + +endif # SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX + +# Logic to set flash size for all IMXRT parts +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) +DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_FLEXSPI) + +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(DT_FLASH_HAS_SIZE_PROP) + +if FLASH_MCUX_FLEXSPI_XIP + +# Avoid RWW hazards by defaulting logging to disabled +choice FLASH_LOG_LEVEL_CHOICE + default FLASH_LOG_LEVEL_OFF +endchoice + +choice MEMC_LOG_LEVEL_CHOICE + default MEMC_LOG_LEVEL_OFF +endchoice + +endif + +endif # SOC_FAMILY_NXP_IMXRT diff --git a/soc/nxp/imxrt/Kconfig.soc b/soc/nxp/imxrt/Kconfig.soc new file mode 100644 index 00000000000000..a12e7f5917e95e --- /dev/null +++ b/soc/nxp/imxrt/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_IMXRT + bool + +config SOC_FAMILY + default "nxp_imxrt" if SOC_FAMILY_NXP_IMXRT + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/imxrt/boot_header.ld b/soc/nxp/imxrt/boot_header.ld new file mode 100644 index 00000000000000..e46fa5789e340e --- /dev/null +++ b/soc/nxp/imxrt/boot_header.ld @@ -0,0 +1,21 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; +#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) +KEEP(*(.boot_hdr.conf)) +#endif +#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) +KEEP(*(.flash_conf)) +#endif +. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET; +KEEP(*(.boot_hdr.ivt)) +#if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) +KEEP(*(.boot_hdr.data)) +#ifdef CONFIG_DEVICE_CONFIGURATION_DATA + KEEP(*(.boot_hdr.dcd_data)) +#endif /* CONFIG_DEVICE_CONFIGURATION_DATA */ +#endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */ diff --git a/soc/arm/nxp_imx/rt/flexspi_nor_config.h b/soc/nxp/imxrt/flexspi_nor_config.h similarity index 99% rename from soc/arm/nxp_imx/rt/flexspi_nor_config.h rename to soc/nxp/imxrt/flexspi_nor_config.h index 3eac1ce548c54e..34ce949936f20a 100644 --- a/soc/arm/nxp_imx/rt/flexspi_nor_config.h +++ b/soc/nxp/imxrt/flexspi_nor_config.h @@ -91,7 +91,7 @@ enum { kFlexSpiSerialClk_133MHz = 7, }; #elif defined(CONFIG_SOC_MIMXRT1051) || defined(CONFIG_SOC_MIMXRT1052) || \ - defined(CONFIG_SOC_SERIES_IMX_RT11XX) + defined(CONFIG_SOC_SERIES_IMXRT11XX) enum { kFlexSpiSerialClk_30MHz = 1, kFlexSpiSerialClk_50MHz = 2, diff --git a/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt new file mode 100644 index 00000000000000..5eb0d46c0f377a --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt @@ -0,0 +1,27 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) + +if(CONFIG_PM) + zephyr_sources(power.c) + zephyr_code_relocate(FILES power.c LOCATION ITCM_TEXT) + if(CONFIG_SOC_MIMXRT1064) + zephyr_sources(lpm_rt1064.c) + zephyr_code_relocate(FILES lpm_rt1064 LOCATION ITCM_TEXT) + endif() +endif() + +if(CONFIG_MEMC_MCUX_FLEXSPI) + zephyr_sources(flexspi.c) + if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flexspi.c LOCATION ITCM_TEXT) + endif() +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig new file mode 100644 index 00000000000000..7884383b3a65bb --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig @@ -0,0 +1,150 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT10XX + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select ARM + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_CACHE + select HAS_MCUX_12B1MSPS_SAR if !SOC_MIMXRT1042 + select HAS_MCUX_CCM if !SOC_MIMXRT1042 + select HAS_MCUX_FLEXSPI + select HAS_MCUX_IGPIO + select HAS_MCUX_LPI2C if !SOC_MIMXRT1042 + select HAS_MCUX_LPSPI if !SOC_MIMXRT1042 + select HAS_MCUX_LPUART if !SOC_MIMXRT1042 + select HAS_MCUX_GPT if !SOC_MIMXRT1042 + select HAS_MCUX_TRNG if !SOC_MIMXRT1042 + select HAS_MCUX_EDMA + select HAS_MCUX_GPC + select HAS_MCUX_IOMUXC + select HAS_MCUX_PMU + select HAS_MCUX_DCDC + select HAS_MCUX_USB_EHCI + select HAS_SWO + +config SOC_MIMXRT1011 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select INIT_ENET_PLL + +config SOC_MIMXRT1015 + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ENET_PLL + +config SOC_MIMXRT1021 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ENET_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_FLEXCAN + select HAS_MCUX_PWM + +config SOC_MIMXRT1024 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ENET_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_FLEXCAN + select HAS_MCUX_SRC + +config SOC_MIMXRT1042 + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + +config SOC_MIMXRT1051 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + +config SOC_MIMXRT1052 + select HAS_MCUX_ELCDIF + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + select HAS_MCUX_PWM + select HAS_MCUX_SRC + select HAS_MCUX_XBARA + +config SOC_MIMXRT1061 + select HAS_MCUX_ENET + select HAS_MCUX_SEMC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + +config SOC_MIMXRT1062 + select HAS_MCUX_ELCDIF + select HAS_MCUX_ENET + select HAS_MCUX_PWM + select HAS_MCUX_QTMR + select HAS_MCUX_SEMC + select HAS_MCUX_SNVS + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + select HAS_MCUX_I2S + select HAS_MCUX_ADC_ETC + select HAS_MCUX_SRC + select HAS_MCUX_XBARA + +config SOC_MIMXRT1064 + select HAS_MCUX_ELCDIF + select HAS_MCUX_ENET + select HAS_MCUX_PWM + select HAS_MCUX_QTMR + select HAS_MCUX_SEMC + select HAS_MCUX_SNVS + select HAS_MCUX_SRC + select CPU_HAS_FPU_DOUBLE_PRECISION + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_CSI + select HAS_MCUX_FLEXCAN + select HAS_SWO diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig new file mode 100644 index 00000000000000..b93d77ef77599e --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + + +if SOC_SERIES_IMXRT10XX + +config NUM_IRQS + default 80 if SOC_MIMXRT1011 + default 142 if SOC_MIMXRT1015 || \ + SOC_MIMXRT1021 || \ + SOC_MIMXRT1024 + default 157 if SOC_MIMXRT1042 + default 160 if SOC_MIMXRT1052 || \ + SOC_MIMXRT1062 || \ + SOC_MIMXRT1064 + +config DCDC_VALUE + default 0x12 if SOC_MIMXRT1011 || \ + SOC_MIMXRT1015 || \ + SOC_MIMXRT1021 || \ + SOC_MIMXRT1024 + default 0x13 + +config GPIO + default y + + +endif # SOC_SERIES_IMXRT10XX diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig.soc b/soc/nxp/imxrt/imxrt10xx/Kconfig.soc new file mode 100644 index 00000000000000..4aa203c79f5bc2 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/Kconfig.soc @@ -0,0 +1,238 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT10XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_SERIES + default "imxrt10xx" if SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1011 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1015 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1021 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1024 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1042 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1051 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1052 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1061 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1062 + bool + select SOC_SERIES_IMXRT10XX + +config SOC_MIMXRT1064 + bool + select SOC_SERIES_IMXRT10XX + +config SOC + default "mimxrt1011" if SOC_MIMXRT1011 + default "mimxrt1015" if SOC_MIMXRT1015 + default "mimxrt1021" if SOC_MIMXRT1021 + default "mimxrt1024" if SOC_MIMXRT1024 + default "mimxrt1042" if SOC_MIMXRT1042 + default "mimxrt1051" if SOC_MIMXRT1051 + default "mimxrt1052" if SOC_MIMXRT1052 + default "mimxrt1061" if SOC_MIMXRT1061 + default "mimxrt1062" if SOC_MIMXRT1062 + default "mimxrt1064" if SOC_MIMXRT1064 + +config SOC_PART_NUMBER_MIMXRT1011CAE4A + bool + select SOC_MIMXRT1011 + +config SOC_PART_NUMBER_MIMXRT1011DAE5A + bool + select SOC_MIMXRT1011 + +config SOC_PART_NUMBER_MIMXRT1015CAF4A + bool + select SOC_MIMXRT1015 + +config SOC_PART_NUMBER_MIMXRT1015DAF5A + bool + select SOC_MIMXRT1015 + +config SOC_PART_NUMBER_MIMXRT1021CAF4A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1021CAG4A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1021DAF5A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1021DAG5A + bool + select SOC_MIMXRT1021 + +config SOC_PART_NUMBER_MIMXRT1024CAG4A + bool + select SOC_MIMXRT1024 + +config SOC_PART_NUMBER_MIMXRT1024DAG5A + bool + select SOC_MIMXRT1024 + +config SOC_PART_NUMBER_MIMXRT1041DFP6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1041DJM6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1041XFP5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1041XJM5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042DFP6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042DJM6B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042XFP5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1042XJM5B + bool + select SOC_MIMXRT1042 + +config SOC_PART_NUMBER_MIMXRT1051CVL5A + bool + select SOC_MIMXRT1051 + +config SOC_PART_NUMBER_MIMXRT1051DVL6A + bool + select SOC_MIMXRT1051 + +config SOC_PART_NUMBER_MIMXRT1052CVJ5B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052CVL5A + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052CVL5B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052DVJ6B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052DVL6A + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1052DVL6B + bool + select SOC_MIMXRT1052 + +config SOC_PART_NUMBER_MIMXRT1061CVL5A + bool + select SOC_MIMXRT1061 + +config SOC_PART_NUMBER_MIMXRT1061DVL6A + bool + select SOC_MIMXRT1061 + +config SOC_PART_NUMBER_MIMXRT1062CVJ5A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062CVJ5B + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062CVL5A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062DVJ6A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1062DVL6A + bool + select SOC_MIMXRT1062 + +config SOC_PART_NUMBER_MIMXRT1064CVL5A + bool + select SOC_MIMXRT1064 + +config SOC_PART_NUMBER_MIMXRT1064DVL6A + bool + select SOC_MIMXRT1064 + +config SOC_PART_NUMBER + default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A + default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A + default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A + default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A + default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A + default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A + default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A + default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A + default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A + default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A + default "MIMXRT1041DFP6B" if SOC_PART_NUMBER_MIMXRT1041DFP6B + default "MIMXRT1041DJM6B" if SOC_PART_NUMBER_MIMXRT1041DJM6B + default "MIMXRT1041XFP5B" if SOC_PART_NUMBER_MIMXRT1041XFP5B + default "MIMXRT1041XJM5B" if SOC_PART_NUMBER_MIMXRT1041XJM5B + default "MIMXRT1042DFP6B" if SOC_PART_NUMBER_MIMXRT1042DFP6B + default "MIMXRT1042DJM6B" if SOC_PART_NUMBER_MIMXRT1042DJM6B + default "MIMXRT1042XFP5B" if SOC_PART_NUMBER_MIMXRT1042XFP5B + default "MIMXRT1042XJM5B" if SOC_PART_NUMBER_MIMXRT1042XJM5B + default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A + default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A + default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B + default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A + default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B + default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B + default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A + default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B + default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A + default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A + default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A + default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B + default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A + default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A + default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A + default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A + default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A diff --git a/soc/arm/nxp_imx/rt/flexspi_rt10xx.c b/soc/nxp/imxrt/imxrt10xx/flexspi.c similarity index 100% rename from soc/arm/nxp_imx/rt/flexspi_rt10xx.c rename to soc/nxp/imxrt/imxrt10xx/flexspi.c diff --git a/soc/nxp/imxrt/imxrt10xx/linker.ld b/soc/nxp/imxrt/imxrt10xx/linker.ld new file mode 100644 index 00000000000000..a7e5123804cfd3 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/linker.ld @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) + +MEMORY + { + +#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) + SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) +#endif + + } + +#include diff --git a/soc/arm/nxp_imx/rt/lpm_rt1064.c b/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c similarity index 96% rename from soc/arm/nxp_imx/rt/lpm_rt1064.c rename to soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c index e4f76bb19bd596..42d1110b3cadb4 100644 --- a/soc/arm/nxp_imx/rt/lpm_rt1064.c +++ b/soc/nxp/imxrt/imxrt10xx/lpm_rt1064.c @@ -8,7 +8,7 @@ */ #include -#include +#include #include #include @@ -117,7 +117,7 @@ static void clock_init_usb1_pll(const clock_usb_pll_config_t *config) static void flexspi_enter_critical(void) { -#if CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) /* Wait for flexspi to be inactive, and gate the clock */ while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { @@ -126,7 +126,9 @@ static void flexspi_enter_critical(void) /* Disable clock gate of flexspi2. */ CCM->CCGR7 &= (~CCM_CCGR7_CG1_MASK); -#elif CONFIG_CODE_FLEXSPI +#endif + +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) /* Wait for flexspi to be inactive, and gate the clock */ while (!((FLEXSPI->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { @@ -140,7 +142,7 @@ static void flexspi_enter_critical(void) static void flexspi_exit_critical(void) { -#if CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) /* Enable clock gate of flexspi2. */ CCM->CCGR7 |= (CCM_CCGR7_CG1_MASK); @@ -151,7 +153,7 @@ static void flexspi_exit_critical(void) while (!((FLEXSPI2->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (FLEXSPI2->STS0 & FLEXSPI_STS0_SEQIDLE_MASK))) { } -#elif CONFIG_CODE_FLEXSPI +#elif DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) /* Enable clock of flexspi. */ CCM->CCGR6 |= CCM_CCGR6_CG5_MASK; @@ -209,10 +211,10 @@ void clock_full_power(void) #endif /* Set Flexspi divider before increasing frequency of PLL3 PDF0. */ -#if CONFIG_CODE_FLEXSPI +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_FlexspiDiv, flexspi_div); clock_set_mux(kCLOCK_FlexspiMux, 3); -#elif CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_Flexspi2Div, flexspi_div); clock_set_mux(kCLOCK_Flexspi2Mux, 1); #endif @@ -255,11 +257,11 @@ void clock_low_power(void) CCM_ANALOG->PLL_USB1_SET = CCM_ANALOG_PLL_USB1_ENABLE_MASK; CCM_ANALOG->PFD_480_CLR = CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK; /* Change flexspi to use PLL3 PFD0 with no divisor (24M flexspi clock) */ -#if CONFIG_CODE_FLEXSPI +#if DT_SAME_NODE(DT_NODELABEL(flexspi), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_FlexspiDiv, 0); /* FLEXSPI1 mux to PLL3 PFD0 BYPASS */ clock_set_mux(kCLOCK_FlexspiMux, 3); -#elif CONFIG_CODE_FLEXSPI2 +#if DT_SAME_NODE(DT_NODELABEL(flexspi2), DT_PARENT(DT_CHOSEN(flash))) clock_set_div(kCLOCK_Flexspi2Div, 0); /* FLEXSPI2 mux to PLL3 PFD0 BYPASS */ clock_set_mux(kCLOCK_Flexspi2Mux, 1); diff --git a/soc/arm/nxp_imx/rt/pinctrl_rt10xx.h b/soc/nxp/imxrt/imxrt10xx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt/pinctrl_rt10xx.h rename to soc/nxp/imxrt/imxrt10xx/pinctrl_soc.h diff --git a/soc/nxp/imxrt/imxrt10xx/power.c b/soc/nxp/imxrt/imxrt10xx/power.c new file mode 100644 index 00000000000000..fac3180c0db414 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/power.c @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + * + * Note: this file is linked to RAM. Any functions called while preparing for + * sleep mode must be defined within this file, or linked to RAM. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "power.h" + +LOG_MODULE_REGISTER(soc_power, CONFIG_SOC_LOG_LEVEL); + + +static struct clock_callbacks lpm_clock_hooks; + +/* + * Boards with RT10XX SOCs can register callbacks to set their clocks into + * normal/full speed mode, low speed mode, and low power mode. + * If callbacks are present, the low power subsystem will disable + * PLLs for power savings when entering low power states. + */ +void imxrt_clock_pm_callbacks_register(struct clock_callbacks *callbacks) +{ + /* If run callback is set, low power must be as well. */ + __ASSERT_NO_MSG(callbacks && callbacks->clock_set_run && callbacks->clock_set_low_power); + lpm_clock_hooks.clock_set_run = callbacks->clock_set_run; + lpm_clock_hooks.clock_set_low_power = callbacks->clock_set_low_power; + if (callbacks->clock_lpm_init) { + lpm_clock_hooks.clock_lpm_init = callbacks->clock_lpm_init; + } +} + +static void lpm_set_sleep_mode_config(clock_mode_t mode) +{ + uint32_t clpcr; + + /* Set GPC wakeup config to GPT timer interrupt */ + GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); + /* + * ERR050143: CCM: When improper low-power sequence is used, + * the SoC enters low power mode before the ARM core executes WFI. + * + * Software workaround: + * 1) Software should trigger IRQ #41 (GPR_IRQ) to be always pending + * by setting IOMUXC_GPR_GPR1_GINT. + * 2) Software should then unmask IRQ #41 in GPC before setting CCM + * Low-Power mode. + * 3) Software should mask IRQ #41 right after CCM Low-Power mode + * is set (set bits 0-1 of CCM_CLPCR). + */ + GPC_EnableIRQ(GPC, GPR_IRQ_IRQn); + clpcr = CCM->CLPCR & (~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)); + /* Note: if CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK is set, + * debugger will not connect in sleep mode + */ + /* Set clock control module to transfer system to idle mode */ + clpcr |= CCM_CLPCR_LPM(mode) | CCM_CLPCR_MASK_SCU_IDLE_MASK | + CCM_CLPCR_MASK_L2CC_IDLE_MASK | + CCM_CLPCR_STBY_COUNT_MASK | + CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK; +#ifndef CONFIG_SOC_MIMXRT1011 + /* RT1011 does not include handshake bits */ + clpcr |= CCM_CLPCR_BYPASS_LPM_HS0_MASK | CCM_CLPCR_BYPASS_LPM_HS1_MASK; +#endif + CCM->CLPCR = clpcr; + GPC_DisableIRQ(GPC, GPR_IRQ_IRQn); +} + +static void lpm_enter_soft_off_mode(void) +{ + /* Enable the SNVS RTC as a wakeup source from soft-off mode, in case an RTC alarm + * was set. + */ + GPC_EnableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_imx_snvs_rtc))); + SNVS->LPCR |= SNVS_LPCR_TOP_MASK; +} + +static void lpm_enter_sleep_mode(clock_mode_t mode) +{ + /* FIXME: When this function is entered the Kernel has disabled + * interrupts using BASEPRI register. This is incorrect as it prevents + * waking up from any interrupt which priority is not 0. Work around the + * issue and disable interrupts using PRIMASK register as recommended + * by ARM. + */ + + /* Set PRIMASK */ + __disable_irq(); + /* Set BASEPRI to 0 */ + irq_unlock(0); + barrier_dsync_fence_full(); + barrier_isync_fence_full(); + + if (mode == kCLOCK_ModeWait) { + /* Clear the SLEEPDEEP bit to go into sleep mode (WAIT) */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + } else { + /* Set the SLEEPDEEP bit to enable deep sleep mode (STOP) */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + } + /* WFI instruction will start entry into WAIT/STOP mode */ + __WFI(); + +} + +static void lpm_set_run_mode_config(void) +{ + /* Clear GPC wakeup source */ + GPC_DisableIRQ(GPC, DT_IRQN(DT_INST(0, nxp_gpt_hw_timer))); + CCM->CLPCR &= ~(CCM_CLPCR_LPM_MASK | CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK); +} + +/* Toggle the analog bandgap reference circuitry on and off */ +static void bandgap_set(bool on) +{ + if (on) { + /* Enable bandgap in PMU */ + PMU->MISC0_CLR = PMU_MISC0_REFTOP_PWD_MASK; + /* Wait for it to stabilize */ + while ((PMU->MISC0 & PMU_MISC0_REFTOP_VBGUP_MASK) == 0) { + + } + /* Disable low power bandgap */ + XTALOSC24M->LOWPWR_CTRL_CLR = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; + } else { + /* Disable bandgap in PMU and switch to low power one */ + XTALOSC24M->LOWPWR_CTRL_SET = XTALOSC24M_LOWPWR_CTRL_LPBG_SEL_MASK; + PMU->MISC0_SET = PMU_MISC0_REFTOP_PWD_MASK; + } +} + +/* Should only be used if core clocks have been reduced- drops SOC voltage */ +static void lpm_drop_voltage(void) +{ + /* Move to the internal RC oscillator, since we are using low power clocks */ + CLOCK_InitRcOsc24M(); + /* Switch to internal RC oscillator */ + CLOCK_SwitchOsc(kCLOCK_RcOsc); + CLOCK_DeinitExternalClk(); + /* + * Change to 1.075V SOC voltage. If you are experiencing issues with + * low power mode stability, try raising this voltage value. + */ + DCDC_AdjustRunTargetVoltage(DCDC, 0xB); + /* Enable 2.5 and 1.1V weak regulators */ + PMU_2P5EnableWeakRegulator(PMU, true); + PMU_1P1EnableWeakRegulator(PMU, true); + /* Disable normal regulators */ + PMU_2P5EnableOutput(PMU, false); + PMU_1P1EnableOutput(PMU, false); + /* Disable analog bandgap */ + bandgap_set(false); +} + +/* Undo the changes made by lpm_drop_voltage so clocks can be raised */ +static void lpm_raise_voltage(void) +{ + /* Enable analog bandgap */ + bandgap_set(true); + /* Enable regulator LDOs */ + PMU_2P5EnableOutput(PMU, true); + PMU_1P1EnableOutput(PMU, true); + /* Disable weak LDOs */ + PMU_2P5EnableWeakRegulator(PMU, false); + PMU_1P1EnableWeakRegulator(PMU, false); + /* Change to 1.275V SOC voltage */ + DCDC_AdjustRunTargetVoltage(DCDC, 0x13); + /* Move to the external RC oscillator */ + CLOCK_InitExternalClk(0); + /* Switch clock source to external OSC. */ + CLOCK_SwitchOsc(kCLOCK_XtalOsc); +} + + +/* Sets device into low power mode */ +void pm_state_set(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + switch (state) { + case PM_STATE_RUNTIME_IDLE: + LOG_DBG("entering PM state runtime idle"); + lpm_set_sleep_mode_config(kCLOCK_ModeWait); + lpm_enter_sleep_mode(kCLOCK_ModeWait); + break; + case PM_STATE_SUSPEND_TO_IDLE: + LOG_DBG("entering PM state suspend to idle"); + if (lpm_clock_hooks.clock_set_low_power) { + /* Drop the SOC clocks to low power mode, and decrease core voltage */ + lpm_clock_hooks.clock_set_low_power(); + lpm_drop_voltage(); + } + lpm_set_sleep_mode_config(kCLOCK_ModeWait); + lpm_enter_sleep_mode(kCLOCK_ModeWait); + break; + case PM_STATE_SOFT_OFF: + LOG_DBG("Entering PM state soft off"); + lpm_enter_soft_off_mode(); + break; + default: + return; + } +} + +/* Handle SOC specific activity after Low Power Mode Exit */ +void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id) +{ + ARG_UNUSED(substate_id); + + /* Set run mode config after wakeup */ + switch (state) { + case PM_STATE_RUNTIME_IDLE: + lpm_set_run_mode_config(); + LOG_DBG("exited PM state runtime idle"); + break; + case PM_STATE_SUSPEND_TO_IDLE: + lpm_set_run_mode_config(); + if (lpm_clock_hooks.clock_set_run) { + /* Raise core voltage and restore SOC clocks */ + lpm_raise_voltage(); + lpm_clock_hooks.clock_set_run(); + } + LOG_DBG("exited PM state suspend to idle"); + break; + default: + break; + } + /* Clear PRIMASK after wakeup */ + __enable_irq(); +} + +/* Initialize power system */ +static int rt10xx_power_init(void) +{ + dcdc_internal_regulator_config_t reg_config; + + + /* Ensure clocks to ARM core memory will not be gated in low power mode + * if interrupt is pending + */ + CCM->CGPR |= CCM_CGPR_INT_MEM_CLK_LPM_MASK; + + if (lpm_clock_hooks.clock_lpm_init) { + lpm_clock_hooks.clock_lpm_init(); + } + + /* Errata ERR050143 */ + IOMUXC_GPR->GPR1 |= IOMUXC_GPR_GPR1_GINT_MASK; + + /* Configure DCDC */ + DCDC_BootIntoDCM(DCDC); + /* Set target voltage for low power mode to 0.925V*/ + DCDC_AdjustLowPowerTargetVoltage(DCDC, 0x1); + /* Reconfigure DCDC to disable internal load resistor */ + reg_config.enableLoadResistor = false; + reg_config.feedbackPoint = 0x1; /* 1.0V with 1.3V reference voltage */ + DCDC_SetInternalRegulatorConfig(DCDC, ®_config); + + /* Enable high gate drive on power FETs to reduce leakage current */ + PMU_CoreEnableIncreaseGateDrive(PMU, true); + + + return 0; +} + +SYS_INIT(rt10xx_power_init, PRE_KERNEL_2, 0); diff --git a/soc/arm/nxp_imx/rt/power_rt10xx.h b/soc/nxp/imxrt/imxrt10xx/power.h similarity index 100% rename from soc/arm/nxp_imx/rt/power_rt10xx.h rename to soc/nxp/imxrt/imxrt10xx/power.h diff --git a/soc/nxp/imxrt/imxrt10xx/soc.c b/soc/nxp/imxrt/imxrt10xx/soc.c new file mode 100644 index 00000000000000..0e4bae616a6af5 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/soc.c @@ -0,0 +1,344 @@ +/* + * Copyright 2017-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#include +#endif +#include +#include +#if CONFIG_USB_DC_NXP_EHCI +#include "usb_phy.h" +#include "usb.h" +#endif + +#include "memc_nxp_flexram.h" + +#include + +#define CCM_NODE DT_INST(0, nxp_imx_ccm) + +#define BUILD_ASSERT_PODF_IN_RANGE(podf, a, b) \ + BUILD_ASSERT(DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) >= (a) && \ + DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \ + #podf " is out of supported range (" #a ", " #b ")") + +#ifdef CONFIG_INIT_ARM_PLL +/* ARM PLL configuration for RUN mode */ +const clock_arm_pll_config_t armPllConfig = { + .loopDivider = 100U +}; +#endif + +#if CONFIG_USB_DC_NXP_EHCI +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +#ifdef CONFIG_INIT_ENET_PLL +/* ENET PLL configuration for RUN mode */ +const clock_enet_pll_config_t ethPllConfig = { +#if defined(CONFIG_SOC_MIMXRT1011) || \ + defined(CONFIG_SOC_MIMXRT1015) || \ + defined(CONFIG_SOC_MIMXRT1021) || \ + defined(CONFIG_SOC_MIMXRT1024) + .enableClkOutput500M = true, +#endif +#if defined(CONFIG_ETH_NXP_ENET) || defined(CONFIG_ETH_MCUX) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) + .enableClkOutput = true, +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) + .enableClkOutput1 = true, +#endif +#endif +#if defined(CONFIG_PTP_CLOCK_MCUX) + .enableClkOutput25M = true, +#else + .enableClkOutput25M = false, +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) + .loopDivider = 1, +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) + .loopDivider1 = 1, +#endif +}; +#endif + +#if CONFIG_USB_DC_NXP_EHCI + usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM, + }; +#endif + +#ifdef CONFIG_INIT_VIDEO_PLL +const clock_video_pll_config_t videoPllConfig = { + .loopDivider = 31, + .postDivider = 8, + .numerator = 0, + .denominator = 0, +}; +#endif + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +const __imx_boot_data_section BOOT_DATA_T boot_data = { +#ifdef CONFIG_XIP + .start = CONFIG_FLASH_BASE_ADDRESS, + .size = (uint32_t)&_flash_used, +#else + .start = CONFIG_SRAM_BASE_ADDRESS, + .size = (uint32_t)&_image_ram_size, +#endif + .plugin = PLUGIN_FLAG, + .placeholder = 0xFFFFFFFF, +}; + +const __imx_boot_ivt_section ivt image_vector_table = { + .hdr = IVT_HEADER, + .entry = (uint32_t) _vector_start, + .reserved1 = IVT_RSVD, +#ifdef CONFIG_DEVICE_CONFIGURATION_DATA + .dcd = (uint32_t) dcd_data, +#else + .dcd = (uint32_t) NULL, +#endif + .boot_data = (uint32_t) &boot_data, + .self = (uint32_t) &image_vector_table, + .csf = (uint32_t)CSF_ADDRESS, + .reserved2 = IVT_RSVD, +}; +#endif + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ + /* Boot ROM did initialize the XTAL, here we only sets external XTAL + * OSC freq + */ + CLOCK_SetXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, xtal), + clock_frequency)); + CLOCK_SetRtcXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, rtc_xtal), + clock_frequency)); + + /* Set PERIPH_CLK2 MUX to OSC */ + CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); + + /* Set PERIPH_CLK MUX to PERIPH_CLK2 */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); + + /* Setting the VDD_SOC value. + */ + DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE); + /* Waiting for DCDC_STS_DC_OK bit is asserted */ + while (DCDC_REG0_STS_DC_OK_MASK != + (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) { + ; + } + +#ifdef CONFIG_INIT_ARM_PLL + CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */ +#endif +#ifdef CONFIG_INIT_ENET_PLL + CLOCK_InitEnetPll(ðPllConfig); +#endif +#ifdef CONFIG_INIT_VIDEO_PLL + CLOCK_InitVideoPll(&videoPllConfig); +#endif + +#if DT_NODE_EXISTS(DT_CHILD(CCM_NODE, arm_podf)) + /* Set ARM PODF */ + BUILD_ASSERT_PODF_IN_RANGE(arm_podf, 1, 8); + CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1); +#endif + /* Set AHB PODF */ + BUILD_ASSERT_PODF_IN_RANGE(ahb_podf, 1, 8); + CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1); + /* Set IPG PODF */ + BUILD_ASSERT_PODF_IN_RANGE(ipg_podf, 1, 4); + CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1); + + /* Set PRE_PERIPH_CLK to PLL1, 1200M */ + CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); + + /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */ + CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); + +#ifdef CONFIG_UART_MCUX_LPUART + /* Configure UART divider to default */ + CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */ + CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */ +#endif + +#ifdef CONFIG_I2C_MCUX_LPI2C + CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */ + CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set I2C divider to 6 */ +#endif + +#ifdef CONFIG_SPI_MCUX_LPSPI + CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */ + CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */ +#endif + +#ifdef CONFIG_DISPLAY_MCUX_ELCDIF + /* MUX selects video PLL, which is initialized to 93MHz */ + CLOCK_SetMux(kCLOCK_LcdifPreMux, 2); + /* Divide output by 2 */ + CLOCK_SetDiv(kCLOCK_LcdifDiv, 1); + /* Set final div based on LCDIF clock-frequency */ + CLOCK_SetDiv(kCLOCK_LcdifPreDiv, + ((CLOCK_GetPllFreq(kCLOCK_PllVideo) / 2) / + DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), + clock_frequency)) - 1); +#endif + + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET +#if CONFIG_ETH_MCUX_RMII_EXT_CLK + /* Enable clock input for ENET1 */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false); +#else + /* Enable clock output for ENET1 */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); +#endif +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) && CONFIG_NET_L2_ETHERNET + /* Set ENET2 ref clock to be generated by External OSC,*/ + /* direction as output and frequency to 50MHz */ + IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir | + kIOMUXC_GPR_ENET2RefClkMode, true); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC + /* Configure USDHC clock source and divider */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); + CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U); + CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U); + CLOCK_EnableClock(kCLOCK_Usdhc1); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC + /* Configure USDHC clock source and divider */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U); + CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1U); + CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U); + CLOCK_EnableClock(kCLOCK_Usdhc2); +#endif + +#ifdef CONFIG_VIDEO_MCUX_CSI + CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */ + CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */ + CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Set CSI source to OSC 24M */ +#endif +#ifdef CONFIG_CAN_MCUX_FLEXCAN + CLOCK_SetDiv(kCLOCK_CanDiv, 1); /* Set CAN_CLK_PODF. */ + CLOCK_SetMux(kCLOCK_CanMux, 2); /* Set Can clock source. */ +#endif + +#ifdef CONFIG_LOG_BACKEND_SWO + /* Enable ARM trace clock to enable SWO output */ + CLOCK_EnableClock(kCLOCK_Trace); + /* Divide root clock output by 3 */ + CLOCK_SetDiv(kCLOCK_TraceDiv, 3); + /* Source clock from 528MHz system PLL */ + CLOCK_SetMux(kCLOCK_TraceMux, 0); +#endif + + /* Keep the system clock running so SYSTICK can wake up the system from + * wfi. + */ + CLOCK_SetMode(kCLOCK_ModeRun); + +} + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div) +{ + switch (clock_name) { + case IMX_CCM_SAI1_CLK: + CLOCK_SetMux(kCLOCK_Sai1Mux, clk_src); + CLOCK_SetDiv(kCLOCK_Sai1PreDiv, clk_pre_div); + CLOCK_SetDiv(kCLOCK_Sai1Div, clk_src_div); + break; + case IMX_CCM_SAI2_CLK: + CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); + CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); + break; + case IMX_CCM_SAI3_CLK: + CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src); + CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div); + CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div); + break; + default: + return; + } +} +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ + +static int imxrt_init(void) +{ + sys_cache_instr_enable(); + sys_cache_data_enable(); + + /* Initialize system clock */ + clock_init(); + + return 0; +} + +#ifdef CONFIG_PLATFORM_SPECIFIC_INIT +void z_arm_platform_init(void) +{ + /* Call CMSIS SystemInit */ + SystemInit(); + +#if defined(FLEXRAM_RUNTIME_BANKS_USED) + /* Configure flexram if not running from RAM */ + memc_flexram_dt_partition(); +#endif +} +#endif + +SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); diff --git a/soc/nxp/imxrt/imxrt10xx/soc.h b/soc/nxp/imxrt/imxrt10xx/soc.h new file mode 100644 index 00000000000000..88b344541793c3 --- /dev/null +++ b/soc/nxp/imxrt/imxrt10xx/soc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifndef _ASMLANGUAGE + +#include + +/* Add include for DTS generated information */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div); + +#endif + +#if CONFIG_MIPI_DSI +void imxrt_pre_init_display_interface(void); + +void imxrt_post_init_display_interface(void); +#endif + +void flexspi_clock_set_div(uint32_t value); +uint32_t flexspi_clock_get_freq(void); + +#ifdef CONFIG_MEMC +uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/imxrt/imxrt11xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt11xx/CMakeLists.txt new file mode 100644 index 00000000000000..49636be86e6317 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) +zephyr_sources_ifdef(CONFIG_PM power.c) + +zephyr_include_directories(.) + +if(CONFIG_MEMC_MCUX_FLEXSPI) + zephyr_sources(flexspi.c) + if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flexspi.c LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT) + endif() +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig new file mode 100644 index 00000000000000..064c28ea238067 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig @@ -0,0 +1,75 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT11XX + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select CPU_CORTEX_M_HAS_DWT + select PLATFORM_SPECIFIC_INIT + select ARM + select CLOCK_CONTROL + select HAS_MCUX_CACHE + select HAS_MCUX + select HAS_MCUX_SEMC + select HAS_MCUX_CCM_REV2 + select HAS_MCUX_IGPIO + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_LPADC + select HAS_MCUX_LPUART + select HAS_MCUX_ELCDIF + select HAS_MCUX_MIPI_DSI + select HAS_MCUX_GPT + select HAS_MCUX_FLEXSPI + select HAS_MCUX_FLEXCAN + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER + select INIT_VIDEO_PLL + select HAS_MCUX_EDMA + select CPU_HAS_ICACHE if CPU_CORTEX_M7 + select CPU_HAS_DCACHE if CPU_CORTEX_M7 + select CPU_HAS_FPU + select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 + select BYPASS_LDO_LPSR + select ADJUST_LDO + select HAS_MCUX_PWM + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_ENET + select HAS_MCUX_GPC + select HAS_MCUX_I2S + select HAS_MCUX_USB_EHCI + select HAS_MCUX_ACMP + select HAS_MCUX_SRC_V2 + select HAS_MCUX_IOMUXC + select HAS_MCUX_XBARA + select HAS_SWO + +config SOC_MIMXRT1176_CM4 + select CPU_CORTEX_M4 + +config SOC_MIMXRT1176_CM7 + select CPU_CORTEX_M7 + +config SOC_MIMXRT1166_CM4 + select CPU_CORTEX_M4 + +config SOC_MIMXRT1166_CM7 + select CPU_CORTEX_M7 + +if SOC_SERIES_IMXRT11XX + +config MCUX_CORE_SUFFIX + default "_cm7" if SOC_MIMXRT1176_CM7 || SOC_MIMXRT1166_CM7 + default "_cm4" if SOC_MIMXRT1176_CM4 || SOC_MIMXRT1166_CM4 + +config BYPASS_LDO_LPSR + bool "Bypass LDO lpsr" + +config ADJUST_LDO + bool "Adjust LDO setting" + +config ADJUST_DCDC + bool "Adjust internal DCDC output" + +endif # SOC_SERIES_IMXRT11XX diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig new file mode 100644 index 00000000000000..b66e4ff851c820 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig.defconfig @@ -0,0 +1,35 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMXRT11XX + +config NUM_IRQS + default 218 + +config GPIO + default y + +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 996000000 if SOC_MIMXRT1176_CM7 + default 600000000 if SOC_MIMXRT1166_CM7 + default 400000000 if SOC_MIMXRT1176_CM4 + default 240000000 if SOC_MIMXRT1166_CM4 + +endif # CORTEX_M_SYSTICK + +config DCDC_VALUE + default 0x13 + +config FLEXSPI_CONFIG_BLOCK_OFFSET + default 0x400 if BOOT_FLEXSPI_NOR + +if SECOND_CORE_MCUX + +# RT Boot header is only needed on primary core +config NXP_IMXRT_BOOT_HEADER + depends on CPU_CORTEX_M7 + +endif +endif diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig.soc b/soc/nxp/imxrt/imxrt11xx/Kconfig.soc new file mode 100644 index 00000000000000..1ae193120fdeb1 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/Kconfig.soc @@ -0,0 +1,95 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT11XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_SERIES + default "imxrt11xx" if SOC_SERIES_IMXRT11XX + +config SOC_MIMXRT1166 + bool + select SOC_SERIES_IMXRT11XX + +config SOC_MIMXRT1176 + bool + select SOC_SERIES_IMXRT11XX + +config SOC_MIMXRT1166_CM4 + bool + select SOC_MIMXRT1166 + +config SOC_MIMXRT1166_CM7 + bool + select SOC_MIMXRT1166 + +config SOC_MIMXRT1176_CM4 + bool + select SOC_MIMXRT1176 + +config SOC_MIMXRT1176_CM7 + bool + select SOC_MIMXRT1176 + +config SOC + default "mimxrt1166" if SOC_MIMXRT1166 + default "mimxrt1176" if SOC_MIMXRT1176 + +config SOC_PART_NUMBER_MIMXRT1166DVM6A + bool + +config SOC_PART_NUMBER_MIMXRT1176AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1176CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1176DVMAA + bool + +config SOC_PART_NUMBER_MIMXRT1175AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1175CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1175DVMAA + bool + +config SOC_PART_NUMBER_MIMXRT1173CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1172AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1172CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1172DVMAA + bool + +config SOC_PART_NUMBER_MIMXRT1171AVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1171CVM8A + bool + +config SOC_PART_NUMBER_MIMXRT1171DVMAA + bool + +config SOC_PART_NUMBER + default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A + default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A + default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA + default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A + default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A + default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A + default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA + default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A + default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A + default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A + default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA + default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A + default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A + default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA diff --git a/soc/arm/nxp_imx/rt/flexspi_rt11xx.c b/soc/nxp/imxrt/imxrt11xx/flexspi.c similarity index 100% rename from soc/arm/nxp_imx/rt/flexspi_rt11xx.c rename to soc/nxp/imxrt/imxrt11xx/flexspi.c diff --git a/soc/nxp/imxrt/imxrt11xx/linker.ld b/soc/nxp/imxrt/imxrt11xx/linker.ld new file mode 100644 index 00000000000000..a7e5123804cfd3 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/linker.ld @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014 Wind River Systems, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + + +#define IS_CHOSEN_SRAM(x) (DT_DEP_ORD(DT_NODELABEL(x)) == DT_DEP_ORD(DT_CHOSEN(zephyr_sram))) + +MEMORY + { + +#if (DT_REG_SIZE(DT_NODELABEL(sdram0)) > 0) && !IS_CHOSEN_SRAM(sdram0) + SDRAM (wx) : ORIGIN = DT_REG_ADDR(DT_NODELABEL(sdram0)), LENGTH = DT_REG_SIZE(DT_NODELABEL(sdram0)) +#endif + + } + +#include diff --git a/soc/arm/nxp_imx/rt/pinctrl_rt11xx.h b/soc/nxp/imxrt/imxrt11xx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt/pinctrl_rt11xx.h rename to soc/nxp/imxrt/imxrt11xx/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/rt/power_rt11xx.c b/soc/nxp/imxrt/imxrt11xx/power.c similarity index 100% rename from soc/arm/nxp_imx/rt/power_rt11xx.c rename to soc/nxp/imxrt/imxrt11xx/power.c diff --git a/soc/arm/nxp_imx/rt/power_rt11xx.h b/soc/nxp/imxrt/imxrt11xx/power.h similarity index 100% rename from soc/arm/nxp_imx/rt/power_rt11xx.h rename to soc/nxp/imxrt/imxrt11xx/power.h diff --git a/soc/nxp/imxrt/imxrt11xx/soc.c b/soc/nxp/imxrt/imxrt11xx/soc.c new file mode 100644 index 00000000000000..065039f38a2b8c --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/soc.c @@ -0,0 +1,728 @@ +/* + * Copyright 2021-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +#include +#endif +#include +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) +#include +/* Memcpy macro to copy segments from secondary core image stored in flash + * to RAM section that secondary core boots from. + * n is the segment number, as defined in zephyr_image_info.h + */ +#define MEMCPY_SEGMENT(n, _) \ + memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \ + (uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n), \ + (SEGMENT_SIZE_ ## n)) +#endif +#if CONFIG_USB_DC_NXP_EHCI +#include "usb_phy.h" +#include "usb.h" +#endif +#include "memc_nxp_flexram.h" + +#include + +#define DUAL_CORE_MU_ENABLED \ + (CONFIG_SECOND_CORE_MCUX && CONFIG_IPM && CONFIG_IPM_IMX) + +#if DUAL_CORE_MU_ENABLED +/* Dual core mode is enabled, and messaging unit is present */ +#include +#define BOOT_FLAG 0x1U +#define MU_BASE (MU_Type *)DT_REG_ADDR(DT_INST(0, nxp_imx_mu)) +#endif + +#if CONFIG_USB_DC_NXP_EHCI /* USB PHY configuration */ +#define BOARD_USB_PHY_D_CAL (0x07U) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +#ifdef CONFIG_INIT_ARM_PLL +static const clock_arm_pll_config_t armPllConfig = { +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) + /* resulting frequency: 24 * (166/(2* 2)) = 984MHz */ + /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .postDivider = kCLOCK_PllPostDiv2, + /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + .loopDivider = 166, +#elif defined(CONFIG_SOC_MIMXRT1166_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM7) + /* resulting frequency: 24 * (200/(2 * 4)) = 600MHz */ + /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .postDivider = kCLOCK_PllPostDiv4, + /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + .loopDivider = 200, +#else + #error "Unknown SOC, no pll configuration defined" +#endif +}; +#endif + +static const clock_sys_pll2_config_t sysPll2Config = { + /* Denominator of spread spectrum */ + .mfd = 268435455, + /* Spread spectrum parameter */ + .ss = NULL, + /* Enable spread spectrum or not */ + .ssEnable = false, +}; + +#ifdef CONFIG_INIT_ENET_PLL +static const clock_sys_pll1_config_t sysPll1Config = { + .pllDiv2En = true, +}; +#endif + +#ifdef CONFIG_INIT_VIDEO_PLL +static const clock_video_pll_config_t videoPllConfig = { + /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ + .loopDivider = 41, + /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ + .postDivider = 0, + /* + * 30 bit numerator of fractional loop divider, + * Fout = Fin * ( loopDivider + numerator / denominator ) + */ + .numerator = 1, + /* + * 30 bit denominator of fractional loop divider, + * Fout = Fin * ( loopDivider + numerator / denominator ) + */ + .denominator = 960000, + /* Spread spectrum parameter */ + .ss = NULL, + /* Enable spread spectrum or not */ + .ssEnable = false, +}; +#endif + +#if CONFIG_USB_DC_NXP_EHCI + usb_phy_config_struct_t usbPhyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; +#endif + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +const __imx_boot_data_section BOOT_DATA_T boot_data = { +#ifdef CONFIG_XIP + .start = CONFIG_FLASH_BASE_ADDRESS, + .size = (uint32_t)&_flash_used, +#else + .start = CONFIG_SRAM_BASE_ADDRESS, + .size = (uint32_t)&_image_ram_size, +#endif + .plugin = PLUGIN_FLAG, + .placeholder = 0xFFFFFFFF, +}; + +extern char __start[]; +const __imx_boot_ivt_section ivt image_vector_table = { + .hdr = IVT_HEADER, + .entry = (uint32_t) __start, + .reserved1 = IVT_RSVD, +#ifdef CONFIG_DEVICE_CONFIGURATION_DATA + .dcd = (uint32_t) dcd_data, +#else + .dcd = (uint32_t) NULL, +#endif + .boot_data = (uint32_t) &boot_data, + .self = (uint32_t) &image_vector_table, + .csf = (uint32_t)CSF_ADDRESS, + .reserved2 = IVT_RSVD, +}; +#endif + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ + clock_root_config_t rootCfg = {0}; + +#if CONFIG_ADJUST_DCDC + DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); +#endif + +/* RT1160 does not have Forward Body Biasing on the CM7 core */ +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) + /* Check if FBB need to be enabled in OverDrive(OD) mode */ + if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); + } else { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); + } +#endif + +#if CONFIG_BYPASS_LDO_LPSR + PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); + PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); +#endif + +#if CONFIG_ADJUST_LDO + pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig; + pmu_static_lpsr_dig_config_t lpsrDigConfig; + + if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & + ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL) { + PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig); + PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig); + } + + if ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & + ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL) { + PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig); + lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V; + PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig); + } +#endif + + /* PLL LDO shall be enabled first before enable PLLs */ + + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); + + /* Init OSC RC 16M */ + ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; + + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + CLOCK_OSC_GateOscRc400M(true); + + /* Init OSC RC 48M */ + CLOCK_OSC_EnableOsc48M(true); + CLOCK_OSC_EnableOsc48MDiv2(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | + ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | + ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | + ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | + ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { + } + + rootCfg.div = 1; + +#ifdef CONFIG_CPU_CORTEX_M7 + /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); + + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + +#if CONFIG_CPU_CORTEX_M4 + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); + + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#endif + + /* + * If DCD is used, please make sure the clock source of SEMC is not + * changed in the following PLL/PFD configuration code. + */ + +#ifdef CONFIG_INIT_ARM_PLL + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig); +#endif + +#ifdef CONFIG_INIT_ENET_PLL + CLOCK_InitSysPll1(&sysPll1Config); +#else + /* Bypass Sys Pll1. */ + CLOCK_SetPllBypass(kCLOCK_PllSys1, true); + + /* DeInit Sys Pll1. */ + CLOCK_DeinitSysPll1(); +#endif + + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config); + + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); + + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + + /* Init System Pll2 pfd3. */ +#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 24); +#else + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); +#endif + + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); + + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); + + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); + + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); + + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); + +#ifdef CONFIG_INIT_VIDEO_PLL + /* Init Video Pll. */ + CLOCK_InitVideoPll(&videoPllConfig); +#endif + + /* Module clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + +#if defined(CONFIG_SOC_MIMXRT1166_CM4) + /* Configure M4 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1176_CM4) + /* Configure M4 using SYS_PLL3_CLK_PFD3_CLK */ + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#endif + + /* Configure BUS using SYS_PLL3_CLK */ +#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET + /* Configure root bus clock at 198M */ + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + /* Keep root bus clock at default 240M */ + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); +#endif + + /* Configure BUS_LPSR using SYS_PLL3_CLK */ +#if defined(CONFIG_SOC_MIMXRT1176_CM4) + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; + rootCfg.div = 3; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1166_CM4) + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#endif + + /* Configure CSSYS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); + + /* Configure CSTRACE using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out; + rootCfg.div = 4; + CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); + + /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4) + rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + +#ifdef CONFIG_UART_MCUX_LPUART + /* Configure Lpuart1 using SysPll2*/ + rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); + + /* Configure Lpuart2 using SysPll2*/ + rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); +#endif + +#ifdef CONFIG_I2C_MCUX_LPI2C + /* Configure Lpi2c1 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); + + /* Configure Lpi2c5 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); +#endif + + +#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) + /* 50 MHz ENET clock */ + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); +#if CONFIG_ETH_MCUX_RMII_EXT_CLK + /* Set ENET_REF_CLK as an input driven by PHY */ + IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U); + IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U); +#else + /* Set ENET_REF_CLK as an output driven by ENET1_CLK_ROOT */ + IOMUXC_GPR->GPR4 |= (IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U) | + IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U)); +#endif +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet1g), okay) + /* + * 50 MHz clock for 10/100Mbit RMII PHY - + * operate ENET1G just like ENET peripheral + */ + rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2; + rootCfg.div = 10; + CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); +#if CONFIG_ETH_MCUX_RMII_EXT_CLK + /* Set ENET1G_REF_CLK as an input driven by PHY */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U); + IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U); +#else + /* Set ENET1G_REF_CLK as an output driven by ENET2_CLK_ROOT */ + IOMUXC_GPR->GPR5 |= (IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U) | + IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U)); +#endif +#endif +#endif + +#ifdef CONFIG_PTP_CLOCK_MCUX + /* 24MHz PTP clock */ + rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); +#endif + +#ifdef CONFIG_SPI_MCUX_LPSPI + /* Configure lpspi using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); +#endif + +#ifdef CONFIG_CAN_MCUX_FLEXCAN +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay) + /* Configure CAN1 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); +#endif +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan3), okay) + /* Configure CAN1 using Osc48MDiv2 */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); +#endif +#endif + +#ifdef CONFIG_MCUX_ACMP +#if DT_NODE_HAS_STATUS(DT_NODELABEL(acmp1), okay) + /* Configure ACMP1 using Osc48MDiv2*/ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); +#endif +#endif + +#ifdef CONFIG_DISPLAY_MCUX_ELCDIF + rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out; + /* + * PLL2 is fixed at 528MHz. Use desired panel clock clock to + * calculate LCDIF clock. + */ + rootCfg.div = ((SYS_PLL2_FREQ / + DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), + clock_frequency)) + 1); + CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); +#endif + +#ifdef CONFIG_COUNTER_MCUX_GPT + rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI + CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, + DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency)); + USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig); +#endif + +#if CONFIG_IMX_USDHC +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) + /* Configure USDHC1 using SysPll2Pfd2*/ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + CLOCK_EnableClock(kCLOCK_Usdhc1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) + /* Configure USDHC2 using SysPll2Pfd2*/ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + CLOCK_EnableClock(kCLOCK_Usdhc2); +#endif +#endif + +#if !(DT_NODE_HAS_COMPAT(DT_CHOSEN(flash), nxp_imx_flexspi)) && \ + defined(CONFIG_MEMC_MCUX_FLEXSPI) && \ + DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay) + /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); +#endif + + /* Keep core clock ungated during WFI */ + CCM->GPR_PRIVATE1_SET = 0x1; + /* Keep the system clock running so SYSTICK can wake up the system from + * wfi. + */ + GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_0, kGPC_RunMode); + GPC_CM_SetNextCpuMode(GPC_CPU_MODE_CTRL_1, kGPC_RunMode); + GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_0, false); + GPC_CM_EnableCpuSleepHold(GPC_CPU_MODE_CTRL_1, false); + +#if !defined(CONFIG_PM) + /* Enable the AHB clock while the CM7 is sleeping to allow debug access + * to TCM + */ + IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK; +#endif +} + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div) +{ + ARG_UNUSED(clk_pre_div); + + switch (clock_name) { + case IMX_CCM_SAI1_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai1, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai1, clk_src_div); + break; + case IMX_CCM_SAI2_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai2, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai2, clk_src_div); + break; + case IMX_CCM_SAI3_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai3, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai3, clk_src_div); + break; + case IMX_CCM_SAI4_CLK: + CLOCK_SetRootClockMux(kCLOCK_Root_Sai4, clk_src); + CLOCK_SetRootClockDiv(kCLOCK_Root_Sai4, clk_src_div); + break; + default: + return; + } +} +#endif + +#if CONFIG_MIPI_DSI +void imxrt_pre_init_display_interface(void) +{ + /* elcdif output to MIPI DSI */ + CLOCK_EnableClock(kCLOCK_Video_Mux); + VIDEO_MUX->VID_MUX_CTRL.CLR = VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK; + + /* Power on and isolation off. */ + PGMC_BPC4->BPC_POWER_CTRL |= (PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK | + PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK); + + /* Assert MIPI reset. */ + IOMUXC_GPR->GPR62 &= ~(IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); + + /* setup clock */ + const clock_root_config_t mipiEscClockConfig = { + .clockOff = false, + .mux = 4, + .div = 11, + }; + + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &mipiEscClockConfig); + + /* TX esc clock */ + const clock_group_config_t mipiEscClockGroupConfig = { + .clockOff = false, + .resetDiv = 2, + .div0 = 2, + }; + + CLOCK_SetGroupConfig(kCLOCK_Group_MipiDsi, &mipiEscClockGroupConfig); + + const clock_root_config_t mipiDphyRefClockConfig = { + .clockOff = false, + .mux = 1, + .div = 1, + }; + + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &mipiDphyRefClockConfig); + + /* Deassert PCLK and ESC reset. */ + IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK); +} + +void imxrt_post_init_display_interface(void) +{ + /* deassert BYTE and DBI reset */ + IOMUXC_GPR->GPR62 |= (IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK | + IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK); +} + +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * If dual core operation is enabled, the second core image will be loaded to RAM + * + * @return 0 + */ + +static int imxrt_init(void) +{ +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) + /** + * Copy CM4 core from flash to memory. Note that depending on where the + * user decided to store CM4 code, this is likely going to read from the + * flexspi while using XIP. Provided we DO NOT WRITE TO THE FLEXSPI, + * this operation is safe. + * + * Note that this copy MUST occur before enabling the M7 caching to + * ensure the data is written directly to RAM (since the M4 core will use it) + */ + LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;)); + /* Set the boot address for the second core */ + uint32_t boot_address = (uint32_t)(DT_REG_ADDR(DT_CHOSEN(zephyr_cpu1_region))); + /* Set VTOR for the CM4 core */ + IOMUXC_LPSR_GPR->GPR0 = IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(boot_address >> 3u); + IOMUXC_LPSR_GPR->GPR1 = IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(boot_address >> 16u); +#endif + +#if DUAL_CORE_MU_ENABLED && CONFIG_CPU_CORTEX_M4 + /* Set boot flag in messaging unit to indicate boot to primary core */ + MU_SetFlags(MU_BASE, BOOT_FLAG); +#endif + + +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) + sys_cache_instr_enable(); + sys_cache_data_enable(); +#endif + + /* Initialize system clock */ + clock_init(); + + return 0; +} + +#ifdef CONFIG_PLATFORM_SPECIFIC_INIT +void z_arm_platform_init(void) +{ + SystemInit(); + +#if defined(FLEXRAM_RUNTIME_BANKS_USED) + /* Configure flexram if not running from RAM */ + memc_flexram_dt_partition(); +#endif +} +#endif + +SYS_INIT(imxrt_init, PRE_KERNEL_1, 0); + +#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M7) +/** + * @brief Kickoff secondary core. + * + * Kick the secondary core out of reset and wait for it to indicate boot. The + * core image was already copied to RAM (and the boot address was set) in + * imxrt_init() + * + * @return 0 + */ +static int second_core_boot(void) +{ + /* Kick CM4 core out of reset */ + SRC->CTRL_M4CORE = SRC_CTRL_M4CORE_SW_RESET_MASK; + SRC->SCR |= SRC_SCR_BT_RELEASE_M4_MASK; +#if DUAL_CORE_MU_ENABLED + /* Wait for the secondary core to start up and set boot flag in + * imxrt_init + */ + while (MU_GetFlags(MU_BASE) != BOOT_FLAG) { + /* Wait for secondary core to set flag */ + } +#endif + return 0; +} + +SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); +#endif diff --git a/soc/nxp/imxrt/imxrt11xx/soc.h b/soc/nxp/imxrt/imxrt11xx/soc.h new file mode 100644 index 00000000000000..88b344541793c3 --- /dev/null +++ b/soc/nxp/imxrt/imxrt11xx/soc.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2017, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#include + +#ifndef _ASMLANGUAGE + +#include + +/* Add include for DTS generated information */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_I2S_MCUX_SAI +void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src, + uint32_t clk_pre_div, uint32_t clk_src_div); + +#endif + +#if CONFIG_MIPI_DSI +void imxrt_pre_init_display_interface(void); + +void imxrt_post_init_display_interface(void); +#endif + +void flexspi_clock_set_div(uint32_t value); +uint32_t flexspi_clock_get_freq(void); + +#ifdef CONFIG_MEMC +uint32_t flexspi_clock_set_freq(uint32_t clock_name, uint32_t rate); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/imxrt/imxrt5xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/CMakeLists.txt new file mode 100644 index 00000000000000..36e3874a8dcccf --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/CMakeLists.txt @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMXRT595S_CM33) + add_subdirectory(cm33) +elseif(CONFIG_SOC_MIMXRT595S_F1) + add_subdirectory(f1) +endif() diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig b/soc/nxp/imxrt/imxrt5xx/Kconfig new file mode 100644 index 00000000000000..75f695d5cc5de7 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/Kconfig @@ -0,0 +1,85 @@ +# Copyright 2024 NXP +# Copyright (c) 2023 Google LLC. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMXRT595S_CM33 + select CPU_CORTEX_M33 + select CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARM + select HAS_PM + select HAS_POWEROFF + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_FLEXSPI + select HAS_MCUX_CACHE + select HAS_MCUX_LPC_DMA + select HAS_MCUX_LPADC + select HAS_MCUX_OS_TIMER + select HAS_MCUX_LPC_RTC + select HAS_MCUX_TRNG + select HAS_MCUX_SCTIMER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select HAS_MCUX_USB_LPCIP3511 + select HAS_MCUX_CTIMER + +config SOC_MIMXRT595S_F1 + select XTENSA + select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") + select XTENSA_RESET_VECTOR + select XTENSA_USE_CORE_CRT1 + +if SOC_SERIES_IMXRT5XX + +if NXP_IMXRT_BOOT_HEADER + +config IMAGE_VECTOR_TABLE_OFFSET + default 0x1000 + +endif # NXP_IMXRT_BOOT_HEADER + +config IMXRT5XX_CODE_CACHE + bool "Code cache" + default y + help + Enable code cache for FlexSPI region at boot. If this Kconfig is + cleared, the CACHE64 controller will be disabled during SOC init + +choice FLEXCOMM0_CLK_SRC + prompt "Clock source for Flexcomm0" + default FLEXCOMM0_CLK_SRC_FRG + +config FLEXCOMM0_CLK_SRC_FRG + bool "FRG is source of Flexcomm0 clock" + +config FLEXCOMM0_CLK_SRC_FRO + bool "FRO_DIV4 is source of Flexcomm0 clock" + +endchoice + +choice MIPI_DPHY_CLK_SRC + prompt "Clock source for MIPI DPHY" + default MIPI_DPHY_CLK_SRC_AUX1_PLL + +config MIPI_DPHY_CLK_SRC_AUX1_PLL + bool "AUX1_PLL is source of MIPI_DPHY clock" + +config MIPI_DPHY_CLK_SRC_FRO + bool "FRO 192/96M is source of MIPI_DPHY clock" + +endchoice + +config MCUX_CORE_SUFFIX + default "_cm33" if SOC_MIMXRT595S_CM33 + default "_dsp" if SOC_MIMXRT595S_F1 + +endif # SOC_SERIES_IMXRT5XX diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig new file mode 100644 index 00000000000000..e99289a1320038 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig @@ -0,0 +1,119 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMXRT595S_CM33 + +config ROM_START_OFFSET + default 0x1200 if NXP_IMXRT_BOOT_HEADER + +# The PVT Sensor uses IRQ #75. For more details, see +# https://www.nxp.com/design/design-center/software/embedded-software/application-software-packs/application-software-pack-dynamic-voltage-scaling-using-pvt-sensor:APP-SW-PACK-DVS-PVT-SENSOR +config NUM_IRQS + default 76 + +config ZTEST_NO_YIELD + default y if (PM && ZTEST) + +# Code relocation is needed for flash clock setup +config CODE_DATA_RELOCATION_SRAM + default y + +# +# MBEDTLS is larger but much faster than TinyCrypt so choose wisely +# +config MBEDTLS +#config TINYCRYPT + default y if CSPRNG_ENABLED + depends on ENTROPY_GENERATOR + +if MBEDTLS +# +# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than +# what the ztest_thread_stack defaults to. +# +config TEST_EXTRA_STACK_SIZE + int + default 1024 +endif # MBEDTLS + +if MCUX_OS_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # MCUX_OS_TIMER + +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 250105263 + +endif # CORTEX_M_SYSTICK + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +if PM_DEVICE +# Enable the MEMC FlexSPI driver when using device power +# management so we can reconfigure the FlexSPI pins to +# save power. The MEMC FlexSPI driver is enabled when we +# enable the Flash subsystem, however we would like to +# reconfigure the FlexSPI pins even when the Flash driver +# is disabled, hence MEMC is selected when PM_DEVICE +# is turned on. +config MEMC + default y + select MEMC_MCUX_FLEXSPI + +endif + +endif # SOC_MIMXRT595S_CM33 + +if SOC_MIMXRT595S_F1 + +config SMP + default n + +config XTENSA_TIMER + default y + +config KERNEL_ENTRY + default "__start" + +config MULTI_LEVEL_INTERRUPTS + default n + +config 2ND_LEVEL_INTERRUPTS + default n + +# To prevent test uses TEST_LOGGING_MINIMAL +config TEST_LOGGING_DEFAULTS + default n + depends on TEST + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 198000000 + +config XTENSA_CCOUNT_HZ + default SYS_CLOCK_HW_CYCLES_PER_SEC + +config SYS_CLOCK_TICKS_PER_SEC + default 1000 + +config DYNAMIC_INTERRUPTS + default n + +config CACHE + default n + +config DCACHE + default n + +config CACHE_MANAGEMENT + default n + +config LOG + default n + +endif # SOC_MIMXRT595S_F1 diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig.soc b/soc/nxp/imxrt/imxrt5xx/Kconfig.soc new file mode 100644 index 00000000000000..6b2c58f57532e9 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/Kconfig.soc @@ -0,0 +1,60 @@ +# i.MX RT5XX Series + +# Copyright 2022-2024, NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT5XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_MIMXRT595S + bool + select SOC_SERIES_IMXRT5XX + +config SOC_MIMXRT595S_CM33 + bool + select SOC_MIMXRT595S + help + NXP RT5xx CM33 core + +config SOC_MIMXRT595S_F1 + bool + select SOC_MIMXRT595S + help + NXP RT5xx ADSP Series + +config SOC_SERIES + default "imxrt5xx" if SOC_SERIES_IMXRT5XX + +config SOC + default "mimxrt595s" if SOC_MIMXRT595S + +config SOC_TOOLCHAIN_NAME + string + default "nxp_rt500_adsp" if SOC_MIMXRT595S_F1 + +config SOC_PART_NUMBER_MIMXRT533SFFOC + bool + +config SOC_PART_NUMBER_MIMXRT555SFFOC + bool + +config SOC_PART_NUMBER_MIMXRT595SFFOC + bool + +config SOC_PART_NUMBER_MIMXRT533SFAWC + bool + +config SOC_PART_NUMBER_MIMXRT555SFAWC + bool + +config SOC_PART_NUMBER_MIMXRT595SFAWC + bool + +config SOC_PART_NUMBER + default "MIMXRT533SFAWC" if SOC_PART_NUMBER_MIMXRT533SFAWC + default "MIMXRT555SFAWC" if SOC_PART_NUMBER_MIMXRT555SFAWC + default "MIMXRT595SFAWC" if SOC_PART_NUMBER_MIMXRT595SFAWC + default "MIMXRT533SFFOC" if SOC_PART_NUMBER_MIMXRT533SFFOC + default "MIMXRT555SFFOC" if SOC_PART_NUMBER_MIMXRT555SFFOC + default "MIMXRT595SFFOC" if SOC_PART_NUMBER_MIMXRT595SFFOC diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt new file mode 100644 index 00000000000000..c47971c8ccc4ba --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt @@ -0,0 +1,29 @@ +# +# Copyright 2022,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) + +zephyr_include_directories(.) + +zephyr_sources( + soc.c + flash_clock_setup.c + ) + +zephyr_sources_ifdef(CONFIG_PM power.c) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/nxp_imx/rt5xx/flash_clock_setup.c b/soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.c similarity index 100% rename from soc/arm/nxp_imx/rt5xx/flash_clock_setup.c rename to soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.c diff --git a/soc/arm/nxp_imx/rt5xx/flash_clock_setup.h b/soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.h similarity index 100% rename from soc/arm/nxp_imx/rt5xx/flash_clock_setup.h rename to soc/nxp/imxrt/imxrt5xx/cm33/flash_clock_setup.h diff --git a/soc/arm/nxp_imx/rt5xx/linker.ld b/soc/nxp/imxrt/imxrt5xx/cm33/linker.ld similarity index 100% rename from soc/arm/nxp_imx/rt5xx/linker.ld rename to soc/nxp/imxrt/imxrt5xx/cm33/linker.ld diff --git a/soc/arm/nxp_imx/rt5xx/pinctrl_soc.h b/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt5xx/pinctrl_soc.h rename to soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/rt5xx/power.c b/soc/nxp/imxrt/imxrt5xx/cm33/power.c similarity index 100% rename from soc/arm/nxp_imx/rt5xx/power.c rename to soc/nxp/imxrt/imxrt5xx/cm33/power.c diff --git a/soc/arm/nxp_imx/rt5xx/poweroff.c b/soc/nxp/imxrt/imxrt5xx/cm33/poweroff.c similarity index 100% rename from soc/arm/nxp_imx/rt5xx/poweroff.c rename to soc/nxp/imxrt/imxrt5xx/cm33/poweroff.c diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/soc.c b/soc/nxp/imxrt/imxrt5xx/cm33/soc.c new file mode 100644 index 00000000000000..4b420ea46d483e --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/cm33/soc.c @@ -0,0 +1,544 @@ +/* + * Copyright 2022-2023, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for NXP RT5XX platform + * + * This module provides routines to initialize and support board-level + * hardware for the RT5XX platforms. + */ + +#include +#include +#include +#include +#include "fsl_power.h" +#include "fsl_clock.h" +#include + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP +#include "flash_clock_setup.h" +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 +#include "usb_phy.h" +#include "usb.h" +#endif + +/* Board System oscillator settling time in us */ +#define BOARD_SYSOSC_SETTLING_US 100U +/* Board xtal frequency in Hz */ +#define BOARD_XTAL_SYS_CLK_HZ 24000000U +/* Core clock frequency: 198000000Hz */ +#define CLOCK_INIT_CORE_CLOCK 198000000U + +#define CTIMER_CLOCK_SOURCE(node_id) \ + TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) +#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) +#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) +#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); + +const clock_sys_pll_config_t g_sysPllConfig_clock_init = { + /* OSC clock */ + .sys_pll_src = kCLOCK_SysPllXtalIn, + /* Numerator of the SYSPLL0 fractional loop divider is 0 */ + .numerator = 0, + /* Denominator of the SYSPLL0 fractional loop divider is 1 */ + .denominator = 1, + /* Divide by 22 */ + .sys_pll_mult = kCLOCK_SysPllMult22 +}; + +const clock_audio_pll_config_t g_audioPllConfig_clock_init = { + /* OSC clock */ + .audio_pll_src = kCLOCK_AudioPllXtalIn, + /* Numerator of the Audio PLL fractional loop divider is 0 */ + .numerator = 5040, + /* Denominator of the Audio PLL fractional loop divider is 1 */ + .denominator = 27000, + /* Divide by 22 */ + .audio_pll_mult = kCLOCK_AudioPllMult22 +}; + +const clock_frg_clk_config_t g_frg0Config_clock_init = { + .num = 0, + .sfg_clock_src = kCLOCK_FrgPllDiv, + .divider = 255U, + .mult = 0 +}; + +const clock_frg_clk_config_t g_frg12Config_clock_init = { + .num = 12, + .sfg_clock_src = kCLOCK_FrgMainClk, + .divider = 255U, + .mult = 167 +}; + +#if CONFIG_USB_DC_NXP_LPCIP3511 +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +/* System clock frequency. */ +extern uint32_t SystemCoreClock; +/* Main stack pointer */ +extern char z_main_stack[]; + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +extern char _flash_used[]; + +extern void z_arm_reset(void); +extern void z_arm_nmi(void); +extern void z_arm_hard_fault(void); +extern void z_arm_mpu_fault(void); +extern void z_arm_bus_fault(void); +extern void z_arm_usage_fault(void); +extern void z_arm_secure_fault(void); +extern void z_arm_svc(void); +extern void z_arm_debug_monitor(void); +extern void z_arm_pendsv(void); +extern void sys_clock_isr(void); +extern void z_arm_exc_spurious(void); + +__imx_boot_ivt_section void (* const image_vector_table[])(void) = { + (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ + z_arm_reset, /* 0x04 */ + z_arm_nmi, /* 0x08 */ + z_arm_hard_fault, /* 0x0C */ + z_arm_mpu_fault, /* 0x10 */ + z_arm_bus_fault, /* 0x14 */ + z_arm_usage_fault, /* 0x18 */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + z_arm_secure_fault, /* 0x1C */ +#else + z_arm_exc_spurious, +#endif /* CONFIG_ARM_SECURE_FIRMWARE */ + (void (*)())_flash_used, /* 0x20, imageLength. */ + 0, /* 0x24, imageType (Plain Image) */ + 0, /* 0x28, authBlockOffset/crcChecksum */ + z_arm_svc, /* 0x2C */ + z_arm_debug_monitor, /* 0x30 */ + (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ + z_arm_pendsv, /* 0x38 */ +#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ + defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) + sys_clock_isr, /* 0x3C */ +#else + z_arm_exc_spurious, +#endif +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ + +#if CONFIG_USB_DC_NXP_LPCIP3511 + +static void usb_device_clock_init(void) +{ + uint8_t usbClockDiv = 1; + uint32_t usbClockFreq; + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + /* Make sure USBHS ram buffer and usb1 phy has power up */ + POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); + POWER_ApplyPD(); + + RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); + + /* enable usb ip clock */ + CLOCK_EnableUsbHs0DeviceClock(kOSC_CLK_to_USB_CLK, usbClockDiv); + /* save usb ip clock freq*/ + usbClockFreq = g_xtalFreq / usbClockDiv; + CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4); + /* enable usb ram clock */ + CLOCK_EnableClock(kCLOCK_UsbhsSram); + /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ + CLOCK_EnableUsbHs0PhyPllClock(kOSC_CLK_to_USB_CLK, usbClockFreq); + + /* USB PHY initialization */ + USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL_SYS_CLK_HZ, &phyConfig); + +#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) + for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { + ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; + } +#endif + + /* The following code should run after phy initialization and should wait + * some microseconds to make sure utmi clock valid + */ + /* enable usb1 host clock */ + CLOCK_EnableClock(kCLOCK_UsbhsHost); + /* Wait until host_needclk de-asserts */ + while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) { + __ASM("nop"); + } + /* According to reference mannual, device mode setting has to be set by access + * usb host register + */ + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + /* disable usb1 host clock */ + CLOCK_DisableClock(kCLOCK_UsbhsHost); +} + +#endif + +void z_arm_platform_init(void) +{ +#ifndef CONFIG_NXP_IMXRT_BOOT_HEADER + /* + * If boot did not proceed using a boot header, we should not assume + * the core is in reset state. Disable the MPU and correctly + * set the stack pointer, since we are about to push to + * the stack when we call SystemInit + */ + /* Clear stack limit registers */ + __set_MSPLIM(0); + __set_PSPLIM(0); + /* Disable MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + /* Set stack pointer */ + __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); +#endif /* !CONFIG_NXP_IMXRT_BOOT_HEADER */ + /* This is provided by the SDK */ + SystemInit(); +} + +/* Weak so that board can override with their own clock init routine. */ +void __weak rt5xx_clock_init(void) +{ + /* Configure LPOSC 1M */ + /* Power on LPOSC (1MHz) */ + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + /* Wait until LPOSC stable */ + CLOCK_EnableLpOscClk(); + + /* Configure FRO clock source */ + /* Power on FRO (192MHz or 96MHz) */ + POWER_DisablePD(kPDRUNCFG_PD_FFRO); + /* FRO_DIV1 is always enabled and used as Main clock during PLL update. */ + /* Enable all FRO outputs */ + CLOCK_EnableFroClk(kCLOCK_FroAllOutEn); + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable + * clock source to avoid instruction/data fetch issue when updating PLL and Main + * clock if XIP(execute code on FLEXSPI memory). + */ + flexspi_clock_safe_config(); +#endif + + /* Let CPU run on FRO with divider 2 for safe switching. */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2); + CLOCK_AttachClk(kFRO_DIV1_to_MAIN_CLK); + + /* Configure SYSOSC clock source. */ + /* Power on SYSXTAL */ + POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); + /* Updated XTAL oscillator settling time */ + POWER_UpdateOscSettlingTime(BOARD_SYSOSC_SETTLING_US); + /* Enable system OSC */ + CLOCK_EnableSysOscClk(true, true, BOARD_SYSOSC_SETTLING_US); + /* Sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(BOARD_XTAL_SYS_CLK_HZ); + + /* Configure SysPLL0 clock source. */ + CLOCK_InitSysPll(&g_sysPllConfig_clock_init); + /* Enable MAIN PLL clock */ + CLOCK_InitSysPfd(kCLOCK_Pfd0, 24); + /* Enable AUX0 PLL clock */ + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); + + /* Configure Audio PLL clock source. */ + CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); + /* Enable Audio PLL clock */ + CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); + + /* Set SYSCPUAHBCLKDIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); + + /* Setup FRG0 clock */ + CLOCK_SetFRGClock(&g_frg0Config_clock_init); + /* Setup FRG12 clock */ + CLOCK_SetFRGClock(&g_frg12Config_clock_init); + + /* Set up clock selectors - Attach clocks to the peripheries. */ + /* Switch MAIN_CLK to MAIN_PLL */ + CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); + /* Switch SYSTICK_CLK to MAIN_CLK_DIV */ + CLOCK_AttachClk(kMAIN_CLK_DIV_to_SYSTICK_CLK); +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) + #ifdef CONFIG_FLEXCOMM0_CLK_SRC_FRG + /* Switch FLEXCOMM0 to FRG */ + CLOCK_AttachClk(kFRG_to_FLEXCOMM0); + #elif defined(CONFIG_FLEXCOMM0_CLK_SRC_FRO) + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM0); + #endif +#endif +#if CONFIG_USB_DC_NXP_LPCIP3511 + usb_device_clock_init(); +#endif + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay) && CONFIG_I2S) + /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay) && CONFIG_I2S) + /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_i2c, okay) + /* Switch FLEXCOMM4 to FRO_DIV4 */ + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM4); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay) + /* Attach main clock to I3C, divider will be set in i3c_mcux.c */ + CLOCK_AttachClk(kMAIN_CLK_to_I3C_CLK); + CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(hs_spi1), nxp_lpc_spi, okay) + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM16); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm12), nxp_lpc_usart, okay) + /* Switch FLEXCOMM12 to FRG */ + CLOCK_AttachClk(kFRG_to_FLEXCOMM12); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) + CLOCK_AttachClk(kFRO_DIV4_to_FLEXCOMM15); +#endif +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_dcnano_lcdif, okay) && CONFIG_DISPLAY + POWER_DisablePD(kPDRUNCFG_APD_DCNANO_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_DCNANO_SRAM); + POWER_ApplyPD(); + + CLOCK_AttachClk(kAUX0_PLL_to_DCPIXEL_CLK); + /* Note- pixel clock follows formula + * (height + VSW + VFP + VBP) * (width + HSW + HFP + HBP) * frame rate. + * this means the clock divider will vary depending on + * the attached display. + * + * The root clock used here is the AUX0 PLL (PLL0 PFD2). + */ + CLOCK_SetClkDiv(kCLOCK_DivDcPixelClk, + ((CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / + DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), + clock_frequency)) + 1)); + + CLOCK_EnableClock(kCLOCK_DisplayCtrl); + RESET_ClearPeripheralReset(kDISP_CTRL_RST_SHIFT_RSTn); + + CLOCK_EnableClock(kCLOCK_AxiSwitch); + RESET_ClearPeripheralReset(kAXI_SWITCH_RST_SHIFT_RSTn); +#if defined(CONFIG_MEMC) && DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), \ + nxp_imx_flexspi, okay) + /* Enable write-through for FlexSPI1 space */ + CACHE64_POLSEL0->REG1_TOP = 0x27FFFC00U; + CACHE64_POLSEL0->POLSEL = 0x11U; +#endif +#endif + + /* Switch CLKOUT to FRO_DIV2 */ + CLOCK_AttachClk(kFRO_DIV2_to_CLKOUT); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC + /* Make sure USDHC ram buffer has been power up*/ + POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + POWER_ApplyPD(); + + /* usdhc depend on 32K clock also */ + CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); + CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); + CLOCK_EnableClock(kCLOCK_Sdio0); + RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(smartdma), okay) && CONFIG_DMA_MCUX_SMARTDMA + /* Power up SMARTDMA ram */ + POWER_DisablePD(kPDRUNCFG_APD_SMARTDMA_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_SMARTDMA_SRAM); + POWER_ApplyPD(); + + RESET_ClearPeripheralReset(kSMART_DMA_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_Smartdma); +#endif + + DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) + + /* Set up dividers. */ + /* Set AUDIOPLLCLKDIV divider to value 15 */ + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); + /* Set FRGPLLCLKDIV divider to value 11 */ + CLOCK_SetClkDiv(kCLOCK_DivPLLFRGClk, 11U); + /* Set SYSTICKFCLKDIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 2U); + /* Set PFC0DIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); + /* Set PFC1DIV divider to value 4 */ + CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 4U); + /* Set CLKOUTFCLKDIV divider to value 100 */ + CLOCK_SetClkDiv(kCLOCK_DivClockOut, 100U); + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_setup_clock() to set user configured clock source/divider + * for FlexSPI. + */ + flexspi_setup_clock(FLEXSPI0, 0U, 2U); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexspi2), nxp_imx_flexspi, okay) + /* Power up FlexSPI1 SRAM */ + POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI1_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI1_SRAM); + POWER_ApplyPD(); + /* Setup clock frequency for FlexSPI1 */ + CLOCK_AttachClk(kMAIN_CLK_to_FLEXSPI1_CLK); + CLOCK_SetClkDiv(kCLOCK_DivFlexspi1Clk, 1); + /* Reset peripheral module */ + RESET_PeripheralReset(kFLEXSPI1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; + RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); + CLOCK_AttachClk(kFRO_DIV4_to_ADC_CLK); + CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1); +#endif + +#if CONFIG_COUNTER_NXP_MRT + RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(dmic0), nxp_dmic, okay) + /* Using the Audio PLL as input clock leads to better clock dividers + * for typical PCM sample rates ({8,16,24,32,48,96} kHz. + */ + /* DMIC source from audio pll, divider 8, 24.576M/8=3.072MHZ + * Select Audio PLL as clock source. This should produce a bit clock + * of 3.072MHZ + */ + CLOCK_AttachClk(kAUDIO_PLL_to_DMIC); + CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 8); + +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + + /* Set main clock to FRO as deep sleep clock by default. */ + POWER_SetDeepSleepClock(kDeepSleepClk_Fro); +} + +#if CONFIG_MIPI_DSI +/* Weak so board can override this function */ +void __weak imxrt_pre_init_display_interface(void) +{ + /* Assert MIPI DPHY reset. */ + RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); + POWER_DisablePD(kPDRUNCFG_APD_MIPIDSI_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_MIPIDSI_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_MIPIDSI); + POWER_ApplyPD(); + + /* RxClkEsc max 60MHz, TxClkEsc 12 to 20MHz. */ + CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHYESC_CLK); + /* RxClkEsc = 192MHz / 4 = 48MHz. */ + CLOCK_SetClkDiv(kCLOCK_DivDphyEscRxClk, 4); + /* TxClkEsc = 192MHz / 4 / 3 = 16MHz. */ + CLOCK_SetClkDiv(kCLOCK_DivDphyEscTxClk, 3); + + /* + * The DPHY bit clock must be fast enough to send out the pixels, + * it should be larger than: + * + * (Pixel clock * bit per output pixel) / number of MIPI data lane + * + * DPHY supports up to 895.1MHz bit clock. + * We set the divider of the PFD3 output of the SYSPLL, which has a + * fixed multiplied of 18, and use this output frequency for the DPHY. + */ + +#ifdef CONFIG_MIPI_DPHY_CLK_SRC_AUX1_PLL + /* Note: AUX1 PLL clock is system pll clock * 18 / pfd. + * system pll clock is configured at 528MHz by default. + */ + CLOCK_AttachClk(kAUX1_PLL_to_MIPI_DPHY_CLK); + CLOCK_InitSysPfd(kCLOCK_Pfd3, + ((CLOCK_GetSysPllFreq() * 18ull) / + ((unsigned long long)(DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))))); + CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1); +#elif defined(CONFIG_MIPI_DPHY_CLK_SRC_FRO) + CLOCK_AttachClk(kFRO_DIV1_to_MIPI_DPHY_CLK); + CLOCK_SetClkDiv(kCLOCK_DivDphyClk, + (CLK_FRO_CLK / DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock))); +#endif + /* Clear DSI control reset (Note that DPHY reset is cleared later)*/ + RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); +} + +void __weak imxrt_post_init_display_interface(void) +{ + /* Deassert MIPI DPHY reset. */ + RESET_ClearPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); +} + +void __weak imxrt_deinit_display_interface(void) +{ + /* Assert MIPI DPHY and DSI reset */ + RESET_SetPeripheralReset(kMIPI_DSI_PHY_RST_SHIFT_RSTn); + RESET_SetPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn); + /* Remove clock from DPHY */ + CLOCK_AttachClk(kNONE_to_MIPI_DPHY_CLK); +} + + +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ +static int nxp_rt500_init(void) +{ + /* Initialize clocks with tool generated code */ + rt5xx_clock_init(); + +#ifndef CONFIG_IMXRT5XX_CODE_CACHE + CACHE64_DisableCache(CACHE64_CTRL0); +#endif + + /* Some ROM versions may have errata leaving these pins in a non-reset state, + * which can often cause power leakage on most expected board designs, + * restore the reset state here and leave the pin configuration up to board/user DT + */ + IOPCTL->PIO[1][15] = 0; + IOPCTL->PIO[3][28] = 0; + IOPCTL->PIO[3][29] = 0; + + return 0; +} + +SYS_INIT(nxp_rt500_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt5xx/soc.h b/soc/nxp/imxrt/imxrt5xx/cm33/soc.h similarity index 100% rename from soc/arm/nxp_imx/rt5xx/soc.h rename to soc/nxp/imxrt/imxrt5xx/cm33/soc.h diff --git a/soc/arm/nxp_imx/rt5xx/usb.ld b/soc/nxp/imxrt/imxrt5xx/cm33/usb.ld similarity index 100% rename from soc/arm/nxp_imx/rt5xx/usb.ld rename to soc/nxp/imxrt/imxrt5xx/cm33/usb.ld diff --git a/soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt new file mode 100644 index 00000000000000..f54b5dd53a4071 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/CMakeLists.txt @@ -0,0 +1,23 @@ +# NXP RT SoC family CMake file +# +# Copyright (c) 2021 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_compile_definitions(CPU_MIMXRT595SFFOC_dsp) + +zephyr_include_directories(include) + +# west sign + +add_custom_target(zephyr.ri ALL + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri +) + +add_custom_command( + OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri + COMMENT "west sign --if-tool-available --tool rimage ..." + COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} + DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} +) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/nxp_adsp/rt5xx/include/_soc_inthandlers.h b/soc/nxp/imxrt/imxrt5xx/f1/include/_soc_inthandlers.h similarity index 100% rename from soc/xtensa/nxp_adsp/rt5xx/include/_soc_inthandlers.h rename to soc/nxp/imxrt/imxrt5xx/f1/include/_soc_inthandlers.h diff --git a/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/cache.h b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/cache.h new file mode 100644 index 00000000000000..067c08901403cf --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/cache.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __COMMON_ADSP_CACHE_H__ +#define __COMMON_ADSP_CACHE_H__ + +#include + +#endif diff --git a/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h new file mode 100644 index 00000000000000..3d1f0ed98d5a74 --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/include/adsp/io.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INCLUDE_IO__ +#define __INCLUDE_IO__ + +#include +#include +#include +#include + +static inline uint32_t io_reg_read(uint32_t reg) +{ + return sys_read32(reg); +} + +static inline void io_reg_write(uint32_t reg, uint32_t val) +{ + sys_write32(val, reg); +} + +static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, + uint32_t value) +{ + io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask)); +} + +static inline uint16_t io_reg_read16(uint32_t reg) +{ + return sys_read16(reg); +} + +static inline void io_reg_write16(uint32_t reg, uint16_t val) +{ + sys_write16(val, reg); +} + +#endif diff --git a/soc/nxp/imxrt/imxrt5xx/f1/include/soc.h b/soc/nxp/imxrt/imxrt5xx/f1/include/soc.h new file mode 100644 index 00000000000000..89ee9d96a5207b --- /dev/null +++ b/soc/nxp/imxrt/imxrt5xx/f1/include/soc.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2021 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include + +#include + +#ifndef __INC_IMX_SOC_H +#define __INC_IMX_SOC_H + +/* Macros related to interrupt handling */ +#define XTENSA_IRQ_NUM_SHIFT 0 +#define XTENSA_IRQ_NUM_MASK 0xff + +/* + * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00. + * + * 1. Peripheral Register bit offset. + */ +#define XTENSA_IRQ_NUMBER(_irq) \ + ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK) + +extern void z_soc_irq_enable(uint32_t irq); +extern void z_soc_irq_disable(uint32_t irq); +extern int z_soc_irq_is_enabled(unsigned int irq); + +#endif /* __INC_IMX_SOC_H */ diff --git a/soc/xtensa/nxp_adsp/rt5xx/include/soc/memory.h b/soc/nxp/imxrt/imxrt5xx/f1/include/soc/memory.h similarity index 100% rename from soc/xtensa/nxp_adsp/rt5xx/include/soc/memory.h rename to soc/nxp/imxrt/imxrt5xx/f1/include/soc/memory.h diff --git a/soc/xtensa/nxp_adsp/rt5xx/linker.ld b/soc/nxp/imxrt/imxrt5xx/f1/linker.ld similarity index 100% rename from soc/xtensa/nxp_adsp/rt5xx/linker.ld rename to soc/nxp/imxrt/imxrt5xx/f1/linker.ld diff --git a/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt new file mode 100644 index 00000000000000..7ed2c42c708c0c --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/CMakeLists.txt @@ -0,0 +1,26 @@ +# +# Copyright (c) 2020, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) + +zephyr_sources(soc.c) + +zephyr_sources_ifdef(CONFIG_PM power.c) + +zephyr_sources_ifdef(CONFIG_FLASH_MCUX_FLEXSPI_XIP flash_clock_setup.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) + +if(CONFIG_FLASH_MCUX_FLEXSPI_XIP) + zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig new file mode 100644 index 00000000000000..eeeb3ab7af43c1 --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig @@ -0,0 +1,65 @@ +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT6XX + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select CODE_DATA_RELOCATION_SRAM if FLASH_MCUX_FLEXSPI_XIP + select PLATFORM_SPECIFIC_INIT + select HAS_PM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_FLEXSPI + select HAS_MCUX_CACHE + select HAS_MCUX_LPC_DMA + select HAS_MCUX_LPADC + select HAS_MCUX_OS_TIMER + select HAS_MCUX_LPC_RTC + select HAS_MCUX_TRNG + select HAS_MCUX_SCTIMER + select HAS_MCUX_USDHC1 + select HAS_MCUX_USDHC2 + select INIT_SYS_PLL + select HAS_MCUX_USB_LPCIP3511 + select HAS_MCUX_CTIMER + +if SOC_SERIES_IMXRT6XX + +config MCUX_CORE_SUFFIX + default "_cm33" if SOC_MIMXRT685S_CM33 + +config INIT_SYS_PLL + bool "Initialize SYS PLL" + +config INIT_AUDIO_PLL + bool "Initialize Audio PLL" + +config XTAL_SYS_CLK_HZ + int "External oscillator frequency" + help + Set the external oscillator frequency in Hz. This should be set by the + board's defconfig. + +config SYSOSC_SETTLING_US + int "System oscillator settling time" + help + Set the board system oscillator settling time in us. This should be set by the + board's defconfig. + +config IMXRT6XX_CODE_CACHE + bool "Code cache" + default y + help + Enable code cache for FlexSPI region at boot. If this Kconfig is + cleared, the CACHE64 controller will be disabled during SOC init + +endif diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig new file mode 100644 index 00000000000000..2133577418dabc --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig @@ -0,0 +1,113 @@ +# i.MX RT6XX series configuration options + +# Copyright 2020, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_IMXRT6XX + +# alias for hal +config SOC_SERIES_IMX_RT6XX + bool + default y + +# another alias for hal +config SOC_SERIES_IMXRT_6XX + bool + default y + +config ROM_START_OFFSET + default 0x1200 if NXP_IMXRT_BOOT_HEADER + +config NUM_IRQS + default 60 + +config ZTEST_NO_YIELD + default y if (ZTEST && PM) + +# Setup LMA adjustment if using the RAMLOADER feature of ROM +FLASH_CHOSEN := zephyr,flash +FLASH_BASE := $(dt_chosen_reg_addr_hex,$(FLASH_CHOSEN)) +FLEXSPI_BASE := $(dt_node_reg_addr_hex,/soc/spi@134000,1) +config BUILD_OUTPUT_ADJUST_LMA + default "$(FLEXSPI_BASE) - $(FLASH_BASE)" if NXP_IMX_RT_ROM_RAMLOADER + +# The base address is determined from the zephyr,flash node with the following +# precedence: +# FlexSPI base address (if flash node is on a FlexSPI bus) +# node reg property (used for memory regions such as SRAM) + +# Workaround for not being able to have commas in macro arguments + +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_FLEXSPI := nxp,imx-flexspi + +# Macros to shorten Kconfig definitions +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI)) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +# The RT6xx has no internal flash. If the flash node has a size property, +# use that over the reg property. This is used for the external flash +# present on the board. Otherwise, fallback to the reg property +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \ + if $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +if FLASH_MCUX_FLEXSPI_XIP + +# Avoid RWW hazards by defaulting logging to disabled +choice FLASH_LOG_LEVEL_CHOICE + default FLASH_LOG_LEVEL_OFF +endchoice + +choice MEMC_LOG_LEVEL_CHOICE + default MEMC_LOG_LEVEL_OFF +endchoice + +endif + +# +# MBEDTLS is larger but much faster than TinyCrypt so choose wisely +# +config MBEDTLS +#config TINYCRYPT + default y if CSPRNG_ENABLED + depends on ENTROPY_GENERATOR + +if MBEDTLS +# +# MBEDTLS CTR_DRBG code path needs extra stack space for initialization than +# what the ztest_thread_stack defaults to. +# +config TEST_EXTRA_STACK_SIZE + int + default 1024 +endif # MBEDTLS + +config I2S_MCUX_FLEXCOMM + select INIT_AUDIO_PLL + +if MCUX_OS_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 1000000 + +endif # MCUX_OS_TIMER + +if CORTEX_M_SYSTICK + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 250105263 + +endif # CORTEX_M_SYSTICK + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +endif # SOC_SERIES_MIMXRT6XX diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.soc b/soc/nxp/imxrt/imxrt6xx/Kconfig.soc new file mode 100644 index 00000000000000..14cb945b36ec78 --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.soc @@ -0,0 +1,33 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT6XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_SERIES + default "imxrt6xx" if SOC_SERIES_IMXRT6XX + +config SOC_MIMXRT685S_CM33 + bool + select SOC_SERIES_IMXRT6XX + +config SOC + default "mimxrt685s" if SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER_MIMXRT685SFVKB + bool + select SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER_MIMXRT685SFFOB + bool + select SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER_MIMXRT685SFAWBR + bool + select SOC_MIMXRT685S_CM33 + +config SOC_PART_NUMBER + default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB + default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB + default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR diff --git a/soc/arm/nxp_imx/rt6xx/flash_clock_setup.c b/soc/nxp/imxrt/imxrt6xx/flash_clock_setup.c similarity index 100% rename from soc/arm/nxp_imx/rt6xx/flash_clock_setup.c rename to soc/nxp/imxrt/imxrt6xx/flash_clock_setup.c diff --git a/soc/arm/nxp_imx/rt6xx/flash_clock_setup.h b/soc/nxp/imxrt/imxrt6xx/flash_clock_setup.h similarity index 100% rename from soc/arm/nxp_imx/rt6xx/flash_clock_setup.h rename to soc/nxp/imxrt/imxrt6xx/flash_clock_setup.h diff --git a/soc/arm/nxp_imx/rt6xx/pinctrl_soc.h b/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_imx/rt6xx/pinctrl_soc.h rename to soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h diff --git a/soc/arm/nxp_imx/rt6xx/power.c b/soc/nxp/imxrt/imxrt6xx/power.c similarity index 100% rename from soc/arm/nxp_imx/rt6xx/power.c rename to soc/nxp/imxrt/imxrt6xx/power.c diff --git a/soc/nxp/imxrt/imxrt6xx/soc.c b/soc/nxp/imxrt/imxrt6xx/soc.c new file mode 100644 index 00000000000000..de658a285be9f6 --- /dev/null +++ b/soc/nxp/imxrt/imxrt6xx/soc.c @@ -0,0 +1,395 @@ +/* + * Copyright 2020-2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for nxp_lpc55s69 platform + * + * This module provides routines to initialize and support board-level + * hardware for the nxp_lpc55s69 platform. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP +#include "flash_clock_setup.h" +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 +#include "usb_phy.h" +#include "usb.h" +#endif + +/* Core clock frequency: 250105263Hz */ +#define CLOCK_INIT_CORE_CLOCK 250105263U + +#define SYSTEM_IS_XIP_FLEXSPI() \ + ((((uint32_t)nxp_rt600_init >= 0x08000000U) && \ + ((uint32_t)nxp_rt600_init < 0x10000000U)) || \ + (((uint32_t)nxp_rt600_init >= 0x18000000U) && \ + ((uint32_t)nxp_rt600_init < 0x20000000U))) + +#define CTIMER_CLOCK_SOURCE(node_id) \ + TO_CTIMER_CLOCK_SOURCE(DT_CLOCKS_CELL(node_id, name), DT_PROP(node_id, clk_source)) +#define TO_CTIMER_CLOCK_SOURCE(inst, val) TO_CLOCK_ATTACH_ID(inst, val) +#define TO_CLOCK_ATTACH_ID(inst, val) CLKCTL1_TUPLE_MUXA(CT32BIT##inst##FCLKSEL_OFFSET, val) +#define CTIMER_CLOCK_SETUP(node_id) CLOCK_AttachClk(CTIMER_CLOCK_SOURCE(node_id)); + +#ifdef CONFIG_INIT_SYS_PLL +const clock_sys_pll_config_t g_sysPllConfig = { + .sys_pll_src = kCLOCK_SysPllXtalIn, + .numerator = 0, + .denominator = 1, + .sys_pll_mult = kCLOCK_SysPllMult22 +}; +#endif + +#ifdef CONFIG_INIT_AUDIO_PLL +const clock_audio_pll_config_t g_audioPllConfig = { + .audio_pll_src = kCLOCK_AudioPllXtalIn, + .numerator = 5040, + .denominator = 27000, + .audio_pll_mult = kCLOCK_AudioPllMult22 +}; +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 +/* USB PHY condfiguration */ +#define BOARD_USB_PHY_D_CAL (0x0CU) +#define BOARD_USB_PHY_TXCAL45DP (0x06U) +#define BOARD_USB_PHY_TXCAL45DM (0x06U) +#endif + +/* System clock frequency. */ +extern uint32_t SystemCoreClock; +/* Main stack pointer */ +extern char z_main_stack[]; + +#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER +extern char _flash_used[]; +extern void z_arm_reset(void); +extern void z_arm_nmi(void); +extern void z_arm_hard_fault(void); +extern void z_arm_mpu_fault(void); +extern void z_arm_bus_fault(void); +extern void z_arm_usage_fault(void); +extern void z_arm_secure_fault(void); +extern void z_arm_svc(void); +extern void z_arm_debug_monitor(void); +extern void z_arm_pendsv(void); +extern void sys_clock_isr(void); +extern void z_arm_exc_spurious(void); + +__imx_boot_ivt_section void (* const image_vector_table[])(void) = { + (void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */ + z_arm_reset, /* 0x04 */ + z_arm_nmi, /* 0x08 */ + z_arm_hard_fault, /* 0x0C */ + z_arm_mpu_fault, /* 0x10 */ + z_arm_bus_fault, /* 0x14 */ + z_arm_usage_fault, /* 0x18 */ +#if defined(CONFIG_ARM_SECURE_FIRMWARE) + z_arm_secure_fault, /* 0x1C */ +#else + z_arm_exc_spurious, +#endif /* CONFIG_ARM_SECURE_FIRMWARE */ + (void (*)())_flash_used, /* 0x20, imageLength. */ + 0, /* 0x24, imageType (Plain Image) */ + 0, /* 0x28, authBlockOffset/crcChecksum */ + z_arm_svc, /* 0x2C */ + z_arm_debug_monitor, /* 0x30 */ + (void (*)())image_vector_table, /* 0x34, imageLoadAddress. */ + z_arm_pendsv, /* 0x38 */ +#if defined(CONFIG_SYS_CLOCK_EXISTS) && \ + defined(CONFIG_CORTEX_M_SYSTICK_INSTALL_ISR) + sys_clock_isr, /* 0x3C */ +#else + z_arm_exc_spurious, +#endif +}; +#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */ + +#if CONFIG_USB_DC_NXP_LPCIP3511 + +static void usb_device_clock_init(void) +{ + uint8_t usbClockDiv = 1; + uint32_t usbClockFreq; + usb_phy_config_struct_t phyConfig = { + BOARD_USB_PHY_D_CAL, + BOARD_USB_PHY_TXCAL45DP, + BOARD_USB_PHY_TXCAL45DM, + }; + + /* enable USB IP clock */ + CLOCK_SetClkDiv(kCLOCK_DivPfc1Clk, 5); + CLOCK_AttachClk(kXTALIN_CLK_to_USB_CLK); + CLOCK_SetClkDiv(kCLOCK_DivUsbHsFclk, usbClockDiv); + CLOCK_EnableUsbhsDeviceClock(); + RESET_PeripheralReset(kUSBHS_PHY_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_DEVICE_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_HOST_RST_SHIFT_RSTn); + RESET_PeripheralReset(kUSBHS_SRAM_RST_SHIFT_RSTn); + /*Make sure USBHS ram buffer has power up*/ + POWER_DisablePD(kPDRUNCFG_APD_USBHS_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USBHS_SRAM); + POWER_ApplyPD(); + + /* save usb ip clock freq*/ + usbClockFreq = g_xtalFreq / usbClockDiv; + /* enable USB PHY PLL clock, the phy bus clock (480MHz) source is same with USB IP */ + CLOCK_EnableUsbHs0PhyPllClock(kXTALIN_CLK_to_USB_CLK, usbClockFreq); + +#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM) + for (int i = 0; i < FSL_FEATURE_USBHSD_USB_RAM; i++) { + ((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS)[i] = 0x00U; + } +#endif + USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_XTAL_OSC_CLK, &phyConfig); + + /* the following code should run after phy initialization and + * should wait some microseconds to make sure utmi clock valid + */ + /* enable usb1 host clock */ + CLOCK_EnableClock(kCLOCK_UsbhsHost); + /* Wait until host_needclk de-asserts */ + while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) { + __ASM("nop"); + } + /* According to reference mannual, device mode setting has to be set by + * access usb host register + */ + USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK; + /* disable usb1 host clock */ + CLOCK_DisableClock(kCLOCK_UsbhsHost); +} + +#endif + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ +#ifdef CONFIG_SOC_MIMXRT685S_CM33 + /* Configure LPOSC clock*/ + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + /* Configure FFRO clock */ + POWER_DisablePD(kPDRUNCFG_PD_FFRO); + CLOCK_EnableFfroClk(kCLOCK_Ffro48M); + /* Configure SFRO clock */ + POWER_DisablePD(kPDRUNCFG_PD_SFRO); + CLOCK_EnableSfroClk(); + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_clock_safe_config() to move FlexSPI clock to a stable + * clock source to avoid instruction/data fetch issue when updating PLL and Main + * clock if XIP(execute code on FLEXSPI memory). + */ + flexspi_clock_safe_config(); +#endif + + /* Let CPU run on FFRO for safe switching. */ + CLOCK_AttachClk(kFFRO_to_MAIN_CLK); + + /* Configure SYSOSC clock source */ + POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); + POWER_UpdateOscSettlingTime(CONFIG_SYSOSC_SETTLING_US); + CLOCK_EnableSysOscClk(true, true, CONFIG_SYSOSC_SETTLING_US); + CLOCK_SetXtalFreq(CONFIG_XTAL_SYS_CLK_HZ); + +#ifdef CONFIG_INIT_SYS_PLL + /* Configure SysPLL0 clock source */ + CLOCK_InitSysPll(&g_sysPllConfig); + CLOCK_InitSysPfd(kCLOCK_Pfd0, 19); + CLOCK_InitSysPfd(kCLOCK_Pfd2, 24); +#endif + +#ifdef CONFIG_INIT_AUDIO_PLL + /* Configure Audio PLL clock source */ + CLOCK_InitAudioPll(&g_audioPllConfig); + CLOCK_InitAudioPfd(kCLOCK_Pfd0, 26); + CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 15U); +#endif + + /* Set SYSCPUAHBCLKDIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 2U); + + /* Set up clock selectors - Attach clocks to the peripheries */ + CLOCK_AttachClk(kMAIN_PLL_to_MAIN_CLK); + + /* Set up dividers */ + /* Set PFC0DIV divider to value 2 */ + CLOCK_SetClkDiv(kCLOCK_DivPfc0Clk, 2U); + /* Set FRGPLLCLKDIV divider to value 12 */ + CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 12U); + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_usart, okay) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM0); +#endif + +#if CONFIG_USB_DC_NXP_LPCIP3511 + usb_device_clock_init(); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2c, okay) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM2); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pmic_i2c), nxp_lpc_i2c, okay) + CLOCK_AttachClk(kFFRO_to_FLEXCOMM15); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm4), nxp_lpc_usart, okay) + CLOCK_AttachClk(kSFRO_to_FLEXCOMM4); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm5), nxp_lpc_spi, okay) + CLOCK_AttachClk(kFFRO_to_FLEXCOMM5); +#endif + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay)) + /* attach AUDIO PLL clock to FLEXCOMM1 (I2S1) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1); +#endif +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay)) + /* attach AUDIO PLL clock to FLEXCOMM3 (I2S3) */ + CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3); +#endif + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(wwdt0), nxp_lpc_wwdt, okay)) + CLOCK_AttachClk(kLPOSC_to_WDT0_CLK); +#else + /* Allowed to select none if not being used for watchdog to + * reduce power + */ + CLOCK_AttachClk(kNONE_to_WDT0_CLK); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC + /* Make sure USDHC ram buffer has been power up*/ + POWER_DisablePD(kPDRUNCFG_APD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PPD_USDHC0_SRAM); + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + POWER_ApplyPD(); + + /* usdhc depend on 32K clock also */ + CLOCK_AttachClk(kLPOSC_DIV32_to_32KHZWAKE_CLK); + CLOCK_AttachClk(kAUX0_PLL_to_SDIO0_CLK); + CLOCK_SetClkDiv(kCLOCK_DivSdio0Clk, 1); + CLOCK_EnableClock(kCLOCK_Sdio0); + RESET_PeripheralReset(kSDIO0_RST_SHIFT_RSTn); +#endif + + DT_FOREACH_STATUS_OKAY(nxp_lpc_ctimer, CTIMER_CLOCK_SETUP) + DT_FOREACH_STATUS_OKAY(nxp_ctimer_pwm, CTIMER_CLOCK_SETUP) + +#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(i3c0), nxp_mcux_i3c, okay)) + CLOCK_AttachClk(kFFRO_to_I3C_CLK); + CLOCK_AttachClk(kLPOSC_to_I3C_TC_CLK); +#endif + +#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpadc0), nxp_lpc_lpadc, okay) + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_PD_MASK; + SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_ADC_LP_MASK; + RESET_PeripheralReset(kADC0_RST_SHIFT_RSTn); + CLOCK_AttachClk(kSFRO_to_ADC_CLK); + CLOCK_SetClkDiv(kCLOCK_DivAdcClk, DT_PROP(DT_NODELABEL(lpadc0), clk_divider)); +#endif + +#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP + /* + * Call function flexspi_setup_clock() to set user configured clock source/divider + * for FlexSPI. + */ + flexspi_setup_clock(FLEXSPI, 1U, 9U); +#endif + +#if CONFIG_COUNTER_NXP_MRT + RESET_PeripheralReset(kMRT0_RST_SHIFT_RSTn); +#endif + + /* Set SystemCoreClock variable. */ + SystemCoreClock = CLOCK_INIT_CORE_CLOCK; + +#endif /* CONFIG_SOC_MIMXRT685S_CM33 */ +} + +#if (DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc0), okay) && CONFIG_IMX_USDHC) + +void imxrt_usdhc_pinmux(uint16_t nusdhc, bool init, + uint32_t speed, uint32_t strength) +{ + +} + +void imxrt_usdhc_dat3_pull(bool pullup) +{ + +} +#endif + +/** + * + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ + +static int nxp_rt600_init(void) +{ + /* Initialize clock */ + clock_init(); + +#ifndef CONFIG_IMXRT6XX_CODE_CACHE + CACHE64_DisableCache(CACHE64); +#endif + + return 0; +} + +#ifdef CONFIG_PLATFORM_SPECIFIC_INIT + +void z_arm_platform_init(void) +{ +#ifndef CONFIG_NXP_IMXRT_BOOT_HEADER + /* + * If boot did not proceed using a boot header, we should not assume + * the core is in reset state. Disable the MPU and correctly + * set the stack pointer, since we are about to push to + * the stack when we call SystemInit + */ + /* Clear stack limit registers */ + __set_MSPLIM(0); + __set_PSPLIM(0); + /* Disable MPU */ + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + /* Set stack pointer */ + __set_MSP((uint32_t)(z_main_stack + CONFIG_MAIN_STACK_SIZE)); +#endif /* !CONFIG_NXP_IMXRT_BOOT_HEADER */ + /* This is provided by the SDK */ + SystemInit(); +} + +#endif + +SYS_INIT(nxp_rt600_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_imx/rt6xx/soc.h b/soc/nxp/imxrt/imxrt6xx/soc.h similarity index 100% rename from soc/arm/nxp_imx/rt6xx/soc.h rename to soc/nxp/imxrt/imxrt6xx/soc.h diff --git a/soc/arm/nxp_imx/rt/mpu_regions.c b/soc/nxp/imxrt/mpu_regions.c similarity index 100% rename from soc/arm/nxp_imx/rt/mpu_regions.c rename to soc/nxp/imxrt/mpu_regions.c diff --git a/soc/nxp/imxrt/soc.yml b/soc/nxp/imxrt/soc.yml new file mode 100644 index 00000000000000..319d5b947e217b --- /dev/null +++ b/soc/nxp/imxrt/soc.yml @@ -0,0 +1,34 @@ +family: +- name: nxp_imxrt + series: + - name: imxrt10xx + socs: + - name: mimxrt1011 + - name: mimxrt1015 + - name: mimxrt1021 + - name: mimxrt1024 + - name: mimxrt1042 + - name: mimxrt1051 + - name: mimxrt1052 + - name: mimxrt1061 + - name: mimxrt1062 + - name: mimxrt1064 + - name: imxrt11xx + socs: + - name: mimxrt1166 + cpuclusters: + - name: cm7 + - name: cm4 + - name: mimxrt1176 + cpuclusters: + - name: cm7 + - name: cm4 + - name: imxrt5xx + socs: + - name: mimxrt595s + cpuclusters: + - name: cm33 + - name: f1 + - name: imxrt6xx + socs: + - name: mimxrt685s diff --git a/soc/arm/nxp_imx/rt6xx/usb.ld b/soc/nxp/imxrt/usb.ld similarity index 91% rename from soc/arm/nxp_imx/rt6xx/usb.ld rename to soc/nxp/imxrt/usb.ld index 170e2cefd8404d..2e10b4b12dc4a0 100644 --- a/soc/arm/nxp_imx/rt6xx/usb.ld +++ b/soc/nxp/imxrt/usb.ld @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 NXP + * Copyright 2021-2022, 2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ diff --git a/soc/arm/nxp_kinetis/CMakeLists.txt b/soc/nxp/kinetis/CMakeLists.txt similarity index 100% rename from soc/arm/nxp_kinetis/CMakeLists.txt rename to soc/nxp/kinetis/CMakeLists.txt diff --git a/soc/nxp/kinetis/Kconfig b/soc/nxp/kinetis/Kconfig new file mode 100644 index 00000000000000..4476e8f1697ac0 --- /dev/null +++ b/soc/nxp/kinetis/Kconfig @@ -0,0 +1,156 @@ +# Copyright (c) 2016 Intel Corporation +# Copyright (c) 2016, Freescale Semiconductor, Inc. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_KINETIS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + +if SOC_FAMILY_KINETIS + +config HAS_OSC + bool + help + Set if the oscillator (OSC) module is present in the SoC. + +config HAS_MCG + bool + help + Set if the multipurpose clock generator (MCG) module is present in the SoC. + +if HAS_OSC + +choice + prompt "Oscillator Mode Selection" + default OSC_EXTERNAL + +config OSC_EXTERNAL + bool "External reference clock" + help + Set this option to use the oscillator in external reference clock mode. + +config OSC_LOW_POWER + bool "Low power oscillator" + help + Set this option to use the oscillator in low-power mode. + +config OSC_HIGH_GAIN + bool "High gain oscillator" + help + Set this option to use the oscillator in high-gain mode. + +endchoice + +config OSC_XTAL0_FREQ + int "External oscillator frequency" + help + Set the external oscillator frequency in Hz. This should be set by the + board's defconfig. + +endif # HAS_OSC + +if HAS_MCG + +config MCG_PRDIV0 + hex "PLL external reference divider" + range 0 0x18 + default 0 + help + Selects the amount to divide down the external reference clock for the PLL. + The resulting frequency must be in the range of 2 MHz to 4 MHz. + +config MCG_VDIV0 + hex "VCO 0 divider" + range 0 0x1F + default 0 + help + Selects the amount to divide the VCO output of the PLL. The VDIV 0 bits + establish the multiplication factor (M) applied to the reference clock + frequency. + +config MCG_FCRDIV + int "Fast internal reference clock divider" + range 0 7 + default 1 + help + Selects the amount to divide down the fast internal reference clock. The + resulting frequency must be in the range 31.25 kHz to 4 MHz. + +config MCG_FRDIV + int "FLL external reference divider" + range 0 7 + default 0 + help + Selects the amount to divide down the external reference clock for the + FLL. The resulting frequency must be in the range 31.25 kHz to 39.0625 + kHz. + +endif # HAS_MCG + +config KINETIS_FLASH_CONFIG + bool "Kinetis flash configuration field" + default y if XIP && !BOOTLOADER_MCUBOOT + help + Include the 16-byte flash configuration field that stores default + protection settings (loaded on reset) and security information that + allows the MCU to restrict access to the FTFx module. + +if KINETIS_FLASH_CONFIG + +config KINETIS_FLASH_CONFIG_OFFSET + hex "Kinetis flash configuration field offset" + default 0x400 + +config KINETIS_FLASH_CONFIG_FSEC + hex "Flash security byte (FSEC)" + range 0 0xff + default 0xfe + help + Configures the reset value of the FSEC register, which includes + backdoor key access, mass erase, factory access, and flash security + options. + +config KINETIS_FLASH_CONFIG_FOPT + hex "Flash nonvolatile option byte (FOPT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FOPT register, which includes boot, + NMI, and EzPort options. + +config KINETIS_FLASH_CONFIG_FEPROT + hex "EEPROM protection byte (FEPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FEPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +config KINETIS_FLASH_CONFIG_FDPROT + hex "Data flash protection byte (FDPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FDPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +endif # KINETIS_FLASH_CONFIG + +config WDOG_ENABLE_AT_BOOT + bool "Keep watchdog timer enabled at boot" + help + Leave SOC watchdog timer enabled at boot. The specific timeout + and clock configuration of the watchdog at boot is SOC dependent. + Note: if the watchdog timer is enabled at boot, the user will + need to configure the watchdog using z_arm_watchdog_init, as + the SOC requires watchdog configuration before initial expiration + +# Enable watchdog configuration function if watchdog is left enabled at boot +config WDOG_INIT + bool + default WDOG_ENABLE_AT_BOOT + + +rsource "*/Kconfig" + +endif # SOC_FAMILY_KINETIS diff --git a/soc/nxp/kinetis/Kconfig.defconfig b/soc/nxp/kinetis/Kconfig.defconfig new file mode 100644 index 00000000000000..33f477c0230978 --- /dev/null +++ b/soc/nxp/kinetis/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_KINETIS + +config SERIAL_INIT_PRIORITY + default 55 + depends on SERIAL + +config ADC_INIT_PRIORITY + default 80 if ADC_MCUX_ADC16_ENABLE_EDMA + depends on ADC + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_KINETIS diff --git a/soc/nxp/kinetis/Kconfig.soc b/soc/nxp/kinetis/Kconfig.soc new file mode 100644 index 00000000000000..b5fcf5db79a580 --- /dev/null +++ b/soc/nxp/kinetis/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_KINETIS + bool + +config SOC_FAMILY + default "nxp_kinetis" if SOC_FAMILY_KINETIS + +rsource "*/Kconfig.soc" diff --git a/soc/arm/nxp_kinetis/common/pinctrl_soc.h b/soc/nxp/kinetis/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_kinetis/common/pinctrl_soc.h rename to soc/nxp/kinetis/common/pinctrl_soc.h diff --git a/soc/arm/nxp_kinetis/flash_config.ld b/soc/nxp/kinetis/flash_config.ld similarity index 100% rename from soc/arm/nxp_kinetis/flash_config.ld rename to soc/nxp/kinetis/flash_config.ld diff --git a/soc/arm/nxp_kinetis/flash_configuration.c b/soc/nxp/kinetis/flash_configuration.c similarity index 100% rename from soc/arm/nxp_kinetis/flash_configuration.c rename to soc/nxp/kinetis/flash_configuration.c diff --git a/soc/nxp/kinetis/k2x/CMakeLists.txt b/soc/nxp/kinetis/k2x/CMakeLists.txt new file mode 100644 index 00000000000000..915f002e0eda79 --- /dev/null +++ b/soc/nxp/kinetis/k2x/CMakeLists.txt @@ -0,0 +1,19 @@ +# +# Copyright (c) 2018 Prevas A/S +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources( + soc.c + ) + +if(DEFINED CONFIG_ARM_MPU AND DEFINED CONFIG_CPU_HAS_NXP_MPU) + # MK22F12 series MCUs have NXP MPU + zephyr_sources(nxp_mpu_regions.c) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/k2x/Kconfig b/soc/nxp/kinetis/k2x/Kconfig new file mode 100644 index 00000000000000..29317c2239cc61 --- /dev/null +++ b/soc/nxp/kinetis/k2x/Kconfig @@ -0,0 +1,47 @@ +# Kinetis K2X MCU line + +# Copyright (c) 2018 Prevas A/S +# Copyright (c) 2019 Thomas Burdick +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_KINETIS_K2X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MK22F51212 + select HAS_MCUX + select HAS_MCUX_SMC + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_DAC + select HAS_MCUX_RCM + +# Note- the MK22F12 SKU is a legacy SOC, no longer officially supported by +# NXP's MCUX SDK, and not recommended for new designs. +config SOC_MK22F12 + select HAS_MCUX + select HAS_MCUX_SMC + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_DAC + select HAS_MCUX_RCM + select CPU_HAS_NXP_MPU diff --git a/soc/nxp/kinetis/k2x/Kconfig.defconfig b/soc/nxp/kinetis/k2x/Kconfig.defconfig new file mode 100644 index 00000000000000..8095c7a1842025 --- /dev/null +++ b/soc/nxp/kinetis/k2x/Kconfig.defconfig @@ -0,0 +1,26 @@ +# Kinetis K2x series configuration options + +# Copyright (c) 2018 Prevas A/S +# Copyright (c) 2019 Thomas Burdick +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_KINETIS_K2X + +config GPIO + default y if SOC_MK22F51212 + +config NUM_IRQS + default 74 + +config NUM_IRQS + default 81 if SOC_MK22F12 + default 74 if SOC_MK22F51212 + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y if SOC_MK22F12 + +endif # SOC_SERIES_KINETIS_K2X diff --git a/soc/nxp/kinetis/k2x/Kconfig.soc b/soc/nxp/kinetis/k2x/Kconfig.soc new file mode 100644 index 00000000000000..60979d8a9d8733 --- /dev/null +++ b/soc/nxp/kinetis/k2x/Kconfig.soc @@ -0,0 +1,40 @@ +# Kinetis K2X MCU line + +# Copyright (c) 2018 Prevas A/S +# Copyright (c) 2019 Thomas Burdick +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_KINETIS_K2X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "k2x" if SOC_SERIES_KINETIS_K2X + +config SOC_MK22F51212 + bool + select SOC_SERIES_KINETIS_K2X + +# Note- the MK22F12 SKU is a legacy SOC, no longer officially supported by +# NXP's MCUX SDK, and not recommended for new designs. +config SOC_MK22F12 + bool + select SOC_SERIES_KINETIS_K2X + +config SOC + default "mk22f51212" if SOC_MK22F51212 + default "mk22f12" if SOC_MK22F12 + +config SOC_PART_NUMBER_MK22FN512VLH12 + bool + +config SOC_PART_NUMBER_MK22FX512VLQ12 + bool + +config SOC_PART_NUMBER + default "MK22FN512VLH12" if SOC_PART_NUMBER_MK22FN512VLH12 + default "MK22FX512VLQ12" if SOC_PART_NUMBER_MK22FX512VLQ12 diff --git a/soc/arm/nxp_kinetis/k2x/nxp_mpu_regions.c b/soc/nxp/kinetis/k2x/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/k2x/nxp_mpu_regions.c rename to soc/nxp/kinetis/k2x/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/k2x/soc.c b/soc/nxp/kinetis/k2x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/k2x/soc.c rename to soc/nxp/kinetis/k2x/soc.c diff --git a/soc/arm/nxp_kinetis/k2x/soc.h b/soc/nxp/kinetis/k2x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/k2x/soc.h rename to soc/nxp/kinetis/k2x/soc.h diff --git a/soc/nxp/kinetis/k6x/CMakeLists.txt b/soc/nxp/kinetis/k6x/CMakeLists.txt new file mode 100644 index 00000000000000..ef8279861fddf6 --- /dev/null +++ b/soc/nxp/kinetis/k6x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + nxp_mpu_regions.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/k6x/Kconfig b/soc/nxp/kinetis/k6x/Kconfig new file mode 100644 index 00000000000000..4f7bd55078da66 --- /dev/null +++ b/soc/nxp/kinetis/k6x/Kconfig @@ -0,0 +1,59 @@ +# Kinetis K6x series configuration + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K6X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_NXP_MPU + select HAS_MCUX_PIT + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MK64F12 + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_ENET + select HAS_MCUX_FLEXCAN + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_RTC + select HAS_MCUX_DAC + select HAS_MCUX_EDMA + select HAS_MCUX_RCM + +config SOC_MK66F18 + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_ENET + select HAS_MCUX_FLEXCAN + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select CPU_HAS_FPU + select HAS_MCUX_RTC + select HAS_MCUX_DAC + select HAS_MCUX_EDMA + select HAS_MCUX_RCM + select HAS_MCUX_LPUART + + +if SOC_MK66F18 + +config K6X_HSRUN + bool "High Speed RUN mode" + default y + help + This options enables support for High Speed RUN mode on K66F SoC. + +endif # SOC_MK66F18 diff --git a/soc/nxp/kinetis/k6x/Kconfig.defconfig b/soc/nxp/kinetis/k6x/Kconfig.defconfig new file mode 100644 index 00000000000000..94136541855ff9 --- /dev/null +++ b/soc/nxp/kinetis/k6x/Kconfig.defconfig @@ -0,0 +1,22 @@ +# Kinetis K6x series default configurations + +# Copyright (c) 2014-2016 Wind River Systems, Inc. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_K6X + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y + +config NUM_IRQS + default 100 if SOC_MK66F18 + default 86 if SOC_MK64F12 + +config GPIO + default y + +config SPI + default n if SOC_MK64F12 + +endif # SOC_SERIES_KINETIS_K6X diff --git a/soc/nxp/kinetis/k6x/Kconfig.soc b/soc/nxp/kinetis/k6x/Kconfig.soc new file mode 100644 index 00000000000000..2e8d8f7b924903 --- /dev/null +++ b/soc/nxp/kinetis/k6x/Kconfig.soc @@ -0,0 +1,70 @@ +# Kinetis K6X MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K6X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "k6x" if SOC_SERIES_KINETIS_K6X + +config SOC_MK64F12 + bool + select SOC_SERIES_KINETIS_K6X + +config SOC_MK66F18 + bool + select SOC_SERIES_KINETIS_K6X + +config SOC + default "mk64f12" if SOC_MK64F12 + default "mk66f18" if SOC_MK66F18 + +config SOC_PART_NUMBER_MK64FN1M0CAJ12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VDC12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VLL12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VLQ12 + bool + +config SOC_PART_NUMBER_MK64FN1M0VMD12 + bool + +config SOC_PART_NUMBER_MK64FX512VDC12 + bool + +config SOC_PART_NUMBER_MK64FX512VLL12 + bool + +config SOC_PART_NUMBER_MK64FX512VLQ12 + bool + +config SOC_PART_NUMBER_MK64FX512VMD12 + bool + +config SOC_PART_NUMBER_MK66FN2M0VMD18 + bool + +config SOC_PART_NUMBER_MK66FN2M0VLQ18 + bool + +config SOC_PART_NUMBER + default "MK64FN1M0CAJ12" if SOC_PART_NUMBER_MK64FN1M0CAJ12 + default "MK64FN1M0VDC12" if SOC_PART_NUMBER_MK64FN1M0VDC12 + default "MK64FN1M0VLL12" if SOC_PART_NUMBER_MK64FN1M0VLL12 + default "MK64FN1M0VLQ12" if SOC_PART_NUMBER_MK64FN1M0VLQ12 + default "MK64FN1M0VMD12" if SOC_PART_NUMBER_MK64FN1M0VMD12 + default "MK64FX512VDC12" if SOC_PART_NUMBER_MK64FX512VDC12 + default "MK64FX512VLL12" if SOC_PART_NUMBER_MK64FX512VLL12 + default "MK64FX512VLQ12" if SOC_PART_NUMBER_MK64FX512VLQ12 + default "MK64FX512VMD12" if SOC_PART_NUMBER_MK64FX512VMD12 + default "MK66FN2M0VMD18" if SOC_PART_NUMBER_MK66FN2M0VMD18 + default "MK66FN2M0VLQ18" if SOC_PART_NUMBER_MK66FN2M0VLQ18 diff --git a/soc/arm/nxp_kinetis/k6x/README.txt b/soc/nxp/kinetis/k6x/README.txt similarity index 100% rename from soc/arm/nxp_kinetis/k6x/README.txt rename to soc/nxp/kinetis/k6x/README.txt diff --git a/soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c b/soc/nxp/kinetis/k6x/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/k6x/nxp_mpu_regions.c rename to soc/nxp/kinetis/k6x/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/k6x/soc.c b/soc/nxp/kinetis/k6x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/k6x/soc.c rename to soc/nxp/kinetis/k6x/soc.c diff --git a/soc/arm/nxp_kinetis/k6x/soc.h b/soc/nxp/kinetis/k6x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/k6x/soc.h rename to soc/nxp/kinetis/k6x/soc.h diff --git a/soc/nxp/kinetis/k8x/CMakeLists.txt b/soc/nxp/kinetis/k8x/CMakeLists.txt new file mode 100644 index 00000000000000..ef8279861fddf6 --- /dev/null +++ b/soc/nxp/kinetis/k8x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + nxp_mpu_regions.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/k8x/Kconfig b/soc/nxp/kinetis/k8x/Kconfig new file mode 100644 index 00000000000000..ad8c4c85589051 --- /dev/null +++ b/soc/nxp/kinetis/k8x/Kconfig @@ -0,0 +1,61 @@ +# Kinetis K8x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K8X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_NXP_MPU + select CPU_HAS_FPU + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_LPUART + select HAS_MCUX_PIT + select HAS_MCUX_RTC + select HAS_MCUX_SIM + select HAS_MCUX_TRNG + select HAS_OSC + select HAS_MCG + select HAS_MCUX_EDMA + select HAS_MCUX_PIT + select HAS_MCUX_RCM + select HAS_MCUX_CACHE + select PLATFORM_SPECIFIC_INIT + +if SOC_SERIES_KINETIS_K8X + +config K8X_CORE_CLOCK_DIVIDER + int "Freescale K8x core clock divider" + default 1 + help + This option specifies the divide value for the K8x processor core clock + from the system clock. + +config K8X_BUS_CLOCK_DIVIDER + int "Freescale K8x bus clock divider" + default 2 + help + This option specifies the divide value for the K8x bus clock from the + system clock. + +config K8X_FLEXBUS_CLOCK_DIVIDER + int "Freescale K8x FlexBus clock divider" + default 2 + help + This option specifies the divide value for the K8x FlexBus clock from the + system clock. + +config K8X_FLASH_CLOCK_DIVIDER + int "Freescale K8x flash clock divider" + default 5 + help + This option specifies the divide value for the K8x flash clock from the + system clock. + +endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/nxp/kinetis/k8x/Kconfig.defconfig b/soc/nxp/kinetis/k8x/Kconfig.defconfig new file mode 100644 index 00000000000000..777c123c5ac113 --- /dev/null +++ b/soc/nxp/kinetis/k8x/Kconfig.defconfig @@ -0,0 +1,23 @@ +# Kinetis K8x series configuration options + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_K8X + +config NUM_IRQS + # must be >= the highest interrupt number used + default 106 + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y + +config KINETIS_FLASH_CONFIG_FOPT + default 0x3f + depends on KINETIS_FLASH_CONFIG + +config GPIO + default y + +endif # SOC_SERIES_KINETIS_K8X diff --git a/soc/nxp/kinetis/k8x/Kconfig.soc b/soc/nxp/kinetis/k8x/Kconfig.soc new file mode 100644 index 00000000000000..53bf2d656e384b --- /dev/null +++ b/soc/nxp/kinetis/k8x/Kconfig.soc @@ -0,0 +1,42 @@ +# Kinetis K8x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_K8X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "k8x" if SOC_SERIES_KINETIS_K8X + +config SOC_MK80F25615 + bool + select SOC_SERIES_KINETIS_K8X + +config SOC_MK82F25615 + bool + select SOC_SERIES_KINETIS_K8X + +config SOC + default "mk80f25615" if SOC_MK80F25615 + default "mk82f25615" if SOC_MK82F25615 + +config SOC_PART_NUMBER_MK80FN256VDC15 + bool + +config SOC_PART_NUMBER_MK80FN256VLL15 + bool + +config SOC_PART_NUMBER_MK82FN256VDC15 + bool + +config SOC_PART_NUMBER_MK82FN256VLL15 + bool + +config SOC_PART_NUMBER + default "MK80FN256VDC15" if SOC_PART_NUMBER_MK80FN256VDC15 + default "MK80FN256VLL15" if SOC_PART_NUMBER_MK80FN256VLL15 + default "MK82FN256VDC15" if SOC_PART_NUMBER_MK82FN256VDC15 + default "MK82FN256VLL15" if SOC_PART_NUMBER_MK82FN256VLL15 diff --git a/soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c b/soc/nxp/kinetis/k8x/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/k8x/nxp_mpu_regions.c rename to soc/nxp/kinetis/k8x/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/k8x/soc.c b/soc/nxp/kinetis/k8x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/k8x/soc.c rename to soc/nxp/kinetis/k8x/soc.c diff --git a/soc/arm/nxp_kinetis/k8x/soc.h b/soc/nxp/kinetis/k8x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/k8x/soc.h rename to soc/nxp/kinetis/k8x/soc.h diff --git a/soc/nxp/kinetis/ke1xf/CMakeLists.txt b/soc/nxp/kinetis/ke1xf/CMakeLists.txt new file mode 100644 index 00000000000000..9a2e98801ac3f1 --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/CMakeLists.txt @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + nxp_mpu_regions.c + ) +zephyr_sources_ifdef( + CONFIG_PM + power.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_include_directories(.) diff --git a/soc/nxp/kinetis/ke1xf/Kconfig b/soc/nxp/kinetis/ke1xf/Kconfig new file mode 100644 index 00000000000000..df752ab9da3922 --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/Kconfig @@ -0,0 +1,68 @@ +# Kinetis KE1xF series MCU + +# Copyright (c) 2019 Vestas Wind Systems A/S +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KE1XF + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_NXP_MPU + select CPU_HAS_FPU + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_CACHE + select HAS_MCUX_FTFX + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_LPUART + select HAS_MCUX_PCC + select HAS_MCUX_RTC + select HAS_MCUX_SIM + select HAS_MCUX_ADC12 + select HAS_MCUX_SCG + select HAS_MCUX_WDOG32 + select HAS_MCUX_FTM + select HAS_MCUX_LPTMR + select HAS_MCUX_DAC32 + select HAS_MCUX_EDMA + select HAS_MCUX_ACMP + select HAS_MCUX_PWT + select HAS_MCUX_RCM + select PLATFORM_SPECIFIC_INIT + select HAS_PM + +config SOC_MKE16F16 + select HAS_MCUX + select HAS_MCUX_FLEXCAN + +config SOC_MKE18F16 + select HAS_MCUX + select HAS_MCUX_FLEXCAN + +if SOC_SERIES_KINETIS_KE1XF + +config WDOG_ENABLE_AT_BOOT + bool "Keep watchdog timer enabled at boot" + help + Keep the watchdog timer enabled at boot with the internal + 128kHz LPO clock (and a prescaler of 256) as clock + source. The application can take over control of the + watchdog timer after boot and install a different timeout, + if needed. + +config WDOG_INITIAL_TIMEOUT + int "Initial timeout for the watchdog timer in milliseconds" + depends on WDOG_ENABLE_AT_BOOT && WDOG_INIT + range 2 131070 + default 2048 + help + Initial timeout value for the watchdog timer in + milliseconds. + +config KINETIS_KE1XF_ENABLE_CODE_CACHE + bool "Code cache" + default y + +endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/nxp/kinetis/ke1xf/Kconfig.defconfig b/soc/nxp/kinetis/ke1xf/Kconfig.defconfig new file mode 100644 index 00000000000000..bf6d1e532eadb2 --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/Kconfig.defconfig @@ -0,0 +1,37 @@ +# Kinetis KE1xF series configuration options + +# Copyright (c) 2019-2021 Vestas Wind Systems A/S +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KE1XF + +config MCUX_LPTMR_TIMER + default y if PM + +config CORTEX_M_SYSTICK + default n if MCUX_LPTMR_TIMER + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK + default $(dt_node_int_prop_int,/soc/lptmr@40040000,clock-frequency) if MCUX_LPTMR_TIMER + +config NUM_IRQS + # must be >= the highest interrupt number used + default 91 + +config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + default y + +config KINETIS_FLASH_CONFIG_FOPT + default 0x7d + depends on KINETIS_FLASH_CONFIG + +config PWM_MCUX_PWT + default y + depends on PWM_CAPTURE + +config GPIO + default y + +endif # SOC_SERIES_KINETIS_KE1XF diff --git a/soc/nxp/kinetis/ke1xf/Kconfig.soc b/soc/nxp/kinetis/ke1xf/Kconfig.soc new file mode 100644 index 00000000000000..979882204288ad --- /dev/null +++ b/soc/nxp/kinetis/ke1xf/Kconfig.soc @@ -0,0 +1,79 @@ +# Kinetis KE1xF MCU line + +# Copyright (c) 2019 Vestas Wind Systems A/S +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KE1XF + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "ke1xf" if SOC_SERIES_KINETIS_KE1XF + +config SOC_MKE14F16 + bool + select SOC_SERIES_KINETIS_KE1XF + +config SOC_MKE16F16 + bool + select SOC_SERIES_KINETIS_KE1XF + +config SOC_MKE18F16 + bool + select SOC_SERIES_KINETIS_KE1XF + +config SOC + default "mke14f16" if SOC_MKE14F16 + default "mke16f16" if SOC_MKE16F16 + default "mke18f16" if SOC_MKE18F16 + +config SOC_PART_NUMBER_MKE14F256VLH16 + bool + +config SOC_PART_NUMBER_MKE14F256VLL16 + bool + +config SOC_PART_NUMBER_MKE14F512VLH16 + bool + +config SOC_PART_NUMBER_MKE14F512VLL16 + bool + +config SOC_PART_NUMBER_MKE16F256VLH16 + bool + +config SOC_PART_NUMBER_MKE16F256VLL16 + bool + +config SOC_PART_NUMBER_MKE16F512VLH16 + bool + +config SOC_PART_NUMBER_MKE16F512VLL16 + bool + +config SOC_PART_NUMBER_MKE18F256VLH16 + bool + +config SOC_PART_NUMBER_MKE18F256VLL16 + bool + +config SOC_PART_NUMBER_MKE18F512VLH16 + bool + +config SOC_PART_NUMBER_MKE18F512VLL16 + bool + +config SOC_PART_NUMBER + default "MKE14F256VLH16" if SOC_PART_NUMBER_MKE14F256VLH16 + default "MKE14F256VLL16" if SOC_PART_NUMBER_MKE14F256VLL16 + default "MKE14F512VLH16" if SOC_PART_NUMBER_MKE14F512VLH16 + default "MKE14F512VLL16" if SOC_PART_NUMBER_MKE14F512VLL16 + default "MKE16F256VLH16" if SOC_PART_NUMBER_MKE16F256VLH16 + default "MKE16F256VLL16" if SOC_PART_NUMBER_MKE16F256VLL16 + default "MKE16F512VLH16" if SOC_PART_NUMBER_MKE16F512VLH16 + default "MKE16F512VLL16" if SOC_PART_NUMBER_MKE16F512VLL16 + default "MKE18F256VLH16" if SOC_PART_NUMBER_MKE18F256VLH16 + default "MKE18F256VLL16" if SOC_PART_NUMBER_MKE18F256VLL16 + default "MKE18F512VLH16" if SOC_PART_NUMBER_MKE18F512VLH16 + default "MKE18F512VLL16" if SOC_PART_NUMBER_MKE18F512VLL16 diff --git a/soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c b/soc/nxp/kinetis/ke1xf/nxp_mpu_regions.c similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c rename to soc/nxp/kinetis/ke1xf/nxp_mpu_regions.c diff --git a/soc/arm/nxp_kinetis/ke1xf/power.c b/soc/nxp/kinetis/ke1xf/power.c similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/power.c rename to soc/nxp/kinetis/ke1xf/power.c diff --git a/soc/arm/nxp_kinetis/ke1xf/soc.c b/soc/nxp/kinetis/ke1xf/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/soc.c rename to soc/nxp/kinetis/ke1xf/soc.c diff --git a/soc/arm/nxp_kinetis/ke1xf/soc.h b/soc/nxp/kinetis/ke1xf/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/ke1xf/soc.h rename to soc/nxp/kinetis/ke1xf/soc.h diff --git a/soc/nxp/kinetis/kl2x/CMakeLists.txt b/soc/nxp/kinetis/kl2x/CMakeLists.txt new file mode 100644 index 00000000000000..15835842aa8853 --- /dev/null +++ b/soc/nxp/kinetis/kl2x/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_include_directories(.) diff --git a/soc/nxp/kinetis/kl2x/Kconfig b/soc/nxp/kinetis/kl2x/Kconfig new file mode 100644 index 00000000000000..6e88ad79fc2a6e --- /dev/null +++ b/soc/nxp/kinetis/kl2x/Kconfig @@ -0,0 +1,23 @@ +# Kinetis KL2x MCU series + +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KL2X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MKL25Z4 + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_LPSCI + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM diff --git a/soc/nxp/kinetis/kl2x/Kconfig.defconfig b/soc/nxp/kinetis/kl2x/Kconfig.defconfig new file mode 100644 index 00000000000000..d51313e95982b7 --- /dev/null +++ b/soc/nxp/kinetis/kl2x/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Kinetis KL2x series configuration options + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KL2X + +config NUM_IRQS + default 32 if SOC_MKL25Z4 + +endif # SOC_SERIES_KINETIS_KL2X diff --git a/soc/nxp/kinetis/kl2x/Kconfig.soc b/soc/nxp/kinetis/kl2x/Kconfig.soc new file mode 100644 index 00000000000000..f1525737db6be4 --- /dev/null +++ b/soc/nxp/kinetis/kl2x/Kconfig.soc @@ -0,0 +1,68 @@ +# Kinetis KL2x MCU series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KL2X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "kl2x" if SOC_SERIES_KINETIS_KL2X + +config SOC_MKL25Z4 + bool + select SOC_SERIES_KINETIS_KL2X + +config SOC + default "mkl25z4" if SOC_MKL25Z4 + +config SOC_PART_NUMBER_MKL25Z32VFM4 + bool + +config SOC_PART_NUMBER_MKL25Z64VFM4 + bool + +config SOC_PART_NUMBER_MKL25Z128VFM4 + bool + +config SOC_PART_NUMBER_MKL25Z32VFT4 + bool + +config SOC_PART_NUMBER_MKL25Z64VFT4 + bool + +config SOC_PART_NUMBER_MKL25Z128VFT4 + bool + +config SOC_PART_NUMBER_MKL25Z32VLH4 + bool + +config SOC_PART_NUMBER_MKL25Z64VLH4 + bool + +config SOC_PART_NUMBER_MKL25Z128VLH4 + bool + +config SOC_PART_NUMBER_MKL25Z32VLK4 + bool + +config SOC_PART_NUMBER_MKL25Z64VLK4 + bool + +config SOC_PART_NUMBER_MKL25Z128VLK4 + bool + +config SOC_PART_NUMBER + default "MKL25Z32VFM4" if SOC_PART_NUMBER_MKL25Z32VFM4 + default "MKL25Z64VFM4" if SOC_PART_NUMBER_MKL25Z64VFM4 + default "MKL25Z128VFM4" if SOC_PART_NUMBER_MKL25Z128VFM4 + default "MKL25Z32VFT4" if SOC_PART_NUMBER_MKL25Z32VFT4 + default "MKL25Z64VFT4" if SOC_PART_NUMBER_MKL25Z64VFT4 + default "MKL25Z128VFT4" if SOC_PART_NUMBER_MKL25Z128VFT4 + default "MKL25Z32VLH4" if SOC_PART_NUMBER_MKL25Z32VLH4 + default "MKL25Z64VLH4" if SOC_PART_NUMBER_MKL25Z64VLH4 + default "MKL25Z128VLH4" if SOC_PART_NUMBER_MKL25Z128VLH4 + default "MKL25Z32VLK4" if SOC_PART_NUMBER_MKL25Z32VLK4 + default "MKL25Z64VLK4" if SOC_PART_NUMBER_MKL25Z64VLK4 + default "MKL25Z128VLK4" if SOC_PART_NUMBER_MKL25Z128VLK4 diff --git a/soc/arm/nxp_kinetis/kl2x/soc.c b/soc/nxp/kinetis/kl2x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/kl2x/soc.c rename to soc/nxp/kinetis/kl2x/soc.c diff --git a/soc/arm/nxp_kinetis/kl2x/soc.h b/soc/nxp/kinetis/kl2x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/kl2x/soc.h rename to soc/nxp/kinetis/kl2x/soc.h diff --git a/soc/nxp/kinetis/kv5x/CMakeLists.txt b/soc/nxp/kinetis/kv5x/CMakeLists.txt new file mode 100644 index 00000000000000..11a75f9d221762 --- /dev/null +++ b/soc/nxp/kinetis/kv5x/CMakeLists.txt @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_include_directories(.) diff --git a/soc/nxp/kinetis/kv5x/Kconfig b/soc/nxp/kinetis/kv5x/Kconfig new file mode 100644 index 00000000000000..93a48b3caba5f3 --- /dev/null +++ b/soc/nxp/kinetis/kv5x/Kconfig @@ -0,0 +1,24 @@ +# Kinetis KV5x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KV5X + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + select PLATFORM_SPECIFIC_INIT diff --git a/soc/nxp/kinetis/kv5x/Kconfig.defconfig b/soc/nxp/kinetis/kv5x/Kconfig.defconfig new file mode 100644 index 00000000000000..206a2c4de0c6b7 --- /dev/null +++ b/soc/nxp/kinetis/kv5x/Kconfig.defconfig @@ -0,0 +1,16 @@ +# Kinetis KV5x series configuration options + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KV5X + +config NUM_IRQS + # must be >= the highest interrupt number used + default 121 + +config GPIO + default y + +endif # SOC_SERIES_KINETIS_KV5X diff --git a/soc/nxp/kinetis/kv5x/Kconfig.soc b/soc/nxp/kinetis/kv5x/Kconfig.soc new file mode 100644 index 00000000000000..ce717b2f371af9 --- /dev/null +++ b/soc/nxp/kinetis/kv5x/Kconfig.soc @@ -0,0 +1,58 @@ +# Kinetis KV5x series MCU + +# Copyright (c) 2019 SEAL AG +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KV5X + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "kv5x" if SOC_SERIES_KINETIS_KV5X + +config SOC_MKV56F24 + bool + select SOC_SERIES_KINETIS_KV5X + +config SOC_MKV58F24 + bool + select SOC_SERIES_KINETIS_KV5X + +config SOC + default "mkv56f24" if SOC_MKV56F24 + default "mkv58f24" if SOC_MKV58F24 + +config SOC_PART_NUMBER_MKV56F512VLL24 + bool + +config SOC_PART_NUMBER_MKV56F512VLQ24 + bool + +config SOC_PART_NUMBER_MKV56F1M0VLL24 + bool + +config SOC_PART_NUMBER_MKV56F1M0VLQ24 + bool + +config SOC_PART_NUMBER_MKV58F512VLL24 + bool + +config SOC_PART_NUMBER_MKV58F512VLQ24 + bool + +config SOC_PART_NUMBER_MKV58F1M0VLL24 + bool + +config SOC_PART_NUMBER_MKV58F1M0VLQ24 + bool + +config SOC_PART_NUMBER + default "MKV56F512VLL24" if SOC_PART_NUMBER_MKV56F512VLL24 + default "MKV56F512VLQ24" if SOC_PART_NUMBER_MKV56F512VLQ24 + default "MKV56F1M0VLL24" if SOC_PART_NUMBER_MKV56F1M0VLL24 + default "MKV56F1M0VLQ24" if SOC_PART_NUMBER_MKV56F1M0VLQ24 + default "MKV58F512VLL24" if SOC_PART_NUMBER_MKV58F512VLL24 + default "MKV58F512VLQ24" if SOC_PART_NUMBER_MKV58F512VLQ24 + default "MKV58F1M0VLL24" if SOC_PART_NUMBER_MKV58F1M0VLL24 + default "MKV58F1M0VLQ24" if SOC_PART_NUMBER_MKV58F1M0VLQ24 diff --git a/soc/arm/nxp_kinetis/kv5x/soc.c b/soc/nxp/kinetis/kv5x/soc.c similarity index 100% rename from soc/arm/nxp_kinetis/kv5x/soc.c rename to soc/nxp/kinetis/kv5x/soc.c diff --git a/soc/arm/nxp_kinetis/kv5x/soc.h b/soc/nxp/kinetis/kv5x/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/kv5x/soc.h rename to soc/nxp/kinetis/kv5x/soc.h diff --git a/soc/arm/nxp_kinetis/kv5x/wdog.S b/soc/nxp/kinetis/kv5x/wdog.S similarity index 100% rename from soc/arm/nxp_kinetis/kv5x/wdog.S rename to soc/nxp/kinetis/kv5x/wdog.S diff --git a/soc/nxp/kinetis/kwx/CMakeLists.txt b/soc/nxp/kinetis/kwx/CMakeLists.txt new file mode 100644 index 00000000000000..5355c9c96fed14 --- /dev/null +++ b/soc/nxp/kinetis/kwx/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_SOC_MKW24D5 soc_kw2xd.c) +zephyr_sources_ifdef(CONFIG_SOC_MKW22D5 soc_kw2xd.c) +zephyr_sources_ifdef(CONFIG_SOC_MKW41Z4 soc_kw4xz.c) +zephyr_sources_ifdef(CONFIG_SOC_MKW40Z4 soc_kw4xz.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/kinetis/kwx/Kconfig b/soc/nxp/kinetis/kwx/Kconfig new file mode 100644 index 00000000000000..d3e209e3f969bc --- /dev/null +++ b/soc/nxp/kinetis/kwx/Kconfig @@ -0,0 +1,62 @@ +# Kinetis KWx MCU series + +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KWX + select ARM + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CLOCK_CONTROL + select PLATFORM_SPECIFIC_INIT + +config SOC_MKW22D5 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + +config SOC_MKW24D5 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_FTM + select HAS_MCUX_RNGA + select HAS_MCUX_SIM + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + +config SOC_MKW40Z4 + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_LPUART + select HAS_MCUX_SIM + select HAS_MCUX_TRNG + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM + +config SOC_MKW41Z4 + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_ADC16 + select HAS_MCUX_FTFX + select HAS_MCUX_LPUART + select HAS_MCUX_RTC + select HAS_MCUX_SIM + select HAS_MCUX_TPM + select HAS_MCUX_TRNG + select HAS_OSC + select HAS_MCG + select HAS_MCUX_RCM diff --git a/soc/nxp/kinetis/kwx/Kconfig.defconfig b/soc/nxp/kinetis/kwx/Kconfig.defconfig new file mode 100644 index 00000000000000..d2fb4f0de0daab --- /dev/null +++ b/soc/nxp/kinetis/kwx/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Kinetis KWx series configuration options + +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_KINETIS_KWX + +config NUM_IRQS + default 65 if SOC_MKW22D5 || SOC_MKW24D5 + default 32 if SOC_MKW40Z4 || SOC_MKW41Z4 + +config SPI + default y if SOC_MKW22D5 || SOC_MKW24D5 + +config NET_L2_IEEE802154 + default y if !NET_L2_OPENTHREAD && SOC_MKW41Z4 + +if SOC_MKW40Z4 || SOC_MKW41Z4 + +choice CSPRNG_GENERATOR_CHOICE + default CTR_DRBG_CSPRNG_GENERATOR +endchoice + +choice RNG_GENERATOR_CHOICE + default XOSHIRO_RANDOM_GENERATOR +endchoice + +config TINYCRYPT + default y + depends on ENTROPY_GENERATOR && SOC_MKW41Z4 + +endif # SOC_MKW40Z4 || SOC_MKW41Z4 + +endif # SOC_SERIES_KINETIS_KWX diff --git a/soc/nxp/kinetis/kwx/Kconfig.soc b/soc/nxp/kinetis/kwx/Kconfig.soc new file mode 100644 index 00000000000000..ad2a46072218c8 --- /dev/null +++ b/soc/nxp/kinetis/kwx/Kconfig.soc @@ -0,0 +1,55 @@ +# Kinetis KWx MCU series + +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_KINETIS_KWX + bool + select SOC_FAMILY_KINETIS + +config SOC_SERIES + default "kwx" if SOC_SERIES_KINETIS_KWX + +config SOC_MKW22D5 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC_MKW24D5 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC_MKW40Z4 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC_MKW41Z4 + bool + select SOC_SERIES_KINETIS_KWX + +config SOC + default "mkw22d5" if SOC_MKW22D5 + default "mkw24d5" if SOC_MKW24D5 + default "mkw40z4" if SOC_MKW40Z4 + default "mkw41z4" if SOC_MKW41Z4 + +config SOC_PART_NUMBER_MKW22D512VHA5 + bool + +config SOC_PART_NUMBER_MKW24D512VHA5 + bool + +config SOC_PART_NUMBER_MKW40Z160VHT4 + bool + +config SOC_PART_NUMBER_MKW41Z256VHT4 + bool + +config SOC_PART_NUMBER_MKW41Z512VHT4 + bool + +config SOC_PART_NUMBER + default "MKW22D512VHA5" if SOC_PART_NUMBER_MKW22D512VHA5 + default "MKW24D512VHA5" if SOC_PART_NUMBER_MKW24D512VHA5 + default "MKW40Z160VHT4" if SOC_PART_NUMBER_MKW40Z160VHT4 + default "MKW41Z256VHT4" if SOC_PART_NUMBER_MKW41Z256VHT4 + default "MKW41Z512VHT4" if SOC_PART_NUMBER_MKW41Z512VHT4 diff --git a/soc/arm/nxp_kinetis/kwx/soc.h b/soc/nxp/kinetis/kwx/soc.h similarity index 100% rename from soc/arm/nxp_kinetis/kwx/soc.h rename to soc/nxp/kinetis/kwx/soc.h diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw2xd.c b/soc/nxp/kinetis/kwx/soc_kw2xd.c similarity index 100% rename from soc/arm/nxp_kinetis/kwx/soc_kw2xd.c rename to soc/nxp/kinetis/kwx/soc_kw2xd.c diff --git a/soc/arm/nxp_kinetis/kwx/soc_kw4xz.c b/soc/nxp/kinetis/kwx/soc_kw4xz.c similarity index 100% rename from soc/arm/nxp_kinetis/kwx/soc_kw4xz.c rename to soc/nxp/kinetis/kwx/soc_kw4xz.c diff --git a/soc/nxp/kinetis/soc.yml b/soc/nxp/kinetis/soc.yml new file mode 100644 index 00000000000000..c2b27eb9841cd6 --- /dev/null +++ b/soc/nxp/kinetis/soc.yml @@ -0,0 +1,31 @@ +family: +- name: kinetis + series: + - name: kwx + socs: + - name: mkw22d5 + - name: mkw24d5 + - name: mkw40z4 + - name: mkw41z4 + - name: k6x + socs: + - name: mk64f12 + - name: mk66f18 + - name: k2x + socs: + - name: mk22f51212 + - name: mk22f12 + - name: ke1xf + socs: + - name: mke18f16 + - name: k8x + socs: + - name: mk80f25615 + - name: mk82f25615 + - name: kl2x + socs: + - name: mkl25z4 + - name: kv5x + socs: + - name: mkv56f24 + - name: mkv58f24 diff --git a/soc/arm64/nxp_layerscape/CMakeLists.txt b/soc/nxp/layerscape/CMakeLists.txt similarity index 100% rename from soc/arm64/nxp_layerscape/CMakeLists.txt rename to soc/nxp/layerscape/CMakeLists.txt diff --git a/soc/nxp/layerscape/Kconfig b/soc/nxp/layerscape/Kconfig new file mode 100644 index 00000000000000..5b5b1c572f80d4 --- /dev/null +++ b/soc/nxp/layerscape/Kconfig @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +# +if SOC_FAMILY_NXP_LAYERSCAPE + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NXP_LAYERSCAPE diff --git a/soc/nxp/layerscape/Kconfig.defconfig b/soc/nxp/layerscape/Kconfig.defconfig new file mode 100644 index 00000000000000..99feef9bf8490c --- /dev/null +++ b/soc/nxp/layerscape/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_NXP_LAYERSCAPE + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NXP_LAYERSCAPE diff --git a/soc/nxp/layerscape/Kconfig.soc b/soc/nxp/layerscape/Kconfig.soc new file mode 100644 index 00000000000000..0ea005c817551c --- /dev/null +++ b/soc/nxp/layerscape/Kconfig.soc @@ -0,0 +1,13 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_FAMILY_NXP_LAYERSCAPE + bool + +config SOC_FAMILY + default "nxp_layerscape" if SOC_FAMILY_NXP_LAYERSCAPE + +rsource "*/Kconfig.soc" diff --git a/soc/arm64/nxp_layerscape/ls1046a/CMakeLists.txt b/soc/nxp/layerscape/ls1046a/CMakeLists.txt similarity index 100% rename from soc/arm64/nxp_layerscape/ls1046a/CMakeLists.txt rename to soc/nxp/layerscape/ls1046a/CMakeLists.txt diff --git a/soc/nxp/layerscape/ls1046a/Kconfig b/soc/nxp/layerscape/ls1046a/Kconfig new file mode 100644 index 00000000000000..bc151b6b66540d --- /dev/null +++ b/soc/nxp/layerscape/ls1046a/Kconfig @@ -0,0 +1,10 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_LS1046A + select ARM64 + select CPU_CORTEX_A72 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS diff --git a/soc/nxp/layerscape/ls1046a/Kconfig.defconfig b/soc/nxp/layerscape/ls1046a/Kconfig.defconfig new file mode 100644 index 00000000000000..f22b14b4e26c88 --- /dev/null +++ b/soc/nxp/layerscape/ls1046a/Kconfig.defconfig @@ -0,0 +1,19 @@ +# +# Copyright 2021,2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_LS1046A + +config NUM_IRQS + int + default 240 + +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 + +endif diff --git a/soc/nxp/layerscape/ls1046a/Kconfig.soc b/soc/nxp/layerscape/ls1046a/Kconfig.soc new file mode 100644 index 00000000000000..cced813a62c895 --- /dev/null +++ b/soc/nxp/layerscape/ls1046a/Kconfig.soc @@ -0,0 +1,31 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LS1046A + bool + select SOC_FAMILY_NXP_LAYERSCAPE + +config SOC_LS1046A + bool + select SOC_SERIES_LS1046A + help + NXP Layerscape ls1046a + +config SOC + default "ls1046a" if SOC_LS1046A + +config SOC_SERIES + default "ls1046a" if SOC_SERIES_LS1046A + +config SOC_PART_NUMBER_LS1046A + bool + +config SOC_PART_NUMBER_LS1026A + bool + +config SOC_PART_NUMBER + default "LS1046A" if SOC_PART_NUMBER_LS1046A + default "LS1026A" if SOC_PART_NUMBER_LS1026A diff --git a/soc/arm64/nxp_layerscape/ls1046a/mmu_regions.c b/soc/nxp/layerscape/ls1046a/mmu_regions.c similarity index 100% rename from soc/arm64/nxp_layerscape/ls1046a/mmu_regions.c rename to soc/nxp/layerscape/ls1046a/mmu_regions.c diff --git a/soc/nxp/layerscape/soc.yml b/soc/nxp/layerscape/soc.yml new file mode 100644 index 00000000000000..69fae2c6abd71d --- /dev/null +++ b/soc/nxp/layerscape/soc.yml @@ -0,0 +1,6 @@ +family: +- name: nxp_layerscape + series: + - name: ls1046a + socs: + - name: ls1046a diff --git a/soc/arm/nxp_lpc/CMakeLists.txt b/soc/nxp/lpc/CMakeLists.txt similarity index 100% rename from soc/arm/nxp_lpc/CMakeLists.txt rename to soc/nxp/lpc/CMakeLists.txt diff --git a/soc/nxp/lpc/Kconfig b/soc/nxp/lpc/Kconfig new file mode 100644 index 00000000000000..ac4411e6c5ff72 --- /dev/null +++ b/soc/nxp/lpc/Kconfig @@ -0,0 +1,12 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_LPC + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select CLOCK_CONTROL + select ARM + +if SOC_FAMILY_LPC +rsource "*/Kconfig" + +endif # SOC_FAMILY_LPC diff --git a/soc/nxp/lpc/Kconfig.defconfig b/soc/nxp/lpc/Kconfig.defconfig new file mode 100644 index 00000000000000..ca61dec3a84479 --- /dev/null +++ b/soc/nxp/lpc/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_LPC + +config SERIAL_INIT_PRIORITY + default 55 if SERIAL + +config BUILD_WITH_TFM + default y if TRUSTED_EXECUTION_NONSECURE + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_LPC diff --git a/soc/nxp/lpc/Kconfig.soc b/soc/nxp/lpc/Kconfig.soc new file mode 100644 index 00000000000000..46b6b54c2f1cc0 --- /dev/null +++ b/soc/nxp/lpc/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2017,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_LPC + bool + +config SOC_FAMILY + default "lpc" if SOC_FAMILY_LPC + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/lpc/lpc11u6x/CMakeLists.txt b/soc/nxp/lpc/lpc11u6x/CMakeLists.txt new file mode 100644 index 00000000000000..628e4ab155d404 --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc11u6x/Kconfig b/soc/nxp/lpc/lpc11u6x/Kconfig new file mode 100644 index 00000000000000..52ccbdd5ed8bfa --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/Kconfig @@ -0,0 +1,14 @@ +# LPC LPC11U6X MCU line +# +# Copyright (c) 2020, Seagate +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LPC11U6X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select PINCTRL + select CLOCK_CONTROL diff --git a/soc/nxp/lpc/lpc11u6x/Kconfig.defconfig b/soc/nxp/lpc/lpc11u6x/Kconfig.defconfig new file mode 100644 index 00000000000000..7f924a52a7b819 --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/Kconfig.defconfig @@ -0,0 +1,15 @@ +# LPC LPC11U6X MCU line +# +# Copyright (c) 2020, Seagate +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_LPC11U6X + +config NUM_IRQS + # must be >= the highest interrupt number used + default 40 + +endif # SOC_SERIES_LPC11U6X diff --git a/soc/nxp/lpc/lpc11u6x/Kconfig.soc b/soc/nxp/lpc/lpc11u6x/Kconfig.soc new file mode 100644 index 00000000000000..94a5067b29c295 --- /dev/null +++ b/soc/nxp/lpc/lpc11u6x/Kconfig.soc @@ -0,0 +1,55 @@ +# NXP LPC11U6x series + +# Copyright 2024 NXP + +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LPC11U6X + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc11u6x" if SOC_SERIES_LPC11U6X + +config SOC_LPC11U68 + bool + select SOC_SERIES_LPC11U6X + +config SOC_LPC11U67 + bool + select SOC_SERIES_LPC11U6X + +config SOC_LPC11U66 + bool + select SOC_SERIES_LPC11U6X + +config SOC + default "lpc11u66" if SOC_LPC11U66 + default "lpc11u67" if SOC_LPC11U67 + default "lpc11u68" if SOC_LPC11U68 + +config SOC_PART_NUMBER_LPC11U66JBD48 + bool +config SOC_PART_NUMBER_LPC11U67JBD48 + bool +config SOC_PART_NUMBER_LPC11U67JBD64 + bool +config SOC_PART_NUMBER_LPC11U67JBD100 + bool +config SOC_PART_NUMBER_LPC11U68JBD48 + bool +config SOC_PART_NUMBER_LPC11U68JBD64 + bool +config SOC_PART_NUMBER_LPC11U68JBD100 + bool + +config SOC_PART_NUMBER + default "LPC11U66JBD48" if SOC_PART_NUMBER_LPC11U66JBD48 + default "LPC11U67JBD48" if SOC_PART_NUMBER_LPC11U67JBD48 + default "LPC11U67JBD64" if SOC_PART_NUMBER_LPC11U67JBD64 + default "LPC11U67JBD100" if SOC_PART_NUMBER_LPC11U67JBD100 + default "LPC11U68JBD48" if SOC_PART_NUMBER_LPC11U68JBD48 + default "LPC11U68JBD64" if SOC_PART_NUMBER_LPC11U68JBD64 + default "LPC11U68JBD100" if SOC_PART_NUMBER_LPC11U68JBD100 diff --git a/soc/arm/nxp_lpc/lpc11u6x/iap.h b/soc/nxp/lpc/lpc11u6x/iap.h similarity index 100% rename from soc/arm/nxp_lpc/lpc11u6x/iap.h rename to soc/nxp/lpc/lpc11u6x/iap.h diff --git a/soc/arm/nxp_lpc/lpc11u6x/pinctrl_soc.h b/soc/nxp/lpc/lpc11u6x/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc11u6x/pinctrl_soc.h rename to soc/nxp/lpc/lpc11u6x/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc11u6x/soc.h b/soc/nxp/lpc/lpc11u6x/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc11u6x/soc.h rename to soc/nxp/lpc/lpc11u6x/soc.h diff --git a/soc/nxp/lpc/lpc51u68/CMakeLists.txt b/soc/nxp/lpc/lpc51u68/CMakeLists.txt new file mode 100644 index 00000000000000..3bae960a47e198 --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/CMakeLists.txt @@ -0,0 +1,18 @@ +# +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(soc.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc51u68/Kconfig b/soc/nxp/lpc/lpc51u68/Kconfig new file mode 100644 index 00000000000000..fc920bb89e4ddd --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/Kconfig @@ -0,0 +1,21 @@ +# LPC51U68 series configuration options +# +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_SERIES_LPC51U68 + select ARM + select CPU_CORTEX_M0PLUS + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_SYSCON + select HAS_MCUX_SCTIMER + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select PLATFORM_SPECIFIC_INIT + +config SOC_LPC51U68 + select CLOCK_CONTROL diff --git a/soc/nxp/lpc/lpc51u68/Kconfig.defconfig b/soc/nxp/lpc/lpc51u68/Kconfig.defconfig new file mode 100644 index 00000000000000..b62054ea6db9fa --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/Kconfig.defconfig @@ -0,0 +1,17 @@ +# LPC51U68 series configuration options + +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_LPC51U68 + +config NUM_IRQS + # must be >= the highest interrupt number used. + default 32 + +config SOC_FLASH_LPC + default y + depends on FLASH + +endif # SOC_SERIES_LPC51U86 diff --git a/soc/nxp/lpc/lpc51u68/Kconfig.soc b/soc/nxp/lpc/lpc51u68/Kconfig.soc new file mode 100644 index 00000000000000..a09015b66f14b9 --- /dev/null +++ b/soc/nxp/lpc/lpc51u68/Kconfig.soc @@ -0,0 +1,29 @@ +# LPC LPC51U68 MCU line + +# Copyright (c) 2021 metraTec GmbH +# Copyright 2024 NXP +# SPDX-License Identifier: Apache-2.0 + +config SOC_SERIES_LPC51U68 + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc51u68" if SOC_SERIES_LPC51U68 + +config SOC_LPC51U68 + bool + select SOC_SERIES_LPC51U68 + +config SOC + default "lpc51u68" if SOC_LPC51U68 + +config SOC_PART_NUMBER_LPC51U68JBD48 + bool + +config SOC_PART_NUMBER_LPC51U68JBD64 + bool + +config SOC_PART_NUMBER + default "LPC51U68JBD48" if SOC_PART_NUMBER_LPC51U68JBD48 + default "LPC51U68JBD64" if SOC_PART_NUMBER_LPC51U68JBD64 diff --git a/soc/arm/nxp_lpc/lpc51u68/linker.ld b/soc/nxp/lpc/lpc51u68/linker.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/linker.ld rename to soc/nxp/lpc/lpc51u68/linker.ld diff --git a/soc/arm/nxp_lpc/lpc51u68/pinctrl_soc.h b/soc/nxp/lpc/lpc51u68/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/pinctrl_soc.h rename to soc/nxp/lpc/lpc51u68/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc51u68/soc.c b/soc/nxp/lpc/lpc51u68/soc.c similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/soc.c rename to soc/nxp/lpc/lpc51u68/soc.c diff --git a/soc/arm/nxp_lpc/lpc51u68/soc.h b/soc/nxp/lpc/lpc51u68/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc51u68/soc.h rename to soc/nxp/lpc/lpc51u68/soc.h diff --git a/soc/nxp/lpc/lpc54xxx/CMakeLists.txt b/soc/nxp/lpc/lpc54xxx/CMakeLists.txt new file mode 100644 index 00000000000000..d8fab22133dbca --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/CMakeLists.txt @@ -0,0 +1,25 @@ +# +# Copyright (c) 2017, 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(soc.c) +zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT gcc/startup_LPC54114_cm4.S) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + + +# CMSIS SystemInit allows us to skip enabling clock to SRAM2 bank via +# this compiler definition +if(NOT DEFINED CONFIG_LPC54XXX_SRAM2_CLOCK) +zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc54xxx/Kconfig b/soc/nxp/lpc/lpc54xxx/Kconfig new file mode 100644 index 00000000000000..78997d6504b3e9 --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/Kconfig @@ -0,0 +1,69 @@ +# LPC LPC54XXX MCU line + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC54XXX + select ARM + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_SYSCON + select CPU_CORTEX_M_HAS_SYSTICK + select PLATFORM_SPECIFIC_INIT + +config SOC_LPC54114_M4 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select PLATFORM_SPECIFIC_INIT + select CLOCK_CONTROL + select HAS_MCUX_IAP_LEGACY + +config SOC_LPC54114_M0 + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select CLOCK_CONTROL + +config MCUX_CORE_SUFFIX + default "_cm4" if SOC_LPC54114_M4 + default "_cm0plus" if SOC_LPC54114_M0 + +if SOC_SERIES_LPC54XXX + +config SECOND_CORE_MCUX + bool "LPC54114 Cortex-M0 second core" + help + Driver for second core startup + +config SECOND_CORE_BOOT_ADDRESS_MCUX + depends on SECOND_CORE_MCUX + hex "Address the second core will boot at" + default 0x20010000 + help + This is the address the second core will boot from. Additionally this + address is where we will copy the SECOND_IMAGE to. We default this to + the base of SRAM1. + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition + +# Move the LMA address of second core into flash +config BUILD_OUTPUT_ADJUST_LMA + depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 + default "-0x20010000+\ + $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))" + +config BUILD_OUTPUT_INFO_HEADER + default y + depends on SECOND_CORE_MCUX && SOC_LPC54114_M0 + +config LPC54XXX_SRAM2_CLOCK + bool "Clock LPC54XXX SRAM2" + default y + help + SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit + will enable the clock to this RAM bank. Disable this Kconfig to leave + this ram bank untouched out of reset. + +endif # SOC_SERIES_LPC54XXX diff --git a/soc/nxp/lpc/lpc54xxx/Kconfig.defconfig b/soc/nxp/lpc/lpc54xxx/Kconfig.defconfig new file mode 100644 index 00000000000000..5955a2f8e36086 --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/Kconfig.defconfig @@ -0,0 +1,15 @@ +# NXP LPC54114 M0 platform configuration options + +# Copyright 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_LPC54XXX + +config GPIO + default n if SOC_LPC54114_M0 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 40 + +endif # SOC_SERIES_LPC54XXX diff --git a/soc/nxp/lpc/lpc54xxx/Kconfig.soc b/soc/nxp/lpc/lpc54xxx/Kconfig.soc new file mode 100644 index 00000000000000..346facb71291d7 --- /dev/null +++ b/soc/nxp/lpc/lpc54xxx/Kconfig.soc @@ -0,0 +1,38 @@ +# LPC LPC54XXX MCU line + +# Copyright (c) 2017, 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC54XXX + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc54xxx" if SOC_SERIES_LPC54XXX + +config SOC_LPC54114 + bool + select SOC_SERIES_LPC54XXX + +config SOC_LPC54114_M4 + bool + select SOC_LPC54114 + +config SOC_LPC54114_M0 + bool + select SOC_LPC54114 + +# The NXP HAL expects the SOC to just be lpc54114 if targeting +# the M4. When targeting M0 it expects lpc54114_m0. +# +# Action to update the NXP HAL to support checking for SOC_LPC54114_M0 +# instead. +config SOC + default "lpc54114" if SOC_LPC54114_M4 + default "lpc54114" if SOC_LPC54114_M0 + +config SOC_PART_NUMBER_LPC54114J256BD64 + bool + +config SOC_PART_NUMBER + default "LPC54114J256BD64" if SOC_PART_NUMBER_LPC54114J256BD64 diff --git a/soc/arm/nxp_lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S b/soc/nxp/lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S rename to soc/nxp/lpc/lpc54xxx/gcc/startup_LPC54114_cm4.S diff --git a/soc/arm/nxp_lpc/lpc54xxx/linker.ld b/soc/nxp/lpc/lpc54xxx/linker.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/linker.ld rename to soc/nxp/lpc/lpc54xxx/linker.ld diff --git a/soc/arm/nxp_lpc/lpc54xxx/pinctrl_soc.h b/soc/nxp/lpc/lpc54xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/pinctrl_soc.h rename to soc/nxp/lpc/lpc54xxx/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.c b/soc/nxp/lpc/lpc54xxx/soc.c similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/soc.c rename to soc/nxp/lpc/lpc54xxx/soc.c diff --git a/soc/arm/nxp_lpc/lpc54xxx/soc.h b/soc/nxp/lpc/lpc54xxx/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc54xxx/soc.h rename to soc/nxp/lpc/lpc54xxx/soc.h diff --git a/soc/nxp/lpc/lpc55xxx/CMakeLists.txt b/soc/nxp/lpc/lpc55xxx/CMakeLists.txt new file mode 100644 index 00000000000000..5f66a3eb9d8a8a --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/CMakeLists.txt @@ -0,0 +1,29 @@ +# +# Copyright (c) 2019, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# +zephyr_library() + +zephyr_library_sources(soc.c) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) +if(DEFINED CONFIG_LPC55XXX_USB_RAM) +zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER + SECTIONS usb.ld) + +zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1) +endif() + +# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via +# this compiler definition +if(NOT DEFINED CONFIG_LPC55XXX_SRAM_CLOCKS) +zephyr_compile_definitions(DONT_ENABLE_DISABLED_RAMBANKS=1) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig b/soc/nxp/lpc/lpc55xxx/Kconfig new file mode 100644 index 00000000000000..2fcc3e4ee66e9f --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/Kconfig @@ -0,0 +1,114 @@ +# Copyright 2019,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC55XXX + select HAS_MCUX + select HAS_MCUX_FLEXCOMM + select HAS_MCUX_SYSCON + select HAS_MCUX_WWDT + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_DWT + select PLATFORM_SPECIFIC_INIT + +config SOC_LPC55S06 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE + select HAS_MCUX_RNG + +config SOC_LPC55S16 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE + select HAS_MCUX_MCAN + select HAS_MCUX_RNG + +config SOC_LPC55S28 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select HAS_MCUX_IAP + select HAS_MCUX_LPADC + select HAS_MCUX_LPC_DMA + select HAS_MCUX_RNG + +config SOC_LPC55S36 + select CPU_CORTEX_M33 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_MCAN + select HAS_MCUX_PWM + +config SOC_LPC55S69 + select CPU_CORTEX_M33 + +config SOC_LPC55S69_CPU0 + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select HAS_MCUX_IAP + select HAS_MCUX_LPADC + select HAS_MCUX_LPC_DMA + select HAS_MCUX_USB_LPCIP3511 + select HAS_MCUX_CTIMER + select HAS_MCUX_SCTIMER + select HAS_MCUX_RNG + +if SOC_SERIES_LPC55XXX + +config INIT_PLL0 + bool "Initialize PLL0" + +config INIT_PLL1 + bool "Initialize PLL1" + default "y" + depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM) + help + In the LPC55XXX Family, this is currently being used to set the + core clock value at it's highest frequency which clocks at 150MHz. + Note that flash programming operations are limited to 100MHz, and + this PLL should not be used as the core clock in those cases. + +config SECOND_CORE_MCUX + bool "LPC55xxx's second core" + +config SECOND_CORE_BOOT_ADDRESS_MCUX + depends on SECOND_CORE_MCUX + hex "Address the second core will boot at" + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION)) + help + This is the address the second core will boot from. + +config LPC55XXX_SRAM_CLOCKS + bool "CLock LPC SRAM banks" + +config LPC55XXX_USB_RAM + bool + +if SOC_LPC55S69 + +config SOC_FLASH_MCUX + bool + +endif # SOC_LPC55S69 + +config MCUX_CORE_SUFFIX + default "_cm33_core0" if SOC_LPC55S69_CPU0 + default "_cm33_core1" if SOC_LPC55S69_CPU1 + +endif # SOC_SERIES_LPC55XXX diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig new file mode 100644 index 00000000000000..ed43f5041ede5d --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/Kconfig.defconfig @@ -0,0 +1,114 @@ +# Copyright 2019,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_LPC55XXX + +config NUM_IRQS + # must be >= the highest interrupt number used + default 60 + +# In the LPC55XXX Family, this is currently being used to set the +# core clock value at it's highest frequency which clocks at 150MHz. +# Note that flash programming operations are limited to 100MHz, and +# this PLL should not be used as the core clock in those cases. +config INIT_PLL1 + default "y" + depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 144000000 if INIT_PLL1 + default 96000000 + +# Indicates the second core will be enabled, and the part will run +# in dual core mode. +config SECOND_CORE_MCUX + depends on HAS_MCUX + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CODE_CPU1_PARTITION := zephyr,code-cpu1-partition + + +# Move the LMA for the second core image to be in the flash region of primary +# core, so that JLink flash will load it correctly. +config BUILD_OUTPUT_ADJUST_LMA + depends on SECOND_CORE_MCUX && SOC_LPC55S69_CPU1 + default "0x10000000" + +# SRAM controllers 1,2,3, and 4 are disabled at reset. +# By default, CMSIS SystemInit will enable the clock to these RAM banks. +# Disable this Kconfig to leave the ram banks untouched out of reset. +config LPC55XXX_SRAM_CLOCKS + default y + +# Some SoC's in the LPC5500 Series do have a dedicated USB RAM. +# By default, USB RAM is assumed to be present. +# Disable this Kconfig in case there is no dedicated USB RAM. +config LPC55XXX_USB_RAM + default y + +if SOC_LPC55S06 + +config LPC55XXX_USB_RAM + default n + +endif # SOC_LPC55S06 + +if SOC_LPC55S16 + +config CAN_MCUX_MCAN + default y + depends on CAN + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +endif # SOC_LPC55S16 + +if SOC_LPC55S28 + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +endif # SOC_LPC55S28 + +if SOC_LPC55S36 + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +config LPC55XXX_USB_RAM + default n + +endif # SOC_LPC55S36 + +if SOC_LPC55S69 + +config SOC_FLASH_MCUX + default y + depends on FLASH + depends on !TRUSTED_EXECUTION_NONSECURE + +choice USB_MCUX_CONTROLLER_TYPE + default USB_DC_NXP_LPCIP3511 +endchoice + +config I2S_MCUX_FLEXCOMM + select INIT_PLL0 + +endif # SOC_LPC55S69 + +if SOC_LPC55S69_CPU1 + + +config GPIO + default y + +config SERIAL + default n + +endif # SOC_LPC55S69_CPU1 + +endif # SOC_SERIES_LPC55XXX diff --git a/soc/nxp/lpc/lpc55xxx/Kconfig.soc b/soc/nxp/lpc/lpc55xxx/Kconfig.soc new file mode 100644 index 00000000000000..e5b668b54fabe6 --- /dev/null +++ b/soc/nxp/lpc/lpc55xxx/Kconfig.soc @@ -0,0 +1,74 @@ +# Copyright 2019, 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_LPC55XXX + bool + select SOC_FAMILY_LPC + +config SOC_SERIES + default "lpc55xxx" if SOC_SERIES_LPC55XXX + +config SOC_LPC55S06 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S16 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S28 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S36 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S69 + bool + select SOC_SERIES_LPC55XXX + +config SOC_LPC55S69_CPU0 + bool + select SOC_LPC55S69 + +config SOC_LPC55S69_CPU1 + bool + select SOC_LPC55S69 + +config SOC + default "lpc55s69" if SOC_LPC55S69_CPU0 || SOC_LPC55S69_CPU1 + default "lpc55s06" if SOC_LPC55S06 + default "lpc55s16" if SOC_LPC55S16 + default "lpc55s28" if SOC_LPC55S28 + default "lpc55s36" if SOC_LPC55S36 + +config SOC_PART_NUMBER_LPC55S06JBD64 + bool + +config SOC_PART_NUMBER_LPC55S16JBD64 + bool + +config SOC_PART_NUMBER_LPC55S16JBD100 + bool + +config SOC_PART_NUMBER_LPC55S28JBD100 + bool + +config SOC_PART_NUMBER_LPC55S36JBD100 + bool + +config SOC_PART_NUMBER_LPC55S69JBD100 + bool + +config SOC_PART_NUMBER_LPC55S69JET98 + bool + +config SOC_PART_NUMBER + default "LPC55S06JBD64" if SOC_PART_NUMBER_LPC55S06JBD64 + default "LPC55S16JBD64" if SOC_PART_NUMBER_LPC55S16JBD64 + default "LPC55S16JBD100" if SOC_PART_NUMBER_LPC55S16JBD100 + default "LPC55S28JBD100" if SOC_PART_NUMBER_LPC55S28JBD100 + default "LPC55S36JBD100" if SOC_PART_NUMBER_LPC55S36JBD100 + default "LPC55S69JBD100" if SOC_PART_NUMBER_LPC55S69JBD100 + default "LPC55S69JET98" if SOC_PART_NUMBER_LPC55S69JET98 diff --git a/soc/arm/nxp_lpc/lpc55xxx/linker.ld b/soc/nxp/lpc/lpc55xxx/linker.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/linker.ld rename to soc/nxp/lpc/lpc55xxx/linker.ld diff --git a/soc/arm/nxp_lpc/lpc55xxx/pinctrl_soc.h b/soc/nxp/lpc/lpc55xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/pinctrl_soc.h rename to soc/nxp/lpc/lpc55xxx/pinctrl_soc.h diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.c b/soc/nxp/lpc/lpc55xxx/soc.c similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/soc.c rename to soc/nxp/lpc/lpc55xxx/soc.c diff --git a/soc/arm/nxp_lpc/lpc55xxx/soc.h b/soc/nxp/lpc/lpc55xxx/soc.h similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/soc.h rename to soc/nxp/lpc/lpc55xxx/soc.h diff --git a/soc/arm/nxp_lpc/lpc55xxx/usb.ld b/soc/nxp/lpc/lpc55xxx/usb.ld similarity index 100% rename from soc/arm/nxp_lpc/lpc55xxx/usb.ld rename to soc/nxp/lpc/lpc55xxx/usb.ld diff --git a/soc/nxp/lpc/soc.yml b/soc/nxp/lpc/soc.yml new file mode 100644 index 00000000000000..32b07924fb6f36 --- /dev/null +++ b/soc/nxp/lpc/soc.yml @@ -0,0 +1,27 @@ +family: +- name: lpc + series: + - name: lpc11u6x + socs: + - name: lpc11u66 + - name: lpc11u67 + - name: lpc11u68 + - name: lpc51u68 + socs: + - name: lpc51u68 + - name: lpc54xxx + socs: + - name: lpc54114 + cpuclusters: + - name: m4 + - name: m0 + - name: lpc55xxx + socs: + - name: lpc55s06 + - name: lpc55s16 + - name: lpc55s28 + - name: lpc55s36 + - name: lpc55s69 + cpuclusters: + - name: cpu0 + - name: cpu1 diff --git a/soc/arm/nxp_s32/CMakeLists.txt b/soc/nxp/s32/CMakeLists.txt similarity index 100% rename from soc/arm/nxp_s32/CMakeLists.txt rename to soc/nxp/s32/CMakeLists.txt diff --git a/soc/nxp/s32/Kconfig b/soc/nxp/s32/Kconfig new file mode 100644 index 00000000000000..9b608588e21ca3 --- /dev/null +++ b/soc/nxp/s32/Kconfig @@ -0,0 +1,31 @@ +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_S32 + +config NXP_S32_FUNC_RESET_THRESHOLD + int "Functional Reset Escalation threshold" + default 15 + range 0 15 + help + If the value of this option is 0, the Functional reset escalation + function is disabled. Any other value is the number of Functional + resets that causes a Destructive reset, if the FRET register isn't + written to beforehand. + Default to maximum threshold (hardware reset value). + +config NXP_S32_DEST_RESET_THRESHOLD + int "Destructive Reset Escalation threshold" + default 0 + range 0 15 + help + If the value of this field is 0, the Destructive reset escalation + function is disabled. Any other value is the number of Destructive + resets which keeps the chip in the reset state until the next power-on + reset triggers a new reset sequence, if the DRET register isn't + written to beforehand. + Default to disabled (hardware reset value). + +rsource "*/Kconfig" + +endif # SOC_FAMILY_NXP_S32 diff --git a/soc/nxp/s32/Kconfig.defconfig b/soc/nxp/s32/Kconfig.defconfig new file mode 100644 index 00000000000000..47d7caffcfb213 --- /dev/null +++ b/soc/nxp/s32/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_NXP_S32 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_NXP_S32 diff --git a/soc/nxp/s32/Kconfig.soc b/soc/nxp/s32/Kconfig.soc new file mode 100644 index 00000000000000..875db9b12fe2ba --- /dev/null +++ b/soc/nxp/s32/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_NXP_S32 + bool + +config SOC_FAMILY + default "nxp_s32" if SOC_FAMILY_NXP_S32 + +rsource "*/Kconfig.soc" diff --git a/soc/nxp/s32/common/CMakeLists.txt b/soc/nxp/s32/common/CMakeLists.txt new file mode 100644 index 00000000000000..7b98b446338192 --- /dev/null +++ b/soc/nxp/s32/common/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright 2022-2023 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_sources(osif.c) +zephyr_sources_ifdef(CONFIG_SOC_SERIES_S32K3 power_soc.c) diff --git a/soc/arm/nxp_s32/common/cmsis_rtos_v2_adapt.h b/soc/nxp/s32/common/cmsis_rtos_v2_adapt.h similarity index 100% rename from soc/arm/nxp_s32/common/cmsis_rtos_v2_adapt.h rename to soc/nxp/s32/common/cmsis_rtos_v2_adapt.h diff --git a/soc/arm/nxp_s32/common/osif.c b/soc/nxp/s32/common/osif.c similarity index 94% rename from soc/arm/nxp_s32/common/osif.c rename to soc/nxp/s32/common/osif.c index 73b5c6c1d1fe4b..5216f632a116fe 100644 --- a/soc/arm/nxp_s32/common/osif.c +++ b/soc/nxp/s32/common/osif.c @@ -8,7 +8,7 @@ #include #include -#if defined(CONFIG_SOC_SERIES_S32K1XX) +#if defined(CONFIG_SOC_SERIES_S32K1) /* Aliases needed to build with different SoC-specific HAL versions */ #define CPXNUM CPxNUM #define MSCM_CPXNUM_CPN_MASK MSCM_CPxNUM_CPN_MASK diff --git a/soc/arm/nxp_s32/common/pinctrl_soc.h b/soc/nxp/s32/common/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_s32/common/pinctrl_soc.h rename to soc/nxp/s32/common/pinctrl_soc.h diff --git a/soc/arm/nxp_s32/common/power_soc.c b/soc/nxp/s32/common/power_soc.c similarity index 98% rename from soc/arm/nxp_s32/common/power_soc.c rename to soc/nxp/s32/common/power_soc.c index 3e277155cb82ea..a2ca0cabfcaf9b 100644 --- a/soc/arm/nxp_s32/common/power_soc.c +++ b/soc/nxp/s32/common/power_soc.c @@ -71,7 +71,7 @@ static int nxp_s32_power_init(void) }; const Power_Ip_PMC_ConfigType pmc_cfg = { -#ifdef CONFIG_SOC_SERIES_S32K3XX +#ifdef CONFIG_SOC_SERIES_S32K3 /* PMC Configuration Register (CONFIG) */ .ConfigRegister = PMC_CONFIG_LMEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMEN)) | PMC_CONFIG_LMBCTLEN(IS_ENABLED(CONFIG_NXP_S32_PMC_LMBCTLEN)), diff --git a/soc/nxp/s32/s32k1/CMakeLists.txt b/soc/nxp/s32/s32k1/CMakeLists.txt new file mode 100644 index 00000000000000..cb66e9e1ffc7b7 --- /dev/null +++ b/soc/nxp/s32/s32k1/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_sources(soc.c) +zephyr_sources_ifdef(CONFIG_ARM_MPU nxp_mpu_regions.c) + +zephyr_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG flash_configuration.c) +zephyr_linker_sources_ifdef(CONFIG_NXP_S32_FLASH_CONFIG ROM_START SORT_KEY 0x1 flash_config.ld) diff --git a/soc/nxp/s32/s32k1/Kconfig b/soc/nxp/s32/s32k1/Kconfig new file mode 100644 index 00000000000000..c1b6de3e3efdf3 --- /dev/null +++ b/soc/nxp/s32/s32k1/Kconfig @@ -0,0 +1,124 @@ +# NXP S32K1XX MCUs series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K1 + select ARM + select HAS_NXP_S32_HAL + select HAS_MCUX + select CPU_HAS_NXP_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select MPU_ALLOW_FLASH_WRITE if !XIP + select CLOCK_CONTROL + select HAS_MCUX_LPUART + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_FTM + select HAS_MCUX_FLEXCAN + select HAS_MCUX_WDOG32 + select HAS_MCUX_RTC + +config SOC_S32K116 + select CPU_CORTEX_M0PLUS + +config SOC_S32K118 + select CPU_CORTEX_M0PLUS + +config SOC_S32K142 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K142W + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K144 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K144W + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K146 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +config SOC_S32K148 + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_MCUX_CACHE + +if SOC_SERIES_S32K1 + +config WDOG_INIT + bool + default y + +config NXP_S32_FLASH_CONFIG + bool "NXP S32 flash configuration field" + default y if XIP && !BOOTLOADER_MCUBOOT + help + Include the 16-byte flash configuration field that stores default + protection settings (loaded on reset) and security information that + allows the MCU to restrict access to the FTFx module. + +if NXP_S32_FLASH_CONFIG + +config NXP_S32_FLASH_CONFIG_OFFSET + hex "NXP S32 flash configuration field offset" + default 0x400 + +config NXP_S32_FLASH_CONFIG_FSEC + hex "Flash security byte (FSEC)" + range 0 0xff + default 0xfe + help + Configures the reset value of the FSEC register, which includes + backdoor key access, mass erase, factory access, and flash security + options. + +config NXP_S32_FLASH_CONFIG_FOPT + hex "Flash nonvolatile option byte (FOPT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FOPT register, which includes boot, + NMI, and EzPort options. + +config NXP_S32_FLASH_CONFIG_FEPROT + hex "EEPROM protection byte (FEPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FEPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +config NXP_S32_FLASH_CONFIG_FDPROT + hex "Data flash protection byte (FDPROT)" + range 0 0xff + default 0xff + help + Configures the reset value of the FDPROT register for FlexNVM + devices. For program flash only devices, this byte is reserved. + +endif # NXP_S32_FLASH_CONFIG + +config NXP_S32_ENABLE_CODE_CACHE + bool "Code cache" + default y + depends on HAS_MCUX_CACHE + +endif # SOC_SERIES_S32K1 diff --git a/soc/nxp/s32/s32k1/Kconfig.defconfig b/soc/nxp/s32/s32k1/Kconfig.defconfig new file mode 100644 index 00000000000000..582ebf0e3269de --- /dev/null +++ b/soc/nxp/s32/s32k1/Kconfig.defconfig @@ -0,0 +1,30 @@ +# NXP S32K1XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_S32K1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 80000000 + +config NUM_IRQS + default 239 if CPU_CORTEX_M4 + default 47 if CPU_CORTEX_M0PLUS + +config FPU + default y if CPU_HAS_FPU + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +# The S32K1xx have 8 MPU regions, which is not enough for both HW stack protection +# and userspace. Only enable HW stack protection if userspace is not enabled. +config HW_STACK_PROTECTION + default y if !USERSPACE + +endif # SOC_SERIES_S32K1 diff --git a/soc/nxp/s32/s32k1/Kconfig.soc b/soc/nxp/s32/s32k1/Kconfig.soc new file mode 100644 index 00000000000000..26a5210bbb7c2a --- /dev/null +++ b/soc/nxp/s32/s32k1/Kconfig.soc @@ -0,0 +1,371 @@ +# NXP S32K1XX MCUs series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K1 + bool + select SOC_FAMILY_NXP_S32 + +config SOC_SERIES + default "s32k1" if SOC_SERIES_S32K1 + +config SOC_S32K116 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K118 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K142 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K142W + bool + select SOC_SERIES_S32K1 + +config SOC_S32K144 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K144W + bool + select SOC_SERIES_S32K1 + +config SOC_S32K146 + bool + select SOC_SERIES_S32K1 + +config SOC_S32K148 + bool + select SOC_SERIES_S32K1 + +config SOC + default "s32k116" if SOC_S32K116 + default "s32k118" if SOC_S32K118 + default "s32k142" if SOC_S32K142 + default "s32k142w" if SOC_S32K142W + default "s32k144" if SOC_S32K144 + default "s32k144w" if SOC_S32K144W + default "s32k146" if SOC_S32K146 + default "s32k148" if SOC_S32K148 + +config SOC_PART_NUMBER_FS32K116LAT0MFMT + bool + +config SOC_PART_NUMBER_FS32K116LAT0MLFR + bool + +config SOC_PART_NUMBER_FS32K116LAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K116LIT0VFMT + bool + +config SOC_PART_NUMBER_FS32K116LIT0VLFT + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLFR + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLHR + bool + +config SOC_PART_NUMBER_FS32K118LAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K118LIT0VLFT + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K142HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K142HVT0VLHT + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLFT + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLHR + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLHT + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLLR + bool + +config SOC_PART_NUMBER_FS32K142UAT0VLLT + bool + +config SOC_PART_NUMBER_FS32K142UIT0VLHT + bool + +config SOC_PART_NUMBER_FS32K142WAT0WLFT + bool + +config SOC_PART_NUMBER_FS32K142WAT0WLHT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLFT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLHR + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K144HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K144HAT0MMHR + bool + +config SOC_PART_NUMBER_FS32K144HAT0MMHT + bool + +config SOC_PART_NUMBER_FS32K144HVT0VLHR + bool + +config SOC_PART_NUMBER_FS32K144HVT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144HXT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144HXT0VLLT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLFT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLHR + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VLLT + bool + +config SOC_PART_NUMBER_FS32K144UAT0VMHR + bool + +config SOC_PART_NUMBER_FS32K144UAT0VMHT + bool + +config SOC_PART_NUMBER_FS32K144UIT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144ULT0VLHT + bool + +config SOC_PART_NUMBER_FS32K144ULT0VLLR + bool + +config SOC_PART_NUMBER_FS32K144ULT0VLLT + bool + +config SOC_PART_NUMBER_FS32K144WAT0WLFT + bool + +config SOC_PART_NUMBER_FS32K144WAT0WLHT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLHR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLHT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLQR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MLQT + bool + +config SOC_PART_NUMBER_FS32K146HAT0MMHR + bool + +config SOC_PART_NUMBER_FS32K146HAT0MMHT + bool + +config SOC_PART_NUMBER_FS32K146HVT0VLHT + bool + +config SOC_PART_NUMBER_FS32K146HXT0VLLT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLHR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLHT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLLR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLLT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLQR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VLQT + bool + +config SOC_PART_NUMBER_FS32K146UAT0VMHR + bool + +config SOC_PART_NUMBER_FS32K146UAT0VMHT + bool + +config SOC_PART_NUMBER_FS32K146UIT0VLLT + bool + +config SOC_PART_NUMBER_FS32K146ULT0VLLT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLLR + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLLT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLQR + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLQT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MLUT + bool + +config SOC_PART_NUMBER_FS32K148HAT0MMHT + bool + +config SOC_PART_NUMBER_FS32K148UGT0VLQT + bool + +config SOC_PART_NUMBER_FS32K148UIT0VLQT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VLLT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VLQT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VLUT + bool + +config SOC_PART_NUMBER_FS32K148UJT0VMHR + bool + +config SOC_PART_NUMBER_FS32K148UJT0VMHT + bool + +config SOC_PART_NUMBER + default "FS32K116LAT0MFMT" if SOC_PART_NUMBER_FS32K116LAT0MFMT + default "FS32K116LAT0MLFR" if SOC_PART_NUMBER_FS32K116LAT0MLFR + default "FS32K116LAT0MLFT" if SOC_PART_NUMBER_FS32K116LAT0MLFT + default "FS32K116LIT0VFMT" if SOC_PART_NUMBER_FS32K116LIT0VFMT + default "FS32K116LIT0VLFT" if SOC_PART_NUMBER_FS32K116LIT0VLFT + default "FS32K118LAT0MLFR" if SOC_PART_NUMBER_FS32K118LAT0MLFR + default "FS32K118LAT0MLFT" if SOC_PART_NUMBER_FS32K118LAT0MLFT + default "FS32K118LAT0MLHR" if SOC_PART_NUMBER_FS32K118LAT0MLHR + default "FS32K118LAT0MLHT" if SOC_PART_NUMBER_FS32K118LAT0MLHT + default "FS32K118LIT0VLFT" if SOC_PART_NUMBER_FS32K118LIT0VLFT + default "FS32K142HAT0MLFT" if SOC_PART_NUMBER_FS32K142HAT0MLFT + default "FS32K142HAT0MLHT" if SOC_PART_NUMBER_FS32K142HAT0MLHT + default "FS32K142HAT0MLLR" if SOC_PART_NUMBER_FS32K142HAT0MLLR + default "FS32K142HAT0MLLT" if SOC_PART_NUMBER_FS32K142HAT0MLLT + default "FS32K142HVT0VLHT" if SOC_PART_NUMBER_FS32K142HVT0VLHT + default "FS32K142UAT0VLFT" if SOC_PART_NUMBER_FS32K142UAT0VLFT + default "FS32K142UAT0VLHR" if SOC_PART_NUMBER_FS32K142UAT0VLHR + default "FS32K142UAT0VLHT" if SOC_PART_NUMBER_FS32K142UAT0VLHT + default "FS32K142UAT0VLLR" if SOC_PART_NUMBER_FS32K142UAT0VLLR + default "FS32K142UAT0VLLT" if SOC_PART_NUMBER_FS32K142UAT0VLLT + default "FS32K142UIT0VLHT" if SOC_PART_NUMBER_FS32K142UIT0VLHT + default "FS32K142WAT0WLFT" if SOC_PART_NUMBER_FS32K142WAT0WLFT + default "FS32K142WAT0WLHT" if SOC_PART_NUMBER_FS32K142WAT0WLHT + default "FS32K144HAT0MLFT" if SOC_PART_NUMBER_FS32K144HAT0MLFT + default "FS32K144HAT0MLHR" if SOC_PART_NUMBER_FS32K144HAT0MLHR + default "FS32K144HAT0MLHT" if SOC_PART_NUMBER_FS32K144HAT0MLHT + default "FS32K144HAT0MLLR" if SOC_PART_NUMBER_FS32K144HAT0MLLR + default "FS32K144HAT0MLLT" if SOC_PART_NUMBER_FS32K144HAT0MLLT + default "FS32K144HAT0MMHR" if SOC_PART_NUMBER_FS32K144HAT0MMHR + default "FS32K144HAT0MMHT" if SOC_PART_NUMBER_FS32K144HAT0MMHT + default "FS32K144HVT0VLHR" if SOC_PART_NUMBER_FS32K144HVT0VLHR + default "FS32K144HVT0VLHT" if SOC_PART_NUMBER_FS32K144HVT0VLHT + default "FS32K144HXT0VLHT" if SOC_PART_NUMBER_FS32K144HXT0VLHT + default "FS32K144HXT0VLLT" if SOC_PART_NUMBER_FS32K144HXT0VLLT + default "FS32K144UAT0VLFT" if SOC_PART_NUMBER_FS32K144UAT0VLFT + default "FS32K144UAT0VLHR" if SOC_PART_NUMBER_FS32K144UAT0VLHR + default "FS32K144UAT0VLHT" if SOC_PART_NUMBER_FS32K144UAT0VLHT + default "FS32K144UAT0VLLT" if SOC_PART_NUMBER_FS32K144UAT0VLLT + default "FS32K144UAT0VMHR" if SOC_PART_NUMBER_FS32K144UAT0VMHR + default "FS32K144UAT0VMHT" if SOC_PART_NUMBER_FS32K144UAT0VMHT + default "FS32K144UIT0VLHT" if SOC_PART_NUMBER_FS32K144UIT0VLHT + default "FS32K144ULT0VLHT" if SOC_PART_NUMBER_FS32K144ULT0VLHT + default "FS32K144ULT0VLLR" if SOC_PART_NUMBER_FS32K144ULT0VLLR + default "FS32K144ULT0VLLT" if SOC_PART_NUMBER_FS32K144ULT0VLLT + default "FS32K144WAT0WLFT" if SOC_PART_NUMBER_FS32K144WAT0WLFT + default "FS32K144WAT0WLHT" if SOC_PART_NUMBER_FS32K144WAT0WLHT + default "FS32K146HAT0MLHR" if SOC_PART_NUMBER_FS32K146HAT0MLHR + default "FS32K146HAT0MLHT" if SOC_PART_NUMBER_FS32K146HAT0MLHT + default "FS32K146HAT0MLLR" if SOC_PART_NUMBER_FS32K146HAT0MLLR + default "FS32K146HAT0MLLT" if SOC_PART_NUMBER_FS32K146HAT0MLLT + default "FS32K146HAT0MLQR" if SOC_PART_NUMBER_FS32K146HAT0MLQR + default "FS32K146HAT0MLQT" if SOC_PART_NUMBER_FS32K146HAT0MLQT + default "FS32K146HAT0MMHR" if SOC_PART_NUMBER_FS32K146HAT0MMHR + default "FS32K146HAT0MMHT" if SOC_PART_NUMBER_FS32K146HAT0MMHT + default "FS32K146HVT0VLHT" if SOC_PART_NUMBER_FS32K146HVT0VLHT + default "FS32K146HXT0VLLT" if SOC_PART_NUMBER_FS32K146HXT0VLLT + default "FS32K146UAT0VLHR" if SOC_PART_NUMBER_FS32K146UAT0VLHR + default "FS32K146UAT0VLHT" if SOC_PART_NUMBER_FS32K146UAT0VLHT + default "FS32K146UAT0VLLR" if SOC_PART_NUMBER_FS32K146UAT0VLLR + default "FS32K146UAT0VLLT" if SOC_PART_NUMBER_FS32K146UAT0VLLT + default "FS32K146UAT0VLQR" if SOC_PART_NUMBER_FS32K146UAT0VLQR + default "FS32K146UAT0VLQT" if SOC_PART_NUMBER_FS32K146UAT0VLQT + default "FS32K146UAT0VMHR" if SOC_PART_NUMBER_FS32K146UAT0VMHR + default "FS32K146UAT0VMHT" if SOC_PART_NUMBER_FS32K146UAT0VMHT + default "FS32K146UIT0VLLT" if SOC_PART_NUMBER_FS32K146UIT0VLLT + default "FS32K146ULT0VLLT" if SOC_PART_NUMBER_FS32K146ULT0VLLT + default "FS32K148HAT0MLLR" if SOC_PART_NUMBER_FS32K148HAT0MLLR + default "FS32K148HAT0MLLT" if SOC_PART_NUMBER_FS32K148HAT0MLLT + default "FS32K148HAT0MLQR" if SOC_PART_NUMBER_FS32K148HAT0MLQR + default "FS32K148HAT0MLQT" if SOC_PART_NUMBER_FS32K148HAT0MLQT + default "FS32K148HAT0MLUT" if SOC_PART_NUMBER_FS32K148HAT0MLUT + default "FS32K148HAT0MMHT" if SOC_PART_NUMBER_FS32K148HAT0MMHT + default "FS32K148UGT0VLQT" if SOC_PART_NUMBER_FS32K148UGT0VLQT + default "FS32K148UIT0VLQT" if SOC_PART_NUMBER_FS32K148UIT0VLQT + default "FS32K148UJT0VLLT" if SOC_PART_NUMBER_FS32K148UJT0VLLT + default "FS32K148UJT0VLQT" if SOC_PART_NUMBER_FS32K148UJT0VLQT + default "FS32K148UJT0VLUT" if SOC_PART_NUMBER_FS32K148UJT0VLUT + default "FS32K148UJT0VMHR" if SOC_PART_NUMBER_FS32K148UJT0VMHR + default "FS32K148UJT0VMHT" if SOC_PART_NUMBER_FS32K148UJT0VMHT diff --git a/soc/arm/nxp_s32/s32k1/flash_config.ld b/soc/nxp/s32/s32k1/flash_config.ld similarity index 100% rename from soc/arm/nxp_s32/s32k1/flash_config.ld rename to soc/nxp/s32/s32k1/flash_config.ld diff --git a/soc/arm/nxp_s32/s32k1/flash_configuration.c b/soc/nxp/s32/s32k1/flash_configuration.c similarity index 100% rename from soc/arm/nxp_s32/s32k1/flash_configuration.c rename to soc/nxp/s32/s32k1/flash_configuration.c diff --git a/soc/arm/nxp_s32/s32k1/nxp_mpu_regions.c b/soc/nxp/s32/s32k1/nxp_mpu_regions.c similarity index 94% rename from soc/arm/nxp_s32/s32k1/nxp_mpu_regions.c rename to soc/nxp/s32/s32k1/nxp_mpu_regions.c index 5c8ac8de3b95b5..fb66036dfc7084 100644 --- a/soc/arm/nxp_s32/s32k1/nxp_mpu_regions.c +++ b/soc/nxp/s32/s32k1/nxp_mpu_regions.c @@ -1,7 +1,7 @@ /* * Copyright 2023 NXP * - * Based on soc/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c, which is: + * Based on soc/soc_legacy/arm/nxp_kinetis/ke1xf/nxp_mpu_regions.c, which is: * Copyright (c) 2017 Linaro Limited. * * SPDX-License-Identifier: Apache-2.0 diff --git a/soc/arm/nxp_s32/s32k1/pinctrl_soc.h b/soc/nxp/s32/s32k1/pinctrl_soc.h similarity index 100% rename from soc/arm/nxp_s32/s32k1/pinctrl_soc.h rename to soc/nxp/s32/s32k1/pinctrl_soc.h diff --git a/soc/nxp/s32/s32k1/soc.c b/soc/nxp/s32/s32k1/soc.c new file mode 100644 index 00000000000000..20a27eb13c0d84 --- /dev/null +++ b/soc/nxp/s32/s32k1/soc.c @@ -0,0 +1,78 @@ +/* + * Copyright 2023 NXP + * + * Based on zephyr/soc/soc_legacy/arm/nxp_kinetis/ke1xf/soc.c, which is: + * Copyright (c) 2019-2021 Vestas Wind Systems A/S + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include +#include + +#if defined(CONFIG_HAS_MCUX_CACHE) +#include +#endif + +#if defined(CONFIG_WDOG_INIT) +void z_arm_watchdog_init(void) +{ + /* + * NOTE: DO NOT SINGLE STEP THROUGH THIS SECTION!!! Watchdog + * reconfiguration must take place within 128 bus clocks from + * unlocking. Single stepping through the code will cause the + * watchdog to close the unlock window again. + */ + if ((IP_WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U) { + IP_WDOG->CNT = WDOG_UPDATE_KEY; + } else { + IP_WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU; + IP_WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU; + } + while (!(IP_WDOG->CS & WDOG_CS_ULK_MASK)) { + ; + } + + IP_WDOG->TOVAL = 0xFFFFU; + IP_WDOG->CS = (uint32_t) ((IP_WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK; + + /* Wait for new configuration to take effect */ + while (!(IP_WDOG->CS & WDOG_CS_RCS_MASK)) { + ; + } +} +#endif /* CONFIG_WDOG_INIT */ + +static int soc_init(void) +{ +#if !defined(CONFIG_ARM_MPU) + uint32_t tmp; + + /* + * Disable memory protection and clear slave port errors. + * Note that the S32K1xx does not implement the optional Arm MPU but + * instead the Soc includes its own NXP MPU module. + */ + tmp = IP_MPU->CESR; + tmp &= ~MPU_CESR_VLD_MASK; + tmp |= MPU_CESR_SPERR0_MASK | MPU_CESR_SPERR1_MASK + | MPU_CESR_SPERR2_MASK | MPU_CESR_SPERR3_MASK; + IP_MPU->CESR = tmp; +#endif /* !CONFIG_ARM_MPU */ + +#if defined(CONFIG_HAS_MCUX_CACHE) && defined(CONFIG_NXP_S32_ENABLE_CODE_CACHE) + L1CACHE_EnableCodeCache(); + barrier_isync_fence_full(); +#endif + + OsIf_Init(NULL); + + return 0; +} + +SYS_INIT(soc_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/nxp_s32/s32k1/soc.h b/soc/nxp/s32/s32k1/soc.h similarity index 100% rename from soc/arm/nxp_s32/s32k1/soc.h rename to soc/nxp/s32/s32k1/soc.h diff --git a/soc/nxp/s32/s32k3/CMakeLists.txt b/soc/nxp/s32/s32k3/CMakeLists.txt new file mode 100644 index 00000000000000..4d18223a61c675 --- /dev/null +++ b/soc/nxp/s32/s32k3/CMakeLists.txt @@ -0,0 +1,13 @@ +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_include_directories(.) + +zephyr_library_sources(soc.c) +zephyr_library_sources_ifdef(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS mpu_regions.c) +zephyr_linker_sources(SECTIONS sections.ld) +zephyr_library_sources_ifdef(CONFIG_PLATFORM_SPECIFIC_INIT s32k3xx_startup.S) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/s32/s32k3/Kconfig b/soc/nxp/s32/s32k3/Kconfig new file mode 100644 index 00000000000000..0ca5882062c33e --- /dev/null +++ b/soc/nxp/s32/s32k3/Kconfig @@ -0,0 +1,60 @@ +# NXP S32K3XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K3 + select ARM + select CPU_CORTEX_M7 + select HAS_NXP_S32_HAL + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select PLATFORM_SPECIFIC_INIT if XIP + select USE_DT_CODE_PARTITION if XIP + select CLOCK_CONTROL + select HAS_MCUX + select HAS_MCUX_LPUART + select HAS_MCUX_FLEXCAN + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_CACHE + +if SOC_SERIES_S32K3 + +config IVT_HEADER_OFFSET + hex + depends on XIP + default $(dt_node_reg_addr_hex,$(dt_nodelabel_path,ivt_header)) + help + The offset address from flash base address for ivt header + +config IVT_HEADER_SIZE + hex + depends on XIP + default $(dt_node_reg_size_hex,$(dt_nodelabel_path,ivt_header)) + help + Size of ivt header region + +config NXP_S32_PMC_LMEN + bool "Last Mile regulator" + default y if CLOCK_CONTROL + help + Enables the Last Mile regulator, which regulates an external 1.5V + voltage on V15 down to the core and logic supply (V11 power domain), + which is typically 1.1V. + When enabling PLL as system clock, the PMC last mile regulator should + be enabled. + +config NXP_S32_PMC_LMBCTLEN + bool "External BCTL regulator for V15" + depends on NXP_S32_PMC_LMEN + help + This option must be selected if an external BJT between VDD_HV_A and + V15 is used on the PCB. The base of this BJT must be connected to the + VRC_CTRL pin and is controlled by the PMC to regulate a voltage of + 1.5V on V15 pin. + +endif # SOC_SERIES_S32K3 diff --git a/soc/nxp/s32/s32k3/Kconfig.defconfig b/soc/nxp/s32/s32k3/Kconfig.defconfig new file mode 100644 index 00000000000000..6c58f348ea64b3 --- /dev/null +++ b/soc/nxp/s32/s32k3/Kconfig.defconfig @@ -0,0 +1,38 @@ +# NXP S32K3XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_S32K3 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 2000000 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 239 + +config FPU + default y + +if !XIP +config FLASH_SIZE + default 0 +config FLASH_BASE_ADDRESS + default 0 +endif + +if NET_L2_ETHERNET + +config NET_TCP_CHECKSUM + default n + +config NET_UDP_CHECKSUM + default n + +endif # NET_L2_ETHERNET + +config CACHE_MANAGEMENT + default y + +endif # SOC_SERIES_S32K3 diff --git a/soc/nxp/s32/s32k3/Kconfig.soc b/soc/nxp/s32/s32k3/Kconfig.soc new file mode 100644 index 00000000000000..164edf56231c3a --- /dev/null +++ b/soc/nxp/s32/s32k3/Kconfig.soc @@ -0,0 +1,24 @@ +# NXP S32K3XX MCU series + +# Copyright 2023-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32K3 + bool + select SOC_FAMILY_NXP_S32 + +config SOC_SERIES + default "s32k3" if SOC_SERIES_S32K3 + +config SOC_S32K344 + bool + select SOC_SERIES_S32K3 + +config SOC + default "s32k344" if SOC_S32K344 + +config SOC_PART_NUMBER_PS32K344EHVPBS + bool + +config SOC_PART_NUMBER + default "PS32K344EHVPBS" if SOC_PART_NUMBER_PS32K344EHVPBS diff --git a/soc/arm/nxp_s32/s32k3/linker.ld b/soc/nxp/s32/s32k3/linker.ld similarity index 100% rename from soc/arm/nxp_s32/s32k3/linker.ld rename to soc/nxp/s32/s32k3/linker.ld diff --git a/soc/arm/nxp_s32/s32k3/mpu_regions.c b/soc/nxp/s32/s32k3/mpu_regions.c similarity index 100% rename from soc/arm/nxp_s32/s32k3/mpu_regions.c rename to soc/nxp/s32/s32k3/mpu_regions.c diff --git a/soc/arm/nxp_s32/s32k3/s32k3xx_startup.S b/soc/nxp/s32/s32k3/s32k3xx_startup.S similarity index 100% rename from soc/arm/nxp_s32/s32k3/s32k3xx_startup.S rename to soc/nxp/s32/s32k3/s32k3xx_startup.S diff --git a/soc/arm/nxp_s32/s32k3/sections.ld b/soc/nxp/s32/s32k3/sections.ld similarity index 100% rename from soc/arm/nxp_s32/s32k3/sections.ld rename to soc/nxp/s32/s32k3/sections.ld diff --git a/soc/arm/nxp_s32/s32k3/soc.c b/soc/nxp/s32/s32k3/soc.c similarity index 100% rename from soc/arm/nxp_s32/s32k3/soc.c rename to soc/nxp/s32/s32k3/soc.c diff --git a/soc/arm/nxp_s32/s32k3/soc.h b/soc/nxp/s32/s32k3/soc.h similarity index 100% rename from soc/arm/nxp_s32/s32k3/soc.h rename to soc/nxp/s32/s32k3/soc.h diff --git a/soc/nxp/s32/s32ze/CMakeLists.txt b/soc/nxp/s32/s32ze/CMakeLists.txt new file mode 100644 index 00000000000000..b7ce37a2f00777 --- /dev/null +++ b/soc/nxp/s32/s32ze/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_library_sources( + soc.c +) + +zephyr_library_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/s32/s32ze/Kconfig b/soc/nxp/s32/s32ze/Kconfig new file mode 100644 index 00000000000000..5adac36dce4dfe --- /dev/null +++ b/soc/nxp/s32/s32ze/Kconfig @@ -0,0 +1,30 @@ +# NXP S32ZE MCUs series + +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32ZE + select ARM + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select CPU_CORTEX_R52 + select CPU_HAS_DCLS + select CPU_HAS_ARM_MPU + select GIC_SINGLE_SECURITY_STATE + select VFP_DP_D16 + select PLATFORM_SPECIFIC_INIT + select CLOCK_CONTROL + select HAS_NXP_S32_HAL + select HAS_MCUX + select HAS_MCUX_PIT + +if SOC_SERIES_S32ZE + +config NXP_S32_RTU_INDEX + int + range 0 1 + default 0 if SOC_S32Z270_RTU0 + default 1 if SOC_S32Z270_RTU1 + help + This option indicates the index of the target RTU (Real-Time Unit) subsystem. + +endif # SOC_SERIES_S32ZE diff --git a/soc/nxp/s32/s32ze/Kconfig.defconfig b/soc/nxp/s32/s32ze/Kconfig.defconfig new file mode 100644 index 00000000000000..7deb599e3a24e7 --- /dev/null +++ b/soc/nxp/s32/s32ze/Kconfig.defconfig @@ -0,0 +1,40 @@ +# NXP S32ZE MCUs series + +# Copyright 2022,2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_S32ZE + +config NUM_IRQS + # must be >= the highest interrupt number used + default 991 + +config FPU + default y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 2000000 + +config MAIN_STACK_SIZE + default 1024 + +if !XIP +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 +endif # !XIP + +if NET_L2_ETHERNET + +# NETC drops TCP/UDP packets with invalid checksum +config NET_TCP_CHECKSUM + default n + +config NET_UDP_CHECKSUM + default n + +endif # NET_L2_ETHERNET + +endif # SOC_SERIES_S32ZE diff --git a/soc/nxp/s32/s32ze/Kconfig.soc b/soc/nxp/s32/s32ze/Kconfig.soc new file mode 100644 index 00000000000000..8578508ddb172b --- /dev/null +++ b/soc/nxp/s32/s32ze/Kconfig.soc @@ -0,0 +1,32 @@ +# NXP S32ZE MCUs series + +# Copyright 2022-2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_S32ZE + bool + select SOC_FAMILY_NXP_S32 + +config SOC_SERIES + default "s32ze" if SOC_SERIES_S32ZE + +config SOC_S32Z270 + bool + select SOC_SERIES_S32ZE + +config SOC_S32Z270_RTU0 + bool + select SOC_S32Z270 + +config SOC_S32Z270_RTU1 + bool + select SOC_S32Z270 + +config SOC + default "s32z270" if SOC_S32Z270 + +config SOC_PART_NUMBER_P32Z270ADCK0MJFT + bool + +config SOC_PART_NUMBER + default "P32Z270ADCK0MJFT" if SOC_PART_NUMBER_P32Z270ADCK0MJFT diff --git a/soc/arm/nxp_s32/s32ze/mpu_regions.c b/soc/nxp/s32/s32ze/mpu_regions.c similarity index 100% rename from soc/arm/nxp_s32/s32ze/mpu_regions.c rename to soc/nxp/s32/s32ze/mpu_regions.c diff --git a/soc/arm/nxp_s32/s32ze/soc.c b/soc/nxp/s32/s32ze/soc.c similarity index 100% rename from soc/arm/nxp_s32/s32ze/soc.c rename to soc/nxp/s32/s32ze/soc.c diff --git a/soc/nxp/s32/s32ze/soc.h b/soc/nxp/s32/s32ze/soc.h new file mode 100644 index 00000000000000..57e8fb0b8b87da --- /dev/null +++ b/soc/nxp/s32/s32ze/soc.h @@ -0,0 +1,74 @@ +/* + * Copyright 2022-2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef _NXP_S32_S32ZE_SOC_H_ +#define _NXP_S32_S32ZE_SOC_H_ + +/* Do not let CMSIS to handle GIC */ +#define __GIC_PRESENT 0 + +#if defined(CONFIG_SOC_S32Z270) +#include +#else +#error "SoC not supported" +#endif + +#if defined(CONFIG_CMSIS_RTOS_V2) +#include +#endif + +/* Aliases for peripheral base addresses */ + +/* SIUL2 */ +#define IP_SIUL2_2_BASE 0U /* instance does not exist on this SoC */ + +/* LINFlexD*/ +#define IP_LINFLEX_12_BASE IP_MSC_0_LIN_BASE + +/* SWT */ +#define IP_SWT_0_BASE IP_CE_SWT_0_BASE +#define IP_SWT_1_BASE IP_CE_SWT_1_BASE +#define IP_SWT_2_BASE IP_RTU0__SWT_0_BASE +#define IP_SWT_3_BASE IP_RTU0__SWT_1_BASE +#define IP_SWT_4_BASE IP_RTU0__SWT_2_BASE +#define IP_SWT_5_BASE IP_RTU0__SWT_3_BASE +#define IP_SWT_6_BASE IP_RTU0__SWT_4_BASE +#define IP_SWT_7_BASE IP_RTU1__SWT_0_BASE +#define IP_SWT_8_BASE IP_RTU1__SWT_1_BASE +#define IP_SWT_9_BASE IP_RTU1__SWT_2_BASE +#define IP_SWT_10_BASE IP_RTU1__SWT_3_BASE +#define IP_SWT_11_BASE IP_RTU1__SWT_4_BASE +#define IP_SWT_12_BASE IP_SMU__SWT_BASE + +/* STM */ +#define IP_STM_0_BASE IP_CE_STM_0_BASE +#define IP_STM_1_BASE IP_CE_STM_1_BASE +#define IP_STM_2_BASE IP_CE_STM_2_BASE +#define IP_STM_3_BASE IP_RTU0__STM_0_BASE +#define IP_STM_4_BASE IP_RTU0__STM_1_BASE +#define IP_STM_5_BASE IP_RTU0__STM_2_BASE +#define IP_STM_6_BASE IP_RTU0__STM_3_BASE +#define IP_STM_7_BASE IP_RTU1__STM_0_BASE +#define IP_STM_8_BASE IP_RTU1__STM_1_BASE +#define IP_STM_9_BASE IP_RTU1__STM_2_BASE +#define IP_STM_10_BASE IP_RTU1__STM_3_BASE +#define IP_STM_11_BASE IP_SMU__STM_0_BASE +#define IP_STM_12_BASE IP_SMU__STM_2_BASE + +/* NETC */ +#define IP_NETC_EMDIO_0_BASE IP_NETC__EMDIO_BASE_BASE + +/* MRU */ +#define IP_MRU_0_BASE IP_RTU0__MRU_0_BASE +#define IP_MRU_1_BASE IP_RTU0__MRU_1_BASE +#define IP_MRU_2_BASE IP_RTU0__MRU_2_BASE +#define IP_MRU_3_BASE IP_RTU0__MRU_3_BASE +#define IP_MRU_4_BASE IP_RTU1__MRU_0_BASE +#define IP_MRU_5_BASE IP_RTU1__MRU_1_BASE +#define IP_MRU_6_BASE IP_RTU1__MRU_2_BASE +#define IP_MRU_7_BASE IP_RTU1__MRU_3_BASE + +#endif /* _NXP_S32_S32ZE_SOC_H_ */ diff --git a/soc/nxp/s32/soc.yml b/soc/nxp/s32/soc.yml new file mode 100644 index 00000000000000..8d71e2b53aa60d --- /dev/null +++ b/soc/nxp/s32/soc.yml @@ -0,0 +1,22 @@ +family: +- name: nxp_s32 + series: + - name: s32k1 + socs: + - name: s32k116 + - name: s32k118 + - name: s32k142 + - name: s32k142w + - name: s32k144 + - name: s32k144w + - name: s32k146 + - name: s32k148 + - name: s32k3 + socs: + - name: s32k344 + - name: s32ze + socs: + - name: s32z270 + cpuclusters: + - name: rtu0 + - name: rtu1 diff --git a/soc/openisa/rv32m1/CMakeLists.txt b/soc/openisa/rv32m1/CMakeLists.txt new file mode 100644 index 00000000000000..cd65ea9d62868d --- /dev/null +++ b/soc/openisa/rv32m1/CMakeLists.txt @@ -0,0 +1,26 @@ +# Copyright (c) 2018 Foundries.io Ltd +# +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) + if (CONFIG_RISCV_GENERIC_TOOLCHAIN) + zephyr_compile_options(-march=rv32imc_zicsr_zifencei) + else() + zephyr_compile_options(-march=rv32imcxpulpv2) + endif() +elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) + zephyr_compile_options(-march=rv32imc_zicsr_zifencei) +endif() + +zephyr_sources( + vector.S + soc_irq.S + wdog.S + soc.c +) + +zephyr_include_directories(.) + +zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/openisa/rv32m1/Kconfig b/soc/openisa/rv32m1/Kconfig new file mode 100644 index 00000000000000..21fe5d9297d942 --- /dev/null +++ b/soc/openisa/rv32m1/Kconfig @@ -0,0 +1,22 @@ +# Copyright (c) 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENISA_RV32M1 + select RISCV + select XIP + select HAS_RV32M1_LPUART + select HAS_RV32M1_LPI2C + select HAS_RV32M1_LPSPI + select HAS_RV32M1_TPM + select ATOMIC_OPERATIONS_C + select VEGA_SDK_HAL + select RISCV_SOC_INTERRUPT_INIT + select CLOCK_CONTROL + select HAS_RV32M1_FTFX + select HAS_FLASH_LOAD_OFFSET + select BUILD_OUTPUT_HEX + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/openisa/rv32m1/Kconfig.defconfig b/soc/openisa/rv32m1/Kconfig.defconfig new file mode 100644 index 00000000000000..10d6bca39d5d3e --- /dev/null +++ b/soc/openisa/rv32m1/Kconfig.defconfig @@ -0,0 +1,122 @@ +# RV32M1 SoC RISC-V core default configuration values + +# Copyright (c) 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +if SOC_OPENISA_RV32M1 + +# 32 from event unit + 32 * (1 + max enabled INTMUX channel) +config NUM_IRQS + default 288 if RV32M1_INTMUX_CHANNEL_7 + default 256 if RV32M1_INTMUX_CHANNEL_6 + default 224 if RV32M1_INTMUX_CHANNEL_5 + default 192 if RV32M1_INTMUX_CHANNEL_4 + default 160 if RV32M1_INTMUX_CHANNEL_3 + default 128 if RV32M1_INTMUX_CHANNEL_2 + default 96 if RV32M1_INTMUX_CHANNEL_1 + default 64 if RV32M1_INTMUX_CHANNEL_0 + default 32 + +config RISCV_GENERIC_TOOLCHAIN + default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" + default n + +config RISCV_SOC_CONTEXT_SAVE + default y if SOC_OPENISA_RV32M1_RI5CY + +config RISCV_SOC_OFFSETS + default y + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_MCAUSE_EXCEPTION_MASK + default 0x1F + +# We need to disable the watchdog out of reset, as it's enabled by +# default. Use the WDOG_INIT hook for doing that. +config WDOG_INIT + def_bool y + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 8000000 + +if MULTI_LEVEL_INTERRUPTS + +config MAX_IRQ_PER_AGGREGATOR + default 32 + +config 2ND_LEVEL_INTERRUPTS + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 32 + +config NUM_2ND_LEVEL_AGGREGATORS + default 8 if RV32M1_INTMUX_CHANNEL_7 + default 7 if RV32M1_INTMUX_CHANNEL_6 + default 6 if RV32M1_INTMUX_CHANNEL_5 + default 5 if RV32M1_INTMUX_CHANNEL_4 + default 4 if RV32M1_INTMUX_CHANNEL_3 + default 3 if RV32M1_INTMUX_CHANNEL_2 + default 2 if RV32M1_INTMUX_CHANNEL_1 + default 1 # just channel 0 + +config 2ND_LVL_INTR_00_OFFSET + default 24 + +config 2ND_LVL_INTR_01_OFFSET + int + default 25 + +config 2ND_LVL_INTR_02_OFFSET + int + default 26 + +config 2ND_LVL_INTR_03_OFFSET + int + default 27 + +config 2ND_LVL_INTR_04_OFFSET + int + default 28 + +config 2ND_LVL_INTR_05_OFFSET + int + default 29 + +config 2ND_LVL_INTR_06_OFFSET + int + default 30 + +config 2ND_LVL_INTR_07_OFFSET + int + default 31 + +config RV32M1_INTMUX_CHANNEL_0 + default y + +config RV32M1_INTMUX_CHANNEL_1 + default y + +config RV32M1_INTMUX_CHANNEL_2 + default y + +config RV32M1_INTMUX_CHANNEL_3 + default y + +config RV32M1_INTMUX_CHANNEL_4 + default y + +config RV32M1_INTMUX_CHANNEL_5 + default y + +config RV32M1_INTMUX_CHANNEL_6 + default y + +config RV32M1_INTMUX_CHANNEL_7 + default y + +endif # MULTI_LEVEL_INTERRUPTS + +endif # SOC_OPENISA_RV32M1 diff --git a/soc/openisa/rv32m1/Kconfig.soc b/soc/openisa/rv32m1/Kconfig.soc new file mode 100644 index 00000000000000..0144d82b011651 --- /dev/null +++ b/soc/openisa/rv32m1/Kconfig.soc @@ -0,0 +1,24 @@ +# Copyright (c) 2018 Foundries.io Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_OPENISA_RV32M1 + bool + help + Enable support for OpenISA RV32M1 RISC-V processors. Choose + this option to target the RI5CY or ZERO-RISCY core. This + option should not be used to target either Arm core. + +config SOC_OPENISA_RV32M1_RI5CY + bool + select SOC_OPENISA_RV32M1 + help + OpenISA RV32M1 RI5CY core + +config SOC_OPENISA_RV32M1_ZERO_RISCY + bool + select SOC_OPENISA_RV32M1 + help + OpenISA RV32M1 ZERO-RISCY core + +config SOC + default "openisa_rv32m1" if SOC_OPENISA_RV32M1 diff --git a/soc/riscv/openisa_rv32m1/linker.ld b/soc/openisa/rv32m1/linker.ld similarity index 100% rename from soc/riscv/openisa_rv32m1/linker.ld rename to soc/openisa/rv32m1/linker.ld diff --git a/soc/riscv/openisa_rv32m1/pinctrl_soc.h b/soc/openisa/rv32m1/pinctrl_soc.h similarity index 100% rename from soc/riscv/openisa_rv32m1/pinctrl_soc.h rename to soc/openisa/rv32m1/pinctrl_soc.h diff --git a/soc/riscv/openisa_rv32m1/soc.c b/soc/openisa/rv32m1/soc.c similarity index 100% rename from soc/riscv/openisa_rv32m1/soc.c rename to soc/openisa/rv32m1/soc.c diff --git a/soc/riscv/openisa_rv32m1/soc.h b/soc/openisa/rv32m1/soc.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc.h rename to soc/openisa/rv32m1/soc.h diff --git a/soc/openisa/rv32m1/soc.yml b/soc/openisa/rv32m1/soc.yml new file mode 100644 index 00000000000000..135006f7eb9917 --- /dev/null +++ b/soc/openisa/rv32m1/soc.yml @@ -0,0 +1,5 @@ +socs: +- name: openisa_rv32m1 + cpuclusters: + - name: zero_riscy + - name: ri5cy diff --git a/soc/riscv/openisa_rv32m1/soc_context.h b/soc/openisa/rv32m1/soc_context.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_context.h rename to soc/openisa/rv32m1/soc_context.h diff --git a/soc/riscv/openisa_rv32m1/soc_irq.S b/soc/openisa/rv32m1/soc_irq.S similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_irq.S rename to soc/openisa/rv32m1/soc_irq.S diff --git a/soc/riscv/openisa_rv32m1/soc_offsets.h b/soc/openisa/rv32m1/soc_offsets.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_offsets.h rename to soc/openisa/rv32m1/soc_offsets.h diff --git a/soc/riscv/openisa_rv32m1/soc_ri5cy.h b/soc/openisa/rv32m1/soc_ri5cy.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_ri5cy.h rename to soc/openisa/rv32m1/soc_ri5cy.h diff --git a/soc/riscv/openisa_rv32m1/soc_zero_riscy.h b/soc/openisa/rv32m1/soc_zero_riscy.h similarity index 100% rename from soc/riscv/openisa_rv32m1/soc_zero_riscy.h rename to soc/openisa/rv32m1/soc_zero_riscy.h diff --git a/soc/riscv/openisa_rv32m1/vector.S b/soc/openisa/rv32m1/vector.S similarity index 100% rename from soc/riscv/openisa_rv32m1/vector.S rename to soc/openisa/rv32m1/vector.S diff --git a/soc/riscv/openisa_rv32m1/vector_table.ld b/soc/openisa/rv32m1/vector_table.ld similarity index 100% rename from soc/riscv/openisa_rv32m1/vector_table.ld rename to soc/openisa/rv32m1/vector_table.ld diff --git a/soc/riscv/openisa_rv32m1/wdog.S b/soc/openisa/rv32m1/wdog.S similarity index 100% rename from soc/riscv/openisa_rv32m1/wdog.S rename to soc/openisa/rv32m1/wdog.S diff --git a/soc/posix/CMakeLists.txt b/soc/posix/CMakeLists.txt deleted file mode 100644 index b42e9be886372e..00000000000000 --- a/soc/posix/CMakeLists.txt +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() - diff --git a/soc/posix/inf_clock/CMakeLists.txt b/soc/posix/inf_clock/CMakeLists.txt deleted file mode 100644 index 5bc6ab3c428c6d..00000000000000 --- a/soc/posix/inf_clock/CMakeLists.txt +++ /dev/null @@ -1,17 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() - -zephyr_library_compile_definitions(NO_POSIX_CHEATS) - -zephyr_library_sources( - soc.c - native_tasks.c - ) - -zephyr_library_include_directories( - ${ZEPHYR_BASE}/kernel/include - ${ZEPHYR_BASE}/arch/posix/include - ) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/posix/linker.ld CACHE INTERNAL "") diff --git a/soc/posix/inf_clock/Kconfig b/soc/posix/inf_clock/Kconfig deleted file mode 100644 index 27a5d511ec5bee..00000000000000 --- a/soc/posix/inf_clock/Kconfig +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2023 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config NATIVE_SIMULATOR_MCU_N - int "CPU Number this image targets" - range 0 15 - default 0 - depends on NATIVE_LIBRARY - help - Which native simulator microcontroller/CPU number is this image targeting. - This option is only applicable for targets which use the - native simulator as their runner. - -config NATIVE_SIMULATOR_NUMBER_MCUS - int "Total number of MCUs this target has" - range 1 16 - default 1 - depends on NATIVE_LIBRARY - help - How many AMP MCUs does this target have in total. - -config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX - int "Which CPU is the primary/preferred" - default 0 - depends on NATIVE_LIBRARY - help - On a multi MCU device, which MCU is the preferred one. - This MCU will for example have its tests command line parameters presented - without any prefix. Note that an MCU being primary does not imply it will be - the first one to boot, or even that it will boot automatically. - -config NATIVE_SIMULATOR_EXTRA_IMAGE_PATHS - string "Other cores images to include" - depends on NATIVE_LIBRARY - help - This option can be used to provide the native simulator with other MCUs/Cores images which have - been produced by either other Zephyr builds or different OS builds. - So you can, for ex., use this application build to produce one core image, and at the same time - have it produce the final link with the native simulator runner and the other MCU images. - -config NATIVE_SIMULATOR_AUTOSTART_MCU - bool "Auto-start this MCU" - depends on NATIVE_LIBRARY - help - Automatically start the MCU this Zephyr image is built for during HW boot, - even if in other circumstances this MCU would not start automatically (for ex. because - another core is meant to release its reset). - If that MCU was, by HW design, going to start at HW boot anyhow, this option does nothing. - This option is meant to facilitate development. diff --git a/soc/posix/inf_clock/Kconfig.defconfig b/soc/posix/inf_clock/Kconfig.defconfig deleted file mode 100644 index fd74815c4a6981..00000000000000 --- a/soc/posix/inf_clock/Kconfig.defconfig +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "inf_clock" - depends on SOC_POSIX diff --git a/soc/posix/inf_clock/Kconfig.soc b/soc/posix/inf_clock/Kconfig.soc deleted file mode 100644 index 5c300b6eaff858..00000000000000 --- a/soc/posix/inf_clock/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_POSIX - bool "Native port" - select ARCH_POSIX - select CPU_HAS_FPU - help - SOC for to the POSIX arch. It emulates a CPU running at an infinitely fast - clock. That means the CPU will always run in zero time until completion after - each wake reason (e.g. interrupts), before going back to idle. Note that an - infinite loop in the code which does not sleep the CPU will cause the process - to appear "hung", as simulated time does not advance while the CPU does not - sleep. Therefore do not use busy waits while waiting for something to happen - (if needed use k_busy_wait()). - Note that the interrupt handling is provided by the board. diff --git a/soc/qemu_malta/CMakeLists.txt b/soc/qemu_malta/CMakeLists.txt new file mode 100644 index 00000000000000..fd24f78c41d7b5 --- /dev/null +++ b/soc/qemu_malta/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2020, 2021 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_compile_options( + -mips32 + ${TOOLCHAIN_C_FLAGS} +) + +zephyr_sources( + vector.S +) + +zephyr_ld_options( + -mips32 + ${TOOLCHAIN_LD_FLAGS} +) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/mips/linker.ld CACHE INTERNAL "") diff --git a/soc/qemu_malta/Kconfig b/soc/qemu_malta/Kconfig new file mode 100644 index 00000000000000..f113aed676473c --- /dev/null +++ b/soc/qemu_malta/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_MALTA + select MIPS diff --git a/soc/qemu_malta/Kconfig.defconfig b/soc/qemu_malta/Kconfig.defconfig new file mode 100644 index 00000000000000..6eb3470689dbd9 --- /dev/null +++ b/soc/qemu_malta/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_MALTA + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 200000000 + +config NUM_IRQS + default 8 + +endif # SOC_QEMU_MALTA diff --git a/soc/qemu_malta/Kconfig.soc b/soc/qemu_malta/Kconfig.soc new file mode 100644 index 00000000000000..2ffbdea589d8cd --- /dev/null +++ b/soc/qemu_malta/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2020 Antony Pavlov +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_MALTA + bool + +config SOC + default "qemu_malta" if SOC_QEMU_MALTA diff --git a/soc/mips/qemu_malta/soc.h b/soc/qemu_malta/soc.h similarity index 100% rename from soc/mips/qemu_malta/soc.h rename to soc/qemu_malta/soc.h diff --git a/soc/qemu_malta/soc.yml b/soc/qemu_malta/soc.yml new file mode 100644 index 00000000000000..0ba23c27381094 --- /dev/null +++ b/soc/qemu_malta/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: qemu_malta diff --git a/soc/mips/qemu_malta/vector.S b/soc/qemu_malta/vector.S similarity index 100% rename from soc/mips/qemu_malta/vector.S rename to soc/qemu_malta/vector.S diff --git a/soc/quicklogic/eos_s3/CMakeLists.txt b/soc/quicklogic/eos_s3/CMakeLists.txt new file mode 100644 index 00000000000000..5c821692a4bcd8 --- /dev/null +++ b/soc/quicklogic/eos_s3/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/quicklogic/eos_s3/Kconfig b/soc/quicklogic/eos_s3/Kconfig new file mode 100644 index 00000000000000..e294a43277845e --- /dev/null +++ b/soc/quicklogic/eos_s3/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EOS_S3 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select EOS_S3_HAL diff --git a/soc/quicklogic/eos_s3/Kconfig.defconfig b/soc/quicklogic/eos_s3/Kconfig.defconfig new file mode 100644 index 00000000000000..2d4f48b45e3bd5 --- /dev/null +++ b/soc/quicklogic/eos_s3/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EOS_S3 + +config NUM_IRQS + default 52 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 61440000 + +if SERIAL + +config UART_INTERRUPT_DRIVEN + default y + +endif # SERIAL + +endif # SOC_EOS_S3 diff --git a/soc/quicklogic/eos_s3/Kconfig.soc b/soc/quicklogic/eos_s3/Kconfig.soc new file mode 100644 index 00000000000000..0f762d3927e60f --- /dev/null +++ b/soc/quicklogic/eos_s3/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2020 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EOS_S3 + bool + help + QuickLogic EOS S3 SoC + +config SOC + default "quicklogic_eos_s3" if SOC_EOS_S3 diff --git a/soc/arm/quicklogic_eos_s3/pinctrl_soc.h b/soc/quicklogic/eos_s3/pinctrl_soc.h similarity index 100% rename from soc/arm/quicklogic_eos_s3/pinctrl_soc.h rename to soc/quicklogic/eos_s3/pinctrl_soc.h diff --git a/soc/arm/quicklogic_eos_s3/soc.c b/soc/quicklogic/eos_s3/soc.c similarity index 100% rename from soc/arm/quicklogic_eos_s3/soc.c rename to soc/quicklogic/eos_s3/soc.c diff --git a/soc/arm/quicklogic_eos_s3/soc.h b/soc/quicklogic/eos_s3/soc.h similarity index 100% rename from soc/arm/quicklogic_eos_s3/soc.h rename to soc/quicklogic/eos_s3/soc.h diff --git a/soc/quicklogic/eos_s3/soc.yml b/soc/quicklogic/eos_s3/soc.yml new file mode 100644 index 00000000000000..6a21734180763b --- /dev/null +++ b/soc/quicklogic/eos_s3/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: quicklogic_eos_s3 diff --git a/soc/arm/quicklogic_eos_s3/soc_pinmap.h b/soc/quicklogic/eos_s3/soc_pinmap.h similarity index 100% rename from soc/arm/quicklogic_eos_s3/soc_pinmap.h rename to soc/quicklogic/eos_s3/soc_pinmap.h diff --git a/soc/arm/bcm_vk/CMakeLists.txt b/soc/raspberrypi/CMakeLists.txt similarity index 100% rename from soc/arm/bcm_vk/CMakeLists.txt rename to soc/raspberrypi/CMakeLists.txt diff --git a/soc/raspberrypi/Kconfig b/soc/raspberrypi/Kconfig new file mode 100644 index 00000000000000..2085e72f2b1343 --- /dev/null +++ b/soc/raspberrypi/Kconfig @@ -0,0 +1,11 @@ +# Raspberry Pi (RP) MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RPI_PICO + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RPI_PICO diff --git a/soc/raspberrypi/Kconfig.defconfig b/soc/raspberrypi/Kconfig.defconfig new file mode 100644 index 00000000000000..6cc52817a8f9d5 --- /dev/null +++ b/soc/raspberrypi/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Raspberry Pi (RP) MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RPI_PICO + +rsource "*/Kconfig.defconfig" + +config PINCTRL + default y + +endif # SOC_FAMILY_RPI_PICO diff --git a/soc/raspberrypi/Kconfig.soc b/soc/raspberrypi/Kconfig.soc new file mode 100644 index 00000000000000..b0b8b7b761feab --- /dev/null +++ b/soc/raspberrypi/Kconfig.soc @@ -0,0 +1,12 @@ +# Raspberry Pi (RP) MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RPI_PICO + bool + +config SOC_FAMILY + default "rpi_pico" if SOC_FAMILY_RPI_PICO + +rsource "*/Kconfig.soc" diff --git a/soc/raspberrypi/rp2xxx/CMakeLists.txt b/soc/raspberrypi/rp2xxx/CMakeLists.txt new file mode 100644 index 00000000000000..8f48fc01aba957 --- /dev/null +++ b/soc/raspberrypi/rp2xxx/CMakeLists.txt @@ -0,0 +1,10 @@ +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/raspberrypi/rp2xxx/Kconfig b/soc/raspberrypi/rp2xxx/Kconfig new file mode 100644 index 00000000000000..1abc32af2ceee4 --- /dev/null +++ b/soc/raspberrypi/rp2xxx/Kconfig @@ -0,0 +1,53 @@ +# Raspberry Pi RP2XXX MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RP2XXX + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select HAS_RPI_PICO + select XIP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + help + Enable support for Raspberry Pi RP2 MCU series + +config RP2_REQUIRES_SECOND_STAGE_BOOT + bool + default y if FLASH_LOAD_OFFSET = 0x100 + +# Flash type used by the SoC. The board should select the one used. + +config RP2_FLASH_W25Q080 + bool + help + Configure RP2 to use a W25Q080 flash chip, or similar. Should be selected + by the board definition, not the user. + +config RP2_FLASH_GENERIC_03H + bool + help + Configure RP2 to use a flash chip supporting the standard 03h command. + Should be selected by the board definition, not the user. + +config RP2_FLASH_IS25LP080 + bool + help + Configure RP2 to use a IS25LP080 flash chip, or similar. Should be selected + by the board definition, not the user. + +config RP2_FLASH_W25X10CL + bool + help + Configure RP2 to use a W25X10CL flash chip, or similar. Should be selected + by the board definition, not the user. + +config RP2_FLASH_AT25SF128A + bool + help + Configure RP2 to use a AT25SF128A flash chip, or similar. Should be selected + by the board definition, not the user. diff --git a/soc/raspberrypi/rp2xxx/Kconfig.defconfig b/soc/raspberrypi/rp2xxx/Kconfig.defconfig new file mode 100644 index 00000000000000..82256e806d0532 --- /dev/null +++ b/soc/raspberrypi/rp2xxx/Kconfig.defconfig @@ -0,0 +1,14 @@ +# Raspberry Pi RP2XXX MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RP2XXX + +rsource "Kconfig.defconfig.rp2*" + +config NUM_IRQS + default 26 + +endif # SOC_SERIES_RP2XXX diff --git a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2040 b/soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 similarity index 84% rename from soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2040 rename to soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 index 0470f2aaa69c13..304e2629afd99e 100644 --- a/soc/arm/rpi_pico/rp2/Kconfig.defconfig.rp2040 +++ b/soc/raspberrypi/rp2xxx/Kconfig.defconfig.rp2040 @@ -3,10 +3,6 @@ # Copyright (c) 2021 Nordic Semiconductor ASA # SPDX-License-Identifier: Apache-2.0 -config SOC - default "rp2040" - depends on SOC_RP2040 - config BUILD_OUTPUT_UF2_USE_FLASH_BASE default y if RP2_REQUIRES_SECOND_STAGE_BOOT diff --git a/soc/raspberrypi/rp2xxx/Kconfig.soc b/soc/raspberrypi/rp2xxx/Kconfig.soc new file mode 100644 index 00000000000000..045061697fe3ed --- /dev/null +++ b/soc/raspberrypi/rp2xxx/Kconfig.soc @@ -0,0 +1,19 @@ +# Raspberry Pi RP2XXX MCU line + +# Copyright (c) 2021 Nordic Semiconductor ASA +# Copyright (c) 2021 Yonatan Schachter +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RP2040 + bool + select SOC_SERIES_RP2XXX + +config SOC_SERIES_RP2XXX + bool + select SOC_FAMILY_RPI_PICO + +config SOC_SERIES + default "rp2xxx" if SOC_SERIES_RP2XXX + +config SOC + default "rp2040" if SOC_RP2040 diff --git a/soc/arm/rpi_pico/rp2/linker.ld b/soc/raspberrypi/rp2xxx/linker.ld similarity index 100% rename from soc/arm/rpi_pico/rp2/linker.ld rename to soc/raspberrypi/rp2xxx/linker.ld diff --git a/soc/arm/rpi_pico/rp2/pinctrl_soc.h b/soc/raspberrypi/rp2xxx/pinctrl_soc.h similarity index 100% rename from soc/arm/rpi_pico/rp2/pinctrl_soc.h rename to soc/raspberrypi/rp2xxx/pinctrl_soc.h diff --git a/soc/arm/rpi_pico/rp2/soc.c b/soc/raspberrypi/rp2xxx/soc.c similarity index 100% rename from soc/arm/rpi_pico/rp2/soc.c rename to soc/raspberrypi/rp2xxx/soc.c diff --git a/soc/arm/rpi_pico/rp2/soc.h b/soc/raspberrypi/rp2xxx/soc.h similarity index 100% rename from soc/arm/rpi_pico/rp2/soc.h rename to soc/raspberrypi/rp2xxx/soc.h diff --git a/soc/raspberrypi/soc.yml b/soc/raspberrypi/soc.yml new file mode 100644 index 00000000000000..192d7a947f265b --- /dev/null +++ b/soc/raspberrypi/soc.yml @@ -0,0 +1,6 @@ +family: +- name: rpi_pico + series: + - name: rp2xxx + socs: + - name: rp2040 diff --git a/soc/arm/renesas_ra/CMakeLists.txt b/soc/renesas/ra/CMakeLists.txt similarity index 100% rename from soc/arm/renesas_ra/CMakeLists.txt rename to soc/renesas/ra/CMakeLists.txt diff --git a/soc/renesas/ra/Kconfig b/soc/renesas/ra/Kconfig new file mode 100644 index 00000000000000..52a056a7612652 --- /dev/null +++ b/soc/renesas/ra/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RA + +config SERIES_SPECIFIC_SOC_INIT + bool "Use series specific initialize" + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_RA diff --git a/soc/renesas/ra/Kconfig.defconfig b/soc/renesas/ra/Kconfig.defconfig new file mode 100644 index 00000000000000..beb1aa718da821 --- /dev/null +++ b/soc/renesas/ra/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RA + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_RENESAS_RA diff --git a/soc/renesas/ra/Kconfig.soc b/soc/renesas/ra/Kconfig.soc new file mode 100644 index 00000000000000..52449b517a50fd --- /dev/null +++ b/soc/renesas/ra/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RA + bool + +config SOC_FAMILY + default "renesas_ra" if SOC_FAMILY_RENESAS_RA + +rsource "*/Kconfig.soc" diff --git a/soc/arm/renesas_ra/common/pinctrl_ra.h b/soc/renesas/ra/common/pinctrl_ra.h similarity index 100% rename from soc/arm/renesas_ra/common/pinctrl_ra.h rename to soc/renesas/ra/common/pinctrl_ra.h diff --git a/soc/arm/renesas_ra/common/ra_common_soc.h b/soc/renesas/ra/common/ra_common_soc.h similarity index 100% rename from soc/arm/renesas_ra/common/ra_common_soc.h rename to soc/renesas/ra/common/ra_common_soc.h diff --git a/soc/renesas/ra/ra4m1/CMakeLists.txt b/soc/renesas/ra/ra4m1/CMakeLists.txt new file mode 100644 index 00000000000000..c0d9c7b1baa0be --- /dev/null +++ b/soc/renesas/ra/ra4m1/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/ra/ra4m1/Kconfig b/soc/renesas/ra/ra4m1/Kconfig new file mode 100644 index 00000000000000..56153d0732ff3a --- /dev/null +++ b/soc/renesas/ra/ra4m1/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M1 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_SYSTICK + select DYNAMIC_INTERRUPTS + select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME + select XIP diff --git a/soc/renesas/ra/ra4m1/Kconfig.defconfig b/soc/renesas/ra/ra4m1/Kconfig.defconfig new file mode 100644 index 00000000000000..5913bd7257fa86 --- /dev/null +++ b/soc/renesas/ra/ra4m1/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RA4M1 + +config NUM_IRQS + default 32 + +endif # SOC_SERIES_RA4M1 diff --git a/soc/renesas/ra/ra4m1/Kconfig.soc b/soc/renesas/ra/ra4m1/Kconfig.soc new file mode 100644 index 00000000000000..e83c7bf3629ab8 --- /dev/null +++ b/soc/renesas/ra/ra4m1/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2023 TOKITA Hiroshi +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RA4M1 + bool + select SOC_FAMILY_RENESAS_RA + help + Renesas RA4M1 + +config SOC_R7FA4M1AB3CFM + bool + select SOC_SERIES_RA4M1 + help + R7FA4M1AB3CFM + +config SOC_SERIES + default "ra4m1" if SOC_SERIES_RA4M1 + +config SOC + default "r7fa4m1ab3cfm" if SOC_R7FA4M1AB3CFM diff --git a/soc/arm/renesas_ra/ra4m1/pinctrl_soc.h b/soc/renesas/ra/ra4m1/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_ra/ra4m1/pinctrl_soc.h rename to soc/renesas/ra/ra4m1/pinctrl_soc.h diff --git a/soc/arm/renesas_ra/ra4m1/soc.h b/soc/renesas/ra/ra4m1/soc.h similarity index 100% rename from soc/arm/renesas_ra/ra4m1/soc.h rename to soc/renesas/ra/ra4m1/soc.h diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml new file mode 100644 index 00000000000000..e031d88606738d --- /dev/null +++ b/soc/renesas/ra/soc.yml @@ -0,0 +1,6 @@ +family: + - name: renesas_ra + series: + - name: ra4m1 + socs: + - name: r7fa4m1ab3cfm diff --git a/soc/arm/renesas_rcar/CMakeLists.txt b/soc/renesas/rcar/CMakeLists.txt similarity index 100% rename from soc/arm/renesas_rcar/CMakeLists.txt rename to soc/renesas/rcar/CMakeLists.txt diff --git a/soc/renesas/rcar/Kconfig b/soc/renesas/rcar/Kconfig new file mode 100644 index 00000000000000..76a07262bf76c9 --- /dev/null +++ b/soc/renesas/rcar/Kconfig @@ -0,0 +1,9 @@ +# Renesas R-Car SoC line +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RCAR + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_RCAR diff --git a/soc/renesas/rcar/Kconfig.defconfig b/soc/renesas/rcar/Kconfig.defconfig new file mode 100644 index 00000000000000..9a7fa2d5d73662 --- /dev/null +++ b/soc/renesas/rcar/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_RCAR + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_RENESAS_RCAR diff --git a/soc/renesas/rcar/Kconfig.soc b/soc/renesas/rcar/Kconfig.soc new file mode 100644 index 00000000000000..6869cbd86f5310 --- /dev/null +++ b/soc/renesas/rcar/Kconfig.soc @@ -0,0 +1,11 @@ +# Renesas R-Car SoC line +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_RCAR + bool + +config SOC_FAMILY + default "renesas_rcar" if SOC_FAMILY_RENESAS_RCAR + +rsource "*/Kconfig.soc" diff --git a/soc/arm/renesas_rcar/common/pinctrl_rcar.h b/soc/renesas/rcar/common/pinctrl_rcar.h similarity index 100% rename from soc/arm/renesas_rcar/common/pinctrl_rcar.h rename to soc/renesas/rcar/common/pinctrl_rcar.h diff --git a/soc/renesas/rcar/rcar_gen3/CMakeLists.txt b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt new file mode 100644 index 00000000000000..7f96e60788e526 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/CMakeLists.txt @@ -0,0 +1,18 @@ +# Copyright (c) 2021 IoT.bzh +# Copyright (c) 2023 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_SOC_SERIES_RCAR_GEN3_R7) + zephyr_sources(r7/soc.c) + zephyr_include_directories(r7) + zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951_R7 pfc_r8a77951.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_SERIES_RCAR_GEN3_A57) + zephyr_include_directories(a57) + zephyr_library_sources_ifdef(CONFIG_SOC_R8A77951_A57 pfc_r8a77951.c) + zephyr_library_sources_ifdef(CONFIG_SOC_R8A77961 pfc_r8a77961.c) + zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig b/soc/renesas/rcar/rcar_gen3/Kconfig new file mode 100644 index 00000000000000..3d4c577e46abaf --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/Kconfig @@ -0,0 +1,26 @@ +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN3_R7 + bool + select ARM + select CPU_CORTEX_R7 + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_DCLS + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + +config SOC_SERIES_RCAR_GEN3_A57 + bool + select ARM64 + select CPU_CORTEX_A57 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + +config SOC_R8A77951_R7 + select SOC_SERIES_RCAR_GEN3_R7 + +config SOC_R8A77951_A57 + select SOC_SERIES_RCAR_GEN3_A57 + +config SOC_R8A77961 + select SOC_SERIES_RCAR_GEN3_A57 diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig b/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig new file mode 100644 index 00000000000000..173efde91373b4 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Renesas R-Car Gen3 SoC line + +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RCAR_GEN3 + +config NUM_IRQS + default 512 if SOC_R8A77951_R7 + default 240 if SOC_R8A77961 || SOC_R8A77951_A57 + +config PINCTRL + default y + +endif # SOC_SERIES_RCAR_GEN3 diff --git a/soc/renesas/rcar/rcar_gen3/Kconfig.soc b/soc/renesas/rcar/rcar_gen3/Kconfig.soc new file mode 100644 index 00000000000000..d1476c91d4fdb9 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen3/Kconfig.soc @@ -0,0 +1,31 @@ +# Copyright (c) 2021 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN3 + bool + select SOC_FAMILY_RENESAS_RCAR + +config SOC_R8A77951_R7 + bool + select SOC_SERIES_RCAR_GEN3 + help + R8A77951 R7 + +config SOC_R8A77951_A57 + bool + select SOC_SERIES_RCAR_GEN3 + help + R8A77951 A57 + +config SOC_R8A77961 + bool + select SOC_SERIES_RCAR_GEN3 + help + R8A77961 + +config SOC_SERIES + default "rcar_gen3" if SOC_SERIES_RCAR_GEN3 + +config SOC + default "r8a77951" if SOC_R8A77951_R7 || SOC_R8A77951_A57 + default "r8a77961" if SOC_R8A77961 diff --git a/soc/arm64/renesas_rcar/gen3/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h similarity index 100% rename from soc/arm64/renesas_rcar/gen3/pinctrl_soc.h rename to soc/renesas/rcar/rcar_gen3/a57/pinctrl_soc.h diff --git a/soc/arm64/renesas_rcar/gen3/mmu_regions.c b/soc/renesas/rcar/rcar_gen3/mmu_regions.c similarity index 100% rename from soc/arm64/renesas_rcar/gen3/mmu_regions.c rename to soc/renesas/rcar/rcar_gen3/mmu_regions.c diff --git a/soc/arm/renesas_rcar/gen3/pfc_r8a77951.c b/soc/renesas/rcar/rcar_gen3/pfc_r8a77951.c similarity index 100% rename from soc/arm/renesas_rcar/gen3/pfc_r8a77951.c rename to soc/renesas/rcar/rcar_gen3/pfc_r8a77951.c diff --git a/soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c b/soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c similarity index 100% rename from soc/arm64/renesas_rcar/gen3/pfc_r8a77961.c rename to soc/renesas/rcar/rcar_gen3/pfc_r8a77961.c diff --git a/soc/arm/renesas_rcar/gen3/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen3/pinctrl_soc.h rename to soc/renesas/rcar/rcar_gen3/r7/pinctrl_soc.h diff --git a/soc/arm/renesas_rcar/gen3/soc.c b/soc/renesas/rcar/rcar_gen3/r7/soc.c similarity index 100% rename from soc/arm/renesas_rcar/gen3/soc.c rename to soc/renesas/rcar/rcar_gen3/r7/soc.c diff --git a/soc/arm/renesas_rcar/gen3/soc.h b/soc/renesas/rcar/rcar_gen3/r7/soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen3/soc.h rename to soc/renesas/rcar/rcar_gen3/r7/soc.h diff --git a/soc/renesas/rcar/rcar_gen4/CMakeLists.txt b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt new file mode 100644 index 00000000000000..79be28ffe553cf --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/CMakeLists.txt @@ -0,0 +1,6 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) +zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F0 pfc_r8a779f0.c) +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig b/soc/renesas/rcar/rcar_gen4/Kconfig new file mode 100644 index 00000000000000..a084ac558b8457 --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN4 + bool + select ARM + select CPU_CORTEX_R52 + select GIC_SINGLE_SECURITY_STATE + select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL + select ARM_ARCH_TIMER diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig new file mode 100644 index 00000000000000..cdb614fdc624ba --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig @@ -0,0 +1,10 @@ +# Renesas R-Car Gen4 SoC line + +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RCAR_GEN4 + +rsource "Kconfig.defconfig.r8a779*" + +endif # SOC_SERIES_RCAR_GEN4 diff --git a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0 b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 similarity index 85% rename from soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0 rename to soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 index 6da34845bf95f0..c3c09787e1195b 100644 --- a/soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0 +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.defconfig.r8a779f0 @@ -3,9 +3,6 @@ if SOC_R8A779F0 -config SOC - default "r8a779f0" - config NUM_IRQS default 1216 #960 SPI + 256 LPI diff --git a/soc/renesas/rcar/rcar_gen4/Kconfig.soc b/soc/renesas/rcar/rcar_gen4/Kconfig.soc new file mode 100644 index 00000000000000..99193973d59bcb --- /dev/null +++ b/soc/renesas/rcar/rcar_gen4/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2023 IoT.bzh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RCAR_GEN4 + bool + select SOC_FAMILY_RENESAS_RCAR + +config SOC_R8A779F0 + bool + select SOC_SERIES_RCAR_GEN4 + help + r8a779f0 + +config SOC_SERIES + default "rcar_gen4" if SOC_SERIES_RCAR_GEN4 + +config SOC + default "r8a779f0" if SOC_R8A779F0 diff --git a/soc/arm/renesas_rcar/gen4/pfc_r8a779f0.c b/soc/renesas/rcar/rcar_gen4/pfc_r8a779f0.c similarity index 100% rename from soc/arm/renesas_rcar/gen4/pfc_r8a779f0.c rename to soc/renesas/rcar/rcar_gen4/pfc_r8a779f0.c diff --git a/soc/arm/renesas_rcar/gen4/pinctrl_soc.h b/soc/renesas/rcar/rcar_gen4/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen4/pinctrl_soc.h rename to soc/renesas/rcar/rcar_gen4/pinctrl_soc.h diff --git a/soc/arm/renesas_rcar/gen4/soc.h b/soc/renesas/rcar/rcar_gen4/soc.h similarity index 100% rename from soc/arm/renesas_rcar/gen4/soc.h rename to soc/renesas/rcar/rcar_gen4/soc.h diff --git a/soc/renesas/rcar/soc.yml b/soc/renesas/rcar/soc.yml new file mode 100644 index 00000000000000..6c936a7b7c927d --- /dev/null +++ b/soc/renesas/rcar/soc.yml @@ -0,0 +1,13 @@ +family: + - name: renesas_rcar + series: + - name: rcar_gen3 + socs: + - name: r8a77951 + cpuclusters: + - name: r7 + - name: a57 + - name: r8a77961 + - name: rcar_gen4 + socs: + - name: r8a779f0 diff --git a/soc/renesas/rzt2m/CMakeLists.txt b/soc/renesas/rzt2m/CMakeLists.txt new file mode 100644 index 00000000000000..8cf72713d110d5 --- /dev/null +++ b/soc/renesas/rzt2m/CMakeLists.txt @@ -0,0 +1,8 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/rzt2m/Kconfig b/soc/renesas/rzt2m/Kconfig new file mode 100644 index 00000000000000..5b26c6bcba7ce7 --- /dev/null +++ b/soc/renesas/rzt2m/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RENESAS_RZT2M + select ARM + select CPU_CORTEX_R52 + select CPU_HAS_ARM_MPU + select GIC_V3 + select GIC_SINGLE_SECURITY_STATE + select ARM_ARCH_TIMER + select SYSCON diff --git a/soc/renesas/rzt2m/Kconfig.defconfig b/soc/renesas/rzt2m/Kconfig.defconfig new file mode 100644 index 00000000000000..7eedc53ffc64df --- /dev/null +++ b/soc/renesas/rzt2m/Kconfig.defconfig @@ -0,0 +1,21 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RENESAS_RZT2M + +config NUM_IRQS + default 994 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 20000000 + +config FPU + default y + +config FLASH_SIZE + default 0 + +config FLASH_BASE_ADDRESS + default 0 + +endif # SOC_RENESAS_RZT2M diff --git a/soc/renesas/rzt2m/Kconfig.soc b/soc/renesas/rzt2m/Kconfig.soc new file mode 100644 index 00000000000000..9304484d06558c --- /dev/null +++ b/soc/renesas/rzt2m/Kconfig.soc @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RENESAS_RZT2M + bool + +config SOC_PART_NUMBER_R9A07G075 + bool + +config SOC + default "renesas_rzt2m" if SOC_RENESAS_RZT2M + +config SOC_PART_NUMBER + default "R9A07G075" if SOC_PART_NUMBER_R9A07G075 diff --git a/soc/arm/renesas_rzt2m/linker.ld b/soc/renesas/rzt2m/linker.ld similarity index 100% rename from soc/arm/renesas_rzt2m/linker.ld rename to soc/renesas/rzt2m/linker.ld diff --git a/soc/arm/renesas_rzt2m/pinctrl_soc.h b/soc/renesas/rzt2m/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_rzt2m/pinctrl_soc.h rename to soc/renesas/rzt2m/pinctrl_soc.h diff --git a/soc/arm/renesas_rzt2m/soc.c b/soc/renesas/rzt2m/soc.c similarity index 100% rename from soc/arm/renesas_rzt2m/soc.c rename to soc/renesas/rzt2m/soc.c diff --git a/soc/arm/renesas_rzt2m/soc.h b/soc/renesas/rzt2m/soc.h similarity index 100% rename from soc/arm/renesas_rzt2m/soc.h rename to soc/renesas/rzt2m/soc.h diff --git a/soc/renesas/rzt2m/soc.yml b/soc/renesas/rzt2m/soc.yml new file mode 100644 index 00000000000000..35c7cc27f77039 --- /dev/null +++ b/soc/renesas/rzt2m/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: renesas_rzt2m diff --git a/soc/arm/renesas_smartbond/CMakeLists.txt b/soc/renesas/smartbond/CMakeLists.txt similarity index 100% rename from soc/arm/renesas_smartbond/CMakeLists.txt rename to soc/renesas/smartbond/CMakeLists.txt diff --git a/soc/renesas/smartbond/Kconfig b/soc/renesas/smartbond/Kconfig new file mode 100644 index 00000000000000..184f4b77ca2115 --- /dev/null +++ b/soc/renesas/smartbond/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_SMARTBOND + +rsource "*/Kconfig" + +endif # SOC_FAMILY_RENESAS_SMARTBOND diff --git a/soc/renesas/smartbond/Kconfig.defconfig b/soc/renesas/smartbond/Kconfig.defconfig new file mode 100644 index 00000000000000..0df71b16f2e56d --- /dev/null +++ b/soc/renesas/smartbond/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_RENESAS_SMARTBOND + +rsource "*/Kconfig.defconfig" + +config PINCTRL + default y + +endif # SOC_FAMILY_RENESAS_SMARTBOND diff --git a/soc/renesas/smartbond/Kconfig.soc b/soc/renesas/smartbond/Kconfig.soc new file mode 100644 index 00000000000000..584bb522944555 --- /dev/null +++ b/soc/renesas/smartbond/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_RENESAS_SMARTBOND + bool + +config SOC_FAMILY + default "renesas_smartbond" if SOC_FAMILY_RENESAS_SMARTBOND + +rsource "*/Kconfig.soc" diff --git a/soc/renesas/smartbond/da1469x/CMakeLists.txt b/soc/renesas/smartbond/da1469x/CMakeLists.txt new file mode 100644 index 00000000000000..0c45be52d2d8b0 --- /dev/null +++ b/soc/renesas/smartbond/da1469x/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_linker_sources( + RAM_SECTIONS + SORT_KEY 0 + intvect_reserved.ld +) +zephyr_library() +zephyr_library_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/renesas/smartbond/da1469x/Kconfig b/soc/renesas/smartbond/da1469x/Kconfig new file mode 100644 index 00000000000000..267df2ea79d0bf --- /dev/null +++ b/soc/renesas/smartbond/da1469x/Kconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DA1469X + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_CORTEX_M_HAS_SYSTICK + select ARMV8_M_DSP + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select CLOCK_CONTROL + select CLOCK_CONTROL_SMARTBOND diff --git a/soc/renesas/smartbond/da1469x/Kconfig.defconfig b/soc/renesas/smartbond/da1469x/Kconfig.defconfig new file mode 100644 index 00000000000000..fedbde9f19e59a --- /dev/null +++ b/soc/renesas/smartbond/da1469x/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_DA1469X + +config NUM_IRQS + default 40 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) + +config SRAM_VECTOR_TABLE + default y + +config USE_DT_CODE_PARTITION + default y if MCUBOOT + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config FLASH_LOAD_OFFSET + default 0x2400 if !USE_DT_CODE_PARTITION + +config PLATFORM_SPECIFIC_INIT + default y + +endif # SOC_SERIES_DA1469X diff --git a/soc/renesas/smartbond/da1469x/Kconfig.soc b/soc/renesas/smartbond/da1469x/Kconfig.soc new file mode 100644 index 00000000000000..b52b2905936153 --- /dev/null +++ b/soc/renesas/smartbond/da1469x/Kconfig.soc @@ -0,0 +1,27 @@ +# Copyright (c) 2022 Renesas Electronics Corporation +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_DA1469X + bool + select SOC_FAMILY_RENESAS_SMARTBOND + help + Renesas SmartBond(tm) DA1469x series MCU + +config SOC_DA14695 + bool + select SOC_SERIES_DA1469X + help + DA14695 + +config SOC_DA14699 + bool + select SOC_SERIES_DA1469X + help + DA14699 + +config SOC_SERIES + default "da1469x" if SOC_SERIES_DA1469X + +config SOC + default "da14695" if SOC_DA14695 + default "da14699" if SOC_DA14699 diff --git a/soc/arm/renesas_smartbond/da1469x/intvect_reserved.ld b/soc/renesas/smartbond/da1469x/intvect_reserved.ld similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/intvect_reserved.ld rename to soc/renesas/smartbond/da1469x/intvect_reserved.ld diff --git a/soc/arm/renesas_smartbond/da1469x/pinctrl_soc.h b/soc/renesas/smartbond/da1469x/pinctrl_soc.h similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/pinctrl_soc.h rename to soc/renesas/smartbond/da1469x/pinctrl_soc.h diff --git a/soc/arm/renesas_smartbond/da1469x/soc.c b/soc/renesas/smartbond/da1469x/soc.c similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/soc.c rename to soc/renesas/smartbond/da1469x/soc.c diff --git a/soc/arm/renesas_smartbond/da1469x/soc.h b/soc/renesas/smartbond/da1469x/soc.h similarity index 100% rename from soc/arm/renesas_smartbond/da1469x/soc.h rename to soc/renesas/smartbond/da1469x/soc.h diff --git a/soc/renesas/smartbond/soc.yml b/soc/renesas/smartbond/soc.yml new file mode 100644 index 00000000000000..ee32857c5b75ee --- /dev/null +++ b/soc/renesas/smartbond/soc.yml @@ -0,0 +1,7 @@ +family: + - name: renesas_smartbond + series: + - name: da1469x + socs: + - name: da14695 + - name: da14699 diff --git a/soc/riscv/renode_virt/CMakeLists.txt b/soc/renode/riscv_virtual/CMakeLists.txt similarity index 100% rename from soc/riscv/renode_virt/CMakeLists.txt rename to soc/renode/riscv_virtual/CMakeLists.txt diff --git a/soc/renode/riscv_virtual/Kconfig b/soc/renode/riscv_virtual/Kconfig new file mode 100644 index 00000000000000..37c4578df80d1e --- /dev/null +++ b/soc/renode/riscv_virtual/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RISCV_VIRTUAL_RENODE + select RISCV + select RISCV_PRIVILEGED + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_HAS_PLIC diff --git a/soc/renode/riscv_virtual/Kconfig.defconfig b/soc/renode/riscv_virtual/Kconfig.defconfig new file mode 100644 index 00000000000000..8b00c5867ab056 --- /dev/null +++ b/soc/renode/riscv_virtual/Kconfig.defconfig @@ -0,0 +1,39 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +if SOC_RISCV_VIRTUAL_RENODE + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 4000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 1ST_LEVEL_INTERRUPT_BITS + default 4 + +config NUM_2ND_LEVEL_AGGREGATORS + default 2 + +config 2ND_LEVEL_INTERRUPT_BITS + default 11 + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config 2ND_LVL_INTR_01_OFFSET + default 4 + +config MAX_IRQ_PER_AGGREGATOR + default 1023 + +config NUM_IRQS + default 2058 + +endif # SOC_RISCV_VIRTUAL_RENODE diff --git a/soc/renode/riscv_virtual/Kconfig.soc b/soc/renode/riscv_virtual/Kconfig.soc new file mode 100644 index 00000000000000..f047830815c370 --- /dev/null +++ b/soc/renode/riscv_virtual/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Meta +# SPDX-License-Identifier: Apache-2.0 + +config SOC_RISCV_VIRTUAL_RENODE + bool + help + Renode RISCV32 Virtual system implementation + +config SOC + default "riscv_virtual_renode" if SOC_RISCV_VIRTUAL_RENODE diff --git a/soc/renode/riscv_virtual/soc.yml b/soc/renode/riscv_virtual/soc.yml new file mode 100644 index 00000000000000..f971b54978d9c5 --- /dev/null +++ b/soc/renode/riscv_virtual/soc.yml @@ -0,0 +1,2 @@ +socs: + - name: riscv_virtual_renode diff --git a/soc/riscv/CMakeLists.txt b/soc/riscv/CMakeLists.txt deleted file mode 100644 index 79d115704b2943..00000000000000 --- a/soc/riscv/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/riscv/andes_v5/Kconfig b/soc/riscv/andes_v5/Kconfig deleted file mode 100644 index f3c78ab7f813c6..00000000000000 --- a/soc/riscv/andes_v5/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ANDES_V5 - bool - -if SOC_FAMILY_ANDES_V5 - -config SOC_FAMILY - string - default "andes_v5" - -source "soc/riscv/andes_v5/*/Kconfig.soc" - -endif # SOC_FAMILY_ANDES_V5 diff --git a/soc/riscv/andes_v5/Kconfig.defconfig b/soc/riscv/andes_v5/Kconfig.defconfig deleted file mode 100644 index 6213f28d2cb38e..00000000000000 --- a/soc/riscv/andes_v5/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/andes_v5/*/Kconfig.defconfig.series" diff --git a/soc/riscv/andes_v5/Kconfig.soc b/soc/riscv/andes_v5/Kconfig.soc deleted file mode 100644 index 9efb478193444c..00000000000000 --- a/soc/riscv/andes_v5/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/andes_v5/*/Kconfig.series" diff --git a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series b/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series deleted file mode 100644 index 7b9bbc3eadbbc0..00000000000000 --- a/soc/riscv/andes_v5/ae350/Kconfig.defconfig.series +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ANDES_AE350 - -# Kconfig picks the first default with a satisfied condition. -# SoC defaults should be parsed before SoC Series defaults, because SoCs usually -# overrides SoC Series values. -source "soc/riscv/andes_v5/ae350/Kconfig.defconfig.ae*" - -config SOC_SERIES - default "ae350" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 60000000 - -config KERNEL_ENTRY - default "entry" - -config RISCV_GENERIC_TOOLCHAIN - default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" - default n - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/riscv/andes_v5/ae350/Kconfig.series b/soc/riscv/andes_v5/ae350/Kconfig.series deleted file mode 100644 index c2e9b40bfb7f5b..00000000000000 --- a/soc/riscv/andes_v5/ae350/Kconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ANDES_AE350 - bool "Andes V5 AE350 SoC Series Implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_ANDES_V5 - help - Enable support for Andes V5 AE350 SoC Series diff --git a/soc/riscv/andes_v5/ae350/Kconfig.soc b/soc/riscv/andes_v5/ae350/Kconfig.soc deleted file mode 100644 index 1731cc08f51c98..00000000000000 --- a/soc/riscv/andes_v5/ae350/Kconfig.soc +++ /dev/null @@ -1,124 +0,0 @@ -# Copyright (c) 2021 Andes Technology Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "Andes V5 SoC Selection" -depends on SOC_SERIES_ANDES_AE350 - -config SOC_ANDES_AE350 - bool "Andes AE350 SoC implementation" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select RISCV_PMP - -endchoice - -if SOC_SERIES_ANDES_AE350 - -choice -prompt "Base CPU ISA options" -default RV32I_CPU - -config RV32I_CPU - bool "RISCV32 CPU ISA" - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config RV32E_CPU - bool "RISCV32E CPU ISA" - select RISCV_ISA_RV32E - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config RV64I_CPU - bool "RISCV64 CPU ISA" - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select 64BIT - -endchoice - -choice -prompt "FPU options" -default NO_FPU - -config NO_FPU - bool "No FPU" - -config SINGLE_PRECISION_FPU - bool "Single precision FPU" - select CPU_HAS_FPU - -config DOUBLE_PRECISION_FPU - bool "Double precision FPU" - select CPU_HAS_FPU_DOUBLE_PRECISION - -endchoice - -config SOC_ANDES_V5_HWDSP - bool "AndeStar V5 DSP ISA" - select RISCV_SOC_CONTEXT_SAVE - depends on !RISCV_GENERIC_TOOLCHAIN - help - This option enables the AndeStar v5 hardware DSP, in order to - support using the DSP instructions. - -config SOC_ANDES_V5_PFT - bool "Andes V5 PowerBrake extension" - default y - select RISCV_SOC_CONTEXT_SAVE - help - The PowerBrake extension throttles performance by reducing instruction - executing rate. - -config SOC_ANDES_V5_EXECIT - bool "Andes V5 EXEC.IT extension" - depends on RISCV_ISA_EXT_C - depends on !RISCV_GENERIC_TOOLCHAIN - depends on !LINKER_USE_NO_RELAX - help - The EXEC.IT extension (Execution on Instruction Table) generate - a look-up table and replaces suitable 32-bit instructions with - the 16-bit "exec.it ". - -config SOC_ANDES_V5_PMA - bool "Andes V5 Physical Memory Attribute (PMA)" - select ARCH_HAS_NOCACHE_MEMORY_SUPPORT - help - This option enables the Andes V5 PMA, in order to support SW to - configure physical memory attribute by PMA CSRs. The address - matching of Andes V5 PMA is like RISC-V PMP NAPOT mode - (power-of-two alignment). - -config SOC_ANDES_V5_PMA_REGION_MIN_ALIGN_AND_SIZE - int - depends on SOC_ANDES_V5_PMA - default 4096 - help - Minimum size (and alignment) of an PMA region. Use this symbol - to guarantee minimum size and alignment of PMA regions. - -# Workaround for not being able to have commas in macro arguments -DT_ANDESTECH_L2C := andestech,l2c - -config SOC_ANDES_V5_L2C - bool - default $(dt_compat_enabled,$(DT_ANDESTECH_L2C)) - -config SOC_ANDES_V5_IOCP - bool "Andes V5 I/O Coherence Port (IOCP)" - depends on SOC_ANDES_V5_L2C - depends on DCACHE - help - Support Andes V5 I/O Coherence Port to handle cache coherency - between cache and external non-caching master, such as DMA - controller. - -endif # SOC_SERIES_ANDES_AE350 diff --git a/soc/riscv/common/CMakeLists.txt b/soc/riscv/common/CMakeLists.txt deleted file mode 100644 index 91ef5c975b919a..00000000000000 --- a/soc/riscv/common/CMakeLists.txt +++ /dev/null @@ -1 +0,0 @@ -add_subdirectory_ifdef(CONFIG_RISCV_PRIVILEGED riscv-privileged) diff --git a/soc/riscv/common/Kconfig b/soc/riscv/common/Kconfig deleted file mode 100644 index 91f2c5cf80a434..00000000000000 --- a/soc/riscv/common/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 -# -source "soc/riscv/common/riscv-privileged/Kconfig" diff --git a/soc/riscv/efinix_sapphire/Kconfig.defconfig b/soc/riscv/efinix_sapphire/Kconfig.defconfig deleted file mode 100644 index 95a33b4ab82906..00000000000000 --- a/soc/riscv/efinix_sapphire/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_EFINIX_SAPPHIRE - -config SOC - default "efinix_sapphire" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config RISCV_SOC_INTERRUPT_INIT - bool - default y - -config NUM_IRQS - int - default 36 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -endif # SOC_EFINIX_SAPPHIRE diff --git a/soc/riscv/efinix_sapphire/Kconfig.soc b/soc/riscv/efinix_sapphire/Kconfig.soc deleted file mode 100644 index 4bad3b5cb79f99..00000000000000 --- a/soc/riscv/efinix_sapphire/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Efinix Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_EFINIX_SAPPHIRE - bool "Efinix Sapphire VexRiscv system implementation" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC diff --git a/soc/riscv/espressif_esp32/CMakeLists.txt b/soc/riscv/espressif_esp32/CMakeLists.txt deleted file mode 100644 index 31ef76aadeef99..00000000000000 --- a/soc/riscv/espressif_esp32/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) diff --git a/soc/riscv/espressif_esp32/Kconfig b/soc/riscv/espressif_esp32/Kconfig deleted file mode 100644 index 0a6d3f90be9837..00000000000000 --- a/soc/riscv/espressif_esp32/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ESP32 - bool - -if SOC_FAMILY_ESP32 - -config SOC_FAMILY - string - default "espressif_esp32" - -source "soc/riscv/espressif_esp32/common/Kconfig.soc" -source "soc/riscv/espressif_esp32/*/Kconfig.soc" - -endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/Kconfig.defconfig b/soc/riscv/espressif_esp32/Kconfig.defconfig deleted file mode 100644 index ee9d04c4daba5a..00000000000000 --- a/soc/riscv/espressif_esp32/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/espressif_esp32/common/Kconfig.defconfig.series" -source "soc/riscv/espressif_esp32/*/Kconfig.defconfig.series" diff --git a/soc/riscv/espressif_esp32/Kconfig.soc b/soc/riscv/espressif_esp32/Kconfig.soc deleted file mode 100644 index ce15ddcf10e3ab..00000000000000 --- a/soc/riscv/espressif_esp32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/espressif_esp32/*/Kconfig.series" diff --git a/soc/riscv/espressif_esp32/common/CMakeLists.txt b/soc/riscv/espressif_esp32/common/CMakeLists.txt deleted file mode 100644 index 9edbe85c8217b7..00000000000000 --- a/soc/riscv/espressif_esp32/common/CMakeLists.txt +++ /dev/null @@ -1,2 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 diff --git a/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series deleted file mode 100644 index a0a4b4f49432dc..00000000000000 --- a/soc/riscv/espressif_esp32/common/Kconfig.defconfig.series +++ /dev/null @@ -1,52 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -config GEN_ISR_TABLES - default y - -config GEN_SW_ISR_TABLE - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config DYNAMIC_INTERRUPTS - default y - -config ISR_STACK_SIZE - default 2048 - -config ATOMIC_OPERATIONS_C - default y - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 16000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config CLOCK_CONTROL - default y - -if BOOTLOADER_MCUBOOT - - config HAS_FLASH_LOAD_OFFSET - default y - config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y - config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y - config ROM_START_OFFSET - default 0x20 - -endif # BOOTLOADER_MCUBOOT config - -endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/common/Kconfig.soc b/soc/riscv/espressif_esp32/common/Kconfig.soc deleted file mode 100644 index 5eb40f3b3405e8..00000000000000 --- a/soc/riscv/espressif_esp32/common/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -config ESPTOOLPY_FLASHFREQ_80M - bool - -config FLASH_SIZE - int - -config FLASH_BASE_ADDRESS - hex - -endif # SOC_FAMILY_ESP32 diff --git a/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt b/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt deleted file mode 100644 index d6772eacbfc95d..00000000000000 --- a/soc/riscv/espressif_esp32/esp32c3/CMakeLists.txt +++ /dev/null @@ -1,101 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - vectors.S - soc_irq.S - soc_irq.c - soc.c - loader.c - ) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -# get code-partition slot0 address -dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") -dt_reg_addr(img_0_off PATH ${dts_partition_path}) - -# get code-partition boot address -dt_nodelabel(dts_partition_path NODELABEL "boot_partition") -dt_reg_addr(boot_off PATH ${dts_partition_path}) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32c3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - -board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series deleted file mode 100644 index 50d52b3f5bfc3b..00000000000000 --- a/soc/riscv/espressif_esp32/esp32c3/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32C3 - -config SOC_SERIES - default "esp32c3" - -config NUM_IRQS - default 62 - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) - -endif # SOC_SERIES_ESP32C3 diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.series b/soc/riscv/espressif_esp32/esp32c3/Kconfig.series deleted file mode 100644 index 2b845a3f057a95..00000000000000 --- a/soc/riscv/espressif_esp32/esp32c3/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32C3 - bool "ESP32C3" - select RISCV - select RISCV_GP - select DYNAMIC_INTERRUPTS - select CLOCK_CONTROL - select PINCTRL - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select HAS_ESPRESSIF_HAL - select SOC_FAMILY_ESP32 - select XIP if !MCUBOOT - select HAS_PM - select HAS_POWEROFF - help - Enable support for Espressif ESP32-C3 diff --git a/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc b/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc deleted file mode 100644 index 66a6e918f31e51..00000000000000 --- a/soc/riscv/espressif_esp32/esp32c3/Kconfig.soc +++ /dev/null @@ -1,99 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32C3 - -config IDF_TARGET_ESP32C3 - bool "ESP32C3 as target board" - default y - -choice SOC_PART_NUMBER - prompt "ESP32-C3 SOC Selection" - depends on SOC_SERIES_ESP32C3 - - config SOC_ESP32C3 - bool "ESP32C3" - config SOC_ESP32C3_FX4 - bool "ESP32C3_FX4" - config SOC_ESP32C3_MINI_N4 - bool "ESP32C3_MINI_N4" - config SOC_ESP32C3_WROOM_02_N4 - bool "ESP32C3_WROOM_02_N4" - config SOC_ESP32C3_WROOM_02_N8 - bool "ESP32C3_WROOM_02_N8" - -endchoice # SOC_PART_NUMBER - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32C3_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32C3_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - -config ESP32C3_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config ESP32C3_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32C3_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32C3_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice # ESP32C3_RTC_CLK_SRC - -config ESP32C3_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32C3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32C3_RTC_CLK_SRC_EXT_CRYS || ESP32C3_RTC_CLK_SRC_EXT_OSC || ESP32C3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32C3_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -config MAC_BB_PD - bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" - depends on SOC_SERIES_ESP32C3 && TICKLESS_KERNEL - default n - help - If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered - down when PHY is disabled. Enabling this setting reduces power consumption - by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only), - 2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth). - -endif # SOC_SERIES_ESP32C3 diff --git a/soc/riscv/gd_gd32/Kconfig b/soc/riscv/gd_gd32/Kconfig deleted file mode 100644 index 46f2dd0b1d6b01..00000000000000 --- a/soc/riscv/gd_gd32/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_GD32 - bool - -if SOC_FAMILY_GD32 - -config SOC_FAMILY - string - default "gd_gd32" - -source "soc/riscv/gd_gd32/*/Kconfig.soc" - -endif # SOC_FAMILY_GIGADEVICE_GD32 diff --git a/soc/riscv/gd_gd32/Kconfig.defconfig b/soc/riscv/gd_gd32/Kconfig.defconfig deleted file mode 100644 index 2be284db7eac4c..00000000000000 --- a/soc/riscv/gd_gd32/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/gd_gd32/*/Kconfig.defconfig.series" diff --git a/soc/riscv/gd_gd32/Kconfig.soc b/soc/riscv/gd_gd32/Kconfig.soc deleted file mode 100644 index 09d7d5d627ea5f..00000000000000 --- a/soc/riscv/gd_gd32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/gd_gd32/*/Kconfig.series" diff --git a/soc/riscv/gd_gd32/gd32vf103/CMakeLists.txt b/soc/riscv/gd_gd32/gd32vf103/CMakeLists.txt deleted file mode 100644 index 9fa5868a2a6a4d..00000000000000 --- a/soc/riscv/gd_gd32/gd32vf103/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(entry.S) -zephyr_sources(soc.c) - -zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.series b/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.series deleted file mode 100644 index 17ab7a87c392f0..00000000000000 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.series +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_GD32VF103 - -source "soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103*" - -config SOC_SERIES - default "gd32vf103" - -endif # SOC_SERIES_GD32VF103 diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.series b/soc/riscv/gd_gd32/gd32vf103/Kconfig.series deleted file mode 100644 index e50567e07980a4..00000000000000 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# GD32VF103 SOC implementation - -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_GD32VF103 - bool "GigaDevice GD32VF103 series SoC implementation" - select RISCV - select RISCV_PRIVILEGED - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select BUILD_OUTPUT_HEX - select XIP - select GD32_HAS_AFIO_PINMUX - select GD32_HAS_IRC_40K - select HAS_GD32_HAL - select RISCV_HAS_CLIC - select SOC_FAMILY_GD32 - help - Enable support for GigaDevice GD32VF1 series SoC diff --git a/soc/riscv/gd_gd32/gd32vf103/Kconfig.soc b/soc/riscv/gd_gd32/gd32vf103/Kconfig.soc deleted file mode 100644 index a2da5540e41aea..00000000000000 --- a/soc/riscv/gd_gd32/gd32vf103/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# GD32VF103 SOC configuration options - -# Copyright (c) 2021 Tokita, Hiroshi -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "GigaDevice GD32VF103 SOC implementation" - depends on SOC_SERIES_GD32VF103 - -config SOC_GD32VF103 - bool "GD32VF103" - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/gd_gd32/gd32vf103/pinctrl_soc.h b/soc/riscv/gd_gd32/gd32vf103/pinctrl_soc.h deleted file mode 100644 index 7d703caa97aa6f..00000000000000 --- a/soc/riscv/gd_gd32/gd32vf103/pinctrl_soc.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2021 Tokita, Hiroshi - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * Gigadevice SoC specific helpers for pinctrl driver - */ - -#ifndef ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ -#define ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ - -#include - -#endif /* ZEPHYR_SOC_RISCV_RISCV_PRIVILEGED_NUCLEI_GD32VF103_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/riscv/intel_niosv/Kconfig b/soc/riscv/intel_niosv/Kconfig deleted file mode 100644 index b841d19c922759..00000000000000 --- a/soc/riscv/intel_niosv/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_NIOSV - bool - -if SOC_FAMILY_INTEL_NIOSV - -config SOC_FAMILY - string - default "intel_niosv" - -source "soc/riscv/intel_niosv/*/Kconfig.soc" - -endif # SOC_FAMILY_INTEL_NIOSV diff --git a/soc/riscv/intel_niosv/Kconfig.defconfig b/soc/riscv/intel_niosv/Kconfig.defconfig deleted file mode 100644 index 2afa0f7e0e6059..00000000000000 --- a/soc/riscv/intel_niosv/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/intel_niosv/*/Kconfig.defconfig.series" diff --git a/soc/riscv/intel_niosv/Kconfig.soc b/soc/riscv/intel_niosv/Kconfig.soc deleted file mode 100644 index 8567429c61f6c4..00000000000000 --- a/soc/riscv/intel_niosv/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/intel_niosv/*/Kconfig.series" diff --git a/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series b/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series deleted file mode 100644 index 15e98314c8937b..00000000000000 --- a/soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NIOSV - -config SOC_SERIES - default "niosv" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config NUM_IRQS # Platform interrupts IRQs index start from index 16 - default 32 - -config RISCV_GP - default y - -config RISCV_SOC_INTERRUPT_INIT - default y - -endif # SOC_NIOSV diff --git a/soc/riscv/intel_niosv/niosv/Kconfig.series b/soc/riscv/intel_niosv/niosv/Kconfig.series deleted file mode 100644 index 9d7aa4926921cb..00000000000000 --- a/soc/riscv/intel_niosv/niosv/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NIOSV - bool "INTEL FPGA NIOSV" - select RISCV - select RISCV_PRIVILEGED - select SOC_FAMILY_INTEL_NIOSV - help - Enable support for the INTEL FPGA NIOSV. diff --git a/soc/riscv/intel_niosv/niosv/Kconfig.soc b/soc/riscv/intel_niosv/niosv/Kconfig.soc deleted file mode 100644 index 67da5ccee383c6..00000000000000 --- a/soc/riscv/intel_niosv/niosv/Kconfig.soc +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (C) 2023, Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "FPGA NIOSV" - depends on SOC_SERIES_NIOSV - -config SOC_NIOSV_M - bool "Intel FPGA NIOSV Microcontroller Core Processor" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -config SOC_NIOSV_G - bool "Intel FPGA NIOSV General Purpose Processor" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/ite_ec/Kconfig b/soc/riscv/ite_ec/Kconfig deleted file mode 100644 index 54628029a4ece1..00000000000000 --- a/soc/riscv/ite_ec/Kconfig +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ITE_EC - bool - help - ITE Embedded Controller SoC family - -if SOC_FAMILY_ITE_EC - -config SOC_FAMILY - string - default "ite_ec" - -source "soc/riscv/ite_ec/*/Kconfig.soc" - -endif # SOC_FAMILY_ITE_EC diff --git a/soc/riscv/ite_ec/Kconfig.defconfig b/soc/riscv/ite_ec/Kconfig.defconfig deleted file mode 100644 index 8994f47abd9c87..00000000000000 --- a/soc/riscv/ite_ec/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/ite_ec/*/Kconfig.defconfig.series" diff --git a/soc/riscv/ite_ec/Kconfig.soc b/soc/riscv/ite_ec/Kconfig.soc deleted file mode 100644 index 13f951c04666c3..00000000000000 --- a/soc/riscv/ite_ec/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/ite_ec/*/Kconfig.series" diff --git a/soc/riscv/ite_ec/it8xxx2/CMakeLists.txt b/soc/riscv/ite_ec/it8xxx2/CMakeLists.txt deleted file mode 100644 index df4d9021745f96..00000000000000 --- a/soc/riscv/ite_ec/it8xxx2/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -zephyr_sources( - soc.c -) -zephyr_library_sources_ifndef(CONFIG_RISCV_ISA_EXT_M __arithmetic.S) -zephyr_sources_ifdef(CONFIG_SOC_IT8XXX2_USE_ILM ilm.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld - CACHE INTERNAL "SoC Linker script ${SOC_NAME}" -) diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82302ax b/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82302ax deleted file mode 100644 index 9dd33cc00eccdf..00000000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it82302ax +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2023 ITE Corporation. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_IT82302_AX - -config SOC - default "it82302ax" - -endif diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series b/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series deleted file mode 100644 index 0ed7358b631db0..00000000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series +++ /dev/null @@ -1,59 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ITE_IT8XXX2 - -config SOC_SERIES - default "it8xxx2" - -config RISCV_GP - default y - -config ARCH_HAS_CUSTOM_BUSY_WAIT - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config SYS_CLOCK_TICKS_PER_SEC - default 4096 - -config UART_NS16550_WA_ISR_REENABLE_INTERRUPT - default y - depends on UART_NS16550 - -config FLASH_INIT_PRIORITY - default 0 - -config IT8XXX2_PLL_SEQUENCE_PRIORITY - int - default 1 - depends on SOC_IT8XXX2_PLL_FLASH_48M - -config VCMP_IT8XXX2_INIT_PRIORITY - default 91 if VCMP_IT8XXX2_WORKQUEUE - -config PINCTRL - default y - -config NUM_IRQS - default 185 - -config DYNAMIC_INTERRUPTS - default y - -config GEN_ISR_TABLES - default y - -config GEN_IRQ_START_VECTOR - default 0 - -config GEN_SW_ISR_TABLE - default y - -config RISCV_SOC_INTERRUPT_INIT - default y - -source "soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.it8*" - -endif # SOC_SERIES_ITE_IT8XXX2 diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.series b/soc/riscv/ite_ec/it8xxx2/Kconfig.series deleted file mode 100644 index 265bf855f12c30..00000000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ITE_IT8XXX2 - bool "ITE IT8XXX2 implementation" - #depends on RISCV - # RV32IAFC is an uncommon configuration which is not supported by - # default in most toolchains, causing link-time errors. - select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M - select SOC_FAMILY_ITE_EC - select HAS_PM - help - Enable support for ITE IT8XXX2 diff --git a/soc/riscv/ite_ec/it8xxx2/Kconfig.soc b/soc/riscv/ite_ec/it8xxx2/Kconfig.soc deleted file mode 100644 index d918318dfaaaaa..00000000000000 --- a/soc/riscv/ite_ec/it8xxx2/Kconfig.soc +++ /dev/null @@ -1,173 +0,0 @@ -# Copyright (c) 2020 ITE Corporation. All Rights Reserved. -# SPDX-License-Identifier: Apache-2.0 - -choice -prompt "ITE IT8XXX2 system implementation" -depends on SOC_SERIES_ITE_IT8XXX2 - -config SOC_IT8XXX2 - bool "ITE IT8XXX2 system implementation" - select RISCV - select ATOMIC_OPERATIONS_BUILTIN - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - # Workaround mul instruction bug, see: - # https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf - select RISCV_ISA_EXT_M if !(SOC_IT81302_BX || SOC_IT81202_BX) - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select FLASH - select FLASH_HAS_PAGE_LAYOUT - select FLASH_HAS_DRIVER_ENABLED - select HAS_FLASH_LOAD_OFFSET - -endchoice - -config SOC_IT8XXX2_REG_SET_V1 - bool - help - This option is selected by a variable of which soc, and will - determine the register for the IT81xx2 specification. - -config SOC_IT8XXX2_REG_SET_V2 - bool - help - This option is selected by a variable of which soc, and will - determine the register for the IT82xx2 specification. - -if SOC_IT8XXX2 - -choice IT8XXX2_SERIES - prompt "IT8XXX2 Series" - default SOC_IT81302_BX - -config SOC_IT81302_BX - bool "IT81302 BX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT81202_BX - bool "IT81202 BX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT81302_CX - bool "IT81302 CX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT81202_CX - bool "IT81202 CX version" - select SOC_IT8XXX2_REG_SET_V1 - -config SOC_IT82202_AX - bool "IT82202 AX version" - select SOC_IT8XXX2_REG_SET_V2 - select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED - -config SOC_IT82302_AX - bool "IT82302 AX version" - select SOC_IT8XXX2_REG_SET_V2 - select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED - -config SOC_IT82002_AW - bool "IT82002 AW version" - select SOC_IT8XXX2_REG_SET_V2 - select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED - -endchoice - -config SOC_IT8XXX2_PLL_FLASH_48M - bool "Flash frequency is 48MHz" - default y - help - Change frequency of PLL, CPU, and flash to 48MHz during initialization. - - Set n to use the default settings. - (PLL and CPU run at 48MHz, flash frequency is 16MHz) - -config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN - bool "The pins of GPIO group K and L aren't bonding with pad" - default y - help - On IT81202 (128-pins package), the pins of GPIO group K and L aren't - bonding with pad. So we configure these pins as internal pull-down - at default to prevent leakage current due to floating. - -config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW - bool "The GPIOH7 isn't bonding with pad and is left floating internally" - default y - help - On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left - floating internally. We need to enable internal pull-down for the pin - to prevent leakage current, but IT81202/IT81302 doesn't have the - capability to pull it down. We can only set it as output low, - so we enable output low for it at initialization to prevent leakage. - -config SOC_IT8XXX2_CPU_IDLE_GATING - bool - help - This option determines whether the entering CPU idle mode can be - gated by individual drivers. When this option is disabled, CPU idle - mode is always permitted. - -config SOC_IT8XXX2_EC_BUS_24MHZ - bool "EC bus is 24MHz" - help - Raise EC bus to 24MHz (default is 8MHz). - This reduces read/write EC registers latency by 50%. - NOTE: There is limitation to enabling this config on it81xx2 series. - The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will - be fixed at 400KHz. - -choice - prompt "Clock source for PLL reference clock" - -config SOC_IT8XXX2_INT_32K - bool "Use the +/-2.3% internal clock generator" - -config SOC_IT8XXX2_EXT_32K - bool "Use external 32.768 kHz clock source" - -endchoice - -config SOC_IT8XXX2_USE_ILM - bool - default y - help - If enabled, Instruction Local Memory (ILM) will be configured to execute - code placed in the .__ram_code section out of RAM. This consumes RAM in - blocks of 4 kilobytes, but performance of code in ILM is much more - predictable than executing from Flash directly, and some code (such as code - that writes to the internal Flash) must execute out of RAM. - -config SOC_IT8XXX2_EXCEPTIONS_IN_RAM - bool "Place exception handling code in RAM" - default y - select SOC_IT8XXX2_USE_ILM - help - Place exception handling (ISR entry/exit and related) code in ILM, which - has more reliable performance characteristics than executing directly from - Flash. This can significantly improve performance when under I-cache - pressure. - -config SOC_IT8XXX2_SHA256_HW_ACCELERATE - bool "HW SHA256 calculation" - help - IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW. - We place SHA256 message, hash and key data (total 512bytes) in RAM. - If we enable this config, because HW limits, the sha256 data must place in - first 4KB of RAM. - -DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash - -config SOC_IT8XXX2_FLASH_SIZE_BYTES - hex - default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH)) - help - Total size of writable flash. - -config ILM_MAX_SIZE - int "ILM Size in kB" - default 60 if SOC_IT81202_CX || SOC_IT81302_CX - default SRAM_SIZE - -endif # SOC_IT8XXX2 diff --git a/soc/riscv/litex_vexriscv/CMakeLists.txt b/soc/riscv/litex_vexriscv/CMakeLists.txt deleted file mode 100644 index 98386f6b57a60d..00000000000000 --- a/soc/riscv/litex_vexriscv/CMakeLists.txt +++ /dev/null @@ -1,12 +0,0 @@ -# -# Copyright (c) 2018 - 2019 Antmicro -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_sources( - ../common/riscv-privileged/soc_irq.S - ../common/riscv-privileged/vector.S -) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/litex_vexriscv/Kconfig.defconfig b/soc/riscv/litex_vexriscv/Kconfig.defconfig deleted file mode 100644 index 0088420459f025..00000000000000 --- a/soc/riscv/litex_vexriscv/Kconfig.defconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RISCV32_LITEX_VEXRISCV - -config SOC - default "litex_vexriscv" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 100000000 - -config NUM_IRQS - default 12 - -endif # SOC_RISCV32_LITEX_VEXRISCV diff --git a/soc/riscv/litex_vexriscv/Kconfig.soc b/soc/riscv/litex_vexriscv/Kconfig.soc deleted file mode 100644 index a7e632e3afdeba..00000000000000 --- a/soc/riscv/litex_vexriscv/Kconfig.soc +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2018 - 2019 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RISCV32_LITEX_VEXRISCV - bool "LiteX VexRiscv system implementation" - select RISCV - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -if SOC_RISCV32_LITEX_VEXRISCV - -config LITEX_CSR_DATA_WIDTH - int "Select Control/Status register width" - default 32 - -endif # SOC_RISCV32_LITEX_VEXRISCV diff --git a/soc/riscv/microchip_miv/CMakeLists.txt b/soc/riscv/microchip_miv/CMakeLists.txt deleted file mode 100644 index 69b2926358e5cf..00000000000000 --- a/soc/riscv/microchip_miv/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/microchip_miv/Kconfig b/soc/riscv/microchip_miv/Kconfig deleted file mode 100644 index 46616636aa1277..00000000000000 --- a/soc/riscv/microchip_miv/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_MICROCHIP_MIV - bool - -if SOC_FAMILY_MICROCHIP_MIV - -config SOC_FAMILY - string - default "microchip_miv" - -source "soc/riscv/microchip_miv/*/Kconfig.soc" - -endif # SOC_FAMILY_MICROCHIP_MIV diff --git a/soc/riscv/microchip_miv/Kconfig.defconfig b/soc/riscv/microchip_miv/Kconfig.defconfig deleted file mode 100644 index 2fe508bddbac0e..00000000000000 --- a/soc/riscv/microchip_miv/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/microchip_miv/*/Kconfig.defconfig.series" diff --git a/soc/riscv/microchip_miv/Kconfig.soc b/soc/riscv/microchip_miv/Kconfig.soc deleted file mode 100644 index 8677f1ba44875a..00000000000000 --- a/soc/riscv/microchip_miv/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/microchip_miv/*/Kconfig.series" diff --git a/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series b/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series deleted file mode 100644 index 35f4365b02b6bd..00000000000000 --- a/soc/riscv/microchip_miv/miv/Kconfig.defconfig.series +++ /dev/null @@ -1,29 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_MIV - -config SOC_SERIES - default "miv" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 4000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 30 - -config NUM_IRQS - default 42 - -endif # SOC_SERIES_MIV diff --git a/soc/riscv/microchip_miv/miv/Kconfig.series b/soc/riscv/microchip_miv/miv/Kconfig.series deleted file mode 100644 index 9f3486196246c6..00000000000000 --- a/soc/riscv/microchip_miv/miv/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV32_MIV implementation - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_MIV - bool "Microchip Mi-V implementation" - select SOC_FAMILY_MICROCHIP_MIV - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Microchip Mi-V diff --git a/soc/riscv/microchip_miv/miv/Kconfig.soc b/soc/riscv/microchip_miv/miv/Kconfig.soc deleted file mode 100644 index 0a48c2e0524e41..00000000000000 --- a/soc/riscv/microchip_miv/miv/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# RISCV32_MIV configuration options - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Microchip Mi-V system implementation" - depends on SOC_SERIES_MIV - -config SOC_MIV - bool "Microchip Mi-V system implementation" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/microchip_miv/polarfire/CMakeLists.txt b/soc/riscv/microchip_miv/polarfire/CMakeLists.txt deleted file mode 100644 index 316f08474bab7d..00000000000000 --- a/soc/riscv/microchip_miv/polarfire/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources() - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series b/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series deleted file mode 100644 index 53e88f1096efa9..00000000000000 --- a/soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2020-2021 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_POLARFIRE - -config SOC_SERIES - default "polarfire" - -# MPFS should be configured so that the mtimer clock is 1MHz independent of the CPU clock... - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 13 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 186 - -config NUM_IRQS - default 186 - -endif # SOC_SERIES_POLARFIRE diff --git a/soc/riscv/microchip_miv/polarfire/Kconfig.series b/soc/riscv/microchip_miv/polarfire/Kconfig.series deleted file mode 100644 index 59ec4dbdd7a98f..00000000000000 --- a/soc/riscv/microchip_miv/polarfire/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV64_MIV implementation - -# Copyright (c) 2018 Antmicro -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_POLARFIRE - bool "Microchip RV64 implementation" - select SOC_FAMILY_MICROCHIP_MIV - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Microchip RISCV 64bit diff --git a/soc/riscv/microchip_miv/polarfire/Kconfig.soc b/soc/riscv/microchip_miv/polarfire/Kconfig.soc deleted file mode 100644 index 101e8b4d02940b..00000000000000 --- a/soc/riscv/microchip_miv/polarfire/Kconfig.soc +++ /dev/null @@ -1,30 +0,0 @@ -# RISCV64_MIV Microchip Polarfire SOC configuration options - -# Copyright (c) 2020-2021 Microchip Technology Inc -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Microchip Polarfire SOC implementation" - depends on SOC_SERIES_POLARFIRE - -config SOC_POLARFIRE - bool "Microchip MPFS system implementation" - select ATOMIC_OPERATIONS_BUILTIN - select RISCV_GP - select USE_SWITCH_SUPPORTED - select USE_SWITCH - select CPU_HAS_FPU - select SCHED_IPI_SUPPORTED - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice - -config MPFS_HAL - depends on SOC_POLARFIRE - bool "Microchip Polarfire SOC hardware abstracton layer" - select HAS_MPFS_HAL diff --git a/soc/riscv/neorv32/Kconfig.defconfig b/soc/riscv/neorv32/Kconfig.defconfig deleted file mode 100644 index bc37ea74727dce..00000000000000 --- a/soc/riscv/neorv32/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -if SOC_NEORV32 - -config SOC - default "neorv32" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER - -config NUM_IRQS - default 32 - -config RISCV_GP - default y - -config SYSCON - default y - -config SERIAL_INIT_PRIORITY - default 55 - depends on SERIAL - -config ENTROPY_INIT_PRIORITY - default 55 - depends on ENTROPY_GENERATOR - -endif # SOC_NEORV32 diff --git a/soc/riscv/neorv32/Kconfig.soc b/soc/riscv/neorv32/Kconfig.soc deleted file mode 100644 index 3155d1b7c31c2c..00000000000000 --- a/soc/riscv/neorv32/Kconfig.soc +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (c) 2021 Henrik Brix Andersen -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NEORV32 - bool "NEORV32 Processor" - select RISCV - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_PRIVILEGED - help - Enable support for the NEORV32 Processor (SoC). - - The NEORV32 CPU implementation must have the following RISC-V ISA - extensions enabled in order to support Zephyr: - - M (Integer Multiplication and Division) - - Zicsr (Control and Status Register (CSR) Instructions) - - The following NEORV32 CPU ISA extensions are not currently supported - by Zephyr and can safely be disabled: - - A (Atomic Instructions) - - E (Embedded, only 16 integer registers) - - Zbb (Basic Bit Manipulation) - - Zfinx (Floating Point in Integer Registers) - -if SOC_NEORV32 - -config SOC_NEORV32_V1_8_6 - bool "v1.8.6" - # NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO - select ATOMIC_OPERATIONS_C - -config SOC_NEORV32_VERSION - hex - default 0x01080600 if SOC_NEORV32_V1_8_6 - help - The targeted NEORV32 version as BCD-coded number. The format is - identical to that of the NEORV32 Machine implementation ID (mimpid) - register. - -config SOC_NEORV32_ISA_C - bool "RISC-V ISA Extension \"C\"" - select RISCV_ISA_EXT_C - help - Enable this if the NEORV32 CPU implementation supports the RISC-V ISA - "C" extension (Compressed Instructions). - -endif # SOC_NEORV32 diff --git a/soc/riscv/nordic_nrf/Kconfig b/soc/riscv/nordic_nrf/Kconfig deleted file mode 100644 index a39db4671d5cd1..00000000000000 --- a/soc/riscv/nordic_nrf/Kconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NRF - bool - -if SOC_FAMILY_NRF - -config SOC_FAMILY - string - default "nordic_nrf" - -source "soc/riscv/nordic_nrf/common/Kconfig" - -source "soc/common/nordic_nrf/Kconfig.peripherals" -source "soc/riscv/nordic_nrf/*/Kconfig.soc" - -endif # SOC_FAMILY_NRF diff --git a/soc/riscv/nordic_nrf/Kconfig.defconfig b/soc/riscv/nordic_nrf/Kconfig.defconfig deleted file mode 100644 index cc3ec9549854ea..00000000000000 --- a/soc/riscv/nordic_nrf/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_NRF - -source "soc/riscv/nordic_nrf/*/Kconfig.defconfig.series" -source "soc/riscv/nordic_nrf/common/Kconfig.defconfig" - -config BUILD_OUTPUT_HEX - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 if NRF_GRTC_TIMER - default 32768 if NRF_RTC_TIMER - -endif # SOC_FAMILY_NRF diff --git a/soc/riscv/nordic_nrf/Kconfig.soc b/soc/riscv/nordic_nrf/Kconfig.soc deleted file mode 100644 index 593d6f91769b0d..00000000000000 --- a/soc/riscv/nordic_nrf/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/nordic_nrf/*/Kconfig.series" diff --git a/soc/riscv/nordic_nrf/common/CMakeLists.txt b/soc/riscv/nordic_nrf/common/CMakeLists.txt deleted file mode 100644 index 806a295ea22ca6..00000000000000 --- a/soc/riscv/nordic_nrf/common/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr) diff --git a/soc/riscv/nordic_nrf/common/Kconfig b/soc/riscv/nordic_nrf/common/Kconfig deleted file mode 100644 index 610689ecc6dfdd..00000000000000 --- a/soc/riscv/nordic_nrf/common/Kconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/nordic_nrf/common/vpr/Kconfig" diff --git a/soc/riscv/nordic_nrf/common/Kconfig.defconfig b/soc/riscv/nordic_nrf/common/Kconfig.defconfig deleted file mode 100644 index 9beb943edb8045..00000000000000 --- a/soc/riscv/nordic_nrf/common/Kconfig.defconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if RISCV_CORE_NORDIC_VPR - -source "soc/riscv/nordic_nrf/common/vpr/Kconfig.defconfig" - -endif # RISCV_CORE_NORDIC_VPR diff --git a/soc/riscv/nordic_nrf/common/vpr/CMakeLists.txt b/soc/riscv/nordic_nrf/common/vpr/CMakeLists.txt deleted file mode 100644 index e0331bb8e0ba6e..00000000000000 --- a/soc/riscv/nordic_nrf/common/vpr/CMakeLists.txt +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(.) - -zephyr_library() -zephyr_library_sources(soc_irq.S soc_irq.c vector.S) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/nordic_nrf/nrf54h/CMakeLists.txt b/soc/riscv/nordic_nrf/nrf54h/CMakeLists.txt deleted file mode 100644 index 5b37b3a54d893f..00000000000000 --- a/soc/riscv/nordic_nrf/nrf54h/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -# Ensure that image size aligns with 16 bytes so that MRAMC finalizes all writes -# for the image correctly -zephyr_linker_sources(SECTIONS SORT_KEY zzz_place_align_at_end align.ld) diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.series b/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.series deleted file mode 100644 index 0f827fbe96b2df..00000000000000 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.defconfig.series +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NRF54HX - -rsource "Kconfig.defconfig.nrf54h*" - -config SOC_SERIES - default "nrf54h" - -DT_CHOSEN_Z_SRAM = zephyr,sram -DT_CHOSEN_Z_CODE = zephyr,code-partition - -config BUILD_OUTPUT_ADJUST_LMA - depends on !XIP - default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_Z_CODE)) - \ - $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM))" - -endif # SOC_SERIES_NRF54HX diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.series b/soc/riscv/nordic_nrf/nrf54h/Kconfig.series deleted file mode 100644 index acb85b5623a670..00000000000000 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NRF54HX - bool "Nordic Semiconductor nRF54H series MCU" - select SOC_FAMILY_NRF - select HAS_NRFX - select HAS_NORDIC_DRIVERS - help - Enable support for nRF54H MCU series diff --git a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc b/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc deleted file mode 100644 index 760e05a0e64c0d..00000000000000 --- a/soc/riscv/nordic_nrf/nrf54h/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_NRF54H20 - bool "nRF54H20" - depends on SOC_SERIES_NRF54HX - -if SOC_NRF54H20 - -choice - prompt "nRF54Hx MCU Selection" - -config SOC_NRF54H20_ENGA_CPUPPR - bool "nRF54H20 ENGA CPUPPR" - depends on RISCV_CORE_NORDIC_VPR - -endchoice - -endif # SOC_NRF54H20 diff --git a/soc/riscv/nordic_nrf/nrf54h/align.ld b/soc/riscv/nordic_nrf/nrf54h/align.ld deleted file mode 100644 index 0905aa7f7bccdf..00000000000000 --- a/soc/riscv/nordic_nrf/nrf54h/align.ld +++ /dev/null @@ -1,10 +0,0 @@ -/* - * Copyright (c) 2024 Nordic Semiconductor ASA. - * SPDX-License-Identifier: Apache-2.0 - */ - -SECTION_PROLOGUE(.align16,,) -{ - . = (ALIGN(16) > 0 ? ALIGN(16) : 16) - 1; - BYTE(0); -} GROUP_LINK_IN(ROMABLE_REGION) diff --git a/soc/riscv/openisa_rv32m1/CMakeLists.txt b/soc/riscv/openisa_rv32m1/CMakeLists.txt deleted file mode 100644 index a7a722279c3420..00000000000000 --- a/soc/riscv/openisa_rv32m1/CMakeLists.txt +++ /dev/null @@ -1,24 +0,0 @@ -# Copyright (c) 2018 Foundries.io Ltd -# -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_SOC_OPENISA_RV32M1_RI5CY) - if (CONFIG_RISCV_GENERIC_TOOLCHAIN) - zephyr_compile_options(-march=rv32imc_zicsr_zifencei) - else() - zephyr_compile_options(-march=rv32imcxpulpv2) - endif() -elseif(CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY) - zephyr_compile_options(-march=rv32imc_zicsr_zifencei) -endif() - -zephyr_sources( - vector.S - soc_irq.S - wdog.S - soc.c -) - -zephyr_linker_sources(ROM_START SORT_KEY 0x0vectors vector_table.ld) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/openisa_rv32m1/Kconfig b/soc/riscv/openisa_rv32m1/Kconfig deleted file mode 100644 index b9dc0e55f1102e..00000000000000 --- a/soc/riscv/openisa_rv32m1/Kconfig +++ /dev/null @@ -1,25 +0,0 @@ -# Copyright (c) 2018 Foundries.io Ltd -# SPDX-License-Identifier: Apache-2.0 - -# The OpenISA RV32M1 SoC directory in riscv supports the RISC-V -# cores on OpenISA RV32M1 SoCs. -# -# The Zephyr "soc" abstraction isn't a great fit here. These SoCs (in -# the strict physical sense of "systems on chip") also contain Arm -# cores, so this type of "soc" doesn't really belong to a single "arch". -# -# However, due to constraints imposed by Zephyr's file hierarchy -# conventions, those "other" cores would need to be supported under a -# different soc subdirectory, e.g. soc/arm instead of soc/riscv. - -choice - prompt "OpenISA RV32M1 RISC-V Core Selection" - depends on SOC_OPENISA_RV32M1_RISCV32 - -config SOC_OPENISA_RV32M1_RI5CY - bool "OpenISA RV32M1 RI5CY core" - -config SOC_OPENISA_RV32M1_ZERO_RISCY - bool "OpenISA RV32M1 ZERO-RISCY core" - -endchoice diff --git a/soc/riscv/openisa_rv32m1/Kconfig.defconfig b/soc/riscv/openisa_rv32m1/Kconfig.defconfig deleted file mode 100644 index 52d652a061e64a..00000000000000 --- a/soc/riscv/openisa_rv32m1/Kconfig.defconfig +++ /dev/null @@ -1,125 +0,0 @@ -# RV32M1 SoC RISC-V core default configuration values - -# Copyright (c) 2018 Foundries.io Ltd -# SPDX-License-Identifier: Apache-2.0 - -if SOC_OPENISA_RV32M1_RISCV32 - -config SOC - default "openisa_rv32m1" - -# 32 from event unit + 32 * (1 + max enabled INTMUX channel) -config NUM_IRQS - default 288 if RV32M1_INTMUX_CHANNEL_7 - default 256 if RV32M1_INTMUX_CHANNEL_6 - default 224 if RV32M1_INTMUX_CHANNEL_5 - default 192 if RV32M1_INTMUX_CHANNEL_4 - default 160 if RV32M1_INTMUX_CHANNEL_3 - default 128 if RV32M1_INTMUX_CHANNEL_2 - default 96 if RV32M1_INTMUX_CHANNEL_1 - default 64 if RV32M1_INTMUX_CHANNEL_0 - default 32 - -config RISCV_GENERIC_TOOLCHAIN - default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" - default n - -config RISCV_SOC_CONTEXT_SAVE - default y if SOC_OPENISA_RV32M1_RI5CY - -config RISCV_SOC_OFFSETS - default y - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_MCAUSE_EXCEPTION_MASK - default 0x1F - -# We need to disable the watchdog out of reset, as it's enabled by -# default. Use the WDOG_INIT hook for doing that. -config WDOG_INIT - def_bool y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 8000000 - -if MULTI_LEVEL_INTERRUPTS - -config MAX_IRQ_PER_AGGREGATOR - default 32 - -config 2ND_LEVEL_INTERRUPTS - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 32 - -config NUM_2ND_LEVEL_AGGREGATORS - default 8 if RV32M1_INTMUX_CHANNEL_7 - default 7 if RV32M1_INTMUX_CHANNEL_6 - default 6 if RV32M1_INTMUX_CHANNEL_5 - default 5 if RV32M1_INTMUX_CHANNEL_4 - default 4 if RV32M1_INTMUX_CHANNEL_3 - default 3 if RV32M1_INTMUX_CHANNEL_2 - default 2 if RV32M1_INTMUX_CHANNEL_1 - default 1 # just channel 0 - -config 2ND_LVL_INTR_00_OFFSET - default 24 - -config 2ND_LVL_INTR_01_OFFSET - int - default 25 - -config 2ND_LVL_INTR_02_OFFSET - int - default 26 - -config 2ND_LVL_INTR_03_OFFSET - int - default 27 - -config 2ND_LVL_INTR_04_OFFSET - int - default 28 - -config 2ND_LVL_INTR_05_OFFSET - int - default 29 - -config 2ND_LVL_INTR_06_OFFSET - int - default 30 - -config 2ND_LVL_INTR_07_OFFSET - int - default 31 - -config RV32M1_INTMUX_CHANNEL_0 - default y - -config RV32M1_INTMUX_CHANNEL_1 - default y - -config RV32M1_INTMUX_CHANNEL_2 - default y - -config RV32M1_INTMUX_CHANNEL_3 - default y - -config RV32M1_INTMUX_CHANNEL_4 - default y - -config RV32M1_INTMUX_CHANNEL_5 - default y - -config RV32M1_INTMUX_CHANNEL_6 - default y - -config RV32M1_INTMUX_CHANNEL_7 - default y - -endif # MULTI_LEVEL_INTERRUPTS - -endif # SOC_OPENISA_RV32M1_RISCV32 diff --git a/soc/riscv/openisa_rv32m1/Kconfig.soc b/soc/riscv/openisa_rv32m1/Kconfig.soc deleted file mode 100644 index c1264e95b46260..00000000000000 --- a/soc/riscv/openisa_rv32m1/Kconfig.soc +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2018 Foundries.io Ltd -# SPDX-License-Identifier: Apache-2.0 - -config SOC_OPENISA_RV32M1_RISCV32 - bool "OpenISA RV32M1 RISC-V cores" - select RISCV - # The following select is due to limitations in the linker script. - # (We can't make it a 'depends on' without causing a dependency loop). - select XIP - select HAS_RV32M1_LPUART - select HAS_RV32M1_LPI2C - select HAS_RV32M1_LPSPI - select HAS_RV32M1_TPM - select ATOMIC_OPERATIONS_C - select VEGA_SDK_HAL - select RISCV_SOC_INTERRUPT_INIT - select CLOCK_CONTROL - select HAS_RV32M1_FTFX - select HAS_FLASH_LOAD_OFFSET - select BUILD_OUTPUT_HEX - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - help - Enable support for OpenISA RV32M1 RISC-V processors. Choose - this option to target the RI5CY or ZERO-RISCY core. This - option should not be used to target either Arm core. diff --git a/soc/riscv/opentitan/Kconfig.defconfig b/soc/riscv/opentitan/Kconfig.defconfig deleted file mode 100644 index 4b067ef76afba3..00000000000000 --- a/soc/riscv/opentitan/Kconfig.defconfig +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2023 Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_OPENTITAN - -config SOC - default "opentitan" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 1000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 32 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config NUM_IRQS - default 256 - -endif # SOC_OPENTITAN diff --git a/soc/riscv/opentitan/Kconfig.soc b/soc/riscv/opentitan/Kconfig.soc deleted file mode 100644 index c76cfe013b18ce..00000000000000 --- a/soc/riscv/opentitan/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# Copyright (c) 2023 Rivos Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_OPENTITAN - bool "OpenTitan implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_ISA_EXT_ZBA - select RISCV_ISA_EXT_ZBB - select RISCV_ISA_EXT_ZBC - select RISCV_ISA_EXT_ZBS - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - # OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode. - select RISCV_VECTORED_MODE - select GEN_IRQ_VECTOR_TABLE diff --git a/soc/riscv/qemu_virt_riscv/CMakeLists.txt b/soc/riscv/qemu_virt_riscv/CMakeLists.txt new file mode 100644 index 00000000000000..ce57a74e239ab5 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") +add_subdirectory(common) diff --git a/soc/riscv/qemu_virt_riscv/Kconfig b/soc/riscv/qemu_virt_riscv/Kconfig new file mode 100644 index 00000000000000..1c3382371bb46c --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_QEMU_VIRT_RISCV + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +if SOC_FAMILY_QEMU_VIRT_RISCV + +rsource "*/Kconfig" + +endif # SOC_FAMILY_QEMU_VIRT_RISCV diff --git a/soc/riscv/qemu_virt_riscv/Kconfig.defconfig b/soc/riscv/qemu_virt_riscv/Kconfig.defconfig new file mode 100644 index 00000000000000..4eb51b6d889e26 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/Kconfig.defconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2020 Cobham Gaisler AB +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_QEMU_VIRT_RISCV + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 10000000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 1035 + +config PMP_SLOTS + default 16 + +endif # SOC_FAMILY_QEMU_VIRT_RISCV diff --git a/soc/riscv/qemu_virt_riscv/Kconfig.soc b/soc/riscv/qemu_virt_riscv/Kconfig.soc new file mode 100644 index 00000000000000..ba3a1bd5961242 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_QEMU_VIRT_RISCV + bool + +config SOC_FAMILY + default "qemu_virt_riscv" if SOC_FAMILY_QEMU_VIRT_RISCV + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt b/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt new file mode 100644 index 00000000000000..77a7ba35d26040 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/common/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) diff --git a/soc/riscv/virt/soc.c b/soc/riscv/qemu_virt_riscv/common/soc.c similarity index 100% rename from soc/riscv/virt/soc.c rename to soc/riscv/qemu_virt_riscv/common/soc.c diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig new file mode 100644 index 00000000000000..ff49d3fe3ab983 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32 + select CPU_HAS_FPU + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc new file mode 100644 index 00000000000000..4b1ee59adc1c9c --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32 + bool + select SOC_FAMILY_QEMU_VIRT_RISCV + +config SOC + default "qemu_virt_riscv32" if SOC_QEMU_VIRT_RISCV32 diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig new file mode 100644 index 00000000000000..9ad39ce22ad971 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2020 Cobham Gaisler AB +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32E + select RISCV_ISA_RV32E + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc new file mode 100644 index 00000000000000..38b51ee58ffcf9 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv32e/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV32E + bool + select SOC_FAMILY_QEMU_VIRT_RISCV + +config SOC + default "qemu_virt_riscv32e" if SOC_QEMU_VIRT_RISCV32E diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig new file mode 100644 index 00000000000000..f8560c607f0720 --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV64 + select 64BIT + select CPU_HAS_FPU_DOUBLE_PRECISION + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc new file mode 100644 index 00000000000000..cfcf51103de24d --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/qemu_virt_riscv64/Kconfig.soc @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_VIRT_RISCV64 + bool + select SOC_FAMILY_QEMU_VIRT_RISCV + +config SOC + default "qemu_virt_riscv64" if SOC_QEMU_VIRT_RISCV64 diff --git a/soc/riscv/qemu_virt_riscv/soc.yml b/soc/riscv/qemu_virt_riscv/soc.yml new file mode 100644 index 00000000000000..746051f76a902c --- /dev/null +++ b/soc/riscv/qemu_virt_riscv/soc.yml @@ -0,0 +1,6 @@ +family: +- name: qemu_virt_riscv + socs: + - name: qemu_virt_riscv32 + - name: qemu_virt_riscv32e + - name: qemu_virt_riscv64 diff --git a/soc/riscv/renode_virt/Kconfig.defconfig b/soc/riscv/renode_virt/Kconfig.defconfig deleted file mode 100644 index fab59719595056..00000000000000 --- a/soc/riscv/renode_virt/Kconfig.defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RISCV32_VIRTUAL_RENODE - -config SOC - default "renode_virt" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 4000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 1ST_LEVEL_INTERRUPT_BITS - default 4 - -config NUM_2ND_LEVEL_AGGREGATORS - default 2 - -config 2ND_LEVEL_INTERRUPT_BITS - default 11 - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config 2ND_LVL_INTR_01_OFFSET - default 4 - -config MAX_IRQ_PER_AGGREGATOR - default 1023 - -config NUM_IRQS - default 2058 - -endif # SOC_RISCV32_VIRTUAL_RENODE diff --git a/soc/riscv/renode_virt/Kconfig.soc b/soc/riscv/renode_virt/Kconfig.soc deleted file mode 100644 index ba42c40c28d1e8..00000000000000 --- a/soc/riscv/renode_virt/Kconfig.soc +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Meta -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RISCV32_VIRTUAL_RENODE - bool "Renode RISCV32 Virtual system implementation" - select RISCV - select RISCV_PRIVILEGED - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_HAS_PLIC diff --git a/soc/riscv/sifive_freedom/CMakeLists.txt b/soc/riscv/sifive_freedom/CMakeLists.txt deleted file mode 100644 index 6a5b10545ff103..00000000000000 --- a/soc/riscv/sifive_freedom/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/sifive_freedom/Kconfig b/soc/riscv/sifive_freedom/Kconfig deleted file mode 100644 index 0fed11158afca5..00000000000000 --- a/soc/riscv/sifive_freedom/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_SIFIVE_FREEDOM - bool - -if SOC_FAMILY_SIFIVE_FREEDOM - -config SOC_FAMILY - string - default "sifive_freedom" - -source "soc/riscv/sifive_freedom/*/Kconfig.soc" - -endif # SOC_FAMILY_SIFIVE_FREEDOM diff --git a/soc/riscv/sifive_freedom/Kconfig.defconfig b/soc/riscv/sifive_freedom/Kconfig.defconfig deleted file mode 100644 index 5adf8fc437e54c..00000000000000 --- a/soc/riscv/sifive_freedom/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/sifive_freedom/*/Kconfig.defconfig.series" diff --git a/soc/riscv/sifive_freedom/Kconfig.soc b/soc/riscv/sifive_freedom/Kconfig.soc deleted file mode 100644 index 54274defd919aa..00000000000000 --- a/soc/riscv/sifive_freedom/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/sifive_freedom/*/Kconfig.series" diff --git a/soc/riscv/sifive_freedom/e300/CMakeLists.txt b/soc/riscv/sifive_freedom/e300/CMakeLists.txt deleted file mode 100644 index baf01a6b047377..00000000000000 --- a/soc/riscv/sifive_freedom/e300/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(clock.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e340 b/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e340 deleted file mode 100644 index cb0131f142706a..00000000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e340 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "e340" if SOC_SIFIVE_FREEDOM_E340 diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series deleted file mode 100644 index eaa43e68e705e9..00000000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SIFIVE_FREEDOM_E300 - -config SOC_SERIES - default "e300" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -source "soc/riscv/sifive_freedom/e300/Kconfig.defconfig.e*" - -endif # SOC_SERIES_SIFIVE_FREEDOM_E300 diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.series b/soc/riscv/sifive_freedom/e300/Kconfig.series deleted file mode 100644 index 81634da000d4b3..00000000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC implementation - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SIFIVE_FREEDOM_E300 - bool "SiFive Freedom E300 SOC implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_SIFIVE_FREEDOM - help - Enable support for SiFive Freedom FE300 SOC diff --git a/soc/riscv/sifive_freedom/e300/Kconfig.soc b/soc/riscv/sifive_freedom/e300/Kconfig.soc deleted file mode 100644 index e53b84c08907d1..00000000000000 --- a/soc/riscv/sifive_freedom/e300/Kconfig.soc +++ /dev/null @@ -1,20 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC configuration options - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "SiFive Freedom SOC implementation" - depends on SOC_SERIES_SIFIVE_FREEDOM_E300 - -config SOC_SIFIVE_FREEDOM_E340 - bool "SiFive Freedom SOC implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/sifive_freedom/u500/CMakeLists.txt b/soc/riscv/sifive_freedom/u500/CMakeLists.txt deleted file mode 100644 index baf01a6b047377..00000000000000 --- a/soc/riscv/sifive_freedom/u500/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(clock.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series deleted file mode 100644 index d306b60252a708..00000000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SIFIVE_FREEDOM_U500 - -config SOC_SERIES - default "u500" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -source "soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u*" - -endif # SOC_SERIES_SIFIVE_FREEDOM_U500 diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u540 b/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u540 deleted file mode 100644 index f559f5914b3f09..00000000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.defconfig.u540 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "u540" if SOC_SIFIVE_FREEDOM_U540 diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.series b/soc/riscv/sifive_freedom/u500/Kconfig.series deleted file mode 100644 index 7335a1a529366c..00000000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC implementation - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SIFIVE_FREEDOM_U500 - bool "SiFive Freedom U500 SOC implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_SIFIVE_FREEDOM - help - Enable support for SiFive Freedom U500 SOC diff --git a/soc/riscv/sifive_freedom/u500/Kconfig.soc b/soc/riscv/sifive_freedom/u500/Kconfig.soc deleted file mode 100644 index 0a88ccf8cc1ffd..00000000000000 --- a/soc/riscv/sifive_freedom/u500/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC configuration options - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "SiFive Freedom SOC implementation" - depends on SOC_SERIES_SIFIVE_FREEDOM_U500 - -config SOC_SIFIVE_FREEDOM_U540 - bool "SiFive Freedom U540 SOC implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select 64BIT - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/sifive_freedom/u700/CMakeLists.txt b/soc/riscv/sifive_freedom/u700/CMakeLists.txt deleted file mode 100644 index baf01a6b047377..00000000000000 --- a/soc/riscv/sifive_freedom/u700/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(clock.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series b/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series deleted file mode 100644 index a0e730d608f86c..00000000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_SIFIVE_FREEDOM_U700 - -config SOC_SERIES - default "u700" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 64 - -source "soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u*" - -endif # SOC_SERIES_SIFIVE_FREEDOM_U700 diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u740 b/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u740 deleted file mode 100644 index ca935f772eb002..00000000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.defconfig.u740 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "u740" if SOC_SIFIVE_FREEDOM_U740 diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.series b/soc/riscv/sifive_freedom/u700/Kconfig.series deleted file mode 100644 index 04bdc1fb9b2bca..00000000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.series +++ /dev/null @@ -1,13 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC implementation - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_SIFIVE_FREEDOM_U700 - bool "SiFive Freedom SOC U700 implementation" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select SOC_FAMILY_SIFIVE_FREEDOM - help - Enable support for SiFive Freedom U700 SOC diff --git a/soc/riscv/sifive_freedom/u700/Kconfig.soc b/soc/riscv/sifive_freedom/u700/Kconfig.soc deleted file mode 100644 index 1eec9b4bb17a71..00000000000000 --- a/soc/riscv/sifive_freedom/u700/Kconfig.soc +++ /dev/null @@ -1,22 +0,0 @@ -# RISCV_SIFIVE_FREEDOM SOC configuration options - -# Copyright (c) 2017 Jean-Paul Etienne -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "SiFive Freedom SOC implementation" - depends on SOC_SERIES_SIFIVE_FREEDOM_U700 - -config SOC_SIFIVE_FREEDOM_U740 - bool "SiFive Freedom U740 SOC implementation" - select ATOMIC_OPERATIONS_C - select INCLUDE_RESET_VECTOR - select 64BIT - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/starfive_jh71xx/CMakeLists.txt b/soc/riscv/starfive_jh71xx/CMakeLists.txt deleted file mode 100644 index 69b2926358e5cf..00000000000000 --- a/soc/riscv/starfive_jh71xx/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/starfive_jh71xx/Kconfig b/soc/riscv/starfive_jh71xx/Kconfig deleted file mode 100644 index 65694c07eff78f..00000000000000 --- a/soc/riscv/starfive_jh71xx/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_STARFIVE_JH71XX - bool - -if SOC_FAMILY_STARFIVE_JH71XX - -config SOC_FAMILY - string - default "starfive_jh71xx" - -source "soc/riscv/starfive_jh71xx/*/Kconfig.soc" - -endif # SOC_FAMILY_STARFIVE_JH71XX diff --git a/soc/riscv/starfive_jh71xx/Kconfig.defconfig b/soc/riscv/starfive_jh71xx/Kconfig.defconfig deleted file mode 100644 index b399e38b3406df..00000000000000 --- a/soc/riscv/starfive_jh71xx/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/starfive_jh71xx/*/Kconfig.defconfig.series" diff --git a/soc/riscv/starfive_jh71xx/Kconfig.soc b/soc/riscv/starfive_jh71xx/Kconfig.soc deleted file mode 100644 index 1ff54faa97013d..00000000000000 --- a/soc/riscv/starfive_jh71xx/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/starfive_jh71xx/*/Kconfig.series" diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh7100 b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh7100 deleted file mode 100644 index 6f38d61dd4e5ce..00000000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh7100 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "jh7100" if SOC_JH7100 diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series deleted file mode 100644 index 0f058cb6c252d1..00000000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2021 Rajnesh Kanwal -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_STARFIVE_JH71XX - -config SOC_SERIES - default "jh71xx" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 6250000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config NUM_IRQS - default 139 - -source "soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.jh71*" - -endif diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.series b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.series deleted file mode 100644 index f392a5d1f9726a..00000000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.series +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2021 Rajnesh Kanwal -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_STARFIVE_JH71XX - bool "Starfive JH71XX series" - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - help - Enable support for Starfive JH71XX SoC Series. diff --git a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.soc b/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.soc deleted file mode 100644 index 8be7ebe5dbe986..00000000000000 --- a/soc/riscv/starfive_jh71xx/jh71xx/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2021 Rajnesh Kanwal -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Starfive JH7100 SoC" - depends on SOC_SERIES_STARFIVE_JH71XX - -config SOC_JH7100 - bool "Starfive JH7100" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_RV64I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - -endchoice diff --git a/soc/riscv/telink_tlsr/CMakeLists.txt b/soc/riscv/telink_tlsr/CMakeLists.txt deleted file mode 100644 index 69b2926358e5cf..00000000000000 --- a/soc/riscv/telink_tlsr/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) diff --git a/soc/riscv/telink_tlsr/Kconfig b/soc/riscv/telink_tlsr/Kconfig deleted file mode 100644 index 144751311ba963..00000000000000 --- a/soc/riscv/telink_tlsr/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_TELINK_TLSR - bool - -if SOC_FAMILY_TELINK_TLSR - -config SOC_FAMILY - string - default "telink_tlsr" - -source "soc/riscv/telink_tlsr/*/Kconfig.soc" - -endif # SOC_FAMILY_TELINK_TLSR diff --git a/soc/riscv/telink_tlsr/Kconfig.defconfig b/soc/riscv/telink_tlsr/Kconfig.defconfig deleted file mode 100644 index 04a888381fa9c1..00000000000000 --- a/soc/riscv/telink_tlsr/Kconfig.defconfig +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/telink_tlsr/*/Kconfig.defconfig.series" diff --git a/soc/riscv/telink_tlsr/Kconfig.soc b/soc/riscv/telink_tlsr/Kconfig.soc deleted file mode 100644 index db09c69d1f4ec0..00000000000000 --- a/soc/riscv/telink_tlsr/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -source "soc/riscv/telink_tlsr/*/Kconfig.series" diff --git a/soc/riscv/telink_tlsr/tlsr951x/CMakeLists.txt b/soc/riscv/telink_tlsr/tlsr951x/CMakeLists.txt deleted file mode 100644 index 8c489ac6dd7985..00000000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/CMakeLists.txt +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - start.S - soc_irq.S - soc.c -) - -# Force using BFD-LD -zephyr_ld_options(-fuse-ld=bfd) - -# Set compile options -zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp) -zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax) -zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series deleted file mode 100644 index 2b72ad9960cc2c..00000000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series +++ /dev/null @@ -1,53 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_TELINK_TLSR951X - -config SOC_SERIES - string - default "tlsr951x" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 32000 - -config RISCV_SOC_INTERRUPT_INIT - bool - default y - -config RISCV_GP - bool - default y - -config NUM_IRQS - int - default 64 - -config PINCTRL - default y - -config XIP - bool - default n - -config MAIN_STACK_SIZE - int - default 2048 - -config IDLE_STACK_SIZE - int - default 1536 - -config TEST_EXTRA_STACK_SIZE - int - default 1024 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config HAS_FLASH_LOAD_OFFSET - default y if BOOTLOADER_MCUBOOT - -source "soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr*" - -endif # SOC_SERIES_TELINK_TLSR951X diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr9518 b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr9518 deleted file mode 100644 index 4ffdebdaf6b6ec..00000000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.tlsr9518 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2024 Nordic Semiconductor ASA -# SPDX-License-Identifier: Apache-2.0 - -config SOC - default "tlsr9518" if SOC_TELINK_TLSR9518 diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.series b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.series deleted file mode 100644 index 5d5fc3226e5bd2..00000000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.series +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_TELINK_TLSR951X - bool "Telink TLSR951X" - select RISCV - select RISCV_ISA_RV32I - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV_ISA_EXT_ZICSR - select RISCV_ISA_EXT_ZIFENCEI - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC - select HAS_TELINK_DRIVERS - select ATOMIC_OPERATIONS_BUILTIN - select CPU_HAS_FPU - select INCLUDE_RESET_VECTOR - select SOC_FAMILY_TELINK_TLSR - help - Enable support for Telink TLSR951X diff --git a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.soc b/soc/riscv/telink_tlsr/tlsr951x/Kconfig.soc deleted file mode 100644 index 2abc12cc58c5b7..00000000000000 --- a/soc/riscv/telink_tlsr/tlsr951x/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Telink Semiconductor -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_TELINK_TLSR951X - -choice - prompt "Telink TLSR951X SoC implementation" - -config SOC_TELINK_TLSR9518 - bool "Telink TLSR9518" - -endchoice - -config TELINK_B91_HWDSP - bool "Support Hardware DSP" - select RISCV_SOC_CONTEXT_SAVE - -config TELINK_B91_PFT_ARCH - bool "Support performance throttling" - default y - select RISCV_SOC_CONTEXT_SAVE - -endif # SOC_SERIES_TELINK_TLSR951X diff --git a/soc/riscv/virt/CMakeLists.txt b/soc/riscv/virt/CMakeLists.txt deleted file mode 100644 index 6a1826b29f92bc..00000000000000 --- a/soc/riscv/virt/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(soc.c) - -set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/riscv/virt/Kconfig.defconfig b/soc/riscv/virt/Kconfig.defconfig deleted file mode 100644 index bed5ff8bec7bff..00000000000000 --- a/soc/riscv/virt/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RISCV_VIRT - -config SOC - default "virt" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 10000000 - -config RISCV_SOC_INTERRUPT_INIT - default y - -config RISCV_GP - default y - -config 2ND_LVL_ISR_TBL_OFFSET - default 12 - -config 2ND_LVL_INTR_00_OFFSET - default 11 - -config MAX_IRQ_PER_AGGREGATOR - default 52 - -config NUM_IRQS - default 1035 - -config PMP_SLOTS - default 16 - -endif diff --git a/soc/riscv/virt/Kconfig.soc b/soc/riscv/virt/Kconfig.soc deleted file mode 100644 index 59e553a9d7bc5e..00000000000000 --- a/soc/riscv/virt/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RISCV_VIRT - bool "QEMU RISC-V VirtIO Board" - select ATOMIC_OPERATIONS_BUILTIN - select INCLUDE_RESET_VECTOR - select RISCV_ISA_EXT_M - select RISCV_ISA_EXT_A - select RISCV_ISA_EXT_C - select RISCV - select RISCV_PRIVILEGED - select RISCV_HAS_PLIC diff --git a/soc/rockchip/CMakeLists.txt b/soc/rockchip/CMakeLists.txt new file mode 100644 index 00000000000000..5e343b6e2669dd --- /dev/null +++ b/soc/rockchip/CMakeLists.txt @@ -0,0 +1,7 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/rockchip/Kconfig b/soc/rockchip/Kconfig new file mode 100644 index 00000000000000..80f0d67eb4d949 --- /dev/null +++ b/soc/rockchip/Kconfig @@ -0,0 +1,11 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_ROCKCHIP + +rsource "*/Kconfig" + +endif # SOC_FAMILY_ROCKCHIP diff --git a/soc/rockchip/Kconfig.defconfig b/soc/rockchip/Kconfig.defconfig new file mode 100644 index 00000000000000..122e92dc999965 --- /dev/null +++ b/soc/rockchip/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_ROCKCHIP + +rsource "*/Kconfig.defconfig" + +endif diff --git a/soc/rockchip/Kconfig.soc b/soc/rockchip/Kconfig.soc new file mode 100644 index 00000000000000..2e782486499881 --- /dev/null +++ b/soc/rockchip/Kconfig.soc @@ -0,0 +1,13 @@ +# +# Copyright 2021 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_FAMILY_ROCKCHIP + bool + +config SOC_FAMILY + default "rockchip" if SOC_FAMILY_ROCKCHIP + +rsource "*/Kconfig.soc" diff --git a/soc/arm64/rockchip/rk3399/CMakeLists.txt b/soc/rockchip/rk3399/CMakeLists.txt similarity index 100% rename from soc/arm64/rockchip/rk3399/CMakeLists.txt rename to soc/rockchip/rk3399/CMakeLists.txt diff --git a/soc/rockchip/rk3399/Kconfig b/soc/rockchip/rk3399/Kconfig new file mode 100644 index 00000000000000..d85c98ec4a5543 --- /dev/null +++ b/soc/rockchip/rk3399/Kconfig @@ -0,0 +1,13 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_RK3399 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + +config SOC_PART_NUMBER + default "RK3399" if SOC_SERIES_RK3399 diff --git a/soc/rockchip/rk3399/Kconfig.defconfig b/soc/rockchip/rk3399/Kconfig.defconfig new file mode 100644 index 00000000000000..775e37bf0c9b11 --- /dev/null +++ b/soc/rockchip/rk3399/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_RK3399 + +rsource "Kconfig.defconfig.rk3399" + +endif # SOC_SERIES_RK3399 diff --git a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399 b/soc/rockchip/rk3399/Kconfig.defconfig.rk3399 similarity index 87% rename from soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399 rename to soc/rockchip/rk3399/Kconfig.defconfig.rk3399 index 53eb8ae452aee4..07751909f32099 100644 --- a/soc/arm64/rockchip/rk3399/Kconfig.defconfig.rk3399 +++ b/soc/rockchip/rk3399/Kconfig.defconfig.rk3399 @@ -6,9 +6,6 @@ if SOC_RK3399 -config SOC - default "rk3399" - config NUM_IRQS int default 240 diff --git a/soc/rockchip/rk3399/Kconfig.soc b/soc/rockchip/rk3399/Kconfig.soc new file mode 100644 index 00000000000000..9d3885591dc399 --- /dev/null +++ b/soc/rockchip/rk3399/Kconfig.soc @@ -0,0 +1,19 @@ +# +# Copyright 2022 Huawei France Technologies SASU +# +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_RK3399 + bool + select SOC_SERIES_RK3399 + +config SOC_SERIES_RK3399 + bool + select SOC_FAMILY_ROCKCHIP + +config SOC + default "rk3399" if SOC_RK3399 + +config SOC_SERIES + default "rk3399" if SOC_SERIES_RK3399 diff --git a/soc/arm64/rockchip/rk3399/mmu_regions.c b/soc/rockchip/rk3399/mmu_regions.c similarity index 100% rename from soc/arm64/rockchip/rk3399/mmu_regions.c rename to soc/rockchip/rk3399/mmu_regions.c diff --git a/soc/rockchip/rk3568/CMakeLists.txt b/soc/rockchip/rk3568/CMakeLists.txt new file mode 100644 index 00000000000000..22fc2aa11bee46 --- /dev/null +++ b/soc/rockchip/rk3568/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/rockchip/rk3568/Kconfig b/soc/rockchip/rk3568/Kconfig new file mode 100644 index 00000000000000..8fc53a80fd9f0e --- /dev/null +++ b/soc/rockchip/rk3568/Kconfig @@ -0,0 +1,12 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RK3568 + select ARM64 + select CPU_CORTEX_A55 + select ARM_ARCH_TIMER + select GIC_V3 + +config SOC_PART_NUMBER + default "RK3568" if SOC_SERIES_RK3568 diff --git a/soc/rockchip/rk3568/Kconfig.defconfig b/soc/rockchip/rk3568/Kconfig.defconfig new file mode 100644 index 00000000000000..b7f52249abe261 --- /dev/null +++ b/soc/rockchip/rk3568/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_RK3568 + +rsource "Kconfig.defconfig.rk3568" + +endif # SOC_SERIES_RK3568 diff --git a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 b/soc/rockchip/rk3568/Kconfig.defconfig.rk3568 similarity index 90% rename from soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 rename to soc/rockchip/rk3568/Kconfig.defconfig.rk3568 index 13dca55c6e9eca..58cf932996f569 100644 --- a/soc/arm64/rockchip/rk3568/Kconfig.defconfig.rk3568 +++ b/soc/rockchip/rk3568/Kconfig.defconfig.rk3568 @@ -4,9 +4,6 @@ if SOC_RK3568 -config SOC - default "rk3568" - config FLASH_SIZE default 0 diff --git a/soc/rockchip/rk3568/Kconfig.soc b/soc/rockchip/rk3568/Kconfig.soc new file mode 100644 index 00000000000000..7d965d764cbcc0 --- /dev/null +++ b/soc/rockchip/rk3568/Kconfig.soc @@ -0,0 +1,17 @@ +# Copyright 2022 HNU-ESNL +# Copyright 2022 openEuler SIG-Zephyr +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_RK3568 + bool + select SOC_FAMILY_ROCKCHIP + +config SOC_RK3568 + bool + select SOC_SERIES_RK3568 + +config SOC + default "rk3568" if SOC_RK3568 + +config SOC_SERIES + default "rk3568" if SOC_RK3568 diff --git a/soc/arm64/rockchip/rk3568/mmu_regions.c b/soc/rockchip/rk3568/mmu_regions.c similarity index 100% rename from soc/arm64/rockchip/rk3568/mmu_regions.c rename to soc/rockchip/rk3568/mmu_regions.c diff --git a/soc/rockchip/soc.yml b/soc/rockchip/soc.yml new file mode 100644 index 00000000000000..5568a11aa49aea --- /dev/null +++ b/soc/rockchip/soc.yml @@ -0,0 +1,9 @@ +family: + - name: rockchip + series: + - name: rk3399 + socs: + - name: rk3399 + - name: rk3568 + socs: + - name: rk3568 diff --git a/soc/riscv/nordic_nrf/CMakeLists.txt b/soc/sifive/sifive_freedom/CMakeLists.txt similarity index 100% rename from soc/riscv/nordic_nrf/CMakeLists.txt rename to soc/sifive/sifive_freedom/CMakeLists.txt diff --git a/soc/sifive/sifive_freedom/Kconfig b/soc/sifive/sifive_freedom/Kconfig new file mode 100644 index 00000000000000..cee97a755b6350 --- /dev/null +++ b/soc/sifive/sifive_freedom/Kconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_SIFIVE_FREEDOM + +rsource "*/Kconfig" + +endif # SOC_FAMILY_SIFIVE_FREEDOM diff --git a/soc/sifive/sifive_freedom/Kconfig.defconfig b/soc/sifive/sifive_freedom/Kconfig.defconfig new file mode 100644 index 00000000000000..004ef668fcf331 --- /dev/null +++ b/soc/sifive/sifive_freedom/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_SIFIVE_FREEDOM + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_SIFIVE_FREEDOM diff --git a/soc/sifive/sifive_freedom/Kconfig.soc b/soc/sifive/sifive_freedom/Kconfig.soc new file mode 100644 index 00000000000000..e0bf27cb808cec --- /dev/null +++ b/soc/sifive/sifive_freedom/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SIFIVE_FREEDOM + bool + +config SOC_FAMILY + default "sifive_freedom" if SOC_FAMILY_SIFIVE_FREEDOM + +rsource "*/Kconfig.soc" diff --git a/soc/riscv/sifive_freedom/common/CMakeLists.txt b/soc/sifive/sifive_freedom/common/CMakeLists.txt similarity index 100% rename from soc/riscv/sifive_freedom/common/CMakeLists.txt rename to soc/sifive/sifive_freedom/common/CMakeLists.txt diff --git a/soc/riscv/sifive_freedom/common/pinctrl_soc.h b/soc/sifive/sifive_freedom/common/pinctrl_soc.h similarity index 100% rename from soc/riscv/sifive_freedom/common/pinctrl_soc.h rename to soc/sifive/sifive_freedom/common/pinctrl_soc.h diff --git a/soc/sifive/sifive_freedom/fe300/CMakeLists.txt b/soc/sifive/sifive_freedom/fe300/CMakeLists.txt new file mode 100644 index 00000000000000..4c3ee8c2ad8f93 --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(clock.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig b/soc/sifive/sifive_freedom/fe300/Kconfig new file mode 100644 index 00000000000000..e5796d7c9dcb58 --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FE300 + bool + + # RISC-V options + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + + select ATOMIC_OPERATIONS_C + select INCLUDE_RESET_VECTOR diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig b/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig new file mode 100644 index 00000000000000..c280c62ef4372e --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SIFIVE_FREEDOM_FE300 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_SIFIVE_FREEDOM_FE300 diff --git a/soc/sifive/sifive_freedom/fe300/Kconfig.soc b/soc/sifive/sifive_freedom/fe300/Kconfig.soc new file mode 100644 index 00000000000000..e5229d167100e7 --- /dev/null +++ b/soc/sifive/sifive_freedom/fe300/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FE300 + bool + select SOC_FAMILY_SIFIVE_FREEDOM + +config SOC_SERIES + default "fe300" if SOC_SERIES_SIFIVE_FREEDOM_FE300 + +config SOC_SIFIVE_FREEDOM_FE310 + bool + select SOC_SERIES_SIFIVE_FREEDOM_FE300 + +config SOC + default "fe310" if SOC_SIFIVE_FREEDOM_FE310 diff --git a/soc/riscv/sifive_freedom/e300/clock.c b/soc/sifive/sifive_freedom/fe300/clock.c similarity index 100% rename from soc/riscv/sifive_freedom/e300/clock.c rename to soc/sifive/sifive_freedom/fe300/clock.c diff --git a/soc/riscv/sifive_freedom/e300/prci.h b/soc/sifive/sifive_freedom/fe300/prci.h similarity index 100% rename from soc/riscv/sifive_freedom/e300/prci.h rename to soc/sifive/sifive_freedom/fe300/prci.h diff --git a/soc/riscv/sifive_freedom/e300/soc.h b/soc/sifive/sifive_freedom/fe300/soc.h similarity index 100% rename from soc/riscv/sifive_freedom/e300/soc.h rename to soc/sifive/sifive_freedom/fe300/soc.h diff --git a/soc/sifive/sifive_freedom/fu500/CMakeLists.txt b/soc/sifive/sifive_freedom/fu500/CMakeLists.txt new file mode 100644 index 00000000000000..4c3ee8c2ad8f93 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(clock.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig b/soc/sifive/sifive_freedom/fu500/Kconfig new file mode 100644 index 00000000000000..dbe9e074ddde38 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/Kconfig @@ -0,0 +1,20 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU500 + bool + + # RISC-V options + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + + select 64BIT + select INCLUDE_RESET_VECTOR diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig b/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig new file mode 100644 index 00000000000000..4db8701beb2d9d --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SIFIVE_FREEDOM_FU500 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_SIFIVE_FREEDOM_FU500 diff --git a/soc/sifive/sifive_freedom/fu500/Kconfig.soc b/soc/sifive/sifive_freedom/fu500/Kconfig.soc new file mode 100644 index 00000000000000..87a9e6d6edb770 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu500/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU500 + bool + select SOC_FAMILY_SIFIVE_FREEDOM + +config SOC_SERIES + default "fu500" if SOC_SERIES_SIFIVE_FREEDOM_FU500 + +config SOC_SIFIVE_FREEDOM_FU540 + bool + select SOC_SERIES_SIFIVE_FREEDOM_FU500 + +config SOC + default "fu540" if SOC_SIFIVE_FREEDOM_FU540 diff --git a/soc/riscv/sifive_freedom/u500/clock.c b/soc/sifive/sifive_freedom/fu500/clock.c similarity index 100% rename from soc/riscv/sifive_freedom/u500/clock.c rename to soc/sifive/sifive_freedom/fu500/clock.c diff --git a/soc/riscv/sifive_freedom/u500/prci.h b/soc/sifive/sifive_freedom/fu500/prci.h similarity index 100% rename from soc/riscv/sifive_freedom/u500/prci.h rename to soc/sifive/sifive_freedom/fu500/prci.h diff --git a/soc/riscv/sifive_freedom/u500/soc.h b/soc/sifive/sifive_freedom/fu500/soc.h similarity index 100% rename from soc/riscv/sifive_freedom/u500/soc.h rename to soc/sifive/sifive_freedom/fu500/soc.h diff --git a/soc/sifive/sifive_freedom/fu700/CMakeLists.txt b/soc/sifive/sifive_freedom/fu700/CMakeLists.txt new file mode 100644 index 00000000000000..4c3ee8c2ad8f93 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/CMakeLists.txt @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(clock.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "") diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig b/soc/sifive/sifive_freedom/fu700/Kconfig new file mode 100644 index 00000000000000..11804e56b92535 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/Kconfig @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU700 + bool + + # RISC-V options + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + + select INCLUDE_RESET_VECTOR + select 64BIT diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig b/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig new file mode 100644 index 00000000000000..56aab7e3df8792 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig @@ -0,0 +1,27 @@ +# Copyright (c) 2017 Jean-Paul Etienne +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_SIFIVE_FREEDOM_FU700 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config MAX_IRQ_PER_AGGREGATOR + default 52 + +config NUM_IRQS + default 64 + +endif # SOC_SERIES_SIFIVE_FREEDOM_FU700 diff --git a/soc/sifive/sifive_freedom/fu700/Kconfig.soc b/soc/sifive/sifive_freedom/fu700/Kconfig.soc new file mode 100644 index 00000000000000..db58d77a2c3645 --- /dev/null +++ b/soc/sifive/sifive_freedom/fu700/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2024 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_SIFIVE_FREEDOM_FU700 + bool + select SOC_FAMILY_SIFIVE_FREEDOM + +config SOC_SERIES + default "fu700" if SOC_SERIES_SIFIVE_FREEDOM_FU700 + +config SOC_SIFIVE_FREEDOM_FU740 + bool + select SOC_SERIES_SIFIVE_FREEDOM_FU700 + +config SOC + default "fu740" if SOC_SIFIVE_FREEDOM_FU740 diff --git a/soc/riscv/sifive_freedom/u700/clock.c b/soc/sifive/sifive_freedom/fu700/clock.c similarity index 100% rename from soc/riscv/sifive_freedom/u700/clock.c rename to soc/sifive/sifive_freedom/fu700/clock.c diff --git a/soc/riscv/sifive_freedom/u700/prci.h b/soc/sifive/sifive_freedom/fu700/prci.h similarity index 100% rename from soc/riscv/sifive_freedom/u700/prci.h rename to soc/sifive/sifive_freedom/fu700/prci.h diff --git a/soc/riscv/sifive_freedom/u700/soc.h b/soc/sifive/sifive_freedom/fu700/soc.h similarity index 100% rename from soc/riscv/sifive_freedom/u700/soc.h rename to soc/sifive/sifive_freedom/fu700/soc.h diff --git a/soc/sifive/sifive_freedom/soc.yml b/soc/sifive/sifive_freedom/soc.yml new file mode 100644 index 00000000000000..1590d495d15bc5 --- /dev/null +++ b/soc/sifive/sifive_freedom/soc.yml @@ -0,0 +1,12 @@ +family: + - name: sifive_freedom + series: + - name: fe300 + socs: + - name: fe310 + - name: fu500 + socs: + - name: fu540 + - name: fu700 + socs: + - name: fu740 diff --git a/soc/silabs/CMakeLists.txt b/soc/silabs/CMakeLists.txt new file mode 100644 index 00000000000000..17eca2d8d6b6ab --- /dev/null +++ b/soc/silabs/CMakeLists.txt @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Christian Taedcke + +add_subdirectory(common) +zephyr_include_directories(${SOC_FAMILY}/${SOC_SERIES}) diff --git a/soc/silabs/Kconfig b/soc/silabs/Kconfig new file mode 100644 index 00000000000000..4e86a6e2b74fc2 --- /dev/null +++ b/soc/silabs/Kconfig @@ -0,0 +1,325 @@ +# Copyright (c) 2017 Christian Taedcke +# Copyright (c) 2018 Gil Benkoe +# SPDX-License-Identifier: Apache-2.0 + +config SOC_VENDOR_SILABS + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select BUILD_OUTPUT_HEX + +if SOC_VENDOR_SILABS + +rsource "*/*/Kconfig" + +config SOC_GECKO_SDID + int + help + Gecko SDK sometime refere to the chipset using the internal ID. This + entry reflects this ID. + +config SOC_GECKO_BURTC + bool + help + Set if the Back-Up Real Time Counter (BURTC) HAL module is used. + +config SOC_GECKO_CORE + bool + default y + help + Set if the Core interrupt handling (CORE) HAL module is used. + +config SOC_GECKO_ADC + bool + help + Set if the Analog to Digital Converter (ADC) HAL module is used. + +config SOC_GECKO_IADC + bool + help + Set if the Incremental Analog to Digital Converter (IADC) HAL module is used. + +config SOC_GECKO_CRYOTIMER + bool + help + Set if the Ultra Low Energy Timer/Counter (CRYOTIMER) HAL module is used. + +config SOC_GECKO_EMU + bool + help + Set if the Energy Management Unit (EMU) HAL module is used. + +config SOC_GECKO_GPIO + bool + help + Set if the General Purpose Input/Output (GPIO) HAL module is used. + +config SOC_GECKO_I2C + bool + help + Set if the Inter-Integrated Circuit Interface (I2C) HAL module is used. + +config SOC_GECKO_LETIMER + bool + help + Set if the Low Energy Timer (LETIMER) HAL module is used. + +config SOC_GECKO_LEUART + bool + help + Set if the Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) + HAL module is used. + +config SOC_GECKO_MSC + bool + help + Set if the Memory System Controller (MSC) HAL module is used. + +config SOC_GECKO_PRS + bool + help + Set if the Peripheral Reflex System (PRS) HAL module is used. + +config SOC_GECKO_RMU + bool + help + Set if the Reset Management Unit (RMU) HAL module is used. + +config SOC_GECKO_RTC + bool + help + Set if the Real Time Counter (RTC) HAL module is used. + +config SOC_GECKO_RTCC + bool + help + Set if the Real Time Counter and Calendar (RTCC) HAL module is used. + +config SOC_GECKO_SE + bool + help + Set if the Secure Element (SE) HAL module is used. + +config SOC_GECKO_TIMER + bool + help + Set if the Timer/Counter (TIMER) HAL module is used. + +config SOC_GECKO_USART + bool + help + Set if the Universal Synchronous Asynchronous Receiver/Transmitter (USART) + HAL module is used. + +config SOC_GECKO_WDOG + bool + help + Set if the Watchdog Timer (WDOG) HAL module is used. + +config SOC_GECKO_TRNG + bool + help + Set if the SoC has a True Random Number Generator (TRNG) module. + +if PM + +config SOC_GECKO_PM_BACKEND_PMGR + bool + depends on SOC_GECKO_DEV_INIT + default y if SOC_FAMILY_SILABS_S2 + help + Implement PM using sl_power_manager service from Gecko SDK + +config SOC_GECKO_PM_BACKEND_EMU + bool + default y if !SOC_GECKO_PM_BACKEND_PMGR + help + Implement PM using direct calls to EMU driver in emlib + +endif + +config SOC_GECKO_EMU_DCDC + bool "SoC DC/DC regulator" + select SOC_GECKO_EMU + help + Enable the on chip DC/DC regulator + +choice SOC_GECKO_EMU_DCDC_MODE + prompt "DC/DC mode" + depends on SOC_GECKO_EMU_DCDC + help + Select power configuration mode of the on chip DC/DC converter. + + config SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED + bool "Initial / Unconfigured" + + config SOC_GECKO_EMU_DCDC_MODE_ON + bool "DC/DC On" + + config SOC_GECKO_EMU_DCDC_MODE_OFF + bool "DC/DC Off" + + config SOC_GECKO_EMU_DCDC_MODE_BYPASS + bool "Bypass" +endchoice + +config CRYPTO_ACC_GECKO_TRNG + bool + help + Enable Entropy driver based on the CRYPTO_ACC module for Silicon Labs + Gecko chips. + +config SOC_GECKO_DEV_INIT + bool + help + Use the device initialization routines from the device_init service + in Silicon Labs HAL. These routines initialize and tune HFXOs, + configures DPLLs and manages the Energy Management Unit. + + Disabling these services may negatively impact counter and timer + routines in Silabs SoCs. + +config COUNTER_GECKO_STIMER + bool + help + Enable counter driver based on the Sleep Timer driver for Silicon Labs + Gecko chips. + +config SOC_GECKO_CMU + bool + help + Set if the clock management unit (CMU) is present in the SoC. + +if SOC_GECKO_CMU + +config CMU_NEED_LFXO + bool + help + Set if LFXO oscillator should be configured and enabled, potentially + in on-demand mode, after SoC is initialized. + +choice + prompt "High Frequency Clock Selection" + default CMU_HFCLK_HFXO + +config CMU_HFCLK_HFXO + bool "External high frequency crystal oscillator" + help + Set this option to use the external high frequency crystal oscillator + as high frequency clock. + +config CMU_HFCLK_LFXO + bool "External low frequency crystal oscillator" + select CMU_NEED_LFXO + help + Set this option to use the external low frequency crystal oscillator + as high frequency clock. + +config CMU_HFCLK_HFRCO + bool "Internal high frequency RC oscillator" + help + Set this option to use the internal high frequency RC oscillator as high frequency clock. + +endchoice + + +choice + prompt "BURTC Clock Selection" + depends on SOC_GECKO_BURTC + default CMU_BURTCCLK_LFRCO + +config CMU_BURTCCLK_LFXO + bool "LFXO - external low frequency crystal oscillator" + select CMU_NEED_LFXO + help + Set this option to use LFXO - the external low freqency crystal oscillator + as BURTC clock. + Frequency is set by external crystal, typically 32.768 kHz. + +config CMU_BURTCCLK_LFRCO + bool "LFRCO - internal low frequency RC oscillator" + help + Set this option to use LFRCO - the internal low freqency RC oscillator + as BURTC clock. + Frequency is approximately 32.768 kHz. + +config CMU_BURTCCLK_ULFRCO + bool "ULFRCO - internal ultra low frequency RC oscillator" + help + Set this option to use ULFRCO - the external low freqency crystal oscillator + as BURTC clock. + Frequency is approximately 1 kHz. + +endchoice + + +config CMU_HFXO_FREQ + int "External high frequency oscillator frequency" + help + Set the external high frequency oscillator frequency in Hz. This should be set by the + board's defconfig. + +config CMU_LFXO_FREQ + int "External low frequency oscillator frequency" + help + Set the external low frequency oscillator frequency in Hz. This should be set by the + board's defconfig. + +config CMU_HFRCO_FREQ + int "Internal high frequency RC oscillator frequency" + default 0 + depends on SOC_GECKO_HAS_HFRCO_FREQRANGE + help + Set the internal high frequency RC oscillator frequency in Hz. This should be set by the + board's defconfig. Only supported values may be used here. Setting this to 0, skips the + configuration of the high frequency RC oscillator completely. This may be desired, if + the bootloader already configured it properly or the device's default clock source should + be used with it's default configuration. + +endif # SOC_GECKO_CMU + +config SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + bool + help + If enabled, indicates that SoC allows to configure individual pin + locations. This is supported by e.g. efr32fg1p, efr32mg12p series. + If disabled, indicates that pin locations are configured in groups. + This is supported by e.g. efm32hg, efm32wg series. + +config SOC_GECKO_HAS_ERRATA_RTCC_E201 + bool + help + Set if the SoC is affected by errata RTCC_E201: + "When the RTCC is configured with a prescaler, the CCV1 top value enable + feature enabled by setting CCV1TOP in RTCC_CTRL fails to wrap the counter + when RTCC_CNT is equal to RTCC_CC1_CCV, as intended." + +config SOC_GECKO_HAS_HFRCO_FREQRANGE + bool + help + If enabled, indicates that configuration of HFRCO frequency for this SOC is supported + via FREQRANGE field. This is supported for e.g. efr32fg1p, efr32mg12p series. + If disabled, indicates that configuration of HFRCO frequency for corresponding SOC + is not supported via this field. This is the case for e.g. efm32hg, efm32wg series. + +config SOC_GECKO_HAS_RADIO + bool + help + If enabled, indicates that the SoC has a Radio PHY. + +config SOC_GECKO_USE_RAIL + bool "Use RAIL (Radio Abstraction Interface Layer)" + depends on SOC_GECKO_HAS_RADIO + help + RAIL (Radio Abstraction Interface Layer) is a library needed to use the EFR radio + hardware. This option enable the proper set of features to allow to properly compile + with the RAIL blob. + +config SOC_GECKO_CUSTOM_RADIO_PHY + bool "Use RAIL for custom radio phy packet sending and receiving" + depends on SOC_GECKO_HAS_RADIO + select SOC_GECKO_USE_RAIL + help + If enabled, RAIL can be used for user generated custom radio phy + management, sending and receiving packets on radio phy. User has + to provide the radio_config.c and radio_config.h files for the phy. + +endif # SOC_VENDOR_SILABS diff --git a/soc/silabs/Kconfig.defconfig b/soc/silabs/Kconfig.defconfig new file mode 100644 index 00000000000000..530325a76a8c0f --- /dev/null +++ b/soc/silabs/Kconfig.defconfig @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Christian Taedcke + +if SOC_VENDOR_SILABS + +rsource "*/*/Kconfig.defconfig" + +config SOC_GECKO_EMU + default y + select SOC_GECKO_CORE + depends on PM + +config CORTEX_M_SYSTICK + default n if GECKO_BURTC_TIMER + +# With sl_power_manager, pm_state_set()'s stack footrpting is noticeably +# large, especially with logs enabled. Since it is called from IDLE task, +# its stack size has to be increased +config IDLE_STACK_SIZE + default 512 if SOC_GECKO_PM_BACKEND_PMGR + +endif diff --git a/soc/silabs/Kconfig.soc b/soc/silabs/Kconfig.soc new file mode 100644 index 00000000000000..bea030078b79f6 --- /dev/null +++ b/soc/silabs/Kconfig.soc @@ -0,0 +1,12 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_VENDOR_SILABS + bool + +config SOC_FAMILY + default "silabs_s0" if SOC_FAMILY_SILABS_S0 + default "silabs_s1" if SOC_FAMILY_SILABS_S1 + default "silabs_s2" if SOC_FAMILY_SILABS_S2 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/silabs_exx32/common/CMakeLists.txt b/soc/silabs/common/CMakeLists.txt similarity index 100% rename from soc/arm/silabs_exx32/common/CMakeLists.txt rename to soc/silabs/common/CMakeLists.txt diff --git a/soc/silabs/common/pinctrl_soc.h b/soc/silabs/common/pinctrl_soc.h new file mode 100644 index 00000000000000..967b7c0245556b --- /dev/null +++ b/soc/silabs/common/pinctrl_soc.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2022 Silicon Labs + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * Silabs SoC specific helpers for pinctrl driver + */ + +#ifndef ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ + +#include + +#include +#if CONFIG_SOC_FAMILY_SILABS_S1 +#include +#else +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +/** Type for gecko pin. */ +typedef uint32_t pinctrl_soc_pin_t; + +/** + * @brief Utility macro to initialize each pin. + * + * @param node_id Node identifier. + * @param prop Property name. + * @param idx Property entry index. + */ +#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) (DT_PROP_BY_IDX(node_id, prop, idx)), + +/** + * @brief Utility macro to initialize state pins contained in a given property. + * + * @param node_id Node identifier. + * @param prop Property name describing state pins. + */ +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + { \ + DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, psels, \ + Z_PINCTRL_STATE_PIN_INIT) \ + } + +/** + * @brief Utility macro to obtain pin function. + * + * @param pincfg Pin configuration bit field. + */ +#define GECKO_GET_FUN(pincfg) (((pincfg) >> GECKO_FUN_POS) & GECKO_FUN_MSK) + +/** + * @brief Utility macro to obtain port configuration. + * + * @param pincfg port configuration bit field. + */ +#define GECKO_GET_PORT(pincfg) (((pincfg) >> GECKO_PORT_POS) & GECKO_PORT_MSK) + +/** + * @brief Utility macro to obtain pin configuration. + * + * @param pincfg pin configuration bit field. + */ +#define GECKO_GET_PIN(pincfg) (((pincfg) >> GECKO_PIN_POS) & GECKO_PIN_MSK) + +/** + * @brief Utility macro to obtain location configuration. + * + * @param pincfg Loc configuration bit field. + */ +#define GECKO_GET_LOC(pincfg) (((pincfg) >> GECKO_LOC_POS) & GECKO_LOC_MSK) + +/** + * @brief Utility macro to obtain speed configuration. + * + * @param pincfg speed configuration bit field. + */ +#define GECKO_GET_SPEED(pincfg) (((pincfg) >> GECKO_SPEED_POS) & GECKO_SPEED_MSK) + +/** @endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_SILABS_GECKO_COMMON_PINCTRL_SOC_H_ */ diff --git a/soc/arm/silabs_exx32/common/sl_device_init_hfxo_config.h b/soc/silabs/common/sl_device_init_hfxo_config.h similarity index 100% rename from soc/arm/silabs_exx32/common/sl_device_init_hfxo_config.h rename to soc/silabs/common/sl_device_init_hfxo_config.h diff --git a/soc/silabs/common/soc.c b/soc/silabs/common/soc.c new file mode 100644 index 00000000000000..1136a1fedfd4ea --- /dev/null +++ b/soc/silabs/common/soc.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2018, Christian Taedcke + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Common SoC initialization for the Silabs products + */ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_SOC_GECKO_DEV_INIT +#include +#include +#include +#include +#include + +#ifdef CONFIG_PM +#include +#include +#endif + +#endif + +LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); + +#ifdef CONFIG_CMU_HFCLK_HFXO +/** + * @brief Initialization parameters for the external high frequency oscillator + */ +static CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_DEFAULT; +#endif + +#ifdef CONFIG_CMU_NEED_LFXO +/** + * @brief Initialization parameters for the external low frequency oscillator + */ +static CMU_LFXOInit_TypeDef lfxoInit = CMU_LFXOINIT_DEFAULT; + +static void init_lfxo(void) +{ + /* + * Configuring LFXO disables it, so we can do that only if it's not + * used as a SYSCLK/HFCLK source. + */ +#if defined(_SILICON_LABS_32B_SERIES_2) + if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_LFXO) { + /* + * Check if device has LFXO configuration info in DEVINFO + * See AN0016.2 + */ + if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_LFXOCALVAL) == + DEVINFO_MODULEINFO_LFXOCALVAL_VALID) { + lfxoInit.capTune = + (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_LFXOCAPTUNE_MASK) >> + _DEVINFO_MODXOCAL_LFXOCAPTUNE_SHIFT; + } + CMU_LFXOInit(&lfxoInit); + } +#else + if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_LFXO) { + CMU_LFXOInit(&lfxoInit); + CMU_OscillatorEnable(cmuOsc_LFXO, true, true); + } +#endif /* _SILICON_LABS_32B_SERIES_2 */ + SystemLFXOClockSet(CONFIG_CMU_LFXO_FREQ); +} + +#endif /* CONFIG_CMU_NEED_LFXO */ + +/** + * @brief Initialize the system clock + */ +static ALWAYS_INLINE void clock_init(void) +{ +#ifdef CONFIG_CMU_HFCLK_HFXO +#if defined(_SILICON_LABS_32B_SERIES_2) + if (CMU_ClockSelectGet(cmuClock_SYSCLK) != cmuSelect_HFXO) { + /* + * Check if device has HFXO configuration info in DEVINFO + * See AN0016.2 + */ + if ((DEVINFO->MODULEINFO & DEVINFO_MODULEINFO_HFXOCALVAL) == + DEVINFO_MODULEINFO_HFXOCALVAL_VALID) { + hfxoInit.ctuneXoAna = + (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_MASK) >> + _DEVINFO_MODXOCAL_HFXOCTUNEXOANA_SHIFT; + hfxoInit.ctuneXiAna = + (DEVINFO->MODXOCAL & _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_MASK) >> + _DEVINFO_MODXOCAL_HFXOCTUNEXIANA_SHIFT; + } + + CMU_HFXOInit(&hfxoInit); + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_HFXO); + } + + SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); +#else + if (CMU_ClockSelectGet(cmuClock_HF) != cmuSelect_HFXO) { + CMU_HFXOInit(&hfxoInit); + CMU_OscillatorEnable(cmuOsc_HFXO, true, true); + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); + } + SystemHFXOClockSet(CONFIG_CMU_HFXO_FREQ); + CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); +#endif /* _SILICON_LABS_32B_SERIES_2 */ +#elif (defined CONFIG_CMU_HFCLK_LFXO) + /* LFXO should've been already brought up by init_lfxo() */ +#if defined(_SILICON_LABS_32B_SERIES_2) + CMU_ClockSelectSet(cmuClock_SYSCLK, cmuSelect_LFXO); +#else + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_LFXO); + CMU_OscillatorEnable(cmuOsc_HFRCO, false, false); +#endif /* _SILICON_LABS_32B_SERIES_2 */ +#elif (defined CONFIG_CMU_HFCLK_HFRCO) + /* + * This is the default clock, the controller starts with + */ + +#ifdef CONFIG_SOC_GECKO_HAS_HFRCO_FREQRANGE + if (CONFIG_CMU_HFRCO_FREQ) { + /* Setting system HFRCO frequency */ + CMU_HFRCOBandSet(CONFIG_CMU_HFRCO_FREQ); + + /* Using HFRCO as high frequency clock, HFCLK */ + CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFRCO); + } +#endif +#else +#error "Unsupported clock source for HFCLK selected" +#endif + +#if defined(_SILICON_LABS_32B_SERIES_2) + /* Enable the High Frequency Peripheral Clock */ + CMU_ClockEnable(cmuClock_PCLK, true); +#else + /* Enable the High Frequency Peripheral Clock */ + CMU_ClockEnable(cmuClock_HFPER, true); +#endif /* _SILICON_LABS_32B_SERIES_2 */ + +#if defined(CONFIG_GPIO_GECKO) || defined(CONFIG_LOG_BACKEND_SWO) + CMU_ClockEnable(cmuClock_GPIO, true); +#endif +} + +#ifdef CONFIG_SOC_GECKO_EMU_DCDC +static ALWAYS_INLINE void dcdc_init(void) +{ +#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_UNCONFIGURED) + /* Nothing to do, leave DC/DC converter in unconfigured, safe state. */ +#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_ON) || defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) + EMU_DCDCInit_TypeDef init_cfg = EMU_DCDCINIT_DEFAULT; +#if defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_BYPASS) + init_cfg.dcdcMode = emuDcdcMode_Bypass; +#endif + EMU_DCDCInit(&init_cfg); +#elif defined(CONFIG_SOC_GECKO_EMU_DCDC_MODE_OFF) + EMU_DCDCPowerOff(); +#else +#error "Unsupported power configuration mode of the on chip DC/DC converter." +#endif +} +#endif + +#ifdef CONFIG_LOG_BACKEND_SWO +static void swo_init(void) +{ + struct soc_gpio_pin pin_swo = PIN_SWO; + +#if defined(_SILICON_LABS_32B_SERIES_2) + GPIO->TRACEROUTEPEN = GPIO_TRACEROUTEPEN_SWVPEN; +#else + /* Select HFCLK as the debug trace clock */ + CMU->DBGCLKSEL = CMU_DBGCLKSEL_DBG_HFCLK; + +#if defined(_GPIO_ROUTEPEN_MASK) + /* Enable Serial wire output pin */ + GPIO->ROUTEPEN |= GPIO_ROUTEPEN_SWVPEN; + /* Set SWO location */ + GPIO->ROUTELOC0 = SWO_LOCATION << _GPIO_ROUTELOC0_SWVLOC_SHIFT; +#else + GPIO->ROUTE = GPIO_ROUTE_SWOPEN | (SWO_LOCATION << 8); +#endif +#endif /* _SILICON_LABS_32B_SERIES_2 */ + + GPIO_PinModeSet(pin_swo.port, pin_swo.pin, pin_swo.mode, pin_swo.out); +} +#endif /* CONFIG_LOG_BACKEND_SWO */ + +/** + * @brief Perform basic hardware initialization + * + * Initialize the interrupt controller device drivers. + * Also initialize the timer device driver, if required. + * + * @return 0 + */ +static int silabs_init(void) +{ + /* handle chip errata */ + CHIP_Init(); + +#ifdef CONFIG_CMU_NEED_LFXO + init_lfxo(); +#endif + +#ifdef CONFIG_SOC_GECKO_DEV_INIT + sl_device_init_dcdc(); + sl_device_init_hfxo(); + sl_device_init_dpll(); + sl_device_init_emu(); + +#ifdef CONFIG_PM + sl_power_manager_init(); + sl_hfxo_manager_init(); +#endif + +#else /* !CONFIG_SOC_GECKO_DEV_INIT */ + +#ifdef CONFIG_SOC_GECKO_EMU_DCDC + dcdc_init(); +#endif + + /* Initialize system clock according to CONFIG_CMU settings */ + clock_init(); + +#ifdef CONFIG_LOG_BACKEND_SWO + /* Configure SWO debug output */ + swo_init(); +#endif +#endif /* !CONFIG_SOC_GECKO_DEV_INIT */ + + return 0; +} + +SYS_INIT(silabs_init, PRE_KERNEL_1, 0); diff --git a/soc/silabs/common/soc_gpio.h b/soc/silabs/common/soc_gpio.h new file mode 100644 index 00000000000000..3d3faeac8b76d4 --- /dev/null +++ b/soc/silabs/common/soc_gpio.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017 Christian Taedcke + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs MCU family General Purpose Input Output (GPIO) + * module HAL driver. + */ + +#ifndef _SILABS_COMMON_SOC_GPIO_H_ +#define _SILABS_COMMON_SOC_GPIO_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct soc_gpio_pin { + GPIO_Port_TypeDef port; /** GPIO port */ + unsigned int pin; /** GPIO pin on the port */ + GPIO_Mode_TypeDef mode; /** mode of the pin, e.g. gpioModeInput */ + unsigned int out; /** out register value */ +}; + +#ifdef __cplusplus +} +#endif + +#endif /* _SILABS_COMMON_SOC_GPIO_H_ */ diff --git a/soc/arm/silabs_exx32/common/soc_power.c b/soc/silabs/common/soc_power.c similarity index 100% rename from soc/arm/silabs_exx32/common/soc_power.c rename to soc/silabs/common/soc_power.c diff --git a/soc/arm/silabs_exx32/common/soc_power_pmgr.c b/soc/silabs/common/soc_power_pmgr.c similarity index 100% rename from soc/arm/silabs_exx32/common/soc_power_pmgr.c rename to soc/silabs/common/soc_power_pmgr.c diff --git a/soc/silabs/silabs_s0/Kconfig.soc b/soc/silabs/silabs_s0/Kconfig.soc new file mode 100644 index 00000000000000..870fecc2a4a495 --- /dev/null +++ b/soc/silabs/silabs_s0/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SILABS_S0 + bool + select SOC_VENDOR_SILABS + +rsource "*/Kconfig.soc" diff --git a/soc/silabs/silabs_s0/efm32hg/Kconfig b/soc/silabs/silabs_s0/efm32hg/Kconfig new file mode 100644 index 00000000000000..8470c48163497a --- /dev/null +++ b/soc/silabs/silabs_s0/efm32hg/Kconfig @@ -0,0 +1,17 @@ +# EFM32HG (Happy Gecko) MCU line + +# Copyright (c) 2018 Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32HG + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_SYSTICK + select CPU_CORTEX_M_HAS_VTOR + select HAS_SILABS_GECKO + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 77 if SOC_SERIES_EFM32HG diff --git a/soc/silabs/silabs_s0/efm32hg/Kconfig.defconfig b/soc/silabs/silabs_s0/efm32hg/Kconfig.defconfig new file mode 100644 index 00000000000000..eaedcb9a996573 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32hg/Kconfig.defconfig @@ -0,0 +1,13 @@ +# EFM32HG series configuration options + +# Copyright (c) 2018 Christian Taedcke +# Copyright (c) 2018 Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32HG + +config NUM_IRQS + # must be >= the highest interrupt number used + default 20 + +endif # SOC_SERIES_EFM32HG diff --git a/soc/silabs/silabs_s0/efm32hg/Kconfig.soc b/soc/silabs/silabs_s0/efm32hg/Kconfig.soc new file mode 100644 index 00000000000000..c5dbfa03cf5aa8 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32hg/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32HG (Happy Gecko) MCU line + +# Copyright (c) 2018 Marcio Montenegro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32HG + bool + select SOC_FAMILY_SILABS_S0 + help + EFM32HG Series MCU + +config SOC_PART_NUMBER_EFM32HG322F64 + bool + select SOC_SERIES_EFM32HG + +config SOC_SERIES + default "efm32hg" if SOC_SERIES_EFM32HG + +config SOC + default "efm32hg322f64" if SOC_PART_NUMBER_EFM32HG322F64 + +config SOC_PART_NUMBER + default "EFM32HG322F64" if SOC_PART_NUMBER_EFM32HG322F64 diff --git a/soc/arm/silabs_exx32/efm32hg/soc.h b/soc/silabs/silabs_s0/efm32hg/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32hg/soc.h rename to soc/silabs/silabs_s0/efm32hg/soc.h diff --git a/soc/arm/silabs_exx32/efm32hg/soc_pinmap.h b/soc/silabs/silabs_s0/efm32hg/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32hg/soc_pinmap.h rename to soc/silabs/silabs_s0/efm32hg/soc_pinmap.h diff --git a/soc/silabs/silabs_s0/efm32wg/Kconfig b/soc/silabs/silabs_s0/efm32wg/Kconfig new file mode 100644 index 00000000000000..9afdfa8846e80e --- /dev/null +++ b/soc/silabs/silabs_s0/efm32wg/Kconfig @@ -0,0 +1,18 @@ +# EFM32WG (Wonder Gecko) MCU line + +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32WG + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select HAS_SILABS_GECKO + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 74 if SOC_SERIES_EFM32WG diff --git a/soc/silabs/silabs_s0/efm32wg/Kconfig.defconfig b/soc/silabs/silabs_s0/efm32wg/Kconfig.defconfig new file mode 100644 index 00000000000000..93664abc5f43a9 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32wg/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32WG series configuration options + +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32WG + +config NUM_IRQS + # must be >= the highest interrupt number used + default 39 + +endif # SOC_SERIES_EFM32WG diff --git a/soc/silabs/silabs_s0/efm32wg/Kconfig.soc b/soc/silabs/silabs_s0/efm32wg/Kconfig.soc new file mode 100644 index 00000000000000..bdf6bac595a3e7 --- /dev/null +++ b/soc/silabs/silabs_s0/efm32wg/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32WG (Wonder Gecko) MCU line + +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32WG + bool + select SOC_FAMILY_SILABS_S0 + help + EFM32WG Series MCU + +config SOC_PART_NUMBER_EFM32WG990F256 + bool + select SOC_SERIES_EFM32WG + +config SOC_SERIES + default "efm32wg" if SOC_SERIES_EFM32WG + +config SOC + default "efm32wg990f256" if SOC_PART_NUMBER_EFM32WG990F256 + +config SOC_PART_NUMBER + default "EFM32WG990F256" if SOC_PART_NUMBER_EFM32WG990F256 diff --git a/soc/arm/silabs_exx32/efm32wg/soc.h b/soc/silabs/silabs_s0/efm32wg/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32wg/soc.h rename to soc/silabs/silabs_s0/efm32wg/soc.h diff --git a/soc/arm/silabs_exx32/efm32wg/soc_pinmap.h b/soc/silabs/silabs_s0/efm32wg/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32wg/soc_pinmap.h rename to soc/silabs/silabs_s0/efm32wg/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/Kconfig.soc b/soc/silabs/silabs_s1/Kconfig.soc new file mode 100644 index 00000000000000..d2771e803ec856 --- /dev/null +++ b/soc/silabs/silabs_s1/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SILABS_S1 + bool + select SOC_VENDOR_SILABS + +rsource "*/Kconfig.soc" diff --git a/soc/silabs/silabs_s1/efm32gg11b/Kconfig b/soc/silabs/silabs_s1/efm32gg11b/Kconfig new file mode 100644 index 00000000000000..8dcc746fb6ea15 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg11b/Kconfig @@ -0,0 +1,21 @@ +# EFM32GG11B (Giant Gecko) MCU line +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG11B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + +config SOC_GECKO_SDID + default 100 if SOC_SERIES_EFM32GG11B diff --git a/soc/silabs/silabs_s1/efm32gg11b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.defconfig new file mode 100644 index 00000000000000..07a92c66b8254f --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.defconfig @@ -0,0 +1,17 @@ +# EFM32GG11B series configuration options +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32GG11B + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 68 + +config GPIO_GECKO + default y + depends on GPIO || LOG_BACKEND_SWO + +endif # SOC_SERIES_EFM32GG11B diff --git a/soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc new file mode 100644 index 00000000000000..0d136b520c798f --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg11b/Kconfig.soc @@ -0,0 +1,29 @@ +# EFM32GG11B (Giant Gecko) MCU line +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG11B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32GG11B Series MCU + +config SOC_PART_NUMBER_EFM32GG11B820F2048GL192 + bool + select SOC_SERIES_EFM32GG11B + +config SOC_PART_NUMBER_EFM32GG11B820F2048GM64 + bool + select SOC_SERIES_EFM32GG11B + +config SOC_SERIES + default "efm32gg11b" if SOC_SERIES_EFM32GG11B + +config SOC + default "efm32gg11b820f2048gl192" if SOC_PART_NUMBER_EFM32GG11B820F2048GL192 + default "efm32gg11b820f2048gm64" if SOC_PART_NUMBER_EFM32GG11B820F2048GM64 + +config SOC_PART_NUMBER + default "EFM32GG11B820F2048GL192" if SOC_PART_NUMBER_EFM32GG11B820F2048GL192 + default "EFM32GG11B820F2048GM64" if SOC_PART_NUMBER_EFM32GG11B820F2048GM64 diff --git a/soc/arm/silabs_exx32/efm32gg11b/soc.h b/soc/silabs/silabs_s1/efm32gg11b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg11b/soc.h rename to soc/silabs/silabs_s1/efm32gg11b/soc.h diff --git a/soc/arm/silabs_exx32/efm32gg11b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32gg11b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg11b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32gg11b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32gg12b/Kconfig b/soc/silabs/silabs_s1/efm32gg12b/Kconfig new file mode 100644 index 00000000000000..f8be8f8b9939c6 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg12b/Kconfig @@ -0,0 +1,20 @@ +# EFM32GG12B (Giant Gecko) MCU line +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG12B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + +config SOC_GECKO_SDID + default 106 if SOC_SERIES_EFM32GG12B diff --git a/soc/silabs/silabs_s1/efm32gg12b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.defconfig new file mode 100644 index 00000000000000..7bcb50e8ef728e --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.defconfig @@ -0,0 +1,16 @@ +# EFM32GG12B series configuration options +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32GG12B + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 68 + +config GPIO_GECKO + default y + depends on GPIO || LOG_BACKEND_SWO + +endif # SOC_SERIES_EFM32GG12B diff --git a/soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc new file mode 100644 index 00000000000000..8367ffcd908620 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32gg12b/Kconfig.soc @@ -0,0 +1,22 @@ +# EFM32GG12B (Giant Gecko) MCU line +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32GG12B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32GG12B Series MCU + +config SOC_PART_NUMBER_EFM32GG12B810F1024GM64 + bool + select SOC_SERIES_EFM32GG12B + +config SOC_SERIES + default "efm32gg12b" if SOC_SERIES_EFM32GG12B + +config SOC + default "efm32gg12b810f1024gm64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64 + +config SOC_PART_NUMBER + default "EFM32GG12B810F1024GM64" if SOC_PART_NUMBER_EFM32GG12B810F1024GM64 diff --git a/soc/arm/silabs_exx32/efm32gg12b/soc.h b/soc/silabs/silabs_s1/efm32gg12b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg12b/soc.h rename to soc/silabs/silabs_s1/efm32gg12b/soc.h diff --git a/soc/arm/silabs_exx32/efm32gg12b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32gg12b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32gg12b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32gg12b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32jg12b/Kconfig b/soc/silabs/silabs_s1/efm32jg12b/Kconfig new file mode 100644 index 00000000000000..adb3d67c04c22e --- /dev/null +++ b/soc/silabs/silabs_s1/efm32jg12b/Kconfig @@ -0,0 +1,21 @@ +# EFM32JG12B (Jade Gecko) MCU line + +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32JG12B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M3 + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + select HAS_PM + +config SOC_GECKO_SDID + default 84 if SOC_SERIES_EFM32JG12B diff --git a/soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig new file mode 100644 index 00000000000000..d0d04a59ba3a4c --- /dev/null +++ b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32JG12B series configuration options + +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32JG12B + +config NUM_IRQS + # must be >= the highest interrupt number used + default 50 + +endif # SOC_SERIES_EFM32JG12B diff --git a/soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc new file mode 100644 index 00000000000000..1142c09a25a907 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32jg12b/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32JG12B (Jade Gecko) MCU line + +# Copyright (c) 2019 Lemonbeat GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32JG12B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32JG12B Series MCU + +config SOC_PART_NUMBER_EFM32JG12B500F1024GL125 + bool + select SOC_SERIES_EFM32JG12B + +config SOC_SERIES + default "efm32jg12b" if SOC_SERIES_EFM32JG12B + +config SOC + default "efm32jg12b500f1024gl125" if SOC_PART_NUMBER_EFM32JG12B500F1024GL125 + +config SOC_PART_NUMBER + default "EFM32JG12B500F1024GL125" if SOC_PART_NUMBER_EFM32JG12B500F1024GL125 diff --git a/soc/arm/silabs_exx32/efm32jg12b/soc.h b/soc/silabs/silabs_s1/efm32jg12b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32jg12b/soc.h rename to soc/silabs/silabs_s1/efm32jg12b/soc.h diff --git a/soc/arm/silabs_exx32/efm32jg12b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32jg12b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32jg12b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32jg12b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32pg12b/Kconfig b/soc/silabs/silabs_s1/efm32pg12b/Kconfig new file mode 100644 index 00000000000000..6919ee1e71b775 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg12b/Kconfig @@ -0,0 +1,24 @@ +# EFM32PG12B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG12B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + select SOC_GECKO_ADC + select HAS_PM + +config SOC_GECKO_SDID + default 84 if SOC_SERIES_EFM32PG12B diff --git a/soc/silabs/silabs_s1/efm32pg12b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.defconfig new file mode 100644 index 00000000000000..2fce94f7c2b031 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32PG12B series configuration options + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32PG12B + +config NUM_IRQS + # must be >= the highest interrupt number used + default 50 + +endif # SOC_SERIES_EFM32PG12B diff --git a/soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc new file mode 100644 index 00000000000000..1a8a70060451c2 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg12b/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32PG12B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG12B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32PG12B Series MCU + +config SOC_PART_NUMBER_EFM32PG12B500F1024GL125 + bool + select SOC_SERIES_EFM32PG12B + +config SOC_SERIES + default "efm32pg12b" if SOC_SERIES_EFM32PG12B + +config SOC + default "efm32pg12b500f1024gl125" if SOC_PART_NUMBER_EFM32PG12B500F1024GL125 + +config SOC_PART_NUMBER + default "EFM32PG12B500F1024GL125" if SOC_PART_NUMBER_EFM32PG12B500F1024GL125 diff --git a/soc/arm/silabs_exx32/efm32pg12b/soc.h b/soc/silabs/silabs_s1/efm32pg12b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg12b/soc.h rename to soc/silabs/silabs_s1/efm32pg12b/soc.h diff --git a/soc/arm/silabs_exx32/efm32pg12b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32pg12b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg12b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32pg12b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efm32pg1b/Kconfig b/soc/silabs/silabs_s1/efm32pg1b/Kconfig new file mode 100644 index 00000000000000..44596bb5d3c31a --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg1b/Kconfig @@ -0,0 +1,22 @@ +# EFM32PG1B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG1B + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 80 if SOC_SERIES_EFM32PG1B diff --git a/soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig new file mode 100644 index 00000000000000..7a0549d800e840 --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32PG1B series configuration options + +# Copyright (c) 2020 Rafael Dias Menezes +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFM32PG1B + +config NUM_IRQS + # must be >= the highest interrupt number used + default 34 + +endif # SOC_SERIES_EFM32PG1B diff --git a/soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc new file mode 100644 index 00000000000000..428c49847bdd6f --- /dev/null +++ b/soc/silabs/silabs_s1/efm32pg1b/Kconfig.soc @@ -0,0 +1,23 @@ +# EFM32PG1B (Pearl Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFM32PG1B + bool + select SOC_FAMILY_SILABS_S1 + help + EFM32PG1B Series MCU + +config SOC_PART_NUMBER_EFM32PG1B200F256GM48 + bool + select SOC_SERIES_EFM32PG1B + +config SOC_SERIES + default "efm32pg1b" if SOC_SERIES_EFM32PG1B + +config SOC + default "efm32pg1b200f256gm48" if SOC_PART_NUMBER_EFM32PG1B200F256GM48 + +config SOC_PART_NUMBER + default "EFM32PG1B200F256GM48" if SOC_PART_NUMBER_EFM32PG1B200F256GM48 diff --git a/soc/arm/silabs_exx32/efm32pg1b/soc.h b/soc/silabs/silabs_s1/efm32pg1b/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg1b/soc.h rename to soc/silabs/silabs_s1/efm32pg1b/soc.h diff --git a/soc/arm/silabs_exx32/efm32pg1b/soc_pinmap.h b/soc/silabs/silabs_s1/efm32pg1b/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efm32pg1b/soc_pinmap.h rename to soc/silabs/silabs_s1/efm32pg1b/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32bg13p/Kconfig b/soc/silabs/silabs_s1/efr32bg13p/Kconfig new file mode 100644 index 00000000000000..041615668780f1 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32bg13p/Kconfig @@ -0,0 +1,22 @@ +# Silicon Labs EFR32BG13P (Blue Gecko) MCU series + +# Copyright (c) 2020 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG13P + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select HAS_PM + +config SOC_GECKO_SDID + default 89 if SOC_SERIES_EFR32BG13P diff --git a/soc/silabs/silabs_s1/efr32bg13p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.defconfig new file mode 100644 index 00000000000000..ec5e8cd1f6629c --- /dev/null +++ b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# Silicon Labs EFR32BG13P (Blue Gecko) MCU configuration options + +# Copyright (c) 2020 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32BG13P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 47 + +endif # SOC_SERIES_EFR32BG13P diff --git a/soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc new file mode 100644 index 00000000000000..971e7932b95e3d --- /dev/null +++ b/soc/silabs/silabs_s1/efr32bg13p/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32BG13P (Blue Gecko) MCU series + +# Copyright (c) 2020 Piotr Mienkowski +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG13P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32BG13P Series MCU + +config SOC_PART_NUMBER_EFR32BG13P632F512GM48 + bool + select SOC_SERIES_EFR32BG13P + +config SOC_SERIES + default "efr32bg13p" if SOC_SERIES_EFR32BG13P + +config SOC + default "efr32bg13p632f512gm48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48 + +config SOC_PART_NUMBER + default "EFR32BG13P632F512GM48" if SOC_PART_NUMBER_EFR32BG13P632F512GM48 diff --git a/soc/arm/silabs_exx32/efr32bg13p/soc.h b/soc/silabs/silabs_s1/efr32bg13p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg13p/soc.h rename to soc/silabs/silabs_s1/efr32bg13p/soc.h diff --git a/soc/arm/silabs_exx32/efr32bg13p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32bg13p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg13p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32bg13p/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32fg13p/Kconfig b/soc/silabs/silabs_s1/efr32fg13p/Kconfig new file mode 100644 index 00000000000000..9b68eb580660cf --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg13p/Kconfig @@ -0,0 +1,23 @@ +# EFR32FG13P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG13P + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select SOC_GECKO_HAS_ERRATA_RTCC_E201 + select HAS_PM + +config SOC_GECKO_SDID + default 89 if SOC_SERIES_EFR32FG13P diff --git a/soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig new file mode 100644 index 00000000000000..5d3bdc086184d8 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFR32FG13P series configuration options + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32FG13P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 45 + +endif # SOC_SERIES_EFR32FG13P diff --git a/soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc new file mode 100644 index 00000000000000..e65132a49e69d4 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg13p/Kconfig.soc @@ -0,0 +1,23 @@ +# EFR32FG13P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG13P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32FG13P Series MCU + +config SOC_PART_NUMBER_EFR32FG13P233F512GM48 + bool + select SOC_SERIES_EFR32FG13P + +config SOC_SERIES + default "efr32fg13p" if SOC_SERIES_EFR32FG13P + +config SOC + default "efr32fg13p233f512gm48" if SOC_PART_NUMBER_EFR32FG13P233F512GM48 + +config SOC_PART_NUMBER + default "EFR32FG13P233F512GM48" if SOC_PART_NUMBER_EFR32FG13P233F512GM48 diff --git a/soc/arm/silabs_exx32/efr32fg13p/soc.h b/soc/silabs/silabs_s1/efr32fg13p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg13p/soc.h rename to soc/silabs/silabs_s1/efr32fg13p/soc.h diff --git a/soc/arm/silabs_exx32/efr32fg13p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32fg13p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg13p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32fg13p/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32fg1p/Kconfig b/soc/silabs/silabs_s1/efr32fg1p/Kconfig new file mode 100644 index 00000000000000..19c8ef7af9878c --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg1p/Kconfig @@ -0,0 +1,23 @@ +# EFR32FG1P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG1P + select ARM + select HAS_SILABS_GECKO + select HAS_SWO + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_GPIO + select SOC_GECKO_HAS_ERRATA_RTCC_E201 + select HAS_PM + +config SOC_GECKO_SDID + default 80 if SOC_SERIES_EFR32FG1P diff --git a/soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig new file mode 100644 index 00000000000000..8e6645f22e1e85 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFR32FG1P series configuration options + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32FG1P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 33 + +endif # SOC_SERIES_EFR32FG1P diff --git a/soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc new file mode 100644 index 00000000000000..ed0f05860f79c0 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32fg1p/Kconfig.soc @@ -0,0 +1,23 @@ +# EFR32FG1P (Flex Gecko) MCU line + +# Copyright (c) 2018 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32FG1P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32FG1P Series MCU + +config SOC_PART_NUMBER_EFR32FG1P133F256GM48 + bool + select SOC_SERIES_EFR32FG1P + +config SOC_SERIES + default "efr32fg1p" if SOC_SERIES_EFR32FG1P + +config SOC + default "efr32fg1p133f256gm48" if SOC_PART_NUMBER_EFR32FG1P133F256GM48 + +config SOC_PART_NUMBER + default "EFR32FG1P133F256GM48" if SOC_PART_NUMBER_EFR32FG1P133F256GM48 diff --git a/soc/arm/silabs_exx32/efr32fg1p/soc.h b/soc/silabs/silabs_s1/efr32fg1p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg1p/soc.h rename to soc/silabs/silabs_s1/efr32fg1p/soc.h diff --git a/soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32fg1p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32fg1p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32fg1p/soc_pinmap.h diff --git a/soc/silabs/silabs_s1/efr32mg12p/Kconfig b/soc/silabs/silabs_s1/efr32mg12p/Kconfig new file mode 100644 index 00000000000000..cba1530dbf8a24 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32mg12p/Kconfig @@ -0,0 +1,24 @@ +# EFR32MG12P (Mighty Gecko) MCU line + +# Copyright (c) 2018 Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG12P + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION + select SOC_GECKO_HAS_HFRCO_FREQRANGE + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_TRNG + select HAS_PM + +config SOC_GECKO_SDID + default 84 if SOC_SERIES_EFR32MG12P diff --git a/soc/silabs/silabs_s1/efr32mg12p/Kconfig.defconfig b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.defconfig new file mode 100644 index 00000000000000..bb2b6c314b9c56 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.defconfig @@ -0,0 +1,12 @@ +# EFM32WG series configuration options + +# Copyright (c) 2018 Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32MG12P + +config NUM_IRQS + # must be >= the highest interrupt number used + default 49 + +endif # SOC_SERIES_EFR32MG12P diff --git a/soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc new file mode 100644 index 00000000000000..61890df2ccf3e1 --- /dev/null +++ b/soc/silabs/silabs_s1/efr32mg12p/Kconfig.soc @@ -0,0 +1,35 @@ +# EFR32MG12P (Mighty Gecko) MCU line + +# Copyright (c) 2018 Diego Sueiro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG12P + bool + select SOC_FAMILY_SILABS_S1 + help + EFR32MG12P Series MCU + +config SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + bool + select SOC_SERIES_EFR32MG12P + +config SOC_PART_NUMBER_EFR32MG12P433F1024GM68 + bool + select SOC_SERIES_EFR32MG12P + +config SOC_PART_NUMBER_EFR32MG12P432F1024GL125 + bool + select SOC_SERIES_EFR32MG12P + +config SOC_SERIES + default "efr32mg12p" if SOC_SERIES_EFR32MG12P + +config SOC + default "efr32mg12p332f1024gl125" if SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + default "efr32mg12p432f1024gl125" if SOC_PART_NUMBER_EFR32MG12P432F1024GL125 + default "efr32mg12p433f1024gm68" if SOC_PART_NUMBER_EFR32MG12P433F1024GM68 + +config SOC_PART_NUMBER + default "EFR32MG12P332F1024GL125" if SOC_PART_NUMBER_EFR32MG12P332F1024GL125 + default "EFR32MG12P432F1024GL125" if SOC_PART_NUMBER_EFR32MG12P432F1024GL125 + default "EFR32MG12P433F1024GM68" if SOC_PART_NUMBER_EFR32MG12P433F1024GM68 diff --git a/soc/arm/silabs_exx32/efr32mg12p/soc.h b/soc/silabs/silabs_s1/efr32mg12p/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32mg12p/soc.h rename to soc/silabs/silabs_s1/efr32mg12p/soc.h diff --git a/soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h b/soc/silabs/silabs_s1/efr32mg12p/soc_pinmap.h similarity index 100% rename from soc/arm/silabs_exx32/efr32mg12p/soc_pinmap.h rename to soc/silabs/silabs_s1/efr32mg12p/soc_pinmap.h diff --git a/soc/silabs/silabs_s2/Kconfig.soc b/soc/silabs/silabs_s2/Kconfig.soc new file mode 100644 index 00000000000000..c8926b83e6ee3a --- /dev/null +++ b/soc/silabs/silabs_s2/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2017 Christian Taedcke +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_SILABS_S2 + bool + select SOC_VENDOR_SILABS + +rsource "*/Kconfig.soc" diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig b/soc/silabs/silabs_s2/efr32bg22/Kconfig new file mode 100644 index 00000000000000..75747fd76aa2e8 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg22/Kconfig @@ -0,0 +1,25 @@ +# Silicon Labs EFR32BG22 (Blue Gecko) MCU series + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG22 + select ARM + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_GPIO + select SOC_GECKO_CMU + select SOC_GECKO_CORE + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 205 if SOC_SERIES_EFR32BG22 diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig new file mode 100644 index 00000000000000..d0cdff43ea656c --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg22/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Silicon Labs EFR32BG22 (Blue Gecko) MCU configuration options + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32BG22 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 60 + +config PM + select COUNTER + select UART_INTERRUPT_DRIVEN + +config GPIO_GECKO + default y + +endif # SOC_SERIES_EFR32BG22 diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc b/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc new file mode 100644 index 00000000000000..5625510eccbc58 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg22/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32BG22 (Blue Gecko) MCU series + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG22 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32BG22P Series MCU + +config SOC_PART_NUMBER_EFR32BG22C224F512IM40 + bool + select SOC_SERIES_EFR32BG22 + +config SOC_SERIES + default "efr32bg22" if SOC_SERIES_EFR32BG22 + +config SOC + default "efr32bg22c224f512im40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 + +config SOC_PART_NUMBER + default "EFR32BG22C224F512IM40" if SOC_PART_NUMBER_EFR32BG22C224F512IM40 diff --git a/soc/arm/silabs_exx32/efr32bg22/soc.h b/soc/silabs/silabs_s2/efr32bg22/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg22/soc.h rename to soc/silabs/silabs_s2/efr32bg22/soc.h diff --git a/soc/silabs/silabs_s2/efr32bg27/Kconfig b/soc/silabs/silabs_s2/efr32bg27/Kconfig new file mode 100644 index 00000000000000..69825f9b5392dc --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg27/Kconfig @@ -0,0 +1,24 @@ +# Silicon Labs EFR32BG27 (Blue Gecko) MCU series + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG27 + select ARM + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M33 + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_HAS_FPU + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_HAS_RADIO + select SOC_GECKO_CMU + select SOC_GECKO_CORE + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 230 if SOC_SERIES_EFR32BG27 diff --git a/soc/silabs/silabs_s2/efr32bg27/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32bg27/Kconfig.defconfig new file mode 100644 index 00000000000000..a997408c74e5e7 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg27/Kconfig.defconfig @@ -0,0 +1,18 @@ +# Silicon Labs EFR32BG27 (Blue Gecko) MCU configuration options + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32BG27 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 66 + +config PM + select COUNTER + +config GPIO_GECKO + default y + +endif # SOC_SERIES_EFR32BG27 diff --git a/soc/silabs/silabs_s2/efr32bg27/Kconfig.soc b/soc/silabs/silabs_s2/efr32bg27/Kconfig.soc new file mode 100644 index 00000000000000..33998241d5ae8a --- /dev/null +++ b/soc/silabs/silabs_s2/efr32bg27/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32BG27 (Blue Gecko) MCU series + +# Copyright (c) 2023 Antmicro +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32BG27 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32BG27 Series MCU + +config SOC_PART_NUMBER_EFR32BG27C140F768IM40 + bool + select SOC_SERIES_EFR32BG27 + +config SOC_SERIES + default "efr32bg27" if SOC_SERIES_EFR32BG27 + +config SOC + default "efr32bg27c140f768im40" if SOC_PART_NUMBER_EFR32BG27C140F768IM40 + +config SOC_PART_NUMBER + default "EFR32BG27C140F768IM40" if SOC_PART_NUMBER_EFR32BG27C140F768IM40 diff --git a/soc/arm/silabs_exx32/efr32bg27/soc.h b/soc/silabs/silabs_s2/efr32bg27/soc.h similarity index 100% rename from soc/arm/silabs_exx32/efr32bg27/soc.h rename to soc/silabs/silabs_s2/efr32bg27/soc.h diff --git a/soc/silabs/silabs_s2/efr32mg21/Kconfig b/soc/silabs/silabs_s2/efr32mg21/Kconfig new file mode 100644 index 00000000000000..e63182b6efa1fb --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/Kconfig @@ -0,0 +1,24 @@ +# Silicon Labs EFR32MG21 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG21 + select ARM + select CPU_CORTEX_M33 + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 200 if SOC_SERIES_EFR32MG21 diff --git a/soc/silabs/silabs_s2/efr32mg21/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32mg21/Kconfig.defconfig new file mode 100644 index 00000000000000..76555bbaa1c9af --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/Kconfig.defconfig @@ -0,0 +1,17 @@ +# Silicon Labs EFR32MG21 (Might Gecko) series configuration options + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32MG21 + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 61 + +config GPIO_GECKO + default y + depends on GPIO || LOG_BACKEND_SWO + +endif # SOC_SERIES_EFR32MG21 diff --git a/soc/silabs/silabs_s2/efr32mg21/Kconfig.soc b/soc/silabs/silabs_s2/efr32mg21/Kconfig.soc new file mode 100644 index 00000000000000..abdfaf79625970 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/Kconfig.soc @@ -0,0 +1,23 @@ +# Silicon Labs EFR32MG21 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG21 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32MG21 Series MCU + +config SOC_PART_NUMBER_EFR32MG21A020F1024IM32 + bool + select SOC_SERIES_EFR32MG21 + +config SOC_SERIES + default "efr32mg21" if SOC_SERIES_EFR32MG21 + +config SOC + default "efr32mg21a020f1024im32" if SOC_PART_NUMBER_EFR32MG21A020F1024IM32 + +config SOC_PART_NUMBER + default "EFR32MG21A020F1024IM32" if SOC_PART_NUMBER_EFR32MG21A020F1024IM32 diff --git a/soc/silabs/silabs_s2/efr32mg21/soc.h b/soc/silabs/silabs_s2/efr32mg21/soc.h new file mode 100644 index 00000000000000..90b93a0acd14d9 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/soc.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the EFR32MG21 SoC + * + */ + +#ifndef _SILABS_EFR32MG21_SOC_H +#define _SILABS_EFR32MG21_SOC_H + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include "soc_pinmap.h" +#include "../common/soc_gpio.h" + + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SILABS_EFR32MG21_SOC_H */ diff --git a/soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h b/soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h new file mode 100644 index 00000000000000..1f38208d0d347b --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg21/soc_pinmap.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs EFR32MG21 MCU pin definitions. + * + * This file contains pin configuration data required by different MCU + * modules to correctly configure GPIO controller. + */ + +#ifndef _SILABS_EFR32MG21_SOC_PINMAP_H_ +#define _SILABS_EFR32MG21_SOC_PINMAP_H_ + +#include + +#ifdef CONFIG_LOG_BACKEND_SWO +#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } +#endif /* CONFIG_LOG_BACKEND_SWO */ + +#endif /* _SILABS_EFR32MG21_SOC_PINMAP_H_ */ diff --git a/soc/silabs/silabs_s2/efr32mg24/Kconfig b/soc/silabs/silabs_s2/efr32mg24/Kconfig new file mode 100644 index 00000000000000..eb8c1ea667363b --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/Kconfig @@ -0,0 +1,26 @@ +# Silicon Labs EFR32MG24 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG24 + select ARM + select CPU_CORTEX_M33 + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + select CPU_HAS_ARM_SAU + select CPU_CORTEX_M_HAS_DWT + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select SOC_GECKO_HAS_RADIO + select HAS_SILABS_GECKO + select HAS_SWO + select SOC_GECKO_CMU + select SOC_GECKO_EMU + select SOC_GECKO_GPIO + select SOC_GECKO_DEV_INIT + select SOC_GECKO_SE + select HAS_PM + +config SOC_GECKO_SDID + default 215 if SOC_SERIES_EFR32MG24 diff --git a/soc/silabs/silabs_s2/efr32mg24/Kconfig.defconfig b/soc/silabs/silabs_s2/efr32mg24/Kconfig.defconfig new file mode 100644 index 00000000000000..34428b46915aa5 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/Kconfig.defconfig @@ -0,0 +1,22 @@ +# Silicon Labs EFR32MG24 (Mighty Gecko) MCU configuration options + +# Copyright (c) 2021 Sateesh Kotapati +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_EFR32MG24 + +config NUM_IRQS + # must be >= the highest interrupt number used + default 75 + +config PM + default n + select COUNTER + select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT + +choice PM_POLICY + default PM_POLICY_DEFAULT + depends on PM +endchoice + +endif # SOC_SERIES_EFR32MG24 diff --git a/soc/silabs/silabs_s2/efr32mg24/Kconfig.soc b/soc/silabs/silabs_s2/efr32mg24/Kconfig.soc new file mode 100644 index 00000000000000..ae2cd2f26fbf96 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/Kconfig.soc @@ -0,0 +1,29 @@ +# Silicon Labs EFR32MG24 (Mighty Gecko) MCU line + +# Copyright (c) 2020 TriaGnoSys GmbH +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_EFR32MG24 + bool + select SOC_FAMILY_SILABS_S2 + help + EFR32MG24 Series MCU + +config SOC_PART_NUMBER_EFR32MG24B220F1536IM48 + bool + select SOC_SERIES_EFR32MG24 + +config SOC_PART_NUMBER_EFR32MG24B310F1536IM48 + bool + select SOC_SERIES_EFR32MG24 + +config SOC_SERIES + default "efr32mg24" if SOC_SERIES_EFR32MG24 + +config SOC + default "efr32mg24b220f1536im48" if SOC_PART_NUMBER_EFR32MG24B220F1536IM48 + default "efr32mg24b310f1536im48" if SOC_PART_NUMBER_EFR32MG24B310F1536IM48 + +config SOC_PART_NUMBER + default "EFR32MG24B220F1536IM48" if SOC_PART_NUMBER_EFR32MG24B220F1536IM48 + default "EFR32MG24B310F1536IM48" if SOC_PART_NUMBER_EFR32MG24B310F1536IM48 diff --git a/soc/silabs/silabs_s2/efr32mg24/soc.h b/soc/silabs/silabs_s2/efr32mg24/soc.h new file mode 100644 index 00000000000000..210526c11099b8 --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/soc.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the EFR32MG24 SoC + * + */ + +#ifndef _SILABS_EFR32MG24_SOC_H +#define _SILABS_EFR32MG24_SOC_H + +#include + +#ifndef _ASMLANGUAGE + +#include + +#include "soc_pinmap.h" +#include "../common/soc_gpio.h" + +/* Add include for DTS generated information */ +#include + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SILABS_EFR32MG24_SOC_H */ diff --git a/soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h b/soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h new file mode 100644 index 00000000000000..37c1924599fabf --- /dev/null +++ b/soc/silabs/silabs_s2/efr32mg24/soc_pinmap.h @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2020 TriaGnoSys GmbH + * SPDX-License-Identifier: Apache-2.0 + */ + +/** @file + * @brief Silabs EFR32MG24 MCU pin definitions. + * + * This file contains pin configuration data required by different MCU + * modules to correctly configure GPIO controller. + */ + +#ifndef _SILABS_EFR32MG24_SOC_PINMAP_H_ +#define _SILABS_EFR32MG24_SOC_PINMAP_H_ + +#include + +#ifdef CONFIG_LOG_BACKEND_SWO +#define PIN_SWO { gpioPortA, 3, gpioModePushPull, 1 } +#endif /* CONFIG_LOG_BACKEND_SWO */ + +#endif /* _SILABS_EFR32MG24_SOC_PINMAP_H_ */ diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml new file mode 100644 index 00000000000000..d6b2cc7866ae99 --- /dev/null +++ b/soc/silabs/soc.yml @@ -0,0 +1,56 @@ +family: + - name: silabs_s0 + series: + - name: efm32wg + socs: + - name: efm32wg990f256 + - name: efm32hg + socs: + - name: efm32hg322f64 + - name: silabs_s1 + series: + - name: efm32pg1b + socs: + - name: efm32pg1b200f256gm48 + - name: efr32fg1p + socs: + - name: efr32fg1p133f256gm48 + - name: efm32pg12b + socs: + - name: efm32pg12b500f1024gl125 + - name: efr32bg13p + socs: + - name: efr32bg13p632f512gm48 + - name: efr32fg13p + socs: + - name: efr32fg13p233f512gm48 + - name: efm32jg12b + socs: + - name: efm32jg12b500f1024gl125 + - name: efr32mg12p + socs: + - name: efr32mg12p332f1024gl125 + - name: efr32mg12p432f1024gl125 + - name: efr32mg12p433f1024gm68 + - name: efm32gg11b + socs: + - name: efm32gg11b820f2048gl192 + - name: efm32gg11b820f2048gm64 + - name: efm32gg12b + socs: + - name: efm32gg12b810f1024gm64 + - name: silabs_s2 + series: + - name: efr32mg21 + socs: + - name: efr32mg21a020f1024im32 + - name: efr32bg22 + socs: + - name: efr32bg22c224f512im40 + - name: efr32mg24 + socs: + - name: efr32mg24b220f1536im48 + - name: efr32mg24b310f1536im48 + - name: efr32bg27 + socs: + - name: efr32bg27c140f768im40 diff --git a/soc/sparc/Kconfig b/soc/sparc/Kconfig deleted file mode 100644 index de68a73004895b..00000000000000 --- a/soc/sparc/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SPARC_CASA - default y if SPARC - -config SOC_SPARC_LEON - bool diff --git a/soc/sparc/gr716a/CMakeLists.txt b/soc/sparc/gr716a/CMakeLists.txt deleted file mode 100644 index 888e386817e6bc..00000000000000 --- a/soc/sparc/gr716a/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(../leon3/idle.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/sparc/gr716a/Kconfig.defconfig b/soc/sparc/gr716a/Kconfig.defconfig deleted file mode 100644 index ef9bf0ca77811b..00000000000000 --- a/soc/sparc/gr716a/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -if SOC_GR716A - -config SOC - default "gr716a" - -config SPARC_NWIN - default 31 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - int - default 50000000 - -if FLASH - -config SPI - default y - -config SPI_NOR - default y - -config SPI_GRLIB_SPIMCTRL - default y - -endif - -endif diff --git a/soc/sparc/gr716a/Kconfig.soc b/soc/sparc/gr716a/Kconfig.soc deleted file mode 100644 index d74f04a28eb8d1..00000000000000 --- a/soc/sparc/gr716a/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SOC_GR716A - bool "GR716A LEON3 fault-tolerant microcontroller" - select SPARC - select SOC_SPARC_LEON - select CPU_HAS_FPU diff --git a/soc/sparc/leon3/CMakeLists.txt b/soc/sparc/leon3/CMakeLists.txt deleted file mode 100644 index 722526c00cf8ae..00000000000000 --- a/soc/sparc/leon3/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources(idle.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/sparc/leon3/Kconfig.defconfig b/soc/sparc/leon3/Kconfig.defconfig deleted file mode 100644 index 52a71b68275ea8..00000000000000 --- a/soc/sparc/leon3/Kconfig.defconfig +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LEON3 - -config SOC - default "leon3" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 40000000 - -endif diff --git a/soc/sparc/leon3/Kconfig.soc b/soc/sparc/leon3/Kconfig.soc deleted file mode 100644 index f3e01822092a91..00000000000000 --- a/soc/sparc/leon3/Kconfig.soc +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2019-2020 Cobham Gaisler AB -# SPDX-License-Identifier: Apache-2.0 - -config SOC_LEON3 - bool "A LEON3 SOC which you can configure" - select SPARC - select SOC_SPARC_LEON diff --git a/soc/st/stm32/CMakeLists.txt b/soc/st/stm32/CMakeLists.txt new file mode 100644 index 00000000000000..cda6e428374852 --- /dev/null +++ b/soc/st/stm32/CMakeLists.txt @@ -0,0 +1,5 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(common) +add_subdirectory(${SOC_SERIES}) diff --git a/soc/st/stm32/Kconfig b/soc/st/stm32/Kconfig new file mode 100644 index 00000000000000..363f772f74d1a9 --- /dev/null +++ b/soc/st/stm32/Kconfig @@ -0,0 +1,84 @@ +# Copyright (c) 2024 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_STM32 + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select STM32_ENABLE_DEBUG_SLEEP_STOP if DEBUG || ZTEST + select BUILD_OUTPUT_HEX + +if SOC_FAMILY_STM32 + +rsource "*/Kconfig" + +# STM32 wide symbols definitions + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_CCM := zephyr,ccm + +config STM32_CCM + def_bool $(dt_chosen_enabled,$(DT_CHOSEN_Z_CCM)) + +config USE_STM32_ASSERT + depends on ASSERT + bool "STM32Cube HAL and LL drivers asserts" + help + Enable asserts in STM32Cube HAL and LL drivers. + +config STM32_BACKUP_SRAM + bool "STM32 Backup SRAM" + depends on DT_HAS_ST_STM32_BACKUP_SRAM_ENABLED + help + Enable support for STM32 backup SRAM. + +config STM32_ENABLE_DEBUG_SLEEP_STOP + bool "Allow debugger attach in stop/sleep Mode" + help + Some STM32 parts disable the DBGMCU in sleep/stop modes because + of power consumption. As a side-effects this prevents + debuggers from attaching w/o resetting the target. This + effectivly destroys the use-case of `west attach`. Also + SEGGER RTT and similar technologies need this. + +choice POWER_SUPPLY_CHOICE + prompt "STM32 power supply configuration" + default POWER_SUPPLY_LDO + depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32U5X || \ + SOC_STM32WBA55XX + +config POWER_SUPPLY_LDO + bool "LDO supply" + +config POWER_SUPPLY_DIRECT_SMPS + bool "Direct SMPS supply" + +config POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO + bool "SMPS 1.8V supplies LDO (no external supply)" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO + bool "SMPS 2.5V supplies LDO (no external supply)" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO + bool "External SMPS 1.8V supply, supplies LDO" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO + bool "External SMPS 2.5V supply, supplies LDO" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT + bool "External SMPS 1.8V supply and bypass" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT + bool "External SMPS 2.5V supply and bypass" + depends on SOC_SERIES_STM32H7X + +config POWER_SUPPLY_EXTERNAL_SOURCE + bool "Bypass" + depends on SOC_SERIES_STM32H7X + +endchoice + +endif # SOC_FAMILY_STM32 diff --git a/soc/st/stm32/Kconfig.defconfig b/soc/st/stm32/Kconfig.defconfig new file mode 100644 index 00000000000000..b214f103723f9b --- /dev/null +++ b/soc/st/stm32/Kconfig.defconfig @@ -0,0 +1,63 @@ +# ST Microelectronics STM32 all MCU lines + +# Copyright (c) 2017, I-SENSE group of ICCS +# SPDX-License-Identifier: Apache-2.0 + +# Default configurations appplied tp the whole STM32 family + +if SOC_FAMILY_STM32 + +rsource "*/Kconfig.defconfig" + +config CORTEX_M_SYSTICK + default n if STM32_LPTIM_TIMER + +DT_STM32_RCC_PATH := $(dt_nodelabel_path,rcc) +DT_STM32_RCC_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_RCC_PATH),clock-frequency) + +DT_ST_PRESCALER := st,prescaler +DT_STM32_LPTIM_PATH := $(dt_nodelabel_path,stm32_lp_tick_source) + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" + +config LOG_BACKEND_SWO_REF_FREQ_HZ + default "$(DT_STM32_RCC_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,rcc)" + depends on LOG_BACKEND_SWO + +# set the tick per sec as a divider of the LPTIM clock source +# with a minimum value of 4096 for SYS_CLOCK_TICKS_PER_SEC to keep +# SYS_CLOCK_TICKS_PER_SEC not too high compared to the LPTIM counter clock +config SYS_CLOCK_TICKS_PER_SEC + default 4096 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 + default 2048 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 + default 1024 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 + default 512 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 + default 256 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 + depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSE + +config SYS_CLOCK_TICKS_PER_SEC + default 4000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" < 16 + default 2000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 16 + default 1000 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 32 + default 500 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 64 + default 250 if "$(dt_node_int_prop_int,$(DT_STM32_LPTIM_PATH),$(DT_ST_PRESCALER))" = 128 + depends on STM32_LPTIM_TIMER && STM32_LPTIM_CLOCK_LSI + +config CLOCK_CONTROL_STM32_CUBE + default y + depends on CLOCK_CONTROL + +config CLOCK_CONTROL_INIT_PRIORITY + default 1 + depends on CLOCK_CONTROL + +config MEMC_STM32 + default y + depends on MEMC + +# Get flash configuration for NS image from dts flash partition +config USE_DT_CODE_PARTITION + default y if TRUSTED_EXECUTION_NONSECURE + +endif # SOC_FAMILY_STM32 diff --git a/soc/st/stm32/Kconfig.soc b/soc/st/stm32/Kconfig.soc new file mode 100644 index 00000000000000..dce2d0d6557523 --- /dev/null +++ b/soc/st/stm32/Kconfig.soc @@ -0,0 +1,12 @@ +# ST Microelectronics STM32 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_STM32 + bool + +config SOC_FAMILY + default "stm32" if SOC_FAMILY_STM32 + +rsource "*/Kconfig.soc" diff --git a/soc/st/stm32/common/CMakeLists.txt b/soc/st/stm32/common/CMakeLists.txt new file mode 100644 index 00000000000000..abc9793b2c5391 --- /dev/null +++ b/soc/st/stm32/common/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_sources( + stm32cube_hal.c + soc_config.c +) + +zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld) + +zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c) +zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld) diff --git a/soc/arm/st_stm32/common/ccm.ld b/soc/st/stm32/common/ccm.ld similarity index 100% rename from soc/arm/st_stm32/common/ccm.ld rename to soc/st/stm32/common/ccm.ld diff --git a/soc/arm/st_stm32/common/pinctrl_soc.h b/soc/st/stm32/common/pinctrl_soc.h similarity index 100% rename from soc/arm/st_stm32/common/pinctrl_soc.h rename to soc/st/stm32/common/pinctrl_soc.h diff --git a/soc/arm/st_stm32/common/soc_config.c b/soc/st/stm32/common/soc_config.c similarity index 100% rename from soc/arm/st_stm32/common/soc_config.c rename to soc/st/stm32/common/soc_config.c diff --git a/soc/arm/st_stm32/common/stm32_backup_sram.c b/soc/st/stm32/common/stm32_backup_sram.c similarity index 100% rename from soc/arm/st_stm32/common/stm32_backup_sram.c rename to soc/st/stm32/common/stm32_backup_sram.c diff --git a/soc/arm/st_stm32/common/stm32_backup_sram.ld b/soc/st/stm32/common/stm32_backup_sram.ld similarity index 100% rename from soc/arm/st_stm32/common/stm32_backup_sram.ld rename to soc/st/stm32/common/stm32_backup_sram.ld diff --git a/soc/arm/st_stm32/common/stm32_hsem.h b/soc/st/stm32/common/stm32_hsem.h similarity index 100% rename from soc/arm/st_stm32/common/stm32_hsem.h rename to soc/st/stm32/common/stm32_hsem.h diff --git a/soc/arm/st_stm32/common/stm32cube_hal.c b/soc/st/stm32/common/stm32cube_hal.c similarity index 100% rename from soc/arm/st_stm32/common/stm32cube_hal.c rename to soc/st/stm32/common/stm32cube_hal.c diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml new file mode 100644 index 00000000000000..304ab56acfc686 --- /dev/null +++ b/soc/st/stm32/soc.yml @@ -0,0 +1,192 @@ +family: +- name: stm32 + series: + - name: stm32c0x + socs: + - name: stm32c031xx + - name: stm32f0x + socs: + - name: stm32f030x6 + - name: stm32f030x8 + - name: stm32f030xc + - name: stm32f031x6 + - name: stm32f042x6 + - name: stm32f051x8 + - name: stm32f070xb + - name: stm32f072xb + - name: stm32f091xc + - name: stm32f098xx + - name: stm32f1x + socs: + - name: stm32f100xb + - name: stm32f100xe + - name: stm32f103xb + - name: stm32f103xe + - name: stm32f105xc + - name: stm32f107xc + - name: stm32f2x + socs: + - name: stm32f205xx + - name: stm32f207xx + - name: stm32f3x + socs: + - name: stm32f302x8 + - name: stm32f302xc + - name: stm32f303x8 + - name: stm32f303xb + - name: stm32f303xc + - name: stm32f303xe + - name: stm32f334x8 + - name: stm32f373xc + - name: stm32f4x + socs: + - name: stm32f401xc + - name: stm32f401xe + - name: stm32f405xx + - name: stm32f407xx + - name: stm32f410rx + - name: stm32f411xe + - name: stm32f412cx + - name: stm32f412rx + - name: stm32f412vx + - name: stm32f412zx + - name: stm32f413xx + - name: stm32f415xx + - name: stm32f417xx + - name: stm32f423xx + - name: stm32f427xx + - name: stm32f429xx + - name: stm32f437xx + - name: stm32f446xx + - name: stm32f469xx + - name: stm32f7x + socs: + - name: stm32f722xx + - name: stm32f723xx + - name: stm32f745xx + - name: stm32f746xx + - name: stm32f750xx + - name: stm32f756xx + - name: stm32f765xx + - name: stm32f767xx + - name: stm32f769xx + - name: stm32g0x + socs: + - name: stm32g030xx + - name: stm32g031xx + - name: stm32g041xx + - name: stm32g050xx + - name: stm32g051xx + - name: stm32g061xx + - name: stm32g070xx + - name: stm32g071xx + - name: stm32g081xx + - name: stm32g0b0xx + - name: stm32g0b1xx + - name: stm32g0c1xx + - name: stm32g4x + socs: + - name: stm32g431xx + - name: stm32g441xx + - name: stm32g473xx + - name: stm32g474xx + - name: stm32g483xx + - name: stm32g484xx + - name: stm32g491xx + - name: stm32g4a1xx + - name: stm32h5x + socs: + - name: stm32h503xx + - name: stm32h562xx + - name: stm32h563xx + - name: stm32h573xx + - name: stm32h7x + socs: + - name: stm32h7a3xx + - name: stm32h7b0xx + - name: stm32h7b3xx + - name: stm32h723xx + - name: stm32h725xx + - name: stm32h730xx + - name: stm32h735xx + - name: stm32h743xx + - name: stm32h745xx + cpuclusters: + - name: m7 + - name: m4 + - name: stm32h747xx + cpuclusters: + - name: m7 + - name: m4 + - name: stm32h750xx + - name: stm32h753xx + - name: stm32l0x + socs: + - name: stm32l010x4 + - name: stm32l010x6 + - name: stm32l010x8 + - name: stm32l010xb + - name: stm32l011xx + - name: stm32l031xx + - name: stm32l051xx + - name: stm32l053xx + - name: stm32l071xx + - name: stm32l072xx + - name: stm32l073xx + - name: stm32l081xx + - name: stm32l1x + socs: + - name: stm32l151xb + - name: stm32l151xba + - name: stm32l151xc + - name: stm32l152xc + - name: stm32l152xe + - name: stm32l4x + socs: + - name: stm32l412xx + - name: stm32l422xx + - name: stm32l431xx + - name: stm32l432xx + - name: stm32l433xx + - name: stm32l451xx + - name: stm32l452xx + - name: stm32l462xx + - name: stm32l471xx + - name: stm32l475xx + - name: stm32l476xx + - name: stm32l486xx + - name: stm32l496xx + - name: stm32l4a6xx + - name: stm32l4p5xx + - name: stm32l4q5xx + - name: stm32l4s5xx + - name: stm32l4r5xx + - name: stm32l4r9xx + - name: stm32l5x + socs: + - name: stm32l552xx + - name: stm32l562xx + - name: stm32mp1x + socs: + - name: stm32mp157cxx + - name: stm32u5x + socs: + - name: stm32u5a5xx + - name: stm32u5a9xx + - name: stm32u575xx + - name: stm32u585xx + - name: stm32u595xx + - name: stm32u599xx + - name: stm32wbx + socs: + - name: stm32wb55xx + - name: stm32wbax + socs: + - name: stm32wba52xx + - name: stm32wba55xx + - name: stm32wlx + socs: + - name: stm32wle4xx + - name: stm32wle5xx + - name: stm32wl54xx + - name: stm32wl55xx diff --git a/soc/st/stm32/stm32c0x/CMakeLists.txt b/soc/st/stm32/stm32c0x/CMakeLists.txt new file mode 100644 index 00000000000000..eebd281cd96be5 --- /dev/null +++ b/soc/st/stm32/stm32c0x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32c0x/Kconfig b/soc/st/stm32/stm32c0x/Kconfig new file mode 100644 index 00000000000000..8d8c1b89d18721 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32C0 MCU series + +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32C0X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select HAS_STM32CUBE + select CPU_CORTEX_M_HAS_SYSTICK diff --git a/soc/st/stm32/stm32c0x/Kconfig.defconfig b/soc/st/stm32/stm32c0x/Kconfig.defconfig new file mode 100644 index 00000000000000..b960c560bc5cc4 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig.defconfig @@ -0,0 +1,10 @@ +# STMicroelectronics STM32C0 MCU line + +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32C0X + +rsource "Kconfig.defconfig.stm32c0*" + +endif # SOC_SERIES_STM32C0X diff --git a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c031xx b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c031xx similarity index 86% rename from soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c031xx rename to soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c031xx index 5a84b4ff31a12b..96f2cc8da2ab5a 100644 --- a/soc/arm/st_stm32/stm32c0/Kconfig.defconfig.stm32c031xx +++ b/soc/st/stm32/stm32c0x/Kconfig.defconfig.stm32c031xx @@ -5,9 +5,6 @@ if SOC_STM32C031XX -config SOC - default "stm32c031xx" - config NUM_IRQS default 29 diff --git a/soc/st/stm32/stm32c0x/Kconfig.soc b/soc/st/stm32/stm32c0x/Kconfig.soc new file mode 100644 index 00000000000000..c91158abbb15f0 --- /dev/null +++ b/soc/st/stm32/stm32c0x/Kconfig.soc @@ -0,0 +1,18 @@ +# STMicroelectronics STM32C0 MCU line + +# Copyright (c) 2023 Benjamin Björnsson +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32C0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32c0x" if SOC_SERIES_STM32C0X + +config SOC_STM32C031XX + bool + select SOC_SERIES_STM32C0X + +config SOC + default "stm32c031xx" if SOC_STM32C031XX diff --git a/soc/arm/st_stm32/stm32c0/soc.c b/soc/st/stm32/stm32c0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32c0/soc.c rename to soc/st/stm32/stm32c0x/soc.c diff --git a/soc/arm/st_stm32/stm32c0/soc.h b/soc/st/stm32/stm32c0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32c0/soc.h rename to soc/st/stm32/stm32c0x/soc.h diff --git a/soc/st/stm32/stm32f0x/CMakeLists.txt b/soc/st/stm32/stm32f0x/CMakeLists.txt new file mode 100644 index 00000000000000..0ce31c70062bfe --- /dev/null +++ b/soc/st/stm32/stm32f0x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +# The vector table must be placed at the start of SRAM +zephyr_linker_sources_ifdef(CONFIG_SRAM_VECTOR_TABLE + RAM_SECTIONS + SORT_KEY 0 + sram_vector_table.ld +) +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f0x/Kconfig b/soc/st/stm32/stm32f0x/Kconfig new file mode 100644 index 00000000000000..54eb854963a186 --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig @@ -0,0 +1,11 @@ +# ST Microelectronics STM32F0 MCU series + +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F0X + select ARM + select CPU_CORTEX_M0 + select CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_STM32CUBE diff --git a/soc/st/stm32/stm32f0x/Kconfig.defconfig b/soc/st/stm32/stm32f0x/Kconfig.defconfig new file mode 100644 index 00000000000000..23687080b8f7b4 --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig @@ -0,0 +1,20 @@ +# ST Microelectronics STM32F0 MCU line + +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F0 series + +if SOC_SERIES_STM32F0X + +rsource "Kconfig.defconfig.stm32f0*" + +config SRAM_VECTOR_TABLE + default y + +# adjust the fallback because of the LSI oscillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 100 + +endif # SOC_SERIES_STM32F0X diff --git a/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x4 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x4 new file mode 100644 index 00000000000000..3492ea11c99f9e --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x4 @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Antony Pavlov +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F030X4 + +config NUM_IRQS + default 28 + +endif # SOC_STM32F030X4 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x6 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x6 similarity index 83% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x6 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x6 index b65641f1232882..f43a019d232eaa 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x6 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x6 @@ -3,9 +3,6 @@ if SOC_STM32F030X6 -config SOC - default "stm32f030x6" - config NUM_IRQS default 28 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x8 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x8 similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x8 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x8 index f7263ed17ecef0..5fe9da0085d66a 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030x8 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030x8 @@ -5,9 +5,6 @@ if SOC_STM32F030X8 -config SOC - default "stm32f030x8" - config NUM_IRQS default 29 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030xc b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030xc similarity index 82% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030xc rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030xc index 6885f82295cb12..29a31c57bdd8f0 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f030xc +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f030xc @@ -3,9 +3,6 @@ if SOC_STM32F030XC -config SOC - default "stm32f030xc" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f031x6 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f031x6 similarity index 86% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f031x6 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f031x6 index c7f2d37b3e5944..90c240908d412f 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f031x6 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f031x6 @@ -5,9 +5,6 @@ if SOC_STM32F031X6 -config SOC - default "stm32f031x6" - config NUM_IRQS default 28 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f042x6 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f042x6 similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f042x6 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f042x6 index fe4a08966b5974..eacebeedb7a137 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f042x6 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f042x6 @@ -5,9 +5,6 @@ if SOC_STM32F042X6 -config SOC - default "stm32f042x6" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f051x8 b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f051x8 similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f051x8 rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f051x8 index 66f76cc9b24efd..d5af754f15e90a 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f051x8 +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f051x8 @@ -5,9 +5,6 @@ if SOC_STM32F051X8 -config SOC - default "stm32f051x8" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f070xb b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f070xb similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f070xb rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f070xb index 6c6a67a0297172..35b7c18a61e6f8 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f070xb +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f070xb @@ -5,9 +5,6 @@ if SOC_STM32F070XB -config SOC - default "stm32f070xb" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f072xx b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f072xx similarity index 86% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f072xx rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f072xx index 8bfed8c7b109ae..8b8b5a178c25a6 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f072xx +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f072xx @@ -5,9 +5,6 @@ if SOC_STM32F072X8 || SOC_STM32F072XB -config SOC - default "stm32f072xb" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f091xc b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f091xc similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f091xc rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f091xc index 9d17769f7930ea..ba3a9e8058833d 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f091xc +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f091xc @@ -5,9 +5,6 @@ if SOC_STM32F091XC -config SOC - default "stm32f091xc" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f098xx b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f098xx similarity index 84% rename from soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f098xx rename to soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f098xx index 0a877cb26f7461..f82775d9ee9d58 100644 --- a/soc/arm/st_stm32/stm32f0/Kconfig.defconfig.stm32f098xx +++ b/soc/st/stm32/stm32f0x/Kconfig.defconfig.stm32f098xx @@ -5,9 +5,6 @@ if SOC_STM32F098XX -config SOC - default "stm32f098xx" - config NUM_IRQS default 31 diff --git a/soc/st/stm32/stm32f0x/Kconfig.soc b/soc/st/stm32/stm32f0x/Kconfig.soc new file mode 100644 index 00000000000000..d9f4d96a847d75 --- /dev/null +++ b/soc/st/stm32/stm32f0x/Kconfig.soc @@ -0,0 +1,73 @@ +# ST Microelectronics STM32F0 MCU line + +# Copyright (c) 2017 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f0x" if SOC_SERIES_STM32F0X + +config SOC_STM32F030X4 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F030X6 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F030X8 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F030XC + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F031X6 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F042X6 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F051X8 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F070XB + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F072X8 + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F072XB + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F091XC + bool + select SOC_SERIES_STM32F0X + +config SOC_STM32F098XX + bool + select SOC_SERIES_STM32F0X + +# STM32F0 Cube package advises to use 'stm32f030x6' code +# for both STM32F030x4 and STM32F030x6 +config SOC + default "stm32f030x6" if SOC_STM32F030X4 || SOC_STM32F030X6 + default "stm32f030x8" if SOC_STM32F030X8 + default "stm32f030xc" if SOC_STM32F030XC + default "stm32f031x6" if SOC_STM32F031X6 + default "stm32f042x6" if SOC_STM32F042X6 + default "stm32f051x8" if SOC_STM32F051X8 + default "stm32f070xb" if SOC_STM32F070XB + default "stm32f072xb" if SOC_STM32F072X8 || SOC_STM32F072XB + default "stm32f091xc" if SOC_STM32F091XC + default "stm32f098xx" if SOC_STM32F098XX diff --git a/soc/arm/st_stm32/stm32f0/soc.c b/soc/st/stm32/stm32f0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f0/soc.c rename to soc/st/stm32/stm32f0x/soc.c diff --git a/soc/arm/st_stm32/stm32f0/soc.h b/soc/st/stm32/stm32f0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f0/soc.h rename to soc/st/stm32/stm32f0x/soc.h diff --git a/soc/arm/st_stm32/stm32f0/sram_vector_table.ld b/soc/st/stm32/stm32f0x/sram_vector_table.ld similarity index 100% rename from soc/arm/st_stm32/stm32f0/sram_vector_table.ld rename to soc/st/stm32/stm32f0x/sram_vector_table.ld diff --git a/soc/st/stm32/stm32f1x/CMakeLists.txt b/soc/st/stm32/stm32f1x/CMakeLists.txt new file mode 100644 index 00000000000000..eebd281cd96be5 --- /dev/null +++ b/soc/st/stm32/stm32f1x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f1x/Kconfig b/soc/st/stm32/stm32f1x/Kconfig new file mode 100644 index 00000000000000..13680c516c14a6 --- /dev/null +++ b/soc/st/stm32/stm32f1x/Kconfig @@ -0,0 +1,11 @@ +# ST Microelectronics STM32F1 MCU series + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F1X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO diff --git a/soc/st/stm32/stm32f1x/Kconfig.defconfig b/soc/st/stm32/stm32f1x/Kconfig.defconfig new file mode 100644 index 00000000000000..0ca499ef81f351 --- /dev/null +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32F1 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F1 series + +if SOC_SERIES_STM32F1X + +rsource "Kconfig.defconfig.stm32f1*" + +# adjust the fallback because of the LSI oscaillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +endif # SOC_SERIES_STM32F1X diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f100xx b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f100xx similarity index 100% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f100xx rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f100xx diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f103xx similarity index 81% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f103xx index 10a141e0d983e5..d4d30f8a25a7d7 100644 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f103xx +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f103xx @@ -5,9 +5,6 @@ if SOC_STM32F103XB || SOC_STM32F103X8 -config SOC - default "stm32f103xb" - config NUM_IRQS default 43 @@ -15,9 +12,6 @@ endif # SOC_STM32F103XB || SOC_STM32F103X8 if SOC_STM32F103XE -config SOC - default "stm32f103xe" - config NUM_IRQS default 60 diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f105xx b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f105xx similarity index 84% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f105xx rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f105xx index b7963eacb6a246..ac031d653d1441 100644 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f105xx +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f105xx @@ -5,10 +5,6 @@ if SOC_STM32F105XC || SOC_STM32F105XB -config SOC - string - default "stm32f105xc" - config NUM_IRQS int default 68 diff --git a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f107xc similarity index 84% rename from soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc rename to soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f107xc index 5ce4d9f6f1d6ca..944cd2df2ae0e7 100644 --- a/soc/arm/st_stm32/stm32f1/Kconfig.defconfig.stm32f107xc +++ b/soc/st/stm32/stm32f1x/Kconfig.defconfig.stm32f107xc @@ -5,9 +5,6 @@ if SOC_STM32F107XC -config SOC - default "stm32f107xc" - config NUM_IRQS default 68 diff --git a/soc/st/stm32/stm32f1x/Kconfig.soc b/soc/st/stm32/stm32f1x/Kconfig.soc new file mode 100644 index 00000000000000..38258ce187e533 --- /dev/null +++ b/soc/st/stm32/stm32f1x/Kconfig.soc @@ -0,0 +1,76 @@ +# ST Microelectronics STM32F1 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F1X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f1x" if SOC_SERIES_STM32F1X + +config SOC_STM32F100XB + bool + select SOC_SERIES_STM32F1X + +config SOC_STM32F100XE + bool + select SOC_SERIES_STM32F1X + +config SOC_STM32F103XE + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_DENSITY_DEVICE + +config SOC_STM32F103XB + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_DENSITY_DEVICE + +config SOC_STM32F103X8 + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_DENSITY_DEVICE + +config SOC_STM32F105XB + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + +config SOC_STM32F105XC + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + +config SOC_STM32F107XC + bool + select SOC_SERIES_STM32F1X + select SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + +config SOC_STM32F10X_DENSITY_DEVICE + bool + help + STM32F101xx, STM32F102xx, STM32F103xx: + * Low density Value line devices + * Medium density Value line devices + * High density Value line devices + * XL-density devices Value line devices + +config SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE + bool + help + Connectivity line devices are STM32F105xx and STM32F107xx + microcontrollers. They are intended for applications where + connectivity and real-time performances are required such as + industrial control, control panels for security applications, UPS or + home audio. For STM32F107xx also the Ethernet MAC is available. + +config SOC + default "stm32f100xb" if SOC_STM32F100XB + default "stm32f100xe" if SOC_STM32F100XE + default "stm32f103xb" if SOC_STM32F103XB || SOC_STM32F103X8 + default "stm32f103xe" if SOC_STM32F103XE + default "stm32f105xc" if SOC_STM32F105XC || SOC_STM32F105XB + default "stm32f107xc" if SOC_STM32F107XC diff --git a/soc/arm/st_stm32/stm32f1/soc.c b/soc/st/stm32/stm32f1x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f1/soc.c rename to soc/st/stm32/stm32f1x/soc.c diff --git a/soc/arm/st_stm32/stm32f1/soc.h b/soc/st/stm32/stm32f1x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f1/soc.h rename to soc/st/stm32/stm32f1x/soc.h diff --git a/soc/st/stm32/stm32f2x/CMakeLists.txt b/soc/st/stm32/stm32f2x/CMakeLists.txt new file mode 100644 index 00000000000000..eebd281cd96be5 --- /dev/null +++ b/soc/st/stm32/stm32f2x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f2x/Kconfig b/soc/st/stm32/stm32f2x/Kconfig new file mode 100644 index 00000000000000..4821425c09c2d1 --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F2X MCU series + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F2X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO + select CPU_HAS_ARM_MPU diff --git a/soc/st/stm32/stm32f2x/Kconfig.defconfig b/soc/st/stm32/stm32f2x/Kconfig.defconfig new file mode 100644 index 00000000000000..eff10490e63116 --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F2 MCU line + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F2 series + +if SOC_SERIES_STM32F2X + +rsource "Kconfig.defconfig.stm32f2*" + +endif # SOC_SERIES_STM32F2X diff --git a/soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f205xx b/soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f205xx new file mode 100644 index 00000000000000..d045e6d4560f77 --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig.defconfig.stm32f205xx @@ -0,0 +1,11 @@ +# STMicroelectronics stm32f205 MCU + +# Copyright (c) 2021 Manuel Forcen +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F207XX + +config NUM_IRQS + default 81 + +endif diff --git a/soc/st/stm32/stm32f2x/Kconfig.soc b/soc/st/stm32/stm32f2x/Kconfig.soc new file mode 100644 index 00000000000000..f37690b0fa0404 --- /dev/null +++ b/soc/st/stm32/stm32f2x/Kconfig.soc @@ -0,0 +1,23 @@ +# STMicroelectronics stm32f2 MCU line + +# Copyright (c) 2018 qianfan Zhao +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F2X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f2x" if SOC_SERIES_STM32F2X + +config SOC_STM32F205XX + bool + select SOC_SERIES_STM32F2X + +config SOC_STM32F207XX + bool + select SOC_SERIES_STM32F2X + +config SOC + default "stm32f205xx" if SOC_STM32F205XX + default "stm32f207xx" if SOC_STM32F207XX diff --git a/soc/arm/st_stm32/stm32f2/soc.c b/soc/st/stm32/stm32f2x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f2/soc.c rename to soc/st/stm32/stm32f2x/soc.c diff --git a/soc/arm/st_stm32/stm32f2/soc.h b/soc/st/stm32/stm32f2x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f2/soc.h rename to soc/st/stm32/stm32f2x/soc.h diff --git a/soc/st/stm32/stm32f3x/CMakeLists.txt b/soc/st/stm32/stm32f3x/CMakeLists.txt new file mode 100644 index 00000000000000..eebd281cd96be5 --- /dev/null +++ b/soc/st/stm32/stm32f3x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f3x/Kconfig b/soc/st/stm32/stm32f3x/Kconfig new file mode 100644 index 00000000000000..50b83a2a4b6944 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F3 MCU series + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F3X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select HAS_SWO diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig b/soc/st/stm32/stm32f3x/Kconfig.defconfig new file mode 100644 index 00000000000000..e1e87a8e5e58c5 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32F3 MCU line + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F3 series + +if SOC_SERIES_STM32F3X + +rsource "Kconfig.defconfig.stm32f3*" + +endif # SOC_SERIES_STM32F3X diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302x8 b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302x8 new file mode 100644 index 00000000000000..ca69c9eec62944 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302x8 @@ -0,0 +1,11 @@ +# STMicroelectronics STM32F302X8 MCU + +# Copyright (c) 2018 Seitz & Associates +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F302X8 + +config NUM_IRQS + default 82 + +endif # SOC_STM32F302X8 diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302xc b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302xc new file mode 100644 index 00000000000000..9a5268d563eca9 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f302xc @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F302XC MCU + +# Copyright (c) 2022, SECO Spa +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F302XC + +config NUM_IRQS + default 82 + +config CPU_HAS_ARM_MPU + default y + +endif # SOC_STM32F302XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x(b-c) b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x(b-c) similarity index 80% rename from soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x(b-c) rename to soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x(b-c) index 752bef89690812..5971b6f4c246a9 100644 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x(b-c) +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x(b-c) @@ -1,4 +1,4 @@ -# ST Microelectronics STM32F303XC MCU +# STMicroelectronics STM32F303XC MCU # Copyright (c) 2016 RnDity Sp. z o.o. # SPDX-License-Identifier: Apache-2.0 @@ -7,10 +7,10 @@ # size differ). if SOC_STM32F303XB || SOC_STM32F303XC -config SOC - default "stm32f303xc" - config NUM_IRQS default 82 +config CPU_HAS_ARM_MPU + default y + endif # SOC_STM32F303XB || SOC_STM32F303XC diff --git a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x8 b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x8 similarity index 78% rename from soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x8 rename to soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x8 index e585815feb8f8b..827744b868bd4d 100644 --- a/soc/arm/st_stm32/stm32f3/Kconfig.defconfig.stm32f303x8 +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303x8 @@ -1,4 +1,4 @@ -# ST Microelectronics STM32F303x8 MCU +# STMicroelectronics STM32F303x8 MCU # Copyright (c) 2020 Sebastian Schwabe # Fabian Paschke @@ -6,9 +6,6 @@ if SOC_STM32F303X8 -config SOC - default "stm32f303x8" - config NUM_IRQS default 82 diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303xe b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303xe new file mode 100644 index 00000000000000..839c30d4d1a74d --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f303xe @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F303XC MCU + +# Copyright (c) 2020 Paul M. Bendixen +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F303XE + +config NUM_IRQS + default 85 + +config CPU_HAS_ARM_MPU + default y + +endif # SOC_STM32F303XE diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f334x8 b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f334x8 new file mode 100644 index 00000000000000..b115e9d07e4260 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f334x8 @@ -0,0 +1,11 @@ +# STMicroelectronics STM32F334X8 MCU + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F334X8 + +config NUM_IRQS + default 82 + +endif # SOC_STM32F334X8 diff --git a/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f373xc b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f373xc new file mode 100644 index 00000000000000..b3f0dd03d916a6 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.defconfig.stm32f373xc @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F373XC MCU + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F373XC + +config NUM_IRQS + default 82 + +config CPU_HAS_ARM_MPU + default y + +endif # SOC_STM32F373XC diff --git a/soc/st/stm32/stm32f3x/Kconfig.soc b/soc/st/stm32/stm32f3x/Kconfig.soc new file mode 100644 index 00000000000000..cb26880f98d766 --- /dev/null +++ b/soc/st/stm32/stm32f3x/Kconfig.soc @@ -0,0 +1,53 @@ +# STMicroelectronics STM32F3 MCU line + +# Copyright (c) 2016 RnDity Sp. z o.o. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F3X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f3x" if SOC_SERIES_STM32F3X + +config SOC_STM32F302X8 + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F302XC + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303X8 + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303XB + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303XC + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F303XE + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F334X8 + bool + select SOC_SERIES_STM32F3X + +config SOC_STM32F373XC + bool + select SOC_SERIES_STM32F3X + +config SOC + default "stm32f302x8" if SOC_STM32F302X8 + default "stm32f302xc" if SOC_STM32F302XC + default "stm32f303x8" if SOC_STM32F303X8 + default "stm32f303xb" if SOC_STM32F303XB + default "stm32f303xc" if SOC_STM32F303XC + default "stm32f303xe" if SOC_STM32F303XE + default "stm32f334x8" if SOC_STM32F334X8 + default "stm32f373xc" if SOC_STM32F373XC diff --git a/soc/arm/st_stm32/stm32f3/soc.c b/soc/st/stm32/stm32f3x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f3/soc.c rename to soc/st/stm32/stm32f3x/soc.c diff --git a/soc/arm/st_stm32/stm32f3/soc.h b/soc/st/stm32/stm32f3x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f3/soc.h rename to soc/st/stm32/stm32f3x/soc.h diff --git a/soc/st/stm32/stm32f4x/CMakeLists.txt b/soc/st/stm32/stm32f4x/CMakeLists.txt new file mode 100644 index 00000000000000..ea800d26565a0b --- /dev/null +++ b/soc/st/stm32/stm32f4x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) diff --git a/soc/st/stm32/stm32f4x/Kconfig b/soc/st/stm32/stm32f4x/Kconfig new file mode 100644 index 00000000000000..92bba3347755f5 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig @@ -0,0 +1,14 @@ +# STMicroelectronics STM32F4 MCU series + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig b/soc/st/stm32/stm32f4x/Kconfig.defconfig new file mode 100644 index 00000000000000..26fc770096c614 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig @@ -0,0 +1,30 @@ +# STMicroelectronics STM32F4 MCU line + +# Copyright (c) 2016 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F4 series + +if SOC_SERIES_STM32F4X + +rsource "Kconfig.defconfig.stm32f4*" + +# adjust the fallback because of the LSI oscaillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +if PM + +config COUNTER + default y + +config COUNTER_RTC_STM32_SUBSECONDS + default y if DT_HAS_ST_STM32_RTC_ENABLED + +config IDLE_STACK_SIZE + default 512 + +endif # PM + +endif # SOC_SERIES_STM32F4X diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xc b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xc similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xc rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xc index 21549f883fa997..2149fac901e446 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xc +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xc @@ -5,9 +5,6 @@ if SOC_STM32F401XC -config SOC - default "stm32f401xc" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xe b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xe similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xe rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xe index 643d071c5e9b4d..60e85df4d93dd9 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f401xe +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xe @@ -5,9 +5,6 @@ if SOC_STM32F401XE -config SOC - default "stm32f401xe" - config NUM_IRQS default 85 diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f405xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f405xx new file mode 100644 index 00000000000000..646517bfbedf0b --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f405xx @@ -0,0 +1,11 @@ +# ST STM32F405XX MCU configuration options + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F405XX + +config NUM_IRQS + default 82 + +endif # SOC_STM32F405XX diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f407xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f407xx new file mode 100644 index 00000000000000..ee8c67085aac50 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f407xx @@ -0,0 +1,11 @@ +# ST STM32F407XX MCU configuration options + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F407XE || SOC_STM32F407XG + +config NUM_IRQS + default 82 + +endif diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f410xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f410xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f410xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f410xx index dde123f61737ec..ecd4452303cac7 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f410xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f410xx @@ -5,9 +5,6 @@ if SOC_STM32F410RX -config SOC - default "stm32f410rx" - config NUM_IRQS default 97 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f411xe b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f411xe similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f411xe rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f411xe index e83c7bbcbabc97..f403532b493a3b 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f411xe +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f411xe @@ -5,9 +5,6 @@ if SOC_STM32F411XE -config SOC - default "stm32f411xe" - config NUM_IRQS default 86 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412rx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412rx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412rx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412rx index 94d4a1bc0a8651..32df074def118a 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f412rx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412rx @@ -5,9 +5,6 @@ if SOC_STM32F412RX -config SOC - default "stm32f412rx" - config NUM_IRQS default 97 diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412xx new file mode 100644 index 00000000000000..e86d8c1f0b4e32 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f412xx @@ -0,0 +1,11 @@ +# ST STM32F412XX MCU configuration options + +# Copyright (c) 2024 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32F412CX || SOC_STM32F412VX || SOC_STM32F412ZX + +config NUM_IRQS + default 97 + +endif diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f413xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f413xx similarity index 85% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f413xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f413xx index 568afdddf849c0..ef74ff5ff77514 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f413xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f413xx @@ -5,9 +5,6 @@ if SOC_STM32F413XX -config SOC - default "stm32f413xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f415xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f415xx similarity index 85% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f415xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f415xx index 8b9be0ce0d6ac6..b79b20746a14bf 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f415xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f415xx @@ -5,9 +5,6 @@ if SOC_STM32F415XX -config SOC - default "stm32f415xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f417xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f417xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f417xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f417xx index beb1c1b1db2dc1..6bc928003ca939 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f417xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f417xx @@ -5,9 +5,6 @@ if SOC_STM32F417XX -config SOC - default "stm32f417xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f423xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f423xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f423xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f423xx index c7f6d30aeb1749..36b4d0987d781c 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f423xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f423xx @@ -5,9 +5,6 @@ if SOC_STM32F423XX -config SOC - default "stm32f423xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f427xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f427xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f427xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f427xx index 46415d356d4af2..66a1ae8963bc76 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f427xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f427xx @@ -5,9 +5,6 @@ if SOC_STM32F427XX -config SOC - default "stm32f427xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f429xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f429xx index f68bf7bedd0928..681dd9b0a8fe79 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f429xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f429xx @@ -5,9 +5,6 @@ if SOC_STM32F429XX -config SOC - default "stm32f429xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f437xx similarity index 86% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f437xx index bb20242284eed6..60aeb2807d4b03 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f437xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f437xx @@ -5,9 +5,6 @@ if SOC_STM32F437XX -config SOC - default "stm32f437xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f446xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f446xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f446xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f446xx index 6c3f98140a850b..bafecebf0f5a71 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f446xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f446xx @@ -5,9 +5,6 @@ if SOC_STM32F446XX -config SOC - default "stm32f446xx" - config NUM_IRQS default 97 diff --git a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f469xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f469xx similarity index 84% rename from soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f469xx rename to soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f469xx index e9b17f18886020..b8e768c86cdd0c 100644 --- a/soc/arm/st_stm32/stm32f4/Kconfig.defconfig.stm32f469xx +++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f469xx @@ -5,9 +5,6 @@ if SOC_STM32F469XX -config SOC - default "stm32f469xx" - config NUM_IRQS default 93 diff --git a/soc/st/stm32/stm32f4x/Kconfig.soc b/soc/st/stm32/stm32f4x/Kconfig.soc new file mode 100644 index 00000000000000..0f830e8a365660 --- /dev/null +++ b/soc/st/stm32/stm32f4x/Kconfig.soc @@ -0,0 +1,113 @@ +# STMicroelectronics STM32F4 MCU line + +# Copyright (c) 2016 Linaro Limited. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F4X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f4x" if SOC_SERIES_STM32F4X + +config SOC_STM32F401XC + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F401XE + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F405XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F407XE + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F407XG + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F410RX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F411XE + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412CX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412RX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412VX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F412ZX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F413XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F415XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F417XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F423XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F427XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F429XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F437XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F446XX + bool + select SOC_SERIES_STM32F4X + +config SOC_STM32F469XX + bool + select SOC_SERIES_STM32F4X + +config SOC + default "stm32f401xc" if SOC_STM32F401XC + default "stm32f401xe" if SOC_STM32F401XE + default "stm32f405xx" if SOC_STM32F405XX + default "stm32f407xx" if SOC_STM32F407XE + default "stm32f407xx" if SOC_STM32F407XG + default "stm32f410rx" if SOC_STM32F410RX + default "stm32f411xe" if SOC_STM32F411XE + default "stm32f412cx" if SOC_STM32F412CX + default "stm32f412rx" if SOC_STM32F412RX + default "stm32f412vx" if SOC_STM32F412VX + default "stm32f412zx" if SOC_STM32F412ZX + default "stm32f413xx" if SOC_STM32F413XX + default "stm32f415xx" if SOC_STM32F415XX + default "stm32f417xx" if SOC_STM32F417XX + default "stm32f423xx" if SOC_STM32F423XX + default "stm32f427xx" if SOC_STM32F427XX + default "stm32f429xx" if SOC_STM32F429XX + default "stm32f437xx" if SOC_STM32F437XX + default "stm32f446xx" if SOC_STM32F446XX + default "stm32f469xx" if SOC_STM32F469XX diff --git a/soc/arm/st_stm32/stm32f4/power.c b/soc/st/stm32/stm32f4x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32f4/power.c rename to soc/st/stm32/stm32f4x/power.c diff --git a/soc/arm/st_stm32/stm32f4/soc.c b/soc/st/stm32/stm32f4x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f4/soc.c rename to soc/st/stm32/stm32f4x/soc.c diff --git a/soc/arm/st_stm32/stm32f4/soc.h b/soc/st/stm32/stm32f4x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f4/soc.h rename to soc/st/stm32/stm32f4x/soc.h diff --git a/soc/st/stm32/stm32f7x/CMakeLists.txt b/soc/st/stm32/stm32f7x/CMakeLists.txt new file mode 100644 index 00000000000000..eebd281cd96be5 --- /dev/null +++ b/soc/st/stm32/stm32f7x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32f7x/Kconfig b/soc/st/stm32/stm32f7x/Kconfig new file mode 100644 index 00000000000000..1af203c4680b7e --- /dev/null +++ b/soc/st/stm32/stm32f7x/Kconfig @@ -0,0 +1,15 @@ +# ST Microelectronics STM32F7 MCU series + +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F7X + select ARM + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select CPU_HAS_ICACHE + select CPU_HAS_DCACHE + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO diff --git a/soc/st/stm32/stm32f7x/Kconfig.defconfig b/soc/st/stm32/stm32f7x/Kconfig.defconfig new file mode 100644 index 00000000000000..ef1d4ba528304d --- /dev/null +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# ST Microelectronics STM32F7 MCU line + +# Copyright (c) 2018 Yurii Hamann +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32F7 series + +if SOC_SERIES_STM32F7X + +rsource "Kconfig.defconfig.stm32f7*" + +endif # SOC_SERIES_STM32F7X diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f722xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f722xx index 5b85551f939ad3..1ab0276fd91869 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f722xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f722xx @@ -6,9 +6,6 @@ if SOC_STM32F722XX -config SOC - default "stm32f722xx" - config NUM_IRQS default 104 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f723xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f723xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f723xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f723xx index ff7db64ebec8e5..e5195cf396e01d 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f723xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f723xx @@ -5,9 +5,6 @@ if SOC_STM32F723XX -config SOC - default "stm32f723xx" - config NUM_IRQS default 104 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f745xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f745xx similarity index 85% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f745xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f745xx index ec2b00093fc891..83344e1fae4ce5 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f745xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f745xx @@ -5,9 +5,6 @@ if SOC_STM32F745XX -config SOC - default "stm32f745xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f746xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f746xx index 11c009360399fa..a3024dbe00e3b8 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f746xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f746xx @@ -5,9 +5,6 @@ if SOC_STM32F746XX -config SOC - default "stm32f746xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f750xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f750xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f750xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f750xx index d73314e11a42ef..1b228f95f5703f 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f750xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f750xx @@ -5,9 +5,6 @@ if SOC_STM32F750XX -config SOC - default "stm32f750xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f756xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f756xx similarity index 84% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f756xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f756xx index ff59bd3b9b5fad..e9f64abf7bb967 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f756xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f756xx @@ -5,9 +5,6 @@ if SOC_STM32F756XX -config SOC - default "stm32f756xx" - config NUM_IRQS default 98 diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f765xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f765xx similarity index 75% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f765xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f765xx index 37b8d5379398cb..5f0ef8314d732d 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f765xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f765xx @@ -5,10 +5,10 @@ if SOC_STM32F765XX -config SOC - default "stm32f765xx" - config NUM_IRQS - default 110 + default 100 + +config CPU_HAS_FPU_DOUBLE_PRECISION + default y endif # SOC_STM32F765XX diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f767xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f767xx similarity index 80% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f767xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f767xx index e816a061933c71..f906cd308315d2 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f767xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f767xx @@ -5,10 +5,10 @@ if SOC_STM32F767XX -config SOC - default "stm32f767xx" - config NUM_IRQS default 110 +config CPU_HAS_FPU_DOUBLE_PRECISION + default y + endif # SOC_STM32F767XX diff --git a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f769xx b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f769xx similarity index 80% rename from soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f769xx rename to soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f769xx index 4b90ad5a65990d..9a709388c672a0 100644 --- a/soc/arm/st_stm32/stm32f7/Kconfig.defconfig.stm32f769xx +++ b/soc/st/stm32/stm32f7x/Kconfig.defconfig.stm32f769xx @@ -5,10 +5,10 @@ if SOC_STM32F769XX -config SOC - default "stm32f769xx" - config NUM_IRQS default 110 +config CPU_HAS_FPU_DOUBLE_PRECISION + default y + endif # SOC_STM32F769XX diff --git a/soc/st/stm32/stm32f7x/Kconfig.soc b/soc/st/stm32/stm32f7x/Kconfig.soc new file mode 100644 index 00000000000000..4ade7ca8fbf138 --- /dev/null +++ b/soc/st/stm32/stm32f7x/Kconfig.soc @@ -0,0 +1,61 @@ +# ST Microelectronics STM32F7 MCU line + +# Copyright (c) 2018 Yurii Hamann +# Copyright (c) 2022, Rtone. +# Copyright (c) 2023, Rahul Arasikere. +# Copyright (c) 2023 Evan Perry Grove +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32F7X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32f7x" if SOC_SERIES_STM32F7X + +config SOC_STM32F722XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F723XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F745XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F746XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F756XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F750XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F765XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F767XX + bool + select SOC_SERIES_STM32F7X + +config SOC_STM32F769XX + bool + select SOC_SERIES_STM32F7X + +config SOC + default "stm32f722xx" if SOC_STM32F722XX + default "stm32f723xx" if SOC_STM32F723XX + default "stm32f745xx" if SOC_STM32F745XX + default "stm32f746xx" if SOC_STM32F746XX + default "stm32f750xx" if SOC_STM32F750XX + default "stm32f756xx" if SOC_STM32F756XX + default "stm32f765xx" if SOC_STM32F765XX + default "stm32f767xx" if SOC_STM32F767XX + default "stm32f769xx" if SOC_STM32F769XX diff --git a/soc/arm/st_stm32/stm32f7/soc.c b/soc/st/stm32/stm32f7x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32f7/soc.c rename to soc/st/stm32/stm32f7x/soc.c diff --git a/soc/arm/st_stm32/stm32f7/soc.h b/soc/st/stm32/stm32f7x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32f7/soc.h rename to soc/st/stm32/stm32f7x/soc.h diff --git a/soc/st/stm32/stm32g0x/CMakeLists.txt b/soc/st/stm32/stm32g0x/CMakeLists.txt new file mode 100644 index 00000000000000..65706e73bfa099 --- /dev/null +++ b/soc/st/stm32/stm32g0x/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2021 G-Technologies Sdn. Bhd. +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32g0x/Kconfig b/soc/st/stm32/stm32g0x/Kconfig new file mode 100644 index 00000000000000..8fac199d153de0 --- /dev/null +++ b/soc/st/stm32/stm32g0x/Kconfig @@ -0,0 +1,14 @@ +# STMicroelectronics STM32G0 MCU series + +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G0X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select CPU_HAS_ARM_MPU + select HAS_STM32CUBE + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_PM diff --git a/soc/st/stm32/stm32g0x/Kconfig.defconfig b/soc/st/stm32/stm32g0x/Kconfig.defconfig new file mode 100644 index 00000000000000..e4978d0cfe483f --- /dev/null +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32G0 MCU line + +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# Copyright (c) 2021 G-Technologies Sdn. Bhd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32G0X + +rsource "Kconfig.defconfig.stm32g0*" + +endif # SOC_SERIES_STM32G0X diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g030xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g030xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g030xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g030xx index c72bb7058660e7..4800b2584f58c1 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g030xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g030xx @@ -5,9 +5,6 @@ if SOC_STM32G030XX -config SOC - default "stm32g030xx" - config NUM_IRQS default 29 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g031xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g031xx similarity index 83% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g031xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g031xx index 9b7236b98533dc..d6890a5b3727f5 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g031xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g031xx @@ -5,9 +5,6 @@ if SOC_STM32G031XX -config SOC - default "stm32g031xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g041xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g041xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g041xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g041xx index dc63f9e2520246..327f7a42261c36 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g041xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g041xx @@ -5,9 +5,6 @@ if SOC_STM32G041XX -config SOC - default "stm32g041xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g050xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g050xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g050xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g050xx index f2e1592504685b..efaab9634cce94 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g050xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g050xx @@ -5,9 +5,6 @@ if SOC_STM32G050XX -config SOC - default "stm32g050xx" - config NUM_IRQS default 29 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g051xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g051xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g051xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g051xx index 67a06d1c13905f..88177fb506f44a 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g051xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g051xx @@ -5,9 +5,6 @@ if SOC_STM32G051XX -config SOC - default "stm32g051xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g061xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g061xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g061xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g061xx index 4d052632eb6a2d..b81c12efefa0a8 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g061xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g061xx @@ -5,9 +5,6 @@ if SOC_STM32G061XX -config SOC - default "stm32g061xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g070xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g070xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g070xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g070xx index d7eb915534f16d..502dfe952fb75e 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g070xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g070xx @@ -5,9 +5,6 @@ if SOC_STM32G070XX -config SOC - default "stm32g070xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g071xx similarity index 87% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g071xx index a1814043d4d222..3c953d99823229 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g071xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g071xx @@ -6,9 +6,6 @@ if SOC_STM32G071XX -config SOC - default "stm32g071xx" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g081xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g081xx similarity index 86% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g081xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g081xx index ab46bc38c9d9d1..f308c47e668fa6 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g081xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g081xx @@ -6,9 +6,6 @@ if SOC_STM32G081XX -config SOC - default "stm32g081xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b0xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b0xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b0xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b0xx index 3be972e356ab81..02829267715db8 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b0xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b0xx @@ -5,9 +5,6 @@ if SOC_STM32G0B0XX -config SOC - default "stm32g0b0xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b1xx similarity index 90% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b1xx index 767cea2556cd77..9a226fc0ad7332 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0b1xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0b1xx @@ -5,9 +5,6 @@ if SOC_STM32G0B1XX -config SOC - default "stm32g0b1xx" - config NUM_IRQS default 31 diff --git a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0c1xx b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0c1xx similarity index 84% rename from soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0c1xx rename to soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0c1xx index fed2a1f09328fb..0e1e696b72a425 100644 --- a/soc/arm/st_stm32/stm32g0/Kconfig.defconfig.stm32g0c1xx +++ b/soc/st/stm32/stm32g0x/Kconfig.defconfig.stm32g0c1xx @@ -5,9 +5,6 @@ if SOC_STM32G0C1XX -config SOC - default "stm32g0c1xx" - config NUM_IRQS default 32 diff --git a/soc/st/stm32/stm32g0x/Kconfig.soc b/soc/st/stm32/stm32g0x/Kconfig.soc new file mode 100644 index 00000000000000..cc1b5e58a6c360 --- /dev/null +++ b/soc/st/stm32/stm32g0x/Kconfig.soc @@ -0,0 +1,75 @@ +# STMicroelectronics STM32G0 MCU line + +# Copyright (c) 2019 Philippe Retornaz +# Copyright (c) 2019 STMicroelectronics +# Copyright (c) 2020 Thomas Stranger +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32g0x" if SOC_SERIES_STM32G0X + +config SOC_STM32G030XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G031XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G041XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G050XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G051XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G061XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G070XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G071XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G081XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G0B0XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G0B1XX + bool + select SOC_SERIES_STM32G0X + +config SOC_STM32G0C1XX + bool + select SOC_SERIES_STM32G0X + +config SOC + default "stm32g030xx" if SOC_STM32G030XX + default "stm32g031xx" if SOC_STM32G031XX + default "stm32g041xx" if SOC_STM32G041XX + default "stm32g050xx" if SOC_STM32G050XX + default "stm32g051xx" if SOC_STM32G051XX + default "stm32g061xx" if SOC_STM32G061XX + default "stm32g070xx" if SOC_STM32G070XX + default "stm32g071xx" if SOC_STM32G071XX + default "stm32g081xx" if SOC_STM32G081XX + default "stm32g0b0xx" if SOC_STM32G0B0XX + default "stm32g0b1xx" if SOC_STM32G0B1XX + default "stm32g0c1xx" if SOC_STM32G0C1XX diff --git a/soc/arm/st_stm32/stm32g0/power.c b/soc/st/stm32/stm32g0x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32g0/power.c rename to soc/st/stm32/stm32g0x/power.c diff --git a/soc/arm/st_stm32/stm32g0/soc.c b/soc/st/stm32/stm32g0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32g0/soc.c rename to soc/st/stm32/stm32g0x/soc.c diff --git a/soc/arm/st_stm32/stm32g0/soc.h b/soc/st/stm32/stm32g0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32g0/soc.h rename to soc/st/stm32/stm32g0x/soc.h diff --git a/soc/st/stm32/stm32g4x/CMakeLists.txt b/soc/st/stm32/stm32g4x/CMakeLists.txt new file mode 100644 index 00000000000000..cfbedf4ff854df --- /dev/null +++ b/soc/st/stm32/stm32g4x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32g4x/Kconfig b/soc/st/stm32/stm32g4x/Kconfig new file mode 100644 index 00000000000000..50aecbbca3c6cf --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig @@ -0,0 +1,15 @@ +# STMicroelectronics STM32G4 MCU series + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL + select HAS_PM + select HAS_SWO diff --git a/soc/st/stm32/stm32g4x/Kconfig.defconfig b/soc/st/stm32/stm32g4x/Kconfig.defconfig new file mode 100644 index 00000000000000..0a9488d7e4c0b8 --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig @@ -0,0 +1,18 @@ +# STMicroelectronics STM32G4 MCU line + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32G4X + +rsource "Kconfig.defconfig.stm32g4*" + +if PM +config PM_DEVICE + default y + +config STM32_LPTIM_TIMER + default y +endif # PM + +endif # SOC_SERIES_STM32G4X diff --git a/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g431xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g431xx new file mode 100644 index 00000000000000..73d1c70368e314 --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g431xx @@ -0,0 +1,11 @@ +# STMicroelectronics STM32G431XX MCU + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32G431XX + +config NUM_IRQS + default 102 + +endif # SOC_STM32G431XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g441xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g441xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g441xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g441xx index 3630ac865d224b..ec5a0092cd0f9e 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g441xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g441xx @@ -5,9 +5,6 @@ if SOC_STM32G441XX -config SOC - default "stm32g441xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g473xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g473xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g473xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g473xx index 108ca2aecf1c72..46caf1f4bc0bdf 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g473xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g473xx @@ -5,9 +5,6 @@ if SOC_STM32G473XX -config SOC - default "stm32g473xx" - config NUM_IRQS default 102 diff --git a/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g474xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g474xx new file mode 100644 index 00000000000000..dac9df141e10d7 --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g474xx @@ -0,0 +1,11 @@ +# STMicroelectronics STM32G474XX MCU + +# Copyright (c) 2019 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32G474XX + +config NUM_IRQS + default 102 + +endif # SOC_STM32G474XX diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g483xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g483xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g483xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g483xx index 5564372b3bbe5e..b0cd7a2b55dfca 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g483xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g483xx @@ -5,9 +5,6 @@ if SOC_STM32G483XX -config SOC - default "stm32g483xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g484xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g484xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g484xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g484xx index 2c5b500833c62e..ed1165bef1f15c 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g484xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g484xx @@ -5,9 +5,6 @@ if SOC_STM32G484XX -config SOC - default "stm32g484xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g491xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g491xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g491xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g491xx index a8cbbe859f0a9b..33a14e1c58e281 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g491xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g491xx @@ -5,9 +5,6 @@ if SOC_STM32G491XX -config SOC - default "stm32g491xx" - config NUM_IRQS default 102 diff --git a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4a1xx b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g4a1xx similarity index 84% rename from soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4a1xx rename to soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g4a1xx index 280eb0790a2abb..f472e8323e627a 100644 --- a/soc/arm/st_stm32/stm32g4/Kconfig.defconfig.stm32g4a1xx +++ b/soc/st/stm32/stm32g4x/Kconfig.defconfig.stm32g4a1xx @@ -5,9 +5,6 @@ if SOC_STM32G4A1XX -config SOC - default "stm32g4a1xx" - config NUM_IRQS default 102 diff --git a/soc/st/stm32/stm32g4x/Kconfig.soc b/soc/st/stm32/stm32g4x/Kconfig.soc new file mode 100644 index 00000000000000..110fe503fabd23 --- /dev/null +++ b/soc/st/stm32/stm32g4x/Kconfig.soc @@ -0,0 +1,53 @@ +# STMicroelectronics STM32G4 MCU line + +# Copyright (c) 2019 Richard Osterloh +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32G4X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32g4x" if SOC_SERIES_STM32G4X + +config SOC_STM32G431XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G441XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G473XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G474XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G483XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G484XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G491XX + bool + select SOC_SERIES_STM32G4X + +config SOC_STM32G4A1XX + bool + select SOC_SERIES_STM32G4X + +config SOC + default "stm32g431xx" if SOC_STM32G431XX + default "stm32g441xx" if SOC_STM32G441XX + default "stm32g473xx" if SOC_STM32G473XX + default "stm32g474xx" if SOC_STM32G474XX + default "stm32g483xx" if SOC_STM32G483XX + default "stm32g484xx" if SOC_STM32G484XX + default "stm32g491xx" if SOC_STM32G491XX + default "stm32g4a1xx" if SOC_STM32G4A1XX diff --git a/soc/arm/st_stm32/stm32g4/power.c b/soc/st/stm32/stm32g4x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32g4/power.c rename to soc/st/stm32/stm32g4x/power.c diff --git a/soc/st/stm32/stm32g4x/soc.c b/soc/st/stm32/stm32g4x/soc.c new file mode 100644 index 00000000000000..c8d41f474f94fa --- /dev/null +++ b/soc/st/stm32/stm32g4x/soc.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2019 Richard Osterloh + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for STM32G4 processor + */ + +#include +#include +#include +#include + +#include +#if defined(PWR_CR3_UCPD_DBDIS) +#include +#include +#endif /* PWR_CR3_UCPD_DBDIS */ + +/** + * @brief Perform basic hardware initialization at boot. + * + * This needs to be run from the very beginning. + * So the init priority has to be 0 (zero). + * + * @return 0 + */ +static int stm32g4_init(void) +{ + /* Update CMSIS SystemCoreClock variable (HCLK) */ + /* At reset, system core clock is set to 16 MHz from HSI */ + SystemCoreClock = 16000000; + + /* allow reflashing board */ + LL_DBGMCU_EnableDBGSleepMode(); + +#if defined(PWR_CR3_UCPD_DBDIS) + /* Disable USB Type-C dead battery pull-down behavior */ + LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR); + LL_PWR_DisableUCPDDeadBattery(); +#endif /* PWR_CR3_UCPD_DBDIS */ + return 0; +} + +SYS_INIT(stm32g4_init, PRE_KERNEL_1, 0); diff --git a/soc/arm/st_stm32/stm32g4/soc.h b/soc/st/stm32/stm32g4x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32g4/soc.h rename to soc/st/stm32/stm32g4x/soc.h diff --git a/soc/st/stm32/stm32h5x/CMakeLists.txt b/soc/st/stm32/stm32h5x/CMakeLists.txt new file mode 100644 index 00000000000000..eebd281cd96be5 --- /dev/null +++ b/soc/st/stm32/stm32h5x/CMakeLists.txt @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32h5x/Kconfig b/soc/st/stm32/stm32h5x/Kconfig new file mode 100644 index 00000000000000..9ff02424ebd048 --- /dev/null +++ b/soc/st/stm32/stm32h5x/Kconfig @@ -0,0 +1,16 @@ +# ST Microelectronics STM32H5 MCU series + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H5X + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M if !SOC_STM32H503XX + select CPU_HAS_ARM_SAU if !SOC_STM32H503XX + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO diff --git a/soc/st/stm32/stm32h5x/Kconfig.defconfig b/soc/st/stm32/stm32h5x/Kconfig.defconfig new file mode 100644 index 00000000000000..f8167440f3360d --- /dev/null +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32H5 MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32H5X + +rsource "Kconfig.defconfig.stm32h5*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32H5X diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h503xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h503xx index e7d7b508baace3..fb6e125f87fb11 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h503xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h503xx @@ -5,9 +5,6 @@ if SOC_STM32H503XX -config SOC - default "stm32h503xx" - config NUM_IRQS default 134 diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h562xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h562xx index eb76a2d798925a..f7dc9451df09dd 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h562xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h562xx @@ -5,9 +5,6 @@ if SOC_STM32H562XX -config SOC - default "stm32h562xx" - config NUM_IRQS default 131 diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h563xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h563xx index 94994a7d060ad8..1a36a617e5309f 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h563xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h563xx @@ -5,9 +5,6 @@ if SOC_STM32H563XX -config SOC - default "stm32h563xx" - config NUM_IRQS default 131 diff --git a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h573xx similarity index 84% rename from soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx rename to soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h573xx index d6641c126eca8b..af698c3e81ccbf 100644 --- a/soc/arm/st_stm32/stm32h5/Kconfig.defconfig.stm32h573xx +++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig.stm32h573xx @@ -5,9 +5,6 @@ if SOC_STM32H573XX -config SOC - default "stm32h573xx" - config NUM_IRQS default 131 diff --git a/soc/st/stm32/stm32h5x/Kconfig.soc b/soc/st/stm32/stm32h5x/Kconfig.soc new file mode 100644 index 00000000000000..f218ad100648e4 --- /dev/null +++ b/soc/st/stm32/stm32h5x/Kconfig.soc @@ -0,0 +1,33 @@ +# ST Microelectronics STM32H5 MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H5X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32h5x" if SOC_SERIES_STM32H5X + +config SOC_STM32H503XX + bool + select SOC_SERIES_STM32H5X + +config SOC_STM32H562XX + bool + select SOC_SERIES_STM32H5X + +config SOC_STM32H563XX + bool + select SOC_SERIES_STM32H5X + +config SOC_STM32H573XX + bool + select SOC_SERIES_STM32H5X + +config SOC + default "stm32h503xx" if SOC_STM32H503XX + default "stm32h562xx" if SOC_STM32H562XX + default "stm32h563xx" if SOC_STM32H563XX + default "stm32h573xx" if SOC_STM32H573XX diff --git a/soc/arm/st_stm32/stm32h5/soc.c b/soc/st/stm32/stm32h5x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32h5/soc.c rename to soc/st/stm32/stm32h5x/soc.c diff --git a/soc/arm/st_stm32/stm32h5/soc.h b/soc/st/stm32/stm32h5x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32h5/soc.h rename to soc/st/stm32/stm32h5x/soc.h diff --git a/soc/st/stm32/stm32h7x/CMakeLists.txt b/soc/st/stm32/stm32h7x/CMakeLists.txt new file mode 100644 index 00000000000000..b4ea68f3c47583 --- /dev/null +++ b/soc/st/stm32/stm32h7x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) + +zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M7 soc_m7.c) +zephyr_sources_ifdef(CONFIG_CPU_CORTEX_M4 soc_m4.c) + +zephyr_sources(mpu_regions.c) +zephyr_linker_sources(SECTIONS sections.ld) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32h7x/Kconfig b/soc/st/stm32/stm32h7x/Kconfig new file mode 100644 index 00000000000000..f72707ae0067c6 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig @@ -0,0 +1,82 @@ +# ST Microelectronics STM32H7 MCU series + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H7X + select ARM + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select USE_STM32_HAL_CORTEX + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS + select CPU_HAS_FPU_DOUBLE_PRECISION if CPU_CORTEX_M7 + select CPU_HAS_ICACHE if CPU_CORTEX_M7 + select CPU_HAS_DCACHE if CPU_CORTEX_M7 + +config SOC_STM32H723XX + select CPU_CORTEX_M7 + +config SOC_STM32H725XX + select CPU_CORTEX_M7 + +config SOC_STM32H730XX + select CPU_CORTEX_M7 + +config SOC_STM32H730XXQ + select CPU_CORTEX_M7 + +config SOC_STM32H735XX + select CPU_CORTEX_M7 + +config SOC_STM32H743XX + select CPU_CORTEX_M7 + +config SOC_STM32H745XX_M7 + select CPU_CORTEX_M7 + +config SOC_STM32H745XX_M4 + select CPU_CORTEX_M4 + +config SOC_STM32H747XX_M7 + select CPU_CORTEX_M7 + +config SOC_STM32H747XX_M4 + select CPU_CORTEX_M4 + +config SOC_STM32H750XX + select CPU_CORTEX_M7 + +config SOC_STM32H753XX + select CPU_CORTEX_M7 + +config SOC_STM32H7A3XX + select CPU_CORTEX_M7 + +config SOC_STM32H7A3XXQ + select CPU_CORTEX_M7 + +config SOC_STM32H7B0XX + select CPU_CORTEX_M7 + +config SOC_STM32H7B0XXQ + select CPU_CORTEX_M7 + +config SOC_STM32H7B3XX + select CPU_CORTEX_M7 + +config SOC_STM32H7B3XXQ + select CPU_CORTEX_M7 + +if SOC_SERIES_STM32H7X + +config STM32H7_DUAL_CORE + bool "Dual Core" + +config STM32H7_BOOT_M4_AT_INIT + bool "Boot M4 core during M7 init independent of option byte BCM4." + default y + +endif # SOC_SERIES_STM32H7X diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig b/soc/st/stm32/stm32h7x/Kconfig.defconfig new file mode 100644 index 00000000000000..790b1659c05140 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32H7 MCU line + +# Copyright (c) 2019 Linaro Limited +# Copyright (c) 2022 SILA Embedded Solutions GmbH +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32H7 series + +if SOC_SERIES_STM32H7X + +rsource "Kconfig.defconfig.stm32h7*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + default 0x0 if !BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32H7X diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h723xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h723xx similarity index 86% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h723xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h723xx index b640a00eeef6d8..53acf7448b9425 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h723xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h723xx @@ -5,9 +5,6 @@ if SOC_STM32H723XX -config SOC - default "stm32h723xx" - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h725xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h725xx similarity index 84% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h725xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h725xx index b5e50ed4fa15ce..061ea62a2a37bb 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h725xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h725xx @@ -5,9 +5,6 @@ if SOC_STM32H725XX -config SOC - default "stm32h725xx" - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h730xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h730xx similarity index 75% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h730xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h730xx index 51b110dbc9f879..93befd25a9c471 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h730xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h730xx @@ -6,10 +6,6 @@ if SOC_STM32H730XX || SOC_STM32H730XXQ -config SOC - default "stm32h730xxQ" if SOC_STM32H730XXQ - default "stm32h730xx" if SOC_STM32H730XX - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h735xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h735xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h735xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h735xx index fec1b04d46e658..33d0a741f899f4 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h735xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h735xx @@ -5,9 +5,6 @@ if SOC_STM32H735XX -config SOC - default "stm32h735xx" - config NUM_IRQS default 163 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h743xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h743xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h743xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h743xx index 3774f4f8a9398e..d54e5b0d6d57e9 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h743xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h743xx @@ -5,9 +5,6 @@ if SOC_STM32H743XX -config SOC - default "stm32h743xx" - config NUM_IRQS default 150 diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h745xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h745xx new file mode 100644 index 00000000000000..feeba8cff1e63e --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h745xx @@ -0,0 +1,14 @@ +# ST STM32H745X MCU configuration options + +# Copyright (c) 2020 Alexander Kozhinov +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4 + +config STM32H7_DUAL_CORE + default y + +config NUM_IRQS + default 150 + +endif # SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4 diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h747xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h747xx new file mode 100644 index 00000000000000..32496e0711e236 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h747xx @@ -0,0 +1,14 @@ +# ST STM32H747X MCU configuration options + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4 + +config STM32H7_DUAL_CORE + default y + +config NUM_IRQS + default 150 + +endif # SOC_STM32H747XX_M7 || SOC_STM32H747XX_M7 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h750xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h750xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h750xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h750xx index 13d859aa53e831..1d00fdc403b1e4 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h750xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h750xx @@ -5,9 +5,6 @@ if SOC_STM32H750XX -config SOC - default "stm32h750xx" - config NUM_IRQS default 150 diff --git a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h753xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h753xx similarity index 85% rename from soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h753xx rename to soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h753xx index 20253b33784e79..06b08dfcdc2f35 100644 --- a/soc/arm/st_stm32/stm32h7/Kconfig.defconfig.stm32h753xx +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h753xx @@ -5,9 +5,6 @@ if SOC_STM32H753XX -config SOC - default "stm32h753xx" - config NUM_IRQS default 150 diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7a3xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7a3xx new file mode 100644 index 00000000000000..ab1ff87833b7f9 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7a3xx @@ -0,0 +1,11 @@ +# ST STM32H7A3X MCU configuration options + +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H7A3XX || SOC_STM32H7A3XXQ + +config NUM_IRQS + default 155 + +endif # SOC_STM32H7A3XX || SOC_STM32H7A3XXQ diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b0xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b0xx new file mode 100644 index 00000000000000..0cb129871b697a --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b0xx @@ -0,0 +1,11 @@ +# ST STM32H7B0XX MCU configuration options + +# Copyright (c) 2023 Charles Dias +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H7B0XX || SOC_STM32H7B0XXQ + +config NUM_IRQS + default 155 + +endif # SOC_STM32H7B0XX || SOC_STM32H7B0XXQ diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b3xx b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b3xx new file mode 100644 index 00000000000000..92de5028545925 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig.stm32h7b3xx @@ -0,0 +1,11 @@ +# ST STM32H7B3X MCU configuration options + +# Copyright (c) 2022 Byte-Lab d.o.o +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32H7B3XX || SOC_STM32H7B3XXQ + +config NUM_IRQS + default 155 + +endif # SOC_STM32H7B3XX || SOC_STM32H7B3XXQ diff --git a/soc/st/stm32/stm32h7x/Kconfig.soc b/soc/st/stm32/stm32h7x/Kconfig.soc new file mode 100644 index 00000000000000..18841c0262c478 --- /dev/null +++ b/soc/st/stm32/stm32h7x/Kconfig.soc @@ -0,0 +1,103 @@ +# ST Microelectronics STM32H7 MCU line + +# Copyright (c) 2019 Linaro Limited +# Copyright (c) 2020 Teslabs Engineering S.L. +# Copyright (c) 2021 Electrolance Solutions +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32H7X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32h7x" if SOC_SERIES_STM32H7X + +config SOC_STM32H723XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H725XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H730XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H730XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H735XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H743XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H745XX_M7 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H745XX_M4 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H747XX_M7 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H747XX_M4 + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H750XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H753XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7A3XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7A3XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B0XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B0XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B3XX + bool + select SOC_SERIES_STM32H7X + +config SOC_STM32H7B3XXQ + bool + select SOC_SERIES_STM32H7X + +config SOC + default "stm32h7a3xx" if SOC_STM32H7A3XX + default "stm32h7a3xxq" if SOC_STM32H7A3XXQ + default "stm32h7b0xx" if SOC_STM32H7B0XX + default "stm32h7b0xxq" if SOC_STM32H7B0XXQ + default "stm32h7b3xx" if SOC_STM32H7B3XX + default "stm32h7b3xxq"if SOC_STM32H7B3XXQ + default "stm32h723xx" if SOC_STM32H723XX + default "stm32h725xx" if SOC_STM32H725XX + default "stm32h730xx" if SOC_STM32H730XX + default "stm32h730xxq" if SOC_STM32H730XXQ + default "stm32h735xx" if SOC_STM32H735XX + default "stm32h743xx" if SOC_STM32H743XX + default "stm32h745xx" if SOC_STM32H745XX_M7 || SOC_STM32H745XX_M4 + default "stm32h747xx" if SOC_STM32H747XX_M7 || SOC_STM32H747XX_M4 + default "stm32h750xx" if SOC_STM32H750XX + default "stm32h753xx" if SOC_STM32H753XX diff --git a/soc/arm/st_stm32/stm32h7/mpu_regions.c b/soc/st/stm32/stm32h7x/mpu_regions.c similarity index 100% rename from soc/arm/st_stm32/stm32h7/mpu_regions.c rename to soc/st/stm32/stm32h7x/mpu_regions.c diff --git a/soc/arm/st_stm32/stm32h7/sections.ld b/soc/st/stm32/stm32h7x/sections.ld similarity index 100% rename from soc/arm/st_stm32/stm32h7/sections.ld rename to soc/st/stm32/stm32h7x/sections.ld diff --git a/soc/arm/st_stm32/stm32h7/soc.h b/soc/st/stm32/stm32h7x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32h7/soc.h rename to soc/st/stm32/stm32h7x/soc.h diff --git a/soc/arm/st_stm32/stm32h7/soc_m4.c b/soc/st/stm32/stm32h7x/soc_m4.c similarity index 100% rename from soc/arm/st_stm32/stm32h7/soc_m4.c rename to soc/st/stm32/stm32h7x/soc_m4.c diff --git a/soc/arm/st_stm32/stm32h7/soc_m7.c b/soc/st/stm32/stm32h7x/soc_m7.c similarity index 100% rename from soc/arm/st_stm32/stm32h7/soc_m7.c rename to soc/st/stm32/stm32h7x/soc_m7.c diff --git a/soc/st/stm32/stm32l0x/CMakeLists.txt b/soc/st/stm32/stm32l0x/CMakeLists.txt new file mode 100644 index 00000000000000..bc9a65c0049227 --- /dev/null +++ b/soc/st/stm32/stm32l0x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l0x/Kconfig b/soc/st/stm32/stm32l0x/Kconfig new file mode 100644 index 00000000000000..80479edffec975 --- /dev/null +++ b/soc/st/stm32/stm32l0x/Kconfig @@ -0,0 +1,30 @@ +# ST Microelectronics STM32L0 MCU series + +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L0X + select ARM + select CPU_CORTEX_M0PLUS + select CPU_CORTEX_M_HAS_VTOR + select HAS_STM32CUBE + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_PM + +config SOC_STM32L051XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L053XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L071XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L072XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L073XX + select CPU_HAS_ARM_MPU + +config SOC_STM32L081XX + select CPU_HAS_ARM_MPU diff --git a/soc/st/stm32/stm32l0x/Kconfig.defconfig b/soc/st/stm32/stm32l0x/Kconfig.defconfig new file mode 100644 index 00000000000000..098889979b545b --- /dev/null +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32L0 MCU line + +# Copyright (c) 2018 Endre Karlson +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32L0 series + +if SOC_SERIES_STM32L0X + +rsource "Kconfig.defconfig.stm32l0*" + +# adjust the fallback because of the LSI oscillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +endif # SOC_SERIES_STM32L0X diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x4 b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x4 similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x4 rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x4 index 779d26245082b2..f47057ce5d4857 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x4 +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x4 @@ -5,9 +5,6 @@ if SOC_STM32L010X4 -config SOC - default "stm32l010x4" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x6 b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x6 similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x6 rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x6 index dd86c005ad8054..555ac98a02c329 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x6 +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x6 @@ -5,9 +5,6 @@ if SOC_STM32L010X6 -config SOC - default "stm32l010x6" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x8 b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x8 similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x8 rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x8 index 20dd0b0c09a83a..39dbb520c706be 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010x8 +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010x8 @@ -5,9 +5,6 @@ if SOC_STM32L010X8 -config SOC - default "stm32l010x8" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010xb b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010xb similarity index 86% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010xb rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010xb index 89e20292fc1281..a3aa500c32f64f 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l010xb +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l010xb @@ -5,9 +5,6 @@ if SOC_STM32L010XB -config SOC - default "stm32l010xb" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l011xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l011xx similarity index 84% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l011xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l011xx index fe4c3045d63796..2d31620a4200c1 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l011xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l011xx @@ -5,9 +5,6 @@ if SOC_STM32L011XX -config SOC - default "stm32l011xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l031xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l031xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l031xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l031xx index 554fe3ed1aceae..098e7f2fd77b6b 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l031xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l031xx @@ -5,9 +5,6 @@ if SOC_STM32L031XX -config SOC - default "stm32l031xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l051xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l051xx similarity index 83% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l051xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l051xx index 3b5ff4ffd64571..23f96935824205 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l051xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l051xx @@ -5,9 +5,6 @@ if SOC_STM32L051XX -config SOC - default "stm32l051xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l053xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l053xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l053xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l053xx index 2d2e37e38c8ed7..3ea376859cf808 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l053xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l053xx @@ -5,9 +5,6 @@ if SOC_STM32L053XX -config SOC - default "stm32l053xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l071xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l071xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l071xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l071xx index dcc6b685281e88..41a40c94662b8e 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l071xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l071xx @@ -5,9 +5,6 @@ if SOC_STM32L071XX -config SOC - default "stm32l071xx" - config NUM_IRQS default 30 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l072xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l072xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l072xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l072xx index a03a7696e27914..33089c6253b075 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l072xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l072xx @@ -5,9 +5,6 @@ if SOC_STM32L072XX -config SOC - default "stm32l072xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l073xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l073xx similarity index 85% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l073xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l073xx index d0a7acfd8e52aa..4cf34179d1b623 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l073xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l073xx @@ -5,9 +5,6 @@ if SOC_STM32L073XX -config SOC - default "stm32l073xx" - config NUM_IRQS default 32 diff --git a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l081xx b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l081xx similarity index 86% rename from soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l081xx rename to soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l081xx index f3cc93c38c84f7..87f248e400d14e 100644 --- a/soc/arm/st_stm32/stm32l0/Kconfig.defconfig.stm32l081xx +++ b/soc/st/stm32/stm32l0x/Kconfig.defconfig.stm32l081xx @@ -5,9 +5,6 @@ if SOC_STM32L081XX -config SOC - default "stm32l081xx" - config NUM_IRQS default 32 diff --git a/soc/st/stm32/stm32l0x/Kconfig.soc b/soc/st/stm32/stm32l0x/Kconfig.soc new file mode 100644 index 00000000000000..c3ef0032e2e5e8 --- /dev/null +++ b/soc/st/stm32/stm32l0x/Kconfig.soc @@ -0,0 +1,76 @@ +# ST Microelectronics STM32L0 MCU line + +# Copyright (c) 2018 Endre Karlson +# Copyright (c) 2021 Nomono AS +# Copyright (c) 2023 OS Systems +# +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L0X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l0x" if SOC_SERIES_STM32L0X + +config SOC_STM32L010X4 + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L010X6 + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L010X8 + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L010XB + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L011XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L031XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L051XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L053XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L071XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L072XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L073XX + bool + select SOC_SERIES_STM32L0X + +config SOC_STM32L081XX + bool + select SOC_SERIES_STM32L0X + +config SOC + default "stm32l010x4" if SOC_STM32L010X4 + default "stm32l010x6" if SOC_STM32L010X6 + default "stm32l010x8" if SOC_STM32L010X8 + default "stm32l010xb" if SOC_STM32L010XB + default "stm32l011xx" if SOC_STM32L011XX + default "stm32l031xx" if SOC_STM32L031XX + default "stm32l051xx" if SOC_STM32L051XX + default "stm32l053xx" if SOC_STM32L053XX + default "stm32l071xx" if SOC_STM32L071XX + default "stm32l072xx" if SOC_STM32L072XX + default "stm32l073xx" if SOC_STM32L073XX + default "stm32l081xx" if SOC_STM32L081XX diff --git a/soc/arm/st_stm32/stm32l0/power.c b/soc/st/stm32/stm32l0x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32l0/power.c rename to soc/st/stm32/stm32l0x/power.c diff --git a/soc/arm/st_stm32/stm32l0/soc.c b/soc/st/stm32/stm32l0x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l0/soc.c rename to soc/st/stm32/stm32l0x/soc.c diff --git a/soc/arm/st_stm32/stm32l0/soc.h b/soc/st/stm32/stm32l0x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l0/soc.h rename to soc/st/stm32/stm32l0x/soc.h diff --git a/soc/st/stm32/stm32l1x/CMakeLists.txt b/soc/st/stm32/stm32l1x/CMakeLists.txt new file mode 100644 index 00000000000000..3e033529043e0a --- /dev/null +++ b/soc/st/stm32/stm32l1x/CMakeLists.txt @@ -0,0 +1,8 @@ +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l1x/Kconfig b/soc/st/stm32/stm32l1x/Kconfig new file mode 100644 index 00000000000000..db21b1d0bde839 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig @@ -0,0 +1,12 @@ +# STMicroelectronics STM32L1 MCU series + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L1X + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_SWO + select CPU_HAS_ARM_MPU diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig b/soc/st/stm32/stm32l1x/Kconfig.defconfig new file mode 100644 index 00000000000000..e04f33b22ddedf --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig @@ -0,0 +1,15 @@ +# STMicroelectronics STM32L1 MCU line + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32L1X + +rsource "Kconfig.defconfig.stm32l1*" + +# adjust the fallback because of the LSI oscaillator characteristics +config TASK_WDT_HW_FALLBACK_DELAY + depends on TASK_WDT_HW_FALLBACK + default 200 + +endif # SOC_SERIES_STM32L1X diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xb b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xb new file mode 100644 index 00000000000000..dc9c04cda24000 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xb @@ -0,0 +1,11 @@ +# STMicroelectronics STM32L151XB MCU + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L151XB + +config NUM_IRQS + default 45 + +endif # SOC_STM32L151XB diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xba b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xba new file mode 100644 index 00000000000000..f28ad4276288ea --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xba @@ -0,0 +1,11 @@ +# STMicroelectronics STM32L151XB-A MCU + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L151XBA + +config NUM_IRQS + default 45 + +endif # SOC_STM32L151XBA diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xc b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xc new file mode 100644 index 00000000000000..ba82596f38f5a0 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l151xc @@ -0,0 +1,12 @@ +# STMicroelectronics STM32L151XC MCU + +# Copyright (c) 2020 Abel Sensors +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L151XC + +# Based on stm32cube number of interrupts+1, not datasheet +config NUM_IRQS + default 57 + +endif # SOC_STM32L151XC diff --git a/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xc b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xc new file mode 100644 index 00000000000000..661ce869a45b05 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xc @@ -0,0 +1,12 @@ +# STMicroelectronics STM32L152XC MCU + +# Copyright (c) 2020 Abel Sensors +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32L152XC + +config NUM_IRQS + int + default 57 + +endif # SOC_STM32L152XC diff --git a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xe b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xe similarity index 83% rename from soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xe rename to soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xe index 9a979aa80941b7..604cad7aaf5849 100644 --- a/soc/arm/st_stm32/stm32l1/Kconfig.defconfig.stm32l152xe +++ b/soc/st/stm32/stm32l1x/Kconfig.defconfig.stm32l152xe @@ -5,10 +5,6 @@ if SOC_STM32L152XE -config SOC - string - default "stm32l152xe" - config NUM_IRQS int default 57 diff --git a/soc/st/stm32/stm32l1x/Kconfig.soc b/soc/st/stm32/stm32l1x/Kconfig.soc new file mode 100644 index 00000000000000..b0165c76991ae7 --- /dev/null +++ b/soc/st/stm32/stm32l1x/Kconfig.soc @@ -0,0 +1,38 @@ +# STMicroelectronics STM32L1 MCU line + +# Copyright (c) 2019 Linaro Ltd. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L1X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l1x" if SOC_SERIES_STM32L1X + +config SOC_STM32L151XB + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L151XBA + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L151XC + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L152XC + bool + select SOC_SERIES_STM32L1X + +config SOC_STM32L152XE + bool + select SOC_SERIES_STM32L1X + +config SOC + default "stm32l151xb" if SOC_STM32L151XB + default "stm32l151xba" if SOC_STM32L151XBA + default "stm32l151xc" if SOC_STM32L151XC + default "stm32l152xc" if SOC_STM32L152XC + default "stm32l152xe" if SOC_STM32L152XE diff --git a/soc/arm/st_stm32/stm32l1/soc.c b/soc/st/stm32/stm32l1x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l1/soc.c rename to soc/st/stm32/stm32l1x/soc.c diff --git a/soc/arm/st_stm32/stm32l1/soc.h b/soc/st/stm32/stm32l1x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l1/soc.h rename to soc/st/stm32/stm32l1x/soc.h diff --git a/soc/st/stm32/stm32l4x/CMakeLists.txt b/soc/st/stm32/stm32l4x/CMakeLists.txt new file mode 100644 index 00000000000000..2a910ba75121d3 --- /dev/null +++ b/soc/st/stm32/stm32l4x/CMakeLists.txt @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l4x/Kconfig b/soc/st/stm32/stm32l4x/Kconfig new file mode 100644 index 00000000000000..80bc62075c3fce --- /dev/null +++ b/soc/st/stm32/stm32l4x/Kconfig @@ -0,0 +1,16 @@ +# ST Microelectronics STM32L4 MCU series + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L4X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32l4x/Kconfig.defconfig b/soc/st/stm32/stm32l4x/Kconfig.defconfig new file mode 100644 index 00000000000000..3e4402b556edfa --- /dev/null +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32L4 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# SPDX-License-Identifier: Apache-2.0 + +# Kconfig symbols common to STM32L4 series + +if SOC_SERIES_STM32L4X + +rsource "Kconfig.defconfig.stm32l4*" + +endif # SOC_SERIES_STM32L4X diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l412xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l412xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l412xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l412xx index 2918e3d3dd2608..eb73f26dc4df67 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l412xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l412xx @@ -5,9 +5,6 @@ if SOC_STM32L412XX -config SOC - default "stm32l412xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l422xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l422xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l422xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l422xx index f6be07396bad9c..24143f8ede9445 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l422xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l422xx @@ -5,9 +5,6 @@ if SOC_STM32L422XX -config SOC - default "stm32l422xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l431xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l431xx similarity index 83% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l431xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l431xx index d21a2bd58f94ed..65b1136536859d 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l431xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l431xx @@ -5,9 +5,6 @@ if SOC_STM32L431XX -config SOC - default "stm32l431xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l432xx similarity index 86% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l432xx index d6ed27b7b44f37..b16bdfd5090bf9 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l432xx @@ -6,9 +6,6 @@ if SOC_STM32L432XX -config SOC - default "stm32l432xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l433xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l433xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l433xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l433xx index d10133eb1a8939..2cb0b3162a0ef8 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l433xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l433xx @@ -5,9 +5,6 @@ if SOC_STM32L433XX -config SOC - default "stm32l433xx" - config NUM_IRQS default 83 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l451xx similarity index 85% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l451xx index d3f5867a8dc123..36350d41b5e63c 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l451xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l451xx @@ -5,9 +5,6 @@ if SOC_STM32L451XX -config SOC - default "stm32l451xx" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l452xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l452xx index 0c6cc32f1f896d..c1564d0513d837 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l452xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l452xx @@ -5,9 +5,6 @@ if SOC_STM32L452XX -config SOC - default "stm32l452xx" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l462xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l462xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l462xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l462xx index 1c3575884b283e..57d136e67c55a0 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l462xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l462xx @@ -5,9 +5,6 @@ if SOC_STM32L462XX -config SOC - default "stm32l462xx" - config NUM_IRQS default 85 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l471xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l471xx index afb35990beebfe..22e8dd61d44fc1 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l471xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l471xx @@ -5,9 +5,6 @@ if SOC_STM32L471XX -config SOC - default "stm32l471xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l475xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l475xx index 25e11c3bcec364..0e3e1d231e6f58 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l475xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l475xx @@ -5,9 +5,6 @@ if SOC_STM32L475XX -config SOC - default "stm32l475xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l476xx similarity index 86% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l476xx index d2f70cd6c662d6..bd53c4066cc3ac 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l476xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l476xx @@ -6,9 +6,6 @@ if SOC_STM32L476XX -config SOC - default "stm32l476xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l486xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l486xx similarity index 88% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l486xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l486xx index 600948c5ffa477..4e5cbd8b5815aa 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l486xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l486xx @@ -7,9 +7,6 @@ if SOC_STM32L486XX -config SOC - default "stm32l486xx" - config NUM_IRQS default 82 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l496xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l496xx similarity index 88% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l496xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l496xx index 6d5dcb62bade26..d7100e5c9caa74 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l496xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l496xx @@ -7,9 +7,6 @@ if SOC_STM32L496XX -config SOC - default "stm32l496xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4a6xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4a6xx similarity index 89% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4a6xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4a6xx index 12a88ee608f3af..7cfcecfe204655 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4a6xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4a6xx @@ -8,9 +8,6 @@ if SOC_STM32L4A6XX -config SOC - default "stm32l4a6xx" - config NUM_IRQS default 91 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4p5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4p5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4p5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4p5xx index 605264f36a04e6..2c55c2d0113075 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4p5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4p5xx @@ -5,9 +5,6 @@ if SOC_STM32L4P5XX -config SOC - default "stm32l4p5xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4q5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4q5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4q5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4q5xx index 964cd4ad9ad2ab..779d194eb4c234 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4q5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4q5xx @@ -5,9 +5,6 @@ if SOC_STM32L4Q5XX -config SOC - default "stm32l4q5xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r5xx index 3a22131077408d..301004d3a84a09 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r5xx @@ -5,9 +5,6 @@ if SOC_STM32L4R5XX -config SOC - default "stm32l4r5xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r9xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r9xx index fd39575c550211..150a22332b7927 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4r9xx @@ -5,9 +5,6 @@ if SOC_STM32L4R9XX -config SOC - default "stm32l4r9xx" - config NUM_IRQS default 95 diff --git a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4s5xx b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4s5xx similarity index 84% rename from soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4s5xx rename to soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4s5xx index 79d97dbe08356f..85ab309e848bcc 100644 --- a/soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4s5xx +++ b/soc/st/stm32/stm32l4x/Kconfig.defconfig.stm32l4s5xx @@ -5,9 +5,6 @@ if SOC_STM32L4S5XX -config SOC - default "stm32l4s5xx" - config NUM_IRQS default 95 diff --git a/soc/st/stm32/stm32l4x/Kconfig.soc b/soc/st/stm32/stm32l4x/Kconfig.soc new file mode 100644 index 00000000000000..e48579d93b7b13 --- /dev/null +++ b/soc/st/stm32/stm32l4x/Kconfig.soc @@ -0,0 +1,111 @@ +# ST Microelectronics STM32L4 MCU line + +# Copyright (c) 2016 Open-RnD Sp. z o.o. +# Copyright (c) 2016 BayLibre, SAS +# Copyright (c) 2019 Centaur Analytics, Inc +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L4X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l4x" if SOC_SERIES_STM32L4X + +config SOC_STM32L412XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L422XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L431XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L432XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L433XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L451XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L452XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L462XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L471XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L475XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L476XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L486XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L496XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4A6XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4P5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4Q5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4S5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4R5XX + bool + select SOC_SERIES_STM32L4X + +config SOC_STM32L4R9XX + bool + select SOC_SERIES_STM32L4X + +config SOC + default "stm32l412xx" if SOC_STM32L412XX + default "stm32l422xx" if SOC_STM32L422XX + default "stm32l431xx" if SOC_STM32L431XX + default "stm32l432xx" if SOC_STM32L432XX + default "stm32l433xx" if SOC_STM32L433XX + default "stm32l451xx" if SOC_STM32L451XX + default "stm32l452xx" if SOC_STM32L452XX + default "stm32l462xx" if SOC_STM32L462XX + default "stm32l471xx" if SOC_STM32L471XX + default "stm32l475xx" if SOC_STM32L475XX + default "stm32l476xx" if SOC_STM32L476XX + default "stm32l486xx" if SOC_STM32L486XX + default "stm32l496xx" if SOC_STM32L496XX + default "stm32l4a6xx" if SOC_STM32L4A6XX + default "stm32l4p5xx" if SOC_STM32L4P5XX + default "stm32l4q5xx" if SOC_STM32L4Q5XX + default "stm32l4s5xx" if SOC_STM32L4S5XX + default "stm32l4r5xx" if SOC_STM32L4R5XX + default "stm32l4r9xx" if SOC_STM32L4R9XX diff --git a/soc/arm/st_stm32/stm32l4/power.c b/soc/st/stm32/stm32l4x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32l4/power.c rename to soc/st/stm32/stm32l4x/power.c diff --git a/soc/arm/st_stm32/stm32l4/poweroff.c b/soc/st/stm32/stm32l4x/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32l4/poweroff.c rename to soc/st/stm32/stm32l4x/poweroff.c diff --git a/soc/arm/st_stm32/stm32l4/soc.c b/soc/st/stm32/stm32l4x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l4/soc.c rename to soc/st/stm32/stm32l4x/soc.c diff --git a/soc/arm/st_stm32/stm32l4/soc.h b/soc/st/stm32/stm32l4x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l4/soc.h rename to soc/st/stm32/stm32l4x/soc.h diff --git a/soc/st/stm32/stm32l5x/CMakeLists.txt b/soc/st/stm32/stm32l5x/CMakeLists.txt new file mode 100644 index 00000000000000..bc9a65c0049227 --- /dev/null +++ b/soc/st/stm32/stm32l5x/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32l5x/Kconfig b/soc/st/stm32/stm32l5x/Kconfig new file mode 100644 index 00000000000000..ac7de0dfd7d557 --- /dev/null +++ b/soc/st/stm32/stm32l5x/Kconfig @@ -0,0 +1,16 @@ +# ST Microelectronics STM32L5 MCU series + +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L5X + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_PM diff --git a/soc/st/stm32/stm32l5x/Kconfig.defconfig b/soc/st/stm32/stm32l5x/Kconfig.defconfig new file mode 100644 index 00000000000000..2c8607c9b79ee9 --- /dev/null +++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32L5 MCU line + +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32L5X + +rsource "Kconfig.defconfig.stm32l5*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32L5X diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l552xx b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l552xx similarity index 84% rename from soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l552xx rename to soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l552xx index 7692fbd74510c5..29d2e2d8147607 100644 --- a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l552xx +++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l552xx @@ -5,9 +5,6 @@ if SOC_STM32L552XX -config SOC - default "stm32l552xx" - config NUM_IRQS default 108 diff --git a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l562xx b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l562xx similarity index 84% rename from soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l562xx rename to soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l562xx index 484880dc910e5b..5b1490c11c9588 100644 --- a/soc/arm/st_stm32/stm32l5/Kconfig.defconfig.stm32l562xx +++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig.stm32l562xx @@ -5,9 +5,6 @@ if SOC_STM32L562XX -config SOC - default "stm32l562xx" - config NUM_IRQS default 109 diff --git a/soc/st/stm32/stm32l5x/Kconfig.soc b/soc/st/stm32/stm32l5x/Kconfig.soc new file mode 100644 index 00000000000000..a2752f86bc12f1 --- /dev/null +++ b/soc/st/stm32/stm32l5x/Kconfig.soc @@ -0,0 +1,23 @@ +# ST Microelectronics STM32L5 MCU line + +# Copyright (c) 2020 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32L5X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32l5x" if SOC_SERIES_STM32L5X + +config SOC_STM32L552XX + bool + select SOC_SERIES_STM32L5X + +config SOC_STM32L562XX + bool + select SOC_SERIES_STM32L5X + +config SOC + default "stm32l552xx" if SOC_STM32L552XX + default "stm32l562xx" if SOC_STM32L562XX diff --git a/soc/arm/st_stm32/stm32l5/power.c b/soc/st/stm32/stm32l5x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32l5/power.c rename to soc/st/stm32/stm32l5x/power.c diff --git a/soc/arm/st_stm32/stm32l5/soc.c b/soc/st/stm32/stm32l5x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32l5/soc.c rename to soc/st/stm32/stm32l5x/soc.c diff --git a/soc/arm/st_stm32/stm32l5/soc.h b/soc/st/stm32/stm32l5x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32l5/soc.h rename to soc/st/stm32/stm32l5x/soc.h diff --git a/soc/st/stm32/stm32mp1x/CMakeLists.txt b/soc/st/stm32/stm32mp1x/CMakeLists.txt new file mode 100644 index 00000000000000..65004cceca8cf0 --- /dev/null +++ b/soc/st/stm32/stm32mp1x/CMakeLists.txt @@ -0,0 +1,12 @@ +# Copyright (c) 2019 STMicroelectronics +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32mp1x/Kconfig b/soc/st/stm32/stm32mp1x/Kconfig new file mode 100644 index 00000000000000..76e50a92e4a63d --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig @@ -0,0 +1,13 @@ +# STMicroelectronics STM32MP1 MPU series + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32MP1X + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select OPENAMP_RSC_TABLE if RAM_CONSOLE diff --git a/soc/st/stm32/stm32mp1x/Kconfig.defconfig b/soc/st/stm32/stm32mp1x/Kconfig.defconfig new file mode 100644 index 00000000000000..3a27f9118d9890 --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig.defconfig @@ -0,0 +1,10 @@ +# STMicroelectronics STM32MP1 MCU/MPU line + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32MP1X + +rsource "Kconfig.defconfig.stm32mp15_m4" + +endif # SOC_SERIES_STM32MP1X diff --git a/soc/st/stm32/stm32mp1x/Kconfig.defconfig.stm32mp15_m4 b/soc/st/stm32/stm32mp1x/Kconfig.defconfig.stm32mp15_m4 new file mode 100644 index 00000000000000..08a4e1bf0acbb7 --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig.defconfig.stm32mp15_m4 @@ -0,0 +1,11 @@ +# STMicroelectronics STM32MP157C_M4 MCU + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_STM32MP15_M4 + +config NUM_IRQS + default 150 + +endif # SOC_STM32MP15_M4 diff --git a/soc/st/stm32/stm32mp1x/Kconfig.soc b/soc/st/stm32/stm32mp1x/Kconfig.soc new file mode 100644 index 00000000000000..b67930b89dc402 --- /dev/null +++ b/soc/st/stm32/stm32mp1x/Kconfig.soc @@ -0,0 +1,18 @@ +# STMicroelectronics STM32MP1 MPU line + +# Copyright (c) 2019 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32MP1X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32mp1x" if SOC_SERIES_STM32MP1X + +config SOC_STM32MP15_M4 + bool + select SOC_SERIES_STM32MP1X + +config SOC + default "stm32mp157cxx" if SOC_STM32MP15_M4 diff --git a/soc/arm/st_stm32/stm32mp1/linker.ld b/soc/st/stm32/stm32mp1x/linker.ld similarity index 100% rename from soc/arm/st_stm32/stm32mp1/linker.ld rename to soc/st/stm32/stm32mp1x/linker.ld diff --git a/soc/arm/st_stm32/stm32mp1/soc.c b/soc/st/stm32/stm32mp1x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32mp1/soc.c rename to soc/st/stm32/stm32mp1x/soc.c diff --git a/soc/arm/st_stm32/stm32mp1/soc.h b/soc/st/stm32/stm32mp1x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32mp1/soc.h rename to soc/st/stm32/stm32mp1x/soc.h diff --git a/soc/st/stm32/stm32u5x/CMakeLists.txt b/soc/st/stm32/stm32u5x/CMakeLists.txt new file mode 100644 index 00000000000000..f737c62ce24d78 --- /dev/null +++ b/soc/st/stm32/stm32u5x/CMakeLists.txt @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM power.c) +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32u5x/Kconfig b/soc/st/stm32/stm32u5x/Kconfig new file mode 100644 index 00000000000000..a2e4145abc3fe2 --- /dev/null +++ b/soc/st/stm32/stm32u5x/Kconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32U5 MCU series + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32U5X + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32u5x/Kconfig.defconfig b/soc/st/stm32/stm32u5x/Kconfig.defconfig new file mode 100644 index 00000000000000..354cc6cd0abb00 --- /dev/null +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32U5 MCU line + +# Copyright (c) 2021 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32U5X + +rsource "Kconfig.defconfig.stm32u5*" + +config ROM_START_OFFSET + default 0x400 if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_STM32U5X diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u575xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u575xx index 47c61114b7a09d..7c2ed2282c25b3 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u575xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u575xx @@ -5,9 +5,6 @@ if SOC_STM32U575XX -config SOC - default "stm32u575xx" - config NUM_IRQS default 125 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u585xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u585xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u585xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u585xx index d1ac8788b7a16a..117dc3fe4817b6 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u585xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u585xx @@ -5,9 +5,6 @@ if SOC_STM32U585XX -config SOC - default "stm32u585xx" - config NUM_IRQS default 125 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u595xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u595xx index d0bd4f9945022d..05f932ea7b7f45 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u595xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u595xx @@ -5,9 +5,6 @@ if SOC_STM32U595XX -config SOC - default "stm32u595xx" - config NUM_IRQS default 132 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u599xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u599xx index df30e49fd020ec..01aa1f4663aeaf 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u599xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u599xx @@ -5,9 +5,6 @@ if SOC_STM32U599XX -config SOC - default "stm32u599xx" - config NUM_IRQS default 139 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a5xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a5xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a5xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a5xx index 1759406a580fda..f8812b1fa40677 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a5xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a5xx @@ -5,9 +5,6 @@ if SOC_STM32U5A5XX -config SOC - default "stm32u5a5xx" - config NUM_IRQS default 139 diff --git a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a9xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a9xx similarity index 84% rename from soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a9xx rename to soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a9xx index 0553382acb1e06..5e77b7b8c04e91 100644 --- a/soc/arm/st_stm32/stm32u5/Kconfig.defconfig.stm32u5a9xx +++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5a9xx @@ -5,9 +5,6 @@ if SOC_STM32U5A9XX -config SOC - default "stm32u5a9xx" - config NUM_IRQS default 139 diff --git a/soc/st/stm32/stm32u5x/Kconfig.soc b/soc/st/stm32/stm32u5x/Kconfig.soc new file mode 100644 index 00000000000000..59324d5619355d --- /dev/null +++ b/soc/st/stm32/stm32u5x/Kconfig.soc @@ -0,0 +1,45 @@ +# ST Microelectronics STM32U5 MCU line + +# Copyright (c) 2021 Linaro Limited +# Copyright (c) 2023 PSICONTROL nv +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32U5X + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32u5x" if SOC_SERIES_STM32U5X + +config SOC_STM32U575XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U585XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U595XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U599XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U5A5XX + bool + select SOC_SERIES_STM32U5X + +config SOC_STM32U5A9XX + bool + select SOC_SERIES_STM32U5X + +config SOC + default "stm32u5a5xx" if SOC_STM32U5A5XX + default "stm32u5a9xx" if SOC_STM32U5A9XX + default "stm32u575xx" if SOC_STM32U575XX + default "stm32u585xx" if SOC_STM32U585XX + default "stm32u595xx" if SOC_STM32U595XX + default "stm32u599xx" if SOC_STM32U599XX diff --git a/soc/arm/st_stm32/stm32u5/power.c b/soc/st/stm32/stm32u5x/power.c similarity index 100% rename from soc/arm/st_stm32/stm32u5/power.c rename to soc/st/stm32/stm32u5x/power.c diff --git a/soc/arm/st_stm32/stm32u5/poweroff.c b/soc/st/stm32/stm32u5x/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32u5/poweroff.c rename to soc/st/stm32/stm32u5x/poweroff.c diff --git a/soc/arm/st_stm32/stm32u5/soc.c b/soc/st/stm32/stm32u5x/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32u5/soc.c rename to soc/st/stm32/stm32u5x/soc.c diff --git a/soc/arm/st_stm32/stm32u5/soc.h b/soc/st/stm32/stm32u5x/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32u5/soc.h rename to soc/st/stm32/stm32u5x/soc.h diff --git a/soc/st/stm32/stm32wbax/CMakeLists.txt b/soc/st/stm32/stm32wbax/CMakeLists.txt new file mode 100644 index 00000000000000..0c9707564428c3 --- /dev/null +++ b/soc/st/stm32/stm32wbax/CMakeLists.txt @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +if(CONFIG_BT_STM32WBA) + zephyr_include_directories(hci_if) + + zephyr_sources(hci_if/linklayer_plat.c) + zephyr_sources(hci_if/bleplat.c) + zephyr_sources(hci_if/host_stack_if.c) + zephyr_sources(hci_if/ll_sys_if.c) + zephyr_sources(hci_if/stm32_timer.c) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32wbax/Kconfig b/soc/st/stm32/stm32wbax/Kconfig new file mode 100644 index 00000000000000..2f737ebb4b9f61 --- /dev/null +++ b/soc/st/stm32/stm32wbax/Kconfig @@ -0,0 +1,17 @@ +# ST Microelectronics STM32WBA MCU series + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBAX + select ARM + select CPU_CORTEX_M33 + select ARM_TRUSTZONE_M + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select USE_STM32_HAL_PWR_EX + select HAS_PM diff --git a/soc/st/stm32/stm32wbax/Kconfig.defconfig b/soc/st/stm32/stm32wbax/Kconfig.defconfig new file mode 100644 index 00000000000000..8a7e2c0ab047a4 --- /dev/null +++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig @@ -0,0 +1,61 @@ +# ST Microelectronics STM32WBA MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32WBAX + +rsource "Kconfig.defconfig.stm32wba*" + +config STM32_LPTIM_TIMER + default y if PM + +choice BT_HCI_BUS_TYPE + default BT_STM32WBA + depends on BT +endchoice + +config BT_STM32WBA + select DYNAMIC_INTERRUPTS + select DYNAMIC_DIRECT_INTERRUPTS + select ENTROPY_GENERATOR + select USE_STM32_HAL_RAMCFG + +if BT_STM32WBA + +choice LIBC_IMPLEMENTATION + default NEWLIB_LIBC +endchoice + +choice LINKER_ORPHAN_CONFIGURATION + default LINKER_ORPHAN_SECTION_PLACE +endchoice + +config ENTROPY_STM32_CLK_CHECK + default n + +endif + +if PM_S2RAM + +config COUNTER + default y + +config COUNTER_RTC_STM32_SUBSECONDS + default y + +config STM32_LPTIM_STDBY_TIMER + default y + +config TICKLESS_KERNEL + default y + +config COUNTER_RTC_STM32_SAVE_VALUE_BETWEEN_RESETS + default y + +config IDLE_STACK_SIZE + default 512 + +endif + +endif # SOC_SERIES_STM32WBAX diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba52xx b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba52xx similarity index 84% rename from soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba52xx rename to soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba52xx index b9d54cdfc72796..d48a67710b836a 100644 --- a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba52xx +++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba52xx @@ -5,9 +5,6 @@ if SOC_STM32WBA52XX -config SOC - default "stm32wba52xx" - config NUM_IRQS default 70 diff --git a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba55xx b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba55xx similarity index 84% rename from soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba55xx rename to soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba55xx index ca745f874711c8..ce80f32291bff6 100644 --- a/soc/arm/st_stm32/stm32wba/Kconfig.defconfig.stm32wba55xx +++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba55xx @@ -5,9 +5,6 @@ if SOC_STM32WBA55XX -config SOC - default "stm32wba55xx" - config NUM_IRQS default 70 diff --git a/soc/st/stm32/stm32wbax/Kconfig.soc b/soc/st/stm32/stm32wbax/Kconfig.soc new file mode 100644 index 00000000000000..104a3923989bd4 --- /dev/null +++ b/soc/st/stm32/stm32wbax/Kconfig.soc @@ -0,0 +1,23 @@ +# ST Microelectronics STM32WBA MCU line + +# Copyright (c) 2023 STMicroelectronics +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBAX + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32wbax" if SOC_SERIES_STM32WBAX + +config SOC_STM32WBA52XX + bool + select SOC_SERIES_STM32WBAX + +config SOC_STM32WBA55XX + bool + select SOC_SERIES_STM32WBAX + +config SOC + default "stm32wba52xx" if SOC_STM32WBA52XX + default "stm32wba55xx" if SOC_STM32WBA55XX diff --git a/soc/arm/st_stm32/stm32wba/hci_if/bleplat.c b/soc/st/stm32/stm32wbax/hci_if/bleplat.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/bleplat.c rename to soc/st/stm32/stm32wbax/hci_if/bleplat.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/host_stack_if.c b/soc/st/stm32/stm32wbax/hci_if/host_stack_if.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/host_stack_if.c rename to soc/st/stm32/stm32wbax/hci_if/host_stack_if.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat.c b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat.c rename to soc/st/stm32/stm32wbax/hci_if/linklayer_plat.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat_local.h b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_local.h similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/linklayer_plat_local.h rename to soc/st/stm32/stm32wbax/hci_if/linklayer_plat_local.h diff --git a/soc/arm/st_stm32/stm32wba/hci_if/ll_sys_if.c b/soc/st/stm32/stm32wbax/hci_if/ll_sys_if.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/ll_sys_if.c rename to soc/st/stm32/stm32wbax/hci_if/ll_sys_if.c diff --git a/soc/arm/st_stm32/stm32wba/hci_if/stm32_timer.c b/soc/st/stm32/stm32wbax/hci_if/stm32_timer.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/hci_if/stm32_timer.c rename to soc/st/stm32/stm32wbax/hci_if/stm32_timer.c diff --git a/soc/arm/st_stm32/stm32wba/power.c b/soc/st/stm32/stm32wbax/power.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/power.c rename to soc/st/stm32/stm32wbax/power.c diff --git a/soc/arm/st_stm32/stm32wba/soc.c b/soc/st/stm32/stm32wbax/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32wba/soc.c rename to soc/st/stm32/stm32wbax/soc.c diff --git a/soc/arm/st_stm32/stm32wba/soc.h b/soc/st/stm32/stm32wbax/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32wba/soc.h rename to soc/st/stm32/stm32wbax/soc.h diff --git a/soc/st/stm32/stm32wbx/CMakeLists.txt b/soc/st/stm32/stm32wbx/CMakeLists.txt new file mode 100644 index 00000000000000..6806b1fa772468 --- /dev/null +++ b/soc/st/stm32/stm32wbx/CMakeLists.txt @@ -0,0 +1,19 @@ +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources( + soc.c + ) + +zephyr_linker_sources_ifdef(CONFIG_BT_STM32_IPM + SECTIONS + ipm.ld + ) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32wbx/Kconfig b/soc/st/stm32/stm32wbx/Kconfig new file mode 100644 index 00000000000000..65aadce28082f6 --- /dev/null +++ b/soc/st/stm32/stm32wbx/Kconfig @@ -0,0 +1,15 @@ +# ST Microelectronics STM32WB MCU series + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select HAS_SWO + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32wbx/Kconfig.defconfig b/soc/st/stm32/stm32wbx/Kconfig.defconfig new file mode 100644 index 00000000000000..948e9cc0f2c6a3 --- /dev/null +++ b/soc/st/stm32/stm32wbx/Kconfig.defconfig @@ -0,0 +1,13 @@ +# ST Microelectronics STM32WB MCU line + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32WBX + +rsource "Kconfig.defconfig.stm32wb*" + +config BT_USER_PHY_UPDATE + default y if BT + +endif # SOC_SERIES_STM32WBX diff --git a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx b/soc/st/stm32/stm32wbx/Kconfig.defconfig.stm32wb55xx similarity index 84% rename from soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx rename to soc/st/stm32/stm32wbx/Kconfig.defconfig.stm32wb55xx index 175518e3ff132b..c7659b460ffb36 100644 --- a/soc/arm/st_stm32/stm32wb/Kconfig.defconfig.stm32wb55xx +++ b/soc/st/stm32/stm32wbx/Kconfig.defconfig.stm32wb55xx @@ -5,9 +5,6 @@ if SOC_STM32WB55XX -config SOC - default "stm32wb55xx" - config NUM_IRQS default 63 diff --git a/soc/st/stm32/stm32wbx/Kconfig.soc b/soc/st/stm32/stm32wbx/Kconfig.soc new file mode 100644 index 00000000000000..0ba89943c8d45c --- /dev/null +++ b/soc/st/stm32/stm32wbx/Kconfig.soc @@ -0,0 +1,18 @@ +# ST Microelectronics STM32WB MCU line + +# Copyright (c) 2019 Linaro Limited +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WBX + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32wbx" if SOC_SERIES_STM32WBX + +config SOC_STM32WB55XX + bool + select SOC_SERIES_STM32WBX + +config SOC + default "stm32wb55xx" if SOC_STM32WB55XX diff --git a/soc/arm/st_stm32/stm32wb/ipm.ld b/soc/st/stm32/stm32wbx/ipm.ld similarity index 100% rename from soc/arm/st_stm32/stm32wb/ipm.ld rename to soc/st/stm32/stm32wbx/ipm.ld diff --git a/soc/arm/st_stm32/stm32wb/power.c b/soc/st/stm32/stm32wbx/power.c similarity index 100% rename from soc/arm/st_stm32/stm32wb/power.c rename to soc/st/stm32/stm32wbx/power.c diff --git a/soc/arm/st_stm32/stm32wb/poweroff.c b/soc/st/stm32/stm32wbx/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32wb/poweroff.c rename to soc/st/stm32/stm32wbx/poweroff.c diff --git a/soc/arm/st_stm32/stm32wb/soc.c b/soc/st/stm32/stm32wbx/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32wb/soc.c rename to soc/st/stm32/stm32wbx/soc.c diff --git a/soc/arm/st_stm32/stm32wb/soc.h b/soc/st/stm32/stm32wbx/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32wb/soc.h rename to soc/st/stm32/stm32wbx/soc.h diff --git a/soc/st/stm32/stm32wlx/CMakeLists.txt b/soc/st/stm32/stm32wlx/CMakeLists.txt new file mode 100644 index 00000000000000..54069f6b599879 --- /dev/null +++ b/soc/st/stm32/stm32wlx/CMakeLists.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_sources(soc.c) + +zephyr_sources_ifdef(CONFIG_PM + power.c + ) + +zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/st/stm32/stm32wlx/Kconfig b/soc/st/stm32/stm32wlx/Kconfig new file mode 100644 index 00000000000000..a4983fdad0a053 --- /dev/null +++ b/soc/st/stm32/stm32wlx/Kconfig @@ -0,0 +1,14 @@ +# STMicroelectronics STM32WL MCU series + +# Copyright (c) 2020 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WLX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select HAS_STM32CUBE + select CPU_HAS_ARM_MPU + select CLOCK_CONTROL_STM32_CUBE if CLOCK_CONTROL + select HAS_PM + select HAS_POWEROFF diff --git a/soc/st/stm32/stm32wlx/Kconfig.defconfig b/soc/st/stm32/stm32wlx/Kconfig.defconfig new file mode 100644 index 00000000000000..277a9046c73f07 --- /dev/null +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig @@ -0,0 +1,10 @@ +# STMicroelectronics STM32WL MCU line + +# Copyright (c) 2020 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STM32WLX + +rsource "Kconfig.defconfig.stm32wl*" + +endif # SOC_SERIES_STM32WLX diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl54xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl54xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl54xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl54xx index d692e02e28cbf4..876c15437b5f5e 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl54xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl54xx @@ -5,9 +5,6 @@ if SOC_STM32WL54XX -config SOC - default "stm32wl54xx" - config NUM_IRQS default 62 diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl55xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl55xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl55xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl55xx index 1358c9d0487100..247c174e020a65 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wl55xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wl55xx @@ -5,9 +5,6 @@ if SOC_STM32WL55XX -config SOC - default "stm32wl55xx" - config NUM_IRQS default 62 diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle4xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle4xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle4xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle4xx index cbdfe62f9a3305..0ebb75b9155e0b 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle4xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle4xx @@ -5,9 +5,6 @@ if SOC_STM32WLE4XX -config SOC - default "stm32wle4xx" - config NUM_IRQS default 62 diff --git a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle5xx b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle5xx similarity index 84% rename from soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle5xx rename to soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle5xx index 14f16697216582..97682fdc65c7fc 100644 --- a/soc/arm/st_stm32/stm32wl/Kconfig.defconfig.stm32wle5xx +++ b/soc/st/stm32/stm32wlx/Kconfig.defconfig.stm32wle5xx @@ -5,9 +5,6 @@ if SOC_STM32WLE5XX -config SOC - default "stm32wle5xx" - config NUM_IRQS default 62 diff --git a/soc/st/stm32/stm32wlx/Kconfig.soc b/soc/st/stm32/stm32wlx/Kconfig.soc new file mode 100644 index 00000000000000..4b130d029be262 --- /dev/null +++ b/soc/st/stm32/stm32wlx/Kconfig.soc @@ -0,0 +1,33 @@ +# STMicroelectronics STM32WL MCU line + +# Copyright (c) 2020 STMicroelectronics. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STM32WLX + bool + select SOC_FAMILY_STM32 + +config SOC_SERIES + default "stm32wlx" if SOC_SERIES_STM32WLX + +config SOC_STM32WLE4XX + bool + select SOC_SERIES_STM32WLX + +config SOC_STM32WLE5XX + bool + select SOC_SERIES_STM32WLX + +config SOC_STM32WL54XX + bool + select SOC_SERIES_STM32WLX + +config SOC_STM32WL55XX + bool + select SOC_SERIES_STM32WLX + +config SOC + default "stm32wle4xx" if SOC_STM32WLE4XX + default "stm32wle5xx" if SOC_STM32WLE5XX + default "stm32wl54xx" if SOC_STM32WL54XX + default "stm32wl55xx" if SOC_STM32WL55XX diff --git a/soc/arm/st_stm32/stm32wl/power.c b/soc/st/stm32/stm32wlx/power.c similarity index 100% rename from soc/arm/st_stm32/stm32wl/power.c rename to soc/st/stm32/stm32wlx/power.c diff --git a/soc/arm/st_stm32/stm32wl/poweroff.c b/soc/st/stm32/stm32wlx/poweroff.c similarity index 100% rename from soc/arm/st_stm32/stm32wl/poweroff.c rename to soc/st/stm32/stm32wlx/poweroff.c diff --git a/soc/arm/st_stm32/stm32wl/soc.c b/soc/st/stm32/stm32wlx/soc.c similarity index 100% rename from soc/arm/st_stm32/stm32wl/soc.c rename to soc/st/stm32/stm32wlx/soc.c diff --git a/soc/arm/st_stm32/stm32wl/soc.h b/soc/st/stm32/stm32wlx/soc.h similarity index 100% rename from soc/arm/st_stm32/stm32wl/soc.h rename to soc/st/stm32/stm32wlx/soc.h diff --git a/soc/riscv/starfive_jh71xx/jh71xx/CMakeLists.txt b/soc/starfive/jh71xx/CMakeLists.txt similarity index 100% rename from soc/riscv/starfive_jh71xx/jh71xx/CMakeLists.txt rename to soc/starfive/jh71xx/CMakeLists.txt diff --git a/soc/starfive/jh71xx/Kconfig b/soc/starfive/jh71xx/Kconfig new file mode 100644 index 00000000000000..91ef208f9c1b7b --- /dev/null +++ b/soc/starfive/jh71xx/Kconfig @@ -0,0 +1,17 @@ +# Copyright (c) 2021 Rajnesh Kanwal +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STARFIVE_JH71XX + select RISCV + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + +config SOC_JH7100 + select ATOMIC_OPERATIONS_BUILTIN + select INCLUDE_RESET_VECTOR + select RISCV_ISA_RV64I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI diff --git a/soc/starfive/jh71xx/Kconfig.defconfig b/soc/starfive/jh71xx/Kconfig.defconfig new file mode 100644 index 00000000000000..c20bde5ee5880c --- /dev/null +++ b/soc/starfive/jh71xx/Kconfig.defconfig @@ -0,0 +1,24 @@ +# Copyright (c) 2021 Rajnesh Kanwal +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_STARFIVE_JH71XX + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 6250000 + +config RISCV_SOC_INTERRUPT_INIT + default y + +config RISCV_GP + default y + +config 2ND_LVL_ISR_TBL_OFFSET + default 12 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config NUM_IRQS + default 139 + +endif diff --git a/soc/starfive/jh71xx/Kconfig.soc b/soc/starfive/jh71xx/Kconfig.soc new file mode 100644 index 00000000000000..48d6d506cc9884 --- /dev/null +++ b/soc/starfive/jh71xx/Kconfig.soc @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_STARFIVE_JH71XX + bool + help + Starfive JH71XX series + +config SOC_JH7100 + bool + select SOC_SERIES_STARFIVE_JH71XX + help + Starfive JH7100 + +config SOC_SERIES + default "starfive_jh71xx" if SOC_SERIES_STARFIVE_JH71XX + +config SOC + default "jh7100" if SOC_JH7100 diff --git a/soc/starfive/jh71xx/soc.yml b/soc/starfive/jh71xx/soc.yml new file mode 100644 index 00000000000000..1d424c2f5407e8 --- /dev/null +++ b/soc/starfive/jh71xx/soc.yml @@ -0,0 +1,4 @@ +series: +- name: starfive_jh71xx + socs: + - name: jh7100 diff --git a/soc/arc/snps_arc_iot/CMakeLists.txt b/soc/synopsys/arc_iot/CMakeLists.txt similarity index 100% rename from soc/arc/snps_arc_iot/CMakeLists.txt rename to soc/synopsys/arc_iot/CMakeLists.txt diff --git a/soc/synopsys/arc_iot/Kconfig b/soc/synopsys/arc_iot/Kconfig new file mode 100644 index 00000000000000..362d2d1ae716ad --- /dev/null +++ b/soc/synopsys/arc_iot/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_IOT + select ARC + select CPU_HAS_MPU + select CPU_HAS_FPU diff --git a/soc/synopsys/arc_iot/Kconfig.defconfig b/soc/synopsys/arc_iot/Kconfig.defconfig new file mode 100644 index 00000000000000..9c64732bf1fd87 --- /dev/null +++ b/soc/synopsys/arc_iot/Kconfig.defconfig @@ -0,0 +1,34 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_IOT + +config CPU_EM4_FPUS + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 4 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). + default 4 + +config ARC_MPU_VER + default 2 + +config NUM_IRQS + # must be > the highest interrupt number used + default 95 + +config RGF_NUM_BANKS + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 144000000 + +config HARVARD + default y + +config ARC_FIRQ + default y + +endif # ARC_IOT diff --git a/soc/synopsys/arc_iot/Kconfig.soc b/soc/synopsys/arc_iot/Kconfig.soc new file mode 100644 index 00000000000000..d7e5a54079f265 --- /dev/null +++ b/soc/synopsys/arc_iot/Kconfig.soc @@ -0,0 +1,11 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_IOT + bool + help + Synopsys ARC IoT SoC + +config SOC + default "arc_iot" if SOC_ARC_IOT diff --git a/soc/arc/snps_arc_iot/linker.ld b/soc/synopsys/arc_iot/linker.ld similarity index 100% rename from soc/arc/snps_arc_iot/linker.ld rename to soc/synopsys/arc_iot/linker.ld diff --git a/soc/arc/snps_arc_iot/soc.c b/soc/synopsys/arc_iot/soc.c similarity index 100% rename from soc/arc/snps_arc_iot/soc.c rename to soc/synopsys/arc_iot/soc.c diff --git a/soc/synopsys/arc_iot/soc.yml b/soc/synopsys/arc_iot/soc.yml new file mode 100644 index 00000000000000..9ee993439e69ad --- /dev/null +++ b/soc/synopsys/arc_iot/soc.yml @@ -0,0 +1,4 @@ +series: +- name: arc_iot + socs: + - name: arc_iot diff --git a/soc/arc/snps_arc_iot/sysconf.c b/soc/synopsys/arc_iot/sysconf.c similarity index 100% rename from soc/arc/snps_arc_iot/sysconf.c rename to soc/synopsys/arc_iot/sysconf.c diff --git a/soc/arc/snps_arc_iot/sysconf.h b/soc/synopsys/arc_iot/sysconf.h similarity index 100% rename from soc/arc/snps_arc_iot/sysconf.h rename to soc/synopsys/arc_iot/sysconf.h diff --git a/soc/synopsys/emsdp/CMakeLists.txt b/soc/synopsys/emsdp/CMakeLists.txt new file mode 100644 index 00000000000000..ce71339f63759d --- /dev/null +++ b/soc/synopsys/emsdp/CMakeLists.txt @@ -0,0 +1,24 @@ +# SPDX-License-Identifier: Apache-2.0 +zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata) + +if(CONFIG_SOC_EMSDP_EM4) + zephyr_compile_options(-mmpy-option=3 -mno-div-rem) +elseif(CONFIG_SOC_EMSDP_EM6) + zephyr_compile_options(-mmpy-option=3 -mno-div-rem) +elseif(CONFIG_SOC_EMSDP_EM5D) + zephyr_compile_options(-mmpy-option=6) +elseif(CONFIG_SOC_EMSDP_EM7D) + zephyr_compile_options(-mmpy-option=6) +elseif(CONFIG_SOC_EMSDP_EM7D_ESP) + zephyr_compile_options(-mmpy-option=6) +elseif(CONFIG_SOC_EMSDP_EM9D) + zephyr_compile_options(-mmpy-option=6) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) +elseif(CONFIG_SOC_EMSDP_EM11D) + zephyr_compile_options(-mmpy-option=6) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/emsdp/Kconfig b/soc/synopsys/emsdp/Kconfig new file mode 100644 index 00000000000000..424620ed6fc5a9 --- /dev/null +++ b/soc/synopsys/emsdp/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_EMSDP + select ARC + +config SOC_EMSDP_EM4 + select CPU_HAS_MPU + +config SOC_EMSDP_EM5D + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_EMSDP_EM6 + select CPU_HAS_MPU + +config SOC_EMSDP_EM7D + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_EMSDP_EM7D_ESP + select CPU_HAS_MPU + select CPU_HAS_FPU + select ARC_HAS_SECURE + +config SOC_EMSDP_EM9D + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_EMSDP_EM11D + select CPU_HAS_MPU + select CPU_HAS_FPU diff --git a/soc/synopsys/emsdp/Kconfig.defconfig b/soc/synopsys/emsdp/Kconfig.defconfig new file mode 100644 index 00000000000000..7807c53c9311c5 --- /dev/null +++ b/soc/synopsys/emsdp/Kconfig.defconfig @@ -0,0 +1,13 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_EMSDP + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 4 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). + default 4 + +rsource "Kconfig.defconfig.*" + +endif # SOC_ARC_EMSDP diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em11d b/soc/synopsys/emsdp/Kconfig.defconfig.em11d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em11d rename to soc/synopsys/emsdp/Kconfig.defconfig.em11d diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em4 b/soc/synopsys/emsdp/Kconfig.defconfig.em4 similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em4 rename to soc/synopsys/emsdp/Kconfig.defconfig.em4 diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em5d b/soc/synopsys/emsdp/Kconfig.defconfig.em5d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em5d rename to soc/synopsys/emsdp/Kconfig.defconfig.em5d diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em6 b/soc/synopsys/emsdp/Kconfig.defconfig.em6 similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em6 rename to soc/synopsys/emsdp/Kconfig.defconfig.em6 diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em7d b/soc/synopsys/emsdp/Kconfig.defconfig.em7d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em7d rename to soc/synopsys/emsdp/Kconfig.defconfig.em7d diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em7d_esp b/soc/synopsys/emsdp/Kconfig.defconfig.em7d_esp similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em7d_esp rename to soc/synopsys/emsdp/Kconfig.defconfig.em7d_esp diff --git a/soc/arc/snps_emsdp/Kconfig.defconfig.em9d b/soc/synopsys/emsdp/Kconfig.defconfig.em9d similarity index 100% rename from soc/arc/snps_emsdp/Kconfig.defconfig.em9d rename to soc/synopsys/emsdp/Kconfig.defconfig.em9d diff --git a/soc/synopsys/emsdp/Kconfig.soc b/soc/synopsys/emsdp/Kconfig.soc new file mode 100644 index 00000000000000..faa62ee05e7196 --- /dev/null +++ b/soc/synopsys/emsdp/Kconfig.soc @@ -0,0 +1,59 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_EMSDP + bool + +config SOC_EMSDP_EM4 + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM4 of EMSDP + +config SOC_EMSDP_EM5D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM5D of EMSDP + +config SOC_EMSDP_EM6 + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM6 of EMSDP + +config SOC_EMSDP_EM7D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM7D of EMSDP + +config SOC_EMSDP_EM7D_ESP + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM7D+ESP of EMSDP + +config SOC_EMSDP_EM9D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM9D of EMSDP + +config SOC_EMSDP_EM11D + bool + select SOC_ARC_EMSDP + help + Synopsys ARC EM11D of EMSDP + +config SOC_SERIES + default "emsdp" if SOC_ARC_EMSDP + +config SOC + default "emsdp_em4" if SOC_EMSDP_EM4 + default "emsdp_em5d" if SOC_EMSDP_EM5D + default "emsdp_em6" if SOC_EMSDP_EM6 + default "emsdp_em7d" if SOC_EMSDP_EM7D + default "emsdp_em7d_esp" if SOC_EMSDP_EM7D_ESP + default "emsdp_em9d" if SOC_EMSDP_EM9D + default "emsdp_em11d" if SOC_EMSDP_EM11D diff --git a/soc/arc/snps_emsdp/linker.ld b/soc/synopsys/emsdp/linker.ld similarity index 100% rename from soc/arc/snps_emsdp/linker.ld rename to soc/synopsys/emsdp/linker.ld diff --git a/soc/arc/snps_emsdp/pinctrl_soc.h b/soc/synopsys/emsdp/pinctrl_soc.h similarity index 100% rename from soc/arc/snps_emsdp/pinctrl_soc.h rename to soc/synopsys/emsdp/pinctrl_soc.h diff --git a/soc/synopsys/emsdp/soc.yml b/soc/synopsys/emsdp/soc.yml new file mode 100644 index 00000000000000..c308d85d0f0101 --- /dev/null +++ b/soc/synopsys/emsdp/soc.yml @@ -0,0 +1,10 @@ +series: +- name: emsdp + socs: + - name: emsdp_em4 + - name: emsdp_em5d + - name: emsdp_em6 + - name: emsdp_em7d + - name: emsdp_em7d_esp + - name: emsdp_em9d + - name: emsdp_em11d diff --git a/soc/synopsys/emsk/CMakeLists.txt b/soc/synopsys/emsk/CMakeLists.txt new file mode 100644 index 00000000000000..ea14ab053c8a69 --- /dev/null +++ b/soc/synopsys/emsk/CMakeLists.txt @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 +zephyr_compile_options(-mcpu=${GCC_M_CPU} -mno-sdata -mmpy-option=6) + +if(CONFIG_SOC_EMSK_EM9D) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpus_all) +elseif(CONFIG_SOC_EMSK_EM11D) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpuda_all) +endif() + +zephyr_sources(soc_config.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/emsk/Kconfig b/soc/synopsys/emsk/Kconfig new file mode 100644 index 00000000000000..88cdfe70671169 --- /dev/null +++ b/soc/synopsys/emsk/Kconfig @@ -0,0 +1,15 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EMSK + select ARC + +config SOC_EMSK_EM7D + select CPU_HAS_MPU + +config SOC_EMSK_EM9D + select CPU_HAS_FPU + +config SOC_EMSK_EM11D + select CPU_HAS_FPU diff --git a/soc/synopsys/emsk/Kconfig.defconfig b/soc/synopsys/emsk/Kconfig.defconfig new file mode 100644 index 00000000000000..e7f231ebcf2f9e --- /dev/null +++ b/soc/synopsys/emsk/Kconfig.defconfig @@ -0,0 +1,9 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EMSK + +rsource "Kconfig.defconfig.*" + +endif # SOC_EMSK diff --git a/soc/arc/snps_emsk/Kconfig.defconfig.em11d b/soc/synopsys/emsk/Kconfig.defconfig.em11d similarity index 87% rename from soc/arc/snps_emsk/Kconfig.defconfig.em11d rename to soc/synopsys/emsk/Kconfig.defconfig.em11d index ad965710b51bfc..4c0854682fd472 100644 --- a/soc/arc/snps_emsk/Kconfig.defconfig.em11d +++ b/soc/synopsys/emsk/Kconfig.defconfig.em11d @@ -14,8 +14,8 @@ config NUM_IRQ_PRIO_LEVELS config NUM_IRQS # must be > the highest interrupt number used - default 38 if BOARD_EM_STARTERKIT_R23 - default 36 if BOARD_EM_STARTERKIT_R22 + default 38 if "$(BOARD_REVISION)" = "2.3" + default 36 if "$(BOARD_REVISION)" = "2.2" config RGF_NUM_BANKS default 2 diff --git a/soc/synopsys/emsk/Kconfig.defconfig.em7d b/soc/synopsys/emsk/Kconfig.defconfig.em7d new file mode 100644 index 00000000000000..3decdef43cb3ea --- /dev/null +++ b/soc/synopsys/emsk/Kconfig.defconfig.em7d @@ -0,0 +1,55 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_EMSK_EM7D + +config CPU_EM4_DMIPS + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 4 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs). + default 4 + +config NUM_IRQS + # must be > the highest interrupt number used + default 38 if "$(BOARD_REVISION)" = "2.3" + default 36 if "$(BOARD_REVISION)" = "2.2" + +config ARC_MPU_VER + default 4 if "$(BOARD_REVISION)" = "2.3" + default 2 if "$(BOARD_REVISION)" = "2.2" + +config RGF_NUM_BANKS + default 1 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 25000000 if "$(BOARD_REVISION)" = "2.3" + default 30000000 if "$(BOARD_REVISION)" = "2.2" + +config HARVARD + default y + +config ARC_FIRQ + default n if "$(BOARD_REVISION)" = "2.3" + default y if "$(BOARD_REVISION)" = "2.2" + +config CACHE_MANAGEMENT + default y + +if (ARC_MPU_VER = 2) + +config MAIN_STACK_SIZE + default 2048 + +config IDLE_STACK_SIZE + default 2048 + +config ZTEST_STACK_SIZE + default 2048 + depends on ZTEST + +endif # ARC_MPU_VER + +endif # SOC_EMSK_EM7D diff --git a/soc/arc/snps_emsk/Kconfig.defconfig.em9d b/soc/synopsys/emsk/Kconfig.defconfig.em9d similarity index 86% rename from soc/arc/snps_emsk/Kconfig.defconfig.em9d rename to soc/synopsys/emsk/Kconfig.defconfig.em9d index 00114baac3e97d..cebfde7d74d73e 100644 --- a/soc/arc/snps_emsk/Kconfig.defconfig.em9d +++ b/soc/synopsys/emsk/Kconfig.defconfig.em9d @@ -14,8 +14,8 @@ config NUM_IRQ_PRIO_LEVELS config NUM_IRQS # must be > the highest interrupt number used - default 38 if BOARD_EM_STARTERKIT_R23 - default 36 if BOARD_EM_STARTERKIT_R22 + default 38 if "$(BOARD_REVISION)" = "2.3" + default 36 if "$(BOARD_REVISION)" = "2.2" config RGF_NUM_BANKS default 2 diff --git a/soc/synopsys/emsk/Kconfig.soc b/soc/synopsys/emsk/Kconfig.soc new file mode 100644 index 00000000000000..d74e73ddc8985c --- /dev/null +++ b/soc/synopsys/emsk/Kconfig.soc @@ -0,0 +1,34 @@ +# Copyright (c) 2014 Wind River Systems, Inc. +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_EMSK + bool + help + Synopsys ARC EM Starter Kit SoC + +config SOC_EMSK_EM7D + bool + select SOC_EMSK + help + Synopsys ARC EM7D of EMSK + +config SOC_EMSK_EM9D + bool + select SOC_EMSK + help + Synopsys ARC EM9D of EMSK + +config SOC_EMSK_EM11D + bool + select SOC_EMSK + help + Synopsys ARC EM11D of EMSK + +config SOC_SERIES + default "emsk" if SOC_EMSK + +config SOC + default "emsk_em7d" if SOC_EMSK_EM7D + default "emsk_em9d" if SOC_EMSK_EM9D + default "emsk_em11d" if SOC_EMSK_EM11D diff --git a/soc/arc/snps_emsk/linker.ld b/soc/synopsys/emsk/linker.ld similarity index 100% rename from soc/arc/snps_emsk/linker.ld rename to soc/synopsys/emsk/linker.ld diff --git a/soc/synopsys/emsk/soc.yml b/soc/synopsys/emsk/soc.yml new file mode 100644 index 00000000000000..43623616a49495 --- /dev/null +++ b/soc/synopsys/emsk/soc.yml @@ -0,0 +1,6 @@ +series: +- name: emsk + socs: + - name: emsk_em7d + - name: emsk_em9d + - name: emsk_em11d diff --git a/soc/arc/snps_emsk/soc_config.c b/soc/synopsys/emsk/soc_config.c similarity index 100% rename from soc/arc/snps_emsk/soc_config.c rename to soc/synopsys/emsk/soc_config.c diff --git a/soc/arc/snps_arc_hsdk/CMakeLists.txt b/soc/synopsys/hsdk/CMakeLists.txt similarity index 100% rename from soc/arc/snps_arc_hsdk/CMakeLists.txt rename to soc/synopsys/hsdk/CMakeLists.txt diff --git a/soc/synopsys/hsdk/Kconfig b/soc/synopsys/hsdk/Kconfig new file mode 100644 index 00000000000000..1c92ff4bb531f4 --- /dev/null +++ b/soc/synopsys/hsdk/Kconfig @@ -0,0 +1,6 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK + select ARC + select CPU_HAS_FPU diff --git a/soc/synopsys/hsdk/Kconfig.defconfig b/soc/synopsys/hsdk/Kconfig.defconfig new file mode 100644 index 00000000000000..c86f4e25c67050 --- /dev/null +++ b/soc/synopsys/hsdk/Kconfig.defconfig @@ -0,0 +1,46 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_HSDK + +config CPU_HS3X + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 2 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). + default 2 + +config NUM_IRQS + # must be > the highest interrupt number used + default 88 + +config RGF_NUM_BANKS + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 500000000 + +config ARC_FIRQ + default y + +config CODE_DENSITY + default y + +config ARCV2_TIMER_IRQ_PRIORITY + default 1 + +config ARC_CONNECT + default y + +config MP_MAX_NUM_CPUS + default 4 + +config UART_NS16550_ACCESS_WORD_ONLY + default y + depends on UART_NS16550 + +config ARC_HAS_ACCL_REGS + default y + +endif # ARC_HSDK diff --git a/soc/synopsys/hsdk/Kconfig.soc b/soc/synopsys/hsdk/Kconfig.soc new file mode 100644 index 00000000000000..51375c0861bf6f --- /dev/null +++ b/soc/synopsys/hsdk/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2019 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK + bool + +config SOC + default "arc_hsdk" if SOC_ARC_HSDK diff --git a/soc/arc/snps_arc_hsdk/linker.ld b/soc/synopsys/hsdk/linker.ld similarity index 100% rename from soc/arc/snps_arc_hsdk/linker.ld rename to soc/synopsys/hsdk/linker.ld diff --git a/soc/synopsys/hsdk/soc.yml b/soc/synopsys/hsdk/soc.yml new file mode 100644 index 00000000000000..b66e87202281c8 --- /dev/null +++ b/soc/synopsys/hsdk/soc.yml @@ -0,0 +1,4 @@ +series: +- name: arc_hsdk + socs: + - name: arc_hsdk diff --git a/soc/synopsys/hsdk4xd/CMakeLists.txt b/soc/synopsys/hsdk4xd/CMakeLists.txt new file mode 100644 index 00000000000000..e1765fe1136396 --- /dev/null +++ b/soc/synopsys/hsdk4xd/CMakeLists.txt @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(COMPILER STREQUAL gcc) + # GNU compiler options + zephyr_compile_options(-mno-sdata) + zephyr_compile_options_ifdef(CONFIG_FPU -mfpu=fpud_all) +else() + # MWDT compiler options + zephyr_compile_options(-arcv2hs -core4 -Xdual_issue -Xcode_density -Hrgf_banked_regs=32 -HL + -Xatomic -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist + -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc -Hld_cycles=2) + + zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div) + + zephyr_ld_options(-Hlib=hs48_slc_full) +endif() + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/hsdk4xd/Kconfig b/soc/synopsys/hsdk4xd/Kconfig new file mode 100644 index 00000000000000..27abcacf83f355 --- /dev/null +++ b/soc/synopsys/hsdk4xd/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK4XD + select ARC + select CPU_HAS_FPU + select CPU_HAS_DSP diff --git a/soc/synopsys/hsdk4xd/Kconfig.defconfig b/soc/synopsys/hsdk4xd/Kconfig.defconfig new file mode 100644 index 00000000000000..a47f25d09d0196 --- /dev/null +++ b/soc/synopsys/hsdk4xd/Kconfig.defconfig @@ -0,0 +1,53 @@ +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_ARC_HSDK4XD + +config CPU_HS4X + default y + +config NUM_IRQ_PRIO_LEVELS + # This processor supports 2 priority levels: + # 0 for Fast Interrupts (FIRQs) and 1 for Regular Interrupts (IRQs). + default 2 + +config NUM_IRQS + # must be > the highest interrupt number used + default 88 + +config RGF_NUM_BANKS + # Actually cpu has 4 banks but zephys currently supports up to 2 + default 2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 500000000 + +config ARC_FIRQ + default y + +config CODE_DENSITY + default y + +config ARCV2_TIMER_IRQ_PRIORITY + default 1 + +config ARC_CONNECT + default y + +config MP_MAX_NUM_CPUS + default 4 + +config UART_NS16550_ACCESS_WORD_ONLY + default y + depends on UART_NS16550 + +config ARC_HAS_ACCL_REGS + default y + +config ARC_EARLY_SOC_INIT + default y + +config ARC_HAS_STACK_CHECKING + default n + +endif # SOC_ARC_HS4XD diff --git a/soc/synopsys/hsdk4xd/Kconfig.soc b/soc/synopsys/hsdk4xd/Kconfig.soc new file mode 100644 index 00000000000000..878a800b6bf8df --- /dev/null +++ b/soc/synopsys/hsdk4xd/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2023 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_ARC_HSDK4XD + bool + help + Synopsys ARC HSDK4XD SoC + +config SOC + default "arc_hsdk4xd" if SOC_ARC_HSDK4XD diff --git a/soc/arc/snps_arc_hsdk4xd/linker.ld b/soc/synopsys/hsdk4xd/linker.ld similarity index 100% rename from soc/arc/snps_arc_hsdk4xd/linker.ld rename to soc/synopsys/hsdk4xd/linker.ld diff --git a/soc/synopsys/hsdk4xd/soc.yml b/soc/synopsys/hsdk4xd/soc.yml new file mode 100644 index 00000000000000..2200428bde57ea --- /dev/null +++ b/soc/synopsys/hsdk4xd/soc.yml @@ -0,0 +1,4 @@ +series: +- name: arc_hsdk4xd + socs: + - name: arc_hsdk4xd diff --git a/soc/arc/snps_arc_hsdk4xd/soc_ctrl.h b/soc/synopsys/hsdk4xd/soc_ctrl.h similarity index 99% rename from soc/arc/snps_arc_hsdk4xd/soc_ctrl.h rename to soc/synopsys/hsdk4xd/soc_ctrl.h index bde8f04f6edb7f..93d50d3eb2073f 100644 --- a/soc/arc/snps_arc_hsdk4xd/soc_ctrl.h +++ b/soc/synopsys/hsdk4xd/soc_ctrl.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ - #ifndef _ARC_HSDK4XD_SOC_CTRL_H_ #define _ARC_HSDK4XD_SOC_CTRL_H_ diff --git a/soc/arc/snps_arc_hsdk4xd/tune_build_ops.cmake b/soc/synopsys/hsdk4xd/tune_build_ops.cmake similarity index 100% rename from soc/arc/snps_arc_hsdk4xd/tune_build_ops.cmake rename to soc/synopsys/hsdk4xd/tune_build_ops.cmake diff --git a/soc/arc/snps_nsim/CMakeLists.txt b/soc/synopsys/nsim/CMakeLists.txt similarity index 100% rename from soc/arc/snps_nsim/CMakeLists.txt rename to soc/synopsys/nsim/CMakeLists.txt diff --git a/soc/synopsys/nsim/Kconfig b/soc/synopsys/nsim/Kconfig new file mode 100644 index 00000000000000..c307711526568b --- /dev/null +++ b/soc/synopsys/nsim/Kconfig @@ -0,0 +1,32 @@ +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NSIM + select ARC + +config SOC_NSIM_EM + select CPU_HAS_MPU + +config SOC_NSIM_EM7D_V22 + select CPU_HAS_MPU + select CPU_HAS_FPU + +config SOC_NSIM_EM11D + select CPU_HAS_MPU + select CPU_HAS_DSP + +config SOC_NSIM_SEM + select CPU_HAS_MPU + select CPU_HAS_FPU + select ARC_HAS_SECURE + +config SOC_NSIM_HS + select CPU_HAS_FPU + select CPU_HAS_MPU + +config SOC_NSIM_HS_SMP + select CPU_HAS_FPU + +config SOC_NSIM_HS_MPUV6 + select CPU_HAS_MPU + select CPU_HAS_FPU diff --git a/soc/synopsys/nsim/Kconfig.defconfig b/soc/synopsys/nsim/Kconfig.defconfig new file mode 100644 index 00000000000000..3121966114259d --- /dev/null +++ b/soc/synopsys/nsim/Kconfig.defconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_NSIM + +config XIP + default n + +rsource "Kconfig.defconfig.*" + +endif # SOC_NSIM diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.em b/soc/synopsys/nsim/Kconfig.defconfig.em similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.em rename to soc/synopsys/nsim/Kconfig.defconfig.em diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.em11d b/soc/synopsys/nsim/Kconfig.defconfig.em11d similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.em11d rename to soc/synopsys/nsim/Kconfig.defconfig.em11d diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22 b/soc/synopsys/nsim/Kconfig.defconfig.em7d_v22 similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22 rename to soc/synopsys/nsim/Kconfig.defconfig.em7d_v22 diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs b/soc/synopsys/nsim/Kconfig.defconfig.hs similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs rename to soc/synopsys/nsim/Kconfig.defconfig.hs diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs5x b/soc/synopsys/nsim/Kconfig.defconfig.hs5x similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs5x rename to soc/synopsys/nsim/Kconfig.defconfig.hs5x diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs5x_smp b/soc/synopsys/nsim/Kconfig.defconfig.hs5x_smp similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs5x_smp rename to soc/synopsys/nsim/Kconfig.defconfig.hs5x_smp diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs6x b/soc/synopsys/nsim/Kconfig.defconfig.hs6x similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs6x rename to soc/synopsys/nsim/Kconfig.defconfig.hs6x diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp b/soc/synopsys/nsim/Kconfig.defconfig.hs6x_smp similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs6x_smp rename to soc/synopsys/nsim/Kconfig.defconfig.hs6x_smp diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6 b/soc/synopsys/nsim/Kconfig.defconfig.hs_mpuv6 similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs_mpuv6 rename to soc/synopsys/nsim/Kconfig.defconfig.hs_mpuv6 diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.hs_smp b/soc/synopsys/nsim/Kconfig.defconfig.hs_smp similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.hs_smp rename to soc/synopsys/nsim/Kconfig.defconfig.hs_smp diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.sem b/soc/synopsys/nsim/Kconfig.defconfig.sem similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.sem rename to soc/synopsys/nsim/Kconfig.defconfig.sem diff --git a/soc/arc/snps_nsim/Kconfig.defconfig.vpx5 b/soc/synopsys/nsim/Kconfig.defconfig.vpx5 similarity index 100% rename from soc/arc/snps_nsim/Kconfig.defconfig.vpx5 rename to soc/synopsys/nsim/Kconfig.defconfig.vpx5 diff --git a/soc/synopsys/nsim/Kconfig.soc b/soc/synopsys/nsim/Kconfig.soc new file mode 100644 index 00000000000000..f12b143a871eaa --- /dev/null +++ b/soc/synopsys/nsim/Kconfig.soc @@ -0,0 +1,94 @@ +# Copyright (c) 2018 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_NSIM + bool + +config SOC_NSIM_EM + bool + select SOC_NSIM + help + Synopsys ARC EM4 in nSIM + +config SOC_NSIM_EM7D_V22 + bool + select SOC_NSIM + help + Synopsys ARC EM7D_V22 in nSIM + +config SOC_NSIM_EM11D + bool + select SOC_NSIM + help + Synopsys ARC EM11D in nSIM + +config SOC_NSIM_SEM + bool + select SOC_NSIM + help + Synopsys ARC SEM in nSIM + +config SOC_NSIM_HS + bool + select SOC_NSIM + help + Synopsys ARC HS3X in nSIM + +config SOC_NSIM_HS_SMP + bool + select SOC_NSIM + help + Multi-core Synopsys ARC HS3X in nSIM + +config SOC_NSIM_HS_MPUV6 + bool + select SOC_NSIM + help + Synopsys ARC HS3X with MPU v6 in nSIM + +config SOC_NSIM_VPX5 + bool + select SOC_NSIM + help + Synopsys ARC VPX5 in nSIM + +config SOC_NSIM_HS5X + bool + select SOC_NSIM + help + Synopsys ARC HS5x in nSIM + +config SOC_NSIM_HS5X_SMP + bool + select SOC_NSIM + help + Multi-core Synopsys ARC HS5x in nSIM + +config SOC_NSIM_HS6X + bool + select SOC_NSIM + help + Synopsys ARC HS6x in nSIM + +config SOC_NSIM_HS6X_SMP + bool + select SOC_NSIM + help + Multi-core Synopsys ARC HS6x in nSIM + +config SOC + default "nsim_em" if SOC_NSIM_EM + default "nsim_em7d_v22" if SOC_NSIM_EM7D_V22 + default "nsim_em11d" if SOC_NSIM_EM11D + default "nsim_sem" if SOC_NSIM_SEM + default "nsim_hs" if SOC_NSIM_HS + default "nsim_hs_smp" if SOC_NSIM_HS_SMP + default "nsim_hs_mpuv6" if SOC_NSIM_HS_MPUV6 + default "nsim_vpx5" if SOC_NSIM_VPX5 + default "nsim_hs5x" if SOC_NSIM_HS5X + default "nsim_hs5x_smp" if SOC_NSIM_HS5X_SMP + default "nsim_hs6x" if SOC_NSIM_HS6X + default "nsim_hs6x_smp" if SOC_NSIM_HS6X_SMP + +config SOC_SERIES + default "nsim" if SOC_NSIM diff --git a/soc/arc/snps_nsim/linker.ld b/soc/synopsys/nsim/linker.ld similarity index 100% rename from soc/arc/snps_nsim/linker.ld rename to soc/synopsys/nsim/linker.ld diff --git a/soc/synopsys/nsim/soc.yml b/soc/synopsys/nsim/soc.yml new file mode 100644 index 00000000000000..a3a427ca006f1d --- /dev/null +++ b/soc/synopsys/nsim/soc.yml @@ -0,0 +1,15 @@ +series: +- name: nsim + socs: + - name: nsim_em + - name: nsim_em7d_v22 + - name: nsim_em11d + - name: nsim_hs + - name: nsim_hs_smp + - name: nsim_hs_mpuv6 + - name: nsim_hs5x + - name: nsim_hs5x_smp + - name: nsim_hs6x + - name: nsim_hs6x_smp + - name: nsim_vpx5 + - name: nsim_sem diff --git a/soc/synopsys/qemu_arc/CMakeLists.txt b/soc/synopsys/qemu_arc/CMakeLists.txt new file mode 100644 index 00000000000000..f2925afa745c89 --- /dev/null +++ b/soc/synopsys/qemu_arc/CMakeLists.txt @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: Apache-2.0 + +if(COMPILER STREQUAL gcc) + zephyr_compile_options(-mcpu=${GCC_M_CPU}) + + zephyr_compile_options_ifdef(CONFIG_ISA_ARCV2 -mno-sdata) +else() + zephyr_compile_options_ifdef(CONFIG_SOC_QEMU_ARC_HS -arcv2hs -core2 -Xatomic + -Xunaligned -Xcode_density -Xswap -Xbitscan + -Xmpy_option=qmpyh -Xshift_assist -Xbarrel_shifter + -Xtimer0 -Xtimer1) + + zephyr_ld_option_ifdef(CONFIG_SOC_QEMU_ARC_HS -Hlib=hs38_full) + + if(NOT CONFIG_SOC_QEMU_ARC_HS) + message(WARNING "QEMU ARC platforms other than HS3X are not supported yet with MW toolchain") + endif() +endif() + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/synopsys/qemu_arc/Kconfig b/soc/synopsys/qemu_arc/Kconfig new file mode 100644 index 00000000000000..ef3cfb984d3349 --- /dev/null +++ b/soc/synopsys/qemu_arc/Kconfig @@ -0,0 +1,18 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_ARC + select ARC + select CPU_HAS_MPU + +config SOC_QEMU_ARC_EM + select CPU_EM4 + +config SOC_QEMU_ARC_HS + select CPU_HS3X + +config SOC_QEMU_ARC_HS5X + select CPU_HS5X + +config SOC_QEMU_ARC_HS6X + select CPU_HS6X diff --git a/soc/synopsys/qemu_arc/Kconfig.defconfig b/soc/synopsys/qemu_arc/Kconfig.defconfig new file mode 100644 index 00000000000000..a8a7550ef53599 --- /dev/null +++ b/soc/synopsys/qemu_arc/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_QEMU_ARC + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 10000000 + +config RGF_NUM_BANKS + default 1 + +config ARC_FIRQ + default n + +config NUM_IRQ_PRIO_LEVELS + default 15 + +config NUM_IRQS + default 26 + +# Technically ARC HS supports MPUv3, but not v2. But given MPUv3 +# is the same as v2 but with minimal region size of 32 bytes, we +# may assume MPUv3 is just a subset of MPUv2. + +config ARC_MPU_VER + default 2 + +endif diff --git a/soc/synopsys/qemu_arc/Kconfig.soc b/soc/synopsys/qemu_arc/Kconfig.soc new file mode 100644 index 00000000000000..9644bd9a534419 --- /dev/null +++ b/soc/synopsys/qemu_arc/Kconfig.soc @@ -0,0 +1,30 @@ +# Copyright (c) 2020 Synopsys, Inc. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_QEMU_ARC + bool + +config SOC_QEMU_ARC_EM + bool + select SOC_QEMU_ARC + +config SOC_QEMU_ARC_HS + bool + select SOC_QEMU_ARC + +config SOC_QEMU_ARC_HS5X + bool + select SOC_QEMU_ARC + +config SOC_QEMU_ARC_HS6X + bool + select SOC_QEMU_ARC + +config SOC_SERIES + default "qemu_arc" if SOC_QEMU_ARC + +config SOC + default "qemu_arc_em" if SOC_QEMU_ARC_EM + default "qemu_arc_hs" if SOC_QEMU_ARC_HS + default "qemu_arc_hs5x" if SOC_QEMU_ARC_HS5X + default "qemu_arc_hs6x" if SOC_QEMU_ARC_HS6X diff --git a/soc/arc/snps_qemu/linker.ld b/soc/synopsys/qemu_arc/linker.ld similarity index 100% rename from soc/arc/snps_qemu/linker.ld rename to soc/synopsys/qemu_arc/linker.ld diff --git a/soc/synopsys/qemu_arc/soc.yml b/soc/synopsys/qemu_arc/soc.yml new file mode 100644 index 00000000000000..06caef5f3d9d4d --- /dev/null +++ b/soc/synopsys/qemu_arc/soc.yml @@ -0,0 +1,7 @@ +series: +- name: qemu_arc + socs: + - name: qemu_arc_em + - name: qemu_arc_hs + - name: qemu_arc_hs5x + - name: qemu_arc_hs6x diff --git a/soc/riscv/intel_niosv/CMakeLists.txt b/soc/telink/tlsr/CMakeLists.txt similarity index 100% rename from soc/riscv/intel_niosv/CMakeLists.txt rename to soc/telink/tlsr/CMakeLists.txt diff --git a/soc/telink/tlsr/Kconfig b/soc/telink/tlsr/Kconfig new file mode 100644 index 00000000000000..ffc4a398905985 --- /dev/null +++ b/soc/telink/tlsr/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TELINK_TLSR + +rsource "*/Kconfig" + +endif # SOC_FAMILY_TELINK_TLSR diff --git a/soc/telink/tlsr/Kconfig.defconfig b/soc/telink/tlsr/Kconfig.defconfig new file mode 100644 index 00000000000000..58492dd1ac998c --- /dev/null +++ b/soc/telink/tlsr/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TELINK_TLSR + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_TELINK_TLSR diff --git a/soc/telink/tlsr/Kconfig.soc b/soc/telink/tlsr/Kconfig.soc new file mode 100644 index 00000000000000..98f5cbf1b83650 --- /dev/null +++ b/soc/telink/tlsr/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_TELINK_TLSR + bool + +config SOC_FAMILY + default "telink_tlsr" if SOC_FAMILY_TELINK_TLSR + +rsource "*/Kconfig.soc" diff --git a/soc/telink/tlsr/soc.yml b/soc/telink/tlsr/soc.yml new file mode 100644 index 00000000000000..e982d5e69dc36a --- /dev/null +++ b/soc/telink/tlsr/soc.yml @@ -0,0 +1,6 @@ +family: + - name: telink_tlsr + series: + - name: tlsr951x + socs: + - name: tlsr9518 diff --git a/soc/telink/tlsr/tlsr951x/CMakeLists.txt b/soc/telink/tlsr/tlsr951x/CMakeLists.txt new file mode 100644 index 00000000000000..9e1dff40e4b1b7 --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/CMakeLists.txt @@ -0,0 +1,20 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + start.S + soc_irq.S + soc.c +) + +zephyr_include_directories(.) + +# Force using BFD-LD +zephyr_ld_options(-fuse-ld=bfd) + +# Set compile options +zephyr_compile_options_ifdef(CONFIG_TELINK_B91_HWDSP -mext-dsp) +zephyr_compile_options_ifndef(CONFIG_RISCV_GP -mno-relax) +zephyr_linker_sources(ROM_START SORT_KEY 0x0 init.ld) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/telink/tlsr/tlsr951x/Kconfig b/soc/telink/tlsr/tlsr951x/Kconfig new file mode 100644 index 00000000000000..80fa44e6658c22 --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/Kconfig @@ -0,0 +1,31 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_TLSR951X + bool + select RISCV + select RISCV_ISA_RV32I + select RISCV_ISA_EXT_M + select RISCV_ISA_EXT_A + select RISCV_ISA_EXT_C + select RISCV_ISA_EXT_ZICSR + select RISCV_ISA_EXT_ZIFENCEI + select RISCV_PRIVILEGED + select RISCV_HAS_PLIC + select HAS_TELINK_DRIVERS + select ATOMIC_OPERATIONS_BUILTIN + select CPU_HAS_FPU + select INCLUDE_RESET_VECTOR + +if SOC_SERIES_TLSR951X + +config TELINK_B91_HWDSP + bool "Support Hardware DSP" + select RISCV_SOC_CONTEXT_SAVE + +config TELINK_B91_PFT_ARCH + bool "Support performance throttling" + default y + select RISCV_SOC_CONTEXT_SAVE + +endif # SOC_SERIES_TLSR951X diff --git a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig new file mode 100644 index 00000000000000..7ad94f134304ef --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig @@ -0,0 +1,47 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_TLSR951X + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 32000 + +config RISCV_SOC_INTERRUPT_INIT + bool + default y + +config RISCV_GP + bool + default y + +config NUM_IRQS + int + default 64 + +config PINCTRL + default y + +config XIP + bool + default n + +config MAIN_STACK_SIZE + int + default 2048 + +config IDLE_STACK_SIZE + int + default 1536 + +config TEST_EXTRA_STACK_SIZE + int + default 1024 + +config 2ND_LVL_INTR_00_OFFSET + default 11 + +config HAS_FLASH_LOAD_OFFSET + default y if BOOTLOADER_MCUBOOT + +endif # SOC_SERIES_TLSR951X diff --git a/soc/telink/tlsr/tlsr951x/Kconfig.soc b/soc/telink/tlsr/tlsr951x/Kconfig.soc new file mode 100644 index 00000000000000..102ef4390a6863 --- /dev/null +++ b/soc/telink/tlsr/tlsr951x/Kconfig.soc @@ -0,0 +1,20 @@ +# Copyright (c) 2021 Telink Semiconductor +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_TLSR951X + bool + select SOC_FAMILY_TELINK_TLSR + help + Telink TLSR951X + +config SOC_TLSR9518 + bool + select SOC_SERIES_TLSR951X + help + Telink TLSR9518 + +config SOC_SERIES + default "tlsr951x" if SOC_SERIES_TLSR951X + +config SOC + default "tlsr9518" if SOC_TLSR9518 diff --git a/soc/riscv/telink_tlsr/tlsr951x/init.ld b/soc/telink/tlsr/tlsr951x/init.ld similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/init.ld rename to soc/telink/tlsr/tlsr951x/init.ld diff --git a/soc/riscv/telink_tlsr/tlsr951x/linker.ld b/soc/telink/tlsr/tlsr951x/linker.ld similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/linker.ld rename to soc/telink/tlsr/tlsr951x/linker.ld diff --git a/soc/riscv/telink_tlsr/tlsr951x/pinctrl_soc.h b/soc/telink/tlsr/tlsr951x/pinctrl_soc.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/pinctrl_soc.h rename to soc/telink/tlsr/tlsr951x/pinctrl_soc.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc.c b/soc/telink/tlsr/tlsr951x/soc.c similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc.c rename to soc/telink/tlsr/tlsr951x/soc.c diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc.h b/soc/telink/tlsr/tlsr951x/soc.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc.h rename to soc/telink/tlsr/tlsr951x/soc.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc_context.h b/soc/telink/tlsr/tlsr951x/soc_context.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc_context.h rename to soc/telink/tlsr/tlsr951x/soc_context.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc_irq.S b/soc/telink/tlsr/tlsr951x/soc_irq.S similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc_irq.S rename to soc/telink/tlsr/tlsr951x/soc_irq.S diff --git a/soc/riscv/telink_tlsr/tlsr951x/soc_offsets.h b/soc/telink/tlsr/tlsr951x/soc_offsets.h similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/soc_offsets.h rename to soc/telink/tlsr/tlsr951x/soc_offsets.h diff --git a/soc/riscv/telink_tlsr/tlsr951x/start.S b/soc/telink/tlsr/tlsr951x/start.S similarity index 100% rename from soc/riscv/telink_tlsr/tlsr951x/start.S rename to soc/telink/tlsr/tlsr951x/start.S diff --git a/soc/ti/k3/CMakeLists.txt b/soc/ti/k3/CMakeLists.txt new file mode 100644 index 00000000000000..9d3cdd0d7af330 --- /dev/null +++ b/soc/ti/k3/CMakeLists.txt @@ -0,0 +1,4 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/ti/k3/Kconfig b/soc/ti/k3/Kconfig new file mode 100644 index 00000000000000..4bc3bc6b2a975b --- /dev/null +++ b/soc/ti/k3/Kconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TI_K3 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_TI_K3 diff --git a/soc/ti/k3/Kconfig.defconfig b/soc/ti/k3/Kconfig.defconfig new file mode 100644 index 00000000000000..2889e544ad0878 --- /dev/null +++ b/soc/ti/k3/Kconfig.defconfig @@ -0,0 +1,8 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +if SOC_FAMILY_TI_K3 + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_TI_K3 diff --git a/soc/ti/k3/Kconfig.soc b/soc/ti/k3/Kconfig.soc new file mode 100644 index 00000000000000..d49a35ebfe8058 --- /dev/null +++ b/soc/ti/k3/Kconfig.soc @@ -0,0 +1,10 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +config SOC_FAMILY_TI_K3 + bool + +config SOC_FAMILY + default "ti_k3" if SOC_FAMILY_TI_K3 + +rsource "*/Kconfig.soc" diff --git a/soc/ti/k3/am6x/CMakeLists.txt b/soc/ti/k3/am6x/CMakeLists.txt new file mode 100644 index 00000000000000..9f0cb3dd2f5bb8 --- /dev/null +++ b/soc/ti/k3/am6x/CMakeLists.txt @@ -0,0 +1,21 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +if(CONFIG_SOC_AM6234_A53) + zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c) + + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "") +elseif(CONFIG_SOC_AM6234_M4) + zephyr_sources(m4/soc.c) + + zephyr_include_directories(m4) + + if(CONFIG_OPENAMP_RSC_TABLE) + zephyr_linker_section(NAME .resource_table GROUP ROM_REGION NOINPUT) + zephyr_linker_section_configure(SECTION .resource_table KEEP INPUT ".resource_table*") + endif() + + set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/m4/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/ti/k3/am6x/Kconfig b/soc/ti/k3/am6x/Kconfig new file mode 100644 index 00000000000000..8eb993db66f39f --- /dev/null +++ b/soc/ti/k3/am6x/Kconfig @@ -0,0 +1,23 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AM6X_A53 + select ARM64 + select CPU_CORTEX_A53 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + +config SOC_SERIES_AM6X_M4 + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_SYSTICK + select DYNAMIC_INTERRUPTS + select CPU_CORTEX_M_HAS_DWT + select OPENAMP_RSC_TABLE + select UART_NS16550_ACCESS_WORD_ONLY + select EXTERNAL_ADDRESS_TRANSLATION + select MM_DRV + select MM_TI_RAT + +config SOC_PART_NUMBER + default "AM6234" if SOC_AM6234_A53 + default "AM6234" if SOC_AM6234_M4 diff --git a/soc/ti/k3/am6x/Kconfig.defconfig b/soc/ti/k3/am6x/Kconfig.defconfig new file mode 100644 index 00000000000000..f8a999baf50eaf --- /dev/null +++ b/soc/ti/k3/am6x/Kconfig.defconfig @@ -0,0 +1,45 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_AM6X + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config NUM_IRQS + int + default 64 if SOC_SERIES_AM6X_M4 + default 280 if SOC_SERIES_AM6X_A53 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 400000000 if SOC_SERIES_AM6X_M4 + default 200000000 if SOC_SERIES_AM6X_A53 + +config PINCTRL + default y + +if SERIAL + +config UART_NS16550 + default y + +config UART_NS16550_TI_K3 + default y if SOC_SERIES_AM6X_M4 + +choice UART_NS16550_VARIANT + default UART_NS16550_VARIANT_NS16750 +endchoice + +endif # SERIAL + +config BUILD_OUTPUT_BIN + default n if SOC_SERIES_AM6X_M4 + +endif # SOC_SERIES_AM6X diff --git a/soc/ti/k3/am6x/Kconfig.soc b/soc/ti/k3/am6x/Kconfig.soc new file mode 100644 index 00000000000000..fa9c8e20f7e3f9 --- /dev/null +++ b/soc/ti/k3/am6x/Kconfig.soc @@ -0,0 +1,32 @@ +# Copyright (c) 2023 Enphase Energy +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_AM6X + bool + select SOC_FAMILY_TI_K3 + +config SOC_SERIES_AM6X_A53 + bool + select SOC_SERIES_AM6X + help + Enable support for AM6X A53 Series. + +config SOC_SERIES_AM6X_M4 + bool + select SOC_SERIES_AM6X + help + Enable support for AM62X M4 Series. + +config SOC_AM6234_A53 + bool + select SOC_SERIES_AM6X_A53 + +config SOC_AM6234_M4 + bool + select SOC_SERIES_AM6X_M4 + +config SOC_SERIES + default "am6x" if SOC_SERIES_AM6X + +config SOC + default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53 diff --git a/soc/arm64/ti_k3/am6x/mmu_regions.c b/soc/ti/k3/am6x/a53/mmu_regions.c similarity index 100% rename from soc/arm64/ti_k3/am6x/mmu_regions.c rename to soc/ti/k3/am6x/a53/mmu_regions.c diff --git a/soc/arm/ti_k3/am62x_m4/linker.ld b/soc/ti/k3/am6x/m4/linker.ld similarity index 100% rename from soc/arm/ti_k3/am62x_m4/linker.ld rename to soc/ti/k3/am6x/m4/linker.ld diff --git a/soc/arm/ti_k3/am62x_m4/soc.c b/soc/ti/k3/am6x/m4/soc.c similarity index 100% rename from soc/arm/ti_k3/am62x_m4/soc.c rename to soc/ti/k3/am6x/m4/soc.c diff --git a/soc/arm/ti_k3/am62x_m4/soc.h b/soc/ti/k3/am6x/m4/soc.h similarity index 100% rename from soc/arm/ti_k3/am62x_m4/soc.h rename to soc/ti/k3/am6x/m4/soc.h diff --git a/soc/arm64/ti_k3/pinctrl_soc.h b/soc/ti/k3/am6x/pinctrl_soc.h similarity index 100% rename from soc/arm64/ti_k3/pinctrl_soc.h rename to soc/ti/k3/am6x/pinctrl_soc.h diff --git a/soc/ti/k3/soc.yml b/soc/ti/k3/soc.yml new file mode 100644 index 00000000000000..92ae28d5a0ad46 --- /dev/null +++ b/soc/ti/k3/soc.yml @@ -0,0 +1,9 @@ +family: +- name: ti_k3 + series: + - name: am6x + socs: + - name: am6234 + cpuclusters: + - name: m4 + - name: a53 diff --git a/soc/ti/lm3s6965/CMakeLists.txt b/soc/ti/lm3s6965/CMakeLists.txt new file mode 100644 index 00000000000000..b490726e5078dc --- /dev/null +++ b/soc/ti/lm3s6965/CMakeLists.txt @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_library() + +zephyr_library_sources( + soc_config.c + reboot.S + sys_arch_reboot.c + ) + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/arm/include + ) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/lm3s6965/Kconfig b/soc/ti/lm3s6965/Kconfig new file mode 100644 index 00000000000000..16a9c5c083fb6b --- /dev/null +++ b/soc/ti/lm3s6965/Kconfig @@ -0,0 +1,7 @@ +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_TI_LM3S6965 + select ARM + select CPU_CORTEX_M3 + select CPU_CORTEX_M_HAS_DWT diff --git a/soc/ti/lm3s6965/Kconfig.defconfig b/soc/ti/lm3s6965/Kconfig.defconfig new file mode 100644 index 00000000000000..097a4969c37c93 --- /dev/null +++ b/soc/ti/lm3s6965/Kconfig.defconfig @@ -0,0 +1,29 @@ +# TI LM3S6965 platform configuration options + +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_TI_LM3S6965 + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts and ethernet interrupts + default 43 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 12000000 + +if UART_STELLARIS + +config UART_STELLARIS_PORT_0 + default y + +config UART_STELLARIS_PORT_1 + default y + +config UART_STELLARIS_PORT_2 + default y + +endif # UART_STELLARIS + +endif diff --git a/soc/ti/lm3s6965/Kconfig.soc b/soc/ti/lm3s6965/Kconfig.soc new file mode 100644 index 00000000000000..dc1da3fa35b5ce --- /dev/null +++ b/soc/ti/lm3s6965/Kconfig.soc @@ -0,0 +1,16 @@ +# Copyright (c) 2014-2015 Wind River Systems, Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_TI_LM3S6965 + bool + help + TI LM3S6965 + +config SOC_TI_LM3S6965_QEMU + def_bool y + depends on SOC_TI_LM3S6965 + # Platform has only been tested on QEMU, not on real hardware, so always + # assume it is used for a QEMU target. + +config SOC + default "ti_lm3s6965" if SOC_TI_LM3S6965 diff --git a/soc/arm/ti_lm3s6965/reboot.S b/soc/ti/lm3s6965/reboot.S similarity index 100% rename from soc/arm/ti_lm3s6965/reboot.S rename to soc/ti/lm3s6965/reboot.S diff --git a/soc/arm/ti_lm3s6965/soc.h b/soc/ti/lm3s6965/soc.h similarity index 100% rename from soc/arm/ti_lm3s6965/soc.h rename to soc/ti/lm3s6965/soc.h diff --git a/soc/ti/lm3s6965/soc.yml b/soc/ti/lm3s6965/soc.yml new file mode 100644 index 00000000000000..6f80cd356af921 --- /dev/null +++ b/soc/ti/lm3s6965/soc.yml @@ -0,0 +1,2 @@ +socs: +- name: ti_lm3s6965 diff --git a/soc/arm/ti_lm3s6965/soc_config.c b/soc/ti/lm3s6965/soc_config.c similarity index 100% rename from soc/arm/ti_lm3s6965/soc_config.c rename to soc/ti/lm3s6965/soc_config.c diff --git a/soc/arm/ti_lm3s6965/sys_arch_reboot.c b/soc/ti/lm3s6965/sys_arch_reboot.c similarity index 100% rename from soc/arm/ti_lm3s6965/sys_arch_reboot.c rename to soc/ti/lm3s6965/sys_arch_reboot.c diff --git a/soc/ti/simplelink/CMakeLists.txt b/soc/ti/simplelink/CMakeLists.txt new file mode 100644 index 00000000000000..c9df1f11486c0d --- /dev/null +++ b/soc/ti/simplelink/CMakeLists.txt @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +add_subdirectory(${SOC_SERIES}) diff --git a/soc/ti/simplelink/Kconfig b/soc/ti/simplelink/Kconfig new file mode 100644 index 00000000000000..af4cd5f74333ef --- /dev/null +++ b/soc/ti/simplelink/Kconfig @@ -0,0 +1,15 @@ +# Texas Instruments SimpleLink Family +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +if SOC_FAMILY_TI_SIMPLELINK + +rsource "*/Kconfig" + +config HAS_TI_CCFG + bool + help + Selected when CCFG (Customer Configuration) registers + appear at the end of flash + +endif # SOC_FAMILY_TI_SIMPLELINK diff --git a/soc/ti/simplelink/Kconfig.defconfig b/soc/ti/simplelink/Kconfig.defconfig new file mode 100644 index 00000000000000..0051bdd7801a7e --- /dev/null +++ b/soc/ti/simplelink/Kconfig.defconfig @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +if SOC_FAMILY_TI_SIMPLELINK + +rsource "*/Kconfig.defconfig" + +endif # SOC_FAMILY_TI_SIMPLELINK diff --git a/soc/ti/simplelink/Kconfig.soc b/soc/ti/simplelink/Kconfig.soc new file mode 100644 index 00000000000000..d1f3a505e21846 --- /dev/null +++ b/soc/ti/simplelink/Kconfig.soc @@ -0,0 +1,11 @@ +# Texas Instruments SimpleLink Family +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2017 Zephyr Contributors + +config SOC_FAMILY_TI_SIMPLELINK + bool + +config SOC_FAMILY + default "ti_simplelink" if SOC_FAMILY_TI_SIMPLELINK + +rsource "*/Kconfig.soc" diff --git a/soc/ti/simplelink/cc13x2_cc26x2/CMakeLists.txt b/soc/ti/simplelink/cc13x2_cc26x2/CMakeLists.txt new file mode 100644 index 00000000000000..5da2629b5c0ed1 --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/CMakeLists.txt @@ -0,0 +1,16 @@ +# Copyright (c) 2019 Brett Witherspoon +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_sources(ccfg.c) +zephyr_include_directories(.) + +if(CONFIG_PM OR CONFIG_PM_DEVICE OR CONFIG_POWEROFF) + zephyr_library_sources(power.c) +endif() +zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) + +zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc13x2_cc26x2/Kconfig b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig new file mode 100644 index 00000000000000..056e6162523605 --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig @@ -0,0 +1,62 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2_CC26X2 + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select DYNAMIC_INTERRUPTS + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_CC13X2_CC26X2_SDK + select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_PM + select HAS_POWEROFF + +menu "Customer Configuration (CCFG)" +depends on SOC_SERIES_CC13X2_CC26X2 + +config CC13X2_CC26X2_BOOST_MODE + bool "Radio boost mode (VDDR_HH)" + help + Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). + +config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS + bool "Board defines custom RFCC26XX hwAttrs structure" + help + The board defines its own RFCC26XX_hwAttrs structure (e.g., for + custom antenna switching callback). + +config CC13X2_CC26X2_BOOTLOADER_ENABLE + bool "ROM bootloader" + help + Enable the serial bootloader which resides in ROM on CC13xx / CC26xx + devices. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + bool "ROM bootloader backdoor" + depends on CC13X2_CC26X2_BOOTLOADER_ENABLE + help + Enable the ROM bootloader backdoor which starts the bootloader if the + associated pin is at the correct logic level on reset. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN + int "ROM bootloader backdoor pin" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 255 + default 255 + help + Set the pin that is level checked if the bootloader backdoor is + enabled. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL + int "ROM bootloader backdoor level" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 1 + default 0 + help + Set the active level of the pin selected for the bootloader backdoor. + +endmenu diff --git a/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.defconfig b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.defconfig new file mode 100644 index 00000000000000..fa1d5d9b6dc52f --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.defconfig @@ -0,0 +1,41 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CC13X2_CC26X2 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Note that when using the RTC as system clock, this needs to be 32768 +# to reduce truncation errors from accumulating due to conversion to/from +# time, ticks, and HW cycles +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +config NUM_IRQS + default 38 + +if IEEE802154 + +config IEEE802154_CC13XX_CC26XX + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +config IEEE802154_CC13XX_CC26XX_SUB_GHZ + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +endif # IEEE802154 + +if BT + +config BLE_CC13XX_CC26XX + bool + default y + +endif # BT + +endif # SOC_SERIES_CC13X2_CC26X2 diff --git a/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc new file mode 100644 index 00000000000000..0642c518ec7c2c --- /dev/null +++ b/soc/ti/simplelink/cc13x2_cc26x2/Kconfig.soc @@ -0,0 +1,43 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 + +# Copyright (c) 2019 Brett Witherspoon +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2_CC26X2 + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink CC13x2 / CC26x2 SoCs + +config SOC_CC1352P + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC1352P + +config SOC_CC1352R + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC1352R + +config SOC_CC2652P + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC2652P + +config SOC_CC2652R + bool + select SOC_SERIES_CC13X2_CC26X2 + help + CC2652R + +config SOC_SERIES + default "cc13x2_cc26x2" if SOC_SERIES_CC13X2_CC26X2 + +config SOC + default "cc1352p" if SOC_CC1352P + default "cc1352r" if SOC_CC1352R + default "cc2652p" if SOC_CC2652P + default "cc2652r" if SOC_CC2652R diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.c b/soc/ti/simplelink/cc13x2_cc26x2/ccfg.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.c rename to soc/ti/simplelink/cc13x2_cc26x2/ccfg.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld b/soc/ti/simplelink/cc13x2_cc26x2/ccfg.ld similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/ccfg.ld rename to soc/ti/simplelink/cc13x2_cc26x2/ccfg.ld diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/pinctrl_soc.h b/soc/ti/simplelink/cc13x2_cc26x2/pinctrl_soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/pinctrl_soc.h rename to soc/ti/simplelink/cc13x2_cc26x2/pinctrl_soc.h diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/power.c b/soc/ti/simplelink/cc13x2_cc26x2/power.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/power.c rename to soc/ti/simplelink/cc13x2_cc26x2/power.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/poweroff.c b/soc/ti/simplelink/cc13x2_cc26x2/poweroff.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/poweroff.c rename to soc/ti/simplelink/cc13x2_cc26x2/poweroff.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.c b/soc/ti/simplelink/cc13x2_cc26x2/soc.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/soc.c rename to soc/ti/simplelink/cc13x2_cc26x2/soc.c diff --git a/soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h b/soc/ti/simplelink/cc13x2_cc26x2/soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2_cc26x2/soc.h rename to soc/ti/simplelink/cc13x2_cc26x2/soc.h diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt b/soc/ti/simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt new file mode 100644 index 00000000000000..634e6995f5362b --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/CMakeLists.txt @@ -0,0 +1,15 @@ +# Copyright (c) 2022 Vaishnav Achath +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources(soc.c) +zephyr_sources(ccfg.c) + +zephyr_include_directories(.) + +zephyr_library_sources_ifdef(CONFIG_PM power.c) +zephyr_library_sources_ifdef(CONFIG_PM_DEVICE power.c) + +zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig new file mode 100644 index 00000000000000..42789af2526b54 --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig @@ -0,0 +1,69 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2X7_CC26X2X7 + bool + select ARM + select CPU_CORTEX_M4 + select CPU_HAS_ARM_MPU + select DYNAMIC_INTERRUPTS + select CPU_CORTEX_M_HAS_DWT + select CPU_HAS_FPU + select HAS_CC13X2X7_CC26X2X7_SDK + select HAS_TI_CCFG if !BOOTLOADER_MCUBOOT + select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE + select HAS_PM + +menu "Customer Configuration (CCFG)" +depends on SOC_SERIES_CC13X2X7_CC26X2X7 + +config CC13X2_CC26X2_BOOST_MODE + bool "Radio boost mode (VDDR_HH)" + help + Enable the radio boost mode +14dBm (sets CCFG_FORCE_VDDR_HH to 1). + +config CC13X2_CC26X2_HAS_CUSTOM_RF_HWATTRS + bool "Board defines custom RFCC26XX hwAttrs structure" + help + The board defines its own RFCC26XX_hwAttrs structure (e.g., for + custom antenna switching callback). + +config CC13X2_CC26X2_BOOTLOADER_ENABLE + bool "ROM bootloader" + help + Enable the serial bootloader which resides in ROM on CC13xx / CC26xx + devices. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + bool "ROM bootloader backdoor" + depends on CC13X2_CC26X2_BOOTLOADER_ENABLE + help + Enable the ROM bootloader backdoor which starts the bootloader if the + associated pin is at the correct logic level on reset. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_PIN + int "ROM bootloader backdoor pin" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 255 + default 255 + help + Set the pin that is level checked if the bootloader backdoor is + enabled. + +config CC13X2_CC26X2_BOOTLOADER_BACKDOOR_LEVEL + int "ROM bootloader backdoor level" + depends on CC13X2_CC26X2_BOOTLOADER_BACKDOOR_ENABLE + range 0 1 + default 0 + help + Set the active level of the pin selected for the bootloader backdoor. + +config CC13X2_CC26X2_XOSC_CAPARRAY_DELTA + hex "Cap array tuning delta" + range 0 0xFF + default 0xD5 + help + Enable a specific cap array tunning delta. + +endmenu diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig new file mode 100644 index 00000000000000..c453227ad4c8da --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.defconfig @@ -0,0 +1,41 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_CC13X2X7_CC26X2X7 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 32768 + +# Note that when using the RTC as system clock, this needs to be 32768 +# to reduce truncation errors from accumulating due to conversion to/from +# time, ticks, and HW cycles +config SYS_CLOCK_TICKS_PER_SEC + default 32768 + +config NUM_IRQS + default 38 + +if IEEE802154 + +config IEEE802154_CC13XX_CC26XX + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +config IEEE802154_CC13XX_CC26XX_SUB_GHZ + # required for linking with PowerCC26X2_config in + # soc/soc_legacy/arm/ti_simplelink/cc13x2_cc26x2/power.c + select PM + +endif # IEEE802154 + +if BT + +config BLE_CC13XX_CC26XX + bool + default y + +endif # BT + +endif # SOC_SERIES_CC13X2X7_CC26X2X7 diff --git a/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc new file mode 100644 index 00000000000000..8ab5dc1ea6e2f9 --- /dev/null +++ b/soc/ti/simplelink/cc13x2x7_cc26x2x7/Kconfig.soc @@ -0,0 +1,42 @@ +# Texas Instruments SimpleLink CC13x2 / CC26x2 +# Copyright (c) 2022 Vaishnav Achath +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_CC13X2X7_CC26X2X7 + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink CC13x2x7 / CC26x2x7 SoCs + +config SOC_CC1352P7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC1352P7 + +config SOC_CC1352R7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC1352R7 + +config SOC_CC2652P7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC2652P7 + +config SOC_CC2652R7 + bool + select SOC_SERIES_CC13X2X7_CC26X2X7 + help + CC2652R7 + +config SOC_SERIES + default "cc13x2x7_cc26x2x7" if SOC_SERIES_CC13X2X7_CC26X2X7 + +config SOC + default "cc1352p7" if SOC_CC1352P7 + default "cc1352r7" if SOC_CC1352R7 + default "cc2652p7" if SOC_CC2652P7 + default "cc2652r7" if SOC_CC2652R7 diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.c b/soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.c rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.c diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.ld b/soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.ld similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/ccfg.ld rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/ccfg.ld diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h b/soc/ti/simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/pinctrl_soc.h diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/power.c b/soc/ti/simplelink/cc13x2x7_cc26x2x7/power.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/power.c rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/power.c diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.c b/soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.c similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.c rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.c diff --git a/soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.h b/soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc13x2x7_cc26x2x7/soc.h rename to soc/ti/simplelink/cc13x2x7_cc26x2x7/soc.h diff --git a/soc/ti/simplelink/cc32xx/CMakeLists.txt b/soc/ti/simplelink/cc32xx/CMakeLists.txt new file mode 100644 index 00000000000000..4142f958e0572c --- /dev/null +++ b/soc/ti/simplelink/cc32xx/CMakeLists.txt @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +zephyr_sources(soc.c) +zephyr_include_directories(.) + +if(DEFINED CONFIG_CC3220SF_DEBUG OR DEFINED CONFIG_CC3235SF_DEBUG) + zephyr_linker_sources(ROM_START SORT_KEY 0 cc32xx_debug.ld) +endif() + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/cc32xx/Kconfig b/soc/ti/simplelink/cc32xx/Kconfig new file mode 100644 index 00000000000000..d8ec2f2071592c --- /dev/null +++ b/soc/ti/simplelink/cc32xx/Kconfig @@ -0,0 +1,25 @@ +# Texas Instruments CC32XX +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +config SOC_SERIES_CC32XX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select DYNAMIC_INTERRUPTS + +config SOC_CC3220SF + select HAS_CC3220SDK + +config SOC_CC3235SF + select HAS_CC3220SDK + +config CC3220SF_DEBUG + bool "Prepend debug header, disabling flash verification" if XIP + default XIP + depends on SOC_CC3220SF + +config CC3235SF_DEBUG + bool "Prepend debug header, disabling flash verification" if XIP + default XIP + depends on SOC_CC3235SF diff --git a/soc/ti/simplelink/cc32xx/Kconfig.defconfig b/soc/ti/simplelink/cc32xx/Kconfig.defconfig new file mode 100644 index 00000000000000..f782322c9cca7a --- /dev/null +++ b/soc/ti/simplelink/cc32xx/Kconfig.defconfig @@ -0,0 +1,9 @@ +# TI SimpleLink Family +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +if SOC_SERIES_CC32XX + +rsource "Kconfig.defconfig.cc32*" + +endif # SOC_SERIES_CC32XX diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3220sf similarity index 88% rename from soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf rename to soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3220sf index 461802f2155ad4..ac26dbe66f7489 100644 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3220sf +++ b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3220sf @@ -1,12 +1,9 @@ # TI SimpleLink CC3220SF SoC - # SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated if SOC_CC3220SF -config SOC - default "cc3220sf" - config NUM_IRQS # must be >= the highest interrupt number used # This includes the NWP interrupt @@ -20,10 +17,12 @@ config ROM_START_OFFSET default 0x0 if !XIP if !XIP + config FLASH_SIZE default 0 config FLASH_BASE_ADDRESS default 0 + endif endif # SOC_CC3220SF diff --git a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3235sf b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3235sf similarity index 93% rename from soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3235sf rename to soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3235sf index 37852a154a015b..9da363f006cb62 100644 --- a/soc/arm/ti_simplelink/cc32xx/Kconfig.defconfig.cc3235sf +++ b/soc/ti/simplelink/cc32xx/Kconfig.defconfig.cc3235sf @@ -1,13 +1,9 @@ # TI SimpleLink CC3235SF SoC - # Copyright (c) 2019, Texas Instruments Incorporated # SPDX-License-Identifier: Apache-2.0 if SOC_CC3235SF -config SOC - default "cc3235sf" - config NUM_IRQS # must be >= the highest interrupt number used # This includes the NWP interrupt @@ -21,10 +17,12 @@ config ROM_START_OFFSET default 0x0 if !XIP if !XIP + config FLASH_SIZE default 0 config FLASH_BASE_ADDRESS default 0 + endif endif # SOC_CC3235SF diff --git a/soc/ti/simplelink/cc32xx/Kconfig.soc b/soc/ti/simplelink/cc32xx/Kconfig.soc new file mode 100644 index 00000000000000..44cd0123b9443b --- /dev/null +++ b/soc/ti/simplelink/cc32xx/Kconfig.soc @@ -0,0 +1,28 @@ +# TI SimpleLink CC32xx +# SPDX-License-Identifier: Apache-2.0 +# Copyright (c) 2016-2017, Texas Instruments Incorporated + +config SOC_SERIES_CC32XX + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink CC32xx + +config SOC_CC3220SF + bool + select SOC_SERIES_CC32XX + help + CC3220SF + +config SOC_CC3235SF + bool + select SOC_SERIES_CC32XX + help + CC3235SF + +config SOC_SERIES + default "cc32xx" if SOC_SERIES_CC32XX + +config SOC + default "cc3220sf" if SOC_CC3220SF + default "cc3235sf" if SOC_CC3235SF diff --git a/soc/arm/ti_simplelink/cc32xx/README b/soc/ti/simplelink/cc32xx/README similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/README rename to soc/ti/simplelink/cc32xx/README diff --git a/soc/arm/ti_simplelink/cc32xx/cc32xx_debug.ld b/soc/ti/simplelink/cc32xx/cc32xx_debug.ld similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/cc32xx_debug.ld rename to soc/ti/simplelink/cc32xx/cc32xx_debug.ld diff --git a/soc/arm/ti_simplelink/cc32xx/pinctrl_soc.h b/soc/ti/simplelink/cc32xx/pinctrl_soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/pinctrl_soc.h rename to soc/ti/simplelink/cc32xx/pinctrl_soc.h diff --git a/soc/arm/ti_simplelink/cc32xx/soc.c b/soc/ti/simplelink/cc32xx/soc.c similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/soc.c rename to soc/ti/simplelink/cc32xx/soc.c diff --git a/soc/arm/ti_simplelink/cc32xx/soc.h b/soc/ti/simplelink/cc32xx/soc.h similarity index 100% rename from soc/arm/ti_simplelink/cc32xx/soc.h rename to soc/ti/simplelink/cc32xx/soc.h diff --git a/soc/ti/simplelink/msp432p4xx/CMakeLists.txt b/soc/ti/simplelink/msp432p4xx/CMakeLists.txt new file mode 100644 index 00000000000000..537a7cb4287766 --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/CMakeLists.txt @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_compile_definitions(-D__MSP432P401R__) +zephyr_sources(soc.c) +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/ti/simplelink/msp432p4xx/Kconfig b/soc/ti/simplelink/msp432p4xx/Kconfig new file mode 100644 index 00000000000000..9b44c5f34ab830 --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/Kconfig @@ -0,0 +1,14 @@ +# Texas Instruments MSP432P401R +# Copyright (c) 2017, Linaro Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MSP432P4XX + select ARM + select CPU_CORTEX_M4 + select CPU_CORTEX_M_HAS_DWT + select DYNAMIC_INTERRUPTS + select CPU_HAS_FPU + select CPU_HAS_ARM_MPU + +config SOC_MSP432P401R + select HAS_MSP432P4XXSDK diff --git a/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig new file mode 100644 index 00000000000000..449e9fd020b9bc --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig @@ -0,0 +1,9 @@ +# TI SimpleLink MSP432P4XX +# Copyright (c) 2017, Linaro Ltd +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_MSP432P4XX + +rsource "Kconfig.defconfig.msp432p4*" + +endif # SOC_SERIES_MSP432P4XX diff --git a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r similarity index 86% rename from soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r rename to soc/ti/simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r index af491c6b8ad5de..3c984147a6d20e 100644 --- a/soc/arm/ti_simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r +++ b/soc/ti/simplelink/msp432p4xx/Kconfig.defconfig.msp432p401r @@ -1,13 +1,9 @@ # TI SimpleLink MSP432P401R SoC - # Copyright (c) 2017, Linaro Ltd # SPDX-License-Identifier: Apache-2.0 if SOC_MSP432P401R -config SOC - default "msp432p401r" - config SYS_CLOCK_HW_CYCLES_PER_SEC default 48000000 diff --git a/soc/ti/simplelink/msp432p4xx/Kconfig.soc b/soc/ti/simplelink/msp432p4xx/Kconfig.soc new file mode 100644 index 00000000000000..aca5e6b425af3e --- /dev/null +++ b/soc/ti/simplelink/msp432p4xx/Kconfig.soc @@ -0,0 +1,21 @@ +# Texas Instruments MSP432P401R +# Copyright (c) 2017, Linaro Ltd +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_MSP432P4XX + bool + select SOC_FAMILY_TI_SIMPLELINK + help + Enable support for TI SimpleLink MSP432P4XX. + +config SOC_MSP432P401R + bool + select SOC_SERIES_MSP432P4XX + help + MSP432P401R + +config SOC_SERIES + default "msp432p4xx" if SOC_SERIES_MSP432P4XX + +config SOC + default "msp432p401r" if SOC_MSP432P401R diff --git a/soc/arm/ti_simplelink/msp432p4xx/soc.c b/soc/ti/simplelink/msp432p4xx/soc.c similarity index 100% rename from soc/arm/ti_simplelink/msp432p4xx/soc.c rename to soc/ti/simplelink/msp432p4xx/soc.c diff --git a/soc/arm/ti_simplelink/msp432p4xx/soc.h b/soc/ti/simplelink/msp432p4xx/soc.h similarity index 100% rename from soc/arm/ti_simplelink/msp432p4xx/soc.h rename to soc/ti/simplelink/msp432p4xx/soc.h diff --git a/soc/ti/simplelink/soc.yml b/soc/ti/simplelink/soc.yml new file mode 100644 index 00000000000000..2dbf91f315e6fe --- /dev/null +++ b/soc/ti/simplelink/soc.yml @@ -0,0 +1,22 @@ +family: +- name: ti_simplelink + series: + - name: cc13x2_cc26x2 + socs: + - name: cc1352p + - name: cc1352r + - name: cc2652p + - name: cc2652r + - name: cc13x2x7_cc26x2x7 + socs: + - name: cc1352p7 + - name: cc1352r7 + - name: cc2652p7 + - name: cc2652r7 + - name: cc32xx + socs: + - name: cc3220sf + - name: cc3235sf + - name: msp432p4xx + socs: + - name: msp432p401r diff --git a/soc/x86/alder_lake/CMakeLists.txt b/soc/x86/alder_lake/CMakeLists.txt deleted file mode 100644 index 47325b7a8091ff..00000000000000 --- a/soc/x86/alder_lake/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_cc_option(-march=goldmont) - -zephyr_library_sources(cpu.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/alder_lake/Kconfig.defconfig b/soc/x86/alder_lake/Kconfig.defconfig deleted file mode 100644 index c2cd55fc85abeb..00000000000000 --- a/soc/x86/alder_lake/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Alder Lake SoC configuration options - -# Copyright (c) 2018-2023 Intel Corporation -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ALDER_LAKE - -config SOC - default "alder_lake" - -config PCIE_MMIO_CFG - default y - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_ALDER_LAKE diff --git a/soc/x86/alder_lake/Kconfig.soc b/soc/x86/alder_lake/Kconfig.soc deleted file mode 100644 index 1f046e0b92d111..00000000000000 --- a/soc/x86/alder_lake/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2018-2023 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ALDER_LAKE - bool "Intel Alder Lake SOC" - select X86 - select CPU_ATOM - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU diff --git a/soc/x86/apollo_lake/CMakeLists.txt b/soc/x86/apollo_lake/CMakeLists.txt deleted file mode 100644 index 47325b7a8091ff..00000000000000 --- a/soc/x86/apollo_lake/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_cc_option(-march=goldmont) - -zephyr_library_sources(cpu.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/apollo_lake/Kconfig.defconfig b/soc/x86/apollo_lake/Kconfig.defconfig deleted file mode 100644 index a865865b1dd967..00000000000000 --- a/soc/x86/apollo_lake/Kconfig.defconfig +++ /dev/null @@ -1,29 +0,0 @@ -# Apollo Lake SoC configuration options - -# Copyright (c) 2018-2019 Intel Corporation -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_APOLLO_LAKE - -config SOC - default "apollo_lake" - -config PCIE_MMIO_CFG - default y - -if APIC_TIMER - -config APIC_TIMER_IRQ - default 24 - -config APIC_TIMER_TSC - default y - -endif # APIC_TIMER - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_APOLLO_LAKE diff --git a/soc/x86/apollo_lake/Kconfig.soc b/soc/x86/apollo_lake/Kconfig.soc deleted file mode 100644 index 6eae75b8c5ece7..00000000000000 --- a/soc/x86/apollo_lake/Kconfig.soc +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2018 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_APOLLO_LAKE - bool "Intel Apollo Lake Soc" - select X86 - select CPU_APOLLO_LAKE - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU - select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/x86/atom/CMakeLists.txt b/soc/x86/atom/CMakeLists.txt deleted file mode 100644 index 66d55c6ba96466..00000000000000 --- a/soc/x86/atom/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/atom/Kconfig.defconfig b/soc/x86/atom/Kconfig.defconfig deleted file mode 100644 index 743b43465f4305..00000000000000 --- a/soc/x86/atom/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# ATOM SoC configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ATOM - -config SOC - default "atom" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 if HPET_TIMER - -endif diff --git a/soc/x86/atom/Kconfig.soc b/soc/x86/atom/Kconfig.soc deleted file mode 100644 index ac396eec8802e7..00000000000000 --- a/soc/x86/atom/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ATOM - bool "Intel ATOM SoC" - select X86 - select CPU_ATOM - select X86_MMU - select ARCH_HAS_USERSPACE - select ARCH_HAS_RESERVED_PAGE_FRAMES diff --git a/soc/x86/atom/soc.h b/soc/x86/atom/soc.h deleted file mode 100644 index 199820fa7bdb8e..00000000000000 --- a/soc/x86/atom/soc.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2010-2015, Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the ia32 platform - * - * This header file is used to specify and describe board-level aspects for - * the 'ia32' platform. - */ - -#ifndef __SOC_H_ -#define __SOC_H_ - -#include - -#ifndef _ASMLANGUAGE -#include -#include -#endif - -/* PCI definitions */ -/* FIXME: The values below copied from generic ia32 soc, we need to get the - * correct numbers for Atom and the minnowboard - * - * This is added now to get basic enumeration of devices and verify that PCI - * driver is functional. - */ -#define PCI_BUS_NUMBERS 1 - -#define PCI_CTRL_ADDR_REG 0xCF8 -#define PCI_CTRL_DATA_REG 0xCFC - -#define PCI_INTA 1 -#define PCI_INTB 2 -#define PCI_INTC 3 -#define PCI_INTD 4 - -/** - * - * @brief Convert PCI interrupt PIN to IRQ - * - * @return IRQ number, -1 if the result is incorrect - * - */ - -static inline int pci_pin2irq(int bus, int dev, int pin) -{ - ARG_UNUSED(bus); - - if ((pin < PCI_INTA) || (pin > PCI_INTD)) { - return -1; - } - return 10 + (((pin + dev - 1) >> 1) & 1); -} - -#endif /* __SOC_H_ */ diff --git a/soc/x86/elkhart_lake/CMakeLists.txt b/soc/x86/elkhart_lake/CMakeLists.txt deleted file mode 100644 index 47325b7a8091ff..00000000000000 --- a/soc/x86/elkhart_lake/CMakeLists.txt +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_library() -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_cc_option(-march=goldmont) - -zephyr_library_sources(cpu.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/elkhart_lake/Kconfig.defconfig b/soc/x86/elkhart_lake/Kconfig.defconfig deleted file mode 100644 index ba983ea7eb7ecf..00000000000000 --- a/soc/x86/elkhart_lake/Kconfig.defconfig +++ /dev/null @@ -1,19 +0,0 @@ -# Elkhart Lake SoC configuration options - -# Copyright (c) 2018-2020 Intel Corporation -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_ELKHART_LAKE - -config SOC - default "elkhart_lake" - -config PCIE_MMIO_CFG - default y - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_ELKHART_LAKE diff --git a/soc/x86/elkhart_lake/Kconfig.soc b/soc/x86/elkhart_lake/Kconfig.soc deleted file mode 100644 index 26c1139238882c..00000000000000 --- a/soc/x86/elkhart_lake/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2018-2020 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_ELKHART_LAKE - bool "Intel Elkhart Lake Soc" - select X86 - select CPU_ATOM - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU diff --git a/soc/x86/ia32/CMakeLists.txt b/soc/x86/ia32/CMakeLists.txt deleted file mode 100644 index 66d55c6ba96466..00000000000000 --- a/soc/x86/ia32/CMakeLists.txt +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/ia32/Kconfig.defconfig b/soc/x86/ia32/Kconfig.defconfig deleted file mode 100644 index 87600183a20c74..00000000000000 --- a/soc/x86/ia32/Kconfig.defconfig +++ /dev/null @@ -1,14 +0,0 @@ -# Generic PC platform configuration options - -# Copyright (c) 2014-2015 Wind River Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_IA32 - -config SOC - default "ia32" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 25000000 if HPET_TIMER - -endif diff --git a/soc/x86/ia32/Kconfig.soc b/soc/x86/ia32/Kconfig.soc deleted file mode 100644 index d2731afdba36db..00000000000000 --- a/soc/x86/ia32/Kconfig.soc +++ /dev/null @@ -1,9 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -config SOC_IA32 - bool "Generic IA32 SoC" - select X86 - select CPU_ATOM - select X86_CPU_HAS_MMX - select X86_CPU_HAS_SSE - select ARCH_HAS_RESERVED_PAGE_FRAMES if SRAM_BASE_ADDRESS = 0 diff --git a/soc/x86/ia32/soc.h b/soc/x86/ia32/soc.h deleted file mode 100644 index 51da1d1cdf4d36..00000000000000 --- a/soc/x86/ia32/soc.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2010-2015, Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Board configuration macros for the ia32 platform - * - * This header file is used to specify and describe board-level aspects for - * the 'ia32' platform. - */ - -#ifndef __SOC_H_ -#define __SOC_H_ - -#include - -#ifndef _ASMLANGUAGE -#include -#include -#endif - -/* PCI definitions */ -#define PCI_BUS_NUMBERS 1 - -#define PCI_CTRL_ADDR_REG 0xCF8 -#define PCI_CTRL_DATA_REG 0xCFC - -#define PCI_INTA 1 -#define PCI_INTB 2 -#define PCI_INTC 3 -#define PCI_INTD 4 - -/** - * - * @brief Convert PCI interrupt PIN to IRQ - * - * This file is only used by QEMU, which emulates the i440fx chipset. - * INTx are mapped to IRQs 10 and 11 after being swizzled. - * - * @return IRQ number, -1 if the result is incorrect - * - */ - -static inline int pci_pin2irq(int bus, int dev, int pin) -{ - ARG_UNUSED(bus); - - if ((pin < PCI_INTA) || (pin > PCI_INTD)) { - return -1; - } - - return 10 + (((pin + dev - 1) >> 1) & 1); -} - -#endif /* __SOC_H_ */ diff --git a/soc/x86/intel_ish/Kconfig b/soc/x86/intel_ish/Kconfig deleted file mode 100644 index b3865915a2a259..00000000000000 --- a/soc/x86/intel_ish/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Intel ISH family configuration options -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_ISH - bool "Intel ISH SoC family" - select X86 - select X86_NO_SPECULATIVE_VULNERABILITIES - select IOAPIC - select LOAPIC - select CPU_HAS_FPU - select INTEL_HAL - select HAS_PM - select HAS_COVERAGE_SUPPORT diff --git a/soc/x86/intel_ish/Kconfig.defconfig b/soc/x86/intel_ish/Kconfig.defconfig deleted file mode 100644 index adcca64b9a8069..00000000000000 --- a/soc/x86/intel_ish/Kconfig.defconfig +++ /dev/null @@ -1,30 +0,0 @@ -# Intel ISH family default configuration options -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_INTEL_ISH - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 if HPET_TIMER - -config SOC_FAMILY - string - default "intel_ish" - -config X86_VERY_EARLY_CONSOLE - default n - -config SRAM_OFFSET - hex - default 0x0 - -# Target platforms are not PC-compatible -# (e.g. without BIOS, ACPI, CMOS, etc.). -config X86_PC_COMPATIBLE - default n - -endif # SOC_FAMILY_INTEL_ISH - -rsource "*/Kconfig.defconfig.series" diff --git a/soc/x86/intel_ish/Kconfig.soc b/soc/x86/intel_ish/Kconfig.soc deleted file mode 100644 index b4b1e1456b93f3..00000000000000 --- a/soc/x86/intel_ish/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Intel ISH family selection -# -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -rsource "*/Kconfig.series" -rsource "*/Kconfig.soc" diff --git a/soc/x86/intel_ish/intel_ish5/CMakeLists.txt b/soc/x86/intel_ish/intel_ish5/CMakeLists.txt deleted file mode 100644 index 3c253ac264835d..00000000000000 --- a/soc/x86/intel_ish/intel_ish5/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -zephyr_cc_option(-march=pentium -mtune=i486) - -zephyr_sources(soc.c) -add_subdirectory_ifdef(CONFIG_PM pm) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") - -include(../utils/build_ish_firmware.cmake) diff --git a/soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series b/soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series deleted file mode 100644 index fecc6d2428f323..00000000000000 --- a/soc/x86/intel_ish/intel_ish5/Kconfig.defconfig.series +++ /dev/null @@ -1,20 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -if SOC_SERIES_INTEL_ISH5 - -config SOC_SERIES - string - default "intel_ish5" - -config SOC - string - default "intel_ish_5_4_1" if SOC_INTEL_ISH_5_4_1 - default "intel_ish_5_6_0" if SOC_INTEL_ISH_5_6_0 - default "intel_ish_5_8_0" if SOC_INTEL_ISH_5_8_0 - -endif # SOC_SERIES_INTEL_ISH5 - -rsource "pm/Kconfig.pm" diff --git a/soc/x86/intel_ish/intel_ish5/Kconfig.series b/soc/x86/intel_ish/intel_ish5/Kconfig.series deleted file mode 100644 index ef39ee29c20aee..00000000000000 --- a/soc/x86/intel_ish/intel_ish5/Kconfig.series +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -config SOC_SERIES_INTEL_ISH5 - bool "Intel ISH5 SoC" - select SOC_FAMILY_INTEL_ISH diff --git a/soc/x86/intel_ish/intel_ish5/Kconfig.soc b/soc/x86/intel_ish/intel_ish5/Kconfig.soc deleted file mode 100644 index bbc4a76fdae429..00000000000000 --- a/soc/x86/intel_ish/intel_ish5/Kconfig.soc +++ /dev/null @@ -1,19 +0,0 @@ -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 -# - -choice - prompt "Intel ISH5 SoCs" - depends on SOC_SERIES_INTEL_ISH5 - -config SOC_INTEL_ISH_5_4_1 - bool "Intel ISH 5.4.1 SoC" - -config SOC_INTEL_ISH_5_6_0 - bool "Intel ISH 5.6.0 SoC" - -config SOC_INTEL_ISH_5_8_0 - bool "Intel ISH 5.8.0 SoC" - -endchoice diff --git a/soc/x86/lakemont/CMakeLists.txt b/soc/x86/lakemont/CMakeLists.txt deleted file mode 100644 index 4527b084519e34..00000000000000 --- a/soc/x86/lakemont/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -zephyr_cc_option(-march=pentium) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/lakemont/Kconfig.defconfig b/soc/x86/lakemont/Kconfig.defconfig deleted file mode 100644 index 3e21fbe3e00478..00000000000000 --- a/soc/x86/lakemont/Kconfig.defconfig +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_LAKEMONT - -config SOC - default "lakemont" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 32768 - -# Can be enabled once UART is defined in board -# configuration. -config X86_VERY_EARLY_CONSOLE - default n - -# Target platforms are usually not PC-compatible -# (e.g. without BIOS, ACPI, etc.). -config X86_PC_COMPATIBLE - default n - -endif diff --git a/soc/x86/lakemont/Kconfig.soc b/soc/x86/lakemont/Kconfig.soc deleted file mode 100644 index 9a62a2d1e44f4d..00000000000000 --- a/soc/x86/lakemont/Kconfig.soc +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2021 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_LAKEMONT - bool "Intel Lakemont SoC" - select X86 - select CPU_LAKEMONT - select X86_MMU if FPU - select X86_SSE if FPU - select X86_SSE2 if FPU - select X86_SSE3 if FPU - select X86_SSSE3 if FPU - select ARCH_HAS_USERSPACE diff --git a/soc/x86/lakemont/linker.ld b/soc/x86/lakemont/linker.ld deleted file mode 100644 index d77f13846dd48b..00000000000000 --- a/soc/x86/lakemont/linker.ld +++ /dev/null @@ -1,8 +0,0 @@ -/* - * Copyright (c) 2011-2014, Wind River Systems, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include diff --git a/soc/x86/raptor_lake/CMakeLists.txt b/soc/x86/raptor_lake/CMakeLists.txt deleted file mode 100644 index 06c46752f818fb..00000000000000 --- a/soc/x86/raptor_lake/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_cc_option(-march=goldmont) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/x86/raptor_lake/Kconfig.defconfig b/soc/x86/raptor_lake/Kconfig.defconfig deleted file mode 100644 index f9b14da95d027d..00000000000000 --- a/soc/x86/raptor_lake/Kconfig.defconfig +++ /dev/null @@ -1,18 +0,0 @@ -# Raptor Lake SoC configuration options - -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_RAPTOR_LAKE - -config SOC - default "raptor_lake" - -config PCIE_MMIO_CFG - default y - -config X86_DYNAMIC_IRQ_STUBS - default 16 - depends on DYNAMIC_INTERRUPTS - -endif # SOC_RAPTOR_LAKE diff --git a/soc/x86/raptor_lake/Kconfig.soc b/soc/x86/raptor_lake/Kconfig.soc deleted file mode 100644 index b172bc44869428..00000000000000 --- a/soc/x86/raptor_lake/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2022 Intel Corporation Inc. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_RAPTOR_LAKE - bool "Intel Raptor Lake Soc" - select X86 - select CPU_ATOM - select PCIE - select PCIE_MSI - select DYNAMIC_INTERRUPTS - select X86_MMU diff --git a/soc/arm64/xenvm/CMakeLists.txt b/soc/xen/CMakeLists.txt similarity index 100% rename from soc/arm64/xenvm/CMakeLists.txt rename to soc/xen/CMakeLists.txt diff --git a/soc/xen/Kconfig b/soc/xen/Kconfig new file mode 100644 index 00000000000000..966c5fc6ba0fcb --- /dev/null +++ b/soc/xen/Kconfig @@ -0,0 +1,7 @@ +# Copyright 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XENVM + select ARM64 + select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS + select CPU_CORTEX_A72 diff --git a/soc/xen/Kconfig.defconfig b/soc/xen/Kconfig.defconfig new file mode 100644 index 00000000000000..eeb2cf9aa0e49a --- /dev/null +++ b/soc/xen/Kconfig.defconfig @@ -0,0 +1,19 @@ +# Copyright 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +if SOC_XENVM + +config NUM_IRQS + int + default 500 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + int + default 8320000 + +# We need at least 16M of virtual address space to map memory of Xen node +# 32M should be enough for basic use-cases +config KERNEL_VM_SIZE + default 0x2000000 + +endif diff --git a/soc/xen/Kconfig.soc b/soc/xen/Kconfig.soc new file mode 100644 index 00000000000000..654525267495bd --- /dev/null +++ b/soc/xen/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright 2020 EPAM Systems +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XENVM + bool + +config SOC + default "xenvm" if SOC_XENVM diff --git a/soc/arm64/xenvm/mmu_regions.c b/soc/xen/mmu_regions.c similarity index 100% rename from soc/arm64/xenvm/mmu_regions.c rename to soc/xen/mmu_regions.c diff --git a/soc/xen/soc.yml b/soc/xen/soc.yml new file mode 100644 index 00000000000000..c559004e7c64b9 --- /dev/null +++ b/soc/xen/soc.yml @@ -0,0 +1,4 @@ +series: +- name: xenvm + socs: + - name: xenvm diff --git a/soc/arm/xilinx_zynq7000/CMakeLists.txt b/soc/xlnx/zynq7000/CMakeLists.txt similarity index 100% rename from soc/arm/xilinx_zynq7000/CMakeLists.txt rename to soc/xlnx/zynq7000/CMakeLists.txt diff --git a/soc/xlnx/zynq7000/Kconfig b/soc/xlnx/zynq7000/Kconfig new file mode 100644 index 00000000000000..478c5bb4010829 --- /dev/null +++ b/soc/xlnx/zynq7000/Kconfig @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_XILINX_ZYNQ7000 + +rsource "*/Kconfig" + +endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/xlnx/zynq7000/Kconfig.defconfig b/soc/xlnx/zynq7000/Kconfig.defconfig new file mode 100644 index 00000000000000..8976925507fa3d --- /dev/null +++ b/soc/xlnx/zynq7000/Kconfig.defconfig @@ -0,0 +1,27 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_FAMILY_XILINX_ZYNQ7000 + +rsource "*/Kconfig.defconfig" + +config NUM_IRQS + int + # must be >= the highest interrupt number used + default 96 + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config PLATFORM_SPECIFIC_INIT + default y + +endif # SOC_FAMILY_XILINX_ZYNQ7000 diff --git a/soc/xlnx/zynq7000/Kconfig.soc b/soc/xlnx/zynq7000/Kconfig.soc new file mode 100644 index 00000000000000..c925637d7835f6 --- /dev/null +++ b/soc/xlnx/zynq7000/Kconfig.soc @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +config SOC_FAMILY_XILINX_ZYNQ7000 + bool + +config SOC_FAMILY + default "xilinx_zynq7000" if SOC_FAMILY_XILINX_ZYNQ7000 + +rsource "*/Kconfig.soc" diff --git a/soc/arm/xilinx_zynq7000/common/pinctrl_soc.h b/soc/xlnx/zynq7000/common/pinctrl_soc.h similarity index 100% rename from soc/arm/xilinx_zynq7000/common/pinctrl_soc.h rename to soc/xlnx/zynq7000/common/pinctrl_soc.h diff --git a/soc/xlnx/zynq7000/soc.yml b/soc/xlnx/zynq7000/soc.yml new file mode 100644 index 00000000000000..25c5d0f227fcab --- /dev/null +++ b/soc/xlnx/zynq7000/soc.yml @@ -0,0 +1,18 @@ +family: +- name: xilinx_zynq7000 + series: + - name: xc7zxxx + socs: + - name: xc7z010 + - name: xc7z010 + - name: xc7z015 + - name: xc7z020 + - name: xc7z030 + - name: xc7z035 + - name: xc7z045 + - name: xc7z100 + - name: xc7zxxxs + socs: + - name: xc7z007s + - name: xc7z012s + - name: xc7z014s diff --git a/soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt b/soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt new file mode 100644 index 00000000000000..dcdc25a830aa06 --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/xlnx/zynq7000/xc7zxxx/Kconfig b/soc/xlnx/zynq7000/xc7zxxx/Kconfig new file mode 100644 index 00000000000000..7a94994fd8d005 --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/Kconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXX + select ARM + select CPU_CORTEX_A9 + select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER diff --git a/soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig new file mode 100644 index 00000000000000..b7e4f98dfbe20c --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.defconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_XC7ZXXX + +# Zephyr does not support SMP on aarch32 yet, so we default to 1 CPU core +config MP_MAX_NUM_CPUS + default 1 + +endif # SOC_SERIES_XC7ZXXX diff --git a/soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc new file mode 100644 index 00000000000000..6405dc488afe49 --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc @@ -0,0 +1,80 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXX + bool + select SOC_FAMILY_XILINX_ZYNQ7000 + help + Enable support for the Xilinx Zynq-7000 (XC7Zxxx) + SoC series (dual core ARM Cortex-A9). + +config SOC_XILINX_XC7Z010 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, + 28k logic cells, 2.1Mb block RAM, 800 DSP slices, up to 100 I/O pins. + +config SOC_XILINX_XC7Z015 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, + 74k logic cells, 3.3Mb block RAM, 160 DSP slices, up to 150 I/O pins, + up to 4 transceivers. + +config SOC_XILINX_XC7Z020 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 866 MHz, Artix-7 programmable logic, + 85k logic cells, 4.9Mb block RAM, 220 DSP slices, up to 200 I/O pins. + +config SOC_XILINX_XC7Z030 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 125k logic cells, 9.3Mb block RAM, 400 DSP slices, up to 250 I/O pins, + up to 4 transceivers. + +config SOC_XILINX_XC7Z035 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 275k logic cells, 17.6Mb block RAM, 900 DSP slices, up to 362 I/O pins, + up to 16 transceivers. + +config SOC_XILINX_XC7Z045 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 350k logic cells, 19.1Mb block RAM, 900 DSP slices, up to 362 I/O pins, + up to 16 transceivers. + +config SOC_XILINX_XC7Z100 + bool + select SOC_SERIES_XC7ZXXX + help + 2 ARM Cortex-A9 cores up to 1 GHz, Kintex-7 programmable logic, + 444k logic cells, 26.5Mb block RAM, 2020 DSP slices, up to 400 I/O pins, + up to 16 transceivers. + +config SOC_SERIES + default "xc7zxxx" if SOC_SERIES_XC7ZXXX + +config SOC + default "xc7z010" if SOC_XILINX_XC7Z010 + default "xc7z015" if SOC_XILINX_XC7Z015 + default "xc7z020" if SOC_XILINX_XC7Z020 + default "xc7z030" if SOC_XILINX_XC7Z030 + default "xc7z035" if SOC_XILINX_XC7Z035 + default "xc7z045" if SOC_XILINX_XC7Z045 + default "xc7z100" if SOC_XILINX_XC7Z100 diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.c b/soc/xlnx/zynq7000/xc7zxxx/soc.c similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxx/soc.c rename to soc/xlnx/zynq7000/xc7zxxx/soc.c diff --git a/soc/arm/xilinx_zynq7000/xc7zxxx/soc.h b/soc/xlnx/zynq7000/xc7zxxx/soc.h similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxx/soc.h rename to soc/xlnx/zynq7000/xc7zxxx/soc.h diff --git a/soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt b/soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt new file mode 100644 index 00000000000000..dcdc25a830aa06 --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/CMakeLists.txt @@ -0,0 +1,10 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_sources(soc.c) + +zephyr_include_directories(.) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/xlnx/zynq7000/xc7zxxxs/Kconfig b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig new file mode 100644 index 00000000000000..ecac57425fe817 --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig @@ -0,0 +1,12 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXXS + select ARM + select CPU_CORTEX_A9 + select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER diff --git a/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig new file mode 100644 index 00000000000000..6b4c6558c9ae1a --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.defconfig @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# + +if SOC_SERIES_XC7ZXXXS + +config MP_MAX_NUM_CPUS + default 1 + +endif # SOC_SERIES_XC7ZXXXS diff --git a/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc new file mode 100644 index 00000000000000..71a0bf0199190d --- /dev/null +++ b/soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc @@ -0,0 +1,44 @@ +# +# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG +# SPDX-License-Identifier: Apache-2.0 +# +# Device data: comp. +# https://www.xilinx.com/products/silicon-devices/soc/zynq-7000.html#productTable +# + +config SOC_SERIES_XC7ZXXXS + bool + select SOC_FAMILY_XILINX_ZYNQ7000 + help + Enable support for the Xilinx Zynq-7000S (XC7ZxxxS) + SoC series (single core ARM Cortex-A9). + +config SOC_XILINX_XC7Z007S + bool + select SOC_SERIES_XC7ZXXXS + help + 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, + 23k logic cells, 1.8 Mb block RAM, 60 DSP slices, up to 100 I/O pins. + +config SOC_XILINX_XC7Z012S + bool + select SOC_SERIES_XC7ZXXXS + help + 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, + 55k logic cells, 2.5Mb block RAM, 120 DSP slices, up to 150 I/O pins, + up to 4 transceivers. + +config SOC_XILINX_XC7Z014S + bool + select SOC_SERIES_XC7ZXXXS + help + 1 ARM Cortex-A9 core up to 766 MHz, Artix-7 programmable logic, + 65k logic cells, 3.8Mb block RAM, 170 DSP slices, up to 200 I/O pins. + +config SOC_SERIES + default "xc7zxxxs" if SOC_SERIES_XC7ZXXXS + +config SOC + default "xc7z007s" if SOC_XILINX_XC7Z007S + default "xc7z012s" if SOC_XILINX_XC7Z012S + default "xc7z014s" if SOC_XILINX_XC7Z014S diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c b/soc/xlnx/zynq7000/xc7zxxxs/soc.c similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxxs/soc.c rename to soc/xlnx/zynq7000/xc7zxxxs/soc.c diff --git a/soc/arm/xilinx_zynq7000/xc7zxxxs/soc.h b/soc/xlnx/zynq7000/xc7zxxxs/soc.h similarity index 100% rename from soc/arm/xilinx_zynq7000/xc7zxxxs/soc.h rename to soc/xlnx/zynq7000/xc7zxxxs/soc.h diff --git a/soc/xlnx/zynqmp/CMakeLists.txt b/soc/xlnx/zynqmp/CMakeLists.txt new file mode 100644 index 00000000000000..70885608559b36 --- /dev/null +++ b/soc/xlnx/zynqmp/CMakeLists.txt @@ -0,0 +1,17 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# +# SPDX-License-Identifier: Apache-2.0 + +zephyr_sources( + soc.c +) +zephyr_sources_ifdef( + CONFIG_ARM_MPU + arm_mpu_regions.c +) + +zephyr_include_directories(.) + +if(CONFIG_SOC_XILINX_ZYNQMP_RPU) + set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "") +endif() diff --git a/soc/xlnx/zynqmp/Kconfig b/soc/xlnx/zynqmp/Kconfig new file mode 100644 index 00000000000000..f28454573c6f9b --- /dev/null +++ b/soc/xlnx/zynqmp/Kconfig @@ -0,0 +1,10 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# Copyright (c) 2019 Stephanos Ioannidis +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XILINX_ZYNQMP_RPU + select ARM + select CPU_CORTEX_R5 + select PLATFORM_SPECIFIC_INIT + select CPU_HAS_ARM_MPU + select VFP_DP_D16 diff --git a/soc/xlnx/zynqmp/Kconfig.defconfig b/soc/xlnx/zynqmp/Kconfig.defconfig new file mode 100644 index 00000000000000..869f4403d32021 --- /dev/null +++ b/soc/xlnx/zynqmp/Kconfig.defconfig @@ -0,0 +1,28 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# Copyright (c) 2019 Stephanos Ioannidis +# SPDX-License-Identifier: Apache-2.0 + +if SOC_XILINX_ZYNQMP + +if SOC_XILINX_ZYNQMP_RPU + +config NUM_IRQS + # must be >= the highest interrupt number used + # - include the UART interrupts + default 220 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 5000000 + +endif # SOC_XILINX_ZYNQMP_RPU + +# Workaround for not being able to have commas in macro arguments +DT_CHOSEN_Z_FLASH := zephyr,flash + +config FLASH_SIZE + default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) + +config FLASH_BASE_ADDRESS + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +endif # SOC_XILINX_ZYNQMP diff --git a/soc/xlnx/zynqmp/Kconfig.soc b/soc/xlnx/zynqmp/Kconfig.soc new file mode 100644 index 00000000000000..136e1d1f1a078f --- /dev/null +++ b/soc/xlnx/zynqmp/Kconfig.soc @@ -0,0 +1,18 @@ +# Copyright (c) 2019 Lexmark International, Inc. +# Copyright (c) 2019 Stephanos Ioannidis +# SPDX-License-Identifier: Apache-2.0 + +config SOC_XILINX_ZYNQMP + bool + +config SOC_XILINX_ZYNQMP_RPU + bool + select SOC_XILINX_ZYNQMP + help + Xilinx ZynqMP RPU + +config SOC_FAMILY + default "xilinx_zynqmp" if SOC_XILINX_ZYNQMP + +config SOC + default "zynqmp_rpu" if SOC_XILINX_ZYNQMP_RPU diff --git a/soc/arm/xilinx_zynqmp/arm_mpu_regions.c b/soc/xlnx/zynqmp/arm_mpu_regions.c similarity index 100% rename from soc/arm/xilinx_zynqmp/arm_mpu_regions.c rename to soc/xlnx/zynqmp/arm_mpu_regions.c diff --git a/soc/arm/xilinx_zynqmp/pinctrl_soc.h b/soc/xlnx/zynqmp/pinctrl_soc.h similarity index 100% rename from soc/arm/xilinx_zynqmp/pinctrl_soc.h rename to soc/xlnx/zynqmp/pinctrl_soc.h diff --git a/soc/arm/xilinx_zynqmp/soc.c b/soc/xlnx/zynqmp/soc.c similarity index 100% rename from soc/arm/xilinx_zynqmp/soc.c rename to soc/xlnx/zynqmp/soc.c diff --git a/soc/arm/xilinx_zynqmp/soc.h b/soc/xlnx/zynqmp/soc.h similarity index 100% rename from soc/arm/xilinx_zynqmp/soc.h rename to soc/xlnx/zynqmp/soc.h diff --git a/soc/xlnx/zynqmp/soc.yml b/soc/xlnx/zynqmp/soc.yml new file mode 100644 index 00000000000000..e1a20c4a5efb54 --- /dev/null +++ b/soc/xlnx/zynqmp/soc.yml @@ -0,0 +1,4 @@ +family: +- name: xilinx_zynqmp + socs: + - name: zynqmp_rpu diff --git a/soc/xtensa/CMakeLists.txt b/soc/xtensa/CMakeLists.txt deleted file mode 100644 index b826da926caf12..00000000000000 --- a/soc/xtensa/CMakeLists.txt +++ /dev/null @@ -1,7 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if(SOC_FAMILY) - add_subdirectory(${SOC_FAMILY}) -else() - add_subdirectory(${SOC_NAME}) -endif() diff --git a/soc/xtensa/dc233c/Kconfig.defconfig b/soc/xtensa/dc233c/Kconfig.defconfig deleted file mode 100644 index dc5be860b4a55d..00000000000000 --- a/soc/xtensa/dc233c/Kconfig.defconfig +++ /dev/null @@ -1,32 +0,0 @@ -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# Copyright (c) 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XTENSA_DC233C - -config SOC - default "dc233c" - -config SOC_TOOLCHAIN_NAME - string - default "dc233c" - -config XTENSA_MMU_NUM_L2_TABLES - int - default 48 if XTENSA_MMU - -# Both SRAM_OFFSET and KERNEL_VM_OFFSET are set at 1MB. -# This is to allow VECBASE to be mapped permanently -# via TLB way 4 (which covers 1MB). -config SRAM_OFFSET - hex - default 0x100000 if XTENSA_MMU - default 0x2400 - -config KERNEL_VM_OFFSET - hex - default 0x100000 - -endif diff --git a/soc/xtensa/dc233c/Kconfig.soc b/soc/xtensa/dc233c/Kconfig.soc deleted file mode 100644 index ecbe77a9febb14..00000000000000 --- a/soc/xtensa/dc233c/Kconfig.soc +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2017, 2023 Intel Corporation -# -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XTENSA_DC233C - bool "Xtensa dc233c core" - select XTENSA - select XTENSA_HAL - select ARCH_HAS_THREAD_LOCAL_STORAGE - select CPU_HAS_DCACHE - select CPU_HAS_ICACHE - select CPU_HAS_MMU - select ARCH_HAS_RESERVED_PAGE_FRAMES if XTENSA_MMU - select ARCH_HAS_USERSPACE if XTENSA_MMU - select XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP if XTENSA_MMU diff --git a/soc/xtensa/espressif_esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/CMakeLists.txt deleted file mode 100644 index 31ef76aadeef99..00000000000000 --- a/soc/xtensa/espressif_esp32/CMakeLists.txt +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(${SOC_SERIES}) -add_subdirectory(common) diff --git a/soc/xtensa/espressif_esp32/Kconfig b/soc/xtensa/espressif_esp32/Kconfig deleted file mode 100644 index 31e176291ab8bc..00000000000000 --- a/soc/xtensa/espressif_esp32/Kconfig +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_ESP32 - bool - -if SOC_FAMILY_ESP32 - -config SOC_FAMILY - string - default "espressif_esp32" - -source "soc/xtensa/espressif_esp32/common/Kconfig.soc" -source "soc/xtensa/espressif_esp32/*/Kconfig.soc" - -endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/Kconfig.defconfig b/soc/xtensa/espressif_esp32/Kconfig.defconfig deleted file mode 100644 index fedabb82b8c749..00000000000000 --- a/soc/xtensa/espressif_esp32/Kconfig.defconfig +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series" -source "soc/xtensa/espressif_esp32/*/Kconfig.defconfig.series" diff --git a/soc/xtensa/espressif_esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/Kconfig.soc deleted file mode 100644 index 6b28e800868952..00000000000000 --- a/soc/xtensa/espressif_esp32/Kconfig.soc +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/espressif_esp32/*/Kconfig.series" diff --git a/soc/xtensa/espressif_esp32/common/CMakeLists.txt b/soc/xtensa/espressif_esp32/common/CMakeLists.txt deleted file mode 100644 index e097e8ce4eec43..00000000000000 --- a/soc/xtensa/espressif_esp32/common/CMakeLists.txt +++ /dev/null @@ -1,4 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) diff --git a/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series deleted file mode 100644 index 771976bc66d53c..00000000000000 --- a/soc/xtensa/espressif_esp32/common/Kconfig.defconfig.series +++ /dev/null @@ -1,44 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -# Xtensa default options for ESP32 family -config XTENSA_RESET_VECTOR - default n - -config XTENSA_USE_CORE_CRT1 - default n - -config GEN_ISR_TABLES - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -config CLOCK_CONTROL - default y - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -if BOOTLOADER_MCUBOOT - - config HAS_FLASH_LOAD_OFFSET - default y - config MCUBOOT_GENERATE_UNSIGNED_IMAGE - default y - config MCUBOOT_GENERATE_CONFIRMED_IMAGE - default y - config ROM_START_OFFSET - default 0x20 - -endif # BOOTLOADER_MCUBOOT - -endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/common/Kconfig.soc b/soc/xtensa/espressif_esp32/common/Kconfig.soc deleted file mode 100644 index c8eaad62d5b573..00000000000000 --- a/soc/xtensa/espressif_esp32/common/Kconfig.soc +++ /dev/null @@ -1,215 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_ESP32 - -config ESPTOOLPY_FLASHFREQ_80M - bool - -config FLASH_SIZE - int - -config FLASH_BASE_ADDRESS - hex - -config ESP_SPIRAM - bool "Support for external, SPI-connected RAM" - help - This enables support for an external SPI RAM chip, connected in - parallel with the main SPI flash chip. - -config ESP_HEAP_MIN_EXTRAM_THRESHOLD - int "Minimum threshold for external RAM allocation" - default 8192 - range 1024 131072 - depends on ESP_SPIRAM - help - Threshold to decide if memory will be allocated from DRAM - or SPIRAM. If value of allocation size is less than this value, - memory will be allocated from internal RAM. - -config ESP_HEAP_SEARCH_ALL_REGIONS - bool "Search for all available heap regions" - depends on ESP_SPIRAM - default y - help - This configuration enables searching all available heap - regions. If the region of desired capability is exhausted, - memory will be allocated from other available region. - -config ESP_SPIRAM_HEAP_SIZE - int "Size of SPIRAM heap" - default 262134 if SYS_HEAP_SMALL_ONLY - default 1048576 if !SYS_HEAP_SMALL_ONLY - depends on ESP_SPIRAM - help - Specify size of SPIRAM heap. - -menu "SPI RAM config" - depends on ESP_SPIRAM - -choice SPIRAM_MODE - prompt "Mode (QUAD/OCT) of SPI RAM chip in use" - default SPIRAM_MODE_QUAD - -config SPIRAM_MODE_QUAD - bool "Quad Mode PSRAM" - -endchoice # SPIRAM_MODE - -choice SPIRAM_TYPE - prompt "Type of SPI RAM chip in use" - depends on ESP_SPIRAM - default SPIRAM_TYPE_ESPPSRAM16 - -config SPIRAM_TYPE_ESPPSRAM16 - bool "ESP-PSRAM16 or APS1604" - -config SPIRAM_TYPE_ESPPSRAM32 - bool "ESP-PSRAM32 or IS25WP032" - -config SPIRAM_TYPE_ESPPSRAM64 - bool "ESP-PSRAM64 or LY68L6400" - -endchoice # SPIRAM_TYPE - -config ESP_SPIRAM_SIZE - int "Size of SPIRAM part" - default 2097152 if SPIRAM_TYPE_ESPPSRAM16 - default 4194304 if SPIRAM_TYPE_ESPPSRAM32 - default 8388608 if SPIRAM_TYPE_ESPPSRAM64 - help - Specify size of SPIRAM part. - NOTE: If SPIRAM size is greater than 4MB, only - lower 4MB can be allocated using k_malloc(). - -choice SPIRAM_SPEED - prompt "Set RAM clock speed" - default SPIRAM_SPEED_40M - help - Select the speed for the SPI RAM chip. - If SPI RAM is enabled, we only support three combinations of SPI speed mode we supported now: - - 1. Flash SPI running at 40MHz and RAM SPI running at 40MHz - 2. Flash SPI running at 80MHz and RAM SPI running at 40MHz - 3. Flash SPI running at 80MHz and RAM SPI running at 80MHz - - Note: If the third mode(80MHz+80MHz) is enabled for SPI RAM of type 32MBit, one of the HSPI/VSPI host - will be occupied by the system. Which SPI host to use can be selected by the config item - SPIRAM_OCCUPY_SPI_HOST. Application code should never touch HSPI/VSPI hardware in this case. The - option to select 80MHz will only be visible if the flash SPI speed is also 80MHz. - (ESPTOOLPY_FLASHFREQ_79M is true) - -config SPIRAM_SPEED_26M - bool "26MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_20M - bool "20MHz clock speed" - depends on SOC_SERIES_ESP32S2 - -config SPIRAM_SPEED_40M - bool "40MHz clock speed" - -config SPIRAM_SPEED_80M - depends on ESPTOOLPY_FLASHFREQ_80M - bool "80MHz clock speed" - -config SPIRAM_SPEED_120M - depends on SPIRAM_MODE_QUAD && SOC_SERIES_ESP32S3 - bool "120MHz clock speed" - -endchoice # SPIRAM_SPEED - -menu "PSRAM clock and cs IO for ESP32-DOWD" - -config D0WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 17 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D0WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 16 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. If user use - 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-DOWD - -menu "PSRAM clock and cs IO for ESP32-D2WD" - -config D2WD_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 9 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -config D2WD_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram, - so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17. - -endmenu # PSRAM clock and cs IO for ESP32-D2WD - -menu "PSRAM clock and cs IO for ESP32-PICO" - -config PICO_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 10 - help - The PSRAM CS IO can be any unused GPIO, user can config it based on hardware design. - - For ESP32-PICO chip, the psram share clock with flash, so user do not need to configure the clock - IO. - For the reference hardware design, please refer to - https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf - -endmenu # PSRAM clock and cs IO for ESP32-PICO - -config SPIRAM_CUSTOM_SPIWP_SD3_PIN - bool "Use custom SPI PSRAM WP(SD3) Pin when flash pins set in eFuse (read help)" - default y if SPIRAM_SPIWP_SD3_PIN != 7 # backwards compatibility, can remove in IDF 5 - default n - help - This setting is only used if the SPI flash pins have been overridden by setting the eFuses - SPI_PAD_CONFIG_xxx, and the SPI flash mode is DIO or DOUT. - - When this is the case, the eFuse config only defines 3 of the 4 Quad I/O data pins. The WP pin (aka - ESP32 pin "SD_DATA_3" or SPI flash pin "IO2") is not specified in eFuse. The psram only has QPI - mode, so a WP pin setting is necessary. - - If this config item is set to N (default), the correct WP pin will be automatically used for any - Espressif chip or module with integrated flash. If a custom setting is needed, set this config item - to Y and specify the GPIO number connected to the WP pin. - - When flash mode is set to QIO or QOUT, the PSRAM WP pin will be set the same as the SPI Flash WP pin - configured in the bootloader. - -config SPIRAM_SPIWP_SD3_PIN - int "Custom SPI PSRAM WP(SD3) Pin" - range 0 33 - default 7 - help - The option "Use custom SPI PSRAM WP(SD3) pin" must be set or this value is ignored - - If burning a customized set of SPI flash pins in eFuse and using DIO or DOUT mode for flash, set this - value to the GPIO number of the SPIRAM WP pin. - -config SPIRAM - bool - default y - -endmenu # SPI RAM config - -endif # SOC_FAMILY_ESP32 diff --git a/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt deleted file mode 100644 index c71c016a706ed9..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32/CMakeLists.txt +++ /dev/null @@ -1,123 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if (CONFIG_SOC_ESP32_APPCPU) - zephyr_sources(soc_appcpu.c) -else() - zephyr_sources( - soc.c - loader.c - esp32-mp.c - ) -endif() - -zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) - -zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -## When building for APPCPU -if (CONFIG_SOC_ESP32_APPCPU) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py - ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c - -a "esp32_appcpu_fw_array") - endif() - -else() - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - # get code-partition slot0 address - dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") - dt_reg_addr(img_0_off PATH ${dts_partition_path}) - - # get code-partition boot address - dt_nodelabel(dts_partition_path NODELABEL "boot_partition") - dt_reg_addr(boot_off PATH ${dts_partition_path}) - - board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") -endif() - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -elseif(CONFIG_SOC_ESP32_APPCPU) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series deleted file mode 100644 index 50a7e9e8124f0a..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32/Kconfig.defconfig.series +++ /dev/null @@ -1,49 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32 - -config SOC_SERIES - default "esp32" - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@3ff42000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@3ff42000/flash@0) - -if SMP - -config SCHED_IPI_SUPPORTED - default y - -config SCHED_CPU_MASK - default y - -config MP_MAX_NUM_CPUS - default 2 - -endif # SMP config - -if GDBSTUB - -# ESP32 GDB expects 420 bytes G-packet. -# So double for hexadecimal digits. -config GDBSTUB_BUF_SZ - default 840 if GDBSTUB - -endif # GDBSTUB config - -endif # SOC_SERIES_ESP32 config diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.series b/soc/xtensa/espressif_esp32/esp32/Kconfig.series deleted file mode 100644 index 858386e4fd089a..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32/Kconfig.series +++ /dev/null @@ -1,33 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32 - bool "ESP32 Series" - select XTENSA - select SOC_FAMILY_ESP32 - select CLOCK_CONTROL - select DYNAMIC_INTERRUPTS - select ARCH_HAS_GDBSTUB - select ARCH_SUPPORTS_COREDUMP - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select CPU_HAS_FPU - select HAS_PM - select HAS_POWEROFF - help - Enable support for Espressif ESP32 - -config SOC_ESP32_PROCPU - bool "Application runs in ESP32 PROCPU (core 0)" - depends on SOC_SERIES_ESP32 - help - When this SOC is enabled, it will run application on PROCPU (core 0). It will automatically - enable AMP support by building, flashing and loading APPCPU (core 1) image if exists. - -config SOC_ESP32_APPCPU - bool "Application runs in ESP32 APPCPU (core 1)" - depends on SOC_SERIES_ESP32 - help - When this SOC is enabled, it will run application on APPCPU (core 1). It is expected that - there is another image running on PROCPU (core 0) to trigger the AMP support. diff --git a/soc/xtensa/espressif_esp32/esp32/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32/Kconfig.soc deleted file mode 100644 index 6b53076770391f..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32/Kconfig.soc +++ /dev/null @@ -1,281 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32 - -config IDF_TARGET_ESP32 - bool "ESP32 as target board" - default y - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32" - -choice SOC_PART_NUMBER - prompt "ESP32 SOC/SIP Selection" - - # SoC with/without embedded flash - config SOC_ESP32_D0WD_V3 - bool "ESP32_D0WD_V3" - config SOC_ESP32_D0WDR2_V3 - bool "ESP32_D0WDR2_V3" - config SOC_ESP32_U4WDH - bool "ESP32_U4WDH" - config SOC_ESP32_PICO_V3 - bool "ESP32_PICO_V3" - config SOC_ESP32_PICO_V3_02 - bool "ESP32_PICO_V3_02" - config SOC_ESP32_PICO_D4 - bool "ESP32_PICO_D4" - # SiP with external flash / psram - config SOC_ESP32_WROOM_DA_N4 - bool "ESP32_WROOM_DA_N4" - config SOC_ESP32_WROOM_DA_N8 - bool "ESP32_WROOM_DA_N8" - config SOC_ESP32_WROOM_DA_N16 - bool "ESP32_WROOM_DA_N16" - config SOC_ESP32_WROOM_32UE_N4 - bool "ESP32_WROOM_32UE_N4" - config SOC_ESP32_WROOM_32UE_N8 - bool "ESP32_WROOM_32UE_N8" - config SOC_ESP32_WROOM_32UE_N16 - bool "ESP32_WROOM_32UE_N16" - config SOC_ESP32_WROVER_E_N4R2 - bool "ESP32_WROVER_E_N4R2" - config SOC_ESP32_WROVER_E_N8R2 - bool "ESP32_WROVER_E_N8R2" - config SOC_ESP32_WROVER_E_N16R2 - bool "ESP32_WROVER_E_N16R2" - config SOC_ESP32_WROVER_E_N4R8 - bool "ESP32_WROVER_E_N4R8" - config SOC_ESP32_WROVER_E_N8R8 - bool "ESP32_WROVER_E_N8R8" - config SOC_ESP32_WROVER_E_N16R8 - bool "ESP32_WROVER_E_N16R8" - -endchoice # SOC_PART_NUMBER - -config ESP32_APPCPU_IRAM - hex "ESP32 APPCPU IRAM size" - depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU - default 0x20000 - help - Defines APPCPU IRAM area in bytes. - -config ESP32_APPCPU_DRAM - hex "ESP32 APPCPU DRAM size" - depends on SOC_ESP32_PROCPU || SOC_ESP32_APPCPU - default 0x10000 - help - Defines APPCPU DRAM area in bytes. - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -config ESP32_BT_RESERVE_DRAM - hex "Bluetooth controller reserved RAM region" - default 0xdb5c if BT - default 0 - -config ESP_HEAP_MEM_POOL_REGION_1_SIZE - int "Internal DRAM region 1 mempool size" - default 0 if MCUBOOT - default 1024 if SOC_ESP32_PROCPU - default 49152 - help - ESP32 has two banks of size 192K and 128K which can be used - as DRAM, system heap allocates area from region 0. - This configuration can be used to add memory from region 1 - to heap and can be allocated using k_malloc. - -choice ESP32_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 150kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8.5MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 150kHz oscillator. It does not require external components. - -config ESP32_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - -config ESP32_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" - -endchoice # ESP32_RTC_CLK_SRC - -config ESP32_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32_RTC_CLK_SRC_EXT_CRYS || ESP32_RTC_CLK_SRC_EXT_OSC || ESP32_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -config ESP32_RTC_XTAL_CAL_RETRY - int "Number of attempts to repeat 32k XTAL calibration" - default 1 - depends on ESP32_RTC_CLK_SRC_EXT_CRYS - help - Number of attempts to repeat 32k XTAL calibration - before giving up and switching to the internal RC. - Increase this option if the 32k crystal oscillator - does not start and switches to internal RC. - -config ESP32_DEEP_SLEEP_WAKEUP_DELAY - int "Extra delay in deep sleep wake stub (in us)" - default 2000 - range 0 5000 - help - When ESP32 exits deep sleep, the CPU and the flash chip are powered on - at the same time. CPU will run deep sleep stub first, and then - proceed to load code from flash. Some flash chips need sufficient - time to pass between power on and first read operation. By default, - without any extra delay, this time is approximately 900us, although - some flash chip types need more than that. - - By default extra delay is set to 2000us. When optimizing startup time - for applications which require it, this value may be reduced. - - If you are seeing "flash read err, 1000" message printed to the - console after deep sleep reset, try increasing this value. - -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi/BLE TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -config ESP32_EMAC - bool - default y if ETH_ESP32 - default y if MDIO_ESP32 - default n - help - Hidden option to enable the ESP32 Ethernet MAC driver. - Both Ethernet and MDIO depend on this driver. - This option allows enabling MDIO independently of Ethernet. - -if ESP32_EMAC - -config ETH_DMA_BUFFER_SIZE - int "Ethernet DMA buffer size (Byte)" - range 256 1600 - default 512 - help - Set the size of each buffer used by Ethernet MAC DMA. - -config ETH_DMA_RX_BUFFER_NUM - int "Amount of Ethernet DMA Rx buffers" - range 3 30 - default 10 - help - Number of DMA receive buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. - Larger number of buffers could increase throughput somehow. - -config ETH_DMA_TX_BUFFER_NUM - int "Amount of Ethernet DMA Tx buffers" - range 3 30 - default 10 - help - Number of DMA transmit buffers. Each buffer's size is ETH_DMA_BUFFER_SIZE. - Larger number of buffers could increase throughput somehow. - -endif # ESP32_EMAC config - -endif # SOC_SERIES_ESP32 config diff --git a/soc/xtensa/espressif_esp32/esp32/default.ld b/soc/xtensa/espressif_esp32/esp32/default.ld deleted file mode 100644 index d0eb9b46f4ae4c..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32/default.ld +++ /dev/null @@ -1,583 +0,0 @@ -/* - * Copyright (c) 2016 Cadence Design Systems, Inc. - * Copyright (c) 2017 Intel Corporation - * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the Xtensa platform. - */ - -#include -#include -#include -#include - -#define RAMABLE_REGION dram0_0_seg -#ifndef CONFIG_SOC_ESP32_PROCPU -#define RAMABLE_REGION_1 dram0_1_seg -#else -#define RAMABLE_REGION_1 dram0_0_seg -#endif -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define FLASH_CODE_REGION irom0_0_seg - -#define ROMABLE_REGION ROM - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE -#else -#define FLASH_SIZE 0x400000 -#endif - -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x400D0020 -#define IROM_SEG_LEN FLASH_SIZE-0x20 -#define IROM_SEG_ALIGN 0x4 -#else -#define IROM_SEG_ORG 0x400D0000 -#define IROM_SEG_LEN FLASH_SIZE -#define IROM_SEG_ALIGN 0x10000 -#endif -#define IRAM_SEG_LEN 0x20000 - -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. - * Executing directly from LMA is not possible. */ -#undef GROUP_ROM_LINK_IN -#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion - -MEMORY -{ - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 - - #ifdef CONFIG_SOC_ESP32_PROCPU - iram0_0_seg(RX): org = 0x40080000, len = 0x08000 - #else - iram0_0_seg(RX): org = 0x40080000, len = IRAM_SEG_LEN - #endif - - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - /* - * Following is DRAM memory split with reserved address ranges in ESP32: - * - * 0x3FFA_E000 - 0x3FFB_0000 (Reserved: data memory for ROM functions) - * 0x3FFB_0000 - 0x3FFE_0000 (RAM bank 1 for application usage) - * 0x3FFE_0000 - 0x3FFE_0440 (Reserved: data memory for ROM PRO CPU) - * 0x3FFE_3F20 - 0x3FFE_4350 (Reserved: data memory for ROM APP CPU) - * 0x3FFE_4350 - 0x3F10_0000 (RAM bank 2 for application usage) - * - * FIXME: - * - Utilize available memory regions to full capacity - */ - dram0_0_seg(RW): org = 0x3FFB0000 + CONFIG_ESP32_BT_RESERVE_DRAM, len = 0x2c200 - CONFIG_ESP32_BT_RESERVE_DRAM - - #ifdef CONFIG_SOC_ESP32_PROCPU - dram0_shm0_seg(RW): org = 0x3FFE5230, len = 2K /* shared RAM reserved for IPM */ - dram0_sem0_seg(RW): org = 0x3FFE5A30, len = 8 /* shared data reserved for IPM data header */ - dram0_1_seg(RW): org = 0x3FFE5A38, len = 0K /* for AMP builds dram0_1 is reserved for network core */ - #else - dram0_1_seg(RW): org = 0x3FFE5230, len = 0x1BCB0 - 0xEE0 /* skip data for APP CPU initialization usage */ - #endif - - /* DROM is the first segment placed in generated binary. - * MCUboot binary for ESP32 has image header of 0x20 bytes. - * Additional load header of 0x20 bytes are appended to the image. - * Hence, an offset of 0x40 is added to DROM segment origin. - */ - drom0_0_seg(R): org = 0x3F400040, len = 0x400000 - 0x40 - rtc_iram_seg(RWX): org = 0x400C0000, len = 0x2000 - rtc_slow_seg(RW): org = 0x50000000, len = 0x1000 -#if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RW): org = 0x3F800000, len = CONFIG_ESP_SPIRAM_SIZE -#endif -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 -#endif -} - -/* Default entry point: */ -PROVIDE ( _ResetVector = 0x40000400 ); -ENTRY(CONFIG_KERNEL_ENTRY) - -_rom_store_table = 0; - -PROVIDE(_memmap_vecbase_reset = 0x40000450); -PROVIDE(_memmap_reset_vector = 0x40000400); - -SECTIONS -{ - /* Reserve space for MCUboot header in the binary */ - .mcuboot_header : - { - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - } > mcuboot_hdr - .metadata : - { - /* Magic byte for load header */ - LONG(0xace637d3) - - /* Application entry point address */ - KEEP(*(.entry_addr)) - - /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region - */ - - LONG(ADDR(.iram0.vectors)) - LONG(LOADADDR(.iram0.vectors)) - LONG(LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - LOADADDR(.iram0.vectors)) - - /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region - */ - - LONG(ADDR(.dram0.data)) - LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) - } > metadata - -#include - - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); - - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. - */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) - { - __rodata_region_start = ABSOLUTE(.); - - . = ALIGN(4); - #include - - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libdrivers__flash.a:esp32_mp.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__flash.a:flash_esp32.* *libdrivers__serial.a:uart_esp32.* *libzephyr.a:spi_flash_rom_patch.*) .rodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - #include - #include - #include - #include - - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,) - { - . = ALIGN(4); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - _image_dram_start = LOADADDR(.dram0.data); - _image_dram_size = LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - _image_dram_start; - _image_dram_vaddr = ADDR(.dram0.data); - - .dram0.data : - { - __data_start = ABSOLUTE(.); - - _btdm_data_start = ABSOLUTE(.); - *libbtdm_app.a:(.data .data.*) - . = ALIGN (4); - _btdm_data_end = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - /* rodata for panic handler(libarch__xtensa__core.a) and all - * dependent functions should be placed in DRAM to avoid issue - * when flash cache is disabled */ - *libarch__xtensa__core.a:(.rodata .rodata.*) - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - - /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ - #pragma push_macro("GROUP_ROM_LINK_IN") - #undef GROUP_ROM_LINK_IN - #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN - #include - #pragma pop_macro("GROUP_ROM_LINK_IN") - - .dram0.end : - { - . = ALIGN(4); - #include - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - _image_iram_start = LOADADDR(.iram0.vectors); - _image_iram_size = LOADADDR(_TEXT_SECTION_NAME) + SIZEOF(_TEXT_SECTION_NAME) - _image_iram_start; - _image_iram_vaddr = ADDR(.iram0.vectors); - - /* Send .iram0 code to iram */ - .iram0.vectors : ALIGN(4) - { - /* Vectors go to IRAM */ - _init_start = ABSOLUTE(.); - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - . = 0x0; - KEEP(*(.WindowVectors.text)); - . = 0x180; - KEEP(*(.Level2InterruptVector.text)); - . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); - . = 0x200; - KEEP(*(.Level4InterruptVector.text)); - . = 0x240; - KEEP(*(.Level5InterruptVector.text)); - . = 0x280; - KEEP(*(.DebugExceptionVector.text)); - . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); - . = 0x300; - KEEP(*(.KernelExceptionVector.text)); - . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); - . = 0x400; - *(.*Vector.literal) - - *(.UserEnter.literal); - *(.UserEnter.text); - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - - /* This goes here, not at top of linker script, so addr2line finds it last, - and uses it in preference to the first symbol in IRAM */ - _iram_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - SECTION_PROLOGUE(_TEXT_SECTION_NAME, , ALIGN(4)) - { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) - *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) - *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) - *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) - *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) - *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) - *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) - *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) - *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:loader.*(.literal .text .literal.* .text.*) - *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) - *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) - *libphy.a:( .phyiram .phyiram.*) - *libgcov.a:(.literal .text .literal.* .text.*) - -#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - _iram_text_end = ABSOLUTE(.); - . = ALIGN(4); - _iram_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - /* RTC fast memory holds RTC wake stub code, - including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - *rtc_wake_stub*.o(.literal .text .literal.* .text.*) - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - /* RTC slow memory holds RTC wake stub - data/rodata, including from any source file - named rtc_wake_stub*.c - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.o(.bss .bss.*) - *rtc_wake_stub*.o(COMMON) - _rtc_bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(rtc_slow_seg) - - /* This section located in RTC SLOW Memory area. - It holds data marked with RTC_SLOW_ATTR attribute. - See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } > rtc_slow_seg - - /* Get size of rtc slow data */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); - -#if defined(CONFIG_ESP_SPIRAM) - .ext_ram.bss (NOLOAD): - { - _ext_ram_data_start = ABSOLUTE(.); - -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - - *(.ext_ram.bss*) - - _ext_ram_data_end = ABSOLUTE(.); - } GROUP_LINK_IN(ext_ram_seg) -#endif - - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); /* required by bluetooth library */ - __bss_start = ABSOLUTE(.); - - _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); - _btdm_bss_end = ABSOLUTE(.); - - /* Buffer for system heap should be placed in dram0_0_seg */ - *libkernel.a:mempool.*(.noinit.kheap_buf__system_heap .noinit.*.kheap_buf__system_heap) - - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - _end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), - "DRAM segment data does not fit.") - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN (8); - *(.noinit) - *(.noinit.*) - . = ALIGN (8); - } GROUP_LINK_IN(RAMABLE_REGION_1) - - _image_irom_start = LOADADDR(.flash.text); - _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; - _image_irom_vaddr = ADDR(.flash.text); - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - -#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - *(.literal .text .literal.* .text.*) - . = ALIGN(4); - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - resolved by addr2line in preference to the first symbol in - the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - -_heap_sentry = 0x3ffe3f20; - -#include - - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif - -} - -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), - "IRAM0 segment data does not fit.") - -#if defined(CONFIG_ESP_SPIRAM) -ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), - "External SPIRAM overflowed.") -#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32/soc.c b/soc/xtensa/espressif_esp32/esp32/soc.c deleted file mode 100644 index 16df3aca6452bf..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32/soc.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Include esp-idf headers first to avoid redefining BIT() macro */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "esp_private/system_internal.h" -#include "esp32/rom/cache.h" -#include "hal/soc_ll.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp32/spiram.h" -#include "esp_app_format.h" -#include "hal/wdt_hal.h" - -#ifndef CONFIG_SOC_ESP32_PROCPU -#include "esp_clk_internal.h" -#endif /* CONFIG_SOC_ESP32_PROCPU */ - -#ifdef CONFIG_MCUBOOT -#include "bootloader_init.h" -#endif /* CONFIG_MCUBOOT */ -#include - -extern void z_cstart(void); -extern void esp_reset_reason_init(void); - -#ifdef CONFIG_SOC_ESP32_PROCPU -extern const unsigned char esp32_appcpu_fw_array[]; - -void IRAM_ATTR esp_start_appcpu(void) -{ - esp_image_header_t *header = (esp_image_header_t *)&esp32_appcpu_fw_array[0]; - esp_image_segment_header_t *segment = - (esp_image_segment_header_t *)&esp32_appcpu_fw_array[sizeof(esp_image_header_t)]; - uint8_t *segment_payload; - uint32_t entry_addr = header->entry_addr; - uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); - - for (int i = 0; i < header->segment_count; i++) { - segment_payload = (uint8_t *)&esp32_appcpu_fw_array[idx]; - - if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { - /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ - volatile uint32_t *src = (volatile uint32_t *)segment_payload; - volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; - - for (int j = 0; j < segment->data_len / 4; j++) { - dst[j] = src[j]; - } - } else if (segment->load_addr >= SOC_DRAM_LOW && - segment->load_addr < SOC_DRAM_HIGH) { - - memcpy((void *)segment->load_addr, (const void *)segment_payload, - segment->data_len); - } - - idx += segment->data_len; - segment = (esp_image_segment_header_t *)&esp32_appcpu_fw_array[idx]; - idx += sizeof(esp_image_segment_header_t); - } - - esp_appcpu_start((void *)entry_addr); -} -#endif /* CONFIG_SOC_ESP32_PROCPU */ - -/* - * This is written in C rather than assembly since, during the port bring up, - * Zephyr is being booted by the Espressif bootloader. With it, the C stack - * is already set up. - */ -void __attribute__((section(".iram1"))) __esp_platform_start(void) -{ - extern uint32_t _init_start; - - /* Move the exception vector table to IRAM. */ - __asm__ __volatile__ ( - "wsr %0, vecbase" - : - : "r"(&_init_start)); - - z_bss_zero(); - - __asm__ __volatile__ ( - "" - : - : "g"(&__bss_start) - : "memory"); - - /* Disable normal interrupts. */ - __asm__ __volatile__ ( - "wsr %0, PS" - : - : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); - - /* Initialize the architecture CPU pointer. Some of the - * initialization code wants a valid _current before - * arch_kernel_init() is invoked. - */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); - - esp_reset_reason_init(); - -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else - /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check - * on startup sequence related issues in application. Hence disable that - * as we are about to start Zephyr environment. - */ - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_disable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - -#ifndef CONFIG_SOC_ESP32_PROCPU - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. - */ - esp_clk_init(); -#endif - - esp_timer_early_init(); - -#if CONFIG_SOC_ESP32_PROCPU - /* start the ESP32 APP CPU */ - esp_start_appcpu(); -#endif - -#if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); - - if (err != ESP_OK) { - printk("Failed to Initialize SPIRAM, aborting.\n"); - abort(); - } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { - printk("SPIRAM size is less than configured size, aborting.\n"); - abort(); - } -#endif - -/* Scheduler is not started at this point. Hence, guard functions - * must be initialized after esp_spiram_init_cache which internally - * uses guard functions. Setting guard functions before SPIRAM - * cache initialization will result in a crash. - */ -#if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif - -#endif /* CONFIG_MCUBOOT */ - - esp_intr_initialize(); - - /* Start Zephyr */ - z_cstart(); - - CODE_UNREACHABLE; -} - -/* Boot-time static default printk handler, possibly to be overridden later. */ -int IRAM_ATTR arch_printk_char_out(int c) -{ - if (c == '\n') { - esp_rom_uart_tx_one_char('\r'); - } - esp_rom_uart_tx_one_char(c); - return 0; -} - -void sys_arch_reboot(int type) -{ - esp_restart_noos(); -} - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - const uint32_t core_id = cpu_hal_get_core_id(); - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Read_Disable(0); - Cache_Read_Disable(1); - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | - DPORT_BT_RST | DPORT_BTMAC_RST | - DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | - DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - /* UART TX FIFO cannot be reset correctly on ESP32, */ - /* so reset the UART memory by DPORT here. */ - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_UART_RST | - DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Clear entry point for APP CPU */ - DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt deleted file mode 100644 index b9f361d1d5c094..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/CMakeLists.txt +++ /dev/null @@ -1,101 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -zephyr_sources( - soc.c - soc_cache.c - loader.c - ) - -zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) - -zephyr_library_sources_ifdef(CONFIG_PM power.c) -zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c) - -# get code-partition slot0 address -dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") -dt_reg_addr(img_0_off PATH ${dts_partition_path}) - -# get code-partition boot address -dt_nodelabel(dts_partition_path NODELABEL "boot_partition") -dt_reg_addr(boot_off PATH ${dts_partition_path}) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - -board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series deleted file mode 100644 index 177c5184e9806a..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.defconfig.series +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S2 - -config SOC_SERIES - default "esp32s2" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config MP_MAX_NUM_CPUS - default 1 - -config ISR_STACK_SIZE - default 2048 - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) - -endif # SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series deleted file mode 100644 index 63a5d3218dbed2..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.series +++ /dev/null @@ -1,18 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32S2 - bool "ESP32-S2 Series" - select XTENSA - select SOC_FAMILY_ESP32 - select ATOMIC_OPERATIONS_C - select DYNAMIC_INTERRUPTS - select CLOCK_CONTROL - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select ARCH_SUPPORTS_COREDUMP - select HAS_PM - select HAS_POWEROFF - help - Enable support for Espressif ESP32-S2 diff --git a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc deleted file mode 100644 index 85d190d6472b20..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s2/Kconfig.soc +++ /dev/null @@ -1,259 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S2 - -config IDF_TARGET_ESP32S2 - bool "ESP32S2 as target SOC" - default y - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32s2" - -choice SOC_PART_NUMBER - prompt "ESP32-S2 SOC Selection" - depends on SOC_SERIES_ESP32S2 - - # SoC with/without embedded flash - config SOC_ESP32S2 - bool "ESP32S2" - config SOC_ESP32S2_R2 - bool "ESP32S2_R2" - config SOC_ESP32S2_FH2 - bool "ESP32S2_FH2" - config SOC_ESP32S2_FH4 - bool "ESP32S2_FH4" - config SOC_ESP32S2_FN4R2 - bool "ESP32S2_FN4R2" - # SiP with external flash / psram - config SOC_ESP32S2_SOLO_N4 - bool "ESP32S2_SOLO_N4" - config SOC_ESP32S2_SOLO_N8 - bool "ESP32S2_SOLO_N8" - config SOC_ESP32S2_SOLO_N16 - bool "ESP32S2_SOLO_N16" - config SOC_ESP32S2_SOLO_N4R2 - bool "ESP32S2_SOLO_N4R2" - config SOC_ESP32S2_MINI_N4 - bool "ESP32S2_MINI_N4" - config SOC_ESP32S2_MINI_N4R2 - bool "ESP32S2_MINI_N4R2" - config SOC_ESP32S2_WROOM - bool "ESP32S2_WROOM" - config SOC_ESP32S2_WROVER_N4R2 - bool "ESP32S2_WROVER_N4R2" - config SOC_ESP32S2_WROVER_N8R2 - bool "ESP32S2_WROVER_N8R2" - config SOC_ESP32S2_WROVER_N16R2 - bool "ESP32S2_WROVER_N16R2" - -endchoice # SOC_PART_NUMBER - -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32S2_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S2_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 90kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 90kHz oscillator. It does not require external components. - -config ESP32S2_RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" - -config ESP32S2_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32S2_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32S2_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice - -config ESP32S2_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 - default 576 if ESP32S2_RTC_CLK_SRC_INT_RC - range 0 125000 - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -menu "Cache config" - -choice - prompt "Instruction cache line size" - default ESP32S2_INSTRUCTION_CACHE_LINE_32B - - config ESP32S2_INSTRUCTION_CACHE_LINE_16B - bool "16 Bytes" - - config ESP32S2_INSTRUCTION_CACHE_LINE_32B - bool "32 Bytes" - -endchoice - -choice - prompt "Instruction cache size" - default ESP32S2_INSTRUCTION_CACHE_8KB - - config ESP32S2_INSTRUCTION_CACHE_8KB - bool "8KB instruction cache size" - - config ESP32S2_INSTRUCTION_CACHE_16KB - bool "16KB instruction cache size" - -endchoice - -choice - prompt "Data cache size" - default ESP32S2_DATA_CACHE_0KB if !ESP_SPIRAM - default ESP32S2_DATA_CACHE_8KB if ESP_SPIRAM - - config ESP32S2_DATA_CACHE_0KB - bool "0KB data cache size" - - config ESP32S2_DATA_CACHE_8KB - bool "8KB data cache size" - - config ESP32S2_DATA_CACHE_16KB - bool "16KB data cache size" - -endchoice - -choice - prompt "Data cache line size" - default ESP32S2_DATA_CACHE_LINE_32B - - config ESP32S2_DATA_CACHE_LINE_16B - bool "16 Bytes" - - config ESP32S2_DATA_CACHE_LINE_32B - bool "32 Bytes" - -endchoice - -config ESP32S2_INSTRUCTION_CACHE_SIZE - hex - default 0x4000 if ESP32S2_INSTRUCTION_CACHE_16KB - default 0x2000 - -config ESP32S2_DATA_CACHE_SIZE - hex - default 0x2000 if ESP32S2_DATA_CACHE_8KB - default 0x4000 if ESP32S2_DATA_CACHE_16KB - default 0x0000 - -endmenu # Cache config - -menu "PSRAM clock and cs IO for ESP32-S2" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config - it based on hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, user can config it - based on hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S2 - -choice ESP32S2_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is two, - all interfaces (WiFi station, WiFi softap) receive a universally administered MAC - address. - They are generated sequentially by adding 0, and 1 (respectively) to the final octet of - the base MAC address. If the number of universal MAC addresses is one, only WiFi station - receives a universally administered MAC address. - The WiFi softap receives local MAC addresses. It's derived from the universal WiFi - station MAC addresses. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 1 or 2 per device). - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - bool "One" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - -endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES - int - default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -endif # SOC_SERIES_ESP32S2 diff --git a/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt b/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt deleted file mode 100644 index cb5291614bcb81..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/CMakeLists.txt +++ /dev/null @@ -1,122 +0,0 @@ -# SPDX-License-Identifier: Apache-2.0 - -if (CONFIG_SOC_ESP32S3_APPCPU) - zephyr_sources(soc_appcpu.c) -else() - zephyr_sources( - soc.c - soc_cache.c - loader.c - esp32s3-mp.c - ) -endif() - -zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c) - -# get flash size to use in esptool as string -math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") - -if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) - - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) - - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") - - board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") - -endif() - -if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py - ARGS --chip esp32s3 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) - endif() - - if(CONFIG_MCUBOOT) - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin") - endif() - -endif() - -## When building for APPCPU -if (CONFIG_SOC_ESP32S3_APPCPU) - - if(CONFIG_BUILD_OUTPUT_BIN) - set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esp_bin2c_array.py - ARGS -i ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin - -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.c - -a "esp32s3_appcpu_fw_array") - endif() - -else() - - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - # get code-partition slot0 address - dt_nodelabel(dts_partition_path NODELABEL "slot0_partition") - dt_reg_addr(img_0_off PATH ${dts_partition_path}) - - # get code-partition boot address - dt_nodelabel(dts_partition_path NODELABEL "boot_partition") - dt_reg_addr(boot_off PATH ${dts_partition_path}) - - board_finalize_runner_args(esp32 "--esp-boot-address=${boot_off}") - - board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}") - -endif() - -if(CONFIG_MCUBOOT) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "") -elseif(CONFIG_SOC_ESP32S3_APPCPU) - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "") -else() - set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "") -endif() diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series deleted file mode 100644 index 30d0480cad28e0..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S3 - -config SOC_SERIES - default "esp32s3" - -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0) - -endif # SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series deleted file mode 100644 index 6f5fcf88c17c72..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_ESP32S3 - bool "ESP32-S3 Series" - select XTENSA - select SOC_FAMILY_ESP32 - select DYNAMIC_INTERRUPTS - select ARCH_SUPPORTS_COREDUMP - select CLOCK_CONTROL - select PINCTRL - select XIP if !MCUBOOT - select HAS_ESPRESSIF_HAL - select CPU_HAS_FPU - -config SOC_ESP32S3_PROCPU - bool "Application runs in ESP32S3 PROCPU (core 0)" - depends on SOC_SERIES_ESP32S3 - help - When this SOC is enabled, it will run application on PROCPU (core 0). It will automatically - enable AMP support by building, flashing and loading APPCPU (core 1) image if exists. - -config SOC_ESP32S3_APPCPU - bool "Application runs in ESP32S3 APPCPU (core 1)" - depends on SOC_SERIES_ESP32S3 - help - When this SOC is enabled, it will run application on APPCPU (core 1). It is expected that - there is another image running on PROCPU (core 0) to trigger the AMP support. diff --git a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc b/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc deleted file mode 100644 index ad8b4b4234b8a9..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/Kconfig.soc +++ /dev/null @@ -1,332 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S3 - -config IDF_TARGET_ESP32S3 - bool "ESP32S3 as target SOC" - default y - -config SOC_TOOLCHAIN_NAME - string - default "espressif_esp32s3" - -choice SOC_PART_NUMBER - prompt "ESP32-S3 SOC Selection" - - # SoC with/without embedded flash - config SOC_ESP32S3_R2 - bool "ESP32S3_R2" - config SOC_ESP32S3_R8 - bool "ESP32S3_R8" - config SOC_ESP32S3_R8V - bool "ESP32S3_R8V" - config SOC_ESP32S3_FN8 - bool "ESP32S3_FN8" - config SOC_ESP32S3_PICO_N8R2 - bool "ESP32S3_PICO_N8R2" - config SOC_ESP32S3_PICO_N8R8 - bool "ESP32S3_PICO_N8R8" - # SiP with flash and/or psram - config SOC_ESP32S3_MINI_N8 - bool "ESP32S3_MINI_N8" - config SOC_ESP32S3_MINI_N4R2 - bool "ESP32S3_MINI_N4R2" - config SOC_ESP32S3_WROOM_N4 - bool "ESP32S3_WROOM_N4" - config SOC_ESP32S3_WROOM_N8 - bool "ESP32S3_WROOM_N8" - config SOC_ESP32S3_WROOM_N16 - bool "ESP32S3_WROOM_N16" - config SOC_ESP32S3_WROOM_N4R8 - bool "ESP32S3_WROOM_N4R8" - config SOC_ESP32S3_WROOM_N8R8 - bool "ESP32S3_WROOM_N8R8" - config SOC_ESP32S3_WROOM_N16R8 - bool "ESP32S3_WROOM_N16R8" - config SOC_ESP32S3_WROOM_N4R2 - bool "ESP32S3_WROOM_N4R2" - config SOC_ESP32S3_WROOM_N8R2 - bool "ESP32S3_WROOM_N8R2" - config SOC_ESP32S3_WROOM_N16R2 - bool "ESP32S3_WROOM_N16R2" - -endchoice # SOC_PART_NUMBER - -config ESP32S3_APPCPU_IRAM - hex "ESP32S3 APPCPU IRAM size" - depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU - default 0x20000 - help - Defines APPCPU IRAM area in bytes. - -config ESP32S3_APPCPU_DRAM - hex "ESP32S3 APPCPU DRAM size" - depends on SOC_ESP32S3_PROCPU || SOC_ESP32S3_APPCPU - default 0x10000 - help - Defines APPCPU DRAM area in bytes. - -choice ESP32S3_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S3_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - config ESP32S3_RTC_CLK_SRC_INT_RC - bool "Internal 150kHz RC oscillator" - config ESP32S3_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - config ESP32S3_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XP pin" - select ESP_SYSTEM_RTC_EXT_OSC - config ESP32S3_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" -endchoice - -config ESP32S3_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - default 1024 if ESP32S3_RTC_CLK_SRC_INT_RC - range 0 27000 if ESP32S3_RTC_CLK_SRC_EXT_CRYS || ESP32S3_RTC_CLK_SRC_EXT_OSC || ESP32S3_RTC_CLK_SRC_INT_8MD256 - range 0 32766 if ESP32S3_RTC_CLK_SRC_INT_RC - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 150000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - -choice ESP32_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is four, - all four interfaces (WiFi station, WiFi softap, Bluetooth and Ethernet) receive a universally - administered MAC address. These are generated sequentially by adding 0, 1, 2 and 3 (respectively) - to the final octet of the base MAC address. If the number of universal MAC addresses is two, - only two interfaces (WiFi station and Bluetooth) receive a universally administered MAC address. - These are generated sequentially by adding 0 and 1 (respectively) to the base MAC address. - The remaining two interfaces (WiFi softap and Ethernet) receive local MAC addresses. - These are derived from the universal WiFi station and Bluetooth MAC addresses, respectively. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 2 or 4 per device.) - -config ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_BT - -config ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - bool "Four" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - select ESP_MAC_ADDR_UNIVERSE_BT - select ESP_MAC_ADDR_UNIVERSE_ETH - -endchoice # ESP32_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP_MAC_ADDR_UNIVERSE_BT - bool - -config ESP_MAC_ADDR_UNIVERSE_ETH - bool - -config ESP32_UNIVERSAL_MAC_ADDRESSES - int - default 2 if ESP32_UNIVERSAL_MAC_ADDRESSES_TWO - default 4 if ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR - -config ESP32_PHY_MAX_WIFI_TX_POWER - int "Max WiFi/BLE TX power (dBm)" - range 10 20 - default 20 - help - Set maximum transmit power for WiFi radio. Actual transmit power for high - data rates may be lower than this setting. - -config ESP32_PHY_MAX_TX_POWER - int - default ESP32_PHY_MAX_WIFI_TX_POWER - -menu "Cache config" - -choice ESP32S3_INSTRUCTION_CACHE_SIZE - prompt "Instruction cache size" - default ESP32S3_INSTRUCTION_CACHE_16KB - help - Instruction cache size to be set on application startup. - If you use 16KB instruction cache rather than 32KB instruction cache, - then the other 16KB will be managed by heap allocator. - - config ESP32S3_INSTRUCTION_CACHE_16KB - bool "16KB" - config ESP32S3_INSTRUCTION_CACHE_32KB - bool "32KB" -endchoice - -config ESP32S3_INSTRUCTION_CACHE_SIZE - hex - default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB - default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB - -choice ESP32S3_ICACHE_ASSOCIATED_WAYS - prompt "Instruction cache associated ways" - default ESP32S3_INSTRUCTION_CACHE_8WAYS - help - Instruction cache associated ways to be set on application startup. - - config ESP32S3_INSTRUCTION_CACHE_4WAYS - bool "4 ways" - config ESP32S3_INSTRUCTION_CACHE_8WAYS - bool "8 ways" -endchoice - -config ESP32S3_ICACHE_ASSOCIATED_WAYS - int - default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS - default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS - -choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE - prompt "Instruction cache line size" - default ESP32S3_INSTRUCTION_CACHE_LINE_32B - help - Instruction cache line size to be set on application startup. - - config ESP32S3_INSTRUCTION_CACHE_LINE_16B - bool "16 Bytes" - depends on ESP32S3_INSTRUCTION_CACHE_16KB - config ESP32S3_INSTRUCTION_CACHE_LINE_32B - bool "32 Bytes" -endchoice - -config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE - int - default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B - default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B - -config ESP32S3_INSTRUCTION_CACHE_WRAP - bool "Define instruction cache wrap mode" - help - If enabled, instruction cache will use wrap mode to read spi flash or spi ram. - The wrap length equals to ESP32S3_INSTRUCTION_CACHE_LINE_SIZE. - However, it depends on complex conditions. - -choice ESP32S3_DATA_CACHE_SIZE - prompt "Data cache size" - default ESP32S3_DATA_CACHE_32KB - help - Data cache size to be set on application startup. - If you use 32KB data cache rather than 64KB data cache, - the other 32KB will be added to the heap. - - config ESP32S3_DATA_CACHE_16KB - bool "16KB" - config ESP32S3_DATA_CACHE_32KB - bool "32KB" - config ESP32S3_DATA_CACHE_64KB - bool "64KB" -endchoice - -config ESP32S3_DATA_CACHE_SIZE - hex - # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup - default 0x8000 if ESP32S3_DATA_CACHE_16KB - default 0x8000 if ESP32S3_DATA_CACHE_32KB - default 0x10000 if ESP32S3_DATA_CACHE_64KB - -choice ESP32S3_DCACHE_ASSOCIATED_WAYS - prompt "Data cache associated ways" - default ESP32S3_DATA_CACHE_8WAYS - help - Data cache associated ways to be set on application startup. - - config ESP32S3_DATA_CACHE_4WAYS - bool "4 ways" - config ESP32S3_DATA_CACHE_8WAYS - bool "8 ways" -endchoice - -config ESP32S3_DCACHE_ASSOCIATED_WAYS - int - default 4 if ESP32S3_DATA_CACHE_4WAYS - default 8 if ESP32S3_DATA_CACHE_8WAYS - -choice ESP32S3_DATA_CACHE_LINE_SIZE - prompt "Data cache line size" - default ESP32S3_DATA_CACHE_LINE_32B - help - Data cache line size to be set on application startup. - - config ESP32S3_DATA_CACHE_LINE_16B - bool "16 Bytes" - depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB - config ESP32S3_DATA_CACHE_LINE_32B - bool "32 Bytes" - config ESP32S3_DATA_CACHE_LINE_64B - bool "64 Bytes" -endchoice - -config ESP32S3_DATA_CACHE_LINE_SIZE - int - default 16 if ESP32S3_DATA_CACHE_LINE_16B - default 32 if ESP32S3_DATA_CACHE_LINE_32B - default 64 if ESP32S3_DATA_CACHE_LINE_64B - -config ESP32S3_DATA_CACHE_WRAP - bool "Define data cache wrap mode" - help - If enabled, data cache will use wrap mode to read spi flash or spi ram. - The wrap length equals to ESP32S3_DATA_CACHE_LINE_SIZE. - However, it depends on complex conditions. - -config MAC_BB_PD - bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled" - depends on SOC_SERIES_ESP32S3 && TICKLESS_KERNEL - default n - help - If enabled, the MAC and baseband of Wi-Fi and Bluetooth will be powered - down when PHY is disabled. Enabling this setting reduces power consumption - by a small amount but increases RAM use by approximat - -endmenu # Cache config - -menu "PSRAM Clock and CS IO for ESP32S3" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM Clock IO can be any unused GPIO, please refer to your hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, please refer to your hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S3 - -endif # SOC_SERIES_ESP32S3 diff --git a/soc/xtensa/espressif_esp32/esp32s3/default.ld b/soc/xtensa/espressif_esp32/esp32s3/default.ld deleted file mode 100644 index 4076ea7c1af13e..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/default.ld +++ /dev/null @@ -1,693 +0,0 @@ -/* - * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. - * SPDX-License-Identifier: Apache-2.0 - */ - -/** - * @file - * @brief Linker command/script file - * - * Linker script for the ESP32S3 platform. - */ - -#include -#include -#include -#include - -#define SRAM_IRAM_START 0x40370000 -#define SRAM_DIRAM_I_START 0x40378000 -/* SRAM_IRAM_END is equivalent 2nd stage bootloader iram_loader_seg - start address (that should not be overlapped) */ -#define SRAM_IRAM_END 0x403BA000 -#define I_D_SRAM_OFFSET (SRAM_DIRAM_I_START - SRAM_DRAM_START) - -#define SRAM_DRAM_START 0x3FC88000 -#define SRAM_DRAM_END (SRAM_IRAM_END - I_D_SRAM_OFFSET) -#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_START) - -#define ICACHE_SIZE 0x8000 -#define SRAM_IRAM_ORG (SRAM_IRAM_START + CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) -#define SRAM_IRAM_SIZE (I_D_SRAM_SIZE + ICACHE_SIZE - CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE) - -#define DCACHE_SIZE 0x10000 -#define SRAM_DRAM_ORG (SRAM_DRAM_START) - -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - -#define FLASH_CODE_REGION irom0_0_seg -#define RODATA_REGION drom0_0_seg -#define IRAM_REGION iram0_0_seg -#define RAMABLE_REGION dram0_0_seg -#define ROMABLE_REGION ROM - -#define EXT_RAM_ORG (0x3E000000 - CONFIG_ESP_SPIRAM_SIZE) - -#ifdef CONFIG_FLASH_SIZE -#define FLASH_SIZE CONFIG_FLASH_SIZE -#else -#define FLASH_SIZE 0x800000 -#endif - -#ifdef CONFIG_BOOTLOADER_ESP_IDF -#define IROM_SEG_ORG 0x42000020 -#define IROM_SEG_LEN FLASH_SIZE-0x20 -#else -#define IROM_SEG_ORG 0x42000000 -#define IROM_SEG_LEN FLASH_SIZE -#endif - -#ifdef CONFIG_SOC_ESP32S3_PROCPU -#define APPCPU_IRAM_SIZE CONFIG_ESP32S3_APPCPU_IRAM -#define APPCPU_DRAM_SIZE CONFIG_ESP32S3_APPCPU_DRAM -#else -#define APPCPU_IRAM_SIZE 0x0 -#define APPCPU_DRAM_SIZE 0x0 -#endif - -#define IROM_SEG_ALIGN 0x10000 - -/* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA. - * Executing directly from LMA is not possible. */ -#undef GROUP_ROM_LINK_IN -#define GROUP_ROM_LINK_IN(vregion, lregion) > RODATA_REGION AT > lregion - -MEMORY -{ - mcuboot_hdr (RX): org = 0x0, len = 0x20 - metadata (RX): org = 0x20, len = 0x20 - ROM (RX): org = 0x40, len = FLASH_SIZE - 0x40 - iram0_0_seg(RX): org = SRAM_IRAM_ORG, len = SRAM_IRAM_SIZE - APPCPU_IRAM_SIZE - dram0_0_seg(RW): org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - APPCPU_DRAM_SIZE - - irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN - - /* DROM is the first segment placed in generated binary. - * MCUboot binary for ESP32 has image header of 0x20 bytes. - * Additional load header of 0x20 bytes are appended to the image. - * Hence, an offset of 0x40 is added to DROM segment origin. - */ - drom0_0_seg(R): org = 0x3C000040, len = FLASH_SIZE - 0x40 - /** - * `extern_ram_seg` and `drom0_0_seg` share the same bus and the address region. - * so we allocate `extern_ram_seg` at the end of the address region. - */ -#if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RWX): org = EXT_RAM_ORG, len = CONFIG_ESP_SPIRAM_SIZE -#endif - - /* RTC fast memory (executable). Persists over deep sleep. - */ - rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 - - /* RTC fast memory (same block as above), viewed from data bus - */ - rtc_data_seg(RW): org = 0x600fe000, len = 0x2000 - - /* RTC slow memory (data accessible). Persists over deep sleep. - */ - rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 - -#ifdef CONFIG_GEN_ISR_TABLES - IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 -#endif -} - -/* Default entry point: */ -ENTRY(CONFIG_KERNEL_ENTRY) - -SECTIONS -{ - /* Reserve space for MCUboot header in the binary */ - .mcuboot_header : - { - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - QUAD(0x0) - } > mcuboot_hdr - .metadata : - { - /* Magic byte for load header */ - LONG(0xace637d3) - - /* Application entry point address */ - KEEP(*(.entry_addr)) - - /* IRAM metadata: - * - Destination address (VMA) for IRAM region - * - Flash offset (LMA) for start of IRAM region - * - Size of IRAM region - */ - LONG(ADDR(.iram0.vectors)) - LONG(LOADADDR(.iram0.vectors)) - LONG(LOADADDR(.iram0.text) + SIZEOF(.iram0.text) - LOADADDR(.iram0.vectors)) - - /* DRAM metadata: - * - Destination address (VMA) for DRAM region - * - Flash offset (LMA) for start of DRAM region - * - Size of DRAM region - */ - LONG(ADDR(.dram0.data)) - LONG(LOADADDR(.dram0.data)) - LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data)) - } > metadata - - #include - - _image_drom_start = LOADADDR(_RODATA_SECTION_NAME); - _image_drom_size = LOADADDR(_RODATA_SECTION_END) + SIZEOF(_RODATA_SECTION_END) - _image_drom_start; - _image_drom_vaddr = ADDR(_RODATA_SECTION_NAME); - - /* NOTE: .rodata section should be the first section in the linker script and no - * other section should appear before .rodata section. This is the requirement - * to align ROM section to 64K page offset. - * Adding .rodata as first section helps to reduce size of generated binary by - * few kBs. - */ - SECTION_PROLOGUE(_RODATA_SECTION_NAME,,ALIGN(0x10)) - { - _rodata_reserved_start = ABSOLUTE(.); - _rodata_start = ABSOLUTE(.); - - *(.rodata_desc .rodata_desc.*) /* Should be the first. App version info. DO NOT PUT ANYTHING BEFORE IT! */ - *(.rodata_custom_desc .rodata_custom_desc.*) /* Should be the second. Custom app version info. DO NOT PUT ANYTHING BEFORE IT! */ - - __rodata_region_start = ABSOLUTE(.); - . = ALIGN(4); - #include - - . = ALIGN(4); - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata) - *(EXCLUDE_FILE (*libarch__xtensa__core.a:* *libkernel.a:fatal.* *libkernel.a:init.* *libzephyr.a:cbprintf_complete* *libzephyr.a:log_core.* *libzephyr.a:log_backend_uart.* *libzephyr.a:log_output.* *libzephyr.a:loader.* *libdrivers__serial.a:uart_esp32.*) .rodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ exception handlers table: */ - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - . = ALIGN(4); - __rodata_region_end = ABSOLUTE(.); - /* Literals are also RO data. */ - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - *(.rodata_wlog) - *(.rodata_wlog*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - #include - #include - #include - #include - - /* Create an explicit section at the end of all the data that shall be mapped into drom. - * This is used to calculate the size of the _image_drom_size variable */ - SECTION_PROLOGUE(_RODATA_SECTION_END,,ALIGN(0x10)) - { - _rodata_reserved_end = ABSOLUTE(.); - . = ALIGN(16); - _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) - -#if defined(CONFIG_ESP_SPIRAM) - /* This section holds .ext_ram.bss data, and will be put in PSRAM */ - .ext_ram.bss (NOLOAD) : - { - _ext_ram_data_start = ABSOLUTE(.); - _ext_ram_bss_start = ABSOLUTE(.); - *(.ext_ram.bss*) - . = ALIGN(4); - _ext_ram_bss_end = ABSOLUTE(.); - } > ext_ram_seg - - .ext_ram_noinit (NOLOAD) : - { -#if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) - *libdrivers__wifi.a:(.noinit .noinit.*) - *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) - *libsubsys__net__lib__config.a:(.noinit .noinit.*) - *libsubsys__net__ip.a:(.noinit .noinit.*) - *libsubsys__net.a:(.noinit .noinit.*) -#endif - _spiram_heap_start = ABSOLUTE(.); - . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - - _ext_ram_data_end = ABSOLUTE(.); - } > ext_ram_seg -#endif - - /* Send .iram0 code to iram */ - .iram0.vectors : ALIGN(4) - { - _iram_start = ABSOLUTE(.); - /* Vectors go to IRAM */ - _init_start = ABSOLUTE(.); - /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ - . = 0x0; - KEEP(*(.WindowVectors.text)); - . = 0x180; - KEEP(*(.Level2InterruptVector.text)); - . = 0x1c0; - KEEP(*(.Level3InterruptVector.text)); - . = 0x200; - KEEP(*(.Level4InterruptVector.text)); - . = 0x240; - KEEP(*(.Level5InterruptVector.text)); - . = 0x280; - KEEP(*(.DebugExceptionVector.text)); - . = 0x2c0; - KEEP(*(.NMIExceptionVector.text)); - . = 0x300; - KEEP(*(.KernelExceptionVector.text)); - . = 0x340; - KEEP(*(.UserExceptionVector.text)); - . = 0x3C0; - KEEP(*(.DoubleExceptionVector.text)); - . = 0x400; - _invalid_pc_placeholder = ABSOLUTE(.); - *(.*Vector.literal) - - *(.UserEnter.literal); - *(.UserEnter.text); - . = ALIGN (16); - *(.entry.text) - *(.init.literal) - *(.init) - _init_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.text : ALIGN(4) - { - /* Code marked as running out of IRAM */ - _iram_text_start = ABSOLUTE(.); - *(.iram1 .iram1.*) - *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) - *libesp32.a:panic.*(.literal .text .literal.* .text.*) - *librtc.a:(.literal .text .literal.* .text.*) - *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) - *libkernel.a:(.literal .text .literal.* .text.*) - *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) - *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) - *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libzephyr.a:spiram*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_timing*.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash*.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) - *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) - *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_core.*(.literal .text .literal.* .text.*) - *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*) - *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out) - *libzephyr.a:log_msg.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_list.*(.literal .text .literal.* .text.*) - *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) - *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) - *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) - *libzephyr.a:loader.*(.literal .text .literal.* .text.*) - *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) - *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) - *libc.a:*(.literal .text .literal.* .text.*) - *libphy.a:(.phyiram .phyiram.*) - *libgcov.a:(.literal .text .literal.* .text.*) - -#if defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - . = ALIGN(4) + 16; - - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - /* Marks the end of IRAM code segment */ - .iram0.text_end (NOLOAD) : - { - /* ESP32-S3 memprot requires 16B padding for possible CPU - * prefetch and 256B alignment for PMS split lines */ - . = ALIGN(16); - _iram_text_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION) - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } GROUP_LINK_IN(IRAM_REGION) - - - /* This section is required to skip .iram0.text area because iram0_0_seg and - * dram0_0_seg reflect the same address space on different buses. - */ - .dram0.dummy (NOLOAD): - { - . = ALIGN (8); - . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM_DIRAM_I_START) - SRAM_DIRAM_I_START; - } GROUP_LINK_IN(RAMABLE_REGION) - - /* Shared RAM */ - SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),) - { - . = ALIGN (8); - _bss_start = ABSOLUTE(.); /* required by bluetooth library */ - __bss_start = ABSOLUTE(.); - - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN (8); - __bss_end = ABSOLUTE(.); - } GROUP_LINK_IN(RAMABLE_REGION) - - ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.") - - SECTION_DATA_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD),) - { - . = ALIGN(8); - *(.noinit) - *(.noinit.*) - . = ALIGN(8) ; - } GROUP_LINK_IN(RAMABLE_REGION) - - .dram0.data : - { - . = ALIGN (8); - __data_start = ABSOLUTE(.); - - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - /* rodata for panic handler(libarch__xtensa__core.a) and all - * dependent functions should be placed in DRAM to avoid issue - * when flash cache is disabled */ - *libarch__xtensa__core.a:(.rodata .rodata.*) - *libkernel.a:fatal.*(.rodata .rodata.*) - *libkernel.a:init.*(.rodata .rodata.*) - *libzephyr.a:cbprintf_complete*(.rodata .rodata.*) - *libzephyr.a:systimer_hal.*(.rodata .rodata.*) - *libzephyr.a:log_core.*(.rodata .rodata.*) - *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) - *libzephyr.a:log_output.*(.rodata .rodata.*) - *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - - KEEP(*(.jcr)) - *(.dram1 .dram1.*) - . = ALIGN(4); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - #include - #include - #include - #include - #include - - /* logging sections should be placed in RAM area to avoid flash cache disabled issues */ - #pragma push_macro("GROUP_ROM_LINK_IN") - #undef GROUP_ROM_LINK_IN - #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN - #include - #pragma pop_macro("GROUP_ROM_LINK_IN") - - .dram0.end : - { - . = ALIGN(4); - - #include - - . = ALIGN(4); - _end = ABSOLUTE(.); - __data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) - - _image_irom_start = LOADADDR(.flash.text); - _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start; - _image_irom_vaddr = ADDR(.flash.text); - - .flash_text_dummy (NOLOAD): ALIGN(IROM_SEG_ALIGN) - { - . = SIZEOF(_RODATA_SECTION_NAME); - . = ALIGN(IROM_SEG_ALIGN) + 0x20; - } GROUP_LINK_IN(FLASH_CODE_REGION) - - .flash.text : ALIGN(IROM_SEG_ALIGN) - { - _stext = .; - _text_start = ABSOLUTE(.); - -#if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) - *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) - *libpp.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.*) -#endif - -#if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT) - *libnet80211.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) - *libpp.a:( .wifirxiram .wifirxiram.* .wifislprxiram .wifislprxiram.*) -#endif - - *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - *(.literal .text .literal.* .text.*) - - /* CPU will try to prefetch up to 16 bytes of - * of instructions. This means that any configuration (e.g. MMU, PMS) must allow - * safe access to up to 16 bytes after the last real instruction, add - * dummy bytes to ensure this - */ - . += 16; - - _text_end = ABSOLUTE(.); - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - _flash_cache_start = ABSOLUTE(0); - } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION) - - /* RTC fast memory holds RTC wake stub code, - * including from any source file named rtc_wake_stub*.c - */ - .rtc.text : - { - . = ALIGN(4); - _rtc_text_start = ABSOLUTE(.); - *(.rtc.literal .rtc.text) - *(.rtc.entry.text) - *rtc_wake_stub*.*(.literal .text .literal.* .text.*) - _rtc_text_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION) - - /* This section is required to skip rtc.text area because rtc_iram_seg and - * rtc_data_seg are reflect the same address space on different buses. - */ - .rtc.dummy : - { - _rtc_dummy_start = ABSOLUTE(.); - _rtc_fast_start = ABSOLUTE(.); - . = SIZEOF(.rtc.text); - _rtc_dummy_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) - - /* This section located in RTC FAST Memory area. - * It holds data marked with RTC_FAST_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_fast : - { - . = ALIGN(4); - _rtc_force_fast_start = ABSOLUTE(.); - - *(.rtc.force_fast .rtc.force_fast.*) - . = ALIGN(4) ; - _rtc_force_fast_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION) - - /* RTC data section holds RTC wake stub - * data/rodata, including from any source file - * named rtc_wake_stub*.c and the data marked with - * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes. - */ - .rtc.data : - { - _rtc_data_start = ABSOLUTE(.); - *(.rtc.data) - *(.rtc.rodata) - *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*) - _rtc_data_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) - - *(.rtc.data) - *(.rtc.rodata) - - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* RTC bss, from any source file named rtc_wake_stub*.c */ - .rtc.bss (NOLOAD) : - { - _rtc_bss_start = ABSOLUTE(.); - *rtc_wake_stub*.*(.bss .bss.*) - *rtc_wake_stub*.*(COMMON) - - _rtc_bss_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* This section holds data that should not be initialized at power up - * and will be retained during deep sleep. - * User data marked with RTC_NOINIT_ATTR will be placed - * into this section. See the file "esp_attr.h" for more information. - */ - .rtc_noinit (NOLOAD): - { - . = ALIGN(4); - _rtc_noinit_start = ABSOLUTE(.); - *(.rtc_noinit .rtc_noinit.*) - . = ALIGN(4) ; - _rtc_noinit_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* This section located in RTC SLOW Memory area. - * It holds data marked with RTC_SLOW_ATTR attribute. - * See the file "esp_attr.h" for more information. - */ - .rtc.force_slow : - { - . = ALIGN(4); - _rtc_force_slow_start = ABSOLUTE(.); - *(.rtc.force_slow .rtc.force_slow.*) - . = ALIGN(4) ; - _rtc_force_slow_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION) - - /* Get size of rtc slow data based on rtc_data_location alias */ - _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); - _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start); - - ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.") - ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.") - -#ifdef CONFIG_GEN_ISR_TABLES -#include -#endif - -_heap_sentry = 0x3fceb910; - -#include - - .xtensa.info 0 : { *(.xtensa.info) } - .xt.insn 0 : - { - KEEP (*(.xt.insn)) - KEEP (*(.gnu.linkonce.x.*)) - } - .xt.prop 0 : - { - KEEP (*(.xt.prop)) - KEEP (*(.xt.prop.*)) - KEEP (*(.gnu.linkonce.prop.*)) - } - .xt.lit 0 : - { - KEEP (*(.xt.lit)) - KEEP (*(.xt.lit.*)) - KEEP (*(.gnu.linkonce.p.*)) - } - .xt.profile_range 0 : - { - KEEP (*(.xt.profile_range)) - KEEP (*(.gnu.linkonce.profile_range.*)) - } - .xt.profile_ranges 0 : - { - KEEP (*(.xt.profile_ranges)) - KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) - } - .xt.profile_files 0 : - { - KEEP (*(.xt.profile_files)) - KEEP (*(.gnu.linkonce.xt.profile_files.*)) - } - -} - -ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)), - "IRAM0 segment data does not fit.") - -#if defined(CONFIG_ESP_SPIRAM) -ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE), - "External SPIRAM overflowed.") -#endif /* CONFIG_ESP_SPIRAM */ diff --git a/soc/xtensa/espressif_esp32/esp32s3/soc.c b/soc/xtensa/espressif_esp32/esp32s3/soc.c deleted file mode 100644 index d250657c49ef96..00000000000000 --- a/soc/xtensa/espressif_esp32/esp32s3/soc.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2017 Intel Corporation - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/* Include esp-idf headers first to avoid redefining BIT() macro */ -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "esp_private/system_internal.h" -#include "esp32s3/rom/cache.h" -#include "esp32s3/rom/rtc.h" -#include "soc/syscon_reg.h" -#include "hal/soc_ll.h" -#include "hal/wdt_hal.h" -#include "soc/cpu.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_err.h" -#include "esp_timer.h" -#include "esp_app_format.h" -#include "esp_clk_internal.h" - -#include "esp32s3/spiram.h" - -#ifdef CONFIG_MCUBOOT -#include "bootloader_init.h" -#endif /* CONFIG_MCUBOOT */ -#include - -#if CONFIG_ESP_SPIRAM -extern int _ext_ram_bss_start; -extern int _ext_ram_bss_end; -#endif - -extern void z_cstart(void); -extern void esp_reset_reason_init(void); - -#ifdef CONFIG_SOC_ESP32S3_PROCPU -extern const unsigned char esp32s3_appcpu_fw_array[]; - -void IRAM_ATTR esp_start_appcpu(void) -{ - esp_image_header_t *header = (esp_image_header_t *)&esp32s3_appcpu_fw_array[0]; - esp_image_segment_header_t *segment = - (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[sizeof(esp_image_header_t)]; - uint8_t *segment_payload; - uint32_t entry_addr = header->entry_addr; - uint32_t idx = sizeof(esp_image_header_t) + sizeof(esp_image_segment_header_t); - - for (int i = 0; i < header->segment_count; i++) { - segment_payload = (uint8_t *)&esp32s3_appcpu_fw_array[idx]; - - if (segment->load_addr >= SOC_IRAM_LOW && segment->load_addr < SOC_IRAM_HIGH) { - /* IRAM segment only accepts 4 byte access, avoid memcpy usage here */ - volatile uint32_t *src = (volatile uint32_t *)segment_payload; - volatile uint32_t *dst = (volatile uint32_t *)segment->load_addr; - - for (int i = 0; i < segment->data_len / 4; i++) { - dst[i] = src[i]; - } - - } else if (segment->load_addr >= SOC_DRAM_LOW && - segment->load_addr < SOC_DRAM_HIGH) { - memcpy((void *)segment->load_addr, (const void *)segment_payload, - segment->data_len); - } - - idx += segment->data_len; - segment = (esp_image_segment_header_t *)&esp32s3_appcpu_fw_array[idx]; - idx += sizeof(esp_image_segment_header_t); - } - - esp_appcpu_start((void *)entry_addr); -} -#endif /* CONFIG_SOC_ESP32S3_PROCPU*/ - -#ifndef CONFIG_MCUBOOT -/* - * This function is a container for SoC patches - * that needs to be applied during the startup. - */ -static void IRAM_ATTR esp_errata(void) -{ - /* Handle the clock gating fix */ - REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_CLKGATE_EN); - /* The clock gating signal of the App core is invalid. We use RUNSTALL and RESETTING - * signals to ensure that the App core stops running in single-core mode. - */ - REG_SET_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RUNSTALL); - REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETTING); - - /* Handle the Dcache case following the IDF startup code */ -#if CONFIG_ESP32S3_DATA_CACHE_16KB - Cache_Invalidate_DCache_All(); - Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000); -#endif -} -#endif /* CONFIG_MCUBOOT */ - -/* - * This is written in C rather than assembly since, during the port bring up, - * Zephyr is being booted by the Espressif bootloader. With it, the C stack - * is already set up. - */ -void IRAM_ATTR __esp_platform_start(void) -{ - extern uint32_t _init_start; - - /* Move the exception vector table to IRAM. */ - __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); - - z_bss_zero(); - - /* Disable normal interrupts. */ - __asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); - - /* Initialize the architecture CPU pointer. Some of the - * initialization code wants a valid _current before - * arch_kernel_init() is invoked. - */ - __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); - -#ifdef CONFIG_MCUBOOT - /* MCUboot early initialisation. */ - if (bootloader_init()) { - abort(); - } -#else - /* Configure the mode of instruction cache : cache size, cache line size. */ - esp_config_instruction_cache_mode(); - - /* If we need use SPIRAM, we should use data cache. - * Configure the mode of data : cache size, cache line size. - */ - esp_config_data_cache_mode(); - - /* Apply SoC patches */ - esp_errata(); - -#if CONFIG_ESP_SPIRAM - esp_err_t err = esp_spiram_init(); - - if (err != ESP_OK) { - printk("Failed to Initialize external RAM, aborting.\n"); - abort(); - } - - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { - printk("External RAM size is less than configured, aborting.\n"); - abort(); - } - - if (!esp_spiram_test()) { - printk("External RAM failed memory test!\n"); - abort(); - } - - memset(&_ext_ram_bss_start, 0, - (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); - -#endif /* CONFIG_ESP_SPIRAM */ - - /* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence - * related issues in application. Hence disable that as we are about to start - * Zephyr environment. - */ - wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL}; - - wdt_hal_write_protect_disable(&rtc_wdt_ctx); - wdt_hal_disable(&rtc_wdt_ctx); - wdt_hal_write_protect_enable(&rtc_wdt_ctx); - - esp_reset_reason_init(); - - esp_clk_init(); - - esp_timer_early_init(); - -#if CONFIG_SOC_ESP32S3_PROCPU - /* start the ESP32S3 APP CPU */ - esp_start_appcpu(); -#endif - -#if CONFIG_SOC_FLASH_ESP32 - spi_flash_guard_set(&g_flash_guard_default_ops); -#endif -#endif /* CONFIG_MCUBOOT */ - - esp_intr_initialize(); - - /* Start Zephyr */ - z_cstart(); - - CODE_UNREACHABLE; -} - -/* Boot-time static default printk handler, possibly to be overridden later. */ -int IRAM_ATTR arch_printk_char_out(int c) -{ - if (c == '\n') { - esp_rom_uart_tx_one_char('\r'); - } - esp_rom_uart_tx_one_char(c); - return 0; -} - -void sys_arch_reboot(int type) -{ - esp_restart_noos(); -} - -void IRAM_ATTR esp_restart_noos(void) -{ - /* disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* enable RTC watchdog for 1 second */ - wdt_hal_context_t wdt_ctx; - uint32_t timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL); - - wdt_hal_init(&wdt_ctx, WDT_RWDT, 0, false); - wdt_hal_write_protect_disable(&wdt_ctx); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE0, timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM); - wdt_hal_config_stage(&wdt_ctx, WDT_STAGE1, timeout_ticks, WDT_STAGE_ACTION_RESET_RTC); - - /* enable flash boot mode so that flash booting after restart is protected by the RTC WDT */ - wdt_hal_set_flashboot_en(&wdt_ctx, true); - wdt_hal_write_protect_enable(&wdt_ctx); - - /* disable TG0/TG1 watchdogs */ - wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0}; - - wdt_hal_write_protect_disable(&wdt0_context); - wdt_hal_disable(&wdt0_context); - wdt_hal_write_protect_enable(&wdt0_context); - - wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1}; - - wdt_hal_write_protect_disable(&wdt1_context); - wdt_hal_disable(&wdt1_context); - wdt_hal_write_protect_enable(&wdt1_context); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - esp_rom_uart_tx_wait_idle(2); - - /* Disable cache */ - Cache_Disable_ICache(); - Cache_Disable_DCache(); - - const uint32_t core_id = cpu_hal_get_core_id(); -#if CONFIG_SMP - const uint32_t other_core_id = (core_id == 0) ? 1 : 0; - - soc_ll_reset_core(other_core_id); - soc_ll_stall_core(other_core_id); -#endif - - /* 2nd stage bootloader reconfigures SPI flash signals. */ - /* Reset them to the defaults expected by ROM */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/bluetooth/ethernet/sdio (bb/mac) */ - SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, - SYSTEM_BB_RST | SYSTEM_FE_RST | SYSTEM_MAC_RST | SYSTEM_BT_RST | - SYSTEM_BTMAC_RST | SYSTEM_SDIO_RST | SYSTEM_SDIO_HOST_RST | - SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_RW_BTMAC_RST | - SYSTEM_RW_BTLP_RST | SYSTEM_BLE_REG_RST | SYSTEM_PWR_REG_RST); - REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | - SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0); - - /* Reset DMA */ - SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST); - REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0); - - SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET); - - rtc_clk_cpu_freq_set_xtal(); - - /* Reset CPUs */ - if (core_id == 0) { - /* Running on PRO CPU: APP CPU is stalled. Can reset both CPUs. */ - soc_ll_reset_core(1); - soc_ll_reset_core(0); - } else { - /* Running on APP CPU: need to reset PRO CPU and unstall it, */ - /* then reset APP CPU */ - soc_ll_reset_core(0); - soc_ll_stall_core(0); - soc_ll_reset_core(1); - } - - while (true) { - ; - } -} diff --git a/soc/xtensa/intel_adsp/CMakeLists.txt b/soc/xtensa/intel_adsp/CMakeLists.txt deleted file mode 100644 index 2cee15bbcf6b9b..00000000000000 --- a/soc/xtensa/intel_adsp/CMakeLists.txt +++ /dev/null @@ -1,13 +0,0 @@ -# Intel ADSP SoCs family CMake file -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -add_subdirectory(common) -if(CONFIG_SOC_SERIES_INTEL_ACE) - add_subdirectory(ace) -endif() -if(CONFIG_INTEL_ADSP_CAVS) - add_subdirectory(cavs) -endif() -zephyr_include_directories(common/include) diff --git a/soc/xtensa/intel_adsp/Kconfig b/soc/xtensa/intel_adsp/Kconfig deleted file mode 100644 index 32dae7612f5ea2..00000000000000 --- a/soc/xtensa/intel_adsp/Kconfig +++ /dev/null @@ -1,138 +0,0 @@ -# Intel CAVS SoC family configuration options -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_INTEL_ADSP - select WINSTREAM - select ARCH_SUPPORTS_COREDUMP - select CPU_HAS_DCACHE - select ARCH_HAS_USERSPACE if XTENSA_MMU - select CPU_CACHE_INCOHERENT - bool - -if SOC_FAMILY_INTEL_ADSP - -config SOC_FAMILY - string - default "intel_adsp" - -# Select SoC Part No. and configuration options -source "soc/xtensa/intel_adsp/*/Kconfig.soc" - -DT_COMPAT_INTEL_ADSP_HOST_IPC := intel,adsp-host-ipc -DT_COMPAT_INTEL_ADSP_IDC := intel,adsp-idc - -config INTEL_ADSP_IPC - bool "Driver for the host IPC interrupt delivery" - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_HOST_IPC)) if !SOF - default $(dt_compat_enabled,$(DT_COMPAT_INTEL_ADSP_IDC)) if !SOF - help - Driver for the host IPC interrupt delivery mechanism. - Currently SOF has its own driver for this hardware. - -config MEMORY_WIN_0_SIZE - int "Size of memory window 0" - default 8192 - help - Size of memory window 0. - - This window is used for firmware status & outbox/uplink mbox. - -config MEMORY_WIN_1_SIZE - int "Size of memory window 1" - default 8192 - help - Size of memory window 1. - - This window is used for inbox/downlink mbox. - -config MEMORY_WIN_2_SIZE - int "Size of memory window 2" - default 8192 - help - Size of memory window 2. - - This window is used for debug. - -config MEMORY_WIN_3_SIZE - int "Size of memory window 3" - default 8192 - help - Size of memory window 3. - - This window is used for trace. - -config ADSP_CLOCK - bool - help - Driver for the CAVS clocks. Allow type of clock (and - thus frequency) to be chosen. - -config HP_SRAM_RESERVE - int "Bytes to reserve at start of HP-SRAM" - default 65536 - help - Bytes to reserve at the start of HP-SRAM. Zephyr will not - place any symbols here, though the host windows have - addresses here. The SOF application also makes direct use - of this region, so be very careful changing this value. - -config ADSP_TRACE_SIMCALL - bool "Emit SIMCALL output in addition to window tracing" - help - When true, the trace_out layer will also use a SIMCALL - instruction to emit the passed data to the standard output - of an enclosing simulator process. All window contents will - remain identical. - -config ADSP_NEED_POWER_ON_CACHE - bool - help - Need to power cache SRAM banks on. - -config ADSP_INIT_HPSRAM - bool - default y - help - Need to init HP SRAM. - -config ADSP_POWER_DOWN_HPSRAM - bool - default n if ZTEST - default y - help - Switch off HP SRAM during power down. - -config ADSP_DISABLE_L2CACHE_AT_BOOT - bool - -config ADSP_IMR_CONTEXT_SAVE - bool "Saves FW context into IMR before core is shut down" - default n - help - When true, FW will store its entire context into IMR before - entering D3 state. Later this context can be used to FW restore - when Host power up DSP again. - -config XTENSA_CPU_IDLE_SPIN - bool "Use busy loop for k_cpu_idle" - help - Use a spin loop instead of WAITI for the CPU idle state. - -config XTENSA_WAITI_BUG - bool "Workaround sequence for WAITI bug on LX6" - help - SOF traditionally contains this workaround on its ADSP - platforms which prefixes a WAITI entry with 128 NOP - instructions followed by an ISYNC and EXTW. - -config ADSP_IDLE_CLOCK_GATING - bool "DSP clock gating in Idle" - help - When true, FW will run with enabled clock gating. This options change - HW configuration of a DSP. Evry time core goes to the WAITI state - (wait for interrupt) during idle, the clock can be gated (however, this - does not mean that this will happen). - -endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/xtensa/intel_adsp/Kconfig.defconfig b/soc/xtensa/intel_adsp/Kconfig.defconfig deleted file mode 100644 index 1f48b33ee689e9..00000000000000 --- a/soc/xtensa/intel_adsp/Kconfig.defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# Intel CAVS SoC family default configuration options -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_INTEL_ADSP -source "soc/xtensa/intel_adsp/*/Kconfig.defconfig.series" - - -config XTENSA_RPO_CACHE - def_bool y - -# console can't handle the amount of data coming from many tests, so introduce -# a delay beween testcases. -if ZTEST -config ZTEST_TEST_DELAY_MS - default 100 -endif - -if XTENSA_RPO_CACHE -config XTENSA_CACHED_REGION - default 5 - -config XTENSA_UNCACHED_REGION - default 4 - -endif # XTENSA_RPO_CACHE - -config CONSOLE - def_bool y - -if CONSOLE -config WINSTREAM_CONSOLE - def_bool y -endif - -config CACHE_MANAGEMENT - def_bool y - -choice CACHE_TYPE - default ARCH_CACHE -endchoice - -endif # SOC_FAMILY_INTEL_ADSP diff --git a/soc/xtensa/intel_adsp/Kconfig.soc b/soc/xtensa/intel_adsp/Kconfig.soc deleted file mode 100644 index 448b16450797fa..00000000000000 --- a/soc/xtensa/intel_adsp/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# Intel CAVS SoC series selection -# -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/intel_adsp/*/Kconfig.series" diff --git a/soc/xtensa/intel_adsp/ace/CMakeLists.txt b/soc/xtensa/intel_adsp/ace/CMakeLists.txt deleted file mode 100644 index 28626787c5e68b..00000000000000 --- a/soc/xtensa/intel_adsp/ace/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# Intel ACE SoC family CMake file -# -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - - -zephyr_library_sources( - sram.c - multiprocessing.c - irq.c - power_down.S - power.c - boot.c - timestamp.c - ) - -zephyr_include_directories(include) -zephyr_include_directories(include/${SOC_NAME}) -zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c) -zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm b/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm deleted file mode 100644 index 937b3e2b3c5dba..00000000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace15_mtpm +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - - -if SOC_INTEL_ACE15_MTPM - -config SOC - string - default "intel_ace15_mtpm" - -config MP_MAX_NUM_CPUS - default 3 - -endif diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace20_lnl b/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace20_lnl deleted file mode 100644 index 2dc9365ffb52bb..00000000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace20_lnl +++ /dev/null @@ -1,14 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - - -if SOC_INTEL_ACE20_LNL - -config SOC - string - default "intel_ace20_lnl" - -config MP_MAX_NUM_CPUS - default 5 - -endif diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series deleted file mode 100644 index 5057e5cb16a03d..00000000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.defconfig.series +++ /dev/null @@ -1,73 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_INTEL_ACE - -config SOC_SERIES - string - default "ace" - -config SOC_TOOLCHAIN_NAME - string - default "intel_ace15_mtpm" - -config SMP - default y - -config POWER_DOMAIN - default y - -# MTL leaves the upper mapping in the same spot as cAVS, but moves the -# lower one inexplicably. -config XTENSA_UNCACHED_REGION - default 2 - -# Parameters for gen_isr_tables.py: - -config 2ND_LVL_INTR_00_OFFSET - default 4 - -config MULTI_LEVEL_INTERRUPTS - default y - -config MAX_IRQ_PER_AGGREGATOR - default 29 - -config NUM_2ND_LEVEL_AGGREGATORS - default 1 - -config 2ND_LVL_ISR_TBL_OFFSET - default 9 - -config 2ND_LEVEL_INTERRUPTS - default y - -config XTENSA_TIMER - default n - -config XTENSA_TIMER_ID - default 0 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 393216000 if XTENSA_TIMER - default 38400000 if INTEL_ADSP_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 12000 - -config XTENSA_CCOUNT_HZ - default 393216000 - -config DYNAMIC_INTERRUPTS - default y - -if LOG - -config LOG_BACKEND_ADSP - default y - -endif # LOG - -source "soc/xtensa/intel_adsp/ace/Kconfig.defconfig.ace*" - -endif # SOC_SERIES_INTEL_ACE diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.series b/soc/xtensa/intel_adsp/ace/Kconfig.series deleted file mode 100644 index 963c33bdf6153e..00000000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_INTEL_ACE - bool "Intel ACE" - select SOC_FAMILY_INTEL_ADSP - select XTENSA - select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) - select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select ARCH_HAS_COHERENCE - select SCHED_IPI_SUPPORTED - select DW_ICTL_ACE - select SOC_HAS_RUNTIME_NUM_CPUS - select HAS_PM - help - Intel ADSP ACE diff --git a/soc/xtensa/intel_adsp/ace/Kconfig.soc b/soc/xtensa/intel_adsp/ace/Kconfig.soc deleted file mode 100644 index 69f8ebd887a41a..00000000000000 --- a/soc/xtensa/intel_adsp/ace/Kconfig.soc +++ /dev/null @@ -1,23 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel ADSP SoC Selection" - - config SOC_INTEL_ACE15_MTPM - bool "ACE 1.5 Meteor PCH M" - depends on SOC_SERIES_INTEL_ACE - - config SOC_INTEL_ACE20_LNL - bool "ACE 2.0 Lunar Lake PCH" - depends on SOC_SERIES_INTEL_ACE - -endchoice - -config SOC_INTEL_COMM_WIDGET - bool "Intel Communication Widget driver" - default y - depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED - help - Select this to enable Intel Communication Widget driver. - DSP Communication Widget is a device for generic sideband message transmit/receive. diff --git a/soc/xtensa/intel_adsp/cavs/CMakeLists.txt b/soc/xtensa/intel_adsp/cavs/CMakeLists.txt deleted file mode 100644 index 5226f1b0535200..00000000000000 --- a/soc/xtensa/intel_adsp/cavs/CMakeLists.txt +++ /dev/null @@ -1,22 +0,0 @@ -# Intel ADSP SoCs family CMake file -# -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) -zephyr_include_directories(include/${SOC_NAME}) -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_library_sources( - sram.c - power.c - power_down_cavs.S - ) - -if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) - zephyr_library_sources(multiprocessing.c) -endif() - -zephyr_library_sources_ifdef(CONFIG_CAVS_ICTL irq.c) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/include/xtensa-cavs-linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series deleted file mode 100644 index d29c01a7988851..00000000000000 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.series +++ /dev/null @@ -1,50 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_INTEL_ADSP_CAVS - -config SOC_SERIES - string - default "cavs" - -config INTEL_ADSP_CAVS - def_bool y - -source "soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs*" - -config DMA_INTEL_ADSP_GPDMA - default y - depends on DMA - -config XTENSA_CCOUNT_HZ - default 400000000 - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config SMP - default y - -config XTENSA_TIMER - default n - -config KERNEL_ENTRY - default "_MainEntry" - -config MULTI_LEVEL_INTERRUPTS - default y - -config 2ND_LEVEL_INTERRUPTS - default y - -config DYNAMIC_INTERRUPTS - default y - -if LOG - -config LOG_BACKEND_ADSP - default y - -endif # LOG - -endif # SOC_SERIES_INTEL_ADSP_CAVS diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.series b/soc/xtensa/intel_adsp/cavs/Kconfig.series deleted file mode 100644 index a88bec1ec2e431..00000000000000 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.series +++ /dev/null @@ -1,16 +0,0 @@ -# Copyright (c) 2017,2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_INTEL_ADSP_CAVS - bool "Intel CAVS" - select SOC_FAMILY_INTEL_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")) - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" - select ATOMIC_OPERATIONS_ARCH if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xcc" - select ARCH_HAS_COHERENCE - select HAS_PM - help - Intel ADSP CAVS diff --git a/soc/xtensa/intel_adsp/cavs/Kconfig.soc b/soc/xtensa/intel_adsp/cavs/Kconfig.soc deleted file mode 100644 index 0d054e0ee2a39c..00000000000000 --- a/soc/xtensa/intel_adsp/cavs/Kconfig.soc +++ /dev/null @@ -1,13 +0,0 @@ -# Copyright (c) 2020 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "Intel CAVS SoC Selection" - depends on SOC_SERIES_INTEL_ADSP_CAVS - -config SOC_INTEL_CAVS_V25 - bool "Intel Tiger Lake" - select XTENSA_WAITI_BUG - select SCHED_IPI_SUPPORTED - -endchoice diff --git a/soc/xtensa/intel_adsp/common/CMakeLists.txt b/soc/xtensa/intel_adsp/common/CMakeLists.txt deleted file mode 100644 index c463e4453fcddf..00000000000000 --- a/soc/xtensa/intel_adsp/common/CMakeLists.txt +++ /dev/null @@ -1,149 +0,0 @@ -# Intel CAVS SoC family CMake file -# -# Copyright (c) 2020-2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -zephyr_interface_library_named(INTEL_ADSP_COMMON) - -zephyr_library_named(intel_adsp_common) -zephyr_include_directories(include) -zephyr_library_include_directories(${ZEPHYR_BASE}/drivers) - -zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_IPC ipc.c) - -zephyr_library_sources( - rimage_modules.c - boot.c - soc.c - mem_window.c - boot_complete.c - ) - -zephyr_library_sources_ifdef(CONFIG_ADSP_CLOCK clk.c) - -if(CONFIG_SMP OR CONFIG_MP_MAX_NUM_CPUS GREATER 1) - zephyr_library_sources(multiprocessing.c) -endif() - -zephyr_library_link_libraries(INTEL_ADSP_COMMON) - -target_include_directories(INTEL_ADSP_COMMON INTERFACE include) -target_link_libraries(INTEL_ADSP_COMMON INTERFACE intel_adsp_common) - -set(KERNEL_REMAPPED ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}-remapped.elf) -set(EXTMAN ${CMAKE_BINARY_DIR}/zephyr/extman.bin) - -if(${CMAKE_HOST_WIN32}) - set(NULL_FILE nul) -elseif(${CMAKE_HOST_UNIX}) - set(NULL_FILE /dev/null) -endif() - -# Generate rimage modules from the base kernel ELF file. Note the -# warning squashing on the objcopy steps. Binutils has a misfeature -# where if the copy removes all the sections from an input ELF program -# header (our link generates lots of phdrs because of the disjoint -# cacheability addresses), it will warn about an "empty" segment even -# though it was TOLD to drop the contents! -# -# Also note that rimage is picky with section flags: it will try to -# include a section in the output data (even its own metadata in -# .module!) if it has any of ALLOC, WRITABLE or EXEC flags in the ELF -# file. The GNU linker will set these automatically based on the -# flags of the sections coming out of C code, so this is fragile and -# breaks easily. Set noload flags explicitly here. -add_custom_target( - gen_modules ALL - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod -) - -add_custom_command( - OUTPUT ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod - COMMENT "Extracting .mod(ule) files for rimage" - DEPENDS ${ZEPHYR_FINAL_EXECUTABLE} ${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME} - - # The .fw_metadata section may not be present (xcc's older linker - # will remove it if empty). Extract it here (which will create an - # empty file if not present) and add it back when we generate the - # main.mod file below. - COMMAND ${CMAKE_OBJCOPY} -O binary --only-section=.fw_metadata - ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${EXTMAN} - - # Remap uncached section addresses so they appear contiguous - COMMAND ${CMAKE_COMMAND} -E - copy ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_NAME}.elf ${KERNEL_REMAPPED} - - # Extract modules for rimage - COMMAND ${CMAKE_OBJCOPY} - --only-section .imr - --only-section .imrdata - --only-section .module.boot - --set-section-flags .module.boot=noload,readonly - --rename-section .module.boot=.module - ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/boot.mod 2>${NULL_FILE} - - # Remove .fw_metadata here... - COMMAND ${CMAKE_OBJCOPY} - --remove-section .imr - --remove-section .imrdata - --remove-section .module.boot - --remove-section .fw_metadata - --set-section-flags .module.main=noload,readonly - --set-section-flags .static_uuid_entries=noload,readonly - --set-section-flags .static_log_entries=noload,readonly - --rename-section .module.main=.module - ${KERNEL_REMAPPED} ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} - - # ...and copy it back in - COMMAND ${CMAKE_OBJCOPY} - --add-section .fw_metadata=${EXTMAN} - --set-section-flags .fw_metadata=noload,readonly - ${CMAKE_BINARY_DIR}/zephyr/main.mod - ${CMAKE_BINARY_DIR}/zephyr/main.mod 2>${NULL_FILE} -) - -if(CONFIG_BUILD_OUTPUT_STRIPPED) -add_custom_command( - COMMENT "strip main.mod" - APPEND OUTPUT ${CMAKE_BINARY_DIR}/zephyr/main.mod - COMMAND $ - $ - $ - $${CMAKE_BINARY_DIR}/zephyr/main.mod - $${CMAKE_BINARY_DIR}/zephyr/main-stripped.mod - $ -) -endif() - - -# west sign -add_custom_target(zephyr.ri ALL - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri -) - -# If some of your board(s) need to override default rimage parameters -# then you can define WEST_SIGN_OPTS in boards/my/board/board.cmake. -# Example: -# -# set(WEST_SIGN_OPTS -- -c "/home/sweet home/rimage/config/abc.toml" -i 4) - -# Parameters after the double dash -- are passed through to rimage. For -# other ways to override default rimage parameters check -# boards/xtensa/intel_adsp_cavs25/doc/intel_adsp_generic.rst - -# Warning: because `west sign` can also be used interactively, using -# ${WEST_SIGN_OPTS} like this has _higher_ precedence than `west config -# rimage.extra-args`! Avoid overriding default rimage parameters in -# multiple places to avoid unexpected precedence rules. -add_custom_command( - OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri - COMMENT "west sign --if-tool-available --tool rimage ..." - # Use --if-tool-available so we don't force every CI to install - # rimage. We don't want to break build-only and other tests that don't - # require signing. When rimage is missing, `west flash` fails with a - # clear "zephyr.ri missing" error with an "rimage not found" warning - # from west sign immediately before it. - COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} - DEPENDS gen_modules - ${CMAKE_BINARY_DIR}/zephyr/boot.mod ${CMAKE_BINARY_DIR}/zephyr/main.mod -) diff --git a/soc/xtensa/nxp_adsp/CMakeLists.txt b/soc/xtensa/nxp_adsp/CMakeLists.txt deleted file mode 100644 index a0ab21fb6a8c1e..00000000000000 --- a/soc/xtensa/nxp_adsp/CMakeLists.txt +++ /dev/null @@ -1,27 +0,0 @@ -# NXP i.MX8/RT SoC family CMake file -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if(CONFIG_SOC_NXP_RT595) - zephyr_compile_definitions(CPU_MIMXRT595SFFOC_dsp) -endif() - -add_subdirectory(common) -zephyr_include_directories(${SOC_SERIES}/include) - -# west sign - -# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt -add_custom_target(zephyr.ri ALL - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri -) - -add_custom_command( - OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri - COMMENT "west sign --if-tool-available --tool rimage ..." - COMMAND west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS} - DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME} -) - -set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/${SOC_SERIES}/linker.ld CACHE INTERNAL "") diff --git a/soc/xtensa/nxp_adsp/Kconfig b/soc/xtensa/nxp_adsp/Kconfig deleted file mode 100644 index 486cb7bad54e13..00000000000000 --- a/soc/xtensa/nxp_adsp/Kconfig +++ /dev/null @@ -1,20 +0,0 @@ -# NXP i.MX8 SoC family configuration options -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_FAMILY_NXP_ADSP - bool - select ARCH_HAS_COHERENCE - select CPU_HAS_DCACHE - -if SOC_FAMILY_NXP_ADSP - -config SOC_FAMILY - string - default "nxp_adsp" - -# Select SoC Part No. and configuration options -source "soc/xtensa/nxp_adsp/*/Kconfig.soc" - -endif # SOC_FAMILY_NXP_ADSP diff --git a/soc/xtensa/nxp_adsp/Kconfig.defconfig b/soc/xtensa/nxp_adsp/Kconfig.defconfig deleted file mode 100644 index cdee20c75f5305..00000000000000 --- a/soc/xtensa/nxp_adsp/Kconfig.defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# NXP i.MX8/RT SoC family default configuration options -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_FAMILY_NXP_ADSP - -source "soc/xtensa/nxp_adsp/*/Kconfig.defconfig.series" - -config CACHE_MANAGEMENT - default y - -config SMP - default n - -config XTENSA_TIMER - default y - -config KERNEL_ENTRY - default "__start" - -config MULTI_LEVEL_INTERRUPTS - default n - -config 2ND_LEVEL_INTERRUPTS - default n - -# To prevent test uses TEST_LOGGING_MINIMAL -config TEST_LOGGING_DEFAULTS - default n - depends on TEST - -endif diff --git a/soc/xtensa/nxp_adsp/Kconfig.soc b/soc/xtensa/nxp_adsp/Kconfig.soc deleted file mode 100644 index c56da8e7551b1e..00000000000000 --- a/soc/xtensa/nxp_adsp/Kconfig.soc +++ /dev/null @@ -1,6 +0,0 @@ -# NXP i.MX8 SoC series selection -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -source "soc/xtensa/nxp_adsp/*/Kconfig.series" diff --git a/soc/xtensa/nxp_adsp/common/CMakeLists.txt b/soc/xtensa/nxp_adsp/common/CMakeLists.txt deleted file mode 100644 index 5c53c771f0841d..00000000000000 --- a/soc/xtensa/nxp_adsp/common/CMakeLists.txt +++ /dev/null @@ -1,6 +0,0 @@ -# NXP SoC family CMake file -# -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -zephyr_include_directories(include) diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qm b/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qm deleted file mode 100644 index e678be835925a2..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qm +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QM_ADSP - -config SOC - default "mimx8qm6" - -endif # SOC_MIMX8QM_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qxp b/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qxp deleted file mode 100644 index e4fcdd92fd0558..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8qxp +++ /dev/null @@ -1,9 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QXP_ADSP - -config SOC - default "mimx8qx6" - -endif # SOC_MIMX8QXP_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series deleted file mode 100644 index a5f4597f06917a..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.series +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_IMX8 - -config SOC_SERIES - string - default "imx8" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_imx_adsp" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 666000000 if XTENSA_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config DCACHE_LINE_SIZE - default 128 - -config GEN_IRQ_VECTOR_TABLE - default n - -source "soc/xtensa/nxp_adsp/imx8/Kconfig.defconfig.imx8q*" - -endif # SOC_SERIES_NXP_IMX8 diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.series b/soc/xtensa/nxp_adsp/imx8/Kconfig.series deleted file mode 100644 index 003784e842b144..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_IMX8 - bool "NXP i.MX8" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN - select GEN_ISR_TABLES - select XTENSA_SMALL_VECTOR_TABLE_ENTRY - help - NXP i.MX8 diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc b/soc/xtensa/nxp_adsp/imx8/Kconfig.soc deleted file mode 100644 index 33794a85c2be70..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc +++ /dev/null @@ -1,28 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP i.MX SoC Selection" - depends on SOC_SERIES_NXP_IMX8 - - config SOC_MIMX8QM_ADSP - bool "NXP i.MX8QM Audio DSP" - depends on SOC_SERIES_NXP_IMX8 - select HAS_MCUX - - config SOC_MIMX8QXP_ADSP - bool "NXP i.MX8QXP Audio DSP" - depends on SOC_SERIES_NXP_IMX8 - select HAS_MCUX -endchoice - -if SOC_SERIES_NXP_IMX8 - -config SOC_PART_NUMBER - string - default SOC_PART_NUMBER_MIMX8QM_DSP if SOC_MIMX8QM_ADSP - default SOC_PART_NUMBER_MIMX8QXP_DSP if SOC_MIMX8QXP_ADSP - -source "soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8q*" - -endif # SOC_SERIES_NXP_IMX8 diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm b/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm deleted file mode 100644 index fd5334cfee5d3b..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qm +++ /dev/null @@ -1,17 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QM_ADSP - -config SOC_PART_NUMBER_MIMX8QM6AVUFF - bool - -config SOC_PART_NUMBER_MIMX8QM_DSP - string - default "MIMX8QM6AVUFF_dsp" if SOC_PART_NUMBER_MIMX8QM6AVUFF - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -endif # SOC_MIMX8QM_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp b/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp deleted file mode 100644 index 20f0a13e11724f..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8/Kconfig.soc.imx8qxp +++ /dev/null @@ -1,21 +0,0 @@ -# Copyright 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_MIMX8QXP_ADSP - -config SOC_PART_NUMBER_MIMX8QX6AVLFZ - bool - -config SOC_PART_NUMBER_MIMX8QX6CVLDZ - bool - -config SOC_PART_NUMBER_MIMX8QXP_DSP - string - default "MIMX8QX6AVLFZ_dsp" if SOC_PART_NUMBER_MIMX8QX6AVLFZ - default "MIMX8QX6CVLDZ_dsp" if SOC_PART_NUMBER_MIMX8QX6CVLDZ - help - This string holds the full part number of the SoC. It is a hidden - option that you should not set directly. The part number selection - choice defines the default value for this string. - -endif # SOC_MIMX8QXP_ADSP diff --git a/soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series deleted file mode 100644 index 2d00a5e93d96f1..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8m/Kconfig.defconfig.series +++ /dev/null @@ -1,37 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_IMX8M - -config SOC_SERIES - string - default "imx8m" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_imx8m_adsp" - -if SOC_MIMX8M_ADSP - -config SOC - string - default "mimx8ml8" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 800000000 if XTENSA_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config DCACHE_LINE_SIZE - default 128 - -config DYNAMIC_INTERRUPTS - default y - -config GEN_IRQ_VECTOR_TABLE - default n - -endif # SOC_MIMX8M_ADSP - -endif # SOC_SERIES_NXP_IMX8M diff --git a/soc/xtensa/nxp_adsp/imx8m/Kconfig.series b/soc/xtensa/nxp_adsp/imx8m/Kconfig.series deleted file mode 100644 index 3847f52d2dad1b..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8m/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_IMX8M - bool "NXP i.MX8M Audio DSP Series" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN - select GEN_ISR_TABLES - select XTENSA_SMALL_VECTOR_TABLE_ENTRY - help - Enable support for NXP i.MX8M Audio DSP diff --git a/soc/xtensa/nxp_adsp/imx8m/Kconfig.soc b/soc/xtensa/nxp_adsp/imx8m/Kconfig.soc deleted file mode 100644 index 5ad3c1b9b1ecca..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8m/Kconfig.soc +++ /dev/null @@ -1,38 +0,0 @@ -# Copyright (c) 2021 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP i.MX8M Audio DSP Selection" - depends on SOC_SERIES_NXP_IMX8M - - config SOC_MIMX8M_ADSP - bool "NXP i.MX8MP Audio DSP" - select HAS_MCUX if CLOCK_CONTROL - select HAS_MCUX_CCM if CLOCK_CONTROL - select HAS_MCUX_IOMUXC if PINCTRL - select PINCTRL_IMX if HAS_MCUX_IOMUXC - -endchoice - -if SOC_SERIES_NXP_IMX8M - -config SOC_PART_NUMBER_MIMX8ML8DVNLZ - bool - -config SOC_PART_NUMBER_MIMX8ML8CVNKZ - bool - -config SOC_PART_NUMBER_MIMX8MP_DSP - string - default "MIMX8ML8DVNLZ_dsp" if SOC_PART_NUMBER_MIMX8ML8DVNLZ - default "MIMX8ML8CVNKZ_dsp" if SOC_PART_NUMBER_MIMX8ML8CVNKZ - help - This string holds the full part number of the SoC. It is a hidden option - that you should not set directly. The part number selection choice defines - the default value for this string. - -config SOC_PART_NUMBER - string - default SOC_PART_NUMBER_MIMX8MP_DSP if SOC_MIMX8M_ADSP - -endif # SOC_SERIES_NXP_IMX8M diff --git a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series deleted file mode 100644 index ebd9377660b018..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.defconfig.series +++ /dev/null @@ -1,30 +0,0 @@ -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_IMX8ULP - -config SOC_SERIES - string - default "imx8ulp" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_imx8ulp_adsp" - -config SOC - string - default "nxp_imx8ulp" - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 528000000 if XTENSA_TIMER - -config SYS_CLOCK_TICKS_PER_SEC - default 50000 - -config DCACHE_LINE_SIZE - default 128 - -config GEN_IRQ_VECTOR_TABLE - default n - -endif # SOC_SERIES_NXP_IMX8ULP diff --git a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series b/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series deleted file mode 100644 index 34e9b3a1a1dbc3..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.series +++ /dev/null @@ -1,15 +0,0 @@ -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_IMX8ULP - bool "NXP i.MX8ULP Audio DSP Series" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - select ATOMIC_OPERATIONS_BUILTIN - select GEN_ISR_TABLES - select XTENSA_SMALL_VECTOR_TABLE_ENTRY - help - Enable support for NXP i.MX8ULP Audio DSP diff --git a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc b/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc deleted file mode 100644 index b90fada22d4a4f..00000000000000 --- a/soc/xtensa/nxp_adsp/imx8ulp/Kconfig.soc +++ /dev/null @@ -1,11 +0,0 @@ -# Copyright (c) 2023 NXP -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP i.MX8ULP Audio DSP Selection" - depends on SOC_SERIES_NXP_IMX8ULP - - config SOC_NXP_IMX8ULP - bool "NXP i.MX8ULP Audio DSP" - -endchoice diff --git a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.defconfig.series b/soc/xtensa/nxp_adsp/rt5xx/Kconfig.defconfig.series deleted file mode 100644 index b5a56658c7da20..00000000000000 --- a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.defconfig.series +++ /dev/null @@ -1,46 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_NXP_RT5XX - -config SOC_SERIES - string - default "rt5xx" - -config SOC_TOOLCHAIN_NAME - string - default "nxp_rt500_adsp" - -config SOC - string - default "nxp_rt5xx" - -config SOC_PART_NUMBER - string - default "MIMXRT595SFFOC_dsp" if SOC_NXP_RT595 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default 198000000 - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config SYS_CLOCK_TICKS_PER_SEC - default 1000 - -config DYNAMIC_INTERRUPTS - default n - -config CACHE - default n - -config DCACHE - default n - -config CACHE_MANAGEMENT - default n - -config LOG - default n - -endif # SOC_SERIES_NXP_RT5XX diff --git a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.series b/soc/xtensa/nxp_adsp/rt5xx/Kconfig.series deleted file mode 100644 index 5135b881638a36..00000000000000 --- a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.series +++ /dev/null @@ -1,12 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -config SOC_SERIES_NXP_RT5XX - bool "NXP RT5xx Series" - select SOC_FAMILY_NXP_ADSP - select XTENSA - select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang") - select XTENSA_RESET_VECTOR - select XTENSA_USE_CORE_CRT1 - help - NXP RT5xx ADSP Series diff --git a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc b/soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc deleted file mode 100644 index e5b598c4f57089..00000000000000 --- a/soc/xtensa/nxp_adsp/rt5xx/Kconfig.soc +++ /dev/null @@ -1,10 +0,0 @@ -# Copyright (c) 2023 Google LLC. -# SPDX-License-Identifier: Apache-2.0 - -choice - prompt "NXP RT5xx ADSP SoC Selection" - - config SOC_NXP_RT595 - bool "NXP RT595" - depends on SOC_SERIES_NXP_RT5XX -endchoice diff --git a/soc/xtensa/sample_controller/Kconfig.defconfig b/soc/xtensa/sample_controller/Kconfig.defconfig deleted file mode 100644 index cc2040a5e93490..00000000000000 --- a/soc/xtensa/sample_controller/Kconfig.defconfig +++ /dev/null @@ -1,16 +0,0 @@ -# XTENSA board configuration - -# Copyright (c) 2016 Open-RnD Sp. z o.o. -# Copyright (c) 2016 Cadence Design Systems, Inc. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_XTENSA_SAMPLE_CONTROLLER - -config SOC - default "sample_controller" - -config SOC_TOOLCHAIN_NAME - string - default "sample_controller" - -endif diff --git a/soc/xtensa/sample_controller/Kconfig.soc b/soc/xtensa/sample_controller/Kconfig.soc deleted file mode 100644 index 0fbdce896c7bd0..00000000000000 --- a/soc/xtensa/sample_controller/Kconfig.soc +++ /dev/null @@ -1,8 +0,0 @@ -# Copyright (c) 2017 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -config SOC_XTENSA_SAMPLE_CONTROLLER - bool "Xtensa sample_controller core" - select XTENSA - select XTENSA_HAL - select ARCH_SUPPORTS_COREDUMP diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml index 02eb081df6a5b7..39faa5f38876ae 100644 --- a/submanifests/optional.yaml +++ b/submanifests/optional.yaml @@ -34,7 +34,7 @@ manifest: groups: - optional - name: sof - revision: 0606152d4aafc1f7ed43df1b1813252bfc74e154 + revision: 3e70d036a2df94b854add51742681b64ea0df729 path: modules/audio/sof remote: upstream groups: @@ -60,7 +60,7 @@ manifest: - optional - name: zscilib path: modules/lib/zscilib - revision: a4bb6cfd6800e14373261904825f7f34a3a7f2e5 + revision: ee1b287d9dd07208d2cc52284240ac25bb66eae3 remote: upstream groups: - optional diff --git a/subsys/bluetooth/controller/CMakeLists.txt b/subsys/bluetooth/controller/CMakeLists.txt index fa5c22f2e28819..36d093c803715b 100644 --- a/subsys/bluetooth/controller/CMakeLists.txt +++ b/subsys/bluetooth/controller/CMakeLists.txt @@ -188,7 +188,7 @@ zephyr_library_include_directories_ifdef( ) zephyr_library_include_directories_ifdef( - CONFIG_SOC_OPENISA_RV32M1_RISCV32 + CONFIG_SOC_OPENISA_RV32M1 ll_sw/openisa hci/openisa ) @@ -204,7 +204,7 @@ add_subdirectory_ifdef( ) add_subdirectory_ifdef( - CONFIG_SOC_OPENISA_RV32M1_RISCV32 + CONFIG_SOC_OPENISA_RV32M1 ll_sw/openisa ) diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig index 2f154ad7d5a3fd..bbd045b093c0f8 100644 --- a/subsys/bluetooth/controller/Kconfig +++ b/subsys/bluetooth/controller/Kconfig @@ -557,8 +557,8 @@ config BT_CTLR_FAL_SIZE int "LE Controller-based Privacy White List size" depends on BT_CTLR_FILTER_ACCEPT_LIST default 8 - range 1 8 if (SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1_RISCV32) - range 1 16 if !(SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1_RISCV32) + range 1 8 if (SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1) + range 1 16 if !(SOC_COMPATIBLE_NRF || SOC_OPENISA_RV32M1) help Set the size of the Filter Accept List for LE Controller-based Privacy. On nRF5x-based controllers, the hardware imposes a limit of 8 devices. @@ -569,7 +569,7 @@ config BT_CTLR_RL_SIZE depends on BT_CTLR_PRIVACY default 8 range 1 8 if SOC_COMPATIBLE_NRF - range 1 8 if SOC_OPENISA_RV32M1_RISCV32 + range 1 8 if SOC_OPENISA_RV32M1 help Set the size of the Resolving List for LE Controller-based Privacy. On nRF5x-based controllers, the hardware imposes a limit of 8 devices. diff --git a/subsys/bluetooth/controller/Kconfig.ll_sw_split b/subsys/bluetooth/controller/Kconfig.ll_sw_split index b3cd1e9f8f8e05..97f7161bf07bb4 100644 --- a/subsys/bluetooth/controller/Kconfig.ll_sw_split +++ b/subsys/bluetooth/controller/Kconfig.ll_sw_split @@ -63,7 +63,7 @@ config BT_LLL_VENDOR_NORDIC config BT_LLL_VENDOR_OPENISA bool "Use OpenISA LLL" - depends on SOC_OPENISA_RV32M1_RISCV32 + depends on SOC_OPENISA_RV32M1 select BT_CTLR_PHY_UPDATE_SUPPORT select BT_CTLR_EXT_REJ_IND_SUPPORT select BT_HAS_HCI_VS @@ -1209,7 +1209,7 @@ config BT_CTLR_PROFILE_ISR config BT_CTLR_DEBUG_PINS bool "Bluetooth Controller Debug Pins" - depends on BOARD_NRF51DK_NRF51422 || BOARD_NRF52DK_NRF52832 || BOARD_NRF52DK_NRF52810 || BOARD_NRF52840DK_NRF52840 || BOARD_NRF52833DK_NRF52833 || BOARD_NRF5340DK_NRF5340_CPUNET || BOARD_RV32M1_VEGA + depends on BOARD_NRF51DK_NRF51822 || BOARD_NRF52DK_NRF52832 || BOARD_NRF52DK_NRF52810 || BOARD_NRF52840DK_NRF52840 || BOARD_NRF52833DK_NRF52833 || BOARD_NRF5340DK_NRF5340_CPUNET || BOARD_RV32M1_VEGA help Turn on debug GPIO toggling for the BLE Controller. This is useful when debugging with a logic analyzer or profiling certain sections of diff --git a/subsys/bluetooth/controller/hci/hci_driver.c b/subsys/bluetooth/controller/hci/hci_driver.c index 8be4255cb4a275..fa3966c945f963 100644 --- a/subsys/bluetooth/controller/hci/hci_driver.c +++ b/subsys/bluetooth/controller/hci/hci_driver.c @@ -35,9 +35,9 @@ #include "hal/ccm.h" -#if defined(CONFIG_SOC_FAMILY_NRF) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) #include "hal/radio.h" -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ #include "ll_sw/pdu_df.h" #include "lll/pdu_vendor.h" diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h index 93229080688314..dca94d2a811053 100644 --- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h +++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/debug.h @@ -74,7 +74,7 @@ #define DEBUG_PIN7 BIT(18) #define DEBUG_PIN8 BIT(19) #define DEBUG_PIN9 BIT(20) -#elif defined(CONFIG_BOARD_NRF51DK_NRF51422) +#elif defined(CONFIG_BOARD_NRF51DK_NRF51822) #define DEBUG_PORT NRF_GPIO #define DEBUG_PIN0 BIT(12) #define DEBUG_PIN1 BIT(13) diff --git a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c index ccf18702dce7e0..e34dd883d4e8c6 100644 --- a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c +++ b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll_conn.c @@ -542,11 +542,11 @@ void lll_conn_pdu_tx_prep(struct lll_conn *lll, struct pdu_data **pdu_data_tx) p->rfu = 0U; -#if !defined(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +#if !defined(CONFIG_SOC_OPENISA_RV32M1) #if !defined(CONFIG_BT_CTLR_DATA_LENGTH_CLEAR) p->resv = 0U; #endif /* !CONFIG_BT_CTLR_DATA_LENGTH_CLEAR */ -#endif /* !CONFIG_SOC_OPENISA_RV32M1_RISCV32 */ +#endif /* !CONFIG_SOC_OPENISA_RV32M1 */ *pdu_data_tx = p; } diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c index 990e3472585db3..662837a96b56a8 100644 --- a/subsys/bluetooth/host/hci_core.c +++ b/subsys/bluetooth/host/hci_core.c @@ -18,7 +18,6 @@ #include #include #include -#include #include diff --git a/subsys/testsuite/Kconfig b/subsys/testsuite/Kconfig index 5fa2a240f4d425..266b8533025770 100644 --- a/subsys/testsuite/Kconfig +++ b/subsys/testsuite/Kconfig @@ -131,8 +131,8 @@ config TEST_ENABLE_USERSPACE bool depends on TEST_USERSPACE depends on ARCH_HAS_USERSPACE - select USERSPACE - select DYNAMIC_OBJECTS + imply USERSPACE + imply DYNAMIC_OBJECTS default y help This hidden option implements the TEST_USERSPACE logic. It turns on @@ -143,7 +143,7 @@ config TEST_ENABLE_USERSPACE config TEST_USERSPACE_WITHOUT_HW_STACK_PROTECTION bool "Run User Mode tests without additionally enabling stack protection" depends on TEST_ENABLE_USERSPACE - default y if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K1XX + default y if SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K1 help A HW platform might not have sufficient MPU/MMU capabilities to support running all test cases with User Mode and HW Stack Protection features diff --git a/subsys/testsuite/arch/Kconfig.v1 b/subsys/testsuite/arch/Kconfig.v1 new file mode 100644 index 00000000000000..28d4b43df0bbda --- /dev/null +++ b/subsys/testsuite/arch/Kconfig.v1 @@ -0,0 +1,4 @@ +# Copyright (c) 2023 Nordic Semiconductor ASA +# SPDX-License-Identifier: Apache-2.0 + +rsource "unit_testing/Kconfig" diff --git a/subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.board b/subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.board similarity index 100% rename from subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.board rename to subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.board diff --git a/subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.defconfig b/subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.defconfig similarity index 100% rename from subsys/testsuite/boards/unit_testing/unit_testing/Kconfig.defconfig rename to subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/Kconfig.defconfig diff --git a/subsys/testsuite/boards/unit_testing/unit_testing/unit_testing_defconfig b/subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/unit_testing_defconfig similarity index 100% rename from subsys/testsuite/boards/unit_testing/unit_testing/unit_testing_defconfig rename to subsys/testsuite/boards/boards_legacy/unit_testing/unit_testing/unit_testing_defconfig diff --git a/subsys/testsuite/soc/unit_testing/unit_testing/Kconfig.soc b/subsys/testsuite/soc/soc_legacy/unit_testing/unit_testing/Kconfig.soc similarity index 100% rename from subsys/testsuite/soc/unit_testing/unit_testing/Kconfig.soc rename to subsys/testsuite/soc/soc_legacy/unit_testing/unit_testing/Kconfig.soc diff --git a/tests/application_development/code_relocation/testcase.yaml b/tests/application_development/code_relocation/testcase.yaml index e67885390d8dfe..2fcf97b6aa629c 100644 --- a/tests/application_development/code_relocation/testcase.yaml +++ b/tests/application_development/code_relocation/testcase.yaml @@ -26,8 +26,8 @@ tests: - _CUSTOM_SECTION_NAME2 platform_allow: - qemu_cortex_m3 - - mps2_an385 - - sam_e70_xplained + - mps2/an385 + - sam_e70_xplained/same70q21 integration_platforms: - qemu_cortex_m3 application_development.code_relocation.riscv: diff --git a/tests/arch/arc/arc_dsp_sharing/testcase.yaml b/tests/arch/arc/arc_dsp_sharing/testcase.yaml index c2149b0570e8fe..67ade8fbbcd86a 100644 --- a/tests/arch/arc/arc_dsp_sharing/testcase.yaml +++ b/tests/arch/arc/arc_dsp_sharing/testcase.yaml @@ -1,8 +1,8 @@ tests: arch.arc.dsp_sharing.test_load_store: filter: CONFIG_ISA_ARCV2 and CONFIG_CPU_HAS_DSP - platform_allow: nsim_em11d + platform_allow: nsim/nsim_em11d arch.arc.dsp_sharing.test_calculation: filter: CONFIG_ISA_ARCV2 and CONFIG_CPU_HAS_DSP toolchain_allow: arcmwdt - platform_allow: nsim_em11d + platform_allow: nsim/nsim_em11d diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c index 61679107103e4d..eaf9ddd2a6d44b 100644 --- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c +++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c @@ -16,7 +16,7 @@ */ #define _ISR_OFFSET 0 -#if defined(CONFIG_SOC_FAMILY_NRF) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) #undef _ISR_OFFSET #if defined(CONFIG_BOARD_QEMU_CORTEX_M0) /* For the nRF51-based QEMU Cortex-M0 platform, the first set of consecutive @@ -34,7 +34,7 @@ /* For other nRF targets, use TIMER0-2 interrupt lines. */ #define _ISR_OFFSET TIMER0_IRQn #endif -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ struct k_sem sem[3]; @@ -130,7 +130,7 @@ ZTEST(vector_table, test_arm_irq_vector_table) typedef void (*vth)(void); /* Vector Table Handler */ -#if defined(CONFIG_SOC_FAMILY_NRF) +#if defined(CONFIG_SOC_FAMILY_NORDIC_NRF) /* nRF5X- and nRF91X-based platforms employ a Hardware RTC peripheral * to implement the Kernel system timer, instead of the ARM Cortex-M * SysTick. Therefore, a pointer to the timer ISR needs to be added in @@ -184,7 +184,7 @@ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, rtc_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT6XX) || defined(CONFIG_SOC_SERIES_IMX_RT5XX) && \ +#elif defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) && \ defined(CONFIG_MCUX_OS_TIMER) /* MXRT685 employs a OS Event timer to implement the Kernel system * timer, instead of the ARM Cortex-M SysTick. Therefore, a pointer to @@ -197,7 +197,8 @@ vth __irq_vector_table _irq_vector_table[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_lpc_ostick_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT) && defined(CONFIG_MCUX_GPT_TIMER) +#elif (defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)) && \ + defined(CONFIG_MCUX_GPT_TIMER) /** MXRT parts employ a GPT timer peripheral to implement the Kernel system * timer, instead of the ARM Cortex-M Systick. Thereforce, a pointer to the * timer ISR need to be added in the custom vector table to handle @@ -210,7 +211,7 @@ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_imx_gpt_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT10XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT10XX) /* RT10xx GPT timer interrupt is at offset 100 */ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -219,7 +220,7 @@ vth __irq_vector_table _irq_vector_table[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_imx_gpt_isr }; -#elif defined(CONFIG_SOC_SERIES_IMX_RT11XX) +#elif defined(CONFIG_SOC_SERIES_IMXRT11XX) /* RT11xx GPT timer interrupt is at offset 119 */ vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -236,7 +237,7 @@ vth __irq_vector_table _irq_vector_table[] = { vth __irq_vector_table _irq_vector_table[] = { isr0, isr1, isr2 }; -#endif /* CONFIG_SOC_FAMILY_NRF */ +#endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */ /** * @} diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml index b2cd459d1d30ca..638e54f59d7313 100644 --- a/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml +++ b/tests/arch/arm/arm_irq_zero_latency_levels/testcase.yaml @@ -1,6 +1,6 @@ common: filter: (CONFIG_ARMV6_M_ARMV8_M_BASELINE or CONFIG_ARMV7_M_ARMV8_M_MAINLINE) and - not CONFIG_SOC_FAMILY_NRF + not CONFIG_SOC_FAMILY_NORDIC_NRF tags: - arm - interrupt @@ -9,8 +9,8 @@ tests: arch.arm.irq_zero_latency_levels: filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE integration_platforms: - - mps2_an521_remote + - mps2/an521/cpu1 arch.arm.irq_zero_latency_levels.secure_fw: filter: CONFIG_TRUSTED_EXECUTION_SECURE integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 diff --git a/tests/arch/arm/arm_no_multithreading/testcase.yaml b/tests/arch/arm/arm_no_multithreading/testcase.yaml index 43ab80279f0376..855a94ca97e9e0 100644 --- a/tests/arch/arm/arm_no_multithreading/testcase.yaml +++ b/tests/arch/arm/arm_no_multithreading/testcase.yaml @@ -8,11 +8,11 @@ tests: platform_allow: - qemu_cortex_m0 - qemu_cortex_m3 - - mps2_an385 - - mps2_an521 - - mps3_an547 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf51dk_nrf51422 + - mps2/an385 + - mps2/an521/cpu0 + - mps3/an547 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf51dk/nrf51822 integration_platforms: - qemu_cortex_m0 diff --git a/tests/arch/arm/arm_sw_vector_relay/testcase.yaml b/tests/arch/arm/arm_sw_vector_relay/testcase.yaml index 37433433d914a5..7c5dfc149030aa 100644 --- a/tests/arch/arm/arm_sw_vector_relay/testcase.yaml +++ b/tests/arch/arm/arm_sw_vector_relay/testcase.yaml @@ -5,4 +5,4 @@ tests: - vector_relay arch_allow: arm integration_platforms: - - mps2_an385 + - mps2/an385 diff --git a/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_ns.overlay b/tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_ns.overlay rename to tests/arch/arm/arm_thread_swap_tz/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/tests/arch/arm/arm_thread_swap_tz/testcase.yaml b/tests/arch/arm/arm_thread_swap_tz/testcase.yaml index f8bbbc8dd93759..808aa5250d2b7e 100644 --- a/tests/arch/arm/arm_thread_swap_tz/testcase.yaml +++ b/tests/arch/arm/arm_thread_swap_tz/testcase.yaml @@ -9,16 +9,16 @@ tests: arch.arm.swap.tz: # NOTE: this platform disables FPU access in TFM. platform_exclude: - - mps3_an547_ns - - nucleo_l552ze_q_ns + - mps3/an547/ns + - nucleo_l552ze_q/stm32l552xx/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns arch.arm.swap.tz_off: extra_configs: - CONFIG_ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS=n # NOTE: this platform disables FPU access in TFM. platform_exclude: - - mps3_an547_ns - - nucleo_l552ze_q_ns + - mps3/an547/ns + - nucleo_l552ze_q/stm32l552xx/ns integration_platforms: - - mps2_an521_ns + - mps2/an521/cpu0/ns diff --git a/tests/arch/arm/arm_tz_wrap_func/testcase.yaml b/tests/arch/arm/arm_tz_wrap_func/testcase.yaml index ef0e1eda7dbd45..43826147ad814e 100644 --- a/tests/arch/arm/arm_tz_wrap_func/testcase.yaml +++ b/tests/arch/arm/arm_tz_wrap_func/testcase.yaml @@ -7,4 +7,4 @@ tests: - tz_wrap_func filter: CONFIG_CPU_CORTEX_M integration_platforms: - - mps2_an385 + - mps2/an385 diff --git a/tests/arch/arm64/arm64_smc_call/testcase.yaml b/tests/arch/arm64/arm64_smc_call/testcase.yaml index d6254cfa67dca9..763192878e67be 100644 --- a/tests/arch/arm64/arm64_smc_call/testcase.yaml +++ b/tests/arch/arm64/arm64_smc_call/testcase.yaml @@ -1,6 +1,6 @@ tests: arch.arm64.smc_call.smc: - platform_allow: fvp_base_revc_2xaemv8a_smp_ns + platform_allow: fvp_base_revc_2xaemv8a//smp/ns tags: - arm - smc diff --git a/tests/arch/common/ramfunc/boards/arty_a7_arm_designstart_m1.overlay b/tests/arch/common/ramfunc/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/arch/common/ramfunc/boards/arty_a7_arm_designstart_m1.overlay rename to tests/arch/common/ramfunc/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/benchmarks/app_kernel/testcase.yaml b/tests/benchmarks/app_kernel/testcase.yaml index 2b07dedad66663..32790a43e4e1be 100644 --- a/tests/benchmarks/app_kernel/testcase.yaml +++ b/tests/benchmarks/app_kernel/testcase.yaml @@ -8,11 +8,11 @@ common: tests: benchmark.kernel.application: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 benchmark.kernel.application.objcore.stats: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_configs: - CONFIG_OBJ_CORE=y @@ -34,7 +34,7 @@ tests: - CONFIG_OBJ_CORE_STATS=y benchmark.kernel.application.timeslicing: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_configs: - CONFIG_TIMESLICING=y @@ -42,7 +42,7 @@ tests: extra_args: CONF_FILE=prj_user.conf filter: CONFIG_ARCH_HAS_USERSPACE integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_configs: - CONFIG_TIMESLICING=y diff --git a/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml b/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml index c2527111322666..d63b4f0aa8323a 100644 --- a/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml +++ b/tests/benchmarks/cmsis_dsp/basicmath/testcase.yaml @@ -11,13 +11,13 @@ tests: benchmark.cmsis_dsp.basicmath: integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 benchmark.cmsis_dsp.basicmath.fpu: filter: CONFIG_CPU_HAS_FPU integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - fpu extra_configs: diff --git a/tests/benchmarks/footprints/testcase.yaml b/tests/benchmarks/footprints/testcase.yaml index 926b582ddcb86f..2e9165e8b8be08 100644 --- a/tests/benchmarks/footprints/testcase.yaml +++ b/tests/benchmarks/footprints/testcase.yaml @@ -6,14 +6,14 @@ tests: benchmark.kernel.footprints.default: build_only: true integration_platforms: - - mps2_an385 + - mps2/an385 benchmark.kernel.footprints.pm: tags: - pm build_only: true extra_args: CONF_FILE=prj_pm.conf integration_platforms: - - mps2_an385 + - mps2/an385 benchmark.kernel.footprints.userspace: filter: CONFIG_ARCH_HAS_USERSPACE extra_args: CONF_FILE=prj_userspace.conf @@ -25,4 +25,4 @@ tests: - userspace build_only: true integration_platforms: - - mps2_an385 + - mps2/an385 diff --git a/tests/benchmarks/latency_measure/boards/atsame54_xpro.conf b/tests/benchmarks/latency_measure/boards/same54_xpro.conf similarity index 100% rename from tests/benchmarks/latency_measure/boards/atsame54_xpro.conf rename to tests/benchmarks/latency_measure/boards/same54_xpro.conf diff --git a/tests/benchmarks/latency_measure/testcase.yaml b/tests/benchmarks/latency_measure/testcase.yaml index e6af80305c764b..76ed840c7cfa86 100644 --- a/tests/benchmarks/latency_measure/testcase.yaml +++ b/tests/benchmarks/latency_measure/testcase.yaml @@ -12,7 +12,7 @@ tests: harness: console integration_platforms: - qemu_x86 - - qemu_arc_em + - qemu_arc/qemu_arc_em harness_config: type: one_line record: @@ -30,7 +30,7 @@ tests: harness: console integration_platforms: - qemu_x86 - - qemu_arc_em + - qemu_arc/qemu_arc_em extra_configs: - CONFIG_OBJ_CORE=y - CONFIG_OBJ_CORE_STATS=y @@ -107,7 +107,7 @@ tests: harness: console integration_platforms: - qemu_x86 - - qemu_arc_em + - qemu_arc/qemu_arc_em extra_configs: - CONFIG_TIMESLICING=y harness_config: diff --git a/tests/benchmarks/sched/testcase.yaml b/tests/benchmarks/sched/testcase.yaml index 6ec2987d3352d0..9ae091c3d6249b 100644 --- a/tests/benchmarks/sched/testcase.yaml +++ b/tests/benchmarks/sched/testcase.yaml @@ -4,7 +4,7 @@ tests: - benchmark - kernel integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 slow: true harness: console diff --git a/tests/bluetooth/adv/testcase.yaml b/tests/bluetooth/adv/testcase.yaml index 12a927be910d81..d20f6436d1eb9b 100644 --- a/tests/bluetooth/adv/testcase.yaml +++ b/tests/bluetooth/adv/testcase.yaml @@ -2,10 +2,10 @@ tests: bluetooth.adv: platform_allow: - nrf52_bsim - - nrf51dk_nrf51422 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52840dk/nrf52840 tags: bluetooth slow: true timeout: 360 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/bluetooth/ctrl_user_ext/CMakeLists.txt b/tests/bluetooth/ctrl_user_ext/CMakeLists.txt index 087435e8884620..9a6673eb324916 100644 --- a/tests/bluetooth/ctrl_user_ext/CMakeLists.txt +++ b/tests/bluetooth/ctrl_user_ext/CMakeLists.txt @@ -13,7 +13,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connection_cte_req/CMakeLists.txt b/tests/bluetooth/df/connection_cte_req/CMakeLists.txt index 9b6dc63809092b..f2828b825aad8c 100644 --- a/tests/bluetooth/df/connection_cte_req/CMakeLists.txt +++ b/tests/bluetooth/df/connection_cte_req/CMakeLists.txt @@ -27,7 +27,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt b/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt index a2ae350c4f0f98..d03e6e15ba291d 100644 --- a/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt +++ b/tests/bluetooth/df/connection_cte_tx_params/CMakeLists.txt @@ -28,7 +28,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt b/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt index 4af6a0694ca1d9..cac22fa3401053 100644 --- a/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt +++ b/tests/bluetooth/df/connectionless_cte_rx/CMakeLists.txt @@ -26,7 +26,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt b/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt index 4af6a0694ca1d9..cac22fa3401053 100644 --- a/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt +++ b/tests/bluetooth/df/connectionless_cte_tx/CMakeLists.txt @@ -26,7 +26,7 @@ if(CONFIG_SOC_COMPATIBLE_NRF) ${ZEPHYR_BASE}/subsys/bluetooth/controller/ll_sw/nordic ${ZEPHYR_BASE}/subsys/bluetooth/hci/nordic ) -elseif(CONFIG_SOC_OPENISA_RV32M1_RISCV32) +elseif(CONFIG_SOC_OPENISA_RV32M1) zephyr_library_include_directories( ${ZEPHYR_BASE}/bluetooth/controller/ll_sw/openisa ${ZEPHYR_BASE}/bluetooth/hci/openisa diff --git a/tests/bluetooth/init/testcase.yaml b/tests/bluetooth/init/testcase.yaml index 060c51a3f81e3c..63267a96c8e5de 100644 --- a/tests/bluetooth/init/testcase.yaml +++ b/tests/bluetooth/init/testcase.yaml @@ -76,255 +76,255 @@ tests: bluetooth.init.test_ctlr: extra_args: CONF_FILE=prj_ctlr.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_4_0: extra_args: CONF_FILE=prj_ctlr_4_0.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_4_0_dbg: extra_args: CONF_FILE=prj_ctlr_4_0_dbg.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_tiny: extra_args: CONF_FILE=prj_ctlr_tiny.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_dbg: extra_args: - CONF_FILE=prj_ctlr_dbg.conf - DTC_OVERLAY_FILE=pa_lna.overlay platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_5_x_dbg: extra_args: - CONF_FILE=prj_ctlr_5_x_dbg.conf - DTC_OVERLAY_FILE=pa_lna.overlay platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_sw_switch_single_timer: extra_args: - CONF_FILE=prj_ctlr.conf - CONFIG_BT_CTLR_ADVANCED_FEATURES=y - CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER=y platform_allow: - - nrf5340dk_nrf5340_cpunet - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf5340dk/nrf5340/cpunet + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf5340dk_nrf5340_cpunet - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf5340dk/nrf5340/cpunet + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_ticker: extra_args: - CONF_FILE=prj_ctlr_ticker.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 bluetooth.init.test_ctlr_broadcaster: extra_args: CONF_FILE=prj_ctlr_broadcaster.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_peripheral: extra_args: CONF_FILE=prj_ctlr_peripheral.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_peripheral_priv: extra_args: CONF_FILE=prj_ctlr_peripheral_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_observer: extra_args: CONF_FILE=prj_ctlr_observer.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_central: extra_args: CONF_FILE=prj_ctlr_central.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_central_priv: extra_args: CONF_FILE=prj_ctlr_central_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 - - rv32m1_vega_ri5cy + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_ctlr_broadcaster_ext: extra_args: CONF_FILE=prj_ctlr_broadcaster_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_peripheral_ext: extra_args: CONF_FILE=prj_ctlr_peripheral_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_peripheral_ext_priv: extra_args: CONF_FILE=prj_ctlr_peripheral_ext_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_oberver_ext: extra_args: CONF_FILE=prj_ctlr_observer_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_central_ext: extra_args: CONF_FILE=prj_ctlr_central_ext.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_central_ext_priv: extra_args: CONF_FILE=prj_ctlr_central_ext_priv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_adv: extra_args: CONF_FILE=prj_ctlr_per_adv.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_adv_no_adi: extra_args: CONF_FILE=prj_ctlr_per_adv_no_adi.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_sync: extra_args: CONF_FILE=prj_ctlr_per_sync.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_sync_no_adi: extra_args: CONF_FILE=prj_ctlr_per_sync_no_adi.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_per_sync_no_filter: extra_args: CONF_FILE=prj_ctlr_per_sync_no_filter.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_peripheral_iso: extra_args: CONF_FILE=prj_ctlr_peripheral_iso.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_ctlr_central_iso: extra_args: CONF_FILE=prj_ctlr_central_iso.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 integration_platforms: - - nrf52840dk_nrf52840 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf51dk/nrf51822 bluetooth.init.test_h5: extra_args: CONF_FILE=prj_h5.conf platform_allow: qemu_cortex_m3 @@ -334,16 +334,16 @@ tests: bluetooth.init.test_llcp: extra_args: CONF_FILE=prj_llcp.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - rv32m1_vega/openisa_rv32m1/ri5cy integration_platforms: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - rv32m1_vega_ri5cy + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - rv32m1_vega/openisa_rv32m1/ri5cy bluetooth.init.test_config_bt_recv_workq_bt: extra_args: - CONF_FILE=prj_ctlr.conf - CONFIG_BT_RECV_WORKQ_BT=y platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/tests/bluetooth/mesh/basic/testcase.yaml b/tests/bluetooth/mesh/basic/testcase.yaml index 1e417baa343098..b299442f8acc75 100644 --- a/tests/bluetooth/mesh/basic/testcase.yaml +++ b/tests/bluetooth/mesh/basic/testcase.yaml @@ -3,7 +3,7 @@ tests: build_only: true platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -14,7 +14,7 @@ tests: extra_args: CONF_FILE=dbg.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -25,7 +25,7 @@ tests: extra_args: CONF_FILE=friend.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -36,7 +36,7 @@ tests: extra_args: CONF_FILE=gatt.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -47,7 +47,7 @@ tests: extra_args: CONF_FILE=lpn.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -58,7 +58,7 @@ tests: extra_args: CONF_FILE=pb_gatt.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -69,7 +69,7 @@ tests: extra_args: CONF_FILE=proxy.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -80,7 +80,7 @@ tests: extra_args: CONF_FILE=ext_adv.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: @@ -91,7 +91,7 @@ tests: extra_args: CONF_FILE=multi_ext_adv.conf platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 tags: diff --git a/tests/bluetooth/mesh_shell/testcase.yaml b/tests/bluetooth/mesh_shell/testcase.yaml index 5d08287a43c4fc..7e565b493a24ac 100644 --- a/tests/bluetooth/mesh_shell/testcase.yaml +++ b/tests/bluetooth/mesh_shell/testcase.yaml @@ -5,7 +5,7 @@ tests: bluetooth.mesh.mesh_shell: platform_allow: - qemu_x86 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml index c47b845a5dc23d..b561844db6e9b6 100644 --- a/tests/bluetooth/shell/testcase.yaml +++ b/tests/bluetooth/shell/testcase.yaml @@ -15,10 +15,10 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - qemu_x86 - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 tags: bluetooth harness: keyboard min_flash: 145 @@ -39,10 +39,10 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - native_sim - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 tags: bluetooth harness: keyboard min_flash: 350 @@ -59,7 +59,7 @@ tests: - native_sim_64 integration_platforms: - native_sim - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 tags: bluetooth harness: keyboard bluetooth.shell.no_privacy: diff --git a/tests/bluetooth/tester/testcase.yaml b/tests/bluetooth/tester/testcase.yaml index 37c7ab3193d08c..7721cabf15318e 100644 --- a/tests/bluetooth/tester/testcase.yaml +++ b/tests/bluetooth/tester/testcase.yaml @@ -5,7 +5,7 @@ tests: - qemu_x86 - native_posix - native_sim - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: bluetooth harness: bluetooth bluetooth.general.tester_le_audio: @@ -14,7 +14,7 @@ tests: - qemu_x86 - native_posix - native_sim - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp extra_args: OVERLAY_CONFIG="overlay-le-audio.conf" tags: bluetooth harness: bluetooth @@ -24,7 +24,7 @@ tests: - qemu_x86 - native_posix - native_sim - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG="overlay-mesh.conf" tags: bluetooth harness: bluetooth diff --git a/tests/boards/espressif_esp32/cache_coex/testcase.yaml b/tests/boards/espressif_esp32/cache_coex/testcase.yaml index 063d4e9fb3b0e4..a7205b75cd20a7 100644 --- a/tests/boards/espressif_esp32/cache_coex/testcase.yaml +++ b/tests/boards/espressif_esp32/cache_coex/testcase.yaml @@ -1,9 +1,9 @@ tests: boards.esp32.cache_coex: platform_allow: - - esp32_devkitc_wrover + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - - esp32s3_devkitm + - esp32s3_devkitm/esp32s3/procpu tags: - spiram - spiflash diff --git a/tests/boards/intel_adsp/cache/testcase.yaml b/tests/boards/intel_adsp/cache/testcase.yaml index 93aaae71841b85..7c2b30614faf22 100644 --- a/tests/boards/intel_adsp/cache/testcase.yaml +++ b/tests/boards/intel_adsp/cache/testcase.yaml @@ -2,6 +2,6 @@ common: tags: boards tests: boards.intel_adsp.cache: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/boards/intel_adsp/hda/testcase.yaml b/tests/boards/intel_adsp/hda/testcase.yaml index 7e801157de5a41..fd657b95b25e28 100644 --- a/tests/boards/intel_adsp/hda/testcase.yaml +++ b/tests/boards/intel_adsp/hda/testcase.yaml @@ -1,7 +1,7 @@ common: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 tests: boards.intel_adsp.hda: tags: diff --git a/tests/boards/intel_adsp/mm/testcase.yaml b/tests/boards/intel_adsp/mm/testcase.yaml index f7a80b8139fd12..c714f41fe009b8 100644 --- a/tests/boards/intel_adsp/mm/testcase.yaml +++ b/tests/boards/intel_adsp/mm/testcase.yaml @@ -2,4 +2,4 @@ common: tags: boards tests: boards.intel_adsp.mm: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 diff --git a/tests/boards/intel_adsp/smoke/testcase.yaml b/tests/boards/intel_adsp/smoke/testcase.yaml index 4339486839fa38..9561d1c2d57740 100644 --- a/tests/boards/intel_adsp/smoke/testcase.yaml +++ b/tests/boards/intel_adsp/smoke/testcase.yaml @@ -1,5 +1,5 @@ tests: boards.intel_adsp.smoke: - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/boards/intel_adsp/ssp/testcase.yaml b/tests/boards/intel_adsp/ssp/testcase.yaml index d196a487aff7ce..e524a87784f7e8 100644 --- a/tests/boards/intel_adsp/ssp/testcase.yaml +++ b/tests/boards/intel_adsp/ssp/testcase.yaml @@ -7,6 +7,6 @@ tests: depends_on: - dai - dma - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/boards/nrf52_bsim/egu/testcase.yaml b/tests/boards/nrf52_bsim/egu/testcase.yaml index 952a83781d558f..2f3f28f734e009 100644 --- a/tests/boards/nrf52_bsim/egu/testcase.yaml +++ b/tests/boards/nrf52_bsim/egu/testcase.yaml @@ -1,5 +1,5 @@ tests: boards.nrf52_bsim.egu: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nrf52_bsim diff --git a/tests/boot/mcuboot_data_sharing/testcase.yaml b/tests/boot/mcuboot_data_sharing/testcase.yaml index b12fb012f4ba4c..cc1ca4a4140ca2 100644 --- a/tests/boot/mcuboot_data_sharing/testcase.yaml +++ b/tests/boot/mcuboot_data_sharing/testcase.yaml @@ -7,7 +7,7 @@ common: sysbuild: true tests: bootloader.mcuboot.data.sharing: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - mcuboot - sysbuild diff --git a/tests/boot/mcuboot_recovery_retention/testcase.yaml b/tests/boot/mcuboot_recovery_retention/testcase.yaml index 084aedcba58c4f..8ec7fa4749621d 100644 --- a/tests/boot/mcuboot_recovery_retention/testcase.yaml +++ b/tests/boot/mcuboot_recovery_retention/testcase.yaml @@ -22,13 +22,13 @@ common: - "Boot source: none" tests: bootloader.mcuboot.recovery.retention: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - mcuboot - sysbuild - recovery bootloader.mcuboot.recovery.retention.mem: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG="boards/nrf52840dk_nrf52840_mem.conf" - DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_mem.overlay" diff --git a/tests/boot/test_mcuboot/testcase.yaml b/tests/boot/test_mcuboot/testcase.yaml index b4b7735c1c8557..6669dc5efdba73 100644 --- a/tests/boot/test_mcuboot/testcase.yaml +++ b/tests/boot/test_mcuboot/testcase.yaml @@ -20,7 +20,7 @@ tests: - lpcxpresso55s16 - lpcxpresso55s28 - lpcxpresso55s36 - - lpcxpresso55s69_cpu0 + - lpcxpresso55s69/lpc55s69/cpu0 - mimxrt1010_evk - mimxrt1015_evk - mimxrt1020_evk @@ -29,14 +29,14 @@ tests: - mimxrt1050_evk - mimxrt1060_evk - mimxrt1064_evk - - mimxrt1160_evk_cm7 - - mimxrt1170_evk_cm7 - - mimxrt595_evk_cm33 - - mimxrt685_evk_cm33 - - nrf52840dk_nrf52840 + - mimxrt1160_evk/mimxrt1166/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt595_evk/mimxrt595s/cm33 + - mimxrt685_evk + - nrf52840dk/nrf52840 integration_platforms: - frdm_k64f - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 bootloader.mcuboot.assert: tags: mcuboot platform_allow: diff --git a/tests/boot/with_mcumgr/README.rst b/tests/boot/with_mcumgr/README.rst index f3281f57c5c921..e937d08163cb6b 100644 --- a/tests/boot/with_mcumgr/README.rst +++ b/tests/boot/with_mcumgr/README.rst @@ -10,13 +10,13 @@ using **sysbuild**. Tests are automated with pytest, a new harness of Twister in the system PATH. More information about MCUmgr can be found here :ref:`mcu_mgr`. -To run tests with Twister on ``nrf52840dk_nrf52840`` platform, +To run tests with Twister on ``nrf52840dk/nrf52840`` platform, use following command: .. code-block:: console ./zephyr/scripts/twister -vv --west-flash --enable-slow -T zephyr/tests/boot/with_mcumgr \ - -p nrf52840dk_nrf52840 --device-testing --device-serial /dev/ttyACM0 + -p nrf52840dk/nrf52840 --device-testing --device-serial /dev/ttyACM0 .. note:: Twister requires ``--west-flash`` flag enabled (without additional parameters diff --git a/tests/boot/with_mcumgr/testcase.yaml b/tests/boot/with_mcumgr/testcase.yaml index 08904c177bd219..3926819e6f2ffd 100644 --- a/tests/boot/with_mcumgr/testcase.yaml +++ b/tests/boot/with_mcumgr/testcase.yaml @@ -1,11 +1,11 @@ common: sysbuild: true platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 timeout: 600 slow: true tests: diff --git a/tests/crypto/rand32/testcase.yaml b/tests/crypto/rand32/testcase.yaml index 5db814833669f3..5561511b2c6e1a 100644 --- a/tests/crypto/rand32/testcase.yaml +++ b/tests/crypto/rand32/testcase.yaml @@ -33,4 +33,4 @@ tests: tags: - psa-crypto integration_platforms: - - nrf5340dk_nrf5340_cpuapp_ns + - nrf5340dk/nrf5340/cpuapp/ns diff --git a/tests/crypto/tinycrypt/testcase.yaml b/tests/crypto/tinycrypt/testcase.yaml index ac08d94fd9580c..74c4853a9cca76 100644 --- a/tests/crypto/tinycrypt/testcase.yaml +++ b/tests/crypto/tinycrypt/testcase.yaml @@ -6,8 +6,8 @@ tests: - aes - ccm platform_exclude: - - qemu_arc_em - - qemu_arc_hs + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs - m2gl025_miv timeout: 500 integration_platforms: diff --git a/tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_sense.overlay b/tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_nrf52840_sense.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_sense.overlay rename to tests/drivers/adc/adc_api/boards/arduino_nano_33_ble_nrf52840_sense.overlay diff --git a/tests/drivers/adc/adc_api/boards/hexiwear_k64.overlay b/tests/drivers/adc/adc_api/boards/hexiwear_mk64f12.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/hexiwear_k64.overlay rename to tests/drivers/adc/adc_api/boards/hexiwear_mk64f12.overlay diff --git a/tests/drivers/adc/adc_api/boards/hexiwear_kw40z.overlay b/tests/drivers/adc/adc_api/boards/hexiwear_mkw40z4.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/hexiwear_kw40z.overlay rename to tests/drivers/adc/adc_api/boards/hexiwear_mkw40z4.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/adc/adc_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/adc/adc_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/adc/adc_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/adc/adc_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.conf b/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.conf similarity index 100% rename from tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.conf rename to tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.conf diff --git a/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.overlay b/tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/adc/adc_api/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/adc/adc_api/boards/rpi_pico_w.overlay b/tests/drivers/adc/adc_api/boards/rpi_pico_rp2040_w.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/rpi_pico_w.overlay rename to tests/drivers/adc/adc_api/boards/rpi_pico_rp2040_w.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam4e_xpro.overlay b/tests/drivers/adc/adc_api/boards/sam4e_xpro.overlay new file mode 100644 index 00000000000000..3486ce077fc6a1 --- /dev/null +++ b/tests/drivers/adc/adc_api/boards/sam4e_xpro.overlay @@ -0,0 +1,25 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + * + * Copyright (c) 2024 Gerson Fernando Budke + */ + +/ { + zephyr,user { + io-channels = <&afec0 0>; + }; +}; + +&afec0 { + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + zephyr,gain = "ADC_GAIN_1"; + zephyr,reference = "ADC_REF_EXTERNAL0"; + zephyr,acquisition-time = ; + zephyr,resolution = <12>; + zephyr,input-positive = <15>; + }; +}; diff --git a/tests/drivers/adc/adc_api/boards/sam_e70_xplained.overlay b/tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_e70_xplained.overlay rename to tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam_e70b_xplained.overlay b/tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21b.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_e70b_xplained.overlay rename to tests/drivers/adc/adc_api/boards/sam_e70_xplained_same70q21b.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam_v71_xult.overlay b/tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_v71_xult.overlay rename to tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21.overlay diff --git a/tests/drivers/adc/adc_api/boards/sam_v71b_xult.overlay b/tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21b.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/sam_v71b_xult.overlay rename to tests/drivers/adc/adc_api/boards/sam_v71_xult_samv71q21b.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamc21n_xpro.overlay b/tests/drivers/adc/adc_api/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamc21n_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samc21n_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamd20_xpro.overlay b/tests/drivers/adc/adc_api/boards/samd20_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamd20_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samd20_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamd21_xpro.overlay b/tests/drivers/adc/adc_api/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamd21_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samd21_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsame54_xpro.overlay b/tests/drivers/adc/adc_api/boards/same54_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsame54_xpro.overlay rename to tests/drivers/adc/adc_api/boards/same54_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsaml21_xpro.overlay b/tests/drivers/adc/adc_api/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsaml21_xpro.overlay rename to tests/drivers/adc/adc_api/boards/saml21_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamr21_xpro.overlay b/tests/drivers/adc/adc_api/boards/samr21_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamr21_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samr21_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/atsamr34_xpro.overlay b/tests/drivers/adc/adc_api/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/atsamr34_xpro.overlay rename to tests/drivers/adc/adc_api/boards/samr34_xpro.overlay diff --git a/tests/drivers/adc/adc_api/boards/xiao_ble_sense.overlay b/tests/drivers/adc/adc_api/boards/xiao_ble_nrf52840_sense.overlay similarity index 100% rename from tests/drivers/adc/adc_api/boards/xiao_ble_sense.overlay rename to tests/drivers/adc/adc_api/boards/xiao_ble_nrf52840_sense.overlay diff --git a/tests/drivers/audio/dmic_api/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/audio/dmic_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/audio/dmic_api/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/audio/dmic_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/audio/dmic_api/testcase.yaml b/tests/drivers/audio/dmic_api/testcase.yaml index 960aad3323a809..28f9643f6caee1 100644 --- a/tests/drivers/audio/dmic_api/testcase.yaml +++ b/tests/drivers/audio/dmic_api/testcase.yaml @@ -5,4 +5,4 @@ tests: harness: ztest filter: dt_alias_exists("dmic-dev") integration_platforms: - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 diff --git a/tests/drivers/build_all/adc/testcase.yaml b/tests/drivers/build_all/adc/testcase.yaml index 0d2df1769ea745..9c4afb9cc0d549 100644 --- a/tests/drivers/build_all/adc/testcase.yaml +++ b/tests/drivers/build_all/adc/testcase.yaml @@ -26,13 +26,13 @@ tests: drivers.adc.npcx.build: platform_allow: npcx7m6fb_evb drivers.adc.nrf.build: - platform_allow: nrf51dk_nrf51422 + platform_allow: nrf51dk/nrf51822 drivers.adc.nrf.saadc.build: - platform_allow: nrf21540dk_nrf52840 + platform_allow: nrf21540dk/nrf52840 drivers.adc.sam0.build: - platform_allow: atsame54_xpro + platform_allow: same54_xpro drivers.adc.sam.afec.build: - platform_allow: sam_e70_xplained + platform_allow: sam_e70_xplained/same70q21 drivers.adc.stm32.build: platform_allow: disco_l475_iot1 drivers.adc.xec.build: diff --git a/tests/drivers/build_all/counter/boards/arty_a7_arm_designstart_m1.overlay b/tests/drivers/build_all/counter/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/drivers/build_all/counter/boards/arty_a7_arm_designstart_m1.overlay rename to tests/drivers/build_all/counter/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/drivers/build_all/counter/testcase.yaml b/tests/drivers/build_all/counter/testcase.yaml index ff50c81289cb7d..d5861c45eae1da 100644 --- a/tests/drivers/build_all/counter/testcase.yaml +++ b/tests/drivers/build_all/counter/testcase.yaml @@ -5,6 +5,6 @@ common: - counter tests: drivers.counter.build.xlnx: - platform_allow: arty_a7_arm_designstart_m1 + platform_allow: arty_a7/designstart_fpga_cortex_m1 extra_configs: - CONFIG_COUNTER_XLNX_AXI_TIMER=y diff --git a/tests/drivers/build_all/dac/boards/atsamd21_xpro.overlay b/tests/drivers/build_all/dac/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/build_all/dac/boards/atsamd21_xpro.overlay rename to tests/drivers/build_all/dac/boards/samd21_xpro.overlay diff --git a/tests/drivers/build_all/dac/testcase.yaml b/tests/drivers/build_all/dac/testcase.yaml index a298ded77b466d..4192c6ca0856de 100644 --- a/tests/drivers/build_all/dac/testcase.yaml +++ b/tests/drivers/build_all/dac/testcase.yaml @@ -15,6 +15,6 @@ tests: drivers.dac.mcux32.build: platform_allow: twr_ke18f drivers.dac.sam0.build: - platform_allow: atsamd21_xpro + platform_allow: samd21_xpro drivers.dac.stm32.build: platform_allow: nucleo_f091rc diff --git a/tests/drivers/build_all/gpio/testcase.yaml b/tests/drivers/build_all/gpio/testcase.yaml index 88d62c5b7707ed..b3f761413962d0 100644 --- a/tests/drivers/build_all/gpio/testcase.yaml +++ b/tests/drivers/build_all/gpio/testcase.yaml @@ -26,7 +26,7 @@ tests: drivers.gpio.build.adc_ads1145s0x_gpio: min_ram: 32 - platform_allow: m5stack_core2 nrf52840dk_nrf52840 + platform_allow: m5stack_core2/esp32/procpu nrf52840dk/nrf52840 depends_on: - gpio - adc diff --git a/tests/drivers/build_all/ieee802154/testcase.yaml b/tests/drivers/build_all/ieee802154/testcase.yaml index 1d9ab3617f94a6..176cd1acff16f6 100644 --- a/tests/drivers/build_all/ieee802154/testcase.yaml +++ b/tests/drivers/build_all/ieee802154/testcase.yaml @@ -15,7 +15,7 @@ tests: drivers.ieee802154.build.mcr20a: platform_allow: usb_kw24d512 drivers.ieee802154.build.nrf5: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 drivers.ieee802154.build.telink_b91: platform_allow: tlsr9518adk80d drivers.ieee802154.build.upipe: diff --git a/tests/drivers/build_all/pwm/boards/arty_a7_arm_designstart_m1.overlay b/tests/drivers/build_all/pwm/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/drivers/build_all/pwm/boards/arty_a7_arm_designstart_m1.overlay rename to tests/drivers/build_all/pwm/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/drivers/build_all/pwm/testcase.yaml b/tests/drivers/build_all/pwm/testcase.yaml index 61d93f789d0753..3bcb57b6100194 100644 --- a/tests/drivers/build_all/pwm/testcase.yaml +++ b/tests/drivers/build_all/pwm/testcase.yaml @@ -7,9 +7,9 @@ tests: drivers.pwm.cc13xx_cc26xx_timer.build: platform_allow: cc1352p1_launchxl drivers.pwm.gecko.build: - platform_allow: efr32_radio_brd4250b + platform_allow: efr32_radio/efr32fg1p133f256gm48 drivers.pwm.imx.build: - platform_allow: colibri_imx7d_m4 + platform_allow: colibri_imx7d/mcimx7d/m4 drivers.pwm.litex.build: platform_allow: litex_vexriscv drivers.pwm.mcux.ftm.build: @@ -23,32 +23,32 @@ tests: drivers.pwm.mcux.build: platform_allow: mimxrt1064_evk drivers.pwm.mcux.sctimer.build: - platform_allow: mimxrt685_evk_cm33 + platform_allow: mimxrt685_evk drivers.pwm.rv32m1.tpm.build: - platform_allow: rv32m1_vega_ri5cy + platform_allow: rv32m1_vega/openisa_rv32m1/ri5cy drivers.pwm.sifive.build: - platform_allow: hifive1_revb + platform_allow: hifive1@B drivers.pwm.npcx.build: platform_allow: npcx7m6fb_evb drivers.pwm.nrf.sw.build: - platform_allow: nrf51dk_nrf51422 + platform_allow: nrf51dk/nrf51822 drivers.pwm.nrf.build: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 drivers.pwm.pca9685.build: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: SHIELD=adafruit_pca9685 drivers.pwm.sam0.tcc.build: - platform_allow: atsame54_xpro + platform_allow: same54_xpro drivers.pwm.build.sam: platform_allow: - - sam_e70_xplained - - sam_v71b_xult + - sam_e70_xplained/same70q21 + - sam_v71_xult/samv71q21b drivers.pwm.stm32.build: platform_allow: disco_l475_iot1 drivers.pwm.xec.build: platform_allow: mec15xxevb_assy6853 drivers.pwm.build.xlnx: - platform_allow: arty_a7_arm_designstart_m1 + platform_allow: arty_a7/designstart_fpga_cortex_m1 drivers.pwm.build.test: platform_allow: qemu_cortex_m3 drivers.pwm.max31790.build: diff --git a/tests/drivers/can/api/testcase.yaml b/tests/drivers/can/api/testcase.yaml index 9ee9777fcef177..75bb509f827efb 100644 --- a/tests/drivers/can/api/testcase.yaml +++ b/tests/drivers/can/api/testcase.yaml @@ -16,12 +16,12 @@ tests: extra_args: DTC_OVERLAY_FILE=twai-enable.overlay filter: dt_compat_enabled("espressif,esp32-twai") platform_allow: - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32c3_devkitm - esp32s2_saola - - esp32s3_devkitm - - xiao_esp32s3 + - esp32s3_devkitm/esp32s3/procpu + - xiao_esp32s3/esp32s3/procpu drivers.can.api.nxp_s32_canxl.non_rx_fifo: extra_configs: - CONFIG_CAN_NXP_S32_RX_FIFO=n diff --git a/tests/drivers/charger/sbs_charger/testcase.yaml b/tests/drivers/charger/sbs_charger/testcase.yaml index 7256c6530e9d72..75c9994b8f5e0b 100644 --- a/tests/drivers/charger/sbs_charger/testcase.yaml +++ b/tests/drivers/charger/sbs_charger/testcase.yaml @@ -12,13 +12,13 @@ tests: DTC_OVERLAY_FILE="boards/emulated_board.overlay" platform_exclude: - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 + - xenvm/xenvm/gicv3 - hifive_unmatched - - rcar_h3ulcb_ca57 - - rcar_salvator_xs_m3 + - rcar_h3ulcb/r8a77951/a57 + - rcar_salvator_xs - numaker_pfm_m467 drivers.charger.sbs.emulated_64_bit_i2c_addr: tags: @@ -29,10 +29,10 @@ tests: (CONFIG_QEMU_TARGET or CONFIG_ARCH_POSIX) platform_allow: - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 + - xenvm/xenvm/gicv3 extra_args: CONF_FILE="prj.conf;boards/qemu_cortex_a53.conf" DTC_OVERLAY_FILE="boards/qemu_cortex_a53.overlay" diff --git a/tests/drivers/clock_control/adsp_clock/testcase.yaml b/tests/drivers/clock_control/adsp_clock/testcase.yaml index 48df05a8462353..04de6e55838f48 100644 --- a/tests/drivers/clock_control/adsp_clock/testcase.yaml +++ b/tests/drivers/clock_control/adsp_clock/testcase.yaml @@ -3,6 +3,6 @@ tests: tags: - drivers - clock_control - platform_allow: intel_adsp_cavs25 + platform_allow: intel_adsp/cavs25 integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 diff --git a/tests/drivers/clock_control/clock_control_api/testcase.yaml b/tests/drivers/clock_control/clock_control_api/testcase.yaml index be789c8382a316..7a3552fd4e7d77 100644 --- a/tests/drivers/clock_control/clock_control_api/testcase.yaml +++ b/tests/drivers/clock_control/clock_control_api/testcase.yaml @@ -4,20 +4,20 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 drivers.clock.clock_control_nrf5_lfclk_rc: tags: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_args: CONF_FILE="nrf_lfclk_rc.conf" diff --git a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml index 092471d30e4d69..2e2934b33eacdb 100644 --- a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml +++ b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml @@ -4,8 +4,8 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml index f4940d79896f69..a5716326ab9b71 100644 --- a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml +++ b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml @@ -3,124 +3,124 @@ common: - drivers - clock_control integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 tests: drivers.clock.nrf_lf_clock_start_xtal_stable: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 drivers.clock.nrf_lf_clock_start_xtal_available: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 drivers.clock.nrf_lf_clock_start_xtal_no_wait: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_NO_WAIT=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y drivers.clock.nrf_lf_clock_start_rc_stable: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y drivers.clock.nrf_lf_clock_start_rc_available: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y drivers.clock.nrf_lf_clock_start_rc_no_wait: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_NO_WAIT=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y drivers.clock.nrf_lf_clock_start_synth_stable: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y drivers.clock.nrf_lf_clock_start_synth_available: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y drivers.clock.nrf_lf_clock_start_synth_no_wait: platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf5340dk_nrf5340_cpunet + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf5340dk/nrf5340/cpunet integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 extra_configs: - CONFIG_SYSTEM_CLOCK_NO_WAIT=y - CONFIG_CLOCK_CONTROL_NRF_K32SRC_SYNTH=y diff --git a/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml b/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml index 19c774969335aa..4f5eff4456ba86 100644 --- a/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml +++ b/tests/drivers/clock_control/nrf_onoff_and_bt/testcase.yaml @@ -4,8 +4,8 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/drivers/clock_control/onoff/testcase.yaml b/tests/drivers/clock_control/onoff/testcase.yaml index a6e03d9a0eca88..91239e3b5382cd 100644 --- a/tests/drivers/clock_control/onoff/testcase.yaml +++ b/tests/drivers/clock_control/onoff/testcase.yaml @@ -4,9 +4,9 @@ tests: - drivers - clock_control platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 integration_platforms: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_cm33_rtc_1khz.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_rtc_1khz.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_cm33_rtc_1khz.overlay rename to tests/drivers/counter/counter_basic_api/boards/mimxrt685_evk_rtc_1khz.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51422.overlay b/tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/counter/counter_basic_api/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/counter/counter_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_m7.overlay b/tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_m7.overlay rename to tests/drivers/counter/counter_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/tests/drivers/counter/counter_basic_api/testcase.yaml b/tests/drivers/counter/counter_basic_api/testcase.yaml index f6210c0bc747cf..f4f1120fdf9501 100644 --- a/tests/drivers/counter/counter_basic_api/testcase.yaml +++ b/tests/drivers/counter/counter_basic_api/testcase.yaml @@ -12,7 +12,7 @@ tests: - drivers - counter depends_on: counter - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 timeout: 400 extra_configs: - CONFIG_ZERO_LATENCY_IRQS=y @@ -32,7 +32,7 @@ tests: - drivers - counter depends_on: counter - platform_allow: mimxrt685_evk_cm33 + platform_allow: mimxrt685_evk timeout: 400 extra_args: - DTC_OVERLAY_FILE="boards/mimxrt685_evk_cm33_rtc_1khz.overlay" + DTC_OVERLAY_FILE="boards/mimxrt685_evk_rtc_1khz.overlay" diff --git a/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml b/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml index 5c46deb6e6161e..af42d7b327cbd0 100644 --- a/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml +++ b/tests/drivers/counter/counter_nrf_rtc/fixed_top/testcase.yaml @@ -4,4 +4,4 @@ tests: - drivers - counter depends_on: counter - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 diff --git a/tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51422.overlay b/tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/counter/maxim_ds3231_api/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/dac/dac_api/src/test_dac.c b/tests/drivers/dac/dac_api/src/test_dac.c index 53ffb2ac0e9a57..612aa824ec0bee 100644 --- a/tests/drivers/dac/dac_api/src/test_dac.c +++ b/tests/drivers/dac/dac_api/src/test_dac.c @@ -57,7 +57,7 @@ #elif defined(CONFIG_BOARD_BL652_DVK) || \ defined(CONFIG_BOARD_BL653_DVK) || \ defined(CONFIG_BOARD_BL654_DVK) || \ - defined(CONFIG_BOARD_BL5340_DVK_CPUAPP) + defined(CONFIG_BOARD_BL5340_DVK) /* Note external DAC MCP4725 is not populated on BL652_DVK, BL653_DVK and * BL654_DVK at factory */ diff --git a/tests/drivers/dac/dac_loopback/src/test_dac.c b/tests/drivers/dac/dac_loopback/src/test_dac.c index 9b571bf384c600..38d71c4b8a1dd6 100644 --- a/tests/drivers/dac/dac_loopback/src/test_dac.c +++ b/tests/drivers/dac/dac_loopback/src/test_dac.c @@ -144,7 +144,7 @@ #elif defined(CONFIG_BOARD_BL652_DVK) || \ defined(CONFIG_BOARD_BL653_DVK) || \ defined(CONFIG_BOARD_BL654_DVK) || \ - defined(CONFIG_BOARD_BL5340_DVK_CPUAPP) + defined(CONFIG_BOARD_BL5340_DVK) #include /* DAC output from MCP4725 pin 1 * On BL65x ADC_1 input is read from pin SIO_3 @@ -184,7 +184,7 @@ static const struct adc_channel_cfg adc_ch_cfg = { #if defined(CONFIG_BOARD_BL652_DVK) || \ defined(CONFIG_BOARD_BL653_DVK) || \ defined(CONFIG_BOARD_BL654_DVK) || \ - defined(CONFIG_BOARD_BL5340_DVK_CPUAPP) || \ + defined(CONFIG_BOARD_BL5340_DVK) || \ defined(CONFIG_BOARD_LPCXPRESSO55S36) .input_positive = ADC_1ST_CHANNEL_INPUT, #endif diff --git a/tests/drivers/dac/dac_loopback/testcase.yaml b/tests/drivers/dac/dac_loopback/testcase.yaml index f1a682f2f5b11e..1a2c06758b6314 100644 --- a/tests/drivers/dac/dac_loopback/testcase.yaml +++ b/tests/drivers/dac/dac_loopback/testcase.yaml @@ -20,7 +20,7 @@ tests: - bl652_dvk - bl653_dvk - bl654_dvk - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp - stm32f3_disco - stm32l562e_dk - nucleo_l552ze_q diff --git a/tests/drivers/disk/disk_performance/testcase.yaml b/tests/drivers/disk/disk_performance/testcase.yaml index af008bf56e000d..5f39653838a943 100644 --- a/tests/drivers/disk/disk_performance/testcase.yaml +++ b/tests/drivers/disk/disk_performance/testcase.yaml @@ -10,7 +10,7 @@ tests: tags: sdhc integration_platforms: - mimxrt1064_evk - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 drivers.disk.disk_performance.disk.nvme: extra_configs: - CONFIG_NVME=y diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000000..cdc6eb7c7f19b8 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000000..5e8bafa1d9b1b0 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000000..f3ceb4ecbb8a9f --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_NOCACHE_MEMORY=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000000..5e8bafa1d9b1b0 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000000..cdc6eb7c7f19b8 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000000..5e8bafa1d9b1b0 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000000..433a67585be577 --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM" diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000000..82f0bbe94e899a --- /dev/null +++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&dtcm { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma0 { }; diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsamc21n_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsamc21n_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/samc21n_xpro.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsamd21_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsamd21_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/samd21_xpro.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsaml21_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsaml21_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/saml21_xpro.overlay diff --git a/tests/drivers/dma/chan_blen_transfer/boards/atsamr34_xpro.overlay b/tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/dma/chan_blen_transfer/boards/atsamr34_xpro.overlay rename to tests/drivers/dma/chan_blen_transfer/boards/samr34_xpro.overlay diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/dma/chan_link_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000000..9d2f44e723160c --- /dev/null +++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2022 Kumar Gala + * + * SPDX-License-Identifier: Apache-2.0 + */ + +dma0: &edma0 { }; diff --git a/tests/drivers/dma/chan_link_transfer/testcase.yaml b/tests/drivers/dma/chan_link_transfer/testcase.yaml index 930ab1067ebca9..23bb9c6bc8ac3d 100644 --- a/tests/drivers/dma/chan_link_transfer/testcase.yaml +++ b/tests/drivers/dma/chan_link_transfer/testcase.yaml @@ -7,14 +7,14 @@ tests: - dma platform_allow: - frdm_k64f - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 - mimxrt1050_evk - mimxrt1060_evk - mimxrt1064_evk - - mimxrt1160_evk_cm7 - - mimxrt1170_evk_cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 - mimxrt1024_evk - - lpcxpresso55s69_cpu0 + - lpcxpresso55s69/lpc55s69/cpu0 - lpcxpresso55s36 - native_posix - native_posix_64 diff --git a/tests/drivers/dma/loop_transfer/boards/longan_nano_lite.overlay b/tests/drivers/dma/loop_transfer/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/longan_nano_lite.overlay rename to tests/drivers/dma/loop_transfer/boards/longan_nano_gd32vf103_lite.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000000..cdc6eb7c7f19b8 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000000..5e8bafa1d9b1b0 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.conf diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000000..cdc6eb7c7f19b8 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000000..5e8bafa1d9b1b0 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000000..cdc6eb7c7f19b8 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000000..5e8bafa1d9b1b0 --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&sram1 { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma_lpsr0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000000..8aa11602c69fda --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000000..43b7fc3782656a --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2022 Kumar Gala + * Copyright (c) 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&itcm { + zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>; +}; + +tst_dma0: &edma0 { }; diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000000..8aa11602c69fda --- /dev/null +++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_CODE_DATA_RELOCATION=y +CONFIG_MEM_ATTR_HEAP=y +CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="ITCM" diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/dma/loop_transfer/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsamc21n_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsamc21n_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsamd21_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsamd21_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsaml21_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsaml21_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay diff --git a/tests/drivers/dma/loop_transfer/boards/atsamr34_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/dma/loop_transfer/boards/atsamr34_xpro.overlay rename to tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay diff --git a/tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/dma/scatter_gather/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/dma/scatter_gather/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/dma/scatter_gather/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/dma/scatter_gather/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/dma/scatter_gather/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/dma/scatter_gather/testcase.yaml b/tests/drivers/dma/scatter_gather/testcase.yaml index 6b05448a96cac3..78b5e0f115ef84 100644 --- a/tests/drivers/dma/scatter_gather/testcase.yaml +++ b/tests/drivers/dma/scatter_gather/testcase.yaml @@ -5,7 +5,7 @@ tests: - drivers - dma platform_allow: - - intel_adsp_cavs25 + - intel_adsp/cavs25 - frdm_k64f - mimxrt1060_evk - lpcxpresso55s36 @@ -13,6 +13,6 @@ tests: - native_posix_64 filter: dt_alias_exists("dma0") integration_platforms: - - intel_adsp_cavs25 + - intel_adsp/cavs25 - native_posix - native_posix_64 diff --git a/tests/drivers/flash/common/boards/b_u585i_iot02a_ns.overlay b/tests/drivers/flash/common/boards/b_u585i_iot02a_stm32u585xx_ns.overlay similarity index 100% rename from tests/drivers/flash/common/boards/b_u585i_iot02a_ns.overlay rename to tests/drivers/flash/common/boards/b_u585i_iot02a_stm32u585xx_ns.overlay diff --git a/tests/drivers/flash/common/boards/mimxrt595_evk_cm33.conf b/tests/drivers/flash/common/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/flash/common/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/flash/common/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf b/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf index 60f91e378f90b0..f995a2d2993f25 100644 --- a/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf +++ b/tests/drivers/flash/common/boards/nrf52840_flash_qspi.conf @@ -1,4 +1,4 @@ # Minimal configuration for testing flash driver -# on nrf52840dk_nrf52840 board +# on nrf52840dk/nrf52840 board CONFIG_NORDIC_QSPI_NOR=y diff --git a/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf b/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf index 3e24ed6e555250..f28de713011145 100644 --- a/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf +++ b/tests/drivers/flash/common/boards/nrf52840_flash_soc.conf @@ -1,4 +1,4 @@ # Minimal configuration for testing flash driver -# on nrf52840dk_nrf52840 board +# on nrf52840dk/nrf52840 board CONFIG_MPU_ALLOW_FLASH_WRITE=y diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml index c7a60cbff5c91c..7b7827db069767 100644 --- a/tests/drivers/flash/common/testcase.yaml +++ b/tests/drivers/flash/common/testcase.yaml @@ -4,31 +4,31 @@ common: - flash tests: drivers.flash.common.nrf_qspi_nor: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.nrf_qspi_nor.size_in_bytes: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840_size_in_bytes.overlay integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.nrf_qspi_nor_4B_addr: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840_flash_qspi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_mx25l51245g.overlay harness_config: fixture: external_flash_mx25l51245g integration_platforms: - - nrf52840dk_nrf52840 - drivers.flash.common.soc_flash_nrf: - platform_allow: nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 + drivers.flash.common.soc_flash/nrf: + platform_allow: nrf52840dk/nrf52840 extra_args: OVERLAY_CONFIG=boards/nrf52840_flash_soc.conf integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.default: filter: ((CONFIG_FLASH_HAS_DRIVER_ENABLED and not CONFIG_TRUSTED_EXECUTION_NONSECURE) and dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")) @@ -40,7 +40,7 @@ tests: filter: (CONFIG_FLASH_HAS_DRIVER_ENABLED and CONFIG_TRUSTED_EXECUTION_NONSECURE and dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")) integration_platforms: - - nrf9161dk_nrf9161_ns + - nrf9161dk/nrf9161/ns drivers.flash.common.stm32: platform_allow: - nucleo_f103rb @@ -57,32 +57,32 @@ tests: - nucleo_wb55rg - nucleo_wl55jc - stm32l562e_dk - - stm32l562e_dk_ns + - stm32l562e_dk/stm32l562xx/ns integration_platforms: - nucleo_f103rb filter: (dt_compat_enabled("st,stm32-flash-controller") or dt_compat_enabled("st,stm32h7-flash-controller")) and dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions") drivers.flash.common.mx25r_high_perf: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_mx25r_high_perf.overlay integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.flash.common.mr_canhubk3_sfdp_runtime: platform_allow: mr_canhubk3 extra_configs: - CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME=y drivers.flash.common.spi_nor: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_spi_nor.overlay harness_config: fixture: external_flash_mx25v1635f drivers.flash.common.spi_nor_wp_hold: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG=boards/nrf52840dk_flash_spi.conf - DTC_OVERLAY_FILE=boards/nrf52840dk_spi_nor_wp_hold.overlay @@ -90,9 +90,9 @@ tests: fixture: external_flash_mx25v1635f drivers.flash.common.sam0: platform_allow: - - atsamd20_xpro - - atsamr21_xpro - - atsame54_xpro + - samd20_xpro + - samr21_xpro + - same54_xpro drivers.flash.common.gd32: platform_allow: - gd32vf103v_eval diff --git a/tests/drivers/flash/erase_blocks/testcase.yaml b/tests/drivers/flash/erase_blocks/testcase.yaml index 2382563bd4e1a8..5be1ff92c1f0ad 100644 --- a/tests/drivers/flash/erase_blocks/testcase.yaml +++ b/tests/drivers/flash/erase_blocks/testcase.yaml @@ -11,7 +11,7 @@ tests: harness: ztest build_only: true platform_allow: - - sam_v71_xult + - sam_v71_xult/samv71q21 - b_u585i_iot02a - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp diff --git a/tests/drivers/flash/stm32/testcase.yaml b/tests/drivers/flash/stm32/testcase.yaml index f3346c96052e9a..fe13b3444fd4f2 100644 --- a/tests/drivers/flash/stm32/testcase.yaml +++ b/tests/drivers/flash/stm32/testcase.yaml @@ -14,7 +14,7 @@ tests: dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions") drivers.flash.stm32.l4: platform_allow: - - nucleo_l452re_p + - nucleo_l452re/stm32l452xx/p - disco_l475_iot1 extra_configs: - CONFIG_FLASH_STM32_READOUT_PROTECTION=y diff --git a/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml b/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml index 97d25b26a050b8..bcdcd84127bbf8 100644 --- a/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml +++ b/tests/drivers/fuel_gauge/sbs_gauge/testcase.yaml @@ -12,12 +12,12 @@ tests: platform_exclude: - hifive_unmatched - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 - - rcar_h3ulcb_ca57 - - rcar_salvator_xs_m3 + - xenvm/xenvm/gicv3 + - rcar_h3ulcb/r8a77951/a57 + - rcar_salvator_xs integration_platforms: - qemu_x86 drivers.fuel_gauge.sbs_gauge_new_api.emulated_64_bit_i2c_addr: @@ -30,10 +30,10 @@ tests: platform_allow: - hifive_unmatched - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_kvm_arm64 - xenvm - - xenvm_gicv3 + - xenvm/xenvm/gicv3 integration_platforms: - qemu_cortex_a53 extra_args: diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_api_1pin/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_api_1pin/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml index 18b8bc1bd696c8..66f36a4a14f6a9 100644 --- a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml +++ b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml @@ -7,7 +7,8 @@ tests: min_flash: 48 # Fix exclude when we can exclude just sim run platform_exclude: - - mps2_an385 - - mps2_an521 + - mps2/an385 + - mps2/an521/cpu0 - neorv32 + - hifive1 # see #69350 filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_cpuapp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_nrf5340_cpuapp.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_cpuapp.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/bl5340_dvk_nrf5340_cpuapp.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/hifive1_revb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/hifive1_fe310_B.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/hifive1_revb.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/hifive1_fe310_B.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_lpc54114_m4.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_m4.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/lpcxpresso54114_lpc54114_m4.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_ri5cy.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_ri5cy.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained.overlay b/tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/atsamd21_xpro.overlay b/tests/drivers/gpio/gpio_basic_api/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/atsamd21_xpro.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/samd21_xpro.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_m7.overlay b/tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_m7.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/stm32h747i_disco_stm32h747xx_m7.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_mcimx6x_m4.overlay similarity index 100% rename from tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_m4.overlay rename to tests/drivers/gpio/gpio_basic_api/boards/udoo_neo_full_mcimx6x_m4.overlay diff --git a/tests/drivers/gpio/gpio_basic_api/src/main.c b/tests/drivers/gpio/gpio_basic_api/src/main.c index 143be7d314d2cd..67326505e986c8 100644 --- a/tests/drivers/gpio/gpio_basic_api/src/main.c +++ b/tests/drivers/gpio/gpio_basic_api/src/main.c @@ -10,7 +10,7 @@ /* Grotesque hack for pinmux boards */ #if defined(CONFIG_BOARD_RV32M1_VEGA) #include -#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_M4) +#elif defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4) #include "device_imx.h" #elif defined(CONFIG_BOARD_MIMXRT1050_EVK) #include @@ -32,7 +32,7 @@ static void board_setup(void) } #endif -#if defined(CONFIG_BOARD_UDOO_NEO_FULL_M4) +#if defined(CONFIG_BOARD_UDOO_NEO_FULL_MCIMX6X_M4) /* * Configure pin mux. * The following code needs to configure the same GPIOs which were diff --git a/tests/drivers/gpio/gpio_basic_api/testcase.yaml b/tests/drivers/gpio/gpio_basic_api/testcase.yaml index cc572e82ef06d0..e431230f5aa13d 100644 --- a/tests/drivers/gpio/gpio_basic_api/testcase.yaml +++ b/tests/drivers/gpio/gpio_basic_api/testcase.yaml @@ -13,7 +13,7 @@ tests: filter: dt_compat_enabled("test-gpio-basic-api") drivers.gpio.nrf_sense_edge: - platform_allow: nrf52840dk_nrf52840 nrf52_bsim + platform_allow: nrf52840dk/nrf52840 nrf52_bsim extra_args: "DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840.overlay;\ boards/nrf52840dk_nrf52840_sense_edge.overlay" diff --git a/tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_get_direction/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_get_direction/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_get_direction/testcase.yaml b/tests/drivers/gpio/gpio_get_direction/testcase.yaml index a957a3cb1b84fd..b66145fc9af4aa 100644 --- a/tests/drivers/gpio/gpio_get_direction/testcase.yaml +++ b/tests/drivers/gpio/gpio_get_direction/testcase.yaml @@ -7,7 +7,7 @@ tests: min_flash: 48 # Fix exclude when we can exclude just sim run platform_exclude: - - mps2_an385 - - mps2_an521 + - mps2/an385 + - mps2/an521/cpu0 - neorv32 filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds") diff --git a/tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/gpio/gpio_hogs/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/gpio/gpio_hogs/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/gpio/gpio_hogs/testcase.yaml b/tests/drivers/gpio/gpio_hogs/testcase.yaml index 98e279b789c810..357ed4388c3b70 100644 --- a/tests/drivers/gpio/gpio_hogs/testcase.yaml +++ b/tests/drivers/gpio/gpio_hogs/testcase.yaml @@ -8,12 +8,14 @@ tests: - native_sim - native_sim_64 - frdm_k64f - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nucleo_g474re - nrf52_bsim - mr_canhubk3 - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 integration_platforms: - native_sim - native_sim_64 diff --git a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt index 1079605a2b4178..39ef8a7b979539 100644 --- a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt +++ b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/CMakeLists.txt @@ -13,8 +13,8 @@ target_include_directories(app PRIVATE zephyr_include_directories( include - ${ZEPHYR_BASE}/soc/riscv/ite_ec/common - ${ZEPHYR_BASE}/soc/riscv/ite_ec/it8xxx2 + ${ZEPHYR_BASE}/soc/ite/ec/common + ${ZEPHYR_BASE}/soc/ite/ec/it8xxx2 ) target_sources(app diff --git a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h index d3c1f7c827eb13..67c86ccdc40525 100644 --- a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h +++ b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include <../soc/riscv/ite_ec/common/chip_chipregs.h> +#include <../soc/ite/ec/common/chip_chipregs.h> /* * Macros for emulated hardware registers access. diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay similarity index 100% rename from tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000000..4e17adc5dce5b8 --- /dev/null +++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,25 @@ +/* + * Copyright 2023 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/* To test this sample, connect J26.12 <-> J10.20 and J26.10 <-> J10.18 */ + +&lpi2c1 { + status = "okay"; + eeprom0: eeprom@54 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x54>; + size = <1024>; + }; +}; + +&lpi2c5 { + status = "okay"; + eeprom1: eeprom@56 { + compatible = "zephyr,i2c-target-eeprom"; + reg = <0x56>; + size = <1024>; + }; +}; diff --git a/tests/drivers/i2c/i2c_tca954x/testcase.yaml b/tests/drivers/i2c/i2c_tca954x/testcase.yaml index 0f6d12b77c5a05..2304bc62c5610e 100644 --- a/tests/drivers/i2c/i2c_tca954x/testcase.yaml +++ b/tests/drivers/i2c/i2c_tca954x/testcase.yaml @@ -6,4 +6,4 @@ tests: - drivers depends_on: i2c filter: dt_compat_enabled("ti,tca9546a") - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 diff --git a/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/i2s/i2s_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/i2s/i2s_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/i2s/i2s_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/sam_e70_xplained.overlay b/tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/sam_e70_xplained.overlay rename to tests/drivers/i2s/i2s_api/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/i2s/i2s_api/boards/sam_v71_xult.overlay b/tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from tests/drivers/i2s/i2s_api/boards/sam_v71_xult.overlay rename to tests/drivers/i2s/i2s_api/boards/sam_v71_xult_samv71q21.overlay diff --git a/tests/drivers/i2s/i2s_api/testcase.yaml b/tests/drivers/i2s/i2s_api/testcase.yaml index 5d8b66e29ac7f3..84a1d2bede97cb 100644 --- a/tests/drivers/i2s/i2s_api/testcase.yaml +++ b/tests/drivers/i2s/i2s_api/testcase.yaml @@ -6,8 +6,8 @@ tests: - userspace filter: not CONFIG_I2S_TEST_USE_GPIO_LOOPBACK platform_exclude: - - mimxrt595_evk_cm33 - - mimxrt685_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 + - mimxrt685_evk drivers.i2s.gpio_loopback: depends_on: - i2s @@ -18,7 +18,7 @@ tests: filter: CONFIG_I2S_TEST_USE_GPIO_LOOPBACK harness: ztest platform_exclude: - - mimxrt595_evk_cm33 - - mimxrt685_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 + - mimxrt685_evk harness_config: fixture: gpio_loopback diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_rt1176_cm7.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_rt1176_cm7.conf new file mode 100644 index 00000000000000..9473f58b112c52 --- /dev/null +++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_rt1176_cm7.conf @@ -0,0 +1,25 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +# SAI peripheral does not have loopback mode. Use 2 SAI peripherals connected +# together externally. +CONFIG_I2S_TEST_SEPARATE_DEVICES=y + +# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs) +# together, and should be sized as needed by the application. If not large +# enough, the DMA may starve. Symptoms of this issue include transmit blocks +# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3. +CONFIG_DMA_TCD_QUEUE_SIZE=4 + +# Repeat test continually to help find intermittent issues +CONFIG_ZTEST_RETEST_IF_PASSED=y + +# I2S and DMA logging can occur in interrupt context, and interfere with I2S +# stream timing. If using either logging, set logging to deferred +# CONFIG_LOG_MODE_DEFERRED=y + +CONFIG_DMA_LOG_LEVEL_OFF=y +CONFIG_I2S_LOG_LEVEL_OFF=y diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/i2s/i2s_speed/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/i2s/i2s_speed/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/mbox/mbox_data/CMakeLists.txt b/tests/drivers/mbox/mbox_data/CMakeLists.txt index a410ac3d214940..fa444f592df913 100644 --- a/tests/drivers/mbox/mbox_data/CMakeLists.txt +++ b/tests/drivers/mbox/mbox_data/CMakeLists.txt @@ -9,10 +9,10 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm7") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm7") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu0")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as Main in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/tests/drivers/mbox/mbox_data/Kconfig.sysbuild b/tests/drivers/mbox/mbox_data/Kconfig.sysbuild index 2ddab22817754b..66a4e929ae2f95 100644 --- a/tests/drivers/mbox/mbox_data/Kconfig.sysbuild +++ b/tests/drivers/mbox/mbox_data/Kconfig.sysbuild @@ -6,7 +6,7 @@ source "share/sysbuild/Kconfig" config REMOTE_BOARD string - default "mimxrt1170_evkb_cm4" if $(BOARD) = "mimxrt1170_evkb_cm7" - default "mimxrt1170_evk_cm4" if $(BOARD) = "mimxrt1170_evk_cm7" - default "mimxrt1160_evk_cm4" if $(BOARD) = "mimxrt1160_evk_cm7" - default "lpcxpresso55s69_cpu1" if $(BOARD) = "lpcxpresso55s69_cpu0" + default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb" + default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk" + default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk" + default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69" diff --git a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.conf b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.conf rename to tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.conf diff --git a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.overlay b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_cpu0.overlay rename to tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf new file mode 100644 index 00000000000000..583b495036082b --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf new file mode 100644 index 00000000000000..583b495036082b --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_INCLUDE_REMOTE_DIR=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000000..870b9928faf9e2 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,29 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c48000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c48000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c48000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf new file mode 100644 index 00000000000000..0dfb100ed70476 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf @@ -0,0 +1,3 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_SECOND_CORE_MCUX=y +CONFIG_INCLUDE_REMOTE_DIR=y diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay new file mode 100644 index 00000000000000..870b9928faf9e2 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay @@ -0,0 +1,29 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c48000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c48000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c48000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; diff --git a/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt b/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt index 47e1cae86284fd..234d58a2164369 100644 --- a/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt +++ b/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt @@ -7,10 +7,10 @@ cmake_minimum_required(VERSION 3.20.0) find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE}) -if(("${BOARD}" STREQUAL "mimxrt1170_evkb_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1170_evk_cm4") OR - ("${BOARD}" STREQUAL "mimxrt1160_evk_cm4") OR - ("${BOARD}" STREQUAL "lpcxpresso55s69_cpu1")) +if(("${BOARD}" STREQUAL "mimxrt1170_evkb") OR + ("${BOARD}" STREQUAL "mimxrt1170_evk") OR + ("${BOARD}" STREQUAL "mimxrt1160_evk") OR + ("${BOARD}" STREQUAL "lpcxpresso55s69")) message(STATUS "${BOARD} compile as remote in this sample") else() message(FATAL_ERROR "${BOARD} is not supported for this sample") diff --git a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf similarity index 100% rename from tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.conf rename to tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.conf diff --git a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay similarity index 100% rename from tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_cpu1.overlay rename to tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000000..3f6115b9c583b7 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000000..3f6115b9c583b7 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,54 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf new file mode 100644 index 00000000000000..0d36a72aec6a91 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf @@ -0,0 +1,4 @@ +CONFIG_MBOX_NXP_IMX_MU=y +CONFIG_BUILD_OUTPUT_INFO_HEADER=y +CONFIG_BUILD_OUTPUT_HEX=y +CONFIG_SECOND_CORE_MCUX=y diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay new file mode 100644 index 00000000000000..e3576826702554 --- /dev/null +++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay @@ -0,0 +1,55 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + chosen { + zephyr,flash = &ocram; + zephyr,console = &lpuart2; + zephyr,shell-uart = &lpuart2; + + /* Delete ipc chosen property where old IPM mailbox driver bellow is + * configured. + */ + /delete-property/ zephyr,ipc; + }; + + soc { + /delete-node/ gpt@400f0000; + + /* Replace GPT2 with another GPT kernel timer */ + gpt2_hw_timer:gpt@400f0000 { + compatible = "nxp,gpt-hw-timer"; + reg = <0x400f0000 0x4000>; + interrupts = <120 0>; + status = "okay"; + }; + + /* Delete IPM Driver node nxp,imx-mu */ + /delete-node/ mailbox@40c4c000; + + /* Attach MBOX driver to MU Unit */ + mbox:mbox@40c4c000 { + compatible = "nxp,mbox-imx-mu"; + reg = <0x40c4c000 0x4000>; + interrupts = <118 0>; + rx-channels = <4>; + #mbox-cells = <1>; + status = "okay"; + }; + }; + +}; + +/* Enable secondary LPUART */ +&lpuart2 { + status = "okay"; + current-speed = <115200>; +}; + +/* Disable primary GPT timer */ +&gpt_hw_timer { + status = "disabled"; +}; diff --git a/tests/drivers/mbox/mbox_data/sysbuild.cmake b/tests/drivers/mbox/mbox_data/sysbuild.cmake index 5c536a6229aaad..91ee9bf4b6bbc6 100644 --- a/tests/drivers/mbox/mbox_data/sysbuild.cmake +++ b/tests/drivers/mbox/mbox_data/sysbuild.cmake @@ -16,9 +16,9 @@ ExternalZephyrProject_Add( BOARD ${SB_CONFIG_REMOTE_BOARD} ) -if ("${BOARD}" STREQUAL "mimxrt1170_evkb_cm7" OR - "${BOARD}" STREQUAL "mimxrt1170_evk_cm7" OR - "${BOARD}" STREQUAL "mimxrt1160_evk_cm7" +if ("${BOARD}" STREQUAL "mimxrt1170_evkb" OR + "${BOARD}" STREQUAL "mimxrt1170_evk" OR + "${BOARD}" STREQUAL "mimxrt1160_evk" ) # For these NXP boards the main core application is dependent on # 'zephyr_image_info.h' generated by remote application. diff --git a/tests/drivers/mbox/mbox_data/testcase.yaml b/tests/drivers/mbox/mbox_data/testcase.yaml index 72aff63ac3ac08..0044581cdb8e96 100644 --- a/tests/drivers/mbox/mbox_data/testcase.yaml +++ b/tests/drivers/mbox/mbox_data/testcase.yaml @@ -5,10 +5,10 @@ tests: - mbox sysbuild: true platform_allow: - - mimxrt1170_evkb_cm7 - - mimxrt1170_evk_cm7 - - mimxrt1160_evk_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - mimxrt1170_evk/mimxrt1176/cm7 + - mimxrt1160_evk/mimxrt1166/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 integration_platforms: - - mimxrt1170_evkb_cm7 - - lpcxpresso55s69_cpu0 + - mimxrt1170_evk@B/mimxrt1176/cm7 + - lpcxpresso55s69/lpc55s69/cpu0 diff --git a/tests/drivers/mm/sys_mm_drv_api/testcase.yaml b/tests/drivers/mm/sys_mm_drv_api/testcase.yaml index e25212a3e0a4f4..10c9480cc1ee90 100644 --- a/tests/drivers/mm/sys_mm_drv_api/testcase.yaml +++ b/tests/drivers/mm/sys_mm_drv_api/testcase.yaml @@ -5,4 +5,4 @@ tests: - mm filter: dt_compat_enabled("intel,adsp-mtl-tlb") or dt_compat_enabled("intel,adsp-tlb") integration_platforms: - - intel_adsp_ace15_mtpm + - intel_adsp/ace15_mtpm diff --git a/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml b/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml index 73ce465b0e65ef..3bdd847797d26f 100644 --- a/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml +++ b/tests/drivers/mm/sys_mm_drv_bank/testcase.yaml @@ -5,4 +5,4 @@ tests: - mm filter: dt_compat_enabled("intel,adsp-mtl-tlb") or dt_compat_enabled("intel,adsp-tlb") integration_platforms: - - intel_adsp_ace15_mtpm + - intel_adsp/ace15_mtpm diff --git a/tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_cr7.overlay b/tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_r8a77951_r7.overlay similarity index 100% rename from tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_cr7.overlay rename to tests/drivers/pwm/pwm_api/boards/rcar_h3ulcb_r8a77951_r7.overlay diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c index 867025d99b149c..c04bca4568a73b 100644 --- a/tests/drivers/pwm/pwm_api/src/test_pwm.c +++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c @@ -54,7 +54,7 @@ #error "Define a PWM device" #endif -#if defined(CONFIG_BOARD_COLIBRI_IMX7D_M4) || defined(CONFIG_SOC_MK64F12) || \ +#if defined(CONFIG_BOARD_COLIBRI_IMX7D_MCIMX7D_M4) || defined(CONFIG_SOC_MK64F12) || \ defined(CONFIG_SOC_MKW41Z4) || defined(CONFIG_SOC_SERIES_ESP32S2) || \ defined(CONFIG_SOC_SERIES_ESP32S3) || defined(CONFIG_SOC_SERIES_ESP32C3) #define DEFAULT_PERIOD_CYCLE 1024 @@ -81,7 +81,7 @@ #define DEFAULT_PWM_PORT 2 /* TCC1/WO[2] on PA18 (D7) */ #elif defined CONFIG_BOARD_MIMXRT685_EVK #define DEFAULT_PWM_PORT 7 /* D3 on Arduino connector J27 */ -#elif defined CONFIG_BOARD_LPCXPRESSO55S69_CPU0 +#elif defined CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 #define DEFAULT_PWM_PORT 2 /* D2 on Arduino connector P18 */ #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_pwm) /* Default port should be adapted per board to fit the channel diff --git a/tests/drivers/regulator/fixed/testcase.yaml b/tests/drivers/regulator/fixed/testcase.yaml index 35a80a37669ba0..28f61b36ff4041 100644 --- a/tests/drivers/regulator/fixed/testcase.yaml +++ b/tests/drivers/regulator/fixed/testcase.yaml @@ -8,10 +8,10 @@ tests: fixture: gpio_loopback depends_on: gpio platform_allow: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 integration_platforms: - - nrf52840dk_nrf52840 - - nrf5340dk_nrf5340_cpuapp - - nrf9160dk_nrf9160 + - nrf52840dk/nrf52840 + - nrf5340dk/nrf5340/cpuapp + - nrf9160dk/nrf9160 diff --git a/tests/drivers/regulator/voltage/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/regulator/voltage/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/regulator/voltage/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/regulator/voltage/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/regulator/voltage/testcase.yaml b/tests/drivers/regulator/voltage/testcase.yaml index 04b83333079d6b..19dac31742124a 100644 --- a/tests/drivers/regulator/voltage/testcase.yaml +++ b/tests/drivers/regulator/voltage/testcase.yaml @@ -9,7 +9,7 @@ common: tests: drivers.regulator.voltage.nrf52840dk_nrf52840_npm6001: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_npm6001.overlay - SHIELD=npm6001_ek @@ -17,7 +17,7 @@ tests: fixture: npm6001_ek_to_adc drivers.regulator.voltage.nxp: platform_allow: - - mimxrt685_evk_cm33 + - mimxrt685_evk - lpcxpresso55s36 harness_config: fixture: gpio_loopback diff --git a/tests/drivers/retained_mem/api/testcase.yaml b/tests/drivers/retained_mem/api/testcase.yaml index 3ec6a2cf5d48b9..d55716083330d7 100644 --- a/tests/drivers/retained_mem/api/testcase.yaml +++ b/tests/drivers/retained_mem/api/testcase.yaml @@ -1,6 +1,6 @@ tests: drivers.retained_mem.api.gpregret: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - drivers - retained_mem @@ -10,7 +10,7 @@ tests: - drivers - retained_mem drivers.retained_mem.api.ram.nrf52840dk_nrf52840: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_ram.overlay" - OVERLAY_CONFIG="boards/nrf52840dk_nrf52840_ram.conf" diff --git a/tests/drivers/sensor/generic/testcase.yaml b/tests/drivers/sensor/generic/testcase.yaml index a742d6129edf0f..80735430c800c7 100644 --- a/tests/drivers/sensor/generic/testcase.yaml +++ b/tests/drivers/sensor/generic/testcase.yaml @@ -1,7 +1,7 @@ common: integration_platforms: - qemu_x86 - - mps2_an385 + - mps2/an385 tests: drivers.sensor.generic: tags: diff --git a/tests/drivers/sensor/sbs_gauge/boards/qemu_arc_hs.overlay b/tests/drivers/sensor/sbs_gauge/boards/qemu_arc_qemu_arc_hs.overlay similarity index 100% rename from tests/drivers/sensor/sbs_gauge/boards/qemu_arc_hs.overlay rename to tests/drivers/sensor/sbs_gauge/boards/qemu_arc_qemu_arc_hs.overlay diff --git a/tests/drivers/sensor/sbs_gauge/testcase.yaml b/tests/drivers/sensor/sbs_gauge/testcase.yaml index e585ed6f8071f2..eb5170ed1551d5 100644 --- a/tests/drivers/sensor/sbs_gauge/testcase.yaml +++ b/tests/drivers/sensor/sbs_gauge/testcase.yaml @@ -17,7 +17,7 @@ tests: platform_allow: - native_sim - qemu_cortex_a9 - - qemu_arc_hs + - qemu_arc/qemu_arc_hs integration_platforms: - native_sim extra_configs: diff --git a/tests/drivers/spi/spi_loopback/boards/96b_carbon.conf b/tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/96b_carbon.conf rename to tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.conf diff --git a/tests/drivers/spi/spi_loopback/boards/96b_carbon.overlay b/tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/96b_carbon.overlay rename to tests/drivers/spi/spi_loopback/boards/96b_carbon_stm32f401xe.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.conf b/tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.conf rename to tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.conf diff --git a/tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.overlay b/tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/arty_a7_arm_designstart_m1.overlay rename to tests/drivers/spi/spi_loopback/boards/arty_a7_designstart_fpga_cortex_m1.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/longan_nano_lite.overlay b/tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/longan_nano_lite.overlay rename to tests/drivers/spi/spi_loopback/boards/longan_nano_gd32vf103_lite.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_m4.overlay b/tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_lpc54114_m4.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_m4.overlay rename to tests/drivers/spi/spi_loopback/boards/lpcxpresso54114_lpc54114_m4.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm4.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm4.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.conf rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm7.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt1170_evkb_cm7.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.conf rename to tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.conf diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/spi/spi_loopback/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51422.overlay b/tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51822.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51422.overlay rename to tests/drivers/spi/spi_loopback/boards/nrf51dk_nrf51822.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/tdk_robokit1.conf b/tests/drivers/spi/spi_loopback/boards/robokit1.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/tdk_robokit1.conf rename to tests/drivers/spi/spi_loopback/boards/robokit1.conf diff --git a/tests/drivers/spi/spi_loopback/boards/tdk_robokit1.overlay b/tests/drivers/spi/spi_loopback/boards/robokit1.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/tdk_robokit1.overlay rename to tests/drivers/spi/spi_loopback/boards/robokit1.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/rv32m1_vega_ri5cy.overlay b/tests/drivers/spi/spi_loopback/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/rv32m1_vega_ri5cy.overlay rename to tests/drivers/spi/spi_loopback/boards/rv32m1_vega_openisa_rv32m1_ri5cy.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu0_r52.overlay b/tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu0_r52.overlay rename to tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu1_r52.overlay b/tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/s32z270dc2_rtu1_r52.overlay rename to tests/drivers/spi/spi_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained.overlay b/tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/sam_e70_xplained.overlay rename to tests/drivers/spi/spi_loopback/boards/sam_e70_xplained_same70q21.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/sam_v71_xult.overlay b/tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/sam_v71_xult.overlay rename to tests/drivers/spi/spi_loopback/boards/sam_v71_xult_samv71q21.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.conf b/tests/drivers/spi/spi_loopback/boards/samd21_xpro.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.conf rename to tests/drivers/spi/spi_loopback/boards/samd21_xpro.conf diff --git a/tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.overlay b/tests/drivers/spi/spi_loopback/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamd21_xpro.overlay rename to tests/drivers/spi/spi_loopback/boards/samd21_xpro.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/atsame54_xpro.overlay b/tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsame54_xpro.overlay rename to tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay diff --git a/tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.conf b/tests/drivers/spi/spi_loopback/boards/samr21_xpro.conf similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.conf rename to tests/drivers/spi/spi_loopback/boards/samr21_xpro.conf diff --git a/tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.overlay b/tests/drivers/spi/spi_loopback/boards/samr21_xpro.overlay similarity index 100% rename from tests/drivers/spi/spi_loopback/boards/atsamr21_xpro.overlay rename to tests/drivers/spi/spi_loopback/boards/samr21_xpro.overlay diff --git a/tests/drivers/spi/spi_loopback/testcase.yaml b/tests/drivers/spi/spi_loopback/testcase.yaml index fef5e5b361d532..bb2e69961f64de 100644 --- a/tests/drivers/spi/spi_loopback/testcase.yaml +++ b/tests/drivers/spi/spi_loopback/testcase.yaml @@ -31,9 +31,9 @@ tests: extra_configs: - CONFIG_SPI_RTIO=y platform_allow: - - tdk_robokit1 - - mimxrt1170_evk_cm7 - - vmu_rt1170 + - robokit1 + - mimxrt1170_evk/mimxrt1176/cm7 + - vmu_rt1170/mimxrt1176/cm7 drivers.spi.mcux_dspi_dma.loopback: extra_args: - OVERLAY_CONFIG="overlay-mcux-dspi-dma.conf" @@ -44,11 +44,11 @@ tests: - OVERLAY_CONFIG="overlay-sam-spi-dma.conf" - DTC_OVERLAY_FILE="overlay-sam-spi-dma.overlay" platform_allow: - - sam_e70_xplained - - sam_v71_xult - - tdk_robokit1 + - sam_e70_xplained/same70q21 + - sam_v71_xult/samv71q21 + - robokit1 integration_platforms: - - sam_e70_xplained + - sam_e70_xplained/same70q21 drivers.spi.stm32_spi_16bits_frames.loopback: extra_args: - OVERLAY_CONFIG="overlay-stm32-spi-16bits.conf" @@ -113,7 +113,7 @@ tests: - gd32vf103c_starter - gd32vf103v_eval - longan_nano - - longan_nano_lite + - longan_nano/gd32vf103/lite drivers.spi.gd32_spi_dma.loopback: extra_args: OVERLAY_CONFIG="overlay-gd32-spi-dma.conf" platform_allow: @@ -126,7 +126,7 @@ tests: - gd32vf103c_starter - gd32vf103v_eval - longan_nano - - longan_nano_lite + - longan_nano/gd32vf103/lite drivers.spi.pl022_spi_interrupt.loopback: extra_configs: - CONFIG_SPI_PL022_INTERRUPT=y diff --git a/tests/drivers/timer/nrf_rtc_timer/testcase.yaml b/tests/drivers/timer/nrf_rtc_timer/testcase.yaml index 9c3f9a944133b6..d946e37062d001 100644 --- a/tests/drivers/timer/nrf_rtc_timer/testcase.yaml +++ b/tests/drivers/timer/nrf_rtc_timer/testcase.yaml @@ -4,10 +4,10 @@ tests: - drivers - timer platform_allow: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 extra_configs: - CONFIG_ZERO_LATENCY_IRQS=y @@ -16,10 +16,10 @@ tests: - drivers - timer platform_allow: - - nrf52dk_nrf52832 - - nrf52840dk_nrf52840 + - nrf52dk/nrf52832 + - nrf52840dk/nrf52840 - nrf52_bsim - nrf5340bsim_nrf5340_cpuapp - nrf5340bsim_nrf5340_cpunet integration_platforms: - - nrf52dk_nrf52832 + - nrf52dk/nrf52832 diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay new file mode 100644 index 00000000000000..4f031193d15229 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +dut: &lpuart2 { + status = "okay"; + current-speed = <115200>; + nxp,loopback; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm7.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_cm7.overlay rename to tests/drivers/uart/uart_async_api/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay new file mode 100644 index 00000000000000..4f031193d15229 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +dut: &lpuart2 { + status = "okay"; + current-speed = <115200>; + nxp,loopback; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay new file mode 100644 index 00000000000000..37f2577dc2a0e2 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: Apache-2.0 */ + +/ { + chosen { + zephyr,sram = &dtcm; + }; +}; + +dut: &lpuart2 { + status = "okay"; + current-speed = <115200>; + nxp,loopback; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_cm33.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_cm33.overlay rename to tests/drivers/uart/uart_async_api/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt685_evk_cm33.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/mimxrt685_evk_cm33.overlay rename to tests/drivers/uart/uart_async_api/boards/mimxrt685_evk.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_ns.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_ns.overlay rename to tests/drivers/uart/uart_async_api/boards/nucleo_l552ze_q_stm32l552xx_ns.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamc21n_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samc21n_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamc21n_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samc21n_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamd21_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samd21_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamd21_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samd21_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsame54_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/same54_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsame54_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/same54_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsaml21_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/saml21_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsaml21_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/saml21_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamr21_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samr21_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamr21_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samr21_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/atsamr34_xpro.overlay b/tests/drivers/uart/uart_async_api/boards/samr34_xpro.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/atsamr34_xpro.overlay rename to tests/drivers/uart/uart_async_api/boards/samr34_xpro.overlay diff --git a/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_ns.overlay b/tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay similarity index 100% rename from tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_ns.overlay rename to tests/drivers/uart/uart_async_api/boards/stm32l562e_dk_stm32l562xx_ns.overlay diff --git a/tests/drivers/uart/uart_async_api/testcase.yaml b/tests/drivers/uart/uart_async_api/testcase.yaml index 8d53d9354120b4..84bbd9c439beda 100644 --- a/tests/drivers/uart/uart_async_api/testcase.yaml +++ b/tests/drivers/uart/uart_async_api/testcase.yaml @@ -26,7 +26,7 @@ tests: integration_platforms: - nucleo_h743zi drivers.uart.async_api.nrf_uarte_new: - platform_allow: nrf52840dk_nrf52840 nrf52_bsim + platform_allow: nrf52840dk/nrf52840 nrf52_bsim filter: CONFIG_SERIAL_SUPPORT_ASYNC harness: ztest harness_config: @@ -38,13 +38,13 @@ tests: drivers.uart.async_api.nrf_uart: filter: CONFIG_SERIAL_SUPPORT_ASYNC harness: ztest - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 harness_config: fixture: gpio_loopback depends_on: gpio extra_args: DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;boards/nrf_uart.overlay" integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 drivers.uart.async_api.rtt: filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_HAS_SEGGER_RTT and not CONFIG_UART_MCUX_LPUART and not CONFIG_UART_MCUX_FLEXCOMM @@ -63,14 +63,14 @@ tests: harness: ztest depends_on: dma drivers.uart.async_api.sam0: - filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_SOC_FAMILY_SAM0 + filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_SOC_FAMILY_ATMEL_SAM0 platform_allow: - - atsamc21n_xpro - - atsamd21_xpro - - atsaml21_xpro - - atsamr21_xpro - - atsamr34_xpro - - atsame54_xpro + - samc21n_xpro + - samd21_xpro + - saml21_xpro + - samr21_xpro + - samr34_xpro + - same54_xpro extra_configs: - CONFIG_UART_SAM0_ASYNC=y - CONFIG_DMA=y diff --git a/tests/drivers/uart/uart_basic_api/testcase.yaml b/tests/drivers/uart/uart_basic_api/testcase.yaml index ee4fd9346602d6..6d227a2e613816 100644 --- a/tests/drivers/uart/uart_basic_api/testcase.yaml +++ b/tests/drivers/uart/uart_basic_api/testcase.yaml @@ -6,7 +6,7 @@ tests: filter: CONFIG_UART_CONSOLE harness: keyboard integration_platforms: - - mps2_an385 + - mps2/an385 drivers.uart.basic_api.wide: extra_configs: - CONFIG_UART_WIDE_DATA=y @@ -26,7 +26,7 @@ tests: filter: CONFIG_UART_CONSOLE harness: keyboard integration_platforms: - - mps2_an385 + - mps2/an385 drivers.uart.basic_api.shell: extra_args: CONF_FILE=prj_shell.conf min_flash: 64 @@ -36,7 +36,7 @@ tests: filter: CONFIG_UART_CONSOLE harness: keyboard integration_platforms: - - mps2_an385 + - mps2/an385 drivers.uart.basic_api.cdc_acm: extra_args: - OVERLAY_CONFIG="overlay-usb.conf" diff --git a/tests/drivers/uart/uart_mix_fifo_poll/src/main.c b/tests/drivers/uart/uart_mix_fifo_poll/src/main.c index aaf97ea8488d7b..2f38354d21ece4 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/src/main.c +++ b/tests/drivers/uart/uart_mix_fifo_poll/src/main.c @@ -19,11 +19,11 @@ #if DT_NODE_EXISTS(DT_NODELABEL(dut)) #define UART_NODE DT_NODELABEL(dut) -#elif defined(CONFIG_BOARD_ATSAMD21_XPRO) +#elif defined(CONFIG_BOARD_SAMD21_XPRO) #define UART_NODE DT_NODELABEL(sercom1) -#elif defined(CONFIG_BOARD_ATSAMR21_XPRO) +#elif defined(CONFIG_BOARD_SAMR21_XPRO) #define UART_NODE DT_NODELABEL(sercom3) -#elif defined(CONFIG_BOARD_ATSAME54_XPRO) +#elif defined(CONFIG_BOARD_SAME54_XPRO) #define UART_NODE DT_NODELABEL(sercom1) #else #define UART_NODE DT_CHOSEN(zephyr_console) diff --git a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml index ccfdd1aa717848..4cb6c5d1308efb 100644 --- a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml +++ b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml @@ -5,12 +5,12 @@ common: depends_on: gpio harness: ztest platform_allow: - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf5340dk_nrf5340_cpuapp + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf5340dk/nrf5340/cpuapp - nrf52_bsim integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 harness_config: fixture: gpio_loopback tests: diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml index 5417be597e0b9b..f90eed739499c7 100644 --- a/tests/drivers/uart/uart_pm/testcase.yaml +++ b/tests/drivers/uart/uart_pm/testcase.yaml @@ -4,7 +4,7 @@ common: - uart harness: ztest platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - nrf52_bsim harness_config: fixture: gpio_loopback diff --git a/tests/drivers/udc/testcase.yaml b/tests/drivers/udc/testcase.yaml index e15fdd6761cb58..e43a7a11c169ac 100644 --- a/tests/drivers/udc/testcase.yaml +++ b/tests/drivers/udc/testcase.yaml @@ -4,5 +4,5 @@ tests: - usb - drivers platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim_64 diff --git a/tests/drivers/w1/w1_api/testcase.yaml b/tests/drivers/w1/w1_api/testcase.yaml index 19c283863f2bec..f35b156ed5cecd 100644 --- a/tests/drivers/w1/w1_api/testcase.yaml +++ b/tests/drivers/w1/w1_api/testcase.yaml @@ -6,9 +6,9 @@ common: harness: ztest platform_allow: - nucleo_g0b1re - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tests: drivers.w1.w1-serial: diff --git a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml index a2f8ea97f1f13e..8736f0c20eb81b 100644 --- a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml +++ b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml @@ -8,14 +8,14 @@ tests: filter: > not (CONFIG_WDT_SAM or dt_compat_enabled("st,stm32-window-watchdog") or dt_compat_enabled("st,stm32-watchdog") or CONFIG_SOC_FAMILY_LPC or - CONFIG_SOC_SERIES_IMX_RT6XX or CONFIG_SOC_SERIES_IMX_RT5XX or - CONFIG_SOC_FAMILY_GD32 or SOC_SERIES_GD32VF103) + CONFIG_SOC_SERIES_IMXRT6XX or CONFIG_SOC_SERIES_IMXRT5XX or + CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103) platform_exclude: - mec15xxevb_assy6853 - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 drivers.watchdog.stm32wwdg: filter: dt_compat_enabled("st,stm32-window-watchdog") or dt_compat_enabled("st,stm32-watchdog") extra_args: DTC_OVERLAY_FILE="boards/stm32_wwdg.overlay" @@ -78,7 +78,7 @@ tests: build_only: true platform_allow: mec15xxevb_assy6853 drivers.watchdog.counter_watchdog: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: - OVERLAY_CONFIG="boards/nrf52840dk_nrf52840_counter.conf" - DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_counter.overlay" @@ -117,10 +117,10 @@ tests: drivers.watchdog.nxp_s32: build_only: true platform_allow: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 - mr_canhubk3 drivers.watchdog.mimxrt1050_evk_ti_tps382x: filter: dt_compat_enabled("ti,tps382x") diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml index 0290edbafc19f8..ea75ad5c6e1436 100644 --- a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml +++ b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml @@ -4,10 +4,10 @@ tests: drivers.watchdog.reset_none: platform_allow: - - s32z270dc2_rtu0_r52 - - s32z270dc2_rtu1_r52 - - s32z270dc2_rtu0_r52@D - - s32z270dc2_rtu1_r52@D + - s32z2xxdc2/s32z270/rtu0 + - s32z2xxdc2/s32z270/rtu1 + - s32z2xxdc2@D/s32z270/rtu0 + - s32z2xxdc2@D/s32z270/rtu1 tags: - drivers - watchdog diff --git a/tests/kernel/cache/testcase.yaml b/tests/kernel/cache/testcase.yaml index 37e277c4be2503..2c089e26eaff79 100644 --- a/tests/kernel/cache/testcase.yaml +++ b/tests/kernel/cache/testcase.yaml @@ -5,13 +5,13 @@ tests: - cache filter: CONFIG_CACHE_MANAGEMENT platform_exclude: - - adp_xc7k_ae350 - - bcm958402m2_m7 + - adp_xc7k/ae350 + - bcm958402m2/bcm58402/m7 - bcm958401m2 integration_platforms: - qemu_xtensa - qemu_cortex_a53 - - nsim_em + - nsim/nsim_em - qemu_x86 - qemu_x86_64 kernel.cache.api.minimallibc: @@ -21,13 +21,13 @@ tests: - libc filter: CONFIG_CACHE_MANAGEMENT and CONFIG_MINIMAL_LIBC_SUPPORTED platform_exclude: - - adp_xc7k_ae350 - - bcm958402m2_m7 + - adp_xc7k/ae350 + - bcm958402m2/bcm58402/m7 - bcm958401m2 integration_platforms: - qemu_xtensa - qemu_cortex_a53 - - nsim_em + - nsim/nsim_em - qemu_x86 - qemu_x86_64 extra_configs: diff --git a/tests/kernel/fatal/exception/testcase.yaml b/tests/kernel/fatal/exception/testcase.yaml index 4304040e6eeb5e..6a471ab59a387a 100644 --- a/tests/kernel/fatal/exception/testcase.yaml +++ b/tests/kernel/fatal/exception/testcase.yaml @@ -31,7 +31,7 @@ tests: - kernel - userspace integration_platforms: - - mps2_an385 + - mps2/an385 kernel.common.stack_protection_armv8m_mpu_stack_guard: extra_args: CONF_FILE=prj_armv8m_mpu_stack_guard.conf filter: CONFIG_ARM_MPU and CONFIG_ARMV8_M_MAINLINE @@ -40,7 +40,7 @@ tests: - kernel - userspace integration_platforms: - - mps2_an385 + - mps2/an385 kernel.common.stack_sentinel: extra_args: CONF_FILE=sentinel.conf platform_exclude: diff --git a/tests/kernel/fatal/no-multithreading/testcase.yaml b/tests/kernel/fatal/no-multithreading/testcase.yaml index 973b78aef880d8..ef0b24a79f5fb1 100644 --- a/tests/kernel/fatal/no-multithreading/testcase.yaml +++ b/tests/kernel/fatal/no-multithreading/testcase.yaml @@ -1,21 +1,21 @@ common: platform_allow: - qemu_cortex_m3 - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x integration_platforms: - qemu_cortex_m3 - - nsim_em + - nsim/nsim_em tags: - kernel - scheduler diff --git a/tests/kernel/gen_isr_table/boards/lpcxpresso54114_m4.conf b/tests/kernel/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf similarity index 100% rename from tests/kernel/gen_isr_table/boards/lpcxpresso54114_m4.conf rename to tests/kernel/gen_isr_table/boards/lpcxpresso54114_lpc54114_m4.conf diff --git a/tests/kernel/gen_isr_table/testcase.yaml b/tests/kernel/gen_isr_table/testcase.yaml index a255e0e4caf93c..1b06037c780719 100644 --- a/tests/kernel/gen_isr_table/testcase.yaml +++ b/tests/kernel/gen_isr_table/testcase.yaml @@ -23,8 +23,8 @@ tests: - stmf103_mini - nucleo_f103rb - olimexino_stm32 - - stm32_min_dev_black - - stm32_min_dev_blue + - stm32_min_dev@black + - stm32_min_dev@blue - usb_kw24d512 - v2m_beetle - cc1352r1_launchxl @@ -71,7 +71,7 @@ tests: arch_allow: riscv platform_exclude: - m2gl025_miv - - adp_xc7k_ae350 + - adp_xc7k/ae350 filter: CONFIG_RISCV_PRIVILEGED extra_configs: - CONFIG_GEN_IRQ_VECTOR_TABLE=y diff --git a/tests/kernel/mbox/mbox_api/boards/qemu_x86_tiny_768.conf b/tests/kernel/mbox/mbox_api/boards/qemu_x86_tiny_768.conf deleted file mode 100644 index c10fad4375b552..00000000000000 --- a/tests/kernel/mbox/mbox_api/boards/qemu_x86_tiny_768.conf +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# Need quite some space for coverage. -CONFIG_TEST_EXTRA_STACK_SIZE=1024 diff --git a/tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_smp.conf b/tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf similarity index 100% rename from tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_smp.conf rename to tests/kernel/mem_protect/mem_map/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf diff --git a/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny_768.overlay b/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny_768.overlay deleted file mode 100644 index dffdf462738ad3..00000000000000 --- a/tests/kernel/mem_protect/mem_map/boards/qemu_x86_tiny_768.overlay +++ /dev/null @@ -1,3 +0,0 @@ -&dram0 { - reg = < 0x100000 0x100000 >; -}; diff --git a/tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_smp.conf b/tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf similarity index 100% rename from tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_smp.conf rename to tests/kernel/mem_protect/mem_protect/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf diff --git a/tests/kernel/mem_protect/mem_protect/testcase.yaml b/tests/kernel/mem_protect/mem_protect/testcase.yaml index 39551533e95214..efc1553dec59a6 100644 --- a/tests/kernel/mem_protect/mem_protect/testcase.yaml +++ b/tests/kernel/mem_protect/mem_protect/testcase.yaml @@ -23,9 +23,9 @@ tests: filter: CONFIG_ARCH_HAS_USERSPACE and CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS arch_allow: arm platform_allow: - - efr32_radio_brd4180a - - mps3_an547 - - nrf9160dk_nrf9160 + - efr32_radio/efr32mg21a020f1024im32 + - mps3/an547 + - nrf9160dk/nrf9160 integration_platforms: - - mps3_an547 + - mps3/an547 extra_args: CONFIG_MPU_GAP_FILLING=y diff --git a/tests/kernel/mem_protect/stackprot/boards/qemu_x86_tiny_768.conf b/tests/kernel/mem_protect/stackprot/boards/qemu_x86_tiny_768.conf deleted file mode 100644 index b266485dc1b6e1..00000000000000 --- a/tests/kernel/mem_protect/stackprot/boards/qemu_x86_tiny_768.conf +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright 2022 Intel Corporation -# SPDX-License-Identifier: Apache-2.0 - -# This is needed for coverage. -CONFIG_MAIN_STACK_SIZE=4096 diff --git a/tests/kernel/mem_protect/syscalls/testcase.yaml b/tests/kernel/mem_protect/syscalls/testcase.yaml index 0f2587f38592c7..1f5210ebc89731 100644 --- a/tests/kernel/mem_protect/syscalls/testcase.yaml +++ b/tests/kernel/mem_protect/syscalls/testcase.yaml @@ -1,6 +1,6 @@ tests: kernel.memory_protection.syscalls: - platform_exclude: qemu_arc_em + platform_exclude: qemu_arc/qemu_arc_em filter: CONFIG_ARCH_HAS_USERSPACE arch_exclude: - posix diff --git a/tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_cm33.overlay b/tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_mimxrt595s_cm33.overlay similarity index 100% rename from tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_cm33.overlay rename to tests/kernel/mem_protect/userspace/boards/mimxrt595_evk_mimxrt595s_cm33.overlay diff --git a/tests/kernel/mem_protect/userspace/boards/mimxrt685_evk_cm33.overlay b/tests/kernel/mem_protect/userspace/boards/mimxrt685_evk.overlay similarity index 100% rename from tests/kernel/mem_protect/userspace/boards/mimxrt685_evk_cm33.overlay rename to tests/kernel/mem_protect/userspace/boards/mimxrt685_evk.overlay diff --git a/tests/kernel/mem_protect/userspace/testcase.yaml b/tests/kernel/mem_protect/userspace/testcase.yaml index 858b341875a283..5306d5a7638f9d 100644 --- a/tests/kernel/mem_protect/userspace/testcase.yaml +++ b/tests/kernel/mem_protect/userspace/testcase.yaml @@ -22,9 +22,9 @@ tests: filter: CONFIG_ARCH_HAS_USERSPACE and CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS arch_allow: arm platform_allow: - - efr32_radio_brd4180a - - mps3_an547 - - nrf9160dk_nrf9160 + - efr32_radio/efr32mg21a020f1024im32 + - mps3/an547 + - nrf9160dk/nrf9160 integration_platforms: - - mps3_an547 + - mps3/an547 extra_args: CONFIG_MPU_GAP_FILLING=y diff --git a/tests/kernel/mem_slab/mslab_api/testcase.yaml b/tests/kernel/mem_slab/mslab_api/testcase.yaml index 3f067a1529f0e0..40021091d01264 100644 --- a/tests/kernel/mem_slab/mslab_api/testcase.yaml +++ b/tests/kernel/mem_slab/mslab_api/testcase.yaml @@ -10,21 +10,21 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_cortex_m0 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 - qemu_leon3 integration_platforms: - qemu_cortex_m3 - - qemu_arc_hs + - qemu_arc/qemu_arc_hs extra_configs: - CONFIG_MULTITHREADING=n diff --git a/tests/kernel/obj_core/obj_core/testcase.yaml b/tests/kernel/obj_core/obj_core/testcase.yaml index e6bcafafc56b05..6751c0bcb10a47 100644 --- a/tests/kernel/obj_core/obj_core/testcase.yaml +++ b/tests/kernel/obj_core/obj_core/testcase.yaml @@ -6,4 +6,4 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny@768 + - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/obj_core/obj_core_stats/testcase.yaml b/tests/kernel/obj_core/obj_core_stats/testcase.yaml index 28bbaf1ec71717..1027cac8fec4dd 100644 --- a/tests/kernel/obj_core/obj_core_stats/testcase.yaml +++ b/tests/kernel/obj_core/obj_core_stats/testcase.yaml @@ -6,4 +6,4 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny@768 + - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml b/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml index c17ff99e213803..2c4ecb5bc21f48 100644 --- a/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml +++ b/tests/kernel/obj_core/obj_core_stats_api/testcase.yaml @@ -6,4 +6,4 @@ tests: - qemu_x86 platform_exclude: - qemu_x86_tiny - - qemu_x86_tiny@768 + - qemu_x86_tiny/ia32/768 diff --git a/tests/kernel/poll/testcase.yaml b/tests/kernel/poll/testcase.yaml index 5eb5fc9a6262c3..fdf503e361515d 100644 --- a/tests/kernel/poll/testcase.yaml +++ b/tests/kernel/poll/testcase.yaml @@ -4,10 +4,10 @@ tests: tags: - kernel - userspace - # FIXME: qemu_arc_hs6x is excluded due to a run-time failure, see #49492 + # FIXME: qemu_arc/qemu_arc_hs6x is excluded due to a run-time failure, see #49492 platform_exclude: - - nrf52dk_nrf52810 - - qemu_arc_hs6x + - nrf52dk/nrf52810 + - qemu_arc/qemu_arc_hs6x kernel.poll.minimallibc: filter: CONFIG_MINIMAL_LIBC_SUPPORTED ignore_faults: true @@ -15,9 +15,9 @@ tests: - kernel - userspace - libc - # FIXME: qemu_arc_hs6x is excluded due to a run-time failure, see #49492 + # FIXME: qemu_arc/qemu_arc_hs6x is excluded due to a run-time failure, see #49492 platform_exclude: - - nrf52dk_nrf52810 - - qemu_arc_hs6x + - nrf52dk/nrf52810 + - qemu_arc/qemu_arc_hs6x extra_configs: - CONFIG_MINIMAL_LIBC=y diff --git a/tests/kernel/profiling/profiling_api/testcase.yaml b/tests/kernel/profiling/profiling_api/testcase.yaml index aeec61bad8a32d..d4dad4abd08d1e 100644 --- a/tests/kernel/profiling/profiling_api/testcase.yaml +++ b/tests/kernel/profiling/profiling_api/testcase.yaml @@ -2,11 +2,13 @@ tests: kernel.common.profiling: arch_exclude: nios2 platform_exclude: - - em_starterkit + - em_starterkit/emsk_em7d + - em_starterkit/emsk_em9d + - em_starterkit/emsk_em11d - litex_vexriscv - - rv32m1_vega_zero_riscy - - rv32m1_vega_ri5cy - - nrf5340dk_nrf5340_cpunet + - rv32m1_vega/openisa_rv32m1/zero_riscy + - rv32m1_vega/openisa_rv32m1/ri5cy + - nrf5340dk/nrf5340/cpunet tags: - kernel - pm diff --git a/tests/kernel/sched/metairq/testcase.yaml b/tests/kernel/sched/metairq/testcase.yaml index 041d7d0b696a12..53b0a8a0b530ea 100644 --- a/tests/kernel/sched/metairq/testcase.yaml +++ b/tests/kernel/sched/metairq/testcase.yaml @@ -1,4 +1,4 @@ tests: kernel.scheduler.metairq: tags: kernel - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 diff --git a/tests/kernel/sched/preempt/testcase.yaml b/tests/kernel/sched/preempt/testcase.yaml index 5aa32450d8efe9..affc1ce1944bb2 100644 --- a/tests/kernel/sched/preempt/testcase.yaml +++ b/tests/kernel/sched/preempt/testcase.yaml @@ -1,4 +1,4 @@ tests: kernel.scheduler.preempt: tags: kernel - platform_exclude: nrf52dk_nrf52810 + platform_exclude: nrf52dk/nrf52810 diff --git a/tests/kernel/smp/boards/qemu_cortex_a53_smp.conf b/tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf similarity index 100% rename from tests/kernel/smp/boards/qemu_cortex_a53_smp.conf rename to tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf diff --git a/tests/kernel/smp/boards/qemu_cortex_a53_smp.overlay b/tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay similarity index 100% rename from tests/kernel/smp/boards/qemu_cortex_a53_smp.overlay rename to tests/kernel/smp/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay diff --git a/tests/kernel/smp_boot_delay/testcase.yaml b/tests/kernel/smp_boot_delay/testcase.yaml index 3aef08bc67e099..ea84c6d2cf03d1 100644 --- a/tests/kernel/smp_boot_delay/testcase.yaml +++ b/tests/kernel/smp_boot_delay/testcase.yaml @@ -3,7 +3,7 @@ tests: tags: - kernel - smp - platform_allow: intel_adsp_cavs25 qemu_x86_64 + platform_allow: intel_adsp/cavs25 qemu_x86_64 integration_platforms: - qemu_x86_64 kernel.multiprocessing.smp_boot_delay.minimallibc: @@ -12,7 +12,7 @@ tests: - kernel - smp - libc - platform_allow: intel_adsp_cavs25 qemu_x86_64 + platform_allow: intel_adsp/cavs25 qemu_x86_64 integration_platforms: - qemu_x86_64 extra_configs: diff --git a/tests/kernel/threads/dynamic_thread_stack/testcase.yaml b/tests/kernel/threads/dynamic_thread_stack/testcase.yaml index 69f5651406f967..27bfe6602fbb01 100644 --- a/tests/kernel/threads/dynamic_thread_stack/testcase.yaml +++ b/tests/kernel/threads/dynamic_thread_stack/testcase.yaml @@ -3,15 +3,15 @@ common: min_ram: 32 integration_platforms: - qemu_x86 - - qemu_x86_nommu + - qemu_x86/atom/nommu - qemu_x86_64 - qemu_cortex_a53 - - qemu_cortex_a53_smp + - qemu_cortex_a53/qemu_cortex_a53/smp - qemu_cortex_m3 - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp # Permutations of (pool | alloc | user) tests: diff --git a/tests/kernel/threads/no-multithreading/testcase.yaml b/tests/kernel/threads/no-multithreading/testcase.yaml index d29165f683c7bc..ae0556c54c6336 100644 --- a/tests/kernel/threads/no-multithreading/testcase.yaml +++ b/tests/kernel/threads/no-multithreading/testcase.yaml @@ -5,20 +5,20 @@ tests: platform_allow: - qemu_cortex_m0 - qemu_cortex_m3 - - mps2_an385 - - mps2_an521 - - nrf52840dk_nrf52840 - - nrf9160dk_nrf9160 - - nrf51dk_nrf51422 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - mps2/an385 + - mps2/an521/cpu0 + - nrf52840dk/nrf52840 + - nrf9160dk/nrf9160 + - nrf51dk/nrf51822 + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 diff --git a/tests/kernel/threads/thread_stack/testcase.yaml b/tests/kernel/threads/thread_stack/testcase.yaml index 5303a8ee6989d6..ed47161b97d76c 100644 --- a/tests/kernel/threads/thread_stack/testcase.yaml +++ b/tests/kernel/threads/thread_stack/testcase.yaml @@ -7,7 +7,7 @@ tests: ignore_faults: true min_ram: 16 integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 - qemu_x86 kernel.threads.armv8m_mpu_stack_guard: min_ram: 16 @@ -20,4 +20,4 @@ tests: - userspace ignore_faults: true integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 diff --git a/tests/kernel/tickless/tickless_concept/testcase.yaml b/tests/kernel/tickless/tickless_concept/testcase.yaml index f4c1f95da98171..186f76d539d5a0 100644 --- a/tests/kernel/tickless/tickless_concept/testcase.yaml +++ b/tests/kernel/tickless/tickless_concept/testcase.yaml @@ -5,9 +5,9 @@ tests: # consistently when coverage is enabled. Disable until 14173 is fixed. platform_exclude: - litex_vexriscv - - rv32m1_vega_zero_riscy - - rv32m1_vega_ri5cy - - nrf5340dk_nrf5340_cpunet + - rv32m1_vega/openisa_rv32m1/zero_riscy + - rv32m1_vega/openisa_rv32m1/ri5cy + - nrf5340dk/nrf5340/cpunet - nucleo_l073rz tags: - kernel diff --git a/tests/kernel/timer/timer_api/testcase.yaml b/tests/kernel/timer/timer_api/testcase.yaml index 82919939e43cc9..9337459bf5147f 100644 --- a/tests/kernel/timer/timer_api/testcase.yaml +++ b/tests/kernel/timer/timer_api/testcase.yaml @@ -11,9 +11,9 @@ tests: - posix platform_exclude: - litex_vexriscv - - rv32m1_vega_zero_riscy - - rv32m1_vega_ri5cy - - nrf5340dk_nrf5340_cpunet + - rv32m1_vega/openisa_rv32m1/zero_riscy + - rv32m1_vega/openisa_rv32m1/ri5cy + - nrf5340dk/nrf5340/cpunet tags: - kernel - timer @@ -25,19 +25,19 @@ tests: - timer platform_allow: - qemu_cortex_m3 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_leon3 integration_platforms: - qemu_cortex_m3 - - nsim_em + - nsim/nsim_em extra_configs: - CONFIG_MULTITHREADING=n - CONFIG_TEST_USERSPACE=n diff --git a/tests/kernel/timer/timer_monotonic/testcase.yaml b/tests/kernel/timer/timer_monotonic/testcase.yaml index 9c38d456986120..075f3009e8fabf 100644 --- a/tests/kernel/timer/timer_monotonic/testcase.yaml +++ b/tests/kernel/timer/timer_monotonic/testcase.yaml @@ -3,9 +3,9 @@ tests: tags: - kernel - timer - # FIXME: This test may fail for qemu_arc_hs on certain host systems. + # FIXME: This test may fail for qemu_arc/qemu_arc_hs on certain host systems. # See foss-for-synopsys-dwc-arc-processors/qemu#67. - platform_exclude: qemu_arc_hs + platform_exclude: qemu_arc/qemu_arc_hs kernel.timer.monotonic.apic.tsc: tags: - kernel @@ -20,6 +20,6 @@ tests: tags: - kernel - timer - platform_allow: mps2_an385 + platform_allow: mps2/an385 extra_configs: - CONFIG_QEMU_ICOUNT=n diff --git a/tests/kernel/usage/thread_runtime_stats/testcase.yaml b/tests/kernel/usage/thread_runtime_stats/testcase.yaml index 05fabf3ba574fa..671a01b8a190f3 100644 --- a/tests/kernel/usage/thread_runtime_stats/testcase.yaml +++ b/tests/kernel/usage/thread_runtime_stats/testcase.yaml @@ -15,6 +15,6 @@ tests: filter: not CONFIG_SMP integration_platforms: - qemu_x86 - - mps2_an385 + - mps2/an385 platform_exclude: - mr_canhubk3 diff --git a/tests/kernel/workq/critical/testcase.yaml b/tests/kernel/workq/critical/testcase.yaml index 822e6d2af99ef6..7ba31c3661c8dd 100644 --- a/tests/kernel/workq/critical/testcase.yaml +++ b/tests/kernel/workq/critical/testcase.yaml @@ -4,7 +4,7 @@ common: - workqueue tests: kernel.workqueue.critical: - platform_exclude: nsim_sem_mpu_stack_guard + platform_exclude: nsim/nsim_sem/mpu_stack_guard filter: not CONFIG_WDT_SAM integration_platforms: - qemu_x86 @@ -13,8 +13,8 @@ tests: extra_configs: - CONFIG_WDT_DISABLE_AT_BOOT=y integration_platforms: - - sam_e70_xplained + - sam_e70_xplained/same70q21 kernel.workqueue.critical.nsim: - platform_allow: nsim_sem_mpu_stack_guard + platform_allow: nsim/nsim_sem/mpu_stack_guard extra_configs: - CONFIG_TEST_HW_STACK_PROTECTION=n diff --git a/tests/kernel/xip/testcase.yaml b/tests/kernel/xip/testcase.yaml index 0992d21906475f..44360ec5bee1f2 100644 --- a/tests/kernel/xip/testcase.yaml +++ b/tests/kernel/xip/testcase.yaml @@ -5,15 +5,15 @@ tests: - kernel - xip integration_platforms: - - qemu_arc_em - - qemu_x86_xip + - qemu_arc/qemu_arc_em + - qemu_x86/atom/xip arch.common.xip.minimallibc: filter: CONFIG_XIP and CONFIG_MINIMAL_LIBC_SUPPORTED tags: - kernel - xip integration_platforms: - - qemu_arc_em - - qemu_x86_xip + - qemu_arc/qemu_arc_em + - qemu_x86/atom/xip extra_configs: - CONFIG_MINIMAL_LIBC=y diff --git a/tests/lib/c_lib/common/testcase.yaml b/tests/lib/c_lib/common/testcase.yaml index 28a7d54194c52f..4d184b9536f5f7 100644 --- a/tests/lib/c_lib/common/testcase.yaml +++ b/tests/lib/c_lib/common/testcase.yaml @@ -3,7 +3,7 @@ common: - clib ignore_faults: true integration_platforms: - - mps2_an385 + - mps2/an385 tests: libraries.libc.common: {} libraries.libc.common.minimal: diff --git a/tests/lib/cmsis_dsp/bayes/testcase.yaml b/tests/lib/cmsis_dsp/bayes/testcase.yaml index 3e0ae0018b9044..abdc24b73358af 100644 --- a/tests/lib/cmsis_dsp/bayes/testcase.yaml +++ b/tests/lib/cmsis_dsp/bayes/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: - cmsis-dsp @@ -15,8 +15,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/complexmath/testcase.yaml b/tests/lib/cmsis_dsp/complexmath/testcase.yaml index 58eae41629acbd..5dda156a111868 100644 --- a/tests/lib/cmsis_dsp/complexmath/testcase.yaml +++ b/tests/lib/cmsis_dsp/complexmath/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim - native_posix tags: cmsis-dsp @@ -15,8 +15,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/distance/testcase.yaml b/tests/lib/cmsis_dsp/distance/testcase.yaml index 6c2bc20659e17a..b44b53af16e1a6 100644 --- a/tests/lib/cmsis_dsp/distance/testcase.yaml +++ b/tests/lib/cmsis_dsp/distance/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis_dsp min_flash: 64 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/fastmath/testcase.yaml b/tests/lib/cmsis_dsp/fastmath/testcase.yaml index 8524cb01a60e88..27665a80250474 100644 --- a/tests/lib/cmsis_dsp/fastmath/testcase.yaml +++ b/tests/lib/cmsis_dsp/fastmath/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis_dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/filtering/testcase.yaml b/tests/lib/cmsis_dsp/filtering/testcase.yaml index eb6209385602e7..ef45599a827258 100644 --- a/tests/lib/cmsis_dsp/filtering/testcase.yaml +++ b/tests/lib/cmsis_dsp/filtering/testcase.yaml @@ -12,8 +12,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis_dsp min_flash: 128 @@ -25,8 +25,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -41,8 +41,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -54,8 +54,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -70,8 +70,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -83,8 +83,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -99,8 +99,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 256 @@ -112,9 +112,9 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote + - mps2/an521/cpu1 platform_exclude: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/interpolation/testcase.yaml b/tests/lib/cmsis_dsp/interpolation/testcase.yaml index 2631b5ef19fae6..7c5b516371525f 100644 --- a/tests/lib/cmsis_dsp/interpolation/testcase.yaml +++ b/tests/lib/cmsis_dsp/interpolation/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/matrix/testcase.yaml b/tests/lib/cmsis_dsp/matrix/testcase.yaml index 10a2c60ab3bb25..36aea53d84ba7f 100644 --- a/tests/lib/cmsis_dsp/matrix/testcase.yaml +++ b/tests/lib/cmsis_dsp/matrix/testcase.yaml @@ -9,8 +9,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -22,8 +22,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -38,8 +38,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -51,8 +51,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -67,8 +67,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -80,8 +80,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -96,8 +96,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 128 min_ram: 64 @@ -108,8 +108,8 @@ tests: filter: (CONFIG_CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -124,8 +124,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -137,8 +137,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -153,8 +153,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -166,8 +166,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -182,8 +182,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -196,8 +196,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -213,8 +213,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -227,8 +227,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -244,8 +244,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -258,8 +258,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -275,8 +275,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 128 min_ram: 144 @@ -287,8 +287,8 @@ tests: filter: (CONFIG_CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -303,8 +303,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -317,8 +317,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -334,8 +334,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp platform_exclude: frdm_kw41z @@ -348,8 +348,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml b/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml index f8c45b290eb3cc..e6d59cd451aa00 100644 --- a/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml +++ b/tests/lib/cmsis_dsp/quaternionmath/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/statistics/testcase.yaml b/tests/lib/cmsis_dsp/statistics/testcase.yaml index 1c142870ff3be3..a6ec436ee11ac4 100644 --- a/tests/lib/cmsis_dsp/statistics/testcase.yaml +++ b/tests/lib/cmsis_dsp/statistics/testcase.yaml @@ -4,8 +4,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -15,8 +15,8 @@ tests: and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/support/testcase.yaml b/tests/lib/cmsis_dsp/support/testcase.yaml index c9ac7fd6dc7830..254684346f3e25 100644 --- a/tests/lib/cmsis_dsp/support/testcase.yaml +++ b/tests/lib/cmsis_dsp/support/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/svm/testcase.yaml b/tests/lib/cmsis_dsp/svm/testcase.yaml index a187e2e2648041..895a32bd1810fa 100644 --- a/tests/lib/cmsis_dsp/svm/testcase.yaml +++ b/tests/lib/cmsis_dsp/svm/testcase.yaml @@ -4,8 +4,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 128 @@ -14,8 +14,8 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - cmsis-dsp - fpu diff --git a/tests/lib/cmsis_dsp/transform/testcase.yaml b/tests/lib/cmsis_dsp/transform/testcase.yaml index d4e1ecb980e1f4..3e4fb163cb08da 100644 --- a/tests/lib/cmsis_dsp/transform/testcase.yaml +++ b/tests/lib/cmsis_dsp/transform/testcase.yaml @@ -9,8 +9,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 512 @@ -22,7 +22,7 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -37,8 +37,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 512 @@ -50,7 +50,7 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -65,8 +65,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -91,8 +91,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -117,8 +117,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 512 min_ram: 64 @@ -129,7 +129,7 @@ tests: filter: (CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -144,8 +144,8 @@ tests: and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis-dsp min_flash: 512 min_ram: 64 @@ -156,7 +156,7 @@ tests: filter: (CMSIS_DSP_FLOAT16 and (CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -171,8 +171,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -197,8 +197,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 512 @@ -210,7 +210,7 @@ tests: filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps3_an547 + - mps3/an547 tags: - cmsis-dsp - fpu @@ -225,8 +225,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 @@ -251,8 +251,8 @@ tests: ) or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: cmsis-dsp min_flash: 1024 diff --git a/tests/lib/cmsis_nn/testcase.yaml b/tests/lib/cmsis_nn/testcase.yaml index 438c267ef5c3d1..3952266880e5d3 100644 --- a/tests/lib/cmsis_nn/testcase.yaml +++ b/tests/lib/cmsis_nn/testcase.yaml @@ -3,8 +3,8 @@ tests: filter: CONFIG_CPU_CORTEX_M and CONFIG_FULL_LIBC_SUPPORTED integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 tags: cmsis_nn min_flash: 64 min_ram: 32 diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml index f06b451742baa7..5d1308696055d6 100644 --- a/tests/lib/cpp/cxx/testcase.yaml +++ b/tests/lib/cpp/cxx/testcase.yaml @@ -2,7 +2,7 @@ common: tags: cpp toolchain_exclude: xcc integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_cortex_a53 tests: @@ -36,9 +36,9 @@ tests: arch_exclude: posix # Exclude nRF54L15 and nRF54H20 as Nordic HAL is not compatible with C++98. platform_exclude: - - nrf54l15pdk_nrf54l15_cpuapp - - nrf54h20pdk_nrf54h20_cpuapp - - nrf54h20pdk_nrf54h20_cpurad + - nrf54l15pdk/nrf54l15/cpuapp + - nrf54h20pdk/nrf54h20/cpuapp + - nrf54h20pdk/nrf54h20/cpurad build_only: true extra_configs: - CONFIG_STD_CPP98=y diff --git a/tests/lib/cpp/libcxx/testcase.yaml b/tests/lib/cpp/libcxx/testcase.yaml index a75430644c89b1..fdf0318ebd2fe6 100644 --- a/tests/lib/cpp/libcxx/testcase.yaml +++ b/tests/lib/cpp/libcxx/testcase.yaml @@ -10,7 +10,7 @@ tests: - CONFIG_GLIBCXX_LIBCPP=y - CONFIG_CPP_EXCEPTIONS=y integration_platforms: - - mps2_an385 + - mps2/an385 cpp.libcxx.glibcxx.newlib_nano: filter: TOOLCHAIN_HAS_NEWLIB == 1 toolchain_exclude: xcc @@ -22,7 +22,7 @@ tests: - CONFIG_NEWLIB_LIBC_NANO=y - CONFIG_GLIBCXX_LIBCPP=y integration_platforms: - - mps2_an385 + - mps2/an385 cpp.libcxx.glibcxx.picolibc: filter: TOOLCHAIN_HAS_PICOLIBC == 1 toolchain_exclude: xcc @@ -33,7 +33,7 @@ tests: - CONFIG_GLIBCXX_LIBCPP=y - CONFIG_CPP_EXCEPTIONS=y integration_platforms: - - mps2_an385 + - mps2/an385 cpp.libcxx.arcmwdtlib: toolchain_allow: arcmwdt min_flash: 54 diff --git a/tests/lib/heap/src/main.c b/tests/lib/heap/src/main.c index 7db993dc035a66..a87cc91c480fd5 100644 --- a/tests/lib/heap/src/main.c +++ b/tests/lib/heap/src/main.c @@ -14,7 +14,7 @@ */ #if defined(CONFIG_SOC_MPS2_AN521) && defined(CONFIG_QEMU_TARGET) -/* mps2_an521 blows up if allowed to link into large area, even though +/* mps2/an521 blows up if allowed to link into large area, even though * the link is successful and it claims the memory is there. We get * hard faults on boot in qemu before entry to cstart() once MEMSZ is * allowed to get near 256kb. diff --git a/tests/lib/heap/testcase.yaml b/tests/lib/heap/testcase.yaml index 4427788fb07ebd..8ed06a7431ed17 100644 --- a/tests/lib/heap/testcase.yaml +++ b/tests/lib/heap/testcase.yaml @@ -13,7 +13,6 @@ tests: - qemu_xtensa - esp32s2_saola - esp32s2_lolin_mini - - esp32s3_devkitm filter: not CONFIG_SOC_NSIM timeout: 480 integration_platforms: diff --git a/tests/lib/heap_align/testcase.yaml b/tests/lib/heap_align/testcase.yaml index 3dba0fad765dc4..f9b499b6d5f408 100644 --- a/tests/lib/heap_align/testcase.yaml +++ b/tests/lib/heap_align/testcase.yaml @@ -5,4 +5,4 @@ tests: - heap_align integration_platforms: - native_sim - - mps2_an521 + - mps2/an521/cpu0 diff --git a/tests/lib/mpsc_pbuf/testcase.yaml b/tests/lib/mpsc_pbuf/testcase.yaml index 61341277ec12d5..f2665aa93f56a0 100644 --- a/tests/lib/mpsc_pbuf/testcase.yaml +++ b/tests/lib/mpsc_pbuf/testcase.yaml @@ -2,8 +2,8 @@ tests: libraries.mpsc_pbuf: tags: mpsc_pbuf platform_allow: - - qemu_arc_em - - qemu_arc_hs + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs - qemu_cortex_a53 - qemu_cortex_m0 - qemu_cortex_m3 diff --git a/tests/lib/multi_heap/testcase.yaml b/tests/lib/multi_heap/testcase.yaml index 7780e09193a69f..f327881614f196 100644 --- a/tests/lib/multi_heap/testcase.yaml +++ b/tests/lib/multi_heap/testcase.yaml @@ -10,15 +10,15 @@ tests: platform_allow: - qemu_cortex_m3 - qemu_cortex_m0 - - nsim_em - - nsim_em7d_v22 - - nsim_hs - - nsim_hs_mpuv6 - - nsim_hs5x - - nsim_hs6x - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs6x + - nsim/nsim_em + - nsim/nsim_em7d_v22 + - nsim/nsim_hs + - nsim/nsim_hs/mpuv6 + - nsim/nsim_hs5x + - nsim/nsim_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 diff --git a/tests/lib/newlib/heap_listener/testcase.yaml b/tests/lib/newlib/heap_listener/testcase.yaml index a4620e464ccd85..6c8d5b8ef1fdf9 100644 --- a/tests/lib/newlib/heap_listener/testcase.yaml +++ b/tests/lib/newlib/heap_listener/testcase.yaml @@ -6,5 +6,5 @@ tests: filter: TOOLCHAIN_HAS_NEWLIB == 1 arch_exclude: posix integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 diff --git a/tests/lib/newlib/thread_safety/testcase.yaml b/tests/lib/newlib/thread_safety/testcase.yaml index 91b5d6500833f8..9071f59a5e48f7 100644 --- a/tests/lib/newlib/thread_safety/testcase.yaml +++ b/tests/lib/newlib/thread_safety/testcase.yaml @@ -5,7 +5,7 @@ common: - clib - newlib integration_platforms: - - mps2_an521 + - mps2/an521/cpu0 - qemu_x86 tests: libraries.libc.newlib.thread_safety: diff --git a/tests/lib/shared_multi_heap/testcase.yaml b/tests/lib/shared_multi_heap/testcase.yaml index 5580716785dc18..c821457bb9c97d 100644 --- a/tests/lib/shared_multi_heap/testcase.yaml +++ b/tests/lib/shared_multi_heap/testcase.yaml @@ -5,7 +5,7 @@ tests: libraries.shared_multi_heap: platform_allow: - qemu_cortex_a53 - - mps2_an521 + - mps2/an521/cpu0 integration_platforms: - qemu_cortex_a53 tags: diff --git a/tests/lib/sprintf/testcase.yaml b/tests/lib/sprintf/testcase.yaml index 2fb0850fb036f2..860b4318874711 100644 --- a/tests/lib/sprintf/testcase.yaml +++ b/tests/lib/sprintf/testcase.yaml @@ -4,7 +4,7 @@ common: tests: libraries.libc.sprintf: extra_args: CONF_FILE=prj.conf - filter: not CONFIG_SOC_MCIMX7_M4 and CONFIG_STDOUT_CONSOLE + filter: not CONFIG_SOC_MCIMX7D_M4 and CONFIG_STDOUT_CONSOLE integration_platforms: - qemu_x86 arch_exclude: posix diff --git a/tests/lib/time/testcase.yaml b/tests/lib/time/testcase.yaml index f4e8d91ec1b35f..9b002ace2d940f 100644 --- a/tests/lib/time/testcase.yaml +++ b/tests/lib/time/testcase.yaml @@ -3,7 +3,7 @@ tests: tags: libc timeout: 180 integration_platforms: - - mps2_an385 + - mps2/an385 platform_exclude: - native_posix - native_posix_64 diff --git a/tests/misc/test_build/testcase.yaml b/tests/misc/test_build/testcase.yaml index 42732457c426c2..e7217a3c0548a6 100644 --- a/tests/misc/test_build/testcase.yaml +++ b/tests/misc/test_build/testcase.yaml @@ -1,9 +1,9 @@ tests: buildsystem.debug.build: platform_exclude: - - lpcxpresso55s69_ns - - nrf9160dk_nrf9160_ns - - nrf5340dk_nrf5340_cpuapp_ns + - lpcxpresso55s69/lpc55s69/cpu0/ns + - nrf9160dk/nrf9160/ns + - nrf5340dk/nrf5340/cpuapp/ns build_only: true extra_args: CONF_FILE=debug.conf tags: debug @@ -14,13 +14,13 @@ tests: tags: mcuboot build_only: true platform_allow: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 extra_configs: - CONFIG_BOOTLOADER_MCUBOOT=y integration_platforms: - - nrf51dk_nrf51422 - - nrf52dk_nrf52832 + - nrf51dk/nrf51822 + - nrf52dk/nrf52832 buildsystem.kconfig.utf8_in_values: build_only: true tags: kconfig diff --git a/tests/modules/thrift/ThriftTest/testcase.yaml b/tests/modules/thrift/ThriftTest/testcase.yaml index cc92bef771e564..760b2a6fae679d 100644 --- a/tests/modules/thrift/ThriftTest/testcase.yaml +++ b/tests/modules/thrift/ThriftTest/testcase.yaml @@ -8,7 +8,7 @@ common: # qemu_x86 exluded due to missing long double functions in SDK # See https://github.com/zephyrproject-rtos/sdk-ng/issues/603 platform_allow: - - mps2_an385 + - mps2/an385 - qemu_cortex_a53 - qemu_riscv32 - qemu_riscv64 diff --git a/tests/net/lib/dns_sd/prj-no-ipv6.conf b/tests/net/lib/dns_sd/prj-no-ipv6.conf index d973914fa47eca..f06b5ca10bc098 100644 --- a/tests/net/lib/dns_sd/prj-no-ipv6.conf +++ b/tests/net/lib/dns_sd/prj-no-ipv6.conf @@ -24,5 +24,5 @@ CONFIG_DNS_SD_LOG_LEVEL_DBG=y CONFIG_ZTEST=y CONFIG_ZTEST_STACK_SIZE=2048 -# Maybe avoid stack overflow on mps2_an385? +# Maybe avoid stack overflow on mps2/an385? CONFIG_MAIN_STACK_SIZE=2048 diff --git a/tests/net/lib/dns_sd/prj.conf b/tests/net/lib/dns_sd/prj.conf index f53083ff72d695..6655eb94323301 100644 --- a/tests/net/lib/dns_sd/prj.conf +++ b/tests/net/lib/dns_sd/prj.conf @@ -17,7 +17,7 @@ CONFIG_DNS_SD_LOG_LEVEL_DBG=y CONFIG_ZTEST=y CONFIG_ZTEST_STACK_SIZE=2048 -# Maybe avoid stack overflow on mps2_an385? +# Maybe avoid stack overflow on mps2/an385? CONFIG_MAIN_STACK_SIZE=2048 CONFIG_NET_MAX_CONTEXTS=8 diff --git a/tests/net/ptp/clock/testcase.yaml b/tests/net/ptp/clock/testcase.yaml index 1d72469533700c..6d5134dcf6f360 100644 --- a/tests/net/ptp/clock/testcase.yaml +++ b/tests/net/ptp/clock/testcase.yaml @@ -3,7 +3,7 @@ common: # We can only run this in platforms that support PTP clock platform_allow: - frdm_k64f - - sam_e70_xplained + - sam_e70_xplained/same70q21 - native_posix - native_sim integration_platforms: diff --git a/tests/net/socket/poll/testcase.yaml b/tests/net/socket/poll/testcase.yaml index 54da5b83b7d262..56ac475d13e1ff 100644 --- a/tests/net/socket/poll/testcase.yaml +++ b/tests/net/socket/poll/testcase.yaml @@ -1,9 +1,9 @@ common: depends_on: netif - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.poll: min_ram: 21 diff --git a/tests/net/socket/reuseaddr_reuseport/testcase.yaml b/tests/net/socket/reuseaddr_reuseport/testcase.yaml index c1a4808d1d3c0a..fcfce0b1e490d9 100644 --- a/tests/net/socket/reuseaddr_reuseport/testcase.yaml +++ b/tests/net/socket/reuseaddr_reuseport/testcase.yaml @@ -5,10 +5,10 @@ common: tags: - net - socket - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.reuseaddr_reuseport: extra_configs: diff --git a/tests/net/socket/select/testcase.yaml b/tests/net/socket/select/testcase.yaml index eaae57ab9effcb..320cfbaa3eccff 100644 --- a/tests/net/socket/select/testcase.yaml +++ b/tests/net/socket/select/testcase.yaml @@ -6,10 +6,10 @@ common: - socket - userspace filter: CONFIG_FULL_LIBC_SUPPORTED - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.select: extra_configs: diff --git a/tests/net/socket/service/testcase.yaml b/tests/net/socket/service/testcase.yaml index 74046d08274c9b..a2ea34cfe886fe 100644 --- a/tests/net/socket/service/testcase.yaml +++ b/tests/net/socket/service/testcase.yaml @@ -1,11 +1,11 @@ common: depends_on: netif - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). # eventfd API does not work with native_posix so exclude it here platform_exclude: - - mps2_an385 + - mps2/an385 - native_posix - native_posix_64 tests: diff --git a/tests/net/socket/socketpair/testcase.yaml b/tests/net/socket/socketpair/testcase.yaml index 5410f9383765ac..bb906c29d0c422 100644 --- a/tests/net/socket/socketpair/testcase.yaml +++ b/tests/net/socket/socketpair/testcase.yaml @@ -7,17 +7,17 @@ common: min_ram: 21 tests: net.socket.socketpair: - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 net.socket.socketpair.newlib: filter: CONFIG_FULL_LIBC_SUPPORTED extra_configs: - CONFIG_REQUIRES_FULL_LIBC=y - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 net.socket.socketpair.picolibc: filter: CONFIG_PICOLIBC_SUPPORTED extra_configs: - CONFIG_PICOLIBC=y - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 net.socket.socketpair.high_mem: min_ram: 64 extra_configs: @@ -25,4 +25,4 @@ tests: # fail due to insufficient memory. So, use high buffer sizes. - CONFIG_NET_SOCKETPAIR_BUFFER_SIZE=4096 - CONFIG_HEAP_MEM_POOL_SIZE=32768 - platform_exclude: vmu_rt1170 mimxrt1160_evk_cm7 # See #61246 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 mimxrt1160_evk/mimxrt1166/cm7 # See #61246 diff --git a/tests/net/socket/tcp/testcase.yaml b/tests/net/socket/tcp/testcase.yaml index cff7591d938d4f..cd5f7533226785 100644 --- a/tests/net/socket/tcp/testcase.yaml +++ b/tests/net/socket/tcp/testcase.yaml @@ -7,10 +7,10 @@ common: - userspace filter: CONFIG_FULL_LIBC_SUPPORTED timeout: 180 - # FIXME: This test fails very frequently on mps2_an385 due to the system + # FIXME: This test fails very frequently on mps2/an385 due to the system # timer stability issues, so keep it disabled until the root cause # is fixed (GitHub issue zephyrproject-rtos/zephyr#48608). - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 tests: net.socket.tcp: extra_configs: diff --git a/tests/net/socket/tls/testcase.yaml b/tests/net/socket/tls/testcase.yaml index e10c883312fb24..00a126769c7e7a 100644 --- a/tests/net/socket/tls/testcase.yaml +++ b/tests/net/socket/tls/testcase.yaml @@ -9,7 +9,7 @@ common: filter: CONFIG_FULL_LIBC_SUPPORTED integration_platforms: - qemu_x86 - platform_exclude: vmu_rt1170 # See #61129 + platform_exclude: vmu_rt1170/mimxrt1176/cm7 # See #61129 tests: net.socket.tls: extra_configs: @@ -17,4 +17,4 @@ tests: net.socket.tls.preempt: extra_configs: - CONFIG_NET_TC_THREAD_PREEMPTIVE=y - platform_exclude: mps2_an385 + platform_exclude: mps2/an385 diff --git a/tests/posix/common/testcase.yaml b/tests/posix/common/testcase.yaml index 9617cd8e08f996..1562b00320b9dd 100644 --- a/tests/posix/common/testcase.yaml +++ b/tests/posix/common/testcase.yaml @@ -9,7 +9,7 @@ common: tests: portability.posix.common: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb extra_configs: - CONFIG_NEWLIB_LIBC=n @@ -17,7 +17,7 @@ tests: - qemu_x86 portability.posix.common.newlib: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb - lpcxpresso55s06 filter: TOOLCHAIN_HAS_NEWLIB == 1 @@ -37,7 +37,7 @@ tests: - CONFIG_ARCMWDT_LIBC=y portability.posix.common.tls: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb filter: CONFIG_ARCH_HAS_THREAD_LOCAL_STORAGE and CONFIG_TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE extra_configs: @@ -47,7 +47,7 @@ tests: - qemu_x86 portability.posix.common.tls.newlib: platform_exclude: - - nsim_sem_mpu_stack_guard + - nsim/nsim_sem/mpu_stack_guard - intel_ehl_crb - lpcxpresso55s06 filter: TOOLCHAIN_HAS_NEWLIB == 1 and CONFIG_ARCH_HAS_THREAD_LOCAL_STORAGE and @@ -60,12 +60,12 @@ tests: - CONFIG_NEWLIB_LIBC=y - CONFIG_THREAD_LOCAL_STORAGE=y portability.posix.common.nsim: - platform_allow: nsim_sem_mpu_stack_guard + platform_allow: nsim/nsim_sem/mpu_stack_guard extra_configs: - CONFIG_NEWLIB_LIBC=n - CONFIG_TEST_HW_STACK_PROTECTION=n portability.posix.common.newlib.nsim: - platform_allow: nsim_sem_mpu_stack_guard + platform_allow: nsim/nsim_sem/mpu_stack_guard filter: TOOLCHAIN_HAS_NEWLIB == 1 extra_configs: - CONFIG_NEWLIB_LIBC=y @@ -81,7 +81,7 @@ tests: extra_configs: - CONFIG_SPIN_VALIDATE=n integration_platforms: - - mps2_an385 + - mps2/an385 portability.posix.common.signal.strsignal_no_desc: extra_configs: - CONFIG_POSIX_SIGNAL_STRING_DESC=n diff --git a/tests/posix/pthread_pressure/testcase.yaml b/tests/posix/pthread_pressure/testcase.yaml index 73a8fa34e23104..83492a4c9db39c 100644 --- a/tests/posix/pthread_pressure/testcase.yaml +++ b/tests/posix/pthread_pressure/testcase.yaml @@ -4,7 +4,7 @@ common: arch_exclude: - posix integration_platforms: - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp tests: portability.posix.pthread_pressure: extra_configs: diff --git a/tests/subsys/bindesc/definition/testcase.yaml b/tests/subsys/bindesc/definition/testcase.yaml index 0f44794137461d..6e1884ee0b01f9 100644 --- a/tests/subsys/bindesc/definition/testcase.yaml +++ b/tests/subsys/bindesc/definition/testcase.yaml @@ -14,10 +14,10 @@ tests: - qemu_cortex_m0 - qemu_cortex_m3 - qemu_cortex_r5 - - qemu_arc_em - - qemu_arc_hs - - qemu_arc_hs5x - - qemu_arc_hs6x + - qemu_arc/qemu_arc_em + - qemu_arc/qemu_arc_hs + - qemu_arc/qemu_arc_hs5x + - qemu_arc/qemu_arc_hs6x - qemu_riscv32 - qemu_riscv32e - qemu_riscv64 diff --git a/tests/subsys/debug/coredump/src/main.c b/tests/subsys/debug/coredump/src/main.c index d5e11f2148d1e9..3f18ef9e2d6280 100644 --- a/tests/subsys/debug/coredump/src/main.c +++ b/tests/subsys/debug/coredump/src/main.c @@ -30,7 +30,6 @@ void func_3(uint32_t *addr) #if defined(CONFIG_BOARD_M2GL025_MIV) || \ defined(CONFIG_BOARD_HIFIVE1) || \ defined(CONFIG_BOARD_LONGAN_NANO) || \ - defined(CONFIG_BOARD_LONGAN_NANO_LITE) || \ defined(CONFIG_BOARD_QEMU_XTENSA) || \ defined(CONFIG_SOC_FAMILY_INTEL_ADSP) ARG_UNUSED(addr); diff --git a/tests/subsys/debug/coredump_backends/testcase.yaml b/tests/subsys/debug/coredump_backends/testcase.yaml index d7b5f722f3783a..ff4109f9d50c37 100644 --- a/tests/subsys/debug/coredump_backends/testcase.yaml +++ b/tests/subsys/debug/coredump_backends/testcase.yaml @@ -19,10 +19,10 @@ tests: - CONFIG_TEST_STORED_COREDUMP=y platform_allow: - qemu_x86 - - esp32_devkitc_wroom - - esp32_devkitc_wrover + - esp32_devkitc_wroom/esp32/procpu + - esp32_devkitc_wrover/esp32/procpu - esp32s2_saola - - esp32s3_devkitm + - esp32s3_devkitm/esp32s3/procpu - esp32c3_devkitm debug.coredump.backends.other: filter: CONFIG_ARCH_SUPPORTS_COREDUMP diff --git a/tests/subsys/dfu/img_util/testcase.yaml b/tests/subsys/dfu/img_util/testcase.yaml index e90fb0842b1e59..58cc48f98a6d86 100644 --- a/tests/subsys/dfu/img_util/testcase.yaml +++ b/tests/subsys/dfu/img_util/testcase.yaml @@ -1,12 +1,12 @@ common: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_posix - native_posix_64 - native_sim - native_sim_64 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tests: dfu.image_util: tags: dfu_image_util diff --git a/tests/subsys/dfu/mcuboot/testcase.yaml b/tests/subsys/dfu/mcuboot/testcase.yaml index 6b630c71865d66..3b1ddc39a3cabf 100644 --- a/tests/subsys/dfu/mcuboot/testcase.yaml +++ b/tests/subsys/dfu/mcuboot/testcase.yaml @@ -1,11 +1,11 @@ tests: dfu.mcuboot: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_posix - native_posix_64 - native_sim - native_sim_64 tags: dfu_mcuboot integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/tests/subsys/dfu/mcuboot_multi/testcase.yaml b/tests/subsys/dfu/mcuboot_multi/testcase.yaml index 742bbe38ce62b4..9f6411918038d9 100644 --- a/tests/subsys/dfu/mcuboot_multi/testcase.yaml +++ b/tests/subsys/dfu/mcuboot_multi/testcase.yaml @@ -1,9 +1,9 @@ tests: dfu.mcuboot.multiimage: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim - native_sim_64 tags: dfu_mcuboot integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 diff --git a/tests/subsys/dsp/basicmath/testcase.yaml b/tests/subsys/dsp/basicmath/testcase.yaml index cb8dd1a27655b4..7311f8cb9060f1 100644 --- a/tests/subsys/dsp/basicmath/testcase.yaml +++ b/tests/subsys/dsp/basicmath/testcase.yaml @@ -3,8 +3,8 @@ tests: filter: CONFIG_FULL_LIBC_SUPPORTED or CONFIG_ARCH_POSIX integration_platforms: - frdm_k64f - - sam_e70_xplained - - mps2_an521 + - sam_e70_xplained/same70q21 + - mps2/an521/cpu0 - native_sim tags: zdsp min_flash: 128 @@ -12,8 +12,8 @@ tests: zdsp.basicmath.fpu: filter: (CONFIG_CPU_HAS_FPU and CONFIG_FULL_LIBC_SUPPORTED) or CONFIG_ARCH_POSIX integration_platforms: - - mps2_an521_remote - - mps3_an547 + - mps2/an521/cpu1 + - mps3/an547 tags: - zdsp - fpu @@ -24,5 +24,5 @@ tests: zdsp.basicmath.arcmwdt: filter: CONFIG_ISA_ARCV2 toolchain_allow: arcmwdt - platform_allow: nsim_em11d + platform_allow: nsim/nsim_em11d extra_args: CONF_FILE=prj_arc.conf diff --git a/tests/subsys/fs/ext2/testcase.yaml b/tests/subsys/fs/ext2/testcase.yaml index bb4402c9b0ec58..76ec97de3c875d 100644 --- a/tests/subsys/fs/ext2/testcase.yaml +++ b/tests/subsys/fs/ext2/testcase.yaml @@ -6,7 +6,7 @@ tests: - native_sim - native_sim_64 - hifive_unmatched - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp extra_args: - EXTRA_DTC_OVERLAY_FILE="ramdisk_small.overlay" @@ -23,7 +23,7 @@ tests: - renode platform_allow: - hifive_unmatched - - bl5340_dvk_cpuapp + - bl5340_dvk/nrf5340/cpuapp extra_args: CONF_FILE=prj_sdcard.conf filesystem.ext2.flash: diff --git a/tests/subsys/fs/fcb/boards/nrf51dk_nrf51422.conf b/tests/subsys/fs/fcb/boards/nrf51dk_nrf51822.conf similarity index 100% rename from tests/subsys/fs/fcb/boards/nrf51dk_nrf51422.conf rename to tests/subsys/fs/fcb/boards/nrf51dk_nrf51822.conf diff --git a/tests/subsys/fs/fcb/testcase.yaml b/tests/subsys/fs/fcb/testcase.yaml index 3945049a53462e..9070bbaf7bb218 100644 --- a/tests/subsys/fs/fcb/testcase.yaml +++ b/tests/subsys/fs/fcb/testcase.yaml @@ -1,9 +1,9 @@ tests: filesystem.fcb: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 - - nrf51dk_nrf51422 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 + - nrf51dk/nrf51822 - native_posix - native_posix_64 - native_sim @@ -11,7 +11,7 @@ tests: - mr_canhubk3 tags: flash_circural_buffer integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 filesystem.fcb.native_sim.fcb_0x00: extra_args: DTC_OVERLAY_FILE=boards/native_sim_ev_0x00.overlay platform_allow: native_sim diff --git a/tests/subsys/fs/littlefs/testcase.yaml b/tests/subsys/fs/littlefs/testcase.yaml index 211137180f8a7f..1a125021bf761d 100644 --- a/tests/subsys/fs/littlefs/testcase.yaml +++ b/tests/subsys/fs/littlefs/testcase.yaml @@ -3,13 +3,13 @@ common: - filesystem - littlefs platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim - native_sim_64 - mimxrt1060_evk - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 modules: - littlefs tests: diff --git a/tests/subsys/llext/hello_world/testcase.yaml b/tests/subsys/llext/hello_world/testcase.yaml index c977dc5f94fd9e..391e2f81c92eb4 100644 --- a/tests/subsys/llext/hello_world/testcase.yaml +++ b/tests/subsys/llext/hello_world/testcase.yaml @@ -4,11 +4,11 @@ common: - arm - xtensa platform_exclude: - - nuvoton_pfm_m487 # See #63167 + - numaker_pfm_m487 # See #63167 tests: llext.simple.readonly: arch_exclude: xtensa # for now - filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52 + filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE extra_configs: - arch:arm:CONFIG_ARM_MPU=n - CONFIG_LLEXT_STORAGE_WRITABLE=n @@ -19,7 +19,7 @@ tests: - CONFIG_USERSPACE=y - CONFIG_LLEXT_STORAGE_WRITABLE=n llext.simple.writable: - filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE_R52 + filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE extra_configs: - arch:arm:CONFIG_ARM_MPU=n - CONFIG_LLEXT_STORAGE_WRITABLE=y diff --git a/tests/subsys/logging/log_backend_fs/testcase.yaml b/tests/subsys/logging/log_backend_fs/testcase.yaml index c8caccc8c8f5ca..60ad3a0a2950fc 100644 --- a/tests/subsys/logging/log_backend_fs/testcase.yaml +++ b/tests/subsys/logging/log_backend_fs/testcase.yaml @@ -10,7 +10,7 @@ common: platform_allow: - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - mr_canhubk3 integration_platforms: - native_sim diff --git a/tests/subsys/logging/log_switch_format/testcase.yaml b/tests/subsys/logging/log_switch_format/testcase.yaml index 911c8e2c178aaa..bc1f1e933b7ee0 100644 --- a/tests/subsys/logging/log_switch_format/testcase.yaml +++ b/tests/subsys/logging/log_switch_format/testcase.yaml @@ -13,7 +13,7 @@ common: tests: logging.format.switch.deferred: integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 extra_args: OVERLAY_CONFIG=overlay_deferred.conf # "CONFIG_FULL_LIBC_SUPPORTED" filter was applied @@ -28,7 +28,7 @@ tests: logging.format.switch.immediate: extra_args: OVERLAY_CONFIG=overlay_immediate.conf integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 filter: CONFIG_FULL_LIBC_SUPPORTED extra_configs: @@ -36,7 +36,7 @@ tests: logging.format.switch.custom_output: extra_args: OVERLAY_CONFIG=overlay_custom_output.conf integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 filter: CONFIG_FULL_LIBC_SUPPORTED extra_configs: diff --git a/tests/subsys/logging/log_syst/testcase.yaml b/tests/subsys/logging/log_syst/testcase.yaml index db2160b60f0648..d77a94d1d09b2e 100644 --- a/tests/subsys/logging/log_syst/testcase.yaml +++ b/tests/subsys/logging/log_syst/testcase.yaml @@ -18,9 +18,9 @@ tests: # Not all compilers announced in Zephyr support full libc filter: CONFIG_FULL_LIBC_SUPPORTED integration_platforms: - - mps2_an385 + - mps2/an385 - qemu_x86 - - sam_e70_xplained + - sam_e70_xplained/same70q21 extra_configs: - CONFIG_LOG_MIPI_SYST_ENABLE=y - CONFIG_LOG_BACKEND_MOCK_OUTPUT_SYST=y diff --git a/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml b/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml index 471a96a935f672..f21fad9510f398 100644 --- a/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/all_options/testcase.yaml @@ -4,7 +4,7 @@ # SPDX-License-Identifier: Apache-2.0 # common: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 tags: - mgmt - mcumgr diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/cb_notifications/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml index a2514c4dac80ff..7243c98037560d 100644 --- a/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/cb_notifications/testcase.yaml @@ -11,7 +11,7 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - qemu_riscv32_smp + - qemu_riscv32/qemu_virt_riscv32/smp - qemu_riscv64 tags: - cb_notifications diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml index 5d8994f8541c2a..4f07ecf0211d1b 100644 --- a/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/fs_mgmt_hash_supported/testcase.yaml @@ -15,26 +15,26 @@ tests: extra_args: > OVERLAY_CONFIG="configuration/crc32.conf" platform_exclude: - - arduino_giga_r1_m4 - - arduino_portenta_h7_m4 + - arduino_giga_r1/stm32h747xx/m4 + - arduino_portenta_h7/stm32h747xx/m4 - lpcxpresso51u68 - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 mgmt.mcumgr.fs.mgmt.hash.supported.sha256: extra_args: > OVERLAY_CONFIG="configuration/sha256.conf" platform_exclude: - - arduino_giga_r1_m4 - - arduino_portenta_h7_m4 + - arduino_giga_r1/stm32h747xx/m4 + - arduino_portenta_h7/stm32h747xx/m4 - lpcxpresso51u68 - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 mgmt.mcumgr.fs.mgmt.hash.supported.all: extra_args: > OVERLAY_CONFIG="configuration/all.conf" platform_exclude: - - arduino_giga_r1_m4 - - arduino_portenta_h7_m4 + - arduino_giga_r1/stm32h747xx/m4 + - arduino_portenta_h7/stm32h747xx/m4 - lpcxpresso51u68 - - nucleo_h745zi_q_m4 - - stm32h747i_disco_m4 + - nucleo_h745zi_q/stm32h745xx/m4 + - stm32h747i_disco/stm32h747xx/m4 diff --git a/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml b/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml index 88e6eae4b5e2f9..dbd18f8d1c581e 100644 --- a/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/handler_demo/testcase.yaml @@ -12,15 +12,15 @@ common: tests: mgmt.mcumgr.handler.demo: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 build_only: true mgmt.mcumgr.handler.demo.module: extra_args: - OVERLAY_CONFIG="module.conf" platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 build_only: true diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_hs6x.overlay b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_qemu_arc_hs6x.overlay similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_hs6x.overlay rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_arc_qemu_arc_hs6x.overlay diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.overlay b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.overlay similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_smp.overlay rename to tests/subsys/mgmt/mcumgr/os_mgmt_datetime/boards/qemu_riscv64_qemu_virt_riscv64_smp.overlay diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml index 82d0021d325dd4..9da5603fe743f0 100644 --- a/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/os_mgmt_datetime/testcase.yaml @@ -12,9 +12,9 @@ common: - native_sim - qemu_cortex_m0 - qemu_riscv64 - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp - qemu_malta - - qemu_arc_hs6x + - qemu_arc/qemu_arc_hs6x - qemu_leon3 tests: mgmt.mcumgr.os.datetime: {} diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_echo/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/os_mgmt_info/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml b/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml index 930ae58cd3deab..7c5eeff1919ba0 100644 --- a/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/os_mgmt_info/testcase.yaml @@ -33,13 +33,13 @@ tests: platform_exclude: - qemu_cortex_a9 - qemu_x86 - - qemu_riscv64_smp + - qemu_riscv64/qemu_virt_riscv64/smp - qemu_riscv64 - qemu_riscv32e - qemu_riscv32 - - qemu_riscv32_smp + - qemu_riscv32/qemu_virt_riscv32/smp - qemu_cortex_m3 - - mps2_an385 + - mps2/an385 extra_configs: - CONFIG_NETWORKING=y - CONFIG_NET_HOSTNAME_ENABLE=y diff --git a/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml b/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml index 2e8a68cca64f38..07bf722bbf9185 100644 --- a/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml +++ b/tests/subsys/mgmt/mcumgr/settings_mgmt/testcase.yaml @@ -10,7 +10,7 @@ tests: - native_posix_64 - native_sim - native_sim_64 - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings_mgmt - mcumgr diff --git a/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_smp.conf b/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_smp.conf rename to tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv32_qemu_virt_riscv32_smp.conf diff --git a/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_smp.conf b/tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf similarity index 100% rename from tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_smp.conf rename to tests/subsys/mgmt/mcumgr/smp_version/boards/qemu_riscv64_qemu_virt_riscv64_smp.conf diff --git a/tests/subsys/modem/backends/uart/testcase.yaml b/tests/subsys/modem/backends/uart/testcase.yaml index 54d8a6b94703e5..be53728c7241fa 100644 --- a/tests/subsys/modem/backends/uart/testcase.yaml +++ b/tests/subsys/modem/backends/uart/testcase.yaml @@ -7,7 +7,7 @@ common: fixture: gpio_loopback platform_allow: - b_u585i_iot02a - - nrf5340dk_nrf5340_cpuapp + - nrf5340dk/nrf5340/cpuapp tests: modem.backends.uart.async: diff --git a/tests/subsys/pm/power_mgmt_soc/testcase.yaml b/tests/subsys/pm/power_mgmt_soc/testcase.yaml index 8fe974f0bfa4be..021a3416b9b5ea 100644 --- a/tests/subsys/pm/power_mgmt_soc/testcase.yaml +++ b/tests/subsys/pm/power_mgmt_soc/testcase.yaml @@ -9,7 +9,7 @@ tests: - nucleo_wb55rg - nucleo_l476rg - twr_ke18f - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 tags: pm integration_platforms: - mec15xxevb_assy6853 diff --git a/tests/subsys/sd/mmc/testcase.yaml b/tests/subsys/sd/mmc/testcase.yaml index ac45914242e55a..3c201d0f1e4280 100644 --- a/tests/subsys/sd/mmc/testcase.yaml +++ b/tests/subsys/sd/mmc/testcase.yaml @@ -10,4 +10,4 @@ tests: tags: sdhc min_ram: 32 integration_platforms: - - mimxrt595_evk_cm33 + - mimxrt595_evk/mimxrt595s/cm33 diff --git a/tests/subsys/settings/fcb/testcase.yaml b/tests/subsys/settings/fcb/testcase.yaml index 0382c74ff00af5..01dc9f5bf0f5f3 100644 --- a/tests/subsys/settings/fcb/testcase.yaml +++ b/tests/subsys/settings/fcb/testcase.yaml @@ -1,13 +1,13 @@ tests: settings.fcb.raw: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - native_sim - native_sim_64 - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim tags: - settings diff --git a/tests/subsys/settings/fcb_init/testcase.yaml b/tests/subsys/settings/fcb_init/testcase.yaml index fd0d0209c7161a..8c26410c613159 100644 --- a/tests/subsys/settings/fcb_init/testcase.yaml +++ b/tests/subsys/settings/fcb_init/testcase.yaml @@ -1,10 +1,10 @@ tests: settings.fcb: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings - fcb diff --git a/tests/subsys/settings/file/testcase.yaml b/tests/subsys/settings/file/testcase.yaml index 9491f9b2046870..c98239ca2adf46 100644 --- a/tests/subsys/settings/file/testcase.yaml +++ b/tests/subsys/settings/file/testcase.yaml @@ -4,7 +4,7 @@ tests: settings.file.raw: platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 - native_sim - native_sim_64 - mr_canhubk3 diff --git a/tests/subsys/settings/functional/fcb/testcase.yaml b/tests/subsys/settings/functional/fcb/testcase.yaml index d9d63adc66c383..eaad89b64e6ad4 100644 --- a/tests/subsys/settings/functional/fcb/testcase.yaml +++ b/tests/subsys/settings/functional/fcb/testcase.yaml @@ -1,15 +1,15 @@ tests: settings.functional.fcb: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - native_posix - native_posix_64 - native_sim - native_sim_64 - mr_canhubk3 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings - fcb diff --git a/tests/subsys/settings/functional/file/testcase.yaml b/tests/subsys/settings/functional/file/testcase.yaml index 6f876e93f3f433..bb4b9036f4bd37 100644 --- a/tests/subsys/settings/functional/file/testcase.yaml +++ b/tests/subsys/settings/functional/file/testcase.yaml @@ -1,8 +1,8 @@ tests: settings.file: platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - native_sim - native_sim_64 - mr_canhubk3 diff --git a/tests/subsys/settings/functional/nvs/testcase.yaml b/tests/subsys/settings/functional/nvs/testcase.yaml index def7aa02a5240b..3f0cf37b796028 100644 --- a/tests/subsys/settings/functional/nvs/testcase.yaml +++ b/tests/subsys/settings/functional/nvs/testcase.yaml @@ -22,10 +22,10 @@ tests: settings.functional.nvs.dk: extra_args: OVERLAY_CONFIG=mpu.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: - settings - nvs diff --git a/tests/subsys/storage/flash_map/testcase.yaml b/tests/subsys/storage/flash_map/testcase.yaml index 1d03fc2ed2f24a..027b3865fdd148 100644 --- a/tests/subsys/storage/flash_map/testcase.yaml +++ b/tests/subsys/storage/flash_map/testcase.yaml @@ -1,7 +1,7 @@ tests: storage.flash_map: platform_allow: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - qemu_x86 - native_posix - native_posix_64 @@ -14,18 +14,18 @@ tests: storage.flash_map.mpu: extra_args: OVERLAY_CONFIG=overlay-mpu.conf platform_allow: - - nrf52840dk_nrf52840 - - nrf52dk_nrf52832 + - nrf52840dk/nrf52840 + - nrf52dk/nrf52832 - frdm_k64f - - hexiwear_k64 + - hexiwear/mk64f12 - twr_ke18f integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: flash_map storage.flash_map.mbedtls: extra_args: OVERLAY_CONFIG=overlay-mbedtls.conf platform_allow: - - nrf51dk_nrf51422 + - nrf51dk/nrf51822 - qemu_x86 - native_posix - native_posix_64 diff --git a/tests/subsys/storage/stream/stream_flash/testcase.yaml b/tests/subsys/storage/stream/stream_flash/testcase.yaml index 9f4b8c163838d6..e61557feadc3d0 100644 --- a/tests/subsys/storage/stream/stream_flash/testcase.yaml +++ b/tests/subsys/storage/stream/stream_flash/testcase.yaml @@ -18,7 +18,7 @@ tests: storage.stream_flash.mpu_allow_flash_write: extra_args: OVERLAY_CONFIG=mpu_allow_flash_write.overlay platform_allow: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 integration_platforms: - - nrf52840dk_nrf52840 + - nrf52840dk/nrf52840 tags: stream_flash diff --git a/tests/subsys/zbus/dyn_channel/testcase.yaml b/tests/subsys/zbus/dyn_channel/testcase.yaml index 8bdee772571775..96bd746beaaf22 100644 --- a/tests/subsys/zbus/dyn_channel/testcase.yaml +++ b/tests/subsys/zbus/dyn_channel/testcase.yaml @@ -1,6 +1,6 @@ tests: message_bus.zbus.dyn_channel.static_and_dynamic_channels: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/subsys/zbus/hlp_priority_boost/testcase.yaml b/tests/subsys/zbus/hlp_priority_boost/testcase.yaml index f83e54f59e9f04..54fdf3021fbb22 100644 --- a/tests/subsys/zbus/hlp_priority_boost/testcase.yaml +++ b/tests/subsys/zbus/hlp_priority_boost/testcase.yaml @@ -1,6 +1,6 @@ tests: message_bus.zbus.hlp_priority_boost: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/subsys/zbus/integration/testcase.yaml b/tests/subsys/zbus/integration/testcase.yaml index 410280b1b0dad6..ec123e9477e5cb 100644 --- a/tests/subsys/zbus/integration/testcase.yaml +++ b/tests/subsys/zbus/integration/testcase.yaml @@ -3,7 +3,7 @@ tests: platform_exclude: - qemu_cortex_a9 - hifive_unleashed - - fvp_base_revc_2xaemv8a_smp_ns + - fvp_base_revc_2xaemv8a//smp/ns - fvp_baser_aemv8r_aarch32_smp tags: zbus integration_platforms: diff --git a/tests/subsys/zbus/unittests/testcase.yaml b/tests/subsys/zbus/unittests/testcase.yaml index 6b7076cb680de9..8c9d10c7574950 100644 --- a/tests/subsys/zbus/unittests/testcase.yaml +++ b/tests/subsys/zbus/unittests/testcase.yaml @@ -1,11 +1,11 @@ tests: message_bus.zbus.general_unittests: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim message_bus.zbus.general_unittests_without_priority_boost: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/subsys/zbus/user_data/testcase.yaml b/tests/subsys/zbus/user_data/testcase.yaml index 4f21a9c35c8387..e8f6e936b9be2c 100644 --- a/tests/subsys/zbus/user_data/testcase.yaml +++ b/tests/subsys/zbus/user_data/testcase.yaml @@ -1,6 +1,6 @@ tests: message_bus.zbus.user_data.channel_user_data: - platform_exclude: fvp_base_revc_2xaemv8a_smp_ns + platform_exclude: fvp_base_revc_2xaemv8a//smp/ns tags: zbus integration_platforms: - native_sim diff --git a/tests/ztest/busy_sim/testcase.yaml b/tests/ztest/busy_sim/testcase.yaml index 931871c830a17e..271b2aa8542b75 100644 --- a/tests/ztest/busy_sim/testcase.yaml +++ b/tests/ztest/busy_sim/testcase.yaml @@ -4,7 +4,7 @@ common: depends_on: counter tests: testing.ztest.busy_sim: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 testing.ztest.busy_sim_nrf52840dk_pin: - platform_allow: nrf52840dk_nrf52840 + platform_allow: nrf52840dk/nrf52840 extra_args: DTC_OVERLAY_FILE=boards/nrf52840dk_nrf52840_pin.overlay diff --git a/west.yml b/west.yml index 3e8b2f0fa48ef4..087e25632034ac 100644 --- a/west.yml +++ b/west.yml @@ -147,7 +147,7 @@ manifest: groups: - hal - name: hal_atmel - revision: aad79bf530b69b72712d18873df4120ad052d921 + revision: d6221e73d76a4a31d802e0657342fcbda77e21ae path: modules/hal/atmel groups: - hal @@ -168,7 +168,7 @@ manifest: groups: - hal - name: hal_infineon - revision: 69c883d3bd9fac8a18dd8384624b8c472a68d06f + revision: b1a47231e8671c882c5f055f9f10c32b18133d08 path: modules/hal/infineon groups: - hal @@ -178,7 +178,7 @@ manifest: groups: - hal - name: hal_microchip - revision: 5d079f1683a00b801373bbbbf5d181d4e33b30d5 + revision: 68575aa28cd33c68b3b8d66f510d15746c57fdb5 path: modules/hal/microchip groups: - hal @@ -193,7 +193,7 @@ manifest: groups: - hal - name: hal_nxp - revision: d45b14c198d778658b7853b48378d2e132a6c4be + revision: f436a4529f284067af29ad72af5bd0ad51b09f3e path: modules/hal/nxp groups: - hal @@ -210,7 +210,7 @@ manifest: - hal - name: hal_renesas path: modules/hal/renesas - revision: 0b1f2fdb99d6386f125a8dba72083e3c56aecc2b + revision: 991e060b6825f0f6830f4dbccbed8252598f2a6d groups: - hal - name: hal_rpi_pico @@ -219,7 +219,7 @@ manifest: groups: - hal - name: hal_silabs - revision: b11b29167f3f9a0fd0c34a8eeeb36b0c1d218917 + revision: 59c6c6e2e8862f0ff5c6087ef055793bed125778 path: modules/hal/silabs groups: - hal @@ -249,7 +249,7 @@ manifest: groups: - hal - name: hal_xtensa - revision: 08325d6fb7190a105f5382d35e64ed2812c57cf4 + revision: a2d658525b16c57bea8dd565f5bd5167e4b9f1ee path: modules/hal/xtensa groups: - hal @@ -282,7 +282,7 @@ manifest: groups: - crypto - name: mcuboot - revision: a4eda30f5b0cfd0cf15512be9dcd559239dbfc91 + revision: fefe701a5de7ffcec001938c978ef57ff7d0592d path: bootloader/mcuboot - name: mipi-sys-t path: modules/debug/mipi-sys-t @@ -335,7 +335,7 @@ manifest: revision: 150f4eb2955eaf36ac0f9519d4f4f58d5ade5740 path: modules/lib/uoscore-uedhoc - name: zcbor - revision: d3093b5684f62268c7f27f8a5079f166772619de + revision: 75d088037eb237b18e7ec1f47c9ce494b9b95aab path: modules/lib/zcbor self: